hdac.c revision 186912
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20081226_0122" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 186912 2009-01-08 19:43:47Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 166#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 167#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 168#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 169#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 170#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 171#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 172#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 173#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 174#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 175#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 176 177/* ATI */ 178#define ATI_VENDORID 0x1002 179#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 180#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 181#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 182 183/* VIA */ 184#define VIA_VENDORID 0x1106 185#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 186#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 187 188/* SiS */ 189#define SIS_VENDORID 0x1039 190#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 191#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 192 193/* ULI */ 194#define ULI_VENDORID 0x10b9 195#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 196#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 197 198/* OEM/subvendors */ 199 200/* Intel */ 201#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 202 203/* HP/Compaq */ 204#define HP_VENDORID 0x103c 205#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 206#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 207#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 208#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 209#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 210#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 211#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 212#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 213#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 214#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 215/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 216#define HP_NX6325_SUBVENDORX 0x103c30b0 217 218/* Dell */ 219#define DELL_VENDORID 0x1028 220#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 221#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 222#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 223#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 224#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 225#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 226#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 227#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 228 229/* Clevo */ 230#define CLEVO_VENDORID 0x1558 231#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 232#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 233 234/* Acer */ 235#define ACER_VENDORID 0x1025 236#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 237#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 238#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 239#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 240#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 241#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 242#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 243 244/* Asus */ 245#define ASUS_VENDORID 0x1043 246#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 247#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 248#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 249#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 250#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 251#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 252#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 253#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 254#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 255#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 256#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 257#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 258#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 259#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 260#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 261#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 262 263/* IBM / Lenovo */ 264#define IBM_VENDORID 0x1014 265#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 266#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 267 268/* Lenovo */ 269#define LENOVO_VENDORID 0x17aa 270#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 271#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 272#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 273#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 274 275/* Samsung */ 276#define SAMSUNG_VENDORID 0x144d 277#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 278#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 279 280/* Medion ? */ 281#define MEDION_VENDORID 0x161f 282#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 283#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 284 285/* Apple Computer Inc. */ 286#define APPLE_VENDORID 0x106b 287#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 288 289/* Sony */ 290#define SONY_VENDORID 0x104d 291#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 292#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 293 294/* 295 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 296 * instead of their own, which is beyond my comprehension 297 * (see HDA_CODEC_STAC9221 below). 298 */ 299#define APPLE_INTEL_MAC 0x76808384 300 301/* LG Electronics */ 302#define LG_VENDORID 0x1854 303#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 304#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 305 306/* Fujitsu Siemens */ 307#define FS_VENDORID 0x1734 308#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 309#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 310#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 311 312/* Fujitsu Limited */ 313#define FL_VENDORID 0x10cf 314#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 315#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 316#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 317 318/* Toshiba */ 319#define TOSHIBA_VENDORID 0x1179 320#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 321#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 322#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 323 324/* Micro-Star International (MSI) */ 325#define MSI_VENDORID 0x1462 326#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 327#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 328#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 329 330/* Giga-Byte Technology */ 331#define GB_VENDORID 0x1458 332#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 333#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 334 335/* Uniwill ? */ 336#define UNIWILL_VENDORID 0x1584 337#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 338#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 339 340 341/* Misc constants.. */ 342#define HDA_AMP_VOL_DEFAULT (-1) 343#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 344#define HDA_AMP_MUTE_NONE (0) 345#define HDA_AMP_MUTE_LEFT (1 << 0) 346#define HDA_AMP_MUTE_RIGHT (1 << 1) 347#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 348 349#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 350#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 351 352#define HDA_ADC_MONITOR (1 << 0) 353 354#define HDA_CTL_OUT 1 355#define HDA_CTL_IN 2 356 357#define HDA_GPIO_MAX 8 358/* 0 - 7 = GPIO , 8 = Flush */ 359#define HDA_QUIRK_GPIO0 (1 << 0) 360#define HDA_QUIRK_GPIO1 (1 << 1) 361#define HDA_QUIRK_GPIO2 (1 << 2) 362#define HDA_QUIRK_GPIO3 (1 << 3) 363#define HDA_QUIRK_GPIO4 (1 << 4) 364#define HDA_QUIRK_GPIO5 (1 << 5) 365#define HDA_QUIRK_GPIO6 (1 << 6) 366#define HDA_QUIRK_GPIO7 (1 << 7) 367#define HDA_QUIRK_GPIOFLUSH (1 << 8) 368 369/* 9 - 25 = anything else */ 370#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 371#define HDA_QUIRK_FIXEDRATE (1 << 10) 372#define HDA_QUIRK_FORCESTEREO (1 << 11) 373#define HDA_QUIRK_EAPDINV (1 << 12) 374#define HDA_QUIRK_DMAPOS (1 << 13) 375#define HDA_QUIRK_SENSEINV (1 << 14) 376 377/* 26 - 31 = vrefs */ 378#define HDA_QUIRK_IVREF50 (1 << 26) 379#define HDA_QUIRK_IVREF80 (1 << 27) 380#define HDA_QUIRK_IVREF100 (1 << 28) 381#define HDA_QUIRK_OVREF50 (1 << 29) 382#define HDA_QUIRK_OVREF80 (1 << 30) 383#define HDA_QUIRK_OVREF100 (1 << 31) 384 385#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 386 HDA_QUIRK_IVREF100) 387#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 388 HDA_QUIRK_OVREF100) 389#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 390 391#if __FreeBSD_version < 600000 392#define taskqueue_drain(...) 393#endif 394 395static const struct { 396 char *key; 397 uint32_t value; 398} hdac_quirks_tab[] = { 399 { "gpio0", HDA_QUIRK_GPIO0 }, 400 { "gpio1", HDA_QUIRK_GPIO1 }, 401 { "gpio2", HDA_QUIRK_GPIO2 }, 402 { "gpio3", HDA_QUIRK_GPIO3 }, 403 { "gpio4", HDA_QUIRK_GPIO4 }, 404 { "gpio5", HDA_QUIRK_GPIO5 }, 405 { "gpio6", HDA_QUIRK_GPIO6 }, 406 { "gpio7", HDA_QUIRK_GPIO7 }, 407 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 408 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 409 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 410 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 411 { "eapdinv", HDA_QUIRK_EAPDINV }, 412 { "dmapos", HDA_QUIRK_DMAPOS }, 413 { "senseinv", HDA_QUIRK_SENSEINV }, 414 { "ivref50", HDA_QUIRK_IVREF50 }, 415 { "ivref80", HDA_QUIRK_IVREF80 }, 416 { "ivref100", HDA_QUIRK_IVREF100 }, 417 { "ovref50", HDA_QUIRK_OVREF50 }, 418 { "ovref80", HDA_QUIRK_OVREF80 }, 419 { "ovref100", HDA_QUIRK_OVREF100 }, 420 { "ivref", HDA_QUIRK_IVREF }, 421 { "ovref", HDA_QUIRK_OVREF }, 422 { "vref", HDA_QUIRK_VREF }, 423}; 424#define HDAC_QUIRKS_TAB_LEN \ 425 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 426 427#define HDA_BDL_MIN 2 428#define HDA_BDL_MAX 256 429#define HDA_BDL_DEFAULT HDA_BDL_MIN 430 431#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 432#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 433 434#define HDA_BUFSZ_MIN 4096 435#define HDA_BUFSZ_MAX 65536 436#define HDA_BUFSZ_DEFAULT 16384 437 438#define HDA_PARSE_MAXDEPTH 10 439 440#define HDAC_UNSOLTAG_EVENT_HP 0x00 441 442MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 443 444const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 445 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 446 "White", "Other"}; 447 448const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 449 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 450 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 451 452const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 453 454/* Default */ 455static uint32_t hdac_fmt[] = { 456 AFMT_STEREO | AFMT_S16_LE, 457 0 458}; 459 460static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 461 462static const struct { 463 uint32_t model; 464 char *desc; 465} hdac_devices[] = { 466 { HDA_INTEL_82801F, "Intel 82801F" }, 467 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 468 { HDA_INTEL_82801G, "Intel 82801G" }, 469 { HDA_INTEL_82801H, "Intel 82801H" }, 470 { HDA_INTEL_82801I, "Intel 82801I" }, 471 { HDA_INTEL_82801J, "Intel 82801J" }, 472 { HDA_INTEL_SCH, "Intel SCH" }, 473 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 474 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 475 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 476 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 477 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 478 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 479 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 480 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 481 { HDA_NVIDIA_MCP73_1, "NVidia MCP73" }, 482 { HDA_NVIDIA_MCP73_2, "NVidia MCP73" }, 483 { HDA_NVIDIA_MCP78_1, "NVidia MCP78" }, 484 { HDA_NVIDIA_MCP78_2, "NVidia MCP78" }, 485 { HDA_NVIDIA_MCP78_3, "NVidia MCP78" }, 486 { HDA_NVIDIA_MCP78_4, "NVidia MCP78" }, 487 { HDA_NVIDIA_MCP79_1, "NVidia MCP79" }, 488 { HDA_NVIDIA_MCP79_2, "NVidia MCP79" }, 489 { HDA_NVIDIA_MCP79_3, "NVidia MCP79" }, 490 { HDA_NVIDIA_MCP79_4, "NVidia MCP79" }, 491 { HDA_ATI_SB450, "ATI SB450" }, 492 { HDA_ATI_SB600, "ATI SB600" }, 493 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 494 { HDA_SIS_966, "SiS 966" }, 495 { HDA_ULI_M5461, "ULI M5461" }, 496 /* Unknown */ 497 { HDA_INTEL_ALL, "Intel (Unknown)" }, 498 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 499 { HDA_ATI_ALL, "ATI (Unknown)" }, 500 { HDA_VIA_ALL, "VIA (Unknown)" }, 501 { HDA_SIS_ALL, "SiS (Unknown)" }, 502 { HDA_ULI_ALL, "ULI (Unknown)" }, 503}; 504#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 505 506static const struct { 507 uint16_t vendor; 508 uint8_t reg; 509 uint8_t mask; 510 uint8_t enable; 511} hdac_pcie_snoop[] = { 512 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 513 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 514 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 515}; 516#define HDAC_PCIESNOOP_LEN \ 517 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 518 519static const struct { 520 uint32_t rate; 521 int valid; 522 uint16_t base; 523 uint16_t mul; 524 uint16_t div; 525} hda_rate_tab[] = { 526 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 527 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 528 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 529 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 530 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 531 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 532 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 533 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 534 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 535 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 536 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 537 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 538 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 539 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 540 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 541 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 542 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 543 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 544 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 545 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 546 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 547 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 548 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 549 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 550 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 551 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 552 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 553 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 554 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 555 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 556 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 557 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 558 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 559 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 560 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 561}; 562#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 563 564/* All codecs you can eat... */ 565#define HDA_CODEC_CONSTRUCT(vendor, id) \ 566 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 567 568/* Realtek */ 569#define REALTEK_VENDORID 0x10ec 570#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 571#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 572#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 573#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 574#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 575#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 576#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 577#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 578#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 579#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 580#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 581#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 582#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 583#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 584#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 585#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 586#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 587#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 588 589/* Analog Devices */ 590#define ANALOGDEVICES_VENDORID 0x11d4 591#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 592#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 593#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 594#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 595#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 596#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 597#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 598#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 599#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 600#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 601#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 602#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 603#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 604#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 605#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 606#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 607 608/* CMedia */ 609#define CMEDIA_VENDORID 0x434d 610#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 611#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 612 613/* Sigmatel */ 614#define SIGMATEL_VENDORID 0x8384 615#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 616#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 617#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 618#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 619#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 620#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 621#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 622#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 623#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 624#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 625#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 626#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 627#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 628#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 629#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 630#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 631#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 632#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 633#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 634#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 635#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 636#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 637#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 638#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 639#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 640#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 641#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 642#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 643#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 644#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 645#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 646#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 647#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 648#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 649#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 650#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 651#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 652#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 653#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 654#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 655 656/* IDT */ 657#define IDT_VENDORID 0x111d 658#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 659#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 660#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 661#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 662#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 663#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 664#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 665#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 666#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 667#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 668#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 669#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 670#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 671 672/* Silicon Image */ 673#define SII_VENDORID 0x1095 674#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 675#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 676 677/* Lucent/Agere */ 678#define AGERE_VENDORID 0x11c1 679#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 680 681/* Conexant */ 682#define CONEXANT_VENDORID 0x14f1 683#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 684#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 685#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 686#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 687 688/* VIA */ 689#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 690#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 691#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 692#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 693#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 694#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 695#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 696#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 697#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 698#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 699#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 700#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 701#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 702#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 703#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 704#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 705#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 706#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 707#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 708#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 709#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 710 711/* ATI */ 712#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 713#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 714#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 715#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 716#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 717 718/* NVIDIA */ 719#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 720 721/* INTEL */ 722#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 723 724/* Codecs */ 725static const struct { 726 uint32_t id; 727 char *name; 728} hdac_codecs[] = { 729 { HDA_CODEC_ALC260, "Realtek ALC260" }, 730 { HDA_CODEC_ALC262, "Realtek ALC262" }, 731 { HDA_CODEC_ALC267, "Realtek ALC267" }, 732 { HDA_CODEC_ALC268, "Realtek ALC268" }, 733 { HDA_CODEC_ALC269, "Realtek ALC269" }, 734 { HDA_CODEC_ALC272, "Realtek ALC272" }, 735 { HDA_CODEC_ALC660, "Realtek ALC660" }, 736 { HDA_CODEC_ALC662, "Realtek ALC662" }, 737 { HDA_CODEC_ALC663, "Realtek ALC663" }, 738 { HDA_CODEC_ALC861, "Realtek ALC861" }, 739 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 740 { HDA_CODEC_ALC880, "Realtek ALC880" }, 741 { HDA_CODEC_ALC882, "Realtek ALC882" }, 742 { HDA_CODEC_ALC883, "Realtek ALC883" }, 743 { HDA_CODEC_ALC885, "Realtek ALC885" }, 744 { HDA_CODEC_ALC888, "Realtek ALC888" }, 745 { HDA_CODEC_ALC889, "Realtek ALC889" }, 746 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 747 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 748 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 749 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 750 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 751 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 752 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 753 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 754 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 755 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 756 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 757 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 758 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 759 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 760 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 761 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 762 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 763 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 764 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 765 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 766 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 767 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 768 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 769 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 770 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 771 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 772 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 773 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 774 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 775 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 776 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 777 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 778 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 779 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 780 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 781 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 782 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 783 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 784 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 785 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 786 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 787 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 788 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 789 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 790 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 791 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 792 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 793 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 794 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 795 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 796 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 797 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 798 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 799 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 800 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 801 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 802 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 803 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 804 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 805 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 806 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 807 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 808 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 809 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 810 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 811 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 812 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 813 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 814 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 815 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 816 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 817 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 818 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 819 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 820 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 821 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 822 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 823 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 824 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 825 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 826 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 827 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 828 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 829 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 830 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 831 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 832 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 833 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 834 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 835 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 836 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 837 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 838 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 839 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 840 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 841 /* Unknown codec */ 842 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 843 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 844 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 845 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 846 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 847 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 848 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 849 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 850 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 851 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 852 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 853 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 854}; 855#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 856 857 858/**************************************************************************** 859 * Function prototypes 860 ****************************************************************************/ 861static void hdac_intr_handler(void *); 862static int hdac_reset(struct hdac_softc *, int); 863static int hdac_get_capabilities(struct hdac_softc *); 864static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 865static int hdac_dma_alloc(struct hdac_softc *, 866 struct hdac_dma *, bus_size_t); 867static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 868static int hdac_mem_alloc(struct hdac_softc *); 869static void hdac_mem_free(struct hdac_softc *); 870static int hdac_irq_alloc(struct hdac_softc *); 871static void hdac_irq_free(struct hdac_softc *); 872static void hdac_corb_init(struct hdac_softc *); 873static void hdac_rirb_init(struct hdac_softc *); 874static void hdac_corb_start(struct hdac_softc *); 875static void hdac_rirb_start(struct hdac_softc *); 876static void hdac_scan_codecs(struct hdac_softc *); 877static void hdac_probe_codec(struct hdac_codec *); 878static void hdac_probe_function(struct hdac_codec *, nid_t); 879static int hdac_pcmchannel_setup(struct hdac_chan *); 880 881static void hdac_attach2(void *); 882 883static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 884 uint32_t, int); 885static void hdac_command_send_internal(struct hdac_softc *, 886 struct hdac_command_list *, int); 887 888static int hdac_probe(device_t); 889static int hdac_attach(device_t); 890static int hdac_detach(device_t); 891static int hdac_suspend(device_t); 892static int hdac_resume(device_t); 893static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 894static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 895 uint32_t, int, int); 896static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 897 nid_t, int, int, int); 898static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 899 nid_t, nid_t, int, int, int, int, int, int); 900static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 901 902static int hdac_rirb_flush(struct hdac_softc *sc); 903static int hdac_unsolq_flush(struct hdac_softc *sc); 904 905static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 906 907#define hdac_command(a1, a2, a3) \ 908 hdac_command_sendone_internal(a1, a2, a3) 909 910#define hdac_codec_id(c) \ 911 ((uint32_t)((c == NULL) ? 0x00000000 : \ 912 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 913 ((uint32_t)(c)->device_id & 0x0000ffff)))) 914 915static char * 916hdac_codec_name(struct hdac_codec *codec) 917{ 918 uint32_t id; 919 int i; 920 921 id = hdac_codec_id(codec); 922 923 for (i = 0; i < HDAC_CODECS_LEN; i++) { 924 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 925 return (hdac_codecs[i].name); 926 } 927 928 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 929} 930 931static char * 932hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 933{ 934 static char *ossname[] = SOUND_DEVICE_NAMES; 935 int i, first = 1; 936 937 bzero(buf, len); 938 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 939 if (mask & (1 << i)) { 940 if (first == 0) 941 strlcat(buf, ", ", len); 942 strlcat(buf, ossname[i], len); 943 first = 0; 944 } 945 } 946 return (buf); 947} 948 949static struct hdac_audio_ctl * 950hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 951{ 952 if (devinfo == NULL || 953 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 954 index == NULL || devinfo->function.audio.ctl == NULL || 955 devinfo->function.audio.ctlcnt < 1 || 956 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 957 return (NULL); 958 return (&devinfo->function.audio.ctl[(*index)++]); 959} 960 961static struct hdac_audio_ctl * 962hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 963 int index, int cnt) 964{ 965 struct hdac_audio_ctl *ctl; 966 int i, found = 0; 967 968 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 969 return (NULL); 970 971 i = 0; 972 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 973 if (ctl->enable == 0) 974 continue; 975 if (ctl->widget->nid != nid) 976 continue; 977 if (dir && ctl->ndir != dir) 978 continue; 979 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 980 ctl->dir == ctl->ndir && ctl->index != index) 981 continue; 982 found++; 983 if (found == cnt || cnt <= 0) 984 return (ctl); 985 } 986 987 return (NULL); 988} 989 990/* 991 * Jack detection (Speaker/HP redirection) event handler. 992 */ 993static void 994hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 995{ 996 struct hdac_audio_as *as; 997 struct hdac_softc *sc; 998 struct hdac_widget *w; 999 struct hdac_audio_ctl *ctl; 1000 uint32_t val, res; 1001 int i, j; 1002 nid_t cad; 1003 1004 if (devinfo == NULL || devinfo->codec == NULL || 1005 devinfo->codec->sc == NULL) 1006 return; 1007 1008 sc = devinfo->codec->sc; 1009 cad = devinfo->codec->cad; 1010 as = devinfo->function.audio.as; 1011 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1012 if (as[i].hpredir < 0) 1013 continue; 1014 1015 w = hdac_widget_get(devinfo, as[i].pins[15]); 1016 if (w == NULL || w->enable == 0 || w->type != 1017 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1018 continue; 1019 1020 res = hdac_command(sc, 1021 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1022 1023 HDA_BOOTVERBOSE( 1024 device_printf(sc->dev, 1025 "Pin sense: nid=%d res=0x%08x\n", 1026 as[i].pins[15], res); 1027 ); 1028 1029 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1030 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1031 res ^= 1; 1032 1033 /* (Un)Mute headphone pin. */ 1034 ctl = hdac_audio_ctl_amp_get(devinfo, 1035 as[i].pins[15], HDA_CTL_IN, -1, 1); 1036 if (ctl != NULL && ctl->mute) { 1037 /* If pin has muter - use it. */ 1038 val = (res != 0) ? 0 : 1; 1039 if (val != ctl->forcemute) { 1040 ctl->forcemute = val; 1041 hdac_audio_ctl_amp_set(ctl, 1042 HDA_AMP_MUTE_DEFAULT, 1043 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1044 } 1045 } else { 1046 /* If there is no muter - disable pin output. */ 1047 w = hdac_widget_get(devinfo, as[i].pins[15]); 1048 if (w != NULL && w->type == 1049 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1050 if (res != 0) 1051 val = w->wclass.pin.ctrl | 1052 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1053 else 1054 val = w->wclass.pin.ctrl & 1055 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1056 if (val != w->wclass.pin.ctrl) { 1057 w->wclass.pin.ctrl = val; 1058 hdac_command(sc, 1059 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1060 w->nid, w->wclass.pin.ctrl), cad); 1061 } 1062 } 1063 } 1064 /* (Un)Mute other pins. */ 1065 for (j = 0; j < 15; j++) { 1066 if (as[i].pins[j] <= 0) 1067 continue; 1068 ctl = hdac_audio_ctl_amp_get(devinfo, 1069 as[i].pins[j], HDA_CTL_IN, -1, 1); 1070 if (ctl != NULL && ctl->mute) { 1071 /* If pin has muter - use it. */ 1072 val = (res != 0) ? 1 : 0; 1073 if (val == ctl->forcemute) 1074 continue; 1075 ctl->forcemute = val; 1076 hdac_audio_ctl_amp_set(ctl, 1077 HDA_AMP_MUTE_DEFAULT, 1078 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1079 continue; 1080 } 1081 /* If there is no muter - disable pin output. */ 1082 w = hdac_widget_get(devinfo, as[i].pins[j]); 1083 if (w != NULL && w->type == 1084 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1085 if (res != 0) 1086 val = w->wclass.pin.ctrl & 1087 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1088 else 1089 val = w->wclass.pin.ctrl | 1090 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1091 if (val != w->wclass.pin.ctrl) { 1092 w->wclass.pin.ctrl = val; 1093 hdac_command(sc, 1094 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1095 w->nid, w->wclass.pin.ctrl), cad); 1096 } 1097 } 1098 } 1099 } 1100} 1101 1102/* 1103 * Callback for poll based jack detection. 1104 */ 1105static void 1106hdac_jack_poll_callback(void *arg) 1107{ 1108 struct hdac_devinfo *devinfo = arg; 1109 struct hdac_softc *sc; 1110 1111 if (devinfo == NULL || devinfo->codec == NULL || 1112 devinfo->codec->sc == NULL) 1113 return; 1114 sc = devinfo->codec->sc; 1115 hdac_lock(sc); 1116 if (sc->poll_ival == 0) { 1117 hdac_unlock(sc); 1118 return; 1119 } 1120 hdac_hp_switch_handler(devinfo); 1121 callout_reset(&sc->poll_jack, sc->poll_ival, 1122 hdac_jack_poll_callback, devinfo); 1123 hdac_unlock(sc); 1124} 1125 1126/* 1127 * Jack detection initializer. 1128 */ 1129static void 1130hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1131{ 1132 struct hdac_softc *sc = devinfo->codec->sc; 1133 struct hdac_audio_as *as = devinfo->function.audio.as; 1134 struct hdac_widget *w; 1135 uint32_t id; 1136 int i, enable = 0, poll = 0; 1137 nid_t cad; 1138 1139 id = hdac_codec_id(devinfo->codec); 1140 cad = devinfo->codec->cad; 1141 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1142 if (as[i].hpredir < 0) 1143 continue; 1144 1145 w = hdac_widget_get(devinfo, as[i].pins[15]); 1146 if (w == NULL || w->enable == 0 || w->type != 1147 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1148 continue; 1149 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1150 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1151 device_printf(sc->dev, 1152 "No jack detection support at pin %d\n", 1153 as[i].pins[15]); 1154 continue; 1155 } 1156 enable = 1; 1157 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1158 hdac_command(sc, 1159 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1160 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1161 HDAC_UNSOLTAG_EVENT_HP), cad); 1162 } else 1163 poll = 1; 1164 HDA_BOOTVERBOSE( 1165 device_printf(sc->dev, 1166 "Enabling headphone/speaker " 1167 "audio routing switching:\n"); 1168 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1169 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1170 ); 1171 } 1172 if (enable) { 1173 hdac_hp_switch_handler(devinfo); 1174 if (poll) { 1175 callout_reset(&sc->poll_jack, 1, 1176 hdac_jack_poll_callback, devinfo); 1177 } 1178 } 1179} 1180 1181/* 1182 * Unsolicited messages handler. 1183 */ 1184static void 1185hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1186{ 1187 struct hdac_softc *sc; 1188 struct hdac_devinfo *devinfo = NULL; 1189 int i; 1190 1191 if (codec == NULL || codec->sc == NULL) 1192 return; 1193 1194 sc = codec->sc; 1195 1196 HDA_BOOTVERBOSE( 1197 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1198 ); 1199 1200 for (i = 0; i < codec->num_fgs; i++) { 1201 if (codec->fgs[i].node_type == 1202 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1203 devinfo = &codec->fgs[i]; 1204 break; 1205 } 1206 } 1207 1208 if (devinfo == NULL) 1209 return; 1210 1211 switch (tag) { 1212 case HDAC_UNSOLTAG_EVENT_HP: 1213 hdac_hp_switch_handler(devinfo); 1214 break; 1215 default: 1216 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1217 break; 1218 } 1219} 1220 1221static int 1222hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1223{ 1224 /* XXX to be removed */ 1225#ifdef HDAC_INTR_EXTRA 1226 uint32_t res; 1227#endif 1228 1229 if (!(ch->flags & HDAC_CHN_RUNNING)) 1230 return (0); 1231 1232 /* XXX to be removed */ 1233#ifdef HDAC_INTR_EXTRA 1234 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1235#endif 1236 1237 /* XXX to be removed */ 1238#ifdef HDAC_INTR_EXTRA 1239 HDA_BOOTVERBOSE( 1240 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1241 device_printf(ch->pdevinfo->dev, 1242 "PCMDIR_%s intr triggered beyond stream boundary:" 1243 "%08x\n", 1244 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1245 ); 1246#endif 1247 1248 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1249 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1250 1251 /* XXX to be removed */ 1252#ifdef HDAC_INTR_EXTRA 1253 if (res & HDAC_SDSTS_BCIS) { 1254#endif 1255 return (1); 1256 /* XXX to be removed */ 1257#ifdef HDAC_INTR_EXTRA 1258 } 1259#endif 1260 1261 return (0); 1262} 1263 1264/**************************************************************************** 1265 * void hdac_intr_handler(void *) 1266 * 1267 * Interrupt handler. Processes interrupts received from the hdac. 1268 ****************************************************************************/ 1269static void 1270hdac_intr_handler(void *context) 1271{ 1272 struct hdac_softc *sc; 1273 uint32_t intsts; 1274 uint8_t rirbsts; 1275 struct hdac_rirb *rirb_base; 1276 uint32_t trigger; 1277 int i; 1278 1279 sc = (struct hdac_softc *)context; 1280 1281 hdac_lock(sc); 1282 if (sc->polling != 0) { 1283 hdac_unlock(sc); 1284 return; 1285 } 1286 1287 /* Do we have anything to do? */ 1288 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1289 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1290 hdac_unlock(sc); 1291 return; 1292 } 1293 1294 trigger = 0; 1295 1296 /* Was this a controller interrupt? */ 1297 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1298 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1299 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1300 /* Get as many responses that we can */ 1301 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1302 HDAC_WRITE_1(&sc->mem, 1303 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1304 if (hdac_rirb_flush(sc) != 0) 1305 trigger |= HDAC_TRIGGER_UNSOL; 1306 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1307 } 1308 /* XXX to be removed */ 1309 /* Clear interrupt and exit */ 1310#ifdef HDAC_INTR_EXTRA 1311 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1312#endif 1313 } 1314 1315 if (intsts & HDAC_INTSTS_SIS_MASK) { 1316 for (i = 0; i < sc->num_chans; i++) { 1317 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1318 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1319 trigger |= (1 << i); 1320 } 1321 /* XXX to be removed */ 1322#ifdef HDAC_INTR_EXTRA 1323 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1324 HDAC_INTSTS_SIS_MASK); 1325#endif 1326 } 1327 1328 hdac_unlock(sc); 1329 1330 for (i = 0; i < sc->num_chans; i++) { 1331 if (trigger & (1 << i)) 1332 chn_intr(sc->chans[i].c); 1333 } 1334 if (trigger & HDAC_TRIGGER_UNSOL) 1335 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1336} 1337 1338/**************************************************************************** 1339 * int hdac_reset(hdac_softc *, int) 1340 * 1341 * Reset the hdac to a quiescent and known state. 1342 ****************************************************************************/ 1343static int 1344hdac_reset(struct hdac_softc *sc, int wakeup) 1345{ 1346 uint32_t gctl; 1347 int count, i; 1348 1349 /* 1350 * Stop all Streams DMA engine 1351 */ 1352 for (i = 0; i < sc->num_iss; i++) 1353 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1354 for (i = 0; i < sc->num_oss; i++) 1355 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1356 for (i = 0; i < sc->num_bss; i++) 1357 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1358 1359 /* 1360 * Stop Control DMA engines. 1361 */ 1362 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1363 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1364 1365 /* 1366 * Reset DMA position buffer. 1367 */ 1368 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1369 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1370 1371 /* 1372 * Reset the controller. The reset must remain asserted for 1373 * a minimum of 100us. 1374 */ 1375 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1376 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1377 count = 10000; 1378 do { 1379 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1380 if (!(gctl & HDAC_GCTL_CRST)) 1381 break; 1382 DELAY(10); 1383 } while (--count); 1384 if (gctl & HDAC_GCTL_CRST) { 1385 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1386 return (ENXIO); 1387 } 1388 1389 /* If wakeup is not requested - leave the controller in reset state. */ 1390 if (!wakeup) 1391 return (0); 1392 1393 DELAY(100); 1394 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1395 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1396 count = 10000; 1397 do { 1398 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1399 if (gctl & HDAC_GCTL_CRST) 1400 break; 1401 DELAY(10); 1402 } while (--count); 1403 if (!(gctl & HDAC_GCTL_CRST)) { 1404 device_printf(sc->dev, "Device stuck in reset\n"); 1405 return (ENXIO); 1406 } 1407 1408 /* 1409 * Wait for codecs to finish their own reset sequence. The delay here 1410 * should be of 250us but for some reasons, on it's not enough on my 1411 * computer. Let's use twice as much as necessary to make sure that 1412 * it's reset properly. 1413 */ 1414 DELAY(1000); 1415 1416 return (0); 1417} 1418 1419 1420/**************************************************************************** 1421 * int hdac_get_capabilities(struct hdac_softc *); 1422 * 1423 * Retreive the general capabilities of the hdac; 1424 * Number of Input Streams 1425 * Number of Output Streams 1426 * Number of bidirectional Streams 1427 * 64bit ready 1428 * CORB and RIRB sizes 1429 ****************************************************************************/ 1430static int 1431hdac_get_capabilities(struct hdac_softc *sc) 1432{ 1433 uint16_t gcap; 1434 uint8_t corbsize, rirbsize; 1435 1436 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1437 sc->num_iss = HDAC_GCAP_ISS(gcap); 1438 sc->num_oss = HDAC_GCAP_OSS(gcap); 1439 sc->num_bss = HDAC_GCAP_BSS(gcap); 1440 1441 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1442 1443 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1444 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1445 HDAC_CORBSIZE_CORBSZCAP_256) 1446 sc->corb_size = 256; 1447 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1448 HDAC_CORBSIZE_CORBSZCAP_16) 1449 sc->corb_size = 16; 1450 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1451 HDAC_CORBSIZE_CORBSZCAP_2) 1452 sc->corb_size = 2; 1453 else { 1454 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1455 __func__, corbsize); 1456 return (ENXIO); 1457 } 1458 1459 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1460 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1461 HDAC_RIRBSIZE_RIRBSZCAP_256) 1462 sc->rirb_size = 256; 1463 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1464 HDAC_RIRBSIZE_RIRBSZCAP_16) 1465 sc->rirb_size = 16; 1466 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1467 HDAC_RIRBSIZE_RIRBSZCAP_2) 1468 sc->rirb_size = 2; 1469 else { 1470 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1471 __func__, rirbsize); 1472 return (ENXIO); 1473 } 1474 1475 HDA_BOOTHVERBOSE( 1476 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1477 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1478 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1479 sc->num_iss, sc->num_oss, sc->num_bss); 1480 ); 1481 1482 return (0); 1483} 1484 1485 1486/**************************************************************************** 1487 * void hdac_dma_cb 1488 * 1489 * This function is called by bus_dmamap_load when the mapping has been 1490 * established. We just record the physical address of the mapping into 1491 * the struct hdac_dma passed in. 1492 ****************************************************************************/ 1493static void 1494hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1495{ 1496 struct hdac_dma *dma; 1497 1498 if (error == 0) { 1499 dma = (struct hdac_dma *)callback_arg; 1500 dma->dma_paddr = segs[0].ds_addr; 1501 } 1502} 1503 1504 1505/**************************************************************************** 1506 * int hdac_dma_alloc 1507 * 1508 * This function allocate and setup a dma region (struct hdac_dma). 1509 * It must be freed by a corresponding hdac_dma_free. 1510 ****************************************************************************/ 1511static int 1512hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1513{ 1514 bus_size_t roundsz; 1515 int result; 1516 int lowaddr; 1517 1518 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1519 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1520 BUS_SPACE_MAXADDR_32BIT; 1521 bzero(dma, sizeof(*dma)); 1522 1523 /* 1524 * Create a DMA tag 1525 */ 1526 result = bus_dma_tag_create(NULL, /* parent */ 1527 HDAC_DMA_ALIGNMENT, /* alignment */ 1528 0, /* boundary */ 1529 lowaddr, /* lowaddr */ 1530 BUS_SPACE_MAXADDR, /* highaddr */ 1531 NULL, /* filtfunc */ 1532 NULL, /* fistfuncarg */ 1533 roundsz, /* maxsize */ 1534 1, /* nsegments */ 1535 roundsz, /* maxsegsz */ 1536 0, /* flags */ 1537 NULL, /* lockfunc */ 1538 NULL, /* lockfuncarg */ 1539 &dma->dma_tag); /* dmat */ 1540 if (result != 0) { 1541 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1542 __func__, result); 1543 goto hdac_dma_alloc_fail; 1544 } 1545 1546 /* 1547 * Allocate DMA memory 1548 */ 1549 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1550 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1551 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1552 &dma->dma_map); 1553 if (result != 0) { 1554 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1555 __func__, result); 1556 goto hdac_dma_alloc_fail; 1557 } 1558 1559 dma->dma_size = roundsz; 1560 1561 /* 1562 * Map the memory 1563 */ 1564 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1565 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1566 if (result != 0 || dma->dma_paddr == 0) { 1567 if (result == 0) 1568 result = ENOMEM; 1569 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1570 __func__, result); 1571 goto hdac_dma_alloc_fail; 1572 } 1573 1574 HDA_BOOTHVERBOSE( 1575 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1576 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1577 ); 1578 1579 return (0); 1580 1581hdac_dma_alloc_fail: 1582 hdac_dma_free(sc, dma); 1583 1584 return (result); 1585} 1586 1587 1588/**************************************************************************** 1589 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1590 * 1591 * Free a struct dhac_dma that has been previously allocated via the 1592 * hdac_dma_alloc function. 1593 ****************************************************************************/ 1594static void 1595hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1596{ 1597 if (dma->dma_map != NULL) { 1598#if 0 1599 /* Flush caches */ 1600 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1601 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1602#endif 1603 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1604 } 1605 if (dma->dma_vaddr != NULL) { 1606 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1607 dma->dma_vaddr = NULL; 1608 } 1609 dma->dma_map = NULL; 1610 if (dma->dma_tag != NULL) { 1611 bus_dma_tag_destroy(dma->dma_tag); 1612 dma->dma_tag = NULL; 1613 } 1614 dma->dma_size = 0; 1615} 1616 1617/**************************************************************************** 1618 * int hdac_mem_alloc(struct hdac_softc *) 1619 * 1620 * Allocate all the bus resources necessary to speak with the physical 1621 * controller. 1622 ****************************************************************************/ 1623static int 1624hdac_mem_alloc(struct hdac_softc *sc) 1625{ 1626 struct hdac_mem *mem; 1627 1628 mem = &sc->mem; 1629 mem->mem_rid = PCIR_BAR(0); 1630 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1631 &mem->mem_rid, RF_ACTIVE); 1632 if (mem->mem_res == NULL) { 1633 device_printf(sc->dev, 1634 "%s: Unable to allocate memory resource\n", __func__); 1635 return (ENOMEM); 1636 } 1637 mem->mem_tag = rman_get_bustag(mem->mem_res); 1638 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1639 1640 return (0); 1641} 1642 1643/**************************************************************************** 1644 * void hdac_mem_free(struct hdac_softc *) 1645 * 1646 * Free up resources previously allocated by hdac_mem_alloc. 1647 ****************************************************************************/ 1648static void 1649hdac_mem_free(struct hdac_softc *sc) 1650{ 1651 struct hdac_mem *mem; 1652 1653 mem = &sc->mem; 1654 if (mem->mem_res != NULL) 1655 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1656 mem->mem_res); 1657 mem->mem_res = NULL; 1658} 1659 1660/**************************************************************************** 1661 * int hdac_irq_alloc(struct hdac_softc *) 1662 * 1663 * Allocate and setup the resources necessary for interrupt handling. 1664 ****************************************************************************/ 1665static int 1666hdac_irq_alloc(struct hdac_softc *sc) 1667{ 1668 struct hdac_irq *irq; 1669 int result; 1670 1671 irq = &sc->irq; 1672 irq->irq_rid = 0x0; 1673 1674#ifdef HDAC_MSI_ENABLED 1675 if ((sc->flags & HDAC_F_MSI) && 1676 (result = pci_msi_count(sc->dev)) == 1 && 1677 pci_alloc_msi(sc->dev, &result) == 0) 1678 irq->irq_rid = 0x1; 1679 else 1680#endif 1681 sc->flags &= ~HDAC_F_MSI; 1682 1683 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1684 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1685 if (irq->irq_res == NULL) { 1686 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1687 __func__); 1688 goto hdac_irq_alloc_fail; 1689 } 1690 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1691 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1692 if (result != 0) { 1693 device_printf(sc->dev, 1694 "%s: Unable to setup interrupt handler (%x)\n", 1695 __func__, result); 1696 goto hdac_irq_alloc_fail; 1697 } 1698 1699 return (0); 1700 1701hdac_irq_alloc_fail: 1702 hdac_irq_free(sc); 1703 1704 return (ENXIO); 1705} 1706 1707/**************************************************************************** 1708 * void hdac_irq_free(struct hdac_softc *) 1709 * 1710 * Free up resources previously allocated by hdac_irq_alloc. 1711 ****************************************************************************/ 1712static void 1713hdac_irq_free(struct hdac_softc *sc) 1714{ 1715 struct hdac_irq *irq; 1716 1717 irq = &sc->irq; 1718 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1719 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1720 if (irq->irq_res != NULL) 1721 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1722 irq->irq_res); 1723#ifdef HDAC_MSI_ENABLED 1724 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1725 pci_release_msi(sc->dev); 1726#endif 1727 irq->irq_handle = NULL; 1728 irq->irq_res = NULL; 1729 irq->irq_rid = 0x0; 1730} 1731 1732/**************************************************************************** 1733 * void hdac_corb_init(struct hdac_softc *) 1734 * 1735 * Initialize the corb registers for operations but do not start it up yet. 1736 * The CORB engine must not be running when this function is called. 1737 ****************************************************************************/ 1738static void 1739hdac_corb_init(struct hdac_softc *sc) 1740{ 1741 uint8_t corbsize; 1742 uint64_t corbpaddr; 1743 1744 /* Setup the CORB size. */ 1745 switch (sc->corb_size) { 1746 case 256: 1747 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1748 break; 1749 case 16: 1750 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1751 break; 1752 case 2: 1753 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1754 break; 1755 default: 1756 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1757 } 1758 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1759 1760 /* Setup the CORB Address in the hdac */ 1761 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1762 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1763 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1764 1765 /* Set the WP and RP */ 1766 sc->corb_wp = 0; 1767 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1768 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1769 /* 1770 * The HDA specification indicates that the CORBRPRST bit will always 1771 * read as zero. Unfortunately, it seems that at least the 82801G 1772 * doesn't reset the bit to zero, which stalls the corb engine. 1773 * manually reset the bit to zero before continuing. 1774 */ 1775 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1776 1777 /* Enable CORB error reporting */ 1778#if 0 1779 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1780#endif 1781} 1782 1783/**************************************************************************** 1784 * void hdac_rirb_init(struct hdac_softc *) 1785 * 1786 * Initialize the rirb registers for operations but do not start it up yet. 1787 * The RIRB engine must not be running when this function is called. 1788 ****************************************************************************/ 1789static void 1790hdac_rirb_init(struct hdac_softc *sc) 1791{ 1792 uint8_t rirbsize; 1793 uint64_t rirbpaddr; 1794 1795 /* Setup the RIRB size. */ 1796 switch (sc->rirb_size) { 1797 case 256: 1798 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1799 break; 1800 case 16: 1801 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1802 break; 1803 case 2: 1804 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1805 break; 1806 default: 1807 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1808 } 1809 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1810 1811 /* Setup the RIRB Address in the hdac */ 1812 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1813 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1814 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1815 1816 /* Setup the WP and RP */ 1817 sc->rirb_rp = 0; 1818 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1819 1820 /* Setup the interrupt threshold */ 1821 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1822 1823 /* Enable Overrun and response received reporting */ 1824#if 0 1825 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1826 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1827#else 1828 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1829#endif 1830 1831#if 0 1832 /* 1833 * Make sure that the Host CPU cache doesn't contain any dirty 1834 * cache lines that falls in the rirb. If I understood correctly, it 1835 * should be sufficient to do this only once as the rirb is purely 1836 * read-only from now on. 1837 */ 1838 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1839 BUS_DMASYNC_PREREAD); 1840#endif 1841} 1842 1843/**************************************************************************** 1844 * void hdac_corb_start(hdac_softc *) 1845 * 1846 * Startup the corb DMA engine 1847 ****************************************************************************/ 1848static void 1849hdac_corb_start(struct hdac_softc *sc) 1850{ 1851 uint32_t corbctl; 1852 1853 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1854 corbctl |= HDAC_CORBCTL_CORBRUN; 1855 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1856} 1857 1858/**************************************************************************** 1859 * void hdac_rirb_start(hdac_softc *) 1860 * 1861 * Startup the rirb DMA engine 1862 ****************************************************************************/ 1863static void 1864hdac_rirb_start(struct hdac_softc *sc) 1865{ 1866 uint32_t rirbctl; 1867 1868 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1869 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1870 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1871} 1872 1873 1874/**************************************************************************** 1875 * void hdac_scan_codecs(struct hdac_softc *, int) 1876 * 1877 * Scan the bus for available codecs, starting with num. 1878 ****************************************************************************/ 1879static void 1880hdac_scan_codecs(struct hdac_softc *sc) 1881{ 1882 struct hdac_codec *codec; 1883 int i; 1884 uint16_t statests; 1885 1886 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1887 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1888 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1889 /* We have found a codec. */ 1890 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1891 M_HDAC, M_ZERO | M_NOWAIT); 1892 if (codec == NULL) { 1893 device_printf(sc->dev, 1894 "Unable to allocate memory for codec\n"); 1895 continue; 1896 } 1897 codec->commands = NULL; 1898 codec->responses_received = 0; 1899 codec->verbs_sent = 0; 1900 codec->sc = sc; 1901 codec->cad = i; 1902 sc->codecs[i] = codec; 1903 hdac_probe_codec(codec); 1904 } 1905 } 1906 /* All codecs have been probed, now try to attach drivers to them */ 1907 /* bus_generic_attach(sc->dev); */ 1908} 1909 1910/**************************************************************************** 1911 * void hdac_probe_codec(struct hdac_softc *, int) 1912 * 1913 * Probe a the given codec_id for available function groups. 1914 ****************************************************************************/ 1915static void 1916hdac_probe_codec(struct hdac_codec *codec) 1917{ 1918 struct hdac_softc *sc = codec->sc; 1919 uint32_t vendorid, revisionid, subnode; 1920 int startnode; 1921 int endnode; 1922 int i; 1923 nid_t cad = codec->cad; 1924 1925 HDA_BOOTVERBOSE( 1926 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1927 ); 1928 vendorid = hdac_command(sc, 1929 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1930 cad); 1931 revisionid = hdac_command(sc, 1932 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1933 cad); 1934 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1935 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1936 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1937 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1938 1939 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1940 device_printf(sc->dev, "Codec #%d is not responding!" 1941 " Probing aborted.\n", cad); 1942 return; 1943 } 1944 1945 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1946 cad, hdac_codec_name(codec)); 1947 HDA_BOOTVERBOSE( 1948 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1949 hdac_codec_id(codec)); 1950 device_printf(sc->dev, " Vendor: 0x%04x\n", 1951 codec->vendor_id); 1952 device_printf(sc->dev, " Device: 0x%04x\n", 1953 codec->device_id); 1954 device_printf(sc->dev, " Revision: 0x%02x\n", 1955 codec->revision_id); 1956 device_printf(sc->dev, " Stepping: 0x%02x\n", 1957 codec->stepping_id); 1958 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1959 sc->pci_subvendor); 1960 ); 1961 subnode = hdac_command(sc, 1962 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1963 cad); 1964 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1965 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1966 1967 HDA_BOOTHVERBOSE( 1968 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1969 startnode, endnode); 1970 ); 1971 1972 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1973 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1974 if (codec->fgs == NULL) { 1975 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1976 __func__); 1977 return; 1978 } 1979 1980 for (i = startnode; i < endnode; i++) 1981 hdac_probe_function(codec, i); 1982 return; 1983} 1984 1985/* 1986 * Probe codec function and add it to the list. 1987 */ 1988static void 1989hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1990{ 1991 struct hdac_softc *sc = codec->sc; 1992 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1993 uint32_t fctgrptype; 1994 uint32_t res; 1995 nid_t cad = codec->cad; 1996 1997 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1998 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1999 2000 devinfo->nid = nid; 2001 devinfo->node_type = fctgrptype; 2002 devinfo->codec = codec; 2003 2004 res = hdac_command(sc, 2005 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2006 2007 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2008 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2009 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2010 2011 HDA_BOOTVERBOSE( 2012 device_printf(sc->dev, 2013 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2014 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2015 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2016 "unknown", nid, devinfo->startnode, devinfo->endnode, 2017 devinfo->nodecnt); 2018 ); 2019 2020 if (devinfo->nodecnt > 0) 2021 devinfo->widget = (struct hdac_widget *)malloc( 2022 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2023 M_NOWAIT | M_ZERO); 2024 else 2025 devinfo->widget = NULL; 2026 2027 if (devinfo->widget == NULL) { 2028 device_printf(sc->dev, "unable to allocate widgets!\n"); 2029 devinfo->endnode = devinfo->startnode; 2030 devinfo->nodecnt = 0; 2031 return; 2032 } 2033 2034 codec->num_fgs++; 2035} 2036 2037static void 2038hdac_widget_connection_parse(struct hdac_widget *w) 2039{ 2040 struct hdac_softc *sc = w->devinfo->codec->sc; 2041 uint32_t res; 2042 int i, j, max, ents, entnum; 2043 nid_t cad = w->devinfo->codec->cad; 2044 nid_t nid = w->nid; 2045 nid_t cnid, addcnid, prevcnid; 2046 2047 w->nconns = 0; 2048 2049 res = hdac_command(sc, 2050 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2051 2052 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2053 2054 if (ents < 1) 2055 return; 2056 2057 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2058 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2059 prevcnid = 0; 2060 2061#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2062#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2063#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2064#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2065#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2066 2067 for (i = 0; i < ents; i += entnum) { 2068 res = hdac_command(sc, 2069 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2070 for (j = 0; j < entnum; j++) { 2071 cnid = CONN_CNID(res, entnum, j); 2072 if (cnid == 0) { 2073 if (w->nconns < ents) 2074 device_printf(sc->dev, 2075 "%s: nid=%d WARNING: zero cnid " 2076 "entnum=%d j=%d index=%d " 2077 "entries=%d found=%d res=0x%08x\n", 2078 __func__, nid, entnum, j, i, 2079 ents, w->nconns, res); 2080 else 2081 goto getconns_out; 2082 } 2083 if (cnid < w->devinfo->startnode || 2084 cnid >= w->devinfo->endnode) { 2085 HDA_BOOTVERBOSE( 2086 device_printf(sc->dev, 2087 "GHOST: nid=%d j=%d " 2088 "entnum=%d index=%d res=0x%08x\n", 2089 nid, j, entnum, i, res); 2090 ); 2091 } 2092 if (CONN_RANGE(res, entnum, j) == 0) 2093 addcnid = cnid; 2094 else if (prevcnid == 0 || prevcnid >= cnid) { 2095 device_printf(sc->dev, 2096 "%s: WARNING: Invalid child range " 2097 "nid=%d index=%d j=%d entnum=%d " 2098 "prevcnid=%d cnid=%d res=0x%08x\n", 2099 __func__, nid, i, j, entnum, prevcnid, 2100 cnid, res); 2101 addcnid = cnid; 2102 } else 2103 addcnid = prevcnid + 1; 2104 while (addcnid <= cnid) { 2105 if (w->nconns > max) { 2106 device_printf(sc->dev, 2107 "Adding %d (nid=%d): " 2108 "Max connection reached! max=%d\n", 2109 addcnid, nid, max + 1); 2110 goto getconns_out; 2111 } 2112 w->connsenable[w->nconns] = 1; 2113 w->conns[w->nconns++] = addcnid++; 2114 } 2115 prevcnid = cnid; 2116 } 2117 } 2118 2119getconns_out: 2120 return; 2121} 2122 2123static uint32_t 2124hdac_widget_pin_patch(uint32_t config, const char *str) 2125{ 2126 char buf[256]; 2127 char *key, *value, *rest, *bad; 2128 int ival, i; 2129 2130 strlcpy(buf, str, sizeof(buf)); 2131 rest = buf; 2132 while ((key = strsep(&rest, "=")) != NULL) { 2133 value = strsep(&rest, " \t"); 2134 if (value == NULL) 2135 break; 2136 ival = strtol(value, &bad, 10); 2137 if (strcmp(key, "seq") == 0) { 2138 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2139 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2140 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2141 } else if (strcmp(key, "as") == 0) { 2142 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2143 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2144 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2145 } else if (strcmp(key, "misc") == 0) { 2146 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2147 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2148 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2149 } else if (strcmp(key, "color") == 0) { 2150 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2151 if (bad[0] == 0) { 2152 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2153 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2154 }; 2155 for (i = 0; i < 16; i++) { 2156 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2157 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2158 break; 2159 } 2160 } 2161 } else if (strcmp(key, "ctype") == 0) { 2162 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2163 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2164 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2165 } else if (strcmp(key, "device") == 0) { 2166 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2167 if (bad[0] == 0) { 2168 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2169 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2170 continue; 2171 }; 2172 for (i = 0; i < 16; i++) { 2173 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2174 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2175 break; 2176 } 2177 } 2178 } else if (strcmp(key, "loc") == 0) { 2179 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2180 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2181 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2182 } else if (strcmp(key, "conn") == 0) { 2183 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2184 if (bad[0] == 0) { 2185 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2186 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2187 continue; 2188 }; 2189 for (i = 0; i < 4; i++) { 2190 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2191 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2192 break; 2193 } 2194 } 2195 } 2196 } 2197 return (config); 2198} 2199 2200static uint32_t 2201hdac_widget_pin_getconfig(struct hdac_widget *w) 2202{ 2203 struct hdac_softc *sc; 2204 uint32_t config, orig, id; 2205 nid_t cad, nid; 2206 char buf[32]; 2207 const char *res = NULL, *patch = NULL; 2208 2209 sc = w->devinfo->codec->sc; 2210 cad = w->devinfo->codec->cad; 2211 nid = w->nid; 2212 id = hdac_codec_id(w->devinfo->codec); 2213 2214 config = hdac_command(sc, 2215 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2216 cad); 2217 orig = config; 2218 2219 HDA_BOOTVERBOSE( 2220 hdac_dump_pin_config(w, orig); 2221 ); 2222 2223 /* XXX: Old patches require complete review. 2224 * Now they may create more problem then solve due to 2225 * incorrect associations. 2226 */ 2227 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2228 switch (nid) { 2229 case 26: 2230 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2231 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2232 break; 2233 case 27: 2234 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2235 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2236 break; 2237 default: 2238 break; 2239 } 2240 } else if (id == HDA_CODEC_ALC880 && 2241 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2242 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2243 /* 2244 * Super broken BIOS 2245 */ 2246 switch (nid) { 2247 case 24: /* MIC1 */ 2248 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2249 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2250 break; 2251 case 25: /* XXX MIC2 */ 2252 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2253 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2254 break; 2255 case 26: /* LINE1 */ 2256 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2257 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2258 break; 2259 case 27: /* XXX LINE2 */ 2260 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2261 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2262 break; 2263 case 28: /* CD */ 2264 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2265 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2266 break; 2267 } 2268 } else if (id == HDA_CODEC_ALC883 && 2269 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2270 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2271 switch (nid) { 2272 case 25: 2273 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2274 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2275 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2276 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2277 break; 2278 case 28: 2279 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2280 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2281 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2282 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2283 break; 2284 } 2285 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2286 HP_V3000_SUBVENDOR) { 2287 switch (nid) { 2288 case 18: 2289 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2290 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2291 break; 2292 case 20: 2293 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2294 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2295 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2296 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2297 break; 2298 case 21: 2299 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2300 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2301 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2302 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2303 break; 2304 } 2305 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2306 HP_DV5000_SUBVENDOR) { 2307 switch (nid) { 2308 case 20: 2309 case 21: 2310 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2311 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2312 break; 2313 } 2314 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2315 ASUS_W6F_SUBVENDOR) { 2316 switch (nid) { 2317 case 11: 2318 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2319 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2320 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2321 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2322 break; 2323 case 12: 2324 case 14: 2325 case 16: 2326 case 31: 2327 case 32: 2328 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2329 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2330 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2331 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2332 break; 2333 case 15: 2334 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2335 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2336 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2337 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2338 break; 2339 } 2340 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2341 UNIWILL_9075_SUBVENDOR) { 2342 switch (nid) { 2343 case 15: 2344 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2345 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2346 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2347 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2348 break; 2349 } 2350 } 2351 2352 /* New patches */ 2353 if (id == HDA_CODEC_AD1986A && 2354 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2355 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2356 switch (nid) { 2357 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2358 patch = "device=Line-in as=8 seq=1"; 2359 break; 2360 case 29: 2361 patch = "device=Mic as=8 seq=2"; 2362 break; 2363 case 31: /* Lot of inputs configured with as=15 and unusable */ 2364 patch = "as=8 seq=3"; 2365 break; 2366 case 32: 2367 patch = "as=8 seq=4"; 2368 break; 2369 case 34: 2370 patch = "as=8 seq=5"; 2371 break; 2372 case 36: 2373 patch = "as=8 seq=6"; 2374 break; 2375 } 2376 } else if (id == HDA_CODEC_ALC260 && 2377 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2378 switch (nid) { 2379 case 16: 2380 patch = "seq=15 device=Headphones"; 2381 break; 2382 } 2383 } else if (id == HDA_CODEC_ALC268 && 2384 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2385 switch (nid) { 2386 case 28: 2387 patch = "device=CD conn=fixed"; 2388 break; 2389 } 2390 } 2391 2392 if (patch != NULL) 2393 config = hdac_widget_pin_patch(config, patch); 2394 2395 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2396 if (resource_string_value(device_get_name(sc->dev), 2397 device_get_unit(sc->dev), buf, &res) == 0) { 2398 if (strncmp(res, "0x", 2) == 0) { 2399 config = strtol(res + 2, NULL, 16); 2400 } else { 2401 config = hdac_widget_pin_patch(config, res); 2402 } 2403 } 2404 2405 HDA_BOOTVERBOSE( 2406 if (config != orig) 2407 device_printf(sc->dev, 2408 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2409 nid, orig, config); 2410 ); 2411 2412 return (config); 2413} 2414 2415static uint32_t 2416hdac_widget_pin_getcaps(struct hdac_widget *w) 2417{ 2418 struct hdac_softc *sc; 2419 uint32_t caps, orig, id; 2420 nid_t cad, nid; 2421 2422 sc = w->devinfo->codec->sc; 2423 cad = w->devinfo->codec->cad; 2424 nid = w->nid; 2425 id = hdac_codec_id(w->devinfo->codec); 2426 2427 caps = hdac_command(sc, 2428 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2429 orig = caps; 2430 2431 HDA_BOOTVERBOSE( 2432 if (caps != orig) 2433 device_printf(sc->dev, 2434 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2435 nid, orig, caps); 2436 ); 2437 2438 return (caps); 2439} 2440 2441static void 2442hdac_widget_pin_parse(struct hdac_widget *w) 2443{ 2444 struct hdac_softc *sc = w->devinfo->codec->sc; 2445 uint32_t config, pincap; 2446 const char *devstr; 2447 nid_t cad = w->devinfo->codec->cad; 2448 nid_t nid = w->nid; 2449 int conn, color; 2450 2451 config = hdac_widget_pin_getconfig(w); 2452 w->wclass.pin.config = config; 2453 2454 pincap = hdac_widget_pin_getcaps(w); 2455 w->wclass.pin.cap = pincap; 2456 2457 w->wclass.pin.ctrl = hdac_command(sc, 2458 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2459 2460 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2461 w->param.eapdbtl = hdac_command(sc, 2462 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2463 w->param.eapdbtl &= 0x7; 2464 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2465 } else 2466 w->param.eapdbtl = HDAC_INVALID; 2467 2468 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2469 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2470 2471 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2472 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2473 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2474 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2475 2476 strlcat(w->name, ": ", sizeof(w->name)); 2477 strlcat(w->name, devstr, sizeof(w->name)); 2478 strlcat(w->name, " (", sizeof(w->name)); 2479 if (conn == 0 && color != 0 && color != 15) { 2480 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2481 strlcat(w->name, " ", sizeof(w->name)); 2482 } 2483 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2484 strlcat(w->name, ")", sizeof(w->name)); 2485} 2486 2487static uint32_t 2488hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2489{ 2490 struct hdac_softc *sc; 2491 uint32_t caps, orig, id; 2492 nid_t cad, nid, beeper = -1; 2493 2494 sc = w->devinfo->codec->sc; 2495 cad = w->devinfo->codec->cad; 2496 nid = w->nid; 2497 id = hdac_codec_id(w->devinfo->codec); 2498 2499 caps = hdac_command(sc, 2500 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2501 cad); 2502 orig = caps; 2503 2504 /* On some codecs beeper is an input pin, but it is not recordable 2505 alone. Also most of BIOSes does not declare beeper pin. 2506 Change beeper pin node type to beeper to help parser. */ 2507 *waspin = 0; 2508 switch (id) { 2509 case HDA_CODEC_AD1988: 2510 case HDA_CODEC_AD1988B: 2511 beeper = 26; 2512 break; 2513 case HDA_CODEC_ALC260: 2514 beeper = 23; 2515 break; 2516 case HDA_CODEC_ALC262: 2517 case HDA_CODEC_ALC268: 2518 case HDA_CODEC_ALC880: 2519 case HDA_CODEC_ALC882: 2520 case HDA_CODEC_ALC883: 2521 case HDA_CODEC_ALC885: 2522 case HDA_CODEC_ALC888: 2523 case HDA_CODEC_ALC889: 2524 beeper = 29; 2525 break; 2526 } 2527 if (nid == beeper) { 2528 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2529 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2530 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2531 *waspin = 1; 2532 } 2533 2534 HDA_BOOTVERBOSE( 2535 if (caps != orig) { 2536 device_printf(sc->dev, 2537 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2538 nid, orig, caps); 2539 } 2540 ); 2541 2542 return (caps); 2543} 2544 2545static void 2546hdac_widget_parse(struct hdac_widget *w) 2547{ 2548 struct hdac_softc *sc = w->devinfo->codec->sc; 2549 uint32_t wcap, cap; 2550 char *typestr; 2551 nid_t cad = w->devinfo->codec->cad; 2552 nid_t nid = w->nid; 2553 2554 wcap = hdac_widget_getcaps(w, &w->waspin); 2555 2556 w->param.widget_cap = wcap; 2557 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2558 2559 switch (w->type) { 2560 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2561 typestr = "audio output"; 2562 break; 2563 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2564 typestr = "audio input"; 2565 break; 2566 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2567 typestr = "audio mixer"; 2568 break; 2569 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2570 typestr = "audio selector"; 2571 break; 2572 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2573 typestr = "pin"; 2574 break; 2575 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2576 typestr = "power widget"; 2577 break; 2578 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2579 typestr = "volume widget"; 2580 break; 2581 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2582 typestr = "beep widget"; 2583 break; 2584 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2585 typestr = "vendor widget"; 2586 break; 2587 default: 2588 typestr = "unknown type"; 2589 break; 2590 } 2591 2592 strlcpy(w->name, typestr, sizeof(w->name)); 2593 2594 hdac_widget_connection_parse(w); 2595 2596 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2597 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2598 w->param.outamp_cap = 2599 hdac_command(sc, 2600 HDA_CMD_GET_PARAMETER(cad, nid, 2601 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2602 else 2603 w->param.outamp_cap = 2604 w->devinfo->function.audio.outamp_cap; 2605 } else 2606 w->param.outamp_cap = 0; 2607 2608 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2609 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2610 w->param.inamp_cap = 2611 hdac_command(sc, 2612 HDA_CMD_GET_PARAMETER(cad, nid, 2613 HDA_PARAM_INPUT_AMP_CAP), cad); 2614 else 2615 w->param.inamp_cap = 2616 w->devinfo->function.audio.inamp_cap; 2617 } else 2618 w->param.inamp_cap = 0; 2619 2620 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2621 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2622 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2623 cap = hdac_command(sc, 2624 HDA_CMD_GET_PARAMETER(cad, nid, 2625 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2626 w->param.supp_stream_formats = (cap != 0) ? cap : 2627 w->devinfo->function.audio.supp_stream_formats; 2628 cap = hdac_command(sc, 2629 HDA_CMD_GET_PARAMETER(cad, nid, 2630 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2631 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2632 w->devinfo->function.audio.supp_pcm_size_rate; 2633 } else { 2634 w->param.supp_stream_formats = 2635 w->devinfo->function.audio.supp_stream_formats; 2636 w->param.supp_pcm_size_rate = 2637 w->devinfo->function.audio.supp_pcm_size_rate; 2638 } 2639 } else { 2640 w->param.supp_stream_formats = 0; 2641 w->param.supp_pcm_size_rate = 0; 2642 } 2643 2644 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2645 hdac_widget_pin_parse(w); 2646} 2647 2648static struct hdac_widget * 2649hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2650{ 2651 if (devinfo == NULL || devinfo->widget == NULL || 2652 nid < devinfo->startnode || nid >= devinfo->endnode) 2653 return (NULL); 2654 return (&devinfo->widget[nid - devinfo->startnode]); 2655} 2656 2657static __inline int 2658hda_poll_channel(struct hdac_chan *ch) 2659{ 2660 uint32_t sz, delta; 2661 volatile uint32_t ptr; 2662 2663 if (!(ch->flags & HDAC_CHN_RUNNING)) 2664 return (0); 2665 2666 sz = ch->blksz * ch->blkcnt; 2667 if (ch->dmapos != NULL) 2668 ptr = *(ch->dmapos); 2669 else 2670 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2671 ch->off + HDAC_SDLPIB); 2672 ch->ptr = ptr; 2673 ptr %= sz; 2674 ptr &= ~(ch->blksz - 1); 2675 delta = (sz + ptr - ch->prevptr) % sz; 2676 2677 if (delta < ch->blksz) 2678 return (0); 2679 2680 ch->prevptr = ptr; 2681 2682 return (1); 2683} 2684 2685static void 2686hda_poll_callback(void *arg) 2687{ 2688 struct hdac_softc *sc = arg; 2689 uint32_t trigger; 2690 int i, active = 0; 2691 2692 if (sc == NULL) 2693 return; 2694 2695 hdac_lock(sc); 2696 if (sc->polling == 0) { 2697 hdac_unlock(sc); 2698 return; 2699 } 2700 2701 trigger = 0; 2702 for (i = 0; i < sc->num_chans; i++) { 2703 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2704 continue; 2705 active = 1; 2706 if (hda_poll_channel(&sc->chans[i])) 2707 trigger |= (1 << i); 2708 } 2709 2710 /* XXX */ 2711 if (active) 2712 callout_reset(&sc->poll_hda, sc->poll_ticks, 2713 hda_poll_callback, sc); 2714 2715 hdac_unlock(sc); 2716 2717 for (i = 0; i < sc->num_chans; i++) { 2718 if (trigger & (1 << i)) 2719 chn_intr(sc->chans[i].c); 2720 } 2721} 2722 2723static int 2724hdac_rirb_flush(struct hdac_softc *sc) 2725{ 2726 struct hdac_rirb *rirb_base, *rirb; 2727 struct hdac_codec *codec; 2728 struct hdac_command_list *commands; 2729 nid_t cad; 2730 uint32_t resp; 2731 uint8_t rirbwp; 2732 int ret; 2733 2734 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2735 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2736#if 0 2737 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2738 BUS_DMASYNC_POSTREAD); 2739#endif 2740 2741 ret = 0; 2742 2743 while (sc->rirb_rp != rirbwp) { 2744 sc->rirb_rp++; 2745 sc->rirb_rp %= sc->rirb_size; 2746 rirb = &rirb_base[sc->rirb_rp]; 2747 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2748 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2749 sc->codecs[cad] == NULL) 2750 continue; 2751 resp = rirb->response; 2752 codec = sc->codecs[cad]; 2753 commands = codec->commands; 2754 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2755 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2756 ((resp >> 26) & 0xffff); 2757 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2758 } else if (commands != NULL && commands->num_commands > 0 && 2759 codec->responses_received < commands->num_commands) 2760 commands->responses[codec->responses_received++] = 2761 resp; 2762 ret++; 2763 } 2764 2765 return (ret); 2766} 2767 2768static int 2769hdac_unsolq_flush(struct hdac_softc *sc) 2770{ 2771 nid_t cad; 2772 uint32_t tag; 2773 int ret = 0; 2774 2775 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2776 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2777 while (sc->unsolq_rp != sc->unsolq_wp) { 2778 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2779 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2780 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2781 hdac_unsolicited_handler(sc->codecs[cad], tag); 2782 ret++; 2783 } 2784 sc->unsolq_st = HDAC_UNSOLQ_READY; 2785 } 2786 2787 return (ret); 2788} 2789 2790static void 2791hdac_poll_callback(void *arg) 2792{ 2793 struct hdac_softc *sc = arg; 2794 if (sc == NULL) 2795 return; 2796 2797 hdac_lock(sc); 2798 if (sc->polling == 0 || sc->poll_ival == 0) { 2799 hdac_unlock(sc); 2800 return; 2801 } 2802 if (hdac_rirb_flush(sc) != 0) 2803 hdac_unsolq_flush(sc); 2804 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2805 hdac_unlock(sc); 2806} 2807 2808static void 2809hdac_poll_reinit(struct hdac_softc *sc) 2810{ 2811 int i, pollticks, min = 1000000; 2812 struct hdac_chan *ch; 2813 2814 for (i = 0; i < sc->num_chans; i++) { 2815 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2816 continue; 2817 ch = &sc->chans[i]; 2818 pollticks = ((uint64_t)hz * ch->blksz) / 2819 ((uint64_t)sndbuf_getbps(ch->b) * 2820 sndbuf_getspd(ch->b)); 2821 pollticks >>= 1; 2822 if (pollticks > hz) 2823 pollticks = hz; 2824 if (pollticks < 1) { 2825 HDA_BOOTVERBOSE( 2826 device_printf(sc->dev, 2827 "%s: pollticks=%d < 1 !\n", 2828 __func__, pollticks); 2829 ); 2830 pollticks = 1; 2831 } 2832 if (min > pollticks) 2833 min = pollticks; 2834 } 2835 HDA_BOOTVERBOSE( 2836 device_printf(sc->dev, 2837 "%s: pollticks %d -> %d\n", 2838 __func__, sc->poll_ticks, min); 2839 ); 2840 sc->poll_ticks = min; 2841 if (min == 1000000) 2842 callout_stop(&sc->poll_hda); 2843 else 2844 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2845} 2846 2847static void 2848hdac_stream_stop(struct hdac_chan *ch) 2849{ 2850 struct hdac_softc *sc = ch->devinfo->codec->sc; 2851 uint32_t ctl; 2852 2853 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2854 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2855 HDAC_SDCTL_RUN); 2856 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2857 2858 ch->flags &= ~HDAC_CHN_RUNNING; 2859 2860 if (sc->polling != 0) 2861 hdac_poll_reinit(sc); 2862 2863 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2864 ctl &= ~(1 << (ch->off >> 5)); 2865 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2866} 2867 2868static void 2869hdac_stream_start(struct hdac_chan *ch) 2870{ 2871 struct hdac_softc *sc = ch->devinfo->codec->sc; 2872 uint32_t ctl; 2873 2874 ch->flags |= HDAC_CHN_RUNNING; 2875 2876 if (sc->polling != 0) 2877 hdac_poll_reinit(sc); 2878 2879 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2880 ctl |= 1 << (ch->off >> 5); 2881 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2882 2883 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2884 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2885 HDAC_SDCTL_RUN; 2886 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2887} 2888 2889static void 2890hdac_stream_reset(struct hdac_chan *ch) 2891{ 2892 struct hdac_softc *sc = ch->devinfo->codec->sc; 2893 int timeout = 1000; 2894 int to = timeout; 2895 uint32_t ctl; 2896 2897 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2898 ctl |= HDAC_SDCTL_SRST; 2899 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2900 do { 2901 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2902 if (ctl & HDAC_SDCTL_SRST) 2903 break; 2904 DELAY(10); 2905 } while (--to); 2906 if (!(ctl & HDAC_SDCTL_SRST)) { 2907 device_printf(sc->dev, "timeout in reset\n"); 2908 } 2909 ctl &= ~HDAC_SDCTL_SRST; 2910 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2911 to = timeout; 2912 do { 2913 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2914 if (!(ctl & HDAC_SDCTL_SRST)) 2915 break; 2916 DELAY(10); 2917 } while (--to); 2918 if (ctl & HDAC_SDCTL_SRST) 2919 device_printf(sc->dev, "can't reset!\n"); 2920} 2921 2922static void 2923hdac_stream_setid(struct hdac_chan *ch) 2924{ 2925 struct hdac_softc *sc = ch->devinfo->codec->sc; 2926 uint32_t ctl; 2927 2928 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2929 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2930 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2931 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2932} 2933 2934static void 2935hdac_bdl_setup(struct hdac_chan *ch) 2936{ 2937 struct hdac_softc *sc = ch->devinfo->codec->sc; 2938 struct hdac_bdle *bdle; 2939 uint64_t addr; 2940 uint32_t blksz, blkcnt; 2941 int i; 2942 2943 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2944 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2945 2946 blksz = ch->blksz; 2947 blkcnt = ch->blkcnt; 2948 2949 for (i = 0; i < blkcnt; i++, bdle++) { 2950 bdle->addrl = (uint32_t)addr; 2951 bdle->addrh = (uint32_t)(addr >> 32); 2952 bdle->len = blksz; 2953 bdle->ioc = 1; 2954 addr += blksz; 2955 } 2956 2957 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2958 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2959 addr = ch->bdl_dma.dma_paddr; 2960 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2961 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2962 if (ch->dmapos != NULL && 2963 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2964 addr = sc->pos_dma.dma_paddr; 2965 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2966 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2967 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2968 } 2969} 2970 2971static int 2972hdac_bdl_alloc(struct hdac_chan *ch) 2973{ 2974 struct hdac_softc *sc = ch->devinfo->codec->sc; 2975 int rc; 2976 2977 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2978 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2979 if (rc) { 2980 device_printf(sc->dev, "can't alloc bdl\n"); 2981 return (rc); 2982 } 2983 2984 return (0); 2985} 2986 2987static void 2988hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2989 int index, int lmute, int rmute, 2990 int left, int right, int dir) 2991{ 2992 uint16_t v = 0; 2993 2994 if (sc == NULL) 2995 return; 2996 2997 if (left != right || lmute != rmute) { 2998 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2999 (lmute << 7) | left; 3000 hdac_command(sc, 3001 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3002 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3003 (rmute << 7) | right; 3004 } else 3005 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3006 (lmute << 7) | left; 3007 3008 hdac_command(sc, 3009 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3010} 3011 3012static void 3013hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3014 int left, int right) 3015{ 3016 struct hdac_softc *sc; 3017 nid_t nid, cad; 3018 int lmute, rmute; 3019 3020 sc = ctl->widget->devinfo->codec->sc; 3021 cad = ctl->widget->devinfo->codec->cad; 3022 nid = ctl->widget->nid; 3023 3024 /* Save new values if valid. */ 3025 if (mute != HDA_AMP_MUTE_DEFAULT) 3026 ctl->muted = mute; 3027 if (left != HDA_AMP_VOL_DEFAULT) 3028 ctl->left = left; 3029 if (right != HDA_AMP_VOL_DEFAULT) 3030 ctl->right = right; 3031 /* Prepare effective values */ 3032 if (ctl->forcemute) { 3033 lmute = 1; 3034 rmute = 1; 3035 left = 0; 3036 right = 0; 3037 } else { 3038 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3039 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3040 left = ctl->left; 3041 right = ctl->right; 3042 } 3043 /* Apply effective values */ 3044 if (ctl->dir & HDA_CTL_OUT) 3045 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3046 lmute, rmute, left, right, 0); 3047 if (ctl->dir & HDA_CTL_IN) 3048 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3049 lmute, rmute, left, right, 1); 3050} 3051 3052static void 3053hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3054{ 3055 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3056 return; 3057 hdac_command(w->devinfo->codec->sc, 3058 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3059 w->nid, index), w->devinfo->codec->cad); 3060 w->selconn = index; 3061} 3062 3063 3064/**************************************************************************** 3065 * uint32_t hdac_command_sendone_internal 3066 * 3067 * Wrapper function that sends only one command to a given codec 3068 ****************************************************************************/ 3069static uint32_t 3070hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3071{ 3072 struct hdac_command_list cl; 3073 uint32_t response = HDAC_INVALID; 3074 3075 if (!hdac_lockowned(sc)) 3076 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3077 cl.num_commands = 1; 3078 cl.verbs = &verb; 3079 cl.responses = &response; 3080 3081 hdac_command_send_internal(sc, &cl, cad); 3082 3083 return (response); 3084} 3085 3086/**************************************************************************** 3087 * hdac_command_send_internal 3088 * 3089 * Send a command list to the codec via the corb. We queue as much verbs as 3090 * we can and msleep on the codec. When the interrupt get the responses 3091 * back from the rirb, it will wake us up so we can queue the remaining verbs 3092 * if any. 3093 ****************************************************************************/ 3094static void 3095hdac_command_send_internal(struct hdac_softc *sc, 3096 struct hdac_command_list *commands, nid_t cad) 3097{ 3098 struct hdac_codec *codec; 3099 int corbrp; 3100 uint32_t *corb; 3101 int timeout; 3102 int retry = 10; 3103 struct hdac_rirb *rirb_base; 3104 3105 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3106 commands->num_commands < 1) 3107 return; 3108 3109 codec = sc->codecs[cad]; 3110 codec->commands = commands; 3111 codec->responses_received = 0; 3112 codec->verbs_sent = 0; 3113 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3114 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3115 3116 do { 3117 if (codec->verbs_sent != commands->num_commands) { 3118 /* Queue as many verbs as possible */ 3119 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3120#if 0 3121 bus_dmamap_sync(sc->corb_dma.dma_tag, 3122 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3123#endif 3124 while (codec->verbs_sent != commands->num_commands && 3125 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3126 sc->corb_wp++; 3127 sc->corb_wp %= sc->corb_size; 3128 corb[sc->corb_wp] = 3129 commands->verbs[codec->verbs_sent++]; 3130 } 3131 3132 /* Send the verbs to the codecs */ 3133#if 0 3134 bus_dmamap_sync(sc->corb_dma.dma_tag, 3135 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3136#endif 3137 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3138 } 3139 3140 timeout = 1000; 3141 while (hdac_rirb_flush(sc) == 0 && --timeout) 3142 DELAY(10); 3143 } while ((codec->verbs_sent != commands->num_commands || 3144 codec->responses_received != commands->num_commands) && --retry); 3145 3146 if (retry == 0) 3147 device_printf(sc->dev, 3148 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3149 __func__, commands->num_commands, codec->verbs_sent, 3150 codec->responses_received); 3151 3152 codec->commands = NULL; 3153 codec->responses_received = 0; 3154 codec->verbs_sent = 0; 3155 3156 hdac_unsolq_flush(sc); 3157} 3158 3159 3160/**************************************************************************** 3161 * Device Methods 3162 ****************************************************************************/ 3163 3164/**************************************************************************** 3165 * int hdac_probe(device_t) 3166 * 3167 * Probe for the presence of an hdac. If none is found, check for a generic 3168 * match using the subclass of the device. 3169 ****************************************************************************/ 3170static int 3171hdac_probe(device_t dev) 3172{ 3173 int i, result; 3174 uint32_t model; 3175 uint16_t class, subclass; 3176 char desc[64]; 3177 3178 model = (uint32_t)pci_get_device(dev) << 16; 3179 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3180 class = pci_get_class(dev); 3181 subclass = pci_get_subclass(dev); 3182 3183 bzero(desc, sizeof(desc)); 3184 result = ENXIO; 3185 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3186 if (hdac_devices[i].model == model) { 3187 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3188 result = BUS_PROBE_DEFAULT; 3189 break; 3190 } 3191 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3192 class == PCIC_MULTIMEDIA && 3193 subclass == PCIS_MULTIMEDIA_HDA) { 3194 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3195 result = BUS_PROBE_GENERIC; 3196 break; 3197 } 3198 } 3199 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3200 subclass == PCIS_MULTIMEDIA_HDA) { 3201 strlcpy(desc, "Generic", sizeof(desc)); 3202 result = BUS_PROBE_GENERIC; 3203 } 3204 if (result != ENXIO) { 3205 strlcat(desc, " High Definition Audio Controller", 3206 sizeof(desc)); 3207 device_set_desc_copy(dev, desc); 3208 } 3209 3210 return (result); 3211} 3212 3213static void * 3214hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3215 struct pcm_channel *c, int dir) 3216{ 3217 struct hdac_pcm_devinfo *pdevinfo = data; 3218 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3219 struct hdac_softc *sc = devinfo->codec->sc; 3220 struct hdac_chan *ch; 3221 int i, ord = 0, chid; 3222 3223 hdac_lock(sc); 3224 3225 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3226 ch = &sc->chans[chid]; 3227 for (i = 0; i < sc->num_chans && i < chid; i++) { 3228 if (ch->dir == sc->chans[i].dir) 3229 ord++; 3230 } 3231 if (dir == PCMDIR_PLAY) { 3232 ch->off = (sc->num_iss + ord) << 5; 3233 } else { 3234 ch->off = ord << 5; 3235 } 3236 3237 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3238 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3239 ch->pcmrates[0] = 48000; 3240 ch->pcmrates[1] = 0; 3241 } 3242 if (sc->pos_dma.dma_vaddr != NULL) 3243 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3244 (sc->streamcnt * 8)); 3245 else 3246 ch->dmapos = NULL; 3247 ch->sid = ++sc->streamcnt; 3248 ch->dir = dir; 3249 ch->b = b; 3250 ch->c = c; 3251 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3252 ch->blkcnt = pdevinfo->chan_blkcnt; 3253 hdac_unlock(sc); 3254 3255 if (hdac_bdl_alloc(ch) != 0) { 3256 ch->blkcnt = 0; 3257 return (NULL); 3258 } 3259 3260 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3261 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3262 pdevinfo->chan_size) != 0) 3263 return (NULL); 3264 3265 return (ch); 3266} 3267 3268static int 3269hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3270{ 3271 struct hdac_chan *ch = data; 3272 int i; 3273 3274 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3275 if (format == ch->caps.fmtlist[i]) { 3276 ch->fmt = format; 3277 return (0); 3278 } 3279 } 3280 3281 return (EINVAL); 3282} 3283 3284static int 3285hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3286{ 3287 struct hdac_chan *ch = data; 3288 uint32_t spd = 0, threshold; 3289 int i; 3290 3291 for (i = 0; ch->pcmrates[i] != 0; i++) { 3292 spd = ch->pcmrates[i]; 3293 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3294 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3295 if (speed < threshold) 3296 break; 3297 } 3298 3299 if (spd == 0) /* impossible */ 3300 ch->spd = 48000; 3301 else 3302 ch->spd = spd; 3303 3304 return (ch->spd); 3305} 3306 3307static void 3308hdac_stream_setup(struct hdac_chan *ch) 3309{ 3310 struct hdac_softc *sc = ch->devinfo->codec->sc; 3311 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3312 struct hdac_widget *w; 3313 int i, chn, totalchn, c; 3314 nid_t cad = ch->devinfo->codec->cad; 3315 uint16_t fmt, dfmt; 3316 3317 HDA_BOOTHVERBOSE( 3318 device_printf(ch->pdevinfo->dev, 3319 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3320 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3321 ch->fmt, ch->spd); 3322 ); 3323 fmt = 0; 3324 if (ch->fmt & AFMT_S16_LE) 3325 fmt |= ch->bit16 << 4; 3326 else if (ch->fmt & AFMT_S32_LE) 3327 fmt |= ch->bit32 << 4; 3328 else 3329 fmt |= 1 << 4; 3330 3331 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3332 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3333 fmt |= hda_rate_tab[i].base; 3334 fmt |= hda_rate_tab[i].mul; 3335 fmt |= hda_rate_tab[i].div; 3336 break; 3337 } 3338 } 3339 3340 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3341 fmt |= 1; 3342 totalchn = 2; 3343 } else 3344 totalchn = 1; 3345 3346 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3347 3348 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3349 if (ch->fmt & AFMT_AC3) 3350 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3351 3352 chn = 0; 3353 for (i = 0; ch->io[i] != -1; i++) { 3354 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3355 if (w == NULL) 3356 continue; 3357 3358 if (as->hpredir >= 0 && i == as->pincnt) 3359 chn = 0; 3360 HDA_BOOTHVERBOSE( 3361 device_printf(ch->pdevinfo->dev, 3362 "PCMDIR_%s: Stream setup nid=%d: " 3363 "fmt=0x%04x, dfmt=0x%04x\n", 3364 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3365 ch->io[i], fmt, dfmt); 3366 ); 3367 hdac_command(sc, 3368 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3369 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3370 hdac_command(sc, 3371 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3372 cad); 3373 } 3374 /* If HP redirection is enabled, but failed to use same 3375 DAC make last DAC one to duplicate first one. */ 3376 if (as->hpredir >= 0 && i == as->pincnt) { 3377 c = (ch->sid << 4); 3378 } else if (chn >= totalchn) { 3379 /* This is until OSS will support multichannel. 3380 Should be: c = 0; to disable unused DAC */ 3381 c = (ch->sid << 4); 3382 }else { 3383 c = (ch->sid << 4) | chn; 3384 } 3385 hdac_command(sc, 3386 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3387 chn += 3388 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3389 2 : 1; 3390 } 3391} 3392 3393static int 3394hdac_channel_setfragments(kobj_t obj, void *data, 3395 uint32_t blksz, uint32_t blkcnt) 3396{ 3397 struct hdac_chan *ch = data; 3398 struct hdac_softc *sc = ch->devinfo->codec->sc; 3399 3400 blksz &= HDA_BLK_ALIGN; 3401 3402 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3403 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3404 if (blksz < HDA_BLK_MIN) 3405 blksz = HDA_BLK_MIN; 3406 if (blkcnt > HDA_BDL_MAX) 3407 blkcnt = HDA_BDL_MAX; 3408 if (blkcnt < HDA_BDL_MIN) 3409 blkcnt = HDA_BDL_MIN; 3410 3411 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3412 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3413 blkcnt >>= 1; 3414 else if ((blksz >> 1) >= HDA_BLK_MIN) 3415 blksz >>= 1; 3416 else 3417 break; 3418 } 3419 3420 if ((sndbuf_getblksz(ch->b) != blksz || 3421 sndbuf_getblkcnt(ch->b) != blkcnt) && 3422 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3423 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3424 __func__, blksz, blkcnt); 3425 3426 ch->blksz = sndbuf_getblksz(ch->b); 3427 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3428 3429 return (1); 3430} 3431 3432static int 3433hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3434{ 3435 struct hdac_chan *ch = data; 3436 3437 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3438 3439 return (ch->blksz); 3440} 3441 3442static void 3443hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3444{ 3445 struct hdac_devinfo *devinfo = ch->devinfo; 3446 struct hdac_widget *w; 3447 nid_t cad = devinfo->codec->cad; 3448 int i; 3449 3450 hdac_stream_stop(ch); 3451 3452 for (i = 0; ch->io[i] != -1; i++) { 3453 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3454 if (w == NULL) 3455 continue; 3456 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3457 hdac_command(sc, 3458 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3459 cad); 3460 } 3461 hdac_command(sc, 3462 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3463 0), cad); 3464 } 3465} 3466 3467static void 3468hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3469{ 3470 ch->ptr = 0; 3471 ch->prevptr = 0; 3472 hdac_stream_stop(ch); 3473 hdac_stream_reset(ch); 3474 hdac_bdl_setup(ch); 3475 hdac_stream_setid(ch); 3476 hdac_stream_setup(ch); 3477 hdac_stream_start(ch); 3478} 3479 3480static int 3481hdac_channel_trigger(kobj_t obj, void *data, int go) 3482{ 3483 struct hdac_chan *ch = data; 3484 struct hdac_softc *sc = ch->devinfo->codec->sc; 3485 3486 if (!PCMTRIG_COMMON(go)) 3487 return (0); 3488 3489 hdac_lock(sc); 3490 switch (go) { 3491 case PCMTRIG_START: 3492 hdac_channel_start(sc, ch); 3493 break; 3494 case PCMTRIG_STOP: 3495 case PCMTRIG_ABORT: 3496 hdac_channel_stop(sc, ch); 3497 break; 3498 default: 3499 break; 3500 } 3501 hdac_unlock(sc); 3502 3503 return (0); 3504} 3505 3506static int 3507hdac_channel_getptr(kobj_t obj, void *data) 3508{ 3509 struct hdac_chan *ch = data; 3510 struct hdac_softc *sc = ch->devinfo->codec->sc; 3511 uint32_t ptr; 3512 3513 hdac_lock(sc); 3514 if (sc->polling != 0) 3515 ptr = ch->ptr; 3516 else if (ch->dmapos != NULL) 3517 ptr = *(ch->dmapos); 3518 else 3519 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3520 hdac_unlock(sc); 3521 3522 /* 3523 * Round to available space and force 128 bytes aligment. 3524 */ 3525 ptr %= ch->blksz * ch->blkcnt; 3526 ptr &= HDA_BLK_ALIGN; 3527 3528 return (ptr); 3529} 3530 3531static struct pcmchan_caps * 3532hdac_channel_getcaps(kobj_t obj, void *data) 3533{ 3534 return (&((struct hdac_chan *)data)->caps); 3535} 3536 3537static kobj_method_t hdac_channel_methods[] = { 3538 KOBJMETHOD(channel_init, hdac_channel_init), 3539 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3540 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3541 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3542 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3543 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3544 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3545 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3546 { 0, 0 } 3547}; 3548CHANNEL_DECLARE(hdac_channel); 3549 3550static int 3551hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3552{ 3553 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3554 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3555 struct hdac_softc *sc = devinfo->codec->sc; 3556 struct hdac_widget *w, *cw; 3557 struct hdac_audio_ctl *ctl; 3558 uint32_t mask, recmask, id; 3559 int i, j, softpcmvol; 3560 3561 hdac_lock(sc); 3562 3563 /* Make sure that in case of soft volume it won't stay muted. */ 3564 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3565 pdevinfo->left[i] = 100; 3566 pdevinfo->right[i] = 100; 3567 } 3568 3569 mask = 0; 3570 recmask = 0; 3571 id = hdac_codec_id(devinfo->codec); 3572 3573 /* Declate EAPD as ogain control. */ 3574 if (pdevinfo->play >= 0) { 3575 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3576 w = hdac_widget_get(devinfo, i); 3577 if (w == NULL || w->enable == 0) 3578 continue; 3579 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3580 w->param.eapdbtl == HDAC_INVALID || 3581 w->bindas != sc->chans[pdevinfo->play].as) 3582 continue; 3583 mask |= SOUND_MASK_OGAIN; 3584 break; 3585 } 3586 } 3587 3588 /* Declare volume controls assigned to this association. */ 3589 i = 0; 3590 ctl = NULL; 3591 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3592 if (ctl->enable == 0) 3593 continue; 3594 if ((pdevinfo->play >= 0 && 3595 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3596 (pdevinfo->rec >= 0 && 3597 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3598 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3599 mask |= ctl->ossmask; 3600 } 3601 3602 /* Declare record sources available to this association. */ 3603 if (pdevinfo->rec >= 0) { 3604 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3605 for (i = 0; ch->io[i] != -1; i++) { 3606 w = hdac_widget_get(devinfo, ch->io[i]); 3607 if (w == NULL || w->enable == 0) 3608 continue; 3609 for (j = 0; j < w->nconns; j++) { 3610 if (w->connsenable[j] == 0) 3611 continue; 3612 cw = hdac_widget_get(devinfo, w->conns[j]); 3613 if (cw == NULL || cw->enable == 0) 3614 continue; 3615 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3616 cw->bindas != -2) 3617 continue; 3618 recmask |= cw->ossmask; 3619 } 3620 } 3621 } 3622 3623 /* Declare soft PCM volume if needed. */ 3624 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3625 ctl = NULL; 3626 if ((mask & SOUND_MASK_PCM) == 0 || 3627 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3628 softpcmvol = 1; 3629 mask |= SOUND_MASK_PCM; 3630 } else { 3631 softpcmvol = 0; 3632 i = 0; 3633 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3634 if (ctl->enable == 0) 3635 continue; 3636 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3637 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3638 continue; 3639 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3640 continue; 3641 if (ctl->step > 0) 3642 break; 3643 } 3644 } 3645 3646 if (softpcmvol == 1 || ctl == NULL) { 3647 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3648 HDA_BOOTVERBOSE( 3649 device_printf(pdevinfo->dev, 3650 "%s Soft PCM volume\n", 3651 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3652 ); 3653 } 3654 } 3655 3656 /* Declare master volume if needed. */ 3657 if (pdevinfo->play >= 0) { 3658 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3659 SOUND_MASK_PCM) { 3660 mask |= SOUND_MASK_VOLUME; 3661 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3662 SOUND_MASK_PCM); 3663 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3664 SOUND_MIXER_NONE); 3665 HDA_BOOTVERBOSE( 3666 device_printf(pdevinfo->dev, 3667 "Forcing master volume with PCM\n"); 3668 ); 3669 } 3670 } 3671 3672 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3673 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3674 3675 mix_setrecdevs(m, recmask); 3676 mix_setdevs(m, mask); 3677 3678 hdac_unlock(sc); 3679 3680 return (0); 3681} 3682 3683static int 3684hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3685 unsigned left, unsigned right) 3686{ 3687 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3688 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3689 struct hdac_softc *sc = devinfo->codec->sc; 3690 struct hdac_widget *w; 3691 struct hdac_audio_ctl *ctl; 3692 uint32_t mute; 3693 int lvol, rvol; 3694 int i, j; 3695 3696 hdac_lock(sc); 3697 /* Save new values. */ 3698 pdevinfo->left[dev] = left; 3699 pdevinfo->right[dev] = right; 3700 3701 /* 'ogain' is the special case implemented with EAPD. */ 3702 if (dev == SOUND_MIXER_OGAIN) { 3703 uint32_t orig; 3704 w = NULL; 3705 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3706 w = hdac_widget_get(devinfo, i); 3707 if (w == NULL || w->enable == 0) 3708 continue; 3709 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3710 w->param.eapdbtl == HDAC_INVALID) 3711 continue; 3712 break; 3713 } 3714 if (i >= devinfo->endnode) { 3715 hdac_unlock(sc); 3716 return (-1); 3717 } 3718 orig = w->param.eapdbtl; 3719 if (left == 0) 3720 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3721 else 3722 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3723 if (orig != w->param.eapdbtl) { 3724 uint32_t val; 3725 3726 val = w->param.eapdbtl; 3727 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3728 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3729 hdac_command(sc, 3730 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3731 w->nid, val), devinfo->codec->cad); 3732 } 3733 hdac_unlock(sc); 3734 return (left | (left << 8)); 3735 } 3736 3737 /* Recalculate all controls related to this OSS device. */ 3738 i = 0; 3739 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3740 if (ctl->enable == 0 || 3741 !(ctl->ossmask & (1 << dev))) 3742 continue; 3743 if (!((pdevinfo->play >= 0 && 3744 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3745 (pdevinfo->rec >= 0 && 3746 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3747 ctl->widget->bindas == -2)) 3748 continue; 3749 3750 lvol = 100; 3751 rvol = 100; 3752 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3753 if (ctl->ossmask & (1 << j)) { 3754 lvol = lvol * pdevinfo->left[j] / 100; 3755 rvol = rvol * pdevinfo->right[j] / 100; 3756 } 3757 } 3758 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3759 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3760 lvol = (lvol * ctl->step + 50) / 100; 3761 rvol = (rvol * ctl->step + 50) / 100; 3762 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3763 } 3764 hdac_unlock(sc); 3765 3766 return (left | (right << 8)); 3767} 3768 3769/* 3770 * Commutate specified record source. 3771 */ 3772static uint32_t 3773hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3774{ 3775 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3776 struct hdac_widget *w, *cw; 3777 struct hdac_audio_ctl *ctl; 3778 char buf[64]; 3779 int i, muted; 3780 uint32_t res = 0; 3781 3782 if (depth > HDA_PARSE_MAXDEPTH) 3783 return (0); 3784 3785 w = hdac_widget_get(devinfo, nid); 3786 if (w == NULL || w->enable == 0) 3787 return (0); 3788 3789 for (i = 0; i < w->nconns; i++) { 3790 if (w->connsenable[i] == 0) 3791 continue; 3792 cw = hdac_widget_get(devinfo, w->conns[i]); 3793 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3794 continue; 3795 /* Call recursively to trace signal to it's source if needed. */ 3796 if ((src & cw->ossmask) != 0) { 3797 if (cw->ossdev < 0) { 3798 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3799 w->conns[i], depth + 1); 3800 } else { 3801 res |= cw->ossmask; 3802 } 3803 } 3804 /* We have two special cases: mixers and others (selectors). */ 3805 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3806 ctl = hdac_audio_ctl_amp_get(devinfo, 3807 w->nid, HDA_CTL_IN, i, 1); 3808 if (ctl == NULL) 3809 continue; 3810 /* If we have input control on this node mute them 3811 * according to requested sources. */ 3812 muted = (src & cw->ossmask) ? 0 : 1; 3813 if (muted != ctl->forcemute) { 3814 ctl->forcemute = muted; 3815 hdac_audio_ctl_amp_set(ctl, 3816 HDA_AMP_MUTE_DEFAULT, 3817 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3818 } 3819 HDA_BOOTHVERBOSE( 3820 device_printf(pdevinfo->dev, 3821 "Recsel (%s): nid %d source %d %s\n", 3822 hdac_audio_ctl_ossmixer_mask2allname( 3823 src, buf, sizeof(buf)), 3824 nid, i, muted?"mute":"unmute"); 3825 ); 3826 } else { 3827 if (w->nconns == 1) 3828 break; 3829 if ((src & cw->ossmask) == 0) 3830 continue; 3831 /* If we found requested source - select it and exit. */ 3832 hdac_widget_connection_select(w, i); 3833 HDA_BOOTHVERBOSE( 3834 device_printf(pdevinfo->dev, 3835 "Recsel (%s): nid %d source %d select\n", 3836 hdac_audio_ctl_ossmixer_mask2allname( 3837 src, buf, sizeof(buf)), 3838 nid, i); 3839 ); 3840 break; 3841 } 3842 } 3843 return (res); 3844} 3845 3846static uint32_t 3847hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3848{ 3849 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3850 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3851 struct hdac_widget *w; 3852 struct hdac_softc *sc = devinfo->codec->sc; 3853 struct hdac_chan *ch; 3854 int i; 3855 uint32_t ret = 0xffffffff; 3856 3857 hdac_lock(sc); 3858 3859 /* Commutate requested recsrc for each ADC. */ 3860 ch = &sc->chans[pdevinfo->rec]; 3861 for (i = 0; ch->io[i] != -1; i++) { 3862 w = hdac_widget_get(devinfo, ch->io[i]); 3863 if (w == NULL || w->enable == 0) 3864 continue; 3865 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3866 } 3867 3868 hdac_unlock(sc); 3869 3870 return ((ret == 0xffffffff)? 0 : ret); 3871} 3872 3873static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3874 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3875 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3876 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3877 { 0, 0 } 3878}; 3879MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3880 3881static void 3882hdac_unsolq_task(void *context, int pending) 3883{ 3884 struct hdac_softc *sc; 3885 3886 sc = (struct hdac_softc *)context; 3887 3888 hdac_lock(sc); 3889 hdac_unsolq_flush(sc); 3890 hdac_unlock(sc); 3891} 3892 3893/**************************************************************************** 3894 * int hdac_attach(device_t) 3895 * 3896 * Attach the device into the kernel. Interrupts usually won't be enabled 3897 * when this function is called. Setup everything that doesn't require 3898 * interrupts and defer probing of codecs until interrupts are enabled. 3899 ****************************************************************************/ 3900static int 3901hdac_attach(device_t dev) 3902{ 3903 struct hdac_softc *sc; 3904 int result; 3905 int i; 3906 uint16_t vendor; 3907 uint8_t v; 3908 3909 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3910 3911 sc = device_get_softc(dev); 3912 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3913 sc->dev = dev; 3914 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3915 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3916 vendor = pci_get_vendor(dev); 3917 3918 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3919 /* Screw nx6325 - subdevice/subvendor swapped */ 3920 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3921 } 3922 3923 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3924 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3925 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3926 3927 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3928 3929 sc->poll_ticks = 1000000; 3930 sc->poll_ival = HDAC_POLL_INTERVAL; 3931 if (resource_int_value(device_get_name(dev), 3932 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3933 sc->polling = 1; 3934 else 3935 sc->polling = 0; 3936 3937 result = bus_dma_tag_create(NULL, /* parent */ 3938 HDAC_DMA_ALIGNMENT, /* alignment */ 3939 0, /* boundary */ 3940 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3941 BUS_SPACE_MAXADDR, /* highaddr */ 3942 NULL, /* filtfunc */ 3943 NULL, /* fistfuncarg */ 3944 HDA_BUFSZ_MAX, /* maxsize */ 3945 1, /* nsegments */ 3946 HDA_BUFSZ_MAX, /* maxsegsz */ 3947 0, /* flags */ 3948 NULL, /* lockfunc */ 3949 NULL, /* lockfuncarg */ 3950 &sc->chan_dmat); /* dmat */ 3951 if (result != 0) { 3952 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3953 __func__, result); 3954 snd_mtxfree(sc->lock); 3955 free(sc, M_DEVBUF); 3956 return (ENXIO); 3957 } 3958 3959 3960 sc->hdabus = NULL; 3961 for (i = 0; i < HDAC_CODEC_MAX; i++) 3962 sc->codecs[i] = NULL; 3963 3964 pci_enable_busmaster(dev); 3965 3966 if (vendor == INTEL_VENDORID) { 3967 /* TCSEL -> TC0 */ 3968 v = pci_read_config(dev, 0x44, 1); 3969 pci_write_config(dev, 0x44, v & 0xf8, 1); 3970 HDA_BOOTHVERBOSE( 3971 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3972 pci_read_config(dev, 0x44, 1)); 3973 ); 3974 } 3975 3976#ifdef HDAC_MSI_ENABLED 3977 if (resource_int_value(device_get_name(dev), 3978 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3979 pci_msi_count(dev) == 1) 3980 sc->flags |= HDAC_F_MSI; 3981 else 3982#endif 3983 sc->flags &= ~HDAC_F_MSI; 3984 3985#if defined(__i386__) || defined(__amd64__) 3986 sc->flags |= HDAC_F_DMA_NOCACHE; 3987 3988 if (resource_int_value(device_get_name(dev), 3989 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3990#else 3991 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3992#endif 3993 /* 3994 * Try to enable PCIe snoop to avoid messing around with 3995 * uncacheable DMA attribute. Since PCIe snoop register 3996 * config is pretty much vendor specific, there are no 3997 * general solutions on how to enable it, forcing us (even 3998 * Microsoft) to enable uncacheable or write combined DMA 3999 * by default. 4000 * 4001 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4002 */ 4003 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4004 if (hdac_pcie_snoop[i].vendor != vendor) 4005 continue; 4006 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4007 if (hdac_pcie_snoop[i].reg == 0x00) 4008 break; 4009 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4010 if ((v & hdac_pcie_snoop[i].enable) == 4011 hdac_pcie_snoop[i].enable) 4012 break; 4013 v &= hdac_pcie_snoop[i].mask; 4014 v |= hdac_pcie_snoop[i].enable; 4015 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4016 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4017 if ((v & hdac_pcie_snoop[i].enable) != 4018 hdac_pcie_snoop[i].enable) { 4019 HDA_BOOTVERBOSE( 4020 device_printf(dev, 4021 "WARNING: Failed to enable PCIe " 4022 "snoop!\n"); 4023 ); 4024#if defined(__i386__) || defined(__amd64__) 4025 sc->flags |= HDAC_F_DMA_NOCACHE; 4026#endif 4027 } 4028 break; 4029 } 4030#if defined(__i386__) || defined(__amd64__) 4031 } 4032#endif 4033 4034 HDA_BOOTHVERBOSE( 4035 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4036 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4037 "Uncacheable" : "PCIe snoop", vendor); 4038 ); 4039 4040 /* Allocate resources */ 4041 result = hdac_mem_alloc(sc); 4042 if (result != 0) 4043 goto hdac_attach_fail; 4044 result = hdac_irq_alloc(sc); 4045 if (result != 0) 4046 goto hdac_attach_fail; 4047 4048 /* Get Capabilities */ 4049 result = hdac_get_capabilities(sc); 4050 if (result != 0) 4051 goto hdac_attach_fail; 4052 4053 /* Allocate CORB and RIRB dma memory */ 4054 result = hdac_dma_alloc(sc, &sc->corb_dma, 4055 sc->corb_size * sizeof(uint32_t)); 4056 if (result != 0) 4057 goto hdac_attach_fail; 4058 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4059 sc->rirb_size * sizeof(struct hdac_rirb)); 4060 if (result != 0) 4061 goto hdac_attach_fail; 4062 4063 /* Quiesce everything */ 4064 HDA_BOOTHVERBOSE( 4065 device_printf(dev, "Reset controller...\n"); 4066 ); 4067 hdac_reset(sc, 1); 4068 4069 /* Initialize the CORB and RIRB */ 4070 hdac_corb_init(sc); 4071 hdac_rirb_init(sc); 4072 4073 /* Defer remaining of initialization until interrupts are enabled */ 4074 sc->intrhook.ich_func = hdac_attach2; 4075 sc->intrhook.ich_arg = (void *)sc; 4076 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4077 sc->intrhook.ich_func = NULL; 4078 hdac_attach2((void *)sc); 4079 } 4080 4081 return (0); 4082 4083hdac_attach_fail: 4084 hdac_irq_free(sc); 4085 hdac_dma_free(sc, &sc->rirb_dma); 4086 hdac_dma_free(sc, &sc->corb_dma); 4087 hdac_mem_free(sc); 4088 snd_mtxfree(sc->lock); 4089 free(sc, M_DEVBUF); 4090 4091 return (ENXIO); 4092} 4093 4094static void 4095hdac_audio_parse(struct hdac_devinfo *devinfo) 4096{ 4097 struct hdac_codec *codec = devinfo->codec; 4098 struct hdac_softc *sc = codec->sc; 4099 struct hdac_widget *w; 4100 uint32_t res; 4101 int i; 4102 nid_t cad, nid; 4103 4104 cad = devinfo->codec->cad; 4105 nid = devinfo->nid; 4106 4107 res = hdac_command(sc, 4108 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4109 devinfo->function.audio.gpio = res; 4110 4111 HDA_BOOTVERBOSE( 4112 device_printf(sc->dev, "GPIO: 0x%08x " 4113 "NumGPIO=%d NumGPO=%d " 4114 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4115 devinfo->function.audio.gpio, 4116 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4117 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4118 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4119 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4120 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4121 ); 4122 4123 res = hdac_command(sc, 4124 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4125 cad); 4126 devinfo->function.audio.supp_stream_formats = res; 4127 4128 res = hdac_command(sc, 4129 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4130 cad); 4131 devinfo->function.audio.supp_pcm_size_rate = res; 4132 4133 res = hdac_command(sc, 4134 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4135 cad); 4136 devinfo->function.audio.outamp_cap = res; 4137 4138 res = hdac_command(sc, 4139 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4140 cad); 4141 devinfo->function.audio.inamp_cap = res; 4142 4143 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4144 w = hdac_widget_get(devinfo, i); 4145 if (w == NULL) 4146 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4147 else { 4148 w->devinfo = devinfo; 4149 w->nid = i; 4150 w->enable = 1; 4151 w->selconn = -1; 4152 w->pflags = 0; 4153 w->ossdev = -1; 4154 w->bindas = -1; 4155 w->param.eapdbtl = HDAC_INVALID; 4156 hdac_widget_parse(w); 4157 } 4158 } 4159} 4160 4161static void 4162hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4163{ 4164 struct hdac_softc *sc = devinfo->codec->sc; 4165 struct hdac_audio_ctl *ctls; 4166 struct hdac_widget *w, *cw; 4167 int i, j, cnt, max, ocap, icap; 4168 int mute, offset, step, size; 4169 4170 /* XXX This is redundant */ 4171 max = 0; 4172 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4173 w = hdac_widget_get(devinfo, i); 4174 if (w == NULL || w->enable == 0) 4175 continue; 4176 if (w->param.outamp_cap != 0) 4177 max++; 4178 if (w->param.inamp_cap != 0) { 4179 switch (w->type) { 4180 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4181 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4182 for (j = 0; j < w->nconns; j++) { 4183 cw = hdac_widget_get(devinfo, 4184 w->conns[j]); 4185 if (cw == NULL || cw->enable == 0) 4186 continue; 4187 max++; 4188 } 4189 break; 4190 default: 4191 max++; 4192 break; 4193 } 4194 } 4195 } 4196 4197 devinfo->function.audio.ctlcnt = max; 4198 4199 if (max < 1) 4200 return; 4201 4202 ctls = (struct hdac_audio_ctl *)malloc( 4203 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4204 4205 if (ctls == NULL) { 4206 /* Blekh! */ 4207 device_printf(sc->dev, "unable to allocate ctls!\n"); 4208 devinfo->function.audio.ctlcnt = 0; 4209 return; 4210 } 4211 4212 cnt = 0; 4213 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4214 if (cnt >= max) { 4215 device_printf(sc->dev, "%s: Ctl overflow!\n", 4216 __func__); 4217 break; 4218 } 4219 w = hdac_widget_get(devinfo, i); 4220 if (w == NULL || w->enable == 0) 4221 continue; 4222 ocap = w->param.outamp_cap; 4223 icap = w->param.inamp_cap; 4224 if (ocap != 0) { 4225 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4226 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4227 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4228 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4229 /*if (offset > step) { 4230 HDA_BOOTVERBOSE( 4231 device_printf(sc->dev, 4232 "BUGGY outamp: nid=%d " 4233 "[offset=%d > step=%d]\n", 4234 w->nid, offset, step); 4235 ); 4236 offset = step; 4237 }*/ 4238 ctls[cnt].enable = 1; 4239 ctls[cnt].widget = w; 4240 ctls[cnt].mute = mute; 4241 ctls[cnt].step = step; 4242 ctls[cnt].size = size; 4243 ctls[cnt].offset = offset; 4244 ctls[cnt].left = offset; 4245 ctls[cnt].right = offset; 4246 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4247 w->waspin) 4248 ctls[cnt].ndir = HDA_CTL_IN; 4249 else 4250 ctls[cnt].ndir = HDA_CTL_OUT; 4251 ctls[cnt++].dir = HDA_CTL_OUT; 4252 } 4253 4254 if (icap != 0) { 4255 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4256 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4257 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4258 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4259 /*if (offset > step) { 4260 HDA_BOOTVERBOSE( 4261 device_printf(sc->dev, 4262 "BUGGY inamp: nid=%d " 4263 "[offset=%d > step=%d]\n", 4264 w->nid, offset, step); 4265 ); 4266 offset = step; 4267 }*/ 4268 switch (w->type) { 4269 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4270 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4271 for (j = 0; j < w->nconns; j++) { 4272 if (cnt >= max) { 4273 device_printf(sc->dev, 4274 "%s: Ctl overflow!\n", 4275 __func__); 4276 break; 4277 } 4278 cw = hdac_widget_get(devinfo, 4279 w->conns[j]); 4280 if (cw == NULL || cw->enable == 0) 4281 continue; 4282 ctls[cnt].enable = 1; 4283 ctls[cnt].widget = w; 4284 ctls[cnt].childwidget = cw; 4285 ctls[cnt].index = j; 4286 ctls[cnt].mute = mute; 4287 ctls[cnt].step = step; 4288 ctls[cnt].size = size; 4289 ctls[cnt].offset = offset; 4290 ctls[cnt].left = offset; 4291 ctls[cnt].right = offset; 4292 ctls[cnt].ndir = HDA_CTL_IN; 4293 ctls[cnt++].dir = HDA_CTL_IN; 4294 } 4295 break; 4296 default: 4297 if (cnt >= max) { 4298 device_printf(sc->dev, 4299 "%s: Ctl overflow!\n", 4300 __func__); 4301 break; 4302 } 4303 ctls[cnt].enable = 1; 4304 ctls[cnt].widget = w; 4305 ctls[cnt].mute = mute; 4306 ctls[cnt].step = step; 4307 ctls[cnt].size = size; 4308 ctls[cnt].offset = offset; 4309 ctls[cnt].left = offset; 4310 ctls[cnt].right = offset; 4311 if (w->type == 4312 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4313 ctls[cnt].ndir = HDA_CTL_OUT; 4314 else 4315 ctls[cnt].ndir = HDA_CTL_IN; 4316 ctls[cnt++].dir = HDA_CTL_IN; 4317 break; 4318 } 4319 } 4320 } 4321 4322 devinfo->function.audio.ctl = ctls; 4323} 4324 4325static void 4326hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4327{ 4328 struct hdac_softc *sc = devinfo->codec->sc; 4329 struct hdac_audio_as *as; 4330 struct hdac_widget *w; 4331 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4332 4333 /* Count present associations */ 4334 max = 0; 4335 for (j = 1; j < 16; j++) { 4336 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4337 w = hdac_widget_get(devinfo, i); 4338 if (w == NULL || w->enable == 0) 4339 continue; 4340 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4341 continue; 4342 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4343 != j) 4344 continue; 4345 max++; 4346 if (j != 15) /* There could be many 1-pin assocs #15 */ 4347 break; 4348 } 4349 } 4350 4351 devinfo->function.audio.ascnt = max; 4352 4353 if (max < 1) 4354 return; 4355 4356 as = (struct hdac_audio_as *)malloc( 4357 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4358 4359 if (as == NULL) { 4360 /* Blekh! */ 4361 device_printf(sc->dev, "unable to allocate assocs!\n"); 4362 devinfo->function.audio.ascnt = 0; 4363 return; 4364 } 4365 4366 for (i = 0; i < max; i++) { 4367 as[i].hpredir = -1; 4368 as[i].chan = -1; 4369 as[i].digital = 1; 4370 } 4371 4372 /* Scan associations skipping as=0. */ 4373 cnt = 0; 4374 for (j = 1; j < 16; j++) { 4375 first = 16; 4376 hpredir = 0; 4377 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4378 w = hdac_widget_get(devinfo, i); 4379 if (w == NULL || w->enable == 0) 4380 continue; 4381 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4382 continue; 4383 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4384 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4385 if (assoc != j) { 4386 continue; 4387 } 4388 KASSERT(cnt < max, 4389 ("%s: Associations owerflow (%d of %d)", 4390 __func__, cnt, max)); 4391 type = w->wclass.pin.config & 4392 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4393 /* Get pin direction. */ 4394 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4395 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4396 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4397 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4398 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4399 dir = HDA_CTL_OUT; 4400 else 4401 dir = HDA_CTL_IN; 4402 /* If this is a first pin - create new association. */ 4403 if (as[cnt].pincnt == 0) { 4404 as[cnt].enable = 1; 4405 as[cnt].index = j; 4406 as[cnt].dir = dir; 4407 } 4408 if (seq < first) 4409 first = seq; 4410 /* Check association correctness. */ 4411 if (as[cnt].pins[seq] != 0) { 4412 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4413 "in association %d! Disabling association.\n", 4414 __func__, seq, w->nid, j); 4415 as[cnt].enable = 0; 4416 } 4417 if (dir != as[cnt].dir) { 4418 device_printf(sc->dev, "%s: Pin %d has wrong " 4419 "direction for association %d! Disabling " 4420 "association.\n", 4421 __func__, w->nid, j); 4422 as[cnt].enable = 0; 4423 } 4424 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4425 as[cnt].digital = 0; 4426 /* Headphones with seq=15 may mean redirection. */ 4427 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4428 seq == 15) 4429 hpredir = 1; 4430 as[cnt].pins[seq] = w->nid; 4431 as[cnt].pincnt++; 4432 /* Association 15 is a multiple unassociated pins. */ 4433 if (j == 15) 4434 cnt++; 4435 } 4436 if (j != 15 && as[cnt].pincnt > 0) { 4437 if (hpredir && as[cnt].pincnt > 1) 4438 as[cnt].hpredir = first; 4439 cnt++; 4440 } 4441 } 4442 HDA_BOOTVERBOSE( 4443 device_printf(sc->dev, 4444 "%d associations found:\n", max); 4445 for (i = 0; i < max; i++) { 4446 device_printf(sc->dev, 4447 "Association %d (%d) %s%s:\n", 4448 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4449 as[i].enable?"":" (disabled)"); 4450 for (j = 0; j < 16; j++) { 4451 if (as[i].pins[j] == 0) 4452 continue; 4453 device_printf(sc->dev, 4454 " Pin nid=%d seq=%d\n", 4455 as[i].pins[j], j); 4456 } 4457 } 4458 ); 4459 4460 devinfo->function.audio.as = as; 4461} 4462 4463static const struct { 4464 uint32_t model; 4465 uint32_t id; 4466 uint32_t set, unset; 4467} hdac_quirks[] = { 4468 /* 4469 * XXX Force stereo quirk. Monoural recording / playback 4470 * on few codecs (especially ALC880) seems broken or 4471 * perhaps unsupported. 4472 */ 4473 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4474 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4475 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4476 HDA_QUIRK_GPIO0, 0 }, 4477 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4478 HDA_QUIRK_GPIO0, 0 }, 4479 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4480 HDA_QUIRK_GPIO0, 0 }, 4481 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4482 HDA_QUIRK_GPIO0, 0 }, 4483 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4484 HDA_QUIRK_GPIO0, 0 }, 4485 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4486 HDA_QUIRK_GPIO0, 0 }, 4487 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4488 HDA_QUIRK_EAPDINV, 0 }, 4489 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4490 HDA_QUIRK_EAPDINV, 0 }, 4491 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4492 HDA_QUIRK_OVREF, 0 }, 4493 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4494 HDA_QUIRK_OVREF, 0 }, 4495 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4496 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4497 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4498 HDA_QUIRK_GPIO1, 0 }, 4499 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4500 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4501 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4502 HDA_QUIRK_EAPDINV, 0 }, 4503 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4504 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4505 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4506 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4507 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4508 HDA_QUIRK_GPIO0, 0 }, 4509 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4510 HDA_QUIRK_GPIO2, 0 }, 4511 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4512 HDA_QUIRK_GPIO0, 0 }, 4513 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4514 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4515 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4516 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4517 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4518 0, HDA_QUIRK_FORCESTEREO } 4519}; 4520#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4521 4522static void 4523hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4524{ 4525 struct hdac_widget *w; 4526 uint32_t id, subvendor; 4527 int i; 4528 4529 id = hdac_codec_id(devinfo->codec); 4530 subvendor = devinfo->codec->sc->pci_subvendor; 4531 4532 /* 4533 * Quirks 4534 */ 4535 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4536 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4537 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4538 continue; 4539 if (hdac_quirks[i].set != 0) 4540 devinfo->function.audio.quirks |= 4541 hdac_quirks[i].set; 4542 if (hdac_quirks[i].unset != 0) 4543 devinfo->function.audio.quirks &= 4544 ~(hdac_quirks[i].unset); 4545 } 4546 4547 switch (id) { 4548 case HDA_CODEC_ALC883: 4549 /* 4550 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4551 * Clear vref cap for jack connectivity. 4552 */ 4553 w = hdac_widget_get(devinfo, 24); 4554 if (w != NULL && w->enable != 0 && w->type == 4555 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4556 (w->wclass.pin.config & 4557 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4558 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4559 w->wclass.pin.cap &= ~( 4560 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4561 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4562 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4563 w = hdac_widget_get(devinfo, 25); 4564 if (w != NULL && w->enable != 0 && w->type == 4565 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4566 (w->wclass.pin.config & 4567 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4568 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4569 w->wclass.pin.cap &= ~( 4570 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4571 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4572 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4573 /* 4574 * nid: 26 = Line-in, leave it alone. 4575 */ 4576 break; 4577 case HDA_CODEC_AD1986A: 4578 /* 4579 * This codec has overcomplicated input mixing. 4580 * Make some cleaning there. 4581 */ 4582 /* Disable input mono mixer. Not needed and not supported. */ 4583 w = hdac_widget_get(devinfo, 43); 4584 if (w != NULL) 4585 w->enable = 0; 4586 /* Disable any with any input mixing mesh. Use separately. */ 4587 w = hdac_widget_get(devinfo, 39); 4588 if (w != NULL) 4589 w->enable = 0; 4590 w = hdac_widget_get(devinfo, 40); 4591 if (w != NULL) 4592 w->enable = 0; 4593 w = hdac_widget_get(devinfo, 41); 4594 if (w != NULL) 4595 w->enable = 0; 4596 w = hdac_widget_get(devinfo, 42); 4597 if (w != NULL) 4598 w->enable = 0; 4599 /* Disable duplicate mixer node connector. */ 4600 w = hdac_widget_get(devinfo, 15); 4601 if (w != NULL) 4602 w->connsenable[3] = 0; 4603 4604 if (subvendor == ASUS_A8X_SUBVENDOR) { 4605 /* 4606 * This is just plain ridiculous.. There 4607 * are several A8 series that share the same 4608 * pci id but works differently (EAPD). 4609 */ 4610 w = hdac_widget_get(devinfo, 26); 4611 if (w != NULL && w->type == 4612 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4613 (w->wclass.pin.config & 4614 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4615 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4616 devinfo->function.audio.quirks &= 4617 ~HDA_QUIRK_EAPDINV; 4618 } 4619 break; 4620 case HDA_CODEC_AD1981HD: 4621 /* 4622 * This codec has very unusual design with several 4623 * points inappropriate for the present parser. 4624 */ 4625 /* Disable recording from mono playback mix. */ 4626 w = hdac_widget_get(devinfo, 21); 4627 if (w != NULL) 4628 w->connsenable[3] = 0; 4629 /* Disable rear to front mic mixer, use separately. */ 4630 w = hdac_widget_get(devinfo, 31); 4631 if (w != NULL) 4632 w->enable = 0; 4633 /* Disable playback mixer, use direct bypass. */ 4634 w = hdac_widget_get(devinfo, 14); 4635 if (w != NULL) 4636 w->enable = 0; 4637 break; 4638 } 4639} 4640 4641/* 4642 * Trace path from DAC to pin. 4643 */ 4644static nid_t 4645hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4646 int dupseq, int min, int only, int depth) 4647{ 4648 struct hdac_widget *w; 4649 int i, im = -1; 4650 nid_t m = 0, ret; 4651 4652 if (depth > HDA_PARSE_MAXDEPTH) 4653 return (0); 4654 w = hdac_widget_get(devinfo, nid); 4655 if (w == NULL || w->enable == 0) 4656 return (0); 4657 HDA_BOOTHVERBOSE( 4658 if (!only) { 4659 device_printf(devinfo->codec->sc->dev, 4660 " %*stracing via nid %d\n", 4661 depth + 1, "", w->nid); 4662 } 4663 ); 4664 /* Use only unused widgets */ 4665 if (w->bindas >= 0 && w->bindas != as) { 4666 HDA_BOOTHVERBOSE( 4667 if (!only) { 4668 device_printf(devinfo->codec->sc->dev, 4669 " %*snid %d busy by association %d\n", 4670 depth + 1, "", w->nid, w->bindas); 4671 } 4672 ); 4673 return (0); 4674 } 4675 if (dupseq < 0) { 4676 if (w->bindseqmask != 0) { 4677 HDA_BOOTHVERBOSE( 4678 if (!only) { 4679 device_printf(devinfo->codec->sc->dev, 4680 " %*snid %d busy by seqmask %x\n", 4681 depth + 1, "", w->nid, w->bindseqmask); 4682 } 4683 ); 4684 return (0); 4685 } 4686 } else { 4687 /* If this is headphones - allow duplicate first pin. */ 4688 if (w->bindseqmask != 0 && 4689 (w->bindseqmask & (1 << dupseq)) == 0) { 4690 HDA_BOOTHVERBOSE( 4691 device_printf(devinfo->codec->sc->dev, 4692 " %*snid %d busy by seqmask %x\n", 4693 depth + 1, "", w->nid, w->bindseqmask); 4694 ); 4695 return (0); 4696 } 4697 } 4698 4699 switch (w->type) { 4700 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4701 /* Do not traverse input. AD1988 has digital monitor 4702 for which we are not ready. */ 4703 break; 4704 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4705 /* If we are tracing HP take only dac of first pin. */ 4706 if ((only == 0 || only == w->nid) && 4707 (w->nid >= min) && (dupseq < 0 || w->nid == 4708 devinfo->function.audio.as[as].dacs[dupseq])) 4709 m = w->nid; 4710 break; 4711 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4712 if (depth > 0) 4713 break; 4714 /* Fall */ 4715 default: 4716 /* Find reachable DACs with smallest nid respecting constraints. */ 4717 for (i = 0; i < w->nconns; i++) { 4718 if (w->connsenable[i] == 0) 4719 continue; 4720 if (w->selconn != -1 && w->selconn != i) 4721 continue; 4722 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4723 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4724 if (m == 0 || ret < m) { 4725 m = ret; 4726 im = i; 4727 } 4728 if (only || dupseq >= 0) 4729 break; 4730 } 4731 } 4732 if (m && only && ((w->nconns > 1 && 4733 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4734 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4735 w->selconn = im; 4736 break; 4737 } 4738 if (m && only) { 4739 w->bindas = as; 4740 w->bindseqmask |= (1 << seq); 4741 } 4742 HDA_BOOTHVERBOSE( 4743 if (!only) { 4744 device_printf(devinfo->codec->sc->dev, 4745 " %*snid %d returned %d\n", 4746 depth + 1, "", w->nid, m); 4747 } 4748 ); 4749 return (m); 4750} 4751 4752/* 4753 * Trace path from widget to ADC. 4754 */ 4755static nid_t 4756hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4757 int only, int depth) 4758{ 4759 struct hdac_widget *w, *wc; 4760 int i, j; 4761 nid_t res = 0; 4762 4763 if (depth > HDA_PARSE_MAXDEPTH) 4764 return (0); 4765 w = hdac_widget_get(devinfo, nid); 4766 if (w == NULL || w->enable == 0) 4767 return (0); 4768 HDA_BOOTHVERBOSE( 4769 device_printf(devinfo->codec->sc->dev, 4770 " %*stracing via nid %d\n", 4771 depth + 1, "", w->nid); 4772 ); 4773 /* Use only unused widgets */ 4774 if (w->bindas >= 0 && w->bindas != as) { 4775 HDA_BOOTHVERBOSE( 4776 device_printf(devinfo->codec->sc->dev, 4777 " %*snid %d busy by association %d\n", 4778 depth + 1, "", w->nid, w->bindas); 4779 ); 4780 return (0); 4781 } 4782 4783 switch (w->type) { 4784 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4785 /* If we are tracing HP take only dac of first pin. */ 4786 if (only == w->nid) 4787 res = 1; 4788 break; 4789 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4790 if (depth > 0) 4791 break; 4792 /* Fall */ 4793 default: 4794 /* Try to find reachable ADCs with specified nid. */ 4795 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4796 wc = hdac_widget_get(devinfo, j); 4797 if (wc == NULL || wc->enable == 0) 4798 continue; 4799 for (i = 0; i < wc->nconns; i++) { 4800 if (wc->connsenable[i] == 0) 4801 continue; 4802 if (wc->conns[i] != nid) 4803 continue; 4804 if (hdac_audio_trace_adc(devinfo, as, seq, 4805 j, only, depth + 1) != 0) { 4806 res = 1; 4807 if (((wc->nconns > 1 && 4808 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4809 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4810 wc->selconn == -1) 4811 wc->selconn = i; 4812 } 4813 } 4814 } 4815 break; 4816 } 4817 if (res) { 4818 w->bindas = as; 4819 w->bindseqmask |= (1 << seq); 4820 } 4821 HDA_BOOTHVERBOSE( 4822 device_printf(devinfo->codec->sc->dev, 4823 " %*snid %d returned %d\n", 4824 depth + 1, "", w->nid, res); 4825 ); 4826 return (res); 4827} 4828 4829/* 4830 * Erase trace path of the specified association. 4831 */ 4832static void 4833hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4834{ 4835 struct hdac_widget *w; 4836 int i; 4837 4838 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4839 w = hdac_widget_get(devinfo, i); 4840 if (w == NULL || w->enable == 0) 4841 continue; 4842 if (w->bindas == as) { 4843 if (seq >= 0) { 4844 w->bindseqmask &= ~(1 << seq); 4845 if (w->bindseqmask == 0) { 4846 w->bindas = -1; 4847 w->selconn = -1; 4848 } 4849 } else { 4850 w->bindas = -1; 4851 w->bindseqmask = 0; 4852 w->selconn = -1; 4853 } 4854 } 4855 } 4856} 4857 4858/* 4859 * Trace association path from DAC to output 4860 */ 4861static int 4862hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4863{ 4864 struct hdac_audio_as *ases = devinfo->function.audio.as; 4865 int i, hpredir; 4866 nid_t min, res; 4867 4868 /* Find next pin */ 4869 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4870 ; 4871 /* Check if there is no any left. If so - we succeded. */ 4872 if (i == 16) 4873 return (1); 4874 4875 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4876 min = 0; 4877 res = 0; 4878 do { 4879 HDA_BOOTHVERBOSE( 4880 device_printf(devinfo->codec->sc->dev, 4881 " Tracing pin %d with min nid %d", 4882 ases[as].pins[i], min); 4883 if (hpredir >= 0) 4884 printf(" and hpredir %d", hpredir); 4885 printf("\n"); 4886 ); 4887 /* Trace this pin taking min nid into account. */ 4888 res = hdac_audio_trace_dac(devinfo, as, i, 4889 ases[as].pins[i], hpredir, min, 0, 0); 4890 if (res == 0) { 4891 /* If we failed - return to previous and redo it. */ 4892 HDA_BOOTVERBOSE( 4893 device_printf(devinfo->codec->sc->dev, 4894 " Unable to trace pin %d seq %d with min " 4895 "nid %d", 4896 ases[as].pins[i], i, min); 4897 if (hpredir >= 0) 4898 printf(" and hpredir %d", hpredir); 4899 printf("\n"); 4900 ); 4901 return (0); 4902 } 4903 HDA_BOOTVERBOSE( 4904 device_printf(devinfo->codec->sc->dev, 4905 " Pin %d traced to DAC %d", 4906 ases[as].pins[i], res); 4907 if (hpredir >= 0) 4908 printf(" and hpredir %d", hpredir); 4909 if (ases[as].fakeredir) 4910 printf(" with fake redirection"); 4911 printf("\n"); 4912 ); 4913 /* Trace again to mark the path */ 4914 hdac_audio_trace_dac(devinfo, as, i, 4915 ases[as].pins[i], hpredir, min, res, 0); 4916 ases[as].dacs[i] = res; 4917 /* We succeded, so call next. */ 4918 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4919 return (1); 4920 /* If next failed, we should retry with next min */ 4921 hdac_audio_undo_trace(devinfo, as, i); 4922 ases[as].dacs[i] = 0; 4923 min = res + 1; 4924 } while (1); 4925} 4926 4927/* 4928 * Trace association path from input to ADC 4929 */ 4930static int 4931hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4932{ 4933 struct hdac_audio_as *ases = devinfo->function.audio.as; 4934 struct hdac_widget *w; 4935 int i, j, k; 4936 4937 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4938 w = hdac_widget_get(devinfo, j); 4939 if (w == NULL || w->enable == 0) 4940 continue; 4941 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4942 continue; 4943 if (w->bindas >= 0 && w->bindas != as) 4944 continue; 4945 4946 /* Find next pin */ 4947 for (i = 0; i < 16; i++) { 4948 if (ases[as].pins[i] == 0) 4949 continue; 4950 4951 HDA_BOOTHVERBOSE( 4952 device_printf(devinfo->codec->sc->dev, 4953 " Tracing pin %d to ADC %d\n", 4954 ases[as].pins[i], j); 4955 ); 4956 /* Trace this pin taking goal into account. */ 4957 if (hdac_audio_trace_adc(devinfo, as, i, 4958 ases[as].pins[i], j, 0) == 0) { 4959 /* If we failed - return to previous and redo it. */ 4960 HDA_BOOTVERBOSE( 4961 device_printf(devinfo->codec->sc->dev, 4962 " Unable to trace pin %d to ADC %d, undo traces\n", 4963 ases[as].pins[i], j); 4964 ); 4965 hdac_audio_undo_trace(devinfo, as, -1); 4966 for (k = 0; k < 16; k++) 4967 ases[as].dacs[k] = 0; 4968 break; 4969 } 4970 HDA_BOOTVERBOSE( 4971 device_printf(devinfo->codec->sc->dev, 4972 " Pin %d traced to ADC %d\n", 4973 ases[as].pins[i], j); 4974 ); 4975 ases[as].dacs[i] = j; 4976 } 4977 if (i == 16) 4978 return (1); 4979 } 4980 return (0); 4981} 4982 4983/* 4984 * Trace input monitor path from mixer to output association. 4985 */ 4986static int 4987hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4988{ 4989 struct hdac_audio_as *ases = devinfo->function.audio.as; 4990 struct hdac_widget *w, *wc; 4991 int i, j; 4992 nid_t res = 0; 4993 4994 if (depth > HDA_PARSE_MAXDEPTH) 4995 return (0); 4996 w = hdac_widget_get(devinfo, nid); 4997 if (w == NULL || w->enable == 0) 4998 return (0); 4999 HDA_BOOTHVERBOSE( 5000 device_printf(devinfo->codec->sc->dev, 5001 " %*stracing via nid %d\n", 5002 depth + 1, "", w->nid); 5003 ); 5004 /* Use only unused widgets */ 5005 if (depth > 0 && w->bindas != -1) { 5006 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5007 HDA_BOOTHVERBOSE( 5008 device_printf(devinfo->codec->sc->dev, 5009 " %*snid %d found output association %d\n", 5010 depth + 1, "", w->nid, w->bindas); 5011 ); 5012 return (1); 5013 } else { 5014 HDA_BOOTHVERBOSE( 5015 device_printf(devinfo->codec->sc->dev, 5016 " %*snid %d busy by input association %d\n", 5017 depth + 1, "", w->nid, w->bindas); 5018 ); 5019 return (0); 5020 } 5021 } 5022 5023 switch (w->type) { 5024 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5025 /* Do not traverse input. AD1988 has digital monitor 5026 for which we are not ready. */ 5027 break; 5028 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5029 if (depth > 0) 5030 break; 5031 /* Fall */ 5032 default: 5033 /* Try to find reachable ADCs with specified nid. */ 5034 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5035 wc = hdac_widget_get(devinfo, j); 5036 if (wc == NULL || wc->enable == 0) 5037 continue; 5038 for (i = 0; i < wc->nconns; i++) { 5039 if (wc->connsenable[i] == 0) 5040 continue; 5041 if (wc->conns[i] != nid) 5042 continue; 5043 if (hdac_audio_trace_to_out(devinfo, 5044 j, depth + 1) != 0) { 5045 res = 1; 5046 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5047 wc->selconn == -1) 5048 wc->selconn = i; 5049 } 5050 } 5051 } 5052 break; 5053 } 5054 if (res) 5055 w->bindas = -2; 5056 5057 HDA_BOOTHVERBOSE( 5058 device_printf(devinfo->codec->sc->dev, 5059 " %*snid %d returned %d\n", 5060 depth + 1, "", w->nid, res); 5061 ); 5062 return (res); 5063} 5064 5065/* 5066 * Trace extra associations (beeper, monitor) 5067 */ 5068static void 5069hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5070{ 5071 struct hdac_audio_as *as = devinfo->function.audio.as; 5072 struct hdac_widget *w; 5073 int j; 5074 5075 /* Input monitor */ 5076 /* Find mixer associated with input, but supplying signal 5077 for output associations. Hope it will be input monitor. */ 5078 HDA_BOOTVERBOSE( 5079 device_printf(devinfo->codec->sc->dev, 5080 "Tracing input monitor\n"); 5081 ); 5082 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5083 w = hdac_widget_get(devinfo, j); 5084 if (w == NULL || w->enable == 0) 5085 continue; 5086 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5087 continue; 5088 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5089 continue; 5090 HDA_BOOTVERBOSE( 5091 device_printf(devinfo->codec->sc->dev, 5092 " Tracing nid %d to out\n", 5093 j); 5094 ); 5095 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5096 HDA_BOOTVERBOSE( 5097 device_printf(devinfo->codec->sc->dev, 5098 " nid %d is input monitor\n", 5099 w->nid); 5100 ); 5101 w->pflags |= HDA_ADC_MONITOR; 5102 w->ossdev = SOUND_MIXER_IMIX; 5103 } 5104 } 5105 5106 /* Beeper */ 5107 HDA_BOOTVERBOSE( 5108 device_printf(devinfo->codec->sc->dev, 5109 "Tracing beeper\n"); 5110 ); 5111 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5112 w = hdac_widget_get(devinfo, j); 5113 if (w == NULL || w->enable == 0) 5114 continue; 5115 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5116 continue; 5117 HDA_BOOTHVERBOSE( 5118 device_printf(devinfo->codec->sc->dev, 5119 " Tracing nid %d to out\n", 5120 j); 5121 ); 5122 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5123 HDA_BOOTVERBOSE( 5124 device_printf(devinfo->codec->sc->dev, 5125 " nid %d traced to out\n", 5126 j); 5127 ); 5128 } 5129 w->bindas = -2; 5130 } 5131} 5132 5133/* 5134 * Bind assotiations to PCM channels 5135 */ 5136static void 5137hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5138{ 5139 struct hdac_softc *sc = devinfo->codec->sc; 5140 struct hdac_audio_as *as = devinfo->function.audio.as; 5141 int j, cnt = 0, free; 5142 5143 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5144 if (as[j].enable) 5145 cnt++; 5146 } 5147 if (sc->num_chans == 0) { 5148 sc->chans = (struct hdac_chan *)malloc( 5149 sizeof(struct hdac_chan) * cnt, 5150 M_HDAC, M_ZERO | M_NOWAIT); 5151 if (sc->chans == NULL) { 5152 device_printf(devinfo->codec->sc->dev, 5153 "Channels memory allocation failed!\n"); 5154 return; 5155 } 5156 } else { 5157 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5158 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5159 M_HDAC, M_ZERO | M_NOWAIT); 5160 if (sc->chans == NULL) { 5161 sc->num_chans = 0; 5162 device_printf(devinfo->codec->sc->dev, 5163 "Channels memory allocation failed!\n"); 5164 return; 5165 } 5166 } 5167 free = sc->num_chans; 5168 sc->num_chans += cnt; 5169 5170 for (j = free; j < free + cnt; j++) { 5171 devinfo->codec->sc->chans[j].devinfo = devinfo; 5172 devinfo->codec->sc->chans[j].as = -1; 5173 } 5174 5175 /* Assign associations in order of their numbers, */ 5176 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5177 if (as[j].enable == 0) 5178 continue; 5179 5180 as[j].chan = free; 5181 devinfo->codec->sc->chans[free].as = j; 5182 devinfo->codec->sc->chans[free].dir = 5183 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5184 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5185 free++; 5186 } 5187} 5188 5189static void 5190hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5191{ 5192 struct hdac_widget *w; 5193 int i; 5194 5195 /* Disable power and volume widgets. */ 5196 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5197 w = hdac_widget_get(devinfo, i); 5198 if (w == NULL || w->enable == 0) 5199 continue; 5200 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5201 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5202 w->enable = 0; 5203 HDA_BOOTHVERBOSE( 5204 device_printf(devinfo->codec->sc->dev, 5205 " Disabling nid %d due to it's" 5206 " non-audio type.\n", 5207 w->nid); 5208 ); 5209 } 5210 } 5211} 5212 5213static void 5214hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5215{ 5216 struct hdac_widget *w, *cw; 5217 struct hdac_audio_ctl *ctl; 5218 int done, found, i, j, k; 5219 5220 /* Disable useless pins. */ 5221 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5222 w = hdac_widget_get(devinfo, i); 5223 if (w == NULL || w->enable == 0) 5224 continue; 5225 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5226 if ((w->wclass.pin.config & 5227 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5228 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5229 w->enable = 0; 5230 HDA_BOOTHVERBOSE( 5231 device_printf(devinfo->codec->sc->dev, 5232 " Disabling pin nid %d due" 5233 " to None connectivity.\n", 5234 w->nid); 5235 ); 5236 } else if ((w->wclass.pin.config & 5237 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5238 w->enable = 0; 5239 HDA_BOOTHVERBOSE( 5240 device_printf(devinfo->codec->sc->dev, 5241 " Disabling unassociated" 5242 " pin nid %d.\n", 5243 w->nid); 5244 ); 5245 } 5246 } 5247 } 5248 do { 5249 done = 1; 5250 /* Disable and mute controls for disabled widgets. */ 5251 i = 0; 5252 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5253 if (ctl->enable == 0) 5254 continue; 5255 if (ctl->widget->enable == 0 || 5256 (ctl->childwidget != NULL && 5257 ctl->childwidget->enable == 0)) { 5258 ctl->forcemute = 1; 5259 ctl->muted = HDA_AMP_MUTE_ALL; 5260 ctl->left = 0; 5261 ctl->right = 0; 5262 ctl->enable = 0; 5263 if (ctl->ndir == HDA_CTL_IN) 5264 ctl->widget->connsenable[ctl->index] = 0; 5265 done = 0; 5266 HDA_BOOTHVERBOSE( 5267 device_printf(devinfo->codec->sc->dev, 5268 " Disabling ctl %d nid %d cnid %d due" 5269 " to disabled widget.\n", i, 5270 ctl->widget->nid, 5271 (ctl->childwidget != NULL)? 5272 ctl->childwidget->nid:-1); 5273 ); 5274 } 5275 } 5276 /* Disable useless widgets. */ 5277 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5278 w = hdac_widget_get(devinfo, i); 5279 if (w == NULL || w->enable == 0) 5280 continue; 5281 /* Disable inputs with disabled child widgets. */ 5282 for (j = 0; j < w->nconns; j++) { 5283 if (w->connsenable[j]) { 5284 cw = hdac_widget_get(devinfo, w->conns[j]); 5285 if (cw == NULL || cw->enable == 0) { 5286 w->connsenable[j] = 0; 5287 HDA_BOOTHVERBOSE( 5288 device_printf(devinfo->codec->sc->dev, 5289 " Disabling nid %d connection %d due" 5290 " to disabled child widget.\n", 5291 i, j); 5292 ); 5293 } 5294 } 5295 } 5296 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5297 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5298 continue; 5299 /* Disable mixers and selectors without inputs. */ 5300 found = 0; 5301 for (j = 0; j < w->nconns; j++) { 5302 if (w->connsenable[j]) { 5303 found = 1; 5304 break; 5305 } 5306 } 5307 if (found == 0) { 5308 w->enable = 0; 5309 done = 0; 5310 HDA_BOOTHVERBOSE( 5311 device_printf(devinfo->codec->sc->dev, 5312 " Disabling nid %d due to all it's" 5313 " inputs disabled.\n", w->nid); 5314 ); 5315 } 5316 /* Disable nodes without consumers. */ 5317 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5318 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5319 continue; 5320 found = 0; 5321 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5322 cw = hdac_widget_get(devinfo, k); 5323 if (cw == NULL || cw->enable == 0) 5324 continue; 5325 for (j = 0; j < cw->nconns; j++) { 5326 if (cw->connsenable[j] && cw->conns[j] == i) { 5327 found = 1; 5328 break; 5329 } 5330 } 5331 } 5332 if (found == 0) { 5333 w->enable = 0; 5334 done = 0; 5335 HDA_BOOTHVERBOSE( 5336 device_printf(devinfo->codec->sc->dev, 5337 " Disabling nid %d due to all it's" 5338 " consumers disabled.\n", w->nid); 5339 ); 5340 } 5341 } 5342 } while (done == 0); 5343 5344} 5345 5346static void 5347hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5348{ 5349 struct hdac_audio_as *as = devinfo->function.audio.as; 5350 struct hdac_widget *w, *cw; 5351 struct hdac_audio_ctl *ctl; 5352 int i, j, k; 5353 5354 /* Disable unassosiated widgets. */ 5355 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5356 w = hdac_widget_get(devinfo, i); 5357 if (w == NULL || w->enable == 0) 5358 continue; 5359 if (w->bindas == -1) { 5360 w->enable = 0; 5361 HDA_BOOTHVERBOSE( 5362 device_printf(devinfo->codec->sc->dev, 5363 " Disabling unassociated nid %d.\n", 5364 w->nid); 5365 ); 5366 } 5367 } 5368 /* Disable input connections on input pin and 5369 * output on output. */ 5370 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5371 w = hdac_widget_get(devinfo, i); 5372 if (w == NULL || w->enable == 0) 5373 continue; 5374 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5375 continue; 5376 if (w->bindas < 0) 5377 continue; 5378 if (as[w->bindas].dir == HDA_CTL_IN) { 5379 for (j = 0; j < w->nconns; j++) { 5380 if (w->connsenable[j] == 0) 5381 continue; 5382 w->connsenable[j] = 0; 5383 HDA_BOOTHVERBOSE( 5384 device_printf(devinfo->codec->sc->dev, 5385 " Disabling connection to input pin " 5386 "nid %d conn %d.\n", 5387 i, j); 5388 ); 5389 } 5390 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5391 HDA_CTL_IN, -1, 1); 5392 if (ctl && ctl->enable) { 5393 ctl->forcemute = 1; 5394 ctl->muted = HDA_AMP_MUTE_ALL; 5395 ctl->left = 0; 5396 ctl->right = 0; 5397 ctl->enable = 0; 5398 } 5399 } else { 5400 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5401 HDA_CTL_OUT, -1, 1); 5402 if (ctl && ctl->enable) { 5403 ctl->forcemute = 1; 5404 ctl->muted = HDA_AMP_MUTE_ALL; 5405 ctl->left = 0; 5406 ctl->right = 0; 5407 ctl->enable = 0; 5408 } 5409 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5410 cw = hdac_widget_get(devinfo, k); 5411 if (cw == NULL || cw->enable == 0) 5412 continue; 5413 for (j = 0; j < cw->nconns; j++) { 5414 if (cw->connsenable[j] && cw->conns[j] == i) { 5415 cw->connsenable[j] = 0; 5416 HDA_BOOTHVERBOSE( 5417 device_printf(devinfo->codec->sc->dev, 5418 " Disabling connection from output pin " 5419 "nid %d conn %d cnid %d.\n", 5420 k, j, i); 5421 ); 5422 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5423 cw->nconns > 1) 5424 continue; 5425 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5426 HDA_CTL_IN, j, 1); 5427 if (ctl && ctl->enable) { 5428 ctl->forcemute = 1; 5429 ctl->muted = HDA_AMP_MUTE_ALL; 5430 ctl->left = 0; 5431 ctl->right = 0; 5432 ctl->enable = 0; 5433 } 5434 } 5435 } 5436 } 5437 } 5438 } 5439} 5440 5441static void 5442hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5443{ 5444 struct hdac_audio_as *as = devinfo->function.audio.as; 5445 struct hdac_widget *w; 5446 int i, j; 5447 5448 /* On playback path we can safely disable all unseleted inputs. */ 5449 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5450 w = hdac_widget_get(devinfo, i); 5451 if (w == NULL || w->enable == 0) 5452 continue; 5453 if (w->nconns <= 1) 5454 continue; 5455 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5456 continue; 5457 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5458 continue; 5459 for (j = 0; j < w->nconns; j++) { 5460 if (w->connsenable[j] == 0) 5461 continue; 5462 if (w->selconn < 0 || w->selconn == j) 5463 continue; 5464 w->connsenable[j] = 0; 5465 HDA_BOOTHVERBOSE( 5466 device_printf(devinfo->codec->sc->dev, 5467 " Disabling unselected connection " 5468 "nid %d conn %d.\n", 5469 i, j); 5470 ); 5471 } 5472 } 5473} 5474 5475static void 5476hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5477{ 5478 struct hdac_widget *w, *cw; 5479 struct hdac_audio_ctl *ctl; 5480 int i, j; 5481 5482 /* Disable crossassociatement connections. */ 5483 /* ... using selectors */ 5484 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5485 w = hdac_widget_get(devinfo, i); 5486 if (w == NULL || w->enable == 0) 5487 continue; 5488 if (w->nconns <= 1) 5489 continue; 5490 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5491 continue; 5492 if (w->bindas == -2) 5493 continue; 5494 for (j = 0; j < w->nconns; j++) { 5495 if (w->connsenable[j] == 0) 5496 continue; 5497 cw = hdac_widget_get(devinfo, w->conns[j]); 5498 if (cw == NULL || w->enable == 0) 5499 continue; 5500 if (w->bindas == cw->bindas || cw->bindas == -2) 5501 continue; 5502 w->connsenable[j] = 0; 5503 HDA_BOOTHVERBOSE( 5504 device_printf(devinfo->codec->sc->dev, 5505 " Disabling crossassociatement connection " 5506 "nid %d conn %d cnid %d.\n", 5507 i, j, cw->nid); 5508 ); 5509 } 5510 } 5511 /* ... using controls */ 5512 i = 0; 5513 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5514 if (ctl->enable == 0 || ctl->childwidget == NULL) 5515 continue; 5516 if (ctl->widget->bindas == -2 || 5517 ctl->childwidget->bindas == -2) 5518 continue; 5519 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5520 ctl->forcemute = 1; 5521 ctl->muted = HDA_AMP_MUTE_ALL; 5522 ctl->left = 0; 5523 ctl->right = 0; 5524 ctl->enable = 0; 5525 if (ctl->ndir == HDA_CTL_IN) 5526 ctl->widget->connsenable[ctl->index] = 0; 5527 HDA_BOOTHVERBOSE( 5528 device_printf(devinfo->codec->sc->dev, 5529 " Disabling crossassociatement connection " 5530 "ctl %d nid %d cnid %d.\n", i, 5531 ctl->widget->nid, 5532 ctl->childwidget->nid); 5533 ); 5534 } 5535 } 5536 5537} 5538 5539#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5540 5541/* 5542 * Find controls to control amplification for source. 5543 */ 5544static int 5545hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5546 int ossdev, int ctlable, int depth, int need) 5547{ 5548 struct hdac_widget *w, *wc; 5549 struct hdac_audio_ctl *ctl; 5550 int i, j, conns = 0, rneed; 5551 5552 if (depth > HDA_PARSE_MAXDEPTH) 5553 return (need); 5554 5555 w = hdac_widget_get(devinfo, nid); 5556 if (w == NULL || w->enable == 0) 5557 return (need); 5558 5559 /* Count number of active inputs. */ 5560 if (depth > 0) { 5561 for (j = 0; j < w->nconns; j++) { 5562 if (w->connsenable[j]) 5563 conns++; 5564 } 5565 } 5566 5567 /* If this is not a first step - use input mixer. 5568 Pins have common input ctl so care must be taken. */ 5569 if (depth > 0 && ctlable && (conns == 1 || 5570 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5571 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5572 index, 1); 5573 if (ctl) { 5574 if (HDA_CTL_GIVE(ctl) & need) 5575 ctl->ossmask |= (1 << ossdev); 5576 else 5577 ctl->possmask |= (1 << ossdev); 5578 need &= ~HDA_CTL_GIVE(ctl); 5579 } 5580 } 5581 5582 /* If widget has own ossdev - not traverse it. 5583 It will be traversed on it's own. */ 5584 if (w->ossdev >= 0 && depth > 0) 5585 return (need); 5586 5587 /* We must not traverse pin */ 5588 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5589 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5590 depth > 0) 5591 return (need); 5592 5593 /* record that this widget exports such signal, */ 5594 w->ossmask |= (1 << ossdev); 5595 5596 /* If signals mixed, we can't assign controls farther. 5597 * Ignore this on depth zero. Caller must knows why. 5598 * Ignore this for static selectors if this input selected. 5599 */ 5600 if (conns > 1) 5601 ctlable = 0; 5602 5603 if (ctlable) { 5604 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5605 if (ctl) { 5606 if (HDA_CTL_GIVE(ctl) & need) 5607 ctl->ossmask |= (1 << ossdev); 5608 else 5609 ctl->possmask |= (1 << ossdev); 5610 need &= ~HDA_CTL_GIVE(ctl); 5611 } 5612 } 5613 5614 rneed = 0; 5615 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5616 wc = hdac_widget_get(devinfo, i); 5617 if (wc == NULL || wc->enable == 0) 5618 continue; 5619 for (j = 0; j < wc->nconns; j++) { 5620 if (wc->connsenable[j] && wc->conns[j] == nid) { 5621 rneed |= hdac_audio_ctl_source_amp(devinfo, 5622 wc->nid, j, ossdev, ctlable, depth + 1, need); 5623 } 5624 } 5625 } 5626 rneed &= need; 5627 5628 return (rneed); 5629} 5630 5631/* 5632 * Find controls to control amplification for destination. 5633 */ 5634static void 5635hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5636 int ossdev, int depth, int need) 5637{ 5638 struct hdac_audio_as *as = devinfo->function.audio.as; 5639 struct hdac_widget *w, *wc; 5640 struct hdac_audio_ctl *ctl; 5641 int i, j, consumers; 5642 5643 if (depth > HDA_PARSE_MAXDEPTH) 5644 return; 5645 5646 w = hdac_widget_get(devinfo, nid); 5647 if (w == NULL || w->enable == 0) 5648 return; 5649 5650 if (depth > 0) { 5651 /* If this node produce output for several consumers, 5652 we can't touch it. */ 5653 consumers = 0; 5654 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5655 wc = hdac_widget_get(devinfo, i); 5656 if (wc == NULL || wc->enable == 0) 5657 continue; 5658 for (j = 0; j < wc->nconns; j++) { 5659 if (wc->connsenable[j] && wc->conns[j] == nid) 5660 consumers++; 5661 } 5662 } 5663 /* The only exception is if real HP redirection is configured 5664 and this is a duplication point. 5665 XXX: Actually exception is not completely correct. 5666 XXX: Duplication point check is not perfect. */ 5667 if ((consumers == 2 && (w->bindas < 0 || 5668 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5669 (w->bindseqmask & (1 << 15)) == 0)) || 5670 consumers > 2) 5671 return; 5672 5673 /* Else use it's output mixer. */ 5674 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5675 HDA_CTL_OUT, -1, 1); 5676 if (ctl) { 5677 if (HDA_CTL_GIVE(ctl) & need) 5678 ctl->ossmask |= (1 << ossdev); 5679 else 5680 ctl->possmask |= (1 << ossdev); 5681 need &= ~HDA_CTL_GIVE(ctl); 5682 } 5683 } 5684 5685 /* We must not traverse pin */ 5686 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5687 depth > 0) 5688 return; 5689 5690 for (i = 0; i < w->nconns; i++) { 5691 int tneed = need; 5692 if (w->connsenable[i] == 0) 5693 continue; 5694 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5695 HDA_CTL_IN, i, 1); 5696 if (ctl) { 5697 if (HDA_CTL_GIVE(ctl) & tneed) 5698 ctl->ossmask |= (1 << ossdev); 5699 else 5700 ctl->possmask |= (1 << ossdev); 5701 tneed &= ~HDA_CTL_GIVE(ctl); 5702 } 5703 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5704 depth + 1, tneed); 5705 } 5706} 5707 5708/* 5709 * Assign OSS names to sound sources 5710 */ 5711static void 5712hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5713{ 5714 struct hdac_audio_as *as = devinfo->function.audio.as; 5715 struct hdac_widget *w; 5716 int i, j; 5717 int type = -1, use, used = 0; 5718 static const int types[7][13] = { 5719 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5720 SOUND_MIXER_LINE3, -1 }, /* line */ 5721 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5722 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5723 { SOUND_MIXER_CD, -1 }, /* cd */ 5724 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5725 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5726 -1 }, /* digital */ 5727 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5728 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5729 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5730 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5731 -1 } /* others */ 5732 }; 5733 5734 /* Surely known names */ 5735 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5736 w = hdac_widget_get(devinfo, i); 5737 if (w == NULL || w->enable == 0) 5738 continue; 5739 if (w->bindas == -1) 5740 continue; 5741 use = -1; 5742 switch (w->type) { 5743 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5744 if (as[w->bindas].dir == HDA_CTL_OUT) 5745 break; 5746 type = -1; 5747 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5748 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5749 type = 0; 5750 break; 5751 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5752 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5753 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5754 break; 5755 type = 1; 5756 break; 5757 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5758 type = 3; 5759 break; 5760 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5761 type = 4; 5762 break; 5763 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5764 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5765 type = 5; 5766 break; 5767 } 5768 if (type == -1) 5769 break; 5770 j = 0; 5771 while (types[type][j] >= 0 && 5772 (used & (1 << types[type][j])) != 0) { 5773 j++; 5774 } 5775 if (types[type][j] >= 0) 5776 use = types[type][j]; 5777 break; 5778 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5779 use = SOUND_MIXER_PCM; 5780 break; 5781 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5782 use = SOUND_MIXER_SPEAKER; 5783 break; 5784 default: 5785 break; 5786 } 5787 if (use >= 0) { 5788 w->ossdev = use; 5789 used |= (1 << use); 5790 } 5791 } 5792 /* Semi-known names */ 5793 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5794 w = hdac_widget_get(devinfo, i); 5795 if (w == NULL || w->enable == 0) 5796 continue; 5797 if (w->ossdev >= 0) 5798 continue; 5799 if (w->bindas == -1) 5800 continue; 5801 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5802 continue; 5803 if (as[w->bindas].dir == HDA_CTL_OUT) 5804 continue; 5805 type = -1; 5806 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5807 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5808 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5809 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5810 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5811 type = 0; 5812 break; 5813 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5814 type = 2; 5815 break; 5816 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5817 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5818 type = 5; 5819 break; 5820 } 5821 if (type == -1) 5822 break; 5823 j = 0; 5824 while (types[type][j] >= 0 && 5825 (used & (1 << types[type][j])) != 0) { 5826 j++; 5827 } 5828 if (types[type][j] >= 0) { 5829 w->ossdev = types[type][j]; 5830 used |= (1 << types[type][j]); 5831 } 5832 } 5833 /* Others */ 5834 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5835 w = hdac_widget_get(devinfo, i); 5836 if (w == NULL || w->enable == 0) 5837 continue; 5838 if (w->ossdev >= 0) 5839 continue; 5840 if (w->bindas == -1) 5841 continue; 5842 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5843 continue; 5844 if (as[w->bindas].dir == HDA_CTL_OUT) 5845 continue; 5846 j = 0; 5847 while (types[6][j] >= 0 && 5848 (used & (1 << types[6][j])) != 0) { 5849 j++; 5850 } 5851 if (types[6][j] >= 0) { 5852 w->ossdev = types[6][j]; 5853 used |= (1 << types[6][j]); 5854 } 5855 } 5856} 5857 5858static void 5859hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5860{ 5861 struct hdac_audio_as *as = devinfo->function.audio.as; 5862 int j, res; 5863 5864 /* Trace all associations in order of their numbers, */ 5865 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5866 if (as[j].enable == 0) 5867 continue; 5868 HDA_BOOTVERBOSE( 5869 device_printf(devinfo->codec->sc->dev, 5870 "Tracing association %d (%d)\n", j, as[j].index); 5871 ); 5872 if (as[j].dir == HDA_CTL_OUT) { 5873retry: 5874 res = hdac_audio_trace_as_out(devinfo, j, 0); 5875 if (res == 0 && as[j].hpredir >= 0 && 5876 as[j].fakeredir == 0) { 5877 /* If codec can't do analog HP redirection 5878 try to make it using one more DAC. */ 5879 as[j].fakeredir = 1; 5880 goto retry; 5881 } 5882 } else { 5883 res = hdac_audio_trace_as_in(devinfo, j); 5884 } 5885 if (res) { 5886 HDA_BOOTVERBOSE( 5887 device_printf(devinfo->codec->sc->dev, 5888 "Association %d (%d) trace succeded\n", 5889 j, as[j].index); 5890 ); 5891 } else { 5892 HDA_BOOTVERBOSE( 5893 device_printf(devinfo->codec->sc->dev, 5894 "Association %d (%d) trace failed\n", 5895 j, as[j].index); 5896 ); 5897 as[j].enable = 0; 5898 } 5899 } 5900 5901 /* Trace mixer and beeper pseudo associations. */ 5902 hdac_audio_trace_as_extra(devinfo); 5903} 5904 5905static void 5906hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5907{ 5908 struct hdac_audio_as *as = devinfo->function.audio.as; 5909 struct hdac_audio_ctl *ctl; 5910 struct hdac_widget *w; 5911 int i; 5912 5913 /* Assign mixers to the tree. */ 5914 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5915 w = hdac_widget_get(devinfo, i); 5916 if (w == NULL || w->enable == 0) 5917 continue; 5918 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5919 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5920 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5921 as[w->bindas].dir == HDA_CTL_IN)) { 5922 if (w->ossdev < 0) 5923 continue; 5924 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5925 w->ossdev, 1, 0, 1); 5926 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5927 if (w->ossdev < 0) 5928 continue; 5929 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5930 w->ossdev, 1, 0, 1)) { 5931 /* If we are unable to control input monitor 5932 as source - try to control it as destination. */ 5933 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5934 w->ossdev, 0, 1); 5935 } 5936 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5937 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5938 SOUND_MIXER_RECLEV, 0, 1); 5939 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5940 as[w->bindas].dir == HDA_CTL_OUT) { 5941 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5942 SOUND_MIXER_VOLUME, 0, 1); 5943 } 5944 } 5945 /* Treat unrequired as possible. */ 5946 i = 0; 5947 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5948 if (ctl->ossmask == 0) 5949 ctl->ossmask = ctl->possmask; 5950 } 5951} 5952 5953static void 5954hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5955{ 5956 struct hdac_audio_as *as = devinfo->function.audio.as; 5957 struct hdac_widget *w; 5958 uint32_t pincap; 5959 int i; 5960 5961 for (i = 0; i < devinfo->nodecnt; i++) { 5962 w = &devinfo->widget[i]; 5963 if (w == NULL) 5964 continue; 5965 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5966 continue; 5967 5968 pincap = w->wclass.pin.cap; 5969 5970 /* Disable everything. */ 5971 w->wclass.pin.ctrl &= ~( 5972 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5973 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5974 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5975 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5976 5977 if (w->enable == 0 || 5978 w->bindas < 0 || as[w->bindas].enable == 0) { 5979 /* Pin is unused so left it disabled. */ 5980 continue; 5981 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5982 /* Input pin, configure for input. */ 5983 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5984 w->wclass.pin.ctrl |= 5985 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5986 5987 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5988 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5989 w->wclass.pin.ctrl |= 5990 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5991 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5992 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5993 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5994 w->wclass.pin.ctrl |= 5995 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5996 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5997 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5998 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5999 w->wclass.pin.ctrl |= 6000 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6001 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6002 } else { 6003 /* Output pin, configure for output. */ 6004 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6005 w->wclass.pin.ctrl |= 6006 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6007 6008 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6009 (w->wclass.pin.config & 6010 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6011 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6012 w->wclass.pin.ctrl |= 6013 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6014 6015 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6016 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6017 w->wclass.pin.ctrl |= 6018 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6019 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6020 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6021 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6022 w->wclass.pin.ctrl |= 6023 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6024 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6025 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6026 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6027 w->wclass.pin.ctrl |= 6028 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6029 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6030 } 6031 } 6032} 6033 6034static void 6035hdac_audio_commit(struct hdac_devinfo *devinfo) 6036{ 6037 struct hdac_softc *sc = devinfo->codec->sc; 6038 struct hdac_widget *w; 6039 nid_t cad; 6040 uint32_t gdata, gmask, gdir; 6041 int commitgpio, numgpio; 6042 int i; 6043 6044 cad = devinfo->codec->cad; 6045 6046 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6047 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6048 0x7e7, 0), cad); 6049 6050 gdata = 0; 6051 gmask = 0; 6052 gdir = 0; 6053 commitgpio = 0; 6054 6055 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6056 devinfo->function.audio.gpio); 6057 6058 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6059 commitgpio = (numgpio > 0) ? 1 : 0; 6060 else { 6061 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6062 if (!(devinfo->function.audio.quirks & 6063 (1 << i))) 6064 continue; 6065 if (commitgpio == 0) { 6066 commitgpio = 1; 6067 HDA_BOOTVERBOSE( 6068 gdata = hdac_command(sc, 6069 HDA_CMD_GET_GPIO_DATA(cad, 6070 devinfo->nid), cad); 6071 gmask = hdac_command(sc, 6072 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6073 devinfo->nid), cad); 6074 gdir = hdac_command(sc, 6075 HDA_CMD_GET_GPIO_DIRECTION(cad, 6076 devinfo->nid), cad); 6077 device_printf(sc->dev, 6078 "GPIO init: data=0x%08x " 6079 "mask=0x%08x dir=0x%08x\n", 6080 gdata, gmask, gdir); 6081 gdata = 0; 6082 gmask = 0; 6083 gdir = 0; 6084 ); 6085 } 6086 gdata |= 1 << i; 6087 gmask |= 1 << i; 6088 gdir |= 1 << i; 6089 } 6090 } 6091 6092 if (commitgpio != 0) { 6093 HDA_BOOTVERBOSE( 6094 device_printf(sc->dev, 6095 "GPIO commit: data=0x%08x mask=0x%08x " 6096 "dir=0x%08x\n", 6097 gdata, gmask, gdir); 6098 ); 6099 hdac_command(sc, 6100 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6101 gmask), cad); 6102 hdac_command(sc, 6103 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6104 gdir), cad); 6105 hdac_command(sc, 6106 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6107 gdata), cad); 6108 } 6109 6110 for (i = 0; i < devinfo->nodecnt; i++) { 6111 w = &devinfo->widget[i]; 6112 if (w == NULL) 6113 continue; 6114 if (w->selconn == -1) 6115 w->selconn = 0; 6116 if (w->nconns > 0) 6117 hdac_widget_connection_select(w, w->selconn); 6118 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6119 hdac_command(sc, 6120 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6121 w->wclass.pin.ctrl), cad); 6122 } 6123 if (w->param.eapdbtl != HDAC_INVALID) { 6124 uint32_t val; 6125 6126 val = w->param.eapdbtl; 6127 if (devinfo->function.audio.quirks & 6128 HDA_QUIRK_EAPDINV) 6129 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6130 hdac_command(sc, 6131 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6132 val), cad); 6133 6134 } 6135 } 6136} 6137 6138static void 6139hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6140{ 6141 struct hdac_audio_ctl *ctl; 6142 int i, z; 6143 6144 i = 0; 6145 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6146 if (ctl->enable == 0) { 6147 /* Mute disabled controls. */ 6148 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6149 continue; 6150 } 6151 /* Init controls to 0dB amplification. */ 6152 z = ctl->offset; 6153 if (z > ctl->step) 6154 z = ctl->step; 6155 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6156 } 6157} 6158 6159static void 6160hdac_powerup(struct hdac_devinfo *devinfo) 6161{ 6162 struct hdac_softc *sc = devinfo->codec->sc; 6163 nid_t cad = devinfo->codec->cad; 6164 int i; 6165 6166 hdac_command(sc, 6167 HDA_CMD_SET_POWER_STATE(cad, 6168 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6169 cad); 6170 DELAY(100); 6171 6172 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6173 hdac_command(sc, 6174 HDA_CMD_SET_POWER_STATE(cad, 6175 i, HDA_CMD_POWER_STATE_D0), 6176 cad); 6177 } 6178 DELAY(1000); 6179} 6180 6181static int 6182hdac_pcmchannel_setup(struct hdac_chan *ch) 6183{ 6184 struct hdac_devinfo *devinfo = ch->devinfo; 6185 struct hdac_audio_as *as = devinfo->function.audio.as; 6186 struct hdac_widget *w; 6187 uint32_t cap, fmtcap, pcmcap; 6188 int i, j, ret, max; 6189 6190 ch->caps = hdac_caps; 6191 ch->caps.fmtlist = ch->fmtlist; 6192 ch->bit16 = 1; 6193 ch->bit32 = 0; 6194 ch->pcmrates[0] = 48000; 6195 ch->pcmrates[1] = 0; 6196 6197 ret = 0; 6198 fmtcap = devinfo->function.audio.supp_stream_formats; 6199 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6200 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6201 6202 for (i = 0; i < 16 && ret < max; i++) { 6203 /* Check as is correct */ 6204 if (ch->as < 0) 6205 break; 6206 /* Cound only present DACs */ 6207 if (as[ch->as].dacs[i] <= 0) 6208 continue; 6209 /* Ignore duplicates */ 6210 for (j = 0; j < ret; j++) { 6211 if (ch->io[j] == as[ch->as].dacs[i]) 6212 break; 6213 } 6214 if (j < ret) 6215 continue; 6216 6217 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6218 if (w == NULL || w->enable == 0) 6219 continue; 6220 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6221 continue; 6222 cap = w->param.supp_stream_formats; 6223 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6224 }*/ 6225 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6226 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6227 continue; 6228 /* Many codec does not declare AC3 support on SPDIF. 6229 I don't beleave that they doesn't support it! */ 6230 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6231 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6232 if (ret == 0) { 6233 fmtcap = cap; 6234 pcmcap = w->param.supp_pcm_size_rate; 6235 } else { 6236 fmtcap &= cap; 6237 pcmcap &= w->param.supp_pcm_size_rate; 6238 } 6239 ch->io[ret++] = as[ch->as].dacs[i]; 6240 } 6241 ch->io[ret] = -1; 6242 6243 ch->supp_stream_formats = fmtcap; 6244 ch->supp_pcm_size_rate = pcmcap; 6245 6246 /* 6247 * 8bit = 0 6248 * 16bit = 1 6249 * 20bit = 2 6250 * 24bit = 3 6251 * 32bit = 4 6252 */ 6253 if (ret > 0) { 6254 i = 0; 6255 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6256 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6257 ch->bit16 = 1; 6258 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6259 ch->bit16 = 0; 6260 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6261 ch->bit32 = 4; 6262 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6263 ch->bit32 = 3; 6264 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6265 ch->bit32 = 2; 6266 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6267 ch->fmtlist[i++] = AFMT_S16_LE; 6268 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6269 if (ch->bit32 > 0) { 6270 if (!(devinfo->function.audio.quirks & 6271 HDA_QUIRK_FORCESTEREO)) 6272 ch->fmtlist[i++] = AFMT_S32_LE; 6273 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6274 } 6275 } 6276 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6277 ch->fmtlist[i++] = AFMT_AC3; 6278 } 6279 ch->fmtlist[i] = 0; 6280 i = 0; 6281 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6282 ch->pcmrates[i++] = 8000; 6283 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6284 ch->pcmrates[i++] = 11025; 6285 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6286 ch->pcmrates[i++] = 16000; 6287 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6288 ch->pcmrates[i++] = 22050; 6289 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6290 ch->pcmrates[i++] = 32000; 6291 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6292 ch->pcmrates[i++] = 44100; 6293 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6294 ch->pcmrates[i++] = 48000; 6295 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6296 ch->pcmrates[i++] = 88200; 6297 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6298 ch->pcmrates[i++] = 96000; 6299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6300 ch->pcmrates[i++] = 176400; 6301 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6302 ch->pcmrates[i++] = 192000; 6303 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6304 ch->pcmrates[i] = 0; 6305 if (i > 0) { 6306 ch->caps.minspeed = ch->pcmrates[0]; 6307 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6308 } 6309 } 6310 6311 return (ret); 6312} 6313 6314static void 6315hdac_create_pcms(struct hdac_devinfo *devinfo) 6316{ 6317 struct hdac_softc *sc = devinfo->codec->sc; 6318 struct hdac_audio_as *as = devinfo->function.audio.as; 6319 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6320 6321 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6322 if (as[i].enable == 0) 6323 continue; 6324 if (as[i].dir == HDA_CTL_IN) { 6325 if (as[i].digital) 6326 drdev++; 6327 else 6328 ardev++; 6329 } else { 6330 if (as[i].digital) 6331 dpdev++; 6332 else 6333 apdev++; 6334 } 6335 } 6336 devinfo->function.audio.num_devs = 6337 max(ardev, apdev) + max(drdev, dpdev); 6338 devinfo->function.audio.devs = 6339 (struct hdac_pcm_devinfo *)malloc( 6340 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6341 M_HDAC, M_ZERO | M_NOWAIT); 6342 if (devinfo->function.audio.devs == NULL) { 6343 device_printf(sc->dev, 6344 "Unable to allocate memory for devices\n"); 6345 return; 6346 } 6347 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6348 devinfo->function.audio.devs[i].index = i; 6349 devinfo->function.audio.devs[i].devinfo = devinfo; 6350 devinfo->function.audio.devs[i].play = -1; 6351 devinfo->function.audio.devs[i].rec = -1; 6352 devinfo->function.audio.devs[i].digital = 2; 6353 } 6354 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6355 if (as[i].enable == 0) 6356 continue; 6357 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6358 if (devinfo->function.audio.devs[j].digital != 2 && 6359 devinfo->function.audio.devs[j].digital != 6360 as[i].digital) 6361 continue; 6362 if (as[i].dir == HDA_CTL_IN) { 6363 if (devinfo->function.audio.devs[j].rec >= 0) 6364 continue; 6365 devinfo->function.audio.devs[j].rec 6366 = as[i].chan; 6367 } else { 6368 if (devinfo->function.audio.devs[j].play >= 0) 6369 continue; 6370 devinfo->function.audio.devs[j].play 6371 = as[i].chan; 6372 } 6373 sc->chans[as[i].chan].pdevinfo = 6374 &devinfo->function.audio.devs[j]; 6375 devinfo->function.audio.devs[j].digital = 6376 as[i].digital; 6377 break; 6378 } 6379 } 6380 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6381 struct hdac_pcm_devinfo *pdevinfo = 6382 &devinfo->function.audio.devs[i]; 6383 pdevinfo->dev = 6384 device_add_child(sc->dev, "pcm", -1); 6385 device_set_ivars(pdevinfo->dev, 6386 (void *)pdevinfo); 6387 } 6388} 6389 6390static void 6391hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6392{ 6393 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6394 struct hdac_audio_ctl *ctl; 6395 struct hdac_softc *sc = devinfo->codec->sc; 6396 char buf[64]; 6397 int i, j, printed; 6398 6399 if (flag == 0) { 6400 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6401 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6402 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6403 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6404 } 6405 6406 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6407 if ((flag & (1 << j)) == 0) 6408 continue; 6409 i = 0; 6410 printed = 0; 6411 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6412 if (ctl->enable == 0 || 6413 ctl->widget->enable == 0) 6414 continue; 6415 if (!((pdevinfo->play >= 0 && 6416 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6417 (pdevinfo->rec >= 0 && 6418 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6419 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6420 continue; 6421 if ((ctl->ossmask & (1 << j)) == 0) 6422 continue; 6423 6424 if (printed == 0) { 6425 device_printf(pdevinfo->dev, "\n"); 6426 if (banner != NULL) { 6427 device_printf(pdevinfo->dev, "%s", banner); 6428 } else { 6429 device_printf(pdevinfo->dev, "Unknown Ctl"); 6430 } 6431 printf(" (OSS: %s)\n", 6432 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6433 buf, sizeof(buf))); 6434 device_printf(pdevinfo->dev, " |\n"); 6435 printed = 1; 6436 } 6437 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6438 ctl->widget->nid, 6439 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6440 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6441 printf(" %2d): ", ctl->index); 6442 else 6443 printf("): "); 6444 if (ctl->step > 0) { 6445 printf("%+d/%+ddB (%d steps)%s\n", 6446 (0 - ctl->offset) * (ctl->size + 1) / 4, 6447 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6448 ctl->step + 1, 6449 ctl->mute?" + mute":""); 6450 } else 6451 printf("%s\n", ctl->mute?"mute":""); 6452 } 6453 } 6454} 6455 6456static void 6457hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6458{ 6459 uint32_t cap; 6460 6461 cap = fcap; 6462 if (cap != 0) { 6463 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6464 device_printf(dev, " "); 6465 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6466 printf(" AC3"); 6467 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6468 printf(" FLOAT32"); 6469 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6470 printf(" PCM"); 6471 printf("\n"); 6472 } 6473 cap = pcmcap; 6474 if (cap != 0) { 6475 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6476 device_printf(dev, " "); 6477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6478 printf(" 8"); 6479 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6480 printf(" 16"); 6481 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6482 printf(" 20"); 6483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6484 printf(" 24"); 6485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6486 printf(" 32"); 6487 printf(" bits,"); 6488 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6489 printf(" 8"); 6490 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6491 printf(" 11"); 6492 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6493 printf(" 16"); 6494 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6495 printf(" 22"); 6496 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6497 printf(" 32"); 6498 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6499 printf(" 44"); 6500 printf(" 48"); 6501 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6502 printf(" 88"); 6503 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6504 printf(" 96"); 6505 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6506 printf(" 176"); 6507 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6508 printf(" 192"); 6509 printf(" KHz\n"); 6510 } 6511} 6512 6513static void 6514hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6515{ 6516 uint32_t pincap; 6517 6518 pincap = w->wclass.pin.cap; 6519 6520 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6521 device_printf(sc->dev, " "); 6522 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6523 printf(" ISC"); 6524 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6525 printf(" TRQD"); 6526 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6527 printf(" PDC"); 6528 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6529 printf(" HP"); 6530 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6531 printf(" OUT"); 6532 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6533 printf(" IN"); 6534 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6535 printf(" BAL"); 6536 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6537 printf(" VREF["); 6538 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6539 printf(" 50"); 6540 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6541 printf(" 80"); 6542 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6543 printf(" 100"); 6544 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6545 printf(" GROUND"); 6546 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6547 printf(" HIZ"); 6548 printf(" ]"); 6549 } 6550 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6551 printf(" EAPD"); 6552 printf("\n"); 6553 device_printf(sc->dev, " Pin config: 0x%08x\n", 6554 w->wclass.pin.config); 6555 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6556 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6557 printf(" HP"); 6558 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6559 printf(" IN"); 6560 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6561 printf(" OUT"); 6562 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6563 printf(" VREFs"); 6564 printf("\n"); 6565} 6566 6567static void 6568hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6569{ 6570 struct hdac_softc *sc = w->devinfo->codec->sc; 6571 6572 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6573 "jack %2d loc %2d color %7s misc %d%s\n", 6574 w->nid, conf, 6575 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6576 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6577 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6578 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6579 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6580 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6581 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6582 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6583 (w->enable == 0)?" [DISABLED]":""); 6584} 6585 6586static void 6587hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6588{ 6589 struct hdac_widget *w; 6590 int i; 6591 6592 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6593 w = hdac_widget_get(devinfo, i); 6594 if (w == NULL) 6595 continue; 6596 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6597 continue; 6598 hdac_dump_pin_config(w, w->wclass.pin.config); 6599 } 6600} 6601 6602static void 6603hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6604{ 6605 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6606 device_printf(sc->dev, " " 6607 "mute=%d step=%d size=%d offset=%d\n", 6608 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6609 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6610 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6611 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6612} 6613 6614static void 6615hdac_dump_nodes(struct hdac_devinfo *devinfo) 6616{ 6617 struct hdac_softc *sc = devinfo->codec->sc; 6618 static char *ossname[] = SOUND_DEVICE_NAMES; 6619 struct hdac_widget *w, *cw; 6620 char buf[64]; 6621 int i, j; 6622 6623 device_printf(sc->dev, "\n"); 6624 device_printf(sc->dev, "Default Parameter\n"); 6625 device_printf(sc->dev, "-----------------\n"); 6626 hdac_dump_audio_formats(sc->dev, 6627 devinfo->function.audio.supp_stream_formats, 6628 devinfo->function.audio.supp_pcm_size_rate); 6629 device_printf(sc->dev, " IN amp: 0x%08x\n", 6630 devinfo->function.audio.inamp_cap); 6631 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6632 devinfo->function.audio.outamp_cap); 6633 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6634 w = hdac_widget_get(devinfo, i); 6635 if (w == NULL) { 6636 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6637 continue; 6638 } 6639 device_printf(sc->dev, "\n"); 6640 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6641 (w->enable == 0) ? " [DISABLED]" : ""); 6642 device_printf(sc->dev, " Name: %s\n", w->name); 6643 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6644 w->param.widget_cap); 6645 if (w->param.widget_cap & 0x0ee1) { 6646 device_printf(sc->dev, " "); 6647 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6648 printf(" LRSWAP"); 6649 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6650 printf(" PWR"); 6651 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6652 printf(" DIGITAL"); 6653 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6654 printf(" UNSOL"); 6655 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6656 printf(" PROC"); 6657 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6658 printf(" STRIPE"); 6659 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6660 printf(" STEREO"); 6661 printf("\n"); 6662 } 6663 if (w->bindas != -1) { 6664 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6665 w->bindas, w->bindseqmask); 6666 } 6667 if (w->ossmask != 0 || w->ossdev >= 0) { 6668 device_printf(sc->dev, " OSS: %s", 6669 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6670 if (w->ossdev >= 0) 6671 printf(" (%s)", ossname[w->ossdev]); 6672 printf("\n"); 6673 } 6674 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6675 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6676 hdac_dump_audio_formats(sc->dev, 6677 w->param.supp_stream_formats, 6678 w->param.supp_pcm_size_rate); 6679 } else if (w->type == 6680 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6681 hdac_dump_pin(sc, w); 6682 if (w->param.eapdbtl != HDAC_INVALID) 6683 device_printf(sc->dev, " EAPD: 0x%08x\n", 6684 w->param.eapdbtl); 6685 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6686 w->param.outamp_cap != 0) 6687 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6688 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6689 w->param.inamp_cap != 0) 6690 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6691 if (w->nconns > 0) { 6692 device_printf(sc->dev, " connections: %d\n", w->nconns); 6693 device_printf(sc->dev, " |\n"); 6694 } 6695 for (j = 0; j < w->nconns; j++) { 6696 cw = hdac_widget_get(devinfo, w->conns[j]); 6697 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6698 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6699 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6700 if (cw == NULL) 6701 printf(" [UNKNOWN]"); 6702 else if (cw->enable == 0) 6703 printf(" [DISABLED]"); 6704 if (w->nconns > 1 && w->selconn == j && w->type != 6705 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6706 printf(" (selected)"); 6707 printf("\n"); 6708 } 6709 } 6710 6711} 6712 6713static void 6714hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6715{ 6716 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6717 struct hdac_widget *w, *cw; 6718 char buf[64]; 6719 int i, printed = 0; 6720 6721 if (depth > HDA_PARSE_MAXDEPTH) 6722 return; 6723 6724 w = hdac_widget_get(devinfo, nid); 6725 if (w == NULL || w->enable == 0) 6726 return; 6727 6728 if (depth == 0) 6729 device_printf(pdevinfo->dev, "%*s", 4, ""); 6730 else 6731 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6732 printf("nid=%d [%s]", w->nid, w->name); 6733 6734 if (depth > 0) { 6735 if (w->ossmask == 0) { 6736 printf("\n"); 6737 return; 6738 } 6739 printf(" [src: %s]", 6740 hdac_audio_ctl_ossmixer_mask2allname( 6741 w->ossmask, buf, sizeof(buf))); 6742 if (w->ossdev >= 0) { 6743 printf("\n"); 6744 return; 6745 } 6746 } 6747 printf("\n"); 6748 6749 for (i = 0; i < w->nconns; i++) { 6750 if (w->connsenable[i] == 0) 6751 continue; 6752 cw = hdac_widget_get(devinfo, w->conns[i]); 6753 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6754 continue; 6755 if (printed == 0) { 6756 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6757 printed = 1; 6758 } 6759 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6760 } 6761 6762} 6763 6764static void 6765hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6766{ 6767 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6768 struct hdac_softc *sc = devinfo->codec->sc; 6769 struct hdac_widget *w; 6770 int i, printed = 0; 6771 6772 if (pdevinfo->play < 0) 6773 return; 6774 6775 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6776 w = hdac_widget_get(devinfo, i); 6777 if (w == NULL || w->enable == 0) 6778 continue; 6779 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6780 continue; 6781 if (w->bindas != sc->chans[pdevinfo->play].as) 6782 continue; 6783 if (printed == 0) { 6784 printed = 1; 6785 device_printf(pdevinfo->dev, "\n"); 6786 device_printf(pdevinfo->dev, "Playback:\n"); 6787 } 6788 device_printf(pdevinfo->dev, "\n"); 6789 hdac_dump_dst_nid(pdevinfo, i, 0); 6790 } 6791} 6792 6793static void 6794hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6795{ 6796 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6797 struct hdac_softc *sc = devinfo->codec->sc; 6798 struct hdac_widget *w; 6799 int i; 6800 int printed = 0; 6801 6802 if (pdevinfo->rec < 0) 6803 return; 6804 6805 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6806 w = hdac_widget_get(devinfo, i); 6807 if (w == NULL || w->enable == 0) 6808 continue; 6809 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6810 continue; 6811 if (w->bindas != sc->chans[pdevinfo->rec].as) 6812 continue; 6813 if (printed == 0) { 6814 printed = 1; 6815 device_printf(pdevinfo->dev, "\n"); 6816 device_printf(pdevinfo->dev, "Record:\n"); 6817 } 6818 device_printf(pdevinfo->dev, "\n"); 6819 hdac_dump_dst_nid(pdevinfo, i, 0); 6820 } 6821} 6822 6823static void 6824hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6825{ 6826 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6827 struct hdac_widget *w; 6828 int i; 6829 int printed = 0; 6830 6831 if (pdevinfo->index != 0) 6832 return; 6833 6834 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6835 w = hdac_widget_get(devinfo, i); 6836 if (w == NULL || w->enable == 0) 6837 continue; 6838 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6839 continue; 6840 if (printed == 0) { 6841 printed = 1; 6842 device_printf(pdevinfo->dev, "\n"); 6843 device_printf(pdevinfo->dev, "Input Mix:\n"); 6844 } 6845 device_printf(pdevinfo->dev, "\n"); 6846 hdac_dump_dst_nid(pdevinfo, i, 0); 6847 } 6848} 6849 6850static void 6851hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6852{ 6853 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6854 nid_t *nids; 6855 int i; 6856 6857 if (pdevinfo->play >= 0) { 6858 i = pdevinfo->play; 6859 device_printf(pdevinfo->dev, "\n"); 6860 device_printf(pdevinfo->dev, "Playback:\n"); 6861 device_printf(pdevinfo->dev, "\n"); 6862 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6863 sc->chans[i].supp_pcm_size_rate); 6864 device_printf(pdevinfo->dev, " DAC:"); 6865 for (nids = sc->chans[i].io; *nids != -1; nids++) 6866 printf(" %d", *nids); 6867 printf("\n"); 6868 } 6869 if (pdevinfo->rec >= 0) { 6870 i = pdevinfo->rec; 6871 device_printf(pdevinfo->dev, "\n"); 6872 device_printf(pdevinfo->dev, "Record:\n"); 6873 device_printf(pdevinfo->dev, "\n"); 6874 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6875 sc->chans[i].supp_pcm_size_rate); 6876 device_printf(pdevinfo->dev, " ADC:"); 6877 for (nids = sc->chans[i].io; *nids != -1; nids++) 6878 printf(" %d", *nids); 6879 printf("\n"); 6880 } 6881} 6882 6883static void 6884hdac_release_resources(struct hdac_softc *sc) 6885{ 6886 int i, j; 6887 6888 if (sc == NULL) 6889 return; 6890 6891 hdac_lock(sc); 6892 sc->polling = 0; 6893 sc->poll_ival = 0; 6894 callout_stop(&sc->poll_hda); 6895 callout_stop(&sc->poll_hdac); 6896 callout_stop(&sc->poll_jack); 6897 hdac_reset(sc, 0); 6898 hdac_unlock(sc); 6899 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6900 callout_drain(&sc->poll_hda); 6901 callout_drain(&sc->poll_hdac); 6902 callout_drain(&sc->poll_jack); 6903 6904 hdac_irq_free(sc); 6905 6906 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6907 if (sc->codecs[i] == NULL) 6908 continue; 6909 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6910 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6911 if (sc->codecs[i]->fgs[j].node_type == 6912 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6913 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6914 M_HDAC); 6915 free(sc->codecs[i]->fgs[j].function.audio.as, 6916 M_HDAC); 6917 free(sc->codecs[i]->fgs[j].function.audio.devs, 6918 M_HDAC); 6919 } 6920 } 6921 free(sc->codecs[i]->fgs, M_HDAC); 6922 free(sc->codecs[i], M_HDAC); 6923 sc->codecs[i] = NULL; 6924 } 6925 6926 hdac_dma_free(sc, &sc->pos_dma); 6927 hdac_dma_free(sc, &sc->rirb_dma); 6928 hdac_dma_free(sc, &sc->corb_dma); 6929 for (i = 0; i < sc->num_chans; i++) { 6930 if (sc->chans[i].blkcnt > 0) 6931 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6932 } 6933 free(sc->chans, M_HDAC); 6934 if (sc->chan_dmat != NULL) { 6935 bus_dma_tag_destroy(sc->chan_dmat); 6936 sc->chan_dmat = NULL; 6937 } 6938 hdac_mem_free(sc); 6939 snd_mtxfree(sc->lock); 6940} 6941 6942/* This function surely going to make its way into upper level someday. */ 6943static void 6944hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6945{ 6946 const char *res = NULL; 6947 int i = 0, j, k, len, inv; 6948 6949 if (on != NULL) 6950 *on = 0; 6951 if (off != NULL) 6952 *off = 0; 6953 if (sc == NULL) 6954 return; 6955 if (resource_string_value(device_get_name(sc->dev), 6956 device_get_unit(sc->dev), "config", &res) != 0) 6957 return; 6958 if (!(res != NULL && strlen(res) > 0)) 6959 return; 6960 HDA_BOOTVERBOSE( 6961 device_printf(sc->dev, "HDA Config:"); 6962 ); 6963 for (;;) { 6964 while (res[i] != '\0' && 6965 (res[i] == ',' || isspace(res[i]) != 0)) 6966 i++; 6967 if (res[i] == '\0') { 6968 HDA_BOOTVERBOSE( 6969 printf("\n"); 6970 ); 6971 return; 6972 } 6973 j = i; 6974 while (res[j] != '\0' && 6975 !(res[j] == ',' || isspace(res[j]) != 0)) 6976 j++; 6977 len = j - i; 6978 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6979 inv = 2; 6980 else 6981 inv = 0; 6982 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6983 if (strncmp(res + i + inv, 6984 hdac_quirks_tab[k].key, len - inv) != 0) 6985 continue; 6986 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6987 break; 6988 HDA_BOOTVERBOSE( 6989 printf(" %s%s", (inv != 0) ? "no" : "", 6990 hdac_quirks_tab[k].key); 6991 ); 6992 if (inv == 0 && on != NULL) 6993 *on |= hdac_quirks_tab[k].value; 6994 else if (inv != 0 && off != NULL) 6995 *off |= hdac_quirks_tab[k].value; 6996 break; 6997 } 6998 i = j; 6999 } 7000} 7001 7002#ifdef SND_DYNSYSCTL 7003static int 7004sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7005{ 7006 struct hdac_softc *sc; 7007 device_t dev; 7008 uint32_t ctl; 7009 int err, val; 7010 7011 dev = oidp->oid_arg1; 7012 sc = device_get_softc(dev); 7013 if (sc == NULL) 7014 return (EINVAL); 7015 hdac_lock(sc); 7016 val = sc->polling; 7017 hdac_unlock(sc); 7018 err = sysctl_handle_int(oidp, &val, 0, req); 7019 7020 if (err != 0 || req->newptr == NULL) 7021 return (err); 7022 if (val < 0 || val > 1) 7023 return (EINVAL); 7024 7025 hdac_lock(sc); 7026 if (val != sc->polling) { 7027 if (val == 0) { 7028 callout_stop(&sc->poll_hda); 7029 callout_stop(&sc->poll_hdac); 7030 hdac_unlock(sc); 7031 callout_drain(&sc->poll_hda); 7032 callout_drain(&sc->poll_hdac); 7033 hdac_lock(sc); 7034 sc->polling = 0; 7035 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7036 ctl |= HDAC_INTCTL_GIE; 7037 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7038 } else { 7039 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7040 ctl &= ~HDAC_INTCTL_GIE; 7041 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7042 hdac_unlock(sc); 7043 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7044 hdac_lock(sc); 7045 sc->polling = 1; 7046 hdac_poll_reinit(sc); 7047 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7048 } 7049 } 7050 hdac_unlock(sc); 7051 7052 return (err); 7053} 7054 7055static int 7056sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7057{ 7058 struct hdac_softc *sc; 7059 device_t dev; 7060 int err, val; 7061 7062 dev = oidp->oid_arg1; 7063 sc = device_get_softc(dev); 7064 if (sc == NULL) 7065 return (EINVAL); 7066 hdac_lock(sc); 7067 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7068 hdac_unlock(sc); 7069 err = sysctl_handle_int(oidp, &val, 0, req); 7070 7071 if (err != 0 || req->newptr == NULL) 7072 return (err); 7073 7074 if (val < 1) 7075 val = 1; 7076 if (val > 5000) 7077 val = 5000; 7078 val = ((uint64_t)val * hz) / 1000; 7079 if (val < 1) 7080 val = 1; 7081 if (val > (hz * 5)) 7082 val = hz * 5; 7083 7084 hdac_lock(sc); 7085 sc->poll_ival = val; 7086 hdac_unlock(sc); 7087 7088 return (err); 7089} 7090 7091static int 7092sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7093{ 7094 struct hdac_softc *sc; 7095 struct hdac_codec *codec; 7096 struct hdac_devinfo *devinfo; 7097 struct hdac_widget *w; 7098 device_t dev; 7099 uint32_t res, pincap, delay; 7100 int codec_index, fg_index; 7101 int i, err, val; 7102 nid_t cad; 7103 7104 dev = oidp->oid_arg1; 7105 sc = device_get_softc(dev); 7106 if (sc == NULL) 7107 return (EINVAL); 7108 val = 0; 7109 err = sysctl_handle_int(oidp, &val, 0, req); 7110 if (err != 0 || req->newptr == NULL || val == 0) 7111 return (err); 7112 7113 /* XXX: Temporary. For debugging. */ 7114 if (val == 100) { 7115 hdac_suspend(dev); 7116 return (0); 7117 } else if (val == 101) { 7118 hdac_resume(dev); 7119 return (0); 7120 } 7121 7122 hdac_lock(sc); 7123 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7124 codec = sc->codecs[codec_index]; 7125 if (codec == NULL) 7126 continue; 7127 cad = codec->cad; 7128 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7129 devinfo = &codec->fgs[fg_index]; 7130 if (devinfo->node_type != 7131 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7132 continue; 7133 7134 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7135 codec_index, devinfo->nid); 7136 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7137 w = hdac_widget_get(devinfo, i); 7138 if (w == NULL || w->type != 7139 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7140 continue; 7141 hdac_dump_pin_config(w, w->wclass.pin.config); 7142 pincap = w->wclass.pin.cap; 7143 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7144 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7145 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7146 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7147 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7148 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7149 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7150 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7151 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7152 delay = 0; 7153 hdac_command(sc, 7154 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7155 do { 7156 res = hdac_command(sc, 7157 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7158 if (res != 0x7fffffff && res != 0xffffffff) 7159 break; 7160 DELAY(10); 7161 } while (++delay < 10000); 7162 } else { 7163 delay = 0; 7164 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7165 w->nid), cad); 7166 } 7167 printf(" Sense: 0x%08x", res); 7168 if (delay > 0) 7169 printf(" delay %dus", delay * 10); 7170 } 7171 printf("\n"); 7172 } 7173 device_printf(dev, 7174 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7175 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7176 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7177 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7178 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7179 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7180 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7181 device_printf(dev, " GPI:"); 7182 res = hdac_command(sc, 7183 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7184 printf(" data=0x%08x", res); 7185 res = hdac_command(sc, 7186 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7187 cad); 7188 printf(" wake=0x%08x", res); 7189 res = hdac_command(sc, 7190 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7191 cad); 7192 printf(" unsol=0x%08x", res); 7193 res = hdac_command(sc, 7194 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7195 printf(" sticky=0x%08x\n", res); 7196 } 7197 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7198 device_printf(dev, " GPO:"); 7199 res = hdac_command(sc, 7200 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7201 printf(" data=0x%08x\n", res); 7202 } 7203 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7204 device_printf(dev, "GPIO:"); 7205 res = hdac_command(sc, 7206 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7207 printf(" data=0x%08x", res); 7208 res = hdac_command(sc, 7209 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7210 printf(" enable=0x%08x", res); 7211 res = hdac_command(sc, 7212 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7213 printf(" direction=0x%08x\n", res); 7214 res = hdac_command(sc, 7215 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7216 device_printf(dev, " wake=0x%08x", res); 7217 res = hdac_command(sc, 7218 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7219 cad); 7220 printf(" unsol=0x%08x", res); 7221 res = hdac_command(sc, 7222 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7223 printf(" sticky=0x%08x\n", res); 7224 } 7225 } 7226 } 7227 hdac_unlock(sc); 7228 return (0); 7229} 7230#endif 7231 7232static void 7233hdac_attach2(void *arg) 7234{ 7235 struct hdac_codec *codec; 7236 struct hdac_softc *sc; 7237 struct hdac_audio_ctl *ctl; 7238 uint32_t quirks_on, quirks_off; 7239 int codec_index, fg_index; 7240 int i, dmaalloc = 0; 7241 struct hdac_devinfo *devinfo; 7242 7243 sc = (struct hdac_softc *)arg; 7244 7245 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7246 7247 HDA_BOOTHVERBOSE( 7248 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7249 quirks_on, quirks_off); 7250 ); 7251 7252 hdac_lock(sc); 7253 7254 /* Remove ourselves from the config hooks */ 7255 if (sc->intrhook.ich_func != NULL) { 7256 config_intrhook_disestablish(&sc->intrhook); 7257 sc->intrhook.ich_func = NULL; 7258 } 7259 7260 /* Start the corb and rirb engines */ 7261 HDA_BOOTHVERBOSE( 7262 device_printf(sc->dev, "Starting CORB Engine...\n"); 7263 ); 7264 hdac_corb_start(sc); 7265 HDA_BOOTHVERBOSE( 7266 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7267 ); 7268 hdac_rirb_start(sc); 7269 7270 HDA_BOOTHVERBOSE( 7271 device_printf(sc->dev, 7272 "Enabling controller interrupt...\n"); 7273 ); 7274 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7275 HDAC_GCTL_UNSOL); 7276 if (sc->polling == 0) { 7277 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7278 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7279 } else { 7280 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7281 } 7282 DELAY(1000); 7283 7284 HDA_BOOTHVERBOSE( 7285 device_printf(sc->dev, 7286 "Scanning HDA codecs ...\n"); 7287 ); 7288 hdac_scan_codecs(sc); 7289 7290 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7291 codec = sc->codecs[codec_index]; 7292 if (codec == NULL) 7293 continue; 7294 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7295 devinfo = &codec->fgs[fg_index]; 7296 HDA_BOOTVERBOSE( 7297 device_printf(sc->dev, "\n"); 7298 device_printf(sc->dev, 7299 "Processing %s FG cad=%d nid=%d...\n", 7300 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7301 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7302 "unknown", 7303 devinfo->codec->cad, devinfo->nid); 7304 ); 7305 if (devinfo->node_type != 7306 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7307 HDA_BOOTHVERBOSE( 7308 device_printf(sc->dev, 7309 "Powering down...\n"); 7310 ); 7311 hdac_command(sc, 7312 HDA_CMD_SET_POWER_STATE(codec->cad, 7313 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7314 codec->cad); 7315 continue; 7316 } 7317 7318 HDA_BOOTHVERBOSE( 7319 device_printf(sc->dev, "Powering up...\n"); 7320 ); 7321 hdac_powerup(devinfo); 7322 HDA_BOOTHVERBOSE( 7323 device_printf(sc->dev, "Parsing audio FG...\n"); 7324 ); 7325 hdac_audio_parse(devinfo); 7326 HDA_BOOTHVERBOSE( 7327 device_printf(sc->dev, "Parsing Ctls...\n"); 7328 ); 7329 hdac_audio_ctl_parse(devinfo); 7330 HDA_BOOTHVERBOSE( 7331 device_printf(sc->dev, "Parsing vendor patch...\n"); 7332 ); 7333 hdac_vendor_patch_parse(devinfo); 7334 devinfo->function.audio.quirks |= quirks_on; 7335 devinfo->function.audio.quirks &= ~quirks_off; 7336 7337 HDA_BOOTHVERBOSE( 7338 device_printf(sc->dev, "Disabling nonaudio...\n"); 7339 ); 7340 hdac_audio_disable_nonaudio(devinfo); 7341 HDA_BOOTHVERBOSE( 7342 device_printf(sc->dev, "Disabling useless...\n"); 7343 ); 7344 hdac_audio_disable_useless(devinfo); 7345 HDA_BOOTVERBOSE( 7346 device_printf(sc->dev, "Patched pins configuration:\n"); 7347 hdac_dump_pin_configs(devinfo); 7348 ); 7349 HDA_BOOTHVERBOSE( 7350 device_printf(sc->dev, "Parsing pin associations...\n"); 7351 ); 7352 hdac_audio_as_parse(devinfo); 7353 HDA_BOOTHVERBOSE( 7354 device_printf(sc->dev, "Building AFG tree...\n"); 7355 ); 7356 hdac_audio_build_tree(devinfo); 7357 HDA_BOOTHVERBOSE( 7358 device_printf(sc->dev, "Disabling unassociated " 7359 "widgets...\n"); 7360 ); 7361 hdac_audio_disable_unas(devinfo); 7362 HDA_BOOTHVERBOSE( 7363 device_printf(sc->dev, "Disabling nonselected " 7364 "inputs...\n"); 7365 ); 7366 hdac_audio_disable_notselected(devinfo); 7367 HDA_BOOTHVERBOSE( 7368 device_printf(sc->dev, "Disabling useless...\n"); 7369 ); 7370 hdac_audio_disable_useless(devinfo); 7371 HDA_BOOTHVERBOSE( 7372 device_printf(sc->dev, "Disabling " 7373 "crossassociatement connections...\n"); 7374 ); 7375 hdac_audio_disable_crossas(devinfo); 7376 HDA_BOOTHVERBOSE( 7377 device_printf(sc->dev, "Disabling useless...\n"); 7378 ); 7379 hdac_audio_disable_useless(devinfo); 7380 HDA_BOOTHVERBOSE( 7381 device_printf(sc->dev, "Binding associations to channels...\n"); 7382 ); 7383 hdac_audio_bind_as(devinfo); 7384 HDA_BOOTHVERBOSE( 7385 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7386 ); 7387 hdac_audio_assign_names(devinfo); 7388 HDA_BOOTHVERBOSE( 7389 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7390 ); 7391 hdac_audio_assign_mixers(devinfo); 7392 HDA_BOOTHVERBOSE( 7393 device_printf(sc->dev, "Preparing pin controls...\n"); 7394 ); 7395 hdac_audio_prepare_pin_ctrl(devinfo); 7396 HDA_BOOTHVERBOSE( 7397 device_printf(sc->dev, "AFG commit...\n"); 7398 ); 7399 hdac_audio_commit(devinfo); 7400 HDA_BOOTHVERBOSE( 7401 device_printf(sc->dev, "Ctls commit...\n"); 7402 ); 7403 hdac_audio_ctl_commit(devinfo); 7404 HDA_BOOTHVERBOSE( 7405 device_printf(sc->dev, "HP switch init...\n"); 7406 ); 7407 hdac_hp_switch_init(devinfo); 7408 7409 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7410 dmaalloc == 0) { 7411 if (hdac_dma_alloc(sc, &sc->pos_dma, 7412 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7413 HDA_BOOTVERBOSE( 7414 device_printf(sc->dev, "Failed to " 7415 "allocate DMA pos buffer " 7416 "(non-fatal)\n"); 7417 ); 7418 } else 7419 dmaalloc = 1; 7420 } 7421 7422 HDA_BOOTHVERBOSE( 7423 device_printf(sc->dev, "Creating PCM devices...\n"); 7424 ); 7425 hdac_create_pcms(devinfo); 7426 7427 HDA_BOOTVERBOSE( 7428 if (devinfo->function.audio.quirks != 0) { 7429 device_printf(sc->dev, "FG config/quirks:"); 7430 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7431 if ((devinfo->function.audio.quirks & 7432 hdac_quirks_tab[i].value) == 7433 hdac_quirks_tab[i].value) 7434 printf(" %s", hdac_quirks_tab[i].key); 7435 } 7436 printf("\n"); 7437 } 7438 7439 device_printf(sc->dev, "\n"); 7440 device_printf(sc->dev, "+-------------------+\n"); 7441 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7442 device_printf(sc->dev, "+-------------------+\n"); 7443 hdac_dump_nodes(devinfo); 7444 ); 7445 7446 HDA_BOOTHVERBOSE( 7447 device_printf(sc->dev, "\n"); 7448 device_printf(sc->dev, "+------------------------+\n"); 7449 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7450 device_printf(sc->dev, "+------------------------+\n"); 7451 device_printf(sc->dev, "\n"); 7452 i = 0; 7453 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7454 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7455 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7456 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7457 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7458 ctl->index); 7459 if (ctl->childwidget != NULL) 7460 printf(" cnid %3d", ctl->childwidget->nid); 7461 else 7462 printf(" "); 7463 printf(" ossmask=0x%08x\n", 7464 ctl->ossmask); 7465 device_printf(sc->dev, 7466 " mute: %d step: %3d size: %3d off: %3d%s\n", 7467 ctl->mute, ctl->step, ctl->size, ctl->offset, 7468 (ctl->enable == 0) ? " [DISABLED]" : 7469 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7470 } 7471 ); 7472 } 7473 } 7474 hdac_unlock(sc); 7475 7476 HDA_BOOTVERBOSE( 7477 device_printf(sc->dev, "\n"); 7478 ); 7479 7480 bus_generic_attach(sc->dev); 7481 7482#ifdef SND_DYNSYSCTL 7483 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7484 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7485 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7486 sysctl_hdac_polling, "I", "Enable polling mode"); 7487 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7488 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7489 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7490 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7491 "Controller/Jack Sense polling interval (1-1000 ms)"); 7492 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7493 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7494 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7495 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7496#endif 7497} 7498 7499/**************************************************************************** 7500 * int hdac_suspend(device_t) 7501 * 7502 * Suspend and power down HDA bus and codecs. 7503 ****************************************************************************/ 7504static int 7505hdac_suspend(device_t dev) 7506{ 7507 struct hdac_softc *sc; 7508 struct hdac_codec *codec; 7509 struct hdac_devinfo *devinfo; 7510 int codec_index, fg_index, i; 7511 7512 HDA_BOOTHVERBOSE( 7513 device_printf(dev, "Suspend...\n"); 7514 ); 7515 7516 sc = device_get_softc(dev); 7517 hdac_lock(sc); 7518 7519 HDA_BOOTHVERBOSE( 7520 device_printf(dev, "Stop streams...\n"); 7521 ); 7522 for (i = 0; i < sc->num_chans; i++) { 7523 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7524 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7525 hdac_channel_stop(sc, &sc->chans[i]); 7526 } 7527 } 7528 7529 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7530 codec = sc->codecs[codec_index]; 7531 if (codec == NULL) 7532 continue; 7533 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7534 devinfo = &codec->fgs[fg_index]; 7535 HDA_BOOTHVERBOSE( 7536 device_printf(dev, 7537 "Power down FG" 7538 " cad=%d nid=%d to the D3 state...\n", 7539 codec->cad, devinfo->nid); 7540 ); 7541 hdac_command(sc, 7542 HDA_CMD_SET_POWER_STATE(codec->cad, 7543 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7544 codec->cad); 7545 } 7546 } 7547 7548 HDA_BOOTHVERBOSE( 7549 device_printf(dev, "Reset controller...\n"); 7550 ); 7551 callout_stop(&sc->poll_hda); 7552 callout_stop(&sc->poll_hdac); 7553 callout_stop(&sc->poll_jack); 7554 hdac_reset(sc, 0); 7555 hdac_unlock(sc); 7556 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7557 callout_drain(&sc->poll_hda); 7558 callout_drain(&sc->poll_hdac); 7559 callout_drain(&sc->poll_jack); 7560 7561 HDA_BOOTHVERBOSE( 7562 device_printf(dev, "Suspend done\n"); 7563 ); 7564 7565 return (0); 7566} 7567 7568/**************************************************************************** 7569 * int hdac_resume(device_t) 7570 * 7571 * Powerup and restore HDA bus and codecs state. 7572 ****************************************************************************/ 7573static int 7574hdac_resume(device_t dev) 7575{ 7576 struct hdac_softc *sc; 7577 struct hdac_codec *codec; 7578 struct hdac_devinfo *devinfo; 7579 int codec_index, fg_index, i; 7580 7581 HDA_BOOTHVERBOSE( 7582 device_printf(dev, "Resume...\n"); 7583 ); 7584 7585 sc = device_get_softc(dev); 7586 hdac_lock(sc); 7587 7588 /* Quiesce everything */ 7589 HDA_BOOTHVERBOSE( 7590 device_printf(dev, "Reset controller...\n"); 7591 ); 7592 hdac_reset(sc, 1); 7593 7594 /* Initialize the CORB and RIRB */ 7595 hdac_corb_init(sc); 7596 hdac_rirb_init(sc); 7597 7598 /* Start the corb and rirb engines */ 7599 HDA_BOOTHVERBOSE( 7600 device_printf(dev, "Starting CORB Engine...\n"); 7601 ); 7602 hdac_corb_start(sc); 7603 HDA_BOOTHVERBOSE( 7604 device_printf(dev, "Starting RIRB Engine...\n"); 7605 ); 7606 hdac_rirb_start(sc); 7607 7608 HDA_BOOTHVERBOSE( 7609 device_printf(dev, 7610 "Enabling controller interrupt...\n"); 7611 ); 7612 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7613 HDAC_GCTL_UNSOL); 7614 if (sc->polling == 0) { 7615 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7616 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7617 } else { 7618 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7619 } 7620 DELAY(1000); 7621 7622 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7623 codec = sc->codecs[codec_index]; 7624 if (codec == NULL) 7625 continue; 7626 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7627 devinfo = &codec->fgs[fg_index]; 7628 if (devinfo->node_type != 7629 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7630 HDA_BOOTHVERBOSE( 7631 device_printf(dev, 7632 "Power down unsupported non-audio FG" 7633 " cad=%d nid=%d to the D3 state...\n", 7634 codec->cad, devinfo->nid); 7635 ); 7636 hdac_command(sc, 7637 HDA_CMD_SET_POWER_STATE(codec->cad, 7638 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7639 codec->cad); 7640 continue; 7641 } 7642 7643 HDA_BOOTHVERBOSE( 7644 device_printf(dev, 7645 "Power up audio FG cad=%d nid=%d...\n", 7646 devinfo->codec->cad, devinfo->nid); 7647 ); 7648 hdac_powerup(devinfo); 7649 HDA_BOOTHVERBOSE( 7650 device_printf(dev, "AFG commit...\n"); 7651 ); 7652 hdac_audio_commit(devinfo); 7653 HDA_BOOTHVERBOSE( 7654 device_printf(dev, "Ctls commit...\n"); 7655 ); 7656 hdac_audio_ctl_commit(devinfo); 7657 HDA_BOOTHVERBOSE( 7658 device_printf(dev, "HP switch init...\n"); 7659 ); 7660 hdac_hp_switch_init(devinfo); 7661 7662 hdac_unlock(sc); 7663 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7664 struct hdac_pcm_devinfo *pdevinfo = 7665 &devinfo->function.audio.devs[i]; 7666 HDA_BOOTHVERBOSE( 7667 device_printf(pdevinfo->dev, 7668 "OSS mixer reinitialization...\n"); 7669 ); 7670 if (mixer_reinit(pdevinfo->dev) == -1) 7671 device_printf(pdevinfo->dev, 7672 "unable to reinitialize the mixer\n"); 7673 } 7674 hdac_lock(sc); 7675 } 7676 } 7677 7678 HDA_BOOTHVERBOSE( 7679 device_printf(dev, "Start streams...\n"); 7680 ); 7681 for (i = 0; i < sc->num_chans; i++) { 7682 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7683 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7684 hdac_channel_start(sc, &sc->chans[i]); 7685 } 7686 } 7687 7688 hdac_unlock(sc); 7689 7690 HDA_BOOTHVERBOSE( 7691 device_printf(dev, "Resume done\n"); 7692 ); 7693 7694 return (0); 7695} 7696/**************************************************************************** 7697 * int hdac_detach(device_t) 7698 * 7699 * Detach and free up resources utilized by the hdac device. 7700 ****************************************************************************/ 7701static int 7702hdac_detach(device_t dev) 7703{ 7704 struct hdac_softc *sc; 7705 device_t *devlist; 7706 int i, devcount, error; 7707 7708 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7709 return (error); 7710 for (i = 0; i < devcount; i++) { 7711 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7712 free(devlist, M_TEMP); 7713 return (error); 7714 } 7715 } 7716 free(devlist, M_TEMP); 7717 7718 sc = device_get_softc(dev); 7719 hdac_release_resources(sc); 7720 7721 return (0); 7722} 7723 7724static int 7725hdac_print_child(device_t dev, device_t child) 7726{ 7727 struct hdac_pcm_devinfo *pdevinfo = 7728 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7729 int retval; 7730 7731 retval = bus_print_child_header(dev, child); 7732 retval += printf(" at cad %d nid %d", 7733 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7734 retval += bus_print_child_footer(dev, child); 7735 7736 return (retval); 7737} 7738 7739static device_method_t hdac_methods[] = { 7740 /* device interface */ 7741 DEVMETHOD(device_probe, hdac_probe), 7742 DEVMETHOD(device_attach, hdac_attach), 7743 DEVMETHOD(device_detach, hdac_detach), 7744 DEVMETHOD(device_suspend, hdac_suspend), 7745 DEVMETHOD(device_resume, hdac_resume), 7746 /* Bus interface */ 7747 DEVMETHOD(bus_print_child, hdac_print_child), 7748 { 0, 0 } 7749}; 7750 7751static driver_t hdac_driver = { 7752 "hdac", 7753 hdac_methods, 7754 sizeof(struct hdac_softc), 7755}; 7756 7757static devclass_t hdac_devclass; 7758 7759DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7760MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7761MODULE_VERSION(snd_hda, 1); 7762 7763static int 7764hdac_pcm_probe(device_t dev) 7765{ 7766 struct hdac_pcm_devinfo *pdevinfo = 7767 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7768 char buf[128]; 7769 7770 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7771 hdac_codec_name(pdevinfo->devinfo->codec), 7772 pdevinfo->index, 7773 pdevinfo->digital?"Digital":"Analog"); 7774 device_set_desc_copy(dev, buf); 7775 return (0); 7776} 7777 7778static int 7779hdac_pcm_attach(device_t dev) 7780{ 7781 struct hdac_pcm_devinfo *pdevinfo = 7782 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7783 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7784 char status[SND_STATUSLEN]; 7785 int i; 7786 7787 pdevinfo->chan_size = pcm_getbuffersize(dev, 7788 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7789 7790 HDA_BOOTVERBOSE( 7791 device_printf(dev, "+--------------------------------------+\n"); 7792 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7793 device_printf(dev, "+--------------------------------------+\n"); 7794 hdac_dump_pcmchannels(pdevinfo); 7795 device_printf(dev, "\n"); 7796 device_printf(dev, "+--------------------------------+\n"); 7797 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7798 device_printf(dev, "+--------------------------------+\n"); 7799 hdac_dump_dac(pdevinfo); 7800 hdac_dump_adc(pdevinfo); 7801 hdac_dump_mix(pdevinfo); 7802 device_printf(dev, "\n"); 7803 device_printf(dev, "+-------------------------+\n"); 7804 device_printf(dev, "| DUMPING Volume Controls |\n"); 7805 device_printf(dev, "+-------------------------+\n"); 7806 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7807 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7808 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7809 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7810 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7811 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7812 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7813 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7814 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7815 hdac_dump_ctls(pdevinfo, NULL, 0); 7816 device_printf(dev, "\n"); 7817 ); 7818 7819 if (resource_int_value(device_get_name(dev), 7820 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7821 i &= HDA_BLK_ALIGN; 7822 if (i < HDA_BLK_MIN) 7823 i = HDA_BLK_MIN; 7824 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7825 i = 0; 7826 while (pdevinfo->chan_blkcnt >> i) 7827 i++; 7828 pdevinfo->chan_blkcnt = 1 << (i - 1); 7829 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7830 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7831 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7832 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7833 } else 7834 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7835 7836 /* 7837 * We don't register interrupt handler with snd_setup_intr 7838 * in pcm device. Mark pcm device as MPSAFE manually. 7839 */ 7840 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7841 7842 HDA_BOOTHVERBOSE( 7843 device_printf(dev, "OSS mixer initialization...\n"); 7844 ); 7845 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7846 device_printf(dev, "Can't register mixer\n"); 7847 7848 HDA_BOOTHVERBOSE( 7849 device_printf(dev, "Registering PCM channels...\n"); 7850 ); 7851 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7852 (pdevinfo->rec >= 0)?1:0) != 0) 7853 device_printf(dev, "Can't register PCM\n"); 7854 7855 pdevinfo->registered++; 7856 7857 if (pdevinfo->play >= 0) 7858 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7859 if (pdevinfo->rec >= 0) 7860 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7861 7862 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7863 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7864 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7865 pcm_setstatus(dev, status); 7866 7867 return (0); 7868} 7869 7870static int 7871hdac_pcm_detach(device_t dev) 7872{ 7873 struct hdac_pcm_devinfo *pdevinfo = 7874 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7875 int err; 7876 7877 if (pdevinfo->registered > 0) { 7878 err = pcm_unregister(dev); 7879 if (err != 0) 7880 return (err); 7881 } 7882 7883 return (0); 7884} 7885 7886static device_method_t hdac_pcm_methods[] = { 7887 /* device interface */ 7888 DEVMETHOD(device_probe, hdac_pcm_probe), 7889 DEVMETHOD(device_attach, hdac_pcm_attach), 7890 DEVMETHOD(device_detach, hdac_pcm_detach), 7891 { 0, 0 } 7892}; 7893 7894static driver_t hdac_pcm_driver = { 7895 "pcm", 7896 hdac_pcm_methods, 7897 PCM_SOFTC_SIZE, 7898}; 7899 7900DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7901 7902