hdac.c revision 186503
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20081226_0122" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 186503 2008-12-26 22:47:11Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 166 167/* ATI */ 168#define ATI_VENDORID 0x1002 169#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 170#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 171#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 172 173/* VIA */ 174#define VIA_VENDORID 0x1106 175#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 176#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 177 178/* SiS */ 179#define SIS_VENDORID 0x1039 180#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 181#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 182 183/* ULI */ 184#define ULI_VENDORID 0x10b9 185#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 186#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 187 188/* OEM/subvendors */ 189 190/* Intel */ 191#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 192 193/* HP/Compaq */ 194#define HP_VENDORID 0x103c 195#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 196#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 197#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 198#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 199#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 200#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 201#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 202#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 203#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 204#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 205/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 206#define HP_NX6325_SUBVENDORX 0x103c30b0 207 208/* Dell */ 209#define DELL_VENDORID 0x1028 210#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 211#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 212#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 213#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 214#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 215#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 216#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 217#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 218 219/* Clevo */ 220#define CLEVO_VENDORID 0x1558 221#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 222#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 223 224/* Acer */ 225#define ACER_VENDORID 0x1025 226#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 227#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 228#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 229#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 230#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 231#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 232#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 233 234/* Asus */ 235#define ASUS_VENDORID 0x1043 236#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 237#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 238#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 239#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 240#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 241#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 242#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 243#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 244#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 245#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 246#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 247#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 248#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 249#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 250#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 251#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 252 253/* IBM / Lenovo */ 254#define IBM_VENDORID 0x1014 255#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 256#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 257 258/* Lenovo */ 259#define LENOVO_VENDORID 0x17aa 260#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 261#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 262#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 263#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 264 265/* Samsung */ 266#define SAMSUNG_VENDORID 0x144d 267#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 268#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 269 270/* Medion ? */ 271#define MEDION_VENDORID 0x161f 272#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 273#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 274 275/* Apple Computer Inc. */ 276#define APPLE_VENDORID 0x106b 277#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 278 279/* Sony */ 280#define SONY_VENDORID 0x104d 281#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 282#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 283 284/* 285 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 286 * instead of their own, which is beyond my comprehension 287 * (see HDA_CODEC_STAC9221 below). 288 */ 289#define APPLE_INTEL_MAC 0x76808384 290 291/* LG Electronics */ 292#define LG_VENDORID 0x1854 293#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 294#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 295 296/* Fujitsu Siemens */ 297#define FS_VENDORID 0x1734 298#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 299#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 300#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 301 302/* Fujitsu Limited */ 303#define FL_VENDORID 0x10cf 304#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 305#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 306#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 307 308/* Toshiba */ 309#define TOSHIBA_VENDORID 0x1179 310#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 311#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 312#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 313 314/* Micro-Star International (MSI) */ 315#define MSI_VENDORID 0x1462 316#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 317#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 318#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 319 320/* Giga-Byte Technology */ 321#define GB_VENDORID 0x1458 322#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 323#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 324 325/* Uniwill ? */ 326#define UNIWILL_VENDORID 0x1584 327#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 328#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 329 330 331/* Misc constants.. */ 332#define HDA_AMP_VOL_DEFAULT (-1) 333#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 334#define HDA_AMP_MUTE_NONE (0) 335#define HDA_AMP_MUTE_LEFT (1 << 0) 336#define HDA_AMP_MUTE_RIGHT (1 << 1) 337#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 338 339#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 340#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 341 342#define HDA_ADC_MONITOR (1 << 0) 343 344#define HDA_CTL_OUT 1 345#define HDA_CTL_IN 2 346 347#define HDA_GPIO_MAX 8 348/* 0 - 7 = GPIO , 8 = Flush */ 349#define HDA_QUIRK_GPIO0 (1 << 0) 350#define HDA_QUIRK_GPIO1 (1 << 1) 351#define HDA_QUIRK_GPIO2 (1 << 2) 352#define HDA_QUIRK_GPIO3 (1 << 3) 353#define HDA_QUIRK_GPIO4 (1 << 4) 354#define HDA_QUIRK_GPIO5 (1 << 5) 355#define HDA_QUIRK_GPIO6 (1 << 6) 356#define HDA_QUIRK_GPIO7 (1 << 7) 357#define HDA_QUIRK_GPIOFLUSH (1 << 8) 358 359/* 9 - 25 = anything else */ 360#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 361#define HDA_QUIRK_FIXEDRATE (1 << 10) 362#define HDA_QUIRK_FORCESTEREO (1 << 11) 363#define HDA_QUIRK_EAPDINV (1 << 12) 364#define HDA_QUIRK_DMAPOS (1 << 13) 365#define HDA_QUIRK_SENSEINV (1 << 14) 366 367/* 26 - 31 = vrefs */ 368#define HDA_QUIRK_IVREF50 (1 << 26) 369#define HDA_QUIRK_IVREF80 (1 << 27) 370#define HDA_QUIRK_IVREF100 (1 << 28) 371#define HDA_QUIRK_OVREF50 (1 << 29) 372#define HDA_QUIRK_OVREF80 (1 << 30) 373#define HDA_QUIRK_OVREF100 (1 << 31) 374 375#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 376 HDA_QUIRK_IVREF100) 377#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 378 HDA_QUIRK_OVREF100) 379#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 380 381#if __FreeBSD_version < 600000 382#define taskqueue_drain(...) 383#endif 384 385static const struct { 386 char *key; 387 uint32_t value; 388} hdac_quirks_tab[] = { 389 { "gpio0", HDA_QUIRK_GPIO0 }, 390 { "gpio1", HDA_QUIRK_GPIO1 }, 391 { "gpio2", HDA_QUIRK_GPIO2 }, 392 { "gpio3", HDA_QUIRK_GPIO3 }, 393 { "gpio4", HDA_QUIRK_GPIO4 }, 394 { "gpio5", HDA_QUIRK_GPIO5 }, 395 { "gpio6", HDA_QUIRK_GPIO6 }, 396 { "gpio7", HDA_QUIRK_GPIO7 }, 397 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 398 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 399 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 400 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 401 { "eapdinv", HDA_QUIRK_EAPDINV }, 402 { "dmapos", HDA_QUIRK_DMAPOS }, 403 { "senseinv", HDA_QUIRK_SENSEINV }, 404 { "ivref50", HDA_QUIRK_IVREF50 }, 405 { "ivref80", HDA_QUIRK_IVREF80 }, 406 { "ivref100", HDA_QUIRK_IVREF100 }, 407 { "ovref50", HDA_QUIRK_OVREF50 }, 408 { "ovref80", HDA_QUIRK_OVREF80 }, 409 { "ovref100", HDA_QUIRK_OVREF100 }, 410 { "ivref", HDA_QUIRK_IVREF }, 411 { "ovref", HDA_QUIRK_OVREF }, 412 { "vref", HDA_QUIRK_VREF }, 413}; 414#define HDAC_QUIRKS_TAB_LEN \ 415 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 416 417#define HDA_BDL_MIN 2 418#define HDA_BDL_MAX 256 419#define HDA_BDL_DEFAULT HDA_BDL_MIN 420 421#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 422#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 423 424#define HDA_BUFSZ_MIN 4096 425#define HDA_BUFSZ_MAX 65536 426#define HDA_BUFSZ_DEFAULT 16384 427 428#define HDA_PARSE_MAXDEPTH 10 429 430#define HDAC_UNSOLTAG_EVENT_HP 0x00 431 432MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 433 434const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 435 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 436 "White", "Other"}; 437 438const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 439 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 440 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 441 442const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 443 444/* Default */ 445static uint32_t hdac_fmt[] = { 446 AFMT_STEREO | AFMT_S16_LE, 447 0 448}; 449 450static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 451 452static const struct { 453 uint32_t model; 454 char *desc; 455} hdac_devices[] = { 456 { HDA_INTEL_82801F, "Intel 82801F" }, 457 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 458 { HDA_INTEL_82801G, "Intel 82801G" }, 459 { HDA_INTEL_82801H, "Intel 82801H" }, 460 { HDA_INTEL_82801I, "Intel 82801I" }, 461 { HDA_INTEL_82801J, "Intel 82801J" }, 462 { HDA_INTEL_SCH, "Intel SCH" }, 463 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 464 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 465 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 466 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 467 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 468 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 469 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 470 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 471 { HDA_ATI_SB450, "ATI SB450" }, 472 { HDA_ATI_SB600, "ATI SB600" }, 473 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 474 { HDA_SIS_966, "SiS 966" }, 475 { HDA_ULI_M5461, "ULI M5461" }, 476 /* Unknown */ 477 { HDA_INTEL_ALL, "Intel (Unknown)" }, 478 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 479 { HDA_ATI_ALL, "ATI (Unknown)" }, 480 { HDA_VIA_ALL, "VIA (Unknown)" }, 481 { HDA_SIS_ALL, "SiS (Unknown)" }, 482 { HDA_ULI_ALL, "ULI (Unknown)" }, 483}; 484#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 485 486static const struct { 487 uint16_t vendor; 488 uint8_t reg; 489 uint8_t mask; 490 uint8_t enable; 491} hdac_pcie_snoop[] = { 492 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 493 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 494 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 495}; 496#define HDAC_PCIESNOOP_LEN \ 497 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 498 499static const struct { 500 uint32_t rate; 501 int valid; 502 uint16_t base; 503 uint16_t mul; 504 uint16_t div; 505} hda_rate_tab[] = { 506 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 507 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 508 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 509 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 510 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 511 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 512 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 513 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 514 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 515 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 516 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 517 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 518 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 519 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 520 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 521 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 522 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 523 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 524 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 525 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 526 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 527 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 528 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 529 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 530 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 531 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 532 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 533 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 534 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 535 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 536 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 537 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 538 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 539 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 540 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 541}; 542#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 543 544/* All codecs you can eat... */ 545#define HDA_CODEC_CONSTRUCT(vendor, id) \ 546 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 547 548/* Realtek */ 549#define REALTEK_VENDORID 0x10ec 550#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 551#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 552#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 553#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 554#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 555#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 556#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 557#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 558#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 559#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 560#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 561#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 562#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 563#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 564#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 565#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 566#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 567#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 568 569/* Analog Devices */ 570#define ANALOGDEVICES_VENDORID 0x11d4 571#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 572#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 573#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 574#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 575#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 576#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 577#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 578#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 579#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 580#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 581#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 582#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 583#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 584#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 585#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 586#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 587 588/* CMedia */ 589#define CMEDIA_VENDORID 0x434d 590#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 591#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 592 593/* Sigmatel */ 594#define SIGMATEL_VENDORID 0x8384 595#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 596#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 597#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 598#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 599#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 600#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 601#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 602#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 603#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 604#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 605#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 606#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 607#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 608#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 609#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 610#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 611#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 612#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 613#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 614#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 615#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 616#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 617#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 618#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 619#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 620#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 621#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 622#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 623#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 624#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 625#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 626#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 627#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 628#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 629#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 630#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 631#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 632#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 633#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 634#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 635 636/* IDT */ 637#define IDT_VENDORID 0x111d 638#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 639#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 640#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 641#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 642#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 643#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 644#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 645#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 646#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 647#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 648#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 649#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 650#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 651 652/* Silicon Image */ 653#define SII_VENDORID 0x1095 654#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 655#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 656 657/* Lucent/Agere */ 658#define AGERE_VENDORID 0x11c1 659#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 660 661/* Conexant */ 662#define CONEXANT_VENDORID 0x14f1 663#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 664#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 665#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 666#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 667 668/* VIA */ 669#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 670#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 671#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 672#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 673#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 674#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 675#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 676#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 677#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 678#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 679#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 680#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 681#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 682#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 683#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 684#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 685#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 686#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 687#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 688#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 689#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 690 691/* ATI */ 692#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 693#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 694#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 695#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 696#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 697 698/* NVIDIA */ 699#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 700 701/* INTEL */ 702#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 703 704/* Codecs */ 705static const struct { 706 uint32_t id; 707 char *name; 708} hdac_codecs[] = { 709 { HDA_CODEC_ALC260, "Realtek ALC260" }, 710 { HDA_CODEC_ALC262, "Realtek ALC262" }, 711 { HDA_CODEC_ALC267, "Realtek ALC267" }, 712 { HDA_CODEC_ALC268, "Realtek ALC268" }, 713 { HDA_CODEC_ALC269, "Realtek ALC269" }, 714 { HDA_CODEC_ALC272, "Realtek ALC272" }, 715 { HDA_CODEC_ALC660, "Realtek ALC660" }, 716 { HDA_CODEC_ALC662, "Realtek ALC662" }, 717 { HDA_CODEC_ALC663, "Realtek ALC663" }, 718 { HDA_CODEC_ALC861, "Realtek ALC861" }, 719 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 720 { HDA_CODEC_ALC880, "Realtek ALC880" }, 721 { HDA_CODEC_ALC882, "Realtek ALC882" }, 722 { HDA_CODEC_ALC883, "Realtek ALC883" }, 723 { HDA_CODEC_ALC885, "Realtek ALC885" }, 724 { HDA_CODEC_ALC888, "Realtek ALC888" }, 725 { HDA_CODEC_ALC889, "Realtek ALC889" }, 726 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 727 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 728 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 729 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 730 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 731 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 732 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 733 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 734 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 735 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 736 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 737 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 738 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 739 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 740 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 741 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 742 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 743 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 744 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 745 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 746 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 747 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 748 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 749 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 750 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 751 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 752 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 753 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 754 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 755 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 756 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 757 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 758 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 759 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 760 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 761 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 762 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 763 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 764 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 765 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 766 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 767 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 768 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 769 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 770 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 771 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 772 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 773 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 774 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 775 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 776 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 777 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 778 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 779 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 780 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 781 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 782 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 783 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 784 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 785 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 786 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 787 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 788 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 789 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 790 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 791 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 792 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 793 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 794 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 795 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 796 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 797 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 798 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 799 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 800 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 801 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 802 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 803 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 804 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 805 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 806 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 807 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 808 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 809 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 810 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 811 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 812 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 813 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 814 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 815 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 816 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 817 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 818 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 819 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 820 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 821 /* Unknown codec */ 822 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 823 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 824 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 825 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 826 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 827 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 828 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 829 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 830 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 831 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 832 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 833 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 834}; 835#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 836 837 838/**************************************************************************** 839 * Function prototypes 840 ****************************************************************************/ 841static void hdac_intr_handler(void *); 842static int hdac_reset(struct hdac_softc *, int); 843static int hdac_get_capabilities(struct hdac_softc *); 844static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 845static int hdac_dma_alloc(struct hdac_softc *, 846 struct hdac_dma *, bus_size_t); 847static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 848static int hdac_mem_alloc(struct hdac_softc *); 849static void hdac_mem_free(struct hdac_softc *); 850static int hdac_irq_alloc(struct hdac_softc *); 851static void hdac_irq_free(struct hdac_softc *); 852static void hdac_corb_init(struct hdac_softc *); 853static void hdac_rirb_init(struct hdac_softc *); 854static void hdac_corb_start(struct hdac_softc *); 855static void hdac_rirb_start(struct hdac_softc *); 856static void hdac_scan_codecs(struct hdac_softc *); 857static void hdac_probe_codec(struct hdac_codec *); 858static void hdac_probe_function(struct hdac_codec *, nid_t); 859static int hdac_pcmchannel_setup(struct hdac_chan *); 860 861static void hdac_attach2(void *); 862 863static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 864 uint32_t, int); 865static void hdac_command_send_internal(struct hdac_softc *, 866 struct hdac_command_list *, int); 867 868static int hdac_probe(device_t); 869static int hdac_attach(device_t); 870static int hdac_detach(device_t); 871static int hdac_suspend(device_t); 872static int hdac_resume(device_t); 873static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 874static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 875 uint32_t, int, int); 876static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 877 nid_t, int, int, int); 878static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 879 nid_t, nid_t, int, int, int, int, int, int); 880static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 881 882static int hdac_rirb_flush(struct hdac_softc *sc); 883static int hdac_unsolq_flush(struct hdac_softc *sc); 884 885static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 886 887#define hdac_command(a1, a2, a3) \ 888 hdac_command_sendone_internal(a1, a2, a3) 889 890#define hdac_codec_id(c) \ 891 ((uint32_t)((c == NULL) ? 0x00000000 : \ 892 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 893 ((uint32_t)(c)->device_id & 0x0000ffff)))) 894 895static char * 896hdac_codec_name(struct hdac_codec *codec) 897{ 898 uint32_t id; 899 int i; 900 901 id = hdac_codec_id(codec); 902 903 for (i = 0; i < HDAC_CODECS_LEN; i++) { 904 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 905 return (hdac_codecs[i].name); 906 } 907 908 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 909} 910 911static char * 912hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 913{ 914 static char *ossname[] = SOUND_DEVICE_NAMES; 915 int i, first = 1; 916 917 bzero(buf, len); 918 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 919 if (mask & (1 << i)) { 920 if (first == 0) 921 strlcat(buf, ", ", len); 922 strlcat(buf, ossname[i], len); 923 first = 0; 924 } 925 } 926 return (buf); 927} 928 929static struct hdac_audio_ctl * 930hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 931{ 932 if (devinfo == NULL || 933 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 934 index == NULL || devinfo->function.audio.ctl == NULL || 935 devinfo->function.audio.ctlcnt < 1 || 936 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 937 return (NULL); 938 return (&devinfo->function.audio.ctl[(*index)++]); 939} 940 941static struct hdac_audio_ctl * 942hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 943 int index, int cnt) 944{ 945 struct hdac_audio_ctl *ctl; 946 int i, found = 0; 947 948 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 949 return (NULL); 950 951 i = 0; 952 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 953 if (ctl->enable == 0) 954 continue; 955 if (ctl->widget->nid != nid) 956 continue; 957 if (dir && ctl->ndir != dir) 958 continue; 959 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 960 ctl->dir == ctl->ndir && ctl->index != index) 961 continue; 962 found++; 963 if (found == cnt || cnt <= 0) 964 return (ctl); 965 } 966 967 return (NULL); 968} 969 970/* 971 * Jack detection (Speaker/HP redirection) event handler. 972 */ 973static void 974hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 975{ 976 struct hdac_audio_as *as; 977 struct hdac_softc *sc; 978 struct hdac_widget *w; 979 struct hdac_audio_ctl *ctl; 980 uint32_t val, res; 981 int i, j; 982 nid_t cad; 983 984 if (devinfo == NULL || devinfo->codec == NULL || 985 devinfo->codec->sc == NULL) 986 return; 987 988 sc = devinfo->codec->sc; 989 cad = devinfo->codec->cad; 990 as = devinfo->function.audio.as; 991 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 992 if (as[i].hpredir < 0) 993 continue; 994 995 w = hdac_widget_get(devinfo, as[i].pins[15]); 996 if (w == NULL || w->enable == 0 || w->type != 997 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 998 continue; 999 1000 res = hdac_command(sc, 1001 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1002 1003 HDA_BOOTVERBOSE( 1004 device_printf(sc->dev, 1005 "Pin sense: nid=%d res=0x%08x\n", 1006 as[i].pins[15], res); 1007 ); 1008 1009 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1010 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1011 res ^= 1; 1012 1013 /* (Un)Mute headphone pin. */ 1014 ctl = hdac_audio_ctl_amp_get(devinfo, 1015 as[i].pins[15], HDA_CTL_IN, -1, 1); 1016 if (ctl != NULL && ctl->mute) { 1017 /* If pin has muter - use it. */ 1018 val = (res != 0) ? 0 : 1; 1019 if (val != ctl->forcemute) { 1020 ctl->forcemute = val; 1021 hdac_audio_ctl_amp_set(ctl, 1022 HDA_AMP_MUTE_DEFAULT, 1023 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1024 } 1025 } else { 1026 /* If there is no muter - disable pin output. */ 1027 w = hdac_widget_get(devinfo, as[i].pins[15]); 1028 if (w != NULL && w->type == 1029 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1030 if (res != 0) 1031 val = w->wclass.pin.ctrl | 1032 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1033 else 1034 val = w->wclass.pin.ctrl & 1035 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1036 if (val != w->wclass.pin.ctrl) { 1037 w->wclass.pin.ctrl = val; 1038 hdac_command(sc, 1039 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1040 w->nid, w->wclass.pin.ctrl), cad); 1041 } 1042 } 1043 } 1044 /* (Un)Mute other pins. */ 1045 for (j = 0; j < 15; j++) { 1046 if (as[i].pins[j] <= 0) 1047 continue; 1048 ctl = hdac_audio_ctl_amp_get(devinfo, 1049 as[i].pins[j], HDA_CTL_IN, -1, 1); 1050 if (ctl != NULL && ctl->mute) { 1051 /* If pin has muter - use it. */ 1052 val = (res != 0) ? 1 : 0; 1053 if (val == ctl->forcemute) 1054 continue; 1055 ctl->forcemute = val; 1056 hdac_audio_ctl_amp_set(ctl, 1057 HDA_AMP_MUTE_DEFAULT, 1058 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1059 continue; 1060 } 1061 /* If there is no muter - disable pin output. */ 1062 w = hdac_widget_get(devinfo, as[i].pins[j]); 1063 if (w != NULL && w->type == 1064 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1065 if (res != 0) 1066 val = w->wclass.pin.ctrl & 1067 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1068 else 1069 val = w->wclass.pin.ctrl | 1070 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1071 if (val != w->wclass.pin.ctrl) { 1072 w->wclass.pin.ctrl = val; 1073 hdac_command(sc, 1074 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1075 w->nid, w->wclass.pin.ctrl), cad); 1076 } 1077 } 1078 } 1079 } 1080} 1081 1082/* 1083 * Callback for poll based jack detection. 1084 */ 1085static void 1086hdac_jack_poll_callback(void *arg) 1087{ 1088 struct hdac_devinfo *devinfo = arg; 1089 struct hdac_softc *sc; 1090 1091 if (devinfo == NULL || devinfo->codec == NULL || 1092 devinfo->codec->sc == NULL) 1093 return; 1094 sc = devinfo->codec->sc; 1095 hdac_lock(sc); 1096 if (sc->poll_ival == 0) { 1097 hdac_unlock(sc); 1098 return; 1099 } 1100 hdac_hp_switch_handler(devinfo); 1101 callout_reset(&sc->poll_jack, sc->poll_ival, 1102 hdac_jack_poll_callback, devinfo); 1103 hdac_unlock(sc); 1104} 1105 1106/* 1107 * Jack detection initializer. 1108 */ 1109static void 1110hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1111{ 1112 struct hdac_softc *sc = devinfo->codec->sc; 1113 struct hdac_audio_as *as = devinfo->function.audio.as; 1114 struct hdac_widget *w; 1115 uint32_t id; 1116 int i, enable = 0, poll = 0; 1117 nid_t cad; 1118 1119 id = hdac_codec_id(devinfo->codec); 1120 cad = devinfo->codec->cad; 1121 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1122 if (as[i].hpredir < 0) 1123 continue; 1124 1125 w = hdac_widget_get(devinfo, as[i].pins[15]); 1126 if (w == NULL || w->enable == 0 || w->type != 1127 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1128 continue; 1129 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1130 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1131 device_printf(sc->dev, 1132 "No jack detection support at pin %d\n", 1133 as[i].pins[15]); 1134 continue; 1135 } 1136 enable = 1; 1137 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1138 hdac_command(sc, 1139 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1140 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1141 HDAC_UNSOLTAG_EVENT_HP), cad); 1142 } else 1143 poll = 1; 1144 HDA_BOOTVERBOSE( 1145 device_printf(sc->dev, 1146 "Enabling headphone/speaker " 1147 "audio routing switching:\n"); 1148 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1149 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1150 ); 1151 } 1152 if (enable) { 1153 hdac_hp_switch_handler(devinfo); 1154 if (poll) { 1155 callout_reset(&sc->poll_jack, 1, 1156 hdac_jack_poll_callback, devinfo); 1157 } 1158 } 1159} 1160 1161/* 1162 * Unsolicited messages handler. 1163 */ 1164static void 1165hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1166{ 1167 struct hdac_softc *sc; 1168 struct hdac_devinfo *devinfo = NULL; 1169 int i; 1170 1171 if (codec == NULL || codec->sc == NULL) 1172 return; 1173 1174 sc = codec->sc; 1175 1176 HDA_BOOTVERBOSE( 1177 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1178 ); 1179 1180 for (i = 0; i < codec->num_fgs; i++) { 1181 if (codec->fgs[i].node_type == 1182 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1183 devinfo = &codec->fgs[i]; 1184 break; 1185 } 1186 } 1187 1188 if (devinfo == NULL) 1189 return; 1190 1191 switch (tag) { 1192 case HDAC_UNSOLTAG_EVENT_HP: 1193 hdac_hp_switch_handler(devinfo); 1194 break; 1195 default: 1196 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1197 break; 1198 } 1199} 1200 1201static int 1202hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1203{ 1204 /* XXX to be removed */ 1205#ifdef HDAC_INTR_EXTRA 1206 uint32_t res; 1207#endif 1208 1209 if (!(ch->flags & HDAC_CHN_RUNNING)) 1210 return (0); 1211 1212 /* XXX to be removed */ 1213#ifdef HDAC_INTR_EXTRA 1214 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1215#endif 1216 1217 /* XXX to be removed */ 1218#ifdef HDAC_INTR_EXTRA 1219 HDA_BOOTVERBOSE( 1220 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1221 device_printf(ch->pdevinfo->dev, 1222 "PCMDIR_%s intr triggered beyond stream boundary:" 1223 "%08x\n", 1224 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1225 ); 1226#endif 1227 1228 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1229 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1230 1231 /* XXX to be removed */ 1232#ifdef HDAC_INTR_EXTRA 1233 if (res & HDAC_SDSTS_BCIS) { 1234#endif 1235 return (1); 1236 /* XXX to be removed */ 1237#ifdef HDAC_INTR_EXTRA 1238 } 1239#endif 1240 1241 return (0); 1242} 1243 1244/**************************************************************************** 1245 * void hdac_intr_handler(void *) 1246 * 1247 * Interrupt handler. Processes interrupts received from the hdac. 1248 ****************************************************************************/ 1249static void 1250hdac_intr_handler(void *context) 1251{ 1252 struct hdac_softc *sc; 1253 uint32_t intsts; 1254 uint8_t rirbsts; 1255 struct hdac_rirb *rirb_base; 1256 uint32_t trigger; 1257 int i; 1258 1259 sc = (struct hdac_softc *)context; 1260 1261 hdac_lock(sc); 1262 if (sc->polling != 0) { 1263 hdac_unlock(sc); 1264 return; 1265 } 1266 1267 /* Do we have anything to do? */ 1268 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1269 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1270 hdac_unlock(sc); 1271 return; 1272 } 1273 1274 trigger = 0; 1275 1276 /* Was this a controller interrupt? */ 1277 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1278 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1279 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1280 /* Get as many responses that we can */ 1281 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1282 HDAC_WRITE_1(&sc->mem, 1283 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1284 if (hdac_rirb_flush(sc) != 0) 1285 trigger |= HDAC_TRIGGER_UNSOL; 1286 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1287 } 1288 /* XXX to be removed */ 1289 /* Clear interrupt and exit */ 1290#ifdef HDAC_INTR_EXTRA 1291 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1292#endif 1293 } 1294 1295 if (intsts & HDAC_INTSTS_SIS_MASK) { 1296 for (i = 0; i < sc->num_chans; i++) { 1297 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1298 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1299 trigger |= (1 << i); 1300 } 1301 /* XXX to be removed */ 1302#ifdef HDAC_INTR_EXTRA 1303 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1304 HDAC_INTSTS_SIS_MASK); 1305#endif 1306 } 1307 1308 hdac_unlock(sc); 1309 1310 for (i = 0; i < sc->num_chans; i++) { 1311 if (trigger & (1 << i)) 1312 chn_intr(sc->chans[i].c); 1313 } 1314 if (trigger & HDAC_TRIGGER_UNSOL) 1315 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1316} 1317 1318/**************************************************************************** 1319 * int hdac_reset(hdac_softc *, int) 1320 * 1321 * Reset the hdac to a quiescent and known state. 1322 ****************************************************************************/ 1323static int 1324hdac_reset(struct hdac_softc *sc, int wakeup) 1325{ 1326 uint32_t gctl; 1327 int count, i; 1328 1329 /* 1330 * Stop all Streams DMA engine 1331 */ 1332 for (i = 0; i < sc->num_iss; i++) 1333 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1334 for (i = 0; i < sc->num_oss; i++) 1335 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1336 for (i = 0; i < sc->num_bss; i++) 1337 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1338 1339 /* 1340 * Stop Control DMA engines. 1341 */ 1342 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1343 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1344 1345 /* 1346 * Reset DMA position buffer. 1347 */ 1348 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1349 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1350 1351 /* 1352 * Reset the controller. The reset must remain asserted for 1353 * a minimum of 100us. 1354 */ 1355 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1356 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1357 count = 10000; 1358 do { 1359 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1360 if (!(gctl & HDAC_GCTL_CRST)) 1361 break; 1362 DELAY(10); 1363 } while (--count); 1364 if (gctl & HDAC_GCTL_CRST) { 1365 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1366 return (ENXIO); 1367 } 1368 1369 /* If wakeup is not requested - leave the controller in reset state. */ 1370 if (!wakeup) 1371 return (0); 1372 1373 DELAY(100); 1374 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1375 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1376 count = 10000; 1377 do { 1378 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1379 if (gctl & HDAC_GCTL_CRST) 1380 break; 1381 DELAY(10); 1382 } while (--count); 1383 if (!(gctl & HDAC_GCTL_CRST)) { 1384 device_printf(sc->dev, "Device stuck in reset\n"); 1385 return (ENXIO); 1386 } 1387 1388 /* 1389 * Wait for codecs to finish their own reset sequence. The delay here 1390 * should be of 250us but for some reasons, on it's not enough on my 1391 * computer. Let's use twice as much as necessary to make sure that 1392 * it's reset properly. 1393 */ 1394 DELAY(1000); 1395 1396 return (0); 1397} 1398 1399 1400/**************************************************************************** 1401 * int hdac_get_capabilities(struct hdac_softc *); 1402 * 1403 * Retreive the general capabilities of the hdac; 1404 * Number of Input Streams 1405 * Number of Output Streams 1406 * Number of bidirectional Streams 1407 * 64bit ready 1408 * CORB and RIRB sizes 1409 ****************************************************************************/ 1410static int 1411hdac_get_capabilities(struct hdac_softc *sc) 1412{ 1413 uint16_t gcap; 1414 uint8_t corbsize, rirbsize; 1415 1416 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1417 sc->num_iss = HDAC_GCAP_ISS(gcap); 1418 sc->num_oss = HDAC_GCAP_OSS(gcap); 1419 sc->num_bss = HDAC_GCAP_BSS(gcap); 1420 1421 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1422 1423 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1424 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1425 HDAC_CORBSIZE_CORBSZCAP_256) 1426 sc->corb_size = 256; 1427 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1428 HDAC_CORBSIZE_CORBSZCAP_16) 1429 sc->corb_size = 16; 1430 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1431 HDAC_CORBSIZE_CORBSZCAP_2) 1432 sc->corb_size = 2; 1433 else { 1434 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1435 __func__, corbsize); 1436 return (ENXIO); 1437 } 1438 1439 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1440 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1441 HDAC_RIRBSIZE_RIRBSZCAP_256) 1442 sc->rirb_size = 256; 1443 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1444 HDAC_RIRBSIZE_RIRBSZCAP_16) 1445 sc->rirb_size = 16; 1446 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1447 HDAC_RIRBSIZE_RIRBSZCAP_2) 1448 sc->rirb_size = 2; 1449 else { 1450 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1451 __func__, rirbsize); 1452 return (ENXIO); 1453 } 1454 1455 HDA_BOOTHVERBOSE( 1456 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1457 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1458 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1459 sc->num_iss, sc->num_oss, sc->num_bss); 1460 ); 1461 1462 return (0); 1463} 1464 1465 1466/**************************************************************************** 1467 * void hdac_dma_cb 1468 * 1469 * This function is called by bus_dmamap_load when the mapping has been 1470 * established. We just record the physical address of the mapping into 1471 * the struct hdac_dma passed in. 1472 ****************************************************************************/ 1473static void 1474hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1475{ 1476 struct hdac_dma *dma; 1477 1478 if (error == 0) { 1479 dma = (struct hdac_dma *)callback_arg; 1480 dma->dma_paddr = segs[0].ds_addr; 1481 } 1482} 1483 1484 1485/**************************************************************************** 1486 * int hdac_dma_alloc 1487 * 1488 * This function allocate and setup a dma region (struct hdac_dma). 1489 * It must be freed by a corresponding hdac_dma_free. 1490 ****************************************************************************/ 1491static int 1492hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1493{ 1494 bus_size_t roundsz; 1495 int result; 1496 int lowaddr; 1497 1498 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1499 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1500 BUS_SPACE_MAXADDR_32BIT; 1501 bzero(dma, sizeof(*dma)); 1502 1503 /* 1504 * Create a DMA tag 1505 */ 1506 result = bus_dma_tag_create(NULL, /* parent */ 1507 HDAC_DMA_ALIGNMENT, /* alignment */ 1508 0, /* boundary */ 1509 lowaddr, /* lowaddr */ 1510 BUS_SPACE_MAXADDR, /* highaddr */ 1511 NULL, /* filtfunc */ 1512 NULL, /* fistfuncarg */ 1513 roundsz, /* maxsize */ 1514 1, /* nsegments */ 1515 roundsz, /* maxsegsz */ 1516 0, /* flags */ 1517 NULL, /* lockfunc */ 1518 NULL, /* lockfuncarg */ 1519 &dma->dma_tag); /* dmat */ 1520 if (result != 0) { 1521 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1522 __func__, result); 1523 goto hdac_dma_alloc_fail; 1524 } 1525 1526 /* 1527 * Allocate DMA memory 1528 */ 1529 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1530 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1531 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1532 &dma->dma_map); 1533 if (result != 0) { 1534 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1535 __func__, result); 1536 goto hdac_dma_alloc_fail; 1537 } 1538 1539 dma->dma_size = roundsz; 1540 1541 /* 1542 * Map the memory 1543 */ 1544 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1545 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1546 if (result != 0 || dma->dma_paddr == 0) { 1547 if (result == 0) 1548 result = ENOMEM; 1549 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1550 __func__, result); 1551 goto hdac_dma_alloc_fail; 1552 } 1553 1554 HDA_BOOTHVERBOSE( 1555 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1556 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1557 ); 1558 1559 return (0); 1560 1561hdac_dma_alloc_fail: 1562 hdac_dma_free(sc, dma); 1563 1564 return (result); 1565} 1566 1567 1568/**************************************************************************** 1569 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1570 * 1571 * Free a struct dhac_dma that has been previously allocated via the 1572 * hdac_dma_alloc function. 1573 ****************************************************************************/ 1574static void 1575hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1576{ 1577 if (dma->dma_map != NULL) { 1578#if 0 1579 /* Flush caches */ 1580 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1581 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1582#endif 1583 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1584 } 1585 if (dma->dma_vaddr != NULL) { 1586 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1587 dma->dma_vaddr = NULL; 1588 } 1589 dma->dma_map = NULL; 1590 if (dma->dma_tag != NULL) { 1591 bus_dma_tag_destroy(dma->dma_tag); 1592 dma->dma_tag = NULL; 1593 } 1594 dma->dma_size = 0; 1595} 1596 1597/**************************************************************************** 1598 * int hdac_mem_alloc(struct hdac_softc *) 1599 * 1600 * Allocate all the bus resources necessary to speak with the physical 1601 * controller. 1602 ****************************************************************************/ 1603static int 1604hdac_mem_alloc(struct hdac_softc *sc) 1605{ 1606 struct hdac_mem *mem; 1607 1608 mem = &sc->mem; 1609 mem->mem_rid = PCIR_BAR(0); 1610 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1611 &mem->mem_rid, RF_ACTIVE); 1612 if (mem->mem_res == NULL) { 1613 device_printf(sc->dev, 1614 "%s: Unable to allocate memory resource\n", __func__); 1615 return (ENOMEM); 1616 } 1617 mem->mem_tag = rman_get_bustag(mem->mem_res); 1618 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1619 1620 return (0); 1621} 1622 1623/**************************************************************************** 1624 * void hdac_mem_free(struct hdac_softc *) 1625 * 1626 * Free up resources previously allocated by hdac_mem_alloc. 1627 ****************************************************************************/ 1628static void 1629hdac_mem_free(struct hdac_softc *sc) 1630{ 1631 struct hdac_mem *mem; 1632 1633 mem = &sc->mem; 1634 if (mem->mem_res != NULL) 1635 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1636 mem->mem_res); 1637 mem->mem_res = NULL; 1638} 1639 1640/**************************************************************************** 1641 * int hdac_irq_alloc(struct hdac_softc *) 1642 * 1643 * Allocate and setup the resources necessary for interrupt handling. 1644 ****************************************************************************/ 1645static int 1646hdac_irq_alloc(struct hdac_softc *sc) 1647{ 1648 struct hdac_irq *irq; 1649 int result; 1650 1651 irq = &sc->irq; 1652 irq->irq_rid = 0x0; 1653 1654#ifdef HDAC_MSI_ENABLED 1655 if ((sc->flags & HDAC_F_MSI) && 1656 (result = pci_msi_count(sc->dev)) == 1 && 1657 pci_alloc_msi(sc->dev, &result) == 0) 1658 irq->irq_rid = 0x1; 1659 else 1660#endif 1661 sc->flags &= ~HDAC_F_MSI; 1662 1663 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1664 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1665 if (irq->irq_res == NULL) { 1666 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1667 __func__); 1668 goto hdac_irq_alloc_fail; 1669 } 1670 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1671 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1672 if (result != 0) { 1673 device_printf(sc->dev, 1674 "%s: Unable to setup interrupt handler (%x)\n", 1675 __func__, result); 1676 goto hdac_irq_alloc_fail; 1677 } 1678 1679 return (0); 1680 1681hdac_irq_alloc_fail: 1682 hdac_irq_free(sc); 1683 1684 return (ENXIO); 1685} 1686 1687/**************************************************************************** 1688 * void hdac_irq_free(struct hdac_softc *) 1689 * 1690 * Free up resources previously allocated by hdac_irq_alloc. 1691 ****************************************************************************/ 1692static void 1693hdac_irq_free(struct hdac_softc *sc) 1694{ 1695 struct hdac_irq *irq; 1696 1697 irq = &sc->irq; 1698 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1699 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1700 if (irq->irq_res != NULL) 1701 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1702 irq->irq_res); 1703#ifdef HDAC_MSI_ENABLED 1704 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1705 pci_release_msi(sc->dev); 1706#endif 1707 irq->irq_handle = NULL; 1708 irq->irq_res = NULL; 1709 irq->irq_rid = 0x0; 1710} 1711 1712/**************************************************************************** 1713 * void hdac_corb_init(struct hdac_softc *) 1714 * 1715 * Initialize the corb registers for operations but do not start it up yet. 1716 * The CORB engine must not be running when this function is called. 1717 ****************************************************************************/ 1718static void 1719hdac_corb_init(struct hdac_softc *sc) 1720{ 1721 uint8_t corbsize; 1722 uint64_t corbpaddr; 1723 1724 /* Setup the CORB size. */ 1725 switch (sc->corb_size) { 1726 case 256: 1727 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1728 break; 1729 case 16: 1730 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1731 break; 1732 case 2: 1733 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1734 break; 1735 default: 1736 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1737 } 1738 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1739 1740 /* Setup the CORB Address in the hdac */ 1741 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1742 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1743 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1744 1745 /* Set the WP and RP */ 1746 sc->corb_wp = 0; 1747 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1748 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1749 /* 1750 * The HDA specification indicates that the CORBRPRST bit will always 1751 * read as zero. Unfortunately, it seems that at least the 82801G 1752 * doesn't reset the bit to zero, which stalls the corb engine. 1753 * manually reset the bit to zero before continuing. 1754 */ 1755 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1756 1757 /* Enable CORB error reporting */ 1758#if 0 1759 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1760#endif 1761} 1762 1763/**************************************************************************** 1764 * void hdac_rirb_init(struct hdac_softc *) 1765 * 1766 * Initialize the rirb registers for operations but do not start it up yet. 1767 * The RIRB engine must not be running when this function is called. 1768 ****************************************************************************/ 1769static void 1770hdac_rirb_init(struct hdac_softc *sc) 1771{ 1772 uint8_t rirbsize; 1773 uint64_t rirbpaddr; 1774 1775 /* Setup the RIRB size. */ 1776 switch (sc->rirb_size) { 1777 case 256: 1778 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1779 break; 1780 case 16: 1781 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1782 break; 1783 case 2: 1784 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1785 break; 1786 default: 1787 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1788 } 1789 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1790 1791 /* Setup the RIRB Address in the hdac */ 1792 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1793 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1794 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1795 1796 /* Setup the WP and RP */ 1797 sc->rirb_rp = 0; 1798 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1799 1800 /* Setup the interrupt threshold */ 1801 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1802 1803 /* Enable Overrun and response received reporting */ 1804#if 0 1805 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1806 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1807#else 1808 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1809#endif 1810 1811#if 0 1812 /* 1813 * Make sure that the Host CPU cache doesn't contain any dirty 1814 * cache lines that falls in the rirb. If I understood correctly, it 1815 * should be sufficient to do this only once as the rirb is purely 1816 * read-only from now on. 1817 */ 1818 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1819 BUS_DMASYNC_PREREAD); 1820#endif 1821} 1822 1823/**************************************************************************** 1824 * void hdac_corb_start(hdac_softc *) 1825 * 1826 * Startup the corb DMA engine 1827 ****************************************************************************/ 1828static void 1829hdac_corb_start(struct hdac_softc *sc) 1830{ 1831 uint32_t corbctl; 1832 1833 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1834 corbctl |= HDAC_CORBCTL_CORBRUN; 1835 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1836} 1837 1838/**************************************************************************** 1839 * void hdac_rirb_start(hdac_softc *) 1840 * 1841 * Startup the rirb DMA engine 1842 ****************************************************************************/ 1843static void 1844hdac_rirb_start(struct hdac_softc *sc) 1845{ 1846 uint32_t rirbctl; 1847 1848 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1849 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1850 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1851} 1852 1853 1854/**************************************************************************** 1855 * void hdac_scan_codecs(struct hdac_softc *, int) 1856 * 1857 * Scan the bus for available codecs, starting with num. 1858 ****************************************************************************/ 1859static void 1860hdac_scan_codecs(struct hdac_softc *sc) 1861{ 1862 struct hdac_codec *codec; 1863 int i; 1864 uint16_t statests; 1865 1866 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1867 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1868 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1869 /* We have found a codec. */ 1870 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1871 M_HDAC, M_ZERO | M_NOWAIT); 1872 if (codec == NULL) { 1873 device_printf(sc->dev, 1874 "Unable to allocate memory for codec\n"); 1875 continue; 1876 } 1877 codec->commands = NULL; 1878 codec->responses_received = 0; 1879 codec->verbs_sent = 0; 1880 codec->sc = sc; 1881 codec->cad = i; 1882 sc->codecs[i] = codec; 1883 hdac_probe_codec(codec); 1884 } 1885 } 1886 /* All codecs have been probed, now try to attach drivers to them */ 1887 /* bus_generic_attach(sc->dev); */ 1888} 1889 1890/**************************************************************************** 1891 * void hdac_probe_codec(struct hdac_softc *, int) 1892 * 1893 * Probe a the given codec_id for available function groups. 1894 ****************************************************************************/ 1895static void 1896hdac_probe_codec(struct hdac_codec *codec) 1897{ 1898 struct hdac_softc *sc = codec->sc; 1899 uint32_t vendorid, revisionid, subnode; 1900 int startnode; 1901 int endnode; 1902 int i; 1903 nid_t cad = codec->cad; 1904 1905 HDA_BOOTVERBOSE( 1906 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1907 ); 1908 vendorid = hdac_command(sc, 1909 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1910 cad); 1911 revisionid = hdac_command(sc, 1912 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1913 cad); 1914 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1915 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1916 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1917 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1918 1919 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1920 device_printf(sc->dev, "Codec #%d is not responding!" 1921 " Probing aborted.\n", cad); 1922 return; 1923 } 1924 1925 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1926 cad, hdac_codec_name(codec)); 1927 HDA_BOOTVERBOSE( 1928 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1929 hdac_codec_id(codec)); 1930 device_printf(sc->dev, " Vendor: 0x%04x\n", 1931 codec->vendor_id); 1932 device_printf(sc->dev, " Device: 0x%04x\n", 1933 codec->device_id); 1934 device_printf(sc->dev, " Revision: 0x%02x\n", 1935 codec->revision_id); 1936 device_printf(sc->dev, " Stepping: 0x%02x\n", 1937 codec->stepping_id); 1938 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1939 sc->pci_subvendor); 1940 ); 1941 subnode = hdac_command(sc, 1942 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1943 cad); 1944 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1945 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1946 1947 HDA_BOOTHVERBOSE( 1948 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1949 startnode, endnode); 1950 ); 1951 1952 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1953 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1954 if (codec->fgs == NULL) { 1955 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1956 __func__); 1957 return; 1958 } 1959 1960 for (i = startnode; i < endnode; i++) 1961 hdac_probe_function(codec, i); 1962 return; 1963} 1964 1965/* 1966 * Probe codec function and add it to the list. 1967 */ 1968static void 1969hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1970{ 1971 struct hdac_softc *sc = codec->sc; 1972 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1973 uint32_t fctgrptype; 1974 uint32_t res; 1975 nid_t cad = codec->cad; 1976 1977 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1978 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1979 1980 devinfo->nid = nid; 1981 devinfo->node_type = fctgrptype; 1982 devinfo->codec = codec; 1983 1984 res = hdac_command(sc, 1985 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1986 1987 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1988 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1989 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1990 1991 HDA_BOOTVERBOSE( 1992 device_printf(sc->dev, 1993 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1994 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1995 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1996 "unknown", nid, devinfo->startnode, devinfo->endnode, 1997 devinfo->nodecnt); 1998 ); 1999 2000 if (devinfo->nodecnt > 0) 2001 devinfo->widget = (struct hdac_widget *)malloc( 2002 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2003 M_NOWAIT | M_ZERO); 2004 else 2005 devinfo->widget = NULL; 2006 2007 if (devinfo->widget == NULL) { 2008 device_printf(sc->dev, "unable to allocate widgets!\n"); 2009 devinfo->endnode = devinfo->startnode; 2010 devinfo->nodecnt = 0; 2011 return; 2012 } 2013 2014 codec->num_fgs++; 2015} 2016 2017static void 2018hdac_widget_connection_parse(struct hdac_widget *w) 2019{ 2020 struct hdac_softc *sc = w->devinfo->codec->sc; 2021 uint32_t res; 2022 int i, j, max, ents, entnum; 2023 nid_t cad = w->devinfo->codec->cad; 2024 nid_t nid = w->nid; 2025 nid_t cnid, addcnid, prevcnid; 2026 2027 w->nconns = 0; 2028 2029 res = hdac_command(sc, 2030 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2031 2032 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2033 2034 if (ents < 1) 2035 return; 2036 2037 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2038 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2039 prevcnid = 0; 2040 2041#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2042#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2043#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2044#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2045#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2046 2047 for (i = 0; i < ents; i += entnum) { 2048 res = hdac_command(sc, 2049 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2050 for (j = 0; j < entnum; j++) { 2051 cnid = CONN_CNID(res, entnum, j); 2052 if (cnid == 0) { 2053 if (w->nconns < ents) 2054 device_printf(sc->dev, 2055 "%s: nid=%d WARNING: zero cnid " 2056 "entnum=%d j=%d index=%d " 2057 "entries=%d found=%d res=0x%08x\n", 2058 __func__, nid, entnum, j, i, 2059 ents, w->nconns, res); 2060 else 2061 goto getconns_out; 2062 } 2063 if (cnid < w->devinfo->startnode || 2064 cnid >= w->devinfo->endnode) { 2065 HDA_BOOTVERBOSE( 2066 device_printf(sc->dev, 2067 "GHOST: nid=%d j=%d " 2068 "entnum=%d index=%d res=0x%08x\n", 2069 nid, j, entnum, i, res); 2070 ); 2071 } 2072 if (CONN_RANGE(res, entnum, j) == 0) 2073 addcnid = cnid; 2074 else if (prevcnid == 0 || prevcnid >= cnid) { 2075 device_printf(sc->dev, 2076 "%s: WARNING: Invalid child range " 2077 "nid=%d index=%d j=%d entnum=%d " 2078 "prevcnid=%d cnid=%d res=0x%08x\n", 2079 __func__, nid, i, j, entnum, prevcnid, 2080 cnid, res); 2081 addcnid = cnid; 2082 } else 2083 addcnid = prevcnid + 1; 2084 while (addcnid <= cnid) { 2085 if (w->nconns > max) { 2086 device_printf(sc->dev, 2087 "Adding %d (nid=%d): " 2088 "Max connection reached! max=%d\n", 2089 addcnid, nid, max + 1); 2090 goto getconns_out; 2091 } 2092 w->connsenable[w->nconns] = 1; 2093 w->conns[w->nconns++] = addcnid++; 2094 } 2095 prevcnid = cnid; 2096 } 2097 } 2098 2099getconns_out: 2100 return; 2101} 2102 2103static uint32_t 2104hdac_widget_pin_patch(uint32_t config, const char *str) 2105{ 2106 char buf[256]; 2107 char *key, *value, *rest, *bad; 2108 int ival, i; 2109 2110 strlcpy(buf, str, sizeof(buf)); 2111 rest = buf; 2112 while ((key = strsep(&rest, "=")) != NULL) { 2113 value = strsep(&rest, " \t"); 2114 if (value == NULL) 2115 break; 2116 ival = strtol(value, &bad, 10); 2117 if (strcmp(key, "seq") == 0) { 2118 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2119 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2120 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2121 } else if (strcmp(key, "as") == 0) { 2122 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2123 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2124 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2125 } else if (strcmp(key, "misc") == 0) { 2126 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2127 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2128 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2129 } else if (strcmp(key, "color") == 0) { 2130 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2131 if (bad[0] == 0) { 2132 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2133 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2134 }; 2135 for (i = 0; i < 16; i++) { 2136 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2137 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2138 break; 2139 } 2140 } 2141 } else if (strcmp(key, "ctype") == 0) { 2142 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2143 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2144 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2145 } else if (strcmp(key, "device") == 0) { 2146 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2147 if (bad[0] == 0) { 2148 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2149 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2150 continue; 2151 }; 2152 for (i = 0; i < 16; i++) { 2153 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2154 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2155 break; 2156 } 2157 } 2158 } else if (strcmp(key, "loc") == 0) { 2159 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2160 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2161 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2162 } else if (strcmp(key, "conn") == 0) { 2163 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2164 if (bad[0] == 0) { 2165 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2166 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2167 continue; 2168 }; 2169 for (i = 0; i < 4; i++) { 2170 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2171 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2172 break; 2173 } 2174 } 2175 } 2176 } 2177 return (config); 2178} 2179 2180static uint32_t 2181hdac_widget_pin_getconfig(struct hdac_widget *w) 2182{ 2183 struct hdac_softc *sc; 2184 uint32_t config, orig, id; 2185 nid_t cad, nid; 2186 char buf[32]; 2187 const char *res = NULL, *patch = NULL; 2188 2189 sc = w->devinfo->codec->sc; 2190 cad = w->devinfo->codec->cad; 2191 nid = w->nid; 2192 id = hdac_codec_id(w->devinfo->codec); 2193 2194 config = hdac_command(sc, 2195 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2196 cad); 2197 orig = config; 2198 2199 HDA_BOOTVERBOSE( 2200 hdac_dump_pin_config(w, orig); 2201 ); 2202 2203 /* XXX: Old patches require complete review. 2204 * Now they may create more problem then solve due to 2205 * incorrect associations. 2206 */ 2207 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2208 switch (nid) { 2209 case 26: 2210 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2211 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2212 break; 2213 case 27: 2214 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2215 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2216 break; 2217 default: 2218 break; 2219 } 2220 } else if (id == HDA_CODEC_ALC880 && 2221 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2222 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2223 /* 2224 * Super broken BIOS 2225 */ 2226 switch (nid) { 2227 case 24: /* MIC1 */ 2228 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2229 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2230 break; 2231 case 25: /* XXX MIC2 */ 2232 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2233 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2234 break; 2235 case 26: /* LINE1 */ 2236 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2237 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2238 break; 2239 case 27: /* XXX LINE2 */ 2240 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2241 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2242 break; 2243 case 28: /* CD */ 2244 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2245 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2246 break; 2247 } 2248 } else if (id == HDA_CODEC_ALC883 && 2249 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2250 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2251 switch (nid) { 2252 case 25: 2253 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2254 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2255 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2256 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2257 break; 2258 case 28: 2259 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2260 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2261 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2262 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2263 break; 2264 } 2265 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2266 HP_V3000_SUBVENDOR) { 2267 switch (nid) { 2268 case 18: 2269 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2270 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2271 break; 2272 case 20: 2273 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2274 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2275 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2276 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2277 break; 2278 case 21: 2279 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2280 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2281 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2282 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2283 break; 2284 } 2285 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2286 HP_DV5000_SUBVENDOR) { 2287 switch (nid) { 2288 case 20: 2289 case 21: 2290 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2291 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2292 break; 2293 } 2294 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2295 ASUS_W6F_SUBVENDOR) { 2296 switch (nid) { 2297 case 11: 2298 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2299 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2300 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2301 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2302 break; 2303 case 12: 2304 case 14: 2305 case 16: 2306 case 31: 2307 case 32: 2308 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2309 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2310 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2311 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2312 break; 2313 case 15: 2314 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2315 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2316 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2317 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2318 break; 2319 } 2320 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2321 UNIWILL_9075_SUBVENDOR) { 2322 switch (nid) { 2323 case 15: 2324 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2325 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2326 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2327 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2328 break; 2329 } 2330 } 2331 2332 /* New patches */ 2333 if (id == HDA_CODEC_AD1986A && 2334 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2335 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2336 switch (nid) { 2337 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2338 patch = "device=Line-in as=8 seq=1"; 2339 break; 2340 case 29: 2341 patch = "device=Mic as=8 seq=2"; 2342 break; 2343 case 31: /* Lot of inputs configured with as=15 and unusable */ 2344 patch = "as=8 seq=3"; 2345 break; 2346 case 32: 2347 patch = "as=8 seq=4"; 2348 break; 2349 case 34: 2350 patch = "as=8 seq=5"; 2351 break; 2352 case 36: 2353 patch = "as=8 seq=6"; 2354 break; 2355 } 2356 } else if (id == HDA_CODEC_ALC260 && 2357 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2358 switch (nid) { 2359 case 16: 2360 patch = "seq=15 device=Headphones"; 2361 break; 2362 } 2363 } else if (id == HDA_CODEC_ALC268 && 2364 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2365 switch (nid) { 2366 case 28: 2367 patch = "device=CD conn=fixed"; 2368 break; 2369 } 2370 } 2371 2372 if (patch != NULL) 2373 config = hdac_widget_pin_patch(config, patch); 2374 2375 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2376 if (resource_string_value(device_get_name(sc->dev), 2377 device_get_unit(sc->dev), buf, &res) == 0) { 2378 if (strncmp(res, "0x", 2) == 0) { 2379 config = strtol(res + 2, NULL, 16); 2380 } else { 2381 config = hdac_widget_pin_patch(config, res); 2382 } 2383 } 2384 2385 HDA_BOOTVERBOSE( 2386 if (config != orig) 2387 device_printf(sc->dev, 2388 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2389 nid, orig, config); 2390 ); 2391 2392 return (config); 2393} 2394 2395static uint32_t 2396hdac_widget_pin_getcaps(struct hdac_widget *w) 2397{ 2398 struct hdac_softc *sc; 2399 uint32_t caps, orig, id; 2400 nid_t cad, nid; 2401 2402 sc = w->devinfo->codec->sc; 2403 cad = w->devinfo->codec->cad; 2404 nid = w->nid; 2405 id = hdac_codec_id(w->devinfo->codec); 2406 2407 caps = hdac_command(sc, 2408 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2409 orig = caps; 2410 2411 HDA_BOOTVERBOSE( 2412 if (caps != orig) 2413 device_printf(sc->dev, 2414 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2415 nid, orig, caps); 2416 ); 2417 2418 return (caps); 2419} 2420 2421static void 2422hdac_widget_pin_parse(struct hdac_widget *w) 2423{ 2424 struct hdac_softc *sc = w->devinfo->codec->sc; 2425 uint32_t config, pincap; 2426 const char *devstr, *connstr; 2427 nid_t cad = w->devinfo->codec->cad; 2428 nid_t nid = w->nid; 2429 2430 config = hdac_widget_pin_getconfig(w); 2431 w->wclass.pin.config = config; 2432 2433 pincap = hdac_widget_pin_getcaps(w); 2434 w->wclass.pin.cap = pincap; 2435 2436 w->wclass.pin.ctrl = hdac_command(sc, 2437 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2438 2439 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2440 w->param.eapdbtl = hdac_command(sc, 2441 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2442 w->param.eapdbtl &= 0x7; 2443 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2444 } else 2445 w->param.eapdbtl = HDAC_INVALID; 2446 2447 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2448 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2449 2450 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2451 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2452 2453 strlcat(w->name, ": ", sizeof(w->name)); 2454 strlcat(w->name, devstr, sizeof(w->name)); 2455 strlcat(w->name, " (", sizeof(w->name)); 2456 strlcat(w->name, connstr, sizeof(w->name)); 2457 strlcat(w->name, ")", sizeof(w->name)); 2458} 2459 2460static uint32_t 2461hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2462{ 2463 struct hdac_softc *sc; 2464 uint32_t caps, orig, id; 2465 nid_t cad, nid, beeper = -1; 2466 2467 sc = w->devinfo->codec->sc; 2468 cad = w->devinfo->codec->cad; 2469 nid = w->nid; 2470 id = hdac_codec_id(w->devinfo->codec); 2471 2472 caps = hdac_command(sc, 2473 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2474 cad); 2475 orig = caps; 2476 2477 /* On some codecs beeper is an input pin, but it is not recordable 2478 alone. Also most of BIOSes does not declare beeper pin. 2479 Change beeper pin node type to beeper to help parser. */ 2480 *waspin = 0; 2481 switch (id) { 2482 case HDA_CODEC_AD1988: 2483 case HDA_CODEC_AD1988B: 2484 beeper = 26; 2485 break; 2486 case HDA_CODEC_ALC260: 2487 beeper = 23; 2488 break; 2489 case HDA_CODEC_ALC262: 2490 case HDA_CODEC_ALC268: 2491 case HDA_CODEC_ALC880: 2492 case HDA_CODEC_ALC882: 2493 case HDA_CODEC_ALC883: 2494 case HDA_CODEC_ALC885: 2495 case HDA_CODEC_ALC888: 2496 case HDA_CODEC_ALC889: 2497 beeper = 29; 2498 break; 2499 } 2500 if (nid == beeper) { 2501 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2502 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2503 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2504 *waspin = 1; 2505 } 2506 2507 HDA_BOOTVERBOSE( 2508 if (caps != orig) { 2509 device_printf(sc->dev, 2510 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2511 nid, orig, caps); 2512 } 2513 ); 2514 2515 return (caps); 2516} 2517 2518static void 2519hdac_widget_parse(struct hdac_widget *w) 2520{ 2521 struct hdac_softc *sc = w->devinfo->codec->sc; 2522 uint32_t wcap, cap; 2523 char *typestr; 2524 nid_t cad = w->devinfo->codec->cad; 2525 nid_t nid = w->nid; 2526 2527 wcap = hdac_widget_getcaps(w, &w->waspin); 2528 2529 w->param.widget_cap = wcap; 2530 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2531 2532 switch (w->type) { 2533 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2534 typestr = "audio output"; 2535 break; 2536 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2537 typestr = "audio input"; 2538 break; 2539 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2540 typestr = "audio mixer"; 2541 break; 2542 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2543 typestr = "audio selector"; 2544 break; 2545 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2546 typestr = "pin"; 2547 break; 2548 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2549 typestr = "power widget"; 2550 break; 2551 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2552 typestr = "volume widget"; 2553 break; 2554 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2555 typestr = "beep widget"; 2556 break; 2557 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2558 typestr = "vendor widget"; 2559 break; 2560 default: 2561 typestr = "unknown type"; 2562 break; 2563 } 2564 2565 strlcpy(w->name, typestr, sizeof(w->name)); 2566 2567 hdac_widget_connection_parse(w); 2568 2569 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2570 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2571 w->param.outamp_cap = 2572 hdac_command(sc, 2573 HDA_CMD_GET_PARAMETER(cad, nid, 2574 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2575 else 2576 w->param.outamp_cap = 2577 w->devinfo->function.audio.outamp_cap; 2578 } else 2579 w->param.outamp_cap = 0; 2580 2581 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2582 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2583 w->param.inamp_cap = 2584 hdac_command(sc, 2585 HDA_CMD_GET_PARAMETER(cad, nid, 2586 HDA_PARAM_INPUT_AMP_CAP), cad); 2587 else 2588 w->param.inamp_cap = 2589 w->devinfo->function.audio.inamp_cap; 2590 } else 2591 w->param.inamp_cap = 0; 2592 2593 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2594 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2595 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2596 cap = hdac_command(sc, 2597 HDA_CMD_GET_PARAMETER(cad, nid, 2598 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2599 w->param.supp_stream_formats = (cap != 0) ? cap : 2600 w->devinfo->function.audio.supp_stream_formats; 2601 cap = hdac_command(sc, 2602 HDA_CMD_GET_PARAMETER(cad, nid, 2603 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2604 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2605 w->devinfo->function.audio.supp_pcm_size_rate; 2606 } else { 2607 w->param.supp_stream_formats = 2608 w->devinfo->function.audio.supp_stream_formats; 2609 w->param.supp_pcm_size_rate = 2610 w->devinfo->function.audio.supp_pcm_size_rate; 2611 } 2612 } else { 2613 w->param.supp_stream_formats = 0; 2614 w->param.supp_pcm_size_rate = 0; 2615 } 2616 2617 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2618 hdac_widget_pin_parse(w); 2619} 2620 2621static struct hdac_widget * 2622hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2623{ 2624 if (devinfo == NULL || devinfo->widget == NULL || 2625 nid < devinfo->startnode || nid >= devinfo->endnode) 2626 return (NULL); 2627 return (&devinfo->widget[nid - devinfo->startnode]); 2628} 2629 2630static __inline int 2631hda_poll_channel(struct hdac_chan *ch) 2632{ 2633 uint32_t sz, delta; 2634 volatile uint32_t ptr; 2635 2636 if (!(ch->flags & HDAC_CHN_RUNNING)) 2637 return (0); 2638 2639 sz = ch->blksz * ch->blkcnt; 2640 if (ch->dmapos != NULL) 2641 ptr = *(ch->dmapos); 2642 else 2643 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2644 ch->off + HDAC_SDLPIB); 2645 ch->ptr = ptr; 2646 ptr %= sz; 2647 ptr &= ~(ch->blksz - 1); 2648 delta = (sz + ptr - ch->prevptr) % sz; 2649 2650 if (delta < ch->blksz) 2651 return (0); 2652 2653 ch->prevptr = ptr; 2654 2655 return (1); 2656} 2657 2658static void 2659hda_poll_callback(void *arg) 2660{ 2661 struct hdac_softc *sc = arg; 2662 uint32_t trigger; 2663 int i, active = 0; 2664 2665 if (sc == NULL) 2666 return; 2667 2668 hdac_lock(sc); 2669 if (sc->polling == 0) { 2670 hdac_unlock(sc); 2671 return; 2672 } 2673 2674 trigger = 0; 2675 for (i = 0; i < sc->num_chans; i++) { 2676 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2677 continue; 2678 active = 1; 2679 if (hda_poll_channel(&sc->chans[i])) 2680 trigger |= (1 << i); 2681 } 2682 2683 /* XXX */ 2684 if (active) 2685 callout_reset(&sc->poll_hda, sc->poll_ticks, 2686 hda_poll_callback, sc); 2687 2688 hdac_unlock(sc); 2689 2690 for (i = 0; i < sc->num_chans; i++) { 2691 if (trigger & (1 << i)) 2692 chn_intr(sc->chans[i].c); 2693 } 2694} 2695 2696static int 2697hdac_rirb_flush(struct hdac_softc *sc) 2698{ 2699 struct hdac_rirb *rirb_base, *rirb; 2700 struct hdac_codec *codec; 2701 struct hdac_command_list *commands; 2702 nid_t cad; 2703 uint32_t resp; 2704 uint8_t rirbwp; 2705 int ret; 2706 2707 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2708 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2709#if 0 2710 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2711 BUS_DMASYNC_POSTREAD); 2712#endif 2713 2714 ret = 0; 2715 2716 while (sc->rirb_rp != rirbwp) { 2717 sc->rirb_rp++; 2718 sc->rirb_rp %= sc->rirb_size; 2719 rirb = &rirb_base[sc->rirb_rp]; 2720 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2721 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2722 sc->codecs[cad] == NULL) 2723 continue; 2724 resp = rirb->response; 2725 codec = sc->codecs[cad]; 2726 commands = codec->commands; 2727 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2728 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2729 ((resp >> 26) & 0xffff); 2730 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2731 } else if (commands != NULL && commands->num_commands > 0 && 2732 codec->responses_received < commands->num_commands) 2733 commands->responses[codec->responses_received++] = 2734 resp; 2735 ret++; 2736 } 2737 2738 return (ret); 2739} 2740 2741static int 2742hdac_unsolq_flush(struct hdac_softc *sc) 2743{ 2744 nid_t cad; 2745 uint32_t tag; 2746 int ret = 0; 2747 2748 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2749 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2750 while (sc->unsolq_rp != sc->unsolq_wp) { 2751 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2752 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2753 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2754 hdac_unsolicited_handler(sc->codecs[cad], tag); 2755 ret++; 2756 } 2757 sc->unsolq_st = HDAC_UNSOLQ_READY; 2758 } 2759 2760 return (ret); 2761} 2762 2763static void 2764hdac_poll_callback(void *arg) 2765{ 2766 struct hdac_softc *sc = arg; 2767 if (sc == NULL) 2768 return; 2769 2770 hdac_lock(sc); 2771 if (sc->polling == 0 || sc->poll_ival == 0) { 2772 hdac_unlock(sc); 2773 return; 2774 } 2775 if (hdac_rirb_flush(sc) != 0) 2776 hdac_unsolq_flush(sc); 2777 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2778 hdac_unlock(sc); 2779} 2780 2781static void 2782hdac_poll_reinit(struct hdac_softc *sc) 2783{ 2784 int i, pollticks, min = 1000000; 2785 struct hdac_chan *ch; 2786 2787 for (i = 0; i < sc->num_chans; i++) { 2788 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2789 continue; 2790 ch = &sc->chans[i]; 2791 pollticks = ((uint64_t)hz * ch->blksz) / 2792 ((uint64_t)sndbuf_getbps(ch->b) * 2793 sndbuf_getspd(ch->b)); 2794 pollticks >>= 1; 2795 if (pollticks > hz) 2796 pollticks = hz; 2797 if (pollticks < 1) { 2798 HDA_BOOTVERBOSE( 2799 device_printf(sc->dev, 2800 "%s: pollticks=%d < 1 !\n", 2801 __func__, pollticks); 2802 ); 2803 pollticks = 1; 2804 } 2805 if (min > pollticks) 2806 min = pollticks; 2807 } 2808 HDA_BOOTVERBOSE( 2809 device_printf(sc->dev, 2810 "%s: pollticks %d -> %d\n", 2811 __func__, sc->poll_ticks, min); 2812 ); 2813 sc->poll_ticks = min; 2814 if (min == 1000000) 2815 callout_stop(&sc->poll_hda); 2816 else 2817 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2818} 2819 2820static void 2821hdac_stream_stop(struct hdac_chan *ch) 2822{ 2823 struct hdac_softc *sc = ch->devinfo->codec->sc; 2824 uint32_t ctl; 2825 2826 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2827 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2828 HDAC_SDCTL_RUN); 2829 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2830 2831 ch->flags &= ~HDAC_CHN_RUNNING; 2832 2833 if (sc->polling != 0) 2834 hdac_poll_reinit(sc); 2835 2836 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2837 ctl &= ~(1 << (ch->off >> 5)); 2838 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2839} 2840 2841static void 2842hdac_stream_start(struct hdac_chan *ch) 2843{ 2844 struct hdac_softc *sc = ch->devinfo->codec->sc; 2845 uint32_t ctl; 2846 2847 ch->flags |= HDAC_CHN_RUNNING; 2848 2849 if (sc->polling != 0) 2850 hdac_poll_reinit(sc); 2851 2852 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2853 ctl |= 1 << (ch->off >> 5); 2854 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2855 2856 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2857 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2858 HDAC_SDCTL_RUN; 2859 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2860} 2861 2862static void 2863hdac_stream_reset(struct hdac_chan *ch) 2864{ 2865 struct hdac_softc *sc = ch->devinfo->codec->sc; 2866 int timeout = 1000; 2867 int to = timeout; 2868 uint32_t ctl; 2869 2870 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2871 ctl |= HDAC_SDCTL_SRST; 2872 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2873 do { 2874 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2875 if (ctl & HDAC_SDCTL_SRST) 2876 break; 2877 DELAY(10); 2878 } while (--to); 2879 if (!(ctl & HDAC_SDCTL_SRST)) { 2880 device_printf(sc->dev, "timeout in reset\n"); 2881 } 2882 ctl &= ~HDAC_SDCTL_SRST; 2883 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2884 to = timeout; 2885 do { 2886 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2887 if (!(ctl & HDAC_SDCTL_SRST)) 2888 break; 2889 DELAY(10); 2890 } while (--to); 2891 if (ctl & HDAC_SDCTL_SRST) 2892 device_printf(sc->dev, "can't reset!\n"); 2893} 2894 2895static void 2896hdac_stream_setid(struct hdac_chan *ch) 2897{ 2898 struct hdac_softc *sc = ch->devinfo->codec->sc; 2899 uint32_t ctl; 2900 2901 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2902 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2903 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2904 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2905} 2906 2907static void 2908hdac_bdl_setup(struct hdac_chan *ch) 2909{ 2910 struct hdac_softc *sc = ch->devinfo->codec->sc; 2911 struct hdac_bdle *bdle; 2912 uint64_t addr; 2913 uint32_t blksz, blkcnt; 2914 int i; 2915 2916 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2917 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2918 2919 blksz = ch->blksz; 2920 blkcnt = ch->blkcnt; 2921 2922 for (i = 0; i < blkcnt; i++, bdle++) { 2923 bdle->addrl = (uint32_t)addr; 2924 bdle->addrh = (uint32_t)(addr >> 32); 2925 bdle->len = blksz; 2926 bdle->ioc = 1; 2927 addr += blksz; 2928 } 2929 2930 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2931 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2932 addr = ch->bdl_dma.dma_paddr; 2933 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2934 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2935 if (ch->dmapos != NULL && 2936 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2937 addr = sc->pos_dma.dma_paddr; 2938 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2939 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2940 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2941 } 2942} 2943 2944static int 2945hdac_bdl_alloc(struct hdac_chan *ch) 2946{ 2947 struct hdac_softc *sc = ch->devinfo->codec->sc; 2948 int rc; 2949 2950 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2951 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2952 if (rc) { 2953 device_printf(sc->dev, "can't alloc bdl\n"); 2954 return (rc); 2955 } 2956 2957 return (0); 2958} 2959 2960static void 2961hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2962 int index, int lmute, int rmute, 2963 int left, int right, int dir) 2964{ 2965 uint16_t v = 0; 2966 2967 if (sc == NULL) 2968 return; 2969 2970 if (left != right || lmute != rmute) { 2971 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2972 (lmute << 7) | left; 2973 hdac_command(sc, 2974 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2975 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2976 (rmute << 7) | right; 2977 } else 2978 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2979 (lmute << 7) | left; 2980 2981 hdac_command(sc, 2982 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2983} 2984 2985static void 2986hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2987 int left, int right) 2988{ 2989 struct hdac_softc *sc; 2990 nid_t nid, cad; 2991 int lmute, rmute; 2992 2993 sc = ctl->widget->devinfo->codec->sc; 2994 cad = ctl->widget->devinfo->codec->cad; 2995 nid = ctl->widget->nid; 2996 2997 /* Save new values if valid. */ 2998 if (mute != HDA_AMP_MUTE_DEFAULT) 2999 ctl->muted = mute; 3000 if (left != HDA_AMP_VOL_DEFAULT) 3001 ctl->left = left; 3002 if (right != HDA_AMP_VOL_DEFAULT) 3003 ctl->right = right; 3004 /* Prepare effective values */ 3005 if (ctl->forcemute) { 3006 lmute = 1; 3007 rmute = 1; 3008 left = 0; 3009 right = 0; 3010 } else { 3011 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3012 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3013 left = ctl->left; 3014 right = ctl->right; 3015 } 3016 /* Apply effective values */ 3017 if (ctl->dir & HDA_CTL_OUT) 3018 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3019 lmute, rmute, left, right, 0); 3020 if (ctl->dir & HDA_CTL_IN) 3021 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3022 lmute, rmute, left, right, 1); 3023} 3024 3025static void 3026hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3027{ 3028 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3029 return; 3030 hdac_command(w->devinfo->codec->sc, 3031 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3032 w->nid, index), w->devinfo->codec->cad); 3033 w->selconn = index; 3034} 3035 3036 3037/**************************************************************************** 3038 * uint32_t hdac_command_sendone_internal 3039 * 3040 * Wrapper function that sends only one command to a given codec 3041 ****************************************************************************/ 3042static uint32_t 3043hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3044{ 3045 struct hdac_command_list cl; 3046 uint32_t response = HDAC_INVALID; 3047 3048 if (!hdac_lockowned(sc)) 3049 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3050 cl.num_commands = 1; 3051 cl.verbs = &verb; 3052 cl.responses = &response; 3053 3054 hdac_command_send_internal(sc, &cl, cad); 3055 3056 return (response); 3057} 3058 3059/**************************************************************************** 3060 * hdac_command_send_internal 3061 * 3062 * Send a command list to the codec via the corb. We queue as much verbs as 3063 * we can and msleep on the codec. When the interrupt get the responses 3064 * back from the rirb, it will wake us up so we can queue the remaining verbs 3065 * if any. 3066 ****************************************************************************/ 3067static void 3068hdac_command_send_internal(struct hdac_softc *sc, 3069 struct hdac_command_list *commands, nid_t cad) 3070{ 3071 struct hdac_codec *codec; 3072 int corbrp; 3073 uint32_t *corb; 3074 int timeout; 3075 int retry = 10; 3076 struct hdac_rirb *rirb_base; 3077 3078 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3079 commands->num_commands < 1) 3080 return; 3081 3082 codec = sc->codecs[cad]; 3083 codec->commands = commands; 3084 codec->responses_received = 0; 3085 codec->verbs_sent = 0; 3086 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3087 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3088 3089 do { 3090 if (codec->verbs_sent != commands->num_commands) { 3091 /* Queue as many verbs as possible */ 3092 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3093#if 0 3094 bus_dmamap_sync(sc->corb_dma.dma_tag, 3095 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3096#endif 3097 while (codec->verbs_sent != commands->num_commands && 3098 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3099 sc->corb_wp++; 3100 sc->corb_wp %= sc->corb_size; 3101 corb[sc->corb_wp] = 3102 commands->verbs[codec->verbs_sent++]; 3103 } 3104 3105 /* Send the verbs to the codecs */ 3106#if 0 3107 bus_dmamap_sync(sc->corb_dma.dma_tag, 3108 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3109#endif 3110 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3111 } 3112 3113 timeout = 1000; 3114 while (hdac_rirb_flush(sc) == 0 && --timeout) 3115 DELAY(10); 3116 } while ((codec->verbs_sent != commands->num_commands || 3117 codec->responses_received != commands->num_commands) && --retry); 3118 3119 if (retry == 0) 3120 device_printf(sc->dev, 3121 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3122 __func__, commands->num_commands, codec->verbs_sent, 3123 codec->responses_received); 3124 3125 codec->commands = NULL; 3126 codec->responses_received = 0; 3127 codec->verbs_sent = 0; 3128 3129 hdac_unsolq_flush(sc); 3130} 3131 3132 3133/**************************************************************************** 3134 * Device Methods 3135 ****************************************************************************/ 3136 3137/**************************************************************************** 3138 * int hdac_probe(device_t) 3139 * 3140 * Probe for the presence of an hdac. If none is found, check for a generic 3141 * match using the subclass of the device. 3142 ****************************************************************************/ 3143static int 3144hdac_probe(device_t dev) 3145{ 3146 int i, result; 3147 uint32_t model; 3148 uint16_t class, subclass; 3149 char desc[64]; 3150 3151 model = (uint32_t)pci_get_device(dev) << 16; 3152 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3153 class = pci_get_class(dev); 3154 subclass = pci_get_subclass(dev); 3155 3156 bzero(desc, sizeof(desc)); 3157 result = ENXIO; 3158 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3159 if (hdac_devices[i].model == model) { 3160 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3161 result = BUS_PROBE_DEFAULT; 3162 break; 3163 } 3164 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3165 class == PCIC_MULTIMEDIA && 3166 subclass == PCIS_MULTIMEDIA_HDA) { 3167 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3168 result = BUS_PROBE_GENERIC; 3169 break; 3170 } 3171 } 3172 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3173 subclass == PCIS_MULTIMEDIA_HDA) { 3174 strlcpy(desc, "Generic", sizeof(desc)); 3175 result = BUS_PROBE_GENERIC; 3176 } 3177 if (result != ENXIO) { 3178 strlcat(desc, " High Definition Audio Controller", 3179 sizeof(desc)); 3180 device_set_desc_copy(dev, desc); 3181 } 3182 3183 return (result); 3184} 3185 3186static void * 3187hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3188 struct pcm_channel *c, int dir) 3189{ 3190 struct hdac_pcm_devinfo *pdevinfo = data; 3191 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3192 struct hdac_softc *sc = devinfo->codec->sc; 3193 struct hdac_chan *ch; 3194 int i, ord = 0, chid; 3195 3196 hdac_lock(sc); 3197 3198 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3199 ch = &sc->chans[chid]; 3200 for (i = 0; i < sc->num_chans && i < chid; i++) { 3201 if (ch->dir == sc->chans[i].dir) 3202 ord++; 3203 } 3204 if (dir == PCMDIR_PLAY) { 3205 ch->off = (sc->num_iss + ord) << 5; 3206 } else { 3207 ch->off = ord << 5; 3208 } 3209 3210 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3211 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3212 ch->pcmrates[0] = 48000; 3213 ch->pcmrates[1] = 0; 3214 } 3215 if (sc->pos_dma.dma_vaddr != NULL) 3216 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3217 (sc->streamcnt * 8)); 3218 else 3219 ch->dmapos = NULL; 3220 ch->sid = ++sc->streamcnt; 3221 ch->dir = dir; 3222 ch->b = b; 3223 ch->c = c; 3224 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3225 ch->blkcnt = pdevinfo->chan_blkcnt; 3226 hdac_unlock(sc); 3227 3228 if (hdac_bdl_alloc(ch) != 0) { 3229 ch->blkcnt = 0; 3230 return (NULL); 3231 } 3232 3233 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3234 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3235 pdevinfo->chan_size) != 0) 3236 return (NULL); 3237 3238 return (ch); 3239} 3240 3241static int 3242hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3243{ 3244 struct hdac_chan *ch = data; 3245 int i; 3246 3247 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3248 if (format == ch->caps.fmtlist[i]) { 3249 ch->fmt = format; 3250 return (0); 3251 } 3252 } 3253 3254 return (EINVAL); 3255} 3256 3257static int 3258hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3259{ 3260 struct hdac_chan *ch = data; 3261 uint32_t spd = 0, threshold; 3262 int i; 3263 3264 for (i = 0; ch->pcmrates[i] != 0; i++) { 3265 spd = ch->pcmrates[i]; 3266 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3267 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3268 if (speed < threshold) 3269 break; 3270 } 3271 3272 if (spd == 0) /* impossible */ 3273 ch->spd = 48000; 3274 else 3275 ch->spd = spd; 3276 3277 return (ch->spd); 3278} 3279 3280static void 3281hdac_stream_setup(struct hdac_chan *ch) 3282{ 3283 struct hdac_softc *sc = ch->devinfo->codec->sc; 3284 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3285 struct hdac_widget *w; 3286 int i, chn, totalchn, c; 3287 nid_t cad = ch->devinfo->codec->cad; 3288 uint16_t fmt, dfmt; 3289 3290 HDA_BOOTHVERBOSE( 3291 device_printf(ch->pdevinfo->dev, 3292 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3293 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3294 ch->fmt, ch->spd); 3295 ); 3296 fmt = 0; 3297 if (ch->fmt & AFMT_S16_LE) 3298 fmt |= ch->bit16 << 4; 3299 else if (ch->fmt & AFMT_S32_LE) 3300 fmt |= ch->bit32 << 4; 3301 else 3302 fmt |= 1 << 4; 3303 3304 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3305 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3306 fmt |= hda_rate_tab[i].base; 3307 fmt |= hda_rate_tab[i].mul; 3308 fmt |= hda_rate_tab[i].div; 3309 break; 3310 } 3311 } 3312 3313 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3314 fmt |= 1; 3315 totalchn = 2; 3316 } else 3317 totalchn = 1; 3318 3319 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3320 3321 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3322 if (ch->fmt & AFMT_AC3) 3323 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3324 3325 chn = 0; 3326 for (i = 0; ch->io[i] != -1; i++) { 3327 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3328 if (w == NULL) 3329 continue; 3330 3331 if (as->hpredir >= 0 && i == as->pincnt) 3332 chn = 0; 3333 HDA_BOOTHVERBOSE( 3334 device_printf(ch->pdevinfo->dev, 3335 "PCMDIR_%s: Stream setup nid=%d: " 3336 "fmt=0x%04x, dfmt=0x%04x\n", 3337 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3338 ch->io[i], fmt, dfmt); 3339 ); 3340 hdac_command(sc, 3341 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3342 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3343 hdac_command(sc, 3344 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3345 cad); 3346 } 3347 /* If HP redirection is enabled, but failed to use same 3348 DAC make last DAC one to duplicate first one. */ 3349 if (as->hpredir >= 0 && i == as->pincnt) { 3350 c = (ch->sid << 4); 3351 } else if (chn >= totalchn) { 3352 /* This is until OSS will support multichannel. 3353 Should be: c = 0; to disable unused DAC */ 3354 c = (ch->sid << 4); 3355 }else { 3356 c = (ch->sid << 4) | chn; 3357 } 3358 hdac_command(sc, 3359 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3360 chn += 3361 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3362 2 : 1; 3363 } 3364} 3365 3366static int 3367hdac_channel_setfragments(kobj_t obj, void *data, 3368 uint32_t blksz, uint32_t blkcnt) 3369{ 3370 struct hdac_chan *ch = data; 3371 struct hdac_softc *sc = ch->devinfo->codec->sc; 3372 3373 blksz &= HDA_BLK_ALIGN; 3374 3375 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3376 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3377 if (blksz < HDA_BLK_MIN) 3378 blksz = HDA_BLK_MIN; 3379 if (blkcnt > HDA_BDL_MAX) 3380 blkcnt = HDA_BDL_MAX; 3381 if (blkcnt < HDA_BDL_MIN) 3382 blkcnt = HDA_BDL_MIN; 3383 3384 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3385 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3386 blkcnt >>= 1; 3387 else if ((blksz >> 1) >= HDA_BLK_MIN) 3388 blksz >>= 1; 3389 else 3390 break; 3391 } 3392 3393 if ((sndbuf_getblksz(ch->b) != blksz || 3394 sndbuf_getblkcnt(ch->b) != blkcnt) && 3395 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3396 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3397 __func__, blksz, blkcnt); 3398 3399 ch->blksz = sndbuf_getblksz(ch->b); 3400 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3401 3402 return (1); 3403} 3404 3405static int 3406hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3407{ 3408 struct hdac_chan *ch = data; 3409 3410 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3411 3412 return (ch->blksz); 3413} 3414 3415static void 3416hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3417{ 3418 struct hdac_devinfo *devinfo = ch->devinfo; 3419 struct hdac_widget *w; 3420 nid_t cad = devinfo->codec->cad; 3421 int i; 3422 3423 hdac_stream_stop(ch); 3424 3425 for (i = 0; ch->io[i] != -1; i++) { 3426 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3427 if (w == NULL) 3428 continue; 3429 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3430 hdac_command(sc, 3431 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3432 cad); 3433 } 3434 hdac_command(sc, 3435 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3436 0), cad); 3437 } 3438} 3439 3440static void 3441hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3442{ 3443 ch->ptr = 0; 3444 ch->prevptr = 0; 3445 hdac_stream_stop(ch); 3446 hdac_stream_reset(ch); 3447 hdac_bdl_setup(ch); 3448 hdac_stream_setid(ch); 3449 hdac_stream_setup(ch); 3450 hdac_stream_start(ch); 3451} 3452 3453static int 3454hdac_channel_trigger(kobj_t obj, void *data, int go) 3455{ 3456 struct hdac_chan *ch = data; 3457 struct hdac_softc *sc = ch->devinfo->codec->sc; 3458 3459 if (!PCMTRIG_COMMON(go)) 3460 return (0); 3461 3462 hdac_lock(sc); 3463 switch (go) { 3464 case PCMTRIG_START: 3465 hdac_channel_start(sc, ch); 3466 break; 3467 case PCMTRIG_STOP: 3468 case PCMTRIG_ABORT: 3469 hdac_channel_stop(sc, ch); 3470 break; 3471 default: 3472 break; 3473 } 3474 hdac_unlock(sc); 3475 3476 return (0); 3477} 3478 3479static int 3480hdac_channel_getptr(kobj_t obj, void *data) 3481{ 3482 struct hdac_chan *ch = data; 3483 struct hdac_softc *sc = ch->devinfo->codec->sc; 3484 uint32_t ptr; 3485 3486 hdac_lock(sc); 3487 if (sc->polling != 0) 3488 ptr = ch->ptr; 3489 else if (ch->dmapos != NULL) 3490 ptr = *(ch->dmapos); 3491 else 3492 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3493 hdac_unlock(sc); 3494 3495 /* 3496 * Round to available space and force 128 bytes aligment. 3497 */ 3498 ptr %= ch->blksz * ch->blkcnt; 3499 ptr &= HDA_BLK_ALIGN; 3500 3501 return (ptr); 3502} 3503 3504static struct pcmchan_caps * 3505hdac_channel_getcaps(kobj_t obj, void *data) 3506{ 3507 return (&((struct hdac_chan *)data)->caps); 3508} 3509 3510static kobj_method_t hdac_channel_methods[] = { 3511 KOBJMETHOD(channel_init, hdac_channel_init), 3512 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3513 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3514 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3515 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3516 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3517 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3518 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3519 { 0, 0 } 3520}; 3521CHANNEL_DECLARE(hdac_channel); 3522 3523static int 3524hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3525{ 3526 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3527 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3528 struct hdac_softc *sc = devinfo->codec->sc; 3529 struct hdac_widget *w, *cw; 3530 struct hdac_audio_ctl *ctl; 3531 uint32_t mask, recmask, id; 3532 int i, j, softpcmvol; 3533 3534 hdac_lock(sc); 3535 3536 /* Make sure that in case of soft volume it won't stay muted. */ 3537 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3538 pdevinfo->left[i] = 100; 3539 pdevinfo->right[i] = 100; 3540 } 3541 3542 mask = 0; 3543 recmask = 0; 3544 id = hdac_codec_id(devinfo->codec); 3545 3546 /* Declate EAPD as ogain control. */ 3547 if (pdevinfo->play >= 0) { 3548 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3549 w = hdac_widget_get(devinfo, i); 3550 if (w == NULL || w->enable == 0) 3551 continue; 3552 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3553 w->param.eapdbtl == HDAC_INVALID || 3554 w->bindas != sc->chans[pdevinfo->play].as) 3555 continue; 3556 mask |= SOUND_MASK_OGAIN; 3557 break; 3558 } 3559 } 3560 3561 /* Declare volume controls assigned to this association. */ 3562 i = 0; 3563 ctl = NULL; 3564 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3565 if (ctl->enable == 0) 3566 continue; 3567 if ((pdevinfo->play >= 0 && 3568 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3569 (pdevinfo->rec >= 0 && 3570 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3571 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3572 mask |= ctl->ossmask; 3573 } 3574 3575 /* Declare record sources available to this association. */ 3576 if (pdevinfo->rec >= 0) { 3577 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3578 for (i = 0; ch->io[i] != -1; i++) { 3579 w = hdac_widget_get(devinfo, ch->io[i]); 3580 if (w == NULL || w->enable == 0) 3581 continue; 3582 for (j = 0; j < w->nconns; j++) { 3583 if (w->connsenable[j] == 0) 3584 continue; 3585 cw = hdac_widget_get(devinfo, w->conns[j]); 3586 if (cw == NULL || cw->enable == 0) 3587 continue; 3588 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3589 cw->bindas != -2) 3590 continue; 3591 recmask |= cw->ossmask; 3592 } 3593 } 3594 } 3595 3596 /* Declare soft PCM volume if needed. */ 3597 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3598 ctl = NULL; 3599 if ((mask & SOUND_MASK_PCM) == 0 || 3600 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3601 softpcmvol = 1; 3602 mask |= SOUND_MASK_PCM; 3603 } else { 3604 softpcmvol = 0; 3605 i = 0; 3606 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3607 if (ctl->enable == 0) 3608 continue; 3609 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3610 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3611 continue; 3612 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3613 continue; 3614 if (ctl->step > 0) 3615 break; 3616 } 3617 } 3618 3619 if (softpcmvol == 1 || ctl == NULL) { 3620 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3621 HDA_BOOTVERBOSE( 3622 device_printf(pdevinfo->dev, 3623 "%s Soft PCM volume\n", 3624 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3625 ); 3626 } 3627 } 3628 3629 /* Declare master volume if needed. */ 3630 if (pdevinfo->play >= 0) { 3631 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3632 SOUND_MASK_PCM) { 3633 mask |= SOUND_MASK_VOLUME; 3634 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3635 SOUND_MASK_PCM); 3636 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3637 SOUND_MIXER_NONE); 3638 HDA_BOOTVERBOSE( 3639 device_printf(pdevinfo->dev, 3640 "Forcing master volume with PCM\n"); 3641 ); 3642 } 3643 } 3644 3645 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3646 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3647 3648 mix_setrecdevs(m, recmask); 3649 mix_setdevs(m, mask); 3650 3651 hdac_unlock(sc); 3652 3653 return (0); 3654} 3655 3656static int 3657hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3658 unsigned left, unsigned right) 3659{ 3660 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3661 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3662 struct hdac_softc *sc = devinfo->codec->sc; 3663 struct hdac_widget *w; 3664 struct hdac_audio_ctl *ctl; 3665 uint32_t mute; 3666 int lvol, rvol; 3667 int i, j; 3668 3669 hdac_lock(sc); 3670 /* Save new values. */ 3671 pdevinfo->left[dev] = left; 3672 pdevinfo->right[dev] = right; 3673 3674 /* 'ogain' is the special case implemented with EAPD. */ 3675 if (dev == SOUND_MIXER_OGAIN) { 3676 uint32_t orig; 3677 w = NULL; 3678 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3679 w = hdac_widget_get(devinfo, i); 3680 if (w == NULL || w->enable == 0) 3681 continue; 3682 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3683 w->param.eapdbtl == HDAC_INVALID) 3684 continue; 3685 break; 3686 } 3687 if (i >= devinfo->endnode) { 3688 hdac_unlock(sc); 3689 return (-1); 3690 } 3691 orig = w->param.eapdbtl; 3692 if (left == 0) 3693 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3694 else 3695 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3696 if (orig != w->param.eapdbtl) { 3697 uint32_t val; 3698 3699 val = w->param.eapdbtl; 3700 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3701 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3702 hdac_command(sc, 3703 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3704 w->nid, val), devinfo->codec->cad); 3705 } 3706 hdac_unlock(sc); 3707 return (left | (left << 8)); 3708 } 3709 3710 /* Recalculate all controls related to this OSS device. */ 3711 i = 0; 3712 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3713 if (ctl->enable == 0 || 3714 !(ctl->ossmask & (1 << dev))) 3715 continue; 3716 if (!((pdevinfo->play >= 0 && 3717 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3718 (pdevinfo->rec >= 0 && 3719 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3720 ctl->widget->bindas == -2)) 3721 continue; 3722 3723 lvol = 100; 3724 rvol = 100; 3725 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3726 if (ctl->ossmask & (1 << j)) { 3727 lvol = lvol * pdevinfo->left[j] / 100; 3728 rvol = rvol * pdevinfo->right[j] / 100; 3729 } 3730 } 3731 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3732 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3733 lvol = (lvol * ctl->step + 50) / 100; 3734 rvol = (rvol * ctl->step + 50) / 100; 3735 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3736 } 3737 hdac_unlock(sc); 3738 3739 return (left | (right << 8)); 3740} 3741 3742/* 3743 * Commutate specified record source. 3744 */ 3745static uint32_t 3746hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3747{ 3748 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3749 struct hdac_widget *w, *cw; 3750 struct hdac_audio_ctl *ctl; 3751 char buf[64]; 3752 int i, muted; 3753 uint32_t res = 0; 3754 3755 if (depth > HDA_PARSE_MAXDEPTH) 3756 return (0); 3757 3758 w = hdac_widget_get(devinfo, nid); 3759 if (w == NULL || w->enable == 0) 3760 return (0); 3761 3762 for (i = 0; i < w->nconns; i++) { 3763 if (w->connsenable[i] == 0) 3764 continue; 3765 cw = hdac_widget_get(devinfo, w->conns[i]); 3766 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3767 continue; 3768 /* Call recursively to trace signal to it's source if needed. */ 3769 if ((src & cw->ossmask) != 0) { 3770 if (cw->ossdev < 0) { 3771 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3772 w->conns[i], depth + 1); 3773 } else { 3774 res |= cw->ossmask; 3775 } 3776 } 3777 /* We have two special cases: mixers and others (selectors). */ 3778 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3779 ctl = hdac_audio_ctl_amp_get(devinfo, 3780 w->nid, HDA_CTL_IN, i, 1); 3781 if (ctl == NULL) 3782 continue; 3783 /* If we have input control on this node mute them 3784 * according to requested sources. */ 3785 muted = (src & cw->ossmask) ? 0 : 1; 3786 if (muted != ctl->forcemute) { 3787 ctl->forcemute = muted; 3788 hdac_audio_ctl_amp_set(ctl, 3789 HDA_AMP_MUTE_DEFAULT, 3790 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3791 } 3792 HDA_BOOTHVERBOSE( 3793 device_printf(pdevinfo->dev, 3794 "Recsel (%s): nid %d source %d %s\n", 3795 hdac_audio_ctl_ossmixer_mask2allname( 3796 src, buf, sizeof(buf)), 3797 nid, i, muted?"mute":"unmute"); 3798 ); 3799 } else { 3800 if (w->nconns == 1) 3801 break; 3802 if ((src & cw->ossmask) == 0) 3803 continue; 3804 /* If we found requested source - select it and exit. */ 3805 hdac_widget_connection_select(w, i); 3806 HDA_BOOTHVERBOSE( 3807 device_printf(pdevinfo->dev, 3808 "Recsel (%s): nid %d source %d select\n", 3809 hdac_audio_ctl_ossmixer_mask2allname( 3810 src, buf, sizeof(buf)), 3811 nid, i); 3812 ); 3813 break; 3814 } 3815 } 3816 return (res); 3817} 3818 3819static uint32_t 3820hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3821{ 3822 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3823 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3824 struct hdac_widget *w; 3825 struct hdac_softc *sc = devinfo->codec->sc; 3826 struct hdac_chan *ch; 3827 int i; 3828 uint32_t ret = 0xffffffff; 3829 3830 hdac_lock(sc); 3831 3832 /* Commutate requested recsrc for each ADC. */ 3833 ch = &sc->chans[pdevinfo->rec]; 3834 for (i = 0; ch->io[i] != -1; i++) { 3835 w = hdac_widget_get(devinfo, ch->io[i]); 3836 if (w == NULL || w->enable == 0) 3837 continue; 3838 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3839 } 3840 3841 hdac_unlock(sc); 3842 3843 return ((ret == 0xffffffff)? 0 : ret); 3844} 3845 3846static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3847 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3848 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3849 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3850 { 0, 0 } 3851}; 3852MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3853 3854static void 3855hdac_unsolq_task(void *context, int pending) 3856{ 3857 struct hdac_softc *sc; 3858 3859 sc = (struct hdac_softc *)context; 3860 3861 hdac_lock(sc); 3862 hdac_unsolq_flush(sc); 3863 hdac_unlock(sc); 3864} 3865 3866/**************************************************************************** 3867 * int hdac_attach(device_t) 3868 * 3869 * Attach the device into the kernel. Interrupts usually won't be enabled 3870 * when this function is called. Setup everything that doesn't require 3871 * interrupts and defer probing of codecs until interrupts are enabled. 3872 ****************************************************************************/ 3873static int 3874hdac_attach(device_t dev) 3875{ 3876 struct hdac_softc *sc; 3877 int result; 3878 int i; 3879 uint16_t vendor; 3880 uint8_t v; 3881 3882 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3883 3884 sc = device_get_softc(dev); 3885 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3886 sc->dev = dev; 3887 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3888 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3889 vendor = pci_get_vendor(dev); 3890 3891 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3892 /* Screw nx6325 - subdevice/subvendor swapped */ 3893 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3894 } 3895 3896 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3897 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3898 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3899 3900 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3901 3902 sc->poll_ticks = 1000000; 3903 sc->poll_ival = HDAC_POLL_INTERVAL; 3904 if (resource_int_value(device_get_name(dev), 3905 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3906 sc->polling = 1; 3907 else 3908 sc->polling = 0; 3909 3910 result = bus_dma_tag_create(NULL, /* parent */ 3911 HDAC_DMA_ALIGNMENT, /* alignment */ 3912 0, /* boundary */ 3913 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3914 BUS_SPACE_MAXADDR, /* highaddr */ 3915 NULL, /* filtfunc */ 3916 NULL, /* fistfuncarg */ 3917 HDA_BUFSZ_MAX, /* maxsize */ 3918 1, /* nsegments */ 3919 HDA_BUFSZ_MAX, /* maxsegsz */ 3920 0, /* flags */ 3921 NULL, /* lockfunc */ 3922 NULL, /* lockfuncarg */ 3923 &sc->chan_dmat); /* dmat */ 3924 if (result != 0) { 3925 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3926 __func__, result); 3927 snd_mtxfree(sc->lock); 3928 free(sc, M_DEVBUF); 3929 return (ENXIO); 3930 } 3931 3932 3933 sc->hdabus = NULL; 3934 for (i = 0; i < HDAC_CODEC_MAX; i++) 3935 sc->codecs[i] = NULL; 3936 3937 pci_enable_busmaster(dev); 3938 3939 if (vendor == INTEL_VENDORID) { 3940 /* TCSEL -> TC0 */ 3941 v = pci_read_config(dev, 0x44, 1); 3942 pci_write_config(dev, 0x44, v & 0xf8, 1); 3943 HDA_BOOTHVERBOSE( 3944 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3945 pci_read_config(dev, 0x44, 1)); 3946 ); 3947 } 3948 3949#ifdef HDAC_MSI_ENABLED 3950 if (resource_int_value(device_get_name(dev), 3951 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3952 pci_msi_count(dev) == 1) 3953 sc->flags |= HDAC_F_MSI; 3954 else 3955#endif 3956 sc->flags &= ~HDAC_F_MSI; 3957 3958#if defined(__i386__) || defined(__amd64__) 3959 sc->flags |= HDAC_F_DMA_NOCACHE; 3960 3961 if (resource_int_value(device_get_name(dev), 3962 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3963#else 3964 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3965#endif 3966 /* 3967 * Try to enable PCIe snoop to avoid messing around with 3968 * uncacheable DMA attribute. Since PCIe snoop register 3969 * config is pretty much vendor specific, there are no 3970 * general solutions on how to enable it, forcing us (even 3971 * Microsoft) to enable uncacheable or write combined DMA 3972 * by default. 3973 * 3974 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3975 */ 3976 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3977 if (hdac_pcie_snoop[i].vendor != vendor) 3978 continue; 3979 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3980 if (hdac_pcie_snoop[i].reg == 0x00) 3981 break; 3982 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3983 if ((v & hdac_pcie_snoop[i].enable) == 3984 hdac_pcie_snoop[i].enable) 3985 break; 3986 v &= hdac_pcie_snoop[i].mask; 3987 v |= hdac_pcie_snoop[i].enable; 3988 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3989 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3990 if ((v & hdac_pcie_snoop[i].enable) != 3991 hdac_pcie_snoop[i].enable) { 3992 HDA_BOOTVERBOSE( 3993 device_printf(dev, 3994 "WARNING: Failed to enable PCIe " 3995 "snoop!\n"); 3996 ); 3997#if defined(__i386__) || defined(__amd64__) 3998 sc->flags |= HDAC_F_DMA_NOCACHE; 3999#endif 4000 } 4001 break; 4002 } 4003#if defined(__i386__) || defined(__amd64__) 4004 } 4005#endif 4006 4007 HDA_BOOTHVERBOSE( 4008 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4009 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4010 "Uncacheable" : "PCIe snoop", vendor); 4011 ); 4012 4013 /* Allocate resources */ 4014 result = hdac_mem_alloc(sc); 4015 if (result != 0) 4016 goto hdac_attach_fail; 4017 result = hdac_irq_alloc(sc); 4018 if (result != 0) 4019 goto hdac_attach_fail; 4020 4021 /* Get Capabilities */ 4022 result = hdac_get_capabilities(sc); 4023 if (result != 0) 4024 goto hdac_attach_fail; 4025 4026 /* Allocate CORB and RIRB dma memory */ 4027 result = hdac_dma_alloc(sc, &sc->corb_dma, 4028 sc->corb_size * sizeof(uint32_t)); 4029 if (result != 0) 4030 goto hdac_attach_fail; 4031 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4032 sc->rirb_size * sizeof(struct hdac_rirb)); 4033 if (result != 0) 4034 goto hdac_attach_fail; 4035 4036 /* Quiesce everything */ 4037 HDA_BOOTHVERBOSE( 4038 device_printf(dev, "Reset controller...\n"); 4039 ); 4040 hdac_reset(sc, 1); 4041 4042 /* Initialize the CORB and RIRB */ 4043 hdac_corb_init(sc); 4044 hdac_rirb_init(sc); 4045 4046 /* Defer remaining of initialization until interrupts are enabled */ 4047 sc->intrhook.ich_func = hdac_attach2; 4048 sc->intrhook.ich_arg = (void *)sc; 4049 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4050 sc->intrhook.ich_func = NULL; 4051 hdac_attach2((void *)sc); 4052 } 4053 4054 return (0); 4055 4056hdac_attach_fail: 4057 hdac_irq_free(sc); 4058 hdac_dma_free(sc, &sc->rirb_dma); 4059 hdac_dma_free(sc, &sc->corb_dma); 4060 hdac_mem_free(sc); 4061 snd_mtxfree(sc->lock); 4062 free(sc, M_DEVBUF); 4063 4064 return (ENXIO); 4065} 4066 4067static void 4068hdac_audio_parse(struct hdac_devinfo *devinfo) 4069{ 4070 struct hdac_codec *codec = devinfo->codec; 4071 struct hdac_softc *sc = codec->sc; 4072 struct hdac_widget *w; 4073 uint32_t res; 4074 int i; 4075 nid_t cad, nid; 4076 4077 cad = devinfo->codec->cad; 4078 nid = devinfo->nid; 4079 4080 res = hdac_command(sc, 4081 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4082 devinfo->function.audio.gpio = res; 4083 4084 HDA_BOOTVERBOSE( 4085 device_printf(sc->dev, "GPIO: 0x%08x " 4086 "NumGPIO=%d NumGPO=%d " 4087 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4088 devinfo->function.audio.gpio, 4089 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4090 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4091 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4092 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4093 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4094 ); 4095 4096 res = hdac_command(sc, 4097 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4098 cad); 4099 devinfo->function.audio.supp_stream_formats = res; 4100 4101 res = hdac_command(sc, 4102 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4103 cad); 4104 devinfo->function.audio.supp_pcm_size_rate = res; 4105 4106 res = hdac_command(sc, 4107 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4108 cad); 4109 devinfo->function.audio.outamp_cap = res; 4110 4111 res = hdac_command(sc, 4112 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4113 cad); 4114 devinfo->function.audio.inamp_cap = res; 4115 4116 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4117 w = hdac_widget_get(devinfo, i); 4118 if (w == NULL) 4119 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4120 else { 4121 w->devinfo = devinfo; 4122 w->nid = i; 4123 w->enable = 1; 4124 w->selconn = -1; 4125 w->pflags = 0; 4126 w->ossdev = -1; 4127 w->bindas = -1; 4128 w->param.eapdbtl = HDAC_INVALID; 4129 hdac_widget_parse(w); 4130 } 4131 } 4132} 4133 4134static void 4135hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4136{ 4137 struct hdac_softc *sc = devinfo->codec->sc; 4138 struct hdac_audio_ctl *ctls; 4139 struct hdac_widget *w, *cw; 4140 int i, j, cnt, max, ocap, icap; 4141 int mute, offset, step, size; 4142 4143 /* XXX This is redundant */ 4144 max = 0; 4145 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4146 w = hdac_widget_get(devinfo, i); 4147 if (w == NULL || w->enable == 0) 4148 continue; 4149 if (w->param.outamp_cap != 0) 4150 max++; 4151 if (w->param.inamp_cap != 0) { 4152 switch (w->type) { 4153 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4154 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4155 for (j = 0; j < w->nconns; j++) { 4156 cw = hdac_widget_get(devinfo, 4157 w->conns[j]); 4158 if (cw == NULL || cw->enable == 0) 4159 continue; 4160 max++; 4161 } 4162 break; 4163 default: 4164 max++; 4165 break; 4166 } 4167 } 4168 } 4169 4170 devinfo->function.audio.ctlcnt = max; 4171 4172 if (max < 1) 4173 return; 4174 4175 ctls = (struct hdac_audio_ctl *)malloc( 4176 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4177 4178 if (ctls == NULL) { 4179 /* Blekh! */ 4180 device_printf(sc->dev, "unable to allocate ctls!\n"); 4181 devinfo->function.audio.ctlcnt = 0; 4182 return; 4183 } 4184 4185 cnt = 0; 4186 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4187 if (cnt >= max) { 4188 device_printf(sc->dev, "%s: Ctl overflow!\n", 4189 __func__); 4190 break; 4191 } 4192 w = hdac_widget_get(devinfo, i); 4193 if (w == NULL || w->enable == 0) 4194 continue; 4195 ocap = w->param.outamp_cap; 4196 icap = w->param.inamp_cap; 4197 if (ocap != 0) { 4198 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4199 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4200 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4201 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4202 /*if (offset > step) { 4203 HDA_BOOTVERBOSE( 4204 device_printf(sc->dev, 4205 "BUGGY outamp: nid=%d " 4206 "[offset=%d > step=%d]\n", 4207 w->nid, offset, step); 4208 ); 4209 offset = step; 4210 }*/ 4211 ctls[cnt].enable = 1; 4212 ctls[cnt].widget = w; 4213 ctls[cnt].mute = mute; 4214 ctls[cnt].step = step; 4215 ctls[cnt].size = size; 4216 ctls[cnt].offset = offset; 4217 ctls[cnt].left = offset; 4218 ctls[cnt].right = offset; 4219 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4220 w->waspin) 4221 ctls[cnt].ndir = HDA_CTL_IN; 4222 else 4223 ctls[cnt].ndir = HDA_CTL_OUT; 4224 ctls[cnt++].dir = HDA_CTL_OUT; 4225 } 4226 4227 if (icap != 0) { 4228 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4229 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4230 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4231 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4232 /*if (offset > step) { 4233 HDA_BOOTVERBOSE( 4234 device_printf(sc->dev, 4235 "BUGGY inamp: nid=%d " 4236 "[offset=%d > step=%d]\n", 4237 w->nid, offset, step); 4238 ); 4239 offset = step; 4240 }*/ 4241 switch (w->type) { 4242 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4243 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4244 for (j = 0; j < w->nconns; j++) { 4245 if (cnt >= max) { 4246 device_printf(sc->dev, 4247 "%s: Ctl overflow!\n", 4248 __func__); 4249 break; 4250 } 4251 cw = hdac_widget_get(devinfo, 4252 w->conns[j]); 4253 if (cw == NULL || cw->enable == 0) 4254 continue; 4255 ctls[cnt].enable = 1; 4256 ctls[cnt].widget = w; 4257 ctls[cnt].childwidget = cw; 4258 ctls[cnt].index = j; 4259 ctls[cnt].mute = mute; 4260 ctls[cnt].step = step; 4261 ctls[cnt].size = size; 4262 ctls[cnt].offset = offset; 4263 ctls[cnt].left = offset; 4264 ctls[cnt].right = offset; 4265 ctls[cnt].ndir = HDA_CTL_IN; 4266 ctls[cnt++].dir = HDA_CTL_IN; 4267 } 4268 break; 4269 default: 4270 if (cnt >= max) { 4271 device_printf(sc->dev, 4272 "%s: Ctl overflow!\n", 4273 __func__); 4274 break; 4275 } 4276 ctls[cnt].enable = 1; 4277 ctls[cnt].widget = w; 4278 ctls[cnt].mute = mute; 4279 ctls[cnt].step = step; 4280 ctls[cnt].size = size; 4281 ctls[cnt].offset = offset; 4282 ctls[cnt].left = offset; 4283 ctls[cnt].right = offset; 4284 if (w->type == 4285 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4286 ctls[cnt].ndir = HDA_CTL_OUT; 4287 else 4288 ctls[cnt].ndir = HDA_CTL_IN; 4289 ctls[cnt++].dir = HDA_CTL_IN; 4290 break; 4291 } 4292 } 4293 } 4294 4295 devinfo->function.audio.ctl = ctls; 4296} 4297 4298static void 4299hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4300{ 4301 struct hdac_softc *sc = devinfo->codec->sc; 4302 struct hdac_audio_as *as; 4303 struct hdac_widget *w; 4304 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4305 4306 /* Count present associations */ 4307 max = 0; 4308 for (j = 1; j < 16; j++) { 4309 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4310 w = hdac_widget_get(devinfo, i); 4311 if (w == NULL || w->enable == 0) 4312 continue; 4313 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4314 continue; 4315 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4316 != j) 4317 continue; 4318 max++; 4319 if (j != 15) /* There could be many 1-pin assocs #15 */ 4320 break; 4321 } 4322 } 4323 4324 devinfo->function.audio.ascnt = max; 4325 4326 if (max < 1) 4327 return; 4328 4329 as = (struct hdac_audio_as *)malloc( 4330 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4331 4332 if (as == NULL) { 4333 /* Blekh! */ 4334 device_printf(sc->dev, "unable to allocate assocs!\n"); 4335 devinfo->function.audio.ascnt = 0; 4336 return; 4337 } 4338 4339 for (i = 0; i < max; i++) { 4340 as[i].hpredir = -1; 4341 as[i].chan = -1; 4342 as[i].digital = 1; 4343 } 4344 4345 /* Scan associations skipping as=0. */ 4346 cnt = 0; 4347 for (j = 1; j < 16; j++) { 4348 first = 16; 4349 hpredir = 0; 4350 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4351 w = hdac_widget_get(devinfo, i); 4352 if (w == NULL || w->enable == 0) 4353 continue; 4354 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4355 continue; 4356 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4357 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4358 if (assoc != j) { 4359 continue; 4360 } 4361 KASSERT(cnt < max, 4362 ("%s: Associations owerflow (%d of %d)", 4363 __func__, cnt, max)); 4364 type = w->wclass.pin.config & 4365 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4366 /* Get pin direction. */ 4367 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4368 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4369 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4370 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4371 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4372 dir = HDA_CTL_OUT; 4373 else 4374 dir = HDA_CTL_IN; 4375 /* If this is a first pin - create new association. */ 4376 if (as[cnt].pincnt == 0) { 4377 as[cnt].enable = 1; 4378 as[cnt].index = j; 4379 as[cnt].dir = dir; 4380 } 4381 if (seq < first) 4382 first = seq; 4383 /* Check association correctness. */ 4384 if (as[cnt].pins[seq] != 0) { 4385 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4386 "in association %d! Disabling association.\n", 4387 __func__, seq, w->nid, j); 4388 as[cnt].enable = 0; 4389 } 4390 if (dir != as[cnt].dir) { 4391 device_printf(sc->dev, "%s: Pin %d has wrong " 4392 "direction for association %d! Disabling " 4393 "association.\n", 4394 __func__, w->nid, j); 4395 as[cnt].enable = 0; 4396 } 4397 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4398 as[cnt].digital = 0; 4399 /* Headphones with seq=15 may mean redirection. */ 4400 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4401 seq == 15) 4402 hpredir = 1; 4403 as[cnt].pins[seq] = w->nid; 4404 as[cnt].pincnt++; 4405 /* Association 15 is a multiple unassociated pins. */ 4406 if (j == 15) 4407 cnt++; 4408 } 4409 if (j != 15 && as[cnt].pincnt > 0) { 4410 if (hpredir && as[cnt].pincnt > 1) 4411 as[cnt].hpredir = first; 4412 cnt++; 4413 } 4414 } 4415 HDA_BOOTVERBOSE( 4416 device_printf(sc->dev, 4417 "%d associations found:\n", max); 4418 for (i = 0; i < max; i++) { 4419 device_printf(sc->dev, 4420 "Association %d (%d) %s%s:\n", 4421 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4422 as[i].enable?"":" (disabled)"); 4423 for (j = 0; j < 16; j++) { 4424 if (as[i].pins[j] == 0) 4425 continue; 4426 device_printf(sc->dev, 4427 " Pin nid=%d seq=%d\n", 4428 as[i].pins[j], j); 4429 } 4430 } 4431 ); 4432 4433 devinfo->function.audio.as = as; 4434} 4435 4436static const struct { 4437 uint32_t model; 4438 uint32_t id; 4439 uint32_t set, unset; 4440} hdac_quirks[] = { 4441 /* 4442 * XXX Force stereo quirk. Monoural recording / playback 4443 * on few codecs (especially ALC880) seems broken or 4444 * perhaps unsupported. 4445 */ 4446 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4447 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4448 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4449 HDA_QUIRK_GPIO0, 0 }, 4450 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4451 HDA_QUIRK_GPIO0, 0 }, 4452 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4453 HDA_QUIRK_GPIO0, 0 }, 4454 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4455 HDA_QUIRK_GPIO0, 0 }, 4456 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4457 HDA_QUIRK_GPIO0, 0 }, 4458 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4459 HDA_QUIRK_GPIO0, 0 }, 4460 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4461 HDA_QUIRK_EAPDINV, 0 }, 4462 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4463 HDA_QUIRK_EAPDINV, 0 }, 4464 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4465 HDA_QUIRK_OVREF, 0 }, 4466 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4467 HDA_QUIRK_OVREF, 0 }, 4468 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4469 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4470 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4471 HDA_QUIRK_GPIO1, 0 }, 4472 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4473 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4474 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4475 HDA_QUIRK_EAPDINV, 0 }, 4476 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4477 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4478 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4479 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4480 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4481 HDA_QUIRK_GPIO0, 0 }, 4482 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4483 HDA_QUIRK_GPIO2, 0 }, 4484 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4485 HDA_QUIRK_GPIO0, 0 }, 4486 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4487 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4488 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4489 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4490 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4491 0, HDA_QUIRK_FORCESTEREO } 4492}; 4493#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4494 4495static void 4496hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4497{ 4498 struct hdac_widget *w; 4499 uint32_t id, subvendor; 4500 int i; 4501 4502 id = hdac_codec_id(devinfo->codec); 4503 subvendor = devinfo->codec->sc->pci_subvendor; 4504 4505 /* 4506 * Quirks 4507 */ 4508 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4509 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4510 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4511 continue; 4512 if (hdac_quirks[i].set != 0) 4513 devinfo->function.audio.quirks |= 4514 hdac_quirks[i].set; 4515 if (hdac_quirks[i].unset != 0) 4516 devinfo->function.audio.quirks &= 4517 ~(hdac_quirks[i].unset); 4518 } 4519 4520 switch (id) { 4521 case HDA_CODEC_ALC883: 4522 /* 4523 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4524 * Clear vref cap for jack connectivity. 4525 */ 4526 w = hdac_widget_get(devinfo, 24); 4527 if (w != NULL && w->enable != 0 && w->type == 4528 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4529 (w->wclass.pin.config & 4530 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4531 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4532 w->wclass.pin.cap &= ~( 4533 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4534 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4535 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4536 w = hdac_widget_get(devinfo, 25); 4537 if (w != NULL && w->enable != 0 && w->type == 4538 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4539 (w->wclass.pin.config & 4540 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4541 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4542 w->wclass.pin.cap &= ~( 4543 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4544 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4545 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4546 /* 4547 * nid: 26 = Line-in, leave it alone. 4548 */ 4549 break; 4550 case HDA_CODEC_AD1986A: 4551 /* 4552 * This codec has overcomplicated input mixing. 4553 * Make some cleaning there. 4554 */ 4555 /* Disable input mono mixer. Not needed and not supported. */ 4556 w = hdac_widget_get(devinfo, 43); 4557 if (w != NULL) 4558 w->enable = 0; 4559 /* Disable any with any input mixing mesh. Use separately. */ 4560 w = hdac_widget_get(devinfo, 39); 4561 if (w != NULL) 4562 w->enable = 0; 4563 w = hdac_widget_get(devinfo, 40); 4564 if (w != NULL) 4565 w->enable = 0; 4566 w = hdac_widget_get(devinfo, 41); 4567 if (w != NULL) 4568 w->enable = 0; 4569 w = hdac_widget_get(devinfo, 42); 4570 if (w != NULL) 4571 w->enable = 0; 4572 /* Disable duplicate mixer node connector. */ 4573 w = hdac_widget_get(devinfo, 15); 4574 if (w != NULL) 4575 w->connsenable[3] = 0; 4576 4577 if (subvendor == ASUS_A8X_SUBVENDOR) { 4578 /* 4579 * This is just plain ridiculous.. There 4580 * are several A8 series that share the same 4581 * pci id but works differently (EAPD). 4582 */ 4583 w = hdac_widget_get(devinfo, 26); 4584 if (w != NULL && w->type == 4585 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4586 (w->wclass.pin.config & 4587 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4588 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4589 devinfo->function.audio.quirks &= 4590 ~HDA_QUIRK_EAPDINV; 4591 } 4592 break; 4593 case HDA_CODEC_AD1981HD: 4594 /* 4595 * This codec has very unusual design with several 4596 * points inappropriate for the present parser. 4597 */ 4598 /* Disable recording from mono playback mix. */ 4599 w = hdac_widget_get(devinfo, 21); 4600 if (w != NULL) 4601 w->connsenable[3] = 0; 4602 /* Disable rear to front mic mixer, use separately. */ 4603 w = hdac_widget_get(devinfo, 31); 4604 if (w != NULL) 4605 w->enable = 0; 4606 /* Disable playback mixer, use direct bypass. */ 4607 w = hdac_widget_get(devinfo, 14); 4608 if (w != NULL) 4609 w->enable = 0; 4610 break; 4611 } 4612} 4613 4614/* 4615 * Trace path from DAC to pin. 4616 */ 4617static nid_t 4618hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4619 int dupseq, int min, int only, int depth) 4620{ 4621 struct hdac_widget *w; 4622 int i, im = -1; 4623 nid_t m = 0, ret; 4624 4625 if (depth > HDA_PARSE_MAXDEPTH) 4626 return (0); 4627 w = hdac_widget_get(devinfo, nid); 4628 if (w == NULL || w->enable == 0) 4629 return (0); 4630 HDA_BOOTHVERBOSE( 4631 if (!only) { 4632 device_printf(devinfo->codec->sc->dev, 4633 " %*stracing via nid %d\n", 4634 depth + 1, "", w->nid); 4635 } 4636 ); 4637 /* Use only unused widgets */ 4638 if (w->bindas >= 0 && w->bindas != as) { 4639 HDA_BOOTHVERBOSE( 4640 if (!only) { 4641 device_printf(devinfo->codec->sc->dev, 4642 " %*snid %d busy by association %d\n", 4643 depth + 1, "", w->nid, w->bindas); 4644 } 4645 ); 4646 return (0); 4647 } 4648 if (dupseq < 0) { 4649 if (w->bindseqmask != 0) { 4650 HDA_BOOTHVERBOSE( 4651 if (!only) { 4652 device_printf(devinfo->codec->sc->dev, 4653 " %*snid %d busy by seqmask %x\n", 4654 depth + 1, "", w->nid, w->bindseqmask); 4655 } 4656 ); 4657 return (0); 4658 } 4659 } else { 4660 /* If this is headphones - allow duplicate first pin. */ 4661 if (w->bindseqmask != 0 && 4662 (w->bindseqmask & (1 << dupseq)) == 0) { 4663 HDA_BOOTHVERBOSE( 4664 device_printf(devinfo->codec->sc->dev, 4665 " %*snid %d busy by seqmask %x\n", 4666 depth + 1, "", w->nid, w->bindseqmask); 4667 ); 4668 return (0); 4669 } 4670 } 4671 4672 switch (w->type) { 4673 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4674 /* Do not traverse input. AD1988 has digital monitor 4675 for which we are not ready. */ 4676 break; 4677 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4678 /* If we are tracing HP take only dac of first pin. */ 4679 if ((only == 0 || only == w->nid) && 4680 (w->nid >= min) && (dupseq < 0 || w->nid == 4681 devinfo->function.audio.as[as].dacs[dupseq])) 4682 m = w->nid; 4683 break; 4684 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4685 if (depth > 0) 4686 break; 4687 /* Fall */ 4688 default: 4689 /* Find reachable DACs with smallest nid respecting constraints. */ 4690 for (i = 0; i < w->nconns; i++) { 4691 if (w->connsenable[i] == 0) 4692 continue; 4693 if (w->selconn != -1 && w->selconn != i) 4694 continue; 4695 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4696 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4697 if (m == 0 || ret < m) { 4698 m = ret; 4699 im = i; 4700 } 4701 if (only || dupseq >= 0) 4702 break; 4703 } 4704 } 4705 if (m && only && ((w->nconns > 1 && 4706 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4707 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4708 w->selconn = im; 4709 break; 4710 } 4711 if (m && only) { 4712 w->bindas = as; 4713 w->bindseqmask |= (1 << seq); 4714 } 4715 HDA_BOOTHVERBOSE( 4716 if (!only) { 4717 device_printf(devinfo->codec->sc->dev, 4718 " %*snid %d returned %d\n", 4719 depth + 1, "", w->nid, m); 4720 } 4721 ); 4722 return (m); 4723} 4724 4725/* 4726 * Trace path from widget to ADC. 4727 */ 4728static nid_t 4729hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4730 int only, int depth) 4731{ 4732 struct hdac_widget *w, *wc; 4733 int i, j; 4734 nid_t res = 0; 4735 4736 if (depth > HDA_PARSE_MAXDEPTH) 4737 return (0); 4738 w = hdac_widget_get(devinfo, nid); 4739 if (w == NULL || w->enable == 0) 4740 return (0); 4741 HDA_BOOTHVERBOSE( 4742 device_printf(devinfo->codec->sc->dev, 4743 " %*stracing via nid %d\n", 4744 depth + 1, "", w->nid); 4745 ); 4746 /* Use only unused widgets */ 4747 if (w->bindas >= 0 && w->bindas != as) { 4748 HDA_BOOTHVERBOSE( 4749 device_printf(devinfo->codec->sc->dev, 4750 " %*snid %d busy by association %d\n", 4751 depth + 1, "", w->nid, w->bindas); 4752 ); 4753 return (0); 4754 } 4755 4756 switch (w->type) { 4757 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4758 /* If we are tracing HP take only dac of first pin. */ 4759 if (only == w->nid) 4760 res = 1; 4761 break; 4762 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4763 if (depth > 0) 4764 break; 4765 /* Fall */ 4766 default: 4767 /* Try to find reachable ADCs with specified nid. */ 4768 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4769 wc = hdac_widget_get(devinfo, j); 4770 if (wc == NULL || wc->enable == 0) 4771 continue; 4772 for (i = 0; i < wc->nconns; i++) { 4773 if (wc->connsenable[i] == 0) 4774 continue; 4775 if (wc->conns[i] != nid) 4776 continue; 4777 if (hdac_audio_trace_adc(devinfo, as, seq, 4778 j, only, depth + 1) != 0) { 4779 res = 1; 4780 if (((wc->nconns > 1 && 4781 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4782 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4783 wc->selconn == -1) 4784 wc->selconn = i; 4785 } 4786 } 4787 } 4788 break; 4789 } 4790 if (res) { 4791 w->bindas = as; 4792 w->bindseqmask |= (1 << seq); 4793 } 4794 HDA_BOOTHVERBOSE( 4795 device_printf(devinfo->codec->sc->dev, 4796 " %*snid %d returned %d\n", 4797 depth + 1, "", w->nid, res); 4798 ); 4799 return (res); 4800} 4801 4802/* 4803 * Erase trace path of the specified association. 4804 */ 4805static void 4806hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4807{ 4808 struct hdac_widget *w; 4809 int i; 4810 4811 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4812 w = hdac_widget_get(devinfo, i); 4813 if (w == NULL || w->enable == 0) 4814 continue; 4815 if (w->bindas == as) { 4816 if (seq >= 0) { 4817 w->bindseqmask &= ~(1 << seq); 4818 if (w->bindseqmask == 0) { 4819 w->bindas = -1; 4820 w->selconn = -1; 4821 } 4822 } else { 4823 w->bindas = -1; 4824 w->bindseqmask = 0; 4825 w->selconn = -1; 4826 } 4827 } 4828 } 4829} 4830 4831/* 4832 * Trace association path from DAC to output 4833 */ 4834static int 4835hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4836{ 4837 struct hdac_audio_as *ases = devinfo->function.audio.as; 4838 int i, hpredir; 4839 nid_t min, res; 4840 4841 /* Find next pin */ 4842 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4843 ; 4844 /* Check if there is no any left. If so - we succeded. */ 4845 if (i == 16) 4846 return (1); 4847 4848 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4849 min = 0; 4850 res = 0; 4851 do { 4852 HDA_BOOTHVERBOSE( 4853 device_printf(devinfo->codec->sc->dev, 4854 " Tracing pin %d with min nid %d", 4855 ases[as].pins[i], min); 4856 if (hpredir >= 0) 4857 printf(" and hpredir %d", hpredir); 4858 printf("\n"); 4859 ); 4860 /* Trace this pin taking min nid into account. */ 4861 res = hdac_audio_trace_dac(devinfo, as, i, 4862 ases[as].pins[i], hpredir, min, 0, 0); 4863 if (res == 0) { 4864 /* If we failed - return to previous and redo it. */ 4865 HDA_BOOTVERBOSE( 4866 device_printf(devinfo->codec->sc->dev, 4867 " Unable to trace pin %d seq %d with min " 4868 "nid %d", 4869 ases[as].pins[i], i, min); 4870 if (hpredir >= 0) 4871 printf(" and hpredir %d", hpredir); 4872 printf("\n"); 4873 ); 4874 return (0); 4875 } 4876 HDA_BOOTVERBOSE( 4877 device_printf(devinfo->codec->sc->dev, 4878 " Pin %d traced to DAC %d", 4879 ases[as].pins[i], res); 4880 if (hpredir >= 0) 4881 printf(" and hpredir %d", hpredir); 4882 if (ases[as].fakeredir) 4883 printf(" with fake redirection"); 4884 printf("\n"); 4885 ); 4886 /* Trace again to mark the path */ 4887 hdac_audio_trace_dac(devinfo, as, i, 4888 ases[as].pins[i], hpredir, min, res, 0); 4889 ases[as].dacs[i] = res; 4890 /* We succeded, so call next. */ 4891 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4892 return (1); 4893 /* If next failed, we should retry with next min */ 4894 hdac_audio_undo_trace(devinfo, as, i); 4895 ases[as].dacs[i] = 0; 4896 min = res + 1; 4897 } while (1); 4898} 4899 4900/* 4901 * Trace association path from input to ADC 4902 */ 4903static int 4904hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4905{ 4906 struct hdac_audio_as *ases = devinfo->function.audio.as; 4907 struct hdac_widget *w; 4908 int i, j, k; 4909 4910 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4911 w = hdac_widget_get(devinfo, j); 4912 if (w == NULL || w->enable == 0) 4913 continue; 4914 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4915 continue; 4916 if (w->bindas >= 0 && w->bindas != as) 4917 continue; 4918 4919 /* Find next pin */ 4920 for (i = 0; i < 16; i++) { 4921 if (ases[as].pins[i] == 0) 4922 continue; 4923 4924 HDA_BOOTHVERBOSE( 4925 device_printf(devinfo->codec->sc->dev, 4926 " Tracing pin %d to ADC %d\n", 4927 ases[as].pins[i], j); 4928 ); 4929 /* Trace this pin taking goal into account. */ 4930 if (hdac_audio_trace_adc(devinfo, as, i, 4931 ases[as].pins[i], j, 0) == 0) { 4932 /* If we failed - return to previous and redo it. */ 4933 HDA_BOOTVERBOSE( 4934 device_printf(devinfo->codec->sc->dev, 4935 " Unable to trace pin %d to ADC %d, undo traces\n", 4936 ases[as].pins[i], j); 4937 ); 4938 hdac_audio_undo_trace(devinfo, as, -1); 4939 for (k = 0; k < 16; k++) 4940 ases[as].dacs[k] = 0; 4941 break; 4942 } 4943 HDA_BOOTVERBOSE( 4944 device_printf(devinfo->codec->sc->dev, 4945 " Pin %d traced to ADC %d\n", 4946 ases[as].pins[i], j); 4947 ); 4948 ases[as].dacs[i] = j; 4949 } 4950 if (i == 16) 4951 return (1); 4952 } 4953 return (0); 4954} 4955 4956/* 4957 * Trace input monitor path from mixer to output association. 4958 */ 4959static int 4960hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4961{ 4962 struct hdac_audio_as *ases = devinfo->function.audio.as; 4963 struct hdac_widget *w, *wc; 4964 int i, j; 4965 nid_t res = 0; 4966 4967 if (depth > HDA_PARSE_MAXDEPTH) 4968 return (0); 4969 w = hdac_widget_get(devinfo, nid); 4970 if (w == NULL || w->enable == 0) 4971 return (0); 4972 HDA_BOOTHVERBOSE( 4973 device_printf(devinfo->codec->sc->dev, 4974 " %*stracing via nid %d\n", 4975 depth + 1, "", w->nid); 4976 ); 4977 /* Use only unused widgets */ 4978 if (depth > 0 && w->bindas != -1) { 4979 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4980 HDA_BOOTHVERBOSE( 4981 device_printf(devinfo->codec->sc->dev, 4982 " %*snid %d found output association %d\n", 4983 depth + 1, "", w->nid, w->bindas); 4984 ); 4985 return (1); 4986 } else { 4987 HDA_BOOTHVERBOSE( 4988 device_printf(devinfo->codec->sc->dev, 4989 " %*snid %d busy by input association %d\n", 4990 depth + 1, "", w->nid, w->bindas); 4991 ); 4992 return (0); 4993 } 4994 } 4995 4996 switch (w->type) { 4997 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4998 /* Do not traverse input. AD1988 has digital monitor 4999 for which we are not ready. */ 5000 break; 5001 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5002 if (depth > 0) 5003 break; 5004 /* Fall */ 5005 default: 5006 /* Try to find reachable ADCs with specified nid. */ 5007 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5008 wc = hdac_widget_get(devinfo, j); 5009 if (wc == NULL || wc->enable == 0) 5010 continue; 5011 for (i = 0; i < wc->nconns; i++) { 5012 if (wc->connsenable[i] == 0) 5013 continue; 5014 if (wc->conns[i] != nid) 5015 continue; 5016 if (hdac_audio_trace_to_out(devinfo, 5017 j, depth + 1) != 0) { 5018 res = 1; 5019 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5020 wc->selconn == -1) 5021 wc->selconn = i; 5022 } 5023 } 5024 } 5025 break; 5026 } 5027 if (res) 5028 w->bindas = -2; 5029 5030 HDA_BOOTHVERBOSE( 5031 device_printf(devinfo->codec->sc->dev, 5032 " %*snid %d returned %d\n", 5033 depth + 1, "", w->nid, res); 5034 ); 5035 return (res); 5036} 5037 5038/* 5039 * Trace extra associations (beeper, monitor) 5040 */ 5041static void 5042hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5043{ 5044 struct hdac_audio_as *as = devinfo->function.audio.as; 5045 struct hdac_widget *w; 5046 int j; 5047 5048 /* Input monitor */ 5049 /* Find mixer associated with input, but supplying signal 5050 for output associations. Hope it will be input monitor. */ 5051 HDA_BOOTVERBOSE( 5052 device_printf(devinfo->codec->sc->dev, 5053 "Tracing input monitor\n"); 5054 ); 5055 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5056 w = hdac_widget_get(devinfo, j); 5057 if (w == NULL || w->enable == 0) 5058 continue; 5059 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5060 continue; 5061 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5062 continue; 5063 HDA_BOOTVERBOSE( 5064 device_printf(devinfo->codec->sc->dev, 5065 " Tracing nid %d to out\n", 5066 j); 5067 ); 5068 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5069 HDA_BOOTVERBOSE( 5070 device_printf(devinfo->codec->sc->dev, 5071 " nid %d is input monitor\n", 5072 w->nid); 5073 ); 5074 w->pflags |= HDA_ADC_MONITOR; 5075 w->ossdev = SOUND_MIXER_IMIX; 5076 } 5077 } 5078 5079 /* Beeper */ 5080 HDA_BOOTVERBOSE( 5081 device_printf(devinfo->codec->sc->dev, 5082 "Tracing beeper\n"); 5083 ); 5084 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5085 w = hdac_widget_get(devinfo, j); 5086 if (w == NULL || w->enable == 0) 5087 continue; 5088 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5089 continue; 5090 HDA_BOOTHVERBOSE( 5091 device_printf(devinfo->codec->sc->dev, 5092 " Tracing nid %d to out\n", 5093 j); 5094 ); 5095 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5096 HDA_BOOTVERBOSE( 5097 device_printf(devinfo->codec->sc->dev, 5098 " nid %d traced to out\n", 5099 j); 5100 ); 5101 } 5102 w->bindas = -2; 5103 } 5104} 5105 5106/* 5107 * Bind assotiations to PCM channels 5108 */ 5109static void 5110hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5111{ 5112 struct hdac_softc *sc = devinfo->codec->sc; 5113 struct hdac_audio_as *as = devinfo->function.audio.as; 5114 int j, cnt = 0, free; 5115 5116 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5117 if (as[j].enable) 5118 cnt++; 5119 } 5120 if (sc->num_chans == 0) { 5121 sc->chans = (struct hdac_chan *)malloc( 5122 sizeof(struct hdac_chan) * cnt, 5123 M_HDAC, M_ZERO | M_NOWAIT); 5124 if (sc->chans == NULL) { 5125 device_printf(devinfo->codec->sc->dev, 5126 "Channels memory allocation failed!\n"); 5127 return; 5128 } 5129 } else { 5130 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5131 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5132 M_HDAC, M_ZERO | M_NOWAIT); 5133 if (sc->chans == NULL) { 5134 sc->num_chans = 0; 5135 device_printf(devinfo->codec->sc->dev, 5136 "Channels memory allocation failed!\n"); 5137 return; 5138 } 5139 } 5140 free = sc->num_chans; 5141 sc->num_chans += cnt; 5142 5143 for (j = free; j < free + cnt; j++) { 5144 devinfo->codec->sc->chans[j].devinfo = devinfo; 5145 devinfo->codec->sc->chans[j].as = -1; 5146 } 5147 5148 /* Assign associations in order of their numbers, */ 5149 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5150 if (as[j].enable == 0) 5151 continue; 5152 5153 as[j].chan = free; 5154 devinfo->codec->sc->chans[free].as = j; 5155 devinfo->codec->sc->chans[free].dir = 5156 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5157 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5158 free++; 5159 } 5160} 5161 5162static void 5163hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5164{ 5165 struct hdac_widget *w; 5166 int i; 5167 5168 /* Disable power and volume widgets. */ 5169 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5170 w = hdac_widget_get(devinfo, i); 5171 if (w == NULL || w->enable == 0) 5172 continue; 5173 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5174 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5175 w->enable = 0; 5176 HDA_BOOTHVERBOSE( 5177 device_printf(devinfo->codec->sc->dev, 5178 " Disabling nid %d due to it's" 5179 " non-audio type.\n", 5180 w->nid); 5181 ); 5182 } 5183 } 5184} 5185 5186static void 5187hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5188{ 5189 struct hdac_widget *w, *cw; 5190 struct hdac_audio_ctl *ctl; 5191 int done, found, i, j, k; 5192 5193 /* Disable useless pins. */ 5194 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5195 w = hdac_widget_get(devinfo, i); 5196 if (w == NULL || w->enable == 0) 5197 continue; 5198 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5199 if ((w->wclass.pin.config & 5200 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5201 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5202 w->enable = 0; 5203 HDA_BOOTHVERBOSE( 5204 device_printf(devinfo->codec->sc->dev, 5205 " Disabling pin nid %d due" 5206 " to None connectivity.\n", 5207 w->nid); 5208 ); 5209 } else if ((w->wclass.pin.config & 5210 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5211 w->enable = 0; 5212 HDA_BOOTHVERBOSE( 5213 device_printf(devinfo->codec->sc->dev, 5214 " Disabling unassociated" 5215 " pin nid %d.\n", 5216 w->nid); 5217 ); 5218 } 5219 } 5220 } 5221 do { 5222 done = 1; 5223 /* Disable and mute controls for disabled widgets. */ 5224 i = 0; 5225 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5226 if (ctl->enable == 0) 5227 continue; 5228 if (ctl->widget->enable == 0 || 5229 (ctl->childwidget != NULL && 5230 ctl->childwidget->enable == 0)) { 5231 ctl->forcemute = 1; 5232 ctl->muted = HDA_AMP_MUTE_ALL; 5233 ctl->left = 0; 5234 ctl->right = 0; 5235 ctl->enable = 0; 5236 if (ctl->ndir == HDA_CTL_IN) 5237 ctl->widget->connsenable[ctl->index] = 0; 5238 done = 0; 5239 HDA_BOOTHVERBOSE( 5240 device_printf(devinfo->codec->sc->dev, 5241 " Disabling ctl %d nid %d cnid %d due" 5242 " to disabled widget.\n", i, 5243 ctl->widget->nid, 5244 (ctl->childwidget != NULL)? 5245 ctl->childwidget->nid:-1); 5246 ); 5247 } 5248 } 5249 /* Disable useless widgets. */ 5250 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5251 w = hdac_widget_get(devinfo, i); 5252 if (w == NULL || w->enable == 0) 5253 continue; 5254 /* Disable inputs with disabled child widgets. */ 5255 for (j = 0; j < w->nconns; j++) { 5256 if (w->connsenable[j]) { 5257 cw = hdac_widget_get(devinfo, w->conns[j]); 5258 if (cw == NULL || cw->enable == 0) { 5259 w->connsenable[j] = 0; 5260 HDA_BOOTHVERBOSE( 5261 device_printf(devinfo->codec->sc->dev, 5262 " Disabling nid %d connection %d due" 5263 " to disabled child widget.\n", 5264 i, j); 5265 ); 5266 } 5267 } 5268 } 5269 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5270 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5271 continue; 5272 /* Disable mixers and selectors without inputs. */ 5273 found = 0; 5274 for (j = 0; j < w->nconns; j++) { 5275 if (w->connsenable[j]) { 5276 found = 1; 5277 break; 5278 } 5279 } 5280 if (found == 0) { 5281 w->enable = 0; 5282 done = 0; 5283 HDA_BOOTHVERBOSE( 5284 device_printf(devinfo->codec->sc->dev, 5285 " Disabling nid %d due to all it's" 5286 " inputs disabled.\n", w->nid); 5287 ); 5288 } 5289 /* Disable nodes without consumers. */ 5290 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5291 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5292 continue; 5293 found = 0; 5294 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5295 cw = hdac_widget_get(devinfo, k); 5296 if (cw == NULL || cw->enable == 0) 5297 continue; 5298 for (j = 0; j < cw->nconns; j++) { 5299 if (cw->connsenable[j] && cw->conns[j] == i) { 5300 found = 1; 5301 break; 5302 } 5303 } 5304 } 5305 if (found == 0) { 5306 w->enable = 0; 5307 done = 0; 5308 HDA_BOOTHVERBOSE( 5309 device_printf(devinfo->codec->sc->dev, 5310 " Disabling nid %d due to all it's" 5311 " consumers disabled.\n", w->nid); 5312 ); 5313 } 5314 } 5315 } while (done == 0); 5316 5317} 5318 5319static void 5320hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5321{ 5322 struct hdac_audio_as *as = devinfo->function.audio.as; 5323 struct hdac_widget *w, *cw; 5324 struct hdac_audio_ctl *ctl; 5325 int i, j, k; 5326 5327 /* Disable unassosiated widgets. */ 5328 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5329 w = hdac_widget_get(devinfo, i); 5330 if (w == NULL || w->enable == 0) 5331 continue; 5332 if (w->bindas == -1) { 5333 w->enable = 0; 5334 HDA_BOOTHVERBOSE( 5335 device_printf(devinfo->codec->sc->dev, 5336 " Disabling unassociated nid %d.\n", 5337 w->nid); 5338 ); 5339 } 5340 } 5341 /* Disable input connections on input pin and 5342 * output on output. */ 5343 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5344 w = hdac_widget_get(devinfo, i); 5345 if (w == NULL || w->enable == 0) 5346 continue; 5347 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5348 continue; 5349 if (w->bindas < 0) 5350 continue; 5351 if (as[w->bindas].dir == HDA_CTL_IN) { 5352 for (j = 0; j < w->nconns; j++) { 5353 if (w->connsenable[j] == 0) 5354 continue; 5355 w->connsenable[j] = 0; 5356 HDA_BOOTHVERBOSE( 5357 device_printf(devinfo->codec->sc->dev, 5358 " Disabling connection to input pin " 5359 "nid %d conn %d.\n", 5360 i, j); 5361 ); 5362 } 5363 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5364 HDA_CTL_IN, -1, 1); 5365 if (ctl && ctl->enable) { 5366 ctl->forcemute = 1; 5367 ctl->muted = HDA_AMP_MUTE_ALL; 5368 ctl->left = 0; 5369 ctl->right = 0; 5370 ctl->enable = 0; 5371 } 5372 } else { 5373 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5374 HDA_CTL_OUT, -1, 1); 5375 if (ctl && ctl->enable) { 5376 ctl->forcemute = 1; 5377 ctl->muted = HDA_AMP_MUTE_ALL; 5378 ctl->left = 0; 5379 ctl->right = 0; 5380 ctl->enable = 0; 5381 } 5382 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5383 cw = hdac_widget_get(devinfo, k); 5384 if (cw == NULL || cw->enable == 0) 5385 continue; 5386 for (j = 0; j < cw->nconns; j++) { 5387 if (cw->connsenable[j] && cw->conns[j] == i) { 5388 cw->connsenable[j] = 0; 5389 HDA_BOOTHVERBOSE( 5390 device_printf(devinfo->codec->sc->dev, 5391 " Disabling connection from output pin " 5392 "nid %d conn %d cnid %d.\n", 5393 k, j, i); 5394 ); 5395 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5396 cw->nconns > 1) 5397 continue; 5398 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5399 HDA_CTL_IN, j, 1); 5400 if (ctl && ctl->enable) { 5401 ctl->forcemute = 1; 5402 ctl->muted = HDA_AMP_MUTE_ALL; 5403 ctl->left = 0; 5404 ctl->right = 0; 5405 ctl->enable = 0; 5406 } 5407 } 5408 } 5409 } 5410 } 5411 } 5412} 5413 5414static void 5415hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5416{ 5417 struct hdac_audio_as *as = devinfo->function.audio.as; 5418 struct hdac_widget *w; 5419 int i, j; 5420 5421 /* On playback path we can safely disable all unseleted inputs. */ 5422 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5423 w = hdac_widget_get(devinfo, i); 5424 if (w == NULL || w->enable == 0) 5425 continue; 5426 if (w->nconns <= 1) 5427 continue; 5428 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5429 continue; 5430 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5431 continue; 5432 for (j = 0; j < w->nconns; j++) { 5433 if (w->connsenable[j] == 0) 5434 continue; 5435 if (w->selconn < 0 || w->selconn == j) 5436 continue; 5437 w->connsenable[j] = 0; 5438 HDA_BOOTHVERBOSE( 5439 device_printf(devinfo->codec->sc->dev, 5440 " Disabling unselected connection " 5441 "nid %d conn %d.\n", 5442 i, j); 5443 ); 5444 } 5445 } 5446} 5447 5448static void 5449hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5450{ 5451 struct hdac_widget *w, *cw; 5452 struct hdac_audio_ctl *ctl; 5453 int i, j; 5454 5455 /* Disable crossassociatement connections. */ 5456 /* ... using selectors */ 5457 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5458 w = hdac_widget_get(devinfo, i); 5459 if (w == NULL || w->enable == 0) 5460 continue; 5461 if (w->nconns <= 1) 5462 continue; 5463 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5464 continue; 5465 if (w->bindas == -2) 5466 continue; 5467 for (j = 0; j < w->nconns; j++) { 5468 if (w->connsenable[j] == 0) 5469 continue; 5470 cw = hdac_widget_get(devinfo, w->conns[j]); 5471 if (cw == NULL || w->enable == 0) 5472 continue; 5473 if (w->bindas == cw->bindas || cw->bindas == -2) 5474 continue; 5475 w->connsenable[j] = 0; 5476 HDA_BOOTHVERBOSE( 5477 device_printf(devinfo->codec->sc->dev, 5478 " Disabling crossassociatement connection " 5479 "nid %d conn %d cnid %d.\n", 5480 i, j, cw->nid); 5481 ); 5482 } 5483 } 5484 /* ... using controls */ 5485 i = 0; 5486 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5487 if (ctl->enable == 0 || ctl->childwidget == NULL) 5488 continue; 5489 if (ctl->widget->bindas == -2 || 5490 ctl->childwidget->bindas == -2) 5491 continue; 5492 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5493 ctl->forcemute = 1; 5494 ctl->muted = HDA_AMP_MUTE_ALL; 5495 ctl->left = 0; 5496 ctl->right = 0; 5497 ctl->enable = 0; 5498 if (ctl->ndir == HDA_CTL_IN) 5499 ctl->widget->connsenable[ctl->index] = 0; 5500 HDA_BOOTHVERBOSE( 5501 device_printf(devinfo->codec->sc->dev, 5502 " Disabling crossassociatement connection " 5503 "ctl %d nid %d cnid %d.\n", i, 5504 ctl->widget->nid, 5505 ctl->childwidget->nid); 5506 ); 5507 } 5508 } 5509 5510} 5511 5512#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5513 5514/* 5515 * Find controls to control amplification for source. 5516 */ 5517static int 5518hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5519 int ossdev, int ctlable, int depth, int need) 5520{ 5521 struct hdac_widget *w, *wc; 5522 struct hdac_audio_ctl *ctl; 5523 int i, j, conns = 0, rneed; 5524 5525 if (depth > HDA_PARSE_MAXDEPTH) 5526 return (need); 5527 5528 w = hdac_widget_get(devinfo, nid); 5529 if (w == NULL || w->enable == 0) 5530 return (need); 5531 5532 /* Count number of active inputs. */ 5533 if (depth > 0) { 5534 for (j = 0; j < w->nconns; j++) { 5535 if (w->connsenable[j]) 5536 conns++; 5537 } 5538 } 5539 5540 /* If this is not a first step - use input mixer. 5541 Pins have common input ctl so care must be taken. */ 5542 if (depth > 0 && ctlable && (conns == 1 || 5543 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5544 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5545 index, 1); 5546 if (ctl) { 5547 if (HDA_CTL_GIVE(ctl) & need) 5548 ctl->ossmask |= (1 << ossdev); 5549 else 5550 ctl->possmask |= (1 << ossdev); 5551 need &= ~HDA_CTL_GIVE(ctl); 5552 } 5553 } 5554 5555 /* If widget has own ossdev - not traverse it. 5556 It will be traversed on it's own. */ 5557 if (w->ossdev >= 0 && depth > 0) 5558 return (need); 5559 5560 /* We must not traverse pin */ 5561 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5562 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5563 depth > 0) 5564 return (need); 5565 5566 /* record that this widget exports such signal, */ 5567 w->ossmask |= (1 << ossdev); 5568 5569 /* If signals mixed, we can't assign controls farther. 5570 * Ignore this on depth zero. Caller must knows why. 5571 * Ignore this for static selectors if this input selected. 5572 */ 5573 if (conns > 1) 5574 ctlable = 0; 5575 5576 if (ctlable) { 5577 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5578 if (ctl) { 5579 if (HDA_CTL_GIVE(ctl) & need) 5580 ctl->ossmask |= (1 << ossdev); 5581 else 5582 ctl->possmask |= (1 << ossdev); 5583 need &= ~HDA_CTL_GIVE(ctl); 5584 } 5585 } 5586 5587 rneed = 0; 5588 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5589 wc = hdac_widget_get(devinfo, i); 5590 if (wc == NULL || wc->enable == 0) 5591 continue; 5592 for (j = 0; j < wc->nconns; j++) { 5593 if (wc->connsenable[j] && wc->conns[j] == nid) { 5594 rneed |= hdac_audio_ctl_source_amp(devinfo, 5595 wc->nid, j, ossdev, ctlable, depth + 1, need); 5596 } 5597 } 5598 } 5599 rneed &= need; 5600 5601 return (rneed); 5602} 5603 5604/* 5605 * Find controls to control amplification for destination. 5606 */ 5607static void 5608hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5609 int ossdev, int depth, int need) 5610{ 5611 struct hdac_audio_as *as = devinfo->function.audio.as; 5612 struct hdac_widget *w, *wc; 5613 struct hdac_audio_ctl *ctl; 5614 int i, j, consumers; 5615 5616 if (depth > HDA_PARSE_MAXDEPTH) 5617 return; 5618 5619 w = hdac_widget_get(devinfo, nid); 5620 if (w == NULL || w->enable == 0) 5621 return; 5622 5623 if (depth > 0) { 5624 /* If this node produce output for several consumers, 5625 we can't touch it. */ 5626 consumers = 0; 5627 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5628 wc = hdac_widget_get(devinfo, i); 5629 if (wc == NULL || wc->enable == 0) 5630 continue; 5631 for (j = 0; j < wc->nconns; j++) { 5632 if (wc->connsenable[j] && wc->conns[j] == nid) 5633 consumers++; 5634 } 5635 } 5636 /* The only exception is if real HP redirection is configured 5637 and this is a duplication point. 5638 XXX: Actually exception is not completely correct. 5639 XXX: Duplication point check is not perfect. */ 5640 if ((consumers == 2 && (w->bindas < 0 || 5641 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5642 (w->bindseqmask & (1 << 15)) == 0)) || 5643 consumers > 2) 5644 return; 5645 5646 /* Else use it's output mixer. */ 5647 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5648 HDA_CTL_OUT, -1, 1); 5649 if (ctl) { 5650 if (HDA_CTL_GIVE(ctl) & need) 5651 ctl->ossmask |= (1 << ossdev); 5652 else 5653 ctl->possmask |= (1 << ossdev); 5654 need &= ~HDA_CTL_GIVE(ctl); 5655 } 5656 } 5657 5658 /* We must not traverse pin */ 5659 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5660 depth > 0) 5661 return; 5662 5663 for (i = 0; i < w->nconns; i++) { 5664 int tneed = need; 5665 if (w->connsenable[i] == 0) 5666 continue; 5667 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5668 HDA_CTL_IN, i, 1); 5669 if (ctl) { 5670 if (HDA_CTL_GIVE(ctl) & tneed) 5671 ctl->ossmask |= (1 << ossdev); 5672 else 5673 ctl->possmask |= (1 << ossdev); 5674 tneed &= ~HDA_CTL_GIVE(ctl); 5675 } 5676 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5677 depth + 1, tneed); 5678 } 5679} 5680 5681/* 5682 * Assign OSS names to sound sources 5683 */ 5684static void 5685hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5686{ 5687 struct hdac_audio_as *as = devinfo->function.audio.as; 5688 struct hdac_widget *w; 5689 int i, j; 5690 int type = -1, use, used = 0; 5691 static const int types[7][13] = { 5692 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5693 SOUND_MIXER_LINE3, -1 }, /* line */ 5694 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5695 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5696 { SOUND_MIXER_CD, -1 }, /* cd */ 5697 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5698 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5699 -1 }, /* digital */ 5700 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5701 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5702 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5703 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5704 -1 } /* others */ 5705 }; 5706 5707 /* Surely known names */ 5708 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5709 w = hdac_widget_get(devinfo, i); 5710 if (w == NULL || w->enable == 0) 5711 continue; 5712 if (w->bindas == -1) 5713 continue; 5714 use = -1; 5715 switch (w->type) { 5716 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5717 if (as[w->bindas].dir == HDA_CTL_OUT) 5718 break; 5719 type = -1; 5720 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5721 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5722 type = 0; 5723 break; 5724 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5725 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5726 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5727 break; 5728 type = 1; 5729 break; 5730 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5731 type = 3; 5732 break; 5733 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5734 type = 4; 5735 break; 5736 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5737 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5738 type = 5; 5739 break; 5740 } 5741 if (type == -1) 5742 break; 5743 j = 0; 5744 while (types[type][j] >= 0 && 5745 (used & (1 << types[type][j])) != 0) { 5746 j++; 5747 } 5748 if (types[type][j] >= 0) 5749 use = types[type][j]; 5750 break; 5751 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5752 use = SOUND_MIXER_PCM; 5753 break; 5754 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5755 use = SOUND_MIXER_SPEAKER; 5756 break; 5757 default: 5758 break; 5759 } 5760 if (use >= 0) { 5761 w->ossdev = use; 5762 used |= (1 << use); 5763 } 5764 } 5765 /* Semi-known names */ 5766 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5767 w = hdac_widget_get(devinfo, i); 5768 if (w == NULL || w->enable == 0) 5769 continue; 5770 if (w->ossdev >= 0) 5771 continue; 5772 if (w->bindas == -1) 5773 continue; 5774 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5775 continue; 5776 if (as[w->bindas].dir == HDA_CTL_OUT) 5777 continue; 5778 type = -1; 5779 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5780 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5781 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5782 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5783 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5784 type = 0; 5785 break; 5786 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5787 type = 2; 5788 break; 5789 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5790 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5791 type = 5; 5792 break; 5793 } 5794 if (type == -1) 5795 break; 5796 j = 0; 5797 while (types[type][j] >= 0 && 5798 (used & (1 << types[type][j])) != 0) { 5799 j++; 5800 } 5801 if (types[type][j] >= 0) { 5802 w->ossdev = types[type][j]; 5803 used |= (1 << types[type][j]); 5804 } 5805 } 5806 /* Others */ 5807 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5808 w = hdac_widget_get(devinfo, i); 5809 if (w == NULL || w->enable == 0) 5810 continue; 5811 if (w->ossdev >= 0) 5812 continue; 5813 if (w->bindas == -1) 5814 continue; 5815 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5816 continue; 5817 if (as[w->bindas].dir == HDA_CTL_OUT) 5818 continue; 5819 j = 0; 5820 while (types[6][j] >= 0 && 5821 (used & (1 << types[6][j])) != 0) { 5822 j++; 5823 } 5824 if (types[6][j] >= 0) { 5825 w->ossdev = types[6][j]; 5826 used |= (1 << types[6][j]); 5827 } 5828 } 5829} 5830 5831static void 5832hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5833{ 5834 struct hdac_audio_as *as = devinfo->function.audio.as; 5835 int j, res; 5836 5837 /* Trace all associations in order of their numbers, */ 5838 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5839 if (as[j].enable == 0) 5840 continue; 5841 HDA_BOOTVERBOSE( 5842 device_printf(devinfo->codec->sc->dev, 5843 "Tracing association %d (%d)\n", j, as[j].index); 5844 ); 5845 if (as[j].dir == HDA_CTL_OUT) { 5846retry: 5847 res = hdac_audio_trace_as_out(devinfo, j, 0); 5848 if (res == 0 && as[j].hpredir >= 0 && 5849 as[j].fakeredir == 0) { 5850 /* If codec can't do analog HP redirection 5851 try to make it using one more DAC. */ 5852 as[j].fakeredir = 1; 5853 goto retry; 5854 } 5855 } else { 5856 res = hdac_audio_trace_as_in(devinfo, j); 5857 } 5858 if (res) { 5859 HDA_BOOTVERBOSE( 5860 device_printf(devinfo->codec->sc->dev, 5861 "Association %d (%d) trace succeded\n", 5862 j, as[j].index); 5863 ); 5864 } else { 5865 HDA_BOOTVERBOSE( 5866 device_printf(devinfo->codec->sc->dev, 5867 "Association %d (%d) trace failed\n", 5868 j, as[j].index); 5869 ); 5870 as[j].enable = 0; 5871 } 5872 } 5873 5874 /* Trace mixer and beeper pseudo associations. */ 5875 hdac_audio_trace_as_extra(devinfo); 5876} 5877 5878static void 5879hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5880{ 5881 struct hdac_audio_as *as = devinfo->function.audio.as; 5882 struct hdac_audio_ctl *ctl; 5883 struct hdac_widget *w; 5884 int i; 5885 5886 /* Assign mixers to the tree. */ 5887 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5888 w = hdac_widget_get(devinfo, i); 5889 if (w == NULL || w->enable == 0) 5890 continue; 5891 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5892 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5893 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5894 as[w->bindas].dir == HDA_CTL_IN)) { 5895 if (w->ossdev < 0) 5896 continue; 5897 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5898 w->ossdev, 1, 0, 1); 5899 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5900 if (w->ossdev < 0) 5901 continue; 5902 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5903 w->ossdev, 1, 0, 1)) { 5904 /* If we are unable to control input monitor 5905 as source - try to control it as destination. */ 5906 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5907 w->ossdev, 0, 1); 5908 } 5909 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5910 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5911 SOUND_MIXER_RECLEV, 0, 1); 5912 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5913 as[w->bindas].dir == HDA_CTL_OUT) { 5914 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5915 SOUND_MIXER_VOLUME, 0, 1); 5916 } 5917 } 5918 /* Treat unrequired as possible. */ 5919 i = 0; 5920 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5921 if (ctl->ossmask == 0) 5922 ctl->ossmask = ctl->possmask; 5923 } 5924} 5925 5926static void 5927hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5928{ 5929 struct hdac_audio_as *as = devinfo->function.audio.as; 5930 struct hdac_widget *w; 5931 uint32_t pincap; 5932 int i; 5933 5934 for (i = 0; i < devinfo->nodecnt; i++) { 5935 w = &devinfo->widget[i]; 5936 if (w == NULL) 5937 continue; 5938 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5939 continue; 5940 5941 pincap = w->wclass.pin.cap; 5942 5943 /* Disable everything. */ 5944 w->wclass.pin.ctrl &= ~( 5945 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5946 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5947 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5948 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5949 5950 if (w->enable == 0 || 5951 w->bindas < 0 || as[w->bindas].enable == 0) { 5952 /* Pin is unused so left it disabled. */ 5953 continue; 5954 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5955 /* Input pin, configure for input. */ 5956 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5957 w->wclass.pin.ctrl |= 5958 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5959 5960 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5961 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5962 w->wclass.pin.ctrl |= 5963 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5964 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5965 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5966 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5967 w->wclass.pin.ctrl |= 5968 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5969 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5970 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5971 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5972 w->wclass.pin.ctrl |= 5973 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5974 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5975 } else { 5976 /* Output pin, configure for output. */ 5977 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5978 w->wclass.pin.ctrl |= 5979 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5980 5981 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5982 (w->wclass.pin.config & 5983 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5984 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5985 w->wclass.pin.ctrl |= 5986 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5987 5988 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5989 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5990 w->wclass.pin.ctrl |= 5991 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5992 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5993 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5994 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5995 w->wclass.pin.ctrl |= 5996 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5997 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5998 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5999 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6000 w->wclass.pin.ctrl |= 6001 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6002 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6003 } 6004 } 6005} 6006 6007static void 6008hdac_audio_commit(struct hdac_devinfo *devinfo) 6009{ 6010 struct hdac_softc *sc = devinfo->codec->sc; 6011 struct hdac_widget *w; 6012 nid_t cad; 6013 uint32_t gdata, gmask, gdir; 6014 int commitgpio, numgpio; 6015 int i; 6016 6017 cad = devinfo->codec->cad; 6018 6019 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6020 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6021 0x7e7, 0), cad); 6022 6023 gdata = 0; 6024 gmask = 0; 6025 gdir = 0; 6026 commitgpio = 0; 6027 6028 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6029 devinfo->function.audio.gpio); 6030 6031 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6032 commitgpio = (numgpio > 0) ? 1 : 0; 6033 else { 6034 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6035 if (!(devinfo->function.audio.quirks & 6036 (1 << i))) 6037 continue; 6038 if (commitgpio == 0) { 6039 commitgpio = 1; 6040 HDA_BOOTVERBOSE( 6041 gdata = hdac_command(sc, 6042 HDA_CMD_GET_GPIO_DATA(cad, 6043 devinfo->nid), cad); 6044 gmask = hdac_command(sc, 6045 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6046 devinfo->nid), cad); 6047 gdir = hdac_command(sc, 6048 HDA_CMD_GET_GPIO_DIRECTION(cad, 6049 devinfo->nid), cad); 6050 device_printf(sc->dev, 6051 "GPIO init: data=0x%08x " 6052 "mask=0x%08x dir=0x%08x\n", 6053 gdata, gmask, gdir); 6054 gdata = 0; 6055 gmask = 0; 6056 gdir = 0; 6057 ); 6058 } 6059 gdata |= 1 << i; 6060 gmask |= 1 << i; 6061 gdir |= 1 << i; 6062 } 6063 } 6064 6065 if (commitgpio != 0) { 6066 HDA_BOOTVERBOSE( 6067 device_printf(sc->dev, 6068 "GPIO commit: data=0x%08x mask=0x%08x " 6069 "dir=0x%08x\n", 6070 gdata, gmask, gdir); 6071 ); 6072 hdac_command(sc, 6073 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6074 gmask), cad); 6075 hdac_command(sc, 6076 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6077 gdir), cad); 6078 hdac_command(sc, 6079 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6080 gdata), cad); 6081 } 6082 6083 for (i = 0; i < devinfo->nodecnt; i++) { 6084 w = &devinfo->widget[i]; 6085 if (w == NULL) 6086 continue; 6087 if (w->selconn == -1) 6088 w->selconn = 0; 6089 if (w->nconns > 0) 6090 hdac_widget_connection_select(w, w->selconn); 6091 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6092 hdac_command(sc, 6093 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6094 w->wclass.pin.ctrl), cad); 6095 } 6096 if (w->param.eapdbtl != HDAC_INVALID) { 6097 uint32_t val; 6098 6099 val = w->param.eapdbtl; 6100 if (devinfo->function.audio.quirks & 6101 HDA_QUIRK_EAPDINV) 6102 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6103 hdac_command(sc, 6104 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6105 val), cad); 6106 6107 } 6108 } 6109} 6110 6111static void 6112hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6113{ 6114 struct hdac_audio_ctl *ctl; 6115 int i, z; 6116 6117 i = 0; 6118 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6119 if (ctl->enable == 0) { 6120 /* Mute disabled controls. */ 6121 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6122 continue; 6123 } 6124 /* Init controls to 0dB amplification. */ 6125 z = ctl->offset; 6126 if (z > ctl->step) 6127 z = ctl->step; 6128 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6129 } 6130} 6131 6132static void 6133hdac_powerup(struct hdac_devinfo *devinfo) 6134{ 6135 struct hdac_softc *sc = devinfo->codec->sc; 6136 nid_t cad = devinfo->codec->cad; 6137 int i; 6138 6139 hdac_command(sc, 6140 HDA_CMD_SET_POWER_STATE(cad, 6141 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6142 cad); 6143 DELAY(100); 6144 6145 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6146 hdac_command(sc, 6147 HDA_CMD_SET_POWER_STATE(cad, 6148 i, HDA_CMD_POWER_STATE_D0), 6149 cad); 6150 } 6151 DELAY(1000); 6152} 6153 6154static int 6155hdac_pcmchannel_setup(struct hdac_chan *ch) 6156{ 6157 struct hdac_devinfo *devinfo = ch->devinfo; 6158 struct hdac_audio_as *as = devinfo->function.audio.as; 6159 struct hdac_widget *w; 6160 uint32_t cap, fmtcap, pcmcap; 6161 int i, j, ret, max; 6162 6163 ch->caps = hdac_caps; 6164 ch->caps.fmtlist = ch->fmtlist; 6165 ch->bit16 = 1; 6166 ch->bit32 = 0; 6167 ch->pcmrates[0] = 48000; 6168 ch->pcmrates[1] = 0; 6169 6170 ret = 0; 6171 fmtcap = devinfo->function.audio.supp_stream_formats; 6172 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6173 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6174 6175 for (i = 0; i < 16 && ret < max; i++) { 6176 /* Check as is correct */ 6177 if (ch->as < 0) 6178 break; 6179 /* Cound only present DACs */ 6180 if (as[ch->as].dacs[i] <= 0) 6181 continue; 6182 /* Ignore duplicates */ 6183 for (j = 0; j < ret; j++) { 6184 if (ch->io[j] == as[ch->as].dacs[i]) 6185 break; 6186 } 6187 if (j < ret) 6188 continue; 6189 6190 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6191 if (w == NULL || w->enable == 0) 6192 continue; 6193 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6194 continue; 6195 cap = w->param.supp_stream_formats; 6196 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6197 }*/ 6198 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6199 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6200 continue; 6201 /* Many codec does not declare AC3 support on SPDIF. 6202 I don't beleave that they doesn't support it! */ 6203 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6204 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6205 if (ret == 0) { 6206 fmtcap = cap; 6207 pcmcap = w->param.supp_pcm_size_rate; 6208 } else { 6209 fmtcap &= cap; 6210 pcmcap &= w->param.supp_pcm_size_rate; 6211 } 6212 ch->io[ret++] = as[ch->as].dacs[i]; 6213 } 6214 ch->io[ret] = -1; 6215 6216 ch->supp_stream_formats = fmtcap; 6217 ch->supp_pcm_size_rate = pcmcap; 6218 6219 /* 6220 * 8bit = 0 6221 * 16bit = 1 6222 * 20bit = 2 6223 * 24bit = 3 6224 * 32bit = 4 6225 */ 6226 if (ret > 0) { 6227 i = 0; 6228 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6229 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6230 ch->bit16 = 1; 6231 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6232 ch->bit16 = 0; 6233 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6234 ch->bit32 = 4; 6235 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6236 ch->bit32 = 3; 6237 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6238 ch->bit32 = 2; 6239 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6240 ch->fmtlist[i++] = AFMT_S16_LE; 6241 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6242 if (ch->bit32 > 0) { 6243 if (!(devinfo->function.audio.quirks & 6244 HDA_QUIRK_FORCESTEREO)) 6245 ch->fmtlist[i++] = AFMT_S32_LE; 6246 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6247 } 6248 } 6249 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6250 ch->fmtlist[i++] = AFMT_AC3; 6251 } 6252 ch->fmtlist[i] = 0; 6253 i = 0; 6254 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6255 ch->pcmrates[i++] = 8000; 6256 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6257 ch->pcmrates[i++] = 11025; 6258 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6259 ch->pcmrates[i++] = 16000; 6260 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6261 ch->pcmrates[i++] = 22050; 6262 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6263 ch->pcmrates[i++] = 32000; 6264 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6265 ch->pcmrates[i++] = 44100; 6266 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6267 ch->pcmrates[i++] = 48000; 6268 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6269 ch->pcmrates[i++] = 88200; 6270 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6271 ch->pcmrates[i++] = 96000; 6272 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6273 ch->pcmrates[i++] = 176400; 6274 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6275 ch->pcmrates[i++] = 192000; 6276 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6277 ch->pcmrates[i] = 0; 6278 if (i > 0) { 6279 ch->caps.minspeed = ch->pcmrates[0]; 6280 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6281 } 6282 } 6283 6284 return (ret); 6285} 6286 6287static void 6288hdac_create_pcms(struct hdac_devinfo *devinfo) 6289{ 6290 struct hdac_softc *sc = devinfo->codec->sc; 6291 struct hdac_audio_as *as = devinfo->function.audio.as; 6292 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6293 6294 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6295 if (as[i].enable == 0) 6296 continue; 6297 if (as[i].dir == HDA_CTL_IN) { 6298 if (as[i].digital) 6299 drdev++; 6300 else 6301 ardev++; 6302 } else { 6303 if (as[i].digital) 6304 dpdev++; 6305 else 6306 apdev++; 6307 } 6308 } 6309 devinfo->function.audio.num_devs = 6310 max(ardev, apdev) + max(drdev, dpdev); 6311 devinfo->function.audio.devs = 6312 (struct hdac_pcm_devinfo *)malloc( 6313 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6314 M_HDAC, M_ZERO | M_NOWAIT); 6315 if (devinfo->function.audio.devs == NULL) { 6316 device_printf(sc->dev, 6317 "Unable to allocate memory for devices\n"); 6318 return; 6319 } 6320 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6321 devinfo->function.audio.devs[i].index = i; 6322 devinfo->function.audio.devs[i].devinfo = devinfo; 6323 devinfo->function.audio.devs[i].play = -1; 6324 devinfo->function.audio.devs[i].rec = -1; 6325 devinfo->function.audio.devs[i].digital = 2; 6326 } 6327 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6328 if (as[i].enable == 0) 6329 continue; 6330 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6331 if (devinfo->function.audio.devs[j].digital != 2 && 6332 devinfo->function.audio.devs[j].digital != 6333 as[i].digital) 6334 continue; 6335 if (as[i].dir == HDA_CTL_IN) { 6336 if (devinfo->function.audio.devs[j].rec >= 0) 6337 continue; 6338 devinfo->function.audio.devs[j].rec 6339 = as[i].chan; 6340 } else { 6341 if (devinfo->function.audio.devs[j].play >= 0) 6342 continue; 6343 devinfo->function.audio.devs[j].play 6344 = as[i].chan; 6345 } 6346 sc->chans[as[i].chan].pdevinfo = 6347 &devinfo->function.audio.devs[j]; 6348 devinfo->function.audio.devs[j].digital = 6349 as[i].digital; 6350 break; 6351 } 6352 } 6353 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6354 struct hdac_pcm_devinfo *pdevinfo = 6355 &devinfo->function.audio.devs[i]; 6356 pdevinfo->dev = 6357 device_add_child(sc->dev, "pcm", -1); 6358 device_set_ivars(pdevinfo->dev, 6359 (void *)pdevinfo); 6360 } 6361} 6362 6363static void 6364hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6365{ 6366 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6367 struct hdac_audio_ctl *ctl; 6368 struct hdac_softc *sc = devinfo->codec->sc; 6369 char buf[64]; 6370 int i, j, printed; 6371 6372 if (flag == 0) { 6373 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6374 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6375 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6376 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6377 } 6378 6379 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6380 if ((flag & (1 << j)) == 0) 6381 continue; 6382 i = 0; 6383 printed = 0; 6384 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6385 if (ctl->enable == 0 || 6386 ctl->widget->enable == 0) 6387 continue; 6388 if (!((pdevinfo->play >= 0 && 6389 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6390 (pdevinfo->rec >= 0 && 6391 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6392 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6393 continue; 6394 if ((ctl->ossmask & (1 << j)) == 0) 6395 continue; 6396 6397 if (printed == 0) { 6398 device_printf(pdevinfo->dev, "\n"); 6399 if (banner != NULL) { 6400 device_printf(pdevinfo->dev, "%s", banner); 6401 } else { 6402 device_printf(pdevinfo->dev, "Unknown Ctl"); 6403 } 6404 printf(" (OSS: %s)\n", 6405 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6406 buf, sizeof(buf))); 6407 device_printf(pdevinfo->dev, " |\n"); 6408 printed = 1; 6409 } 6410 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6411 ctl->widget->nid, 6412 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6413 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6414 printf(" %2d): ", ctl->index); 6415 else 6416 printf("): "); 6417 if (ctl->step > 0) { 6418 printf("%+d/%+ddB (%d steps)%s\n", 6419 (0 - ctl->offset) * (ctl->size + 1) / 4, 6420 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6421 ctl->step + 1, 6422 ctl->mute?" + mute":""); 6423 } else 6424 printf("%s\n", ctl->mute?"mute":""); 6425 } 6426 } 6427} 6428 6429static void 6430hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6431{ 6432 uint32_t cap; 6433 6434 cap = fcap; 6435 if (cap != 0) { 6436 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6437 device_printf(dev, " "); 6438 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6439 printf(" AC3"); 6440 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6441 printf(" FLOAT32"); 6442 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6443 printf(" PCM"); 6444 printf("\n"); 6445 } 6446 cap = pcmcap; 6447 if (cap != 0) { 6448 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6449 device_printf(dev, " "); 6450 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6451 printf(" 8"); 6452 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6453 printf(" 16"); 6454 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6455 printf(" 20"); 6456 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6457 printf(" 24"); 6458 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6459 printf(" 32"); 6460 printf(" bits,"); 6461 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6462 printf(" 8"); 6463 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6464 printf(" 11"); 6465 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6466 printf(" 16"); 6467 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6468 printf(" 22"); 6469 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6470 printf(" 32"); 6471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6472 printf(" 44"); 6473 printf(" 48"); 6474 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6475 printf(" 88"); 6476 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6477 printf(" 96"); 6478 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6479 printf(" 176"); 6480 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6481 printf(" 192"); 6482 printf(" KHz\n"); 6483 } 6484} 6485 6486static void 6487hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6488{ 6489 uint32_t pincap; 6490 6491 pincap = w->wclass.pin.cap; 6492 6493 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6494 device_printf(sc->dev, " "); 6495 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6496 printf(" ISC"); 6497 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6498 printf(" TRQD"); 6499 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6500 printf(" PDC"); 6501 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6502 printf(" HP"); 6503 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6504 printf(" OUT"); 6505 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6506 printf(" IN"); 6507 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6508 printf(" BAL"); 6509 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6510 printf(" VREF["); 6511 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6512 printf(" 50"); 6513 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6514 printf(" 80"); 6515 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6516 printf(" 100"); 6517 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6518 printf(" GROUND"); 6519 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6520 printf(" HIZ"); 6521 printf(" ]"); 6522 } 6523 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6524 printf(" EAPD"); 6525 printf("\n"); 6526 device_printf(sc->dev, " Pin config: 0x%08x\n", 6527 w->wclass.pin.config); 6528 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6529 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6530 printf(" HP"); 6531 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6532 printf(" IN"); 6533 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6534 printf(" OUT"); 6535 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6536 printf(" VREFs"); 6537 printf("\n"); 6538} 6539 6540static void 6541hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6542{ 6543 struct hdac_softc *sc = w->devinfo->codec->sc; 6544 6545 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6546 "jack %2d loc %2d color %7s misc %d%s\n", 6547 w->nid, conf, 6548 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6549 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6550 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6551 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6552 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6553 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6554 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6555 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6556 (w->enable == 0)?" [DISABLED]":""); 6557} 6558 6559static void 6560hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6561{ 6562 struct hdac_widget *w; 6563 int i; 6564 6565 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6566 w = hdac_widget_get(devinfo, i); 6567 if (w == NULL) 6568 continue; 6569 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6570 continue; 6571 hdac_dump_pin_config(w, w->wclass.pin.config); 6572 } 6573} 6574 6575static void 6576hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6577{ 6578 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6579 device_printf(sc->dev, " " 6580 "mute=%d step=%d size=%d offset=%d\n", 6581 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6582 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6583 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6584 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6585} 6586 6587static void 6588hdac_dump_nodes(struct hdac_devinfo *devinfo) 6589{ 6590 struct hdac_softc *sc = devinfo->codec->sc; 6591 static char *ossname[] = SOUND_DEVICE_NAMES; 6592 struct hdac_widget *w, *cw; 6593 char buf[64]; 6594 int i, j; 6595 6596 device_printf(sc->dev, "\n"); 6597 device_printf(sc->dev, "Default Parameter\n"); 6598 device_printf(sc->dev, "-----------------\n"); 6599 hdac_dump_audio_formats(sc->dev, 6600 devinfo->function.audio.supp_stream_formats, 6601 devinfo->function.audio.supp_pcm_size_rate); 6602 device_printf(sc->dev, " IN amp: 0x%08x\n", 6603 devinfo->function.audio.inamp_cap); 6604 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6605 devinfo->function.audio.outamp_cap); 6606 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6607 w = hdac_widget_get(devinfo, i); 6608 if (w == NULL) { 6609 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6610 continue; 6611 } 6612 device_printf(sc->dev, "\n"); 6613 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6614 (w->enable == 0) ? " [DISABLED]" : ""); 6615 device_printf(sc->dev, " Name: %s\n", w->name); 6616 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6617 w->param.widget_cap); 6618 if (w->param.widget_cap & 0x0ee1) { 6619 device_printf(sc->dev, " "); 6620 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6621 printf(" LRSWAP"); 6622 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6623 printf(" PWR"); 6624 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6625 printf(" DIGITAL"); 6626 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6627 printf(" UNSOL"); 6628 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6629 printf(" PROC"); 6630 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6631 printf(" STRIPE"); 6632 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6633 printf(" STEREO"); 6634 printf("\n"); 6635 } 6636 if (w->bindas != -1) { 6637 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6638 w->bindas, w->bindseqmask); 6639 } 6640 if (w->ossmask != 0 || w->ossdev >= 0) { 6641 device_printf(sc->dev, " OSS: %s", 6642 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6643 if (w->ossdev >= 0) 6644 printf(" (%s)", ossname[w->ossdev]); 6645 printf("\n"); 6646 } 6647 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6648 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6649 hdac_dump_audio_formats(sc->dev, 6650 w->param.supp_stream_formats, 6651 w->param.supp_pcm_size_rate); 6652 } else if (w->type == 6653 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6654 hdac_dump_pin(sc, w); 6655 if (w->param.eapdbtl != HDAC_INVALID) 6656 device_printf(sc->dev, " EAPD: 0x%08x\n", 6657 w->param.eapdbtl); 6658 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6659 w->param.outamp_cap != 0) 6660 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6661 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6662 w->param.inamp_cap != 0) 6663 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6664 if (w->nconns > 0) { 6665 device_printf(sc->dev, " connections: %d\n", w->nconns); 6666 device_printf(sc->dev, " |\n"); 6667 } 6668 for (j = 0; j < w->nconns; j++) { 6669 cw = hdac_widget_get(devinfo, w->conns[j]); 6670 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6671 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6672 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6673 if (cw == NULL) 6674 printf(" [UNKNOWN]"); 6675 else if (cw->enable == 0) 6676 printf(" [DISABLED]"); 6677 if (w->nconns > 1 && w->selconn == j && w->type != 6678 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6679 printf(" (selected)"); 6680 printf("\n"); 6681 } 6682 } 6683 6684} 6685 6686static void 6687hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6688{ 6689 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6690 struct hdac_widget *w, *cw; 6691 char buf[64]; 6692 int i, printed = 0; 6693 6694 if (depth > HDA_PARSE_MAXDEPTH) 6695 return; 6696 6697 w = hdac_widget_get(devinfo, nid); 6698 if (w == NULL || w->enable == 0) 6699 return; 6700 6701 if (depth == 0) 6702 device_printf(pdevinfo->dev, "%*s", 4, ""); 6703 else 6704 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6705 printf("nid=%d [%s]", w->nid, w->name); 6706 6707 if (depth > 0) { 6708 if (w->ossmask == 0) { 6709 printf("\n"); 6710 return; 6711 } 6712 printf(" [src: %s]", 6713 hdac_audio_ctl_ossmixer_mask2allname( 6714 w->ossmask, buf, sizeof(buf))); 6715 if (w->ossdev >= 0) { 6716 printf("\n"); 6717 return; 6718 } 6719 } 6720 printf("\n"); 6721 6722 for (i = 0; i < w->nconns; i++) { 6723 if (w->connsenable[i] == 0) 6724 continue; 6725 cw = hdac_widget_get(devinfo, w->conns[i]); 6726 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6727 continue; 6728 if (printed == 0) { 6729 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6730 printed = 1; 6731 } 6732 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6733 } 6734 6735} 6736 6737static void 6738hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6739{ 6740 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6741 struct hdac_softc *sc = devinfo->codec->sc; 6742 struct hdac_widget *w; 6743 int i, printed = 0; 6744 6745 if (pdevinfo->play < 0) 6746 return; 6747 6748 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6749 w = hdac_widget_get(devinfo, i); 6750 if (w == NULL || w->enable == 0) 6751 continue; 6752 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6753 continue; 6754 if (w->bindas != sc->chans[pdevinfo->play].as) 6755 continue; 6756 if (printed == 0) { 6757 printed = 1; 6758 device_printf(pdevinfo->dev, "\n"); 6759 device_printf(pdevinfo->dev, "Playback:\n"); 6760 } 6761 device_printf(pdevinfo->dev, "\n"); 6762 hdac_dump_dst_nid(pdevinfo, i, 0); 6763 } 6764} 6765 6766static void 6767hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6768{ 6769 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6770 struct hdac_softc *sc = devinfo->codec->sc; 6771 struct hdac_widget *w; 6772 int i; 6773 int printed = 0; 6774 6775 if (pdevinfo->rec < 0) 6776 return; 6777 6778 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6779 w = hdac_widget_get(devinfo, i); 6780 if (w == NULL || w->enable == 0) 6781 continue; 6782 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6783 continue; 6784 if (w->bindas != sc->chans[pdevinfo->rec].as) 6785 continue; 6786 if (printed == 0) { 6787 printed = 1; 6788 device_printf(pdevinfo->dev, "\n"); 6789 device_printf(pdevinfo->dev, "Record:\n"); 6790 } 6791 device_printf(pdevinfo->dev, "\n"); 6792 hdac_dump_dst_nid(pdevinfo, i, 0); 6793 } 6794} 6795 6796static void 6797hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6798{ 6799 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6800 struct hdac_widget *w; 6801 int i; 6802 int printed = 0; 6803 6804 if (pdevinfo->index != 0) 6805 return; 6806 6807 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6808 w = hdac_widget_get(devinfo, i); 6809 if (w == NULL || w->enable == 0) 6810 continue; 6811 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6812 continue; 6813 if (printed == 0) { 6814 printed = 1; 6815 device_printf(pdevinfo->dev, "\n"); 6816 device_printf(pdevinfo->dev, "Input Mix:\n"); 6817 } 6818 device_printf(pdevinfo->dev, "\n"); 6819 hdac_dump_dst_nid(pdevinfo, i, 0); 6820 } 6821} 6822 6823static void 6824hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6825{ 6826 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6827 nid_t *nids; 6828 int i; 6829 6830 if (pdevinfo->play >= 0) { 6831 i = pdevinfo->play; 6832 device_printf(pdevinfo->dev, "\n"); 6833 device_printf(pdevinfo->dev, "Playback:\n"); 6834 device_printf(pdevinfo->dev, "\n"); 6835 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6836 sc->chans[i].supp_pcm_size_rate); 6837 device_printf(pdevinfo->dev, " DAC:"); 6838 for (nids = sc->chans[i].io; *nids != -1; nids++) 6839 printf(" %d", *nids); 6840 printf("\n"); 6841 } 6842 if (pdevinfo->rec >= 0) { 6843 i = pdevinfo->rec; 6844 device_printf(pdevinfo->dev, "\n"); 6845 device_printf(pdevinfo->dev, "Record:\n"); 6846 device_printf(pdevinfo->dev, "\n"); 6847 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6848 sc->chans[i].supp_pcm_size_rate); 6849 device_printf(pdevinfo->dev, " ADC:"); 6850 for (nids = sc->chans[i].io; *nids != -1; nids++) 6851 printf(" %d", *nids); 6852 printf("\n"); 6853 } 6854} 6855 6856static void 6857hdac_release_resources(struct hdac_softc *sc) 6858{ 6859 int i, j; 6860 6861 if (sc == NULL) 6862 return; 6863 6864 hdac_lock(sc); 6865 sc->polling = 0; 6866 sc->poll_ival = 0; 6867 callout_stop(&sc->poll_hda); 6868 callout_stop(&sc->poll_hdac); 6869 callout_stop(&sc->poll_jack); 6870 hdac_reset(sc, 0); 6871 hdac_unlock(sc); 6872 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6873 callout_drain(&sc->poll_hda); 6874 callout_drain(&sc->poll_hdac); 6875 callout_drain(&sc->poll_jack); 6876 6877 hdac_irq_free(sc); 6878 6879 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6880 if (sc->codecs[i] == NULL) 6881 continue; 6882 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6883 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6884 if (sc->codecs[i]->fgs[j].node_type == 6885 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6886 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6887 M_HDAC); 6888 free(sc->codecs[i]->fgs[j].function.audio.as, 6889 M_HDAC); 6890 free(sc->codecs[i]->fgs[j].function.audio.devs, 6891 M_HDAC); 6892 } 6893 } 6894 free(sc->codecs[i]->fgs, M_HDAC); 6895 free(sc->codecs[i], M_HDAC); 6896 sc->codecs[i] = NULL; 6897 } 6898 6899 hdac_dma_free(sc, &sc->pos_dma); 6900 hdac_dma_free(sc, &sc->rirb_dma); 6901 hdac_dma_free(sc, &sc->corb_dma); 6902 for (i = 0; i < sc->num_chans; i++) { 6903 if (sc->chans[i].blkcnt > 0) 6904 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6905 } 6906 free(sc->chans, M_HDAC); 6907 if (sc->chan_dmat != NULL) { 6908 bus_dma_tag_destroy(sc->chan_dmat); 6909 sc->chan_dmat = NULL; 6910 } 6911 hdac_mem_free(sc); 6912 snd_mtxfree(sc->lock); 6913} 6914 6915/* This function surely going to make its way into upper level someday. */ 6916static void 6917hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6918{ 6919 const char *res = NULL; 6920 int i = 0, j, k, len, inv; 6921 6922 if (on != NULL) 6923 *on = 0; 6924 if (off != NULL) 6925 *off = 0; 6926 if (sc == NULL) 6927 return; 6928 if (resource_string_value(device_get_name(sc->dev), 6929 device_get_unit(sc->dev), "config", &res) != 0) 6930 return; 6931 if (!(res != NULL && strlen(res) > 0)) 6932 return; 6933 HDA_BOOTVERBOSE( 6934 device_printf(sc->dev, "HDA Config:"); 6935 ); 6936 for (;;) { 6937 while (res[i] != '\0' && 6938 (res[i] == ',' || isspace(res[i]) != 0)) 6939 i++; 6940 if (res[i] == '\0') { 6941 HDA_BOOTVERBOSE( 6942 printf("\n"); 6943 ); 6944 return; 6945 } 6946 j = i; 6947 while (res[j] != '\0' && 6948 !(res[j] == ',' || isspace(res[j]) != 0)) 6949 j++; 6950 len = j - i; 6951 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6952 inv = 2; 6953 else 6954 inv = 0; 6955 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6956 if (strncmp(res + i + inv, 6957 hdac_quirks_tab[k].key, len - inv) != 0) 6958 continue; 6959 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6960 break; 6961 HDA_BOOTVERBOSE( 6962 printf(" %s%s", (inv != 0) ? "no" : "", 6963 hdac_quirks_tab[k].key); 6964 ); 6965 if (inv == 0 && on != NULL) 6966 *on |= hdac_quirks_tab[k].value; 6967 else if (inv != 0 && off != NULL) 6968 *off |= hdac_quirks_tab[k].value; 6969 break; 6970 } 6971 i = j; 6972 } 6973} 6974 6975#ifdef SND_DYNSYSCTL 6976static int 6977sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6978{ 6979 struct hdac_softc *sc; 6980 device_t dev; 6981 uint32_t ctl; 6982 int err, val; 6983 6984 dev = oidp->oid_arg1; 6985 sc = device_get_softc(dev); 6986 if (sc == NULL) 6987 return (EINVAL); 6988 hdac_lock(sc); 6989 val = sc->polling; 6990 hdac_unlock(sc); 6991 err = sysctl_handle_int(oidp, &val, 0, req); 6992 6993 if (err != 0 || req->newptr == NULL) 6994 return (err); 6995 if (val < 0 || val > 1) 6996 return (EINVAL); 6997 6998 hdac_lock(sc); 6999 if (val != sc->polling) { 7000 if (val == 0) { 7001 callout_stop(&sc->poll_hda); 7002 callout_stop(&sc->poll_hdac); 7003 hdac_unlock(sc); 7004 callout_drain(&sc->poll_hda); 7005 callout_drain(&sc->poll_hdac); 7006 hdac_lock(sc); 7007 sc->polling = 0; 7008 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7009 ctl |= HDAC_INTCTL_GIE; 7010 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7011 } else { 7012 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7013 ctl &= ~HDAC_INTCTL_GIE; 7014 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7015 hdac_unlock(sc); 7016 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7017 hdac_lock(sc); 7018 sc->polling = 1; 7019 hdac_poll_reinit(sc); 7020 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7021 } 7022 } 7023 hdac_unlock(sc); 7024 7025 return (err); 7026} 7027 7028static int 7029sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7030{ 7031 struct hdac_softc *sc; 7032 device_t dev; 7033 int err, val; 7034 7035 dev = oidp->oid_arg1; 7036 sc = device_get_softc(dev); 7037 if (sc == NULL) 7038 return (EINVAL); 7039 hdac_lock(sc); 7040 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7041 hdac_unlock(sc); 7042 err = sysctl_handle_int(oidp, &val, 0, req); 7043 7044 if (err != 0 || req->newptr == NULL) 7045 return (err); 7046 7047 if (val < 1) 7048 val = 1; 7049 if (val > 5000) 7050 val = 5000; 7051 val = ((uint64_t)val * hz) / 1000; 7052 if (val < 1) 7053 val = 1; 7054 if (val > (hz * 5)) 7055 val = hz * 5; 7056 7057 hdac_lock(sc); 7058 sc->poll_ival = val; 7059 hdac_unlock(sc); 7060 7061 return (err); 7062} 7063 7064static int 7065sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7066{ 7067 struct hdac_softc *sc; 7068 struct hdac_codec *codec; 7069 struct hdac_devinfo *devinfo; 7070 struct hdac_widget *w; 7071 device_t dev; 7072 uint32_t res, pincap, delay; 7073 int codec_index, fg_index; 7074 int i, err, val; 7075 nid_t cad; 7076 7077 dev = oidp->oid_arg1; 7078 sc = device_get_softc(dev); 7079 if (sc == NULL) 7080 return (EINVAL); 7081 val = 0; 7082 err = sysctl_handle_int(oidp, &val, 0, req); 7083 if (err != 0 || req->newptr == NULL || val == 0) 7084 return (err); 7085 7086 /* XXX: Temporary. For debugging. */ 7087 if (val == 100) { 7088 hdac_suspend(dev); 7089 return (0); 7090 } else if (val == 101) { 7091 hdac_resume(dev); 7092 return (0); 7093 } 7094 7095 hdac_lock(sc); 7096 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7097 codec = sc->codecs[codec_index]; 7098 if (codec == NULL) 7099 continue; 7100 cad = codec->cad; 7101 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7102 devinfo = &codec->fgs[fg_index]; 7103 if (devinfo->node_type != 7104 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7105 continue; 7106 7107 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7108 codec_index, devinfo->nid); 7109 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7110 w = hdac_widget_get(devinfo, i); 7111 if (w == NULL || w->type != 7112 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7113 continue; 7114 hdac_dump_pin_config(w, w->wclass.pin.config); 7115 pincap = w->wclass.pin.cap; 7116 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7117 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7118 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7119 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7120 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7121 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7122 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7123 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7124 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7125 delay = 0; 7126 hdac_command(sc, 7127 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7128 do { 7129 res = hdac_command(sc, 7130 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7131 if (res != 0x7fffffff && res != 0xffffffff) 7132 break; 7133 DELAY(10); 7134 } while (++delay < 10000); 7135 } else { 7136 delay = 0; 7137 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7138 w->nid), cad); 7139 } 7140 printf(" Sense: 0x%08x", res); 7141 if (delay > 0) 7142 printf(" delay %dus", delay * 10); 7143 } 7144 printf("\n"); 7145 } 7146 device_printf(dev, 7147 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7148 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7149 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7150 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7151 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7152 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7153 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7154 device_printf(dev, " GPI:"); 7155 res = hdac_command(sc, 7156 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7157 printf(" data=0x%08x", res); 7158 res = hdac_command(sc, 7159 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7160 cad); 7161 printf(" wake=0x%08x", res); 7162 res = hdac_command(sc, 7163 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7164 cad); 7165 printf(" unsol=0x%08x", res); 7166 res = hdac_command(sc, 7167 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7168 printf(" sticky=0x%08x\n", res); 7169 } 7170 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7171 device_printf(dev, " GPO:"); 7172 res = hdac_command(sc, 7173 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7174 printf(" data=0x%08x\n", res); 7175 } 7176 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7177 device_printf(dev, "GPIO:"); 7178 res = hdac_command(sc, 7179 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7180 printf(" data=0x%08x", res); 7181 res = hdac_command(sc, 7182 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7183 printf(" enable=0x%08x", res); 7184 res = hdac_command(sc, 7185 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7186 printf(" direction=0x%08x\n", res); 7187 res = hdac_command(sc, 7188 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7189 device_printf(dev, " wake=0x%08x", res); 7190 res = hdac_command(sc, 7191 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7192 cad); 7193 printf(" unsol=0x%08x", res); 7194 res = hdac_command(sc, 7195 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7196 printf(" sticky=0x%08x\n", res); 7197 } 7198 } 7199 } 7200 hdac_unlock(sc); 7201 return (0); 7202} 7203#endif 7204 7205static void 7206hdac_attach2(void *arg) 7207{ 7208 struct hdac_codec *codec; 7209 struct hdac_softc *sc; 7210 struct hdac_audio_ctl *ctl; 7211 uint32_t quirks_on, quirks_off; 7212 int codec_index, fg_index; 7213 int i, dmaalloc = 0; 7214 struct hdac_devinfo *devinfo; 7215 7216 sc = (struct hdac_softc *)arg; 7217 7218 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7219 7220 HDA_BOOTHVERBOSE( 7221 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7222 quirks_on, quirks_off); 7223 ); 7224 7225 hdac_lock(sc); 7226 7227 /* Remove ourselves from the config hooks */ 7228 if (sc->intrhook.ich_func != NULL) { 7229 config_intrhook_disestablish(&sc->intrhook); 7230 sc->intrhook.ich_func = NULL; 7231 } 7232 7233 /* Start the corb and rirb engines */ 7234 HDA_BOOTHVERBOSE( 7235 device_printf(sc->dev, "Starting CORB Engine...\n"); 7236 ); 7237 hdac_corb_start(sc); 7238 HDA_BOOTHVERBOSE( 7239 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7240 ); 7241 hdac_rirb_start(sc); 7242 7243 HDA_BOOTHVERBOSE( 7244 device_printf(sc->dev, 7245 "Enabling controller interrupt...\n"); 7246 ); 7247 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7248 HDAC_GCTL_UNSOL); 7249 if (sc->polling == 0) { 7250 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7251 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7252 } else { 7253 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7254 } 7255 DELAY(1000); 7256 7257 HDA_BOOTHVERBOSE( 7258 device_printf(sc->dev, 7259 "Scanning HDA codecs ...\n"); 7260 ); 7261 hdac_scan_codecs(sc); 7262 7263 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7264 codec = sc->codecs[codec_index]; 7265 if (codec == NULL) 7266 continue; 7267 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7268 devinfo = &codec->fgs[fg_index]; 7269 HDA_BOOTVERBOSE( 7270 device_printf(sc->dev, "\n"); 7271 device_printf(sc->dev, 7272 "Processing %s FG cad=%d nid=%d...\n", 7273 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7274 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7275 "unknown", 7276 devinfo->codec->cad, devinfo->nid); 7277 ); 7278 if (devinfo->node_type != 7279 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7280 HDA_BOOTHVERBOSE( 7281 device_printf(sc->dev, 7282 "Powering down...\n"); 7283 ); 7284 hdac_command(sc, 7285 HDA_CMD_SET_POWER_STATE(codec->cad, 7286 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7287 codec->cad); 7288 continue; 7289 } 7290 7291 HDA_BOOTHVERBOSE( 7292 device_printf(sc->dev, "Powering up...\n"); 7293 ); 7294 hdac_powerup(devinfo); 7295 HDA_BOOTHVERBOSE( 7296 device_printf(sc->dev, "Parsing audio FG...\n"); 7297 ); 7298 hdac_audio_parse(devinfo); 7299 HDA_BOOTHVERBOSE( 7300 device_printf(sc->dev, "Parsing Ctls...\n"); 7301 ); 7302 hdac_audio_ctl_parse(devinfo); 7303 HDA_BOOTHVERBOSE( 7304 device_printf(sc->dev, "Parsing vendor patch...\n"); 7305 ); 7306 hdac_vendor_patch_parse(devinfo); 7307 devinfo->function.audio.quirks |= quirks_on; 7308 devinfo->function.audio.quirks &= ~quirks_off; 7309 7310 HDA_BOOTHVERBOSE( 7311 device_printf(sc->dev, "Disabling nonaudio...\n"); 7312 ); 7313 hdac_audio_disable_nonaudio(devinfo); 7314 HDA_BOOTHVERBOSE( 7315 device_printf(sc->dev, "Disabling useless...\n"); 7316 ); 7317 hdac_audio_disable_useless(devinfo); 7318 HDA_BOOTVERBOSE( 7319 device_printf(sc->dev, "Patched pins configuration:\n"); 7320 hdac_dump_pin_configs(devinfo); 7321 ); 7322 HDA_BOOTHVERBOSE( 7323 device_printf(sc->dev, "Parsing pin associations...\n"); 7324 ); 7325 hdac_audio_as_parse(devinfo); 7326 HDA_BOOTHVERBOSE( 7327 device_printf(sc->dev, "Building AFG tree...\n"); 7328 ); 7329 hdac_audio_build_tree(devinfo); 7330 HDA_BOOTHVERBOSE( 7331 device_printf(sc->dev, "Disabling unassociated " 7332 "widgets...\n"); 7333 ); 7334 hdac_audio_disable_unas(devinfo); 7335 HDA_BOOTHVERBOSE( 7336 device_printf(sc->dev, "Disabling nonselected " 7337 "inputs...\n"); 7338 ); 7339 hdac_audio_disable_notselected(devinfo); 7340 HDA_BOOTHVERBOSE( 7341 device_printf(sc->dev, "Disabling useless...\n"); 7342 ); 7343 hdac_audio_disable_useless(devinfo); 7344 HDA_BOOTHVERBOSE( 7345 device_printf(sc->dev, "Disabling " 7346 "crossassociatement connections...\n"); 7347 ); 7348 hdac_audio_disable_crossas(devinfo); 7349 HDA_BOOTHVERBOSE( 7350 device_printf(sc->dev, "Disabling useless...\n"); 7351 ); 7352 hdac_audio_disable_useless(devinfo); 7353 HDA_BOOTHVERBOSE( 7354 device_printf(sc->dev, "Binding associations to channels...\n"); 7355 ); 7356 hdac_audio_bind_as(devinfo); 7357 HDA_BOOTHVERBOSE( 7358 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7359 ); 7360 hdac_audio_assign_names(devinfo); 7361 HDA_BOOTHVERBOSE( 7362 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7363 ); 7364 hdac_audio_assign_mixers(devinfo); 7365 HDA_BOOTHVERBOSE( 7366 device_printf(sc->dev, "Preparing pin controls...\n"); 7367 ); 7368 hdac_audio_prepare_pin_ctrl(devinfo); 7369 HDA_BOOTHVERBOSE( 7370 device_printf(sc->dev, "AFG commit...\n"); 7371 ); 7372 hdac_audio_commit(devinfo); 7373 HDA_BOOTHVERBOSE( 7374 device_printf(sc->dev, "Ctls commit...\n"); 7375 ); 7376 hdac_audio_ctl_commit(devinfo); 7377 HDA_BOOTHVERBOSE( 7378 device_printf(sc->dev, "HP switch init...\n"); 7379 ); 7380 hdac_hp_switch_init(devinfo); 7381 7382 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7383 dmaalloc == 0) { 7384 if (hdac_dma_alloc(sc, &sc->pos_dma, 7385 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7386 HDA_BOOTVERBOSE( 7387 device_printf(sc->dev, "Failed to " 7388 "allocate DMA pos buffer " 7389 "(non-fatal)\n"); 7390 ); 7391 } else 7392 dmaalloc = 1; 7393 } 7394 7395 HDA_BOOTHVERBOSE( 7396 device_printf(sc->dev, "Creating PCM devices...\n"); 7397 ); 7398 hdac_create_pcms(devinfo); 7399 7400 HDA_BOOTVERBOSE( 7401 if (devinfo->function.audio.quirks != 0) { 7402 device_printf(sc->dev, "FG config/quirks:"); 7403 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7404 if ((devinfo->function.audio.quirks & 7405 hdac_quirks_tab[i].value) == 7406 hdac_quirks_tab[i].value) 7407 printf(" %s", hdac_quirks_tab[i].key); 7408 } 7409 printf("\n"); 7410 } 7411 7412 device_printf(sc->dev, "\n"); 7413 device_printf(sc->dev, "+-------------------+\n"); 7414 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7415 device_printf(sc->dev, "+-------------------+\n"); 7416 hdac_dump_nodes(devinfo); 7417 ); 7418 7419 HDA_BOOTHVERBOSE( 7420 device_printf(sc->dev, "\n"); 7421 device_printf(sc->dev, "+------------------------+\n"); 7422 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7423 device_printf(sc->dev, "+------------------------+\n"); 7424 device_printf(sc->dev, "\n"); 7425 i = 0; 7426 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7427 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7428 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7429 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7430 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7431 ctl->index); 7432 if (ctl->childwidget != NULL) 7433 printf(" cnid %3d", ctl->childwidget->nid); 7434 else 7435 printf(" "); 7436 printf(" ossmask=0x%08x\n", 7437 ctl->ossmask); 7438 device_printf(sc->dev, 7439 " mute: %d step: %3d size: %3d off: %3d%s\n", 7440 ctl->mute, ctl->step, ctl->size, ctl->offset, 7441 (ctl->enable == 0) ? " [DISABLED]" : 7442 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7443 } 7444 ); 7445 } 7446 } 7447 hdac_unlock(sc); 7448 7449 HDA_BOOTVERBOSE( 7450 device_printf(sc->dev, "\n"); 7451 ); 7452 7453 bus_generic_attach(sc->dev); 7454 7455#ifdef SND_DYNSYSCTL 7456 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7457 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7458 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7459 sysctl_hdac_polling, "I", "Enable polling mode"); 7460 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7461 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7462 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7463 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7464 "Controller/Jack Sense polling interval (1-1000 ms)"); 7465 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7466 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7467 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7468 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7469#endif 7470} 7471 7472/**************************************************************************** 7473 * int hdac_suspend(device_t) 7474 * 7475 * Suspend and power down HDA bus and codecs. 7476 ****************************************************************************/ 7477static int 7478hdac_suspend(device_t dev) 7479{ 7480 struct hdac_softc *sc; 7481 struct hdac_codec *codec; 7482 struct hdac_devinfo *devinfo; 7483 int codec_index, fg_index, i; 7484 7485 HDA_BOOTHVERBOSE( 7486 device_printf(dev, "Suspend...\n"); 7487 ); 7488 7489 sc = device_get_softc(dev); 7490 hdac_lock(sc); 7491 7492 HDA_BOOTHVERBOSE( 7493 device_printf(dev, "Stop streams...\n"); 7494 ); 7495 for (i = 0; i < sc->num_chans; i++) { 7496 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7497 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7498 hdac_channel_stop(sc, &sc->chans[i]); 7499 } 7500 } 7501 7502 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7503 codec = sc->codecs[codec_index]; 7504 if (codec == NULL) 7505 continue; 7506 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7507 devinfo = &codec->fgs[fg_index]; 7508 HDA_BOOTHVERBOSE( 7509 device_printf(dev, 7510 "Power down FG" 7511 " cad=%d nid=%d to the D3 state...\n", 7512 codec->cad, devinfo->nid); 7513 ); 7514 hdac_command(sc, 7515 HDA_CMD_SET_POWER_STATE(codec->cad, 7516 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7517 codec->cad); 7518 } 7519 } 7520 7521 HDA_BOOTHVERBOSE( 7522 device_printf(dev, "Reset controller...\n"); 7523 ); 7524 callout_stop(&sc->poll_hda); 7525 callout_stop(&sc->poll_hdac); 7526 callout_stop(&sc->poll_jack); 7527 hdac_reset(sc, 0); 7528 hdac_unlock(sc); 7529 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7530 callout_drain(&sc->poll_hda); 7531 callout_drain(&sc->poll_hdac); 7532 callout_drain(&sc->poll_jack); 7533 7534 HDA_BOOTHVERBOSE( 7535 device_printf(dev, "Suspend done\n"); 7536 ); 7537 7538 return (0); 7539} 7540 7541/**************************************************************************** 7542 * int hdac_resume(device_t) 7543 * 7544 * Powerup and restore HDA bus and codecs state. 7545 ****************************************************************************/ 7546static int 7547hdac_resume(device_t dev) 7548{ 7549 struct hdac_softc *sc; 7550 struct hdac_codec *codec; 7551 struct hdac_devinfo *devinfo; 7552 int codec_index, fg_index, i; 7553 7554 HDA_BOOTHVERBOSE( 7555 device_printf(dev, "Resume...\n"); 7556 ); 7557 7558 sc = device_get_softc(dev); 7559 hdac_lock(sc); 7560 7561 /* Quiesce everything */ 7562 HDA_BOOTHVERBOSE( 7563 device_printf(dev, "Reset controller...\n"); 7564 ); 7565 hdac_reset(sc, 1); 7566 7567 /* Initialize the CORB and RIRB */ 7568 hdac_corb_init(sc); 7569 hdac_rirb_init(sc); 7570 7571 /* Start the corb and rirb engines */ 7572 HDA_BOOTHVERBOSE( 7573 device_printf(dev, "Starting CORB Engine...\n"); 7574 ); 7575 hdac_corb_start(sc); 7576 HDA_BOOTHVERBOSE( 7577 device_printf(dev, "Starting RIRB Engine...\n"); 7578 ); 7579 hdac_rirb_start(sc); 7580 7581 HDA_BOOTHVERBOSE( 7582 device_printf(dev, 7583 "Enabling controller interrupt...\n"); 7584 ); 7585 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7586 HDAC_GCTL_UNSOL); 7587 if (sc->polling == 0) { 7588 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7589 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7590 } else { 7591 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7592 } 7593 DELAY(1000); 7594 7595 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7596 codec = sc->codecs[codec_index]; 7597 if (codec == NULL) 7598 continue; 7599 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7600 devinfo = &codec->fgs[fg_index]; 7601 if (devinfo->node_type != 7602 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7603 HDA_BOOTHVERBOSE( 7604 device_printf(dev, 7605 "Power down unsupported non-audio FG" 7606 " cad=%d nid=%d to the D3 state...\n", 7607 codec->cad, devinfo->nid); 7608 ); 7609 hdac_command(sc, 7610 HDA_CMD_SET_POWER_STATE(codec->cad, 7611 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7612 codec->cad); 7613 continue; 7614 } 7615 7616 HDA_BOOTHVERBOSE( 7617 device_printf(dev, 7618 "Power up audio FG cad=%d nid=%d...\n", 7619 devinfo->codec->cad, devinfo->nid); 7620 ); 7621 hdac_powerup(devinfo); 7622 HDA_BOOTHVERBOSE( 7623 device_printf(dev, "AFG commit...\n"); 7624 ); 7625 hdac_audio_commit(devinfo); 7626 HDA_BOOTHVERBOSE( 7627 device_printf(dev, "Ctls commit...\n"); 7628 ); 7629 hdac_audio_ctl_commit(devinfo); 7630 HDA_BOOTHVERBOSE( 7631 device_printf(dev, "HP switch init...\n"); 7632 ); 7633 hdac_hp_switch_init(devinfo); 7634 7635 hdac_unlock(sc); 7636 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7637 struct hdac_pcm_devinfo *pdevinfo = 7638 &devinfo->function.audio.devs[i]; 7639 HDA_BOOTHVERBOSE( 7640 device_printf(pdevinfo->dev, 7641 "OSS mixer reinitialization...\n"); 7642 ); 7643 if (mixer_reinit(pdevinfo->dev) == -1) 7644 device_printf(pdevinfo->dev, 7645 "unable to reinitialize the mixer\n"); 7646 } 7647 hdac_lock(sc); 7648 } 7649 } 7650 7651 HDA_BOOTHVERBOSE( 7652 device_printf(dev, "Start streams...\n"); 7653 ); 7654 for (i = 0; i < sc->num_chans; i++) { 7655 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7656 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7657 hdac_channel_start(sc, &sc->chans[i]); 7658 } 7659 } 7660 7661 hdac_unlock(sc); 7662 7663 HDA_BOOTHVERBOSE( 7664 device_printf(dev, "Resume done\n"); 7665 ); 7666 7667 return (0); 7668} 7669/**************************************************************************** 7670 * int hdac_detach(device_t) 7671 * 7672 * Detach and free up resources utilized by the hdac device. 7673 ****************************************************************************/ 7674static int 7675hdac_detach(device_t dev) 7676{ 7677 struct hdac_softc *sc; 7678 device_t *devlist; 7679 int i, devcount, error; 7680 7681 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7682 return (error); 7683 for (i = 0; i < devcount; i++) { 7684 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7685 free(devlist, M_TEMP); 7686 return (error); 7687 } 7688 } 7689 free(devlist, M_TEMP); 7690 7691 sc = device_get_softc(dev); 7692 hdac_release_resources(sc); 7693 7694 return (0); 7695} 7696 7697static int 7698hdac_print_child(device_t dev, device_t child) 7699{ 7700 struct hdac_pcm_devinfo *pdevinfo = 7701 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7702 int retval; 7703 7704 retval = bus_print_child_header(dev, child); 7705 retval += printf(" at cad %d nid %d", 7706 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7707 retval += bus_print_child_footer(dev, child); 7708 7709 return (retval); 7710} 7711 7712static device_method_t hdac_methods[] = { 7713 /* device interface */ 7714 DEVMETHOD(device_probe, hdac_probe), 7715 DEVMETHOD(device_attach, hdac_attach), 7716 DEVMETHOD(device_detach, hdac_detach), 7717 DEVMETHOD(device_suspend, hdac_suspend), 7718 DEVMETHOD(device_resume, hdac_resume), 7719 /* Bus interface */ 7720 DEVMETHOD(bus_print_child, hdac_print_child), 7721 { 0, 0 } 7722}; 7723 7724static driver_t hdac_driver = { 7725 "hdac", 7726 hdac_methods, 7727 sizeof(struct hdac_softc), 7728}; 7729 7730static devclass_t hdac_devclass; 7731 7732DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7733MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7734MODULE_VERSION(snd_hda, 1); 7735 7736static int 7737hdac_pcm_probe(device_t dev) 7738{ 7739 struct hdac_pcm_devinfo *pdevinfo = 7740 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7741 char buf[128]; 7742 7743 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7744 hdac_codec_name(pdevinfo->devinfo->codec), 7745 pdevinfo->index, 7746 pdevinfo->digital?"Digital":"Analog"); 7747 device_set_desc_copy(dev, buf); 7748 return (0); 7749} 7750 7751static int 7752hdac_pcm_attach(device_t dev) 7753{ 7754 struct hdac_pcm_devinfo *pdevinfo = 7755 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7756 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7757 char status[SND_STATUSLEN]; 7758 int i; 7759 7760 pdevinfo->chan_size = pcm_getbuffersize(dev, 7761 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7762 7763 HDA_BOOTVERBOSE( 7764 device_printf(dev, "+--------------------------------------+\n"); 7765 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7766 device_printf(dev, "+--------------------------------------+\n"); 7767 hdac_dump_pcmchannels(pdevinfo); 7768 device_printf(dev, "\n"); 7769 device_printf(dev, "+--------------------------------+\n"); 7770 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7771 device_printf(dev, "+--------------------------------+\n"); 7772 hdac_dump_dac(pdevinfo); 7773 hdac_dump_adc(pdevinfo); 7774 hdac_dump_mix(pdevinfo); 7775 device_printf(dev, "\n"); 7776 device_printf(dev, "+-------------------------+\n"); 7777 device_printf(dev, "| DUMPING Volume Controls |\n"); 7778 device_printf(dev, "+-------------------------+\n"); 7779 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7780 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7781 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7782 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7783 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7784 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7785 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7786 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7787 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7788 hdac_dump_ctls(pdevinfo, NULL, 0); 7789 device_printf(dev, "\n"); 7790 ); 7791 7792 if (resource_int_value(device_get_name(dev), 7793 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7794 i &= HDA_BLK_ALIGN; 7795 if (i < HDA_BLK_MIN) 7796 i = HDA_BLK_MIN; 7797 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7798 i = 0; 7799 while (pdevinfo->chan_blkcnt >> i) 7800 i++; 7801 pdevinfo->chan_blkcnt = 1 << (i - 1); 7802 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7803 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7804 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7805 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7806 } else 7807 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7808 7809 /* 7810 * We don't register interrupt handler with snd_setup_intr 7811 * in pcm device. Mark pcm device as MPSAFE manually. 7812 */ 7813 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7814 7815 HDA_BOOTHVERBOSE( 7816 device_printf(dev, "OSS mixer initialization...\n"); 7817 ); 7818 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7819 device_printf(dev, "Can't register mixer\n"); 7820 7821 HDA_BOOTHVERBOSE( 7822 device_printf(dev, "Registering PCM channels...\n"); 7823 ); 7824 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7825 (pdevinfo->rec >= 0)?1:0) != 0) 7826 device_printf(dev, "Can't register PCM\n"); 7827 7828 pdevinfo->registered++; 7829 7830 if (pdevinfo->play >= 0) 7831 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7832 if (pdevinfo->rec >= 0) 7833 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7834 7835 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7836 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7837 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7838 pcm_setstatus(dev, status); 7839 7840 return (0); 7841} 7842 7843static int 7844hdac_pcm_detach(device_t dev) 7845{ 7846 struct hdac_pcm_devinfo *pdevinfo = 7847 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7848 int err; 7849 7850 if (pdevinfo->registered > 0) { 7851 err = pcm_unregister(dev); 7852 if (err != 0) 7853 return (err); 7854 } 7855 7856 return (0); 7857} 7858 7859static device_method_t hdac_pcm_methods[] = { 7860 /* device interface */ 7861 DEVMETHOD(device_probe, hdac_pcm_probe), 7862 DEVMETHOD(device_attach, hdac_pcm_attach), 7863 DEVMETHOD(device_detach, hdac_pcm_detach), 7864 { 0, 0 } 7865}; 7866 7867static driver_t hdac_pcm_driver = { 7868 "pcm", 7869 hdac_pcm_methods, 7870 PCM_SOFTC_SIZE, 7871}; 7872 7873DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7874 7875