hdac.c revision 186301
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20081219_0119" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 186301 2008-12-18 22:04:13Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 166 167/* ATI */ 168#define ATI_VENDORID 0x1002 169#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 170#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 171#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 172 173/* VIA */ 174#define VIA_VENDORID 0x1106 175#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 176#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 177 178/* SiS */ 179#define SIS_VENDORID 0x1039 180#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 181#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 182 183/* ULI */ 184#define ULI_VENDORID 0x10b9 185#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 186#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 187 188/* OEM/subvendors */ 189 190/* Intel */ 191#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 192 193/* HP/Compaq */ 194#define HP_VENDORID 0x103c 195#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 196#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 197#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 198#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 199#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 200#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 201#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 202#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 203#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 204#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 205/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 206#define HP_NX6325_SUBVENDORX 0x103c30b0 207 208/* Dell */ 209#define DELL_VENDORID 0x1028 210#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 211#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 212#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 213#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 214#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 215#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 216#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 217#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 218 219/* Clevo */ 220#define CLEVO_VENDORID 0x1558 221#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 222#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 223 224/* Acer */ 225#define ACER_VENDORID 0x1025 226#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 227#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 228#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 229#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 230#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 231#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 232#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 233 234/* Asus */ 235#define ASUS_VENDORID 0x1043 236#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 237#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 238#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 239#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 240#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 241#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 242#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 243#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 244#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 245#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 246#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 247#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 248#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 249#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 250#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 251#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 252 253/* IBM / Lenovo */ 254#define IBM_VENDORID 0x1014 255#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 256#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 257 258/* Lenovo */ 259#define LENOVO_VENDORID 0x17aa 260#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 261#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 262#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 263#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 264 265/* Samsung */ 266#define SAMSUNG_VENDORID 0x144d 267#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 268#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 269 270/* Medion ? */ 271#define MEDION_VENDORID 0x161f 272#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 273#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 274 275/* Apple Computer Inc. */ 276#define APPLE_VENDORID 0x106b 277#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 278 279/* Sony */ 280#define SONY_VENDORID 0x104d 281#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 282#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 283 284/* 285 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 286 * instead of their own, which is beyond my comprehension 287 * (see HDA_CODEC_STAC9221 below). 288 */ 289#define APPLE_INTEL_MAC 0x76808384 290 291/* LG Electronics */ 292#define LG_VENDORID 0x1854 293#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 294#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 295 296/* Fujitsu Siemens */ 297#define FS_VENDORID 0x1734 298#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 299#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 300#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 301 302/* Fujitsu Limited */ 303#define FL_VENDORID 0x10cf 304#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 305#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 306#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 307 308/* Toshiba */ 309#define TOSHIBA_VENDORID 0x1179 310#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 311#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 312#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 313 314/* Micro-Star International (MSI) */ 315#define MSI_VENDORID 0x1462 316#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 317#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 318#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 319 320/* Giga-Byte Technology */ 321#define GB_VENDORID 0x1458 322#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 323#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 324 325/* Uniwill ? */ 326#define UNIWILL_VENDORID 0x1584 327#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 328#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 329 330 331/* Misc constants.. */ 332#define HDA_AMP_VOL_DEFAULT (-1) 333#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 334#define HDA_AMP_MUTE_NONE (0) 335#define HDA_AMP_MUTE_LEFT (1 << 0) 336#define HDA_AMP_MUTE_RIGHT (1 << 1) 337#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 338 339#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 340#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 341 342#define HDA_ADC_MONITOR (1 << 0) 343 344#define HDA_CTL_OUT 1 345#define HDA_CTL_IN 2 346 347#define HDA_GPIO_MAX 8 348/* 0 - 7 = GPIO , 8 = Flush */ 349#define HDA_QUIRK_GPIO0 (1 << 0) 350#define HDA_QUIRK_GPIO1 (1 << 1) 351#define HDA_QUIRK_GPIO2 (1 << 2) 352#define HDA_QUIRK_GPIO3 (1 << 3) 353#define HDA_QUIRK_GPIO4 (1 << 4) 354#define HDA_QUIRK_GPIO5 (1 << 5) 355#define HDA_QUIRK_GPIO6 (1 << 6) 356#define HDA_QUIRK_GPIO7 (1 << 7) 357#define HDA_QUIRK_GPIOFLUSH (1 << 8) 358 359/* 9 - 25 = anything else */ 360#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 361#define HDA_QUIRK_FIXEDRATE (1 << 10) 362#define HDA_QUIRK_FORCESTEREO (1 << 11) 363#define HDA_QUIRK_EAPDINV (1 << 12) 364#define HDA_QUIRK_DMAPOS (1 << 13) 365#define HDA_QUIRK_SENSEINV (1 << 14) 366 367/* 26 - 31 = vrefs */ 368#define HDA_QUIRK_IVREF50 (1 << 26) 369#define HDA_QUIRK_IVREF80 (1 << 27) 370#define HDA_QUIRK_IVREF100 (1 << 28) 371#define HDA_QUIRK_OVREF50 (1 << 29) 372#define HDA_QUIRK_OVREF80 (1 << 30) 373#define HDA_QUIRK_OVREF100 (1 << 31) 374 375#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 376 HDA_QUIRK_IVREF100) 377#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 378 HDA_QUIRK_OVREF100) 379#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 380 381#if __FreeBSD_version < 600000 382#define taskqueue_drain(...) 383#endif 384 385static const struct { 386 char *key; 387 uint32_t value; 388} hdac_quirks_tab[] = { 389 { "gpio0", HDA_QUIRK_GPIO0 }, 390 { "gpio1", HDA_QUIRK_GPIO1 }, 391 { "gpio2", HDA_QUIRK_GPIO2 }, 392 { "gpio3", HDA_QUIRK_GPIO3 }, 393 { "gpio4", HDA_QUIRK_GPIO4 }, 394 { "gpio5", HDA_QUIRK_GPIO5 }, 395 { "gpio6", HDA_QUIRK_GPIO6 }, 396 { "gpio7", HDA_QUIRK_GPIO7 }, 397 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 398 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 399 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 400 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 401 { "eapdinv", HDA_QUIRK_EAPDINV }, 402 { "dmapos", HDA_QUIRK_DMAPOS }, 403 { "senseinv", HDA_QUIRK_SENSEINV }, 404 { "ivref50", HDA_QUIRK_IVREF50 }, 405 { "ivref80", HDA_QUIRK_IVREF80 }, 406 { "ivref100", HDA_QUIRK_IVREF100 }, 407 { "ovref50", HDA_QUIRK_OVREF50 }, 408 { "ovref80", HDA_QUIRK_OVREF80 }, 409 { "ovref100", HDA_QUIRK_OVREF100 }, 410 { "ivref", HDA_QUIRK_IVREF }, 411 { "ovref", HDA_QUIRK_OVREF }, 412 { "vref", HDA_QUIRK_VREF }, 413}; 414#define HDAC_QUIRKS_TAB_LEN \ 415 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 416 417#define HDA_BDL_MIN 2 418#define HDA_BDL_MAX 256 419#define HDA_BDL_DEFAULT HDA_BDL_MIN 420 421#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 422#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 423 424#define HDA_BUFSZ_MIN 4096 425#define HDA_BUFSZ_MAX 65536 426#define HDA_BUFSZ_DEFAULT 16384 427 428#define HDA_PARSE_MAXDEPTH 10 429 430#define HDAC_UNSOLTAG_EVENT_HP 0x00 431 432MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 433 434const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 435 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 436 "White", "Other"}; 437 438const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 439 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 440 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 441 442const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 443 444/* Default */ 445static uint32_t hdac_fmt[] = { 446 AFMT_STEREO | AFMT_S16_LE, 447 0 448}; 449 450static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 451 452static const struct { 453 uint32_t model; 454 char *desc; 455} hdac_devices[] = { 456 { HDA_INTEL_82801F, "Intel 82801F" }, 457 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 458 { HDA_INTEL_82801G, "Intel 82801G" }, 459 { HDA_INTEL_82801H, "Intel 82801H" }, 460 { HDA_INTEL_82801I, "Intel 82801I" }, 461 { HDA_INTEL_82801J, "Intel 82801J" }, 462 { HDA_INTEL_SCH, "Intel SCH" }, 463 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 464 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 465 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 466 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 467 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 468 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 469 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 470 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 471 { HDA_ATI_SB450, "ATI SB450" }, 472 { HDA_ATI_SB600, "ATI SB600" }, 473 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 474 { HDA_SIS_966, "SiS 966" }, 475 { HDA_ULI_M5461, "ULI M5461" }, 476 /* Unknown */ 477 { HDA_INTEL_ALL, "Intel (Unknown)" }, 478 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 479 { HDA_ATI_ALL, "ATI (Unknown)" }, 480 { HDA_VIA_ALL, "VIA (Unknown)" }, 481 { HDA_SIS_ALL, "SiS (Unknown)" }, 482 { HDA_ULI_ALL, "ULI (Unknown)" }, 483}; 484#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 485 486static const struct { 487 uint16_t vendor; 488 uint8_t reg; 489 uint8_t mask; 490 uint8_t enable; 491} hdac_pcie_snoop[] = { 492 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 493 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 494 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 495}; 496#define HDAC_PCIESNOOP_LEN \ 497 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 498 499static const struct { 500 uint32_t rate; 501 int valid; 502 uint16_t base; 503 uint16_t mul; 504 uint16_t div; 505} hda_rate_tab[] = { 506 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 507 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 508 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 509 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 510 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 511 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 512 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 513 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 514 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 515 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 516 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 517 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 518 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 519 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 520 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 521 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 522 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 523 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 524 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 525 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 526 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 527 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 528 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 529 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 530 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 531 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 532 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 533 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 534 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 535 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 536 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 537 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 538 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 539 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 540 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 541}; 542#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 543 544/* All codecs you can eat... */ 545#define HDA_CODEC_CONSTRUCT(vendor, id) \ 546 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 547 548/* Realtek */ 549#define REALTEK_VENDORID 0x10ec 550#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 551#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 552#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 553#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 554#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 555#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 556#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 557#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 558#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 559#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 560#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 561#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 562#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 563#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 564#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 565#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 566#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 567#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 568 569/* Analog Devices */ 570#define ANALOGDEVICES_VENDORID 0x11d4 571#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 572#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 573#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 574#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 575#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 576#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 577#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 578 579/* CMedia */ 580#define CMEDIA_VENDORID 0x434d 581#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 582#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 583 584/* Sigmatel */ 585#define SIGMATEL_VENDORID 0x8384 586#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 587#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 588#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 589#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 590#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 591#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 592#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 593#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 594#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 595#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 596#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 597#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 598#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 599#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 600#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 601#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 602#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 603#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 604#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 605#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 606#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 607#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 608#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 609#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 610#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 611#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 612#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 613#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 614#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 615#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 616#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 617#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 618#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 619#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 620#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 621#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 622#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 623#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 624#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 625#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 626 627/* IDT */ 628#define IDT_VENDORID 0x111d 629#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 630#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 631#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 632#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 633#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 634#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 635#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 636#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 637#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 638#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 639#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 640#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 641#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 642 643/* Silicon Image */ 644#define SII_VENDORID 0x1095 645#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 646#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 647 648/* Lucent/Agere */ 649#define AGERE_VENDORID 0x11c1 650#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 651 652/* 653 * Conexant 654 * 655 * Ok, the truth is, I don't have any idea at all whether 656 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 657 * place that tell me it is "Venice" is from its Windows driver INF. 658 * 659 * Venice - CX????? 660 * Waikiki - CX20551-22 661 */ 662#define CONEXANT_VENDORID 0x14f1 663#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 664#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 665#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 666 667/* VIA */ 668#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 669#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 670#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 671#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 672#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 673#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 674#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 675#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 676#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 677#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 678#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 679#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 680#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 681#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 682#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 683#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 684#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 685#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 686#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 687#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 688#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 689 690/* ATI */ 691#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 692#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 693#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 694#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 695#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 696 697/* NVIDIA */ 698#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 699 700/* INTEL */ 701#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 702 703/* Codecs */ 704static const struct { 705 uint32_t id; 706 char *name; 707} hdac_codecs[] = { 708 { HDA_CODEC_ALC260, "Realtek ALC260" }, 709 { HDA_CODEC_ALC262, "Realtek ALC262" }, 710 { HDA_CODEC_ALC267, "Realtek ALC267" }, 711 { HDA_CODEC_ALC268, "Realtek ALC268" }, 712 { HDA_CODEC_ALC269, "Realtek ALC269" }, 713 { HDA_CODEC_ALC272, "Realtek ALC272" }, 714 { HDA_CODEC_ALC660, "Realtek ALC660" }, 715 { HDA_CODEC_ALC662, "Realtek ALC662" }, 716 { HDA_CODEC_ALC663, "Realtek ALC663" }, 717 { HDA_CODEC_ALC861, "Realtek ALC861" }, 718 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 719 { HDA_CODEC_ALC880, "Realtek ALC880" }, 720 { HDA_CODEC_ALC882, "Realtek ALC882" }, 721 { HDA_CODEC_ALC883, "Realtek ALC883" }, 722 { HDA_CODEC_ALC885, "Realtek ALC885" }, 723 { HDA_CODEC_ALC888, "Realtek ALC888" }, 724 { HDA_CODEC_ALC889, "Realtek ALC889" }, 725 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 726 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 727 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 728 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 729 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 730 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 731 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 732 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 733 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 734 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 735 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 736 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 737 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 738 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 739 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 740 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 741 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 742 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 743 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 744 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 745 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 746 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 747 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 748 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 749 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 750 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 751 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 752 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 753 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 754 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 755 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 756 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 757 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 758 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 759 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 760 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 761 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 762 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 763 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 764 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 765 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 766 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 767 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 768 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 769 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 770 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 771 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 772 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 773 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 774 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 775 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 776 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 777 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 778 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 779 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 780 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 781 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 782 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 783 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 784 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 785 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 786 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 787 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 788 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 789 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 790 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 791 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 792 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 793 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 794 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 795 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 796 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 797 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 798 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 799 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 800 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 801 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 802 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 803 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 804 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 805 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 806 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 807 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 808 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 809 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 810 /* Unknown codec */ 811 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 812 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 813 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 814 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 815 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 816 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 817 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 818 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 819 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 820 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 821 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 822 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 823}; 824#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 825 826 827/**************************************************************************** 828 * Function prototypes 829 ****************************************************************************/ 830static void hdac_intr_handler(void *); 831static int hdac_reset(struct hdac_softc *, int); 832static int hdac_get_capabilities(struct hdac_softc *); 833static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 834static int hdac_dma_alloc(struct hdac_softc *, 835 struct hdac_dma *, bus_size_t); 836static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 837static int hdac_mem_alloc(struct hdac_softc *); 838static void hdac_mem_free(struct hdac_softc *); 839static int hdac_irq_alloc(struct hdac_softc *); 840static void hdac_irq_free(struct hdac_softc *); 841static void hdac_corb_init(struct hdac_softc *); 842static void hdac_rirb_init(struct hdac_softc *); 843static void hdac_corb_start(struct hdac_softc *); 844static void hdac_rirb_start(struct hdac_softc *); 845static void hdac_scan_codecs(struct hdac_softc *); 846static void hdac_probe_codec(struct hdac_codec *); 847static void hdac_probe_function(struct hdac_codec *, nid_t); 848static int hdac_pcmchannel_setup(struct hdac_chan *); 849 850static void hdac_attach2(void *); 851 852static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 853 uint32_t, int); 854static void hdac_command_send_internal(struct hdac_softc *, 855 struct hdac_command_list *, int); 856 857static int hdac_probe(device_t); 858static int hdac_attach(device_t); 859static int hdac_detach(device_t); 860static int hdac_suspend(device_t); 861static int hdac_resume(device_t); 862static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 863static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 864 uint32_t, int, int); 865static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 866 nid_t, int, int, int); 867static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 868 nid_t, nid_t, int, int, int, int, int, int); 869static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 870 871static int hdac_rirb_flush(struct hdac_softc *sc); 872static int hdac_unsolq_flush(struct hdac_softc *sc); 873 874static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 875 876#define hdac_command(a1, a2, a3) \ 877 hdac_command_sendone_internal(a1, a2, a3) 878 879#define hdac_codec_id(c) \ 880 ((uint32_t)((c == NULL) ? 0x00000000 : \ 881 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 882 ((uint32_t)(c)->device_id & 0x0000ffff)))) 883 884static char * 885hdac_codec_name(struct hdac_codec *codec) 886{ 887 uint32_t id; 888 int i; 889 890 id = hdac_codec_id(codec); 891 892 for (i = 0; i < HDAC_CODECS_LEN; i++) { 893 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 894 return (hdac_codecs[i].name); 895 } 896 897 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 898} 899 900static char * 901hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 902{ 903 static char *ossname[] = SOUND_DEVICE_NAMES; 904 int i, first = 1; 905 906 bzero(buf, len); 907 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 908 if (mask & (1 << i)) { 909 if (first == 0) 910 strlcat(buf, ", ", len); 911 strlcat(buf, ossname[i], len); 912 first = 0; 913 } 914 } 915 return (buf); 916} 917 918static struct hdac_audio_ctl * 919hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 920{ 921 if (devinfo == NULL || 922 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 923 index == NULL || devinfo->function.audio.ctl == NULL || 924 devinfo->function.audio.ctlcnt < 1 || 925 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 926 return (NULL); 927 return (&devinfo->function.audio.ctl[(*index)++]); 928} 929 930static struct hdac_audio_ctl * 931hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 932 int index, int cnt) 933{ 934 struct hdac_audio_ctl *ctl; 935 int i, found = 0; 936 937 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 938 return (NULL); 939 940 i = 0; 941 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 942 if (ctl->enable == 0) 943 continue; 944 if (ctl->widget->nid != nid) 945 continue; 946 if (dir && ctl->ndir != dir) 947 continue; 948 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 949 ctl->dir == ctl->ndir && ctl->index != index) 950 continue; 951 found++; 952 if (found == cnt || cnt <= 0) 953 return (ctl); 954 } 955 956 return (NULL); 957} 958 959/* 960 * Jack detection (Speaker/HP redirection) event handler. 961 */ 962static void 963hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 964{ 965 struct hdac_audio_as *as; 966 struct hdac_softc *sc; 967 struct hdac_widget *w; 968 struct hdac_audio_ctl *ctl; 969 uint32_t val, res; 970 int i, j; 971 nid_t cad; 972 973 if (devinfo == NULL || devinfo->codec == NULL || 974 devinfo->codec->sc == NULL) 975 return; 976 977 sc = devinfo->codec->sc; 978 cad = devinfo->codec->cad; 979 as = devinfo->function.audio.as; 980 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 981 if (as[i].hpredir < 0) 982 continue; 983 984 w = hdac_widget_get(devinfo, as[i].pins[15]); 985 if (w == NULL || w->enable == 0 || w->type != 986 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 987 continue; 988 989 res = hdac_command(sc, 990 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 991 992 HDA_BOOTVERBOSE( 993 device_printf(sc->dev, 994 "Pin sense: nid=%d res=0x%08x\n", 995 as[i].pins[15], res); 996 ); 997 998 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 999 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1000 res ^= 1; 1001 1002 /* (Un)Mute headphone pin. */ 1003 ctl = hdac_audio_ctl_amp_get(devinfo, 1004 as[i].pins[15], HDA_CTL_IN, -1, 1); 1005 if (ctl != NULL && ctl->mute) { 1006 /* If pin has muter - use it. */ 1007 val = (res != 0) ? 0 : 1; 1008 if (val != ctl->forcemute) { 1009 ctl->forcemute = val; 1010 hdac_audio_ctl_amp_set(ctl, 1011 HDA_AMP_MUTE_DEFAULT, 1012 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1013 } 1014 } else { 1015 /* If there is no muter - disable pin output. */ 1016 w = hdac_widget_get(devinfo, as[i].pins[15]); 1017 if (w != NULL && w->type == 1018 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1019 if (res != 0) 1020 val = w->wclass.pin.ctrl | 1021 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1022 else 1023 val = w->wclass.pin.ctrl & 1024 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1025 if (val != w->wclass.pin.ctrl) { 1026 w->wclass.pin.ctrl = val; 1027 hdac_command(sc, 1028 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1029 w->nid, w->wclass.pin.ctrl), cad); 1030 } 1031 } 1032 } 1033 /* (Un)Mute other pins. */ 1034 for (j = 0; j < 15; j++) { 1035 if (as[i].pins[j] <= 0) 1036 continue; 1037 ctl = hdac_audio_ctl_amp_get(devinfo, 1038 as[i].pins[j], HDA_CTL_IN, -1, 1); 1039 if (ctl != NULL && ctl->mute) { 1040 /* If pin has muter - use it. */ 1041 val = (res != 0) ? 1 : 0; 1042 if (val == ctl->forcemute) 1043 continue; 1044 ctl->forcemute = val; 1045 hdac_audio_ctl_amp_set(ctl, 1046 HDA_AMP_MUTE_DEFAULT, 1047 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1048 continue; 1049 } 1050 /* If there is no muter - disable pin output. */ 1051 w = hdac_widget_get(devinfo, as[i].pins[j]); 1052 if (w != NULL && w->type == 1053 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1054 if (res != 0) 1055 val = w->wclass.pin.ctrl & 1056 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1057 else 1058 val = w->wclass.pin.ctrl | 1059 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1060 if (val != w->wclass.pin.ctrl) { 1061 w->wclass.pin.ctrl = val; 1062 hdac_command(sc, 1063 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1064 w->nid, w->wclass.pin.ctrl), cad); 1065 } 1066 } 1067 } 1068 } 1069} 1070 1071/* 1072 * Callback for poll based jack detection. 1073 */ 1074static void 1075hdac_jack_poll_callback(void *arg) 1076{ 1077 struct hdac_devinfo *devinfo = arg; 1078 struct hdac_softc *sc; 1079 1080 if (devinfo == NULL || devinfo->codec == NULL || 1081 devinfo->codec->sc == NULL) 1082 return; 1083 sc = devinfo->codec->sc; 1084 hdac_lock(sc); 1085 if (sc->poll_ival == 0) { 1086 hdac_unlock(sc); 1087 return; 1088 } 1089 hdac_hp_switch_handler(devinfo); 1090 callout_reset(&sc->poll_jack, sc->poll_ival, 1091 hdac_jack_poll_callback, devinfo); 1092 hdac_unlock(sc); 1093} 1094 1095/* 1096 * Jack detection initializer. 1097 */ 1098static void 1099hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1100{ 1101 struct hdac_softc *sc = devinfo->codec->sc; 1102 struct hdac_audio_as *as = devinfo->function.audio.as; 1103 struct hdac_widget *w; 1104 uint32_t id; 1105 int i, enable = 0, poll = 0; 1106 nid_t cad; 1107 1108 id = hdac_codec_id(devinfo->codec); 1109 cad = devinfo->codec->cad; 1110 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1111 if (as[i].hpredir < 0) 1112 continue; 1113 1114 w = hdac_widget_get(devinfo, as[i].pins[15]); 1115 if (w == NULL || w->enable == 0 || w->type != 1116 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1117 continue; 1118 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1119 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1120 device_printf(sc->dev, 1121 "No jack detection support at pin %d\n", 1122 as[i].pins[15]); 1123 continue; 1124 } 1125 enable = 1; 1126 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1127 hdac_command(sc, 1128 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1129 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1130 HDAC_UNSOLTAG_EVENT_HP), cad); 1131 } else 1132 poll = 1; 1133 HDA_BOOTVERBOSE( 1134 device_printf(sc->dev, 1135 "Enabling headphone/speaker " 1136 "audio routing switching:\n"); 1137 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1138 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1139 ); 1140 } 1141 if (enable) { 1142 hdac_hp_switch_handler(devinfo); 1143 if (poll) { 1144 callout_reset(&sc->poll_jack, 1, 1145 hdac_jack_poll_callback, devinfo); 1146 } 1147 } 1148} 1149 1150/* 1151 * Unsolicited messages handler. 1152 */ 1153static void 1154hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1155{ 1156 struct hdac_softc *sc; 1157 struct hdac_devinfo *devinfo = NULL; 1158 int i; 1159 1160 if (codec == NULL || codec->sc == NULL) 1161 return; 1162 1163 sc = codec->sc; 1164 1165 HDA_BOOTVERBOSE( 1166 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1167 ); 1168 1169 for (i = 0; i < codec->num_fgs; i++) { 1170 if (codec->fgs[i].node_type == 1171 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1172 devinfo = &codec->fgs[i]; 1173 break; 1174 } 1175 } 1176 1177 if (devinfo == NULL) 1178 return; 1179 1180 switch (tag) { 1181 case HDAC_UNSOLTAG_EVENT_HP: 1182 hdac_hp_switch_handler(devinfo); 1183 break; 1184 default: 1185 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1186 break; 1187 } 1188} 1189 1190static int 1191hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1192{ 1193 /* XXX to be removed */ 1194#ifdef HDAC_INTR_EXTRA 1195 uint32_t res; 1196#endif 1197 1198 if (!(ch->flags & HDAC_CHN_RUNNING)) 1199 return (0); 1200 1201 /* XXX to be removed */ 1202#ifdef HDAC_INTR_EXTRA 1203 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1204#endif 1205 1206 /* XXX to be removed */ 1207#ifdef HDAC_INTR_EXTRA 1208 HDA_BOOTVERBOSE( 1209 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1210 device_printf(ch->pdevinfo->dev, 1211 "PCMDIR_%s intr triggered beyond stream boundary:" 1212 "%08x\n", 1213 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1214 ); 1215#endif 1216 1217 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1218 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1219 1220 /* XXX to be removed */ 1221#ifdef HDAC_INTR_EXTRA 1222 if (res & HDAC_SDSTS_BCIS) { 1223#endif 1224 return (1); 1225 /* XXX to be removed */ 1226#ifdef HDAC_INTR_EXTRA 1227 } 1228#endif 1229 1230 return (0); 1231} 1232 1233/**************************************************************************** 1234 * void hdac_intr_handler(void *) 1235 * 1236 * Interrupt handler. Processes interrupts received from the hdac. 1237 ****************************************************************************/ 1238static void 1239hdac_intr_handler(void *context) 1240{ 1241 struct hdac_softc *sc; 1242 uint32_t intsts; 1243 uint8_t rirbsts; 1244 struct hdac_rirb *rirb_base; 1245 uint32_t trigger; 1246 int i; 1247 1248 sc = (struct hdac_softc *)context; 1249 1250 hdac_lock(sc); 1251 if (sc->polling != 0) { 1252 hdac_unlock(sc); 1253 return; 1254 } 1255 1256 /* Do we have anything to do? */ 1257 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1258 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1259 hdac_unlock(sc); 1260 return; 1261 } 1262 1263 trigger = 0; 1264 1265 /* Was this a controller interrupt? */ 1266 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1267 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1268 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1269 /* Get as many responses that we can */ 1270 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1271 HDAC_WRITE_1(&sc->mem, 1272 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1273 if (hdac_rirb_flush(sc) != 0) 1274 trigger |= HDAC_TRIGGER_UNSOL; 1275 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1276 } 1277 /* XXX to be removed */ 1278 /* Clear interrupt and exit */ 1279#ifdef HDAC_INTR_EXTRA 1280 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1281#endif 1282 } 1283 1284 if (intsts & HDAC_INTSTS_SIS_MASK) { 1285 for (i = 0; i < sc->num_chans; i++) { 1286 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1287 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1288 trigger |= (1 << i); 1289 } 1290 /* XXX to be removed */ 1291#ifdef HDAC_INTR_EXTRA 1292 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1293 HDAC_INTSTS_SIS_MASK); 1294#endif 1295 } 1296 1297 hdac_unlock(sc); 1298 1299 for (i = 0; i < sc->num_chans; i++) { 1300 if (trigger & (1 << i)) 1301 chn_intr(sc->chans[i].c); 1302 } 1303 if (trigger & HDAC_TRIGGER_UNSOL) 1304 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1305} 1306 1307/**************************************************************************** 1308 * int hdac_reset(hdac_softc *, int) 1309 * 1310 * Reset the hdac to a quiescent and known state. 1311 ****************************************************************************/ 1312static int 1313hdac_reset(struct hdac_softc *sc, int wakeup) 1314{ 1315 uint32_t gctl; 1316 int count, i; 1317 1318 /* 1319 * Stop all Streams DMA engine 1320 */ 1321 for (i = 0; i < sc->num_iss; i++) 1322 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1323 for (i = 0; i < sc->num_oss; i++) 1324 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1325 for (i = 0; i < sc->num_bss; i++) 1326 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1327 1328 /* 1329 * Stop Control DMA engines. 1330 */ 1331 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1332 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1333 1334 /* 1335 * Reset DMA position buffer. 1336 */ 1337 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1338 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1339 1340 /* 1341 * Reset the controller. The reset must remain asserted for 1342 * a minimum of 100us. 1343 */ 1344 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1345 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1346 count = 10000; 1347 do { 1348 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1349 if (!(gctl & HDAC_GCTL_CRST)) 1350 break; 1351 DELAY(10); 1352 } while (--count); 1353 if (gctl & HDAC_GCTL_CRST) { 1354 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1355 return (ENXIO); 1356 } 1357 1358 /* If wakeup is not requested - leave the controller in reset state. */ 1359 if (!wakeup) 1360 return (0); 1361 1362 DELAY(100); 1363 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1364 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1365 count = 10000; 1366 do { 1367 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1368 if (gctl & HDAC_GCTL_CRST) 1369 break; 1370 DELAY(10); 1371 } while (--count); 1372 if (!(gctl & HDAC_GCTL_CRST)) { 1373 device_printf(sc->dev, "Device stuck in reset\n"); 1374 return (ENXIO); 1375 } 1376 1377 /* 1378 * Wait for codecs to finish their own reset sequence. The delay here 1379 * should be of 250us but for some reasons, on it's not enough on my 1380 * computer. Let's use twice as much as necessary to make sure that 1381 * it's reset properly. 1382 */ 1383 DELAY(1000); 1384 1385 return (0); 1386} 1387 1388 1389/**************************************************************************** 1390 * int hdac_get_capabilities(struct hdac_softc *); 1391 * 1392 * Retreive the general capabilities of the hdac; 1393 * Number of Input Streams 1394 * Number of Output Streams 1395 * Number of bidirectional Streams 1396 * 64bit ready 1397 * CORB and RIRB sizes 1398 ****************************************************************************/ 1399static int 1400hdac_get_capabilities(struct hdac_softc *sc) 1401{ 1402 uint16_t gcap; 1403 uint8_t corbsize, rirbsize; 1404 1405 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1406 sc->num_iss = HDAC_GCAP_ISS(gcap); 1407 sc->num_oss = HDAC_GCAP_OSS(gcap); 1408 sc->num_bss = HDAC_GCAP_BSS(gcap); 1409 1410 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1411 1412 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1413 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1414 HDAC_CORBSIZE_CORBSZCAP_256) 1415 sc->corb_size = 256; 1416 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1417 HDAC_CORBSIZE_CORBSZCAP_16) 1418 sc->corb_size = 16; 1419 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1420 HDAC_CORBSIZE_CORBSZCAP_2) 1421 sc->corb_size = 2; 1422 else { 1423 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1424 __func__, corbsize); 1425 return (ENXIO); 1426 } 1427 1428 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1429 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1430 HDAC_RIRBSIZE_RIRBSZCAP_256) 1431 sc->rirb_size = 256; 1432 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1433 HDAC_RIRBSIZE_RIRBSZCAP_16) 1434 sc->rirb_size = 16; 1435 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1436 HDAC_RIRBSIZE_RIRBSZCAP_2) 1437 sc->rirb_size = 2; 1438 else { 1439 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1440 __func__, rirbsize); 1441 return (ENXIO); 1442 } 1443 1444 HDA_BOOTHVERBOSE( 1445 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1446 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1447 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1448 sc->num_iss, sc->num_oss, sc->num_bss); 1449 ); 1450 1451 return (0); 1452} 1453 1454 1455/**************************************************************************** 1456 * void hdac_dma_cb 1457 * 1458 * This function is called by bus_dmamap_load when the mapping has been 1459 * established. We just record the physical address of the mapping into 1460 * the struct hdac_dma passed in. 1461 ****************************************************************************/ 1462static void 1463hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1464{ 1465 struct hdac_dma *dma; 1466 1467 if (error == 0) { 1468 dma = (struct hdac_dma *)callback_arg; 1469 dma->dma_paddr = segs[0].ds_addr; 1470 } 1471} 1472 1473 1474/**************************************************************************** 1475 * int hdac_dma_alloc 1476 * 1477 * This function allocate and setup a dma region (struct hdac_dma). 1478 * It must be freed by a corresponding hdac_dma_free. 1479 ****************************************************************************/ 1480static int 1481hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1482{ 1483 bus_size_t roundsz; 1484 int result; 1485 int lowaddr; 1486 1487 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1488 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1489 BUS_SPACE_MAXADDR_32BIT; 1490 bzero(dma, sizeof(*dma)); 1491 1492 /* 1493 * Create a DMA tag 1494 */ 1495 result = bus_dma_tag_create(NULL, /* parent */ 1496 HDAC_DMA_ALIGNMENT, /* alignment */ 1497 0, /* boundary */ 1498 lowaddr, /* lowaddr */ 1499 BUS_SPACE_MAXADDR, /* highaddr */ 1500 NULL, /* filtfunc */ 1501 NULL, /* fistfuncarg */ 1502 roundsz, /* maxsize */ 1503 1, /* nsegments */ 1504 roundsz, /* maxsegsz */ 1505 0, /* flags */ 1506 NULL, /* lockfunc */ 1507 NULL, /* lockfuncarg */ 1508 &dma->dma_tag); /* dmat */ 1509 if (result != 0) { 1510 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1511 __func__, result); 1512 goto hdac_dma_alloc_fail; 1513 } 1514 1515 /* 1516 * Allocate DMA memory 1517 */ 1518 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1519 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1520 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1521 &dma->dma_map); 1522 if (result != 0) { 1523 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1524 __func__, result); 1525 goto hdac_dma_alloc_fail; 1526 } 1527 1528 dma->dma_size = roundsz; 1529 1530 /* 1531 * Map the memory 1532 */ 1533 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1534 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1535 if (result != 0 || dma->dma_paddr == 0) { 1536 if (result == 0) 1537 result = ENOMEM; 1538 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1539 __func__, result); 1540 goto hdac_dma_alloc_fail; 1541 } 1542 1543 HDA_BOOTHVERBOSE( 1544 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1545 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1546 ); 1547 1548 return (0); 1549 1550hdac_dma_alloc_fail: 1551 hdac_dma_free(sc, dma); 1552 1553 return (result); 1554} 1555 1556 1557/**************************************************************************** 1558 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1559 * 1560 * Free a struct dhac_dma that has been previously allocated via the 1561 * hdac_dma_alloc function. 1562 ****************************************************************************/ 1563static void 1564hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1565{ 1566 if (dma->dma_map != NULL) { 1567#if 0 1568 /* Flush caches */ 1569 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1570 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1571#endif 1572 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1573 } 1574 if (dma->dma_vaddr != NULL) { 1575 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1576 dma->dma_vaddr = NULL; 1577 } 1578 dma->dma_map = NULL; 1579 if (dma->dma_tag != NULL) { 1580 bus_dma_tag_destroy(dma->dma_tag); 1581 dma->dma_tag = NULL; 1582 } 1583 dma->dma_size = 0; 1584} 1585 1586/**************************************************************************** 1587 * int hdac_mem_alloc(struct hdac_softc *) 1588 * 1589 * Allocate all the bus resources necessary to speak with the physical 1590 * controller. 1591 ****************************************************************************/ 1592static int 1593hdac_mem_alloc(struct hdac_softc *sc) 1594{ 1595 struct hdac_mem *mem; 1596 1597 mem = &sc->mem; 1598 mem->mem_rid = PCIR_BAR(0); 1599 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1600 &mem->mem_rid, RF_ACTIVE); 1601 if (mem->mem_res == NULL) { 1602 device_printf(sc->dev, 1603 "%s: Unable to allocate memory resource\n", __func__); 1604 return (ENOMEM); 1605 } 1606 mem->mem_tag = rman_get_bustag(mem->mem_res); 1607 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1608 1609 return (0); 1610} 1611 1612/**************************************************************************** 1613 * void hdac_mem_free(struct hdac_softc *) 1614 * 1615 * Free up resources previously allocated by hdac_mem_alloc. 1616 ****************************************************************************/ 1617static void 1618hdac_mem_free(struct hdac_softc *sc) 1619{ 1620 struct hdac_mem *mem; 1621 1622 mem = &sc->mem; 1623 if (mem->mem_res != NULL) 1624 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1625 mem->mem_res); 1626 mem->mem_res = NULL; 1627} 1628 1629/**************************************************************************** 1630 * int hdac_irq_alloc(struct hdac_softc *) 1631 * 1632 * Allocate and setup the resources necessary for interrupt handling. 1633 ****************************************************************************/ 1634static int 1635hdac_irq_alloc(struct hdac_softc *sc) 1636{ 1637 struct hdac_irq *irq; 1638 int result; 1639 1640 irq = &sc->irq; 1641 irq->irq_rid = 0x0; 1642 1643#ifdef HDAC_MSI_ENABLED 1644 if ((sc->flags & HDAC_F_MSI) && 1645 (result = pci_msi_count(sc->dev)) == 1 && 1646 pci_alloc_msi(sc->dev, &result) == 0) 1647 irq->irq_rid = 0x1; 1648 else 1649#endif 1650 sc->flags &= ~HDAC_F_MSI; 1651 1652 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1653 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1654 if (irq->irq_res == NULL) { 1655 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1656 __func__); 1657 goto hdac_irq_alloc_fail; 1658 } 1659 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1660 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1661 if (result != 0) { 1662 device_printf(sc->dev, 1663 "%s: Unable to setup interrupt handler (%x)\n", 1664 __func__, result); 1665 goto hdac_irq_alloc_fail; 1666 } 1667 1668 return (0); 1669 1670hdac_irq_alloc_fail: 1671 hdac_irq_free(sc); 1672 1673 return (ENXIO); 1674} 1675 1676/**************************************************************************** 1677 * void hdac_irq_free(struct hdac_softc *) 1678 * 1679 * Free up resources previously allocated by hdac_irq_alloc. 1680 ****************************************************************************/ 1681static void 1682hdac_irq_free(struct hdac_softc *sc) 1683{ 1684 struct hdac_irq *irq; 1685 1686 irq = &sc->irq; 1687 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1688 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1689 if (irq->irq_res != NULL) 1690 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1691 irq->irq_res); 1692#ifdef HDAC_MSI_ENABLED 1693 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1694 pci_release_msi(sc->dev); 1695#endif 1696 irq->irq_handle = NULL; 1697 irq->irq_res = NULL; 1698 irq->irq_rid = 0x0; 1699} 1700 1701/**************************************************************************** 1702 * void hdac_corb_init(struct hdac_softc *) 1703 * 1704 * Initialize the corb registers for operations but do not start it up yet. 1705 * The CORB engine must not be running when this function is called. 1706 ****************************************************************************/ 1707static void 1708hdac_corb_init(struct hdac_softc *sc) 1709{ 1710 uint8_t corbsize; 1711 uint64_t corbpaddr; 1712 1713 /* Setup the CORB size. */ 1714 switch (sc->corb_size) { 1715 case 256: 1716 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1717 break; 1718 case 16: 1719 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1720 break; 1721 case 2: 1722 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1723 break; 1724 default: 1725 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1726 } 1727 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1728 1729 /* Setup the CORB Address in the hdac */ 1730 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1731 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1732 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1733 1734 /* Set the WP and RP */ 1735 sc->corb_wp = 0; 1736 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1737 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1738 /* 1739 * The HDA specification indicates that the CORBRPRST bit will always 1740 * read as zero. Unfortunately, it seems that at least the 82801G 1741 * doesn't reset the bit to zero, which stalls the corb engine. 1742 * manually reset the bit to zero before continuing. 1743 */ 1744 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1745 1746 /* Enable CORB error reporting */ 1747#if 0 1748 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1749#endif 1750} 1751 1752/**************************************************************************** 1753 * void hdac_rirb_init(struct hdac_softc *) 1754 * 1755 * Initialize the rirb registers for operations but do not start it up yet. 1756 * The RIRB engine must not be running when this function is called. 1757 ****************************************************************************/ 1758static void 1759hdac_rirb_init(struct hdac_softc *sc) 1760{ 1761 uint8_t rirbsize; 1762 uint64_t rirbpaddr; 1763 1764 /* Setup the RIRB size. */ 1765 switch (sc->rirb_size) { 1766 case 256: 1767 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1768 break; 1769 case 16: 1770 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1771 break; 1772 case 2: 1773 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1774 break; 1775 default: 1776 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1777 } 1778 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1779 1780 /* Setup the RIRB Address in the hdac */ 1781 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1782 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1783 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1784 1785 /* Setup the WP and RP */ 1786 sc->rirb_rp = 0; 1787 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1788 1789 /* Setup the interrupt threshold */ 1790 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1791 1792 /* Enable Overrun and response received reporting */ 1793#if 0 1794 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1795 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1796#else 1797 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1798#endif 1799 1800#if 0 1801 /* 1802 * Make sure that the Host CPU cache doesn't contain any dirty 1803 * cache lines that falls in the rirb. If I understood correctly, it 1804 * should be sufficient to do this only once as the rirb is purely 1805 * read-only from now on. 1806 */ 1807 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1808 BUS_DMASYNC_PREREAD); 1809#endif 1810} 1811 1812/**************************************************************************** 1813 * void hdac_corb_start(hdac_softc *) 1814 * 1815 * Startup the corb DMA engine 1816 ****************************************************************************/ 1817static void 1818hdac_corb_start(struct hdac_softc *sc) 1819{ 1820 uint32_t corbctl; 1821 1822 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1823 corbctl |= HDAC_CORBCTL_CORBRUN; 1824 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1825} 1826 1827/**************************************************************************** 1828 * void hdac_rirb_start(hdac_softc *) 1829 * 1830 * Startup the rirb DMA engine 1831 ****************************************************************************/ 1832static void 1833hdac_rirb_start(struct hdac_softc *sc) 1834{ 1835 uint32_t rirbctl; 1836 1837 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1838 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1839 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1840} 1841 1842 1843/**************************************************************************** 1844 * void hdac_scan_codecs(struct hdac_softc *, int) 1845 * 1846 * Scan the bus for available codecs, starting with num. 1847 ****************************************************************************/ 1848static void 1849hdac_scan_codecs(struct hdac_softc *sc) 1850{ 1851 struct hdac_codec *codec; 1852 int i; 1853 uint16_t statests; 1854 1855 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1856 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1857 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1858 /* We have found a codec. */ 1859 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1860 M_HDAC, M_ZERO | M_NOWAIT); 1861 if (codec == NULL) { 1862 device_printf(sc->dev, 1863 "Unable to allocate memory for codec\n"); 1864 continue; 1865 } 1866 codec->commands = NULL; 1867 codec->responses_received = 0; 1868 codec->verbs_sent = 0; 1869 codec->sc = sc; 1870 codec->cad = i; 1871 sc->codecs[i] = codec; 1872 hdac_probe_codec(codec); 1873 } 1874 } 1875 /* All codecs have been probed, now try to attach drivers to them */ 1876 /* bus_generic_attach(sc->dev); */ 1877} 1878 1879/**************************************************************************** 1880 * void hdac_probe_codec(struct hdac_softc *, int) 1881 * 1882 * Probe a the given codec_id for available function groups. 1883 ****************************************************************************/ 1884static void 1885hdac_probe_codec(struct hdac_codec *codec) 1886{ 1887 struct hdac_softc *sc = codec->sc; 1888 uint32_t vendorid, revisionid, subnode; 1889 int startnode; 1890 int endnode; 1891 int i; 1892 nid_t cad = codec->cad; 1893 1894 HDA_BOOTVERBOSE( 1895 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1896 ); 1897 vendorid = hdac_command(sc, 1898 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1899 cad); 1900 revisionid = hdac_command(sc, 1901 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1902 cad); 1903 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1904 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1905 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1906 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1907 1908 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1909 device_printf(sc->dev, "Codec #%d is not responding!" 1910 " Probing aborted.\n", cad); 1911 return; 1912 } 1913 1914 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1915 cad, hdac_codec_name(codec)); 1916 HDA_BOOTVERBOSE( 1917 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1918 hdac_codec_id(codec)); 1919 device_printf(sc->dev, " Vendor: 0x%04x\n", 1920 codec->vendor_id); 1921 device_printf(sc->dev, " Device: 0x%04x\n", 1922 codec->device_id); 1923 device_printf(sc->dev, " Revision: 0x%02x\n", 1924 codec->revision_id); 1925 device_printf(sc->dev, " Stepping: 0x%02x\n", 1926 codec->stepping_id); 1927 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1928 sc->pci_subvendor); 1929 ); 1930 subnode = hdac_command(sc, 1931 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1932 cad); 1933 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1934 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1935 1936 HDA_BOOTHVERBOSE( 1937 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1938 startnode, endnode); 1939 ); 1940 1941 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1942 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1943 if (codec->fgs == NULL) { 1944 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1945 __func__); 1946 return; 1947 } 1948 1949 for (i = startnode; i < endnode; i++) 1950 hdac_probe_function(codec, i); 1951 return; 1952} 1953 1954/* 1955 * Probe codec function and add it to the list. 1956 */ 1957static void 1958hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1959{ 1960 struct hdac_softc *sc = codec->sc; 1961 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1962 uint32_t fctgrptype; 1963 uint32_t res; 1964 nid_t cad = codec->cad; 1965 1966 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1967 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1968 1969 devinfo->nid = nid; 1970 devinfo->node_type = fctgrptype; 1971 devinfo->codec = codec; 1972 1973 res = hdac_command(sc, 1974 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1975 1976 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1977 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1978 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1979 1980 HDA_BOOTVERBOSE( 1981 device_printf(sc->dev, 1982 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1983 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1984 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1985 "unknown", nid, devinfo->startnode, devinfo->endnode, 1986 devinfo->nodecnt); 1987 ); 1988 1989 if (devinfo->nodecnt > 0) 1990 devinfo->widget = (struct hdac_widget *)malloc( 1991 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1992 M_NOWAIT | M_ZERO); 1993 else 1994 devinfo->widget = NULL; 1995 1996 if (devinfo->widget == NULL) { 1997 device_printf(sc->dev, "unable to allocate widgets!\n"); 1998 devinfo->endnode = devinfo->startnode; 1999 devinfo->nodecnt = 0; 2000 return; 2001 } 2002 2003 codec->num_fgs++; 2004} 2005 2006static void 2007hdac_widget_connection_parse(struct hdac_widget *w) 2008{ 2009 struct hdac_softc *sc = w->devinfo->codec->sc; 2010 uint32_t res; 2011 int i, j, max, ents, entnum; 2012 nid_t cad = w->devinfo->codec->cad; 2013 nid_t nid = w->nid; 2014 nid_t cnid, addcnid, prevcnid; 2015 2016 w->nconns = 0; 2017 2018 res = hdac_command(sc, 2019 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2020 2021 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2022 2023 if (ents < 1) 2024 return; 2025 2026 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2027 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2028 prevcnid = 0; 2029 2030#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2031#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2032#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2033#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2034#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2035 2036 for (i = 0; i < ents; i += entnum) { 2037 res = hdac_command(sc, 2038 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2039 for (j = 0; j < entnum; j++) { 2040 cnid = CONN_CNID(res, entnum, j); 2041 if (cnid == 0) { 2042 if (w->nconns < ents) 2043 device_printf(sc->dev, 2044 "%s: nid=%d WARNING: zero cnid " 2045 "entnum=%d j=%d index=%d " 2046 "entries=%d found=%d res=0x%08x\n", 2047 __func__, nid, entnum, j, i, 2048 ents, w->nconns, res); 2049 else 2050 goto getconns_out; 2051 } 2052 if (cnid < w->devinfo->startnode || 2053 cnid >= w->devinfo->endnode) { 2054 HDA_BOOTVERBOSE( 2055 device_printf(sc->dev, 2056 "GHOST: nid=%d j=%d " 2057 "entnum=%d index=%d res=0x%08x\n", 2058 nid, j, entnum, i, res); 2059 ); 2060 } 2061 if (CONN_RANGE(res, entnum, j) == 0) 2062 addcnid = cnid; 2063 else if (prevcnid == 0 || prevcnid >= cnid) { 2064 device_printf(sc->dev, 2065 "%s: WARNING: Invalid child range " 2066 "nid=%d index=%d j=%d entnum=%d " 2067 "prevcnid=%d cnid=%d res=0x%08x\n", 2068 __func__, nid, i, j, entnum, prevcnid, 2069 cnid, res); 2070 addcnid = cnid; 2071 } else 2072 addcnid = prevcnid + 1; 2073 while (addcnid <= cnid) { 2074 if (w->nconns > max) { 2075 device_printf(sc->dev, 2076 "Adding %d (nid=%d): " 2077 "Max connection reached! max=%d\n", 2078 addcnid, nid, max + 1); 2079 goto getconns_out; 2080 } 2081 w->connsenable[w->nconns] = 1; 2082 w->conns[w->nconns++] = addcnid++; 2083 } 2084 prevcnid = cnid; 2085 } 2086 } 2087 2088getconns_out: 2089 return; 2090} 2091 2092static uint32_t 2093hdac_widget_pin_patch(uint32_t config, const char *str) 2094{ 2095 char buf[256]; 2096 char *key, *value, *rest, *bad; 2097 int ival, i; 2098 2099 strlcpy(buf, str, sizeof(buf)); 2100 rest = buf; 2101 while ((key = strsep(&rest, "=")) != NULL) { 2102 value = strsep(&rest, " \t"); 2103 if (value == NULL) 2104 break; 2105 ival = strtol(value, &bad, 10); 2106 if (strcmp(key, "seq") == 0) { 2107 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2108 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2109 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2110 } else if (strcmp(key, "as") == 0) { 2111 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2112 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2113 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2114 } else if (strcmp(key, "misc") == 0) { 2115 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2116 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2117 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2118 } else if (strcmp(key, "color") == 0) { 2119 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2120 if (bad[0] == 0) { 2121 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2122 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2123 }; 2124 for (i = 0; i < 16; i++) { 2125 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2126 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2127 break; 2128 } 2129 } 2130 } else if (strcmp(key, "ctype") == 0) { 2131 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2132 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2133 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2134 } else if (strcmp(key, "device") == 0) { 2135 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2136 if (bad[0] == 0) { 2137 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2138 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2139 continue; 2140 }; 2141 for (i = 0; i < 16; i++) { 2142 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2143 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2144 break; 2145 } 2146 } 2147 } else if (strcmp(key, "loc") == 0) { 2148 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2149 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2150 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2151 } else if (strcmp(key, "conn") == 0) { 2152 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2153 if (bad[0] == 0) { 2154 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2155 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2156 continue; 2157 }; 2158 for (i = 0; i < 4; i++) { 2159 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2160 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2161 break; 2162 } 2163 } 2164 } 2165 } 2166 return (config); 2167} 2168 2169static uint32_t 2170hdac_widget_pin_getconfig(struct hdac_widget *w) 2171{ 2172 struct hdac_softc *sc; 2173 uint32_t config, orig, id; 2174 nid_t cad, nid; 2175 char buf[32]; 2176 const char *res = NULL, *patch = NULL; 2177 2178 sc = w->devinfo->codec->sc; 2179 cad = w->devinfo->codec->cad; 2180 nid = w->nid; 2181 id = hdac_codec_id(w->devinfo->codec); 2182 2183 config = hdac_command(sc, 2184 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2185 cad); 2186 orig = config; 2187 2188 HDA_BOOTVERBOSE( 2189 hdac_dump_pin_config(w, orig); 2190 ); 2191 2192 /* XXX: Old patches require complete review. 2193 * Now they may create more problem then solve due to 2194 * incorrect associations. 2195 */ 2196 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2197 switch (nid) { 2198 case 26: 2199 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2200 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2201 break; 2202 case 27: 2203 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2204 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2205 break; 2206 default: 2207 break; 2208 } 2209 } else if (id == HDA_CODEC_ALC880 && 2210 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2211 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2212 /* 2213 * Super broken BIOS 2214 */ 2215 switch (nid) { 2216 case 24: /* MIC1 */ 2217 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2218 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2219 break; 2220 case 25: /* XXX MIC2 */ 2221 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2222 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2223 break; 2224 case 26: /* LINE1 */ 2225 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2226 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2227 break; 2228 case 27: /* XXX LINE2 */ 2229 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2230 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2231 break; 2232 case 28: /* CD */ 2233 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2234 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2235 break; 2236 } 2237 } else if (id == HDA_CODEC_ALC883 && 2238 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2239 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2240 switch (nid) { 2241 case 25: 2242 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2243 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2244 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2245 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2246 break; 2247 case 28: 2248 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2249 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2250 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2251 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2252 break; 2253 } 2254 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2255 HP_V3000_SUBVENDOR) { 2256 switch (nid) { 2257 case 18: 2258 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2259 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2260 break; 2261 case 20: 2262 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2263 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2264 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2265 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2266 break; 2267 case 21: 2268 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2269 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2270 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2271 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2272 break; 2273 } 2274 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2275 HP_DV5000_SUBVENDOR) { 2276 switch (nid) { 2277 case 20: 2278 case 21: 2279 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2280 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2281 break; 2282 } 2283 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2284 ASUS_W6F_SUBVENDOR) { 2285 switch (nid) { 2286 case 11: 2287 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2288 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2289 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2290 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2291 break; 2292 case 12: 2293 case 14: 2294 case 16: 2295 case 31: 2296 case 32: 2297 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2298 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2299 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2300 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2301 break; 2302 case 15: 2303 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2304 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2305 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2306 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2307 break; 2308 } 2309 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2310 UNIWILL_9075_SUBVENDOR) { 2311 switch (nid) { 2312 case 15: 2313 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2314 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2315 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2316 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2317 break; 2318 } 2319 } 2320 2321 /* New patches */ 2322 if (id == HDA_CODEC_AD1986A && 2323 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2324 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2325 switch (nid) { 2326 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2327 patch = "device=Line-in as=8 seq=1"; 2328 break; 2329 case 29: 2330 patch = "device=Mic as=8 seq=2"; 2331 break; 2332 case 31: /* Lot of inputs configured with as=15 and unusable */ 2333 patch = "as=8 seq=3"; 2334 break; 2335 case 32: 2336 patch = "as=8 seq=4"; 2337 break; 2338 case 34: 2339 patch = "as=8 seq=5"; 2340 break; 2341 case 36: 2342 patch = "as=8 seq=6"; 2343 break; 2344 } 2345 } else if (id == HDA_CODEC_ALC260 && 2346 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2347 switch (nid) { 2348 case 16: 2349 patch = "seq=15 device=Headphones"; 2350 break; 2351 } 2352 } else if (id == HDA_CODEC_ALC268 && 2353 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2354 switch (nid) { 2355 case 28: 2356 patch = "device=CD conn=fixed"; 2357 break; 2358 } 2359 } 2360 2361 if (patch != NULL) 2362 config = hdac_widget_pin_patch(config, patch); 2363 2364 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2365 if (resource_string_value(device_get_name(sc->dev), 2366 device_get_unit(sc->dev), buf, &res) == 0) { 2367 if (strncmp(res, "0x", 2) == 0) { 2368 config = strtol(res + 2, NULL, 16); 2369 } else { 2370 config = hdac_widget_pin_patch(config, res); 2371 } 2372 } 2373 2374 HDA_BOOTVERBOSE( 2375 if (config != orig) 2376 device_printf(sc->dev, 2377 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2378 nid, orig, config); 2379 ); 2380 2381 return (config); 2382} 2383 2384static uint32_t 2385hdac_widget_pin_getcaps(struct hdac_widget *w) 2386{ 2387 struct hdac_softc *sc; 2388 uint32_t caps, orig, id; 2389 nid_t cad, nid; 2390 2391 sc = w->devinfo->codec->sc; 2392 cad = w->devinfo->codec->cad; 2393 nid = w->nid; 2394 id = hdac_codec_id(w->devinfo->codec); 2395 2396 caps = hdac_command(sc, 2397 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2398 orig = caps; 2399 2400 HDA_BOOTVERBOSE( 2401 if (caps != orig) 2402 device_printf(sc->dev, 2403 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2404 nid, orig, caps); 2405 ); 2406 2407 return (caps); 2408} 2409 2410static void 2411hdac_widget_pin_parse(struct hdac_widget *w) 2412{ 2413 struct hdac_softc *sc = w->devinfo->codec->sc; 2414 uint32_t config, pincap; 2415 const char *devstr, *connstr; 2416 nid_t cad = w->devinfo->codec->cad; 2417 nid_t nid = w->nid; 2418 2419 config = hdac_widget_pin_getconfig(w); 2420 w->wclass.pin.config = config; 2421 2422 pincap = hdac_widget_pin_getcaps(w); 2423 w->wclass.pin.cap = pincap; 2424 2425 w->wclass.pin.ctrl = hdac_command(sc, 2426 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2427 2428 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2429 w->param.eapdbtl = hdac_command(sc, 2430 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2431 w->param.eapdbtl &= 0x7; 2432 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2433 } else 2434 w->param.eapdbtl = HDAC_INVALID; 2435 2436 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2437 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2438 2439 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2440 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2441 2442 strlcat(w->name, ": ", sizeof(w->name)); 2443 strlcat(w->name, devstr, sizeof(w->name)); 2444 strlcat(w->name, " (", sizeof(w->name)); 2445 strlcat(w->name, connstr, sizeof(w->name)); 2446 strlcat(w->name, ")", sizeof(w->name)); 2447} 2448 2449static uint32_t 2450hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2451{ 2452 struct hdac_softc *sc; 2453 uint32_t caps, orig, id; 2454 nid_t cad, nid, beeper = -1; 2455 2456 sc = w->devinfo->codec->sc; 2457 cad = w->devinfo->codec->cad; 2458 nid = w->nid; 2459 id = hdac_codec_id(w->devinfo->codec); 2460 2461 caps = hdac_command(sc, 2462 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2463 cad); 2464 orig = caps; 2465 2466 /* On some codecs beeper is an input pin, but it is not recordable 2467 alone. Also most of BIOSes does not declare beeper pin. 2468 Change beeper pin node type to beeper to help parser. */ 2469 *waspin = 0; 2470 switch (id) { 2471 case HDA_CODEC_AD1988: 2472 case HDA_CODEC_AD1988B: 2473 beeper = 26; 2474 break; 2475 case HDA_CODEC_ALC260: 2476 beeper = 23; 2477 break; 2478 case HDA_CODEC_ALC262: 2479 case HDA_CODEC_ALC268: 2480 case HDA_CODEC_ALC880: 2481 case HDA_CODEC_ALC882: 2482 case HDA_CODEC_ALC883: 2483 case HDA_CODEC_ALC885: 2484 case HDA_CODEC_ALC888: 2485 case HDA_CODEC_ALC889: 2486 beeper = 29; 2487 break; 2488 } 2489 if (nid == beeper) { 2490 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2491 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2492 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2493 *waspin = 1; 2494 } 2495 2496 HDA_BOOTVERBOSE( 2497 if (caps != orig) { 2498 device_printf(sc->dev, 2499 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2500 nid, orig, caps); 2501 } 2502 ); 2503 2504 return (caps); 2505} 2506 2507static void 2508hdac_widget_parse(struct hdac_widget *w) 2509{ 2510 struct hdac_softc *sc = w->devinfo->codec->sc; 2511 uint32_t wcap, cap; 2512 char *typestr; 2513 nid_t cad = w->devinfo->codec->cad; 2514 nid_t nid = w->nid; 2515 2516 wcap = hdac_widget_getcaps(w, &w->waspin); 2517 2518 w->param.widget_cap = wcap; 2519 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2520 2521 switch (w->type) { 2522 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2523 typestr = "audio output"; 2524 break; 2525 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2526 typestr = "audio input"; 2527 break; 2528 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2529 typestr = "audio mixer"; 2530 break; 2531 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2532 typestr = "audio selector"; 2533 break; 2534 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2535 typestr = "pin"; 2536 break; 2537 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2538 typestr = "power widget"; 2539 break; 2540 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2541 typestr = "volume widget"; 2542 break; 2543 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2544 typestr = "beep widget"; 2545 break; 2546 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2547 typestr = "vendor widget"; 2548 break; 2549 default: 2550 typestr = "unknown type"; 2551 break; 2552 } 2553 2554 strlcpy(w->name, typestr, sizeof(w->name)); 2555 2556 hdac_widget_connection_parse(w); 2557 2558 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2559 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2560 w->param.outamp_cap = 2561 hdac_command(sc, 2562 HDA_CMD_GET_PARAMETER(cad, nid, 2563 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2564 else 2565 w->param.outamp_cap = 2566 w->devinfo->function.audio.outamp_cap; 2567 } else 2568 w->param.outamp_cap = 0; 2569 2570 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2571 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2572 w->param.inamp_cap = 2573 hdac_command(sc, 2574 HDA_CMD_GET_PARAMETER(cad, nid, 2575 HDA_PARAM_INPUT_AMP_CAP), cad); 2576 else 2577 w->param.inamp_cap = 2578 w->devinfo->function.audio.inamp_cap; 2579 } else 2580 w->param.inamp_cap = 0; 2581 2582 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2583 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2584 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2585 cap = hdac_command(sc, 2586 HDA_CMD_GET_PARAMETER(cad, nid, 2587 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2588 w->param.supp_stream_formats = (cap != 0) ? cap : 2589 w->devinfo->function.audio.supp_stream_formats; 2590 cap = hdac_command(sc, 2591 HDA_CMD_GET_PARAMETER(cad, nid, 2592 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2593 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2594 w->devinfo->function.audio.supp_pcm_size_rate; 2595 } else { 2596 w->param.supp_stream_formats = 2597 w->devinfo->function.audio.supp_stream_formats; 2598 w->param.supp_pcm_size_rate = 2599 w->devinfo->function.audio.supp_pcm_size_rate; 2600 } 2601 } else { 2602 w->param.supp_stream_formats = 0; 2603 w->param.supp_pcm_size_rate = 0; 2604 } 2605 2606 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2607 hdac_widget_pin_parse(w); 2608} 2609 2610static struct hdac_widget * 2611hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2612{ 2613 if (devinfo == NULL || devinfo->widget == NULL || 2614 nid < devinfo->startnode || nid >= devinfo->endnode) 2615 return (NULL); 2616 return (&devinfo->widget[nid - devinfo->startnode]); 2617} 2618 2619static __inline int 2620hda_poll_channel(struct hdac_chan *ch) 2621{ 2622 uint32_t sz, delta; 2623 volatile uint32_t ptr; 2624 2625 if (!(ch->flags & HDAC_CHN_RUNNING)) 2626 return (0); 2627 2628 sz = ch->blksz * ch->blkcnt; 2629 if (ch->dmapos != NULL) 2630 ptr = *(ch->dmapos); 2631 else 2632 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2633 ch->off + HDAC_SDLPIB); 2634 ch->ptr = ptr; 2635 ptr %= sz; 2636 ptr &= ~(ch->blksz - 1); 2637 delta = (sz + ptr - ch->prevptr) % sz; 2638 2639 if (delta < ch->blksz) 2640 return (0); 2641 2642 ch->prevptr = ptr; 2643 2644 return (1); 2645} 2646 2647static void 2648hda_poll_callback(void *arg) 2649{ 2650 struct hdac_softc *sc = arg; 2651 uint32_t trigger; 2652 int i, active = 0; 2653 2654 if (sc == NULL) 2655 return; 2656 2657 hdac_lock(sc); 2658 if (sc->polling == 0) { 2659 hdac_unlock(sc); 2660 return; 2661 } 2662 2663 trigger = 0; 2664 for (i = 0; i < sc->num_chans; i++) { 2665 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2666 continue; 2667 active = 1; 2668 if (hda_poll_channel(&sc->chans[i])) 2669 trigger |= (1 << i); 2670 } 2671 2672 /* XXX */ 2673 if (active) 2674 callout_reset(&sc->poll_hda, sc->poll_ticks, 2675 hda_poll_callback, sc); 2676 2677 hdac_unlock(sc); 2678 2679 for (i = 0; i < sc->num_chans; i++) { 2680 if (trigger & (1 << i)) 2681 chn_intr(sc->chans[i].c); 2682 } 2683} 2684 2685static int 2686hdac_rirb_flush(struct hdac_softc *sc) 2687{ 2688 struct hdac_rirb *rirb_base, *rirb; 2689 struct hdac_codec *codec; 2690 struct hdac_command_list *commands; 2691 nid_t cad; 2692 uint32_t resp; 2693 uint8_t rirbwp; 2694 int ret; 2695 2696 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2697 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2698#if 0 2699 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2700 BUS_DMASYNC_POSTREAD); 2701#endif 2702 2703 ret = 0; 2704 2705 while (sc->rirb_rp != rirbwp) { 2706 sc->rirb_rp++; 2707 sc->rirb_rp %= sc->rirb_size; 2708 rirb = &rirb_base[sc->rirb_rp]; 2709 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2710 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2711 sc->codecs[cad] == NULL) 2712 continue; 2713 resp = rirb->response; 2714 codec = sc->codecs[cad]; 2715 commands = codec->commands; 2716 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2717 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2718 ((resp >> 26) & 0xffff); 2719 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2720 } else if (commands != NULL && commands->num_commands > 0 && 2721 codec->responses_received < commands->num_commands) 2722 commands->responses[codec->responses_received++] = 2723 resp; 2724 ret++; 2725 } 2726 2727 return (ret); 2728} 2729 2730static int 2731hdac_unsolq_flush(struct hdac_softc *sc) 2732{ 2733 nid_t cad; 2734 uint32_t tag; 2735 int ret = 0; 2736 2737 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2738 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2739 while (sc->unsolq_rp != sc->unsolq_wp) { 2740 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2741 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2742 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2743 hdac_unsolicited_handler(sc->codecs[cad], tag); 2744 ret++; 2745 } 2746 sc->unsolq_st = HDAC_UNSOLQ_READY; 2747 } 2748 2749 return (ret); 2750} 2751 2752static void 2753hdac_poll_callback(void *arg) 2754{ 2755 struct hdac_softc *sc = arg; 2756 if (sc == NULL) 2757 return; 2758 2759 hdac_lock(sc); 2760 if (sc->polling == 0 || sc->poll_ival == 0) { 2761 hdac_unlock(sc); 2762 return; 2763 } 2764 if (hdac_rirb_flush(sc) != 0) 2765 hdac_unsolq_flush(sc); 2766 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2767 hdac_unlock(sc); 2768} 2769 2770static void 2771hdac_poll_reinit(struct hdac_softc *sc) 2772{ 2773 int i, pollticks, min = 1000000; 2774 struct hdac_chan *ch; 2775 2776 for (i = 0; i < sc->num_chans; i++) { 2777 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2778 continue; 2779 ch = &sc->chans[i]; 2780 pollticks = ((uint64_t)hz * ch->blksz) / 2781 ((uint64_t)sndbuf_getbps(ch->b) * 2782 sndbuf_getspd(ch->b)); 2783 pollticks >>= 1; 2784 if (pollticks > hz) 2785 pollticks = hz; 2786 if (pollticks < 1) { 2787 HDA_BOOTVERBOSE( 2788 device_printf(sc->dev, 2789 "%s: pollticks=%d < 1 !\n", 2790 __func__, pollticks); 2791 ); 2792 pollticks = 1; 2793 } 2794 if (min > pollticks) 2795 min = pollticks; 2796 } 2797 HDA_BOOTVERBOSE( 2798 device_printf(sc->dev, 2799 "%s: pollticks %d -> %d\n", 2800 __func__, sc->poll_ticks, min); 2801 ); 2802 sc->poll_ticks = min; 2803 if (min == 1000000) 2804 callout_stop(&sc->poll_hda); 2805 else 2806 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2807} 2808 2809static void 2810hdac_stream_stop(struct hdac_chan *ch) 2811{ 2812 struct hdac_softc *sc = ch->devinfo->codec->sc; 2813 uint32_t ctl; 2814 2815 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2816 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2817 HDAC_SDCTL_RUN); 2818 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2819 2820 ch->flags &= ~HDAC_CHN_RUNNING; 2821 2822 if (sc->polling != 0) 2823 hdac_poll_reinit(sc); 2824 2825 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2826 ctl &= ~(1 << (ch->off >> 5)); 2827 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2828} 2829 2830static void 2831hdac_stream_start(struct hdac_chan *ch) 2832{ 2833 struct hdac_softc *sc = ch->devinfo->codec->sc; 2834 uint32_t ctl; 2835 2836 ch->flags |= HDAC_CHN_RUNNING; 2837 2838 if (sc->polling != 0) 2839 hdac_poll_reinit(sc); 2840 2841 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2842 ctl |= 1 << (ch->off >> 5); 2843 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2844 2845 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2846 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2847 HDAC_SDCTL_RUN; 2848 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2849} 2850 2851static void 2852hdac_stream_reset(struct hdac_chan *ch) 2853{ 2854 struct hdac_softc *sc = ch->devinfo->codec->sc; 2855 int timeout = 1000; 2856 int to = timeout; 2857 uint32_t ctl; 2858 2859 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2860 ctl |= HDAC_SDCTL_SRST; 2861 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2862 do { 2863 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2864 if (ctl & HDAC_SDCTL_SRST) 2865 break; 2866 DELAY(10); 2867 } while (--to); 2868 if (!(ctl & HDAC_SDCTL_SRST)) { 2869 device_printf(sc->dev, "timeout in reset\n"); 2870 } 2871 ctl &= ~HDAC_SDCTL_SRST; 2872 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2873 to = timeout; 2874 do { 2875 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2876 if (!(ctl & HDAC_SDCTL_SRST)) 2877 break; 2878 DELAY(10); 2879 } while (--to); 2880 if (ctl & HDAC_SDCTL_SRST) 2881 device_printf(sc->dev, "can't reset!\n"); 2882} 2883 2884static void 2885hdac_stream_setid(struct hdac_chan *ch) 2886{ 2887 struct hdac_softc *sc = ch->devinfo->codec->sc; 2888 uint32_t ctl; 2889 2890 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2891 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2892 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2893 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2894} 2895 2896static void 2897hdac_bdl_setup(struct hdac_chan *ch) 2898{ 2899 struct hdac_softc *sc = ch->devinfo->codec->sc; 2900 struct hdac_bdle *bdle; 2901 uint64_t addr; 2902 uint32_t blksz, blkcnt; 2903 int i; 2904 2905 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2906 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2907 2908 blksz = ch->blksz; 2909 blkcnt = ch->blkcnt; 2910 2911 for (i = 0; i < blkcnt; i++, bdle++) { 2912 bdle->addrl = (uint32_t)addr; 2913 bdle->addrh = (uint32_t)(addr >> 32); 2914 bdle->len = blksz; 2915 bdle->ioc = 1; 2916 addr += blksz; 2917 } 2918 2919 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2920 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2921 addr = ch->bdl_dma.dma_paddr; 2922 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2923 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2924 if (ch->dmapos != NULL && 2925 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2926 addr = sc->pos_dma.dma_paddr; 2927 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2928 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2929 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2930 } 2931} 2932 2933static int 2934hdac_bdl_alloc(struct hdac_chan *ch) 2935{ 2936 struct hdac_softc *sc = ch->devinfo->codec->sc; 2937 int rc; 2938 2939 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2940 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2941 if (rc) { 2942 device_printf(sc->dev, "can't alloc bdl\n"); 2943 return (rc); 2944 } 2945 2946 return (0); 2947} 2948 2949static void 2950hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2951 int index, int lmute, int rmute, 2952 int left, int right, int dir) 2953{ 2954 uint16_t v = 0; 2955 2956 if (sc == NULL) 2957 return; 2958 2959 if (left != right || lmute != rmute) { 2960 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2961 (lmute << 7) | left; 2962 hdac_command(sc, 2963 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2964 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2965 (rmute << 7) | right; 2966 } else 2967 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2968 (lmute << 7) | left; 2969 2970 hdac_command(sc, 2971 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2972} 2973 2974static void 2975hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2976 int left, int right) 2977{ 2978 struct hdac_softc *sc; 2979 nid_t nid, cad; 2980 int lmute, rmute; 2981 2982 sc = ctl->widget->devinfo->codec->sc; 2983 cad = ctl->widget->devinfo->codec->cad; 2984 nid = ctl->widget->nid; 2985 2986 /* Save new values if valid. */ 2987 if (mute != HDA_AMP_MUTE_DEFAULT) 2988 ctl->muted = mute; 2989 if (left != HDA_AMP_VOL_DEFAULT) 2990 ctl->left = left; 2991 if (right != HDA_AMP_VOL_DEFAULT) 2992 ctl->right = right; 2993 /* Prepare effective values */ 2994 if (ctl->forcemute) { 2995 lmute = 1; 2996 rmute = 1; 2997 left = 0; 2998 right = 0; 2999 } else { 3000 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3001 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3002 left = ctl->left; 3003 right = ctl->right; 3004 } 3005 /* Apply effective values */ 3006 if (ctl->dir & HDA_CTL_OUT) 3007 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3008 lmute, rmute, left, right, 0); 3009 if (ctl->dir & HDA_CTL_IN) 3010 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3011 lmute, rmute, left, right, 1); 3012} 3013 3014static void 3015hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3016{ 3017 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3018 return; 3019 hdac_command(w->devinfo->codec->sc, 3020 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3021 w->nid, index), w->devinfo->codec->cad); 3022 w->selconn = index; 3023} 3024 3025 3026/**************************************************************************** 3027 * uint32_t hdac_command_sendone_internal 3028 * 3029 * Wrapper function that sends only one command to a given codec 3030 ****************************************************************************/ 3031static uint32_t 3032hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3033{ 3034 struct hdac_command_list cl; 3035 uint32_t response = HDAC_INVALID; 3036 3037 if (!hdac_lockowned(sc)) 3038 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3039 cl.num_commands = 1; 3040 cl.verbs = &verb; 3041 cl.responses = &response; 3042 3043 hdac_command_send_internal(sc, &cl, cad); 3044 3045 return (response); 3046} 3047 3048/**************************************************************************** 3049 * hdac_command_send_internal 3050 * 3051 * Send a command list to the codec via the corb. We queue as much verbs as 3052 * we can and msleep on the codec. When the interrupt get the responses 3053 * back from the rirb, it will wake us up so we can queue the remaining verbs 3054 * if any. 3055 ****************************************************************************/ 3056static void 3057hdac_command_send_internal(struct hdac_softc *sc, 3058 struct hdac_command_list *commands, nid_t cad) 3059{ 3060 struct hdac_codec *codec; 3061 int corbrp; 3062 uint32_t *corb; 3063 int timeout; 3064 int retry = 10; 3065 struct hdac_rirb *rirb_base; 3066 3067 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3068 commands->num_commands < 1) 3069 return; 3070 3071 codec = sc->codecs[cad]; 3072 codec->commands = commands; 3073 codec->responses_received = 0; 3074 codec->verbs_sent = 0; 3075 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3076 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3077 3078 do { 3079 if (codec->verbs_sent != commands->num_commands) { 3080 /* Queue as many verbs as possible */ 3081 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3082#if 0 3083 bus_dmamap_sync(sc->corb_dma.dma_tag, 3084 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3085#endif 3086 while (codec->verbs_sent != commands->num_commands && 3087 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3088 sc->corb_wp++; 3089 sc->corb_wp %= sc->corb_size; 3090 corb[sc->corb_wp] = 3091 commands->verbs[codec->verbs_sent++]; 3092 } 3093 3094 /* Send the verbs to the codecs */ 3095#if 0 3096 bus_dmamap_sync(sc->corb_dma.dma_tag, 3097 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3098#endif 3099 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3100 } 3101 3102 timeout = 1000; 3103 while (hdac_rirb_flush(sc) == 0 && --timeout) 3104 DELAY(10); 3105 } while ((codec->verbs_sent != commands->num_commands || 3106 codec->responses_received != commands->num_commands) && --retry); 3107 3108 if (retry == 0) 3109 device_printf(sc->dev, 3110 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3111 __func__, commands->num_commands, codec->verbs_sent, 3112 codec->responses_received); 3113 3114 codec->commands = NULL; 3115 codec->responses_received = 0; 3116 codec->verbs_sent = 0; 3117 3118 hdac_unsolq_flush(sc); 3119} 3120 3121 3122/**************************************************************************** 3123 * Device Methods 3124 ****************************************************************************/ 3125 3126/**************************************************************************** 3127 * int hdac_probe(device_t) 3128 * 3129 * Probe for the presence of an hdac. If none is found, check for a generic 3130 * match using the subclass of the device. 3131 ****************************************************************************/ 3132static int 3133hdac_probe(device_t dev) 3134{ 3135 int i, result; 3136 uint32_t model; 3137 uint16_t class, subclass; 3138 char desc[64]; 3139 3140 model = (uint32_t)pci_get_device(dev) << 16; 3141 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3142 class = pci_get_class(dev); 3143 subclass = pci_get_subclass(dev); 3144 3145 bzero(desc, sizeof(desc)); 3146 result = ENXIO; 3147 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3148 if (hdac_devices[i].model == model) { 3149 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3150 result = BUS_PROBE_DEFAULT; 3151 break; 3152 } 3153 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3154 class == PCIC_MULTIMEDIA && 3155 subclass == PCIS_MULTIMEDIA_HDA) { 3156 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3157 result = BUS_PROBE_GENERIC; 3158 break; 3159 } 3160 } 3161 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3162 subclass == PCIS_MULTIMEDIA_HDA) { 3163 strlcpy(desc, "Generic", sizeof(desc)); 3164 result = BUS_PROBE_GENERIC; 3165 } 3166 if (result != ENXIO) { 3167 strlcat(desc, " High Definition Audio Controller", 3168 sizeof(desc)); 3169 device_set_desc_copy(dev, desc); 3170 } 3171 3172 return (result); 3173} 3174 3175static void * 3176hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3177 struct pcm_channel *c, int dir) 3178{ 3179 struct hdac_pcm_devinfo *pdevinfo = data; 3180 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3181 struct hdac_softc *sc = devinfo->codec->sc; 3182 struct hdac_chan *ch; 3183 int i, ord = 0, chid; 3184 3185 hdac_lock(sc); 3186 3187 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3188 ch = &sc->chans[chid]; 3189 for (i = 0; i < sc->num_chans && i < chid; i++) { 3190 if (ch->dir == sc->chans[i].dir) 3191 ord++; 3192 } 3193 if (dir == PCMDIR_PLAY) { 3194 ch->off = (sc->num_iss + ord) << 5; 3195 } else { 3196 ch->off = ord << 5; 3197 } 3198 3199 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3200 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3201 ch->pcmrates[0] = 48000; 3202 ch->pcmrates[1] = 0; 3203 } 3204 if (sc->pos_dma.dma_vaddr != NULL) 3205 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3206 (sc->streamcnt * 8)); 3207 else 3208 ch->dmapos = NULL; 3209 ch->sid = ++sc->streamcnt; 3210 ch->dir = dir; 3211 ch->b = b; 3212 ch->c = c; 3213 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3214 ch->blkcnt = pdevinfo->chan_blkcnt; 3215 hdac_unlock(sc); 3216 3217 if (hdac_bdl_alloc(ch) != 0) { 3218 ch->blkcnt = 0; 3219 return (NULL); 3220 } 3221 3222 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3223 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3224 pdevinfo->chan_size) != 0) 3225 return (NULL); 3226 3227 return (ch); 3228} 3229 3230static int 3231hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3232{ 3233 struct hdac_chan *ch = data; 3234 int i; 3235 3236 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3237 if (format == ch->caps.fmtlist[i]) { 3238 ch->fmt = format; 3239 return (0); 3240 } 3241 } 3242 3243 return (EINVAL); 3244} 3245 3246static int 3247hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3248{ 3249 struct hdac_chan *ch = data; 3250 uint32_t spd = 0, threshold; 3251 int i; 3252 3253 for (i = 0; ch->pcmrates[i] != 0; i++) { 3254 spd = ch->pcmrates[i]; 3255 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3256 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3257 if (speed < threshold) 3258 break; 3259 } 3260 3261 if (spd == 0) /* impossible */ 3262 ch->spd = 48000; 3263 else 3264 ch->spd = spd; 3265 3266 return (ch->spd); 3267} 3268 3269static void 3270hdac_stream_setup(struct hdac_chan *ch) 3271{ 3272 struct hdac_softc *sc = ch->devinfo->codec->sc; 3273 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3274 struct hdac_widget *w; 3275 int i, chn, totalchn, c; 3276 nid_t cad = ch->devinfo->codec->cad; 3277 uint16_t fmt, dfmt; 3278 3279 HDA_BOOTHVERBOSE( 3280 device_printf(ch->pdevinfo->dev, 3281 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3282 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3283 ch->fmt, ch->spd); 3284 ); 3285 fmt = 0; 3286 if (ch->fmt & AFMT_S16_LE) 3287 fmt |= ch->bit16 << 4; 3288 else if (ch->fmt & AFMT_S32_LE) 3289 fmt |= ch->bit32 << 4; 3290 else 3291 fmt |= 1 << 4; 3292 3293 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3294 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3295 fmt |= hda_rate_tab[i].base; 3296 fmt |= hda_rate_tab[i].mul; 3297 fmt |= hda_rate_tab[i].div; 3298 break; 3299 } 3300 } 3301 3302 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3303 fmt |= 1; 3304 totalchn = 2; 3305 } else 3306 totalchn = 1; 3307 3308 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3309 3310 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3311 if (ch->fmt & AFMT_AC3) 3312 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3313 3314 chn = 0; 3315 for (i = 0; ch->io[i] != -1; i++) { 3316 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3317 if (w == NULL) 3318 continue; 3319 3320 if (as->hpredir >= 0 && i == as->pincnt) 3321 chn = 0; 3322 HDA_BOOTHVERBOSE( 3323 device_printf(ch->pdevinfo->dev, 3324 "PCMDIR_%s: Stream setup nid=%d: " 3325 "fmt=0x%04x, dfmt=0x%04x\n", 3326 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3327 ch->io[i], fmt, dfmt); 3328 ); 3329 hdac_command(sc, 3330 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3331 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3332 hdac_command(sc, 3333 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3334 cad); 3335 } 3336 /* If HP redirection is enabled, but failed to use same 3337 DAC make last DAC one to duplicate first one. */ 3338 if (as->hpredir >= 0 && i == as->pincnt) { 3339 c = (ch->sid << 4); 3340 } else if (chn >= totalchn) { 3341 /* This is until OSS will support multichannel. 3342 Should be: c = 0; to disable unused DAC */ 3343 c = (ch->sid << 4); 3344 }else { 3345 c = (ch->sid << 4) | chn; 3346 } 3347 hdac_command(sc, 3348 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3349 chn += 3350 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3351 2 : 1; 3352 } 3353} 3354 3355static int 3356hdac_channel_setfragments(kobj_t obj, void *data, 3357 uint32_t blksz, uint32_t blkcnt) 3358{ 3359 struct hdac_chan *ch = data; 3360 struct hdac_softc *sc = ch->devinfo->codec->sc; 3361 3362 blksz &= HDA_BLK_ALIGN; 3363 3364 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3365 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3366 if (blksz < HDA_BLK_MIN) 3367 blksz = HDA_BLK_MIN; 3368 if (blkcnt > HDA_BDL_MAX) 3369 blkcnt = HDA_BDL_MAX; 3370 if (blkcnt < HDA_BDL_MIN) 3371 blkcnt = HDA_BDL_MIN; 3372 3373 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3374 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3375 blkcnt >>= 1; 3376 else if ((blksz >> 1) >= HDA_BLK_MIN) 3377 blksz >>= 1; 3378 else 3379 break; 3380 } 3381 3382 if ((sndbuf_getblksz(ch->b) != blksz || 3383 sndbuf_getblkcnt(ch->b) != blkcnt) && 3384 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3385 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3386 __func__, blksz, blkcnt); 3387 3388 ch->blksz = sndbuf_getblksz(ch->b); 3389 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3390 3391 return (1); 3392} 3393 3394static int 3395hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3396{ 3397 struct hdac_chan *ch = data; 3398 3399 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3400 3401 return (ch->blksz); 3402} 3403 3404static void 3405hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3406{ 3407 struct hdac_devinfo *devinfo = ch->devinfo; 3408 struct hdac_widget *w; 3409 nid_t cad = devinfo->codec->cad; 3410 int i; 3411 3412 hdac_stream_stop(ch); 3413 3414 for (i = 0; ch->io[i] != -1; i++) { 3415 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3416 if (w == NULL) 3417 continue; 3418 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3419 hdac_command(sc, 3420 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3421 cad); 3422 } 3423 hdac_command(sc, 3424 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3425 0), cad); 3426 } 3427} 3428 3429static void 3430hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3431{ 3432 ch->ptr = 0; 3433 ch->prevptr = 0; 3434 hdac_stream_stop(ch); 3435 hdac_stream_reset(ch); 3436 hdac_bdl_setup(ch); 3437 hdac_stream_setid(ch); 3438 hdac_stream_setup(ch); 3439 hdac_stream_start(ch); 3440} 3441 3442static int 3443hdac_channel_trigger(kobj_t obj, void *data, int go) 3444{ 3445 struct hdac_chan *ch = data; 3446 struct hdac_softc *sc = ch->devinfo->codec->sc; 3447 3448 if (!PCMTRIG_COMMON(go)) 3449 return (0); 3450 3451 hdac_lock(sc); 3452 switch (go) { 3453 case PCMTRIG_START: 3454 hdac_channel_start(sc, ch); 3455 break; 3456 case PCMTRIG_STOP: 3457 case PCMTRIG_ABORT: 3458 hdac_channel_stop(sc, ch); 3459 break; 3460 default: 3461 break; 3462 } 3463 hdac_unlock(sc); 3464 3465 return (0); 3466} 3467 3468static int 3469hdac_channel_getptr(kobj_t obj, void *data) 3470{ 3471 struct hdac_chan *ch = data; 3472 struct hdac_softc *sc = ch->devinfo->codec->sc; 3473 uint32_t ptr; 3474 3475 hdac_lock(sc); 3476 if (sc->polling != 0) 3477 ptr = ch->ptr; 3478 else if (ch->dmapos != NULL) 3479 ptr = *(ch->dmapos); 3480 else 3481 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3482 hdac_unlock(sc); 3483 3484 /* 3485 * Round to available space and force 128 bytes aligment. 3486 */ 3487 ptr %= ch->blksz * ch->blkcnt; 3488 ptr &= HDA_BLK_ALIGN; 3489 3490 return (ptr); 3491} 3492 3493static struct pcmchan_caps * 3494hdac_channel_getcaps(kobj_t obj, void *data) 3495{ 3496 return (&((struct hdac_chan *)data)->caps); 3497} 3498 3499static kobj_method_t hdac_channel_methods[] = { 3500 KOBJMETHOD(channel_init, hdac_channel_init), 3501 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3502 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3503 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3504 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3505 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3506 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3507 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3508 { 0, 0 } 3509}; 3510CHANNEL_DECLARE(hdac_channel); 3511 3512static int 3513hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3514{ 3515 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3516 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3517 struct hdac_softc *sc = devinfo->codec->sc; 3518 struct hdac_widget *w, *cw; 3519 struct hdac_audio_ctl *ctl; 3520 uint32_t mask, recmask, id; 3521 int i, j, softpcmvol; 3522 3523 hdac_lock(sc); 3524 3525 /* Make sure that in case of soft volume it won't stay muted. */ 3526 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3527 pdevinfo->left[i] = 100; 3528 pdevinfo->right[i] = 100; 3529 } 3530 3531 mask = 0; 3532 recmask = 0; 3533 id = hdac_codec_id(devinfo->codec); 3534 3535 /* Declate EAPD as ogain control. */ 3536 if (pdevinfo->play >= 0) { 3537 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3538 w = hdac_widget_get(devinfo, i); 3539 if (w == NULL || w->enable == 0) 3540 continue; 3541 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3542 w->param.eapdbtl == HDAC_INVALID || 3543 w->bindas != sc->chans[pdevinfo->play].as) 3544 continue; 3545 mask |= SOUND_MASK_OGAIN; 3546 break; 3547 } 3548 } 3549 3550 /* Declare volume controls assigned to this association. */ 3551 i = 0; 3552 ctl = NULL; 3553 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3554 if (ctl->enable == 0) 3555 continue; 3556 if ((pdevinfo->play >= 0 && 3557 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3558 (pdevinfo->rec >= 0 && 3559 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3560 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3561 mask |= ctl->ossmask; 3562 } 3563 3564 /* Declare record sources available to this association. */ 3565 if (pdevinfo->rec >= 0) { 3566 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3567 for (i = 0; ch->io[i] != -1; i++) { 3568 w = hdac_widget_get(devinfo, ch->io[i]); 3569 if (w == NULL || w->enable == 0) 3570 continue; 3571 for (j = 0; j < w->nconns; j++) { 3572 if (w->connsenable[j] == 0) 3573 continue; 3574 cw = hdac_widget_get(devinfo, w->conns[j]); 3575 if (cw == NULL || cw->enable == 0) 3576 continue; 3577 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3578 cw->bindas != -2) 3579 continue; 3580 recmask |= cw->ossmask; 3581 } 3582 } 3583 } 3584 3585 /* Declare soft PCM volume if needed. */ 3586 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3587 ctl = NULL; 3588 if ((mask & SOUND_MASK_PCM) == 0 || 3589 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3590 softpcmvol = 1; 3591 mask |= SOUND_MASK_PCM; 3592 } else { 3593 softpcmvol = 0; 3594 i = 0; 3595 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3596 if (ctl->enable == 0) 3597 continue; 3598 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3599 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3600 continue; 3601 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3602 continue; 3603 if (ctl->step > 0) 3604 break; 3605 } 3606 } 3607 3608 if (softpcmvol == 1 || ctl == NULL) { 3609 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3610 HDA_BOOTVERBOSE( 3611 device_printf(pdevinfo->dev, 3612 "%s Soft PCM volume\n", 3613 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3614 ); 3615 } 3616 } 3617 3618 /* Declare master volume if needed. */ 3619 if (pdevinfo->play >= 0) { 3620 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3621 SOUND_MASK_PCM) { 3622 mask |= SOUND_MASK_VOLUME; 3623 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3624 SOUND_MASK_PCM); 3625 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3626 SOUND_MIXER_NONE); 3627 HDA_BOOTVERBOSE( 3628 device_printf(pdevinfo->dev, 3629 "Forcing master volume with PCM\n"); 3630 ); 3631 } 3632 } 3633 3634 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3635 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3636 3637 mix_setrecdevs(m, recmask); 3638 mix_setdevs(m, mask); 3639 3640 hdac_unlock(sc); 3641 3642 return (0); 3643} 3644 3645static int 3646hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3647 unsigned left, unsigned right) 3648{ 3649 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3650 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3651 struct hdac_softc *sc = devinfo->codec->sc; 3652 struct hdac_widget *w; 3653 struct hdac_audio_ctl *ctl; 3654 uint32_t mute; 3655 int lvol, rvol; 3656 int i, j; 3657 3658 hdac_lock(sc); 3659 /* Save new values. */ 3660 pdevinfo->left[dev] = left; 3661 pdevinfo->right[dev] = right; 3662 3663 /* 'ogain' is the special case implemented with EAPD. */ 3664 if (dev == SOUND_MIXER_OGAIN) { 3665 uint32_t orig; 3666 w = NULL; 3667 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3668 w = hdac_widget_get(devinfo, i); 3669 if (w == NULL || w->enable == 0) 3670 continue; 3671 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3672 w->param.eapdbtl == HDAC_INVALID) 3673 continue; 3674 break; 3675 } 3676 if (i >= devinfo->endnode) { 3677 hdac_unlock(sc); 3678 return (-1); 3679 } 3680 orig = w->param.eapdbtl; 3681 if (left == 0) 3682 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3683 else 3684 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3685 if (orig != w->param.eapdbtl) { 3686 uint32_t val; 3687 3688 val = w->param.eapdbtl; 3689 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3690 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3691 hdac_command(sc, 3692 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3693 w->nid, val), devinfo->codec->cad); 3694 } 3695 hdac_unlock(sc); 3696 return (left | (left << 8)); 3697 } 3698 3699 /* Recalculate all controls related to this OSS device. */ 3700 i = 0; 3701 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3702 if (ctl->enable == 0 || 3703 !(ctl->ossmask & (1 << dev))) 3704 continue; 3705 if (!((pdevinfo->play >= 0 && 3706 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3707 (pdevinfo->rec >= 0 && 3708 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3709 ctl->widget->bindas == -2)) 3710 continue; 3711 3712 lvol = 100; 3713 rvol = 100; 3714 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3715 if (ctl->ossmask & (1 << j)) { 3716 lvol = lvol * pdevinfo->left[j] / 100; 3717 rvol = rvol * pdevinfo->right[j] / 100; 3718 } 3719 } 3720 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3721 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3722 lvol = (lvol * ctl->step + 50) / 100; 3723 rvol = (rvol * ctl->step + 50) / 100; 3724 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3725 } 3726 hdac_unlock(sc); 3727 3728 return (left | (right << 8)); 3729} 3730 3731/* 3732 * Commutate specified record source. 3733 */ 3734static uint32_t 3735hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3736{ 3737 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3738 struct hdac_widget *w, *cw; 3739 struct hdac_audio_ctl *ctl; 3740 char buf[64]; 3741 int i, muted; 3742 uint32_t res = 0; 3743 3744 if (depth > HDA_PARSE_MAXDEPTH) 3745 return (0); 3746 3747 w = hdac_widget_get(devinfo, nid); 3748 if (w == NULL || w->enable == 0) 3749 return (0); 3750 3751 for (i = 0; i < w->nconns; i++) { 3752 if (w->connsenable[i] == 0) 3753 continue; 3754 cw = hdac_widget_get(devinfo, w->conns[i]); 3755 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3756 continue; 3757 /* Call recursively to trace signal to it's source if needed. */ 3758 if ((src & cw->ossmask) != 0) { 3759 if (cw->ossdev < 0) { 3760 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3761 w->conns[i], depth + 1); 3762 } else { 3763 res |= cw->ossmask; 3764 } 3765 } 3766 /* We have two special cases: mixers and others (selectors). */ 3767 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3768 ctl = hdac_audio_ctl_amp_get(devinfo, 3769 w->nid, HDA_CTL_IN, i, 1); 3770 if (ctl == NULL) 3771 continue; 3772 /* If we have input control on this node mute them 3773 * according to requested sources. */ 3774 muted = (src & cw->ossmask) ? 0 : 1; 3775 if (muted != ctl->forcemute) { 3776 ctl->forcemute = muted; 3777 hdac_audio_ctl_amp_set(ctl, 3778 HDA_AMP_MUTE_DEFAULT, 3779 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3780 } 3781 HDA_BOOTHVERBOSE( 3782 device_printf(pdevinfo->dev, 3783 "Recsel (%s): nid %d source %d %s\n", 3784 hdac_audio_ctl_ossmixer_mask2allname( 3785 src, buf, sizeof(buf)), 3786 nid, i, muted?"mute":"unmute"); 3787 ); 3788 } else { 3789 if (w->nconns == 1) 3790 break; 3791 if ((src & cw->ossmask) == 0) 3792 continue; 3793 /* If we found requested source - select it and exit. */ 3794 hdac_widget_connection_select(w, i); 3795 HDA_BOOTHVERBOSE( 3796 device_printf(pdevinfo->dev, 3797 "Recsel (%s): nid %d source %d select\n", 3798 hdac_audio_ctl_ossmixer_mask2allname( 3799 src, buf, sizeof(buf)), 3800 nid, i); 3801 ); 3802 break; 3803 } 3804 } 3805 return (res); 3806} 3807 3808static uint32_t 3809hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3810{ 3811 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3812 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3813 struct hdac_widget *w; 3814 struct hdac_softc *sc = devinfo->codec->sc; 3815 struct hdac_chan *ch; 3816 int i; 3817 uint32_t ret = 0xffffffff; 3818 3819 hdac_lock(sc); 3820 3821 /* Commutate requested recsrc for each ADC. */ 3822 ch = &sc->chans[pdevinfo->rec]; 3823 for (i = 0; ch->io[i] != -1; i++) { 3824 w = hdac_widget_get(devinfo, ch->io[i]); 3825 if (w == NULL || w->enable == 0) 3826 continue; 3827 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3828 } 3829 3830 hdac_unlock(sc); 3831 3832 return ((ret == 0xffffffff)? 0 : ret); 3833} 3834 3835static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3836 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3837 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3838 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3839 { 0, 0 } 3840}; 3841MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3842 3843static void 3844hdac_unsolq_task(void *context, int pending) 3845{ 3846 struct hdac_softc *sc; 3847 3848 sc = (struct hdac_softc *)context; 3849 3850 hdac_lock(sc); 3851 hdac_unsolq_flush(sc); 3852 hdac_unlock(sc); 3853} 3854 3855/**************************************************************************** 3856 * int hdac_attach(device_t) 3857 * 3858 * Attach the device into the kernel. Interrupts usually won't be enabled 3859 * when this function is called. Setup everything that doesn't require 3860 * interrupts and defer probing of codecs until interrupts are enabled. 3861 ****************************************************************************/ 3862static int 3863hdac_attach(device_t dev) 3864{ 3865 struct hdac_softc *sc; 3866 int result; 3867 int i; 3868 uint16_t vendor; 3869 uint8_t v; 3870 3871 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3872 3873 sc = device_get_softc(dev); 3874 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3875 sc->dev = dev; 3876 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3877 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3878 vendor = pci_get_vendor(dev); 3879 3880 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3881 /* Screw nx6325 - subdevice/subvendor swapped */ 3882 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3883 } 3884 3885 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3886 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3887 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3888 3889 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3890 3891 sc->poll_ticks = 1000000; 3892 sc->poll_ival = HDAC_POLL_INTERVAL; 3893 if (resource_int_value(device_get_name(dev), 3894 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3895 sc->polling = 1; 3896 else 3897 sc->polling = 0; 3898 3899 result = bus_dma_tag_create(NULL, /* parent */ 3900 HDAC_DMA_ALIGNMENT, /* alignment */ 3901 0, /* boundary */ 3902 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3903 BUS_SPACE_MAXADDR, /* highaddr */ 3904 NULL, /* filtfunc */ 3905 NULL, /* fistfuncarg */ 3906 HDA_BUFSZ_MAX, /* maxsize */ 3907 1, /* nsegments */ 3908 HDA_BUFSZ_MAX, /* maxsegsz */ 3909 0, /* flags */ 3910 NULL, /* lockfunc */ 3911 NULL, /* lockfuncarg */ 3912 &sc->chan_dmat); /* dmat */ 3913 if (result != 0) { 3914 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3915 __func__, result); 3916 snd_mtxfree(sc->lock); 3917 free(sc, M_DEVBUF); 3918 return (ENXIO); 3919 } 3920 3921 3922 sc->hdabus = NULL; 3923 for (i = 0; i < HDAC_CODEC_MAX; i++) 3924 sc->codecs[i] = NULL; 3925 3926 pci_enable_busmaster(dev); 3927 3928 if (vendor == INTEL_VENDORID) { 3929 /* TCSEL -> TC0 */ 3930 v = pci_read_config(dev, 0x44, 1); 3931 pci_write_config(dev, 0x44, v & 0xf8, 1); 3932 HDA_BOOTHVERBOSE( 3933 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3934 pci_read_config(dev, 0x44, 1)); 3935 ); 3936 } 3937 3938#ifdef HDAC_MSI_ENABLED 3939 if (resource_int_value(device_get_name(dev), 3940 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3941 pci_msi_count(dev) == 1) 3942 sc->flags |= HDAC_F_MSI; 3943 else 3944#endif 3945 sc->flags &= ~HDAC_F_MSI; 3946 3947#if defined(__i386__) || defined(__amd64__) 3948 sc->flags |= HDAC_F_DMA_NOCACHE; 3949 3950 if (resource_int_value(device_get_name(dev), 3951 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3952#else 3953 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3954#endif 3955 /* 3956 * Try to enable PCIe snoop to avoid messing around with 3957 * uncacheable DMA attribute. Since PCIe snoop register 3958 * config is pretty much vendor specific, there are no 3959 * general solutions on how to enable it, forcing us (even 3960 * Microsoft) to enable uncacheable or write combined DMA 3961 * by default. 3962 * 3963 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3964 */ 3965 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3966 if (hdac_pcie_snoop[i].vendor != vendor) 3967 continue; 3968 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3969 if (hdac_pcie_snoop[i].reg == 0x00) 3970 break; 3971 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3972 if ((v & hdac_pcie_snoop[i].enable) == 3973 hdac_pcie_snoop[i].enable) 3974 break; 3975 v &= hdac_pcie_snoop[i].mask; 3976 v |= hdac_pcie_snoop[i].enable; 3977 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3978 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3979 if ((v & hdac_pcie_snoop[i].enable) != 3980 hdac_pcie_snoop[i].enable) { 3981 HDA_BOOTVERBOSE( 3982 device_printf(dev, 3983 "WARNING: Failed to enable PCIe " 3984 "snoop!\n"); 3985 ); 3986#if defined(__i386__) || defined(__amd64__) 3987 sc->flags |= HDAC_F_DMA_NOCACHE; 3988#endif 3989 } 3990 break; 3991 } 3992#if defined(__i386__) || defined(__amd64__) 3993 } 3994#endif 3995 3996 HDA_BOOTHVERBOSE( 3997 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3998 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3999 "Uncacheable" : "PCIe snoop", vendor); 4000 ); 4001 4002 /* Allocate resources */ 4003 result = hdac_mem_alloc(sc); 4004 if (result != 0) 4005 goto hdac_attach_fail; 4006 result = hdac_irq_alloc(sc); 4007 if (result != 0) 4008 goto hdac_attach_fail; 4009 4010 /* Get Capabilities */ 4011 result = hdac_get_capabilities(sc); 4012 if (result != 0) 4013 goto hdac_attach_fail; 4014 4015 /* Allocate CORB and RIRB dma memory */ 4016 result = hdac_dma_alloc(sc, &sc->corb_dma, 4017 sc->corb_size * sizeof(uint32_t)); 4018 if (result != 0) 4019 goto hdac_attach_fail; 4020 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4021 sc->rirb_size * sizeof(struct hdac_rirb)); 4022 if (result != 0) 4023 goto hdac_attach_fail; 4024 4025 /* Quiesce everything */ 4026 HDA_BOOTHVERBOSE( 4027 device_printf(dev, "Reset controller...\n"); 4028 ); 4029 hdac_reset(sc, 1); 4030 4031 /* Initialize the CORB and RIRB */ 4032 hdac_corb_init(sc); 4033 hdac_rirb_init(sc); 4034 4035 /* Defer remaining of initialization until interrupts are enabled */ 4036 sc->intrhook.ich_func = hdac_attach2; 4037 sc->intrhook.ich_arg = (void *)sc; 4038 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4039 sc->intrhook.ich_func = NULL; 4040 hdac_attach2((void *)sc); 4041 } 4042 4043 return (0); 4044 4045hdac_attach_fail: 4046 hdac_irq_free(sc); 4047 hdac_dma_free(sc, &sc->rirb_dma); 4048 hdac_dma_free(sc, &sc->corb_dma); 4049 hdac_mem_free(sc); 4050 snd_mtxfree(sc->lock); 4051 free(sc, M_DEVBUF); 4052 4053 return (ENXIO); 4054} 4055 4056static void 4057hdac_audio_parse(struct hdac_devinfo *devinfo) 4058{ 4059 struct hdac_codec *codec = devinfo->codec; 4060 struct hdac_softc *sc = codec->sc; 4061 struct hdac_widget *w; 4062 uint32_t res; 4063 int i; 4064 nid_t cad, nid; 4065 4066 cad = devinfo->codec->cad; 4067 nid = devinfo->nid; 4068 4069 res = hdac_command(sc, 4070 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4071 devinfo->function.audio.gpio = res; 4072 4073 HDA_BOOTVERBOSE( 4074 device_printf(sc->dev, "GPIO: 0x%08x " 4075 "NumGPIO=%d NumGPO=%d " 4076 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4077 devinfo->function.audio.gpio, 4078 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4079 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4080 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4081 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4082 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4083 ); 4084 4085 res = hdac_command(sc, 4086 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4087 cad); 4088 devinfo->function.audio.supp_stream_formats = res; 4089 4090 res = hdac_command(sc, 4091 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4092 cad); 4093 devinfo->function.audio.supp_pcm_size_rate = res; 4094 4095 res = hdac_command(sc, 4096 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4097 cad); 4098 devinfo->function.audio.outamp_cap = res; 4099 4100 res = hdac_command(sc, 4101 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4102 cad); 4103 devinfo->function.audio.inamp_cap = res; 4104 4105 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4106 w = hdac_widget_get(devinfo, i); 4107 if (w == NULL) 4108 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4109 else { 4110 w->devinfo = devinfo; 4111 w->nid = i; 4112 w->enable = 1; 4113 w->selconn = -1; 4114 w->pflags = 0; 4115 w->ossdev = -1; 4116 w->bindas = -1; 4117 w->param.eapdbtl = HDAC_INVALID; 4118 hdac_widget_parse(w); 4119 } 4120 } 4121} 4122 4123static void 4124hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4125{ 4126 struct hdac_softc *sc = devinfo->codec->sc; 4127 struct hdac_audio_ctl *ctls; 4128 struct hdac_widget *w, *cw; 4129 int i, j, cnt, max, ocap, icap; 4130 int mute, offset, step, size; 4131 4132 /* XXX This is redundant */ 4133 max = 0; 4134 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4135 w = hdac_widget_get(devinfo, i); 4136 if (w == NULL || w->enable == 0) 4137 continue; 4138 if (w->param.outamp_cap != 0) 4139 max++; 4140 if (w->param.inamp_cap != 0) { 4141 switch (w->type) { 4142 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4143 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4144 for (j = 0; j < w->nconns; j++) { 4145 cw = hdac_widget_get(devinfo, 4146 w->conns[j]); 4147 if (cw == NULL || cw->enable == 0) 4148 continue; 4149 max++; 4150 } 4151 break; 4152 default: 4153 max++; 4154 break; 4155 } 4156 } 4157 } 4158 4159 devinfo->function.audio.ctlcnt = max; 4160 4161 if (max < 1) 4162 return; 4163 4164 ctls = (struct hdac_audio_ctl *)malloc( 4165 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4166 4167 if (ctls == NULL) { 4168 /* Blekh! */ 4169 device_printf(sc->dev, "unable to allocate ctls!\n"); 4170 devinfo->function.audio.ctlcnt = 0; 4171 return; 4172 } 4173 4174 cnt = 0; 4175 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4176 if (cnt >= max) { 4177 device_printf(sc->dev, "%s: Ctl overflow!\n", 4178 __func__); 4179 break; 4180 } 4181 w = hdac_widget_get(devinfo, i); 4182 if (w == NULL || w->enable == 0) 4183 continue; 4184 ocap = w->param.outamp_cap; 4185 icap = w->param.inamp_cap; 4186 if (ocap != 0) { 4187 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4188 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4189 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4190 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4191 /*if (offset > step) { 4192 HDA_BOOTVERBOSE( 4193 device_printf(sc->dev, 4194 "BUGGY outamp: nid=%d " 4195 "[offset=%d > step=%d]\n", 4196 w->nid, offset, step); 4197 ); 4198 offset = step; 4199 }*/ 4200 ctls[cnt].enable = 1; 4201 ctls[cnt].widget = w; 4202 ctls[cnt].mute = mute; 4203 ctls[cnt].step = step; 4204 ctls[cnt].size = size; 4205 ctls[cnt].offset = offset; 4206 ctls[cnt].left = offset; 4207 ctls[cnt].right = offset; 4208 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4209 w->waspin) 4210 ctls[cnt].ndir = HDA_CTL_IN; 4211 else 4212 ctls[cnt].ndir = HDA_CTL_OUT; 4213 ctls[cnt++].dir = HDA_CTL_OUT; 4214 } 4215 4216 if (icap != 0) { 4217 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4218 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4219 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4220 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4221 /*if (offset > step) { 4222 HDA_BOOTVERBOSE( 4223 device_printf(sc->dev, 4224 "BUGGY inamp: nid=%d " 4225 "[offset=%d > step=%d]\n", 4226 w->nid, offset, step); 4227 ); 4228 offset = step; 4229 }*/ 4230 switch (w->type) { 4231 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4232 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4233 for (j = 0; j < w->nconns; j++) { 4234 if (cnt >= max) { 4235 device_printf(sc->dev, 4236 "%s: Ctl overflow!\n", 4237 __func__); 4238 break; 4239 } 4240 cw = hdac_widget_get(devinfo, 4241 w->conns[j]); 4242 if (cw == NULL || cw->enable == 0) 4243 continue; 4244 ctls[cnt].enable = 1; 4245 ctls[cnt].widget = w; 4246 ctls[cnt].childwidget = cw; 4247 ctls[cnt].index = j; 4248 ctls[cnt].mute = mute; 4249 ctls[cnt].step = step; 4250 ctls[cnt].size = size; 4251 ctls[cnt].offset = offset; 4252 ctls[cnt].left = offset; 4253 ctls[cnt].right = offset; 4254 ctls[cnt].ndir = HDA_CTL_IN; 4255 ctls[cnt++].dir = HDA_CTL_IN; 4256 } 4257 break; 4258 default: 4259 if (cnt >= max) { 4260 device_printf(sc->dev, 4261 "%s: Ctl overflow!\n", 4262 __func__); 4263 break; 4264 } 4265 ctls[cnt].enable = 1; 4266 ctls[cnt].widget = w; 4267 ctls[cnt].mute = mute; 4268 ctls[cnt].step = step; 4269 ctls[cnt].size = size; 4270 ctls[cnt].offset = offset; 4271 ctls[cnt].left = offset; 4272 ctls[cnt].right = offset; 4273 if (w->type == 4274 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4275 ctls[cnt].ndir = HDA_CTL_OUT; 4276 else 4277 ctls[cnt].ndir = HDA_CTL_IN; 4278 ctls[cnt++].dir = HDA_CTL_IN; 4279 break; 4280 } 4281 } 4282 } 4283 4284 devinfo->function.audio.ctl = ctls; 4285} 4286 4287static void 4288hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4289{ 4290 struct hdac_softc *sc = devinfo->codec->sc; 4291 struct hdac_audio_as *as; 4292 struct hdac_widget *w; 4293 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4294 4295 /* Count present associations */ 4296 max = 0; 4297 for (j = 1; j < 16; j++) { 4298 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4299 w = hdac_widget_get(devinfo, i); 4300 if (w == NULL || w->enable == 0) 4301 continue; 4302 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4303 continue; 4304 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4305 != j) 4306 continue; 4307 max++; 4308 if (j != 15) /* There could be many 1-pin assocs #15 */ 4309 break; 4310 } 4311 } 4312 4313 devinfo->function.audio.ascnt = max; 4314 4315 if (max < 1) 4316 return; 4317 4318 as = (struct hdac_audio_as *)malloc( 4319 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4320 4321 if (as == NULL) { 4322 /* Blekh! */ 4323 device_printf(sc->dev, "unable to allocate assocs!\n"); 4324 devinfo->function.audio.ascnt = 0; 4325 return; 4326 } 4327 4328 for (i = 0; i < max; i++) { 4329 as[i].hpredir = -1; 4330 as[i].chan = -1; 4331 as[i].digital = 1; 4332 } 4333 4334 /* Scan associations skipping as=0. */ 4335 cnt = 0; 4336 for (j = 1; j < 16; j++) { 4337 first = 16; 4338 hpredir = 0; 4339 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4340 w = hdac_widget_get(devinfo, i); 4341 if (w == NULL || w->enable == 0) 4342 continue; 4343 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4344 continue; 4345 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4346 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4347 if (assoc != j) { 4348 continue; 4349 } 4350 KASSERT(cnt < max, 4351 ("%s: Associations owerflow (%d of %d)", 4352 __func__, cnt, max)); 4353 type = w->wclass.pin.config & 4354 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4355 /* Get pin direction. */ 4356 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4357 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4358 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4359 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4360 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4361 dir = HDA_CTL_OUT; 4362 else 4363 dir = HDA_CTL_IN; 4364 /* If this is a first pin - create new association. */ 4365 if (as[cnt].pincnt == 0) { 4366 as[cnt].enable = 1; 4367 as[cnt].index = j; 4368 as[cnt].dir = dir; 4369 } 4370 if (seq < first) 4371 first = seq; 4372 /* Check association correctness. */ 4373 if (as[cnt].pins[seq] != 0) { 4374 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4375 "in association %d! Disabling association.\n", 4376 __func__, seq, w->nid, j); 4377 as[cnt].enable = 0; 4378 } 4379 if (dir != as[cnt].dir) { 4380 device_printf(sc->dev, "%s: Pin %d has wrong " 4381 "direction for association %d! Disabling " 4382 "association.\n", 4383 __func__, w->nid, j); 4384 as[cnt].enable = 0; 4385 } 4386 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4387 as[cnt].digital = 0; 4388 /* Headphones with seq=15 may mean redirection. */ 4389 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4390 seq == 15) 4391 hpredir = 1; 4392 as[cnt].pins[seq] = w->nid; 4393 as[cnt].pincnt++; 4394 /* Association 15 is a multiple unassociated pins. */ 4395 if (j == 15) 4396 cnt++; 4397 } 4398 if (j != 15 && as[cnt].pincnt > 0) { 4399 if (hpredir && as[cnt].pincnt > 1) 4400 as[cnt].hpredir = first; 4401 cnt++; 4402 } 4403 } 4404 HDA_BOOTVERBOSE( 4405 device_printf(sc->dev, 4406 "%d associations found:\n", max); 4407 for (i = 0; i < max; i++) { 4408 device_printf(sc->dev, 4409 "Association %d (%d) %s%s:\n", 4410 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4411 as[i].enable?"":" (disabled)"); 4412 for (j = 0; j < 16; j++) { 4413 if (as[i].pins[j] == 0) 4414 continue; 4415 device_printf(sc->dev, 4416 " Pin nid=%d seq=%d\n", 4417 as[i].pins[j], j); 4418 } 4419 } 4420 ); 4421 4422 devinfo->function.audio.as = as; 4423} 4424 4425static const struct { 4426 uint32_t model; 4427 uint32_t id; 4428 uint32_t set, unset; 4429} hdac_quirks[] = { 4430 /* 4431 * XXX Force stereo quirk. Monoural recording / playback 4432 * on few codecs (especially ALC880) seems broken or 4433 * perhaps unsupported. 4434 */ 4435 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4436 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4437 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4438 HDA_QUIRK_GPIO0, 0 }, 4439 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4440 HDA_QUIRK_GPIO0, 0 }, 4441 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4442 HDA_QUIRK_GPIO0, 0 }, 4443 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4444 HDA_QUIRK_GPIO0, 0 }, 4445 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4446 HDA_QUIRK_GPIO0, 0 }, 4447 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4448 HDA_QUIRK_GPIO0, 0 }, 4449 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4450 HDA_QUIRK_EAPDINV, 0 }, 4451 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4452 HDA_QUIRK_EAPDINV, 0 }, 4453 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4454 HDA_QUIRK_OVREF, 0 }, 4455 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4456 HDA_QUIRK_OVREF, 0 }, 4457 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4458 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4459 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4460 HDA_QUIRK_GPIO1, 0 }, 4461 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4462 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4463 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4464 HDA_QUIRK_EAPDINV, 0 }, 4465 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4466 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4467 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4468 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4469 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4470 HDA_QUIRK_GPIO0, 0 }, 4471 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4472 HDA_QUIRK_GPIO2, 0 }, 4473 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4474 HDA_QUIRK_GPIO0, 0 }, 4475 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4476 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4477 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4478 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4479 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4480 0, HDA_QUIRK_FORCESTEREO } 4481}; 4482#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4483 4484static void 4485hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4486{ 4487 struct hdac_widget *w; 4488 uint32_t id, subvendor; 4489 int i; 4490 4491 id = hdac_codec_id(devinfo->codec); 4492 subvendor = devinfo->codec->sc->pci_subvendor; 4493 4494 /* 4495 * Quirks 4496 */ 4497 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4498 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4499 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4500 continue; 4501 if (hdac_quirks[i].set != 0) 4502 devinfo->function.audio.quirks |= 4503 hdac_quirks[i].set; 4504 if (hdac_quirks[i].unset != 0) 4505 devinfo->function.audio.quirks &= 4506 ~(hdac_quirks[i].unset); 4507 } 4508 4509 switch (id) { 4510 case HDA_CODEC_ALC883: 4511 /* 4512 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4513 * Clear vref cap for jack connectivity. 4514 */ 4515 w = hdac_widget_get(devinfo, 24); 4516 if (w != NULL && w->enable != 0 && w->type == 4517 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4518 (w->wclass.pin.config & 4519 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4520 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4521 w->wclass.pin.cap &= ~( 4522 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4523 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4524 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4525 w = hdac_widget_get(devinfo, 25); 4526 if (w != NULL && w->enable != 0 && w->type == 4527 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4528 (w->wclass.pin.config & 4529 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4530 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4531 w->wclass.pin.cap &= ~( 4532 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4533 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4534 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4535 /* 4536 * nid: 26 = Line-in, leave it alone. 4537 */ 4538 break; 4539 case HDA_CODEC_AD1986A: 4540 if (subvendor == ASUS_A8X_SUBVENDOR) { 4541 /* 4542 * This is just plain ridiculous.. There 4543 * are several A8 series that share the same 4544 * pci id but works differently (EAPD). 4545 */ 4546 w = hdac_widget_get(devinfo, 26); 4547 if (w != NULL && w->type == 4548 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4549 (w->wclass.pin.config & 4550 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4551 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4552 devinfo->function.audio.quirks &= 4553 ~HDA_QUIRK_EAPDINV; 4554 } 4555 break; 4556 case HDA_CODEC_AD1981HD: 4557 /* 4558 * This codec has very unusual design with several 4559 * points inappropriate for the present parser. 4560 */ 4561 /* Disable recording from mono playback mix. */ 4562 w = hdac_widget_get(devinfo, 21); 4563 if (w != NULL) 4564 w->connsenable[3] = 0; 4565 /* Disable rear to front mic mixer, use separately. */ 4566 w = hdac_widget_get(devinfo, 31); 4567 if (w != NULL) 4568 w->enable = 0; 4569 /* Disable playback mixer, use direct bypass. */ 4570 w = hdac_widget_get(devinfo, 14); 4571 if (w != NULL) 4572 w->enable = 0; 4573 break; 4574 } 4575} 4576 4577/* 4578 * Trace path from DAC to pin. 4579 */ 4580static nid_t 4581hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4582 int dupseq, int min, int only, int depth) 4583{ 4584 struct hdac_widget *w; 4585 int i, im = -1; 4586 nid_t m = 0, ret; 4587 4588 if (depth > HDA_PARSE_MAXDEPTH) 4589 return (0); 4590 w = hdac_widget_get(devinfo, nid); 4591 if (w == NULL || w->enable == 0) 4592 return (0); 4593 HDA_BOOTHVERBOSE( 4594 if (!only) { 4595 device_printf(devinfo->codec->sc->dev, 4596 " %*stracing via nid %d\n", 4597 depth + 1, "", w->nid); 4598 } 4599 ); 4600 /* Use only unused widgets */ 4601 if (w->bindas >= 0 && w->bindas != as) { 4602 HDA_BOOTHVERBOSE( 4603 if (!only) { 4604 device_printf(devinfo->codec->sc->dev, 4605 " %*snid %d busy by association %d\n", 4606 depth + 1, "", w->nid, w->bindas); 4607 } 4608 ); 4609 return (0); 4610 } 4611 if (dupseq < 0) { 4612 if (w->bindseqmask != 0) { 4613 HDA_BOOTHVERBOSE( 4614 if (!only) { 4615 device_printf(devinfo->codec->sc->dev, 4616 " %*snid %d busy by seqmask %x\n", 4617 depth + 1, "", w->nid, w->bindseqmask); 4618 } 4619 ); 4620 return (0); 4621 } 4622 } else { 4623 /* If this is headphones - allow duplicate first pin. */ 4624 if (w->bindseqmask != 0 && 4625 (w->bindseqmask & (1 << dupseq)) == 0) { 4626 HDA_BOOTHVERBOSE( 4627 device_printf(devinfo->codec->sc->dev, 4628 " %*snid %d busy by seqmask %x\n", 4629 depth + 1, "", w->nid, w->bindseqmask); 4630 ); 4631 return (0); 4632 } 4633 } 4634 4635 switch (w->type) { 4636 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4637 /* Do not traverse input. AD1988 has digital monitor 4638 for which we are not ready. */ 4639 break; 4640 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4641 /* If we are tracing HP take only dac of first pin. */ 4642 if ((only == 0 || only == w->nid) && 4643 (w->nid >= min) && (dupseq < 0 || w->nid == 4644 devinfo->function.audio.as[as].dacs[dupseq])) 4645 m = w->nid; 4646 break; 4647 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4648 if (depth > 0) 4649 break; 4650 /* Fall */ 4651 default: 4652 /* Find reachable DACs with smallest nid respecting constraints. */ 4653 for (i = 0; i < w->nconns; i++) { 4654 if (w->connsenable[i] == 0) 4655 continue; 4656 if (w->selconn != -1 && w->selconn != i) 4657 continue; 4658 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4659 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4660 if (m == 0 || ret < m) { 4661 m = ret; 4662 im = i; 4663 } 4664 if (only || dupseq >= 0) 4665 break; 4666 } 4667 } 4668 if (m && only && ((w->nconns > 1 && 4669 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4670 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4671 w->selconn = im; 4672 break; 4673 } 4674 if (m && only) { 4675 w->bindas = as; 4676 w->bindseqmask |= (1 << seq); 4677 } 4678 HDA_BOOTHVERBOSE( 4679 if (!only) { 4680 device_printf(devinfo->codec->sc->dev, 4681 " %*snid %d returned %d\n", 4682 depth + 1, "", w->nid, m); 4683 } 4684 ); 4685 return (m); 4686} 4687 4688/* 4689 * Trace path from widget to ADC. 4690 */ 4691static nid_t 4692hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4693 int only, int depth) 4694{ 4695 struct hdac_widget *w, *wc; 4696 int i, j; 4697 nid_t res = 0; 4698 4699 if (depth > HDA_PARSE_MAXDEPTH) 4700 return (0); 4701 w = hdac_widget_get(devinfo, nid); 4702 if (w == NULL || w->enable == 0) 4703 return (0); 4704 HDA_BOOTHVERBOSE( 4705 device_printf(devinfo->codec->sc->dev, 4706 " %*stracing via nid %d\n", 4707 depth + 1, "", w->nid); 4708 ); 4709 /* Use only unused widgets */ 4710 if (w->bindas >= 0 && w->bindas != as) { 4711 HDA_BOOTHVERBOSE( 4712 device_printf(devinfo->codec->sc->dev, 4713 " %*snid %d busy by association %d\n", 4714 depth + 1, "", w->nid, w->bindas); 4715 ); 4716 return (0); 4717 } 4718 4719 switch (w->type) { 4720 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4721 /* If we are tracing HP take only dac of first pin. */ 4722 if (only == w->nid) 4723 res = 1; 4724 break; 4725 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4726 if (depth > 0) 4727 break; 4728 /* Fall */ 4729 default: 4730 /* Try to find reachable ADCs with specified nid. */ 4731 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4732 wc = hdac_widget_get(devinfo, j); 4733 if (wc == NULL || wc->enable == 0) 4734 continue; 4735 for (i = 0; i < wc->nconns; i++) { 4736 if (wc->connsenable[i] == 0) 4737 continue; 4738 if (wc->conns[i] != nid) 4739 continue; 4740 if (hdac_audio_trace_adc(devinfo, as, seq, 4741 j, only, depth + 1) != 0) { 4742 res = 1; 4743 if (((wc->nconns > 1 && 4744 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4745 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4746 wc->selconn == -1) 4747 wc->selconn = i; 4748 } 4749 } 4750 } 4751 break; 4752 } 4753 if (res) { 4754 w->bindas = as; 4755 w->bindseqmask |= (1 << seq); 4756 } 4757 HDA_BOOTHVERBOSE( 4758 device_printf(devinfo->codec->sc->dev, 4759 " %*snid %d returned %d\n", 4760 depth + 1, "", w->nid, res); 4761 ); 4762 return (res); 4763} 4764 4765/* 4766 * Erase trace path of the specified association. 4767 */ 4768static void 4769hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4770{ 4771 struct hdac_widget *w; 4772 int i; 4773 4774 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4775 w = hdac_widget_get(devinfo, i); 4776 if (w == NULL || w->enable == 0) 4777 continue; 4778 if (w->bindas == as) { 4779 if (seq >= 0) { 4780 w->bindseqmask &= ~(1 << seq); 4781 if (w->bindseqmask == 0) { 4782 w->bindas = -1; 4783 w->selconn = -1; 4784 } 4785 } else { 4786 w->bindas = -1; 4787 w->bindseqmask = 0; 4788 w->selconn = -1; 4789 } 4790 } 4791 } 4792} 4793 4794/* 4795 * Trace association path from DAC to output 4796 */ 4797static int 4798hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4799{ 4800 struct hdac_audio_as *ases = devinfo->function.audio.as; 4801 int i, hpredir; 4802 nid_t min, res; 4803 4804 /* Find next pin */ 4805 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4806 ; 4807 /* Check if there is no any left. If so - we succeded. */ 4808 if (i == 16) 4809 return (1); 4810 4811 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4812 min = 0; 4813 res = 0; 4814 do { 4815 HDA_BOOTHVERBOSE( 4816 device_printf(devinfo->codec->sc->dev, 4817 " Tracing pin %d with min nid %d", 4818 ases[as].pins[i], min); 4819 if (hpredir >= 0) 4820 printf(" and hpredir %d", hpredir); 4821 printf("\n"); 4822 ); 4823 /* Trace this pin taking min nid into account. */ 4824 res = hdac_audio_trace_dac(devinfo, as, i, 4825 ases[as].pins[i], hpredir, min, 0, 0); 4826 if (res == 0) { 4827 /* If we failed - return to previous and redo it. */ 4828 HDA_BOOTVERBOSE( 4829 device_printf(devinfo->codec->sc->dev, 4830 " Unable to trace pin %d seq %d with min " 4831 "nid %d", 4832 ases[as].pins[i], i, min); 4833 if (hpredir >= 0) 4834 printf(" and hpredir %d", hpredir); 4835 printf("\n"); 4836 ); 4837 return (0); 4838 } 4839 HDA_BOOTVERBOSE( 4840 device_printf(devinfo->codec->sc->dev, 4841 " Pin %d traced to DAC %d", 4842 ases[as].pins[i], res); 4843 if (hpredir >= 0) 4844 printf(" and hpredir %d", hpredir); 4845 if (ases[as].fakeredir) 4846 printf(" with fake redirection"); 4847 printf("\n"); 4848 ); 4849 /* Trace again to mark the path */ 4850 hdac_audio_trace_dac(devinfo, as, i, 4851 ases[as].pins[i], hpredir, min, res, 0); 4852 ases[as].dacs[i] = res; 4853 /* We succeded, so call next. */ 4854 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4855 return (1); 4856 /* If next failed, we should retry with next min */ 4857 hdac_audio_undo_trace(devinfo, as, i); 4858 ases[as].dacs[i] = 0; 4859 min = res + 1; 4860 } while (1); 4861} 4862 4863/* 4864 * Trace association path from input to ADC 4865 */ 4866static int 4867hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4868{ 4869 struct hdac_audio_as *ases = devinfo->function.audio.as; 4870 struct hdac_widget *w; 4871 int i, j, k; 4872 4873 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4874 w = hdac_widget_get(devinfo, j); 4875 if (w == NULL || w->enable == 0) 4876 continue; 4877 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4878 continue; 4879 if (w->bindas >= 0 && w->bindas != as) 4880 continue; 4881 4882 /* Find next pin */ 4883 for (i = 0; i < 16; i++) { 4884 if (ases[as].pins[i] == 0) 4885 continue; 4886 4887 HDA_BOOTHVERBOSE( 4888 device_printf(devinfo->codec->sc->dev, 4889 " Tracing pin %d to ADC %d\n", 4890 ases[as].pins[i], j); 4891 ); 4892 /* Trace this pin taking goal into account. */ 4893 if (hdac_audio_trace_adc(devinfo, as, i, 4894 ases[as].pins[i], j, 0) == 0) { 4895 /* If we failed - return to previous and redo it. */ 4896 HDA_BOOTVERBOSE( 4897 device_printf(devinfo->codec->sc->dev, 4898 " Unable to trace pin %d to ADC %d, undo traces\n", 4899 ases[as].pins[i], j); 4900 ); 4901 hdac_audio_undo_trace(devinfo, as, -1); 4902 for (k = 0; k < 16; k++) 4903 ases[as].dacs[k] = 0; 4904 break; 4905 } 4906 HDA_BOOTVERBOSE( 4907 device_printf(devinfo->codec->sc->dev, 4908 " Pin %d traced to ADC %d\n", 4909 ases[as].pins[i], j); 4910 ); 4911 ases[as].dacs[i] = j; 4912 } 4913 if (i == 16) 4914 return (1); 4915 } 4916 return (0); 4917} 4918 4919/* 4920 * Trace input monitor path from mixer to output association. 4921 */ 4922static int 4923hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4924{ 4925 struct hdac_audio_as *ases = devinfo->function.audio.as; 4926 struct hdac_widget *w, *wc; 4927 int i, j; 4928 nid_t res = 0; 4929 4930 if (depth > HDA_PARSE_MAXDEPTH) 4931 return (0); 4932 w = hdac_widget_get(devinfo, nid); 4933 if (w == NULL || w->enable == 0) 4934 return (0); 4935 HDA_BOOTHVERBOSE( 4936 device_printf(devinfo->codec->sc->dev, 4937 " %*stracing via nid %d\n", 4938 depth + 1, "", w->nid); 4939 ); 4940 /* Use only unused widgets */ 4941 if (depth > 0 && w->bindas != -1) { 4942 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4943 HDA_BOOTHVERBOSE( 4944 device_printf(devinfo->codec->sc->dev, 4945 " %*snid %d found output association %d\n", 4946 depth + 1, "", w->nid, w->bindas); 4947 ); 4948 return (1); 4949 } else { 4950 HDA_BOOTHVERBOSE( 4951 device_printf(devinfo->codec->sc->dev, 4952 " %*snid %d busy by input association %d\n", 4953 depth + 1, "", w->nid, w->bindas); 4954 ); 4955 return (0); 4956 } 4957 } 4958 4959 switch (w->type) { 4960 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4961 /* Do not traverse input. AD1988 has digital monitor 4962 for which we are not ready. */ 4963 break; 4964 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4965 if (depth > 0) 4966 break; 4967 /* Fall */ 4968 default: 4969 /* Try to find reachable ADCs with specified nid. */ 4970 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4971 wc = hdac_widget_get(devinfo, j); 4972 if (wc == NULL || wc->enable == 0) 4973 continue; 4974 for (i = 0; i < wc->nconns; i++) { 4975 if (wc->connsenable[i] == 0) 4976 continue; 4977 if (wc->conns[i] != nid) 4978 continue; 4979 if (hdac_audio_trace_to_out(devinfo, 4980 j, depth + 1) != 0) { 4981 res = 1; 4982 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4983 wc->selconn == -1) 4984 wc->selconn = i; 4985 } 4986 } 4987 } 4988 break; 4989 } 4990 if (res) 4991 w->bindas = -2; 4992 4993 HDA_BOOTHVERBOSE( 4994 device_printf(devinfo->codec->sc->dev, 4995 " %*snid %d returned %d\n", 4996 depth + 1, "", w->nid, res); 4997 ); 4998 return (res); 4999} 5000 5001/* 5002 * Trace extra associations (beeper, monitor) 5003 */ 5004static void 5005hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5006{ 5007 struct hdac_audio_as *as = devinfo->function.audio.as; 5008 struct hdac_widget *w; 5009 int j; 5010 5011 /* Input monitor */ 5012 /* Find mixer associated with input, but supplying signal 5013 for output associations. Hope it will be input monitor. */ 5014 HDA_BOOTVERBOSE( 5015 device_printf(devinfo->codec->sc->dev, 5016 "Tracing input monitor\n"); 5017 ); 5018 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5019 w = hdac_widget_get(devinfo, j); 5020 if (w == NULL || w->enable == 0) 5021 continue; 5022 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5023 continue; 5024 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5025 continue; 5026 HDA_BOOTVERBOSE( 5027 device_printf(devinfo->codec->sc->dev, 5028 " Tracing nid %d to out\n", 5029 j); 5030 ); 5031 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5032 HDA_BOOTVERBOSE( 5033 device_printf(devinfo->codec->sc->dev, 5034 " nid %d is input monitor\n", 5035 w->nid); 5036 ); 5037 w->pflags |= HDA_ADC_MONITOR; 5038 w->ossdev = SOUND_MIXER_IMIX; 5039 } 5040 } 5041 5042 /* Beeper */ 5043 HDA_BOOTVERBOSE( 5044 device_printf(devinfo->codec->sc->dev, 5045 "Tracing beeper\n"); 5046 ); 5047 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5048 w = hdac_widget_get(devinfo, j); 5049 if (w == NULL || w->enable == 0) 5050 continue; 5051 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5052 continue; 5053 HDA_BOOTHVERBOSE( 5054 device_printf(devinfo->codec->sc->dev, 5055 " Tracing nid %d to out\n", 5056 j); 5057 ); 5058 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5059 HDA_BOOTVERBOSE( 5060 device_printf(devinfo->codec->sc->dev, 5061 " nid %d traced to out\n", 5062 j); 5063 ); 5064 } 5065 w->bindas = -2; 5066 } 5067} 5068 5069/* 5070 * Bind assotiations to PCM channels 5071 */ 5072static void 5073hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5074{ 5075 struct hdac_softc *sc = devinfo->codec->sc; 5076 struct hdac_audio_as *as = devinfo->function.audio.as; 5077 int j, cnt = 0, free; 5078 5079 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5080 if (as[j].enable) 5081 cnt++; 5082 } 5083 if (sc->num_chans == 0) { 5084 sc->chans = (struct hdac_chan *)malloc( 5085 sizeof(struct hdac_chan) * cnt, 5086 M_HDAC, M_ZERO | M_NOWAIT); 5087 if (sc->chans == NULL) { 5088 device_printf(devinfo->codec->sc->dev, 5089 "Channels memory allocation failed!\n"); 5090 return; 5091 } 5092 } else { 5093 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5094 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5095 M_HDAC, M_ZERO | M_NOWAIT); 5096 if (sc->chans == NULL) { 5097 sc->num_chans = 0; 5098 device_printf(devinfo->codec->sc->dev, 5099 "Channels memory allocation failed!\n"); 5100 return; 5101 } 5102 } 5103 free = sc->num_chans; 5104 sc->num_chans += cnt; 5105 5106 for (j = free; j < free + cnt; j++) { 5107 devinfo->codec->sc->chans[j].devinfo = devinfo; 5108 devinfo->codec->sc->chans[j].as = -1; 5109 } 5110 5111 /* Assign associations in order of their numbers, */ 5112 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5113 if (as[j].enable == 0) 5114 continue; 5115 5116 as[j].chan = free; 5117 devinfo->codec->sc->chans[free].as = j; 5118 devinfo->codec->sc->chans[free].dir = 5119 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5120 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5121 free++; 5122 } 5123} 5124 5125static void 5126hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5127{ 5128 struct hdac_widget *w; 5129 int i; 5130 5131 /* Disable power and volume widgets. */ 5132 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5133 w = hdac_widget_get(devinfo, i); 5134 if (w == NULL || w->enable == 0) 5135 continue; 5136 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5137 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5138 w->enable = 0; 5139 HDA_BOOTHVERBOSE( 5140 device_printf(devinfo->codec->sc->dev, 5141 " Disabling nid %d due to it's" 5142 " non-audio type.\n", 5143 w->nid); 5144 ); 5145 } 5146 } 5147} 5148 5149static void 5150hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5151{ 5152 struct hdac_widget *w, *cw; 5153 struct hdac_audio_ctl *ctl; 5154 int done, found, i, j, k; 5155 5156 /* Disable useless pins. */ 5157 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5158 w = hdac_widget_get(devinfo, i); 5159 if (w == NULL || w->enable == 0) 5160 continue; 5161 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5162 if ((w->wclass.pin.config & 5163 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5164 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5165 w->enable = 0; 5166 HDA_BOOTHVERBOSE( 5167 device_printf(devinfo->codec->sc->dev, 5168 " Disabling pin nid %d due" 5169 " to None connectivity.\n", 5170 w->nid); 5171 ); 5172 } else if ((w->wclass.pin.config & 5173 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5174 w->enable = 0; 5175 HDA_BOOTHVERBOSE( 5176 device_printf(devinfo->codec->sc->dev, 5177 " Disabling unassociated" 5178 " pin nid %d.\n", 5179 w->nid); 5180 ); 5181 } 5182 } 5183 } 5184 do { 5185 done = 1; 5186 /* Disable and mute controls for disabled widgets. */ 5187 i = 0; 5188 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5189 if (ctl->enable == 0) 5190 continue; 5191 if (ctl->widget->enable == 0 || 5192 (ctl->childwidget != NULL && 5193 ctl->childwidget->enable == 0)) { 5194 ctl->forcemute = 1; 5195 ctl->muted = HDA_AMP_MUTE_ALL; 5196 ctl->left = 0; 5197 ctl->right = 0; 5198 ctl->enable = 0; 5199 if (ctl->ndir == HDA_CTL_IN) 5200 ctl->widget->connsenable[ctl->index] = 0; 5201 done = 0; 5202 HDA_BOOTHVERBOSE( 5203 device_printf(devinfo->codec->sc->dev, 5204 " Disabling ctl %d nid %d cnid %d due" 5205 " to disabled widget.\n", i, 5206 ctl->widget->nid, 5207 (ctl->childwidget != NULL)? 5208 ctl->childwidget->nid:-1); 5209 ); 5210 } 5211 } 5212 /* Disable useless widgets. */ 5213 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5214 w = hdac_widget_get(devinfo, i); 5215 if (w == NULL || w->enable == 0) 5216 continue; 5217 /* Disable inputs with disabled child widgets. */ 5218 for (j = 0; j < w->nconns; j++) { 5219 if (w->connsenable[j]) { 5220 cw = hdac_widget_get(devinfo, w->conns[j]); 5221 if (cw == NULL || cw->enable == 0) { 5222 w->connsenable[j] = 0; 5223 HDA_BOOTHVERBOSE( 5224 device_printf(devinfo->codec->sc->dev, 5225 " Disabling nid %d connection %d due" 5226 " to disabled child widget.\n", 5227 i, j); 5228 ); 5229 } 5230 } 5231 } 5232 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5233 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5234 continue; 5235 /* Disable mixers and selectors without inputs. */ 5236 found = 0; 5237 for (j = 0; j < w->nconns; j++) { 5238 if (w->connsenable[j]) { 5239 found = 1; 5240 break; 5241 } 5242 } 5243 if (found == 0) { 5244 w->enable = 0; 5245 done = 0; 5246 HDA_BOOTHVERBOSE( 5247 device_printf(devinfo->codec->sc->dev, 5248 " Disabling nid %d due to all it's" 5249 " inputs disabled.\n", w->nid); 5250 ); 5251 } 5252 /* Disable nodes without consumers. */ 5253 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5254 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5255 continue; 5256 found = 0; 5257 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5258 cw = hdac_widget_get(devinfo, k); 5259 if (cw == NULL || cw->enable == 0) 5260 continue; 5261 for (j = 0; j < cw->nconns; j++) { 5262 if (cw->connsenable[j] && cw->conns[j] == i) { 5263 found = 1; 5264 break; 5265 } 5266 } 5267 } 5268 if (found == 0) { 5269 w->enable = 0; 5270 done = 0; 5271 HDA_BOOTHVERBOSE( 5272 device_printf(devinfo->codec->sc->dev, 5273 " Disabling nid %d due to all it's" 5274 " consumers disabled.\n", w->nid); 5275 ); 5276 } 5277 } 5278 } while (done == 0); 5279 5280} 5281 5282static void 5283hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5284{ 5285 struct hdac_audio_as *as = devinfo->function.audio.as; 5286 struct hdac_widget *w, *cw; 5287 struct hdac_audio_ctl *ctl; 5288 int i, j, k; 5289 5290 /* Disable unassosiated widgets. */ 5291 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5292 w = hdac_widget_get(devinfo, i); 5293 if (w == NULL || w->enable == 0) 5294 continue; 5295 if (w->bindas == -1) { 5296 w->enable = 0; 5297 HDA_BOOTHVERBOSE( 5298 device_printf(devinfo->codec->sc->dev, 5299 " Disabling unassociated nid %d.\n", 5300 w->nid); 5301 ); 5302 } 5303 } 5304 /* Disable input connections on input pin and 5305 * output on output. */ 5306 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5307 w = hdac_widget_get(devinfo, i); 5308 if (w == NULL || w->enable == 0) 5309 continue; 5310 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5311 continue; 5312 if (w->bindas < 0) 5313 continue; 5314 if (as[w->bindas].dir == HDA_CTL_IN) { 5315 for (j = 0; j < w->nconns; j++) { 5316 if (w->connsenable[j] == 0) 5317 continue; 5318 w->connsenable[j] = 0; 5319 HDA_BOOTHVERBOSE( 5320 device_printf(devinfo->codec->sc->dev, 5321 " Disabling connection to input pin " 5322 "nid %d conn %d.\n", 5323 i, j); 5324 ); 5325 } 5326 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5327 HDA_CTL_IN, -1, 1); 5328 if (ctl && ctl->enable) { 5329 ctl->forcemute = 1; 5330 ctl->muted = HDA_AMP_MUTE_ALL; 5331 ctl->left = 0; 5332 ctl->right = 0; 5333 ctl->enable = 0; 5334 } 5335 } else { 5336 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5337 HDA_CTL_OUT, -1, 1); 5338 if (ctl && ctl->enable) { 5339 ctl->forcemute = 1; 5340 ctl->muted = HDA_AMP_MUTE_ALL; 5341 ctl->left = 0; 5342 ctl->right = 0; 5343 ctl->enable = 0; 5344 } 5345 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5346 cw = hdac_widget_get(devinfo, k); 5347 if (cw == NULL || cw->enable == 0) 5348 continue; 5349 for (j = 0; j < cw->nconns; j++) { 5350 if (cw->connsenable[j] && cw->conns[j] == i) { 5351 cw->connsenable[j] = 0; 5352 HDA_BOOTHVERBOSE( 5353 device_printf(devinfo->codec->sc->dev, 5354 " Disabling connection from output pin " 5355 "nid %d conn %d cnid %d.\n", 5356 k, j, i); 5357 ); 5358 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5359 cw->nconns > 1) 5360 continue; 5361 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5362 HDA_CTL_IN, j, 1); 5363 if (ctl && ctl->enable) { 5364 ctl->forcemute = 1; 5365 ctl->muted = HDA_AMP_MUTE_ALL; 5366 ctl->left = 0; 5367 ctl->right = 0; 5368 ctl->enable = 0; 5369 } 5370 } 5371 } 5372 } 5373 } 5374 } 5375} 5376 5377static void 5378hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5379{ 5380 struct hdac_audio_as *as = devinfo->function.audio.as; 5381 struct hdac_widget *w; 5382 int i, j; 5383 5384 /* On playback path we can safely disable all unseleted inputs. */ 5385 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5386 w = hdac_widget_get(devinfo, i); 5387 if (w == NULL || w->enable == 0) 5388 continue; 5389 if (w->nconns <= 1) 5390 continue; 5391 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5392 continue; 5393 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5394 continue; 5395 for (j = 0; j < w->nconns; j++) { 5396 if (w->connsenable[j] == 0) 5397 continue; 5398 if (w->selconn < 0 || w->selconn == j) 5399 continue; 5400 w->connsenable[j] = 0; 5401 HDA_BOOTHVERBOSE( 5402 device_printf(devinfo->codec->sc->dev, 5403 " Disabling unselected connection " 5404 "nid %d conn %d.\n", 5405 i, j); 5406 ); 5407 } 5408 } 5409} 5410 5411static void 5412hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5413{ 5414 struct hdac_widget *w, *cw; 5415 struct hdac_audio_ctl *ctl; 5416 int i, j; 5417 5418 /* Disable crossassociatement connections. */ 5419 /* ... using selectors */ 5420 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5421 w = hdac_widget_get(devinfo, i); 5422 if (w == NULL || w->enable == 0) 5423 continue; 5424 if (w->nconns <= 1) 5425 continue; 5426 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5427 continue; 5428 if (w->bindas == -2) 5429 continue; 5430 for (j = 0; j < w->nconns; j++) { 5431 if (w->connsenable[j] == 0) 5432 continue; 5433 cw = hdac_widget_get(devinfo, w->conns[j]); 5434 if (cw == NULL || w->enable == 0) 5435 continue; 5436 if (w->bindas == cw->bindas || cw->bindas == -2) 5437 continue; 5438 w->connsenable[j] = 0; 5439 HDA_BOOTHVERBOSE( 5440 device_printf(devinfo->codec->sc->dev, 5441 " Disabling crossassociatement connection " 5442 "nid %d conn %d cnid %d.\n", 5443 i, j, cw->nid); 5444 ); 5445 } 5446 } 5447 /* ... using controls */ 5448 i = 0; 5449 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5450 if (ctl->enable == 0 || ctl->childwidget == NULL) 5451 continue; 5452 if (ctl->widget->bindas == -2 || 5453 ctl->childwidget->bindas == -2) 5454 continue; 5455 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5456 ctl->forcemute = 1; 5457 ctl->muted = HDA_AMP_MUTE_ALL; 5458 ctl->left = 0; 5459 ctl->right = 0; 5460 ctl->enable = 0; 5461 if (ctl->ndir == HDA_CTL_IN) 5462 ctl->widget->connsenable[ctl->index] = 0; 5463 HDA_BOOTHVERBOSE( 5464 device_printf(devinfo->codec->sc->dev, 5465 " Disabling crossassociatement connection " 5466 "ctl %d nid %d cnid %d.\n", i, 5467 ctl->widget->nid, 5468 ctl->childwidget->nid); 5469 ); 5470 } 5471 } 5472 5473} 5474 5475#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5476 5477/* 5478 * Find controls to control amplification for source. 5479 */ 5480static int 5481hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5482 int ossdev, int ctlable, int depth, int need) 5483{ 5484 struct hdac_widget *w, *wc; 5485 struct hdac_audio_ctl *ctl; 5486 int i, j, conns = 0, rneed; 5487 5488 if (depth > HDA_PARSE_MAXDEPTH) 5489 return (need); 5490 5491 w = hdac_widget_get(devinfo, nid); 5492 if (w == NULL || w->enable == 0) 5493 return (need); 5494 5495 /* Count number of active inputs. */ 5496 if (depth > 0) { 5497 for (j = 0; j < w->nconns; j++) { 5498 if (w->connsenable[j]) 5499 conns++; 5500 } 5501 } 5502 5503 /* If this is not a first step - use input mixer. 5504 Pins have common input ctl so care must be taken. */ 5505 if (depth > 0 && ctlable && (conns == 1 || 5506 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5507 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5508 index, 1); 5509 if (ctl) { 5510 if (HDA_CTL_GIVE(ctl) & need) 5511 ctl->ossmask |= (1 << ossdev); 5512 else 5513 ctl->possmask |= (1 << ossdev); 5514 need &= ~HDA_CTL_GIVE(ctl); 5515 } 5516 } 5517 5518 /* If widget has own ossdev - not traverse it. 5519 It will be traversed on it's own. */ 5520 if (w->ossdev >= 0 && depth > 0) 5521 return (need); 5522 5523 /* We must not traverse pin */ 5524 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5525 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5526 depth > 0) 5527 return (need); 5528 5529 /* record that this widget exports such signal, */ 5530 w->ossmask |= (1 << ossdev); 5531 5532 /* If signals mixed, we can't assign controls farther. 5533 * Ignore this on depth zero. Caller must knows why. 5534 * Ignore this for static selectors if this input selected. 5535 */ 5536 if (conns > 1) 5537 ctlable = 0; 5538 5539 if (ctlable) { 5540 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5541 if (ctl) { 5542 if (HDA_CTL_GIVE(ctl) & need) 5543 ctl->ossmask |= (1 << ossdev); 5544 else 5545 ctl->possmask |= (1 << ossdev); 5546 need &= ~HDA_CTL_GIVE(ctl); 5547 } 5548 } 5549 5550 rneed = 0; 5551 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5552 wc = hdac_widget_get(devinfo, i); 5553 if (wc == NULL || wc->enable == 0) 5554 continue; 5555 for (j = 0; j < wc->nconns; j++) { 5556 if (wc->connsenable[j] && wc->conns[j] == nid) { 5557 rneed |= hdac_audio_ctl_source_amp(devinfo, 5558 wc->nid, j, ossdev, ctlable, depth + 1, need); 5559 } 5560 } 5561 } 5562 rneed &= need; 5563 5564 return (rneed); 5565} 5566 5567/* 5568 * Find controls to control amplification for destination. 5569 */ 5570static void 5571hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5572 int ossdev, int depth, int need) 5573{ 5574 struct hdac_audio_as *as = devinfo->function.audio.as; 5575 struct hdac_widget *w, *wc; 5576 struct hdac_audio_ctl *ctl; 5577 int i, j, consumers; 5578 5579 if (depth > HDA_PARSE_MAXDEPTH) 5580 return; 5581 5582 w = hdac_widget_get(devinfo, nid); 5583 if (w == NULL || w->enable == 0) 5584 return; 5585 5586 if (depth > 0) { 5587 /* If this node produce output for several consumers, 5588 we can't touch it. */ 5589 consumers = 0; 5590 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5591 wc = hdac_widget_get(devinfo, i); 5592 if (wc == NULL || wc->enable == 0) 5593 continue; 5594 for (j = 0; j < wc->nconns; j++) { 5595 if (wc->connsenable[j] && wc->conns[j] == nid) 5596 consumers++; 5597 } 5598 } 5599 /* The only exception is if real HP redirection is configured 5600 and this is a duplication point. 5601 XXX: Actually exception is not completely correct. 5602 XXX: Duplication point check is not perfect. */ 5603 if ((consumers == 2 && (w->bindas < 0 || 5604 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5605 (w->bindseqmask & (1 << 15)) == 0)) || 5606 consumers > 2) 5607 return; 5608 5609 /* Else use it's output mixer. */ 5610 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5611 HDA_CTL_OUT, -1, 1); 5612 if (ctl) { 5613 if (HDA_CTL_GIVE(ctl) & need) 5614 ctl->ossmask |= (1 << ossdev); 5615 else 5616 ctl->possmask |= (1 << ossdev); 5617 need &= ~HDA_CTL_GIVE(ctl); 5618 } 5619 } 5620 5621 /* We must not traverse pin */ 5622 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5623 depth > 0) 5624 return; 5625 5626 for (i = 0; i < w->nconns; i++) { 5627 int tneed = need; 5628 if (w->connsenable[i] == 0) 5629 continue; 5630 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5631 HDA_CTL_IN, i, 1); 5632 if (ctl) { 5633 if (HDA_CTL_GIVE(ctl) & tneed) 5634 ctl->ossmask |= (1 << ossdev); 5635 else 5636 ctl->possmask |= (1 << ossdev); 5637 tneed &= ~HDA_CTL_GIVE(ctl); 5638 } 5639 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5640 depth + 1, tneed); 5641 } 5642} 5643 5644/* 5645 * Assign OSS names to sound sources 5646 */ 5647static void 5648hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5649{ 5650 struct hdac_audio_as *as = devinfo->function.audio.as; 5651 struct hdac_widget *w; 5652 int i, j; 5653 int type = -1, use, used = 0; 5654 static const int types[7][13] = { 5655 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5656 SOUND_MIXER_LINE3, -1 }, /* line */ 5657 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5658 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5659 { SOUND_MIXER_CD, -1 }, /* cd */ 5660 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5661 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5662 -1 }, /* digital */ 5663 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5664 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5665 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5666 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5667 -1 } /* others */ 5668 }; 5669 5670 /* Surely known names */ 5671 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5672 w = hdac_widget_get(devinfo, i); 5673 if (w == NULL || w->enable == 0) 5674 continue; 5675 if (w->bindas == -1) 5676 continue; 5677 use = -1; 5678 switch (w->type) { 5679 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5680 if (as[w->bindas].dir == HDA_CTL_OUT) 5681 break; 5682 type = -1; 5683 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5684 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5685 type = 0; 5686 break; 5687 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5688 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5689 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5690 break; 5691 type = 1; 5692 break; 5693 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5694 type = 3; 5695 break; 5696 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5697 type = 4; 5698 break; 5699 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5700 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5701 type = 5; 5702 break; 5703 } 5704 if (type == -1) 5705 break; 5706 j = 0; 5707 while (types[type][j] >= 0 && 5708 (used & (1 << types[type][j])) != 0) { 5709 j++; 5710 } 5711 if (types[type][j] >= 0) 5712 use = types[type][j]; 5713 break; 5714 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5715 use = SOUND_MIXER_PCM; 5716 break; 5717 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5718 use = SOUND_MIXER_SPEAKER; 5719 break; 5720 default: 5721 break; 5722 } 5723 if (use >= 0) { 5724 w->ossdev = use; 5725 used |= (1 << use); 5726 } 5727 } 5728 /* Semi-known names */ 5729 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5730 w = hdac_widget_get(devinfo, i); 5731 if (w == NULL || w->enable == 0) 5732 continue; 5733 if (w->ossdev >= 0) 5734 continue; 5735 if (w->bindas == -1) 5736 continue; 5737 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5738 continue; 5739 if (as[w->bindas].dir == HDA_CTL_OUT) 5740 continue; 5741 type = -1; 5742 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5743 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5744 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5745 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5746 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5747 type = 0; 5748 break; 5749 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5750 type = 2; 5751 break; 5752 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5753 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5754 type = 5; 5755 break; 5756 } 5757 if (type == -1) 5758 break; 5759 j = 0; 5760 while (types[type][j] >= 0 && 5761 (used & (1 << types[type][j])) != 0) { 5762 j++; 5763 } 5764 if (types[type][j] >= 0) { 5765 w->ossdev = types[type][j]; 5766 used |= (1 << types[type][j]); 5767 } 5768 } 5769 /* Others */ 5770 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5771 w = hdac_widget_get(devinfo, i); 5772 if (w == NULL || w->enable == 0) 5773 continue; 5774 if (w->ossdev >= 0) 5775 continue; 5776 if (w->bindas == -1) 5777 continue; 5778 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5779 continue; 5780 if (as[w->bindas].dir == HDA_CTL_OUT) 5781 continue; 5782 j = 0; 5783 while (types[6][j] >= 0 && 5784 (used & (1 << types[6][j])) != 0) { 5785 j++; 5786 } 5787 if (types[6][j] >= 0) { 5788 w->ossdev = types[6][j]; 5789 used |= (1 << types[6][j]); 5790 } 5791 } 5792} 5793 5794static void 5795hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5796{ 5797 struct hdac_audio_as *as = devinfo->function.audio.as; 5798 int j, res; 5799 5800 /* Trace all associations in order of their numbers, */ 5801 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5802 if (as[j].enable == 0) 5803 continue; 5804 HDA_BOOTVERBOSE( 5805 device_printf(devinfo->codec->sc->dev, 5806 "Tracing association %d (%d)\n", j, as[j].index); 5807 ); 5808 if (as[j].dir == HDA_CTL_OUT) { 5809retry: 5810 res = hdac_audio_trace_as_out(devinfo, j, 0); 5811 if (res == 0 && as[j].hpredir >= 0 && 5812 as[j].fakeredir == 0) { 5813 /* If codec can't do analog HP redirection 5814 try to make it using one more DAC. */ 5815 as[j].fakeredir = 1; 5816 goto retry; 5817 } 5818 } else { 5819 res = hdac_audio_trace_as_in(devinfo, j); 5820 } 5821 if (res) { 5822 HDA_BOOTVERBOSE( 5823 device_printf(devinfo->codec->sc->dev, 5824 "Association %d (%d) trace succeded\n", 5825 j, as[j].index); 5826 ); 5827 } else { 5828 HDA_BOOTVERBOSE( 5829 device_printf(devinfo->codec->sc->dev, 5830 "Association %d (%d) trace failed\n", 5831 j, as[j].index); 5832 ); 5833 as[j].enable = 0; 5834 } 5835 } 5836 5837 /* Trace mixer and beeper pseudo associations. */ 5838 hdac_audio_trace_as_extra(devinfo); 5839} 5840 5841static void 5842hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5843{ 5844 struct hdac_audio_as *as = devinfo->function.audio.as; 5845 struct hdac_audio_ctl *ctl; 5846 struct hdac_widget *w; 5847 int i; 5848 5849 /* Assign mixers to the tree. */ 5850 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5851 w = hdac_widget_get(devinfo, i); 5852 if (w == NULL || w->enable == 0) 5853 continue; 5854 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5855 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5856 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5857 as[w->bindas].dir == HDA_CTL_IN)) { 5858 if (w->ossdev < 0) 5859 continue; 5860 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5861 w->ossdev, 1, 0, 1); 5862 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5863 if (w->ossdev < 0) 5864 continue; 5865 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5866 w->ossdev, 1, 0, 1)) { 5867 /* If we are unable to control input monitor 5868 as source - try to control it as destination. */ 5869 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5870 w->ossdev, 0, 1); 5871 } 5872 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5873 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5874 SOUND_MIXER_RECLEV, 0, 1); 5875 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5876 as[w->bindas].dir == HDA_CTL_OUT) { 5877 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5878 SOUND_MIXER_VOLUME, 0, 1); 5879 } 5880 } 5881 /* Treat unrequired as possible. */ 5882 i = 0; 5883 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5884 if (ctl->ossmask == 0) 5885 ctl->ossmask = ctl->possmask; 5886 } 5887} 5888 5889static void 5890hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5891{ 5892 struct hdac_audio_as *as = devinfo->function.audio.as; 5893 struct hdac_widget *w; 5894 uint32_t pincap; 5895 int i; 5896 5897 for (i = 0; i < devinfo->nodecnt; i++) { 5898 w = &devinfo->widget[i]; 5899 if (w == NULL) 5900 continue; 5901 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5902 continue; 5903 5904 pincap = w->wclass.pin.cap; 5905 5906 /* Disable everything. */ 5907 w->wclass.pin.ctrl &= ~( 5908 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5909 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5910 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5911 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5912 5913 if (w->enable == 0 || 5914 w->bindas < 0 || as[w->bindas].enable == 0) { 5915 /* Pin is unused so left it disabled. */ 5916 continue; 5917 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5918 /* Input pin, configure for input. */ 5919 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5920 w->wclass.pin.ctrl |= 5921 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5922 5923 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5924 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5925 w->wclass.pin.ctrl |= 5926 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5927 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5928 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5929 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5930 w->wclass.pin.ctrl |= 5931 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5932 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5933 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5934 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5935 w->wclass.pin.ctrl |= 5936 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5937 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5938 } else { 5939 /* Output pin, configure for output. */ 5940 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5941 w->wclass.pin.ctrl |= 5942 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5943 5944 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5945 (w->wclass.pin.config & 5946 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5947 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5948 w->wclass.pin.ctrl |= 5949 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5950 5951 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5952 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5953 w->wclass.pin.ctrl |= 5954 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5955 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5956 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5957 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5958 w->wclass.pin.ctrl |= 5959 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5960 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5961 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5962 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5963 w->wclass.pin.ctrl |= 5964 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5965 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5966 } 5967 } 5968} 5969 5970static void 5971hdac_audio_commit(struct hdac_devinfo *devinfo) 5972{ 5973 struct hdac_softc *sc = devinfo->codec->sc; 5974 struct hdac_widget *w; 5975 nid_t cad; 5976 uint32_t gdata, gmask, gdir; 5977 int commitgpio, numgpio; 5978 int i; 5979 5980 cad = devinfo->codec->cad; 5981 5982 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5983 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5984 0x7e7, 0), cad); 5985 5986 gdata = 0; 5987 gmask = 0; 5988 gdir = 0; 5989 commitgpio = 0; 5990 5991 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5992 devinfo->function.audio.gpio); 5993 5994 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5995 commitgpio = (numgpio > 0) ? 1 : 0; 5996 else { 5997 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5998 if (!(devinfo->function.audio.quirks & 5999 (1 << i))) 6000 continue; 6001 if (commitgpio == 0) { 6002 commitgpio = 1; 6003 HDA_BOOTVERBOSE( 6004 gdata = hdac_command(sc, 6005 HDA_CMD_GET_GPIO_DATA(cad, 6006 devinfo->nid), cad); 6007 gmask = hdac_command(sc, 6008 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6009 devinfo->nid), cad); 6010 gdir = hdac_command(sc, 6011 HDA_CMD_GET_GPIO_DIRECTION(cad, 6012 devinfo->nid), cad); 6013 device_printf(sc->dev, 6014 "GPIO init: data=0x%08x " 6015 "mask=0x%08x dir=0x%08x\n", 6016 gdata, gmask, gdir); 6017 gdata = 0; 6018 gmask = 0; 6019 gdir = 0; 6020 ); 6021 } 6022 gdata |= 1 << i; 6023 gmask |= 1 << i; 6024 gdir |= 1 << i; 6025 } 6026 } 6027 6028 if (commitgpio != 0) { 6029 HDA_BOOTVERBOSE( 6030 device_printf(sc->dev, 6031 "GPIO commit: data=0x%08x mask=0x%08x " 6032 "dir=0x%08x\n", 6033 gdata, gmask, gdir); 6034 ); 6035 hdac_command(sc, 6036 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6037 gmask), cad); 6038 hdac_command(sc, 6039 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6040 gdir), cad); 6041 hdac_command(sc, 6042 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6043 gdata), cad); 6044 } 6045 6046 for (i = 0; i < devinfo->nodecnt; i++) { 6047 w = &devinfo->widget[i]; 6048 if (w == NULL) 6049 continue; 6050 if (w->selconn == -1) 6051 w->selconn = 0; 6052 if (w->nconns > 0) 6053 hdac_widget_connection_select(w, w->selconn); 6054 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6055 hdac_command(sc, 6056 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6057 w->wclass.pin.ctrl), cad); 6058 } 6059 if (w->param.eapdbtl != HDAC_INVALID) { 6060 uint32_t val; 6061 6062 val = w->param.eapdbtl; 6063 if (devinfo->function.audio.quirks & 6064 HDA_QUIRK_EAPDINV) 6065 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6066 hdac_command(sc, 6067 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6068 val), cad); 6069 6070 } 6071 } 6072} 6073 6074static void 6075hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6076{ 6077 struct hdac_audio_ctl *ctl; 6078 int i, z; 6079 6080 i = 0; 6081 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6082 if (ctl->enable == 0) { 6083 /* Mute disabled controls. */ 6084 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6085 continue; 6086 } 6087 /* Init controls to 0dB amplification. */ 6088 z = ctl->offset; 6089 if (z > ctl->step) 6090 z = ctl->step; 6091 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6092 } 6093} 6094 6095static void 6096hdac_powerup(struct hdac_devinfo *devinfo) 6097{ 6098 struct hdac_softc *sc = devinfo->codec->sc; 6099 nid_t cad = devinfo->codec->cad; 6100 int i; 6101 6102 hdac_command(sc, 6103 HDA_CMD_SET_POWER_STATE(cad, 6104 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6105 cad); 6106 DELAY(100); 6107 6108 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6109 hdac_command(sc, 6110 HDA_CMD_SET_POWER_STATE(cad, 6111 i, HDA_CMD_POWER_STATE_D0), 6112 cad); 6113 } 6114 DELAY(1000); 6115} 6116 6117static int 6118hdac_pcmchannel_setup(struct hdac_chan *ch) 6119{ 6120 struct hdac_devinfo *devinfo = ch->devinfo; 6121 struct hdac_audio_as *as = devinfo->function.audio.as; 6122 struct hdac_widget *w; 6123 uint32_t cap, fmtcap, pcmcap; 6124 int i, j, ret, max; 6125 6126 ch->caps = hdac_caps; 6127 ch->caps.fmtlist = ch->fmtlist; 6128 ch->bit16 = 1; 6129 ch->bit32 = 0; 6130 ch->pcmrates[0] = 48000; 6131 ch->pcmrates[1] = 0; 6132 6133 ret = 0; 6134 fmtcap = devinfo->function.audio.supp_stream_formats; 6135 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6136 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6137 6138 for (i = 0; i < 16 && ret < max; i++) { 6139 /* Check as is correct */ 6140 if (ch->as < 0) 6141 break; 6142 /* Cound only present DACs */ 6143 if (as[ch->as].dacs[i] <= 0) 6144 continue; 6145 /* Ignore duplicates */ 6146 for (j = 0; j < ret; j++) { 6147 if (ch->io[j] == as[ch->as].dacs[i]) 6148 break; 6149 } 6150 if (j < ret) 6151 continue; 6152 6153 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6154 if (w == NULL || w->enable == 0) 6155 continue; 6156 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6157 continue; 6158 cap = w->param.supp_stream_formats; 6159 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6160 }*/ 6161 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6162 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6163 continue; 6164 /* Many codec does not declare AC3 support on SPDIF. 6165 I don't beleave that they doesn't support it! */ 6166 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6167 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6168 if (ret == 0) { 6169 fmtcap = cap; 6170 pcmcap = w->param.supp_pcm_size_rate; 6171 } else { 6172 fmtcap &= cap; 6173 pcmcap &= w->param.supp_pcm_size_rate; 6174 } 6175 ch->io[ret++] = as[ch->as].dacs[i]; 6176 } 6177 ch->io[ret] = -1; 6178 6179 ch->supp_stream_formats = fmtcap; 6180 ch->supp_pcm_size_rate = pcmcap; 6181 6182 /* 6183 * 8bit = 0 6184 * 16bit = 1 6185 * 20bit = 2 6186 * 24bit = 3 6187 * 32bit = 4 6188 */ 6189 if (ret > 0) { 6190 i = 0; 6191 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6193 ch->bit16 = 1; 6194 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6195 ch->bit16 = 0; 6196 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6197 ch->bit32 = 4; 6198 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6199 ch->bit32 = 3; 6200 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6201 ch->bit32 = 2; 6202 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6203 ch->fmtlist[i++] = AFMT_S16_LE; 6204 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6205 if (ch->bit32 > 0) { 6206 if (!(devinfo->function.audio.quirks & 6207 HDA_QUIRK_FORCESTEREO)) 6208 ch->fmtlist[i++] = AFMT_S32_LE; 6209 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6210 } 6211 } 6212 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6213 ch->fmtlist[i++] = AFMT_AC3; 6214 } 6215 ch->fmtlist[i] = 0; 6216 i = 0; 6217 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6218 ch->pcmrates[i++] = 8000; 6219 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6220 ch->pcmrates[i++] = 11025; 6221 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6222 ch->pcmrates[i++] = 16000; 6223 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6224 ch->pcmrates[i++] = 22050; 6225 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6226 ch->pcmrates[i++] = 32000; 6227 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6228 ch->pcmrates[i++] = 44100; 6229 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6230 ch->pcmrates[i++] = 48000; 6231 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6232 ch->pcmrates[i++] = 88200; 6233 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6234 ch->pcmrates[i++] = 96000; 6235 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6236 ch->pcmrates[i++] = 176400; 6237 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6238 ch->pcmrates[i++] = 192000; 6239 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6240 ch->pcmrates[i] = 0; 6241 if (i > 0) { 6242 ch->caps.minspeed = ch->pcmrates[0]; 6243 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6244 } 6245 } 6246 6247 return (ret); 6248} 6249 6250static void 6251hdac_create_pcms(struct hdac_devinfo *devinfo) 6252{ 6253 struct hdac_softc *sc = devinfo->codec->sc; 6254 struct hdac_audio_as *as = devinfo->function.audio.as; 6255 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6256 6257 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6258 if (as[i].enable == 0) 6259 continue; 6260 if (as[i].dir == HDA_CTL_IN) { 6261 if (as[i].digital) 6262 drdev++; 6263 else 6264 ardev++; 6265 } else { 6266 if (as[i].digital) 6267 dpdev++; 6268 else 6269 apdev++; 6270 } 6271 } 6272 devinfo->function.audio.num_devs = 6273 max(ardev, apdev) + max(drdev, dpdev); 6274 devinfo->function.audio.devs = 6275 (struct hdac_pcm_devinfo *)malloc( 6276 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6277 M_HDAC, M_ZERO | M_NOWAIT); 6278 if (devinfo->function.audio.devs == NULL) { 6279 device_printf(sc->dev, 6280 "Unable to allocate memory for devices\n"); 6281 return; 6282 } 6283 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6284 devinfo->function.audio.devs[i].index = i; 6285 devinfo->function.audio.devs[i].devinfo = devinfo; 6286 devinfo->function.audio.devs[i].play = -1; 6287 devinfo->function.audio.devs[i].rec = -1; 6288 devinfo->function.audio.devs[i].digital = 2; 6289 } 6290 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6291 if (as[i].enable == 0) 6292 continue; 6293 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6294 if (devinfo->function.audio.devs[j].digital != 2 && 6295 devinfo->function.audio.devs[j].digital != 6296 as[i].digital) 6297 continue; 6298 if (as[i].dir == HDA_CTL_IN) { 6299 if (devinfo->function.audio.devs[j].rec >= 0) 6300 continue; 6301 devinfo->function.audio.devs[j].rec 6302 = as[i].chan; 6303 } else { 6304 if (devinfo->function.audio.devs[j].play >= 0) 6305 continue; 6306 devinfo->function.audio.devs[j].play 6307 = as[i].chan; 6308 } 6309 sc->chans[as[i].chan].pdevinfo = 6310 &devinfo->function.audio.devs[j]; 6311 devinfo->function.audio.devs[j].digital = 6312 as[i].digital; 6313 break; 6314 } 6315 } 6316 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6317 struct hdac_pcm_devinfo *pdevinfo = 6318 &devinfo->function.audio.devs[i]; 6319 pdevinfo->dev = 6320 device_add_child(sc->dev, "pcm", -1); 6321 device_set_ivars(pdevinfo->dev, 6322 (void *)pdevinfo); 6323 } 6324} 6325 6326static void 6327hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6328{ 6329 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6330 struct hdac_audio_ctl *ctl; 6331 struct hdac_softc *sc = devinfo->codec->sc; 6332 char buf[64]; 6333 int i, j, printed; 6334 6335 if (flag == 0) { 6336 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6337 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6338 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6339 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6340 } 6341 6342 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6343 if ((flag & (1 << j)) == 0) 6344 continue; 6345 i = 0; 6346 printed = 0; 6347 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6348 if (ctl->enable == 0 || 6349 ctl->widget->enable == 0) 6350 continue; 6351 if (!((pdevinfo->play >= 0 && 6352 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6353 (pdevinfo->rec >= 0 && 6354 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6355 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6356 continue; 6357 if ((ctl->ossmask & (1 << j)) == 0) 6358 continue; 6359 6360 if (printed == 0) { 6361 device_printf(pdevinfo->dev, "\n"); 6362 if (banner != NULL) { 6363 device_printf(pdevinfo->dev, "%s", banner); 6364 } else { 6365 device_printf(pdevinfo->dev, "Unknown Ctl"); 6366 } 6367 printf(" (OSS: %s)\n", 6368 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6369 buf, sizeof(buf))); 6370 device_printf(pdevinfo->dev, " |\n"); 6371 printed = 1; 6372 } 6373 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6374 ctl->widget->nid, 6375 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6376 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6377 printf(" %2d): ", ctl->index); 6378 else 6379 printf("): "); 6380 if (ctl->step > 0) { 6381 printf("%+d/%+ddB (%d steps)%s\n", 6382 (0 - ctl->offset) * (ctl->size + 1) / 4, 6383 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6384 ctl->step + 1, 6385 ctl->mute?" + mute":""); 6386 } else 6387 printf("%s\n", ctl->mute?"mute":""); 6388 } 6389 } 6390} 6391 6392static void 6393hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6394{ 6395 uint32_t cap; 6396 6397 cap = fcap; 6398 if (cap != 0) { 6399 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6400 device_printf(dev, " "); 6401 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6402 printf(" AC3"); 6403 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6404 printf(" FLOAT32"); 6405 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6406 printf(" PCM"); 6407 printf("\n"); 6408 } 6409 cap = pcmcap; 6410 if (cap != 0) { 6411 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6412 device_printf(dev, " "); 6413 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6414 printf(" 8"); 6415 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6416 printf(" 16"); 6417 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6418 printf(" 20"); 6419 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6420 printf(" 24"); 6421 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6422 printf(" 32"); 6423 printf(" bits,"); 6424 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6425 printf(" 8"); 6426 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6427 printf(" 11"); 6428 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6429 printf(" 16"); 6430 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6431 printf(" 22"); 6432 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6433 printf(" 32"); 6434 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6435 printf(" 44"); 6436 printf(" 48"); 6437 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6438 printf(" 88"); 6439 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6440 printf(" 96"); 6441 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6442 printf(" 176"); 6443 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6444 printf(" 192"); 6445 printf(" KHz\n"); 6446 } 6447} 6448 6449static void 6450hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6451{ 6452 uint32_t pincap; 6453 6454 pincap = w->wclass.pin.cap; 6455 6456 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6457 device_printf(sc->dev, " "); 6458 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6459 printf(" ISC"); 6460 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6461 printf(" TRQD"); 6462 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6463 printf(" PDC"); 6464 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6465 printf(" HP"); 6466 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6467 printf(" OUT"); 6468 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6469 printf(" IN"); 6470 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6471 printf(" BAL"); 6472 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6473 printf(" VREF["); 6474 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6475 printf(" 50"); 6476 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6477 printf(" 80"); 6478 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6479 printf(" 100"); 6480 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6481 printf(" GROUND"); 6482 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6483 printf(" HIZ"); 6484 printf(" ]"); 6485 } 6486 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6487 printf(" EAPD"); 6488 printf("\n"); 6489 device_printf(sc->dev, " Pin config: 0x%08x\n", 6490 w->wclass.pin.config); 6491 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6492 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6493 printf(" HP"); 6494 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6495 printf(" IN"); 6496 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6497 printf(" OUT"); 6498 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6499 printf(" VREFs"); 6500 printf("\n"); 6501} 6502 6503static void 6504hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6505{ 6506 struct hdac_softc *sc = w->devinfo->codec->sc; 6507 6508 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6509 "jack %2d loc %2d color %7s misc %d%s\n", 6510 w->nid, conf, 6511 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6512 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6513 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6514 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6515 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6516 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6517 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6518 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6519 (w->enable == 0)?" [DISABLED]":""); 6520} 6521 6522static void 6523hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6524{ 6525 struct hdac_widget *w; 6526 int i; 6527 6528 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6529 w = hdac_widget_get(devinfo, i); 6530 if (w == NULL) 6531 continue; 6532 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6533 continue; 6534 hdac_dump_pin_config(w, w->wclass.pin.config); 6535 } 6536} 6537 6538static void 6539hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6540{ 6541 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6542 device_printf(sc->dev, " " 6543 "mute=%d step=%d size=%d offset=%d\n", 6544 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6545 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6546 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6547 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6548} 6549 6550static void 6551hdac_dump_nodes(struct hdac_devinfo *devinfo) 6552{ 6553 struct hdac_softc *sc = devinfo->codec->sc; 6554 static char *ossname[] = SOUND_DEVICE_NAMES; 6555 struct hdac_widget *w, *cw; 6556 char buf[64]; 6557 int i, j; 6558 6559 device_printf(sc->dev, "\n"); 6560 device_printf(sc->dev, "Default Parameter\n"); 6561 device_printf(sc->dev, "-----------------\n"); 6562 hdac_dump_audio_formats(sc->dev, 6563 devinfo->function.audio.supp_stream_formats, 6564 devinfo->function.audio.supp_pcm_size_rate); 6565 device_printf(sc->dev, " IN amp: 0x%08x\n", 6566 devinfo->function.audio.inamp_cap); 6567 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6568 devinfo->function.audio.outamp_cap); 6569 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6570 w = hdac_widget_get(devinfo, i); 6571 if (w == NULL) { 6572 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6573 continue; 6574 } 6575 device_printf(sc->dev, "\n"); 6576 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6577 (w->enable == 0) ? " [DISABLED]" : ""); 6578 device_printf(sc->dev, " Name: %s\n", w->name); 6579 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6580 w->param.widget_cap); 6581 if (w->param.widget_cap & 0x0ee1) { 6582 device_printf(sc->dev, " "); 6583 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6584 printf(" LRSWAP"); 6585 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6586 printf(" PWR"); 6587 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6588 printf(" DIGITAL"); 6589 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6590 printf(" UNSOL"); 6591 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6592 printf(" PROC"); 6593 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6594 printf(" STRIPE"); 6595 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6596 printf(" STEREO"); 6597 printf("\n"); 6598 } 6599 if (w->bindas != -1) { 6600 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6601 w->bindas, w->bindseqmask); 6602 } 6603 if (w->ossmask != 0 || w->ossdev >= 0) { 6604 device_printf(sc->dev, " OSS: %s", 6605 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6606 if (w->ossdev >= 0) 6607 printf(" (%s)", ossname[w->ossdev]); 6608 printf("\n"); 6609 } 6610 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6611 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6612 hdac_dump_audio_formats(sc->dev, 6613 w->param.supp_stream_formats, 6614 w->param.supp_pcm_size_rate); 6615 } else if (w->type == 6616 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6617 hdac_dump_pin(sc, w); 6618 if (w->param.eapdbtl != HDAC_INVALID) 6619 device_printf(sc->dev, " EAPD: 0x%08x\n", 6620 w->param.eapdbtl); 6621 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6622 w->param.outamp_cap != 0) 6623 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6624 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6625 w->param.inamp_cap != 0) 6626 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6627 if (w->nconns > 0) { 6628 device_printf(sc->dev, " connections: %d\n", w->nconns); 6629 device_printf(sc->dev, " |\n"); 6630 } 6631 for (j = 0; j < w->nconns; j++) { 6632 cw = hdac_widget_get(devinfo, w->conns[j]); 6633 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6634 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6635 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6636 if (cw == NULL) 6637 printf(" [UNKNOWN]"); 6638 else if (cw->enable == 0) 6639 printf(" [DISABLED]"); 6640 if (w->nconns > 1 && w->selconn == j && w->type != 6641 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6642 printf(" (selected)"); 6643 printf("\n"); 6644 } 6645 } 6646 6647} 6648 6649static void 6650hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6651{ 6652 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6653 struct hdac_widget *w, *cw; 6654 char buf[64]; 6655 int i, printed = 0; 6656 6657 if (depth > HDA_PARSE_MAXDEPTH) 6658 return; 6659 6660 w = hdac_widget_get(devinfo, nid); 6661 if (w == NULL || w->enable == 0) 6662 return; 6663 6664 if (depth == 0) 6665 device_printf(pdevinfo->dev, "%*s", 4, ""); 6666 else 6667 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6668 printf("nid=%d [%s]", w->nid, w->name); 6669 6670 if (depth > 0) { 6671 if (w->ossmask == 0) { 6672 printf("\n"); 6673 return; 6674 } 6675 printf(" [src: %s]", 6676 hdac_audio_ctl_ossmixer_mask2allname( 6677 w->ossmask, buf, sizeof(buf))); 6678 if (w->ossdev >= 0) { 6679 printf("\n"); 6680 return; 6681 } 6682 } 6683 printf("\n"); 6684 6685 for (i = 0; i < w->nconns; i++) { 6686 if (w->connsenable[i] == 0) 6687 continue; 6688 cw = hdac_widget_get(devinfo, w->conns[i]); 6689 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6690 continue; 6691 if (printed == 0) { 6692 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6693 printed = 1; 6694 } 6695 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6696 } 6697 6698} 6699 6700static void 6701hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6702{ 6703 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6704 struct hdac_softc *sc = devinfo->codec->sc; 6705 struct hdac_widget *w; 6706 int i, printed = 0; 6707 6708 if (pdevinfo->play < 0) 6709 return; 6710 6711 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6712 w = hdac_widget_get(devinfo, i); 6713 if (w == NULL || w->enable == 0) 6714 continue; 6715 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6716 continue; 6717 if (w->bindas != sc->chans[pdevinfo->play].as) 6718 continue; 6719 if (printed == 0) { 6720 printed = 1; 6721 device_printf(pdevinfo->dev, "\n"); 6722 device_printf(pdevinfo->dev, "Playback:\n"); 6723 } 6724 device_printf(pdevinfo->dev, "\n"); 6725 hdac_dump_dst_nid(pdevinfo, i, 0); 6726 } 6727} 6728 6729static void 6730hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6731{ 6732 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6733 struct hdac_softc *sc = devinfo->codec->sc; 6734 struct hdac_widget *w; 6735 int i; 6736 int printed = 0; 6737 6738 if (pdevinfo->rec < 0) 6739 return; 6740 6741 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6742 w = hdac_widget_get(devinfo, i); 6743 if (w == NULL || w->enable == 0) 6744 continue; 6745 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6746 continue; 6747 if (w->bindas != sc->chans[pdevinfo->rec].as) 6748 continue; 6749 if (printed == 0) { 6750 printed = 1; 6751 device_printf(pdevinfo->dev, "\n"); 6752 device_printf(pdevinfo->dev, "Record:\n"); 6753 } 6754 device_printf(pdevinfo->dev, "\n"); 6755 hdac_dump_dst_nid(pdevinfo, i, 0); 6756 } 6757} 6758 6759static void 6760hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6761{ 6762 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6763 struct hdac_widget *w; 6764 int i; 6765 int printed = 0; 6766 6767 if (pdevinfo->index != 0) 6768 return; 6769 6770 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6771 w = hdac_widget_get(devinfo, i); 6772 if (w == NULL || w->enable == 0) 6773 continue; 6774 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6775 continue; 6776 if (printed == 0) { 6777 printed = 1; 6778 device_printf(pdevinfo->dev, "\n"); 6779 device_printf(pdevinfo->dev, "Input Mix:\n"); 6780 } 6781 device_printf(pdevinfo->dev, "\n"); 6782 hdac_dump_dst_nid(pdevinfo, i, 0); 6783 } 6784} 6785 6786static void 6787hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6788{ 6789 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6790 nid_t *nids; 6791 int i; 6792 6793 if (pdevinfo->play >= 0) { 6794 i = pdevinfo->play; 6795 device_printf(pdevinfo->dev, "\n"); 6796 device_printf(pdevinfo->dev, "Playback:\n"); 6797 device_printf(pdevinfo->dev, "\n"); 6798 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6799 sc->chans[i].supp_pcm_size_rate); 6800 device_printf(pdevinfo->dev, " DAC:"); 6801 for (nids = sc->chans[i].io; *nids != -1; nids++) 6802 printf(" %d", *nids); 6803 printf("\n"); 6804 } 6805 if (pdevinfo->rec >= 0) { 6806 i = pdevinfo->rec; 6807 device_printf(pdevinfo->dev, "\n"); 6808 device_printf(pdevinfo->dev, "Record:\n"); 6809 device_printf(pdevinfo->dev, "\n"); 6810 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6811 sc->chans[i].supp_pcm_size_rate); 6812 device_printf(pdevinfo->dev, " ADC:"); 6813 for (nids = sc->chans[i].io; *nids != -1; nids++) 6814 printf(" %d", *nids); 6815 printf("\n"); 6816 } 6817} 6818 6819static void 6820hdac_release_resources(struct hdac_softc *sc) 6821{ 6822 int i, j; 6823 6824 if (sc == NULL) 6825 return; 6826 6827 hdac_lock(sc); 6828 sc->polling = 0; 6829 sc->poll_ival = 0; 6830 callout_stop(&sc->poll_hda); 6831 callout_stop(&sc->poll_hdac); 6832 callout_stop(&sc->poll_jack); 6833 hdac_reset(sc, 0); 6834 hdac_unlock(sc); 6835 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6836 callout_drain(&sc->poll_hda); 6837 callout_drain(&sc->poll_hdac); 6838 callout_drain(&sc->poll_jack); 6839 6840 hdac_irq_free(sc); 6841 6842 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6843 if (sc->codecs[i] == NULL) 6844 continue; 6845 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6846 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6847 if (sc->codecs[i]->fgs[j].node_type == 6848 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6849 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6850 M_HDAC); 6851 free(sc->codecs[i]->fgs[j].function.audio.as, 6852 M_HDAC); 6853 free(sc->codecs[i]->fgs[j].function.audio.devs, 6854 M_HDAC); 6855 } 6856 } 6857 free(sc->codecs[i]->fgs, M_HDAC); 6858 free(sc->codecs[i], M_HDAC); 6859 sc->codecs[i] = NULL; 6860 } 6861 6862 hdac_dma_free(sc, &sc->pos_dma); 6863 hdac_dma_free(sc, &sc->rirb_dma); 6864 hdac_dma_free(sc, &sc->corb_dma); 6865 for (i = 0; i < sc->num_chans; i++) { 6866 if (sc->chans[i].blkcnt > 0) 6867 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6868 } 6869 free(sc->chans, M_HDAC); 6870 if (sc->chan_dmat != NULL) { 6871 bus_dma_tag_destroy(sc->chan_dmat); 6872 sc->chan_dmat = NULL; 6873 } 6874 hdac_mem_free(sc); 6875 snd_mtxfree(sc->lock); 6876} 6877 6878/* This function surely going to make its way into upper level someday. */ 6879static void 6880hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6881{ 6882 const char *res = NULL; 6883 int i = 0, j, k, len, inv; 6884 6885 if (on != NULL) 6886 *on = 0; 6887 if (off != NULL) 6888 *off = 0; 6889 if (sc == NULL) 6890 return; 6891 if (resource_string_value(device_get_name(sc->dev), 6892 device_get_unit(sc->dev), "config", &res) != 0) 6893 return; 6894 if (!(res != NULL && strlen(res) > 0)) 6895 return; 6896 HDA_BOOTVERBOSE( 6897 device_printf(sc->dev, "HDA Config:"); 6898 ); 6899 for (;;) { 6900 while (res[i] != '\0' && 6901 (res[i] == ',' || isspace(res[i]) != 0)) 6902 i++; 6903 if (res[i] == '\0') { 6904 HDA_BOOTVERBOSE( 6905 printf("\n"); 6906 ); 6907 return; 6908 } 6909 j = i; 6910 while (res[j] != '\0' && 6911 !(res[j] == ',' || isspace(res[j]) != 0)) 6912 j++; 6913 len = j - i; 6914 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6915 inv = 2; 6916 else 6917 inv = 0; 6918 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6919 if (strncmp(res + i + inv, 6920 hdac_quirks_tab[k].key, len - inv) != 0) 6921 continue; 6922 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6923 break; 6924 HDA_BOOTVERBOSE( 6925 printf(" %s%s", (inv != 0) ? "no" : "", 6926 hdac_quirks_tab[k].key); 6927 ); 6928 if (inv == 0 && on != NULL) 6929 *on |= hdac_quirks_tab[k].value; 6930 else if (inv != 0 && off != NULL) 6931 *off |= hdac_quirks_tab[k].value; 6932 break; 6933 } 6934 i = j; 6935 } 6936} 6937 6938#ifdef SND_DYNSYSCTL 6939static int 6940sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6941{ 6942 struct hdac_softc *sc; 6943 device_t dev; 6944 uint32_t ctl; 6945 int err, val; 6946 6947 dev = oidp->oid_arg1; 6948 sc = device_get_softc(dev); 6949 if (sc == NULL) 6950 return (EINVAL); 6951 hdac_lock(sc); 6952 val = sc->polling; 6953 hdac_unlock(sc); 6954 err = sysctl_handle_int(oidp, &val, 0, req); 6955 6956 if (err != 0 || req->newptr == NULL) 6957 return (err); 6958 if (val < 0 || val > 1) 6959 return (EINVAL); 6960 6961 hdac_lock(sc); 6962 if (val != sc->polling) { 6963 if (val == 0) { 6964 callout_stop(&sc->poll_hda); 6965 callout_stop(&sc->poll_hdac); 6966 hdac_unlock(sc); 6967 callout_drain(&sc->poll_hda); 6968 callout_drain(&sc->poll_hdac); 6969 hdac_lock(sc); 6970 sc->polling = 0; 6971 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6972 ctl |= HDAC_INTCTL_GIE; 6973 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6974 } else { 6975 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6976 ctl &= ~HDAC_INTCTL_GIE; 6977 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6978 hdac_unlock(sc); 6979 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6980 hdac_lock(sc); 6981 sc->polling = 1; 6982 hdac_poll_reinit(sc); 6983 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6984 } 6985 } 6986 hdac_unlock(sc); 6987 6988 return (err); 6989} 6990 6991static int 6992sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6993{ 6994 struct hdac_softc *sc; 6995 device_t dev; 6996 int err, val; 6997 6998 dev = oidp->oid_arg1; 6999 sc = device_get_softc(dev); 7000 if (sc == NULL) 7001 return (EINVAL); 7002 hdac_lock(sc); 7003 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7004 hdac_unlock(sc); 7005 err = sysctl_handle_int(oidp, &val, 0, req); 7006 7007 if (err != 0 || req->newptr == NULL) 7008 return (err); 7009 7010 if (val < 1) 7011 val = 1; 7012 if (val > 5000) 7013 val = 5000; 7014 val = ((uint64_t)val * hz) / 1000; 7015 if (val < 1) 7016 val = 1; 7017 if (val > (hz * 5)) 7018 val = hz * 5; 7019 7020 hdac_lock(sc); 7021 sc->poll_ival = val; 7022 hdac_unlock(sc); 7023 7024 return (err); 7025} 7026 7027static int 7028sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7029{ 7030 struct hdac_softc *sc; 7031 struct hdac_codec *codec; 7032 struct hdac_devinfo *devinfo; 7033 struct hdac_widget *w; 7034 device_t dev; 7035 uint32_t res, pincap, delay; 7036 int codec_index, fg_index; 7037 int i, err, val; 7038 nid_t cad; 7039 7040 dev = oidp->oid_arg1; 7041 sc = device_get_softc(dev); 7042 if (sc == NULL) 7043 return (EINVAL); 7044 val = 0; 7045 err = sysctl_handle_int(oidp, &val, 0, req); 7046 if (err != 0 || req->newptr == NULL || val == 0) 7047 return (err); 7048 7049 /* XXX: Temporary. For debugging. */ 7050 if (val == 100) { 7051 hdac_suspend(dev); 7052 return (0); 7053 } else if (val == 101) { 7054 hdac_resume(dev); 7055 return (0); 7056 } 7057 7058 hdac_lock(sc); 7059 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7060 codec = sc->codecs[codec_index]; 7061 if (codec == NULL) 7062 continue; 7063 cad = codec->cad; 7064 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7065 devinfo = &codec->fgs[fg_index]; 7066 if (devinfo->node_type != 7067 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7068 continue; 7069 7070 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7071 codec_index, devinfo->nid); 7072 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7073 w = hdac_widget_get(devinfo, i); 7074 if (w == NULL || w->type != 7075 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7076 continue; 7077 hdac_dump_pin_config(w, w->wclass.pin.config); 7078 pincap = w->wclass.pin.cap; 7079 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7080 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7081 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7082 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7083 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7084 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7085 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7086 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7087 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7088 delay = 0; 7089 hdac_command(sc, 7090 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7091 do { 7092 res = hdac_command(sc, 7093 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7094 if (res != 0x7fffffff && res != 0xffffffff) 7095 break; 7096 DELAY(10); 7097 } while (++delay < 10000); 7098 } else { 7099 delay = 0; 7100 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7101 w->nid), cad); 7102 } 7103 printf(" Sense: 0x%08x", res); 7104 if (delay > 0) 7105 printf(" delay %dus", delay * 10); 7106 } 7107 printf("\n"); 7108 } 7109 device_printf(dev, 7110 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7111 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7112 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7113 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7114 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7115 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7116 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7117 device_printf(dev, " GPI:"); 7118 res = hdac_command(sc, 7119 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7120 printf(" data=0x%08x", res); 7121 res = hdac_command(sc, 7122 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7123 cad); 7124 printf(" wake=0x%08x", res); 7125 res = hdac_command(sc, 7126 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7127 cad); 7128 printf(" unsol=0x%08x", res); 7129 res = hdac_command(sc, 7130 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7131 printf(" sticky=0x%08x\n", res); 7132 } 7133 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7134 device_printf(dev, " GPO:"); 7135 res = hdac_command(sc, 7136 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7137 printf(" data=0x%08x\n", res); 7138 } 7139 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7140 device_printf(dev, "GPIO:"); 7141 res = hdac_command(sc, 7142 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7143 printf(" data=0x%08x", res); 7144 res = hdac_command(sc, 7145 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7146 printf(" enable=0x%08x", res); 7147 res = hdac_command(sc, 7148 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7149 printf(" direction=0x%08x\n", res); 7150 res = hdac_command(sc, 7151 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7152 device_printf(dev, " wake=0x%08x", res); 7153 res = hdac_command(sc, 7154 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7155 cad); 7156 printf(" unsol=0x%08x", res); 7157 res = hdac_command(sc, 7158 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7159 printf(" sticky=0x%08x\n", res); 7160 } 7161 } 7162 } 7163 hdac_unlock(sc); 7164 return (0); 7165} 7166#endif 7167 7168static void 7169hdac_attach2(void *arg) 7170{ 7171 struct hdac_codec *codec; 7172 struct hdac_softc *sc; 7173 struct hdac_audio_ctl *ctl; 7174 uint32_t quirks_on, quirks_off; 7175 int codec_index, fg_index; 7176 int i, dmaalloc = 0; 7177 struct hdac_devinfo *devinfo; 7178 7179 sc = (struct hdac_softc *)arg; 7180 7181 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7182 7183 HDA_BOOTHVERBOSE( 7184 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7185 quirks_on, quirks_off); 7186 ); 7187 7188 hdac_lock(sc); 7189 7190 /* Remove ourselves from the config hooks */ 7191 if (sc->intrhook.ich_func != NULL) { 7192 config_intrhook_disestablish(&sc->intrhook); 7193 sc->intrhook.ich_func = NULL; 7194 } 7195 7196 /* Start the corb and rirb engines */ 7197 HDA_BOOTHVERBOSE( 7198 device_printf(sc->dev, "Starting CORB Engine...\n"); 7199 ); 7200 hdac_corb_start(sc); 7201 HDA_BOOTHVERBOSE( 7202 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7203 ); 7204 hdac_rirb_start(sc); 7205 7206 HDA_BOOTHVERBOSE( 7207 device_printf(sc->dev, 7208 "Enabling controller interrupt...\n"); 7209 ); 7210 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7211 HDAC_GCTL_UNSOL); 7212 if (sc->polling == 0) { 7213 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7214 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7215 } else { 7216 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7217 } 7218 DELAY(1000); 7219 7220 HDA_BOOTHVERBOSE( 7221 device_printf(sc->dev, 7222 "Scanning HDA codecs ...\n"); 7223 ); 7224 hdac_scan_codecs(sc); 7225 7226 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7227 codec = sc->codecs[codec_index]; 7228 if (codec == NULL) 7229 continue; 7230 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7231 devinfo = &codec->fgs[fg_index]; 7232 HDA_BOOTVERBOSE( 7233 device_printf(sc->dev, "\n"); 7234 device_printf(sc->dev, 7235 "Processing %s FG cad=%d nid=%d...\n", 7236 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7237 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7238 "unknown", 7239 devinfo->codec->cad, devinfo->nid); 7240 ); 7241 if (devinfo->node_type != 7242 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7243 HDA_BOOTHVERBOSE( 7244 device_printf(sc->dev, 7245 "Powering down...\n"); 7246 ); 7247 hdac_command(sc, 7248 HDA_CMD_SET_POWER_STATE(codec->cad, 7249 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7250 codec->cad); 7251 continue; 7252 } 7253 7254 HDA_BOOTHVERBOSE( 7255 device_printf(sc->dev, "Powering up...\n"); 7256 ); 7257 hdac_powerup(devinfo); 7258 HDA_BOOTHVERBOSE( 7259 device_printf(sc->dev, "Parsing audio FG...\n"); 7260 ); 7261 hdac_audio_parse(devinfo); 7262 HDA_BOOTHVERBOSE( 7263 device_printf(sc->dev, "Parsing Ctls...\n"); 7264 ); 7265 hdac_audio_ctl_parse(devinfo); 7266 HDA_BOOTHVERBOSE( 7267 device_printf(sc->dev, "Parsing vendor patch...\n"); 7268 ); 7269 hdac_vendor_patch_parse(devinfo); 7270 devinfo->function.audio.quirks |= quirks_on; 7271 devinfo->function.audio.quirks &= ~quirks_off; 7272 7273 HDA_BOOTHVERBOSE( 7274 device_printf(sc->dev, "Disabling nonaudio...\n"); 7275 ); 7276 hdac_audio_disable_nonaudio(devinfo); 7277 HDA_BOOTHVERBOSE( 7278 device_printf(sc->dev, "Disabling useless...\n"); 7279 ); 7280 hdac_audio_disable_useless(devinfo); 7281 HDA_BOOTVERBOSE( 7282 device_printf(sc->dev, "Patched pins configuration:\n"); 7283 hdac_dump_pin_configs(devinfo); 7284 ); 7285 HDA_BOOTHVERBOSE( 7286 device_printf(sc->dev, "Parsing pin associations...\n"); 7287 ); 7288 hdac_audio_as_parse(devinfo); 7289 HDA_BOOTHVERBOSE( 7290 device_printf(sc->dev, "Building AFG tree...\n"); 7291 ); 7292 hdac_audio_build_tree(devinfo); 7293 HDA_BOOTHVERBOSE( 7294 device_printf(sc->dev, "Disabling unassociated " 7295 "widgets...\n"); 7296 ); 7297 hdac_audio_disable_unas(devinfo); 7298 HDA_BOOTHVERBOSE( 7299 device_printf(sc->dev, "Disabling nonselected " 7300 "inputs...\n"); 7301 ); 7302 hdac_audio_disable_notselected(devinfo); 7303 HDA_BOOTHVERBOSE( 7304 device_printf(sc->dev, "Disabling useless...\n"); 7305 ); 7306 hdac_audio_disable_useless(devinfo); 7307 HDA_BOOTHVERBOSE( 7308 device_printf(sc->dev, "Disabling " 7309 "crossassociatement connections...\n"); 7310 ); 7311 hdac_audio_disable_crossas(devinfo); 7312 HDA_BOOTHVERBOSE( 7313 device_printf(sc->dev, "Disabling useless...\n"); 7314 ); 7315 hdac_audio_disable_useless(devinfo); 7316 HDA_BOOTHVERBOSE( 7317 device_printf(sc->dev, "Binding associations to channels...\n"); 7318 ); 7319 hdac_audio_bind_as(devinfo); 7320 HDA_BOOTHVERBOSE( 7321 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7322 ); 7323 hdac_audio_assign_names(devinfo); 7324 HDA_BOOTHVERBOSE( 7325 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7326 ); 7327 hdac_audio_assign_mixers(devinfo); 7328 HDA_BOOTHVERBOSE( 7329 device_printf(sc->dev, "Preparing pin controls...\n"); 7330 ); 7331 hdac_audio_prepare_pin_ctrl(devinfo); 7332 HDA_BOOTHVERBOSE( 7333 device_printf(sc->dev, "AFG commit...\n"); 7334 ); 7335 hdac_audio_commit(devinfo); 7336 HDA_BOOTHVERBOSE( 7337 device_printf(sc->dev, "Ctls commit...\n"); 7338 ); 7339 hdac_audio_ctl_commit(devinfo); 7340 HDA_BOOTHVERBOSE( 7341 device_printf(sc->dev, "HP switch init...\n"); 7342 ); 7343 hdac_hp_switch_init(devinfo); 7344 7345 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7346 dmaalloc == 0) { 7347 if (hdac_dma_alloc(sc, &sc->pos_dma, 7348 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7349 HDA_BOOTVERBOSE( 7350 device_printf(sc->dev, "Failed to " 7351 "allocate DMA pos buffer " 7352 "(non-fatal)\n"); 7353 ); 7354 } else 7355 dmaalloc = 1; 7356 } 7357 7358 HDA_BOOTHVERBOSE( 7359 device_printf(sc->dev, "Creating PCM devices...\n"); 7360 ); 7361 hdac_create_pcms(devinfo); 7362 7363 HDA_BOOTVERBOSE( 7364 if (devinfo->function.audio.quirks != 0) { 7365 device_printf(sc->dev, "FG config/quirks:"); 7366 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7367 if ((devinfo->function.audio.quirks & 7368 hdac_quirks_tab[i].value) == 7369 hdac_quirks_tab[i].value) 7370 printf(" %s", hdac_quirks_tab[i].key); 7371 } 7372 printf("\n"); 7373 } 7374 7375 device_printf(sc->dev, "\n"); 7376 device_printf(sc->dev, "+-------------------+\n"); 7377 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7378 device_printf(sc->dev, "+-------------------+\n"); 7379 hdac_dump_nodes(devinfo); 7380 ); 7381 7382 HDA_BOOTHVERBOSE( 7383 device_printf(sc->dev, "\n"); 7384 device_printf(sc->dev, "+------------------------+\n"); 7385 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7386 device_printf(sc->dev, "+------------------------+\n"); 7387 device_printf(sc->dev, "\n"); 7388 i = 0; 7389 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7390 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7391 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7392 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7393 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7394 ctl->index); 7395 if (ctl->childwidget != NULL) 7396 printf(" cnid %3d", ctl->childwidget->nid); 7397 else 7398 printf(" "); 7399 printf(" ossmask=0x%08x\n", 7400 ctl->ossmask); 7401 device_printf(sc->dev, 7402 " mute: %d step: %3d size: %3d off: %3d%s\n", 7403 ctl->mute, ctl->step, ctl->size, ctl->offset, 7404 (ctl->enable == 0) ? " [DISABLED]" : 7405 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7406 } 7407 ); 7408 } 7409 } 7410 hdac_unlock(sc); 7411 7412 HDA_BOOTVERBOSE( 7413 device_printf(sc->dev, "\n"); 7414 ); 7415 7416 bus_generic_attach(sc->dev); 7417 7418#ifdef SND_DYNSYSCTL 7419 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7420 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7421 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7422 sysctl_hdac_polling, "I", "Enable polling mode"); 7423 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7424 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7425 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7426 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7427 "Controller/Jack Sense polling interval (1-1000 ms)"); 7428 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7429 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7430 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7431 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7432#endif 7433} 7434 7435/**************************************************************************** 7436 * int hdac_suspend(device_t) 7437 * 7438 * Suspend and power down HDA bus and codecs. 7439 ****************************************************************************/ 7440static int 7441hdac_suspend(device_t dev) 7442{ 7443 struct hdac_softc *sc; 7444 struct hdac_codec *codec; 7445 struct hdac_devinfo *devinfo; 7446 int codec_index, fg_index, i; 7447 7448 HDA_BOOTHVERBOSE( 7449 device_printf(dev, "Suspend...\n"); 7450 ); 7451 7452 sc = device_get_softc(dev); 7453 hdac_lock(sc); 7454 7455 HDA_BOOTHVERBOSE( 7456 device_printf(dev, "Stop streams...\n"); 7457 ); 7458 for (i = 0; i < sc->num_chans; i++) { 7459 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7460 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7461 hdac_channel_stop(sc, &sc->chans[i]); 7462 } 7463 } 7464 7465 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7466 codec = sc->codecs[codec_index]; 7467 if (codec == NULL) 7468 continue; 7469 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7470 devinfo = &codec->fgs[fg_index]; 7471 HDA_BOOTHVERBOSE( 7472 device_printf(dev, 7473 "Power down FG" 7474 " cad=%d nid=%d to the D3 state...\n", 7475 codec->cad, devinfo->nid); 7476 ); 7477 hdac_command(sc, 7478 HDA_CMD_SET_POWER_STATE(codec->cad, 7479 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7480 codec->cad); 7481 } 7482 } 7483 7484 HDA_BOOTHVERBOSE( 7485 device_printf(dev, "Reset controller...\n"); 7486 ); 7487 callout_stop(&sc->poll_hda); 7488 callout_stop(&sc->poll_hdac); 7489 callout_stop(&sc->poll_jack); 7490 hdac_reset(sc, 0); 7491 hdac_unlock(sc); 7492 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7493 callout_drain(&sc->poll_hda); 7494 callout_drain(&sc->poll_hdac); 7495 callout_drain(&sc->poll_jack); 7496 7497 HDA_BOOTHVERBOSE( 7498 device_printf(dev, "Suspend done\n"); 7499 ); 7500 7501 return (0); 7502} 7503 7504/**************************************************************************** 7505 * int hdac_resume(device_t) 7506 * 7507 * Powerup and restore HDA bus and codecs state. 7508 ****************************************************************************/ 7509static int 7510hdac_resume(device_t dev) 7511{ 7512 struct hdac_softc *sc; 7513 struct hdac_codec *codec; 7514 struct hdac_devinfo *devinfo; 7515 int codec_index, fg_index, i; 7516 7517 HDA_BOOTHVERBOSE( 7518 device_printf(dev, "Resume...\n"); 7519 ); 7520 7521 sc = device_get_softc(dev); 7522 hdac_lock(sc); 7523 7524 /* Quiesce everything */ 7525 HDA_BOOTHVERBOSE( 7526 device_printf(dev, "Reset controller...\n"); 7527 ); 7528 hdac_reset(sc, 1); 7529 7530 /* Initialize the CORB and RIRB */ 7531 hdac_corb_init(sc); 7532 hdac_rirb_init(sc); 7533 7534 /* Start the corb and rirb engines */ 7535 HDA_BOOTHVERBOSE( 7536 device_printf(dev, "Starting CORB Engine...\n"); 7537 ); 7538 hdac_corb_start(sc); 7539 HDA_BOOTHVERBOSE( 7540 device_printf(dev, "Starting RIRB Engine...\n"); 7541 ); 7542 hdac_rirb_start(sc); 7543 7544 HDA_BOOTHVERBOSE( 7545 device_printf(dev, 7546 "Enabling controller interrupt...\n"); 7547 ); 7548 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7549 HDAC_GCTL_UNSOL); 7550 if (sc->polling == 0) { 7551 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7552 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7553 } else { 7554 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7555 } 7556 DELAY(1000); 7557 7558 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7559 codec = sc->codecs[codec_index]; 7560 if (codec == NULL) 7561 continue; 7562 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7563 devinfo = &codec->fgs[fg_index]; 7564 if (devinfo->node_type != 7565 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7566 HDA_BOOTHVERBOSE( 7567 device_printf(dev, 7568 "Power down unsupported non-audio FG" 7569 " cad=%d nid=%d to the D3 state...\n", 7570 codec->cad, devinfo->nid); 7571 ); 7572 hdac_command(sc, 7573 HDA_CMD_SET_POWER_STATE(codec->cad, 7574 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7575 codec->cad); 7576 continue; 7577 } 7578 7579 HDA_BOOTHVERBOSE( 7580 device_printf(dev, 7581 "Power up audio FG cad=%d nid=%d...\n", 7582 devinfo->codec->cad, devinfo->nid); 7583 ); 7584 hdac_powerup(devinfo); 7585 HDA_BOOTHVERBOSE( 7586 device_printf(dev, "AFG commit...\n"); 7587 ); 7588 hdac_audio_commit(devinfo); 7589 HDA_BOOTHVERBOSE( 7590 device_printf(dev, "Ctls commit...\n"); 7591 ); 7592 hdac_audio_ctl_commit(devinfo); 7593 HDA_BOOTHVERBOSE( 7594 device_printf(dev, "HP switch init...\n"); 7595 ); 7596 hdac_hp_switch_init(devinfo); 7597 7598 hdac_unlock(sc); 7599 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7600 struct hdac_pcm_devinfo *pdevinfo = 7601 &devinfo->function.audio.devs[i]; 7602 HDA_BOOTHVERBOSE( 7603 device_printf(pdevinfo->dev, 7604 "OSS mixer reinitialization...\n"); 7605 ); 7606 if (mixer_reinit(pdevinfo->dev) == -1) 7607 device_printf(pdevinfo->dev, 7608 "unable to reinitialize the mixer\n"); 7609 } 7610 hdac_lock(sc); 7611 } 7612 } 7613 7614 HDA_BOOTHVERBOSE( 7615 device_printf(dev, "Start streams...\n"); 7616 ); 7617 for (i = 0; i < sc->num_chans; i++) { 7618 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7619 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7620 hdac_channel_start(sc, &sc->chans[i]); 7621 } 7622 } 7623 7624 hdac_unlock(sc); 7625 7626 HDA_BOOTHVERBOSE( 7627 device_printf(dev, "Resume done\n"); 7628 ); 7629 7630 return (0); 7631} 7632/**************************************************************************** 7633 * int hdac_detach(device_t) 7634 * 7635 * Detach and free up resources utilized by the hdac device. 7636 ****************************************************************************/ 7637static int 7638hdac_detach(device_t dev) 7639{ 7640 struct hdac_softc *sc; 7641 device_t *devlist; 7642 int i, devcount, error; 7643 7644 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7645 return (error); 7646 for (i = 0; i < devcount; i++) { 7647 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7648 free(devlist, M_TEMP); 7649 return (error); 7650 } 7651 } 7652 free(devlist, M_TEMP); 7653 7654 sc = device_get_softc(dev); 7655 hdac_release_resources(sc); 7656 7657 return (0); 7658} 7659 7660static int 7661hdac_print_child(device_t dev, device_t child) 7662{ 7663 struct hdac_pcm_devinfo *pdevinfo = 7664 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7665 int retval; 7666 7667 retval = bus_print_child_header(dev, child); 7668 retval += printf(" at cad %d nid %d", 7669 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7670 retval += bus_print_child_footer(dev, child); 7671 7672 return (retval); 7673} 7674 7675static device_method_t hdac_methods[] = { 7676 /* device interface */ 7677 DEVMETHOD(device_probe, hdac_probe), 7678 DEVMETHOD(device_attach, hdac_attach), 7679 DEVMETHOD(device_detach, hdac_detach), 7680 DEVMETHOD(device_suspend, hdac_suspend), 7681 DEVMETHOD(device_resume, hdac_resume), 7682 /* Bus interface */ 7683 DEVMETHOD(bus_print_child, hdac_print_child), 7684 { 0, 0 } 7685}; 7686 7687static driver_t hdac_driver = { 7688 "hdac", 7689 hdac_methods, 7690 sizeof(struct hdac_softc), 7691}; 7692 7693static devclass_t hdac_devclass; 7694 7695DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7696MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7697MODULE_VERSION(snd_hda, 1); 7698 7699static int 7700hdac_pcm_probe(device_t dev) 7701{ 7702 struct hdac_pcm_devinfo *pdevinfo = 7703 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7704 char buf[128]; 7705 7706 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7707 hdac_codec_name(pdevinfo->devinfo->codec), 7708 pdevinfo->index, 7709 pdevinfo->digital?"Digital":"Analog"); 7710 device_set_desc_copy(dev, buf); 7711 return (0); 7712} 7713 7714static int 7715hdac_pcm_attach(device_t dev) 7716{ 7717 struct hdac_pcm_devinfo *pdevinfo = 7718 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7719 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7720 char status[SND_STATUSLEN]; 7721 int i; 7722 7723 pdevinfo->chan_size = pcm_getbuffersize(dev, 7724 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7725 7726 HDA_BOOTVERBOSE( 7727 device_printf(dev, "+--------------------------------------+\n"); 7728 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7729 device_printf(dev, "+--------------------------------------+\n"); 7730 hdac_dump_pcmchannels(pdevinfo); 7731 device_printf(dev, "\n"); 7732 device_printf(dev, "+--------------------------------+\n"); 7733 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7734 device_printf(dev, "+--------------------------------+\n"); 7735 hdac_dump_dac(pdevinfo); 7736 hdac_dump_adc(pdevinfo); 7737 hdac_dump_mix(pdevinfo); 7738 device_printf(dev, "\n"); 7739 device_printf(dev, "+-------------------------+\n"); 7740 device_printf(dev, "| DUMPING Volume Controls |\n"); 7741 device_printf(dev, "+-------------------------+\n"); 7742 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7743 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7744 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7745 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7746 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7747 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7748 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7749 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7750 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7751 hdac_dump_ctls(pdevinfo, NULL, 0); 7752 device_printf(dev, "\n"); 7753 ); 7754 7755 if (resource_int_value(device_get_name(dev), 7756 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7757 i &= HDA_BLK_ALIGN; 7758 if (i < HDA_BLK_MIN) 7759 i = HDA_BLK_MIN; 7760 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7761 i = 0; 7762 while (pdevinfo->chan_blkcnt >> i) 7763 i++; 7764 pdevinfo->chan_blkcnt = 1 << (i - 1); 7765 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7766 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7767 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7768 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7769 } else 7770 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7771 7772 /* 7773 * We don't register interrupt handler with snd_setup_intr 7774 * in pcm device. Mark pcm device as MPSAFE manually. 7775 */ 7776 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7777 7778 HDA_BOOTHVERBOSE( 7779 device_printf(dev, "OSS mixer initialization...\n"); 7780 ); 7781 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7782 device_printf(dev, "Can't register mixer\n"); 7783 7784 HDA_BOOTHVERBOSE( 7785 device_printf(dev, "Registering PCM channels...\n"); 7786 ); 7787 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7788 (pdevinfo->rec >= 0)?1:0) != 0) 7789 device_printf(dev, "Can't register PCM\n"); 7790 7791 pdevinfo->registered++; 7792 7793 if (pdevinfo->play >= 0) 7794 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7795 if (pdevinfo->rec >= 0) 7796 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7797 7798 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7799 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7800 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7801 pcm_setstatus(dev, status); 7802 7803 return (0); 7804} 7805 7806static int 7807hdac_pcm_detach(device_t dev) 7808{ 7809 struct hdac_pcm_devinfo *pdevinfo = 7810 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7811 int err; 7812 7813 if (pdevinfo->registered > 0) { 7814 err = pcm_unregister(dev); 7815 if (err != 0) 7816 return (err); 7817 } 7818 7819 return (0); 7820} 7821 7822static device_method_t hdac_pcm_methods[] = { 7823 /* device interface */ 7824 DEVMETHOD(device_probe, hdac_pcm_probe), 7825 DEVMETHOD(device_attach, hdac_pcm_attach), 7826 DEVMETHOD(device_detach, hdac_pcm_detach), 7827 { 0, 0 } 7828}; 7829 7830static driver_t hdac_pcm_driver = { 7831 "pcm", 7832 hdac_pcm_methods, 7833 PCM_SOFTC_SIZE, 7834}; 7835 7836DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7837 7838