hdac.c revision 186146
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20081123_0118" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 186146 2008-12-16 00:08:51Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 166 167/* ATI */ 168#define ATI_VENDORID 0x1002 169#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 170#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 171#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 172 173/* VIA */ 174#define VIA_VENDORID 0x1106 175#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 176#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 177 178/* SiS */ 179#define SIS_VENDORID 0x1039 180#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 181#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 182 183/* OEM/subvendors */ 184 185/* Intel */ 186#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 187 188/* HP/Compaq */ 189#define HP_VENDORID 0x103c 190#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 191#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 192#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 193#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 194#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 195#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 196#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 197#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 198#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 199#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 200/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 201#define HP_NX6325_SUBVENDORX 0x103c30b0 202 203/* Dell */ 204#define DELL_VENDORID 0x1028 205#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 206#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 207#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 208#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 209#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 210#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 211#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 212#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 213 214/* Clevo */ 215#define CLEVO_VENDORID 0x1558 216#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 217#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 218 219/* Acer */ 220#define ACER_VENDORID 0x1025 221#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 222#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 223#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 224#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 225#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 226#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 227#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 228 229/* Asus */ 230#define ASUS_VENDORID 0x1043 231#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 232#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 233#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 234#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 235#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 236#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 237#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 238#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 239#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 240#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 241#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 242#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 243#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 244#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 245#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 246#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 247 248/* IBM / Lenovo */ 249#define IBM_VENDORID 0x1014 250#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 251#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 252 253/* Lenovo */ 254#define LENOVO_VENDORID 0x17aa 255#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 256#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 257#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 258#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 259 260/* Samsung */ 261#define SAMSUNG_VENDORID 0x144d 262#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 263#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 264 265/* Medion ? */ 266#define MEDION_VENDORID 0x161f 267#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 268#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 269 270/* Apple Computer Inc. */ 271#define APPLE_VENDORID 0x106b 272#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 273 274/* Sony */ 275#define SONY_VENDORID 0x104d 276#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 277#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 278 279/* 280 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 281 * instead of their own, which is beyond my comprehension 282 * (see HDA_CODEC_STAC9221 below). 283 */ 284#define APPLE_INTEL_MAC 0x76808384 285 286/* LG Electronics */ 287#define LG_VENDORID 0x1854 288#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 289#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 290 291/* Fujitsu Siemens */ 292#define FS_VENDORID 0x1734 293#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 294#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 295#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 296 297/* Fujitsu Limited */ 298#define FL_VENDORID 0x10cf 299#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 300#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 301#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 302 303/* Toshiba */ 304#define TOSHIBA_VENDORID 0x1179 305#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 306#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 307#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 308 309/* Micro-Star International (MSI) */ 310#define MSI_VENDORID 0x1462 311#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 312#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 313#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 314 315/* Giga-Byte Technology */ 316#define GB_VENDORID 0x1458 317#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 318#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 319 320/* Uniwill ? */ 321#define UNIWILL_VENDORID 0x1584 322#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 323#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 324 325 326/* Misc constants.. */ 327#define HDA_AMP_VOL_DEFAULT (-1) 328#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 329#define HDA_AMP_MUTE_NONE (0) 330#define HDA_AMP_MUTE_LEFT (1 << 0) 331#define HDA_AMP_MUTE_RIGHT (1 << 1) 332#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 333 334#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 335#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 336 337#define HDA_ADC_MONITOR (1 << 0) 338 339#define HDA_CTL_OUT 1 340#define HDA_CTL_IN 2 341 342#define HDA_GPIO_MAX 8 343/* 0 - 7 = GPIO , 8 = Flush */ 344#define HDA_QUIRK_GPIO0 (1 << 0) 345#define HDA_QUIRK_GPIO1 (1 << 1) 346#define HDA_QUIRK_GPIO2 (1 << 2) 347#define HDA_QUIRK_GPIO3 (1 << 3) 348#define HDA_QUIRK_GPIO4 (1 << 4) 349#define HDA_QUIRK_GPIO5 (1 << 5) 350#define HDA_QUIRK_GPIO6 (1 << 6) 351#define HDA_QUIRK_GPIO7 (1 << 7) 352#define HDA_QUIRK_GPIOFLUSH (1 << 8) 353 354/* 9 - 25 = anything else */ 355#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 356#define HDA_QUIRK_FIXEDRATE (1 << 10) 357#define HDA_QUIRK_FORCESTEREO (1 << 11) 358#define HDA_QUIRK_EAPDINV (1 << 12) 359#define HDA_QUIRK_DMAPOS (1 << 13) 360#define HDA_QUIRK_SENSEINV (1 << 14) 361 362/* 26 - 31 = vrefs */ 363#define HDA_QUIRK_IVREF50 (1 << 26) 364#define HDA_QUIRK_IVREF80 (1 << 27) 365#define HDA_QUIRK_IVREF100 (1 << 28) 366#define HDA_QUIRK_OVREF50 (1 << 29) 367#define HDA_QUIRK_OVREF80 (1 << 30) 368#define HDA_QUIRK_OVREF100 (1 << 31) 369 370#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 371 HDA_QUIRK_IVREF100) 372#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 373 HDA_QUIRK_OVREF100) 374#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 375 376#if __FreeBSD_version < 600000 377#define taskqueue_drain(...) 378#endif 379 380static const struct { 381 char *key; 382 uint32_t value; 383} hdac_quirks_tab[] = { 384 { "gpio0", HDA_QUIRK_GPIO0 }, 385 { "gpio1", HDA_QUIRK_GPIO1 }, 386 { "gpio2", HDA_QUIRK_GPIO2 }, 387 { "gpio3", HDA_QUIRK_GPIO3 }, 388 { "gpio4", HDA_QUIRK_GPIO4 }, 389 { "gpio5", HDA_QUIRK_GPIO5 }, 390 { "gpio6", HDA_QUIRK_GPIO6 }, 391 { "gpio7", HDA_QUIRK_GPIO7 }, 392 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 393 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 394 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 395 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 396 { "eapdinv", HDA_QUIRK_EAPDINV }, 397 { "dmapos", HDA_QUIRK_DMAPOS }, 398 { "senseinv", HDA_QUIRK_SENSEINV }, 399 { "ivref50", HDA_QUIRK_IVREF50 }, 400 { "ivref80", HDA_QUIRK_IVREF80 }, 401 { "ivref100", HDA_QUIRK_IVREF100 }, 402 { "ovref50", HDA_QUIRK_OVREF50 }, 403 { "ovref80", HDA_QUIRK_OVREF80 }, 404 { "ovref100", HDA_QUIRK_OVREF100 }, 405 { "ivref", HDA_QUIRK_IVREF }, 406 { "ovref", HDA_QUIRK_OVREF }, 407 { "vref", HDA_QUIRK_VREF }, 408}; 409#define HDAC_QUIRKS_TAB_LEN \ 410 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 411 412#define HDA_BDL_MIN 2 413#define HDA_BDL_MAX 256 414#define HDA_BDL_DEFAULT HDA_BDL_MIN 415 416#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 417#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 418 419#define HDA_BUFSZ_MIN 4096 420#define HDA_BUFSZ_MAX 65536 421#define HDA_BUFSZ_DEFAULT 16384 422 423#define HDA_PARSE_MAXDEPTH 10 424 425#define HDAC_UNSOLTAG_EVENT_HP 0x00 426 427MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 428 429const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 430 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 431 "White", "Other"}; 432 433const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 434 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 435 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 436 437const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 438 439/* Default */ 440static uint32_t hdac_fmt[] = { 441 AFMT_STEREO | AFMT_S16_LE, 442 0 443}; 444 445static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 446 447static const struct { 448 uint32_t model; 449 char *desc; 450} hdac_devices[] = { 451 { HDA_INTEL_82801F, "Intel 82801F" }, 452 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 453 { HDA_INTEL_82801G, "Intel 82801G" }, 454 { HDA_INTEL_82801H, "Intel 82801H" }, 455 { HDA_INTEL_82801I, "Intel 82801I" }, 456 { HDA_INTEL_82801J, "Intel 82801J" }, 457 { HDA_INTEL_SCH, "Intel SCH" }, 458 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 459 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 460 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 461 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 462 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 463 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 464 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 465 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 466 { HDA_ATI_SB450, "ATI SB450" }, 467 { HDA_ATI_SB600, "ATI SB600" }, 468 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 469 { HDA_SIS_966, "SiS 966" }, 470 /* Unknown */ 471 { HDA_INTEL_ALL, "Intel (Unknown)" }, 472 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 473 { HDA_ATI_ALL, "ATI (Unknown)" }, 474 { HDA_VIA_ALL, "VIA (Unknown)" }, 475 { HDA_SIS_ALL, "SiS (Unknown)" }, 476}; 477#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 478 479static const struct { 480 uint16_t vendor; 481 uint8_t reg; 482 uint8_t mask; 483 uint8_t enable; 484} hdac_pcie_snoop[] = { 485 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 486 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 487 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 488}; 489#define HDAC_PCIESNOOP_LEN \ 490 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 491 492static const struct { 493 uint32_t rate; 494 int valid; 495 uint16_t base; 496 uint16_t mul; 497 uint16_t div; 498} hda_rate_tab[] = { 499 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 500 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 501 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 502 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 503 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 504 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 505 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 506 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 507 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 508 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 509 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 510 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 511 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 512 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 513 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 514 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 515 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 516 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 517 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 518 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 519 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 520 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 521 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 522 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 523 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 524 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 525 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 526 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 527 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 528 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 529 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 530 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 531 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 532 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 533 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 534}; 535#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 536 537/* All codecs you can eat... */ 538#define HDA_CODEC_CONSTRUCT(vendor, id) \ 539 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 540 541/* Realtek */ 542#define REALTEK_VENDORID 0x10ec 543#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 544#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 545#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 546#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 547#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 548#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 549#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 550#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 551#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 552#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 553#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 554#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 555#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 556#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 557#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 558#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 559#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 560#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 561 562/* Analog Devices */ 563#define ANALOGDEVICES_VENDORID 0x11d4 564#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 565#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 566#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 567#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 568#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 569#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 570#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 571 572/* CMedia */ 573#define CMEDIA_VENDORID 0x434d 574#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 575#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 576 577/* Sigmatel */ 578#define SIGMATEL_VENDORID 0x8384 579#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 580#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 581#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 582#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 583#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 584#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 585#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 586#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 587#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 588#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 589#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 590#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 591#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 592#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 593#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 594#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 595#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 596#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 597#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 598#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 599#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 600#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 601#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 602#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 603#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 604#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 605#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 606#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 607#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 608#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 609#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 610#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 611#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 612#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 613#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 614#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 615#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 616#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 617#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 618#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 619 620/* IDT */ 621#define IDT_VENDORID 0x111d 622#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 623#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 624#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 625#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 626#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 627#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 628#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 629#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 630#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 631#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 632#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 633#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 634#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 635 636/* Silicon Image */ 637#define SII_VENDORID 0x1095 638#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 639#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 640 641/* Lucent/Agere */ 642#define AGERE_VENDORID 0x11c1 643#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 644 645/* 646 * Conexant 647 * 648 * Ok, the truth is, I don't have any idea at all whether 649 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 650 * place that tell me it is "Venice" is from its Windows driver INF. 651 * 652 * Venice - CX????? 653 * Waikiki - CX20551-22 654 */ 655#define CONEXANT_VENDORID 0x14f1 656#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 657#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 658#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 659 660/* VIA */ 661#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 662#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 663#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 664#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 665#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 666#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 667#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 668#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 669#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 670#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 671#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 672#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 673#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 674#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 675#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 676#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 677#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 678#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 679#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 680#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 681#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 682 683/* ATI */ 684#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 685#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 686#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 687#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 688#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 689 690/* NVIDIA */ 691#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 692 693/* INTEL */ 694#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 695 696/* Codecs */ 697static const struct { 698 uint32_t id; 699 char *name; 700} hdac_codecs[] = { 701 { HDA_CODEC_ALC260, "Realtek ALC260" }, 702 { HDA_CODEC_ALC262, "Realtek ALC262" }, 703 { HDA_CODEC_ALC267, "Realtek ALC267" }, 704 { HDA_CODEC_ALC268, "Realtek ALC268" }, 705 { HDA_CODEC_ALC269, "Realtek ALC269" }, 706 { HDA_CODEC_ALC272, "Realtek ALC272" }, 707 { HDA_CODEC_ALC660, "Realtek ALC660" }, 708 { HDA_CODEC_ALC662, "Realtek ALC662" }, 709 { HDA_CODEC_ALC663, "Realtek ALC663" }, 710 { HDA_CODEC_ALC861, "Realtek ALC861" }, 711 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 712 { HDA_CODEC_ALC880, "Realtek ALC880" }, 713 { HDA_CODEC_ALC882, "Realtek ALC882" }, 714 { HDA_CODEC_ALC883, "Realtek ALC883" }, 715 { HDA_CODEC_ALC885, "Realtek ALC885" }, 716 { HDA_CODEC_ALC888, "Realtek ALC888" }, 717 { HDA_CODEC_ALC889, "Realtek ALC889" }, 718 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 719 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 720 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 721 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 722 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 723 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 724 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 725 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 726 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 727 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 728 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 729 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 730 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 731 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 732 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 733 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 734 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 735 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 736 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 737 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 738 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 739 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 740 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 741 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 742 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 743 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 744 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 745 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 746 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 747 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 748 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 749 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 750 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 751 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 752 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 753 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 754 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 755 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 756 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 757 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 758 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 759 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 760 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 761 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 762 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 763 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 764 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 765 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 766 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 767 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 768 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 769 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 770 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 771 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 772 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 773 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 774 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 775 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 776 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 777 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 778 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 779 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 780 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 781 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 782 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 783 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 784 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 785 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 786 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 787 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 788 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 789 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 790 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 791 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 792 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 793 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 794 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 795 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 796 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 797 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 798 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 799 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 800 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 801 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 802 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 803 /* Unknown codec */ 804 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 805 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 806 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 807 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 808 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 809 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 810 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 811 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 812 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 813 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 814 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 815 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 816}; 817#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 818 819 820/**************************************************************************** 821 * Function prototypes 822 ****************************************************************************/ 823static void hdac_intr_handler(void *); 824static int hdac_reset(struct hdac_softc *, int); 825static int hdac_get_capabilities(struct hdac_softc *); 826static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 827static int hdac_dma_alloc(struct hdac_softc *, 828 struct hdac_dma *, bus_size_t); 829static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 830static int hdac_mem_alloc(struct hdac_softc *); 831static void hdac_mem_free(struct hdac_softc *); 832static int hdac_irq_alloc(struct hdac_softc *); 833static void hdac_irq_free(struct hdac_softc *); 834static void hdac_corb_init(struct hdac_softc *); 835static void hdac_rirb_init(struct hdac_softc *); 836static void hdac_corb_start(struct hdac_softc *); 837static void hdac_rirb_start(struct hdac_softc *); 838static void hdac_scan_codecs(struct hdac_softc *); 839static void hdac_probe_codec(struct hdac_codec *); 840static void hdac_probe_function(struct hdac_codec *, nid_t); 841static int hdac_pcmchannel_setup(struct hdac_chan *); 842 843static void hdac_attach2(void *); 844 845static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 846 uint32_t, int); 847static void hdac_command_send_internal(struct hdac_softc *, 848 struct hdac_command_list *, int); 849 850static int hdac_probe(device_t); 851static int hdac_attach(device_t); 852static int hdac_detach(device_t); 853static int hdac_suspend(device_t); 854static int hdac_resume(device_t); 855static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 856static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 857 uint32_t, int, int); 858static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 859 nid_t, int, int, int); 860static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 861 nid_t, nid_t, int, int, int, int, int, int); 862static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 863 864static int hdac_rirb_flush(struct hdac_softc *sc); 865static int hdac_unsolq_flush(struct hdac_softc *sc); 866 867static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 868 869#define hdac_command(a1, a2, a3) \ 870 hdac_command_sendone_internal(a1, a2, a3) 871 872#define hdac_codec_id(c) \ 873 ((uint32_t)((c == NULL) ? 0x00000000 : \ 874 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 875 ((uint32_t)(c)->device_id & 0x0000ffff)))) 876 877static char * 878hdac_codec_name(struct hdac_codec *codec) 879{ 880 uint32_t id; 881 int i; 882 883 id = hdac_codec_id(codec); 884 885 for (i = 0; i < HDAC_CODECS_LEN; i++) { 886 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 887 return (hdac_codecs[i].name); 888 } 889 890 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 891} 892 893static char * 894hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 895{ 896 static char *ossname[] = SOUND_DEVICE_NAMES; 897 int i, first = 1; 898 899 bzero(buf, len); 900 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 901 if (mask & (1 << i)) { 902 if (first == 0) 903 strlcat(buf, ", ", len); 904 strlcat(buf, ossname[i], len); 905 first = 0; 906 } 907 } 908 return (buf); 909} 910 911static struct hdac_audio_ctl * 912hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 913{ 914 if (devinfo == NULL || 915 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 916 index == NULL || devinfo->function.audio.ctl == NULL || 917 devinfo->function.audio.ctlcnt < 1 || 918 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 919 return (NULL); 920 return (&devinfo->function.audio.ctl[(*index)++]); 921} 922 923static struct hdac_audio_ctl * 924hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 925 int index, int cnt) 926{ 927 struct hdac_audio_ctl *ctl; 928 int i, found = 0; 929 930 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 931 return (NULL); 932 933 i = 0; 934 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 935 if (ctl->enable == 0) 936 continue; 937 if (ctl->widget->nid != nid) 938 continue; 939 if (dir && ctl->ndir != dir) 940 continue; 941 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 942 ctl->dir == ctl->ndir && ctl->index != index) 943 continue; 944 found++; 945 if (found == cnt || cnt <= 0) 946 return (ctl); 947 } 948 949 return (NULL); 950} 951 952/* 953 * Jack detection (Speaker/HP redirection) event handler. 954 */ 955static void 956hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 957{ 958 struct hdac_audio_as *as; 959 struct hdac_softc *sc; 960 struct hdac_widget *w; 961 struct hdac_audio_ctl *ctl; 962 uint32_t val, res; 963 int i, j; 964 nid_t cad; 965 966 if (devinfo == NULL || devinfo->codec == NULL || 967 devinfo->codec->sc == NULL) 968 return; 969 970 sc = devinfo->codec->sc; 971 cad = devinfo->codec->cad; 972 as = devinfo->function.audio.as; 973 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 974 if (as[i].hpredir < 0) 975 continue; 976 977 w = hdac_widget_get(devinfo, as[i].pins[15]); 978 if (w == NULL || w->enable == 0 || w->type != 979 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 980 continue; 981 982 res = hdac_command(sc, 983 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 984 985 HDA_BOOTVERBOSE( 986 device_printf(sc->dev, 987 "Pin sense: nid=%d res=0x%08x\n", 988 as[i].pins[15], res); 989 ); 990 991 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 992 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 993 res ^= 1; 994 995 /* (Un)Mute headphone pin. */ 996 ctl = hdac_audio_ctl_amp_get(devinfo, 997 as[i].pins[15], HDA_CTL_IN, -1, 1); 998 if (ctl != NULL && ctl->mute) { 999 /* If pin has muter - use it. */ 1000 val = (res != 0) ? 0 : 1; 1001 if (val != ctl->forcemute) { 1002 ctl->forcemute = val; 1003 hdac_audio_ctl_amp_set(ctl, 1004 HDA_AMP_MUTE_DEFAULT, 1005 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1006 } 1007 } else { 1008 /* If there is no muter - disable pin output. */ 1009 w = hdac_widget_get(devinfo, as[i].pins[15]); 1010 if (w != NULL && w->type == 1011 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1012 if (res != 0) 1013 val = w->wclass.pin.ctrl | 1014 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1015 else 1016 val = w->wclass.pin.ctrl & 1017 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1018 if (val != w->wclass.pin.ctrl) { 1019 w->wclass.pin.ctrl = val; 1020 hdac_command(sc, 1021 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1022 w->nid, w->wclass.pin.ctrl), cad); 1023 } 1024 } 1025 } 1026 /* (Un)Mute other pins. */ 1027 for (j = 0; j < 15; j++) { 1028 if (as[i].pins[j] <= 0) 1029 continue; 1030 ctl = hdac_audio_ctl_amp_get(devinfo, 1031 as[i].pins[j], HDA_CTL_IN, -1, 1); 1032 if (ctl != NULL && ctl->mute) { 1033 /* If pin has muter - use it. */ 1034 val = (res != 0) ? 1 : 0; 1035 if (val == ctl->forcemute) 1036 continue; 1037 ctl->forcemute = val; 1038 hdac_audio_ctl_amp_set(ctl, 1039 HDA_AMP_MUTE_DEFAULT, 1040 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1041 continue; 1042 } 1043 /* If there is no muter - disable pin output. */ 1044 w = hdac_widget_get(devinfo, as[i].pins[j]); 1045 if (w != NULL && w->type == 1046 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1047 if (res != 0) 1048 val = w->wclass.pin.ctrl & 1049 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1050 else 1051 val = w->wclass.pin.ctrl | 1052 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1053 if (val != w->wclass.pin.ctrl) { 1054 w->wclass.pin.ctrl = val; 1055 hdac_command(sc, 1056 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1057 w->nid, w->wclass.pin.ctrl), cad); 1058 } 1059 } 1060 } 1061 } 1062} 1063 1064/* 1065 * Callback for poll based jack detection. 1066 */ 1067static void 1068hdac_jack_poll_callback(void *arg) 1069{ 1070 struct hdac_devinfo *devinfo = arg; 1071 struct hdac_softc *sc; 1072 1073 if (devinfo == NULL || devinfo->codec == NULL || 1074 devinfo->codec->sc == NULL) 1075 return; 1076 sc = devinfo->codec->sc; 1077 hdac_lock(sc); 1078 if (sc->poll_ival == 0) { 1079 hdac_unlock(sc); 1080 return; 1081 } 1082 hdac_hp_switch_handler(devinfo); 1083 callout_reset(&sc->poll_jack, sc->poll_ival, 1084 hdac_jack_poll_callback, devinfo); 1085 hdac_unlock(sc); 1086} 1087 1088/* 1089 * Jack detection initializer. 1090 */ 1091static void 1092hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1093{ 1094 struct hdac_softc *sc = devinfo->codec->sc; 1095 struct hdac_audio_as *as = devinfo->function.audio.as; 1096 struct hdac_widget *w; 1097 uint32_t id; 1098 int i, enable = 0, poll = 0; 1099 nid_t cad; 1100 1101 id = hdac_codec_id(devinfo->codec); 1102 cad = devinfo->codec->cad; 1103 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1104 if (as[i].hpredir < 0) 1105 continue; 1106 1107 w = hdac_widget_get(devinfo, as[i].pins[15]); 1108 if (w == NULL || w->enable == 0 || w->type != 1109 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1110 continue; 1111 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1112 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1113 device_printf(sc->dev, 1114 "No jack detection support at pin %d\n", 1115 as[i].pins[15]); 1116 continue; 1117 } 1118 enable = 1; 1119 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1120 hdac_command(sc, 1121 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1122 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1123 HDAC_UNSOLTAG_EVENT_HP), cad); 1124 } else 1125 poll = 1; 1126 HDA_BOOTVERBOSE( 1127 device_printf(sc->dev, 1128 "Enabling headphone/speaker " 1129 "audio routing switching:\n"); 1130 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1131 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1132 ); 1133 } 1134 if (enable) { 1135 hdac_hp_switch_handler(devinfo); 1136 if (poll) { 1137 callout_reset(&sc->poll_jack, 1, 1138 hdac_jack_poll_callback, devinfo); 1139 } 1140 } 1141} 1142 1143/* 1144 * Unsolicited messages handler. 1145 */ 1146static void 1147hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1148{ 1149 struct hdac_softc *sc; 1150 struct hdac_devinfo *devinfo = NULL; 1151 int i; 1152 1153 if (codec == NULL || codec->sc == NULL) 1154 return; 1155 1156 sc = codec->sc; 1157 1158 HDA_BOOTVERBOSE( 1159 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1160 ); 1161 1162 for (i = 0; i < codec->num_fgs; i++) { 1163 if (codec->fgs[i].node_type == 1164 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1165 devinfo = &codec->fgs[i]; 1166 break; 1167 } 1168 } 1169 1170 if (devinfo == NULL) 1171 return; 1172 1173 switch (tag) { 1174 case HDAC_UNSOLTAG_EVENT_HP: 1175 hdac_hp_switch_handler(devinfo); 1176 break; 1177 default: 1178 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1179 break; 1180 } 1181} 1182 1183static int 1184hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1185{ 1186 /* XXX to be removed */ 1187#ifdef HDAC_INTR_EXTRA 1188 uint32_t res; 1189#endif 1190 1191 if (!(ch->flags & HDAC_CHN_RUNNING)) 1192 return (0); 1193 1194 /* XXX to be removed */ 1195#ifdef HDAC_INTR_EXTRA 1196 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1197#endif 1198 1199 /* XXX to be removed */ 1200#ifdef HDAC_INTR_EXTRA 1201 HDA_BOOTVERBOSE( 1202 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1203 device_printf(ch->pdevinfo->dev, 1204 "PCMDIR_%s intr triggered beyond stream boundary:" 1205 "%08x\n", 1206 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1207 ); 1208#endif 1209 1210 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1211 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1212 1213 /* XXX to be removed */ 1214#ifdef HDAC_INTR_EXTRA 1215 if (res & HDAC_SDSTS_BCIS) { 1216#endif 1217 return (1); 1218 /* XXX to be removed */ 1219#ifdef HDAC_INTR_EXTRA 1220 } 1221#endif 1222 1223 return (0); 1224} 1225 1226/**************************************************************************** 1227 * void hdac_intr_handler(void *) 1228 * 1229 * Interrupt handler. Processes interrupts received from the hdac. 1230 ****************************************************************************/ 1231static void 1232hdac_intr_handler(void *context) 1233{ 1234 struct hdac_softc *sc; 1235 uint32_t intsts; 1236 uint8_t rirbsts; 1237 struct hdac_rirb *rirb_base; 1238 uint32_t trigger; 1239 int i; 1240 1241 sc = (struct hdac_softc *)context; 1242 1243 hdac_lock(sc); 1244 if (sc->polling != 0) { 1245 hdac_unlock(sc); 1246 return; 1247 } 1248 1249 /* Do we have anything to do? */ 1250 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1251 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1252 hdac_unlock(sc); 1253 return; 1254 } 1255 1256 trigger = 0; 1257 1258 /* Was this a controller interrupt? */ 1259 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1260 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1261 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1262 /* Get as many responses that we can */ 1263 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1264 HDAC_WRITE_1(&sc->mem, 1265 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1266 if (hdac_rirb_flush(sc) != 0) 1267 trigger |= HDAC_TRIGGER_UNSOL; 1268 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1269 } 1270 /* XXX to be removed */ 1271 /* Clear interrupt and exit */ 1272#ifdef HDAC_INTR_EXTRA 1273 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1274#endif 1275 } 1276 1277 if (intsts & HDAC_INTSTS_SIS_MASK) { 1278 for (i = 0; i < sc->num_chans; i++) { 1279 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1280 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1281 trigger |= (1 << i); 1282 } 1283 /* XXX to be removed */ 1284#ifdef HDAC_INTR_EXTRA 1285 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1286 HDAC_INTSTS_SIS_MASK); 1287#endif 1288 } 1289 1290 hdac_unlock(sc); 1291 1292 for (i = 0; i < sc->num_chans; i++) { 1293 if (trigger & (1 << i)) 1294 chn_intr(sc->chans[i].c); 1295 } 1296 if (trigger & HDAC_TRIGGER_UNSOL) 1297 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1298} 1299 1300/**************************************************************************** 1301 * int hdac_reset(hdac_softc *, int) 1302 * 1303 * Reset the hdac to a quiescent and known state. 1304 ****************************************************************************/ 1305static int 1306hdac_reset(struct hdac_softc *sc, int wakeup) 1307{ 1308 uint32_t gctl; 1309 int count, i; 1310 1311 /* 1312 * Stop all Streams DMA engine 1313 */ 1314 for (i = 0; i < sc->num_iss; i++) 1315 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1316 for (i = 0; i < sc->num_oss; i++) 1317 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1318 for (i = 0; i < sc->num_bss; i++) 1319 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1320 1321 /* 1322 * Stop Control DMA engines. 1323 */ 1324 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1325 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1326 1327 /* 1328 * Reset DMA position buffer. 1329 */ 1330 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1331 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1332 1333 /* 1334 * Reset the controller. The reset must remain asserted for 1335 * a minimum of 100us. 1336 */ 1337 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1338 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1339 count = 10000; 1340 do { 1341 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1342 if (!(gctl & HDAC_GCTL_CRST)) 1343 break; 1344 DELAY(10); 1345 } while (--count); 1346 if (gctl & HDAC_GCTL_CRST) { 1347 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1348 return (ENXIO); 1349 } 1350 1351 /* If wakeup is not requested - leave the controller in reset state. */ 1352 if (!wakeup) 1353 return (0); 1354 1355 DELAY(100); 1356 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1357 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1358 count = 10000; 1359 do { 1360 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1361 if (gctl & HDAC_GCTL_CRST) 1362 break; 1363 DELAY(10); 1364 } while (--count); 1365 if (!(gctl & HDAC_GCTL_CRST)) { 1366 device_printf(sc->dev, "Device stuck in reset\n"); 1367 return (ENXIO); 1368 } 1369 1370 /* 1371 * Wait for codecs to finish their own reset sequence. The delay here 1372 * should be of 250us but for some reasons, on it's not enough on my 1373 * computer. Let's use twice as much as necessary to make sure that 1374 * it's reset properly. 1375 */ 1376 DELAY(1000); 1377 1378 return (0); 1379} 1380 1381 1382/**************************************************************************** 1383 * int hdac_get_capabilities(struct hdac_softc *); 1384 * 1385 * Retreive the general capabilities of the hdac; 1386 * Number of Input Streams 1387 * Number of Output Streams 1388 * Number of bidirectional Streams 1389 * 64bit ready 1390 * CORB and RIRB sizes 1391 ****************************************************************************/ 1392static int 1393hdac_get_capabilities(struct hdac_softc *sc) 1394{ 1395 uint16_t gcap; 1396 uint8_t corbsize, rirbsize; 1397 1398 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1399 sc->num_iss = HDAC_GCAP_ISS(gcap); 1400 sc->num_oss = HDAC_GCAP_OSS(gcap); 1401 sc->num_bss = HDAC_GCAP_BSS(gcap); 1402 1403 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1404 1405 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1406 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1407 HDAC_CORBSIZE_CORBSZCAP_256) 1408 sc->corb_size = 256; 1409 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1410 HDAC_CORBSIZE_CORBSZCAP_16) 1411 sc->corb_size = 16; 1412 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1413 HDAC_CORBSIZE_CORBSZCAP_2) 1414 sc->corb_size = 2; 1415 else { 1416 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1417 __func__, corbsize); 1418 return (ENXIO); 1419 } 1420 1421 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1422 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1423 HDAC_RIRBSIZE_RIRBSZCAP_256) 1424 sc->rirb_size = 256; 1425 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1426 HDAC_RIRBSIZE_RIRBSZCAP_16) 1427 sc->rirb_size = 16; 1428 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1429 HDAC_RIRBSIZE_RIRBSZCAP_2) 1430 sc->rirb_size = 2; 1431 else { 1432 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1433 __func__, rirbsize); 1434 return (ENXIO); 1435 } 1436 1437 HDA_BOOTHVERBOSE( 1438 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1439 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1440 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1441 sc->num_iss, sc->num_oss, sc->num_bss); 1442 ); 1443 1444 return (0); 1445} 1446 1447 1448/**************************************************************************** 1449 * void hdac_dma_cb 1450 * 1451 * This function is called by bus_dmamap_load when the mapping has been 1452 * established. We just record the physical address of the mapping into 1453 * the struct hdac_dma passed in. 1454 ****************************************************************************/ 1455static void 1456hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1457{ 1458 struct hdac_dma *dma; 1459 1460 if (error == 0) { 1461 dma = (struct hdac_dma *)callback_arg; 1462 dma->dma_paddr = segs[0].ds_addr; 1463 } 1464} 1465 1466 1467/**************************************************************************** 1468 * int hdac_dma_alloc 1469 * 1470 * This function allocate and setup a dma region (struct hdac_dma). 1471 * It must be freed by a corresponding hdac_dma_free. 1472 ****************************************************************************/ 1473static int 1474hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1475{ 1476 bus_size_t roundsz; 1477 int result; 1478 int lowaddr; 1479 1480 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1481 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1482 BUS_SPACE_MAXADDR_32BIT; 1483 bzero(dma, sizeof(*dma)); 1484 1485 /* 1486 * Create a DMA tag 1487 */ 1488 result = bus_dma_tag_create(NULL, /* parent */ 1489 HDAC_DMA_ALIGNMENT, /* alignment */ 1490 0, /* boundary */ 1491 lowaddr, /* lowaddr */ 1492 BUS_SPACE_MAXADDR, /* highaddr */ 1493 NULL, /* filtfunc */ 1494 NULL, /* fistfuncarg */ 1495 roundsz, /* maxsize */ 1496 1, /* nsegments */ 1497 roundsz, /* maxsegsz */ 1498 0, /* flags */ 1499 NULL, /* lockfunc */ 1500 NULL, /* lockfuncarg */ 1501 &dma->dma_tag); /* dmat */ 1502 if (result != 0) { 1503 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1504 __func__, result); 1505 goto hdac_dma_alloc_fail; 1506 } 1507 1508 /* 1509 * Allocate DMA memory 1510 */ 1511 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1512 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1513 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1514 &dma->dma_map); 1515 if (result != 0) { 1516 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1517 __func__, result); 1518 goto hdac_dma_alloc_fail; 1519 } 1520 1521 dma->dma_size = roundsz; 1522 1523 /* 1524 * Map the memory 1525 */ 1526 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1527 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1528 if (result != 0 || dma->dma_paddr == 0) { 1529 if (result == 0) 1530 result = ENOMEM; 1531 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1532 __func__, result); 1533 goto hdac_dma_alloc_fail; 1534 } 1535 1536 HDA_BOOTHVERBOSE( 1537 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1538 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1539 ); 1540 1541 return (0); 1542 1543hdac_dma_alloc_fail: 1544 hdac_dma_free(sc, dma); 1545 1546 return (result); 1547} 1548 1549 1550/**************************************************************************** 1551 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1552 * 1553 * Free a struct dhac_dma that has been previously allocated via the 1554 * hdac_dma_alloc function. 1555 ****************************************************************************/ 1556static void 1557hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1558{ 1559 if (dma->dma_map != NULL) { 1560#if 0 1561 /* Flush caches */ 1562 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1563 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1564#endif 1565 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1566 } 1567 if (dma->dma_vaddr != NULL) { 1568 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1569 dma->dma_vaddr = NULL; 1570 } 1571 dma->dma_map = NULL; 1572 if (dma->dma_tag != NULL) { 1573 bus_dma_tag_destroy(dma->dma_tag); 1574 dma->dma_tag = NULL; 1575 } 1576 dma->dma_size = 0; 1577} 1578 1579/**************************************************************************** 1580 * int hdac_mem_alloc(struct hdac_softc *) 1581 * 1582 * Allocate all the bus resources necessary to speak with the physical 1583 * controller. 1584 ****************************************************************************/ 1585static int 1586hdac_mem_alloc(struct hdac_softc *sc) 1587{ 1588 struct hdac_mem *mem; 1589 1590 mem = &sc->mem; 1591 mem->mem_rid = PCIR_BAR(0); 1592 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1593 &mem->mem_rid, RF_ACTIVE); 1594 if (mem->mem_res == NULL) { 1595 device_printf(sc->dev, 1596 "%s: Unable to allocate memory resource\n", __func__); 1597 return (ENOMEM); 1598 } 1599 mem->mem_tag = rman_get_bustag(mem->mem_res); 1600 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1601 1602 return (0); 1603} 1604 1605/**************************************************************************** 1606 * void hdac_mem_free(struct hdac_softc *) 1607 * 1608 * Free up resources previously allocated by hdac_mem_alloc. 1609 ****************************************************************************/ 1610static void 1611hdac_mem_free(struct hdac_softc *sc) 1612{ 1613 struct hdac_mem *mem; 1614 1615 mem = &sc->mem; 1616 if (mem->mem_res != NULL) 1617 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1618 mem->mem_res); 1619 mem->mem_res = NULL; 1620} 1621 1622/**************************************************************************** 1623 * int hdac_irq_alloc(struct hdac_softc *) 1624 * 1625 * Allocate and setup the resources necessary for interrupt handling. 1626 ****************************************************************************/ 1627static int 1628hdac_irq_alloc(struct hdac_softc *sc) 1629{ 1630 struct hdac_irq *irq; 1631 int result; 1632 1633 irq = &sc->irq; 1634 irq->irq_rid = 0x0; 1635 1636#ifdef HDAC_MSI_ENABLED 1637 if ((sc->flags & HDAC_F_MSI) && 1638 (result = pci_msi_count(sc->dev)) == 1 && 1639 pci_alloc_msi(sc->dev, &result) == 0) 1640 irq->irq_rid = 0x1; 1641 else 1642#endif 1643 sc->flags &= ~HDAC_F_MSI; 1644 1645 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1646 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1647 if (irq->irq_res == NULL) { 1648 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1649 __func__); 1650 goto hdac_irq_alloc_fail; 1651 } 1652 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1653 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1654 if (result != 0) { 1655 device_printf(sc->dev, 1656 "%s: Unable to setup interrupt handler (%x)\n", 1657 __func__, result); 1658 goto hdac_irq_alloc_fail; 1659 } 1660 1661 return (0); 1662 1663hdac_irq_alloc_fail: 1664 hdac_irq_free(sc); 1665 1666 return (ENXIO); 1667} 1668 1669/**************************************************************************** 1670 * void hdac_irq_free(struct hdac_softc *) 1671 * 1672 * Free up resources previously allocated by hdac_irq_alloc. 1673 ****************************************************************************/ 1674static void 1675hdac_irq_free(struct hdac_softc *sc) 1676{ 1677 struct hdac_irq *irq; 1678 1679 irq = &sc->irq; 1680 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1681 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1682 if (irq->irq_res != NULL) 1683 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1684 irq->irq_res); 1685#ifdef HDAC_MSI_ENABLED 1686 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1687 pci_release_msi(sc->dev); 1688#endif 1689 irq->irq_handle = NULL; 1690 irq->irq_res = NULL; 1691 irq->irq_rid = 0x0; 1692} 1693 1694/**************************************************************************** 1695 * void hdac_corb_init(struct hdac_softc *) 1696 * 1697 * Initialize the corb registers for operations but do not start it up yet. 1698 * The CORB engine must not be running when this function is called. 1699 ****************************************************************************/ 1700static void 1701hdac_corb_init(struct hdac_softc *sc) 1702{ 1703 uint8_t corbsize; 1704 uint64_t corbpaddr; 1705 1706 /* Setup the CORB size. */ 1707 switch (sc->corb_size) { 1708 case 256: 1709 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1710 break; 1711 case 16: 1712 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1713 break; 1714 case 2: 1715 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1716 break; 1717 default: 1718 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1719 } 1720 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1721 1722 /* Setup the CORB Address in the hdac */ 1723 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1724 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1725 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1726 1727 /* Set the WP and RP */ 1728 sc->corb_wp = 0; 1729 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1730 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1731 /* 1732 * The HDA specification indicates that the CORBRPRST bit will always 1733 * read as zero. Unfortunately, it seems that at least the 82801G 1734 * doesn't reset the bit to zero, which stalls the corb engine. 1735 * manually reset the bit to zero before continuing. 1736 */ 1737 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1738 1739 /* Enable CORB error reporting */ 1740#if 0 1741 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1742#endif 1743} 1744 1745/**************************************************************************** 1746 * void hdac_rirb_init(struct hdac_softc *) 1747 * 1748 * Initialize the rirb registers for operations but do not start it up yet. 1749 * The RIRB engine must not be running when this function is called. 1750 ****************************************************************************/ 1751static void 1752hdac_rirb_init(struct hdac_softc *sc) 1753{ 1754 uint8_t rirbsize; 1755 uint64_t rirbpaddr; 1756 1757 /* Setup the RIRB size. */ 1758 switch (sc->rirb_size) { 1759 case 256: 1760 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1761 break; 1762 case 16: 1763 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1764 break; 1765 case 2: 1766 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1767 break; 1768 default: 1769 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1770 } 1771 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1772 1773 /* Setup the RIRB Address in the hdac */ 1774 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1775 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1776 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1777 1778 /* Setup the WP and RP */ 1779 sc->rirb_rp = 0; 1780 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1781 1782 /* Setup the interrupt threshold */ 1783 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1784 1785 /* Enable Overrun and response received reporting */ 1786#if 0 1787 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1788 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1789#else 1790 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1791#endif 1792 1793#if 0 1794 /* 1795 * Make sure that the Host CPU cache doesn't contain any dirty 1796 * cache lines that falls in the rirb. If I understood correctly, it 1797 * should be sufficient to do this only once as the rirb is purely 1798 * read-only from now on. 1799 */ 1800 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1801 BUS_DMASYNC_PREREAD); 1802#endif 1803} 1804 1805/**************************************************************************** 1806 * void hdac_corb_start(hdac_softc *) 1807 * 1808 * Startup the corb DMA engine 1809 ****************************************************************************/ 1810static void 1811hdac_corb_start(struct hdac_softc *sc) 1812{ 1813 uint32_t corbctl; 1814 1815 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1816 corbctl |= HDAC_CORBCTL_CORBRUN; 1817 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1818} 1819 1820/**************************************************************************** 1821 * void hdac_rirb_start(hdac_softc *) 1822 * 1823 * Startup the rirb DMA engine 1824 ****************************************************************************/ 1825static void 1826hdac_rirb_start(struct hdac_softc *sc) 1827{ 1828 uint32_t rirbctl; 1829 1830 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1831 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1832 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1833} 1834 1835 1836/**************************************************************************** 1837 * void hdac_scan_codecs(struct hdac_softc *, int) 1838 * 1839 * Scan the bus for available codecs, starting with num. 1840 ****************************************************************************/ 1841static void 1842hdac_scan_codecs(struct hdac_softc *sc) 1843{ 1844 struct hdac_codec *codec; 1845 int i; 1846 uint16_t statests; 1847 1848 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1849 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1850 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1851 /* We have found a codec. */ 1852 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1853 M_HDAC, M_ZERO | M_NOWAIT); 1854 if (codec == NULL) { 1855 device_printf(sc->dev, 1856 "Unable to allocate memory for codec\n"); 1857 continue; 1858 } 1859 codec->commands = NULL; 1860 codec->responses_received = 0; 1861 codec->verbs_sent = 0; 1862 codec->sc = sc; 1863 codec->cad = i; 1864 sc->codecs[i] = codec; 1865 hdac_probe_codec(codec); 1866 } 1867 } 1868 /* All codecs have been probed, now try to attach drivers to them */ 1869 /* bus_generic_attach(sc->dev); */ 1870} 1871 1872/**************************************************************************** 1873 * void hdac_probe_codec(struct hdac_softc *, int) 1874 * 1875 * Probe a the given codec_id for available function groups. 1876 ****************************************************************************/ 1877static void 1878hdac_probe_codec(struct hdac_codec *codec) 1879{ 1880 struct hdac_softc *sc = codec->sc; 1881 uint32_t vendorid, revisionid, subnode; 1882 int startnode; 1883 int endnode; 1884 int i; 1885 nid_t cad = codec->cad; 1886 1887 HDA_BOOTVERBOSE( 1888 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1889 ); 1890 vendorid = hdac_command(sc, 1891 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1892 cad); 1893 revisionid = hdac_command(sc, 1894 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1895 cad); 1896 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1897 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1898 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1899 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1900 1901 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1902 device_printf(sc->dev, "Codec #%d is not responding!" 1903 " Probing aborted.\n", cad); 1904 return; 1905 } 1906 1907 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1908 cad, hdac_codec_name(codec)); 1909 HDA_BOOTVERBOSE( 1910 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1911 hdac_codec_id(codec)); 1912 device_printf(sc->dev, " Vendor: 0x%04x\n", 1913 codec->vendor_id); 1914 device_printf(sc->dev, " Device: 0x%04x\n", 1915 codec->device_id); 1916 device_printf(sc->dev, " Revision: 0x%02x\n", 1917 codec->revision_id); 1918 device_printf(sc->dev, " Stepping: 0x%02x\n", 1919 codec->stepping_id); 1920 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1921 sc->pci_subvendor); 1922 ); 1923 subnode = hdac_command(sc, 1924 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1925 cad); 1926 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1927 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1928 1929 HDA_BOOTHVERBOSE( 1930 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1931 startnode, endnode); 1932 ); 1933 1934 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1935 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1936 if (codec->fgs == NULL) { 1937 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1938 __func__); 1939 return; 1940 } 1941 1942 for (i = startnode; i < endnode; i++) 1943 hdac_probe_function(codec, i); 1944 return; 1945} 1946 1947/* 1948 * Probe codec function and add it to the list. 1949 */ 1950static void 1951hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1952{ 1953 struct hdac_softc *sc = codec->sc; 1954 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1955 uint32_t fctgrptype; 1956 uint32_t res; 1957 nid_t cad = codec->cad; 1958 1959 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1960 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1961 1962 devinfo->nid = nid; 1963 devinfo->node_type = fctgrptype; 1964 devinfo->codec = codec; 1965 1966 res = hdac_command(sc, 1967 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1968 1969 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1970 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1971 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1972 1973 HDA_BOOTVERBOSE( 1974 device_printf(sc->dev, 1975 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1976 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1977 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1978 "unknown", nid, devinfo->startnode, devinfo->endnode, 1979 devinfo->nodecnt); 1980 ); 1981 1982 if (devinfo->nodecnt > 0) 1983 devinfo->widget = (struct hdac_widget *)malloc( 1984 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1985 M_NOWAIT | M_ZERO); 1986 else 1987 devinfo->widget = NULL; 1988 1989 if (devinfo->widget == NULL) { 1990 device_printf(sc->dev, "unable to allocate widgets!\n"); 1991 devinfo->endnode = devinfo->startnode; 1992 devinfo->nodecnt = 0; 1993 return; 1994 } 1995 1996 codec->num_fgs++; 1997} 1998 1999static void 2000hdac_widget_connection_parse(struct hdac_widget *w) 2001{ 2002 struct hdac_softc *sc = w->devinfo->codec->sc; 2003 uint32_t res; 2004 int i, j, max, ents, entnum; 2005 nid_t cad = w->devinfo->codec->cad; 2006 nid_t nid = w->nid; 2007 nid_t cnid, addcnid, prevcnid; 2008 2009 w->nconns = 0; 2010 2011 res = hdac_command(sc, 2012 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2013 2014 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2015 2016 if (ents < 1) 2017 return; 2018 2019 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2020 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2021 prevcnid = 0; 2022 2023#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2024#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2025#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2026#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2027#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2028 2029 for (i = 0; i < ents; i += entnum) { 2030 res = hdac_command(sc, 2031 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2032 for (j = 0; j < entnum; j++) { 2033 cnid = CONN_CNID(res, entnum, j); 2034 if (cnid == 0) { 2035 if (w->nconns < ents) 2036 device_printf(sc->dev, 2037 "%s: nid=%d WARNING: zero cnid " 2038 "entnum=%d j=%d index=%d " 2039 "entries=%d found=%d res=0x%08x\n", 2040 __func__, nid, entnum, j, i, 2041 ents, w->nconns, res); 2042 else 2043 goto getconns_out; 2044 } 2045 if (cnid < w->devinfo->startnode || 2046 cnid >= w->devinfo->endnode) { 2047 HDA_BOOTVERBOSE( 2048 device_printf(sc->dev, 2049 "GHOST: nid=%d j=%d " 2050 "entnum=%d index=%d res=0x%08x\n", 2051 nid, j, entnum, i, res); 2052 ); 2053 } 2054 if (CONN_RANGE(res, entnum, j) == 0) 2055 addcnid = cnid; 2056 else if (prevcnid == 0 || prevcnid >= cnid) { 2057 device_printf(sc->dev, 2058 "%s: WARNING: Invalid child range " 2059 "nid=%d index=%d j=%d entnum=%d " 2060 "prevcnid=%d cnid=%d res=0x%08x\n", 2061 __func__, nid, i, j, entnum, prevcnid, 2062 cnid, res); 2063 addcnid = cnid; 2064 } else 2065 addcnid = prevcnid + 1; 2066 while (addcnid <= cnid) { 2067 if (w->nconns > max) { 2068 device_printf(sc->dev, 2069 "Adding %d (nid=%d): " 2070 "Max connection reached! max=%d\n", 2071 addcnid, nid, max + 1); 2072 goto getconns_out; 2073 } 2074 w->connsenable[w->nconns] = 1; 2075 w->conns[w->nconns++] = addcnid++; 2076 } 2077 prevcnid = cnid; 2078 } 2079 } 2080 2081getconns_out: 2082 return; 2083} 2084 2085static uint32_t 2086hdac_widget_pin_patch(uint32_t config, const char *str) 2087{ 2088 char buf[256]; 2089 char *key, *value, *rest, *bad; 2090 int ival, i; 2091 2092 strlcpy(buf, str, sizeof(buf)); 2093 rest = buf; 2094 while ((key = strsep(&rest, "=")) != NULL) { 2095 value = strsep(&rest, " \t"); 2096 if (value == NULL) 2097 break; 2098 ival = strtol(value, &bad, 10); 2099 if (strcmp(key, "seq") == 0) { 2100 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2101 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2102 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2103 } else if (strcmp(key, "as") == 0) { 2104 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2105 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2106 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2107 } else if (strcmp(key, "misc") == 0) { 2108 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2109 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2110 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2111 } else if (strcmp(key, "color") == 0) { 2112 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2113 if (bad[0] == 0) { 2114 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2115 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2116 }; 2117 for (i = 0; i < 16; i++) { 2118 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2119 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2120 break; 2121 } 2122 } 2123 } else if (strcmp(key, "ctype") == 0) { 2124 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2125 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2126 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2127 } else if (strcmp(key, "device") == 0) { 2128 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2129 if (bad[0] == 0) { 2130 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2131 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2132 continue; 2133 }; 2134 for (i = 0; i < 16; i++) { 2135 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2136 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2137 break; 2138 } 2139 } 2140 } else if (strcmp(key, "loc") == 0) { 2141 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2142 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2143 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2144 } else if (strcmp(key, "conn") == 0) { 2145 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2146 if (bad[0] == 0) { 2147 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2148 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2149 continue; 2150 }; 2151 for (i = 0; i < 4; i++) { 2152 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2153 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2154 break; 2155 } 2156 } 2157 } 2158 } 2159 return (config); 2160} 2161 2162static uint32_t 2163hdac_widget_pin_getconfig(struct hdac_widget *w) 2164{ 2165 struct hdac_softc *sc; 2166 uint32_t config, orig, id; 2167 nid_t cad, nid; 2168 char buf[32]; 2169 const char *res = NULL, *patch = NULL; 2170 2171 sc = w->devinfo->codec->sc; 2172 cad = w->devinfo->codec->cad; 2173 nid = w->nid; 2174 id = hdac_codec_id(w->devinfo->codec); 2175 2176 config = hdac_command(sc, 2177 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2178 cad); 2179 orig = config; 2180 2181 HDA_BOOTVERBOSE( 2182 hdac_dump_pin_config(w, orig); 2183 ); 2184 2185 /* XXX: Old patches require complete review. 2186 * Now they may create more problem then solve due to 2187 * incorrect associations. 2188 */ 2189 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2190 switch (nid) { 2191 case 26: 2192 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2193 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2194 break; 2195 case 27: 2196 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2197 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2198 break; 2199 default: 2200 break; 2201 } 2202 } else if (id == HDA_CODEC_ALC880 && 2203 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2204 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2205 /* 2206 * Super broken BIOS 2207 */ 2208 switch (nid) { 2209 case 24: /* MIC1 */ 2210 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2211 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2212 break; 2213 case 25: /* XXX MIC2 */ 2214 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2215 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2216 break; 2217 case 26: /* LINE1 */ 2218 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2219 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2220 break; 2221 case 27: /* XXX LINE2 */ 2222 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2223 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2224 break; 2225 case 28: /* CD */ 2226 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2227 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2228 break; 2229 } 2230 } else if (id == HDA_CODEC_ALC883 && 2231 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2232 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2233 switch (nid) { 2234 case 25: 2235 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2236 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2237 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2238 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2239 break; 2240 case 28: 2241 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2242 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2243 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2244 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2245 break; 2246 } 2247 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2248 HP_V3000_SUBVENDOR) { 2249 switch (nid) { 2250 case 18: 2251 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2252 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2253 break; 2254 case 20: 2255 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2256 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2257 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2258 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2259 break; 2260 case 21: 2261 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2262 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2263 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2264 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2265 break; 2266 } 2267 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2268 HP_DV5000_SUBVENDOR) { 2269 switch (nid) { 2270 case 20: 2271 case 21: 2272 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2273 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2274 break; 2275 } 2276 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2277 ASUS_W6F_SUBVENDOR) { 2278 switch (nid) { 2279 case 11: 2280 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2281 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2282 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2283 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2284 break; 2285 case 12: 2286 case 14: 2287 case 16: 2288 case 31: 2289 case 32: 2290 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2291 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2292 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2293 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2294 break; 2295 case 15: 2296 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2297 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2298 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2299 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2300 break; 2301 } 2302 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2303 UNIWILL_9075_SUBVENDOR) { 2304 switch (nid) { 2305 case 15: 2306 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2307 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2308 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2309 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2310 break; 2311 } 2312 } 2313 2314 /* New patches */ 2315 if (id == HDA_CODEC_AD1986A && 2316 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2317 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2318 switch (nid) { 2319 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2320 patch = "device=Line-in as=8 seq=1"; 2321 break; 2322 case 29: 2323 patch = "device=Mic as=8 seq=2"; 2324 break; 2325 case 31: /* Lot of inputs configured with as=15 and unusable */ 2326 patch = "as=8 seq=3"; 2327 break; 2328 case 32: 2329 patch = "as=8 seq=4"; 2330 break; 2331 case 34: 2332 patch = "as=8 seq=5"; 2333 break; 2334 case 36: 2335 patch = "as=8 seq=6"; 2336 break; 2337 } 2338 } else if (id == HDA_CODEC_ALC260 && 2339 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2340 switch (nid) { 2341 case 16: 2342 patch = "seq=15 device=Headphones"; 2343 break; 2344 } 2345 } else if (id == HDA_CODEC_ALC268 && 2346 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2347 switch (nid) { 2348 case 28: 2349 patch = "device=CD conn=fixed"; 2350 break; 2351 } 2352 } 2353 2354 if (patch != NULL) 2355 config = hdac_widget_pin_patch(config, patch); 2356 2357 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2358 if (resource_string_value(device_get_name(sc->dev), 2359 device_get_unit(sc->dev), buf, &res) == 0) { 2360 if (strncmp(res, "0x", 2) == 0) { 2361 config = strtol(res + 2, NULL, 16); 2362 } else { 2363 config = hdac_widget_pin_patch(config, res); 2364 } 2365 } 2366 2367 HDA_BOOTVERBOSE( 2368 if (config != orig) 2369 device_printf(sc->dev, 2370 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2371 nid, orig, config); 2372 ); 2373 2374 return (config); 2375} 2376 2377static uint32_t 2378hdac_widget_pin_getcaps(struct hdac_widget *w) 2379{ 2380 struct hdac_softc *sc; 2381 uint32_t caps, orig, id; 2382 nid_t cad, nid; 2383 2384 sc = w->devinfo->codec->sc; 2385 cad = w->devinfo->codec->cad; 2386 nid = w->nid; 2387 id = hdac_codec_id(w->devinfo->codec); 2388 2389 caps = hdac_command(sc, 2390 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2391 orig = caps; 2392 2393 HDA_BOOTVERBOSE( 2394 if (caps != orig) 2395 device_printf(sc->dev, 2396 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2397 nid, orig, caps); 2398 ); 2399 2400 return (caps); 2401} 2402 2403static void 2404hdac_widget_pin_parse(struct hdac_widget *w) 2405{ 2406 struct hdac_softc *sc = w->devinfo->codec->sc; 2407 uint32_t config, pincap; 2408 const char *devstr, *connstr; 2409 nid_t cad = w->devinfo->codec->cad; 2410 nid_t nid = w->nid; 2411 2412 config = hdac_widget_pin_getconfig(w); 2413 w->wclass.pin.config = config; 2414 2415 pincap = hdac_widget_pin_getcaps(w); 2416 w->wclass.pin.cap = pincap; 2417 2418 w->wclass.pin.ctrl = hdac_command(sc, 2419 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2420 2421 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2422 w->param.eapdbtl = hdac_command(sc, 2423 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2424 w->param.eapdbtl &= 0x7; 2425 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2426 } else 2427 w->param.eapdbtl = HDAC_INVALID; 2428 2429 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2430 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2431 2432 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2433 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2434 2435 strlcat(w->name, ": ", sizeof(w->name)); 2436 strlcat(w->name, devstr, sizeof(w->name)); 2437 strlcat(w->name, " (", sizeof(w->name)); 2438 strlcat(w->name, connstr, sizeof(w->name)); 2439 strlcat(w->name, ")", sizeof(w->name)); 2440} 2441 2442static uint32_t 2443hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2444{ 2445 struct hdac_softc *sc; 2446 uint32_t caps, orig, id; 2447 nid_t cad, nid, beeper = -1; 2448 2449 sc = w->devinfo->codec->sc; 2450 cad = w->devinfo->codec->cad; 2451 nid = w->nid; 2452 id = hdac_codec_id(w->devinfo->codec); 2453 2454 caps = hdac_command(sc, 2455 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2456 cad); 2457 orig = caps; 2458 2459 /* On some codecs beeper is an input pin, but it is not recordable 2460 alone. Also most of BIOSes does not declare beeper pin. 2461 Change beeper pin node type to beeper to help parser. */ 2462 *waspin = 0; 2463 switch (id) { 2464 case HDA_CODEC_AD1988: 2465 case HDA_CODEC_AD1988B: 2466 beeper = 26; 2467 break; 2468 case HDA_CODEC_ALC260: 2469 beeper = 23; 2470 break; 2471 case HDA_CODEC_ALC262: 2472 case HDA_CODEC_ALC268: 2473 case HDA_CODEC_ALC880: 2474 case HDA_CODEC_ALC882: 2475 case HDA_CODEC_ALC883: 2476 case HDA_CODEC_ALC885: 2477 case HDA_CODEC_ALC888: 2478 case HDA_CODEC_ALC889: 2479 beeper = 29; 2480 break; 2481 } 2482 if (nid == beeper) { 2483 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2484 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2485 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2486 *waspin = 1; 2487 } 2488 2489 HDA_BOOTVERBOSE( 2490 if (caps != orig) { 2491 device_printf(sc->dev, 2492 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2493 nid, orig, caps); 2494 } 2495 ); 2496 2497 return (caps); 2498} 2499 2500static void 2501hdac_widget_parse(struct hdac_widget *w) 2502{ 2503 struct hdac_softc *sc = w->devinfo->codec->sc; 2504 uint32_t wcap, cap; 2505 char *typestr; 2506 nid_t cad = w->devinfo->codec->cad; 2507 nid_t nid = w->nid; 2508 2509 wcap = hdac_widget_getcaps(w, &w->waspin); 2510 2511 w->param.widget_cap = wcap; 2512 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2513 2514 switch (w->type) { 2515 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2516 typestr = "audio output"; 2517 break; 2518 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2519 typestr = "audio input"; 2520 break; 2521 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2522 typestr = "audio mixer"; 2523 break; 2524 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2525 typestr = "audio selector"; 2526 break; 2527 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2528 typestr = "pin"; 2529 break; 2530 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2531 typestr = "power widget"; 2532 break; 2533 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2534 typestr = "volume widget"; 2535 break; 2536 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2537 typestr = "beep widget"; 2538 break; 2539 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2540 typestr = "vendor widget"; 2541 break; 2542 default: 2543 typestr = "unknown type"; 2544 break; 2545 } 2546 2547 strlcpy(w->name, typestr, sizeof(w->name)); 2548 2549 hdac_widget_connection_parse(w); 2550 2551 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2552 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2553 w->param.outamp_cap = 2554 hdac_command(sc, 2555 HDA_CMD_GET_PARAMETER(cad, nid, 2556 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2557 else 2558 w->param.outamp_cap = 2559 w->devinfo->function.audio.outamp_cap; 2560 } else 2561 w->param.outamp_cap = 0; 2562 2563 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2564 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2565 w->param.inamp_cap = 2566 hdac_command(sc, 2567 HDA_CMD_GET_PARAMETER(cad, nid, 2568 HDA_PARAM_INPUT_AMP_CAP), cad); 2569 else 2570 w->param.inamp_cap = 2571 w->devinfo->function.audio.inamp_cap; 2572 } else 2573 w->param.inamp_cap = 0; 2574 2575 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2576 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2577 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2578 cap = hdac_command(sc, 2579 HDA_CMD_GET_PARAMETER(cad, nid, 2580 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2581 w->param.supp_stream_formats = (cap != 0) ? cap : 2582 w->devinfo->function.audio.supp_stream_formats; 2583 cap = hdac_command(sc, 2584 HDA_CMD_GET_PARAMETER(cad, nid, 2585 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2586 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2587 w->devinfo->function.audio.supp_pcm_size_rate; 2588 } else { 2589 w->param.supp_stream_formats = 2590 w->devinfo->function.audio.supp_stream_formats; 2591 w->param.supp_pcm_size_rate = 2592 w->devinfo->function.audio.supp_pcm_size_rate; 2593 } 2594 } else { 2595 w->param.supp_stream_formats = 0; 2596 w->param.supp_pcm_size_rate = 0; 2597 } 2598 2599 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2600 hdac_widget_pin_parse(w); 2601} 2602 2603static struct hdac_widget * 2604hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2605{ 2606 if (devinfo == NULL || devinfo->widget == NULL || 2607 nid < devinfo->startnode || nid >= devinfo->endnode) 2608 return (NULL); 2609 return (&devinfo->widget[nid - devinfo->startnode]); 2610} 2611 2612static __inline int 2613hda_poll_channel(struct hdac_chan *ch) 2614{ 2615 uint32_t sz, delta; 2616 volatile uint32_t ptr; 2617 2618 if (!(ch->flags & HDAC_CHN_RUNNING)) 2619 return (0); 2620 2621 sz = ch->blksz * ch->blkcnt; 2622 if (ch->dmapos != NULL) 2623 ptr = *(ch->dmapos); 2624 else 2625 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2626 ch->off + HDAC_SDLPIB); 2627 ch->ptr = ptr; 2628 ptr %= sz; 2629 ptr &= ~(ch->blksz - 1); 2630 delta = (sz + ptr - ch->prevptr) % sz; 2631 2632 if (delta < ch->blksz) 2633 return (0); 2634 2635 ch->prevptr = ptr; 2636 2637 return (1); 2638} 2639 2640static void 2641hda_poll_callback(void *arg) 2642{ 2643 struct hdac_softc *sc = arg; 2644 uint32_t trigger; 2645 int i, active = 0; 2646 2647 if (sc == NULL) 2648 return; 2649 2650 hdac_lock(sc); 2651 if (sc->polling == 0) { 2652 hdac_unlock(sc); 2653 return; 2654 } 2655 2656 trigger = 0; 2657 for (i = 0; i < sc->num_chans; i++) { 2658 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2659 continue; 2660 active = 1; 2661 if (hda_poll_channel(&sc->chans[i])) 2662 trigger |= (1 << i); 2663 } 2664 2665 /* XXX */ 2666 if (active) 2667 callout_reset(&sc->poll_hda, sc->poll_ticks, 2668 hda_poll_callback, sc); 2669 2670 hdac_unlock(sc); 2671 2672 for (i = 0; i < sc->num_chans; i++) { 2673 if (trigger & (1 << i)) 2674 chn_intr(sc->chans[i].c); 2675 } 2676} 2677 2678static int 2679hdac_rirb_flush(struct hdac_softc *sc) 2680{ 2681 struct hdac_rirb *rirb_base, *rirb; 2682 struct hdac_codec *codec; 2683 struct hdac_command_list *commands; 2684 nid_t cad; 2685 uint32_t resp; 2686 uint8_t rirbwp; 2687 int ret; 2688 2689 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2690 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2691#if 0 2692 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2693 BUS_DMASYNC_POSTREAD); 2694#endif 2695 2696 ret = 0; 2697 2698 while (sc->rirb_rp != rirbwp) { 2699 sc->rirb_rp++; 2700 sc->rirb_rp %= sc->rirb_size; 2701 rirb = &rirb_base[sc->rirb_rp]; 2702 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2703 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2704 sc->codecs[cad] == NULL) 2705 continue; 2706 resp = rirb->response; 2707 codec = sc->codecs[cad]; 2708 commands = codec->commands; 2709 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2710 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2711 ((resp >> 26) & 0xffff); 2712 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2713 } else if (commands != NULL && commands->num_commands > 0 && 2714 codec->responses_received < commands->num_commands) 2715 commands->responses[codec->responses_received++] = 2716 resp; 2717 ret++; 2718 } 2719 2720 return (ret); 2721} 2722 2723static int 2724hdac_unsolq_flush(struct hdac_softc *sc) 2725{ 2726 nid_t cad; 2727 uint32_t tag; 2728 int ret = 0; 2729 2730 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2731 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2732 while (sc->unsolq_rp != sc->unsolq_wp) { 2733 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2734 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2735 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2736 hdac_unsolicited_handler(sc->codecs[cad], tag); 2737 ret++; 2738 } 2739 sc->unsolq_st = HDAC_UNSOLQ_READY; 2740 } 2741 2742 return (ret); 2743} 2744 2745static void 2746hdac_poll_callback(void *arg) 2747{ 2748 struct hdac_softc *sc = arg; 2749 if (sc == NULL) 2750 return; 2751 2752 hdac_lock(sc); 2753 if (sc->polling == 0 || sc->poll_ival == 0) { 2754 hdac_unlock(sc); 2755 return; 2756 } 2757 if (hdac_rirb_flush(sc) != 0) 2758 hdac_unsolq_flush(sc); 2759 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2760 hdac_unlock(sc); 2761} 2762 2763static void 2764hdac_poll_reinit(struct hdac_softc *sc) 2765{ 2766 int i, pollticks, min = 1000000; 2767 struct hdac_chan *ch; 2768 2769 for (i = 0; i < sc->num_chans; i++) { 2770 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2771 continue; 2772 ch = &sc->chans[i]; 2773 pollticks = ((uint64_t)hz * ch->blksz) / 2774 ((uint64_t)sndbuf_getbps(ch->b) * 2775 sndbuf_getspd(ch->b)); 2776 pollticks >>= 1; 2777 if (pollticks > hz) 2778 pollticks = hz; 2779 if (pollticks < 1) { 2780 HDA_BOOTVERBOSE( 2781 device_printf(sc->dev, 2782 "%s: pollticks=%d < 1 !\n", 2783 __func__, pollticks); 2784 ); 2785 pollticks = 1; 2786 } 2787 if (min > pollticks) 2788 min = pollticks; 2789 } 2790 HDA_BOOTVERBOSE( 2791 device_printf(sc->dev, 2792 "%s: pollticks %d -> %d\n", 2793 __func__, sc->poll_ticks, min); 2794 ); 2795 sc->poll_ticks = min; 2796 if (min == 1000000) 2797 callout_stop(&sc->poll_hda); 2798 else 2799 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2800} 2801 2802static void 2803hdac_stream_stop(struct hdac_chan *ch) 2804{ 2805 struct hdac_softc *sc = ch->devinfo->codec->sc; 2806 uint32_t ctl; 2807 2808 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2809 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2810 HDAC_SDCTL_RUN); 2811 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2812 2813 ch->flags &= ~HDAC_CHN_RUNNING; 2814 2815 if (sc->polling != 0) 2816 hdac_poll_reinit(sc); 2817 2818 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2819 ctl &= ~(1 << (ch->off >> 5)); 2820 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2821} 2822 2823static void 2824hdac_stream_start(struct hdac_chan *ch) 2825{ 2826 struct hdac_softc *sc = ch->devinfo->codec->sc; 2827 uint32_t ctl; 2828 2829 ch->flags |= HDAC_CHN_RUNNING; 2830 2831 if (sc->polling != 0) 2832 hdac_poll_reinit(sc); 2833 2834 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2835 ctl |= 1 << (ch->off >> 5); 2836 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2837 2838 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2839 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2840 HDAC_SDCTL_RUN; 2841 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2842} 2843 2844static void 2845hdac_stream_reset(struct hdac_chan *ch) 2846{ 2847 struct hdac_softc *sc = ch->devinfo->codec->sc; 2848 int timeout = 1000; 2849 int to = timeout; 2850 uint32_t ctl; 2851 2852 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2853 ctl |= HDAC_SDCTL_SRST; 2854 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2855 do { 2856 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2857 if (ctl & HDAC_SDCTL_SRST) 2858 break; 2859 DELAY(10); 2860 } while (--to); 2861 if (!(ctl & HDAC_SDCTL_SRST)) { 2862 device_printf(sc->dev, "timeout in reset\n"); 2863 } 2864 ctl &= ~HDAC_SDCTL_SRST; 2865 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2866 to = timeout; 2867 do { 2868 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2869 if (!(ctl & HDAC_SDCTL_SRST)) 2870 break; 2871 DELAY(10); 2872 } while (--to); 2873 if (ctl & HDAC_SDCTL_SRST) 2874 device_printf(sc->dev, "can't reset!\n"); 2875} 2876 2877static void 2878hdac_stream_setid(struct hdac_chan *ch) 2879{ 2880 struct hdac_softc *sc = ch->devinfo->codec->sc; 2881 uint32_t ctl; 2882 2883 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2884 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2885 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2886 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2887} 2888 2889static void 2890hdac_bdl_setup(struct hdac_chan *ch) 2891{ 2892 struct hdac_softc *sc = ch->devinfo->codec->sc; 2893 struct hdac_bdle *bdle; 2894 uint64_t addr; 2895 uint32_t blksz, blkcnt; 2896 int i; 2897 2898 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2899 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2900 2901 blksz = ch->blksz; 2902 blkcnt = ch->blkcnt; 2903 2904 for (i = 0; i < blkcnt; i++, bdle++) { 2905 bdle->addrl = (uint32_t)addr; 2906 bdle->addrh = (uint32_t)(addr >> 32); 2907 bdle->len = blksz; 2908 bdle->ioc = 1; 2909 addr += blksz; 2910 } 2911 2912 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2913 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2914 addr = ch->bdl_dma.dma_paddr; 2915 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2916 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2917 if (ch->dmapos != NULL && 2918 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2919 addr = sc->pos_dma.dma_paddr; 2920 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2921 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2922 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2923 } 2924} 2925 2926static int 2927hdac_bdl_alloc(struct hdac_chan *ch) 2928{ 2929 struct hdac_softc *sc = ch->devinfo->codec->sc; 2930 int rc; 2931 2932 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2933 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2934 if (rc) { 2935 device_printf(sc->dev, "can't alloc bdl\n"); 2936 return (rc); 2937 } 2938 2939 return (0); 2940} 2941 2942static void 2943hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2944 int index, int lmute, int rmute, 2945 int left, int right, int dir) 2946{ 2947 uint16_t v = 0; 2948 2949 if (sc == NULL) 2950 return; 2951 2952 if (left != right || lmute != rmute) { 2953 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2954 (lmute << 7) | left; 2955 hdac_command(sc, 2956 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2957 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2958 (rmute << 7) | right; 2959 } else 2960 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2961 (lmute << 7) | left; 2962 2963 hdac_command(sc, 2964 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2965} 2966 2967static void 2968hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2969 int left, int right) 2970{ 2971 struct hdac_softc *sc; 2972 nid_t nid, cad; 2973 int lmute, rmute; 2974 2975 sc = ctl->widget->devinfo->codec->sc; 2976 cad = ctl->widget->devinfo->codec->cad; 2977 nid = ctl->widget->nid; 2978 2979 /* Save new values if valid. */ 2980 if (mute != HDA_AMP_MUTE_DEFAULT) 2981 ctl->muted = mute; 2982 if (left != HDA_AMP_VOL_DEFAULT) 2983 ctl->left = left; 2984 if (right != HDA_AMP_VOL_DEFAULT) 2985 ctl->right = right; 2986 /* Prepare effective values */ 2987 if (ctl->forcemute) { 2988 lmute = 1; 2989 rmute = 1; 2990 left = 0; 2991 right = 0; 2992 } else { 2993 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2994 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2995 left = ctl->left; 2996 right = ctl->right; 2997 } 2998 /* Apply effective values */ 2999 if (ctl->dir & HDA_CTL_OUT) 3000 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3001 lmute, rmute, left, right, 0); 3002 if (ctl->dir & HDA_CTL_IN) 3003 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3004 lmute, rmute, left, right, 1); 3005} 3006 3007static void 3008hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3009{ 3010 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3011 return; 3012 hdac_command(w->devinfo->codec->sc, 3013 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3014 w->nid, index), w->devinfo->codec->cad); 3015 w->selconn = index; 3016} 3017 3018 3019/**************************************************************************** 3020 * uint32_t hdac_command_sendone_internal 3021 * 3022 * Wrapper function that sends only one command to a given codec 3023 ****************************************************************************/ 3024static uint32_t 3025hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3026{ 3027 struct hdac_command_list cl; 3028 uint32_t response = HDAC_INVALID; 3029 3030 if (!hdac_lockowned(sc)) 3031 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3032 cl.num_commands = 1; 3033 cl.verbs = &verb; 3034 cl.responses = &response; 3035 3036 hdac_command_send_internal(sc, &cl, cad); 3037 3038 return (response); 3039} 3040 3041/**************************************************************************** 3042 * hdac_command_send_internal 3043 * 3044 * Send a command list to the codec via the corb. We queue as much verbs as 3045 * we can and msleep on the codec. When the interrupt get the responses 3046 * back from the rirb, it will wake us up so we can queue the remaining verbs 3047 * if any. 3048 ****************************************************************************/ 3049static void 3050hdac_command_send_internal(struct hdac_softc *sc, 3051 struct hdac_command_list *commands, nid_t cad) 3052{ 3053 struct hdac_codec *codec; 3054 int corbrp; 3055 uint32_t *corb; 3056 int timeout; 3057 int retry = 10; 3058 struct hdac_rirb *rirb_base; 3059 3060 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3061 commands->num_commands < 1) 3062 return; 3063 3064 codec = sc->codecs[cad]; 3065 codec->commands = commands; 3066 codec->responses_received = 0; 3067 codec->verbs_sent = 0; 3068 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3069 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3070 3071 do { 3072 if (codec->verbs_sent != commands->num_commands) { 3073 /* Queue as many verbs as possible */ 3074 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3075#if 0 3076 bus_dmamap_sync(sc->corb_dma.dma_tag, 3077 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3078#endif 3079 while (codec->verbs_sent != commands->num_commands && 3080 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3081 sc->corb_wp++; 3082 sc->corb_wp %= sc->corb_size; 3083 corb[sc->corb_wp] = 3084 commands->verbs[codec->verbs_sent++]; 3085 } 3086 3087 /* Send the verbs to the codecs */ 3088#if 0 3089 bus_dmamap_sync(sc->corb_dma.dma_tag, 3090 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3091#endif 3092 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3093 } 3094 3095 timeout = 1000; 3096 while (hdac_rirb_flush(sc) == 0 && --timeout) 3097 DELAY(10); 3098 } while ((codec->verbs_sent != commands->num_commands || 3099 codec->responses_received != commands->num_commands) && --retry); 3100 3101 if (retry == 0) 3102 device_printf(sc->dev, 3103 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3104 __func__, commands->num_commands, codec->verbs_sent, 3105 codec->responses_received); 3106 3107 codec->commands = NULL; 3108 codec->responses_received = 0; 3109 codec->verbs_sent = 0; 3110 3111 hdac_unsolq_flush(sc); 3112} 3113 3114 3115/**************************************************************************** 3116 * Device Methods 3117 ****************************************************************************/ 3118 3119/**************************************************************************** 3120 * int hdac_probe(device_t) 3121 * 3122 * Probe for the presence of an hdac. If none is found, check for a generic 3123 * match using the subclass of the device. 3124 ****************************************************************************/ 3125static int 3126hdac_probe(device_t dev) 3127{ 3128 int i, result; 3129 uint32_t model; 3130 uint16_t class, subclass; 3131 char desc[64]; 3132 3133 model = (uint32_t)pci_get_device(dev) << 16; 3134 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3135 class = pci_get_class(dev); 3136 subclass = pci_get_subclass(dev); 3137 3138 bzero(desc, sizeof(desc)); 3139 result = ENXIO; 3140 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3141 if (hdac_devices[i].model == model) { 3142 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3143 result = BUS_PROBE_DEFAULT; 3144 break; 3145 } 3146 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3147 class == PCIC_MULTIMEDIA && 3148 subclass == PCIS_MULTIMEDIA_HDA) { 3149 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3150 result = BUS_PROBE_GENERIC; 3151 break; 3152 } 3153 } 3154 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3155 subclass == PCIS_MULTIMEDIA_HDA) { 3156 strlcpy(desc, "Generic", sizeof(desc)); 3157 result = BUS_PROBE_GENERIC; 3158 } 3159 if (result != ENXIO) { 3160 strlcat(desc, " High Definition Audio Controller", 3161 sizeof(desc)); 3162 device_set_desc_copy(dev, desc); 3163 } 3164 3165 return (result); 3166} 3167 3168static void * 3169hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3170 struct pcm_channel *c, int dir) 3171{ 3172 struct hdac_pcm_devinfo *pdevinfo = data; 3173 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3174 struct hdac_softc *sc = devinfo->codec->sc; 3175 struct hdac_chan *ch; 3176 int i, ord = 0, chid; 3177 3178 hdac_lock(sc); 3179 3180 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3181 ch = &sc->chans[chid]; 3182 for (i = 0; i < sc->num_chans && i < chid; i++) { 3183 if (ch->dir == sc->chans[i].dir) 3184 ord++; 3185 } 3186 if (dir == PCMDIR_PLAY) { 3187 ch->off = (sc->num_iss + ord) << 5; 3188 } else { 3189 ch->off = ord << 5; 3190 } 3191 3192 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3193 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3194 ch->pcmrates[0] = 48000; 3195 ch->pcmrates[1] = 0; 3196 } 3197 if (sc->pos_dma.dma_vaddr != NULL) 3198 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3199 (sc->streamcnt * 8)); 3200 else 3201 ch->dmapos = NULL; 3202 ch->sid = ++sc->streamcnt; 3203 ch->dir = dir; 3204 ch->b = b; 3205 ch->c = c; 3206 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3207 ch->blkcnt = pdevinfo->chan_blkcnt; 3208 hdac_unlock(sc); 3209 3210 if (hdac_bdl_alloc(ch) != 0) { 3211 ch->blkcnt = 0; 3212 return (NULL); 3213 } 3214 3215 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3216 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3217 pdevinfo->chan_size) != 0) 3218 return (NULL); 3219 3220 return (ch); 3221} 3222 3223static int 3224hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3225{ 3226 struct hdac_chan *ch = data; 3227 int i; 3228 3229 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3230 if (format == ch->caps.fmtlist[i]) { 3231 ch->fmt = format; 3232 return (0); 3233 } 3234 } 3235 3236 return (EINVAL); 3237} 3238 3239static int 3240hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3241{ 3242 struct hdac_chan *ch = data; 3243 uint32_t spd = 0, threshold; 3244 int i; 3245 3246 for (i = 0; ch->pcmrates[i] != 0; i++) { 3247 spd = ch->pcmrates[i]; 3248 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3249 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3250 if (speed < threshold) 3251 break; 3252 } 3253 3254 if (spd == 0) /* impossible */ 3255 ch->spd = 48000; 3256 else 3257 ch->spd = spd; 3258 3259 return (ch->spd); 3260} 3261 3262static void 3263hdac_stream_setup(struct hdac_chan *ch) 3264{ 3265 struct hdac_softc *sc = ch->devinfo->codec->sc; 3266 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3267 struct hdac_widget *w; 3268 int i, chn, totalchn, c; 3269 nid_t cad = ch->devinfo->codec->cad; 3270 uint16_t fmt, dfmt; 3271 3272 HDA_BOOTHVERBOSE( 3273 device_printf(ch->pdevinfo->dev, 3274 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3275 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3276 ch->fmt, ch->spd); 3277 ); 3278 fmt = 0; 3279 if (ch->fmt & AFMT_S16_LE) 3280 fmt |= ch->bit16 << 4; 3281 else if (ch->fmt & AFMT_S32_LE) 3282 fmt |= ch->bit32 << 4; 3283 else 3284 fmt |= 1 << 4; 3285 3286 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3287 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3288 fmt |= hda_rate_tab[i].base; 3289 fmt |= hda_rate_tab[i].mul; 3290 fmt |= hda_rate_tab[i].div; 3291 break; 3292 } 3293 } 3294 3295 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3296 fmt |= 1; 3297 totalchn = 2; 3298 } else 3299 totalchn = 1; 3300 3301 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3302 3303 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3304 if (ch->fmt & AFMT_AC3) 3305 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3306 3307 chn = 0; 3308 for (i = 0; ch->io[i] != -1; i++) { 3309 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3310 if (w == NULL) 3311 continue; 3312 3313 if (as->hpredir >= 0 && i == as->pincnt) 3314 chn = 0; 3315 HDA_BOOTHVERBOSE( 3316 device_printf(ch->pdevinfo->dev, 3317 "PCMDIR_%s: Stream setup nid=%d: " 3318 "fmt=0x%04x, dfmt=0x%04x\n", 3319 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3320 ch->io[i], fmt, dfmt); 3321 ); 3322 hdac_command(sc, 3323 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3324 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3325 hdac_command(sc, 3326 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3327 cad); 3328 } 3329 /* If HP redirection is enabled, but failed to use same 3330 DAC make last DAC one to duplicate first one. */ 3331 if (as->hpredir >= 0 && i == as->pincnt) { 3332 c = (ch->sid << 4); 3333 } else if (chn >= totalchn) { 3334 /* This is until OSS will support multichannel. 3335 Should be: c = 0; to disable unused DAC */ 3336 c = (ch->sid << 4); 3337 }else { 3338 c = (ch->sid << 4) | chn; 3339 } 3340 hdac_command(sc, 3341 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3342 chn += 3343 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3344 2 : 1; 3345 } 3346} 3347 3348static int 3349hdac_channel_setfragments(kobj_t obj, void *data, 3350 uint32_t blksz, uint32_t blkcnt) 3351{ 3352 struct hdac_chan *ch = data; 3353 struct hdac_softc *sc = ch->devinfo->codec->sc; 3354 3355 blksz &= HDA_BLK_ALIGN; 3356 3357 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3358 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3359 if (blksz < HDA_BLK_MIN) 3360 blksz = HDA_BLK_MIN; 3361 if (blkcnt > HDA_BDL_MAX) 3362 blkcnt = HDA_BDL_MAX; 3363 if (blkcnt < HDA_BDL_MIN) 3364 blkcnt = HDA_BDL_MIN; 3365 3366 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3367 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3368 blkcnt >>= 1; 3369 else if ((blksz >> 1) >= HDA_BLK_MIN) 3370 blksz >>= 1; 3371 else 3372 break; 3373 } 3374 3375 if ((sndbuf_getblksz(ch->b) != blksz || 3376 sndbuf_getblkcnt(ch->b) != blkcnt) && 3377 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3378 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3379 __func__, blksz, blkcnt); 3380 3381 ch->blksz = sndbuf_getblksz(ch->b); 3382 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3383 3384 return (1); 3385} 3386 3387static int 3388hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3389{ 3390 struct hdac_chan *ch = data; 3391 3392 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3393 3394 return (ch->blksz); 3395} 3396 3397static void 3398hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3399{ 3400 struct hdac_devinfo *devinfo = ch->devinfo; 3401 struct hdac_widget *w; 3402 nid_t cad = devinfo->codec->cad; 3403 int i; 3404 3405 hdac_stream_stop(ch); 3406 3407 for (i = 0; ch->io[i] != -1; i++) { 3408 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3409 if (w == NULL) 3410 continue; 3411 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3412 hdac_command(sc, 3413 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3414 cad); 3415 } 3416 hdac_command(sc, 3417 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3418 0), cad); 3419 } 3420} 3421 3422static void 3423hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3424{ 3425 ch->ptr = 0; 3426 ch->prevptr = 0; 3427 hdac_stream_stop(ch); 3428 hdac_stream_reset(ch); 3429 hdac_bdl_setup(ch); 3430 hdac_stream_setid(ch); 3431 hdac_stream_setup(ch); 3432 hdac_stream_start(ch); 3433} 3434 3435static int 3436hdac_channel_trigger(kobj_t obj, void *data, int go) 3437{ 3438 struct hdac_chan *ch = data; 3439 struct hdac_softc *sc = ch->devinfo->codec->sc; 3440 3441 if (!PCMTRIG_COMMON(go)) 3442 return (0); 3443 3444 hdac_lock(sc); 3445 switch (go) { 3446 case PCMTRIG_START: 3447 hdac_channel_start(sc, ch); 3448 break; 3449 case PCMTRIG_STOP: 3450 case PCMTRIG_ABORT: 3451 hdac_channel_stop(sc, ch); 3452 break; 3453 default: 3454 break; 3455 } 3456 hdac_unlock(sc); 3457 3458 return (0); 3459} 3460 3461static int 3462hdac_channel_getptr(kobj_t obj, void *data) 3463{ 3464 struct hdac_chan *ch = data; 3465 struct hdac_softc *sc = ch->devinfo->codec->sc; 3466 uint32_t ptr; 3467 3468 hdac_lock(sc); 3469 if (sc->polling != 0) 3470 ptr = ch->ptr; 3471 else if (ch->dmapos != NULL) 3472 ptr = *(ch->dmapos); 3473 else 3474 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3475 hdac_unlock(sc); 3476 3477 /* 3478 * Round to available space and force 128 bytes aligment. 3479 */ 3480 ptr %= ch->blksz * ch->blkcnt; 3481 ptr &= HDA_BLK_ALIGN; 3482 3483 return (ptr); 3484} 3485 3486static struct pcmchan_caps * 3487hdac_channel_getcaps(kobj_t obj, void *data) 3488{ 3489 return (&((struct hdac_chan *)data)->caps); 3490} 3491 3492static kobj_method_t hdac_channel_methods[] = { 3493 KOBJMETHOD(channel_init, hdac_channel_init), 3494 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3495 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3496 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3497 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3498 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3499 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3500 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3501 { 0, 0 } 3502}; 3503CHANNEL_DECLARE(hdac_channel); 3504 3505static int 3506hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3507{ 3508 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3509 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3510 struct hdac_softc *sc = devinfo->codec->sc; 3511 struct hdac_widget *w, *cw; 3512 struct hdac_audio_ctl *ctl; 3513 uint32_t mask, recmask, id; 3514 int i, j, softpcmvol; 3515 3516 hdac_lock(sc); 3517 3518 /* Make sure that in case of soft volume it won't stay muted. */ 3519 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3520 pdevinfo->left[i] = 100; 3521 pdevinfo->right[i] = 100; 3522 } 3523 3524 mask = 0; 3525 recmask = 0; 3526 id = hdac_codec_id(devinfo->codec); 3527 3528 /* Declate EAPD as ogain control. */ 3529 if (pdevinfo->play >= 0) { 3530 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3531 w = hdac_widget_get(devinfo, i); 3532 if (w == NULL || w->enable == 0) 3533 continue; 3534 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3535 w->param.eapdbtl == HDAC_INVALID || 3536 w->bindas != sc->chans[pdevinfo->play].as) 3537 continue; 3538 mask |= SOUND_MASK_OGAIN; 3539 break; 3540 } 3541 } 3542 3543 /* Declare volume controls assigned to this association. */ 3544 i = 0; 3545 ctl = NULL; 3546 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3547 if (ctl->enable == 0) 3548 continue; 3549 if ((pdevinfo->play >= 0 && 3550 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3551 (pdevinfo->rec >= 0 && 3552 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3553 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3554 mask |= ctl->ossmask; 3555 } 3556 3557 /* Declare record sources available to this association. */ 3558 if (pdevinfo->rec >= 0) { 3559 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3560 for (i = 0; ch->io[i] != -1; i++) { 3561 w = hdac_widget_get(devinfo, ch->io[i]); 3562 if (w == NULL || w->enable == 0) 3563 continue; 3564 for (j = 0; j < w->nconns; j++) { 3565 if (w->connsenable[j] == 0) 3566 continue; 3567 cw = hdac_widget_get(devinfo, w->conns[j]); 3568 if (cw == NULL || cw->enable == 0) 3569 continue; 3570 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3571 cw->bindas != -2) 3572 continue; 3573 recmask |= cw->ossmask; 3574 } 3575 } 3576 } 3577 3578 /* Declare soft PCM volume if needed. */ 3579 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3580 ctl = NULL; 3581 if ((mask & SOUND_MASK_PCM) == 0 || 3582 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3583 softpcmvol = 1; 3584 mask |= SOUND_MASK_PCM; 3585 } else { 3586 softpcmvol = 0; 3587 i = 0; 3588 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3589 if (ctl->enable == 0) 3590 continue; 3591 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3592 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3593 continue; 3594 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3595 continue; 3596 if (ctl->step > 0) 3597 break; 3598 } 3599 } 3600 3601 if (softpcmvol == 1 || ctl == NULL) { 3602 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3603 HDA_BOOTVERBOSE( 3604 device_printf(pdevinfo->dev, 3605 "%s Soft PCM volume\n", 3606 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3607 ); 3608 } 3609 } 3610 3611 /* Declare master volume if needed. */ 3612 if (pdevinfo->play >= 0) { 3613 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3614 SOUND_MASK_PCM) { 3615 mask |= SOUND_MASK_VOLUME; 3616 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3617 SOUND_MASK_PCM); 3618 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3619 SOUND_MIXER_NONE); 3620 HDA_BOOTVERBOSE( 3621 device_printf(pdevinfo->dev, 3622 "Forcing master volume with PCM\n"); 3623 ); 3624 } 3625 } 3626 3627 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3628 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3629 3630 mix_setrecdevs(m, recmask); 3631 mix_setdevs(m, mask); 3632 3633 hdac_unlock(sc); 3634 3635 return (0); 3636} 3637 3638static int 3639hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3640 unsigned left, unsigned right) 3641{ 3642 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3643 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3644 struct hdac_softc *sc = devinfo->codec->sc; 3645 struct hdac_widget *w; 3646 struct hdac_audio_ctl *ctl; 3647 uint32_t mute; 3648 int lvol, rvol; 3649 int i, j; 3650 3651 hdac_lock(sc); 3652 /* Save new values. */ 3653 pdevinfo->left[dev] = left; 3654 pdevinfo->right[dev] = right; 3655 3656 /* 'ogain' is the special case implemented with EAPD. */ 3657 if (dev == SOUND_MIXER_OGAIN) { 3658 uint32_t orig; 3659 w = NULL; 3660 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3661 w = hdac_widget_get(devinfo, i); 3662 if (w == NULL || w->enable == 0) 3663 continue; 3664 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3665 w->param.eapdbtl == HDAC_INVALID) 3666 continue; 3667 break; 3668 } 3669 if (i >= devinfo->endnode) { 3670 hdac_unlock(sc); 3671 return (-1); 3672 } 3673 orig = w->param.eapdbtl; 3674 if (left == 0) 3675 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3676 else 3677 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3678 if (orig != w->param.eapdbtl) { 3679 uint32_t val; 3680 3681 val = w->param.eapdbtl; 3682 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3683 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3684 hdac_command(sc, 3685 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3686 w->nid, val), devinfo->codec->cad); 3687 } 3688 hdac_unlock(sc); 3689 return (left | (left << 8)); 3690 } 3691 3692 /* Recalculate all controls related to this OSS device. */ 3693 i = 0; 3694 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3695 if (ctl->enable == 0 || 3696 !(ctl->ossmask & (1 << dev))) 3697 continue; 3698 if (!((pdevinfo->play >= 0 && 3699 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3700 (pdevinfo->rec >= 0 && 3701 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3702 ctl->widget->bindas == -2)) 3703 continue; 3704 3705 lvol = 100; 3706 rvol = 100; 3707 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3708 if (ctl->ossmask & (1 << j)) { 3709 lvol = lvol * pdevinfo->left[j] / 100; 3710 rvol = rvol * pdevinfo->right[j] / 100; 3711 } 3712 } 3713 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3714 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3715 lvol = (lvol * ctl->step + 50) / 100; 3716 rvol = (rvol * ctl->step + 50) / 100; 3717 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3718 } 3719 hdac_unlock(sc); 3720 3721 return (left | (right << 8)); 3722} 3723 3724/* 3725 * Commutate specified record source. 3726 */ 3727static uint32_t 3728hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3729{ 3730 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3731 struct hdac_widget *w, *cw; 3732 struct hdac_audio_ctl *ctl; 3733 char buf[64]; 3734 int i, muted; 3735 uint32_t res = 0; 3736 3737 if (depth > HDA_PARSE_MAXDEPTH) 3738 return (0); 3739 3740 w = hdac_widget_get(devinfo, nid); 3741 if (w == NULL || w->enable == 0) 3742 return (0); 3743 3744 for (i = 0; i < w->nconns; i++) { 3745 if (w->connsenable[i] == 0) 3746 continue; 3747 cw = hdac_widget_get(devinfo, w->conns[i]); 3748 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3749 continue; 3750 /* Call recursively to trace signal to it's source if needed. */ 3751 if ((src & cw->ossmask) != 0) { 3752 if (cw->ossdev < 0) { 3753 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3754 w->conns[i], depth + 1); 3755 } else { 3756 res |= cw->ossmask; 3757 } 3758 } 3759 /* We have two special cases: mixers and others (selectors). */ 3760 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3761 ctl = hdac_audio_ctl_amp_get(devinfo, 3762 w->nid, HDA_CTL_IN, i, 1); 3763 if (ctl == NULL) 3764 continue; 3765 /* If we have input control on this node mute them 3766 * according to requested sources. */ 3767 muted = (src & cw->ossmask) ? 0 : 1; 3768 if (muted != ctl->forcemute) { 3769 ctl->forcemute = muted; 3770 hdac_audio_ctl_amp_set(ctl, 3771 HDA_AMP_MUTE_DEFAULT, 3772 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3773 } 3774 HDA_BOOTHVERBOSE( 3775 device_printf(pdevinfo->dev, 3776 "Recsel (%s): nid %d source %d %s\n", 3777 hdac_audio_ctl_ossmixer_mask2allname( 3778 src, buf, sizeof(buf)), 3779 nid, i, muted?"mute":"unmute"); 3780 ); 3781 } else { 3782 if (w->nconns == 1) 3783 break; 3784 if ((src & cw->ossmask) == 0) 3785 continue; 3786 /* If we found requested source - select it and exit. */ 3787 hdac_widget_connection_select(w, i); 3788 HDA_BOOTHVERBOSE( 3789 device_printf(pdevinfo->dev, 3790 "Recsel (%s): nid %d source %d select\n", 3791 hdac_audio_ctl_ossmixer_mask2allname( 3792 src, buf, sizeof(buf)), 3793 nid, i); 3794 ); 3795 break; 3796 } 3797 } 3798 return (res); 3799} 3800 3801static uint32_t 3802hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3803{ 3804 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3805 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3806 struct hdac_widget *w; 3807 struct hdac_softc *sc = devinfo->codec->sc; 3808 struct hdac_chan *ch; 3809 int i; 3810 uint32_t ret = 0xffffffff; 3811 3812 hdac_lock(sc); 3813 3814 /* Commutate requested recsrc for each ADC. */ 3815 ch = &sc->chans[pdevinfo->rec]; 3816 for (i = 0; ch->io[i] != -1; i++) { 3817 w = hdac_widget_get(devinfo, ch->io[i]); 3818 if (w == NULL || w->enable == 0) 3819 continue; 3820 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3821 } 3822 3823 hdac_unlock(sc); 3824 3825 return ((ret == 0xffffffff)? 0 : ret); 3826} 3827 3828static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3829 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3830 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3831 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3832 { 0, 0 } 3833}; 3834MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3835 3836static void 3837hdac_unsolq_task(void *context, int pending) 3838{ 3839 struct hdac_softc *sc; 3840 3841 sc = (struct hdac_softc *)context; 3842 3843 hdac_lock(sc); 3844 hdac_unsolq_flush(sc); 3845 hdac_unlock(sc); 3846} 3847 3848/**************************************************************************** 3849 * int hdac_attach(device_t) 3850 * 3851 * Attach the device into the kernel. Interrupts usually won't be enabled 3852 * when this function is called. Setup everything that doesn't require 3853 * interrupts and defer probing of codecs until interrupts are enabled. 3854 ****************************************************************************/ 3855static int 3856hdac_attach(device_t dev) 3857{ 3858 struct hdac_softc *sc; 3859 int result; 3860 int i; 3861 uint16_t vendor; 3862 uint8_t v; 3863 3864 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3865 3866 sc = device_get_softc(dev); 3867 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3868 sc->dev = dev; 3869 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3870 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3871 vendor = pci_get_vendor(dev); 3872 3873 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3874 /* Screw nx6325 - subdevice/subvendor swapped */ 3875 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3876 } 3877 3878 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3879 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3880 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3881 3882 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3883 3884 sc->poll_ticks = 1000000; 3885 sc->poll_ival = HDAC_POLL_INTERVAL; 3886 if (resource_int_value(device_get_name(dev), 3887 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3888 sc->polling = 1; 3889 else 3890 sc->polling = 0; 3891 3892 result = bus_dma_tag_create(NULL, /* parent */ 3893 HDAC_DMA_ALIGNMENT, /* alignment */ 3894 0, /* boundary */ 3895 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3896 BUS_SPACE_MAXADDR, /* highaddr */ 3897 NULL, /* filtfunc */ 3898 NULL, /* fistfuncarg */ 3899 HDA_BUFSZ_MAX, /* maxsize */ 3900 1, /* nsegments */ 3901 HDA_BUFSZ_MAX, /* maxsegsz */ 3902 0, /* flags */ 3903 NULL, /* lockfunc */ 3904 NULL, /* lockfuncarg */ 3905 &sc->chan_dmat); /* dmat */ 3906 if (result != 0) { 3907 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3908 __func__, result); 3909 snd_mtxfree(sc->lock); 3910 free(sc, M_DEVBUF); 3911 return (ENXIO); 3912 } 3913 3914 3915 sc->hdabus = NULL; 3916 for (i = 0; i < HDAC_CODEC_MAX; i++) 3917 sc->codecs[i] = NULL; 3918 3919 pci_enable_busmaster(dev); 3920 3921 if (vendor == INTEL_VENDORID) { 3922 /* TCSEL -> TC0 */ 3923 v = pci_read_config(dev, 0x44, 1); 3924 pci_write_config(dev, 0x44, v & 0xf8, 1); 3925 HDA_BOOTHVERBOSE( 3926 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3927 pci_read_config(dev, 0x44, 1)); 3928 ); 3929 } 3930 3931#ifdef HDAC_MSI_ENABLED 3932 if (resource_int_value(device_get_name(dev), 3933 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3934 pci_msi_count(dev) == 1) 3935 sc->flags |= HDAC_F_MSI; 3936 else 3937#endif 3938 sc->flags &= ~HDAC_F_MSI; 3939 3940#if defined(__i386__) || defined(__amd64__) 3941 sc->flags |= HDAC_F_DMA_NOCACHE; 3942 3943 if (resource_int_value(device_get_name(dev), 3944 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3945#else 3946 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3947#endif 3948 /* 3949 * Try to enable PCIe snoop to avoid messing around with 3950 * uncacheable DMA attribute. Since PCIe snoop register 3951 * config is pretty much vendor specific, there are no 3952 * general solutions on how to enable it, forcing us (even 3953 * Microsoft) to enable uncacheable or write combined DMA 3954 * by default. 3955 * 3956 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3957 */ 3958 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3959 if (hdac_pcie_snoop[i].vendor != vendor) 3960 continue; 3961 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3962 if (hdac_pcie_snoop[i].reg == 0x00) 3963 break; 3964 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3965 if ((v & hdac_pcie_snoop[i].enable) == 3966 hdac_pcie_snoop[i].enable) 3967 break; 3968 v &= hdac_pcie_snoop[i].mask; 3969 v |= hdac_pcie_snoop[i].enable; 3970 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3971 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3972 if ((v & hdac_pcie_snoop[i].enable) != 3973 hdac_pcie_snoop[i].enable) { 3974 HDA_BOOTVERBOSE( 3975 device_printf(dev, 3976 "WARNING: Failed to enable PCIe " 3977 "snoop!\n"); 3978 ); 3979#if defined(__i386__) || defined(__amd64__) 3980 sc->flags |= HDAC_F_DMA_NOCACHE; 3981#endif 3982 } 3983 break; 3984 } 3985#if defined(__i386__) || defined(__amd64__) 3986 } 3987#endif 3988 3989 HDA_BOOTHVERBOSE( 3990 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3991 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3992 "Uncacheable" : "PCIe snoop", vendor); 3993 ); 3994 3995 /* Allocate resources */ 3996 result = hdac_mem_alloc(sc); 3997 if (result != 0) 3998 goto hdac_attach_fail; 3999 result = hdac_irq_alloc(sc); 4000 if (result != 0) 4001 goto hdac_attach_fail; 4002 4003 /* Get Capabilities */ 4004 result = hdac_get_capabilities(sc); 4005 if (result != 0) 4006 goto hdac_attach_fail; 4007 4008 /* Allocate CORB and RIRB dma memory */ 4009 result = hdac_dma_alloc(sc, &sc->corb_dma, 4010 sc->corb_size * sizeof(uint32_t)); 4011 if (result != 0) 4012 goto hdac_attach_fail; 4013 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4014 sc->rirb_size * sizeof(struct hdac_rirb)); 4015 if (result != 0) 4016 goto hdac_attach_fail; 4017 4018 /* Quiesce everything */ 4019 HDA_BOOTHVERBOSE( 4020 device_printf(dev, "Reset controller...\n"); 4021 ); 4022 hdac_reset(sc, 1); 4023 4024 /* Initialize the CORB and RIRB */ 4025 hdac_corb_init(sc); 4026 hdac_rirb_init(sc); 4027 4028 /* Defer remaining of initialization until interrupts are enabled */ 4029 sc->intrhook.ich_func = hdac_attach2; 4030 sc->intrhook.ich_arg = (void *)sc; 4031 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4032 sc->intrhook.ich_func = NULL; 4033 hdac_attach2((void *)sc); 4034 } 4035 4036 return (0); 4037 4038hdac_attach_fail: 4039 hdac_irq_free(sc); 4040 hdac_dma_free(sc, &sc->rirb_dma); 4041 hdac_dma_free(sc, &sc->corb_dma); 4042 hdac_mem_free(sc); 4043 snd_mtxfree(sc->lock); 4044 free(sc, M_DEVBUF); 4045 4046 return (ENXIO); 4047} 4048 4049static void 4050hdac_audio_parse(struct hdac_devinfo *devinfo) 4051{ 4052 struct hdac_codec *codec = devinfo->codec; 4053 struct hdac_softc *sc = codec->sc; 4054 struct hdac_widget *w; 4055 uint32_t res; 4056 int i; 4057 nid_t cad, nid; 4058 4059 cad = devinfo->codec->cad; 4060 nid = devinfo->nid; 4061 4062 res = hdac_command(sc, 4063 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4064 devinfo->function.audio.gpio = res; 4065 4066 HDA_BOOTVERBOSE( 4067 device_printf(sc->dev, "GPIO: 0x%08x " 4068 "NumGPIO=%d NumGPO=%d " 4069 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4070 devinfo->function.audio.gpio, 4071 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4072 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4073 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4074 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4075 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4076 ); 4077 4078 res = hdac_command(sc, 4079 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4080 cad); 4081 devinfo->function.audio.supp_stream_formats = res; 4082 4083 res = hdac_command(sc, 4084 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4085 cad); 4086 devinfo->function.audio.supp_pcm_size_rate = res; 4087 4088 res = hdac_command(sc, 4089 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4090 cad); 4091 devinfo->function.audio.outamp_cap = res; 4092 4093 res = hdac_command(sc, 4094 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4095 cad); 4096 devinfo->function.audio.inamp_cap = res; 4097 4098 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4099 w = hdac_widget_get(devinfo, i); 4100 if (w == NULL) 4101 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4102 else { 4103 w->devinfo = devinfo; 4104 w->nid = i; 4105 w->enable = 1; 4106 w->selconn = -1; 4107 w->pflags = 0; 4108 w->ossdev = -1; 4109 w->bindas = -1; 4110 w->param.eapdbtl = HDAC_INVALID; 4111 hdac_widget_parse(w); 4112 } 4113 } 4114} 4115 4116static void 4117hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4118{ 4119 struct hdac_softc *sc = devinfo->codec->sc; 4120 struct hdac_audio_ctl *ctls; 4121 struct hdac_widget *w, *cw; 4122 int i, j, cnt, max, ocap, icap; 4123 int mute, offset, step, size; 4124 4125 /* XXX This is redundant */ 4126 max = 0; 4127 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4128 w = hdac_widget_get(devinfo, i); 4129 if (w == NULL || w->enable == 0) 4130 continue; 4131 if (w->param.outamp_cap != 0) 4132 max++; 4133 if (w->param.inamp_cap != 0) { 4134 switch (w->type) { 4135 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4136 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4137 for (j = 0; j < w->nconns; j++) { 4138 cw = hdac_widget_get(devinfo, 4139 w->conns[j]); 4140 if (cw == NULL || cw->enable == 0) 4141 continue; 4142 max++; 4143 } 4144 break; 4145 default: 4146 max++; 4147 break; 4148 } 4149 } 4150 } 4151 4152 devinfo->function.audio.ctlcnt = max; 4153 4154 if (max < 1) 4155 return; 4156 4157 ctls = (struct hdac_audio_ctl *)malloc( 4158 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4159 4160 if (ctls == NULL) { 4161 /* Blekh! */ 4162 device_printf(sc->dev, "unable to allocate ctls!\n"); 4163 devinfo->function.audio.ctlcnt = 0; 4164 return; 4165 } 4166 4167 cnt = 0; 4168 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4169 if (cnt >= max) { 4170 device_printf(sc->dev, "%s: Ctl overflow!\n", 4171 __func__); 4172 break; 4173 } 4174 w = hdac_widget_get(devinfo, i); 4175 if (w == NULL || w->enable == 0) 4176 continue; 4177 ocap = w->param.outamp_cap; 4178 icap = w->param.inamp_cap; 4179 if (ocap != 0) { 4180 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4181 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4182 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4183 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4184 /*if (offset > step) { 4185 HDA_BOOTVERBOSE( 4186 device_printf(sc->dev, 4187 "BUGGY outamp: nid=%d " 4188 "[offset=%d > step=%d]\n", 4189 w->nid, offset, step); 4190 ); 4191 offset = step; 4192 }*/ 4193 ctls[cnt].enable = 1; 4194 ctls[cnt].widget = w; 4195 ctls[cnt].mute = mute; 4196 ctls[cnt].step = step; 4197 ctls[cnt].size = size; 4198 ctls[cnt].offset = offset; 4199 ctls[cnt].left = offset; 4200 ctls[cnt].right = offset; 4201 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4202 w->waspin) 4203 ctls[cnt].ndir = HDA_CTL_IN; 4204 else 4205 ctls[cnt].ndir = HDA_CTL_OUT; 4206 ctls[cnt++].dir = HDA_CTL_OUT; 4207 } 4208 4209 if (icap != 0) { 4210 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4211 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4212 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4213 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4214 /*if (offset > step) { 4215 HDA_BOOTVERBOSE( 4216 device_printf(sc->dev, 4217 "BUGGY inamp: nid=%d " 4218 "[offset=%d > step=%d]\n", 4219 w->nid, offset, step); 4220 ); 4221 offset = step; 4222 }*/ 4223 switch (w->type) { 4224 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4225 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4226 for (j = 0; j < w->nconns; j++) { 4227 if (cnt >= max) { 4228 device_printf(sc->dev, 4229 "%s: Ctl overflow!\n", 4230 __func__); 4231 break; 4232 } 4233 cw = hdac_widget_get(devinfo, 4234 w->conns[j]); 4235 if (cw == NULL || cw->enable == 0) 4236 continue; 4237 ctls[cnt].enable = 1; 4238 ctls[cnt].widget = w; 4239 ctls[cnt].childwidget = cw; 4240 ctls[cnt].index = j; 4241 ctls[cnt].mute = mute; 4242 ctls[cnt].step = step; 4243 ctls[cnt].size = size; 4244 ctls[cnt].offset = offset; 4245 ctls[cnt].left = offset; 4246 ctls[cnt].right = offset; 4247 ctls[cnt].ndir = HDA_CTL_IN; 4248 ctls[cnt++].dir = HDA_CTL_IN; 4249 } 4250 break; 4251 default: 4252 if (cnt >= max) { 4253 device_printf(sc->dev, 4254 "%s: Ctl overflow!\n", 4255 __func__); 4256 break; 4257 } 4258 ctls[cnt].enable = 1; 4259 ctls[cnt].widget = w; 4260 ctls[cnt].mute = mute; 4261 ctls[cnt].step = step; 4262 ctls[cnt].size = size; 4263 ctls[cnt].offset = offset; 4264 ctls[cnt].left = offset; 4265 ctls[cnt].right = offset; 4266 if (w->type == 4267 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4268 ctls[cnt].ndir = HDA_CTL_OUT; 4269 else 4270 ctls[cnt].ndir = HDA_CTL_IN; 4271 ctls[cnt++].dir = HDA_CTL_IN; 4272 break; 4273 } 4274 } 4275 } 4276 4277 devinfo->function.audio.ctl = ctls; 4278} 4279 4280static void 4281hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4282{ 4283 struct hdac_softc *sc = devinfo->codec->sc; 4284 struct hdac_audio_as *as; 4285 struct hdac_widget *w; 4286 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4287 4288 /* Count present associations */ 4289 max = 0; 4290 for (j = 1; j < 16; j++) { 4291 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4292 w = hdac_widget_get(devinfo, i); 4293 if (w == NULL || w->enable == 0) 4294 continue; 4295 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4296 continue; 4297 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4298 != j) 4299 continue; 4300 max++; 4301 if (j != 15) /* There could be many 1-pin assocs #15 */ 4302 break; 4303 } 4304 } 4305 4306 devinfo->function.audio.ascnt = max; 4307 4308 if (max < 1) 4309 return; 4310 4311 as = (struct hdac_audio_as *)malloc( 4312 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4313 4314 if (as == NULL) { 4315 /* Blekh! */ 4316 device_printf(sc->dev, "unable to allocate assocs!\n"); 4317 devinfo->function.audio.ascnt = 0; 4318 return; 4319 } 4320 4321 for (i = 0; i < max; i++) { 4322 as[i].hpredir = -1; 4323 as[i].chan = -1; 4324 as[i].digital = 1; 4325 } 4326 4327 /* Scan associations skipping as=0. */ 4328 cnt = 0; 4329 for (j = 1; j < 16; j++) { 4330 first = 16; 4331 hpredir = 0; 4332 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4333 w = hdac_widget_get(devinfo, i); 4334 if (w == NULL || w->enable == 0) 4335 continue; 4336 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4337 continue; 4338 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4339 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4340 if (assoc != j) { 4341 continue; 4342 } 4343 KASSERT(cnt < max, 4344 ("%s: Associations owerflow (%d of %d)", 4345 __func__, cnt, max)); 4346 type = w->wclass.pin.config & 4347 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4348 /* Get pin direction. */ 4349 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4350 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4351 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4352 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4353 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4354 dir = HDA_CTL_OUT; 4355 else 4356 dir = HDA_CTL_IN; 4357 /* If this is a first pin - create new association. */ 4358 if (as[cnt].pincnt == 0) { 4359 as[cnt].enable = 1; 4360 as[cnt].index = j; 4361 as[cnt].dir = dir; 4362 } 4363 if (seq < first) 4364 first = seq; 4365 /* Check association correctness. */ 4366 if (as[cnt].pins[seq] != 0) { 4367 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4368 "in association %d! Disabling association.\n", 4369 __func__, seq, w->nid, j); 4370 as[cnt].enable = 0; 4371 } 4372 if (dir != as[cnt].dir) { 4373 device_printf(sc->dev, "%s: Pin %d has wrong " 4374 "direction for association %d! Disabling " 4375 "association.\n", 4376 __func__, w->nid, j); 4377 as[cnt].enable = 0; 4378 } 4379 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4380 as[cnt].digital = 0; 4381 /* Headphones with seq=15 may mean redirection. */ 4382 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4383 seq == 15) 4384 hpredir = 1; 4385 as[cnt].pins[seq] = w->nid; 4386 as[cnt].pincnt++; 4387 /* Association 15 is a multiple unassociated pins. */ 4388 if (j == 15) 4389 cnt++; 4390 } 4391 if (j != 15 && as[cnt].pincnt > 0) { 4392 if (hpredir && as[cnt].pincnt > 1) 4393 as[cnt].hpredir = first; 4394 cnt++; 4395 } 4396 } 4397 HDA_BOOTVERBOSE( 4398 device_printf(sc->dev, 4399 "%d associations found:\n", max); 4400 for (i = 0; i < max; i++) { 4401 device_printf(sc->dev, 4402 "Association %d (%d) %s%s:\n", 4403 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4404 as[i].enable?"":" (disabled)"); 4405 for (j = 0; j < 16; j++) { 4406 if (as[i].pins[j] == 0) 4407 continue; 4408 device_printf(sc->dev, 4409 " Pin nid=%d seq=%d\n", 4410 as[i].pins[j], j); 4411 } 4412 } 4413 ); 4414 4415 devinfo->function.audio.as = as; 4416} 4417 4418static const struct { 4419 uint32_t model; 4420 uint32_t id; 4421 uint32_t set, unset; 4422} hdac_quirks[] = { 4423 /* 4424 * XXX Force stereo quirk. Monoural recording / playback 4425 * on few codecs (especially ALC880) seems broken or 4426 * perhaps unsupported. 4427 */ 4428 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4429 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4430 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4431 HDA_QUIRK_GPIO0, 0 }, 4432 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4433 HDA_QUIRK_GPIO0, 0 }, 4434 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4435 HDA_QUIRK_GPIO0, 0 }, 4436 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4437 HDA_QUIRK_GPIO0, 0 }, 4438 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4439 HDA_QUIRK_GPIO0, 0 }, 4440 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4441 HDA_QUIRK_GPIO0, 0 }, 4442 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4443 HDA_QUIRK_EAPDINV, 0 }, 4444 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4445 HDA_QUIRK_EAPDINV, 0 }, 4446 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4447 HDA_QUIRK_OVREF, 0 }, 4448 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4449 HDA_QUIRK_OVREF, 0 }, 4450 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4451 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4452 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4453 HDA_QUIRK_GPIO1, 0 }, 4454 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4455 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4456 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4457 HDA_QUIRK_EAPDINV, 0 }, 4458 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4459 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4460 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4461 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4462 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4463 HDA_QUIRK_GPIO0, 0 }, 4464 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4465 HDA_QUIRK_GPIO2, 0 }, 4466 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4467 HDA_QUIRK_GPIO0, 0 }, 4468 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4469 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4470 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4471 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4472 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4473 0, HDA_QUIRK_FORCESTEREO } 4474}; 4475#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4476 4477static void 4478hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4479{ 4480 struct hdac_widget *w; 4481 uint32_t id, subvendor; 4482 int i; 4483 4484 id = hdac_codec_id(devinfo->codec); 4485 subvendor = devinfo->codec->sc->pci_subvendor; 4486 4487 /* 4488 * Quirks 4489 */ 4490 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4491 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4492 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4493 continue; 4494 if (hdac_quirks[i].set != 0) 4495 devinfo->function.audio.quirks |= 4496 hdac_quirks[i].set; 4497 if (hdac_quirks[i].unset != 0) 4498 devinfo->function.audio.quirks &= 4499 ~(hdac_quirks[i].unset); 4500 } 4501 4502 switch (id) { 4503 case HDA_CODEC_ALC883: 4504 /* 4505 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4506 * Clear vref cap for jack connectivity. 4507 */ 4508 w = hdac_widget_get(devinfo, 24); 4509 if (w != NULL && w->enable != 0 && w->type == 4510 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4511 (w->wclass.pin.config & 4512 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4513 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4514 w->wclass.pin.cap &= ~( 4515 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4516 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4517 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4518 w = hdac_widget_get(devinfo, 25); 4519 if (w != NULL && w->enable != 0 && w->type == 4520 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4521 (w->wclass.pin.config & 4522 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4523 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4524 w->wclass.pin.cap &= ~( 4525 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4526 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4527 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4528 /* 4529 * nid: 26 = Line-in, leave it alone. 4530 */ 4531 break; 4532 case HDA_CODEC_AD1986A: 4533 if (subvendor == ASUS_A8X_SUBVENDOR) { 4534 /* 4535 * This is just plain ridiculous.. There 4536 * are several A8 series that share the same 4537 * pci id but works differently (EAPD). 4538 */ 4539 w = hdac_widget_get(devinfo, 26); 4540 if (w != NULL && w->type == 4541 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4542 (w->wclass.pin.config & 4543 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4544 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4545 devinfo->function.audio.quirks &= 4546 ~HDA_QUIRK_EAPDINV; 4547 } 4548 break; 4549 case HDA_CODEC_AD1981HD: 4550 /* 4551 * This codec has very unusual design with several 4552 * points inappropriate for the present parser. 4553 */ 4554 /* Disable recording from mono playback mix. */ 4555 w = hdac_widget_get(devinfo, 21); 4556 if (w != NULL) 4557 w->connsenable[3] = 0; 4558 /* Disable rear to front mic mixer, use separately. */ 4559 w = hdac_widget_get(devinfo, 31); 4560 if (w != NULL) 4561 w->enable = 0; 4562 /* Disable playback mixer, use direct bypass. */ 4563 w = hdac_widget_get(devinfo, 14); 4564 if (w != NULL) 4565 w->enable = 0; 4566 break; 4567 } 4568} 4569 4570/* 4571 * Trace path from DAC to pin. 4572 */ 4573static nid_t 4574hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4575 int dupseq, int min, int only, int depth) 4576{ 4577 struct hdac_widget *w; 4578 int i, im = -1; 4579 nid_t m = 0, ret; 4580 4581 if (depth > HDA_PARSE_MAXDEPTH) 4582 return (0); 4583 w = hdac_widget_get(devinfo, nid); 4584 if (w == NULL || w->enable == 0) 4585 return (0); 4586 HDA_BOOTHVERBOSE( 4587 if (!only) { 4588 device_printf(devinfo->codec->sc->dev, 4589 " %*stracing via nid %d\n", 4590 depth + 1, "", w->nid); 4591 } 4592 ); 4593 /* Use only unused widgets */ 4594 if (w->bindas >= 0 && w->bindas != as) { 4595 HDA_BOOTHVERBOSE( 4596 if (!only) { 4597 device_printf(devinfo->codec->sc->dev, 4598 " %*snid %d busy by association %d\n", 4599 depth + 1, "", w->nid, w->bindas); 4600 } 4601 ); 4602 return (0); 4603 } 4604 if (dupseq < 0) { 4605 if (w->bindseqmask != 0) { 4606 HDA_BOOTHVERBOSE( 4607 if (!only) { 4608 device_printf(devinfo->codec->sc->dev, 4609 " %*snid %d busy by seqmask %x\n", 4610 depth + 1, "", w->nid, w->bindseqmask); 4611 } 4612 ); 4613 return (0); 4614 } 4615 } else { 4616 /* If this is headphones - allow duplicate first pin. */ 4617 if (w->bindseqmask != 0 && 4618 (w->bindseqmask & (1 << dupseq)) == 0) { 4619 HDA_BOOTHVERBOSE( 4620 device_printf(devinfo->codec->sc->dev, 4621 " %*snid %d busy by seqmask %x\n", 4622 depth + 1, "", w->nid, w->bindseqmask); 4623 ); 4624 return (0); 4625 } 4626 } 4627 4628 switch (w->type) { 4629 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4630 /* Do not traverse input. AD1988 has digital monitor 4631 for which we are not ready. */ 4632 break; 4633 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4634 /* If we are tracing HP take only dac of first pin. */ 4635 if ((only == 0 || only == w->nid) && 4636 (w->nid >= min) && (dupseq < 0 || w->nid == 4637 devinfo->function.audio.as[as].dacs[dupseq])) 4638 m = w->nid; 4639 break; 4640 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4641 if (depth > 0) 4642 break; 4643 /* Fall */ 4644 default: 4645 /* Find reachable DACs with smallest nid respecting constraints. */ 4646 for (i = 0; i < w->nconns; i++) { 4647 if (w->connsenable[i] == 0) 4648 continue; 4649 if (w->selconn != -1 && w->selconn != i) 4650 continue; 4651 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4652 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4653 if (m == 0 || ret < m) { 4654 m = ret; 4655 im = i; 4656 } 4657 if (only || dupseq >= 0) 4658 break; 4659 } 4660 } 4661 if (m && only && ((w->nconns > 1 && 4662 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4663 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4664 w->selconn = im; 4665 break; 4666 } 4667 if (m && only) { 4668 w->bindas = as; 4669 w->bindseqmask |= (1 << seq); 4670 } 4671 HDA_BOOTHVERBOSE( 4672 if (!only) { 4673 device_printf(devinfo->codec->sc->dev, 4674 " %*snid %d returned %d\n", 4675 depth + 1, "", w->nid, m); 4676 } 4677 ); 4678 return (m); 4679} 4680 4681/* 4682 * Trace path from widget to ADC. 4683 */ 4684static nid_t 4685hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4686 int only, int depth) 4687{ 4688 struct hdac_widget *w, *wc; 4689 int i, j; 4690 nid_t res = 0; 4691 4692 if (depth > HDA_PARSE_MAXDEPTH) 4693 return (0); 4694 w = hdac_widget_get(devinfo, nid); 4695 if (w == NULL || w->enable == 0) 4696 return (0); 4697 HDA_BOOTHVERBOSE( 4698 device_printf(devinfo->codec->sc->dev, 4699 " %*stracing via nid %d\n", 4700 depth + 1, "", w->nid); 4701 ); 4702 /* Use only unused widgets */ 4703 if (w->bindas >= 0 && w->bindas != as) { 4704 HDA_BOOTHVERBOSE( 4705 device_printf(devinfo->codec->sc->dev, 4706 " %*snid %d busy by association %d\n", 4707 depth + 1, "", w->nid, w->bindas); 4708 ); 4709 return (0); 4710 } 4711 4712 switch (w->type) { 4713 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4714 /* If we are tracing HP take only dac of first pin. */ 4715 if (only == w->nid) 4716 res = 1; 4717 break; 4718 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4719 if (depth > 0) 4720 break; 4721 /* Fall */ 4722 default: 4723 /* Try to find reachable ADCs with specified nid. */ 4724 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4725 wc = hdac_widget_get(devinfo, j); 4726 if (wc == NULL || wc->enable == 0) 4727 continue; 4728 for (i = 0; i < wc->nconns; i++) { 4729 if (wc->connsenable[i] == 0) 4730 continue; 4731 if (wc->conns[i] != nid) 4732 continue; 4733 if (hdac_audio_trace_adc(devinfo, as, seq, 4734 j, only, depth + 1) != 0) { 4735 res = 1; 4736 if (((wc->nconns > 1 && 4737 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4738 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4739 wc->selconn == -1) 4740 wc->selconn = i; 4741 } 4742 } 4743 } 4744 break; 4745 } 4746 if (res) { 4747 w->bindas = as; 4748 w->bindseqmask |= (1 << seq); 4749 } 4750 HDA_BOOTHVERBOSE( 4751 device_printf(devinfo->codec->sc->dev, 4752 " %*snid %d returned %d\n", 4753 depth + 1, "", w->nid, res); 4754 ); 4755 return (res); 4756} 4757 4758/* 4759 * Erase trace path of the specified association. 4760 */ 4761static void 4762hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4763{ 4764 struct hdac_widget *w; 4765 int i; 4766 4767 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4768 w = hdac_widget_get(devinfo, i); 4769 if (w == NULL || w->enable == 0) 4770 continue; 4771 if (w->bindas == as) { 4772 if (seq >= 0) { 4773 w->bindseqmask &= ~(1 << seq); 4774 if (w->bindseqmask == 0) { 4775 w->bindas = -1; 4776 w->selconn = -1; 4777 } 4778 } else { 4779 w->bindas = -1; 4780 w->bindseqmask = 0; 4781 w->selconn = -1; 4782 } 4783 } 4784 } 4785} 4786 4787/* 4788 * Trace association path from DAC to output 4789 */ 4790static int 4791hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4792{ 4793 struct hdac_audio_as *ases = devinfo->function.audio.as; 4794 int i, hpredir; 4795 nid_t min, res; 4796 4797 /* Find next pin */ 4798 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4799 ; 4800 /* Check if there is no any left. If so - we succeded. */ 4801 if (i == 16) 4802 return (1); 4803 4804 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4805 min = 0; 4806 res = 0; 4807 do { 4808 HDA_BOOTHVERBOSE( 4809 device_printf(devinfo->codec->sc->dev, 4810 " Tracing pin %d with min nid %d", 4811 ases[as].pins[i], min); 4812 if (hpredir >= 0) 4813 printf(" and hpredir %d", hpredir); 4814 printf("\n"); 4815 ); 4816 /* Trace this pin taking min nid into account. */ 4817 res = hdac_audio_trace_dac(devinfo, as, i, 4818 ases[as].pins[i], hpredir, min, 0, 0); 4819 if (res == 0) { 4820 /* If we failed - return to previous and redo it. */ 4821 HDA_BOOTVERBOSE( 4822 device_printf(devinfo->codec->sc->dev, 4823 " Unable to trace pin %d seq %d with min " 4824 "nid %d", 4825 ases[as].pins[i], i, min); 4826 if (hpredir >= 0) 4827 printf(" and hpredir %d", hpredir); 4828 printf("\n"); 4829 ); 4830 return (0); 4831 } 4832 HDA_BOOTVERBOSE( 4833 device_printf(devinfo->codec->sc->dev, 4834 " Pin %d traced to DAC %d", 4835 ases[as].pins[i], res); 4836 if (hpredir >= 0) 4837 printf(" and hpredir %d", hpredir); 4838 if (ases[as].fakeredir) 4839 printf(" with fake redirection"); 4840 printf("\n"); 4841 ); 4842 /* Trace again to mark the path */ 4843 hdac_audio_trace_dac(devinfo, as, i, 4844 ases[as].pins[i], hpredir, min, res, 0); 4845 ases[as].dacs[i] = res; 4846 /* We succeded, so call next. */ 4847 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4848 return (1); 4849 /* If next failed, we should retry with next min */ 4850 hdac_audio_undo_trace(devinfo, as, i); 4851 ases[as].dacs[i] = 0; 4852 min = res + 1; 4853 } while (1); 4854} 4855 4856/* 4857 * Trace association path from input to ADC 4858 */ 4859static int 4860hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4861{ 4862 struct hdac_audio_as *ases = devinfo->function.audio.as; 4863 struct hdac_widget *w; 4864 int i, j, k; 4865 4866 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4867 w = hdac_widget_get(devinfo, j); 4868 if (w == NULL || w->enable == 0) 4869 continue; 4870 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4871 continue; 4872 if (w->bindas >= 0 && w->bindas != as) 4873 continue; 4874 4875 /* Find next pin */ 4876 for (i = 0; i < 16; i++) { 4877 if (ases[as].pins[i] == 0) 4878 continue; 4879 4880 HDA_BOOTHVERBOSE( 4881 device_printf(devinfo->codec->sc->dev, 4882 " Tracing pin %d to ADC %d\n", 4883 ases[as].pins[i], j); 4884 ); 4885 /* Trace this pin taking goal into account. */ 4886 if (hdac_audio_trace_adc(devinfo, as, i, 4887 ases[as].pins[i], j, 0) == 0) { 4888 /* If we failed - return to previous and redo it. */ 4889 HDA_BOOTVERBOSE( 4890 device_printf(devinfo->codec->sc->dev, 4891 " Unable to trace pin %d to ADC %d, undo traces\n", 4892 ases[as].pins[i], j); 4893 ); 4894 hdac_audio_undo_trace(devinfo, as, -1); 4895 for (k = 0; k < 16; k++) 4896 ases[as].dacs[k] = 0; 4897 break; 4898 } 4899 HDA_BOOTVERBOSE( 4900 device_printf(devinfo->codec->sc->dev, 4901 " Pin %d traced to ADC %d\n", 4902 ases[as].pins[i], j); 4903 ); 4904 ases[as].dacs[i] = j; 4905 } 4906 if (i == 16) 4907 return (1); 4908 } 4909 return (0); 4910} 4911 4912/* 4913 * Trace input monitor path from mixer to output association. 4914 */ 4915static int 4916hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4917{ 4918 struct hdac_audio_as *ases = devinfo->function.audio.as; 4919 struct hdac_widget *w, *wc; 4920 int i, j; 4921 nid_t res = 0; 4922 4923 if (depth > HDA_PARSE_MAXDEPTH) 4924 return (0); 4925 w = hdac_widget_get(devinfo, nid); 4926 if (w == NULL || w->enable == 0) 4927 return (0); 4928 HDA_BOOTHVERBOSE( 4929 device_printf(devinfo->codec->sc->dev, 4930 " %*stracing via nid %d\n", 4931 depth + 1, "", w->nid); 4932 ); 4933 /* Use only unused widgets */ 4934 if (depth > 0 && w->bindas != -1) { 4935 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4936 HDA_BOOTHVERBOSE( 4937 device_printf(devinfo->codec->sc->dev, 4938 " %*snid %d found output association %d\n", 4939 depth + 1, "", w->nid, w->bindas); 4940 ); 4941 return (1); 4942 } else { 4943 HDA_BOOTHVERBOSE( 4944 device_printf(devinfo->codec->sc->dev, 4945 " %*snid %d busy by input association %d\n", 4946 depth + 1, "", w->nid, w->bindas); 4947 ); 4948 return (0); 4949 } 4950 } 4951 4952 switch (w->type) { 4953 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4954 /* Do not traverse input. AD1988 has digital monitor 4955 for which we are not ready. */ 4956 break; 4957 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4958 if (depth > 0) 4959 break; 4960 /* Fall */ 4961 default: 4962 /* Try to find reachable ADCs with specified nid. */ 4963 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4964 wc = hdac_widget_get(devinfo, j); 4965 if (wc == NULL || wc->enable == 0) 4966 continue; 4967 for (i = 0; i < wc->nconns; i++) { 4968 if (wc->connsenable[i] == 0) 4969 continue; 4970 if (wc->conns[i] != nid) 4971 continue; 4972 if (hdac_audio_trace_to_out(devinfo, 4973 j, depth + 1) != 0) { 4974 res = 1; 4975 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4976 wc->selconn == -1) 4977 wc->selconn = i; 4978 } 4979 } 4980 } 4981 break; 4982 } 4983 if (res) 4984 w->bindas = -2; 4985 4986 HDA_BOOTHVERBOSE( 4987 device_printf(devinfo->codec->sc->dev, 4988 " %*snid %d returned %d\n", 4989 depth + 1, "", w->nid, res); 4990 ); 4991 return (res); 4992} 4993 4994/* 4995 * Trace extra associations (beeper, monitor) 4996 */ 4997static void 4998hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4999{ 5000 struct hdac_audio_as *as = devinfo->function.audio.as; 5001 struct hdac_widget *w; 5002 int j; 5003 5004 /* Input monitor */ 5005 /* Find mixer associated with input, but supplying signal 5006 for output associations. Hope it will be input monitor. */ 5007 HDA_BOOTVERBOSE( 5008 device_printf(devinfo->codec->sc->dev, 5009 "Tracing input monitor\n"); 5010 ); 5011 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5012 w = hdac_widget_get(devinfo, j); 5013 if (w == NULL || w->enable == 0) 5014 continue; 5015 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5016 continue; 5017 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5018 continue; 5019 HDA_BOOTVERBOSE( 5020 device_printf(devinfo->codec->sc->dev, 5021 " Tracing nid %d to out\n", 5022 j); 5023 ); 5024 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5025 HDA_BOOTVERBOSE( 5026 device_printf(devinfo->codec->sc->dev, 5027 " nid %d is input monitor\n", 5028 w->nid); 5029 ); 5030 w->pflags |= HDA_ADC_MONITOR; 5031 w->ossdev = SOUND_MIXER_IMIX; 5032 } 5033 } 5034 5035 /* Beeper */ 5036 HDA_BOOTVERBOSE( 5037 device_printf(devinfo->codec->sc->dev, 5038 "Tracing beeper\n"); 5039 ); 5040 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5041 w = hdac_widget_get(devinfo, j); 5042 if (w == NULL || w->enable == 0) 5043 continue; 5044 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5045 continue; 5046 HDA_BOOTHVERBOSE( 5047 device_printf(devinfo->codec->sc->dev, 5048 " Tracing nid %d to out\n", 5049 j); 5050 ); 5051 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5052 HDA_BOOTVERBOSE( 5053 device_printf(devinfo->codec->sc->dev, 5054 " nid %d traced to out\n", 5055 j); 5056 ); 5057 } 5058 w->bindas = -2; 5059 } 5060} 5061 5062/* 5063 * Bind assotiations to PCM channels 5064 */ 5065static void 5066hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5067{ 5068 struct hdac_softc *sc = devinfo->codec->sc; 5069 struct hdac_audio_as *as = devinfo->function.audio.as; 5070 int j, cnt = 0, free; 5071 5072 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5073 if (as[j].enable) 5074 cnt++; 5075 } 5076 if (sc->num_chans == 0) { 5077 sc->chans = (struct hdac_chan *)malloc( 5078 sizeof(struct hdac_chan) * cnt, 5079 M_HDAC, M_ZERO | M_NOWAIT); 5080 if (sc->chans == NULL) { 5081 device_printf(devinfo->codec->sc->dev, 5082 "Channels memory allocation failed!\n"); 5083 return; 5084 } 5085 } else { 5086 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5087 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5088 M_HDAC, M_ZERO | M_NOWAIT); 5089 if (sc->chans == NULL) { 5090 sc->num_chans = 0; 5091 device_printf(devinfo->codec->sc->dev, 5092 "Channels memory allocation failed!\n"); 5093 return; 5094 } 5095 } 5096 free = sc->num_chans; 5097 sc->num_chans += cnt; 5098 5099 for (j = free; j < free + cnt; j++) { 5100 devinfo->codec->sc->chans[j].devinfo = devinfo; 5101 devinfo->codec->sc->chans[j].as = -1; 5102 } 5103 5104 /* Assign associations in order of their numbers, */ 5105 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5106 if (as[j].enable == 0) 5107 continue; 5108 5109 as[j].chan = free; 5110 devinfo->codec->sc->chans[free].as = j; 5111 devinfo->codec->sc->chans[free].dir = 5112 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5113 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5114 free++; 5115 } 5116} 5117 5118static void 5119hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5120{ 5121 struct hdac_widget *w; 5122 int i; 5123 5124 /* Disable power and volume widgets. */ 5125 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5126 w = hdac_widget_get(devinfo, i); 5127 if (w == NULL || w->enable == 0) 5128 continue; 5129 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5130 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5131 w->enable = 0; 5132 HDA_BOOTHVERBOSE( 5133 device_printf(devinfo->codec->sc->dev, 5134 " Disabling nid %d due to it's" 5135 " non-audio type.\n", 5136 w->nid); 5137 ); 5138 } 5139 } 5140} 5141 5142static void 5143hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5144{ 5145 struct hdac_widget *w, *cw; 5146 struct hdac_audio_ctl *ctl; 5147 int done, found, i, j, k; 5148 5149 /* Disable useless pins. */ 5150 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5151 w = hdac_widget_get(devinfo, i); 5152 if (w == NULL || w->enable == 0) 5153 continue; 5154 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5155 if ((w->wclass.pin.config & 5156 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5157 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5158 w->enable = 0; 5159 HDA_BOOTHVERBOSE( 5160 device_printf(devinfo->codec->sc->dev, 5161 " Disabling pin nid %d due" 5162 " to None connectivity.\n", 5163 w->nid); 5164 ); 5165 } else if ((w->wclass.pin.config & 5166 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5167 w->enable = 0; 5168 HDA_BOOTHVERBOSE( 5169 device_printf(devinfo->codec->sc->dev, 5170 " Disabling unassociated" 5171 " pin nid %d.\n", 5172 w->nid); 5173 ); 5174 } 5175 } 5176 } 5177 do { 5178 done = 1; 5179 /* Disable and mute controls for disabled widgets. */ 5180 i = 0; 5181 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5182 if (ctl->enable == 0) 5183 continue; 5184 if (ctl->widget->enable == 0 || 5185 (ctl->childwidget != NULL && 5186 ctl->childwidget->enable == 0)) { 5187 ctl->forcemute = 1; 5188 ctl->muted = HDA_AMP_MUTE_ALL; 5189 ctl->left = 0; 5190 ctl->right = 0; 5191 ctl->enable = 0; 5192 if (ctl->ndir == HDA_CTL_IN) 5193 ctl->widget->connsenable[ctl->index] = 0; 5194 done = 0; 5195 HDA_BOOTHVERBOSE( 5196 device_printf(devinfo->codec->sc->dev, 5197 " Disabling ctl %d nid %d cnid %d due" 5198 " to disabled widget.\n", i, 5199 ctl->widget->nid, 5200 (ctl->childwidget != NULL)? 5201 ctl->childwidget->nid:-1); 5202 ); 5203 } 5204 } 5205 /* Disable useless widgets. */ 5206 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5207 w = hdac_widget_get(devinfo, i); 5208 if (w == NULL || w->enable == 0) 5209 continue; 5210 /* Disable inputs with disabled child widgets. */ 5211 for (j = 0; j < w->nconns; j++) { 5212 if (w->connsenable[j]) { 5213 cw = hdac_widget_get(devinfo, w->conns[j]); 5214 if (cw == NULL || cw->enable == 0) { 5215 w->connsenable[j] = 0; 5216 HDA_BOOTHVERBOSE( 5217 device_printf(devinfo->codec->sc->dev, 5218 " Disabling nid %d connection %d due" 5219 " to disabled child widget.\n", 5220 i, j); 5221 ); 5222 } 5223 } 5224 } 5225 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5226 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5227 continue; 5228 /* Disable mixers and selectors without inputs. */ 5229 found = 0; 5230 for (j = 0; j < w->nconns; j++) { 5231 if (w->connsenable[j]) { 5232 found = 1; 5233 break; 5234 } 5235 } 5236 if (found == 0) { 5237 w->enable = 0; 5238 done = 0; 5239 HDA_BOOTHVERBOSE( 5240 device_printf(devinfo->codec->sc->dev, 5241 " Disabling nid %d due to all it's" 5242 " inputs disabled.\n", w->nid); 5243 ); 5244 } 5245 /* Disable nodes without consumers. */ 5246 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5247 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5248 continue; 5249 found = 0; 5250 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5251 cw = hdac_widget_get(devinfo, k); 5252 if (cw == NULL || cw->enable == 0) 5253 continue; 5254 for (j = 0; j < cw->nconns; j++) { 5255 if (cw->connsenable[j] && cw->conns[j] == i) { 5256 found = 1; 5257 break; 5258 } 5259 } 5260 } 5261 if (found == 0) { 5262 w->enable = 0; 5263 done = 0; 5264 HDA_BOOTHVERBOSE( 5265 device_printf(devinfo->codec->sc->dev, 5266 " Disabling nid %d due to all it's" 5267 " consumers disabled.\n", w->nid); 5268 ); 5269 } 5270 } 5271 } while (done == 0); 5272 5273} 5274 5275static void 5276hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5277{ 5278 struct hdac_audio_as *as = devinfo->function.audio.as; 5279 struct hdac_widget *w, *cw; 5280 struct hdac_audio_ctl *ctl; 5281 int i, j, k; 5282 5283 /* Disable unassosiated widgets. */ 5284 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5285 w = hdac_widget_get(devinfo, i); 5286 if (w == NULL || w->enable == 0) 5287 continue; 5288 if (w->bindas == -1) { 5289 w->enable = 0; 5290 HDA_BOOTHVERBOSE( 5291 device_printf(devinfo->codec->sc->dev, 5292 " Disabling unassociated nid %d.\n", 5293 w->nid); 5294 ); 5295 } 5296 } 5297 /* Disable input connections on input pin and 5298 * output on output. */ 5299 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5300 w = hdac_widget_get(devinfo, i); 5301 if (w == NULL || w->enable == 0) 5302 continue; 5303 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5304 continue; 5305 if (w->bindas < 0) 5306 continue; 5307 if (as[w->bindas].dir == HDA_CTL_IN) { 5308 for (j = 0; j < w->nconns; j++) { 5309 if (w->connsenable[j] == 0) 5310 continue; 5311 w->connsenable[j] = 0; 5312 HDA_BOOTHVERBOSE( 5313 device_printf(devinfo->codec->sc->dev, 5314 " Disabling connection to input pin " 5315 "nid %d conn %d.\n", 5316 i, j); 5317 ); 5318 } 5319 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5320 HDA_CTL_IN, -1, 1); 5321 if (ctl && ctl->enable) { 5322 ctl->forcemute = 1; 5323 ctl->muted = HDA_AMP_MUTE_ALL; 5324 ctl->left = 0; 5325 ctl->right = 0; 5326 ctl->enable = 0; 5327 } 5328 } else { 5329 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5330 HDA_CTL_OUT, -1, 1); 5331 if (ctl && ctl->enable) { 5332 ctl->forcemute = 1; 5333 ctl->muted = HDA_AMP_MUTE_ALL; 5334 ctl->left = 0; 5335 ctl->right = 0; 5336 ctl->enable = 0; 5337 } 5338 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5339 cw = hdac_widget_get(devinfo, k); 5340 if (cw == NULL || cw->enable == 0) 5341 continue; 5342 for (j = 0; j < cw->nconns; j++) { 5343 if (cw->connsenable[j] && cw->conns[j] == i) { 5344 cw->connsenable[j] = 0; 5345 HDA_BOOTHVERBOSE( 5346 device_printf(devinfo->codec->sc->dev, 5347 " Disabling connection from output pin " 5348 "nid %d conn %d cnid %d.\n", 5349 k, j, i); 5350 ); 5351 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5352 cw->nconns > 1) 5353 continue; 5354 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5355 HDA_CTL_IN, j, 1); 5356 if (ctl && ctl->enable) { 5357 ctl->forcemute = 1; 5358 ctl->muted = HDA_AMP_MUTE_ALL; 5359 ctl->left = 0; 5360 ctl->right = 0; 5361 ctl->enable = 0; 5362 } 5363 } 5364 } 5365 } 5366 } 5367 } 5368} 5369 5370static void 5371hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5372{ 5373 struct hdac_audio_as *as = devinfo->function.audio.as; 5374 struct hdac_widget *w; 5375 int i, j; 5376 5377 /* On playback path we can safely disable all unseleted inputs. */ 5378 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5379 w = hdac_widget_get(devinfo, i); 5380 if (w == NULL || w->enable == 0) 5381 continue; 5382 if (w->nconns <= 1) 5383 continue; 5384 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5385 continue; 5386 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5387 continue; 5388 for (j = 0; j < w->nconns; j++) { 5389 if (w->connsenable[j] == 0) 5390 continue; 5391 if (w->selconn < 0 || w->selconn == j) 5392 continue; 5393 w->connsenable[j] = 0; 5394 HDA_BOOTHVERBOSE( 5395 device_printf(devinfo->codec->sc->dev, 5396 " Disabling unselected connection " 5397 "nid %d conn %d.\n", 5398 i, j); 5399 ); 5400 } 5401 } 5402} 5403 5404static void 5405hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5406{ 5407 struct hdac_widget *w, *cw; 5408 struct hdac_audio_ctl *ctl; 5409 int i, j; 5410 5411 /* Disable crossassociatement connections. */ 5412 /* ... using selectors */ 5413 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5414 w = hdac_widget_get(devinfo, i); 5415 if (w == NULL || w->enable == 0) 5416 continue; 5417 if (w->nconns <= 1) 5418 continue; 5419 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5420 continue; 5421 if (w->bindas == -2) 5422 continue; 5423 for (j = 0; j < w->nconns; j++) { 5424 if (w->connsenable[j] == 0) 5425 continue; 5426 cw = hdac_widget_get(devinfo, w->conns[j]); 5427 if (cw == NULL || w->enable == 0) 5428 continue; 5429 if (w->bindas == cw->bindas || cw->bindas == -2) 5430 continue; 5431 w->connsenable[j] = 0; 5432 HDA_BOOTHVERBOSE( 5433 device_printf(devinfo->codec->sc->dev, 5434 " Disabling crossassociatement connection " 5435 "nid %d conn %d cnid %d.\n", 5436 i, j, cw->nid); 5437 ); 5438 } 5439 } 5440 /* ... using controls */ 5441 i = 0; 5442 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5443 if (ctl->enable == 0 || ctl->childwidget == NULL) 5444 continue; 5445 if (ctl->widget->bindas == -2 || 5446 ctl->childwidget->bindas == -2) 5447 continue; 5448 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5449 ctl->forcemute = 1; 5450 ctl->muted = HDA_AMP_MUTE_ALL; 5451 ctl->left = 0; 5452 ctl->right = 0; 5453 ctl->enable = 0; 5454 if (ctl->ndir == HDA_CTL_IN) 5455 ctl->widget->connsenable[ctl->index] = 0; 5456 HDA_BOOTHVERBOSE( 5457 device_printf(devinfo->codec->sc->dev, 5458 " Disabling crossassociatement connection " 5459 "ctl %d nid %d cnid %d.\n", i, 5460 ctl->widget->nid, 5461 ctl->childwidget->nid); 5462 ); 5463 } 5464 } 5465 5466} 5467 5468#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5469 5470/* 5471 * Find controls to control amplification for source. 5472 */ 5473static int 5474hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5475 int ossdev, int ctlable, int depth, int need) 5476{ 5477 struct hdac_widget *w, *wc; 5478 struct hdac_audio_ctl *ctl; 5479 int i, j, conns = 0, rneed; 5480 5481 if (depth > HDA_PARSE_MAXDEPTH) 5482 return (need); 5483 5484 w = hdac_widget_get(devinfo, nid); 5485 if (w == NULL || w->enable == 0) 5486 return (need); 5487 5488 /* Count number of active inputs. */ 5489 if (depth > 0) { 5490 for (j = 0; j < w->nconns; j++) { 5491 if (w->connsenable[j]) 5492 conns++; 5493 } 5494 } 5495 5496 /* If this is not a first step - use input mixer. 5497 Pins have common input ctl so care must be taken. */ 5498 if (depth > 0 && ctlable && (conns == 1 || 5499 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5500 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5501 index, 1); 5502 if (ctl) { 5503 if (HDA_CTL_GIVE(ctl) & need) 5504 ctl->ossmask |= (1 << ossdev); 5505 else 5506 ctl->possmask |= (1 << ossdev); 5507 need &= ~HDA_CTL_GIVE(ctl); 5508 } 5509 } 5510 5511 /* If widget has own ossdev - not traverse it. 5512 It will be traversed on it's own. */ 5513 if (w->ossdev >= 0 && depth > 0) 5514 return (need); 5515 5516 /* We must not traverse pin */ 5517 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5518 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5519 depth > 0) 5520 return (need); 5521 5522 /* record that this widget exports such signal, */ 5523 w->ossmask |= (1 << ossdev); 5524 5525 /* If signals mixed, we can't assign controls farther. 5526 * Ignore this on depth zero. Caller must knows why. 5527 * Ignore this for static selectors if this input selected. 5528 */ 5529 if (conns > 1) 5530 ctlable = 0; 5531 5532 if (ctlable) { 5533 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5534 if (ctl) { 5535 if (HDA_CTL_GIVE(ctl) & need) 5536 ctl->ossmask |= (1 << ossdev); 5537 else 5538 ctl->possmask |= (1 << ossdev); 5539 need &= ~HDA_CTL_GIVE(ctl); 5540 } 5541 } 5542 5543 rneed = 0; 5544 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5545 wc = hdac_widget_get(devinfo, i); 5546 if (wc == NULL || wc->enable == 0) 5547 continue; 5548 for (j = 0; j < wc->nconns; j++) { 5549 if (wc->connsenable[j] && wc->conns[j] == nid) { 5550 rneed |= hdac_audio_ctl_source_amp(devinfo, 5551 wc->nid, j, ossdev, ctlable, depth + 1, need); 5552 } 5553 } 5554 } 5555 rneed &= need; 5556 5557 return (rneed); 5558} 5559 5560/* 5561 * Find controls to control amplification for destination. 5562 */ 5563static void 5564hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5565 int ossdev, int depth, int need) 5566{ 5567 struct hdac_audio_as *as = devinfo->function.audio.as; 5568 struct hdac_widget *w, *wc; 5569 struct hdac_audio_ctl *ctl; 5570 int i, j, consumers; 5571 5572 if (depth > HDA_PARSE_MAXDEPTH) 5573 return; 5574 5575 w = hdac_widget_get(devinfo, nid); 5576 if (w == NULL || w->enable == 0) 5577 return; 5578 5579 if (depth > 0) { 5580 /* If this node produce output for several consumers, 5581 we can't touch it. */ 5582 consumers = 0; 5583 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5584 wc = hdac_widget_get(devinfo, i); 5585 if (wc == NULL || wc->enable == 0) 5586 continue; 5587 for (j = 0; j < wc->nconns; j++) { 5588 if (wc->connsenable[j] && wc->conns[j] == nid) 5589 consumers++; 5590 } 5591 } 5592 /* The only exception is if real HP redirection is configured 5593 and this is a duplication point. 5594 XXX: Actually exception is not completely correct. 5595 XXX: Duplication point check is not perfect. */ 5596 if ((consumers == 2 && (w->bindas < 0 || 5597 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5598 (w->bindseqmask & (1 << 15)) == 0)) || 5599 consumers > 2) 5600 return; 5601 5602 /* Else use it's output mixer. */ 5603 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5604 HDA_CTL_OUT, -1, 1); 5605 if (ctl) { 5606 if (HDA_CTL_GIVE(ctl) & need) 5607 ctl->ossmask |= (1 << ossdev); 5608 else 5609 ctl->possmask |= (1 << ossdev); 5610 need &= ~HDA_CTL_GIVE(ctl); 5611 } 5612 } 5613 5614 /* We must not traverse pin */ 5615 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5616 depth > 0) 5617 return; 5618 5619 for (i = 0; i < w->nconns; i++) { 5620 int tneed = need; 5621 if (w->connsenable[i] == 0) 5622 continue; 5623 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5624 HDA_CTL_IN, i, 1); 5625 if (ctl) { 5626 if (HDA_CTL_GIVE(ctl) & tneed) 5627 ctl->ossmask |= (1 << ossdev); 5628 else 5629 ctl->possmask |= (1 << ossdev); 5630 tneed &= ~HDA_CTL_GIVE(ctl); 5631 } 5632 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5633 depth + 1, tneed); 5634 } 5635} 5636 5637/* 5638 * Assign OSS names to sound sources 5639 */ 5640static void 5641hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5642{ 5643 struct hdac_audio_as *as = devinfo->function.audio.as; 5644 struct hdac_widget *w; 5645 int i, j; 5646 int type = -1, use, used = 0; 5647 static const int types[7][13] = { 5648 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5649 SOUND_MIXER_LINE3, -1 }, /* line */ 5650 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5651 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5652 { SOUND_MIXER_CD, -1 }, /* cd */ 5653 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5654 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5655 -1 }, /* digital */ 5656 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5657 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5658 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5659 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5660 -1 } /* others */ 5661 }; 5662 5663 /* Surely known names */ 5664 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5665 w = hdac_widget_get(devinfo, i); 5666 if (w == NULL || w->enable == 0) 5667 continue; 5668 if (w->bindas == -1) 5669 continue; 5670 use = -1; 5671 switch (w->type) { 5672 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5673 if (as[w->bindas].dir == HDA_CTL_OUT) 5674 break; 5675 type = -1; 5676 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5677 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5678 type = 0; 5679 break; 5680 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5681 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5682 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5683 break; 5684 type = 1; 5685 break; 5686 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5687 type = 3; 5688 break; 5689 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5690 type = 4; 5691 break; 5692 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5693 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5694 type = 5; 5695 break; 5696 } 5697 if (type == -1) 5698 break; 5699 j = 0; 5700 while (types[type][j] >= 0 && 5701 (used & (1 << types[type][j])) != 0) { 5702 j++; 5703 } 5704 if (types[type][j] >= 0) 5705 use = types[type][j]; 5706 break; 5707 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5708 use = SOUND_MIXER_PCM; 5709 break; 5710 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5711 use = SOUND_MIXER_SPEAKER; 5712 break; 5713 default: 5714 break; 5715 } 5716 if (use >= 0) { 5717 w->ossdev = use; 5718 used |= (1 << use); 5719 } 5720 } 5721 /* Semi-known names */ 5722 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5723 w = hdac_widget_get(devinfo, i); 5724 if (w == NULL || w->enable == 0) 5725 continue; 5726 if (w->ossdev >= 0) 5727 continue; 5728 if (w->bindas == -1) 5729 continue; 5730 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5731 continue; 5732 if (as[w->bindas].dir == HDA_CTL_OUT) 5733 continue; 5734 type = -1; 5735 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5736 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5737 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5738 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5739 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5740 type = 0; 5741 break; 5742 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5743 type = 2; 5744 break; 5745 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5746 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5747 type = 5; 5748 break; 5749 } 5750 if (type == -1) 5751 break; 5752 j = 0; 5753 while (types[type][j] >= 0 && 5754 (used & (1 << types[type][j])) != 0) { 5755 j++; 5756 } 5757 if (types[type][j] >= 0) { 5758 w->ossdev = types[type][j]; 5759 used |= (1 << types[type][j]); 5760 } 5761 } 5762 /* Others */ 5763 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5764 w = hdac_widget_get(devinfo, i); 5765 if (w == NULL || w->enable == 0) 5766 continue; 5767 if (w->ossdev >= 0) 5768 continue; 5769 if (w->bindas == -1) 5770 continue; 5771 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5772 continue; 5773 if (as[w->bindas].dir == HDA_CTL_OUT) 5774 continue; 5775 j = 0; 5776 while (types[6][j] >= 0 && 5777 (used & (1 << types[6][j])) != 0) { 5778 j++; 5779 } 5780 if (types[6][j] >= 0) { 5781 w->ossdev = types[6][j]; 5782 used |= (1 << types[6][j]); 5783 } 5784 } 5785} 5786 5787static void 5788hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5789{ 5790 struct hdac_audio_as *as = devinfo->function.audio.as; 5791 int j, res; 5792 5793 /* Trace all associations in order of their numbers, */ 5794 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5795 if (as[j].enable == 0) 5796 continue; 5797 HDA_BOOTVERBOSE( 5798 device_printf(devinfo->codec->sc->dev, 5799 "Tracing association %d (%d)\n", j, as[j].index); 5800 ); 5801 if (as[j].dir == HDA_CTL_OUT) { 5802retry: 5803 res = hdac_audio_trace_as_out(devinfo, j, 0); 5804 if (res == 0 && as[j].hpredir >= 0 && 5805 as[j].fakeredir == 0) { 5806 /* If codec can't do analog HP redirection 5807 try to make it using one more DAC. */ 5808 as[j].fakeredir = 1; 5809 goto retry; 5810 } 5811 } else { 5812 res = hdac_audio_trace_as_in(devinfo, j); 5813 } 5814 if (res) { 5815 HDA_BOOTVERBOSE( 5816 device_printf(devinfo->codec->sc->dev, 5817 "Association %d (%d) trace succeded\n", 5818 j, as[j].index); 5819 ); 5820 } else { 5821 HDA_BOOTVERBOSE( 5822 device_printf(devinfo->codec->sc->dev, 5823 "Association %d (%d) trace failed\n", 5824 j, as[j].index); 5825 ); 5826 as[j].enable = 0; 5827 } 5828 } 5829 5830 /* Trace mixer and beeper pseudo associations. */ 5831 hdac_audio_trace_as_extra(devinfo); 5832} 5833 5834static void 5835hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5836{ 5837 struct hdac_audio_as *as = devinfo->function.audio.as; 5838 struct hdac_audio_ctl *ctl; 5839 struct hdac_widget *w; 5840 int i; 5841 5842 /* Assign mixers to the tree. */ 5843 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5844 w = hdac_widget_get(devinfo, i); 5845 if (w == NULL || w->enable == 0) 5846 continue; 5847 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5848 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5849 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5850 as[w->bindas].dir == HDA_CTL_IN)) { 5851 if (w->ossdev < 0) 5852 continue; 5853 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5854 w->ossdev, 1, 0, 1); 5855 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5856 if (w->ossdev < 0) 5857 continue; 5858 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5859 w->ossdev, 1, 0, 1)) { 5860 /* If we are unable to control input monitor 5861 as source - try to control it as destination. */ 5862 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5863 w->ossdev, 0, 1); 5864 } 5865 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5866 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5867 SOUND_MIXER_RECLEV, 0, 1); 5868 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5869 as[w->bindas].dir == HDA_CTL_OUT) { 5870 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5871 SOUND_MIXER_VOLUME, 0, 1); 5872 } 5873 } 5874 /* Treat unrequired as possible. */ 5875 i = 0; 5876 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5877 if (ctl->ossmask == 0) 5878 ctl->ossmask = ctl->possmask; 5879 } 5880} 5881 5882static void 5883hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5884{ 5885 struct hdac_audio_as *as = devinfo->function.audio.as; 5886 struct hdac_widget *w; 5887 uint32_t pincap; 5888 int i; 5889 5890 for (i = 0; i < devinfo->nodecnt; i++) { 5891 w = &devinfo->widget[i]; 5892 if (w == NULL) 5893 continue; 5894 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5895 continue; 5896 5897 pincap = w->wclass.pin.cap; 5898 5899 /* Disable everything. */ 5900 w->wclass.pin.ctrl &= ~( 5901 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5902 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5903 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5904 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5905 5906 if (w->enable == 0 || 5907 w->bindas < 0 || as[w->bindas].enable == 0) { 5908 /* Pin is unused so left it disabled. */ 5909 continue; 5910 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5911 /* Input pin, configure for input. */ 5912 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5913 w->wclass.pin.ctrl |= 5914 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5915 5916 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5917 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5918 w->wclass.pin.ctrl |= 5919 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5920 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5921 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5922 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5923 w->wclass.pin.ctrl |= 5924 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5925 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5926 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5927 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5928 w->wclass.pin.ctrl |= 5929 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5930 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5931 } else { 5932 /* Output pin, configure for output. */ 5933 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5934 w->wclass.pin.ctrl |= 5935 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5936 5937 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5938 (w->wclass.pin.config & 5939 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5940 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5941 w->wclass.pin.ctrl |= 5942 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5943 5944 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5945 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5946 w->wclass.pin.ctrl |= 5947 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5948 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5949 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5950 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5951 w->wclass.pin.ctrl |= 5952 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5953 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5954 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5955 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5956 w->wclass.pin.ctrl |= 5957 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5958 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5959 } 5960 } 5961} 5962 5963static void 5964hdac_audio_commit(struct hdac_devinfo *devinfo) 5965{ 5966 struct hdac_softc *sc = devinfo->codec->sc; 5967 struct hdac_widget *w; 5968 nid_t cad; 5969 uint32_t gdata, gmask, gdir; 5970 int commitgpio, numgpio; 5971 int i; 5972 5973 cad = devinfo->codec->cad; 5974 5975 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5976 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5977 0x7e7, 0), cad); 5978 5979 gdata = 0; 5980 gmask = 0; 5981 gdir = 0; 5982 commitgpio = 0; 5983 5984 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5985 devinfo->function.audio.gpio); 5986 5987 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5988 commitgpio = (numgpio > 0) ? 1 : 0; 5989 else { 5990 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5991 if (!(devinfo->function.audio.quirks & 5992 (1 << i))) 5993 continue; 5994 if (commitgpio == 0) { 5995 commitgpio = 1; 5996 HDA_BOOTVERBOSE( 5997 gdata = hdac_command(sc, 5998 HDA_CMD_GET_GPIO_DATA(cad, 5999 devinfo->nid), cad); 6000 gmask = hdac_command(sc, 6001 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6002 devinfo->nid), cad); 6003 gdir = hdac_command(sc, 6004 HDA_CMD_GET_GPIO_DIRECTION(cad, 6005 devinfo->nid), cad); 6006 device_printf(sc->dev, 6007 "GPIO init: data=0x%08x " 6008 "mask=0x%08x dir=0x%08x\n", 6009 gdata, gmask, gdir); 6010 gdata = 0; 6011 gmask = 0; 6012 gdir = 0; 6013 ); 6014 } 6015 gdata |= 1 << i; 6016 gmask |= 1 << i; 6017 gdir |= 1 << i; 6018 } 6019 } 6020 6021 if (commitgpio != 0) { 6022 HDA_BOOTVERBOSE( 6023 device_printf(sc->dev, 6024 "GPIO commit: data=0x%08x mask=0x%08x " 6025 "dir=0x%08x\n", 6026 gdata, gmask, gdir); 6027 ); 6028 hdac_command(sc, 6029 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6030 gmask), cad); 6031 hdac_command(sc, 6032 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6033 gdir), cad); 6034 hdac_command(sc, 6035 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6036 gdata), cad); 6037 } 6038 6039 for (i = 0; i < devinfo->nodecnt; i++) { 6040 w = &devinfo->widget[i]; 6041 if (w == NULL) 6042 continue; 6043 if (w->selconn == -1) 6044 w->selconn = 0; 6045 if (w->nconns > 0) 6046 hdac_widget_connection_select(w, w->selconn); 6047 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6048 hdac_command(sc, 6049 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6050 w->wclass.pin.ctrl), cad); 6051 } 6052 if (w->param.eapdbtl != HDAC_INVALID) { 6053 uint32_t val; 6054 6055 val = w->param.eapdbtl; 6056 if (devinfo->function.audio.quirks & 6057 HDA_QUIRK_EAPDINV) 6058 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6059 hdac_command(sc, 6060 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6061 val), cad); 6062 6063 } 6064 } 6065} 6066 6067static void 6068hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6069{ 6070 struct hdac_audio_ctl *ctl; 6071 int i, z; 6072 6073 i = 0; 6074 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6075 if (ctl->enable == 0) { 6076 /* Mute disabled controls. */ 6077 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6078 continue; 6079 } 6080 /* Init controls to 0dB amplification. */ 6081 z = ctl->offset; 6082 if (z > ctl->step) 6083 z = ctl->step; 6084 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6085 } 6086} 6087 6088static void 6089hdac_powerup(struct hdac_devinfo *devinfo) 6090{ 6091 struct hdac_softc *sc = devinfo->codec->sc; 6092 nid_t cad = devinfo->codec->cad; 6093 int i; 6094 6095 hdac_command(sc, 6096 HDA_CMD_SET_POWER_STATE(cad, 6097 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6098 cad); 6099 DELAY(100); 6100 6101 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6102 hdac_command(sc, 6103 HDA_CMD_SET_POWER_STATE(cad, 6104 i, HDA_CMD_POWER_STATE_D0), 6105 cad); 6106 } 6107 DELAY(1000); 6108} 6109 6110static int 6111hdac_pcmchannel_setup(struct hdac_chan *ch) 6112{ 6113 struct hdac_devinfo *devinfo = ch->devinfo; 6114 struct hdac_audio_as *as = devinfo->function.audio.as; 6115 struct hdac_widget *w; 6116 uint32_t cap, fmtcap, pcmcap; 6117 int i, j, ret, max; 6118 6119 ch->caps = hdac_caps; 6120 ch->caps.fmtlist = ch->fmtlist; 6121 ch->bit16 = 1; 6122 ch->bit32 = 0; 6123 ch->pcmrates[0] = 48000; 6124 ch->pcmrates[1] = 0; 6125 6126 ret = 0; 6127 fmtcap = devinfo->function.audio.supp_stream_formats; 6128 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6129 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6130 6131 for (i = 0; i < 16 && ret < max; i++) { 6132 /* Check as is correct */ 6133 if (ch->as < 0) 6134 break; 6135 /* Cound only present DACs */ 6136 if (as[ch->as].dacs[i] <= 0) 6137 continue; 6138 /* Ignore duplicates */ 6139 for (j = 0; j < ret; j++) { 6140 if (ch->io[j] == as[ch->as].dacs[i]) 6141 break; 6142 } 6143 if (j < ret) 6144 continue; 6145 6146 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6147 if (w == NULL || w->enable == 0) 6148 continue; 6149 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6150 continue; 6151 cap = w->param.supp_stream_formats; 6152 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6153 }*/ 6154 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6155 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6156 continue; 6157 /* Many codec does not declare AC3 support on SPDIF. 6158 I don't beleave that they doesn't support it! */ 6159 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6160 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6161 if (ret == 0) { 6162 fmtcap = cap; 6163 pcmcap = w->param.supp_pcm_size_rate; 6164 } else { 6165 fmtcap &= cap; 6166 pcmcap &= w->param.supp_pcm_size_rate; 6167 } 6168 ch->io[ret++] = as[ch->as].dacs[i]; 6169 } 6170 ch->io[ret] = -1; 6171 6172 ch->supp_stream_formats = fmtcap; 6173 ch->supp_pcm_size_rate = pcmcap; 6174 6175 /* 6176 * 8bit = 0 6177 * 16bit = 1 6178 * 20bit = 2 6179 * 24bit = 3 6180 * 32bit = 4 6181 */ 6182 if (ret > 0) { 6183 i = 0; 6184 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6185 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6186 ch->bit16 = 1; 6187 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6188 ch->bit16 = 0; 6189 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6190 ch->bit32 = 4; 6191 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6192 ch->bit32 = 3; 6193 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6194 ch->bit32 = 2; 6195 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6196 ch->fmtlist[i++] = AFMT_S16_LE; 6197 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6198 if (ch->bit32 > 0) { 6199 if (!(devinfo->function.audio.quirks & 6200 HDA_QUIRK_FORCESTEREO)) 6201 ch->fmtlist[i++] = AFMT_S32_LE; 6202 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6203 } 6204 } 6205 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6206 ch->fmtlist[i++] = AFMT_AC3; 6207 } 6208 ch->fmtlist[i] = 0; 6209 i = 0; 6210 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6211 ch->pcmrates[i++] = 8000; 6212 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6213 ch->pcmrates[i++] = 11025; 6214 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6215 ch->pcmrates[i++] = 16000; 6216 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6217 ch->pcmrates[i++] = 22050; 6218 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6219 ch->pcmrates[i++] = 32000; 6220 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6221 ch->pcmrates[i++] = 44100; 6222 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6223 ch->pcmrates[i++] = 48000; 6224 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6225 ch->pcmrates[i++] = 88200; 6226 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6227 ch->pcmrates[i++] = 96000; 6228 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6229 ch->pcmrates[i++] = 176400; 6230 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6231 ch->pcmrates[i++] = 192000; 6232 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6233 ch->pcmrates[i] = 0; 6234 if (i > 0) { 6235 ch->caps.minspeed = ch->pcmrates[0]; 6236 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6237 } 6238 } 6239 6240 return (ret); 6241} 6242 6243static void 6244hdac_create_pcms(struct hdac_devinfo *devinfo) 6245{ 6246 struct hdac_softc *sc = devinfo->codec->sc; 6247 struct hdac_audio_as *as = devinfo->function.audio.as; 6248 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6249 6250 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6251 if (as[i].enable == 0) 6252 continue; 6253 if (as[i].dir == HDA_CTL_IN) { 6254 if (as[i].digital) 6255 drdev++; 6256 else 6257 ardev++; 6258 } else { 6259 if (as[i].digital) 6260 dpdev++; 6261 else 6262 apdev++; 6263 } 6264 } 6265 devinfo->function.audio.num_devs = 6266 max(ardev, apdev) + max(drdev, dpdev); 6267 devinfo->function.audio.devs = 6268 (struct hdac_pcm_devinfo *)malloc( 6269 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6270 M_HDAC, M_ZERO | M_NOWAIT); 6271 if (devinfo->function.audio.devs == NULL) { 6272 device_printf(sc->dev, 6273 "Unable to allocate memory for devices\n"); 6274 return; 6275 } 6276 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6277 devinfo->function.audio.devs[i].index = i; 6278 devinfo->function.audio.devs[i].devinfo = devinfo; 6279 devinfo->function.audio.devs[i].play = -1; 6280 devinfo->function.audio.devs[i].rec = -1; 6281 devinfo->function.audio.devs[i].digital = 2; 6282 } 6283 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6284 if (as[i].enable == 0) 6285 continue; 6286 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6287 if (devinfo->function.audio.devs[j].digital != 2 && 6288 devinfo->function.audio.devs[j].digital != 6289 as[i].digital) 6290 continue; 6291 if (as[i].dir == HDA_CTL_IN) { 6292 if (devinfo->function.audio.devs[j].rec >= 0) 6293 continue; 6294 devinfo->function.audio.devs[j].rec 6295 = as[i].chan; 6296 } else { 6297 if (devinfo->function.audio.devs[j].play >= 0) 6298 continue; 6299 devinfo->function.audio.devs[j].play 6300 = as[i].chan; 6301 } 6302 sc->chans[as[i].chan].pdevinfo = 6303 &devinfo->function.audio.devs[j]; 6304 devinfo->function.audio.devs[j].digital = 6305 as[i].digital; 6306 break; 6307 } 6308 } 6309 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6310 struct hdac_pcm_devinfo *pdevinfo = 6311 &devinfo->function.audio.devs[i]; 6312 pdevinfo->dev = 6313 device_add_child(sc->dev, "pcm", -1); 6314 device_set_ivars(pdevinfo->dev, 6315 (void *)pdevinfo); 6316 } 6317} 6318 6319static void 6320hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6321{ 6322 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6323 struct hdac_audio_ctl *ctl; 6324 struct hdac_softc *sc = devinfo->codec->sc; 6325 char buf[64]; 6326 int i, j, printed; 6327 6328 if (flag == 0) { 6329 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6330 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6331 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6332 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6333 } 6334 6335 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6336 if ((flag & (1 << j)) == 0) 6337 continue; 6338 i = 0; 6339 printed = 0; 6340 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6341 if (ctl->enable == 0 || 6342 ctl->widget->enable == 0) 6343 continue; 6344 if (!((pdevinfo->play >= 0 && 6345 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6346 (pdevinfo->rec >= 0 && 6347 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6348 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6349 continue; 6350 if ((ctl->ossmask & (1 << j)) == 0) 6351 continue; 6352 6353 if (printed == 0) { 6354 device_printf(pdevinfo->dev, "\n"); 6355 if (banner != NULL) { 6356 device_printf(pdevinfo->dev, "%s", banner); 6357 } else { 6358 device_printf(pdevinfo->dev, "Unknown Ctl"); 6359 } 6360 printf(" (OSS: %s)\n", 6361 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6362 buf, sizeof(buf))); 6363 device_printf(pdevinfo->dev, " |\n"); 6364 printed = 1; 6365 } 6366 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6367 ctl->widget->nid, 6368 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6369 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6370 printf(" %2d): ", ctl->index); 6371 else 6372 printf("): "); 6373 if (ctl->step > 0) { 6374 printf("%+d/%+ddB (%d steps)%s\n", 6375 (0 - ctl->offset) * (ctl->size + 1) / 4, 6376 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6377 ctl->step + 1, 6378 ctl->mute?" + mute":""); 6379 } else 6380 printf("%s\n", ctl->mute?"mute":""); 6381 } 6382 } 6383} 6384 6385static void 6386hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6387{ 6388 uint32_t cap; 6389 6390 cap = fcap; 6391 if (cap != 0) { 6392 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6393 device_printf(dev, " "); 6394 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6395 printf(" AC3"); 6396 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6397 printf(" FLOAT32"); 6398 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6399 printf(" PCM"); 6400 printf("\n"); 6401 } 6402 cap = pcmcap; 6403 if (cap != 0) { 6404 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6405 device_printf(dev, " "); 6406 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6407 printf(" 8"); 6408 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6409 printf(" 16"); 6410 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6411 printf(" 20"); 6412 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6413 printf(" 24"); 6414 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6415 printf(" 32"); 6416 printf(" bits,"); 6417 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6418 printf(" 8"); 6419 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6420 printf(" 11"); 6421 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6422 printf(" 16"); 6423 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6424 printf(" 22"); 6425 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6426 printf(" 32"); 6427 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6428 printf(" 44"); 6429 printf(" 48"); 6430 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6431 printf(" 88"); 6432 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6433 printf(" 96"); 6434 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6435 printf(" 176"); 6436 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6437 printf(" 192"); 6438 printf(" KHz\n"); 6439 } 6440} 6441 6442static void 6443hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6444{ 6445 uint32_t pincap; 6446 6447 pincap = w->wclass.pin.cap; 6448 6449 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6450 device_printf(sc->dev, " "); 6451 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6452 printf(" ISC"); 6453 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6454 printf(" TRQD"); 6455 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6456 printf(" PDC"); 6457 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6458 printf(" HP"); 6459 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6460 printf(" OUT"); 6461 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6462 printf(" IN"); 6463 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6464 printf(" BAL"); 6465 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6466 printf(" VREF["); 6467 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6468 printf(" 50"); 6469 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6470 printf(" 80"); 6471 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6472 printf(" 100"); 6473 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6474 printf(" GROUND"); 6475 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6476 printf(" HIZ"); 6477 printf(" ]"); 6478 } 6479 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6480 printf(" EAPD"); 6481 printf("\n"); 6482 device_printf(sc->dev, " Pin config: 0x%08x\n", 6483 w->wclass.pin.config); 6484 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6485 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6486 printf(" HP"); 6487 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6488 printf(" IN"); 6489 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6490 printf(" OUT"); 6491 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6492 printf(" VREFs"); 6493 printf("\n"); 6494} 6495 6496static void 6497hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6498{ 6499 struct hdac_softc *sc = w->devinfo->codec->sc; 6500 6501 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6502 "jack %2d loc %2d color %7s misc %d%s\n", 6503 w->nid, conf, 6504 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6505 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6506 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6507 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6508 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6509 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6510 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6511 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6512 (w->enable == 0)?" [DISABLED]":""); 6513} 6514 6515static void 6516hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6517{ 6518 struct hdac_widget *w; 6519 int i; 6520 6521 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6522 w = hdac_widget_get(devinfo, i); 6523 if (w == NULL) 6524 continue; 6525 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6526 continue; 6527 hdac_dump_pin_config(w, w->wclass.pin.config); 6528 } 6529} 6530 6531static void 6532hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6533{ 6534 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6535 device_printf(sc->dev, " " 6536 "mute=%d step=%d size=%d offset=%d\n", 6537 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6538 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6539 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6540 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6541} 6542 6543static void 6544hdac_dump_nodes(struct hdac_devinfo *devinfo) 6545{ 6546 struct hdac_softc *sc = devinfo->codec->sc; 6547 static char *ossname[] = SOUND_DEVICE_NAMES; 6548 struct hdac_widget *w, *cw; 6549 char buf[64]; 6550 int i, j; 6551 6552 device_printf(sc->dev, "\n"); 6553 device_printf(sc->dev, "Default Parameter\n"); 6554 device_printf(sc->dev, "-----------------\n"); 6555 hdac_dump_audio_formats(sc->dev, 6556 devinfo->function.audio.supp_stream_formats, 6557 devinfo->function.audio.supp_pcm_size_rate); 6558 device_printf(sc->dev, " IN amp: 0x%08x\n", 6559 devinfo->function.audio.inamp_cap); 6560 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6561 devinfo->function.audio.outamp_cap); 6562 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6563 w = hdac_widget_get(devinfo, i); 6564 if (w == NULL) { 6565 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6566 continue; 6567 } 6568 device_printf(sc->dev, "\n"); 6569 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6570 (w->enable == 0) ? " [DISABLED]" : ""); 6571 device_printf(sc->dev, " Name: %s\n", w->name); 6572 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6573 w->param.widget_cap); 6574 if (w->param.widget_cap & 0x0ee1) { 6575 device_printf(sc->dev, " "); 6576 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6577 printf(" LRSWAP"); 6578 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6579 printf(" PWR"); 6580 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6581 printf(" DIGITAL"); 6582 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6583 printf(" UNSOL"); 6584 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6585 printf(" PROC"); 6586 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6587 printf(" STRIPE"); 6588 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6589 printf(" STEREO"); 6590 printf("\n"); 6591 } 6592 if (w->bindas != -1) { 6593 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6594 w->bindas, w->bindseqmask); 6595 } 6596 if (w->ossmask != 0 || w->ossdev >= 0) { 6597 device_printf(sc->dev, " OSS: %s", 6598 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6599 if (w->ossdev >= 0) 6600 printf(" (%s)", ossname[w->ossdev]); 6601 printf("\n"); 6602 } 6603 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6604 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6605 hdac_dump_audio_formats(sc->dev, 6606 w->param.supp_stream_formats, 6607 w->param.supp_pcm_size_rate); 6608 } else if (w->type == 6609 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6610 hdac_dump_pin(sc, w); 6611 if (w->param.eapdbtl != HDAC_INVALID) 6612 device_printf(sc->dev, " EAPD: 0x%08x\n", 6613 w->param.eapdbtl); 6614 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6615 w->param.outamp_cap != 0) 6616 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6617 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6618 w->param.inamp_cap != 0) 6619 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6620 if (w->nconns > 0) { 6621 device_printf(sc->dev, " connections: %d\n", w->nconns); 6622 device_printf(sc->dev, " |\n"); 6623 } 6624 for (j = 0; j < w->nconns; j++) { 6625 cw = hdac_widget_get(devinfo, w->conns[j]); 6626 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6627 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6628 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6629 if (cw == NULL) 6630 printf(" [UNKNOWN]"); 6631 else if (cw->enable == 0) 6632 printf(" [DISABLED]"); 6633 if (w->nconns > 1 && w->selconn == j && w->type != 6634 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6635 printf(" (selected)"); 6636 printf("\n"); 6637 } 6638 } 6639 6640} 6641 6642static void 6643hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6644{ 6645 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6646 struct hdac_widget *w, *cw; 6647 char buf[64]; 6648 int i, printed = 0; 6649 6650 if (depth > HDA_PARSE_MAXDEPTH) 6651 return; 6652 6653 w = hdac_widget_get(devinfo, nid); 6654 if (w == NULL || w->enable == 0) 6655 return; 6656 6657 if (depth == 0) 6658 device_printf(pdevinfo->dev, "%*s", 4, ""); 6659 else 6660 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6661 printf("nid=%d [%s]", w->nid, w->name); 6662 6663 if (depth > 0) { 6664 if (w->ossmask == 0) { 6665 printf("\n"); 6666 return; 6667 } 6668 printf(" [src: %s]", 6669 hdac_audio_ctl_ossmixer_mask2allname( 6670 w->ossmask, buf, sizeof(buf))); 6671 if (w->ossdev >= 0) { 6672 printf("\n"); 6673 return; 6674 } 6675 } 6676 printf("\n"); 6677 6678 for (i = 0; i < w->nconns; i++) { 6679 if (w->connsenable[i] == 0) 6680 continue; 6681 cw = hdac_widget_get(devinfo, w->conns[i]); 6682 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6683 continue; 6684 if (printed == 0) { 6685 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6686 printed = 1; 6687 } 6688 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6689 } 6690 6691} 6692 6693static void 6694hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6695{ 6696 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6697 struct hdac_softc *sc = devinfo->codec->sc; 6698 struct hdac_widget *w; 6699 int i, printed = 0; 6700 6701 if (pdevinfo->play < 0) 6702 return; 6703 6704 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6705 w = hdac_widget_get(devinfo, i); 6706 if (w == NULL || w->enable == 0) 6707 continue; 6708 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6709 continue; 6710 if (w->bindas != sc->chans[pdevinfo->play].as) 6711 continue; 6712 if (printed == 0) { 6713 printed = 1; 6714 device_printf(pdevinfo->dev, "\n"); 6715 device_printf(pdevinfo->dev, "Playback:\n"); 6716 } 6717 device_printf(pdevinfo->dev, "\n"); 6718 hdac_dump_dst_nid(pdevinfo, i, 0); 6719 } 6720} 6721 6722static void 6723hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6724{ 6725 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6726 struct hdac_softc *sc = devinfo->codec->sc; 6727 struct hdac_widget *w; 6728 int i; 6729 int printed = 0; 6730 6731 if (pdevinfo->rec < 0) 6732 return; 6733 6734 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6735 w = hdac_widget_get(devinfo, i); 6736 if (w == NULL || w->enable == 0) 6737 continue; 6738 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6739 continue; 6740 if (w->bindas != sc->chans[pdevinfo->rec].as) 6741 continue; 6742 if (printed == 0) { 6743 printed = 1; 6744 device_printf(pdevinfo->dev, "\n"); 6745 device_printf(pdevinfo->dev, "Record:\n"); 6746 } 6747 device_printf(pdevinfo->dev, "\n"); 6748 hdac_dump_dst_nid(pdevinfo, i, 0); 6749 } 6750} 6751 6752static void 6753hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6754{ 6755 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6756 struct hdac_widget *w; 6757 int i; 6758 int printed = 0; 6759 6760 if (pdevinfo->index != 0) 6761 return; 6762 6763 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6764 w = hdac_widget_get(devinfo, i); 6765 if (w == NULL || w->enable == 0) 6766 continue; 6767 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6768 continue; 6769 if (printed == 0) { 6770 printed = 1; 6771 device_printf(pdevinfo->dev, "\n"); 6772 device_printf(pdevinfo->dev, "Input Mix:\n"); 6773 } 6774 device_printf(pdevinfo->dev, "\n"); 6775 hdac_dump_dst_nid(pdevinfo, i, 0); 6776 } 6777} 6778 6779static void 6780hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6781{ 6782 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6783 nid_t *nids; 6784 int i; 6785 6786 if (pdevinfo->play >= 0) { 6787 i = pdevinfo->play; 6788 device_printf(pdevinfo->dev, "\n"); 6789 device_printf(pdevinfo->dev, "Playback:\n"); 6790 device_printf(pdevinfo->dev, "\n"); 6791 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6792 sc->chans[i].supp_pcm_size_rate); 6793 device_printf(pdevinfo->dev, " DAC:"); 6794 for (nids = sc->chans[i].io; *nids != -1; nids++) 6795 printf(" %d", *nids); 6796 printf("\n"); 6797 } 6798 if (pdevinfo->rec >= 0) { 6799 i = pdevinfo->rec; 6800 device_printf(pdevinfo->dev, "\n"); 6801 device_printf(pdevinfo->dev, "Record:\n"); 6802 device_printf(pdevinfo->dev, "\n"); 6803 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6804 sc->chans[i].supp_pcm_size_rate); 6805 device_printf(pdevinfo->dev, " ADC:"); 6806 for (nids = sc->chans[i].io; *nids != -1; nids++) 6807 printf(" %d", *nids); 6808 printf("\n"); 6809 } 6810} 6811 6812static void 6813hdac_release_resources(struct hdac_softc *sc) 6814{ 6815 int i, j; 6816 6817 if (sc == NULL) 6818 return; 6819 6820 hdac_lock(sc); 6821 sc->polling = 0; 6822 sc->poll_ival = 0; 6823 callout_stop(&sc->poll_hda); 6824 callout_stop(&sc->poll_hdac); 6825 callout_stop(&sc->poll_jack); 6826 hdac_reset(sc, 0); 6827 hdac_unlock(sc); 6828 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6829 callout_drain(&sc->poll_hda); 6830 callout_drain(&sc->poll_hdac); 6831 callout_drain(&sc->poll_jack); 6832 6833 hdac_irq_free(sc); 6834 6835 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6836 if (sc->codecs[i] == NULL) 6837 continue; 6838 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6839 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6840 if (sc->codecs[i]->fgs[j].node_type == 6841 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6842 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6843 M_HDAC); 6844 free(sc->codecs[i]->fgs[j].function.audio.as, 6845 M_HDAC); 6846 free(sc->codecs[i]->fgs[j].function.audio.devs, 6847 M_HDAC); 6848 } 6849 } 6850 free(sc->codecs[i]->fgs, M_HDAC); 6851 free(sc->codecs[i], M_HDAC); 6852 sc->codecs[i] = NULL; 6853 } 6854 6855 hdac_dma_free(sc, &sc->pos_dma); 6856 hdac_dma_free(sc, &sc->rirb_dma); 6857 hdac_dma_free(sc, &sc->corb_dma); 6858 for (i = 0; i < sc->num_chans; i++) { 6859 if (sc->chans[i].blkcnt > 0) 6860 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6861 } 6862 free(sc->chans, M_HDAC); 6863 if (sc->chan_dmat != NULL) { 6864 bus_dma_tag_destroy(sc->chan_dmat); 6865 sc->chan_dmat = NULL; 6866 } 6867 hdac_mem_free(sc); 6868 snd_mtxfree(sc->lock); 6869} 6870 6871/* This function surely going to make its way into upper level someday. */ 6872static void 6873hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6874{ 6875 const char *res = NULL; 6876 int i = 0, j, k, len, inv; 6877 6878 if (on != NULL) 6879 *on = 0; 6880 if (off != NULL) 6881 *off = 0; 6882 if (sc == NULL) 6883 return; 6884 if (resource_string_value(device_get_name(sc->dev), 6885 device_get_unit(sc->dev), "config", &res) != 0) 6886 return; 6887 if (!(res != NULL && strlen(res) > 0)) 6888 return; 6889 HDA_BOOTVERBOSE( 6890 device_printf(sc->dev, "HDA Config:"); 6891 ); 6892 for (;;) { 6893 while (res[i] != '\0' && 6894 (res[i] == ',' || isspace(res[i]) != 0)) 6895 i++; 6896 if (res[i] == '\0') { 6897 HDA_BOOTVERBOSE( 6898 printf("\n"); 6899 ); 6900 return; 6901 } 6902 j = i; 6903 while (res[j] != '\0' && 6904 !(res[j] == ',' || isspace(res[j]) != 0)) 6905 j++; 6906 len = j - i; 6907 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6908 inv = 2; 6909 else 6910 inv = 0; 6911 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6912 if (strncmp(res + i + inv, 6913 hdac_quirks_tab[k].key, len - inv) != 0) 6914 continue; 6915 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6916 break; 6917 HDA_BOOTVERBOSE( 6918 printf(" %s%s", (inv != 0) ? "no" : "", 6919 hdac_quirks_tab[k].key); 6920 ); 6921 if (inv == 0 && on != NULL) 6922 *on |= hdac_quirks_tab[k].value; 6923 else if (inv != 0 && off != NULL) 6924 *off |= hdac_quirks_tab[k].value; 6925 break; 6926 } 6927 i = j; 6928 } 6929} 6930 6931#ifdef SND_DYNSYSCTL 6932static int 6933sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6934{ 6935 struct hdac_softc *sc; 6936 device_t dev; 6937 uint32_t ctl; 6938 int err, val; 6939 6940 dev = oidp->oid_arg1; 6941 sc = device_get_softc(dev); 6942 if (sc == NULL) 6943 return (EINVAL); 6944 hdac_lock(sc); 6945 val = sc->polling; 6946 hdac_unlock(sc); 6947 err = sysctl_handle_int(oidp, &val, 0, req); 6948 6949 if (err != 0 || req->newptr == NULL) 6950 return (err); 6951 if (val < 0 || val > 1) 6952 return (EINVAL); 6953 6954 hdac_lock(sc); 6955 if (val != sc->polling) { 6956 if (val == 0) { 6957 callout_stop(&sc->poll_hda); 6958 callout_stop(&sc->poll_hdac); 6959 hdac_unlock(sc); 6960 callout_drain(&sc->poll_hda); 6961 callout_drain(&sc->poll_hdac); 6962 hdac_lock(sc); 6963 sc->polling = 0; 6964 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6965 ctl |= HDAC_INTCTL_GIE; 6966 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6967 } else { 6968 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6969 ctl &= ~HDAC_INTCTL_GIE; 6970 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6971 hdac_unlock(sc); 6972 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6973 hdac_lock(sc); 6974 sc->polling = 1; 6975 hdac_poll_reinit(sc); 6976 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6977 } 6978 } 6979 hdac_unlock(sc); 6980 6981 return (err); 6982} 6983 6984static int 6985sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6986{ 6987 struct hdac_softc *sc; 6988 device_t dev; 6989 int err, val; 6990 6991 dev = oidp->oid_arg1; 6992 sc = device_get_softc(dev); 6993 if (sc == NULL) 6994 return (EINVAL); 6995 hdac_lock(sc); 6996 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6997 hdac_unlock(sc); 6998 err = sysctl_handle_int(oidp, &val, 0, req); 6999 7000 if (err != 0 || req->newptr == NULL) 7001 return (err); 7002 7003 if (val < 1) 7004 val = 1; 7005 if (val > 5000) 7006 val = 5000; 7007 val = ((uint64_t)val * hz) / 1000; 7008 if (val < 1) 7009 val = 1; 7010 if (val > (hz * 5)) 7011 val = hz * 5; 7012 7013 hdac_lock(sc); 7014 sc->poll_ival = val; 7015 hdac_unlock(sc); 7016 7017 return (err); 7018} 7019 7020static int 7021sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7022{ 7023 struct hdac_softc *sc; 7024 struct hdac_codec *codec; 7025 struct hdac_devinfo *devinfo; 7026 struct hdac_widget *w; 7027 device_t dev; 7028 uint32_t res, pincap, delay; 7029 int codec_index, fg_index; 7030 int i, err, val; 7031 nid_t cad; 7032 7033 dev = oidp->oid_arg1; 7034 sc = device_get_softc(dev); 7035 if (sc == NULL) 7036 return (EINVAL); 7037 val = 0; 7038 err = sysctl_handle_int(oidp, &val, 0, req); 7039 if (err != 0 || req->newptr == NULL || val == 0) 7040 return (err); 7041 7042 /* XXX: Temporary. For debugging. */ 7043 if (val == 100) { 7044 hdac_suspend(dev); 7045 return (0); 7046 } else if (val == 101) { 7047 hdac_resume(dev); 7048 return (0); 7049 } 7050 7051 hdac_lock(sc); 7052 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7053 codec = sc->codecs[codec_index]; 7054 if (codec == NULL) 7055 continue; 7056 cad = codec->cad; 7057 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7058 devinfo = &codec->fgs[fg_index]; 7059 if (devinfo->node_type != 7060 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7061 continue; 7062 7063 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7064 codec_index, devinfo->nid); 7065 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7066 w = hdac_widget_get(devinfo, i); 7067 if (w == NULL || w->type != 7068 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7069 continue; 7070 hdac_dump_pin_config(w, w->wclass.pin.config); 7071 pincap = w->wclass.pin.cap; 7072 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7073 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7074 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7075 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7076 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7077 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7078 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7079 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7080 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7081 delay = 0; 7082 hdac_command(sc, 7083 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7084 do { 7085 res = hdac_command(sc, 7086 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7087 if (res != 0x7fffffff && res != 0xffffffff) 7088 break; 7089 DELAY(10); 7090 } while (++delay < 10000); 7091 } else { 7092 delay = 0; 7093 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7094 w->nid), cad); 7095 } 7096 printf(" Sense: 0x%08x", res); 7097 if (delay > 0) 7098 printf(" delay %dus", delay * 10); 7099 } 7100 printf("\n"); 7101 } 7102 device_printf(dev, 7103 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7104 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7105 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7106 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7107 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7108 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7109 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7110 device_printf(dev, " GPI:"); 7111 res = hdac_command(sc, 7112 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7113 printf(" data=0x%08x", res); 7114 res = hdac_command(sc, 7115 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7116 cad); 7117 printf(" wake=0x%08x", res); 7118 res = hdac_command(sc, 7119 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7120 cad); 7121 printf(" unsol=0x%08x", res); 7122 res = hdac_command(sc, 7123 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7124 printf(" sticky=0x%08x\n", res); 7125 } 7126 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7127 device_printf(dev, " GPO:"); 7128 res = hdac_command(sc, 7129 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7130 printf(" data=0x%08x\n", res); 7131 } 7132 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7133 device_printf(dev, "GPIO:"); 7134 res = hdac_command(sc, 7135 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7136 printf(" data=0x%08x", res); 7137 res = hdac_command(sc, 7138 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7139 printf(" enable=0x%08x", res); 7140 res = hdac_command(sc, 7141 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7142 printf(" direction=0x%08x\n", res); 7143 res = hdac_command(sc, 7144 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7145 device_printf(dev, " wake=0x%08x", res); 7146 res = hdac_command(sc, 7147 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7148 cad); 7149 printf(" unsol=0x%08x", res); 7150 res = hdac_command(sc, 7151 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7152 printf(" sticky=0x%08x\n", res); 7153 } 7154 } 7155 } 7156 hdac_unlock(sc); 7157 return (0); 7158} 7159#endif 7160 7161static void 7162hdac_attach2(void *arg) 7163{ 7164 struct hdac_codec *codec; 7165 struct hdac_softc *sc; 7166 struct hdac_audio_ctl *ctl; 7167 uint32_t quirks_on, quirks_off; 7168 int codec_index, fg_index; 7169 int i, dmaalloc = 0; 7170 struct hdac_devinfo *devinfo; 7171 7172 sc = (struct hdac_softc *)arg; 7173 7174 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7175 7176 HDA_BOOTHVERBOSE( 7177 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7178 quirks_on, quirks_off); 7179 ); 7180 7181 hdac_lock(sc); 7182 7183 /* Remove ourselves from the config hooks */ 7184 if (sc->intrhook.ich_func != NULL) { 7185 config_intrhook_disestablish(&sc->intrhook); 7186 sc->intrhook.ich_func = NULL; 7187 } 7188 7189 /* Start the corb and rirb engines */ 7190 HDA_BOOTHVERBOSE( 7191 device_printf(sc->dev, "Starting CORB Engine...\n"); 7192 ); 7193 hdac_corb_start(sc); 7194 HDA_BOOTHVERBOSE( 7195 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7196 ); 7197 hdac_rirb_start(sc); 7198 7199 HDA_BOOTHVERBOSE( 7200 device_printf(sc->dev, 7201 "Enabling controller interrupt...\n"); 7202 ); 7203 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7204 HDAC_GCTL_UNSOL); 7205 if (sc->polling == 0) { 7206 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7207 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7208 } else { 7209 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7210 } 7211 DELAY(1000); 7212 7213 HDA_BOOTHVERBOSE( 7214 device_printf(sc->dev, 7215 "Scanning HDA codecs ...\n"); 7216 ); 7217 hdac_scan_codecs(sc); 7218 7219 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7220 codec = sc->codecs[codec_index]; 7221 if (codec == NULL) 7222 continue; 7223 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7224 devinfo = &codec->fgs[fg_index]; 7225 HDA_BOOTVERBOSE( 7226 device_printf(sc->dev, "\n"); 7227 device_printf(sc->dev, 7228 "Processing %s FG cad=%d nid=%d...\n", 7229 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7230 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7231 "unknown", 7232 devinfo->codec->cad, devinfo->nid); 7233 ); 7234 if (devinfo->node_type != 7235 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7236 HDA_BOOTHVERBOSE( 7237 device_printf(sc->dev, 7238 "Powering down...\n"); 7239 ); 7240 hdac_command(sc, 7241 HDA_CMD_SET_POWER_STATE(codec->cad, 7242 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7243 codec->cad); 7244 continue; 7245 } 7246 7247 HDA_BOOTHVERBOSE( 7248 device_printf(sc->dev, "Powering up...\n"); 7249 ); 7250 hdac_powerup(devinfo); 7251 HDA_BOOTHVERBOSE( 7252 device_printf(sc->dev, "Parsing audio FG...\n"); 7253 ); 7254 hdac_audio_parse(devinfo); 7255 HDA_BOOTHVERBOSE( 7256 device_printf(sc->dev, "Parsing Ctls...\n"); 7257 ); 7258 hdac_audio_ctl_parse(devinfo); 7259 HDA_BOOTHVERBOSE( 7260 device_printf(sc->dev, "Parsing vendor patch...\n"); 7261 ); 7262 hdac_vendor_patch_parse(devinfo); 7263 devinfo->function.audio.quirks |= quirks_on; 7264 devinfo->function.audio.quirks &= ~quirks_off; 7265 7266 HDA_BOOTHVERBOSE( 7267 device_printf(sc->dev, "Disabling nonaudio...\n"); 7268 ); 7269 hdac_audio_disable_nonaudio(devinfo); 7270 HDA_BOOTHVERBOSE( 7271 device_printf(sc->dev, "Disabling useless...\n"); 7272 ); 7273 hdac_audio_disable_useless(devinfo); 7274 HDA_BOOTVERBOSE( 7275 device_printf(sc->dev, "Patched pins configuration:\n"); 7276 hdac_dump_pin_configs(devinfo); 7277 ); 7278 HDA_BOOTHVERBOSE( 7279 device_printf(sc->dev, "Parsing pin associations...\n"); 7280 ); 7281 hdac_audio_as_parse(devinfo); 7282 HDA_BOOTHVERBOSE( 7283 device_printf(sc->dev, "Building AFG tree...\n"); 7284 ); 7285 hdac_audio_build_tree(devinfo); 7286 HDA_BOOTHVERBOSE( 7287 device_printf(sc->dev, "Disabling unassociated " 7288 "widgets...\n"); 7289 ); 7290 hdac_audio_disable_unas(devinfo); 7291 HDA_BOOTHVERBOSE( 7292 device_printf(sc->dev, "Disabling nonselected " 7293 "inputs...\n"); 7294 ); 7295 hdac_audio_disable_notselected(devinfo); 7296 HDA_BOOTHVERBOSE( 7297 device_printf(sc->dev, "Disabling useless...\n"); 7298 ); 7299 hdac_audio_disable_useless(devinfo); 7300 HDA_BOOTHVERBOSE( 7301 device_printf(sc->dev, "Disabling " 7302 "crossassociatement connections...\n"); 7303 ); 7304 hdac_audio_disable_crossas(devinfo); 7305 HDA_BOOTHVERBOSE( 7306 device_printf(sc->dev, "Disabling useless...\n"); 7307 ); 7308 hdac_audio_disable_useless(devinfo); 7309 HDA_BOOTHVERBOSE( 7310 device_printf(sc->dev, "Binding associations to channels...\n"); 7311 ); 7312 hdac_audio_bind_as(devinfo); 7313 HDA_BOOTHVERBOSE( 7314 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7315 ); 7316 hdac_audio_assign_names(devinfo); 7317 HDA_BOOTHVERBOSE( 7318 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7319 ); 7320 hdac_audio_assign_mixers(devinfo); 7321 HDA_BOOTHVERBOSE( 7322 device_printf(sc->dev, "Preparing pin controls...\n"); 7323 ); 7324 hdac_audio_prepare_pin_ctrl(devinfo); 7325 HDA_BOOTHVERBOSE( 7326 device_printf(sc->dev, "AFG commit...\n"); 7327 ); 7328 hdac_audio_commit(devinfo); 7329 HDA_BOOTHVERBOSE( 7330 device_printf(sc->dev, "Ctls commit...\n"); 7331 ); 7332 hdac_audio_ctl_commit(devinfo); 7333 HDA_BOOTHVERBOSE( 7334 device_printf(sc->dev, "HP switch init...\n"); 7335 ); 7336 hdac_hp_switch_init(devinfo); 7337 7338 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7339 dmaalloc == 0) { 7340 if (hdac_dma_alloc(sc, &sc->pos_dma, 7341 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7342 HDA_BOOTVERBOSE( 7343 device_printf(sc->dev, "Failed to " 7344 "allocate DMA pos buffer " 7345 "(non-fatal)\n"); 7346 ); 7347 } else 7348 dmaalloc = 1; 7349 } 7350 7351 HDA_BOOTHVERBOSE( 7352 device_printf(sc->dev, "Creating PCM devices...\n"); 7353 ); 7354 hdac_create_pcms(devinfo); 7355 7356 HDA_BOOTVERBOSE( 7357 if (devinfo->function.audio.quirks != 0) { 7358 device_printf(sc->dev, "FG config/quirks:"); 7359 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7360 if ((devinfo->function.audio.quirks & 7361 hdac_quirks_tab[i].value) == 7362 hdac_quirks_tab[i].value) 7363 printf(" %s", hdac_quirks_tab[i].key); 7364 } 7365 printf("\n"); 7366 } 7367 7368 device_printf(sc->dev, "\n"); 7369 device_printf(sc->dev, "+-------------------+\n"); 7370 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7371 device_printf(sc->dev, "+-------------------+\n"); 7372 hdac_dump_nodes(devinfo); 7373 ); 7374 7375 HDA_BOOTHVERBOSE( 7376 device_printf(sc->dev, "\n"); 7377 device_printf(sc->dev, "+------------------------+\n"); 7378 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7379 device_printf(sc->dev, "+------------------------+\n"); 7380 device_printf(sc->dev, "\n"); 7381 i = 0; 7382 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7383 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7384 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7385 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7386 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7387 ctl->index); 7388 if (ctl->childwidget != NULL) 7389 printf(" cnid %3d", ctl->childwidget->nid); 7390 else 7391 printf(" "); 7392 printf(" ossmask=0x%08x\n", 7393 ctl->ossmask); 7394 device_printf(sc->dev, 7395 " mute: %d step: %3d size: %3d off: %3d%s\n", 7396 ctl->mute, ctl->step, ctl->size, ctl->offset, 7397 (ctl->enable == 0) ? " [DISABLED]" : 7398 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7399 } 7400 ); 7401 } 7402 } 7403 hdac_unlock(sc); 7404 7405 HDA_BOOTVERBOSE( 7406 device_printf(sc->dev, "\n"); 7407 ); 7408 7409 bus_generic_attach(sc->dev); 7410 7411#ifdef SND_DYNSYSCTL 7412 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7413 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7414 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7415 sysctl_hdac_polling, "I", "Enable polling mode"); 7416 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7417 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7418 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7419 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7420 "Controller/Jack Sense polling interval (1-1000 ms)"); 7421 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7422 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7423 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7424 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7425#endif 7426} 7427 7428/**************************************************************************** 7429 * int hdac_suspend(device_t) 7430 * 7431 * Suspend and power down HDA bus and codecs. 7432 ****************************************************************************/ 7433static int 7434hdac_suspend(device_t dev) 7435{ 7436 struct hdac_softc *sc; 7437 struct hdac_codec *codec; 7438 struct hdac_devinfo *devinfo; 7439 int codec_index, fg_index, i; 7440 7441 HDA_BOOTHVERBOSE( 7442 device_printf(dev, "Suspend...\n"); 7443 ); 7444 7445 sc = device_get_softc(dev); 7446 hdac_lock(sc); 7447 7448 HDA_BOOTHVERBOSE( 7449 device_printf(dev, "Stop streams...\n"); 7450 ); 7451 for (i = 0; i < sc->num_chans; i++) { 7452 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7453 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7454 hdac_channel_stop(sc, &sc->chans[i]); 7455 } 7456 } 7457 7458 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7459 codec = sc->codecs[codec_index]; 7460 if (codec == NULL) 7461 continue; 7462 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7463 devinfo = &codec->fgs[fg_index]; 7464 HDA_BOOTHVERBOSE( 7465 device_printf(dev, 7466 "Power down FG" 7467 " cad=%d nid=%d to the D3 state...\n", 7468 codec->cad, devinfo->nid); 7469 ); 7470 hdac_command(sc, 7471 HDA_CMD_SET_POWER_STATE(codec->cad, 7472 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7473 codec->cad); 7474 } 7475 } 7476 7477 HDA_BOOTHVERBOSE( 7478 device_printf(dev, "Reset controller...\n"); 7479 ); 7480 callout_stop(&sc->poll_hda); 7481 callout_stop(&sc->poll_hdac); 7482 callout_stop(&sc->poll_jack); 7483 hdac_reset(sc, 0); 7484 hdac_unlock(sc); 7485 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7486 callout_drain(&sc->poll_hda); 7487 callout_drain(&sc->poll_hdac); 7488 callout_drain(&sc->poll_jack); 7489 7490 HDA_BOOTHVERBOSE( 7491 device_printf(dev, "Suspend done\n"); 7492 ); 7493 7494 return (0); 7495} 7496 7497/**************************************************************************** 7498 * int hdac_resume(device_t) 7499 * 7500 * Powerup and restore HDA bus and codecs state. 7501 ****************************************************************************/ 7502static int 7503hdac_resume(device_t dev) 7504{ 7505 struct hdac_softc *sc; 7506 struct hdac_codec *codec; 7507 struct hdac_devinfo *devinfo; 7508 int codec_index, fg_index, i; 7509 7510 HDA_BOOTHVERBOSE( 7511 device_printf(dev, "Resume...\n"); 7512 ); 7513 7514 sc = device_get_softc(dev); 7515 hdac_lock(sc); 7516 7517 /* Quiesce everything */ 7518 HDA_BOOTHVERBOSE( 7519 device_printf(dev, "Reset controller...\n"); 7520 ); 7521 hdac_reset(sc, 1); 7522 7523 /* Initialize the CORB and RIRB */ 7524 hdac_corb_init(sc); 7525 hdac_rirb_init(sc); 7526 7527 /* Start the corb and rirb engines */ 7528 HDA_BOOTHVERBOSE( 7529 device_printf(dev, "Starting CORB Engine...\n"); 7530 ); 7531 hdac_corb_start(sc); 7532 HDA_BOOTHVERBOSE( 7533 device_printf(dev, "Starting RIRB Engine...\n"); 7534 ); 7535 hdac_rirb_start(sc); 7536 7537 HDA_BOOTHVERBOSE( 7538 device_printf(dev, 7539 "Enabling controller interrupt...\n"); 7540 ); 7541 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7542 HDAC_GCTL_UNSOL); 7543 if (sc->polling == 0) { 7544 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7545 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7546 } else { 7547 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7548 } 7549 DELAY(1000); 7550 7551 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7552 codec = sc->codecs[codec_index]; 7553 if (codec == NULL) 7554 continue; 7555 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7556 devinfo = &codec->fgs[fg_index]; 7557 if (devinfo->node_type != 7558 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7559 HDA_BOOTHVERBOSE( 7560 device_printf(dev, 7561 "Power down unsupported non-audio FG" 7562 " cad=%d nid=%d to the D3 state...\n", 7563 codec->cad, devinfo->nid); 7564 ); 7565 hdac_command(sc, 7566 HDA_CMD_SET_POWER_STATE(codec->cad, 7567 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7568 codec->cad); 7569 continue; 7570 } 7571 7572 HDA_BOOTHVERBOSE( 7573 device_printf(dev, 7574 "Power up audio FG cad=%d nid=%d...\n", 7575 devinfo->codec->cad, devinfo->nid); 7576 ); 7577 hdac_powerup(devinfo); 7578 HDA_BOOTHVERBOSE( 7579 device_printf(dev, "AFG commit...\n"); 7580 ); 7581 hdac_audio_commit(devinfo); 7582 HDA_BOOTHVERBOSE( 7583 device_printf(dev, "Ctls commit...\n"); 7584 ); 7585 hdac_audio_ctl_commit(devinfo); 7586 HDA_BOOTHVERBOSE( 7587 device_printf(dev, "HP switch init...\n"); 7588 ); 7589 hdac_hp_switch_init(devinfo); 7590 7591 hdac_unlock(sc); 7592 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7593 struct hdac_pcm_devinfo *pdevinfo = 7594 &devinfo->function.audio.devs[i]; 7595 HDA_BOOTHVERBOSE( 7596 device_printf(pdevinfo->dev, 7597 "OSS mixer reinitialization...\n"); 7598 ); 7599 if (mixer_reinit(pdevinfo->dev) == -1) 7600 device_printf(pdevinfo->dev, 7601 "unable to reinitialize the mixer\n"); 7602 } 7603 hdac_lock(sc); 7604 } 7605 } 7606 7607 HDA_BOOTHVERBOSE( 7608 device_printf(dev, "Start streams...\n"); 7609 ); 7610 for (i = 0; i < sc->num_chans; i++) { 7611 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7612 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7613 hdac_channel_start(sc, &sc->chans[i]); 7614 } 7615 } 7616 7617 hdac_unlock(sc); 7618 7619 HDA_BOOTHVERBOSE( 7620 device_printf(dev, "Resume done\n"); 7621 ); 7622 7623 return (0); 7624} 7625/**************************************************************************** 7626 * int hdac_detach(device_t) 7627 * 7628 * Detach and free up resources utilized by the hdac device. 7629 ****************************************************************************/ 7630static int 7631hdac_detach(device_t dev) 7632{ 7633 struct hdac_softc *sc; 7634 device_t *devlist; 7635 int i, devcount, error; 7636 7637 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7638 return (error); 7639 for (i = 0; i < devcount; i++) { 7640 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7641 free(devlist, M_TEMP); 7642 return (error); 7643 } 7644 } 7645 free(devlist, M_TEMP); 7646 7647 sc = device_get_softc(dev); 7648 hdac_release_resources(sc); 7649 7650 return (0); 7651} 7652 7653static int 7654hdac_print_child(device_t dev, device_t child) 7655{ 7656 struct hdac_pcm_devinfo *pdevinfo = 7657 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7658 int retval; 7659 7660 retval = bus_print_child_header(dev, child); 7661 retval += printf(" at cad %d nid %d", 7662 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7663 retval += bus_print_child_footer(dev, child); 7664 7665 return (retval); 7666} 7667 7668static device_method_t hdac_methods[] = { 7669 /* device interface */ 7670 DEVMETHOD(device_probe, hdac_probe), 7671 DEVMETHOD(device_attach, hdac_attach), 7672 DEVMETHOD(device_detach, hdac_detach), 7673 DEVMETHOD(device_suspend, hdac_suspend), 7674 DEVMETHOD(device_resume, hdac_resume), 7675 /* Bus interface */ 7676 DEVMETHOD(bus_print_child, hdac_print_child), 7677 { 0, 0 } 7678}; 7679 7680static driver_t hdac_driver = { 7681 "hdac", 7682 hdac_methods, 7683 sizeof(struct hdac_softc), 7684}; 7685 7686static devclass_t hdac_devclass; 7687 7688DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7689MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7690MODULE_VERSION(snd_hda, 1); 7691 7692static int 7693hdac_pcm_probe(device_t dev) 7694{ 7695 struct hdac_pcm_devinfo *pdevinfo = 7696 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7697 char buf[128]; 7698 7699 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7700 hdac_codec_name(pdevinfo->devinfo->codec), 7701 pdevinfo->index, 7702 pdevinfo->digital?"Digital":"Analog"); 7703 device_set_desc_copy(dev, buf); 7704 return (0); 7705} 7706 7707static int 7708hdac_pcm_attach(device_t dev) 7709{ 7710 struct hdac_pcm_devinfo *pdevinfo = 7711 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7712 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7713 char status[SND_STATUSLEN]; 7714 int i; 7715 7716 pdevinfo->chan_size = pcm_getbuffersize(dev, 7717 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7718 7719 HDA_BOOTVERBOSE( 7720 device_printf(dev, "+--------------------------------------+\n"); 7721 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7722 device_printf(dev, "+--------------------------------------+\n"); 7723 hdac_dump_pcmchannels(pdevinfo); 7724 device_printf(dev, "\n"); 7725 device_printf(dev, "+--------------------------------+\n"); 7726 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7727 device_printf(dev, "+--------------------------------+\n"); 7728 hdac_dump_dac(pdevinfo); 7729 hdac_dump_adc(pdevinfo); 7730 hdac_dump_mix(pdevinfo); 7731 device_printf(dev, "\n"); 7732 device_printf(dev, "+-------------------------+\n"); 7733 device_printf(dev, "| DUMPING Volume Controls |\n"); 7734 device_printf(dev, "+-------------------------+\n"); 7735 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7736 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7737 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7738 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7739 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7740 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7741 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7742 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7743 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7744 hdac_dump_ctls(pdevinfo, NULL, 0); 7745 device_printf(dev, "\n"); 7746 ); 7747 7748 if (resource_int_value(device_get_name(dev), 7749 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7750 i &= HDA_BLK_ALIGN; 7751 if (i < HDA_BLK_MIN) 7752 i = HDA_BLK_MIN; 7753 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7754 i = 0; 7755 while (pdevinfo->chan_blkcnt >> i) 7756 i++; 7757 pdevinfo->chan_blkcnt = 1 << (i - 1); 7758 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7759 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7760 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7761 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7762 } else 7763 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7764 7765 /* 7766 * We don't register interrupt handler with snd_setup_intr 7767 * in pcm device. Mark pcm device as MPSAFE manually. 7768 */ 7769 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7770 7771 HDA_BOOTHVERBOSE( 7772 device_printf(dev, "OSS mixer initialization...\n"); 7773 ); 7774 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7775 device_printf(dev, "Can't register mixer\n"); 7776 7777 HDA_BOOTHVERBOSE( 7778 device_printf(dev, "Registering PCM channels...\n"); 7779 ); 7780 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7781 (pdevinfo->rec >= 0)?1:0) != 0) 7782 device_printf(dev, "Can't register PCM\n"); 7783 7784 pdevinfo->registered++; 7785 7786 if (pdevinfo->play >= 0) 7787 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7788 if (pdevinfo->rec >= 0) 7789 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7790 7791 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7792 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7793 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7794 pcm_setstatus(dev, status); 7795 7796 return (0); 7797} 7798 7799static int 7800hdac_pcm_detach(device_t dev) 7801{ 7802 struct hdac_pcm_devinfo *pdevinfo = 7803 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7804 int err; 7805 7806 if (pdevinfo->registered > 0) { 7807 err = pcm_unregister(dev); 7808 if (err != 0) 7809 return (err); 7810 } 7811 7812 return (0); 7813} 7814 7815static device_method_t hdac_pcm_methods[] = { 7816 /* device interface */ 7817 DEVMETHOD(device_probe, hdac_pcm_probe), 7818 DEVMETHOD(device_attach, hdac_pcm_attach), 7819 DEVMETHOD(device_detach, hdac_pcm_detach), 7820 { 0, 0 } 7821}; 7822 7823static driver_t hdac_pcm_driver = { 7824 "pcm", 7825 hdac_pcm_methods, 7826 PCM_SOFTC_SIZE, 7827}; 7828 7829DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7830 7831