hdac.c revision 186145
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20081123_0118" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 186145 2008-12-15 23:49:09Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 166 167/* ATI */ 168#define ATI_VENDORID 0x1002 169#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 170#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 171#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 172 173/* VIA */ 174#define VIA_VENDORID 0x1106 175#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 176#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 177 178/* SiS */ 179#define SIS_VENDORID 0x1039 180#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 181#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 182 183/* OEM/subvendors */ 184 185/* Intel */ 186#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 187 188/* HP/Compaq */ 189#define HP_VENDORID 0x103c 190#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 191#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 192#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 193#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 194#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 195#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 196#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 197#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 198#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 199#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 200/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 201#define HP_NX6325_SUBVENDORX 0x103c30b0 202 203/* Dell */ 204#define DELL_VENDORID 0x1028 205#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 206#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 207#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 208#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 209#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 210#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 211#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 212#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 213 214/* Clevo */ 215#define CLEVO_VENDORID 0x1558 216#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 217#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 218 219/* Acer */ 220#define ACER_VENDORID 0x1025 221#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 222#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 223#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 224#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 225#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 226#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 227#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 228 229/* Asus */ 230#define ASUS_VENDORID 0x1043 231#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 232#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 233#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 234#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 235#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 236#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 237#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 238#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 239#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 240#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 241#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 242#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 243#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 244#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 245#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 246#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 247 248/* IBM / Lenovo */ 249#define IBM_VENDORID 0x1014 250#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 251#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 252 253/* Lenovo */ 254#define LENOVO_VENDORID 0x17aa 255#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 256#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 257#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 258#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 259 260/* Samsung */ 261#define SAMSUNG_VENDORID 0x144d 262#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 263#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 264 265/* Medion ? */ 266#define MEDION_VENDORID 0x161f 267#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 268#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 269 270/* Apple Computer Inc. */ 271#define APPLE_VENDORID 0x106b 272#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 273 274/* Sony */ 275#define SONY_VENDORID 0x104d 276#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 277#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 278 279/* 280 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 281 * instead of their own, which is beyond my comprehension 282 * (see HDA_CODEC_STAC9221 below). 283 */ 284#define APPLE_INTEL_MAC 0x76808384 285 286/* LG Electronics */ 287#define LG_VENDORID 0x1854 288#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 289#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 290 291/* Fujitsu Siemens */ 292#define FS_VENDORID 0x1734 293#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 294#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 295#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 296 297/* Fujitsu Limited */ 298#define FL_VENDORID 0x10cf 299#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 300#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 301#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 302 303/* Toshiba */ 304#define TOSHIBA_VENDORID 0x1179 305#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 306#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 307#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 308 309/* Micro-Star International (MSI) */ 310#define MSI_VENDORID 0x1462 311#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 312#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 313#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 314 315/* Giga-Byte Technology */ 316#define GB_VENDORID 0x1458 317#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 318#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 319 320/* Uniwill ? */ 321#define UNIWILL_VENDORID 0x1584 322#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 323#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 324 325 326/* Misc constants.. */ 327#define HDA_AMP_VOL_DEFAULT (-1) 328#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 329#define HDA_AMP_MUTE_NONE (0) 330#define HDA_AMP_MUTE_LEFT (1 << 0) 331#define HDA_AMP_MUTE_RIGHT (1 << 1) 332#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 333 334#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 335#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 336 337#define HDA_ADC_MONITOR (1 << 0) 338 339#define HDA_CTL_OUT 1 340#define HDA_CTL_IN 2 341 342#define HDA_GPIO_MAX 8 343/* 0 - 7 = GPIO , 8 = Flush */ 344#define HDA_QUIRK_GPIO0 (1 << 0) 345#define HDA_QUIRK_GPIO1 (1 << 1) 346#define HDA_QUIRK_GPIO2 (1 << 2) 347#define HDA_QUIRK_GPIO3 (1 << 3) 348#define HDA_QUIRK_GPIO4 (1 << 4) 349#define HDA_QUIRK_GPIO5 (1 << 5) 350#define HDA_QUIRK_GPIO6 (1 << 6) 351#define HDA_QUIRK_GPIO7 (1 << 7) 352#define HDA_QUIRK_GPIOFLUSH (1 << 8) 353 354/* 9 - 25 = anything else */ 355#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 356#define HDA_QUIRK_FIXEDRATE (1 << 10) 357#define HDA_QUIRK_FORCESTEREO (1 << 11) 358#define HDA_QUIRK_EAPDINV (1 << 12) 359#define HDA_QUIRK_DMAPOS (1 << 13) 360#define HDA_QUIRK_SENSEINV (1 << 14) 361 362/* 26 - 31 = vrefs */ 363#define HDA_QUIRK_IVREF50 (1 << 26) 364#define HDA_QUIRK_IVREF80 (1 << 27) 365#define HDA_QUIRK_IVREF100 (1 << 28) 366#define HDA_QUIRK_OVREF50 (1 << 29) 367#define HDA_QUIRK_OVREF80 (1 << 30) 368#define HDA_QUIRK_OVREF100 (1 << 31) 369 370#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 371 HDA_QUIRK_IVREF100) 372#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 373 HDA_QUIRK_OVREF100) 374#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 375 376#if __FreeBSD_version < 600000 377#define taskqueue_drain(...) 378#endif 379 380static const struct { 381 char *key; 382 uint32_t value; 383} hdac_quirks_tab[] = { 384 { "gpio0", HDA_QUIRK_GPIO0 }, 385 { "gpio1", HDA_QUIRK_GPIO1 }, 386 { "gpio2", HDA_QUIRK_GPIO2 }, 387 { "gpio3", HDA_QUIRK_GPIO3 }, 388 { "gpio4", HDA_QUIRK_GPIO4 }, 389 { "gpio5", HDA_QUIRK_GPIO5 }, 390 { "gpio6", HDA_QUIRK_GPIO6 }, 391 { "gpio7", HDA_QUIRK_GPIO7 }, 392 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 393 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 394 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 395 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 396 { "eapdinv", HDA_QUIRK_EAPDINV }, 397 { "dmapos", HDA_QUIRK_DMAPOS }, 398 { "senseinv", HDA_QUIRK_SENSEINV }, 399 { "ivref50", HDA_QUIRK_IVREF50 }, 400 { "ivref80", HDA_QUIRK_IVREF80 }, 401 { "ivref100", HDA_QUIRK_IVREF100 }, 402 { "ovref50", HDA_QUIRK_OVREF50 }, 403 { "ovref80", HDA_QUIRK_OVREF80 }, 404 { "ovref100", HDA_QUIRK_OVREF100 }, 405 { "ivref", HDA_QUIRK_IVREF }, 406 { "ovref", HDA_QUIRK_OVREF }, 407 { "vref", HDA_QUIRK_VREF }, 408}; 409#define HDAC_QUIRKS_TAB_LEN \ 410 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 411 412#define HDA_BDL_MIN 2 413#define HDA_BDL_MAX 256 414#define HDA_BDL_DEFAULT HDA_BDL_MIN 415 416#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 417#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 418 419#define HDA_BUFSZ_MIN 4096 420#define HDA_BUFSZ_MAX 65536 421#define HDA_BUFSZ_DEFAULT 16384 422 423#define HDA_PARSE_MAXDEPTH 10 424 425#define HDAC_UNSOLTAG_EVENT_HP 0x00 426 427MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 428 429const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 430 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 431 "White", "Other"}; 432 433const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 434 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 435 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 436 437const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 438 439/* Default */ 440static uint32_t hdac_fmt[] = { 441 AFMT_STEREO | AFMT_S16_LE, 442 0 443}; 444 445static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 446 447static const struct { 448 uint32_t model; 449 char *desc; 450} hdac_devices[] = { 451 { HDA_INTEL_82801F, "Intel 82801F" }, 452 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 453 { HDA_INTEL_82801G, "Intel 82801G" }, 454 { HDA_INTEL_82801H, "Intel 82801H" }, 455 { HDA_INTEL_82801I, "Intel 82801I" }, 456 { HDA_INTEL_82801J, "Intel 82801J" }, 457 { HDA_INTEL_SCH, "Intel SCH" }, 458 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 459 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 460 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 461 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 462 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 463 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 464 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 465 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 466 { HDA_ATI_SB450, "ATI SB450" }, 467 { HDA_ATI_SB600, "ATI SB600" }, 468 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 469 { HDA_SIS_966, "SiS 966" }, 470 /* Unknown */ 471 { HDA_INTEL_ALL, "Intel (Unknown)" }, 472 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 473 { HDA_ATI_ALL, "ATI (Unknown)" }, 474 { HDA_VIA_ALL, "VIA (Unknown)" }, 475 { HDA_SIS_ALL, "SiS (Unknown)" }, 476}; 477#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 478 479static const struct { 480 uint16_t vendor; 481 uint8_t reg; 482 uint8_t mask; 483 uint8_t enable; 484} hdac_pcie_snoop[] = { 485 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 486 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 487 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 488}; 489#define HDAC_PCIESNOOP_LEN \ 490 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 491 492static const struct { 493 uint32_t rate; 494 int valid; 495 uint16_t base; 496 uint16_t mul; 497 uint16_t div; 498} hda_rate_tab[] = { 499 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 500 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 501 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 502 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 503 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 504 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 505 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 506 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 507 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 508 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 509 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 510 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 511 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 512 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 513 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 514 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 515 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 516 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 517 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 518 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 519 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 520 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 521 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 522 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 523 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 524 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 525 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 526 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 527 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 528 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 529 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 530 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 531 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 532 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 533 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 534}; 535#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 536 537/* All codecs you can eat... */ 538#define HDA_CODEC_CONSTRUCT(vendor, id) \ 539 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 540 541/* Realtek */ 542#define REALTEK_VENDORID 0x10ec 543#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 544#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 545#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 546#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 547#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 548#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 549#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 550#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 551#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 552#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 553#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 554#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 555#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 556#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 557#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 558#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 559#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 560#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 561 562/* Analog Devices */ 563#define ANALOGDEVICES_VENDORID 0x11d4 564#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 565#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 566#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 567#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 568#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 569#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 570#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 571 572/* CMedia */ 573#define CMEDIA_VENDORID 0x434d 574#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 575#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 576 577/* Sigmatel */ 578#define SIGMATEL_VENDORID 0x8384 579#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 580#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 581#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 582#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 583#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 584#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 585#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 586#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 587#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 588#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 589#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 590#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 591#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 592#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 593#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 594#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 595#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 596#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 597#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 598#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 599#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 600#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 601#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 602#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 603#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 604#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 605#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 606#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 607#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 608#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 609#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 610#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 611#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 612#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 613#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 614#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 615#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 616#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 617#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 618#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 619 620/* IDT */ 621#define IDT_VENDORID 0x111d 622#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 623#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 624#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 625#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 626#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 627#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 628#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 629#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 630#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 631#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 632#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 633#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 634#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 635 636/* Silicon Image */ 637#define SII_VENDORID 0x1095 638#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 639 640/* Lucent/Agere */ 641#define AGERE_VENDORID 0x11c1 642#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 643 644/* 645 * Conexant 646 * 647 * Ok, the truth is, I don't have any idea at all whether 648 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 649 * place that tell me it is "Venice" is from its Windows driver INF. 650 * 651 * Venice - CX????? 652 * Waikiki - CX20551-22 653 */ 654#define CONEXANT_VENDORID 0x14f1 655#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 656#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 657#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 658 659/* VIA */ 660#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 661#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 662#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 663#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 664#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 665#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 666#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 667#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 668#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 669#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 670#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 671#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 672#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 673#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 674#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 675#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 676#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 677#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 678#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 679#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 680#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 681 682/* ATI */ 683#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 684 685/* NVIDIA */ 686#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 687 688/* INTEL */ 689#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 690 691/* Codecs */ 692static const struct { 693 uint32_t id; 694 char *name; 695} hdac_codecs[] = { 696 { HDA_CODEC_ALC260, "Realtek ALC260" }, 697 { HDA_CODEC_ALC262, "Realtek ALC262" }, 698 { HDA_CODEC_ALC267, "Realtek ALC267" }, 699 { HDA_CODEC_ALC268, "Realtek ALC268" }, 700 { HDA_CODEC_ALC269, "Realtek ALC269" }, 701 { HDA_CODEC_ALC272, "Realtek ALC272" }, 702 { HDA_CODEC_ALC660, "Realtek ALC660" }, 703 { HDA_CODEC_ALC662, "Realtek ALC662" }, 704 { HDA_CODEC_ALC663, "Realtek ALC663" }, 705 { HDA_CODEC_ALC861, "Realtek ALC861" }, 706 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 707 { HDA_CODEC_ALC880, "Realtek ALC880" }, 708 { HDA_CODEC_ALC882, "Realtek ALC882" }, 709 { HDA_CODEC_ALC883, "Realtek ALC883" }, 710 { HDA_CODEC_ALC885, "Realtek ALC885" }, 711 { HDA_CODEC_ALC888, "Realtek ALC888" }, 712 { HDA_CODEC_ALC889, "Realtek ALC889" }, 713 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 714 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 715 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 716 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 717 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 718 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 719 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 720 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 721 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 722 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 723 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 724 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 725 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 726 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 727 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 728 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 729 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 730 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 731 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 732 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 733 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 734 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 735 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 736 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 737 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 738 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 739 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 740 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 741 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 742 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 743 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 744 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 745 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 746 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 747 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 748 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 749 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 750 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 751 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 752 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 753 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 754 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 755 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 756 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 757 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 758 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 759 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 760 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 761 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 762 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 763 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 764 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 765 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 766 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 767 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 768 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 769 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 770 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 771 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 772 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 773 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 774 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 775 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 776 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 777 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 778 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 779 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 780 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 781 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 782 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 783 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 784 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 785 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 786 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 787 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 788 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 789 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 790 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 791 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 792 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 793 /* Unknown codec */ 794 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 795 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 796 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 797 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 798 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 799 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 800 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 801 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 802 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 803 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 804 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 805 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 806}; 807#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 808 809 810/**************************************************************************** 811 * Function prototypes 812 ****************************************************************************/ 813static void hdac_intr_handler(void *); 814static int hdac_reset(struct hdac_softc *, int); 815static int hdac_get_capabilities(struct hdac_softc *); 816static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 817static int hdac_dma_alloc(struct hdac_softc *, 818 struct hdac_dma *, bus_size_t); 819static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 820static int hdac_mem_alloc(struct hdac_softc *); 821static void hdac_mem_free(struct hdac_softc *); 822static int hdac_irq_alloc(struct hdac_softc *); 823static void hdac_irq_free(struct hdac_softc *); 824static void hdac_corb_init(struct hdac_softc *); 825static void hdac_rirb_init(struct hdac_softc *); 826static void hdac_corb_start(struct hdac_softc *); 827static void hdac_rirb_start(struct hdac_softc *); 828static void hdac_scan_codecs(struct hdac_softc *); 829static void hdac_probe_codec(struct hdac_codec *); 830static void hdac_probe_function(struct hdac_codec *, nid_t); 831static int hdac_pcmchannel_setup(struct hdac_chan *); 832 833static void hdac_attach2(void *); 834 835static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 836 uint32_t, int); 837static void hdac_command_send_internal(struct hdac_softc *, 838 struct hdac_command_list *, int); 839 840static int hdac_probe(device_t); 841static int hdac_attach(device_t); 842static int hdac_detach(device_t); 843static int hdac_suspend(device_t); 844static int hdac_resume(device_t); 845static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 846static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 847 uint32_t, int, int); 848static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 849 nid_t, int, int, int); 850static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 851 nid_t, nid_t, int, int, int, int, int, int); 852static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 853 854static int hdac_rirb_flush(struct hdac_softc *sc); 855static int hdac_unsolq_flush(struct hdac_softc *sc); 856 857static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 858 859#define hdac_command(a1, a2, a3) \ 860 hdac_command_sendone_internal(a1, a2, a3) 861 862#define hdac_codec_id(c) \ 863 ((uint32_t)((c == NULL) ? 0x00000000 : \ 864 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 865 ((uint32_t)(c)->device_id & 0x0000ffff)))) 866 867static char * 868hdac_codec_name(struct hdac_codec *codec) 869{ 870 uint32_t id; 871 int i; 872 873 id = hdac_codec_id(codec); 874 875 for (i = 0; i < HDAC_CODECS_LEN; i++) { 876 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 877 return (hdac_codecs[i].name); 878 } 879 880 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 881} 882 883static char * 884hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 885{ 886 static char *ossname[] = SOUND_DEVICE_NAMES; 887 int i, first = 1; 888 889 bzero(buf, len); 890 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 891 if (mask & (1 << i)) { 892 if (first == 0) 893 strlcat(buf, ", ", len); 894 strlcat(buf, ossname[i], len); 895 first = 0; 896 } 897 } 898 return (buf); 899} 900 901static struct hdac_audio_ctl * 902hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 903{ 904 if (devinfo == NULL || 905 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 906 index == NULL || devinfo->function.audio.ctl == NULL || 907 devinfo->function.audio.ctlcnt < 1 || 908 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 909 return (NULL); 910 return (&devinfo->function.audio.ctl[(*index)++]); 911} 912 913static struct hdac_audio_ctl * 914hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 915 int index, int cnt) 916{ 917 struct hdac_audio_ctl *ctl; 918 int i, found = 0; 919 920 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 921 return (NULL); 922 923 i = 0; 924 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 925 if (ctl->enable == 0) 926 continue; 927 if (ctl->widget->nid != nid) 928 continue; 929 if (dir && ctl->ndir != dir) 930 continue; 931 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 932 ctl->dir == ctl->ndir && ctl->index != index) 933 continue; 934 found++; 935 if (found == cnt || cnt <= 0) 936 return (ctl); 937 } 938 939 return (NULL); 940} 941 942/* 943 * Jack detection (Speaker/HP redirection) event handler. 944 */ 945static void 946hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 947{ 948 struct hdac_audio_as *as; 949 struct hdac_softc *sc; 950 struct hdac_widget *w; 951 struct hdac_audio_ctl *ctl; 952 uint32_t val, res; 953 int i, j; 954 nid_t cad; 955 956 if (devinfo == NULL || devinfo->codec == NULL || 957 devinfo->codec->sc == NULL) 958 return; 959 960 sc = devinfo->codec->sc; 961 cad = devinfo->codec->cad; 962 as = devinfo->function.audio.as; 963 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 964 if (as[i].hpredir < 0) 965 continue; 966 967 w = hdac_widget_get(devinfo, as[i].pins[15]); 968 if (w == NULL || w->enable == 0 || w->type != 969 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 970 continue; 971 972 res = hdac_command(sc, 973 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 974 975 HDA_BOOTVERBOSE( 976 device_printf(sc->dev, 977 "Pin sense: nid=%d res=0x%08x\n", 978 as[i].pins[15], res); 979 ); 980 981 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 982 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 983 res ^= 1; 984 985 /* (Un)Mute headphone pin. */ 986 ctl = hdac_audio_ctl_amp_get(devinfo, 987 as[i].pins[15], HDA_CTL_IN, -1, 1); 988 if (ctl != NULL && ctl->mute) { 989 /* If pin has muter - use it. */ 990 val = (res != 0) ? 0 : 1; 991 if (val != ctl->forcemute) { 992 ctl->forcemute = val; 993 hdac_audio_ctl_amp_set(ctl, 994 HDA_AMP_MUTE_DEFAULT, 995 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 996 } 997 } else { 998 /* If there is no muter - disable pin output. */ 999 w = hdac_widget_get(devinfo, as[i].pins[15]); 1000 if (w != NULL && w->type == 1001 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1002 if (res != 0) 1003 val = w->wclass.pin.ctrl | 1004 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1005 else 1006 val = w->wclass.pin.ctrl & 1007 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1008 if (val != w->wclass.pin.ctrl) { 1009 w->wclass.pin.ctrl = val; 1010 hdac_command(sc, 1011 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1012 w->nid, w->wclass.pin.ctrl), cad); 1013 } 1014 } 1015 } 1016 /* (Un)Mute other pins. */ 1017 for (j = 0; j < 15; j++) { 1018 if (as[i].pins[j] <= 0) 1019 continue; 1020 ctl = hdac_audio_ctl_amp_get(devinfo, 1021 as[i].pins[j], HDA_CTL_IN, -1, 1); 1022 if (ctl != NULL && ctl->mute) { 1023 /* If pin has muter - use it. */ 1024 val = (res != 0) ? 1 : 0; 1025 if (val == ctl->forcemute) 1026 continue; 1027 ctl->forcemute = val; 1028 hdac_audio_ctl_amp_set(ctl, 1029 HDA_AMP_MUTE_DEFAULT, 1030 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1031 continue; 1032 } 1033 /* If there is no muter - disable pin output. */ 1034 w = hdac_widget_get(devinfo, as[i].pins[j]); 1035 if (w != NULL && w->type == 1036 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1037 if (res != 0) 1038 val = w->wclass.pin.ctrl & 1039 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1040 else 1041 val = w->wclass.pin.ctrl | 1042 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1043 if (val != w->wclass.pin.ctrl) { 1044 w->wclass.pin.ctrl = val; 1045 hdac_command(sc, 1046 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1047 w->nid, w->wclass.pin.ctrl), cad); 1048 } 1049 } 1050 } 1051 } 1052} 1053 1054/* 1055 * Callback for poll based jack detection. 1056 */ 1057static void 1058hdac_jack_poll_callback(void *arg) 1059{ 1060 struct hdac_devinfo *devinfo = arg; 1061 struct hdac_softc *sc; 1062 1063 if (devinfo == NULL || devinfo->codec == NULL || 1064 devinfo->codec->sc == NULL) 1065 return; 1066 sc = devinfo->codec->sc; 1067 hdac_lock(sc); 1068 if (sc->poll_ival == 0) { 1069 hdac_unlock(sc); 1070 return; 1071 } 1072 hdac_hp_switch_handler(devinfo); 1073 callout_reset(&sc->poll_jack, sc->poll_ival, 1074 hdac_jack_poll_callback, devinfo); 1075 hdac_unlock(sc); 1076} 1077 1078/* 1079 * Jack detection initializer. 1080 */ 1081static void 1082hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1083{ 1084 struct hdac_softc *sc = devinfo->codec->sc; 1085 struct hdac_audio_as *as = devinfo->function.audio.as; 1086 struct hdac_widget *w; 1087 uint32_t id; 1088 int i, enable = 0, poll = 0; 1089 nid_t cad; 1090 1091 id = hdac_codec_id(devinfo->codec); 1092 cad = devinfo->codec->cad; 1093 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1094 if (as[i].hpredir < 0) 1095 continue; 1096 1097 w = hdac_widget_get(devinfo, as[i].pins[15]); 1098 if (w == NULL || w->enable == 0 || w->type != 1099 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1100 continue; 1101 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1102 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1103 device_printf(sc->dev, 1104 "No jack detection support at pin %d\n", 1105 as[i].pins[15]); 1106 continue; 1107 } 1108 enable = 1; 1109 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1110 hdac_command(sc, 1111 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1112 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1113 HDAC_UNSOLTAG_EVENT_HP), cad); 1114 } else 1115 poll = 1; 1116 HDA_BOOTVERBOSE( 1117 device_printf(sc->dev, 1118 "Enabling headphone/speaker " 1119 "audio routing switching:\n"); 1120 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1121 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1122 ); 1123 } 1124 if (enable) { 1125 hdac_hp_switch_handler(devinfo); 1126 if (poll) { 1127 callout_reset(&sc->poll_jack, 1, 1128 hdac_jack_poll_callback, devinfo); 1129 } 1130 } 1131} 1132 1133/* 1134 * Unsolicited messages handler. 1135 */ 1136static void 1137hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1138{ 1139 struct hdac_softc *sc; 1140 struct hdac_devinfo *devinfo = NULL; 1141 int i; 1142 1143 if (codec == NULL || codec->sc == NULL) 1144 return; 1145 1146 sc = codec->sc; 1147 1148 HDA_BOOTVERBOSE( 1149 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1150 ); 1151 1152 for (i = 0; i < codec->num_fgs; i++) { 1153 if (codec->fgs[i].node_type == 1154 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1155 devinfo = &codec->fgs[i]; 1156 break; 1157 } 1158 } 1159 1160 if (devinfo == NULL) 1161 return; 1162 1163 switch (tag) { 1164 case HDAC_UNSOLTAG_EVENT_HP: 1165 hdac_hp_switch_handler(devinfo); 1166 break; 1167 default: 1168 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1169 break; 1170 } 1171} 1172 1173static int 1174hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1175{ 1176 /* XXX to be removed */ 1177#ifdef HDAC_INTR_EXTRA 1178 uint32_t res; 1179#endif 1180 1181 if (!(ch->flags & HDAC_CHN_RUNNING)) 1182 return (0); 1183 1184 /* XXX to be removed */ 1185#ifdef HDAC_INTR_EXTRA 1186 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1187#endif 1188 1189 /* XXX to be removed */ 1190#ifdef HDAC_INTR_EXTRA 1191 HDA_BOOTVERBOSE( 1192 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1193 device_printf(ch->pdevinfo->dev, 1194 "PCMDIR_%s intr triggered beyond stream boundary:" 1195 "%08x\n", 1196 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1197 ); 1198#endif 1199 1200 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1201 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1202 1203 /* XXX to be removed */ 1204#ifdef HDAC_INTR_EXTRA 1205 if (res & HDAC_SDSTS_BCIS) { 1206#endif 1207 return (1); 1208 /* XXX to be removed */ 1209#ifdef HDAC_INTR_EXTRA 1210 } 1211#endif 1212 1213 return (0); 1214} 1215 1216/**************************************************************************** 1217 * void hdac_intr_handler(void *) 1218 * 1219 * Interrupt handler. Processes interrupts received from the hdac. 1220 ****************************************************************************/ 1221static void 1222hdac_intr_handler(void *context) 1223{ 1224 struct hdac_softc *sc; 1225 uint32_t intsts; 1226 uint8_t rirbsts; 1227 struct hdac_rirb *rirb_base; 1228 uint32_t trigger; 1229 int i; 1230 1231 sc = (struct hdac_softc *)context; 1232 1233 hdac_lock(sc); 1234 if (sc->polling != 0) { 1235 hdac_unlock(sc); 1236 return; 1237 } 1238 1239 /* Do we have anything to do? */ 1240 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1241 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1242 hdac_unlock(sc); 1243 return; 1244 } 1245 1246 trigger = 0; 1247 1248 /* Was this a controller interrupt? */ 1249 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1250 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1251 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1252 /* Get as many responses that we can */ 1253 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1254 HDAC_WRITE_1(&sc->mem, 1255 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1256 if (hdac_rirb_flush(sc) != 0) 1257 trigger |= HDAC_TRIGGER_UNSOL; 1258 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1259 } 1260 /* XXX to be removed */ 1261 /* Clear interrupt and exit */ 1262#ifdef HDAC_INTR_EXTRA 1263 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1264#endif 1265 } 1266 1267 if (intsts & HDAC_INTSTS_SIS_MASK) { 1268 for (i = 0; i < sc->num_chans; i++) { 1269 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1270 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1271 trigger |= (1 << i); 1272 } 1273 /* XXX to be removed */ 1274#ifdef HDAC_INTR_EXTRA 1275 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1276 HDAC_INTSTS_SIS_MASK); 1277#endif 1278 } 1279 1280 hdac_unlock(sc); 1281 1282 for (i = 0; i < sc->num_chans; i++) { 1283 if (trigger & (1 << i)) 1284 chn_intr(sc->chans[i].c); 1285 } 1286 if (trigger & HDAC_TRIGGER_UNSOL) 1287 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1288} 1289 1290/**************************************************************************** 1291 * int hdac_reset(hdac_softc *, int) 1292 * 1293 * Reset the hdac to a quiescent and known state. 1294 ****************************************************************************/ 1295static int 1296hdac_reset(struct hdac_softc *sc, int wakeup) 1297{ 1298 uint32_t gctl; 1299 int count, i; 1300 1301 /* 1302 * Stop all Streams DMA engine 1303 */ 1304 for (i = 0; i < sc->num_iss; i++) 1305 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1306 for (i = 0; i < sc->num_oss; i++) 1307 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1308 for (i = 0; i < sc->num_bss; i++) 1309 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1310 1311 /* 1312 * Stop Control DMA engines. 1313 */ 1314 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1315 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1316 1317 /* 1318 * Reset DMA position buffer. 1319 */ 1320 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1321 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1322 1323 /* 1324 * Reset the controller. The reset must remain asserted for 1325 * a minimum of 100us. 1326 */ 1327 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1328 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1329 count = 10000; 1330 do { 1331 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1332 if (!(gctl & HDAC_GCTL_CRST)) 1333 break; 1334 DELAY(10); 1335 } while (--count); 1336 if (gctl & HDAC_GCTL_CRST) { 1337 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1338 return (ENXIO); 1339 } 1340 1341 /* If wakeup is not requested - leave the controller in reset state. */ 1342 if (!wakeup) 1343 return (0); 1344 1345 DELAY(100); 1346 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1347 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1348 count = 10000; 1349 do { 1350 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1351 if (gctl & HDAC_GCTL_CRST) 1352 break; 1353 DELAY(10); 1354 } while (--count); 1355 if (!(gctl & HDAC_GCTL_CRST)) { 1356 device_printf(sc->dev, "Device stuck in reset\n"); 1357 return (ENXIO); 1358 } 1359 1360 /* 1361 * Wait for codecs to finish their own reset sequence. The delay here 1362 * should be of 250us but for some reasons, on it's not enough on my 1363 * computer. Let's use twice as much as necessary to make sure that 1364 * it's reset properly. 1365 */ 1366 DELAY(1000); 1367 1368 return (0); 1369} 1370 1371 1372/**************************************************************************** 1373 * int hdac_get_capabilities(struct hdac_softc *); 1374 * 1375 * Retreive the general capabilities of the hdac; 1376 * Number of Input Streams 1377 * Number of Output Streams 1378 * Number of bidirectional Streams 1379 * 64bit ready 1380 * CORB and RIRB sizes 1381 ****************************************************************************/ 1382static int 1383hdac_get_capabilities(struct hdac_softc *sc) 1384{ 1385 uint16_t gcap; 1386 uint8_t corbsize, rirbsize; 1387 1388 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1389 sc->num_iss = HDAC_GCAP_ISS(gcap); 1390 sc->num_oss = HDAC_GCAP_OSS(gcap); 1391 sc->num_bss = HDAC_GCAP_BSS(gcap); 1392 1393 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1394 1395 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1396 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1397 HDAC_CORBSIZE_CORBSZCAP_256) 1398 sc->corb_size = 256; 1399 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1400 HDAC_CORBSIZE_CORBSZCAP_16) 1401 sc->corb_size = 16; 1402 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1403 HDAC_CORBSIZE_CORBSZCAP_2) 1404 sc->corb_size = 2; 1405 else { 1406 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1407 __func__, corbsize); 1408 return (ENXIO); 1409 } 1410 1411 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1412 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1413 HDAC_RIRBSIZE_RIRBSZCAP_256) 1414 sc->rirb_size = 256; 1415 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1416 HDAC_RIRBSIZE_RIRBSZCAP_16) 1417 sc->rirb_size = 16; 1418 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1419 HDAC_RIRBSIZE_RIRBSZCAP_2) 1420 sc->rirb_size = 2; 1421 else { 1422 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1423 __func__, rirbsize); 1424 return (ENXIO); 1425 } 1426 1427 HDA_BOOTHVERBOSE( 1428 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1429 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1430 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1431 sc->num_iss, sc->num_oss, sc->num_bss); 1432 ); 1433 1434 return (0); 1435} 1436 1437 1438/**************************************************************************** 1439 * void hdac_dma_cb 1440 * 1441 * This function is called by bus_dmamap_load when the mapping has been 1442 * established. We just record the physical address of the mapping into 1443 * the struct hdac_dma passed in. 1444 ****************************************************************************/ 1445static void 1446hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1447{ 1448 struct hdac_dma *dma; 1449 1450 if (error == 0) { 1451 dma = (struct hdac_dma *)callback_arg; 1452 dma->dma_paddr = segs[0].ds_addr; 1453 } 1454} 1455 1456 1457/**************************************************************************** 1458 * int hdac_dma_alloc 1459 * 1460 * This function allocate and setup a dma region (struct hdac_dma). 1461 * It must be freed by a corresponding hdac_dma_free. 1462 ****************************************************************************/ 1463static int 1464hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1465{ 1466 bus_size_t roundsz; 1467 int result; 1468 int lowaddr; 1469 1470 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1471 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1472 BUS_SPACE_MAXADDR_32BIT; 1473 bzero(dma, sizeof(*dma)); 1474 1475 /* 1476 * Create a DMA tag 1477 */ 1478 result = bus_dma_tag_create(NULL, /* parent */ 1479 HDAC_DMA_ALIGNMENT, /* alignment */ 1480 0, /* boundary */ 1481 lowaddr, /* lowaddr */ 1482 BUS_SPACE_MAXADDR, /* highaddr */ 1483 NULL, /* filtfunc */ 1484 NULL, /* fistfuncarg */ 1485 roundsz, /* maxsize */ 1486 1, /* nsegments */ 1487 roundsz, /* maxsegsz */ 1488 0, /* flags */ 1489 NULL, /* lockfunc */ 1490 NULL, /* lockfuncarg */ 1491 &dma->dma_tag); /* dmat */ 1492 if (result != 0) { 1493 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1494 __func__, result); 1495 goto hdac_dma_alloc_fail; 1496 } 1497 1498 /* 1499 * Allocate DMA memory 1500 */ 1501 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1502 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1503 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1504 &dma->dma_map); 1505 if (result != 0) { 1506 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1507 __func__, result); 1508 goto hdac_dma_alloc_fail; 1509 } 1510 1511 dma->dma_size = roundsz; 1512 1513 /* 1514 * Map the memory 1515 */ 1516 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1517 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1518 if (result != 0 || dma->dma_paddr == 0) { 1519 if (result == 0) 1520 result = ENOMEM; 1521 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1522 __func__, result); 1523 goto hdac_dma_alloc_fail; 1524 } 1525 1526 HDA_BOOTHVERBOSE( 1527 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1528 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1529 ); 1530 1531 return (0); 1532 1533hdac_dma_alloc_fail: 1534 hdac_dma_free(sc, dma); 1535 1536 return (result); 1537} 1538 1539 1540/**************************************************************************** 1541 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1542 * 1543 * Free a struct dhac_dma that has been previously allocated via the 1544 * hdac_dma_alloc function. 1545 ****************************************************************************/ 1546static void 1547hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1548{ 1549 if (dma->dma_map != NULL) { 1550#if 0 1551 /* Flush caches */ 1552 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1553 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1554#endif 1555 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1556 } 1557 if (dma->dma_vaddr != NULL) { 1558 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1559 dma->dma_vaddr = NULL; 1560 } 1561 dma->dma_map = NULL; 1562 if (dma->dma_tag != NULL) { 1563 bus_dma_tag_destroy(dma->dma_tag); 1564 dma->dma_tag = NULL; 1565 } 1566 dma->dma_size = 0; 1567} 1568 1569/**************************************************************************** 1570 * int hdac_mem_alloc(struct hdac_softc *) 1571 * 1572 * Allocate all the bus resources necessary to speak with the physical 1573 * controller. 1574 ****************************************************************************/ 1575static int 1576hdac_mem_alloc(struct hdac_softc *sc) 1577{ 1578 struct hdac_mem *mem; 1579 1580 mem = &sc->mem; 1581 mem->mem_rid = PCIR_BAR(0); 1582 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1583 &mem->mem_rid, RF_ACTIVE); 1584 if (mem->mem_res == NULL) { 1585 device_printf(sc->dev, 1586 "%s: Unable to allocate memory resource\n", __func__); 1587 return (ENOMEM); 1588 } 1589 mem->mem_tag = rman_get_bustag(mem->mem_res); 1590 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1591 1592 return (0); 1593} 1594 1595/**************************************************************************** 1596 * void hdac_mem_free(struct hdac_softc *) 1597 * 1598 * Free up resources previously allocated by hdac_mem_alloc. 1599 ****************************************************************************/ 1600static void 1601hdac_mem_free(struct hdac_softc *sc) 1602{ 1603 struct hdac_mem *mem; 1604 1605 mem = &sc->mem; 1606 if (mem->mem_res != NULL) 1607 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1608 mem->mem_res); 1609 mem->mem_res = NULL; 1610} 1611 1612/**************************************************************************** 1613 * int hdac_irq_alloc(struct hdac_softc *) 1614 * 1615 * Allocate and setup the resources necessary for interrupt handling. 1616 ****************************************************************************/ 1617static int 1618hdac_irq_alloc(struct hdac_softc *sc) 1619{ 1620 struct hdac_irq *irq; 1621 int result; 1622 1623 irq = &sc->irq; 1624 irq->irq_rid = 0x0; 1625 1626#ifdef HDAC_MSI_ENABLED 1627 if ((sc->flags & HDAC_F_MSI) && 1628 (result = pci_msi_count(sc->dev)) == 1 && 1629 pci_alloc_msi(sc->dev, &result) == 0) 1630 irq->irq_rid = 0x1; 1631 else 1632#endif 1633 sc->flags &= ~HDAC_F_MSI; 1634 1635 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1636 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1637 if (irq->irq_res == NULL) { 1638 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1639 __func__); 1640 goto hdac_irq_alloc_fail; 1641 } 1642 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1643 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1644 if (result != 0) { 1645 device_printf(sc->dev, 1646 "%s: Unable to setup interrupt handler (%x)\n", 1647 __func__, result); 1648 goto hdac_irq_alloc_fail; 1649 } 1650 1651 return (0); 1652 1653hdac_irq_alloc_fail: 1654 hdac_irq_free(sc); 1655 1656 return (ENXIO); 1657} 1658 1659/**************************************************************************** 1660 * void hdac_irq_free(struct hdac_softc *) 1661 * 1662 * Free up resources previously allocated by hdac_irq_alloc. 1663 ****************************************************************************/ 1664static void 1665hdac_irq_free(struct hdac_softc *sc) 1666{ 1667 struct hdac_irq *irq; 1668 1669 irq = &sc->irq; 1670 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1671 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1672 if (irq->irq_res != NULL) 1673 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1674 irq->irq_res); 1675#ifdef HDAC_MSI_ENABLED 1676 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1677 pci_release_msi(sc->dev); 1678#endif 1679 irq->irq_handle = NULL; 1680 irq->irq_res = NULL; 1681 irq->irq_rid = 0x0; 1682} 1683 1684/**************************************************************************** 1685 * void hdac_corb_init(struct hdac_softc *) 1686 * 1687 * Initialize the corb registers for operations but do not start it up yet. 1688 * The CORB engine must not be running when this function is called. 1689 ****************************************************************************/ 1690static void 1691hdac_corb_init(struct hdac_softc *sc) 1692{ 1693 uint8_t corbsize; 1694 uint64_t corbpaddr; 1695 1696 /* Setup the CORB size. */ 1697 switch (sc->corb_size) { 1698 case 256: 1699 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1700 break; 1701 case 16: 1702 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1703 break; 1704 case 2: 1705 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1706 break; 1707 default: 1708 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1709 } 1710 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1711 1712 /* Setup the CORB Address in the hdac */ 1713 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1714 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1715 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1716 1717 /* Set the WP and RP */ 1718 sc->corb_wp = 0; 1719 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1720 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1721 /* 1722 * The HDA specification indicates that the CORBRPRST bit will always 1723 * read as zero. Unfortunately, it seems that at least the 82801G 1724 * doesn't reset the bit to zero, which stalls the corb engine. 1725 * manually reset the bit to zero before continuing. 1726 */ 1727 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1728 1729 /* Enable CORB error reporting */ 1730#if 0 1731 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1732#endif 1733} 1734 1735/**************************************************************************** 1736 * void hdac_rirb_init(struct hdac_softc *) 1737 * 1738 * Initialize the rirb registers for operations but do not start it up yet. 1739 * The RIRB engine must not be running when this function is called. 1740 ****************************************************************************/ 1741static void 1742hdac_rirb_init(struct hdac_softc *sc) 1743{ 1744 uint8_t rirbsize; 1745 uint64_t rirbpaddr; 1746 1747 /* Setup the RIRB size. */ 1748 switch (sc->rirb_size) { 1749 case 256: 1750 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1751 break; 1752 case 16: 1753 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1754 break; 1755 case 2: 1756 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1757 break; 1758 default: 1759 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1760 } 1761 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1762 1763 /* Setup the RIRB Address in the hdac */ 1764 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1765 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1766 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1767 1768 /* Setup the WP and RP */ 1769 sc->rirb_rp = 0; 1770 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1771 1772 /* Setup the interrupt threshold */ 1773 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1774 1775 /* Enable Overrun and response received reporting */ 1776#if 0 1777 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1778 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1779#else 1780 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1781#endif 1782 1783#if 0 1784 /* 1785 * Make sure that the Host CPU cache doesn't contain any dirty 1786 * cache lines that falls in the rirb. If I understood correctly, it 1787 * should be sufficient to do this only once as the rirb is purely 1788 * read-only from now on. 1789 */ 1790 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1791 BUS_DMASYNC_PREREAD); 1792#endif 1793} 1794 1795/**************************************************************************** 1796 * void hdac_corb_start(hdac_softc *) 1797 * 1798 * Startup the corb DMA engine 1799 ****************************************************************************/ 1800static void 1801hdac_corb_start(struct hdac_softc *sc) 1802{ 1803 uint32_t corbctl; 1804 1805 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1806 corbctl |= HDAC_CORBCTL_CORBRUN; 1807 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1808} 1809 1810/**************************************************************************** 1811 * void hdac_rirb_start(hdac_softc *) 1812 * 1813 * Startup the rirb DMA engine 1814 ****************************************************************************/ 1815static void 1816hdac_rirb_start(struct hdac_softc *sc) 1817{ 1818 uint32_t rirbctl; 1819 1820 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1821 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1822 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1823} 1824 1825 1826/**************************************************************************** 1827 * void hdac_scan_codecs(struct hdac_softc *, int) 1828 * 1829 * Scan the bus for available codecs, starting with num. 1830 ****************************************************************************/ 1831static void 1832hdac_scan_codecs(struct hdac_softc *sc) 1833{ 1834 struct hdac_codec *codec; 1835 int i; 1836 uint16_t statests; 1837 1838 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1839 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1840 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1841 /* We have found a codec. */ 1842 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1843 M_HDAC, M_ZERO | M_NOWAIT); 1844 if (codec == NULL) { 1845 device_printf(sc->dev, 1846 "Unable to allocate memory for codec\n"); 1847 continue; 1848 } 1849 codec->commands = NULL; 1850 codec->responses_received = 0; 1851 codec->verbs_sent = 0; 1852 codec->sc = sc; 1853 codec->cad = i; 1854 sc->codecs[i] = codec; 1855 hdac_probe_codec(codec); 1856 } 1857 } 1858 /* All codecs have been probed, now try to attach drivers to them */ 1859 /* bus_generic_attach(sc->dev); */ 1860} 1861 1862/**************************************************************************** 1863 * void hdac_probe_codec(struct hdac_softc *, int) 1864 * 1865 * Probe a the given codec_id for available function groups. 1866 ****************************************************************************/ 1867static void 1868hdac_probe_codec(struct hdac_codec *codec) 1869{ 1870 struct hdac_softc *sc = codec->sc; 1871 uint32_t vendorid, revisionid, subnode; 1872 int startnode; 1873 int endnode; 1874 int i; 1875 nid_t cad = codec->cad; 1876 1877 HDA_BOOTVERBOSE( 1878 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1879 ); 1880 vendorid = hdac_command(sc, 1881 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1882 cad); 1883 revisionid = hdac_command(sc, 1884 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1885 cad); 1886 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1887 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1888 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1889 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1890 1891 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1892 device_printf(sc->dev, "Codec #%d is not responding!" 1893 " Probing aborted.\n", cad); 1894 return; 1895 } 1896 1897 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1898 cad, hdac_codec_name(codec)); 1899 HDA_BOOTVERBOSE( 1900 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1901 hdac_codec_id(codec)); 1902 device_printf(sc->dev, " Vendor: 0x%04x\n", 1903 codec->vendor_id); 1904 device_printf(sc->dev, " Device: 0x%04x\n", 1905 codec->device_id); 1906 device_printf(sc->dev, " Revision: 0x%02x\n", 1907 codec->revision_id); 1908 device_printf(sc->dev, " Stepping: 0x%02x\n", 1909 codec->stepping_id); 1910 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1911 sc->pci_subvendor); 1912 ); 1913 subnode = hdac_command(sc, 1914 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1915 cad); 1916 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1917 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1918 1919 HDA_BOOTHVERBOSE( 1920 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1921 startnode, endnode); 1922 ); 1923 1924 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1925 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1926 if (codec->fgs == NULL) { 1927 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1928 __func__); 1929 return; 1930 } 1931 1932 for (i = startnode; i < endnode; i++) 1933 hdac_probe_function(codec, i); 1934 return; 1935} 1936 1937/* 1938 * Probe codec function and add it to the list. 1939 */ 1940static void 1941hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1942{ 1943 struct hdac_softc *sc = codec->sc; 1944 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1945 uint32_t fctgrptype; 1946 uint32_t res; 1947 nid_t cad = codec->cad; 1948 1949 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1950 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1951 1952 devinfo->nid = nid; 1953 devinfo->node_type = fctgrptype; 1954 devinfo->codec = codec; 1955 1956 res = hdac_command(sc, 1957 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1958 1959 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1960 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1961 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1962 1963 HDA_BOOTVERBOSE( 1964 device_printf(sc->dev, 1965 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1966 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1967 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1968 "unknown", nid, devinfo->startnode, devinfo->endnode, 1969 devinfo->nodecnt); 1970 ); 1971 1972 if (devinfo->nodecnt > 0) 1973 devinfo->widget = (struct hdac_widget *)malloc( 1974 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1975 M_NOWAIT | M_ZERO); 1976 else 1977 devinfo->widget = NULL; 1978 1979 if (devinfo->widget == NULL) { 1980 device_printf(sc->dev, "unable to allocate widgets!\n"); 1981 devinfo->endnode = devinfo->startnode; 1982 devinfo->nodecnt = 0; 1983 return; 1984 } 1985 1986 codec->num_fgs++; 1987} 1988 1989static void 1990hdac_widget_connection_parse(struct hdac_widget *w) 1991{ 1992 struct hdac_softc *sc = w->devinfo->codec->sc; 1993 uint32_t res; 1994 int i, j, max, ents, entnum; 1995 nid_t cad = w->devinfo->codec->cad; 1996 nid_t nid = w->nid; 1997 nid_t cnid, addcnid, prevcnid; 1998 1999 w->nconns = 0; 2000 2001 res = hdac_command(sc, 2002 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2003 2004 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2005 2006 if (ents < 1) 2007 return; 2008 2009 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2010 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2011 prevcnid = 0; 2012 2013#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2014#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2015#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2016#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2017#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2018 2019 for (i = 0; i < ents; i += entnum) { 2020 res = hdac_command(sc, 2021 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2022 for (j = 0; j < entnum; j++) { 2023 cnid = CONN_CNID(res, entnum, j); 2024 if (cnid == 0) { 2025 if (w->nconns < ents) 2026 device_printf(sc->dev, 2027 "%s: nid=%d WARNING: zero cnid " 2028 "entnum=%d j=%d index=%d " 2029 "entries=%d found=%d res=0x%08x\n", 2030 __func__, nid, entnum, j, i, 2031 ents, w->nconns, res); 2032 else 2033 goto getconns_out; 2034 } 2035 if (cnid < w->devinfo->startnode || 2036 cnid >= w->devinfo->endnode) { 2037 HDA_BOOTVERBOSE( 2038 device_printf(sc->dev, 2039 "GHOST: nid=%d j=%d " 2040 "entnum=%d index=%d res=0x%08x\n", 2041 nid, j, entnum, i, res); 2042 ); 2043 } 2044 if (CONN_RANGE(res, entnum, j) == 0) 2045 addcnid = cnid; 2046 else if (prevcnid == 0 || prevcnid >= cnid) { 2047 device_printf(sc->dev, 2048 "%s: WARNING: Invalid child range " 2049 "nid=%d index=%d j=%d entnum=%d " 2050 "prevcnid=%d cnid=%d res=0x%08x\n", 2051 __func__, nid, i, j, entnum, prevcnid, 2052 cnid, res); 2053 addcnid = cnid; 2054 } else 2055 addcnid = prevcnid + 1; 2056 while (addcnid <= cnid) { 2057 if (w->nconns > max) { 2058 device_printf(sc->dev, 2059 "Adding %d (nid=%d): " 2060 "Max connection reached! max=%d\n", 2061 addcnid, nid, max + 1); 2062 goto getconns_out; 2063 } 2064 w->connsenable[w->nconns] = 1; 2065 w->conns[w->nconns++] = addcnid++; 2066 } 2067 prevcnid = cnid; 2068 } 2069 } 2070 2071getconns_out: 2072 return; 2073} 2074 2075static uint32_t 2076hdac_widget_pin_patch(uint32_t config, const char *str) 2077{ 2078 char buf[256]; 2079 char *key, *value, *rest, *bad; 2080 int ival, i; 2081 2082 strlcpy(buf, str, sizeof(buf)); 2083 rest = buf; 2084 while ((key = strsep(&rest, "=")) != NULL) { 2085 value = strsep(&rest, " \t"); 2086 if (value == NULL) 2087 break; 2088 ival = strtol(value, &bad, 10); 2089 if (strcmp(key, "seq") == 0) { 2090 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2091 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2092 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2093 } else if (strcmp(key, "as") == 0) { 2094 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2095 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2096 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2097 } else if (strcmp(key, "misc") == 0) { 2098 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2099 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2100 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2101 } else if (strcmp(key, "color") == 0) { 2102 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2103 if (bad[0] == 0) { 2104 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2105 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2106 }; 2107 for (i = 0; i < 16; i++) { 2108 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2109 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2110 break; 2111 } 2112 } 2113 } else if (strcmp(key, "ctype") == 0) { 2114 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2115 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2116 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2117 } else if (strcmp(key, "device") == 0) { 2118 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2119 if (bad[0] == 0) { 2120 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2121 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2122 continue; 2123 }; 2124 for (i = 0; i < 16; i++) { 2125 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2126 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2127 break; 2128 } 2129 } 2130 } else if (strcmp(key, "loc") == 0) { 2131 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2132 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2133 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2134 } else if (strcmp(key, "conn") == 0) { 2135 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2136 if (bad[0] == 0) { 2137 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2138 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2139 continue; 2140 }; 2141 for (i = 0; i < 4; i++) { 2142 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2143 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2144 break; 2145 } 2146 } 2147 } 2148 } 2149 return (config); 2150} 2151 2152static uint32_t 2153hdac_widget_pin_getconfig(struct hdac_widget *w) 2154{ 2155 struct hdac_softc *sc; 2156 uint32_t config, orig, id; 2157 nid_t cad, nid; 2158 char buf[32]; 2159 const char *res = NULL, *patch = NULL; 2160 2161 sc = w->devinfo->codec->sc; 2162 cad = w->devinfo->codec->cad; 2163 nid = w->nid; 2164 id = hdac_codec_id(w->devinfo->codec); 2165 2166 config = hdac_command(sc, 2167 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2168 cad); 2169 orig = config; 2170 2171 HDA_BOOTVERBOSE( 2172 hdac_dump_pin_config(w, orig); 2173 ); 2174 2175 /* XXX: Old patches require complete review. 2176 * Now they may create more problem then solve due to 2177 * incorrect associations. 2178 */ 2179 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2180 switch (nid) { 2181 case 26: 2182 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2183 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2184 break; 2185 case 27: 2186 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2187 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2188 break; 2189 default: 2190 break; 2191 } 2192 } else if (id == HDA_CODEC_ALC880 && 2193 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2194 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2195 /* 2196 * Super broken BIOS 2197 */ 2198 switch (nid) { 2199 case 24: /* MIC1 */ 2200 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2201 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2202 break; 2203 case 25: /* XXX MIC2 */ 2204 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2205 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2206 break; 2207 case 26: /* LINE1 */ 2208 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2209 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2210 break; 2211 case 27: /* XXX LINE2 */ 2212 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2213 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2214 break; 2215 case 28: /* CD */ 2216 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2217 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2218 break; 2219 } 2220 } else if (id == HDA_CODEC_ALC883 && 2221 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2222 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2223 switch (nid) { 2224 case 25: 2225 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2226 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2227 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2228 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2229 break; 2230 case 28: 2231 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2232 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2233 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2234 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2235 break; 2236 } 2237 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2238 HP_V3000_SUBVENDOR) { 2239 switch (nid) { 2240 case 18: 2241 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2242 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2243 break; 2244 case 20: 2245 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2246 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2247 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2248 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2249 break; 2250 case 21: 2251 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2252 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2253 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2254 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2255 break; 2256 } 2257 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2258 HP_DV5000_SUBVENDOR) { 2259 switch (nid) { 2260 case 20: 2261 case 21: 2262 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2263 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2264 break; 2265 } 2266 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2267 ASUS_W6F_SUBVENDOR) { 2268 switch (nid) { 2269 case 11: 2270 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2271 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2272 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2273 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2274 break; 2275 case 12: 2276 case 14: 2277 case 16: 2278 case 31: 2279 case 32: 2280 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2281 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2282 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2283 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2284 break; 2285 case 15: 2286 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2287 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2288 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2289 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2290 break; 2291 } 2292 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2293 UNIWILL_9075_SUBVENDOR) { 2294 switch (nid) { 2295 case 15: 2296 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2297 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2298 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2299 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2300 break; 2301 } 2302 } 2303 2304 /* New patches */ 2305 if (id == HDA_CODEC_AD1986A && 2306 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2307 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2308 switch (nid) { 2309 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2310 patch = "device=Line-in as=8 seq=1"; 2311 break; 2312 case 29: 2313 patch = "device=Mic as=8 seq=2"; 2314 break; 2315 case 31: /* Lot of inputs configured with as=15 and unusable */ 2316 patch = "as=8 seq=3"; 2317 break; 2318 case 32: 2319 patch = "as=8 seq=4"; 2320 break; 2321 case 34: 2322 patch = "as=8 seq=5"; 2323 break; 2324 case 36: 2325 patch = "as=8 seq=6"; 2326 break; 2327 } 2328 } else if (id == HDA_CODEC_ALC260 && 2329 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2330 switch (nid) { 2331 case 16: 2332 patch = "seq=15 device=Headphones"; 2333 break; 2334 } 2335 } else if (id == HDA_CODEC_ALC268 && 2336 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2337 switch (nid) { 2338 case 28: 2339 patch = "device=CD conn=fixed"; 2340 break; 2341 } 2342 } 2343 2344 if (patch != NULL) 2345 config = hdac_widget_pin_patch(config, patch); 2346 2347 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2348 if (resource_string_value(device_get_name(sc->dev), 2349 device_get_unit(sc->dev), buf, &res) == 0) { 2350 if (strncmp(res, "0x", 2) == 0) { 2351 config = strtol(res + 2, NULL, 16); 2352 } else { 2353 config = hdac_widget_pin_patch(config, res); 2354 } 2355 } 2356 2357 HDA_BOOTVERBOSE( 2358 if (config != orig) 2359 device_printf(sc->dev, 2360 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2361 nid, orig, config); 2362 ); 2363 2364 return (config); 2365} 2366 2367static uint32_t 2368hdac_widget_pin_getcaps(struct hdac_widget *w) 2369{ 2370 struct hdac_softc *sc; 2371 uint32_t caps, orig, id; 2372 nid_t cad, nid; 2373 2374 sc = w->devinfo->codec->sc; 2375 cad = w->devinfo->codec->cad; 2376 nid = w->nid; 2377 id = hdac_codec_id(w->devinfo->codec); 2378 2379 caps = hdac_command(sc, 2380 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2381 orig = caps; 2382 2383 HDA_BOOTVERBOSE( 2384 if (caps != orig) 2385 device_printf(sc->dev, 2386 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2387 nid, orig, caps); 2388 ); 2389 2390 return (caps); 2391} 2392 2393static void 2394hdac_widget_pin_parse(struct hdac_widget *w) 2395{ 2396 struct hdac_softc *sc = w->devinfo->codec->sc; 2397 uint32_t config, pincap; 2398 const char *devstr, *connstr; 2399 nid_t cad = w->devinfo->codec->cad; 2400 nid_t nid = w->nid; 2401 2402 config = hdac_widget_pin_getconfig(w); 2403 w->wclass.pin.config = config; 2404 2405 pincap = hdac_widget_pin_getcaps(w); 2406 w->wclass.pin.cap = pincap; 2407 2408 w->wclass.pin.ctrl = hdac_command(sc, 2409 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2410 2411 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2412 w->param.eapdbtl = hdac_command(sc, 2413 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2414 w->param.eapdbtl &= 0x7; 2415 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2416 } else 2417 w->param.eapdbtl = HDAC_INVALID; 2418 2419 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2420 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2421 2422 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2423 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2424 2425 strlcat(w->name, ": ", sizeof(w->name)); 2426 strlcat(w->name, devstr, sizeof(w->name)); 2427 strlcat(w->name, " (", sizeof(w->name)); 2428 strlcat(w->name, connstr, sizeof(w->name)); 2429 strlcat(w->name, ")", sizeof(w->name)); 2430} 2431 2432static uint32_t 2433hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2434{ 2435 struct hdac_softc *sc; 2436 uint32_t caps, orig, id; 2437 nid_t cad, nid, beeper = -1; 2438 2439 sc = w->devinfo->codec->sc; 2440 cad = w->devinfo->codec->cad; 2441 nid = w->nid; 2442 id = hdac_codec_id(w->devinfo->codec); 2443 2444 caps = hdac_command(sc, 2445 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2446 cad); 2447 orig = caps; 2448 2449 /* On some codecs beeper is an input pin, but it is not recordable 2450 alone. Also most of BIOSes does not declare beeper pin. 2451 Change beeper pin node type to beeper to help parser. */ 2452 *waspin = 0; 2453 switch (id) { 2454 case HDA_CODEC_AD1988: 2455 case HDA_CODEC_AD1988B: 2456 beeper = 26; 2457 break; 2458 case HDA_CODEC_ALC260: 2459 beeper = 23; 2460 break; 2461 case HDA_CODEC_ALC262: 2462 case HDA_CODEC_ALC268: 2463 case HDA_CODEC_ALC880: 2464 case HDA_CODEC_ALC882: 2465 case HDA_CODEC_ALC883: 2466 case HDA_CODEC_ALC885: 2467 case HDA_CODEC_ALC888: 2468 case HDA_CODEC_ALC889: 2469 beeper = 29; 2470 break; 2471 } 2472 if (nid == beeper) { 2473 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2474 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2475 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2476 *waspin = 1; 2477 } 2478 2479 HDA_BOOTVERBOSE( 2480 if (caps != orig) { 2481 device_printf(sc->dev, 2482 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2483 nid, orig, caps); 2484 } 2485 ); 2486 2487 return (caps); 2488} 2489 2490static void 2491hdac_widget_parse(struct hdac_widget *w) 2492{ 2493 struct hdac_softc *sc = w->devinfo->codec->sc; 2494 uint32_t wcap, cap; 2495 char *typestr; 2496 nid_t cad = w->devinfo->codec->cad; 2497 nid_t nid = w->nid; 2498 2499 wcap = hdac_widget_getcaps(w, &w->waspin); 2500 2501 w->param.widget_cap = wcap; 2502 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2503 2504 switch (w->type) { 2505 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2506 typestr = "audio output"; 2507 break; 2508 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2509 typestr = "audio input"; 2510 break; 2511 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2512 typestr = "audio mixer"; 2513 break; 2514 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2515 typestr = "audio selector"; 2516 break; 2517 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2518 typestr = "pin"; 2519 break; 2520 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2521 typestr = "power widget"; 2522 break; 2523 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2524 typestr = "volume widget"; 2525 break; 2526 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2527 typestr = "beep widget"; 2528 break; 2529 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2530 typestr = "vendor widget"; 2531 break; 2532 default: 2533 typestr = "unknown type"; 2534 break; 2535 } 2536 2537 strlcpy(w->name, typestr, sizeof(w->name)); 2538 2539 hdac_widget_connection_parse(w); 2540 2541 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2542 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2543 w->param.outamp_cap = 2544 hdac_command(sc, 2545 HDA_CMD_GET_PARAMETER(cad, nid, 2546 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2547 else 2548 w->param.outamp_cap = 2549 w->devinfo->function.audio.outamp_cap; 2550 } else 2551 w->param.outamp_cap = 0; 2552 2553 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2554 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2555 w->param.inamp_cap = 2556 hdac_command(sc, 2557 HDA_CMD_GET_PARAMETER(cad, nid, 2558 HDA_PARAM_INPUT_AMP_CAP), cad); 2559 else 2560 w->param.inamp_cap = 2561 w->devinfo->function.audio.inamp_cap; 2562 } else 2563 w->param.inamp_cap = 0; 2564 2565 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2566 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2567 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2568 cap = hdac_command(sc, 2569 HDA_CMD_GET_PARAMETER(cad, nid, 2570 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2571 w->param.supp_stream_formats = (cap != 0) ? cap : 2572 w->devinfo->function.audio.supp_stream_formats; 2573 cap = hdac_command(sc, 2574 HDA_CMD_GET_PARAMETER(cad, nid, 2575 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2576 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2577 w->devinfo->function.audio.supp_pcm_size_rate; 2578 } else { 2579 w->param.supp_stream_formats = 2580 w->devinfo->function.audio.supp_stream_formats; 2581 w->param.supp_pcm_size_rate = 2582 w->devinfo->function.audio.supp_pcm_size_rate; 2583 } 2584 } else { 2585 w->param.supp_stream_formats = 0; 2586 w->param.supp_pcm_size_rate = 0; 2587 } 2588 2589 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2590 hdac_widget_pin_parse(w); 2591} 2592 2593static struct hdac_widget * 2594hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2595{ 2596 if (devinfo == NULL || devinfo->widget == NULL || 2597 nid < devinfo->startnode || nid >= devinfo->endnode) 2598 return (NULL); 2599 return (&devinfo->widget[nid - devinfo->startnode]); 2600} 2601 2602static __inline int 2603hda_poll_channel(struct hdac_chan *ch) 2604{ 2605 uint32_t sz, delta; 2606 volatile uint32_t ptr; 2607 2608 if (!(ch->flags & HDAC_CHN_RUNNING)) 2609 return (0); 2610 2611 sz = ch->blksz * ch->blkcnt; 2612 if (ch->dmapos != NULL) 2613 ptr = *(ch->dmapos); 2614 else 2615 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2616 ch->off + HDAC_SDLPIB); 2617 ch->ptr = ptr; 2618 ptr %= sz; 2619 ptr &= ~(ch->blksz - 1); 2620 delta = (sz + ptr - ch->prevptr) % sz; 2621 2622 if (delta < ch->blksz) 2623 return (0); 2624 2625 ch->prevptr = ptr; 2626 2627 return (1); 2628} 2629 2630static void 2631hda_poll_callback(void *arg) 2632{ 2633 struct hdac_softc *sc = arg; 2634 uint32_t trigger; 2635 int i, active = 0; 2636 2637 if (sc == NULL) 2638 return; 2639 2640 hdac_lock(sc); 2641 if (sc->polling == 0) { 2642 hdac_unlock(sc); 2643 return; 2644 } 2645 2646 trigger = 0; 2647 for (i = 0; i < sc->num_chans; i++) { 2648 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2649 continue; 2650 active = 1; 2651 if (hda_poll_channel(&sc->chans[i])) 2652 trigger |= (1 << i); 2653 } 2654 2655 /* XXX */ 2656 if (active) 2657 callout_reset(&sc->poll_hda, sc->poll_ticks, 2658 hda_poll_callback, sc); 2659 2660 hdac_unlock(sc); 2661 2662 for (i = 0; i < sc->num_chans; i++) { 2663 if (trigger & (1 << i)) 2664 chn_intr(sc->chans[i].c); 2665 } 2666} 2667 2668static int 2669hdac_rirb_flush(struct hdac_softc *sc) 2670{ 2671 struct hdac_rirb *rirb_base, *rirb; 2672 struct hdac_codec *codec; 2673 struct hdac_command_list *commands; 2674 nid_t cad; 2675 uint32_t resp; 2676 uint8_t rirbwp; 2677 int ret; 2678 2679 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2680 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2681#if 0 2682 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2683 BUS_DMASYNC_POSTREAD); 2684#endif 2685 2686 ret = 0; 2687 2688 while (sc->rirb_rp != rirbwp) { 2689 sc->rirb_rp++; 2690 sc->rirb_rp %= sc->rirb_size; 2691 rirb = &rirb_base[sc->rirb_rp]; 2692 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2693 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2694 sc->codecs[cad] == NULL) 2695 continue; 2696 resp = rirb->response; 2697 codec = sc->codecs[cad]; 2698 commands = codec->commands; 2699 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2700 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2701 ((resp >> 26) & 0xffff); 2702 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2703 } else if (commands != NULL && commands->num_commands > 0 && 2704 codec->responses_received < commands->num_commands) 2705 commands->responses[codec->responses_received++] = 2706 resp; 2707 ret++; 2708 } 2709 2710 return (ret); 2711} 2712 2713static int 2714hdac_unsolq_flush(struct hdac_softc *sc) 2715{ 2716 nid_t cad; 2717 uint32_t tag; 2718 int ret = 0; 2719 2720 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2721 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2722 while (sc->unsolq_rp != sc->unsolq_wp) { 2723 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2724 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2725 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2726 hdac_unsolicited_handler(sc->codecs[cad], tag); 2727 ret++; 2728 } 2729 sc->unsolq_st = HDAC_UNSOLQ_READY; 2730 } 2731 2732 return (ret); 2733} 2734 2735static void 2736hdac_poll_callback(void *arg) 2737{ 2738 struct hdac_softc *sc = arg; 2739 if (sc == NULL) 2740 return; 2741 2742 hdac_lock(sc); 2743 if (sc->polling == 0 || sc->poll_ival == 0) { 2744 hdac_unlock(sc); 2745 return; 2746 } 2747 if (hdac_rirb_flush(sc) != 0) 2748 hdac_unsolq_flush(sc); 2749 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2750 hdac_unlock(sc); 2751} 2752 2753static void 2754hdac_poll_reinit(struct hdac_softc *sc) 2755{ 2756 int i, pollticks, min = 1000000; 2757 struct hdac_chan *ch; 2758 2759 for (i = 0; i < sc->num_chans; i++) { 2760 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2761 continue; 2762 ch = &sc->chans[i]; 2763 pollticks = ((uint64_t)hz * ch->blksz) / 2764 ((uint64_t)sndbuf_getbps(ch->b) * 2765 sndbuf_getspd(ch->b)); 2766 pollticks >>= 1; 2767 if (pollticks > hz) 2768 pollticks = hz; 2769 if (pollticks < 1) { 2770 HDA_BOOTVERBOSE( 2771 device_printf(sc->dev, 2772 "%s: pollticks=%d < 1 !\n", 2773 __func__, pollticks); 2774 ); 2775 pollticks = 1; 2776 } 2777 if (min > pollticks) 2778 min = pollticks; 2779 } 2780 HDA_BOOTVERBOSE( 2781 device_printf(sc->dev, 2782 "%s: pollticks %d -> %d\n", 2783 __func__, sc->poll_ticks, min); 2784 ); 2785 sc->poll_ticks = min; 2786 if (min == 1000000) 2787 callout_stop(&sc->poll_hda); 2788 else 2789 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2790} 2791 2792static void 2793hdac_stream_stop(struct hdac_chan *ch) 2794{ 2795 struct hdac_softc *sc = ch->devinfo->codec->sc; 2796 uint32_t ctl; 2797 2798 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2799 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2800 HDAC_SDCTL_RUN); 2801 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2802 2803 ch->flags &= ~HDAC_CHN_RUNNING; 2804 2805 if (sc->polling != 0) 2806 hdac_poll_reinit(sc); 2807 2808 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2809 ctl &= ~(1 << (ch->off >> 5)); 2810 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2811} 2812 2813static void 2814hdac_stream_start(struct hdac_chan *ch) 2815{ 2816 struct hdac_softc *sc = ch->devinfo->codec->sc; 2817 uint32_t ctl; 2818 2819 ch->flags |= HDAC_CHN_RUNNING; 2820 2821 if (sc->polling != 0) 2822 hdac_poll_reinit(sc); 2823 2824 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2825 ctl |= 1 << (ch->off >> 5); 2826 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2827 2828 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2829 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2830 HDAC_SDCTL_RUN; 2831 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2832} 2833 2834static void 2835hdac_stream_reset(struct hdac_chan *ch) 2836{ 2837 struct hdac_softc *sc = ch->devinfo->codec->sc; 2838 int timeout = 1000; 2839 int to = timeout; 2840 uint32_t ctl; 2841 2842 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2843 ctl |= HDAC_SDCTL_SRST; 2844 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2845 do { 2846 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2847 if (ctl & HDAC_SDCTL_SRST) 2848 break; 2849 DELAY(10); 2850 } while (--to); 2851 if (!(ctl & HDAC_SDCTL_SRST)) { 2852 device_printf(sc->dev, "timeout in reset\n"); 2853 } 2854 ctl &= ~HDAC_SDCTL_SRST; 2855 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2856 to = timeout; 2857 do { 2858 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2859 if (!(ctl & HDAC_SDCTL_SRST)) 2860 break; 2861 DELAY(10); 2862 } while (--to); 2863 if (ctl & HDAC_SDCTL_SRST) 2864 device_printf(sc->dev, "can't reset!\n"); 2865} 2866 2867static void 2868hdac_stream_setid(struct hdac_chan *ch) 2869{ 2870 struct hdac_softc *sc = ch->devinfo->codec->sc; 2871 uint32_t ctl; 2872 2873 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2874 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2875 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2876 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2877} 2878 2879static void 2880hdac_bdl_setup(struct hdac_chan *ch) 2881{ 2882 struct hdac_softc *sc = ch->devinfo->codec->sc; 2883 struct hdac_bdle *bdle; 2884 uint64_t addr; 2885 uint32_t blksz, blkcnt; 2886 int i; 2887 2888 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2889 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2890 2891 blksz = ch->blksz; 2892 blkcnt = ch->blkcnt; 2893 2894 for (i = 0; i < blkcnt; i++, bdle++) { 2895 bdle->addrl = (uint32_t)addr; 2896 bdle->addrh = (uint32_t)(addr >> 32); 2897 bdle->len = blksz; 2898 bdle->ioc = 1; 2899 addr += blksz; 2900 } 2901 2902 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2903 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2904 addr = ch->bdl_dma.dma_paddr; 2905 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2906 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2907 if (ch->dmapos != NULL && 2908 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2909 addr = sc->pos_dma.dma_paddr; 2910 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2911 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2912 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2913 } 2914} 2915 2916static int 2917hdac_bdl_alloc(struct hdac_chan *ch) 2918{ 2919 struct hdac_softc *sc = ch->devinfo->codec->sc; 2920 int rc; 2921 2922 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2923 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2924 if (rc) { 2925 device_printf(sc->dev, "can't alloc bdl\n"); 2926 return (rc); 2927 } 2928 2929 return (0); 2930} 2931 2932static void 2933hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2934 int index, int lmute, int rmute, 2935 int left, int right, int dir) 2936{ 2937 uint16_t v = 0; 2938 2939 if (sc == NULL) 2940 return; 2941 2942 if (left != right || lmute != rmute) { 2943 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2944 (lmute << 7) | left; 2945 hdac_command(sc, 2946 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2947 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2948 (rmute << 7) | right; 2949 } else 2950 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2951 (lmute << 7) | left; 2952 2953 hdac_command(sc, 2954 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2955} 2956 2957static void 2958hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2959 int left, int right) 2960{ 2961 struct hdac_softc *sc; 2962 nid_t nid, cad; 2963 int lmute, rmute; 2964 2965 sc = ctl->widget->devinfo->codec->sc; 2966 cad = ctl->widget->devinfo->codec->cad; 2967 nid = ctl->widget->nid; 2968 2969 /* Save new values if valid. */ 2970 if (mute != HDA_AMP_MUTE_DEFAULT) 2971 ctl->muted = mute; 2972 if (left != HDA_AMP_VOL_DEFAULT) 2973 ctl->left = left; 2974 if (right != HDA_AMP_VOL_DEFAULT) 2975 ctl->right = right; 2976 /* Prepare effective values */ 2977 if (ctl->forcemute) { 2978 lmute = 1; 2979 rmute = 1; 2980 left = 0; 2981 right = 0; 2982 } else { 2983 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2984 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2985 left = ctl->left; 2986 right = ctl->right; 2987 } 2988 /* Apply effective values */ 2989 if (ctl->dir & HDA_CTL_OUT) 2990 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2991 lmute, rmute, left, right, 0); 2992 if (ctl->dir & HDA_CTL_IN) 2993 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2994 lmute, rmute, left, right, 1); 2995} 2996 2997static void 2998hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2999{ 3000 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3001 return; 3002 hdac_command(w->devinfo->codec->sc, 3003 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3004 w->nid, index), w->devinfo->codec->cad); 3005 w->selconn = index; 3006} 3007 3008 3009/**************************************************************************** 3010 * uint32_t hdac_command_sendone_internal 3011 * 3012 * Wrapper function that sends only one command to a given codec 3013 ****************************************************************************/ 3014static uint32_t 3015hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3016{ 3017 struct hdac_command_list cl; 3018 uint32_t response = HDAC_INVALID; 3019 3020 if (!hdac_lockowned(sc)) 3021 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3022 cl.num_commands = 1; 3023 cl.verbs = &verb; 3024 cl.responses = &response; 3025 3026 hdac_command_send_internal(sc, &cl, cad); 3027 3028 return (response); 3029} 3030 3031/**************************************************************************** 3032 * hdac_command_send_internal 3033 * 3034 * Send a command list to the codec via the corb. We queue as much verbs as 3035 * we can and msleep on the codec. When the interrupt get the responses 3036 * back from the rirb, it will wake us up so we can queue the remaining verbs 3037 * if any. 3038 ****************************************************************************/ 3039static void 3040hdac_command_send_internal(struct hdac_softc *sc, 3041 struct hdac_command_list *commands, nid_t cad) 3042{ 3043 struct hdac_codec *codec; 3044 int corbrp; 3045 uint32_t *corb; 3046 int timeout; 3047 int retry = 10; 3048 struct hdac_rirb *rirb_base; 3049 3050 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3051 commands->num_commands < 1) 3052 return; 3053 3054 codec = sc->codecs[cad]; 3055 codec->commands = commands; 3056 codec->responses_received = 0; 3057 codec->verbs_sent = 0; 3058 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3059 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3060 3061 do { 3062 if (codec->verbs_sent != commands->num_commands) { 3063 /* Queue as many verbs as possible */ 3064 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3065#if 0 3066 bus_dmamap_sync(sc->corb_dma.dma_tag, 3067 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3068#endif 3069 while (codec->verbs_sent != commands->num_commands && 3070 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3071 sc->corb_wp++; 3072 sc->corb_wp %= sc->corb_size; 3073 corb[sc->corb_wp] = 3074 commands->verbs[codec->verbs_sent++]; 3075 } 3076 3077 /* Send the verbs to the codecs */ 3078#if 0 3079 bus_dmamap_sync(sc->corb_dma.dma_tag, 3080 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3081#endif 3082 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3083 } 3084 3085 timeout = 1000; 3086 while (hdac_rirb_flush(sc) == 0 && --timeout) 3087 DELAY(10); 3088 } while ((codec->verbs_sent != commands->num_commands || 3089 codec->responses_received != commands->num_commands) && --retry); 3090 3091 if (retry == 0) 3092 device_printf(sc->dev, 3093 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3094 __func__, commands->num_commands, codec->verbs_sent, 3095 codec->responses_received); 3096 3097 codec->commands = NULL; 3098 codec->responses_received = 0; 3099 codec->verbs_sent = 0; 3100 3101 hdac_unsolq_flush(sc); 3102} 3103 3104 3105/**************************************************************************** 3106 * Device Methods 3107 ****************************************************************************/ 3108 3109/**************************************************************************** 3110 * int hdac_probe(device_t) 3111 * 3112 * Probe for the presence of an hdac. If none is found, check for a generic 3113 * match using the subclass of the device. 3114 ****************************************************************************/ 3115static int 3116hdac_probe(device_t dev) 3117{ 3118 int i, result; 3119 uint32_t model; 3120 uint16_t class, subclass; 3121 char desc[64]; 3122 3123 model = (uint32_t)pci_get_device(dev) << 16; 3124 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3125 class = pci_get_class(dev); 3126 subclass = pci_get_subclass(dev); 3127 3128 bzero(desc, sizeof(desc)); 3129 result = ENXIO; 3130 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3131 if (hdac_devices[i].model == model) { 3132 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3133 result = BUS_PROBE_DEFAULT; 3134 break; 3135 } 3136 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3137 class == PCIC_MULTIMEDIA && 3138 subclass == PCIS_MULTIMEDIA_HDA) { 3139 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3140 result = BUS_PROBE_GENERIC; 3141 break; 3142 } 3143 } 3144 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3145 subclass == PCIS_MULTIMEDIA_HDA) { 3146 strlcpy(desc, "Generic", sizeof(desc)); 3147 result = BUS_PROBE_GENERIC; 3148 } 3149 if (result != ENXIO) { 3150 strlcat(desc, " High Definition Audio Controller", 3151 sizeof(desc)); 3152 device_set_desc_copy(dev, desc); 3153 } 3154 3155 return (result); 3156} 3157 3158static void * 3159hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3160 struct pcm_channel *c, int dir) 3161{ 3162 struct hdac_pcm_devinfo *pdevinfo = data; 3163 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3164 struct hdac_softc *sc = devinfo->codec->sc; 3165 struct hdac_chan *ch; 3166 int i, ord = 0, chid; 3167 3168 hdac_lock(sc); 3169 3170 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3171 ch = &sc->chans[chid]; 3172 for (i = 0; i < sc->num_chans && i < chid; i++) { 3173 if (ch->dir == sc->chans[i].dir) 3174 ord++; 3175 } 3176 if (dir == PCMDIR_PLAY) { 3177 ch->off = (sc->num_iss + ord) << 5; 3178 } else { 3179 ch->off = ord << 5; 3180 } 3181 3182 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3183 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3184 ch->pcmrates[0] = 48000; 3185 ch->pcmrates[1] = 0; 3186 } 3187 if (sc->pos_dma.dma_vaddr != NULL) 3188 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3189 (sc->streamcnt * 8)); 3190 else 3191 ch->dmapos = NULL; 3192 ch->sid = ++sc->streamcnt; 3193 ch->dir = dir; 3194 ch->b = b; 3195 ch->c = c; 3196 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3197 ch->blkcnt = pdevinfo->chan_blkcnt; 3198 hdac_unlock(sc); 3199 3200 if (hdac_bdl_alloc(ch) != 0) { 3201 ch->blkcnt = 0; 3202 return (NULL); 3203 } 3204 3205 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3206 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3207 pdevinfo->chan_size) != 0) 3208 return (NULL); 3209 3210 return (ch); 3211} 3212 3213static int 3214hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3215{ 3216 struct hdac_chan *ch = data; 3217 int i; 3218 3219 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3220 if (format == ch->caps.fmtlist[i]) { 3221 ch->fmt = format; 3222 return (0); 3223 } 3224 } 3225 3226 return (EINVAL); 3227} 3228 3229static int 3230hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3231{ 3232 struct hdac_chan *ch = data; 3233 uint32_t spd = 0, threshold; 3234 int i; 3235 3236 for (i = 0; ch->pcmrates[i] != 0; i++) { 3237 spd = ch->pcmrates[i]; 3238 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3239 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3240 if (speed < threshold) 3241 break; 3242 } 3243 3244 if (spd == 0) /* impossible */ 3245 ch->spd = 48000; 3246 else 3247 ch->spd = spd; 3248 3249 return (ch->spd); 3250} 3251 3252static void 3253hdac_stream_setup(struct hdac_chan *ch) 3254{ 3255 struct hdac_softc *sc = ch->devinfo->codec->sc; 3256 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3257 struct hdac_widget *w; 3258 int i, chn, totalchn, c; 3259 nid_t cad = ch->devinfo->codec->cad; 3260 uint16_t fmt, dfmt; 3261 3262 HDA_BOOTHVERBOSE( 3263 device_printf(ch->pdevinfo->dev, 3264 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3265 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3266 ch->fmt, ch->spd); 3267 ); 3268 fmt = 0; 3269 if (ch->fmt & AFMT_S16_LE) 3270 fmt |= ch->bit16 << 4; 3271 else if (ch->fmt & AFMT_S32_LE) 3272 fmt |= ch->bit32 << 4; 3273 else 3274 fmt |= 1 << 4; 3275 3276 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3277 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3278 fmt |= hda_rate_tab[i].base; 3279 fmt |= hda_rate_tab[i].mul; 3280 fmt |= hda_rate_tab[i].div; 3281 break; 3282 } 3283 } 3284 3285 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3286 fmt |= 1; 3287 totalchn = 2; 3288 } else 3289 totalchn = 1; 3290 3291 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3292 3293 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3294 if (ch->fmt & AFMT_AC3) 3295 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3296 3297 chn = 0; 3298 for (i = 0; ch->io[i] != -1; i++) { 3299 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3300 if (w == NULL) 3301 continue; 3302 3303 if (as->hpredir >= 0 && i == as->pincnt) 3304 chn = 0; 3305 HDA_BOOTHVERBOSE( 3306 device_printf(ch->pdevinfo->dev, 3307 "PCMDIR_%s: Stream setup nid=%d: " 3308 "fmt=0x%04x, dfmt=0x%04x\n", 3309 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3310 ch->io[i], fmt, dfmt); 3311 ); 3312 hdac_command(sc, 3313 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3314 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3315 hdac_command(sc, 3316 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3317 cad); 3318 } 3319 /* If HP redirection is enabled, but failed to use same 3320 DAC make last DAC one to duplicate first one. */ 3321 if (as->hpredir >= 0 && i == as->pincnt) { 3322 c = (ch->sid << 4); 3323 } else if (chn >= totalchn) { 3324 /* This is until OSS will support multichannel. 3325 Should be: c = 0; to disable unused DAC */ 3326 c = (ch->sid << 4); 3327 }else { 3328 c = (ch->sid << 4) | chn; 3329 } 3330 hdac_command(sc, 3331 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3332 chn += 3333 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3334 2 : 1; 3335 } 3336} 3337 3338static int 3339hdac_channel_setfragments(kobj_t obj, void *data, 3340 uint32_t blksz, uint32_t blkcnt) 3341{ 3342 struct hdac_chan *ch = data; 3343 struct hdac_softc *sc = ch->devinfo->codec->sc; 3344 3345 blksz &= HDA_BLK_ALIGN; 3346 3347 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3348 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3349 if (blksz < HDA_BLK_MIN) 3350 blksz = HDA_BLK_MIN; 3351 if (blkcnt > HDA_BDL_MAX) 3352 blkcnt = HDA_BDL_MAX; 3353 if (blkcnt < HDA_BDL_MIN) 3354 blkcnt = HDA_BDL_MIN; 3355 3356 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3357 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3358 blkcnt >>= 1; 3359 else if ((blksz >> 1) >= HDA_BLK_MIN) 3360 blksz >>= 1; 3361 else 3362 break; 3363 } 3364 3365 if ((sndbuf_getblksz(ch->b) != blksz || 3366 sndbuf_getblkcnt(ch->b) != blkcnt) && 3367 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3368 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3369 __func__, blksz, blkcnt); 3370 3371 ch->blksz = sndbuf_getblksz(ch->b); 3372 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3373 3374 return (1); 3375} 3376 3377static int 3378hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3379{ 3380 struct hdac_chan *ch = data; 3381 3382 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3383 3384 return (ch->blksz); 3385} 3386 3387static void 3388hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3389{ 3390 struct hdac_devinfo *devinfo = ch->devinfo; 3391 struct hdac_widget *w; 3392 nid_t cad = devinfo->codec->cad; 3393 int i; 3394 3395 hdac_stream_stop(ch); 3396 3397 for (i = 0; ch->io[i] != -1; i++) { 3398 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3399 if (w == NULL) 3400 continue; 3401 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3402 hdac_command(sc, 3403 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3404 cad); 3405 } 3406 hdac_command(sc, 3407 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3408 0), cad); 3409 } 3410} 3411 3412static void 3413hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3414{ 3415 ch->ptr = 0; 3416 ch->prevptr = 0; 3417 hdac_stream_stop(ch); 3418 hdac_stream_reset(ch); 3419 hdac_bdl_setup(ch); 3420 hdac_stream_setid(ch); 3421 hdac_stream_setup(ch); 3422 hdac_stream_start(ch); 3423} 3424 3425static int 3426hdac_channel_trigger(kobj_t obj, void *data, int go) 3427{ 3428 struct hdac_chan *ch = data; 3429 struct hdac_softc *sc = ch->devinfo->codec->sc; 3430 3431 if (!PCMTRIG_COMMON(go)) 3432 return (0); 3433 3434 hdac_lock(sc); 3435 switch (go) { 3436 case PCMTRIG_START: 3437 hdac_channel_start(sc, ch); 3438 break; 3439 case PCMTRIG_STOP: 3440 case PCMTRIG_ABORT: 3441 hdac_channel_stop(sc, ch); 3442 break; 3443 default: 3444 break; 3445 } 3446 hdac_unlock(sc); 3447 3448 return (0); 3449} 3450 3451static int 3452hdac_channel_getptr(kobj_t obj, void *data) 3453{ 3454 struct hdac_chan *ch = data; 3455 struct hdac_softc *sc = ch->devinfo->codec->sc; 3456 uint32_t ptr; 3457 3458 hdac_lock(sc); 3459 if (sc->polling != 0) 3460 ptr = ch->ptr; 3461 else if (ch->dmapos != NULL) 3462 ptr = *(ch->dmapos); 3463 else 3464 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3465 hdac_unlock(sc); 3466 3467 /* 3468 * Round to available space and force 128 bytes aligment. 3469 */ 3470 ptr %= ch->blksz * ch->blkcnt; 3471 ptr &= HDA_BLK_ALIGN; 3472 3473 return (ptr); 3474} 3475 3476static struct pcmchan_caps * 3477hdac_channel_getcaps(kobj_t obj, void *data) 3478{ 3479 return (&((struct hdac_chan *)data)->caps); 3480} 3481 3482static kobj_method_t hdac_channel_methods[] = { 3483 KOBJMETHOD(channel_init, hdac_channel_init), 3484 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3485 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3486 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3487 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3488 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3489 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3490 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3491 { 0, 0 } 3492}; 3493CHANNEL_DECLARE(hdac_channel); 3494 3495static int 3496hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3497{ 3498 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3499 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3500 struct hdac_softc *sc = devinfo->codec->sc; 3501 struct hdac_widget *w, *cw; 3502 struct hdac_audio_ctl *ctl; 3503 uint32_t mask, recmask, id; 3504 int i, j, softpcmvol; 3505 3506 hdac_lock(sc); 3507 3508 /* Make sure that in case of soft volume it won't stay muted. */ 3509 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3510 pdevinfo->left[i] = 100; 3511 pdevinfo->right[i] = 100; 3512 } 3513 3514 mask = 0; 3515 recmask = 0; 3516 id = hdac_codec_id(devinfo->codec); 3517 3518 /* Declate EAPD as ogain control. */ 3519 if (pdevinfo->play >= 0) { 3520 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3521 w = hdac_widget_get(devinfo, i); 3522 if (w == NULL || w->enable == 0) 3523 continue; 3524 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3525 w->param.eapdbtl == HDAC_INVALID || 3526 w->bindas != sc->chans[pdevinfo->play].as) 3527 continue; 3528 mask |= SOUND_MASK_OGAIN; 3529 break; 3530 } 3531 } 3532 3533 /* Declare volume controls assigned to this association. */ 3534 i = 0; 3535 ctl = NULL; 3536 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3537 if (ctl->enable == 0) 3538 continue; 3539 if ((pdevinfo->play >= 0 && 3540 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3541 (pdevinfo->rec >= 0 && 3542 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3543 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3544 mask |= ctl->ossmask; 3545 } 3546 3547 /* Declare record sources available to this association. */ 3548 if (pdevinfo->rec >= 0) { 3549 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3550 for (i = 0; ch->io[i] != -1; i++) { 3551 w = hdac_widget_get(devinfo, ch->io[i]); 3552 if (w == NULL || w->enable == 0) 3553 continue; 3554 for (j = 0; j < w->nconns; j++) { 3555 if (w->connsenable[j] == 0) 3556 continue; 3557 cw = hdac_widget_get(devinfo, w->conns[j]); 3558 if (cw == NULL || cw->enable == 0) 3559 continue; 3560 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3561 cw->bindas != -2) 3562 continue; 3563 recmask |= cw->ossmask; 3564 } 3565 } 3566 } 3567 3568 /* Declare soft PCM volume if needed. */ 3569 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3570 ctl = NULL; 3571 if ((mask & SOUND_MASK_PCM) == 0 || 3572 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3573 softpcmvol = 1; 3574 mask |= SOUND_MASK_PCM; 3575 } else { 3576 softpcmvol = 0; 3577 i = 0; 3578 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3579 if (ctl->enable == 0) 3580 continue; 3581 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3582 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3583 continue; 3584 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3585 continue; 3586 if (ctl->step > 0) 3587 break; 3588 } 3589 } 3590 3591 if (softpcmvol == 1 || ctl == NULL) { 3592 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3593 HDA_BOOTVERBOSE( 3594 device_printf(pdevinfo->dev, 3595 "%s Soft PCM volume\n", 3596 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3597 ); 3598 } 3599 } 3600 3601 /* Declare master volume if needed. */ 3602 if (pdevinfo->play >= 0) { 3603 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3604 SOUND_MASK_PCM) { 3605 mask |= SOUND_MASK_VOLUME; 3606 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3607 SOUND_MASK_PCM); 3608 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3609 SOUND_MIXER_NONE); 3610 HDA_BOOTVERBOSE( 3611 device_printf(pdevinfo->dev, 3612 "Forcing master volume with PCM\n"); 3613 ); 3614 } 3615 } 3616 3617 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3618 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3619 3620 mix_setrecdevs(m, recmask); 3621 mix_setdevs(m, mask); 3622 3623 hdac_unlock(sc); 3624 3625 return (0); 3626} 3627 3628static int 3629hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3630 unsigned left, unsigned right) 3631{ 3632 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3633 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3634 struct hdac_softc *sc = devinfo->codec->sc; 3635 struct hdac_widget *w; 3636 struct hdac_audio_ctl *ctl; 3637 uint32_t mute; 3638 int lvol, rvol; 3639 int i, j; 3640 3641 hdac_lock(sc); 3642 /* Save new values. */ 3643 pdevinfo->left[dev] = left; 3644 pdevinfo->right[dev] = right; 3645 3646 /* 'ogain' is the special case implemented with EAPD. */ 3647 if (dev == SOUND_MIXER_OGAIN) { 3648 uint32_t orig; 3649 w = NULL; 3650 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3651 w = hdac_widget_get(devinfo, i); 3652 if (w == NULL || w->enable == 0) 3653 continue; 3654 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3655 w->param.eapdbtl == HDAC_INVALID) 3656 continue; 3657 break; 3658 } 3659 if (i >= devinfo->endnode) { 3660 hdac_unlock(sc); 3661 return (-1); 3662 } 3663 orig = w->param.eapdbtl; 3664 if (left == 0) 3665 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3666 else 3667 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3668 if (orig != w->param.eapdbtl) { 3669 uint32_t val; 3670 3671 val = w->param.eapdbtl; 3672 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3673 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3674 hdac_command(sc, 3675 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3676 w->nid, val), devinfo->codec->cad); 3677 } 3678 hdac_unlock(sc); 3679 return (left | (left << 8)); 3680 } 3681 3682 /* Recalculate all controls related to this OSS device. */ 3683 i = 0; 3684 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3685 if (ctl->enable == 0 || 3686 !(ctl->ossmask & (1 << dev))) 3687 continue; 3688 if (!((pdevinfo->play >= 0 && 3689 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3690 (pdevinfo->rec >= 0 && 3691 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3692 ctl->widget->bindas == -2)) 3693 continue; 3694 3695 lvol = 100; 3696 rvol = 100; 3697 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3698 if (ctl->ossmask & (1 << j)) { 3699 lvol = lvol * pdevinfo->left[j] / 100; 3700 rvol = rvol * pdevinfo->right[j] / 100; 3701 } 3702 } 3703 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3704 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3705 lvol = (lvol * ctl->step + 50) / 100; 3706 rvol = (rvol * ctl->step + 50) / 100; 3707 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3708 } 3709 hdac_unlock(sc); 3710 3711 return (left | (right << 8)); 3712} 3713 3714/* 3715 * Commutate specified record source. 3716 */ 3717static uint32_t 3718hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3719{ 3720 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3721 struct hdac_widget *w, *cw; 3722 struct hdac_audio_ctl *ctl; 3723 char buf[64]; 3724 int i, muted; 3725 uint32_t res = 0; 3726 3727 if (depth > HDA_PARSE_MAXDEPTH) 3728 return (0); 3729 3730 w = hdac_widget_get(devinfo, nid); 3731 if (w == NULL || w->enable == 0) 3732 return (0); 3733 3734 for (i = 0; i < w->nconns; i++) { 3735 if (w->connsenable[i] == 0) 3736 continue; 3737 cw = hdac_widget_get(devinfo, w->conns[i]); 3738 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3739 continue; 3740 /* Call recursively to trace signal to it's source if needed. */ 3741 if ((src & cw->ossmask) != 0) { 3742 if (cw->ossdev < 0) { 3743 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3744 w->conns[i], depth + 1); 3745 } else { 3746 res |= cw->ossmask; 3747 } 3748 } 3749 /* We have two special cases: mixers and others (selectors). */ 3750 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3751 ctl = hdac_audio_ctl_amp_get(devinfo, 3752 w->nid, HDA_CTL_IN, i, 1); 3753 if (ctl == NULL) 3754 continue; 3755 /* If we have input control on this node mute them 3756 * according to requested sources. */ 3757 muted = (src & cw->ossmask) ? 0 : 1; 3758 if (muted != ctl->forcemute) { 3759 ctl->forcemute = muted; 3760 hdac_audio_ctl_amp_set(ctl, 3761 HDA_AMP_MUTE_DEFAULT, 3762 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3763 } 3764 HDA_BOOTHVERBOSE( 3765 device_printf(pdevinfo->dev, 3766 "Recsel (%s): nid %d source %d %s\n", 3767 hdac_audio_ctl_ossmixer_mask2allname( 3768 src, buf, sizeof(buf)), 3769 nid, i, muted?"mute":"unmute"); 3770 ); 3771 } else { 3772 if (w->nconns == 1) 3773 break; 3774 if ((src & cw->ossmask) == 0) 3775 continue; 3776 /* If we found requested source - select it and exit. */ 3777 hdac_widget_connection_select(w, i); 3778 HDA_BOOTHVERBOSE( 3779 device_printf(pdevinfo->dev, 3780 "Recsel (%s): nid %d source %d select\n", 3781 hdac_audio_ctl_ossmixer_mask2allname( 3782 src, buf, sizeof(buf)), 3783 nid, i); 3784 ); 3785 break; 3786 } 3787 } 3788 return (res); 3789} 3790 3791static uint32_t 3792hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3793{ 3794 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3795 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3796 struct hdac_widget *w; 3797 struct hdac_softc *sc = devinfo->codec->sc; 3798 struct hdac_chan *ch; 3799 int i; 3800 uint32_t ret = 0xffffffff; 3801 3802 hdac_lock(sc); 3803 3804 /* Commutate requested recsrc for each ADC. */ 3805 ch = &sc->chans[pdevinfo->rec]; 3806 for (i = 0; ch->io[i] != -1; i++) { 3807 w = hdac_widget_get(devinfo, ch->io[i]); 3808 if (w == NULL || w->enable == 0) 3809 continue; 3810 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3811 } 3812 3813 hdac_unlock(sc); 3814 3815 return ((ret == 0xffffffff)? 0 : ret); 3816} 3817 3818static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3819 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3820 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3821 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3822 { 0, 0 } 3823}; 3824MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3825 3826static void 3827hdac_unsolq_task(void *context, int pending) 3828{ 3829 struct hdac_softc *sc; 3830 3831 sc = (struct hdac_softc *)context; 3832 3833 hdac_lock(sc); 3834 hdac_unsolq_flush(sc); 3835 hdac_unlock(sc); 3836} 3837 3838/**************************************************************************** 3839 * int hdac_attach(device_t) 3840 * 3841 * Attach the device into the kernel. Interrupts usually won't be enabled 3842 * when this function is called. Setup everything that doesn't require 3843 * interrupts and defer probing of codecs until interrupts are enabled. 3844 ****************************************************************************/ 3845static int 3846hdac_attach(device_t dev) 3847{ 3848 struct hdac_softc *sc; 3849 int result; 3850 int i; 3851 uint16_t vendor; 3852 uint8_t v; 3853 3854 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3855 3856 sc = device_get_softc(dev); 3857 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3858 sc->dev = dev; 3859 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3860 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3861 vendor = pci_get_vendor(dev); 3862 3863 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3864 /* Screw nx6325 - subdevice/subvendor swapped */ 3865 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3866 } 3867 3868 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3869 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3870 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3871 3872 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3873 3874 sc->poll_ticks = 1000000; 3875 sc->poll_ival = HDAC_POLL_INTERVAL; 3876 if (resource_int_value(device_get_name(dev), 3877 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3878 sc->polling = 1; 3879 else 3880 sc->polling = 0; 3881 3882 result = bus_dma_tag_create(NULL, /* parent */ 3883 HDAC_DMA_ALIGNMENT, /* alignment */ 3884 0, /* boundary */ 3885 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3886 BUS_SPACE_MAXADDR, /* highaddr */ 3887 NULL, /* filtfunc */ 3888 NULL, /* fistfuncarg */ 3889 HDA_BUFSZ_MAX, /* maxsize */ 3890 1, /* nsegments */ 3891 HDA_BUFSZ_MAX, /* maxsegsz */ 3892 0, /* flags */ 3893 NULL, /* lockfunc */ 3894 NULL, /* lockfuncarg */ 3895 &sc->chan_dmat); /* dmat */ 3896 if (result != 0) { 3897 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3898 __func__, result); 3899 snd_mtxfree(sc->lock); 3900 free(sc, M_DEVBUF); 3901 return (ENXIO); 3902 } 3903 3904 3905 sc->hdabus = NULL; 3906 for (i = 0; i < HDAC_CODEC_MAX; i++) 3907 sc->codecs[i] = NULL; 3908 3909 pci_enable_busmaster(dev); 3910 3911 if (vendor == INTEL_VENDORID) { 3912 /* TCSEL -> TC0 */ 3913 v = pci_read_config(dev, 0x44, 1); 3914 pci_write_config(dev, 0x44, v & 0xf8, 1); 3915 HDA_BOOTHVERBOSE( 3916 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3917 pci_read_config(dev, 0x44, 1)); 3918 ); 3919 } 3920 3921#ifdef HDAC_MSI_ENABLED 3922 if (resource_int_value(device_get_name(dev), 3923 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3924 pci_msi_count(dev) == 1) 3925 sc->flags |= HDAC_F_MSI; 3926 else 3927#endif 3928 sc->flags &= ~HDAC_F_MSI; 3929 3930#if defined(__i386__) || defined(__amd64__) 3931 sc->flags |= HDAC_F_DMA_NOCACHE; 3932 3933 if (resource_int_value(device_get_name(dev), 3934 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3935#else 3936 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3937#endif 3938 /* 3939 * Try to enable PCIe snoop to avoid messing around with 3940 * uncacheable DMA attribute. Since PCIe snoop register 3941 * config is pretty much vendor specific, there are no 3942 * general solutions on how to enable it, forcing us (even 3943 * Microsoft) to enable uncacheable or write combined DMA 3944 * by default. 3945 * 3946 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3947 */ 3948 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3949 if (hdac_pcie_snoop[i].vendor != vendor) 3950 continue; 3951 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3952 if (hdac_pcie_snoop[i].reg == 0x00) 3953 break; 3954 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3955 if ((v & hdac_pcie_snoop[i].enable) == 3956 hdac_pcie_snoop[i].enable) 3957 break; 3958 v &= hdac_pcie_snoop[i].mask; 3959 v |= hdac_pcie_snoop[i].enable; 3960 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3961 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3962 if ((v & hdac_pcie_snoop[i].enable) != 3963 hdac_pcie_snoop[i].enable) { 3964 HDA_BOOTVERBOSE( 3965 device_printf(dev, 3966 "WARNING: Failed to enable PCIe " 3967 "snoop!\n"); 3968 ); 3969#if defined(__i386__) || defined(__amd64__) 3970 sc->flags |= HDAC_F_DMA_NOCACHE; 3971#endif 3972 } 3973 break; 3974 } 3975#if defined(__i386__) || defined(__amd64__) 3976 } 3977#endif 3978 3979 HDA_BOOTHVERBOSE( 3980 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3981 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3982 "Uncacheable" : "PCIe snoop", vendor); 3983 ); 3984 3985 /* Allocate resources */ 3986 result = hdac_mem_alloc(sc); 3987 if (result != 0) 3988 goto hdac_attach_fail; 3989 result = hdac_irq_alloc(sc); 3990 if (result != 0) 3991 goto hdac_attach_fail; 3992 3993 /* Get Capabilities */ 3994 result = hdac_get_capabilities(sc); 3995 if (result != 0) 3996 goto hdac_attach_fail; 3997 3998 /* Allocate CORB and RIRB dma memory */ 3999 result = hdac_dma_alloc(sc, &sc->corb_dma, 4000 sc->corb_size * sizeof(uint32_t)); 4001 if (result != 0) 4002 goto hdac_attach_fail; 4003 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4004 sc->rirb_size * sizeof(struct hdac_rirb)); 4005 if (result != 0) 4006 goto hdac_attach_fail; 4007 4008 /* Quiesce everything */ 4009 HDA_BOOTHVERBOSE( 4010 device_printf(dev, "Reset controller...\n"); 4011 ); 4012 hdac_reset(sc, 1); 4013 4014 /* Initialize the CORB and RIRB */ 4015 hdac_corb_init(sc); 4016 hdac_rirb_init(sc); 4017 4018 /* Defer remaining of initialization until interrupts are enabled */ 4019 sc->intrhook.ich_func = hdac_attach2; 4020 sc->intrhook.ich_arg = (void *)sc; 4021 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4022 sc->intrhook.ich_func = NULL; 4023 hdac_attach2((void *)sc); 4024 } 4025 4026 return (0); 4027 4028hdac_attach_fail: 4029 hdac_irq_free(sc); 4030 hdac_dma_free(sc, &sc->rirb_dma); 4031 hdac_dma_free(sc, &sc->corb_dma); 4032 hdac_mem_free(sc); 4033 snd_mtxfree(sc->lock); 4034 free(sc, M_DEVBUF); 4035 4036 return (ENXIO); 4037} 4038 4039static void 4040hdac_audio_parse(struct hdac_devinfo *devinfo) 4041{ 4042 struct hdac_codec *codec = devinfo->codec; 4043 struct hdac_softc *sc = codec->sc; 4044 struct hdac_widget *w; 4045 uint32_t res; 4046 int i; 4047 nid_t cad, nid; 4048 4049 cad = devinfo->codec->cad; 4050 nid = devinfo->nid; 4051 4052 res = hdac_command(sc, 4053 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4054 devinfo->function.audio.gpio = res; 4055 4056 HDA_BOOTVERBOSE( 4057 device_printf(sc->dev, "GPIO: 0x%08x " 4058 "NumGPIO=%d NumGPO=%d " 4059 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4060 devinfo->function.audio.gpio, 4061 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4062 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4063 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4064 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4065 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4066 ); 4067 4068 res = hdac_command(sc, 4069 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4070 cad); 4071 devinfo->function.audio.supp_stream_formats = res; 4072 4073 res = hdac_command(sc, 4074 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4075 cad); 4076 devinfo->function.audio.supp_pcm_size_rate = res; 4077 4078 res = hdac_command(sc, 4079 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4080 cad); 4081 devinfo->function.audio.outamp_cap = res; 4082 4083 res = hdac_command(sc, 4084 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4085 cad); 4086 devinfo->function.audio.inamp_cap = res; 4087 4088 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4089 w = hdac_widget_get(devinfo, i); 4090 if (w == NULL) 4091 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4092 else { 4093 w->devinfo = devinfo; 4094 w->nid = i; 4095 w->enable = 1; 4096 w->selconn = -1; 4097 w->pflags = 0; 4098 w->ossdev = -1; 4099 w->bindas = -1; 4100 w->param.eapdbtl = HDAC_INVALID; 4101 hdac_widget_parse(w); 4102 } 4103 } 4104} 4105 4106static void 4107hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4108{ 4109 struct hdac_softc *sc = devinfo->codec->sc; 4110 struct hdac_audio_ctl *ctls; 4111 struct hdac_widget *w, *cw; 4112 int i, j, cnt, max, ocap, icap; 4113 int mute, offset, step, size; 4114 4115 /* XXX This is redundant */ 4116 max = 0; 4117 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4118 w = hdac_widget_get(devinfo, i); 4119 if (w == NULL || w->enable == 0) 4120 continue; 4121 if (w->param.outamp_cap != 0) 4122 max++; 4123 if (w->param.inamp_cap != 0) { 4124 switch (w->type) { 4125 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4126 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4127 for (j = 0; j < w->nconns; j++) { 4128 cw = hdac_widget_get(devinfo, 4129 w->conns[j]); 4130 if (cw == NULL || cw->enable == 0) 4131 continue; 4132 max++; 4133 } 4134 break; 4135 default: 4136 max++; 4137 break; 4138 } 4139 } 4140 } 4141 4142 devinfo->function.audio.ctlcnt = max; 4143 4144 if (max < 1) 4145 return; 4146 4147 ctls = (struct hdac_audio_ctl *)malloc( 4148 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4149 4150 if (ctls == NULL) { 4151 /* Blekh! */ 4152 device_printf(sc->dev, "unable to allocate ctls!\n"); 4153 devinfo->function.audio.ctlcnt = 0; 4154 return; 4155 } 4156 4157 cnt = 0; 4158 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4159 if (cnt >= max) { 4160 device_printf(sc->dev, "%s: Ctl overflow!\n", 4161 __func__); 4162 break; 4163 } 4164 w = hdac_widget_get(devinfo, i); 4165 if (w == NULL || w->enable == 0) 4166 continue; 4167 ocap = w->param.outamp_cap; 4168 icap = w->param.inamp_cap; 4169 if (ocap != 0) { 4170 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4171 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4172 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4173 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4174 /*if (offset > step) { 4175 HDA_BOOTVERBOSE( 4176 device_printf(sc->dev, 4177 "BUGGY outamp: nid=%d " 4178 "[offset=%d > step=%d]\n", 4179 w->nid, offset, step); 4180 ); 4181 offset = step; 4182 }*/ 4183 ctls[cnt].enable = 1; 4184 ctls[cnt].widget = w; 4185 ctls[cnt].mute = mute; 4186 ctls[cnt].step = step; 4187 ctls[cnt].size = size; 4188 ctls[cnt].offset = offset; 4189 ctls[cnt].left = offset; 4190 ctls[cnt].right = offset; 4191 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4192 w->waspin) 4193 ctls[cnt].ndir = HDA_CTL_IN; 4194 else 4195 ctls[cnt].ndir = HDA_CTL_OUT; 4196 ctls[cnt++].dir = HDA_CTL_OUT; 4197 } 4198 4199 if (icap != 0) { 4200 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4201 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4202 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4203 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4204 /*if (offset > step) { 4205 HDA_BOOTVERBOSE( 4206 device_printf(sc->dev, 4207 "BUGGY inamp: nid=%d " 4208 "[offset=%d > step=%d]\n", 4209 w->nid, offset, step); 4210 ); 4211 offset = step; 4212 }*/ 4213 switch (w->type) { 4214 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4215 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4216 for (j = 0; j < w->nconns; j++) { 4217 if (cnt >= max) { 4218 device_printf(sc->dev, 4219 "%s: Ctl overflow!\n", 4220 __func__); 4221 break; 4222 } 4223 cw = hdac_widget_get(devinfo, 4224 w->conns[j]); 4225 if (cw == NULL || cw->enable == 0) 4226 continue; 4227 ctls[cnt].enable = 1; 4228 ctls[cnt].widget = w; 4229 ctls[cnt].childwidget = cw; 4230 ctls[cnt].index = j; 4231 ctls[cnt].mute = mute; 4232 ctls[cnt].step = step; 4233 ctls[cnt].size = size; 4234 ctls[cnt].offset = offset; 4235 ctls[cnt].left = offset; 4236 ctls[cnt].right = offset; 4237 ctls[cnt].ndir = HDA_CTL_IN; 4238 ctls[cnt++].dir = HDA_CTL_IN; 4239 } 4240 break; 4241 default: 4242 if (cnt >= max) { 4243 device_printf(sc->dev, 4244 "%s: Ctl overflow!\n", 4245 __func__); 4246 break; 4247 } 4248 ctls[cnt].enable = 1; 4249 ctls[cnt].widget = w; 4250 ctls[cnt].mute = mute; 4251 ctls[cnt].step = step; 4252 ctls[cnt].size = size; 4253 ctls[cnt].offset = offset; 4254 ctls[cnt].left = offset; 4255 ctls[cnt].right = offset; 4256 if (w->type == 4257 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4258 ctls[cnt].ndir = HDA_CTL_OUT; 4259 else 4260 ctls[cnt].ndir = HDA_CTL_IN; 4261 ctls[cnt++].dir = HDA_CTL_IN; 4262 break; 4263 } 4264 } 4265 } 4266 4267 devinfo->function.audio.ctl = ctls; 4268} 4269 4270static void 4271hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4272{ 4273 struct hdac_softc *sc = devinfo->codec->sc; 4274 struct hdac_audio_as *as; 4275 struct hdac_widget *w; 4276 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4277 4278 /* Count present associations */ 4279 max = 0; 4280 for (j = 1; j < 16; j++) { 4281 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4282 w = hdac_widget_get(devinfo, i); 4283 if (w == NULL || w->enable == 0) 4284 continue; 4285 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4286 continue; 4287 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4288 != j) 4289 continue; 4290 max++; 4291 if (j != 15) /* There could be many 1-pin assocs #15 */ 4292 break; 4293 } 4294 } 4295 4296 devinfo->function.audio.ascnt = max; 4297 4298 if (max < 1) 4299 return; 4300 4301 as = (struct hdac_audio_as *)malloc( 4302 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4303 4304 if (as == NULL) { 4305 /* Blekh! */ 4306 device_printf(sc->dev, "unable to allocate assocs!\n"); 4307 devinfo->function.audio.ascnt = 0; 4308 return; 4309 } 4310 4311 for (i = 0; i < max; i++) { 4312 as[i].hpredir = -1; 4313 as[i].chan = -1; 4314 as[i].digital = 1; 4315 } 4316 4317 /* Scan associations skipping as=0. */ 4318 cnt = 0; 4319 for (j = 1; j < 16; j++) { 4320 first = 16; 4321 hpredir = 0; 4322 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4323 w = hdac_widget_get(devinfo, i); 4324 if (w == NULL || w->enable == 0) 4325 continue; 4326 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4327 continue; 4328 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4329 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4330 if (assoc != j) { 4331 continue; 4332 } 4333 KASSERT(cnt < max, 4334 ("%s: Associations owerflow (%d of %d)", 4335 __func__, cnt, max)); 4336 type = w->wclass.pin.config & 4337 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4338 /* Get pin direction. */ 4339 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4340 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4341 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4342 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4343 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4344 dir = HDA_CTL_OUT; 4345 else 4346 dir = HDA_CTL_IN; 4347 /* If this is a first pin - create new association. */ 4348 if (as[cnt].pincnt == 0) { 4349 as[cnt].enable = 1; 4350 as[cnt].index = j; 4351 as[cnt].dir = dir; 4352 } 4353 if (seq < first) 4354 first = seq; 4355 /* Check association correctness. */ 4356 if (as[cnt].pins[seq] != 0) { 4357 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4358 "in association %d! Disabling association.\n", 4359 __func__, seq, w->nid, j); 4360 as[cnt].enable = 0; 4361 } 4362 if (dir != as[cnt].dir) { 4363 device_printf(sc->dev, "%s: Pin %d has wrong " 4364 "direction for association %d! Disabling " 4365 "association.\n", 4366 __func__, w->nid, j); 4367 as[cnt].enable = 0; 4368 } 4369 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4370 as[cnt].digital = 0; 4371 /* Headphones with seq=15 may mean redirection. */ 4372 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4373 seq == 15) 4374 hpredir = 1; 4375 as[cnt].pins[seq] = w->nid; 4376 as[cnt].pincnt++; 4377 /* Association 15 is a multiple unassociated pins. */ 4378 if (j == 15) 4379 cnt++; 4380 } 4381 if (j != 15 && as[cnt].pincnt > 0) { 4382 if (hpredir && as[cnt].pincnt > 1) 4383 as[cnt].hpredir = first; 4384 cnt++; 4385 } 4386 } 4387 HDA_BOOTVERBOSE( 4388 device_printf(sc->dev, 4389 "%d associations found:\n", max); 4390 for (i = 0; i < max; i++) { 4391 device_printf(sc->dev, 4392 "Association %d (%d) %s%s:\n", 4393 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4394 as[i].enable?"":" (disabled)"); 4395 for (j = 0; j < 16; j++) { 4396 if (as[i].pins[j] == 0) 4397 continue; 4398 device_printf(sc->dev, 4399 " Pin nid=%d seq=%d\n", 4400 as[i].pins[j], j); 4401 } 4402 } 4403 ); 4404 4405 devinfo->function.audio.as = as; 4406} 4407 4408static const struct { 4409 uint32_t model; 4410 uint32_t id; 4411 uint32_t set, unset; 4412} hdac_quirks[] = { 4413 /* 4414 * XXX Force stereo quirk. Monoural recording / playback 4415 * on few codecs (especially ALC880) seems broken or 4416 * perhaps unsupported. 4417 */ 4418 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4419 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4420 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4421 HDA_QUIRK_GPIO0, 0 }, 4422 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4423 HDA_QUIRK_GPIO0, 0 }, 4424 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4425 HDA_QUIRK_GPIO0, 0 }, 4426 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4427 HDA_QUIRK_GPIO0, 0 }, 4428 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4429 HDA_QUIRK_GPIO0, 0 }, 4430 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4431 HDA_QUIRK_GPIO0, 0 }, 4432 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4433 HDA_QUIRK_EAPDINV, 0 }, 4434 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4435 HDA_QUIRK_EAPDINV, 0 }, 4436 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4437 HDA_QUIRK_OVREF, 0 }, 4438 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4439 HDA_QUIRK_OVREF, 0 }, 4440 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4441 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4442 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4443 HDA_QUIRK_GPIO1, 0 }, 4444 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4445 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4446 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4447 HDA_QUIRK_EAPDINV, 0 }, 4448 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4449 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4450 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4451 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4452 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4453 HDA_QUIRK_GPIO0, 0 }, 4454 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4455 HDA_QUIRK_GPIO2, 0 }, 4456 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4457 HDA_QUIRK_GPIO0, 0 }, 4458 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4459 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4460 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4461 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4462 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4463 0, HDA_QUIRK_FORCESTEREO } 4464}; 4465#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4466 4467static void 4468hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4469{ 4470 struct hdac_widget *w; 4471 uint32_t id, subvendor; 4472 int i; 4473 4474 id = hdac_codec_id(devinfo->codec); 4475 subvendor = devinfo->codec->sc->pci_subvendor; 4476 4477 /* 4478 * Quirks 4479 */ 4480 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4481 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4482 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4483 continue; 4484 if (hdac_quirks[i].set != 0) 4485 devinfo->function.audio.quirks |= 4486 hdac_quirks[i].set; 4487 if (hdac_quirks[i].unset != 0) 4488 devinfo->function.audio.quirks &= 4489 ~(hdac_quirks[i].unset); 4490 } 4491 4492 switch (id) { 4493 case HDA_CODEC_ALC883: 4494 /* 4495 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4496 * Clear vref cap for jack connectivity. 4497 */ 4498 w = hdac_widget_get(devinfo, 24); 4499 if (w != NULL && w->enable != 0 && w->type == 4500 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4501 (w->wclass.pin.config & 4502 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4503 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4504 w->wclass.pin.cap &= ~( 4505 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4506 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4507 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4508 w = hdac_widget_get(devinfo, 25); 4509 if (w != NULL && w->enable != 0 && w->type == 4510 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4511 (w->wclass.pin.config & 4512 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4513 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4514 w->wclass.pin.cap &= ~( 4515 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4516 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4517 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4518 /* 4519 * nid: 26 = Line-in, leave it alone. 4520 */ 4521 break; 4522 case HDA_CODEC_AD1986A: 4523 if (subvendor == ASUS_A8X_SUBVENDOR) { 4524 /* 4525 * This is just plain ridiculous.. There 4526 * are several A8 series that share the same 4527 * pci id but works differently (EAPD). 4528 */ 4529 w = hdac_widget_get(devinfo, 26); 4530 if (w != NULL && w->type == 4531 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4532 (w->wclass.pin.config & 4533 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4534 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4535 devinfo->function.audio.quirks &= 4536 ~HDA_QUIRK_EAPDINV; 4537 } 4538 break; 4539 case HDA_CODEC_AD1981HD: 4540 /* 4541 * This codec has very unusual design with several 4542 * points inappropriate for the present parser. 4543 */ 4544 /* Disable recording from mono playback mix. */ 4545 w = hdac_widget_get(devinfo, 21); 4546 if (w != NULL) 4547 w->connsenable[3] = 0; 4548 /* Disable rear to front mic mixer, use separately. */ 4549 w = hdac_widget_get(devinfo, 31); 4550 if (w != NULL) 4551 w->enable = 0; 4552 /* Disable playback mixer, use direct bypass. */ 4553 w = hdac_widget_get(devinfo, 14); 4554 if (w != NULL) 4555 w->enable = 0; 4556 break; 4557 } 4558} 4559 4560/* 4561 * Trace path from DAC to pin. 4562 */ 4563static nid_t 4564hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4565 int dupseq, int min, int only, int depth) 4566{ 4567 struct hdac_widget *w; 4568 int i, im = -1; 4569 nid_t m = 0, ret; 4570 4571 if (depth > HDA_PARSE_MAXDEPTH) 4572 return (0); 4573 w = hdac_widget_get(devinfo, nid); 4574 if (w == NULL || w->enable == 0) 4575 return (0); 4576 HDA_BOOTHVERBOSE( 4577 if (!only) { 4578 device_printf(devinfo->codec->sc->dev, 4579 " %*stracing via nid %d\n", 4580 depth + 1, "", w->nid); 4581 } 4582 ); 4583 /* Use only unused widgets */ 4584 if (w->bindas >= 0 && w->bindas != as) { 4585 HDA_BOOTHVERBOSE( 4586 if (!only) { 4587 device_printf(devinfo->codec->sc->dev, 4588 " %*snid %d busy by association %d\n", 4589 depth + 1, "", w->nid, w->bindas); 4590 } 4591 ); 4592 return (0); 4593 } 4594 if (dupseq < 0) { 4595 if (w->bindseqmask != 0) { 4596 HDA_BOOTHVERBOSE( 4597 if (!only) { 4598 device_printf(devinfo->codec->sc->dev, 4599 " %*snid %d busy by seqmask %x\n", 4600 depth + 1, "", w->nid, w->bindseqmask); 4601 } 4602 ); 4603 return (0); 4604 } 4605 } else { 4606 /* If this is headphones - allow duplicate first pin. */ 4607 if (w->bindseqmask != 0 && 4608 (w->bindseqmask & (1 << dupseq)) == 0) { 4609 HDA_BOOTHVERBOSE( 4610 device_printf(devinfo->codec->sc->dev, 4611 " %*snid %d busy by seqmask %x\n", 4612 depth + 1, "", w->nid, w->bindseqmask); 4613 ); 4614 return (0); 4615 } 4616 } 4617 4618 switch (w->type) { 4619 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4620 /* Do not traverse input. AD1988 has digital monitor 4621 for which we are not ready. */ 4622 break; 4623 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4624 /* If we are tracing HP take only dac of first pin. */ 4625 if ((only == 0 || only == w->nid) && 4626 (w->nid >= min) && (dupseq < 0 || w->nid == 4627 devinfo->function.audio.as[as].dacs[dupseq])) 4628 m = w->nid; 4629 break; 4630 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4631 if (depth > 0) 4632 break; 4633 /* Fall */ 4634 default: 4635 /* Find reachable DACs with smallest nid respecting constraints. */ 4636 for (i = 0; i < w->nconns; i++) { 4637 if (w->connsenable[i] == 0) 4638 continue; 4639 if (w->selconn != -1 && w->selconn != i) 4640 continue; 4641 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4642 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4643 if (m == 0 || ret < m) { 4644 m = ret; 4645 im = i; 4646 } 4647 if (only || dupseq >= 0) 4648 break; 4649 } 4650 } 4651 if (m && only && ((w->nconns > 1 && 4652 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4653 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4654 w->selconn = im; 4655 break; 4656 } 4657 if (m && only) { 4658 w->bindas = as; 4659 w->bindseqmask |= (1 << seq); 4660 } 4661 HDA_BOOTHVERBOSE( 4662 if (!only) { 4663 device_printf(devinfo->codec->sc->dev, 4664 " %*snid %d returned %d\n", 4665 depth + 1, "", w->nid, m); 4666 } 4667 ); 4668 return (m); 4669} 4670 4671/* 4672 * Trace path from widget to ADC. 4673 */ 4674static nid_t 4675hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4676 int only, int depth) 4677{ 4678 struct hdac_widget *w, *wc; 4679 int i, j; 4680 nid_t res = 0; 4681 4682 if (depth > HDA_PARSE_MAXDEPTH) 4683 return (0); 4684 w = hdac_widget_get(devinfo, nid); 4685 if (w == NULL || w->enable == 0) 4686 return (0); 4687 HDA_BOOTHVERBOSE( 4688 device_printf(devinfo->codec->sc->dev, 4689 " %*stracing via nid %d\n", 4690 depth + 1, "", w->nid); 4691 ); 4692 /* Use only unused widgets */ 4693 if (w->bindas >= 0 && w->bindas != as) { 4694 HDA_BOOTHVERBOSE( 4695 device_printf(devinfo->codec->sc->dev, 4696 " %*snid %d busy by association %d\n", 4697 depth + 1, "", w->nid, w->bindas); 4698 ); 4699 return (0); 4700 } 4701 4702 switch (w->type) { 4703 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4704 /* If we are tracing HP take only dac of first pin. */ 4705 if (only == w->nid) 4706 res = 1; 4707 break; 4708 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4709 if (depth > 0) 4710 break; 4711 /* Fall */ 4712 default: 4713 /* Try to find reachable ADCs with specified nid. */ 4714 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4715 wc = hdac_widget_get(devinfo, j); 4716 if (wc == NULL || wc->enable == 0) 4717 continue; 4718 for (i = 0; i < wc->nconns; i++) { 4719 if (wc->connsenable[i] == 0) 4720 continue; 4721 if (wc->conns[i] != nid) 4722 continue; 4723 if (hdac_audio_trace_adc(devinfo, as, seq, 4724 j, only, depth + 1) != 0) { 4725 res = 1; 4726 if (((wc->nconns > 1 && 4727 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4728 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4729 wc->selconn == -1) 4730 wc->selconn = i; 4731 } 4732 } 4733 } 4734 break; 4735 } 4736 if (res) { 4737 w->bindas = as; 4738 w->bindseqmask |= (1 << seq); 4739 } 4740 HDA_BOOTHVERBOSE( 4741 device_printf(devinfo->codec->sc->dev, 4742 " %*snid %d returned %d\n", 4743 depth + 1, "", w->nid, res); 4744 ); 4745 return (res); 4746} 4747 4748/* 4749 * Erase trace path of the specified association. 4750 */ 4751static void 4752hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4753{ 4754 struct hdac_widget *w; 4755 int i; 4756 4757 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4758 w = hdac_widget_get(devinfo, i); 4759 if (w == NULL || w->enable == 0) 4760 continue; 4761 if (w->bindas == as) { 4762 if (seq >= 0) { 4763 w->bindseqmask &= ~(1 << seq); 4764 if (w->bindseqmask == 0) { 4765 w->bindas = -1; 4766 w->selconn = -1; 4767 } 4768 } else { 4769 w->bindas = -1; 4770 w->bindseqmask = 0; 4771 w->selconn = -1; 4772 } 4773 } 4774 } 4775} 4776 4777/* 4778 * Trace association path from DAC to output 4779 */ 4780static int 4781hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4782{ 4783 struct hdac_audio_as *ases = devinfo->function.audio.as; 4784 int i, hpredir; 4785 nid_t min, res; 4786 4787 /* Find next pin */ 4788 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4789 ; 4790 /* Check if there is no any left. If so - we succeded. */ 4791 if (i == 16) 4792 return (1); 4793 4794 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4795 min = 0; 4796 res = 0; 4797 do { 4798 HDA_BOOTHVERBOSE( 4799 device_printf(devinfo->codec->sc->dev, 4800 " Tracing pin %d with min nid %d", 4801 ases[as].pins[i], min); 4802 if (hpredir >= 0) 4803 printf(" and hpredir %d", hpredir); 4804 printf("\n"); 4805 ); 4806 /* Trace this pin taking min nid into account. */ 4807 res = hdac_audio_trace_dac(devinfo, as, i, 4808 ases[as].pins[i], hpredir, min, 0, 0); 4809 if (res == 0) { 4810 /* If we failed - return to previous and redo it. */ 4811 HDA_BOOTVERBOSE( 4812 device_printf(devinfo->codec->sc->dev, 4813 " Unable to trace pin %d seq %d with min " 4814 "nid %d", 4815 ases[as].pins[i], i, min); 4816 if (hpredir >= 0) 4817 printf(" and hpredir %d", hpredir); 4818 printf("\n"); 4819 ); 4820 return (0); 4821 } 4822 HDA_BOOTVERBOSE( 4823 device_printf(devinfo->codec->sc->dev, 4824 " Pin %d traced to DAC %d", 4825 ases[as].pins[i], res); 4826 if (hpredir >= 0) 4827 printf(" and hpredir %d", hpredir); 4828 if (ases[as].fakeredir) 4829 printf(" with fake redirection"); 4830 printf("\n"); 4831 ); 4832 /* Trace again to mark the path */ 4833 hdac_audio_trace_dac(devinfo, as, i, 4834 ases[as].pins[i], hpredir, min, res, 0); 4835 ases[as].dacs[i] = res; 4836 /* We succeded, so call next. */ 4837 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4838 return (1); 4839 /* If next failed, we should retry with next min */ 4840 hdac_audio_undo_trace(devinfo, as, i); 4841 ases[as].dacs[i] = 0; 4842 min = res + 1; 4843 } while (1); 4844} 4845 4846/* 4847 * Trace association path from input to ADC 4848 */ 4849static int 4850hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4851{ 4852 struct hdac_audio_as *ases = devinfo->function.audio.as; 4853 struct hdac_widget *w; 4854 int i, j, k; 4855 4856 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4857 w = hdac_widget_get(devinfo, j); 4858 if (w == NULL || w->enable == 0) 4859 continue; 4860 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4861 continue; 4862 if (w->bindas >= 0 && w->bindas != as) 4863 continue; 4864 4865 /* Find next pin */ 4866 for (i = 0; i < 16; i++) { 4867 if (ases[as].pins[i] == 0) 4868 continue; 4869 4870 HDA_BOOTHVERBOSE( 4871 device_printf(devinfo->codec->sc->dev, 4872 " Tracing pin %d to ADC %d\n", 4873 ases[as].pins[i], j); 4874 ); 4875 /* Trace this pin taking goal into account. */ 4876 if (hdac_audio_trace_adc(devinfo, as, i, 4877 ases[as].pins[i], j, 0) == 0) { 4878 /* If we failed - return to previous and redo it. */ 4879 HDA_BOOTVERBOSE( 4880 device_printf(devinfo->codec->sc->dev, 4881 " Unable to trace pin %d to ADC %d, undo traces\n", 4882 ases[as].pins[i], j); 4883 ); 4884 hdac_audio_undo_trace(devinfo, as, -1); 4885 for (k = 0; k < 16; k++) 4886 ases[as].dacs[k] = 0; 4887 break; 4888 } 4889 HDA_BOOTVERBOSE( 4890 device_printf(devinfo->codec->sc->dev, 4891 " Pin %d traced to ADC %d\n", 4892 ases[as].pins[i], j); 4893 ); 4894 ases[as].dacs[i] = j; 4895 } 4896 if (i == 16) 4897 return (1); 4898 } 4899 return (0); 4900} 4901 4902/* 4903 * Trace input monitor path from mixer to output association. 4904 */ 4905static int 4906hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4907{ 4908 struct hdac_audio_as *ases = devinfo->function.audio.as; 4909 struct hdac_widget *w, *wc; 4910 int i, j; 4911 nid_t res = 0; 4912 4913 if (depth > HDA_PARSE_MAXDEPTH) 4914 return (0); 4915 w = hdac_widget_get(devinfo, nid); 4916 if (w == NULL || w->enable == 0) 4917 return (0); 4918 HDA_BOOTHVERBOSE( 4919 device_printf(devinfo->codec->sc->dev, 4920 " %*stracing via nid %d\n", 4921 depth + 1, "", w->nid); 4922 ); 4923 /* Use only unused widgets */ 4924 if (depth > 0 && w->bindas != -1) { 4925 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4926 HDA_BOOTHVERBOSE( 4927 device_printf(devinfo->codec->sc->dev, 4928 " %*snid %d found output association %d\n", 4929 depth + 1, "", w->nid, w->bindas); 4930 ); 4931 return (1); 4932 } else { 4933 HDA_BOOTHVERBOSE( 4934 device_printf(devinfo->codec->sc->dev, 4935 " %*snid %d busy by input association %d\n", 4936 depth + 1, "", w->nid, w->bindas); 4937 ); 4938 return (0); 4939 } 4940 } 4941 4942 switch (w->type) { 4943 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4944 /* Do not traverse input. AD1988 has digital monitor 4945 for which we are not ready. */ 4946 break; 4947 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4948 if (depth > 0) 4949 break; 4950 /* Fall */ 4951 default: 4952 /* Try to find reachable ADCs with specified nid. */ 4953 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4954 wc = hdac_widget_get(devinfo, j); 4955 if (wc == NULL || wc->enable == 0) 4956 continue; 4957 for (i = 0; i < wc->nconns; i++) { 4958 if (wc->connsenable[i] == 0) 4959 continue; 4960 if (wc->conns[i] != nid) 4961 continue; 4962 if (hdac_audio_trace_to_out(devinfo, 4963 j, depth + 1) != 0) { 4964 res = 1; 4965 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4966 wc->selconn == -1) 4967 wc->selconn = i; 4968 } 4969 } 4970 } 4971 break; 4972 } 4973 if (res) 4974 w->bindas = -2; 4975 4976 HDA_BOOTHVERBOSE( 4977 device_printf(devinfo->codec->sc->dev, 4978 " %*snid %d returned %d\n", 4979 depth + 1, "", w->nid, res); 4980 ); 4981 return (res); 4982} 4983 4984/* 4985 * Trace extra associations (beeper, monitor) 4986 */ 4987static void 4988hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4989{ 4990 struct hdac_audio_as *as = devinfo->function.audio.as; 4991 struct hdac_widget *w; 4992 int j; 4993 4994 /* Input monitor */ 4995 /* Find mixer associated with input, but supplying signal 4996 for output associations. Hope it will be input monitor. */ 4997 HDA_BOOTVERBOSE( 4998 device_printf(devinfo->codec->sc->dev, 4999 "Tracing input monitor\n"); 5000 ); 5001 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5002 w = hdac_widget_get(devinfo, j); 5003 if (w == NULL || w->enable == 0) 5004 continue; 5005 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5006 continue; 5007 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5008 continue; 5009 HDA_BOOTVERBOSE( 5010 device_printf(devinfo->codec->sc->dev, 5011 " Tracing nid %d to out\n", 5012 j); 5013 ); 5014 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5015 HDA_BOOTVERBOSE( 5016 device_printf(devinfo->codec->sc->dev, 5017 " nid %d is input monitor\n", 5018 w->nid); 5019 ); 5020 w->pflags |= HDA_ADC_MONITOR; 5021 w->ossdev = SOUND_MIXER_IMIX; 5022 } 5023 } 5024 5025 /* Beeper */ 5026 HDA_BOOTVERBOSE( 5027 device_printf(devinfo->codec->sc->dev, 5028 "Tracing beeper\n"); 5029 ); 5030 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5031 w = hdac_widget_get(devinfo, j); 5032 if (w == NULL || w->enable == 0) 5033 continue; 5034 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5035 continue; 5036 HDA_BOOTHVERBOSE( 5037 device_printf(devinfo->codec->sc->dev, 5038 " Tracing nid %d to out\n", 5039 j); 5040 ); 5041 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5042 HDA_BOOTVERBOSE( 5043 device_printf(devinfo->codec->sc->dev, 5044 " nid %d traced to out\n", 5045 j); 5046 ); 5047 } 5048 w->bindas = -2; 5049 } 5050} 5051 5052/* 5053 * Bind assotiations to PCM channels 5054 */ 5055static void 5056hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5057{ 5058 struct hdac_softc *sc = devinfo->codec->sc; 5059 struct hdac_audio_as *as = devinfo->function.audio.as; 5060 int j, cnt = 0, free; 5061 5062 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5063 if (as[j].enable) 5064 cnt++; 5065 } 5066 if (sc->num_chans == 0) { 5067 sc->chans = (struct hdac_chan *)malloc( 5068 sizeof(struct hdac_chan) * cnt, 5069 M_HDAC, M_ZERO | M_NOWAIT); 5070 if (sc->chans == NULL) { 5071 device_printf(devinfo->codec->sc->dev, 5072 "Channels memory allocation failed!\n"); 5073 return; 5074 } 5075 } else { 5076 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5077 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5078 M_HDAC, M_ZERO | M_NOWAIT); 5079 if (sc->chans == NULL) { 5080 sc->num_chans = 0; 5081 device_printf(devinfo->codec->sc->dev, 5082 "Channels memory allocation failed!\n"); 5083 return; 5084 } 5085 } 5086 free = sc->num_chans; 5087 sc->num_chans += cnt; 5088 5089 for (j = free; j < free + cnt; j++) { 5090 devinfo->codec->sc->chans[j].devinfo = devinfo; 5091 devinfo->codec->sc->chans[j].as = -1; 5092 } 5093 5094 /* Assign associations in order of their numbers, */ 5095 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5096 if (as[j].enable == 0) 5097 continue; 5098 5099 as[j].chan = free; 5100 devinfo->codec->sc->chans[free].as = j; 5101 devinfo->codec->sc->chans[free].dir = 5102 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5103 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5104 free++; 5105 } 5106} 5107 5108static void 5109hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5110{ 5111 struct hdac_widget *w; 5112 int i; 5113 5114 /* Disable power and volume widgets. */ 5115 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5116 w = hdac_widget_get(devinfo, i); 5117 if (w == NULL || w->enable == 0) 5118 continue; 5119 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5120 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5121 w->enable = 0; 5122 HDA_BOOTHVERBOSE( 5123 device_printf(devinfo->codec->sc->dev, 5124 " Disabling nid %d due to it's" 5125 " non-audio type.\n", 5126 w->nid); 5127 ); 5128 } 5129 } 5130} 5131 5132static void 5133hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5134{ 5135 struct hdac_widget *w, *cw; 5136 struct hdac_audio_ctl *ctl; 5137 int done, found, i, j, k; 5138 5139 /* Disable useless pins. */ 5140 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5141 w = hdac_widget_get(devinfo, i); 5142 if (w == NULL || w->enable == 0) 5143 continue; 5144 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5145 if ((w->wclass.pin.config & 5146 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5147 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5148 w->enable = 0; 5149 HDA_BOOTHVERBOSE( 5150 device_printf(devinfo->codec->sc->dev, 5151 " Disabling pin nid %d due" 5152 " to None connectivity.\n", 5153 w->nid); 5154 ); 5155 } else if ((w->wclass.pin.config & 5156 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5157 w->enable = 0; 5158 HDA_BOOTHVERBOSE( 5159 device_printf(devinfo->codec->sc->dev, 5160 " Disabling unassociated" 5161 " pin nid %d.\n", 5162 w->nid); 5163 ); 5164 } 5165 } 5166 } 5167 do { 5168 done = 1; 5169 /* Disable and mute controls for disabled widgets. */ 5170 i = 0; 5171 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5172 if (ctl->enable == 0) 5173 continue; 5174 if (ctl->widget->enable == 0 || 5175 (ctl->childwidget != NULL && 5176 ctl->childwidget->enable == 0)) { 5177 ctl->forcemute = 1; 5178 ctl->muted = HDA_AMP_MUTE_ALL; 5179 ctl->left = 0; 5180 ctl->right = 0; 5181 ctl->enable = 0; 5182 if (ctl->ndir == HDA_CTL_IN) 5183 ctl->widget->connsenable[ctl->index] = 0; 5184 done = 0; 5185 HDA_BOOTHVERBOSE( 5186 device_printf(devinfo->codec->sc->dev, 5187 " Disabling ctl %d nid %d cnid %d due" 5188 " to disabled widget.\n", i, 5189 ctl->widget->nid, 5190 (ctl->childwidget != NULL)? 5191 ctl->childwidget->nid:-1); 5192 ); 5193 } 5194 } 5195 /* Disable useless widgets. */ 5196 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5197 w = hdac_widget_get(devinfo, i); 5198 if (w == NULL || w->enable == 0) 5199 continue; 5200 /* Disable inputs with disabled child widgets. */ 5201 for (j = 0; j < w->nconns; j++) { 5202 if (w->connsenable[j]) { 5203 cw = hdac_widget_get(devinfo, w->conns[j]); 5204 if (cw == NULL || cw->enable == 0) { 5205 w->connsenable[j] = 0; 5206 HDA_BOOTHVERBOSE( 5207 device_printf(devinfo->codec->sc->dev, 5208 " Disabling nid %d connection %d due" 5209 " to disabled child widget.\n", 5210 i, j); 5211 ); 5212 } 5213 } 5214 } 5215 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5216 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5217 continue; 5218 /* Disable mixers and selectors without inputs. */ 5219 found = 0; 5220 for (j = 0; j < w->nconns; j++) { 5221 if (w->connsenable[j]) { 5222 found = 1; 5223 break; 5224 } 5225 } 5226 if (found == 0) { 5227 w->enable = 0; 5228 done = 0; 5229 HDA_BOOTHVERBOSE( 5230 device_printf(devinfo->codec->sc->dev, 5231 " Disabling nid %d due to all it's" 5232 " inputs disabled.\n", w->nid); 5233 ); 5234 } 5235 /* Disable nodes without consumers. */ 5236 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5237 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5238 continue; 5239 found = 0; 5240 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5241 cw = hdac_widget_get(devinfo, k); 5242 if (cw == NULL || cw->enable == 0) 5243 continue; 5244 for (j = 0; j < cw->nconns; j++) { 5245 if (cw->connsenable[j] && cw->conns[j] == i) { 5246 found = 1; 5247 break; 5248 } 5249 } 5250 } 5251 if (found == 0) { 5252 w->enable = 0; 5253 done = 0; 5254 HDA_BOOTHVERBOSE( 5255 device_printf(devinfo->codec->sc->dev, 5256 " Disabling nid %d due to all it's" 5257 " consumers disabled.\n", w->nid); 5258 ); 5259 } 5260 } 5261 } while (done == 0); 5262 5263} 5264 5265static void 5266hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5267{ 5268 struct hdac_audio_as *as = devinfo->function.audio.as; 5269 struct hdac_widget *w, *cw; 5270 struct hdac_audio_ctl *ctl; 5271 int i, j, k; 5272 5273 /* Disable unassosiated widgets. */ 5274 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5275 w = hdac_widget_get(devinfo, i); 5276 if (w == NULL || w->enable == 0) 5277 continue; 5278 if (w->bindas == -1) { 5279 w->enable = 0; 5280 HDA_BOOTHVERBOSE( 5281 device_printf(devinfo->codec->sc->dev, 5282 " Disabling unassociated nid %d.\n", 5283 w->nid); 5284 ); 5285 } 5286 } 5287 /* Disable input connections on input pin and 5288 * output on output. */ 5289 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5290 w = hdac_widget_get(devinfo, i); 5291 if (w == NULL || w->enable == 0) 5292 continue; 5293 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5294 continue; 5295 if (w->bindas < 0) 5296 continue; 5297 if (as[w->bindas].dir == HDA_CTL_IN) { 5298 for (j = 0; j < w->nconns; j++) { 5299 if (w->connsenable[j] == 0) 5300 continue; 5301 w->connsenable[j] = 0; 5302 HDA_BOOTHVERBOSE( 5303 device_printf(devinfo->codec->sc->dev, 5304 " Disabling connection to input pin " 5305 "nid %d conn %d.\n", 5306 i, j); 5307 ); 5308 } 5309 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5310 HDA_CTL_IN, -1, 1); 5311 if (ctl && ctl->enable) { 5312 ctl->forcemute = 1; 5313 ctl->muted = HDA_AMP_MUTE_ALL; 5314 ctl->left = 0; 5315 ctl->right = 0; 5316 ctl->enable = 0; 5317 } 5318 } else { 5319 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5320 HDA_CTL_OUT, -1, 1); 5321 if (ctl && ctl->enable) { 5322 ctl->forcemute = 1; 5323 ctl->muted = HDA_AMP_MUTE_ALL; 5324 ctl->left = 0; 5325 ctl->right = 0; 5326 ctl->enable = 0; 5327 } 5328 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5329 cw = hdac_widget_get(devinfo, k); 5330 if (cw == NULL || cw->enable == 0) 5331 continue; 5332 for (j = 0; j < cw->nconns; j++) { 5333 if (cw->connsenable[j] && cw->conns[j] == i) { 5334 cw->connsenable[j] = 0; 5335 HDA_BOOTHVERBOSE( 5336 device_printf(devinfo->codec->sc->dev, 5337 " Disabling connection from output pin " 5338 "nid %d conn %d cnid %d.\n", 5339 k, j, i); 5340 ); 5341 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5342 cw->nconns > 1) 5343 continue; 5344 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5345 HDA_CTL_IN, j, 1); 5346 if (ctl && ctl->enable) { 5347 ctl->forcemute = 1; 5348 ctl->muted = HDA_AMP_MUTE_ALL; 5349 ctl->left = 0; 5350 ctl->right = 0; 5351 ctl->enable = 0; 5352 } 5353 } 5354 } 5355 } 5356 } 5357 } 5358} 5359 5360static void 5361hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5362{ 5363 struct hdac_audio_as *as = devinfo->function.audio.as; 5364 struct hdac_widget *w; 5365 int i, j; 5366 5367 /* On playback path we can safely disable all unseleted inputs. */ 5368 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5369 w = hdac_widget_get(devinfo, i); 5370 if (w == NULL || w->enable == 0) 5371 continue; 5372 if (w->nconns <= 1) 5373 continue; 5374 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5375 continue; 5376 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5377 continue; 5378 for (j = 0; j < w->nconns; j++) { 5379 if (w->connsenable[j] == 0) 5380 continue; 5381 if (w->selconn < 0 || w->selconn == j) 5382 continue; 5383 w->connsenable[j] = 0; 5384 HDA_BOOTHVERBOSE( 5385 device_printf(devinfo->codec->sc->dev, 5386 " Disabling unselected connection " 5387 "nid %d conn %d.\n", 5388 i, j); 5389 ); 5390 } 5391 } 5392} 5393 5394static void 5395hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5396{ 5397 struct hdac_widget *w, *cw; 5398 struct hdac_audio_ctl *ctl; 5399 int i, j; 5400 5401 /* Disable crossassociatement connections. */ 5402 /* ... using selectors */ 5403 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5404 w = hdac_widget_get(devinfo, i); 5405 if (w == NULL || w->enable == 0) 5406 continue; 5407 if (w->nconns <= 1) 5408 continue; 5409 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5410 continue; 5411 if (w->bindas == -2) 5412 continue; 5413 for (j = 0; j < w->nconns; j++) { 5414 if (w->connsenable[j] == 0) 5415 continue; 5416 cw = hdac_widget_get(devinfo, w->conns[j]); 5417 if (cw == NULL || w->enable == 0) 5418 continue; 5419 if (w->bindas == cw->bindas || cw->bindas == -2) 5420 continue; 5421 w->connsenable[j] = 0; 5422 HDA_BOOTHVERBOSE( 5423 device_printf(devinfo->codec->sc->dev, 5424 " Disabling crossassociatement connection " 5425 "nid %d conn %d cnid %d.\n", 5426 i, j, cw->nid); 5427 ); 5428 } 5429 } 5430 /* ... using controls */ 5431 i = 0; 5432 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5433 if (ctl->enable == 0 || ctl->childwidget == NULL) 5434 continue; 5435 if (ctl->widget->bindas == -2 || 5436 ctl->childwidget->bindas == -2) 5437 continue; 5438 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5439 ctl->forcemute = 1; 5440 ctl->muted = HDA_AMP_MUTE_ALL; 5441 ctl->left = 0; 5442 ctl->right = 0; 5443 ctl->enable = 0; 5444 if (ctl->ndir == HDA_CTL_IN) 5445 ctl->widget->connsenable[ctl->index] = 0; 5446 HDA_BOOTHVERBOSE( 5447 device_printf(devinfo->codec->sc->dev, 5448 " Disabling crossassociatement connection " 5449 "ctl %d nid %d cnid %d.\n", i, 5450 ctl->widget->nid, 5451 ctl->childwidget->nid); 5452 ); 5453 } 5454 } 5455 5456} 5457 5458#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5459 5460/* 5461 * Find controls to control amplification for source. 5462 */ 5463static int 5464hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5465 int ossdev, int ctlable, int depth, int need) 5466{ 5467 struct hdac_widget *w, *wc; 5468 struct hdac_audio_ctl *ctl; 5469 int i, j, conns = 0, rneed; 5470 5471 if (depth > HDA_PARSE_MAXDEPTH) 5472 return (need); 5473 5474 w = hdac_widget_get(devinfo, nid); 5475 if (w == NULL || w->enable == 0) 5476 return (need); 5477 5478 /* Count number of active inputs. */ 5479 if (depth > 0) { 5480 for (j = 0; j < w->nconns; j++) { 5481 if (w->connsenable[j]) 5482 conns++; 5483 } 5484 } 5485 5486 /* If this is not a first step - use input mixer. 5487 Pins have common input ctl so care must be taken. */ 5488 if (depth > 0 && ctlable && (conns == 1 || 5489 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5490 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5491 index, 1); 5492 if (ctl) { 5493 if (HDA_CTL_GIVE(ctl) & need) 5494 ctl->ossmask |= (1 << ossdev); 5495 else 5496 ctl->possmask |= (1 << ossdev); 5497 need &= ~HDA_CTL_GIVE(ctl); 5498 } 5499 } 5500 5501 /* If widget has own ossdev - not traverse it. 5502 It will be traversed on it's own. */ 5503 if (w->ossdev >= 0 && depth > 0) 5504 return (need); 5505 5506 /* We must not traverse pin */ 5507 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5508 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5509 depth > 0) 5510 return (need); 5511 5512 /* record that this widget exports such signal, */ 5513 w->ossmask |= (1 << ossdev); 5514 5515 /* If signals mixed, we can't assign controls farther. 5516 * Ignore this on depth zero. Caller must knows why. 5517 * Ignore this for static selectors if this input selected. 5518 */ 5519 if (conns > 1) 5520 ctlable = 0; 5521 5522 if (ctlable) { 5523 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5524 if (ctl) { 5525 if (HDA_CTL_GIVE(ctl) & need) 5526 ctl->ossmask |= (1 << ossdev); 5527 else 5528 ctl->possmask |= (1 << ossdev); 5529 need &= ~HDA_CTL_GIVE(ctl); 5530 } 5531 } 5532 5533 rneed = 0; 5534 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5535 wc = hdac_widget_get(devinfo, i); 5536 if (wc == NULL || wc->enable == 0) 5537 continue; 5538 for (j = 0; j < wc->nconns; j++) { 5539 if (wc->connsenable[j] && wc->conns[j] == nid) { 5540 rneed |= hdac_audio_ctl_source_amp(devinfo, 5541 wc->nid, j, ossdev, ctlable, depth + 1, need); 5542 } 5543 } 5544 } 5545 rneed &= need; 5546 5547 return (rneed); 5548} 5549 5550/* 5551 * Find controls to control amplification for destination. 5552 */ 5553static void 5554hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5555 int ossdev, int depth, int need) 5556{ 5557 struct hdac_audio_as *as = devinfo->function.audio.as; 5558 struct hdac_widget *w, *wc; 5559 struct hdac_audio_ctl *ctl; 5560 int i, j, consumers; 5561 5562 if (depth > HDA_PARSE_MAXDEPTH) 5563 return; 5564 5565 w = hdac_widget_get(devinfo, nid); 5566 if (w == NULL || w->enable == 0) 5567 return; 5568 5569 if (depth > 0) { 5570 /* If this node produce output for several consumers, 5571 we can't touch it. */ 5572 consumers = 0; 5573 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5574 wc = hdac_widget_get(devinfo, i); 5575 if (wc == NULL || wc->enable == 0) 5576 continue; 5577 for (j = 0; j < wc->nconns; j++) { 5578 if (wc->connsenable[j] && wc->conns[j] == nid) 5579 consumers++; 5580 } 5581 } 5582 /* The only exception is if real HP redirection is configured 5583 and this is a duplication point. 5584 XXX: Actually exception is not completely correct. 5585 XXX: Duplication point check is not perfect. */ 5586 if ((consumers == 2 && (w->bindas < 0 || 5587 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5588 (w->bindseqmask & (1 << 15)) == 0)) || 5589 consumers > 2) 5590 return; 5591 5592 /* Else use it's output mixer. */ 5593 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5594 HDA_CTL_OUT, -1, 1); 5595 if (ctl) { 5596 if (HDA_CTL_GIVE(ctl) & need) 5597 ctl->ossmask |= (1 << ossdev); 5598 else 5599 ctl->possmask |= (1 << ossdev); 5600 need &= ~HDA_CTL_GIVE(ctl); 5601 } 5602 } 5603 5604 /* We must not traverse pin */ 5605 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5606 depth > 0) 5607 return; 5608 5609 for (i = 0; i < w->nconns; i++) { 5610 int tneed = need; 5611 if (w->connsenable[i] == 0) 5612 continue; 5613 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5614 HDA_CTL_IN, i, 1); 5615 if (ctl) { 5616 if (HDA_CTL_GIVE(ctl) & tneed) 5617 ctl->ossmask |= (1 << ossdev); 5618 else 5619 ctl->possmask |= (1 << ossdev); 5620 tneed &= ~HDA_CTL_GIVE(ctl); 5621 } 5622 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5623 depth + 1, tneed); 5624 } 5625} 5626 5627/* 5628 * Assign OSS names to sound sources 5629 */ 5630static void 5631hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5632{ 5633 struct hdac_audio_as *as = devinfo->function.audio.as; 5634 struct hdac_widget *w; 5635 int i, j; 5636 int type = -1, use, used = 0; 5637 static const int types[7][13] = { 5638 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5639 SOUND_MIXER_LINE3, -1 }, /* line */ 5640 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5641 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5642 { SOUND_MIXER_CD, -1 }, /* cd */ 5643 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5644 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5645 -1 }, /* digital */ 5646 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5647 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5648 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5649 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5650 -1 } /* others */ 5651 }; 5652 5653 /* Surely known names */ 5654 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5655 w = hdac_widget_get(devinfo, i); 5656 if (w == NULL || w->enable == 0) 5657 continue; 5658 if (w->bindas == -1) 5659 continue; 5660 use = -1; 5661 switch (w->type) { 5662 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5663 if (as[w->bindas].dir == HDA_CTL_OUT) 5664 break; 5665 type = -1; 5666 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5667 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5668 type = 0; 5669 break; 5670 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5671 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5672 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5673 break; 5674 type = 1; 5675 break; 5676 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5677 type = 3; 5678 break; 5679 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5680 type = 4; 5681 break; 5682 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5683 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5684 type = 5; 5685 break; 5686 } 5687 if (type == -1) 5688 break; 5689 j = 0; 5690 while (types[type][j] >= 0 && 5691 (used & (1 << types[type][j])) != 0) { 5692 j++; 5693 } 5694 if (types[type][j] >= 0) 5695 use = types[type][j]; 5696 break; 5697 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5698 use = SOUND_MIXER_PCM; 5699 break; 5700 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5701 use = SOUND_MIXER_SPEAKER; 5702 break; 5703 default: 5704 break; 5705 } 5706 if (use >= 0) { 5707 w->ossdev = use; 5708 used |= (1 << use); 5709 } 5710 } 5711 /* Semi-known names */ 5712 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5713 w = hdac_widget_get(devinfo, i); 5714 if (w == NULL || w->enable == 0) 5715 continue; 5716 if (w->ossdev >= 0) 5717 continue; 5718 if (w->bindas == -1) 5719 continue; 5720 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5721 continue; 5722 if (as[w->bindas].dir == HDA_CTL_OUT) 5723 continue; 5724 type = -1; 5725 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5726 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5727 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5728 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5729 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5730 type = 0; 5731 break; 5732 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5733 type = 2; 5734 break; 5735 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5736 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5737 type = 5; 5738 break; 5739 } 5740 if (type == -1) 5741 break; 5742 j = 0; 5743 while (types[type][j] >= 0 && 5744 (used & (1 << types[type][j])) != 0) { 5745 j++; 5746 } 5747 if (types[type][j] >= 0) { 5748 w->ossdev = types[type][j]; 5749 used |= (1 << types[type][j]); 5750 } 5751 } 5752 /* Others */ 5753 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5754 w = hdac_widget_get(devinfo, i); 5755 if (w == NULL || w->enable == 0) 5756 continue; 5757 if (w->ossdev >= 0) 5758 continue; 5759 if (w->bindas == -1) 5760 continue; 5761 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5762 continue; 5763 if (as[w->bindas].dir == HDA_CTL_OUT) 5764 continue; 5765 j = 0; 5766 while (types[6][j] >= 0 && 5767 (used & (1 << types[6][j])) != 0) { 5768 j++; 5769 } 5770 if (types[6][j] >= 0) { 5771 w->ossdev = types[6][j]; 5772 used |= (1 << types[6][j]); 5773 } 5774 } 5775} 5776 5777static void 5778hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5779{ 5780 struct hdac_audio_as *as = devinfo->function.audio.as; 5781 int j, res; 5782 5783 /* Trace all associations in order of their numbers, */ 5784 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5785 if (as[j].enable == 0) 5786 continue; 5787 HDA_BOOTVERBOSE( 5788 device_printf(devinfo->codec->sc->dev, 5789 "Tracing association %d (%d)\n", j, as[j].index); 5790 ); 5791 if (as[j].dir == HDA_CTL_OUT) { 5792retry: 5793 res = hdac_audio_trace_as_out(devinfo, j, 0); 5794 if (res == 0 && as[j].hpredir >= 0 && 5795 as[j].fakeredir == 0) { 5796 /* If codec can't do analog HP redirection 5797 try to make it using one more DAC. */ 5798 as[j].fakeredir = 1; 5799 goto retry; 5800 } 5801 } else { 5802 res = hdac_audio_trace_as_in(devinfo, j); 5803 } 5804 if (res) { 5805 HDA_BOOTVERBOSE( 5806 device_printf(devinfo->codec->sc->dev, 5807 "Association %d (%d) trace succeded\n", 5808 j, as[j].index); 5809 ); 5810 } else { 5811 HDA_BOOTVERBOSE( 5812 device_printf(devinfo->codec->sc->dev, 5813 "Association %d (%d) trace failed\n", 5814 j, as[j].index); 5815 ); 5816 as[j].enable = 0; 5817 } 5818 } 5819 5820 /* Trace mixer and beeper pseudo associations. */ 5821 hdac_audio_trace_as_extra(devinfo); 5822} 5823 5824static void 5825hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5826{ 5827 struct hdac_audio_as *as = devinfo->function.audio.as; 5828 struct hdac_audio_ctl *ctl; 5829 struct hdac_widget *w; 5830 int i; 5831 5832 /* Assign mixers to the tree. */ 5833 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5834 w = hdac_widget_get(devinfo, i); 5835 if (w == NULL || w->enable == 0) 5836 continue; 5837 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5838 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5839 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5840 as[w->bindas].dir == HDA_CTL_IN)) { 5841 if (w->ossdev < 0) 5842 continue; 5843 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5844 w->ossdev, 1, 0, 1); 5845 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5846 if (w->ossdev < 0) 5847 continue; 5848 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5849 w->ossdev, 1, 0, 1)) { 5850 /* If we are unable to control input monitor 5851 as source - try to control it as destination. */ 5852 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5853 w->ossdev, 0, 1); 5854 } 5855 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5856 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5857 SOUND_MIXER_RECLEV, 0, 1); 5858 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5859 as[w->bindas].dir == HDA_CTL_OUT) { 5860 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5861 SOUND_MIXER_VOLUME, 0, 1); 5862 } 5863 } 5864 /* Treat unrequired as possible. */ 5865 i = 0; 5866 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5867 if (ctl->ossmask == 0) 5868 ctl->ossmask = ctl->possmask; 5869 } 5870} 5871 5872static void 5873hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5874{ 5875 struct hdac_audio_as *as = devinfo->function.audio.as; 5876 struct hdac_widget *w; 5877 uint32_t pincap; 5878 int i; 5879 5880 for (i = 0; i < devinfo->nodecnt; i++) { 5881 w = &devinfo->widget[i]; 5882 if (w == NULL) 5883 continue; 5884 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5885 continue; 5886 5887 pincap = w->wclass.pin.cap; 5888 5889 /* Disable everything. */ 5890 w->wclass.pin.ctrl &= ~( 5891 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5892 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5893 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5894 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5895 5896 if (w->enable == 0 || 5897 w->bindas < 0 || as[w->bindas].enable == 0) { 5898 /* Pin is unused so left it disabled. */ 5899 continue; 5900 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5901 /* Input pin, configure for input. */ 5902 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5903 w->wclass.pin.ctrl |= 5904 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5905 5906 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5907 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5908 w->wclass.pin.ctrl |= 5909 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5910 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5911 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5912 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5913 w->wclass.pin.ctrl |= 5914 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5915 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5916 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5917 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5918 w->wclass.pin.ctrl |= 5919 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5920 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5921 } else { 5922 /* Output pin, configure for output. */ 5923 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5924 w->wclass.pin.ctrl |= 5925 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5926 5927 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5928 (w->wclass.pin.config & 5929 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5930 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5931 w->wclass.pin.ctrl |= 5932 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5933 5934 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5935 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5936 w->wclass.pin.ctrl |= 5937 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5938 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5939 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5940 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5941 w->wclass.pin.ctrl |= 5942 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5943 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5944 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5945 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5946 w->wclass.pin.ctrl |= 5947 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5948 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5949 } 5950 } 5951} 5952 5953static void 5954hdac_audio_commit(struct hdac_devinfo *devinfo) 5955{ 5956 struct hdac_softc *sc = devinfo->codec->sc; 5957 struct hdac_widget *w; 5958 nid_t cad; 5959 uint32_t gdata, gmask, gdir; 5960 int commitgpio, numgpio; 5961 int i; 5962 5963 cad = devinfo->codec->cad; 5964 5965 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5966 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5967 0x7e7, 0), cad); 5968 5969 gdata = 0; 5970 gmask = 0; 5971 gdir = 0; 5972 commitgpio = 0; 5973 5974 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5975 devinfo->function.audio.gpio); 5976 5977 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5978 commitgpio = (numgpio > 0) ? 1 : 0; 5979 else { 5980 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5981 if (!(devinfo->function.audio.quirks & 5982 (1 << i))) 5983 continue; 5984 if (commitgpio == 0) { 5985 commitgpio = 1; 5986 HDA_BOOTVERBOSE( 5987 gdata = hdac_command(sc, 5988 HDA_CMD_GET_GPIO_DATA(cad, 5989 devinfo->nid), cad); 5990 gmask = hdac_command(sc, 5991 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5992 devinfo->nid), cad); 5993 gdir = hdac_command(sc, 5994 HDA_CMD_GET_GPIO_DIRECTION(cad, 5995 devinfo->nid), cad); 5996 device_printf(sc->dev, 5997 "GPIO init: data=0x%08x " 5998 "mask=0x%08x dir=0x%08x\n", 5999 gdata, gmask, gdir); 6000 gdata = 0; 6001 gmask = 0; 6002 gdir = 0; 6003 ); 6004 } 6005 gdata |= 1 << i; 6006 gmask |= 1 << i; 6007 gdir |= 1 << i; 6008 } 6009 } 6010 6011 if (commitgpio != 0) { 6012 HDA_BOOTVERBOSE( 6013 device_printf(sc->dev, 6014 "GPIO commit: data=0x%08x mask=0x%08x " 6015 "dir=0x%08x\n", 6016 gdata, gmask, gdir); 6017 ); 6018 hdac_command(sc, 6019 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6020 gmask), cad); 6021 hdac_command(sc, 6022 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6023 gdir), cad); 6024 hdac_command(sc, 6025 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6026 gdata), cad); 6027 } 6028 6029 for (i = 0; i < devinfo->nodecnt; i++) { 6030 w = &devinfo->widget[i]; 6031 if (w == NULL) 6032 continue; 6033 if (w->selconn == -1) 6034 w->selconn = 0; 6035 if (w->nconns > 0) 6036 hdac_widget_connection_select(w, w->selconn); 6037 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6038 hdac_command(sc, 6039 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6040 w->wclass.pin.ctrl), cad); 6041 } 6042 if (w->param.eapdbtl != HDAC_INVALID) { 6043 uint32_t val; 6044 6045 val = w->param.eapdbtl; 6046 if (devinfo->function.audio.quirks & 6047 HDA_QUIRK_EAPDINV) 6048 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6049 hdac_command(sc, 6050 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6051 val), cad); 6052 6053 } 6054 } 6055} 6056 6057static void 6058hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6059{ 6060 struct hdac_audio_ctl *ctl; 6061 int i, z; 6062 6063 i = 0; 6064 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6065 if (ctl->enable == 0) { 6066 /* Mute disabled controls. */ 6067 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6068 continue; 6069 } 6070 /* Init controls to 0dB amplification. */ 6071 z = ctl->offset; 6072 if (z > ctl->step) 6073 z = ctl->step; 6074 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6075 } 6076} 6077 6078static void 6079hdac_powerup(struct hdac_devinfo *devinfo) 6080{ 6081 struct hdac_softc *sc = devinfo->codec->sc; 6082 nid_t cad = devinfo->codec->cad; 6083 int i; 6084 6085 hdac_command(sc, 6086 HDA_CMD_SET_POWER_STATE(cad, 6087 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6088 cad); 6089 DELAY(100); 6090 6091 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6092 hdac_command(sc, 6093 HDA_CMD_SET_POWER_STATE(cad, 6094 i, HDA_CMD_POWER_STATE_D0), 6095 cad); 6096 } 6097 DELAY(1000); 6098} 6099 6100static int 6101hdac_pcmchannel_setup(struct hdac_chan *ch) 6102{ 6103 struct hdac_devinfo *devinfo = ch->devinfo; 6104 struct hdac_audio_as *as = devinfo->function.audio.as; 6105 struct hdac_widget *w; 6106 uint32_t cap, fmtcap, pcmcap; 6107 int i, j, ret, max; 6108 6109 ch->caps = hdac_caps; 6110 ch->caps.fmtlist = ch->fmtlist; 6111 ch->bit16 = 1; 6112 ch->bit32 = 0; 6113 ch->pcmrates[0] = 48000; 6114 ch->pcmrates[1] = 0; 6115 6116 ret = 0; 6117 fmtcap = devinfo->function.audio.supp_stream_formats; 6118 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6119 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6120 6121 for (i = 0; i < 16 && ret < max; i++) { 6122 /* Check as is correct */ 6123 if (ch->as < 0) 6124 break; 6125 /* Cound only present DACs */ 6126 if (as[ch->as].dacs[i] <= 0) 6127 continue; 6128 /* Ignore duplicates */ 6129 for (j = 0; j < ret; j++) { 6130 if (ch->io[j] == as[ch->as].dacs[i]) 6131 break; 6132 } 6133 if (j < ret) 6134 continue; 6135 6136 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6137 if (w == NULL || w->enable == 0) 6138 continue; 6139 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6140 continue; 6141 cap = w->param.supp_stream_formats; 6142 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6143 }*/ 6144 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6145 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6146 continue; 6147 /* Many codec does not declare AC3 support on SPDIF. 6148 I don't beleave that they doesn't support it! */ 6149 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6150 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6151 if (ret == 0) { 6152 fmtcap = cap; 6153 pcmcap = w->param.supp_pcm_size_rate; 6154 } else { 6155 fmtcap &= cap; 6156 pcmcap &= w->param.supp_pcm_size_rate; 6157 } 6158 ch->io[ret++] = as[ch->as].dacs[i]; 6159 } 6160 ch->io[ret] = -1; 6161 6162 ch->supp_stream_formats = fmtcap; 6163 ch->supp_pcm_size_rate = pcmcap; 6164 6165 /* 6166 * 8bit = 0 6167 * 16bit = 1 6168 * 20bit = 2 6169 * 24bit = 3 6170 * 32bit = 4 6171 */ 6172 if (ret > 0) { 6173 i = 0; 6174 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6175 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6176 ch->bit16 = 1; 6177 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6178 ch->bit16 = 0; 6179 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6180 ch->bit32 = 4; 6181 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6182 ch->bit32 = 3; 6183 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6184 ch->bit32 = 2; 6185 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6186 ch->fmtlist[i++] = AFMT_S16_LE; 6187 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6188 if (ch->bit32 > 0) { 6189 if (!(devinfo->function.audio.quirks & 6190 HDA_QUIRK_FORCESTEREO)) 6191 ch->fmtlist[i++] = AFMT_S32_LE; 6192 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6193 } 6194 } 6195 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6196 ch->fmtlist[i++] = AFMT_AC3; 6197 } 6198 ch->fmtlist[i] = 0; 6199 i = 0; 6200 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6201 ch->pcmrates[i++] = 8000; 6202 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6203 ch->pcmrates[i++] = 11025; 6204 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6205 ch->pcmrates[i++] = 16000; 6206 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6207 ch->pcmrates[i++] = 22050; 6208 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6209 ch->pcmrates[i++] = 32000; 6210 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6211 ch->pcmrates[i++] = 44100; 6212 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6213 ch->pcmrates[i++] = 48000; 6214 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6215 ch->pcmrates[i++] = 88200; 6216 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6217 ch->pcmrates[i++] = 96000; 6218 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6219 ch->pcmrates[i++] = 176400; 6220 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6221 ch->pcmrates[i++] = 192000; 6222 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6223 ch->pcmrates[i] = 0; 6224 if (i > 0) { 6225 ch->caps.minspeed = ch->pcmrates[0]; 6226 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6227 } 6228 } 6229 6230 return (ret); 6231} 6232 6233static void 6234hdac_create_pcms(struct hdac_devinfo *devinfo) 6235{ 6236 struct hdac_softc *sc = devinfo->codec->sc; 6237 struct hdac_audio_as *as = devinfo->function.audio.as; 6238 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6239 6240 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6241 if (as[i].enable == 0) 6242 continue; 6243 if (as[i].dir == HDA_CTL_IN) { 6244 if (as[i].digital) 6245 drdev++; 6246 else 6247 ardev++; 6248 } else { 6249 if (as[i].digital) 6250 dpdev++; 6251 else 6252 apdev++; 6253 } 6254 } 6255 devinfo->function.audio.num_devs = 6256 max(ardev, apdev) + max(drdev, dpdev); 6257 devinfo->function.audio.devs = 6258 (struct hdac_pcm_devinfo *)malloc( 6259 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6260 M_HDAC, M_ZERO | M_NOWAIT); 6261 if (devinfo->function.audio.devs == NULL) { 6262 device_printf(sc->dev, 6263 "Unable to allocate memory for devices\n"); 6264 return; 6265 } 6266 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6267 devinfo->function.audio.devs[i].index = i; 6268 devinfo->function.audio.devs[i].devinfo = devinfo; 6269 devinfo->function.audio.devs[i].play = -1; 6270 devinfo->function.audio.devs[i].rec = -1; 6271 devinfo->function.audio.devs[i].digital = 2; 6272 } 6273 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6274 if (as[i].enable == 0) 6275 continue; 6276 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6277 if (devinfo->function.audio.devs[j].digital != 2 && 6278 devinfo->function.audio.devs[j].digital != 6279 as[i].digital) 6280 continue; 6281 if (as[i].dir == HDA_CTL_IN) { 6282 if (devinfo->function.audio.devs[j].rec >= 0) 6283 continue; 6284 devinfo->function.audio.devs[j].rec 6285 = as[i].chan; 6286 } else { 6287 if (devinfo->function.audio.devs[j].play >= 0) 6288 continue; 6289 devinfo->function.audio.devs[j].play 6290 = as[i].chan; 6291 } 6292 sc->chans[as[i].chan].pdevinfo = 6293 &devinfo->function.audio.devs[j]; 6294 devinfo->function.audio.devs[j].digital = 6295 as[i].digital; 6296 break; 6297 } 6298 } 6299 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6300 struct hdac_pcm_devinfo *pdevinfo = 6301 &devinfo->function.audio.devs[i]; 6302 pdevinfo->dev = 6303 device_add_child(sc->dev, "pcm", -1); 6304 device_set_ivars(pdevinfo->dev, 6305 (void *)pdevinfo); 6306 } 6307} 6308 6309static void 6310hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6311{ 6312 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6313 struct hdac_audio_ctl *ctl; 6314 struct hdac_softc *sc = devinfo->codec->sc; 6315 char buf[64]; 6316 int i, j, printed; 6317 6318 if (flag == 0) { 6319 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6320 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6321 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6322 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6323 } 6324 6325 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6326 if ((flag & (1 << j)) == 0) 6327 continue; 6328 i = 0; 6329 printed = 0; 6330 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6331 if (ctl->enable == 0 || 6332 ctl->widget->enable == 0) 6333 continue; 6334 if (!((pdevinfo->play >= 0 && 6335 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6336 (pdevinfo->rec >= 0 && 6337 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6338 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6339 continue; 6340 if ((ctl->ossmask & (1 << j)) == 0) 6341 continue; 6342 6343 if (printed == 0) { 6344 device_printf(pdevinfo->dev, "\n"); 6345 if (banner != NULL) { 6346 device_printf(pdevinfo->dev, "%s", banner); 6347 } else { 6348 device_printf(pdevinfo->dev, "Unknown Ctl"); 6349 } 6350 printf(" (OSS: %s)\n", 6351 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6352 buf, sizeof(buf))); 6353 device_printf(pdevinfo->dev, " |\n"); 6354 printed = 1; 6355 } 6356 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6357 ctl->widget->nid, 6358 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6359 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6360 printf(" %2d): ", ctl->index); 6361 else 6362 printf("): "); 6363 if (ctl->step > 0) { 6364 printf("%+d/%+ddB (%d steps)%s\n", 6365 (0 - ctl->offset) * (ctl->size + 1) / 4, 6366 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6367 ctl->step + 1, 6368 ctl->mute?" + mute":""); 6369 } else 6370 printf("%s\n", ctl->mute?"mute":""); 6371 } 6372 } 6373} 6374 6375static void 6376hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6377{ 6378 uint32_t cap; 6379 6380 cap = fcap; 6381 if (cap != 0) { 6382 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6383 device_printf(dev, " "); 6384 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6385 printf(" AC3"); 6386 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6387 printf(" FLOAT32"); 6388 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6389 printf(" PCM"); 6390 printf("\n"); 6391 } 6392 cap = pcmcap; 6393 if (cap != 0) { 6394 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6395 device_printf(dev, " "); 6396 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6397 printf(" 8"); 6398 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6399 printf(" 16"); 6400 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6401 printf(" 20"); 6402 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6403 printf(" 24"); 6404 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6405 printf(" 32"); 6406 printf(" bits,"); 6407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6408 printf(" 8"); 6409 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6410 printf(" 11"); 6411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6412 printf(" 16"); 6413 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6414 printf(" 22"); 6415 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6416 printf(" 32"); 6417 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6418 printf(" 44"); 6419 printf(" 48"); 6420 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6421 printf(" 88"); 6422 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6423 printf(" 96"); 6424 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6425 printf(" 176"); 6426 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6427 printf(" 192"); 6428 printf(" KHz\n"); 6429 } 6430} 6431 6432static void 6433hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6434{ 6435 uint32_t pincap; 6436 6437 pincap = w->wclass.pin.cap; 6438 6439 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6440 device_printf(sc->dev, " "); 6441 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6442 printf(" ISC"); 6443 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6444 printf(" TRQD"); 6445 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6446 printf(" PDC"); 6447 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6448 printf(" HP"); 6449 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6450 printf(" OUT"); 6451 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6452 printf(" IN"); 6453 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6454 printf(" BAL"); 6455 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6456 printf(" VREF["); 6457 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6458 printf(" 50"); 6459 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6460 printf(" 80"); 6461 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6462 printf(" 100"); 6463 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6464 printf(" GROUND"); 6465 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6466 printf(" HIZ"); 6467 printf(" ]"); 6468 } 6469 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6470 printf(" EAPD"); 6471 printf("\n"); 6472 device_printf(sc->dev, " Pin config: 0x%08x\n", 6473 w->wclass.pin.config); 6474 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6475 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6476 printf(" HP"); 6477 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6478 printf(" IN"); 6479 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6480 printf(" OUT"); 6481 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6482 printf(" VREFs"); 6483 printf("\n"); 6484} 6485 6486static void 6487hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6488{ 6489 struct hdac_softc *sc = w->devinfo->codec->sc; 6490 6491 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6492 "jack %2d loc %2d color %7s misc %d%s\n", 6493 w->nid, conf, 6494 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6495 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6496 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6497 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6498 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6499 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6500 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6501 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6502 (w->enable == 0)?" [DISABLED]":""); 6503} 6504 6505static void 6506hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6507{ 6508 struct hdac_widget *w; 6509 int i; 6510 6511 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6512 w = hdac_widget_get(devinfo, i); 6513 if (w == NULL) 6514 continue; 6515 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6516 continue; 6517 hdac_dump_pin_config(w, w->wclass.pin.config); 6518 } 6519} 6520 6521static void 6522hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6523{ 6524 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6525 device_printf(sc->dev, " " 6526 "mute=%d step=%d size=%d offset=%d\n", 6527 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6528 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6529 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6530 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6531} 6532 6533static void 6534hdac_dump_nodes(struct hdac_devinfo *devinfo) 6535{ 6536 struct hdac_softc *sc = devinfo->codec->sc; 6537 static char *ossname[] = SOUND_DEVICE_NAMES; 6538 struct hdac_widget *w, *cw; 6539 char buf[64]; 6540 int i, j; 6541 6542 device_printf(sc->dev, "\n"); 6543 device_printf(sc->dev, "Default Parameter\n"); 6544 device_printf(sc->dev, "-----------------\n"); 6545 hdac_dump_audio_formats(sc->dev, 6546 devinfo->function.audio.supp_stream_formats, 6547 devinfo->function.audio.supp_pcm_size_rate); 6548 device_printf(sc->dev, " IN amp: 0x%08x\n", 6549 devinfo->function.audio.inamp_cap); 6550 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6551 devinfo->function.audio.outamp_cap); 6552 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6553 w = hdac_widget_get(devinfo, i); 6554 if (w == NULL) { 6555 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6556 continue; 6557 } 6558 device_printf(sc->dev, "\n"); 6559 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6560 (w->enable == 0) ? " [DISABLED]" : ""); 6561 device_printf(sc->dev, " Name: %s\n", w->name); 6562 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6563 w->param.widget_cap); 6564 if (w->param.widget_cap & 0x0ee1) { 6565 device_printf(sc->dev, " "); 6566 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6567 printf(" LRSWAP"); 6568 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6569 printf(" PWR"); 6570 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6571 printf(" DIGITAL"); 6572 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6573 printf(" UNSOL"); 6574 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6575 printf(" PROC"); 6576 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6577 printf(" STRIPE"); 6578 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6579 printf(" STEREO"); 6580 printf("\n"); 6581 } 6582 if (w->bindas != -1) { 6583 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6584 w->bindas, w->bindseqmask); 6585 } 6586 if (w->ossmask != 0 || w->ossdev >= 0) { 6587 device_printf(sc->dev, " OSS: %s", 6588 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6589 if (w->ossdev >= 0) 6590 printf(" (%s)", ossname[w->ossdev]); 6591 printf("\n"); 6592 } 6593 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6594 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6595 hdac_dump_audio_formats(sc->dev, 6596 w->param.supp_stream_formats, 6597 w->param.supp_pcm_size_rate); 6598 } else if (w->type == 6599 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6600 hdac_dump_pin(sc, w); 6601 if (w->param.eapdbtl != HDAC_INVALID) 6602 device_printf(sc->dev, " EAPD: 0x%08x\n", 6603 w->param.eapdbtl); 6604 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6605 w->param.outamp_cap != 0) 6606 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6607 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6608 w->param.inamp_cap != 0) 6609 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6610 if (w->nconns > 0) { 6611 device_printf(sc->dev, " connections: %d\n", w->nconns); 6612 device_printf(sc->dev, " |\n"); 6613 } 6614 for (j = 0; j < w->nconns; j++) { 6615 cw = hdac_widget_get(devinfo, w->conns[j]); 6616 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6617 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6618 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6619 if (cw == NULL) 6620 printf(" [UNKNOWN]"); 6621 else if (cw->enable == 0) 6622 printf(" [DISABLED]"); 6623 if (w->nconns > 1 && w->selconn == j && w->type != 6624 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6625 printf(" (selected)"); 6626 printf("\n"); 6627 } 6628 } 6629 6630} 6631 6632static void 6633hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6634{ 6635 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6636 struct hdac_widget *w, *cw; 6637 char buf[64]; 6638 int i, printed = 0; 6639 6640 if (depth > HDA_PARSE_MAXDEPTH) 6641 return; 6642 6643 w = hdac_widget_get(devinfo, nid); 6644 if (w == NULL || w->enable == 0) 6645 return; 6646 6647 if (depth == 0) 6648 device_printf(pdevinfo->dev, "%*s", 4, ""); 6649 else 6650 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6651 printf("nid=%d [%s]", w->nid, w->name); 6652 6653 if (depth > 0) { 6654 if (w->ossmask == 0) { 6655 printf("\n"); 6656 return; 6657 } 6658 printf(" [src: %s]", 6659 hdac_audio_ctl_ossmixer_mask2allname( 6660 w->ossmask, buf, sizeof(buf))); 6661 if (w->ossdev >= 0) { 6662 printf("\n"); 6663 return; 6664 } 6665 } 6666 printf("\n"); 6667 6668 for (i = 0; i < w->nconns; i++) { 6669 if (w->connsenable[i] == 0) 6670 continue; 6671 cw = hdac_widget_get(devinfo, w->conns[i]); 6672 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6673 continue; 6674 if (printed == 0) { 6675 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6676 printed = 1; 6677 } 6678 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6679 } 6680 6681} 6682 6683static void 6684hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6685{ 6686 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6687 struct hdac_softc *sc = devinfo->codec->sc; 6688 struct hdac_widget *w; 6689 int i, printed = 0; 6690 6691 if (pdevinfo->play < 0) 6692 return; 6693 6694 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6695 w = hdac_widget_get(devinfo, i); 6696 if (w == NULL || w->enable == 0) 6697 continue; 6698 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6699 continue; 6700 if (w->bindas != sc->chans[pdevinfo->play].as) 6701 continue; 6702 if (printed == 0) { 6703 printed = 1; 6704 device_printf(pdevinfo->dev, "\n"); 6705 device_printf(pdevinfo->dev, "Playback:\n"); 6706 } 6707 device_printf(pdevinfo->dev, "\n"); 6708 hdac_dump_dst_nid(pdevinfo, i, 0); 6709 } 6710} 6711 6712static void 6713hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6714{ 6715 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6716 struct hdac_softc *sc = devinfo->codec->sc; 6717 struct hdac_widget *w; 6718 int i; 6719 int printed = 0; 6720 6721 if (pdevinfo->rec < 0) 6722 return; 6723 6724 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6725 w = hdac_widget_get(devinfo, i); 6726 if (w == NULL || w->enable == 0) 6727 continue; 6728 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6729 continue; 6730 if (w->bindas != sc->chans[pdevinfo->rec].as) 6731 continue; 6732 if (printed == 0) { 6733 printed = 1; 6734 device_printf(pdevinfo->dev, "\n"); 6735 device_printf(pdevinfo->dev, "Record:\n"); 6736 } 6737 device_printf(pdevinfo->dev, "\n"); 6738 hdac_dump_dst_nid(pdevinfo, i, 0); 6739 } 6740} 6741 6742static void 6743hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6744{ 6745 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6746 struct hdac_widget *w; 6747 int i; 6748 int printed = 0; 6749 6750 if (pdevinfo->index != 0) 6751 return; 6752 6753 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6754 w = hdac_widget_get(devinfo, i); 6755 if (w == NULL || w->enable == 0) 6756 continue; 6757 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6758 continue; 6759 if (printed == 0) { 6760 printed = 1; 6761 device_printf(pdevinfo->dev, "\n"); 6762 device_printf(pdevinfo->dev, "Input Mix:\n"); 6763 } 6764 device_printf(pdevinfo->dev, "\n"); 6765 hdac_dump_dst_nid(pdevinfo, i, 0); 6766 } 6767} 6768 6769static void 6770hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6771{ 6772 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6773 nid_t *nids; 6774 int i; 6775 6776 if (pdevinfo->play >= 0) { 6777 i = pdevinfo->play; 6778 device_printf(pdevinfo->dev, "\n"); 6779 device_printf(pdevinfo->dev, "Playback:\n"); 6780 device_printf(pdevinfo->dev, "\n"); 6781 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6782 sc->chans[i].supp_pcm_size_rate); 6783 device_printf(pdevinfo->dev, " DAC:"); 6784 for (nids = sc->chans[i].io; *nids != -1; nids++) 6785 printf(" %d", *nids); 6786 printf("\n"); 6787 } 6788 if (pdevinfo->rec >= 0) { 6789 i = pdevinfo->rec; 6790 device_printf(pdevinfo->dev, "\n"); 6791 device_printf(pdevinfo->dev, "Record:\n"); 6792 device_printf(pdevinfo->dev, "\n"); 6793 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6794 sc->chans[i].supp_pcm_size_rate); 6795 device_printf(pdevinfo->dev, " ADC:"); 6796 for (nids = sc->chans[i].io; *nids != -1; nids++) 6797 printf(" %d", *nids); 6798 printf("\n"); 6799 } 6800} 6801 6802static void 6803hdac_release_resources(struct hdac_softc *sc) 6804{ 6805 int i, j; 6806 6807 if (sc == NULL) 6808 return; 6809 6810 hdac_lock(sc); 6811 sc->polling = 0; 6812 sc->poll_ival = 0; 6813 callout_stop(&sc->poll_hda); 6814 callout_stop(&sc->poll_hdac); 6815 callout_stop(&sc->poll_jack); 6816 hdac_reset(sc, 0); 6817 hdac_unlock(sc); 6818 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6819 callout_drain(&sc->poll_hda); 6820 callout_drain(&sc->poll_hdac); 6821 callout_drain(&sc->poll_jack); 6822 6823 hdac_irq_free(sc); 6824 6825 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6826 if (sc->codecs[i] == NULL) 6827 continue; 6828 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6829 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6830 if (sc->codecs[i]->fgs[j].node_type == 6831 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6832 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6833 M_HDAC); 6834 free(sc->codecs[i]->fgs[j].function.audio.as, 6835 M_HDAC); 6836 free(sc->codecs[i]->fgs[j].function.audio.devs, 6837 M_HDAC); 6838 } 6839 } 6840 free(sc->codecs[i]->fgs, M_HDAC); 6841 free(sc->codecs[i], M_HDAC); 6842 sc->codecs[i] = NULL; 6843 } 6844 6845 hdac_dma_free(sc, &sc->pos_dma); 6846 hdac_dma_free(sc, &sc->rirb_dma); 6847 hdac_dma_free(sc, &sc->corb_dma); 6848 for (i = 0; i < sc->num_chans; i++) { 6849 if (sc->chans[i].blkcnt > 0) 6850 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6851 } 6852 free(sc->chans, M_HDAC); 6853 if (sc->chan_dmat != NULL) { 6854 bus_dma_tag_destroy(sc->chan_dmat); 6855 sc->chan_dmat = NULL; 6856 } 6857 hdac_mem_free(sc); 6858 snd_mtxfree(sc->lock); 6859} 6860 6861/* This function surely going to make its way into upper level someday. */ 6862static void 6863hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6864{ 6865 const char *res = NULL; 6866 int i = 0, j, k, len, inv; 6867 6868 if (on != NULL) 6869 *on = 0; 6870 if (off != NULL) 6871 *off = 0; 6872 if (sc == NULL) 6873 return; 6874 if (resource_string_value(device_get_name(sc->dev), 6875 device_get_unit(sc->dev), "config", &res) != 0) 6876 return; 6877 if (!(res != NULL && strlen(res) > 0)) 6878 return; 6879 HDA_BOOTVERBOSE( 6880 device_printf(sc->dev, "HDA Config:"); 6881 ); 6882 for (;;) { 6883 while (res[i] != '\0' && 6884 (res[i] == ',' || isspace(res[i]) != 0)) 6885 i++; 6886 if (res[i] == '\0') { 6887 HDA_BOOTVERBOSE( 6888 printf("\n"); 6889 ); 6890 return; 6891 } 6892 j = i; 6893 while (res[j] != '\0' && 6894 !(res[j] == ',' || isspace(res[j]) != 0)) 6895 j++; 6896 len = j - i; 6897 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6898 inv = 2; 6899 else 6900 inv = 0; 6901 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6902 if (strncmp(res + i + inv, 6903 hdac_quirks_tab[k].key, len - inv) != 0) 6904 continue; 6905 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6906 break; 6907 HDA_BOOTVERBOSE( 6908 printf(" %s%s", (inv != 0) ? "no" : "", 6909 hdac_quirks_tab[k].key); 6910 ); 6911 if (inv == 0 && on != NULL) 6912 *on |= hdac_quirks_tab[k].value; 6913 else if (inv != 0 && off != NULL) 6914 *off |= hdac_quirks_tab[k].value; 6915 break; 6916 } 6917 i = j; 6918 } 6919} 6920 6921#ifdef SND_DYNSYSCTL 6922static int 6923sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6924{ 6925 struct hdac_softc *sc; 6926 device_t dev; 6927 uint32_t ctl; 6928 int err, val; 6929 6930 dev = oidp->oid_arg1; 6931 sc = device_get_softc(dev); 6932 if (sc == NULL) 6933 return (EINVAL); 6934 hdac_lock(sc); 6935 val = sc->polling; 6936 hdac_unlock(sc); 6937 err = sysctl_handle_int(oidp, &val, 0, req); 6938 6939 if (err != 0 || req->newptr == NULL) 6940 return (err); 6941 if (val < 0 || val > 1) 6942 return (EINVAL); 6943 6944 hdac_lock(sc); 6945 if (val != sc->polling) { 6946 if (val == 0) { 6947 callout_stop(&sc->poll_hda); 6948 callout_stop(&sc->poll_hdac); 6949 hdac_unlock(sc); 6950 callout_drain(&sc->poll_hda); 6951 callout_drain(&sc->poll_hdac); 6952 hdac_lock(sc); 6953 sc->polling = 0; 6954 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6955 ctl |= HDAC_INTCTL_GIE; 6956 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6957 } else { 6958 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6959 ctl &= ~HDAC_INTCTL_GIE; 6960 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6961 hdac_unlock(sc); 6962 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6963 hdac_lock(sc); 6964 sc->polling = 1; 6965 hdac_poll_reinit(sc); 6966 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6967 } 6968 } 6969 hdac_unlock(sc); 6970 6971 return (err); 6972} 6973 6974static int 6975sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6976{ 6977 struct hdac_softc *sc; 6978 device_t dev; 6979 int err, val; 6980 6981 dev = oidp->oid_arg1; 6982 sc = device_get_softc(dev); 6983 if (sc == NULL) 6984 return (EINVAL); 6985 hdac_lock(sc); 6986 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6987 hdac_unlock(sc); 6988 err = sysctl_handle_int(oidp, &val, 0, req); 6989 6990 if (err != 0 || req->newptr == NULL) 6991 return (err); 6992 6993 if (val < 1) 6994 val = 1; 6995 if (val > 5000) 6996 val = 5000; 6997 val = ((uint64_t)val * hz) / 1000; 6998 if (val < 1) 6999 val = 1; 7000 if (val > (hz * 5)) 7001 val = hz * 5; 7002 7003 hdac_lock(sc); 7004 sc->poll_ival = val; 7005 hdac_unlock(sc); 7006 7007 return (err); 7008} 7009 7010static int 7011sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7012{ 7013 struct hdac_softc *sc; 7014 struct hdac_codec *codec; 7015 struct hdac_devinfo *devinfo; 7016 struct hdac_widget *w; 7017 device_t dev; 7018 uint32_t res, pincap, delay; 7019 int codec_index, fg_index; 7020 int i, err, val; 7021 nid_t cad; 7022 7023 dev = oidp->oid_arg1; 7024 sc = device_get_softc(dev); 7025 if (sc == NULL) 7026 return (EINVAL); 7027 val = 0; 7028 err = sysctl_handle_int(oidp, &val, 0, req); 7029 if (err != 0 || req->newptr == NULL || val == 0) 7030 return (err); 7031 7032 /* XXX: Temporary. For debugging. */ 7033 if (val == 100) { 7034 hdac_suspend(dev); 7035 return (0); 7036 } else if (val == 101) { 7037 hdac_resume(dev); 7038 return (0); 7039 } 7040 7041 hdac_lock(sc); 7042 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7043 codec = sc->codecs[codec_index]; 7044 if (codec == NULL) 7045 continue; 7046 cad = codec->cad; 7047 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7048 devinfo = &codec->fgs[fg_index]; 7049 if (devinfo->node_type != 7050 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7051 continue; 7052 7053 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7054 codec_index, devinfo->nid); 7055 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7056 w = hdac_widget_get(devinfo, i); 7057 if (w == NULL || w->type != 7058 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7059 continue; 7060 hdac_dump_pin_config(w, w->wclass.pin.config); 7061 pincap = w->wclass.pin.cap; 7062 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7063 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7064 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7065 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7066 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7067 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7068 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7069 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7070 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7071 delay = 0; 7072 hdac_command(sc, 7073 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7074 do { 7075 res = hdac_command(sc, 7076 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7077 if (res != 0x7fffffff && res != 0xffffffff) 7078 break; 7079 DELAY(10); 7080 } while (++delay < 10000); 7081 } else { 7082 delay = 0; 7083 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7084 w->nid), cad); 7085 } 7086 printf(" Sense: 0x%08x", res); 7087 if (delay > 0) 7088 printf(" delay %dus", delay * 10); 7089 } 7090 printf("\n"); 7091 } 7092 device_printf(dev, 7093 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7094 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7095 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7096 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7097 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7098 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7099 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7100 device_printf(dev, " GPI:"); 7101 res = hdac_command(sc, 7102 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7103 printf(" data=0x%08x", res); 7104 res = hdac_command(sc, 7105 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7106 cad); 7107 printf(" wake=0x%08x", res); 7108 res = hdac_command(sc, 7109 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7110 cad); 7111 printf(" unsol=0x%08x", res); 7112 res = hdac_command(sc, 7113 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7114 printf(" sticky=0x%08x\n", res); 7115 } 7116 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7117 device_printf(dev, " GPO:"); 7118 res = hdac_command(sc, 7119 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7120 printf(" data=0x%08x\n", res); 7121 } 7122 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7123 device_printf(dev, "GPIO:"); 7124 res = hdac_command(sc, 7125 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7126 printf(" data=0x%08x", res); 7127 res = hdac_command(sc, 7128 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7129 printf(" enable=0x%08x", res); 7130 res = hdac_command(sc, 7131 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7132 printf(" direction=0x%08x\n", res); 7133 res = hdac_command(sc, 7134 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7135 device_printf(dev, " wake=0x%08x", res); 7136 res = hdac_command(sc, 7137 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7138 cad); 7139 printf(" unsol=0x%08x", res); 7140 res = hdac_command(sc, 7141 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7142 printf(" sticky=0x%08x\n", res); 7143 } 7144 } 7145 } 7146 hdac_unlock(sc); 7147 return (0); 7148} 7149#endif 7150 7151static void 7152hdac_attach2(void *arg) 7153{ 7154 struct hdac_codec *codec; 7155 struct hdac_softc *sc; 7156 struct hdac_audio_ctl *ctl; 7157 uint32_t quirks_on, quirks_off; 7158 int codec_index, fg_index; 7159 int i, dmaalloc = 0; 7160 struct hdac_devinfo *devinfo; 7161 7162 sc = (struct hdac_softc *)arg; 7163 7164 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7165 7166 HDA_BOOTHVERBOSE( 7167 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7168 quirks_on, quirks_off); 7169 ); 7170 7171 hdac_lock(sc); 7172 7173 /* Remove ourselves from the config hooks */ 7174 if (sc->intrhook.ich_func != NULL) { 7175 config_intrhook_disestablish(&sc->intrhook); 7176 sc->intrhook.ich_func = NULL; 7177 } 7178 7179 /* Start the corb and rirb engines */ 7180 HDA_BOOTHVERBOSE( 7181 device_printf(sc->dev, "Starting CORB Engine...\n"); 7182 ); 7183 hdac_corb_start(sc); 7184 HDA_BOOTHVERBOSE( 7185 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7186 ); 7187 hdac_rirb_start(sc); 7188 7189 HDA_BOOTHVERBOSE( 7190 device_printf(sc->dev, 7191 "Enabling controller interrupt...\n"); 7192 ); 7193 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7194 HDAC_GCTL_UNSOL); 7195 if (sc->polling == 0) { 7196 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7197 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7198 } else { 7199 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7200 } 7201 DELAY(1000); 7202 7203 HDA_BOOTHVERBOSE( 7204 device_printf(sc->dev, 7205 "Scanning HDA codecs ...\n"); 7206 ); 7207 hdac_scan_codecs(sc); 7208 7209 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7210 codec = sc->codecs[codec_index]; 7211 if (codec == NULL) 7212 continue; 7213 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7214 devinfo = &codec->fgs[fg_index]; 7215 HDA_BOOTVERBOSE( 7216 device_printf(sc->dev, "\n"); 7217 device_printf(sc->dev, 7218 "Processing %s FG cad=%d nid=%d...\n", 7219 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7220 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7221 "unknown", 7222 devinfo->codec->cad, devinfo->nid); 7223 ); 7224 if (devinfo->node_type != 7225 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7226 HDA_BOOTHVERBOSE( 7227 device_printf(sc->dev, 7228 "Powering down...\n"); 7229 ); 7230 hdac_command(sc, 7231 HDA_CMD_SET_POWER_STATE(codec->cad, 7232 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7233 codec->cad); 7234 continue; 7235 } 7236 7237 HDA_BOOTHVERBOSE( 7238 device_printf(sc->dev, "Powering up...\n"); 7239 ); 7240 hdac_powerup(devinfo); 7241 HDA_BOOTHVERBOSE( 7242 device_printf(sc->dev, "Parsing audio FG...\n"); 7243 ); 7244 hdac_audio_parse(devinfo); 7245 HDA_BOOTHVERBOSE( 7246 device_printf(sc->dev, "Parsing Ctls...\n"); 7247 ); 7248 hdac_audio_ctl_parse(devinfo); 7249 HDA_BOOTHVERBOSE( 7250 device_printf(sc->dev, "Parsing vendor patch...\n"); 7251 ); 7252 hdac_vendor_patch_parse(devinfo); 7253 devinfo->function.audio.quirks |= quirks_on; 7254 devinfo->function.audio.quirks &= ~quirks_off; 7255 7256 HDA_BOOTHVERBOSE( 7257 device_printf(sc->dev, "Disabling nonaudio...\n"); 7258 ); 7259 hdac_audio_disable_nonaudio(devinfo); 7260 HDA_BOOTHVERBOSE( 7261 device_printf(sc->dev, "Disabling useless...\n"); 7262 ); 7263 hdac_audio_disable_useless(devinfo); 7264 HDA_BOOTVERBOSE( 7265 device_printf(sc->dev, "Patched pins configuration:\n"); 7266 hdac_dump_pin_configs(devinfo); 7267 ); 7268 HDA_BOOTHVERBOSE( 7269 device_printf(sc->dev, "Parsing pin associations...\n"); 7270 ); 7271 hdac_audio_as_parse(devinfo); 7272 HDA_BOOTHVERBOSE( 7273 device_printf(sc->dev, "Building AFG tree...\n"); 7274 ); 7275 hdac_audio_build_tree(devinfo); 7276 HDA_BOOTHVERBOSE( 7277 device_printf(sc->dev, "Disabling unassociated " 7278 "widgets...\n"); 7279 ); 7280 hdac_audio_disable_unas(devinfo); 7281 HDA_BOOTHVERBOSE( 7282 device_printf(sc->dev, "Disabling nonselected " 7283 "inputs...\n"); 7284 ); 7285 hdac_audio_disable_notselected(devinfo); 7286 HDA_BOOTHVERBOSE( 7287 device_printf(sc->dev, "Disabling useless...\n"); 7288 ); 7289 hdac_audio_disable_useless(devinfo); 7290 HDA_BOOTHVERBOSE( 7291 device_printf(sc->dev, "Disabling " 7292 "crossassociatement connections...\n"); 7293 ); 7294 hdac_audio_disable_crossas(devinfo); 7295 HDA_BOOTHVERBOSE( 7296 device_printf(sc->dev, "Disabling useless...\n"); 7297 ); 7298 hdac_audio_disable_useless(devinfo); 7299 HDA_BOOTHVERBOSE( 7300 device_printf(sc->dev, "Binding associations to channels...\n"); 7301 ); 7302 hdac_audio_bind_as(devinfo); 7303 HDA_BOOTHVERBOSE( 7304 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7305 ); 7306 hdac_audio_assign_names(devinfo); 7307 HDA_BOOTHVERBOSE( 7308 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7309 ); 7310 hdac_audio_assign_mixers(devinfo); 7311 HDA_BOOTHVERBOSE( 7312 device_printf(sc->dev, "Preparing pin controls...\n"); 7313 ); 7314 hdac_audio_prepare_pin_ctrl(devinfo); 7315 HDA_BOOTHVERBOSE( 7316 device_printf(sc->dev, "AFG commit...\n"); 7317 ); 7318 hdac_audio_commit(devinfo); 7319 HDA_BOOTHVERBOSE( 7320 device_printf(sc->dev, "Ctls commit...\n"); 7321 ); 7322 hdac_audio_ctl_commit(devinfo); 7323 HDA_BOOTHVERBOSE( 7324 device_printf(sc->dev, "HP switch init...\n"); 7325 ); 7326 hdac_hp_switch_init(devinfo); 7327 7328 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7329 dmaalloc == 0) { 7330 if (hdac_dma_alloc(sc, &sc->pos_dma, 7331 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7332 HDA_BOOTVERBOSE( 7333 device_printf(sc->dev, "Failed to " 7334 "allocate DMA pos buffer " 7335 "(non-fatal)\n"); 7336 ); 7337 } else 7338 dmaalloc = 1; 7339 } 7340 7341 HDA_BOOTHVERBOSE( 7342 device_printf(sc->dev, "Creating PCM devices...\n"); 7343 ); 7344 hdac_create_pcms(devinfo); 7345 7346 HDA_BOOTVERBOSE( 7347 if (devinfo->function.audio.quirks != 0) { 7348 device_printf(sc->dev, "FG config/quirks:"); 7349 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7350 if ((devinfo->function.audio.quirks & 7351 hdac_quirks_tab[i].value) == 7352 hdac_quirks_tab[i].value) 7353 printf(" %s", hdac_quirks_tab[i].key); 7354 } 7355 printf("\n"); 7356 } 7357 7358 device_printf(sc->dev, "\n"); 7359 device_printf(sc->dev, "+-------------------+\n"); 7360 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7361 device_printf(sc->dev, "+-------------------+\n"); 7362 hdac_dump_nodes(devinfo); 7363 ); 7364 7365 HDA_BOOTHVERBOSE( 7366 device_printf(sc->dev, "\n"); 7367 device_printf(sc->dev, "+------------------------+\n"); 7368 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7369 device_printf(sc->dev, "+------------------------+\n"); 7370 device_printf(sc->dev, "\n"); 7371 i = 0; 7372 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7373 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7374 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7375 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7376 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7377 ctl->index); 7378 if (ctl->childwidget != NULL) 7379 printf(" cnid %3d", ctl->childwidget->nid); 7380 else 7381 printf(" "); 7382 printf(" ossmask=0x%08x\n", 7383 ctl->ossmask); 7384 device_printf(sc->dev, 7385 " mute: %d step: %3d size: %3d off: %3d%s\n", 7386 ctl->mute, ctl->step, ctl->size, ctl->offset, 7387 (ctl->enable == 0) ? " [DISABLED]" : 7388 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7389 } 7390 ); 7391 } 7392 } 7393 hdac_unlock(sc); 7394 7395 HDA_BOOTVERBOSE( 7396 device_printf(sc->dev, "\n"); 7397 ); 7398 7399 bus_generic_attach(sc->dev); 7400 7401#ifdef SND_DYNSYSCTL 7402 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7403 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7404 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7405 sysctl_hdac_polling, "I", "Enable polling mode"); 7406 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7407 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7408 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7409 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7410 "Controller/Jack Sense polling interval (1-1000 ms)"); 7411 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7412 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7413 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7414 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7415#endif 7416} 7417 7418/**************************************************************************** 7419 * int hdac_suspend(device_t) 7420 * 7421 * Suspend and power down HDA bus and codecs. 7422 ****************************************************************************/ 7423static int 7424hdac_suspend(device_t dev) 7425{ 7426 struct hdac_softc *sc; 7427 struct hdac_codec *codec; 7428 struct hdac_devinfo *devinfo; 7429 int codec_index, fg_index, i; 7430 7431 HDA_BOOTHVERBOSE( 7432 device_printf(dev, "Suspend...\n"); 7433 ); 7434 7435 sc = device_get_softc(dev); 7436 hdac_lock(sc); 7437 7438 HDA_BOOTHVERBOSE( 7439 device_printf(dev, "Stop streams...\n"); 7440 ); 7441 for (i = 0; i < sc->num_chans; i++) { 7442 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7443 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7444 hdac_channel_stop(sc, &sc->chans[i]); 7445 } 7446 } 7447 7448 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7449 codec = sc->codecs[codec_index]; 7450 if (codec == NULL) 7451 continue; 7452 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7453 devinfo = &codec->fgs[fg_index]; 7454 HDA_BOOTHVERBOSE( 7455 device_printf(dev, 7456 "Power down FG" 7457 " cad=%d nid=%d to the D3 state...\n", 7458 codec->cad, devinfo->nid); 7459 ); 7460 hdac_command(sc, 7461 HDA_CMD_SET_POWER_STATE(codec->cad, 7462 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7463 codec->cad); 7464 } 7465 } 7466 7467 HDA_BOOTHVERBOSE( 7468 device_printf(dev, "Reset controller...\n"); 7469 ); 7470 callout_stop(&sc->poll_hda); 7471 callout_stop(&sc->poll_hdac); 7472 callout_stop(&sc->poll_jack); 7473 hdac_reset(sc, 0); 7474 hdac_unlock(sc); 7475 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7476 callout_drain(&sc->poll_hda); 7477 callout_drain(&sc->poll_hdac); 7478 callout_drain(&sc->poll_jack); 7479 7480 HDA_BOOTHVERBOSE( 7481 device_printf(dev, "Suspend done\n"); 7482 ); 7483 7484 return (0); 7485} 7486 7487/**************************************************************************** 7488 * int hdac_resume(device_t) 7489 * 7490 * Powerup and restore HDA bus and codecs state. 7491 ****************************************************************************/ 7492static int 7493hdac_resume(device_t dev) 7494{ 7495 struct hdac_softc *sc; 7496 struct hdac_codec *codec; 7497 struct hdac_devinfo *devinfo; 7498 int codec_index, fg_index, i; 7499 7500 HDA_BOOTHVERBOSE( 7501 device_printf(dev, "Resume...\n"); 7502 ); 7503 7504 sc = device_get_softc(dev); 7505 hdac_lock(sc); 7506 7507 /* Quiesce everything */ 7508 HDA_BOOTHVERBOSE( 7509 device_printf(dev, "Reset controller...\n"); 7510 ); 7511 hdac_reset(sc, 1); 7512 7513 /* Initialize the CORB and RIRB */ 7514 hdac_corb_init(sc); 7515 hdac_rirb_init(sc); 7516 7517 /* Start the corb and rirb engines */ 7518 HDA_BOOTHVERBOSE( 7519 device_printf(dev, "Starting CORB Engine...\n"); 7520 ); 7521 hdac_corb_start(sc); 7522 HDA_BOOTHVERBOSE( 7523 device_printf(dev, "Starting RIRB Engine...\n"); 7524 ); 7525 hdac_rirb_start(sc); 7526 7527 HDA_BOOTHVERBOSE( 7528 device_printf(dev, 7529 "Enabling controller interrupt...\n"); 7530 ); 7531 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7532 HDAC_GCTL_UNSOL); 7533 if (sc->polling == 0) { 7534 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7535 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7536 } else { 7537 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7538 } 7539 DELAY(1000); 7540 7541 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7542 codec = sc->codecs[codec_index]; 7543 if (codec == NULL) 7544 continue; 7545 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7546 devinfo = &codec->fgs[fg_index]; 7547 if (devinfo->node_type != 7548 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7549 HDA_BOOTHVERBOSE( 7550 device_printf(dev, 7551 "Power down unsupported non-audio FG" 7552 " cad=%d nid=%d to the D3 state...\n", 7553 codec->cad, devinfo->nid); 7554 ); 7555 hdac_command(sc, 7556 HDA_CMD_SET_POWER_STATE(codec->cad, 7557 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7558 codec->cad); 7559 continue; 7560 } 7561 7562 HDA_BOOTHVERBOSE( 7563 device_printf(dev, 7564 "Power up audio FG cad=%d nid=%d...\n", 7565 devinfo->codec->cad, devinfo->nid); 7566 ); 7567 hdac_powerup(devinfo); 7568 HDA_BOOTHVERBOSE( 7569 device_printf(dev, "AFG commit...\n"); 7570 ); 7571 hdac_audio_commit(devinfo); 7572 HDA_BOOTHVERBOSE( 7573 device_printf(dev, "Ctls commit...\n"); 7574 ); 7575 hdac_audio_ctl_commit(devinfo); 7576 HDA_BOOTHVERBOSE( 7577 device_printf(dev, "HP switch init...\n"); 7578 ); 7579 hdac_hp_switch_init(devinfo); 7580 7581 hdac_unlock(sc); 7582 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7583 struct hdac_pcm_devinfo *pdevinfo = 7584 &devinfo->function.audio.devs[i]; 7585 HDA_BOOTHVERBOSE( 7586 device_printf(pdevinfo->dev, 7587 "OSS mixer reinitialization...\n"); 7588 ); 7589 if (mixer_reinit(pdevinfo->dev) == -1) 7590 device_printf(pdevinfo->dev, 7591 "unable to reinitialize the mixer\n"); 7592 } 7593 hdac_lock(sc); 7594 } 7595 } 7596 7597 HDA_BOOTHVERBOSE( 7598 device_printf(dev, "Start streams...\n"); 7599 ); 7600 for (i = 0; i < sc->num_chans; i++) { 7601 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7602 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7603 hdac_channel_start(sc, &sc->chans[i]); 7604 } 7605 } 7606 7607 hdac_unlock(sc); 7608 7609 HDA_BOOTHVERBOSE( 7610 device_printf(dev, "Resume done\n"); 7611 ); 7612 7613 return (0); 7614} 7615/**************************************************************************** 7616 * int hdac_detach(device_t) 7617 * 7618 * Detach and free up resources utilized by the hdac device. 7619 ****************************************************************************/ 7620static int 7621hdac_detach(device_t dev) 7622{ 7623 struct hdac_softc *sc; 7624 device_t *devlist; 7625 int i, devcount, error; 7626 7627 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7628 return (error); 7629 for (i = 0; i < devcount; i++) { 7630 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7631 free(devlist, M_TEMP); 7632 return (error); 7633 } 7634 } 7635 free(devlist, M_TEMP); 7636 7637 sc = device_get_softc(dev); 7638 hdac_release_resources(sc); 7639 7640 return (0); 7641} 7642 7643static int 7644hdac_print_child(device_t dev, device_t child) 7645{ 7646 struct hdac_pcm_devinfo *pdevinfo = 7647 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7648 int retval; 7649 7650 retval = bus_print_child_header(dev, child); 7651 retval += printf(" at cad %d nid %d", 7652 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7653 retval += bus_print_child_footer(dev, child); 7654 7655 return (retval); 7656} 7657 7658static device_method_t hdac_methods[] = { 7659 /* device interface */ 7660 DEVMETHOD(device_probe, hdac_probe), 7661 DEVMETHOD(device_attach, hdac_attach), 7662 DEVMETHOD(device_detach, hdac_detach), 7663 DEVMETHOD(device_suspend, hdac_suspend), 7664 DEVMETHOD(device_resume, hdac_resume), 7665 /* Bus interface */ 7666 DEVMETHOD(bus_print_child, hdac_print_child), 7667 { 0, 0 } 7668}; 7669 7670static driver_t hdac_driver = { 7671 "hdac", 7672 hdac_methods, 7673 sizeof(struct hdac_softc), 7674}; 7675 7676static devclass_t hdac_devclass; 7677 7678DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7679MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7680MODULE_VERSION(snd_hda, 1); 7681 7682static int 7683hdac_pcm_probe(device_t dev) 7684{ 7685 struct hdac_pcm_devinfo *pdevinfo = 7686 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7687 char buf[128]; 7688 7689 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7690 hdac_codec_name(pdevinfo->devinfo->codec), 7691 pdevinfo->index, 7692 pdevinfo->digital?"Digital":"Analog"); 7693 device_set_desc_copy(dev, buf); 7694 return (0); 7695} 7696 7697static int 7698hdac_pcm_attach(device_t dev) 7699{ 7700 struct hdac_pcm_devinfo *pdevinfo = 7701 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7702 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7703 char status[SND_STATUSLEN]; 7704 int i; 7705 7706 pdevinfo->chan_size = pcm_getbuffersize(dev, 7707 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7708 7709 HDA_BOOTVERBOSE( 7710 device_printf(dev, "+--------------------------------------+\n"); 7711 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7712 device_printf(dev, "+--------------------------------------+\n"); 7713 hdac_dump_pcmchannels(pdevinfo); 7714 device_printf(dev, "\n"); 7715 device_printf(dev, "+--------------------------------+\n"); 7716 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7717 device_printf(dev, "+--------------------------------+\n"); 7718 hdac_dump_dac(pdevinfo); 7719 hdac_dump_adc(pdevinfo); 7720 hdac_dump_mix(pdevinfo); 7721 device_printf(dev, "\n"); 7722 device_printf(dev, "+-------------------------+\n"); 7723 device_printf(dev, "| DUMPING Volume Controls |\n"); 7724 device_printf(dev, "+-------------------------+\n"); 7725 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7726 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7727 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7728 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7729 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7730 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7731 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7732 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7733 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7734 hdac_dump_ctls(pdevinfo, NULL, 0); 7735 device_printf(dev, "\n"); 7736 ); 7737 7738 if (resource_int_value(device_get_name(dev), 7739 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7740 i &= HDA_BLK_ALIGN; 7741 if (i < HDA_BLK_MIN) 7742 i = HDA_BLK_MIN; 7743 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7744 i = 0; 7745 while (pdevinfo->chan_blkcnt >> i) 7746 i++; 7747 pdevinfo->chan_blkcnt = 1 << (i - 1); 7748 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7749 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7750 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7751 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7752 } else 7753 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7754 7755 /* 7756 * We don't register interrupt handler with snd_setup_intr 7757 * in pcm device. Mark pcm device as MPSAFE manually. 7758 */ 7759 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7760 7761 HDA_BOOTHVERBOSE( 7762 device_printf(dev, "OSS mixer initialization...\n"); 7763 ); 7764 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7765 device_printf(dev, "Can't register mixer\n"); 7766 7767 HDA_BOOTHVERBOSE( 7768 device_printf(dev, "Registering PCM channels...\n"); 7769 ); 7770 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7771 (pdevinfo->rec >= 0)?1:0) != 0) 7772 device_printf(dev, "Can't register PCM\n"); 7773 7774 pdevinfo->registered++; 7775 7776 if (pdevinfo->play >= 0) 7777 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7778 if (pdevinfo->rec >= 0) 7779 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7780 7781 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7782 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7783 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7784 pcm_setstatus(dev, status); 7785 7786 return (0); 7787} 7788 7789static int 7790hdac_pcm_detach(device_t dev) 7791{ 7792 struct hdac_pcm_devinfo *pdevinfo = 7793 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7794 int err; 7795 7796 if (pdevinfo->registered > 0) { 7797 err = pcm_unregister(dev); 7798 if (err != 0) 7799 return (err); 7800 } 7801 7802 return (0); 7803} 7804 7805static device_method_t hdac_pcm_methods[] = { 7806 /* device interface */ 7807 DEVMETHOD(device_probe, hdac_pcm_probe), 7808 DEVMETHOD(device_attach, hdac_pcm_attach), 7809 DEVMETHOD(device_detach, hdac_pcm_detach), 7810 { 0, 0 } 7811}; 7812 7813static driver_t hdac_pcm_driver = { 7814 "pcm", 7815 hdac_pcm_methods, 7816 PCM_SOFTC_SIZE, 7817}; 7818 7819DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7820 7821