hdac.c revision 185230
160573Skris/*- 292555Sdes * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 360573Skris * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 460573Skris * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 560573Skris * All rights reserved. 660573Skris * 760573Skris * Redistribution and use in source and binary forms, with or without 860573Skris * modification, are permitted provided that the following conditions 960573Skris * are met: 1060573Skris * 1. Redistributions of source code must retain the above copyright 1160573Skris * notice, this list of conditions and the following disclaimer. 1260573Skris * 2. Redistributions in binary form must reproduce the above copyright 1360573Skris * notice, this list of conditions and the following disclaimer in the 1460573Skris * documentation and/or other materials provided with the distribution. 1560573Skris * 1660573Skris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1760573Skris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1860573Skris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1960573Skris * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2060573Skris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2160573Skris * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2260573Skris * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2360573Skris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2460573Skris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2560573Skris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26149749Sdes * SUCH DAMAGE. 2760573Skris */ 2876259Sgreen 2976259Sgreen/* 3060573Skris * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 3160573Skris * that this driver still in its early stage, and possible of rewrite are 3260573Skris * pretty much guaranteed. There are supposedly several distinct parent/child 3360573Skris * busses to make this "perfect", but as for now and for the sake of 3461209Skris * simplicity, everything is gobble up within single source. 3560573Skris * 3676259Sgreen * List of subsys: 3760573Skris * 1) HDA Controller support 3876259Sgreen * 2) HDA Codecs support, which may include 3976259Sgreen * - HDA 4076259Sgreen * - Modem 4176259Sgreen * - HDMI 4276259Sgreen * 3) Widget parser - the real magic of why this driver works on so 4398675Sdes * many hardwares with minimal vendor specific quirk. The original 4460573Skris * parser was written using Ruby and can be found at 4561209Skris * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 4661209Skris * ruby parser take the verbose dmesg dump as its input. Refer to 4792555Sdes * http://www.microsoft.com/whdc/device/audio/default.mspx for various 4892555Sdes * interesting documents, especially UAA (Universal Audio Architecture). 4992555Sdes * 4) Possible vendor specific support. 5076259Sgreen * (snd_hda_intel, snd_hda_ati, etc..) 5176259Sgreen * 5292555Sdes * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 5376259Sgreen * Compaq V3000 with Conexant HDA. 5460573Skris * 55149749Sdes * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 5676259Sgreen * * * 5776259Sgreen * * This driver is a collaborative effort made by: * 5898675Sdes * * * 5998675Sdes * * Stephane E. Potvin <sepotvin@videotron.ca> * 6098675Sdes * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 6198675Sdes * * Wesley Morgan <morganw@chemikals.org> * 6298675Sdes * * Daniel Eischen <deischen@FreeBSD.org> * 6398675Sdes * * Maxime Guillaud <bsd-ports@mguillaud.net> * 6460573Skris * * Ariff Abdullah <ariff@FreeBSD.org> * 6576259Sgreen * * Alexander Motin <mav@FreeBSD.org> * 6676259Sgreen * * * 6776259Sgreen * * ....and various people from freebsd-multimedia@FreeBSD.org * 6860573Skris * * * 6960573Skris * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 7076259Sgreen */ 7192555Sdes 72113908Sdes#include <dev/sound/pcm/sound.h> 7361209Skris#include <dev/pci/pcireg.h> 7476259Sgreen#include <dev/pci/pcivar.h> 7561209Skris 7676259Sgreen#include <sys/ctype.h> 7761209Skris#include <sys/taskqueue.h> 7876259Sgreen 7961209Skris#include <dev/sound/pci/hda/hdac_private.h> 8076259Sgreen#include <dev/sound/pci/hda/hdac_reg.h> 8176259Sgreen#include <dev/sound/pci/hda/hda_reg.h> 8261209Skris#include <dev/sound/pci/hda/hdac.h> 8361209Skris 8476259Sgreen#include "mixer_if.h" 8561209Skris 8661209Skris#define HDA_DRV_TEST_REV "20081123_0118" 8776259Sgreen 8876259SgreenSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 185230 2008-11-23 20:19:35Z mav $"); 8961209Skris 9076259Sgreen#define HDA_BOOTVERBOSE(stmt) do { \ 9176259Sgreen if (bootverbose != 0 || snd_verbose > 3) { \ 92113908Sdes stmt \ 93113908Sdes } \ 9476259Sgreen} while(0) 9576259Sgreen 9676259Sgreen#define HDA_BOOTHVERBOSE(stmt) do { \ 9776259Sgreen if (snd_verbose > 3) { \ 9876259Sgreen stmt \ 9961209Skris } \ 10061209Skris} while(0) 10192555Sdes 10276259Sgreen#if 1 10360573Skris#undef HDAC_INTR_EXTRA 104149749Sdes#define HDAC_INTR_EXTRA 1 10560573Skris#endif 10676259Sgreen 10776259Sgreen#define hdac_lock(sc) snd_mtxlock((sc)->lock) 10876259Sgreen#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 10960573Skris#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 11060573Skris#define hdac_lockowned(sc) mtx_owned((sc)->lock) 11192555Sdes 11292555Sdes#undef HDAC_MSI_ENABLED 11360573Skris#if __FreeBSD_version >= 700026 || \ 11492555Sdes (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 11560573Skris#define HDAC_MSI_ENABLED 1 11660573Skris#endif 11792555Sdes 11892555Sdes#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 11969587Sgreen#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 12092555Sdes (fl) == 0xffffffff || \ 12192555Sdes (((fl) & 0xffff0000) == 0xffff0000 && \ 12292555Sdes ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 12369587Sgreen (((fl) & 0x0000ffff) == 0x0000ffff && \ 12469587Sgreen ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 12576259Sgreen#define HDA_MATCH_ALL 0xffffffff 12676259Sgreen#define HDAC_INVALID 0xffffffff 12769587Sgreen 12892555Sdes/* Default controller / jack sense poll: 250ms */ 12969587Sgreen#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 13076259Sgreen 13176259Sgreen/* 13276259Sgreen * Make room for possible 4096 playback/record channels, in 100 years to come. 13376259Sgreen */ 13469587Sgreen#define HDAC_TRIGGER_NONE 0x00000000 135113908Sdes#define HDAC_TRIGGER_PLAY 0x00000fff 13692555Sdes#define HDAC_TRIGGER_REC 0x00fff000 13792555Sdes#define HDAC_TRIGGER_UNSOL 0x80000000 13876259Sgreen 13969587Sgreen#define HDA_MODEL_CONSTRUCT(vendor, model) \ 14076259Sgreen (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 14176259Sgreen 14276259Sgreen/* Controller models */ 14376259Sgreen 14476259Sgreen/* Intel */ 14576259Sgreen#define INTEL_VENDORID 0x8086 14669587Sgreen#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 14769587Sgreen#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 14860573Skris#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 14976259Sgreen#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 15060573Skris#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151137015Sdes#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 15298675Sdes#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153149749Sdes#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 15498675Sdes 15576259Sgreen/* Nvidia */ 15676259Sgreen#define NVIDIA_VENDORID 0x10de 15776259Sgreen#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 15860573Skris#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 15976259Sgreen#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 16076259Sgreen#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 16176259Sgreen#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 16276259Sgreen#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 16376259Sgreen#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 16498675Sdes#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 16598675Sdes#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 16698675Sdes 16798675Sdes/* ATI */ 16898675Sdes#define ATI_VENDORID 0x1002 16998675Sdes#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 17098675Sdes#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 171137015Sdes#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 172137015Sdes 173137015Sdes/* VIA */ 17498675Sdes#define VIA_VENDORID 0x1106 17576259Sgreen#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 17676259Sgreen#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 17776259Sgreen 17876259Sgreen/* SiS */ 17976259Sgreen#define SIS_VENDORID 0x1039 18060573Skris#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 18160573Skris#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 18276259Sgreen 18392555Sdes/* OEM/subvendors */ 18460573Skris 18576259Sgreen/* Intel */ 186149749Sdes#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 18776259Sgreen 18860573Skris/* HP/Compaq */ 18976259Sgreen#define HP_VENDORID 0x103c 19076259Sgreen#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 19176259Sgreen#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 19260573Skris#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 19376259Sgreen#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 19476259Sgreen#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 19560573Skris#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 19676259Sgreen#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 19776259Sgreen#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 19876259Sgreen#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 19976259Sgreen#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 20076259Sgreen/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 20199060Sdes#define HP_NX6325_SUBVENDORX 0x103c30b0 20299060Sdes 20392555Sdes/* Dell */ 20460573Skris#define DELL_VENDORID 0x1028 20576259Sgreen#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 20660573Skris#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 20760573Skris#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 20876259Sgreen#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 20976259Sgreen#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 21069587Sgreen#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 21176259Sgreen#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 21269587Sgreen#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 21376259Sgreen 21476259Sgreen/* Clevo */ 21576259Sgreen#define CLEVO_VENDORID 0x1558 21676259Sgreen#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 21776259Sgreen#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 21876259Sgreen 21969587Sgreen/* Acer */ 22076259Sgreen#define ACER_VENDORID 0x1025 22192555Sdes#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 22269587Sgreen#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 22376259Sgreen#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 22469587Sgreen#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 22569587Sgreen#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 22692555Sdes#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 22776259Sgreen#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 22860573Skris 22976259Sgreen/* Asus */ 23076259Sgreen#define ASUS_VENDORID 0x1043 23160573Skris#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 23276259Sgreen#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 23360573Skris#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 234113908Sdes#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 235113908Sdes#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 236113908Sdes#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 237113908Sdes#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 23876259Sgreen#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 23960573Skris#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 24060573Skris#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 24160573Skris#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 24292555Sdes#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 24360573Skris#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 24460573Skris#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 24576259Sgreen#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 24660573Skris#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 24760573Skris 24892555Sdes/* IBM / Lenovo */ 24969587Sgreen#define IBM_VENDORID 0x1014 25060573Skris#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 25160573Skris#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 25260573Skris 25360573Skris/* Lenovo */ 25492555Sdes#define LENOVO_VENDORID 0x17aa 25592555Sdes#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 25660573Skris#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 25792555Sdes#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 25860573Skris#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 25960573Skris 26076259Sgreen/* Samsung */ 26160573Skris#define SAMSUNG_VENDORID 0x144d 26260573Skris#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 26376259Sgreen#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 26460573Skris 26576259Sgreen/* Medion ? */ 26676259Sgreen#define MEDION_VENDORID 0x161f 26776259Sgreen#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 26860573Skris#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 26960573Skris 27060573Skris/* Apple Computer Inc. */ 27160573Skris#define APPLE_VENDORID 0x106b 27292555Sdes#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 27360573Skris 27460573Skris/* Sony */ 27576259Sgreen#define SONY_VENDORID 0x104d 27660573Skris#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 27760573Skris#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 278149749Sdes 279149749Sdes/* 280149749Sdes * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 281149749Sdes * instead of their own, which is beyond my comprehension 28260573Skris * (see HDA_CODEC_STAC9221 below). 283149749Sdes */ 28460573Skris#define APPLE_INTEL_MAC 0x76808384 28560573Skris 28660573Skris/* LG Electronics */ 28760573Skris#define LG_VENDORID 0x1854 28860573Skris#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 28992555Sdes#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 29060573Skris 29160573Skris/* Fujitsu Siemens */ 29276259Sgreen#define FS_VENDORID 0x1734 29360573Skris#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 29460573Skris#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 29569587Sgreen#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 296113908Sdes 297137015Sdes/* Fujitsu Limited */ 298137015Sdes#define FL_VENDORID 0x10cf 29969587Sgreen#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 300113908Sdes#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 30169587Sgreen#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 30260573Skris 30360573Skris/* Toshiba */ 30492555Sdes#define TOSHIBA_VENDORID 0x1179 30560573Skris#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 30660573Skris#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 30776259Sgreen#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 30876259Sgreen 30960573Skris/* Micro-Star International (MSI) */ 31076259Sgreen#define MSI_VENDORID 0x1462 31176259Sgreen#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 31276259Sgreen#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 31376259Sgreen#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 31460573Skris 31560573Skris/* Giga-Byte Technology */ 316126274Sdes#define GB_VENDORID 0x1458 317113908Sdes#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 318113908Sdes#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 319113908Sdes 320113908Sdes/* Uniwill ? */ 321113908Sdes#define UNIWILL_VENDORID 0x1584 322113908Sdes#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 323113908Sdes#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 324113908Sdes 325113908Sdes 326113908Sdes/* Misc constants.. */ 327113908Sdes#define HDA_AMP_VOL_DEFAULT (-1) 328113908Sdes#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 329113908Sdes#define HDA_AMP_MUTE_NONE (0) 330113908Sdes#define HDA_AMP_MUTE_LEFT (1 << 0) 331113908Sdes#define HDA_AMP_MUTE_RIGHT (1 << 1) 332113908Sdes#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 333113908Sdes 334113908Sdes#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 335113908Sdes#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 336113908Sdes 337113908Sdes#define HDA_ADC_MONITOR (1 << 0) 338113908Sdes 339113908Sdes#define HDA_CTL_OUT 1 34092555Sdes#define HDA_CTL_IN 2 34176259Sgreen 34260573Skris#define HDA_GPIO_MAX 8 34376259Sgreen/* 0 - 7 = GPIO , 8 = Flush */ 34476259Sgreen#define HDA_QUIRK_GPIO0 (1 << 0) 34576259Sgreen#define HDA_QUIRK_GPIO1 (1 << 1) 34676259Sgreen#define HDA_QUIRK_GPIO2 (1 << 2) 347149749Sdes#define HDA_QUIRK_GPIO3 (1 << 3) 348113908Sdes#define HDA_QUIRK_GPIO4 (1 << 4) 34960573Skris#define HDA_QUIRK_GPIO5 (1 << 5) 350113908Sdes#define HDA_QUIRK_GPIO6 (1 << 6) 351113908Sdes#define HDA_QUIRK_GPIO7 (1 << 7) 35260573Skris#define HDA_QUIRK_GPIOFLUSH (1 << 8) 35376259Sgreen 35476259Sgreen/* 9 - 25 = anything else */ 35576259Sgreen#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 35676259Sgreen#define HDA_QUIRK_FIXEDRATE (1 << 10) 35776259Sgreen#define HDA_QUIRK_FORCESTEREO (1 << 11) 35876259Sgreen#define HDA_QUIRK_EAPDINV (1 << 12) 35976259Sgreen#define HDA_QUIRK_DMAPOS (1 << 13) 36076259Sgreen#define HDA_QUIRK_SENSEINV (1 << 14) 36176259Sgreen 36260573Skris/* 26 - 31 = vrefs */ 36376259Sgreen#define HDA_QUIRK_IVREF50 (1 << 26) 36476259Sgreen#define HDA_QUIRK_IVREF80 (1 << 27) 36576259Sgreen#define HDA_QUIRK_IVREF100 (1 << 28) 36676259Sgreen#define HDA_QUIRK_OVREF50 (1 << 29) 36760573Skris#define HDA_QUIRK_OVREF80 (1 << 30) 36860573Skris#define HDA_QUIRK_OVREF100 (1 << 31) 36960573Skris 37076259Sgreen#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 37176259Sgreen HDA_QUIRK_IVREF100) 37276259Sgreen#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 37360573Skris HDA_QUIRK_OVREF100) 37460573Skris#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 37576259Sgreen 37676259Sgreen#if __FreeBSD_version < 600000 37776259Sgreen#define taskqueue_drain(...) 37860573Skris#endif 37976259Sgreen 38076259Sgreenstatic const struct { 38160573Skris char *key; 38260573Skris uint32_t value; 38360573Skris} hdac_quirks_tab[] = { 38476259Sgreen { "gpio0", HDA_QUIRK_GPIO0 }, 38592555Sdes { "gpio1", HDA_QUIRK_GPIO1 }, 38692555Sdes { "gpio2", HDA_QUIRK_GPIO2 }, 38792555Sdes { "gpio3", HDA_QUIRK_GPIO3 }, 38892555Sdes { "gpio4", HDA_QUIRK_GPIO4 }, 38976259Sgreen { "gpio5", HDA_QUIRK_GPIO5 }, 39076259Sgreen { "gpio6", HDA_QUIRK_GPIO6 }, 39160573Skris { "gpio7", HDA_QUIRK_GPIO7 }, 39261209Skris { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 39376259Sgreen { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 39476259Sgreen { "fixedrate", HDA_QUIRK_FIXEDRATE }, 395113908Sdes { "forcestereo", HDA_QUIRK_FORCESTEREO }, 396126274Sdes { "eapdinv", HDA_QUIRK_EAPDINV }, 397149749Sdes { "dmapos", HDA_QUIRK_DMAPOS }, 398113908Sdes { "senseinv", HDA_QUIRK_SENSEINV }, 399113908Sdes { "ivref50", HDA_QUIRK_IVREF50 }, 400113908Sdes { "ivref80", HDA_QUIRK_IVREF80 }, 401113908Sdes { "ivref100", HDA_QUIRK_IVREF100 }, 40276259Sgreen { "ovref50", HDA_QUIRK_OVREF50 }, 40376259Sgreen { "ovref80", HDA_QUIRK_OVREF80 }, 40460573Skris { "ovref100", HDA_QUIRK_OVREF100 }, 40560573Skris { "ivref", HDA_QUIRK_IVREF }, 40692555Sdes { "ovref", HDA_QUIRK_OVREF }, 407149749Sdes { "vref", HDA_QUIRK_VREF }, 40860573Skris}; 40976259Sgreen#define HDAC_QUIRKS_TAB_LEN \ 41092555Sdes (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 41176259Sgreen 41276259Sgreen#define HDA_BDL_MIN 2 413149749Sdes#define HDA_BDL_MAX 256 41492555Sdes#define HDA_BDL_DEFAULT HDA_BDL_MIN 415149749Sdes 41660573Skris#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 417149749Sdes#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 418149749Sdes 419149749Sdes#define HDA_BUFSZ_MIN 4096 420149749Sdes#define HDA_BUFSZ_MAX 65536 42176259Sgreen#define HDA_BUFSZ_DEFAULT 16384 42276259Sgreen 42376259Sgreen#define HDA_PARSE_MAXDEPTH 10 42476259Sgreen 42576259Sgreen#define HDAC_UNSOLTAG_EVENT_HP 0x00 42692555Sdes 42792555SdesMALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 42876259Sgreen 42976259Sgreenconst char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 43076259Sgreen "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 43176259Sgreen "White", "Other"}; 43276259Sgreen 43376259Sgreenconst char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 43476259Sgreen "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 43576259Sgreen "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 43676259Sgreen 43776259Sgreenconst char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 43876259Sgreen 43976259Sgreen/* Default */ 44092555Sdesstatic uint32_t hdac_fmt[] = { 44192555Sdes AFMT_STEREO | AFMT_S16_LE, 44276259Sgreen 0 44376259Sgreen}; 44476259Sgreen 44576259Sgreenstatic struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 44676259Sgreen 44776259Sgreenstatic const struct { 44876259Sgreen uint32_t model; 44976259Sgreen char *desc; 45076259Sgreen} hdac_devices[] = { 45176259Sgreen { HDA_INTEL_82801F, "Intel 82801F" }, 45276259Sgreen { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 45376259Sgreen { HDA_INTEL_82801G, "Intel 82801G" }, 45476259Sgreen { HDA_INTEL_82801H, "Intel 82801H" }, 45576259Sgreen { HDA_INTEL_82801I, "Intel 82801I" }, 45676259Sgreen { HDA_INTEL_82801J, "Intel 82801J" }, 45776259Sgreen { HDA_INTEL_SCH, "Intel SCH" }, 45876259Sgreen { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 45976259Sgreen { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 46076259Sgreen { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 461149749Sdes { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 46276259Sgreen { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 46360573Skris { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 46476259Sgreen { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 46560573Skris { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 466113908Sdes { HDA_ATI_SB450, "ATI SB450" }, 46760573Skris { HDA_ATI_SB600, "ATI SB600" }, 46876259Sgreen { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 46976259Sgreen { HDA_SIS_966, "SiS 966" }, 47076259Sgreen /* Unknown */ 47176259Sgreen { HDA_INTEL_ALL, "Intel (Unknown)" }, 47276259Sgreen { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 47376259Sgreen { HDA_ATI_ALL, "ATI (Unknown)" }, 47460573Skris { HDA_VIA_ALL, "VIA (Unknown)" }, 47560573Skris { HDA_SIS_ALL, "SiS (Unknown)" }, 47676259Sgreen}; 47776259Sgreen#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 47876259Sgreen 47976259Sgreenstatic const struct { 48076259Sgreen uint16_t vendor; 48176259Sgreen uint8_t reg; 48276259Sgreen uint8_t mask; 48376259Sgreen uint8_t enable; 48476259Sgreen} hdac_pcie_snoop[] = { 48576259Sgreen { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 48676259Sgreen { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 487137015Sdes { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 488137015Sdes}; 489137015Sdes#define HDAC_PCIESNOOP_LEN \ 490137015Sdes (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 491137015Sdes 492137015Sdesstatic const struct { 493137015Sdes uint32_t rate; 494137015Sdes int valid; 495137015Sdes uint16_t base; 496137015Sdes uint16_t mul; 497137015Sdes uint16_t div; 498137015Sdes} hda_rate_tab[] = { 499149749Sdes { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 500137015Sdes { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 501137015Sdes { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 502137015Sdes { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 503137015Sdes { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 504137015Sdes { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 505149749Sdes { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 506137015Sdes { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 507137015Sdes { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 508137015Sdes { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 509137015Sdes { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 510137015Sdes { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 511137015Sdes { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 512137015Sdes { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 513137015Sdes { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 514137015Sdes { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 515137015Sdes { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 516137015Sdes { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 517137015Sdes { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 518137015Sdes { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 519137015Sdes { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 52076259Sgreen { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 52176259Sgreen { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 52276259Sgreen { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 52376259Sgreen { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 524149749Sdes { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 52576259Sgreen { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 52676259Sgreen { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 52792555Sdes { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 52876259Sgreen { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 52976259Sgreen { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 53076259Sgreen { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 53176259Sgreen { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 53276259Sgreen { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 53376259Sgreen { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 53476259Sgreen}; 53576259Sgreen#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 53676259Sgreen 537/* All codecs you can eat... */ 538#define HDA_CODEC_CONSTRUCT(vendor, id) \ 539 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 540 541/* Realtek */ 542#define REALTEK_VENDORID 0x10ec 543#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 544#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 545#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 546#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 547#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 548#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 549#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 550#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 551#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 552#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 553#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 554#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 555#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 556#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 557#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 558#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 559#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 560#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 561 562/* Analog Devices */ 563#define ANALOGDEVICES_VENDORID 0x11d4 564#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 565#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 566#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 567#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 568#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 569#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 570#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 571 572/* CMedia */ 573#define CMEDIA_VENDORID 0x434d 574#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 575#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 576 577/* Sigmatel */ 578#define SIGMATEL_VENDORID 0x8384 579#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 580#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 581#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 582#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 583#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 584#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 585#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 586#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 587#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 588#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 589#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 590#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 591#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 592#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 593#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 594#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 595#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 596#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 597#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 598#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 599#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 600#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 601#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 602#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 603#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 604#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 605#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 606#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 607#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 608#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 609#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 610#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 611#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 612#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 613#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 614#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 615#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 616#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 617#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 618#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 619 620/* IDT */ 621#define IDT_VENDORID 0x111d 622#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 623#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 624#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 625#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 626#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 627#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 628#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 629#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 630#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 631#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 632#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 633#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 634#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 635 636/* Silicon Image */ 637#define SII_VENDORID 0x1095 638#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 639 640/* Lucent/Agere */ 641#define AGERE_VENDORID 0x11c1 642#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 643 644/* 645 * Conexant 646 * 647 * Ok, the truth is, I don't have any idea at all whether 648 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 649 * place that tell me it is "Venice" is from its Windows driver INF. 650 * 651 * Venice - CX????? 652 * Waikiki - CX20551-22 653 */ 654#define CONEXANT_VENDORID 0x14f1 655#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 656#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 657#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 658 659/* VIA */ 660#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 661#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 662#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 663#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 664#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 665#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 666#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 667#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 668#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 669#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 670#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 671#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 672#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 673 674/* ATI */ 675#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 676 677/* NVIDIA */ 678#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 679 680/* INTEL */ 681#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 682 683/* Codecs */ 684static const struct { 685 uint32_t id; 686 char *name; 687} hdac_codecs[] = { 688 { HDA_CODEC_ALC260, "Realtek ALC260" }, 689 { HDA_CODEC_ALC262, "Realtek ALC262" }, 690 { HDA_CODEC_ALC267, "Realtek ALC267" }, 691 { HDA_CODEC_ALC268, "Realtek ALC268" }, 692 { HDA_CODEC_ALC269, "Realtek ALC269" }, 693 { HDA_CODEC_ALC272, "Realtek ALC272" }, 694 { HDA_CODEC_ALC660, "Realtek ALC660" }, 695 { HDA_CODEC_ALC662, "Realtek ALC662" }, 696 { HDA_CODEC_ALC663, "Realtek ALC663" }, 697 { HDA_CODEC_ALC861, "Realtek ALC861" }, 698 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 699 { HDA_CODEC_ALC880, "Realtek ALC880" }, 700 { HDA_CODEC_ALC882, "Realtek ALC882" }, 701 { HDA_CODEC_ALC883, "Realtek ALC883" }, 702 { HDA_CODEC_ALC885, "Realtek ALC885" }, 703 { HDA_CODEC_ALC888, "Realtek ALC888" }, 704 { HDA_CODEC_ALC889, "Realtek ALC889" }, 705 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 706 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 707 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 708 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 709 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 710 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 711 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 712 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 713 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 714 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 715 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 716 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 717 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 718 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 719 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 720 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 721 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 722 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 723 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 724 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 725 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 726 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 727 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 728 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 729 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 730 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 731 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 732 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 733 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 734 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 735 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 736 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 737 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 738 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 739 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 740 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 741 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 742 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 743 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 744 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 745 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 746 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 747 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 748 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 749 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 750 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 751 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 752 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 753 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 754 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 755 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 756 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 757 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 758 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 759 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 760 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 761 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 762 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 763 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 764 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 765 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 766 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 767 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 768 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 769 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 770 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 771 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 772 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 773 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 774 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 775 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 776 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 777 /* Unknown codec */ 778 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 779 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 780 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 781 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 782 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 783 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 784 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 785 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 786 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 787 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 788 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 789 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 790}; 791#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 792 793 794/**************************************************************************** 795 * Function prototypes 796 ****************************************************************************/ 797static void hdac_intr_handler(void *); 798static int hdac_reset(struct hdac_softc *, int); 799static int hdac_get_capabilities(struct hdac_softc *); 800static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 801static int hdac_dma_alloc(struct hdac_softc *, 802 struct hdac_dma *, bus_size_t); 803static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 804static int hdac_mem_alloc(struct hdac_softc *); 805static void hdac_mem_free(struct hdac_softc *); 806static int hdac_irq_alloc(struct hdac_softc *); 807static void hdac_irq_free(struct hdac_softc *); 808static void hdac_corb_init(struct hdac_softc *); 809static void hdac_rirb_init(struct hdac_softc *); 810static void hdac_corb_start(struct hdac_softc *); 811static void hdac_rirb_start(struct hdac_softc *); 812static void hdac_scan_codecs(struct hdac_softc *); 813static void hdac_probe_codec(struct hdac_codec *); 814static void hdac_probe_function(struct hdac_codec *, nid_t); 815static int hdac_pcmchannel_setup(struct hdac_chan *); 816 817static void hdac_attach2(void *); 818 819static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 820 uint32_t, int); 821static void hdac_command_send_internal(struct hdac_softc *, 822 struct hdac_command_list *, int); 823 824static int hdac_probe(device_t); 825static int hdac_attach(device_t); 826static int hdac_detach(device_t); 827static int hdac_suspend(device_t); 828static int hdac_resume(device_t); 829static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 830static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 831 uint32_t, int, int); 832static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 833 nid_t, int, int, int); 834static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 835 nid_t, nid_t, int, int, int, int, int, int); 836static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 837 838static int hdac_rirb_flush(struct hdac_softc *sc); 839static int hdac_unsolq_flush(struct hdac_softc *sc); 840 841static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 842 843#define hdac_command(a1, a2, a3) \ 844 hdac_command_sendone_internal(a1, a2, a3) 845 846#define hdac_codec_id(c) \ 847 ((uint32_t)((c == NULL) ? 0x00000000 : \ 848 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 849 ((uint32_t)(c)->device_id & 0x0000ffff)))) 850 851static char * 852hdac_codec_name(struct hdac_codec *codec) 853{ 854 uint32_t id; 855 int i; 856 857 id = hdac_codec_id(codec); 858 859 for (i = 0; i < HDAC_CODECS_LEN; i++) { 860 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 861 return (hdac_codecs[i].name); 862 } 863 864 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 865} 866 867static char * 868hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 869{ 870 static char *ossname[] = SOUND_DEVICE_NAMES; 871 int i, first = 1; 872 873 bzero(buf, len); 874 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 875 if (mask & (1 << i)) { 876 if (first == 0) 877 strlcat(buf, ", ", len); 878 strlcat(buf, ossname[i], len); 879 first = 0; 880 } 881 } 882 return (buf); 883} 884 885static struct hdac_audio_ctl * 886hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 887{ 888 if (devinfo == NULL || 889 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 890 index == NULL || devinfo->function.audio.ctl == NULL || 891 devinfo->function.audio.ctlcnt < 1 || 892 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 893 return (NULL); 894 return (&devinfo->function.audio.ctl[(*index)++]); 895} 896 897static struct hdac_audio_ctl * 898hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 899 int index, int cnt) 900{ 901 struct hdac_audio_ctl *ctl; 902 int i, found = 0; 903 904 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 905 return (NULL); 906 907 i = 0; 908 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 909 if (ctl->enable == 0) 910 continue; 911 if (ctl->widget->nid != nid) 912 continue; 913 if (dir && ctl->ndir != dir) 914 continue; 915 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 916 ctl->dir == ctl->ndir && ctl->index != index) 917 continue; 918 found++; 919 if (found == cnt || cnt <= 0) 920 return (ctl); 921 } 922 923 return (NULL); 924} 925 926/* 927 * Jack detection (Speaker/HP redirection) event handler. 928 */ 929static void 930hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 931{ 932 struct hdac_audio_as *as; 933 struct hdac_softc *sc; 934 struct hdac_widget *w; 935 struct hdac_audio_ctl *ctl; 936 uint32_t val, res; 937 int i, j; 938 nid_t cad; 939 940 if (devinfo == NULL || devinfo->codec == NULL || 941 devinfo->codec->sc == NULL) 942 return; 943 944 sc = devinfo->codec->sc; 945 cad = devinfo->codec->cad; 946 as = devinfo->function.audio.as; 947 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 948 if (as[i].hpredir < 0) 949 continue; 950 951 w = hdac_widget_get(devinfo, as[i].pins[15]); 952 if (w == NULL || w->enable == 0 || w->type != 953 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 954 continue; 955 956 res = hdac_command(sc, 957 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 958 959 HDA_BOOTVERBOSE( 960 device_printf(sc->dev, 961 "Pin sense: nid=%d res=0x%08x\n", 962 as[i].pins[15], res); 963 ); 964 965 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 966 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 967 res ^= 1; 968 969 /* (Un)Mute headphone pin. */ 970 ctl = hdac_audio_ctl_amp_get(devinfo, 971 as[i].pins[15], HDA_CTL_IN, -1, 1); 972 if (ctl != NULL && ctl->mute) { 973 /* If pin has muter - use it. */ 974 val = (res != 0) ? 0 : 1; 975 if (val != ctl->forcemute) { 976 ctl->forcemute = val; 977 hdac_audio_ctl_amp_set(ctl, 978 HDA_AMP_MUTE_DEFAULT, 979 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 980 } 981 } else { 982 /* If there is no muter - disable pin output. */ 983 w = hdac_widget_get(devinfo, as[i].pins[15]); 984 if (w != NULL && w->type == 985 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 986 if (res != 0) 987 val = w->wclass.pin.ctrl | 988 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 989 else 990 val = w->wclass.pin.ctrl & 991 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 992 if (val != w->wclass.pin.ctrl) { 993 w->wclass.pin.ctrl = val; 994 hdac_command(sc, 995 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 996 w->nid, w->wclass.pin.ctrl), cad); 997 } 998 } 999 } 1000 /* (Un)Mute other pins. */ 1001 for (j = 0; j < 15; j++) { 1002 if (as[i].pins[j] <= 0) 1003 continue; 1004 ctl = hdac_audio_ctl_amp_get(devinfo, 1005 as[i].pins[j], HDA_CTL_IN, -1, 1); 1006 if (ctl != NULL && ctl->mute) { 1007 /* If pin has muter - use it. */ 1008 val = (res != 0) ? 1 : 0; 1009 if (val == ctl->forcemute) 1010 continue; 1011 ctl->forcemute = val; 1012 hdac_audio_ctl_amp_set(ctl, 1013 HDA_AMP_MUTE_DEFAULT, 1014 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1015 continue; 1016 } 1017 /* If there is no muter - disable pin output. */ 1018 w = hdac_widget_get(devinfo, as[i].pins[j]); 1019 if (w != NULL && w->type == 1020 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1021 if (res != 0) 1022 val = w->wclass.pin.ctrl & 1023 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1024 else 1025 val = w->wclass.pin.ctrl | 1026 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1027 if (val != w->wclass.pin.ctrl) { 1028 w->wclass.pin.ctrl = val; 1029 hdac_command(sc, 1030 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1031 w->nid, w->wclass.pin.ctrl), cad); 1032 } 1033 } 1034 } 1035 } 1036} 1037 1038/* 1039 * Callback for poll based jack detection. 1040 */ 1041static void 1042hdac_jack_poll_callback(void *arg) 1043{ 1044 struct hdac_devinfo *devinfo = arg; 1045 struct hdac_softc *sc; 1046 1047 if (devinfo == NULL || devinfo->codec == NULL || 1048 devinfo->codec->sc == NULL) 1049 return; 1050 sc = devinfo->codec->sc; 1051 hdac_lock(sc); 1052 if (sc->poll_ival == 0) { 1053 hdac_unlock(sc); 1054 return; 1055 } 1056 hdac_hp_switch_handler(devinfo); 1057 callout_reset(&sc->poll_jack, sc->poll_ival, 1058 hdac_jack_poll_callback, devinfo); 1059 hdac_unlock(sc); 1060} 1061 1062/* 1063 * Jack detection initializer. 1064 */ 1065static void 1066hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1067{ 1068 struct hdac_softc *sc = devinfo->codec->sc; 1069 struct hdac_audio_as *as = devinfo->function.audio.as; 1070 struct hdac_widget *w; 1071 uint32_t id; 1072 int i, enable = 0, poll = 0; 1073 nid_t cad; 1074 1075 id = hdac_codec_id(devinfo->codec); 1076 cad = devinfo->codec->cad; 1077 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1078 if (as[i].hpredir < 0) 1079 continue; 1080 1081 w = hdac_widget_get(devinfo, as[i].pins[15]); 1082 if (w == NULL || w->enable == 0 || w->type != 1083 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1084 continue; 1085 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1086 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1087 device_printf(sc->dev, 1088 "No jack detection support at pin %d\n", 1089 as[i].pins[15]); 1090 continue; 1091 } 1092 enable = 1; 1093 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1094 hdac_command(sc, 1095 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1096 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1097 HDAC_UNSOLTAG_EVENT_HP), cad); 1098 } else 1099 poll = 1; 1100 HDA_BOOTVERBOSE( 1101 device_printf(sc->dev, 1102 "Enabling headphone/speaker " 1103 "audio routing switching:\n"); 1104 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1105 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1106 ); 1107 } 1108 if (enable) { 1109 hdac_hp_switch_handler(devinfo); 1110 if (poll) { 1111 callout_reset(&sc->poll_jack, 1, 1112 hdac_jack_poll_callback, devinfo); 1113 } 1114 } 1115} 1116 1117/* 1118 * Unsolicited messages handler. 1119 */ 1120static void 1121hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1122{ 1123 struct hdac_softc *sc; 1124 struct hdac_devinfo *devinfo = NULL; 1125 int i; 1126 1127 if (codec == NULL || codec->sc == NULL) 1128 return; 1129 1130 sc = codec->sc; 1131 1132 HDA_BOOTVERBOSE( 1133 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1134 ); 1135 1136 for (i = 0; i < codec->num_fgs; i++) { 1137 if (codec->fgs[i].node_type == 1138 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1139 devinfo = &codec->fgs[i]; 1140 break; 1141 } 1142 } 1143 1144 if (devinfo == NULL) 1145 return; 1146 1147 switch (tag) { 1148 case HDAC_UNSOLTAG_EVENT_HP: 1149 hdac_hp_switch_handler(devinfo); 1150 break; 1151 default: 1152 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1153 break; 1154 } 1155} 1156 1157static int 1158hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1159{ 1160 /* XXX to be removed */ 1161#ifdef HDAC_INTR_EXTRA 1162 uint32_t res; 1163#endif 1164 1165 if (!(ch->flags & HDAC_CHN_RUNNING)) 1166 return (0); 1167 1168 /* XXX to be removed */ 1169#ifdef HDAC_INTR_EXTRA 1170 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1171#endif 1172 1173 /* XXX to be removed */ 1174#ifdef HDAC_INTR_EXTRA 1175 HDA_BOOTVERBOSE( 1176 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1177 device_printf(ch->pdevinfo->dev, 1178 "PCMDIR_%s intr triggered beyond stream boundary:" 1179 "%08x\n", 1180 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1181 ); 1182#endif 1183 1184 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1185 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1186 1187 /* XXX to be removed */ 1188#ifdef HDAC_INTR_EXTRA 1189 if (res & HDAC_SDSTS_BCIS) { 1190#endif 1191 return (1); 1192 /* XXX to be removed */ 1193#ifdef HDAC_INTR_EXTRA 1194 } 1195#endif 1196 1197 return (0); 1198} 1199 1200/**************************************************************************** 1201 * void hdac_intr_handler(void *) 1202 * 1203 * Interrupt handler. Processes interrupts received from the hdac. 1204 ****************************************************************************/ 1205static void 1206hdac_intr_handler(void *context) 1207{ 1208 struct hdac_softc *sc; 1209 uint32_t intsts; 1210 uint8_t rirbsts; 1211 struct hdac_rirb *rirb_base; 1212 uint32_t trigger; 1213 int i; 1214 1215 sc = (struct hdac_softc *)context; 1216 1217 hdac_lock(sc); 1218 if (sc->polling != 0) { 1219 hdac_unlock(sc); 1220 return; 1221 } 1222 1223 /* Do we have anything to do? */ 1224 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1225 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1226 hdac_unlock(sc); 1227 return; 1228 } 1229 1230 trigger = 0; 1231 1232 /* Was this a controller interrupt? */ 1233 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1234 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1235 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1236 /* Get as many responses that we can */ 1237 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1238 HDAC_WRITE_1(&sc->mem, 1239 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1240 if (hdac_rirb_flush(sc) != 0) 1241 trigger |= HDAC_TRIGGER_UNSOL; 1242 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1243 } 1244 /* XXX to be removed */ 1245 /* Clear interrupt and exit */ 1246#ifdef HDAC_INTR_EXTRA 1247 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1248#endif 1249 } 1250 1251 if (intsts & HDAC_INTSTS_SIS_MASK) { 1252 for (i = 0; i < sc->num_chans; i++) { 1253 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1254 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1255 trigger |= (1 << i); 1256 } 1257 /* XXX to be removed */ 1258#ifdef HDAC_INTR_EXTRA 1259 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1260 HDAC_INTSTS_SIS_MASK); 1261#endif 1262 } 1263 1264 hdac_unlock(sc); 1265 1266 for (i = 0; i < sc->num_chans; i++) { 1267 if (trigger & (1 << i)) 1268 chn_intr(sc->chans[i].c); 1269 } 1270 if (trigger & HDAC_TRIGGER_UNSOL) 1271 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1272} 1273 1274/**************************************************************************** 1275 * int hdac_reset(hdac_softc *, int) 1276 * 1277 * Reset the hdac to a quiescent and known state. 1278 ****************************************************************************/ 1279static int 1280hdac_reset(struct hdac_softc *sc, int wakeup) 1281{ 1282 uint32_t gctl; 1283 int count, i; 1284 1285 /* 1286 * Stop all Streams DMA engine 1287 */ 1288 for (i = 0; i < sc->num_iss; i++) 1289 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1290 for (i = 0; i < sc->num_oss; i++) 1291 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1292 for (i = 0; i < sc->num_bss; i++) 1293 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1294 1295 /* 1296 * Stop Control DMA engines. 1297 */ 1298 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1299 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1300 1301 /* 1302 * Reset DMA position buffer. 1303 */ 1304 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1305 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1306 1307 /* 1308 * Reset the controller. The reset must remain asserted for 1309 * a minimum of 100us. 1310 */ 1311 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1312 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1313 count = 10000; 1314 do { 1315 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1316 if (!(gctl & HDAC_GCTL_CRST)) 1317 break; 1318 DELAY(10); 1319 } while (--count); 1320 if (gctl & HDAC_GCTL_CRST) { 1321 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1322 return (ENXIO); 1323 } 1324 1325 /* If wakeup is not requested - leave the controller in reset state. */ 1326 if (!wakeup) 1327 return (0); 1328 1329 DELAY(100); 1330 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1331 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1332 count = 10000; 1333 do { 1334 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1335 if (gctl & HDAC_GCTL_CRST) 1336 break; 1337 DELAY(10); 1338 } while (--count); 1339 if (!(gctl & HDAC_GCTL_CRST)) { 1340 device_printf(sc->dev, "Device stuck in reset\n"); 1341 return (ENXIO); 1342 } 1343 1344 /* 1345 * Wait for codecs to finish their own reset sequence. The delay here 1346 * should be of 250us but for some reasons, on it's not enough on my 1347 * computer. Let's use twice as much as necessary to make sure that 1348 * it's reset properly. 1349 */ 1350 DELAY(1000); 1351 1352 return (0); 1353} 1354 1355 1356/**************************************************************************** 1357 * int hdac_get_capabilities(struct hdac_softc *); 1358 * 1359 * Retreive the general capabilities of the hdac; 1360 * Number of Input Streams 1361 * Number of Output Streams 1362 * Number of bidirectional Streams 1363 * 64bit ready 1364 * CORB and RIRB sizes 1365 ****************************************************************************/ 1366static int 1367hdac_get_capabilities(struct hdac_softc *sc) 1368{ 1369 uint16_t gcap; 1370 uint8_t corbsize, rirbsize; 1371 1372 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1373 sc->num_iss = HDAC_GCAP_ISS(gcap); 1374 sc->num_oss = HDAC_GCAP_OSS(gcap); 1375 sc->num_bss = HDAC_GCAP_BSS(gcap); 1376 1377 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1378 1379 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1380 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1381 HDAC_CORBSIZE_CORBSZCAP_256) 1382 sc->corb_size = 256; 1383 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1384 HDAC_CORBSIZE_CORBSZCAP_16) 1385 sc->corb_size = 16; 1386 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1387 HDAC_CORBSIZE_CORBSZCAP_2) 1388 sc->corb_size = 2; 1389 else { 1390 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1391 __func__, corbsize); 1392 return (ENXIO); 1393 } 1394 1395 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1396 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1397 HDAC_RIRBSIZE_RIRBSZCAP_256) 1398 sc->rirb_size = 256; 1399 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1400 HDAC_RIRBSIZE_RIRBSZCAP_16) 1401 sc->rirb_size = 16; 1402 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1403 HDAC_RIRBSIZE_RIRBSZCAP_2) 1404 sc->rirb_size = 2; 1405 else { 1406 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1407 __func__, rirbsize); 1408 return (ENXIO); 1409 } 1410 1411 HDA_BOOTHVERBOSE( 1412 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1413 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1414 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1415 sc->num_iss, sc->num_oss, sc->num_bss); 1416 ); 1417 1418 return (0); 1419} 1420 1421 1422/**************************************************************************** 1423 * void hdac_dma_cb 1424 * 1425 * This function is called by bus_dmamap_load when the mapping has been 1426 * established. We just record the physical address of the mapping into 1427 * the struct hdac_dma passed in. 1428 ****************************************************************************/ 1429static void 1430hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1431{ 1432 struct hdac_dma *dma; 1433 1434 if (error == 0) { 1435 dma = (struct hdac_dma *)callback_arg; 1436 dma->dma_paddr = segs[0].ds_addr; 1437 } 1438} 1439 1440 1441/**************************************************************************** 1442 * int hdac_dma_alloc 1443 * 1444 * This function allocate and setup a dma region (struct hdac_dma). 1445 * It must be freed by a corresponding hdac_dma_free. 1446 ****************************************************************************/ 1447static int 1448hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1449{ 1450 bus_size_t roundsz; 1451 int result; 1452 int lowaddr; 1453 1454 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1455 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1456 BUS_SPACE_MAXADDR_32BIT; 1457 bzero(dma, sizeof(*dma)); 1458 1459 /* 1460 * Create a DMA tag 1461 */ 1462 result = bus_dma_tag_create(NULL, /* parent */ 1463 HDAC_DMA_ALIGNMENT, /* alignment */ 1464 0, /* boundary */ 1465 lowaddr, /* lowaddr */ 1466 BUS_SPACE_MAXADDR, /* highaddr */ 1467 NULL, /* filtfunc */ 1468 NULL, /* fistfuncarg */ 1469 roundsz, /* maxsize */ 1470 1, /* nsegments */ 1471 roundsz, /* maxsegsz */ 1472 0, /* flags */ 1473 NULL, /* lockfunc */ 1474 NULL, /* lockfuncarg */ 1475 &dma->dma_tag); /* dmat */ 1476 if (result != 0) { 1477 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1478 __func__, result); 1479 goto hdac_dma_alloc_fail; 1480 } 1481 1482 /* 1483 * Allocate DMA memory 1484 */ 1485 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1486 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1487 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1488 &dma->dma_map); 1489 if (result != 0) { 1490 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1491 __func__, result); 1492 goto hdac_dma_alloc_fail; 1493 } 1494 1495 dma->dma_size = roundsz; 1496 1497 /* 1498 * Map the memory 1499 */ 1500 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1501 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1502 if (result != 0 || dma->dma_paddr == 0) { 1503 if (result == 0) 1504 result = ENOMEM; 1505 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1506 __func__, result); 1507 goto hdac_dma_alloc_fail; 1508 } 1509 1510 HDA_BOOTHVERBOSE( 1511 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1512 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1513 ); 1514 1515 return (0); 1516 1517hdac_dma_alloc_fail: 1518 hdac_dma_free(sc, dma); 1519 1520 return (result); 1521} 1522 1523 1524/**************************************************************************** 1525 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1526 * 1527 * Free a struct dhac_dma that has been previously allocated via the 1528 * hdac_dma_alloc function. 1529 ****************************************************************************/ 1530static void 1531hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1532{ 1533 if (dma->dma_map != NULL) { 1534#if 0 1535 /* Flush caches */ 1536 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1537 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1538#endif 1539 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1540 } 1541 if (dma->dma_vaddr != NULL) { 1542 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1543 dma->dma_vaddr = NULL; 1544 } 1545 dma->dma_map = NULL; 1546 if (dma->dma_tag != NULL) { 1547 bus_dma_tag_destroy(dma->dma_tag); 1548 dma->dma_tag = NULL; 1549 } 1550 dma->dma_size = 0; 1551} 1552 1553/**************************************************************************** 1554 * int hdac_mem_alloc(struct hdac_softc *) 1555 * 1556 * Allocate all the bus resources necessary to speak with the physical 1557 * controller. 1558 ****************************************************************************/ 1559static int 1560hdac_mem_alloc(struct hdac_softc *sc) 1561{ 1562 struct hdac_mem *mem; 1563 1564 mem = &sc->mem; 1565 mem->mem_rid = PCIR_BAR(0); 1566 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1567 &mem->mem_rid, RF_ACTIVE); 1568 if (mem->mem_res == NULL) { 1569 device_printf(sc->dev, 1570 "%s: Unable to allocate memory resource\n", __func__); 1571 return (ENOMEM); 1572 } 1573 mem->mem_tag = rman_get_bustag(mem->mem_res); 1574 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1575 1576 return (0); 1577} 1578 1579/**************************************************************************** 1580 * void hdac_mem_free(struct hdac_softc *) 1581 * 1582 * Free up resources previously allocated by hdac_mem_alloc. 1583 ****************************************************************************/ 1584static void 1585hdac_mem_free(struct hdac_softc *sc) 1586{ 1587 struct hdac_mem *mem; 1588 1589 mem = &sc->mem; 1590 if (mem->mem_res != NULL) 1591 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1592 mem->mem_res); 1593 mem->mem_res = NULL; 1594} 1595 1596/**************************************************************************** 1597 * int hdac_irq_alloc(struct hdac_softc *) 1598 * 1599 * Allocate and setup the resources necessary for interrupt handling. 1600 ****************************************************************************/ 1601static int 1602hdac_irq_alloc(struct hdac_softc *sc) 1603{ 1604 struct hdac_irq *irq; 1605 int result; 1606 1607 irq = &sc->irq; 1608 irq->irq_rid = 0x0; 1609 1610#ifdef HDAC_MSI_ENABLED 1611 if ((sc->flags & HDAC_F_MSI) && 1612 (result = pci_msi_count(sc->dev)) == 1 && 1613 pci_alloc_msi(sc->dev, &result) == 0) 1614 irq->irq_rid = 0x1; 1615 else 1616#endif 1617 sc->flags &= ~HDAC_F_MSI; 1618 1619 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1620 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1621 if (irq->irq_res == NULL) { 1622 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1623 __func__); 1624 goto hdac_irq_alloc_fail; 1625 } 1626 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1627 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1628 if (result != 0) { 1629 device_printf(sc->dev, 1630 "%s: Unable to setup interrupt handler (%x)\n", 1631 __func__, result); 1632 goto hdac_irq_alloc_fail; 1633 } 1634 1635 return (0); 1636 1637hdac_irq_alloc_fail: 1638 hdac_irq_free(sc); 1639 1640 return (ENXIO); 1641} 1642 1643/**************************************************************************** 1644 * void hdac_irq_free(struct hdac_softc *) 1645 * 1646 * Free up resources previously allocated by hdac_irq_alloc. 1647 ****************************************************************************/ 1648static void 1649hdac_irq_free(struct hdac_softc *sc) 1650{ 1651 struct hdac_irq *irq; 1652 1653 irq = &sc->irq; 1654 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1655 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1656 if (irq->irq_res != NULL) 1657 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1658 irq->irq_res); 1659#ifdef HDAC_MSI_ENABLED 1660 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1661 pci_release_msi(sc->dev); 1662#endif 1663 irq->irq_handle = NULL; 1664 irq->irq_res = NULL; 1665 irq->irq_rid = 0x0; 1666} 1667 1668/**************************************************************************** 1669 * void hdac_corb_init(struct hdac_softc *) 1670 * 1671 * Initialize the corb registers for operations but do not start it up yet. 1672 * The CORB engine must not be running when this function is called. 1673 ****************************************************************************/ 1674static void 1675hdac_corb_init(struct hdac_softc *sc) 1676{ 1677 uint8_t corbsize; 1678 uint64_t corbpaddr; 1679 1680 /* Setup the CORB size. */ 1681 switch (sc->corb_size) { 1682 case 256: 1683 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1684 break; 1685 case 16: 1686 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1687 break; 1688 case 2: 1689 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1690 break; 1691 default: 1692 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1693 } 1694 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1695 1696 /* Setup the CORB Address in the hdac */ 1697 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1698 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1699 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1700 1701 /* Set the WP and RP */ 1702 sc->corb_wp = 0; 1703 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1704 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1705 /* 1706 * The HDA specification indicates that the CORBRPRST bit will always 1707 * read as zero. Unfortunately, it seems that at least the 82801G 1708 * doesn't reset the bit to zero, which stalls the corb engine. 1709 * manually reset the bit to zero before continuing. 1710 */ 1711 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1712 1713 /* Enable CORB error reporting */ 1714#if 0 1715 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1716#endif 1717} 1718 1719/**************************************************************************** 1720 * void hdac_rirb_init(struct hdac_softc *) 1721 * 1722 * Initialize the rirb registers for operations but do not start it up yet. 1723 * The RIRB engine must not be running when this function is called. 1724 ****************************************************************************/ 1725static void 1726hdac_rirb_init(struct hdac_softc *sc) 1727{ 1728 uint8_t rirbsize; 1729 uint64_t rirbpaddr; 1730 1731 /* Setup the RIRB size. */ 1732 switch (sc->rirb_size) { 1733 case 256: 1734 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1735 break; 1736 case 16: 1737 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1738 break; 1739 case 2: 1740 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1741 break; 1742 default: 1743 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1744 } 1745 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1746 1747 /* Setup the RIRB Address in the hdac */ 1748 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1749 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1750 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1751 1752 /* Setup the WP and RP */ 1753 sc->rirb_rp = 0; 1754 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1755 1756 /* Setup the interrupt threshold */ 1757 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1758 1759 /* Enable Overrun and response received reporting */ 1760#if 0 1761 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1762 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1763#else 1764 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1765#endif 1766 1767#if 0 1768 /* 1769 * Make sure that the Host CPU cache doesn't contain any dirty 1770 * cache lines that falls in the rirb. If I understood correctly, it 1771 * should be sufficient to do this only once as the rirb is purely 1772 * read-only from now on. 1773 */ 1774 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1775 BUS_DMASYNC_PREREAD); 1776#endif 1777} 1778 1779/**************************************************************************** 1780 * void hdac_corb_start(hdac_softc *) 1781 * 1782 * Startup the corb DMA engine 1783 ****************************************************************************/ 1784static void 1785hdac_corb_start(struct hdac_softc *sc) 1786{ 1787 uint32_t corbctl; 1788 1789 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1790 corbctl |= HDAC_CORBCTL_CORBRUN; 1791 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1792} 1793 1794/**************************************************************************** 1795 * void hdac_rirb_start(hdac_softc *) 1796 * 1797 * Startup the rirb DMA engine 1798 ****************************************************************************/ 1799static void 1800hdac_rirb_start(struct hdac_softc *sc) 1801{ 1802 uint32_t rirbctl; 1803 1804 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1805 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1806 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1807} 1808 1809 1810/**************************************************************************** 1811 * void hdac_scan_codecs(struct hdac_softc *, int) 1812 * 1813 * Scan the bus for available codecs, starting with num. 1814 ****************************************************************************/ 1815static void 1816hdac_scan_codecs(struct hdac_softc *sc) 1817{ 1818 struct hdac_codec *codec; 1819 int i; 1820 uint16_t statests; 1821 1822 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1823 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1824 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1825 /* We have found a codec. */ 1826 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1827 M_HDAC, M_ZERO | M_NOWAIT); 1828 if (codec == NULL) { 1829 device_printf(sc->dev, 1830 "Unable to allocate memory for codec\n"); 1831 continue; 1832 } 1833 codec->commands = NULL; 1834 codec->responses_received = 0; 1835 codec->verbs_sent = 0; 1836 codec->sc = sc; 1837 codec->cad = i; 1838 sc->codecs[i] = codec; 1839 hdac_probe_codec(codec); 1840 } 1841 } 1842 /* All codecs have been probed, now try to attach drivers to them */ 1843 /* bus_generic_attach(sc->dev); */ 1844} 1845 1846/**************************************************************************** 1847 * void hdac_probe_codec(struct hdac_softc *, int) 1848 * 1849 * Probe a the given codec_id for available function groups. 1850 ****************************************************************************/ 1851static void 1852hdac_probe_codec(struct hdac_codec *codec) 1853{ 1854 struct hdac_softc *sc = codec->sc; 1855 uint32_t vendorid, revisionid, subnode; 1856 int startnode; 1857 int endnode; 1858 int i; 1859 nid_t cad = codec->cad; 1860 1861 HDA_BOOTVERBOSE( 1862 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1863 ); 1864 vendorid = hdac_command(sc, 1865 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1866 cad); 1867 revisionid = hdac_command(sc, 1868 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1869 cad); 1870 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1871 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1872 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1873 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1874 1875 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1876 device_printf(sc->dev, "Codec #%d is not responding!" 1877 " Probing aborted.\n", cad); 1878 return; 1879 } 1880 1881 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1882 cad, hdac_codec_name(codec)); 1883 HDA_BOOTVERBOSE( 1884 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1885 hdac_codec_id(codec)); 1886 device_printf(sc->dev, " Vendor: 0x%04x\n", 1887 codec->vendor_id); 1888 device_printf(sc->dev, " Device: 0x%04x\n", 1889 codec->device_id); 1890 device_printf(sc->dev, " Revision: 0x%02x\n", 1891 codec->revision_id); 1892 device_printf(sc->dev, " Stepping: 0x%02x\n", 1893 codec->stepping_id); 1894 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1895 sc->pci_subvendor); 1896 ); 1897 subnode = hdac_command(sc, 1898 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1899 cad); 1900 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1901 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1902 1903 HDA_BOOTHVERBOSE( 1904 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1905 startnode, endnode); 1906 ); 1907 1908 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1909 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1910 if (codec->fgs == NULL) { 1911 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1912 __func__); 1913 return; 1914 } 1915 1916 for (i = startnode; i < endnode; i++) 1917 hdac_probe_function(codec, i); 1918 return; 1919} 1920 1921/* 1922 * Probe codec function and add it to the list. 1923 */ 1924static void 1925hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1926{ 1927 struct hdac_softc *sc = codec->sc; 1928 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1929 uint32_t fctgrptype; 1930 uint32_t res; 1931 nid_t cad = codec->cad; 1932 1933 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1934 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1935 1936 devinfo->nid = nid; 1937 devinfo->node_type = fctgrptype; 1938 devinfo->codec = codec; 1939 1940 res = hdac_command(sc, 1941 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1942 1943 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1944 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1945 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1946 1947 HDA_BOOTVERBOSE( 1948 device_printf(sc->dev, 1949 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1950 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1951 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1952 "unknown", nid, devinfo->startnode, devinfo->endnode, 1953 devinfo->nodecnt); 1954 ); 1955 1956 if (devinfo->nodecnt > 0) 1957 devinfo->widget = (struct hdac_widget *)malloc( 1958 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1959 M_NOWAIT | M_ZERO); 1960 else 1961 devinfo->widget = NULL; 1962 1963 if (devinfo->widget == NULL) { 1964 device_printf(sc->dev, "unable to allocate widgets!\n"); 1965 devinfo->endnode = devinfo->startnode; 1966 devinfo->nodecnt = 0; 1967 return; 1968 } 1969 1970 codec->num_fgs++; 1971} 1972 1973static void 1974hdac_widget_connection_parse(struct hdac_widget *w) 1975{ 1976 struct hdac_softc *sc = w->devinfo->codec->sc; 1977 uint32_t res; 1978 int i, j, max, ents, entnum; 1979 nid_t cad = w->devinfo->codec->cad; 1980 nid_t nid = w->nid; 1981 nid_t cnid, addcnid, prevcnid; 1982 1983 w->nconns = 0; 1984 1985 res = hdac_command(sc, 1986 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1987 1988 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1989 1990 if (ents < 1) 1991 return; 1992 1993 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1994 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1995 prevcnid = 0; 1996 1997#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1998#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1999#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2000#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2001#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2002 2003 for (i = 0; i < ents; i += entnum) { 2004 res = hdac_command(sc, 2005 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2006 for (j = 0; j < entnum; j++) { 2007 cnid = CONN_CNID(res, entnum, j); 2008 if (cnid == 0) { 2009 if (w->nconns < ents) 2010 device_printf(sc->dev, 2011 "%s: nid=%d WARNING: zero cnid " 2012 "entnum=%d j=%d index=%d " 2013 "entries=%d found=%d res=0x%08x\n", 2014 __func__, nid, entnum, j, i, 2015 ents, w->nconns, res); 2016 else 2017 goto getconns_out; 2018 } 2019 if (cnid < w->devinfo->startnode || 2020 cnid >= w->devinfo->endnode) { 2021 HDA_BOOTVERBOSE( 2022 device_printf(sc->dev, 2023 "GHOST: nid=%d j=%d " 2024 "entnum=%d index=%d res=0x%08x\n", 2025 nid, j, entnum, i, res); 2026 ); 2027 } 2028 if (CONN_RANGE(res, entnum, j) == 0) 2029 addcnid = cnid; 2030 else if (prevcnid == 0 || prevcnid >= cnid) { 2031 device_printf(sc->dev, 2032 "%s: WARNING: Invalid child range " 2033 "nid=%d index=%d j=%d entnum=%d " 2034 "prevcnid=%d cnid=%d res=0x%08x\n", 2035 __func__, nid, i, j, entnum, prevcnid, 2036 cnid, res); 2037 addcnid = cnid; 2038 } else 2039 addcnid = prevcnid + 1; 2040 while (addcnid <= cnid) { 2041 if (w->nconns > max) { 2042 device_printf(sc->dev, 2043 "Adding %d (nid=%d): " 2044 "Max connection reached! max=%d\n", 2045 addcnid, nid, max + 1); 2046 goto getconns_out; 2047 } 2048 w->connsenable[w->nconns] = 1; 2049 w->conns[w->nconns++] = addcnid++; 2050 } 2051 prevcnid = cnid; 2052 } 2053 } 2054 2055getconns_out: 2056 return; 2057} 2058 2059static uint32_t 2060hdac_widget_pin_patch(uint32_t config, const char *str) 2061{ 2062 char buf[256]; 2063 char *key, *value, *rest, *bad; 2064 int ival, i; 2065 2066 strlcpy(buf, str, sizeof(buf)); 2067 rest = buf; 2068 while ((key = strsep(&rest, "=")) != NULL) { 2069 value = strsep(&rest, " \t"); 2070 if (value == NULL) 2071 break; 2072 ival = strtol(value, &bad, 10); 2073 if (strcmp(key, "seq") == 0) { 2074 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2075 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2076 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2077 } else if (strcmp(key, "as") == 0) { 2078 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2079 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2080 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2081 } else if (strcmp(key, "misc") == 0) { 2082 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2083 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2084 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2085 } else if (strcmp(key, "color") == 0) { 2086 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2087 if (bad[0] == 0) { 2088 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2089 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2090 }; 2091 for (i = 0; i < 16; i++) { 2092 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2093 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2094 break; 2095 } 2096 } 2097 } else if (strcmp(key, "ctype") == 0) { 2098 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2099 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2100 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2101 } else if (strcmp(key, "device") == 0) { 2102 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2103 if (bad[0] == 0) { 2104 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2105 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2106 continue; 2107 }; 2108 for (i = 0; i < 16; i++) { 2109 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2110 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2111 break; 2112 } 2113 } 2114 } else if (strcmp(key, "loc") == 0) { 2115 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2116 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2117 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2118 } else if (strcmp(key, "conn") == 0) { 2119 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2120 if (bad[0] == 0) { 2121 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2122 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2123 continue; 2124 }; 2125 for (i = 0; i < 4; i++) { 2126 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2127 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2128 break; 2129 } 2130 } 2131 } 2132 } 2133 return (config); 2134} 2135 2136static uint32_t 2137hdac_widget_pin_getconfig(struct hdac_widget *w) 2138{ 2139 struct hdac_softc *sc; 2140 uint32_t config, orig, id; 2141 nid_t cad, nid; 2142 char buf[32]; 2143 const char *res = NULL, *patch = NULL; 2144 2145 sc = w->devinfo->codec->sc; 2146 cad = w->devinfo->codec->cad; 2147 nid = w->nid; 2148 id = hdac_codec_id(w->devinfo->codec); 2149 2150 config = hdac_command(sc, 2151 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2152 cad); 2153 orig = config; 2154 2155 HDA_BOOTVERBOSE( 2156 hdac_dump_pin_config(w, orig); 2157 ); 2158 2159 /* XXX: Old patches require complete review. 2160 * Now they may create more problem then solve due to 2161 * incorrect associations. 2162 */ 2163 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2164 switch (nid) { 2165 case 26: 2166 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2167 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2168 break; 2169 case 27: 2170 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2171 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2172 break; 2173 default: 2174 break; 2175 } 2176 } else if (id == HDA_CODEC_ALC880 && 2177 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2178 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2179 /* 2180 * Super broken BIOS 2181 */ 2182 switch (nid) { 2183 case 24: /* MIC1 */ 2184 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2185 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2186 break; 2187 case 25: /* XXX MIC2 */ 2188 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2189 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2190 break; 2191 case 26: /* LINE1 */ 2192 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2193 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2194 break; 2195 case 27: /* XXX LINE2 */ 2196 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2197 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2198 break; 2199 case 28: /* CD */ 2200 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2201 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2202 break; 2203 } 2204 } else if (id == HDA_CODEC_ALC883 && 2205 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2206 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2207 switch (nid) { 2208 case 25: 2209 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2210 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2211 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2212 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2213 break; 2214 case 28: 2215 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2216 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2217 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2218 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2219 break; 2220 } 2221 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2222 HP_V3000_SUBVENDOR) { 2223 switch (nid) { 2224 case 18: 2225 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2226 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2227 break; 2228 case 20: 2229 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2230 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2231 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2232 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2233 break; 2234 case 21: 2235 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2236 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2237 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2238 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2239 break; 2240 } 2241 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2242 HP_DV5000_SUBVENDOR) { 2243 switch (nid) { 2244 case 20: 2245 case 21: 2246 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2247 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2248 break; 2249 } 2250 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2251 ASUS_W6F_SUBVENDOR) { 2252 switch (nid) { 2253 case 11: 2254 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2255 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2256 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2257 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2258 break; 2259 case 12: 2260 case 14: 2261 case 16: 2262 case 31: 2263 case 32: 2264 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2265 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2266 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2267 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2268 break; 2269 case 15: 2270 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2271 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2272 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2273 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2274 break; 2275 } 2276 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2277 UNIWILL_9075_SUBVENDOR) { 2278 switch (nid) { 2279 case 15: 2280 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2281 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2282 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2283 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2284 break; 2285 } 2286 } 2287 2288 /* New patches */ 2289 if (id == HDA_CODEC_AD1986A && 2290 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2291 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2292 switch (nid) { 2293 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2294 patch = "device=Line-in as=8 seq=1"; 2295 break; 2296 case 29: 2297 patch = "device=Mic as=8 seq=2"; 2298 break; 2299 case 31: /* Lot of inputs configured with as=15 and unusable */ 2300 patch = "as=8 seq=3"; 2301 break; 2302 case 32: 2303 patch = "as=8 seq=4"; 2304 break; 2305 case 34: 2306 patch = "as=8 seq=5"; 2307 break; 2308 case 36: 2309 patch = "as=8 seq=6"; 2310 break; 2311 } 2312 } else if (id == HDA_CODEC_ALC260 && 2313 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2314 switch (nid) { 2315 case 16: 2316 patch = "seq=15 device=Headphones"; 2317 break; 2318 } 2319 } else if (id == HDA_CODEC_ALC268 && 2320 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2321 switch (nid) { 2322 case 28: 2323 patch = "device=CD conn=fixed"; 2324 break; 2325 } 2326 } 2327 2328 if (patch != NULL) 2329 config = hdac_widget_pin_patch(config, patch); 2330 2331 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2332 if (resource_string_value(device_get_name(sc->dev), 2333 device_get_unit(sc->dev), buf, &res) == 0) { 2334 if (strncmp(res, "0x", 2) == 0) { 2335 config = strtol(res + 2, NULL, 16); 2336 } else { 2337 config = hdac_widget_pin_patch(config, res); 2338 } 2339 } 2340 2341 HDA_BOOTVERBOSE( 2342 if (config != orig) 2343 device_printf(sc->dev, 2344 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2345 nid, orig, config); 2346 ); 2347 2348 return (config); 2349} 2350 2351static uint32_t 2352hdac_widget_pin_getcaps(struct hdac_widget *w) 2353{ 2354 struct hdac_softc *sc; 2355 uint32_t caps, orig, id; 2356 nid_t cad, nid; 2357 2358 sc = w->devinfo->codec->sc; 2359 cad = w->devinfo->codec->cad; 2360 nid = w->nid; 2361 id = hdac_codec_id(w->devinfo->codec); 2362 2363 caps = hdac_command(sc, 2364 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2365 orig = caps; 2366 2367 HDA_BOOTVERBOSE( 2368 if (caps != orig) 2369 device_printf(sc->dev, 2370 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2371 nid, orig, caps); 2372 ); 2373 2374 return (caps); 2375} 2376 2377static void 2378hdac_widget_pin_parse(struct hdac_widget *w) 2379{ 2380 struct hdac_softc *sc = w->devinfo->codec->sc; 2381 uint32_t config, pincap; 2382 const char *devstr, *connstr; 2383 nid_t cad = w->devinfo->codec->cad; 2384 nid_t nid = w->nid; 2385 2386 config = hdac_widget_pin_getconfig(w); 2387 w->wclass.pin.config = config; 2388 2389 pincap = hdac_widget_pin_getcaps(w); 2390 w->wclass.pin.cap = pincap; 2391 2392 w->wclass.pin.ctrl = hdac_command(sc, 2393 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2394 2395 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2396 w->param.eapdbtl = hdac_command(sc, 2397 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2398 w->param.eapdbtl &= 0x7; 2399 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2400 } else 2401 w->param.eapdbtl = HDAC_INVALID; 2402 2403 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2404 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2405 2406 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2408 2409 strlcat(w->name, ": ", sizeof(w->name)); 2410 strlcat(w->name, devstr, sizeof(w->name)); 2411 strlcat(w->name, " (", sizeof(w->name)); 2412 strlcat(w->name, connstr, sizeof(w->name)); 2413 strlcat(w->name, ")", sizeof(w->name)); 2414} 2415 2416static uint32_t 2417hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2418{ 2419 struct hdac_softc *sc; 2420 uint32_t caps, orig, id; 2421 nid_t cad, nid, beeper = -1; 2422 2423 sc = w->devinfo->codec->sc; 2424 cad = w->devinfo->codec->cad; 2425 nid = w->nid; 2426 id = hdac_codec_id(w->devinfo->codec); 2427 2428 caps = hdac_command(sc, 2429 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2430 cad); 2431 orig = caps; 2432 2433 /* On some codecs beeper is an input pin, but it is not recordable 2434 alone. Also most of BIOSes does not declare beeper pin. 2435 Change beeper pin node type to beeper to help parser. */ 2436 *waspin = 0; 2437 switch (id) { 2438 case HDA_CODEC_AD1988: 2439 case HDA_CODEC_AD1988B: 2440 beeper = 26; 2441 break; 2442 case HDA_CODEC_ALC260: 2443 beeper = 23; 2444 break; 2445 case HDA_CODEC_ALC262: 2446 case HDA_CODEC_ALC268: 2447 case HDA_CODEC_ALC880: 2448 case HDA_CODEC_ALC882: 2449 case HDA_CODEC_ALC883: 2450 case HDA_CODEC_ALC885: 2451 case HDA_CODEC_ALC888: 2452 case HDA_CODEC_ALC889: 2453 beeper = 29; 2454 break; 2455 } 2456 if (nid == beeper) { 2457 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2458 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2459 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2460 *waspin = 1; 2461 } 2462 2463 HDA_BOOTVERBOSE( 2464 if (caps != orig) { 2465 device_printf(sc->dev, 2466 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2467 nid, orig, caps); 2468 } 2469 ); 2470 2471 return (caps); 2472} 2473 2474static void 2475hdac_widget_parse(struct hdac_widget *w) 2476{ 2477 struct hdac_softc *sc = w->devinfo->codec->sc; 2478 uint32_t wcap, cap; 2479 char *typestr; 2480 nid_t cad = w->devinfo->codec->cad; 2481 nid_t nid = w->nid; 2482 2483 wcap = hdac_widget_getcaps(w, &w->waspin); 2484 2485 w->param.widget_cap = wcap; 2486 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2487 2488 switch (w->type) { 2489 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2490 typestr = "audio output"; 2491 break; 2492 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2493 typestr = "audio input"; 2494 break; 2495 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2496 typestr = "audio mixer"; 2497 break; 2498 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2499 typestr = "audio selector"; 2500 break; 2501 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2502 typestr = "pin"; 2503 break; 2504 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2505 typestr = "power widget"; 2506 break; 2507 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2508 typestr = "volume widget"; 2509 break; 2510 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2511 typestr = "beep widget"; 2512 break; 2513 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2514 typestr = "vendor widget"; 2515 break; 2516 default: 2517 typestr = "unknown type"; 2518 break; 2519 } 2520 2521 strlcpy(w->name, typestr, sizeof(w->name)); 2522 2523 hdac_widget_connection_parse(w); 2524 2525 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2526 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2527 w->param.outamp_cap = 2528 hdac_command(sc, 2529 HDA_CMD_GET_PARAMETER(cad, nid, 2530 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2531 else 2532 w->param.outamp_cap = 2533 w->devinfo->function.audio.outamp_cap; 2534 } else 2535 w->param.outamp_cap = 0; 2536 2537 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2538 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2539 w->param.inamp_cap = 2540 hdac_command(sc, 2541 HDA_CMD_GET_PARAMETER(cad, nid, 2542 HDA_PARAM_INPUT_AMP_CAP), cad); 2543 else 2544 w->param.inamp_cap = 2545 w->devinfo->function.audio.inamp_cap; 2546 } else 2547 w->param.inamp_cap = 0; 2548 2549 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2550 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2551 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2552 cap = hdac_command(sc, 2553 HDA_CMD_GET_PARAMETER(cad, nid, 2554 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2555 w->param.supp_stream_formats = (cap != 0) ? cap : 2556 w->devinfo->function.audio.supp_stream_formats; 2557 cap = hdac_command(sc, 2558 HDA_CMD_GET_PARAMETER(cad, nid, 2559 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2560 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2561 w->devinfo->function.audio.supp_pcm_size_rate; 2562 } else { 2563 w->param.supp_stream_formats = 2564 w->devinfo->function.audio.supp_stream_formats; 2565 w->param.supp_pcm_size_rate = 2566 w->devinfo->function.audio.supp_pcm_size_rate; 2567 } 2568 } else { 2569 w->param.supp_stream_formats = 0; 2570 w->param.supp_pcm_size_rate = 0; 2571 } 2572 2573 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2574 hdac_widget_pin_parse(w); 2575} 2576 2577static struct hdac_widget * 2578hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2579{ 2580 if (devinfo == NULL || devinfo->widget == NULL || 2581 nid < devinfo->startnode || nid >= devinfo->endnode) 2582 return (NULL); 2583 return (&devinfo->widget[nid - devinfo->startnode]); 2584} 2585 2586static __inline int 2587hda_poll_channel(struct hdac_chan *ch) 2588{ 2589 uint32_t sz, delta; 2590 volatile uint32_t ptr; 2591 2592 if (!(ch->flags & HDAC_CHN_RUNNING)) 2593 return (0); 2594 2595 sz = ch->blksz * ch->blkcnt; 2596 if (ch->dmapos != NULL) 2597 ptr = *(ch->dmapos); 2598 else 2599 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2600 ch->off + HDAC_SDLPIB); 2601 ch->ptr = ptr; 2602 ptr %= sz; 2603 ptr &= ~(ch->blksz - 1); 2604 delta = (sz + ptr - ch->prevptr) % sz; 2605 2606 if (delta < ch->blksz) 2607 return (0); 2608 2609 ch->prevptr = ptr; 2610 2611 return (1); 2612} 2613 2614static void 2615hda_poll_callback(void *arg) 2616{ 2617 struct hdac_softc *sc = arg; 2618 uint32_t trigger; 2619 int i, active = 0; 2620 2621 if (sc == NULL) 2622 return; 2623 2624 hdac_lock(sc); 2625 if (sc->polling == 0) { 2626 hdac_unlock(sc); 2627 return; 2628 } 2629 2630 trigger = 0; 2631 for (i = 0; i < sc->num_chans; i++) { 2632 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2633 continue; 2634 active = 1; 2635 if (hda_poll_channel(&sc->chans[i])) 2636 trigger |= (1 << i); 2637 } 2638 2639 /* XXX */ 2640 if (active) 2641 callout_reset(&sc->poll_hda, sc->poll_ticks, 2642 hda_poll_callback, sc); 2643 2644 hdac_unlock(sc); 2645 2646 for (i = 0; i < sc->num_chans; i++) { 2647 if (trigger & (1 << i)) 2648 chn_intr(sc->chans[i].c); 2649 } 2650} 2651 2652static int 2653hdac_rirb_flush(struct hdac_softc *sc) 2654{ 2655 struct hdac_rirb *rirb_base, *rirb; 2656 struct hdac_codec *codec; 2657 struct hdac_command_list *commands; 2658 nid_t cad; 2659 uint32_t resp; 2660 uint8_t rirbwp; 2661 int ret; 2662 2663 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2664 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2665#if 0 2666 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2667 BUS_DMASYNC_POSTREAD); 2668#endif 2669 2670 ret = 0; 2671 2672 while (sc->rirb_rp != rirbwp) { 2673 sc->rirb_rp++; 2674 sc->rirb_rp %= sc->rirb_size; 2675 rirb = &rirb_base[sc->rirb_rp]; 2676 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2677 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2678 sc->codecs[cad] == NULL) 2679 continue; 2680 resp = rirb->response; 2681 codec = sc->codecs[cad]; 2682 commands = codec->commands; 2683 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2684 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2685 ((resp >> 26) & 0xffff); 2686 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2687 } else if (commands != NULL && commands->num_commands > 0 && 2688 codec->responses_received < commands->num_commands) 2689 commands->responses[codec->responses_received++] = 2690 resp; 2691 ret++; 2692 } 2693 2694 return (ret); 2695} 2696 2697static int 2698hdac_unsolq_flush(struct hdac_softc *sc) 2699{ 2700 nid_t cad; 2701 uint32_t tag; 2702 int ret = 0; 2703 2704 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2705 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2706 while (sc->unsolq_rp != sc->unsolq_wp) { 2707 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2708 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2709 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2710 hdac_unsolicited_handler(sc->codecs[cad], tag); 2711 ret++; 2712 } 2713 sc->unsolq_st = HDAC_UNSOLQ_READY; 2714 } 2715 2716 return (ret); 2717} 2718 2719static void 2720hdac_poll_callback(void *arg) 2721{ 2722 struct hdac_softc *sc = arg; 2723 if (sc == NULL) 2724 return; 2725 2726 hdac_lock(sc); 2727 if (sc->polling == 0 || sc->poll_ival == 0) { 2728 hdac_unlock(sc); 2729 return; 2730 } 2731 if (hdac_rirb_flush(sc) != 0) 2732 hdac_unsolq_flush(sc); 2733 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2734 hdac_unlock(sc); 2735} 2736 2737static void 2738hdac_poll_reinit(struct hdac_softc *sc) 2739{ 2740 int i, pollticks, min = 1000000; 2741 struct hdac_chan *ch; 2742 2743 for (i = 0; i < sc->num_chans; i++) { 2744 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2745 continue; 2746 ch = &sc->chans[i]; 2747 pollticks = ((uint64_t)hz * ch->blksz) / 2748 ((uint64_t)sndbuf_getbps(ch->b) * 2749 sndbuf_getspd(ch->b)); 2750 pollticks >>= 1; 2751 if (pollticks > hz) 2752 pollticks = hz; 2753 if (pollticks < 1) { 2754 HDA_BOOTVERBOSE( 2755 device_printf(sc->dev, 2756 "%s: pollticks=%d < 1 !\n", 2757 __func__, pollticks); 2758 ); 2759 pollticks = 1; 2760 } 2761 if (min > pollticks) 2762 min = pollticks; 2763 } 2764 HDA_BOOTVERBOSE( 2765 device_printf(sc->dev, 2766 "%s: pollticks %d -> %d\n", 2767 __func__, sc->poll_ticks, min); 2768 ); 2769 sc->poll_ticks = min; 2770 if (min == 1000000) 2771 callout_stop(&sc->poll_hda); 2772 else 2773 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2774} 2775 2776static void 2777hdac_stream_stop(struct hdac_chan *ch) 2778{ 2779 struct hdac_softc *sc = ch->devinfo->codec->sc; 2780 uint32_t ctl; 2781 2782 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2783 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2784 HDAC_SDCTL_RUN); 2785 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2786 2787 ch->flags &= ~HDAC_CHN_RUNNING; 2788 2789 if (sc->polling != 0) 2790 hdac_poll_reinit(sc); 2791 2792 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2793 ctl &= ~(1 << (ch->off >> 5)); 2794 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2795} 2796 2797static void 2798hdac_stream_start(struct hdac_chan *ch) 2799{ 2800 struct hdac_softc *sc = ch->devinfo->codec->sc; 2801 uint32_t ctl; 2802 2803 ch->flags |= HDAC_CHN_RUNNING; 2804 2805 if (sc->polling != 0) 2806 hdac_poll_reinit(sc); 2807 2808 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2809 ctl |= 1 << (ch->off >> 5); 2810 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2811 2812 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2813 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2814 HDAC_SDCTL_RUN; 2815 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2816} 2817 2818static void 2819hdac_stream_reset(struct hdac_chan *ch) 2820{ 2821 struct hdac_softc *sc = ch->devinfo->codec->sc; 2822 int timeout = 1000; 2823 int to = timeout; 2824 uint32_t ctl; 2825 2826 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2827 ctl |= HDAC_SDCTL_SRST; 2828 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2829 do { 2830 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2831 if (ctl & HDAC_SDCTL_SRST) 2832 break; 2833 DELAY(10); 2834 } while (--to); 2835 if (!(ctl & HDAC_SDCTL_SRST)) { 2836 device_printf(sc->dev, "timeout in reset\n"); 2837 } 2838 ctl &= ~HDAC_SDCTL_SRST; 2839 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2840 to = timeout; 2841 do { 2842 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2843 if (!(ctl & HDAC_SDCTL_SRST)) 2844 break; 2845 DELAY(10); 2846 } while (--to); 2847 if (ctl & HDAC_SDCTL_SRST) 2848 device_printf(sc->dev, "can't reset!\n"); 2849} 2850 2851static void 2852hdac_stream_setid(struct hdac_chan *ch) 2853{ 2854 struct hdac_softc *sc = ch->devinfo->codec->sc; 2855 uint32_t ctl; 2856 2857 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2858 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2859 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2860 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2861} 2862 2863static void 2864hdac_bdl_setup(struct hdac_chan *ch) 2865{ 2866 struct hdac_softc *sc = ch->devinfo->codec->sc; 2867 struct hdac_bdle *bdle; 2868 uint64_t addr; 2869 uint32_t blksz, blkcnt; 2870 int i; 2871 2872 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2873 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2874 2875 blksz = ch->blksz; 2876 blkcnt = ch->blkcnt; 2877 2878 for (i = 0; i < blkcnt; i++, bdle++) { 2879 bdle->addrl = (uint32_t)addr; 2880 bdle->addrh = (uint32_t)(addr >> 32); 2881 bdle->len = blksz; 2882 bdle->ioc = 1; 2883 addr += blksz; 2884 } 2885 2886 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2887 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2888 addr = ch->bdl_dma.dma_paddr; 2889 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2890 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2891 if (ch->dmapos != NULL && 2892 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2893 addr = sc->pos_dma.dma_paddr; 2894 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2895 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2896 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2897 } 2898} 2899 2900static int 2901hdac_bdl_alloc(struct hdac_chan *ch) 2902{ 2903 struct hdac_softc *sc = ch->devinfo->codec->sc; 2904 int rc; 2905 2906 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2907 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2908 if (rc) { 2909 device_printf(sc->dev, "can't alloc bdl\n"); 2910 return (rc); 2911 } 2912 2913 return (0); 2914} 2915 2916static void 2917hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2918 int index, int lmute, int rmute, 2919 int left, int right, int dir) 2920{ 2921 uint16_t v = 0; 2922 2923 if (sc == NULL) 2924 return; 2925 2926 if (left != right || lmute != rmute) { 2927 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2928 (lmute << 7) | left; 2929 hdac_command(sc, 2930 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2931 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2932 (rmute << 7) | right; 2933 } else 2934 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2935 (lmute << 7) | left; 2936 2937 hdac_command(sc, 2938 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2939} 2940 2941static void 2942hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2943 int left, int right) 2944{ 2945 struct hdac_softc *sc; 2946 nid_t nid, cad; 2947 int lmute, rmute; 2948 2949 sc = ctl->widget->devinfo->codec->sc; 2950 cad = ctl->widget->devinfo->codec->cad; 2951 nid = ctl->widget->nid; 2952 2953 /* Save new values if valid. */ 2954 if (mute != HDA_AMP_MUTE_DEFAULT) 2955 ctl->muted = mute; 2956 if (left != HDA_AMP_VOL_DEFAULT) 2957 ctl->left = left; 2958 if (right != HDA_AMP_VOL_DEFAULT) 2959 ctl->right = right; 2960 /* Prepare effective values */ 2961 if (ctl->forcemute) { 2962 lmute = 1; 2963 rmute = 1; 2964 left = 0; 2965 right = 0; 2966 } else { 2967 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2968 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2969 left = ctl->left; 2970 right = ctl->right; 2971 } 2972 /* Apply effective values */ 2973 if (ctl->dir & HDA_CTL_OUT) 2974 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2975 lmute, rmute, left, right, 0); 2976 if (ctl->dir & HDA_CTL_IN) 2977 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2978 lmute, rmute, left, right, 1); 2979} 2980 2981static void 2982hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2983{ 2984 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2985 return; 2986 hdac_command(w->devinfo->codec->sc, 2987 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2988 w->nid, index), w->devinfo->codec->cad); 2989 w->selconn = index; 2990} 2991 2992 2993/**************************************************************************** 2994 * uint32_t hdac_command_sendone_internal 2995 * 2996 * Wrapper function that sends only one command to a given codec 2997 ****************************************************************************/ 2998static uint32_t 2999hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3000{ 3001 struct hdac_command_list cl; 3002 uint32_t response = HDAC_INVALID; 3003 3004 if (!hdac_lockowned(sc)) 3005 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3006 cl.num_commands = 1; 3007 cl.verbs = &verb; 3008 cl.responses = &response; 3009 3010 hdac_command_send_internal(sc, &cl, cad); 3011 3012 return (response); 3013} 3014 3015/**************************************************************************** 3016 * hdac_command_send_internal 3017 * 3018 * Send a command list to the codec via the corb. We queue as much verbs as 3019 * we can and msleep on the codec. When the interrupt get the responses 3020 * back from the rirb, it will wake us up so we can queue the remaining verbs 3021 * if any. 3022 ****************************************************************************/ 3023static void 3024hdac_command_send_internal(struct hdac_softc *sc, 3025 struct hdac_command_list *commands, nid_t cad) 3026{ 3027 struct hdac_codec *codec; 3028 int corbrp; 3029 uint32_t *corb; 3030 int timeout; 3031 int retry = 10; 3032 struct hdac_rirb *rirb_base; 3033 3034 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3035 commands->num_commands < 1) 3036 return; 3037 3038 codec = sc->codecs[cad]; 3039 codec->commands = commands; 3040 codec->responses_received = 0; 3041 codec->verbs_sent = 0; 3042 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3043 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3044 3045 do { 3046 if (codec->verbs_sent != commands->num_commands) { 3047 /* Queue as many verbs as possible */ 3048 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3049#if 0 3050 bus_dmamap_sync(sc->corb_dma.dma_tag, 3051 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3052#endif 3053 while (codec->verbs_sent != commands->num_commands && 3054 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3055 sc->corb_wp++; 3056 sc->corb_wp %= sc->corb_size; 3057 corb[sc->corb_wp] = 3058 commands->verbs[codec->verbs_sent++]; 3059 } 3060 3061 /* Send the verbs to the codecs */ 3062#if 0 3063 bus_dmamap_sync(sc->corb_dma.dma_tag, 3064 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3065#endif 3066 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3067 } 3068 3069 timeout = 1000; 3070 while (hdac_rirb_flush(sc) == 0 && --timeout) 3071 DELAY(10); 3072 } while ((codec->verbs_sent != commands->num_commands || 3073 codec->responses_received != commands->num_commands) && --retry); 3074 3075 if (retry == 0) 3076 device_printf(sc->dev, 3077 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3078 __func__, commands->num_commands, codec->verbs_sent, 3079 codec->responses_received); 3080 3081 codec->commands = NULL; 3082 codec->responses_received = 0; 3083 codec->verbs_sent = 0; 3084 3085 hdac_unsolq_flush(sc); 3086} 3087 3088 3089/**************************************************************************** 3090 * Device Methods 3091 ****************************************************************************/ 3092 3093/**************************************************************************** 3094 * int hdac_probe(device_t) 3095 * 3096 * Probe for the presence of an hdac. If none is found, check for a generic 3097 * match using the subclass of the device. 3098 ****************************************************************************/ 3099static int 3100hdac_probe(device_t dev) 3101{ 3102 int i, result; 3103 uint32_t model; 3104 uint16_t class, subclass; 3105 char desc[64]; 3106 3107 model = (uint32_t)pci_get_device(dev) << 16; 3108 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3109 class = pci_get_class(dev); 3110 subclass = pci_get_subclass(dev); 3111 3112 bzero(desc, sizeof(desc)); 3113 result = ENXIO; 3114 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3115 if (hdac_devices[i].model == model) { 3116 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3117 result = BUS_PROBE_DEFAULT; 3118 break; 3119 } 3120 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3121 class == PCIC_MULTIMEDIA && 3122 subclass == PCIS_MULTIMEDIA_HDA) { 3123 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3124 result = BUS_PROBE_GENERIC; 3125 break; 3126 } 3127 } 3128 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3129 subclass == PCIS_MULTIMEDIA_HDA) { 3130 strlcpy(desc, "Generic", sizeof(desc)); 3131 result = BUS_PROBE_GENERIC; 3132 } 3133 if (result != ENXIO) { 3134 strlcat(desc, " High Definition Audio Controller", 3135 sizeof(desc)); 3136 device_set_desc_copy(dev, desc); 3137 } 3138 3139 return (result); 3140} 3141 3142static void * 3143hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3144 struct pcm_channel *c, int dir) 3145{ 3146 struct hdac_pcm_devinfo *pdevinfo = data; 3147 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3148 struct hdac_softc *sc = devinfo->codec->sc; 3149 struct hdac_chan *ch; 3150 int i, ord = 0, chid; 3151 3152 hdac_lock(sc); 3153 3154 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3155 ch = &sc->chans[chid]; 3156 for (i = 0; i < sc->num_chans && i < chid; i++) { 3157 if (ch->dir == sc->chans[i].dir) 3158 ord++; 3159 } 3160 if (dir == PCMDIR_PLAY) { 3161 ch->off = (sc->num_iss + ord) << 5; 3162 } else { 3163 ch->off = ord << 5; 3164 } 3165 3166 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3167 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3168 ch->pcmrates[0] = 48000; 3169 ch->pcmrates[1] = 0; 3170 } 3171 if (sc->pos_dma.dma_vaddr != NULL) 3172 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3173 (sc->streamcnt * 8)); 3174 else 3175 ch->dmapos = NULL; 3176 ch->sid = ++sc->streamcnt; 3177 ch->dir = dir; 3178 ch->b = b; 3179 ch->c = c; 3180 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3181 ch->blkcnt = pdevinfo->chan_blkcnt; 3182 hdac_unlock(sc); 3183 3184 if (hdac_bdl_alloc(ch) != 0) { 3185 ch->blkcnt = 0; 3186 return (NULL); 3187 } 3188 3189 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3190 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3191 pdevinfo->chan_size) != 0) 3192 return (NULL); 3193 3194 return (ch); 3195} 3196 3197static int 3198hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3199{ 3200 struct hdac_chan *ch = data; 3201 int i; 3202 3203 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3204 if (format == ch->caps.fmtlist[i]) { 3205 ch->fmt = format; 3206 return (0); 3207 } 3208 } 3209 3210 return (EINVAL); 3211} 3212 3213static int 3214hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3215{ 3216 struct hdac_chan *ch = data; 3217 uint32_t spd = 0, threshold; 3218 int i; 3219 3220 for (i = 0; ch->pcmrates[i] != 0; i++) { 3221 spd = ch->pcmrates[i]; 3222 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3223 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3224 if (speed < threshold) 3225 break; 3226 } 3227 3228 if (spd == 0) /* impossible */ 3229 ch->spd = 48000; 3230 else 3231 ch->spd = spd; 3232 3233 return (ch->spd); 3234} 3235 3236static void 3237hdac_stream_setup(struct hdac_chan *ch) 3238{ 3239 struct hdac_softc *sc = ch->devinfo->codec->sc; 3240 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3241 struct hdac_widget *w; 3242 int i, chn, totalchn, c; 3243 nid_t cad = ch->devinfo->codec->cad; 3244 uint16_t fmt, dfmt; 3245 3246 HDA_BOOTHVERBOSE( 3247 device_printf(ch->pdevinfo->dev, 3248 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3249 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3250 ch->fmt, ch->spd); 3251 ); 3252 fmt = 0; 3253 if (ch->fmt & AFMT_S16_LE) 3254 fmt |= ch->bit16 << 4; 3255 else if (ch->fmt & AFMT_S32_LE) 3256 fmt |= ch->bit32 << 4; 3257 else 3258 fmt |= 1 << 4; 3259 3260 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3261 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3262 fmt |= hda_rate_tab[i].base; 3263 fmt |= hda_rate_tab[i].mul; 3264 fmt |= hda_rate_tab[i].div; 3265 break; 3266 } 3267 } 3268 3269 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3270 fmt |= 1; 3271 totalchn = 2; 3272 } else 3273 totalchn = 1; 3274 3275 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3276 3277 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3278 if (ch->fmt & AFMT_AC3) 3279 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3280 3281 chn = 0; 3282 for (i = 0; ch->io[i] != -1; i++) { 3283 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3284 if (w == NULL) 3285 continue; 3286 3287 if (as->hpredir >= 0 && i == as->pincnt) 3288 chn = 0; 3289 HDA_BOOTHVERBOSE( 3290 device_printf(ch->pdevinfo->dev, 3291 "PCMDIR_%s: Stream setup nid=%d: " 3292 "fmt=0x%04x, dfmt=0x%04x\n", 3293 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3294 ch->io[i], fmt, dfmt); 3295 ); 3296 hdac_command(sc, 3297 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3298 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3299 hdac_command(sc, 3300 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3301 cad); 3302 } 3303 /* If HP redirection is enabled, but failed to use same 3304 DAC make last DAC one to duplicate first one. */ 3305 if (as->hpredir >= 0 && i == as->pincnt) { 3306 c = (ch->sid << 4); 3307 } else if (chn >= totalchn) { 3308 /* This is until OSS will support multichannel. 3309 Should be: c = 0; to disable unused DAC */ 3310 c = (ch->sid << 4); 3311 }else { 3312 c = (ch->sid << 4) | chn; 3313 } 3314 hdac_command(sc, 3315 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3316 chn += 3317 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3318 2 : 1; 3319 } 3320} 3321 3322static int 3323hdac_channel_setfragments(kobj_t obj, void *data, 3324 uint32_t blksz, uint32_t blkcnt) 3325{ 3326 struct hdac_chan *ch = data; 3327 struct hdac_softc *sc = ch->devinfo->codec->sc; 3328 3329 blksz &= HDA_BLK_ALIGN; 3330 3331 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3332 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3333 if (blksz < HDA_BLK_MIN) 3334 blksz = HDA_BLK_MIN; 3335 if (blkcnt > HDA_BDL_MAX) 3336 blkcnt = HDA_BDL_MAX; 3337 if (blkcnt < HDA_BDL_MIN) 3338 blkcnt = HDA_BDL_MIN; 3339 3340 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3341 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3342 blkcnt >>= 1; 3343 else if ((blksz >> 1) >= HDA_BLK_MIN) 3344 blksz >>= 1; 3345 else 3346 break; 3347 } 3348 3349 if ((sndbuf_getblksz(ch->b) != blksz || 3350 sndbuf_getblkcnt(ch->b) != blkcnt) && 3351 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3352 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3353 __func__, blksz, blkcnt); 3354 3355 ch->blksz = sndbuf_getblksz(ch->b); 3356 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3357 3358 return (1); 3359} 3360 3361static int 3362hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3363{ 3364 struct hdac_chan *ch = data; 3365 3366 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3367 3368 return (ch->blksz); 3369} 3370 3371static void 3372hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3373{ 3374 struct hdac_devinfo *devinfo = ch->devinfo; 3375 struct hdac_widget *w; 3376 nid_t cad = devinfo->codec->cad; 3377 int i; 3378 3379 hdac_stream_stop(ch); 3380 3381 for (i = 0; ch->io[i] != -1; i++) { 3382 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3383 if (w == NULL) 3384 continue; 3385 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3386 hdac_command(sc, 3387 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3388 cad); 3389 } 3390 hdac_command(sc, 3391 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3392 0), cad); 3393 } 3394} 3395 3396static void 3397hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3398{ 3399 ch->ptr = 0; 3400 ch->prevptr = 0; 3401 hdac_stream_stop(ch); 3402 hdac_stream_reset(ch); 3403 hdac_bdl_setup(ch); 3404 hdac_stream_setid(ch); 3405 hdac_stream_setup(ch); 3406 hdac_stream_start(ch); 3407} 3408 3409static int 3410hdac_channel_trigger(kobj_t obj, void *data, int go) 3411{ 3412 struct hdac_chan *ch = data; 3413 struct hdac_softc *sc = ch->devinfo->codec->sc; 3414 3415 if (!PCMTRIG_COMMON(go)) 3416 return (0); 3417 3418 hdac_lock(sc); 3419 switch (go) { 3420 case PCMTRIG_START: 3421 hdac_channel_start(sc, ch); 3422 break; 3423 case PCMTRIG_STOP: 3424 case PCMTRIG_ABORT: 3425 hdac_channel_stop(sc, ch); 3426 break; 3427 default: 3428 break; 3429 } 3430 hdac_unlock(sc); 3431 3432 return (0); 3433} 3434 3435static int 3436hdac_channel_getptr(kobj_t obj, void *data) 3437{ 3438 struct hdac_chan *ch = data; 3439 struct hdac_softc *sc = ch->devinfo->codec->sc; 3440 uint32_t ptr; 3441 3442 hdac_lock(sc); 3443 if (sc->polling != 0) 3444 ptr = ch->ptr; 3445 else if (ch->dmapos != NULL) 3446 ptr = *(ch->dmapos); 3447 else 3448 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3449 hdac_unlock(sc); 3450 3451 /* 3452 * Round to available space and force 128 bytes aligment. 3453 */ 3454 ptr %= ch->blksz * ch->blkcnt; 3455 ptr &= HDA_BLK_ALIGN; 3456 3457 return (ptr); 3458} 3459 3460static struct pcmchan_caps * 3461hdac_channel_getcaps(kobj_t obj, void *data) 3462{ 3463 return (&((struct hdac_chan *)data)->caps); 3464} 3465 3466static kobj_method_t hdac_channel_methods[] = { 3467 KOBJMETHOD(channel_init, hdac_channel_init), 3468 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3469 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3470 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3471 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3472 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3473 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3474 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3475 { 0, 0 } 3476}; 3477CHANNEL_DECLARE(hdac_channel); 3478 3479static int 3480hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3481{ 3482 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3483 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3484 struct hdac_softc *sc = devinfo->codec->sc; 3485 struct hdac_widget *w, *cw; 3486 struct hdac_audio_ctl *ctl; 3487 uint32_t mask, recmask, id; 3488 int i, j, softpcmvol; 3489 3490 hdac_lock(sc); 3491 3492 /* Make sure that in case of soft volume it won't stay muted. */ 3493 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3494 pdevinfo->left[i] = 100; 3495 pdevinfo->right[i] = 100; 3496 } 3497 3498 mask = 0; 3499 recmask = 0; 3500 id = hdac_codec_id(devinfo->codec); 3501 3502 /* Declate EAPD as ogain control. */ 3503 if (pdevinfo->play >= 0) { 3504 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3505 w = hdac_widget_get(devinfo, i); 3506 if (w == NULL || w->enable == 0) 3507 continue; 3508 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3509 w->param.eapdbtl == HDAC_INVALID || 3510 w->bindas != sc->chans[pdevinfo->play].as) 3511 continue; 3512 mask |= SOUND_MASK_OGAIN; 3513 break; 3514 } 3515 } 3516 3517 /* Declare volume controls assigned to this association. */ 3518 i = 0; 3519 ctl = NULL; 3520 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3521 if (ctl->enable == 0) 3522 continue; 3523 if ((pdevinfo->play >= 0 && 3524 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3525 (pdevinfo->rec >= 0 && 3526 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3527 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3528 mask |= ctl->ossmask; 3529 } 3530 3531 /* Declare record sources available to this association. */ 3532 if (pdevinfo->rec >= 0) { 3533 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3534 for (i = 0; ch->io[i] != -1; i++) { 3535 w = hdac_widget_get(devinfo, ch->io[i]); 3536 if (w == NULL || w->enable == 0) 3537 continue; 3538 for (j = 0; j < w->nconns; j++) { 3539 if (w->connsenable[j] == 0) 3540 continue; 3541 cw = hdac_widget_get(devinfo, w->conns[j]); 3542 if (cw == NULL || cw->enable == 0) 3543 continue; 3544 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3545 cw->bindas != -2) 3546 continue; 3547 recmask |= cw->ossmask; 3548 } 3549 } 3550 } 3551 3552 /* Declare soft PCM volume if needed. */ 3553 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3554 ctl = NULL; 3555 if ((mask & SOUND_MASK_PCM) == 0 || 3556 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3557 softpcmvol = 1; 3558 mask |= SOUND_MASK_PCM; 3559 } else { 3560 softpcmvol = 0; 3561 i = 0; 3562 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3563 if (ctl->enable == 0) 3564 continue; 3565 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3566 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3567 continue; 3568 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3569 continue; 3570 if (ctl->step > 0) 3571 break; 3572 } 3573 } 3574 3575 if (softpcmvol == 1 || ctl == NULL) { 3576 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3577 HDA_BOOTVERBOSE( 3578 device_printf(pdevinfo->dev, 3579 "%s Soft PCM volume\n", 3580 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3581 ); 3582 } 3583 } 3584 3585 /* Declare master volume if needed. */ 3586 if (pdevinfo->play >= 0) { 3587 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3588 SOUND_MASK_PCM) { 3589 mask |= SOUND_MASK_VOLUME; 3590 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3591 SOUND_MASK_PCM); 3592 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3593 SOUND_MIXER_NONE); 3594 HDA_BOOTVERBOSE( 3595 device_printf(pdevinfo->dev, 3596 "Forcing master volume with PCM\n"); 3597 ); 3598 } 3599 } 3600 3601 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3602 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3603 3604 mix_setrecdevs(m, recmask); 3605 mix_setdevs(m, mask); 3606 3607 hdac_unlock(sc); 3608 3609 return (0); 3610} 3611 3612static int 3613hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3614 unsigned left, unsigned right) 3615{ 3616 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3617 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3618 struct hdac_softc *sc = devinfo->codec->sc; 3619 struct hdac_widget *w; 3620 struct hdac_audio_ctl *ctl; 3621 uint32_t mute; 3622 int lvol, rvol; 3623 int i, j; 3624 3625 hdac_lock(sc); 3626 /* Save new values. */ 3627 pdevinfo->left[dev] = left; 3628 pdevinfo->right[dev] = right; 3629 3630 /* 'ogain' is the special case implemented with EAPD. */ 3631 if (dev == SOUND_MIXER_OGAIN) { 3632 uint32_t orig; 3633 w = NULL; 3634 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3635 w = hdac_widget_get(devinfo, i); 3636 if (w == NULL || w->enable == 0) 3637 continue; 3638 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3639 w->param.eapdbtl == HDAC_INVALID) 3640 continue; 3641 break; 3642 } 3643 if (i >= devinfo->endnode) { 3644 hdac_unlock(sc); 3645 return (-1); 3646 } 3647 orig = w->param.eapdbtl; 3648 if (left == 0) 3649 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3650 else 3651 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3652 if (orig != w->param.eapdbtl) { 3653 uint32_t val; 3654 3655 val = w->param.eapdbtl; 3656 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3657 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3658 hdac_command(sc, 3659 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3660 w->nid, val), devinfo->codec->cad); 3661 } 3662 hdac_unlock(sc); 3663 return (left | (left << 8)); 3664 } 3665 3666 /* Recalculate all controls related to this OSS device. */ 3667 i = 0; 3668 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3669 if (ctl->enable == 0 || 3670 !(ctl->ossmask & (1 << dev))) 3671 continue; 3672 if (!((pdevinfo->play >= 0 && 3673 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3674 (pdevinfo->rec >= 0 && 3675 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3676 ctl->widget->bindas == -2)) 3677 continue; 3678 3679 lvol = 100; 3680 rvol = 100; 3681 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3682 if (ctl->ossmask & (1 << j)) { 3683 lvol = lvol * pdevinfo->left[j] / 100; 3684 rvol = rvol * pdevinfo->right[j] / 100; 3685 } 3686 } 3687 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3688 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3689 lvol = (lvol * ctl->step + 50) / 100; 3690 rvol = (rvol * ctl->step + 50) / 100; 3691 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3692 } 3693 hdac_unlock(sc); 3694 3695 return (left | (right << 8)); 3696} 3697 3698/* 3699 * Commutate specified record source. 3700 */ 3701static uint32_t 3702hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3703{ 3704 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3705 struct hdac_widget *w, *cw; 3706 struct hdac_audio_ctl *ctl; 3707 char buf[64]; 3708 int i, muted; 3709 uint32_t res = 0; 3710 3711 if (depth > HDA_PARSE_MAXDEPTH) 3712 return (0); 3713 3714 w = hdac_widget_get(devinfo, nid); 3715 if (w == NULL || w->enable == 0) 3716 return (0); 3717 3718 for (i = 0; i < w->nconns; i++) { 3719 if (w->connsenable[i] == 0) 3720 continue; 3721 cw = hdac_widget_get(devinfo, w->conns[i]); 3722 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3723 continue; 3724 /* Call recursively to trace signal to it's source if needed. */ 3725 if ((src & cw->ossmask) != 0) { 3726 if (cw->ossdev < 0) { 3727 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3728 w->conns[i], depth + 1); 3729 } else { 3730 res |= cw->ossmask; 3731 } 3732 } 3733 /* We have two special cases: mixers and others (selectors). */ 3734 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3735 ctl = hdac_audio_ctl_amp_get(devinfo, 3736 w->nid, HDA_CTL_IN, i, 1); 3737 if (ctl == NULL) 3738 continue; 3739 /* If we have input control on this node mute them 3740 * according to requested sources. */ 3741 muted = (src & cw->ossmask) ? 0 : 1; 3742 if (muted != ctl->forcemute) { 3743 ctl->forcemute = muted; 3744 hdac_audio_ctl_amp_set(ctl, 3745 HDA_AMP_MUTE_DEFAULT, 3746 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3747 } 3748 HDA_BOOTHVERBOSE( 3749 device_printf(pdevinfo->dev, 3750 "Recsel (%s): nid %d source %d %s\n", 3751 hdac_audio_ctl_ossmixer_mask2allname( 3752 src, buf, sizeof(buf)), 3753 nid, i, muted?"mute":"unmute"); 3754 ); 3755 } else { 3756 if (w->nconns == 1) 3757 break; 3758 if ((src & cw->ossmask) == 0) 3759 continue; 3760 /* If we found requested source - select it and exit. */ 3761 hdac_widget_connection_select(w, i); 3762 HDA_BOOTHVERBOSE( 3763 device_printf(pdevinfo->dev, 3764 "Recsel (%s): nid %d source %d select\n", 3765 hdac_audio_ctl_ossmixer_mask2allname( 3766 src, buf, sizeof(buf)), 3767 nid, i); 3768 ); 3769 break; 3770 } 3771 } 3772 return (res); 3773} 3774 3775static uint32_t 3776hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3777{ 3778 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3779 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3780 struct hdac_widget *w; 3781 struct hdac_softc *sc = devinfo->codec->sc; 3782 struct hdac_chan *ch; 3783 int i; 3784 uint32_t ret = 0xffffffff; 3785 3786 hdac_lock(sc); 3787 3788 /* Commutate requested recsrc for each ADC. */ 3789 ch = &sc->chans[pdevinfo->rec]; 3790 for (i = 0; ch->io[i] != -1; i++) { 3791 w = hdac_widget_get(devinfo, ch->io[i]); 3792 if (w == NULL || w->enable == 0) 3793 continue; 3794 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3795 } 3796 3797 hdac_unlock(sc); 3798 3799 return ((ret == 0xffffffff)? 0 : ret); 3800} 3801 3802static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3803 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3804 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3805 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3806 { 0, 0 } 3807}; 3808MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3809 3810static void 3811hdac_unsolq_task(void *context, int pending) 3812{ 3813 struct hdac_softc *sc; 3814 3815 sc = (struct hdac_softc *)context; 3816 3817 hdac_lock(sc); 3818 hdac_unsolq_flush(sc); 3819 hdac_unlock(sc); 3820} 3821 3822/**************************************************************************** 3823 * int hdac_attach(device_t) 3824 * 3825 * Attach the device into the kernel. Interrupts usually won't be enabled 3826 * when this function is called. Setup everything that doesn't require 3827 * interrupts and defer probing of codecs until interrupts are enabled. 3828 ****************************************************************************/ 3829static int 3830hdac_attach(device_t dev) 3831{ 3832 struct hdac_softc *sc; 3833 int result; 3834 int i; 3835 uint16_t vendor; 3836 uint8_t v; 3837 3838 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3839 3840 sc = device_get_softc(dev); 3841 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3842 sc->dev = dev; 3843 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3844 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3845 vendor = pci_get_vendor(dev); 3846 3847 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3848 /* Screw nx6325 - subdevice/subvendor swapped */ 3849 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3850 } 3851 3852 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3853 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3854 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3855 3856 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3857 3858 sc->poll_ticks = 1000000; 3859 sc->poll_ival = HDAC_POLL_INTERVAL; 3860 if (resource_int_value(device_get_name(dev), 3861 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3862 sc->polling = 1; 3863 else 3864 sc->polling = 0; 3865 3866 result = bus_dma_tag_create(NULL, /* parent */ 3867 HDAC_DMA_ALIGNMENT, /* alignment */ 3868 0, /* boundary */ 3869 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3870 BUS_SPACE_MAXADDR, /* highaddr */ 3871 NULL, /* filtfunc */ 3872 NULL, /* fistfuncarg */ 3873 HDA_BUFSZ_MAX, /* maxsize */ 3874 1, /* nsegments */ 3875 HDA_BUFSZ_MAX, /* maxsegsz */ 3876 0, /* flags */ 3877 NULL, /* lockfunc */ 3878 NULL, /* lockfuncarg */ 3879 &sc->chan_dmat); /* dmat */ 3880 if (result != 0) { 3881 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3882 __func__, result); 3883 snd_mtxfree(sc->lock); 3884 free(sc, M_DEVBUF); 3885 return (ENXIO); 3886 } 3887 3888 3889 sc->hdabus = NULL; 3890 for (i = 0; i < HDAC_CODEC_MAX; i++) 3891 sc->codecs[i] = NULL; 3892 3893 pci_enable_busmaster(dev); 3894 3895 if (vendor == INTEL_VENDORID) { 3896 /* TCSEL -> TC0 */ 3897 v = pci_read_config(dev, 0x44, 1); 3898 pci_write_config(dev, 0x44, v & 0xf8, 1); 3899 HDA_BOOTHVERBOSE( 3900 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3901 pci_read_config(dev, 0x44, 1)); 3902 ); 3903 } 3904 3905#ifdef HDAC_MSI_ENABLED 3906 if (resource_int_value(device_get_name(dev), 3907 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3908 pci_msi_count(dev) == 1) 3909 sc->flags |= HDAC_F_MSI; 3910 else 3911#endif 3912 sc->flags &= ~HDAC_F_MSI; 3913 3914#if defined(__i386__) || defined(__amd64__) 3915 sc->flags |= HDAC_F_DMA_NOCACHE; 3916 3917 if (resource_int_value(device_get_name(dev), 3918 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3919#else 3920 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3921#endif 3922 /* 3923 * Try to enable PCIe snoop to avoid messing around with 3924 * uncacheable DMA attribute. Since PCIe snoop register 3925 * config is pretty much vendor specific, there are no 3926 * general solutions on how to enable it, forcing us (even 3927 * Microsoft) to enable uncacheable or write combined DMA 3928 * by default. 3929 * 3930 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3931 */ 3932 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3933 if (hdac_pcie_snoop[i].vendor != vendor) 3934 continue; 3935 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3936 if (hdac_pcie_snoop[i].reg == 0x00) 3937 break; 3938 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3939 if ((v & hdac_pcie_snoop[i].enable) == 3940 hdac_pcie_snoop[i].enable) 3941 break; 3942 v &= hdac_pcie_snoop[i].mask; 3943 v |= hdac_pcie_snoop[i].enable; 3944 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3945 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3946 if ((v & hdac_pcie_snoop[i].enable) != 3947 hdac_pcie_snoop[i].enable) { 3948 HDA_BOOTVERBOSE( 3949 device_printf(dev, 3950 "WARNING: Failed to enable PCIe " 3951 "snoop!\n"); 3952 ); 3953#if defined(__i386__) || defined(__amd64__) 3954 sc->flags |= HDAC_F_DMA_NOCACHE; 3955#endif 3956 } 3957 break; 3958 } 3959#if defined(__i386__) || defined(__amd64__) 3960 } 3961#endif 3962 3963 HDA_BOOTHVERBOSE( 3964 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3965 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3966 "Uncacheable" : "PCIe snoop", vendor); 3967 ); 3968 3969 /* Allocate resources */ 3970 result = hdac_mem_alloc(sc); 3971 if (result != 0) 3972 goto hdac_attach_fail; 3973 result = hdac_irq_alloc(sc); 3974 if (result != 0) 3975 goto hdac_attach_fail; 3976 3977 /* Get Capabilities */ 3978 result = hdac_get_capabilities(sc); 3979 if (result != 0) 3980 goto hdac_attach_fail; 3981 3982 /* Allocate CORB and RIRB dma memory */ 3983 result = hdac_dma_alloc(sc, &sc->corb_dma, 3984 sc->corb_size * sizeof(uint32_t)); 3985 if (result != 0) 3986 goto hdac_attach_fail; 3987 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3988 sc->rirb_size * sizeof(struct hdac_rirb)); 3989 if (result != 0) 3990 goto hdac_attach_fail; 3991 3992 /* Quiesce everything */ 3993 HDA_BOOTHVERBOSE( 3994 device_printf(dev, "Reset controller...\n"); 3995 ); 3996 hdac_reset(sc, 1); 3997 3998 /* Initialize the CORB and RIRB */ 3999 hdac_corb_init(sc); 4000 hdac_rirb_init(sc); 4001 4002 /* Defer remaining of initialization until interrupts are enabled */ 4003 sc->intrhook.ich_func = hdac_attach2; 4004 sc->intrhook.ich_arg = (void *)sc; 4005 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4006 sc->intrhook.ich_func = NULL; 4007 hdac_attach2((void *)sc); 4008 } 4009 4010 return (0); 4011 4012hdac_attach_fail: 4013 hdac_irq_free(sc); 4014 hdac_dma_free(sc, &sc->rirb_dma); 4015 hdac_dma_free(sc, &sc->corb_dma); 4016 hdac_mem_free(sc); 4017 snd_mtxfree(sc->lock); 4018 free(sc, M_DEVBUF); 4019 4020 return (ENXIO); 4021} 4022 4023static void 4024hdac_audio_parse(struct hdac_devinfo *devinfo) 4025{ 4026 struct hdac_codec *codec = devinfo->codec; 4027 struct hdac_softc *sc = codec->sc; 4028 struct hdac_widget *w; 4029 uint32_t res; 4030 int i; 4031 nid_t cad, nid; 4032 4033 cad = devinfo->codec->cad; 4034 nid = devinfo->nid; 4035 4036 res = hdac_command(sc, 4037 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4038 devinfo->function.audio.gpio = res; 4039 4040 HDA_BOOTVERBOSE( 4041 device_printf(sc->dev, "GPIO: 0x%08x " 4042 "NumGPIO=%d NumGPO=%d " 4043 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4044 devinfo->function.audio.gpio, 4045 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4046 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4047 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4048 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4049 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4050 ); 4051 4052 res = hdac_command(sc, 4053 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4054 cad); 4055 devinfo->function.audio.supp_stream_formats = res; 4056 4057 res = hdac_command(sc, 4058 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4059 cad); 4060 devinfo->function.audio.supp_pcm_size_rate = res; 4061 4062 res = hdac_command(sc, 4063 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4064 cad); 4065 devinfo->function.audio.outamp_cap = res; 4066 4067 res = hdac_command(sc, 4068 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4069 cad); 4070 devinfo->function.audio.inamp_cap = res; 4071 4072 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4073 w = hdac_widget_get(devinfo, i); 4074 if (w == NULL) 4075 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4076 else { 4077 w->devinfo = devinfo; 4078 w->nid = i; 4079 w->enable = 1; 4080 w->selconn = -1; 4081 w->pflags = 0; 4082 w->ossdev = -1; 4083 w->bindas = -1; 4084 w->param.eapdbtl = HDAC_INVALID; 4085 hdac_widget_parse(w); 4086 } 4087 } 4088} 4089 4090static void 4091hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4092{ 4093 struct hdac_softc *sc = devinfo->codec->sc; 4094 struct hdac_audio_ctl *ctls; 4095 struct hdac_widget *w, *cw; 4096 int i, j, cnt, max, ocap, icap; 4097 int mute, offset, step, size; 4098 4099 /* XXX This is redundant */ 4100 max = 0; 4101 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4102 w = hdac_widget_get(devinfo, i); 4103 if (w == NULL || w->enable == 0) 4104 continue; 4105 if (w->param.outamp_cap != 0) 4106 max++; 4107 if (w->param.inamp_cap != 0) { 4108 switch (w->type) { 4109 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4110 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4111 for (j = 0; j < w->nconns; j++) { 4112 cw = hdac_widget_get(devinfo, 4113 w->conns[j]); 4114 if (cw == NULL || cw->enable == 0) 4115 continue; 4116 max++; 4117 } 4118 break; 4119 default: 4120 max++; 4121 break; 4122 } 4123 } 4124 } 4125 4126 devinfo->function.audio.ctlcnt = max; 4127 4128 if (max < 1) 4129 return; 4130 4131 ctls = (struct hdac_audio_ctl *)malloc( 4132 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4133 4134 if (ctls == NULL) { 4135 /* Blekh! */ 4136 device_printf(sc->dev, "unable to allocate ctls!\n"); 4137 devinfo->function.audio.ctlcnt = 0; 4138 return; 4139 } 4140 4141 cnt = 0; 4142 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4143 if (cnt >= max) { 4144 device_printf(sc->dev, "%s: Ctl overflow!\n", 4145 __func__); 4146 break; 4147 } 4148 w = hdac_widget_get(devinfo, i); 4149 if (w == NULL || w->enable == 0) 4150 continue; 4151 ocap = w->param.outamp_cap; 4152 icap = w->param.inamp_cap; 4153 if (ocap != 0) { 4154 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4155 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4156 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4157 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4158 /*if (offset > step) { 4159 HDA_BOOTVERBOSE( 4160 device_printf(sc->dev, 4161 "BUGGY outamp: nid=%d " 4162 "[offset=%d > step=%d]\n", 4163 w->nid, offset, step); 4164 ); 4165 offset = step; 4166 }*/ 4167 ctls[cnt].enable = 1; 4168 ctls[cnt].widget = w; 4169 ctls[cnt].mute = mute; 4170 ctls[cnt].step = step; 4171 ctls[cnt].size = size; 4172 ctls[cnt].offset = offset; 4173 ctls[cnt].left = offset; 4174 ctls[cnt].right = offset; 4175 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4176 w->waspin) 4177 ctls[cnt].ndir = HDA_CTL_IN; 4178 else 4179 ctls[cnt].ndir = HDA_CTL_OUT; 4180 ctls[cnt++].dir = HDA_CTL_OUT; 4181 } 4182 4183 if (icap != 0) { 4184 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4185 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4186 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4187 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4188 /*if (offset > step) { 4189 HDA_BOOTVERBOSE( 4190 device_printf(sc->dev, 4191 "BUGGY inamp: nid=%d " 4192 "[offset=%d > step=%d]\n", 4193 w->nid, offset, step); 4194 ); 4195 offset = step; 4196 }*/ 4197 switch (w->type) { 4198 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4199 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4200 for (j = 0; j < w->nconns; j++) { 4201 if (cnt >= max) { 4202 device_printf(sc->dev, 4203 "%s: Ctl overflow!\n", 4204 __func__); 4205 break; 4206 } 4207 cw = hdac_widget_get(devinfo, 4208 w->conns[j]); 4209 if (cw == NULL || cw->enable == 0) 4210 continue; 4211 ctls[cnt].enable = 1; 4212 ctls[cnt].widget = w; 4213 ctls[cnt].childwidget = cw; 4214 ctls[cnt].index = j; 4215 ctls[cnt].mute = mute; 4216 ctls[cnt].step = step; 4217 ctls[cnt].size = size; 4218 ctls[cnt].offset = offset; 4219 ctls[cnt].left = offset; 4220 ctls[cnt].right = offset; 4221 ctls[cnt].ndir = HDA_CTL_IN; 4222 ctls[cnt++].dir = HDA_CTL_IN; 4223 } 4224 break; 4225 default: 4226 if (cnt >= max) { 4227 device_printf(sc->dev, 4228 "%s: Ctl overflow!\n", 4229 __func__); 4230 break; 4231 } 4232 ctls[cnt].enable = 1; 4233 ctls[cnt].widget = w; 4234 ctls[cnt].mute = mute; 4235 ctls[cnt].step = step; 4236 ctls[cnt].size = size; 4237 ctls[cnt].offset = offset; 4238 ctls[cnt].left = offset; 4239 ctls[cnt].right = offset; 4240 if (w->type == 4241 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4242 ctls[cnt].ndir = HDA_CTL_OUT; 4243 else 4244 ctls[cnt].ndir = HDA_CTL_IN; 4245 ctls[cnt++].dir = HDA_CTL_IN; 4246 break; 4247 } 4248 } 4249 } 4250 4251 devinfo->function.audio.ctl = ctls; 4252} 4253 4254static void 4255hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4256{ 4257 struct hdac_softc *sc = devinfo->codec->sc; 4258 struct hdac_audio_as *as; 4259 struct hdac_widget *w; 4260 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4261 4262 /* Count present associations */ 4263 max = 0; 4264 for (j = 1; j < 16; j++) { 4265 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4266 w = hdac_widget_get(devinfo, i); 4267 if (w == NULL || w->enable == 0) 4268 continue; 4269 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4270 continue; 4271 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4272 != j) 4273 continue; 4274 max++; 4275 if (j != 15) /* There could be many 1-pin assocs #15 */ 4276 break; 4277 } 4278 } 4279 4280 devinfo->function.audio.ascnt = max; 4281 4282 if (max < 1) 4283 return; 4284 4285 as = (struct hdac_audio_as *)malloc( 4286 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4287 4288 if (as == NULL) { 4289 /* Blekh! */ 4290 device_printf(sc->dev, "unable to allocate assocs!\n"); 4291 devinfo->function.audio.ascnt = 0; 4292 return; 4293 } 4294 4295 for (i = 0; i < max; i++) { 4296 as[i].hpredir = -1; 4297 as[i].chan = -1; 4298 as[i].digital = 1; 4299 } 4300 4301 /* Scan associations skipping as=0. */ 4302 cnt = 0; 4303 for (j = 1; j < 16; j++) { 4304 first = 16; 4305 hpredir = 0; 4306 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4307 w = hdac_widget_get(devinfo, i); 4308 if (w == NULL || w->enable == 0) 4309 continue; 4310 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4311 continue; 4312 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4313 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4314 if (assoc != j) { 4315 continue; 4316 } 4317 KASSERT(cnt < max, 4318 ("%s: Associations owerflow (%d of %d)", 4319 __func__, cnt, max)); 4320 type = w->wclass.pin.config & 4321 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4322 /* Get pin direction. */ 4323 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4324 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4325 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4326 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4327 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4328 dir = HDA_CTL_OUT; 4329 else 4330 dir = HDA_CTL_IN; 4331 /* If this is a first pin - create new association. */ 4332 if (as[cnt].pincnt == 0) { 4333 as[cnt].enable = 1; 4334 as[cnt].index = j; 4335 as[cnt].dir = dir; 4336 } 4337 if (seq < first) 4338 first = seq; 4339 /* Check association correctness. */ 4340 if (as[cnt].pins[seq] != 0) { 4341 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4342 "in association %d! Disabling association.\n", 4343 __func__, seq, w->nid, j); 4344 as[cnt].enable = 0; 4345 } 4346 if (dir != as[cnt].dir) { 4347 device_printf(sc->dev, "%s: Pin %d has wrong " 4348 "direction for association %d! Disabling " 4349 "association.\n", 4350 __func__, w->nid, j); 4351 as[cnt].enable = 0; 4352 } 4353 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4354 as[cnt].digital = 0; 4355 /* Headphones with seq=15 may mean redirection. */ 4356 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4357 seq == 15) 4358 hpredir = 1; 4359 as[cnt].pins[seq] = w->nid; 4360 as[cnt].pincnt++; 4361 /* Association 15 is a multiple unassociated pins. */ 4362 if (j == 15) 4363 cnt++; 4364 } 4365 if (j != 15 && as[cnt].pincnt > 0) { 4366 if (hpredir && as[cnt].pincnt > 1) 4367 as[cnt].hpredir = first; 4368 cnt++; 4369 } 4370 } 4371 HDA_BOOTVERBOSE( 4372 device_printf(sc->dev, 4373 "%d associations found:\n", max); 4374 for (i = 0; i < max; i++) { 4375 device_printf(sc->dev, 4376 "Association %d (%d) %s%s:\n", 4377 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4378 as[i].enable?"":" (disabled)"); 4379 for (j = 0; j < 16; j++) { 4380 if (as[i].pins[j] == 0) 4381 continue; 4382 device_printf(sc->dev, 4383 " Pin nid=%d seq=%d\n", 4384 as[i].pins[j], j); 4385 } 4386 } 4387 ); 4388 4389 devinfo->function.audio.as = as; 4390} 4391 4392static const struct { 4393 uint32_t model; 4394 uint32_t id; 4395 uint32_t set, unset; 4396} hdac_quirks[] = { 4397 /* 4398 * XXX Force stereo quirk. Monoural recording / playback 4399 * on few codecs (especially ALC880) seems broken or 4400 * perhaps unsupported. 4401 */ 4402 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4403 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4404 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4405 HDA_QUIRK_GPIO0, 0 }, 4406 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4407 HDA_QUIRK_GPIO0, 0 }, 4408 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4409 HDA_QUIRK_GPIO0, 0 }, 4410 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4411 HDA_QUIRK_GPIO0, 0 }, 4412 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4413 HDA_QUIRK_GPIO0, 0 }, 4414 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4415 HDA_QUIRK_GPIO0, 0 }, 4416 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4417 HDA_QUIRK_EAPDINV, 0 }, 4418 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4419 HDA_QUIRK_EAPDINV, 0 }, 4420 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4421 HDA_QUIRK_OVREF, 0 }, 4422 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4423 HDA_QUIRK_OVREF, 0 }, 4424 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4425 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4426 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4427 HDA_QUIRK_GPIO1, 0 }, 4428 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4429 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4430 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4431 HDA_QUIRK_EAPDINV, 0 }, 4432 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4433 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4434 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4435 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4436 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4437 HDA_QUIRK_GPIO0, 0 }, 4438 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4439 HDA_QUIRK_GPIO2, 0 }, 4440 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4441 HDA_QUIRK_GPIO0, 0 }, 4442 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4443 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4444 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4445 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4446 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4447 0, HDA_QUIRK_FORCESTEREO } 4448}; 4449#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4450 4451static void 4452hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4453{ 4454 struct hdac_widget *w; 4455 uint32_t id, subvendor; 4456 int i; 4457 4458 id = hdac_codec_id(devinfo->codec); 4459 subvendor = devinfo->codec->sc->pci_subvendor; 4460 4461 /* 4462 * Quirks 4463 */ 4464 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4465 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4466 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4467 continue; 4468 if (hdac_quirks[i].set != 0) 4469 devinfo->function.audio.quirks |= 4470 hdac_quirks[i].set; 4471 if (hdac_quirks[i].unset != 0) 4472 devinfo->function.audio.quirks &= 4473 ~(hdac_quirks[i].unset); 4474 } 4475 4476 switch (id) { 4477 case HDA_CODEC_ALC883: 4478 /* 4479 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4480 * Clear vref cap for jack connectivity. 4481 */ 4482 w = hdac_widget_get(devinfo, 24); 4483 if (w != NULL && w->enable != 0 && w->type == 4484 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4485 (w->wclass.pin.config & 4486 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4487 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4488 w->wclass.pin.cap &= ~( 4489 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4490 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4491 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4492 w = hdac_widget_get(devinfo, 25); 4493 if (w != NULL && w->enable != 0 && w->type == 4494 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4495 (w->wclass.pin.config & 4496 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4497 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4498 w->wclass.pin.cap &= ~( 4499 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4500 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4501 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4502 /* 4503 * nid: 26 = Line-in, leave it alone. 4504 */ 4505 break; 4506 case HDA_CODEC_AD1986A: 4507 if (subvendor == ASUS_A8X_SUBVENDOR) { 4508 /* 4509 * This is just plain ridiculous.. There 4510 * are several A8 series that share the same 4511 * pci id but works differently (EAPD). 4512 */ 4513 w = hdac_widget_get(devinfo, 26); 4514 if (w != NULL && w->type == 4515 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4516 (w->wclass.pin.config & 4517 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4518 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4519 devinfo->function.audio.quirks &= 4520 ~HDA_QUIRK_EAPDINV; 4521 } 4522 break; 4523 case HDA_CODEC_AD1981HD: 4524 /* 4525 * This codec has very unusual design with several 4526 * points inappropriate for the present parser. 4527 */ 4528 /* Disable recording from mono playback mix. */ 4529 w = hdac_widget_get(devinfo, 21); 4530 if (w != NULL) 4531 w->connsenable[3] = 0; 4532 /* Disable rear to front mic mixer, use separately. */ 4533 w = hdac_widget_get(devinfo, 31); 4534 if (w != NULL) 4535 w->enable = 0; 4536 /* Disable playback mixer, use direct bypass. */ 4537 w = hdac_widget_get(devinfo, 14); 4538 if (w != NULL) 4539 w->enable = 0; 4540 break; 4541 } 4542} 4543 4544/* 4545 * Trace path from DAC to pin. 4546 */ 4547static nid_t 4548hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4549 int dupseq, int min, int only, int depth) 4550{ 4551 struct hdac_widget *w; 4552 int i, im = -1; 4553 nid_t m = 0, ret; 4554 4555 if (depth > HDA_PARSE_MAXDEPTH) 4556 return (0); 4557 w = hdac_widget_get(devinfo, nid); 4558 if (w == NULL || w->enable == 0) 4559 return (0); 4560 HDA_BOOTHVERBOSE( 4561 if (!only) { 4562 device_printf(devinfo->codec->sc->dev, 4563 " %*stracing via nid %d\n", 4564 depth + 1, "", w->nid); 4565 } 4566 ); 4567 /* Use only unused widgets */ 4568 if (w->bindas >= 0 && w->bindas != as) { 4569 HDA_BOOTHVERBOSE( 4570 if (!only) { 4571 device_printf(devinfo->codec->sc->dev, 4572 " %*snid %d busy by association %d\n", 4573 depth + 1, "", w->nid, w->bindas); 4574 } 4575 ); 4576 return (0); 4577 } 4578 if (dupseq < 0) { 4579 if (w->bindseqmask != 0) { 4580 HDA_BOOTHVERBOSE( 4581 if (!only) { 4582 device_printf(devinfo->codec->sc->dev, 4583 " %*snid %d busy by seqmask %x\n", 4584 depth + 1, "", w->nid, w->bindseqmask); 4585 } 4586 ); 4587 return (0); 4588 } 4589 } else { 4590 /* If this is headphones - allow duplicate first pin. */ 4591 if (w->bindseqmask != 0 && 4592 (w->bindseqmask & (1 << dupseq)) == 0) { 4593 HDA_BOOTHVERBOSE( 4594 device_printf(devinfo->codec->sc->dev, 4595 " %*snid %d busy by seqmask %x\n", 4596 depth + 1, "", w->nid, w->bindseqmask); 4597 ); 4598 return (0); 4599 } 4600 } 4601 4602 switch (w->type) { 4603 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4604 /* Do not traverse input. AD1988 has digital monitor 4605 for which we are not ready. */ 4606 break; 4607 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4608 /* If we are tracing HP take only dac of first pin. */ 4609 if ((only == 0 || only == w->nid) && 4610 (w->nid >= min) && (dupseq < 0 || w->nid == 4611 devinfo->function.audio.as[as].dacs[dupseq])) 4612 m = w->nid; 4613 break; 4614 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4615 if (depth > 0) 4616 break; 4617 /* Fall */ 4618 default: 4619 /* Find reachable DACs with smallest nid respecting constraints. */ 4620 for (i = 0; i < w->nconns; i++) { 4621 if (w->connsenable[i] == 0) 4622 continue; 4623 if (w->selconn != -1 && w->selconn != i) 4624 continue; 4625 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4626 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4627 if (m == 0 || ret < m) { 4628 m = ret; 4629 im = i; 4630 } 4631 if (only || dupseq >= 0) 4632 break; 4633 } 4634 } 4635 if (m && only && ((w->nconns > 1 && 4636 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4637 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4638 w->selconn = im; 4639 break; 4640 } 4641 if (m && only) { 4642 w->bindas = as; 4643 w->bindseqmask |= (1 << seq); 4644 } 4645 HDA_BOOTHVERBOSE( 4646 if (!only) { 4647 device_printf(devinfo->codec->sc->dev, 4648 " %*snid %d returned %d\n", 4649 depth + 1, "", w->nid, m); 4650 } 4651 ); 4652 return (m); 4653} 4654 4655/* 4656 * Trace path from widget to ADC. 4657 */ 4658static nid_t 4659hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4660 int only, int depth) 4661{ 4662 struct hdac_widget *w, *wc; 4663 int i, j; 4664 nid_t res = 0; 4665 4666 if (depth > HDA_PARSE_MAXDEPTH) 4667 return (0); 4668 w = hdac_widget_get(devinfo, nid); 4669 if (w == NULL || w->enable == 0) 4670 return (0); 4671 HDA_BOOTHVERBOSE( 4672 device_printf(devinfo->codec->sc->dev, 4673 " %*stracing via nid %d\n", 4674 depth + 1, "", w->nid); 4675 ); 4676 /* Use only unused widgets */ 4677 if (w->bindas >= 0 && w->bindas != as) { 4678 HDA_BOOTHVERBOSE( 4679 device_printf(devinfo->codec->sc->dev, 4680 " %*snid %d busy by association %d\n", 4681 depth + 1, "", w->nid, w->bindas); 4682 ); 4683 return (0); 4684 } 4685 4686 switch (w->type) { 4687 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4688 /* If we are tracing HP take only dac of first pin. */ 4689 if (only == w->nid) 4690 res = 1; 4691 break; 4692 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4693 if (depth > 0) 4694 break; 4695 /* Fall */ 4696 default: 4697 /* Try to find reachable ADCs with specified nid. */ 4698 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4699 wc = hdac_widget_get(devinfo, j); 4700 if (wc == NULL || wc->enable == 0) 4701 continue; 4702 for (i = 0; i < wc->nconns; i++) { 4703 if (wc->connsenable[i] == 0) 4704 continue; 4705 if (wc->conns[i] != nid) 4706 continue; 4707 if (hdac_audio_trace_adc(devinfo, as, seq, 4708 j, only, depth + 1) != 0) { 4709 res = 1; 4710 if (((wc->nconns > 1 && 4711 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4712 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4713 wc->selconn == -1) 4714 wc->selconn = i; 4715 } 4716 } 4717 } 4718 break; 4719 } 4720 if (res) { 4721 w->bindas = as; 4722 w->bindseqmask |= (1 << seq); 4723 } 4724 HDA_BOOTHVERBOSE( 4725 device_printf(devinfo->codec->sc->dev, 4726 " %*snid %d returned %d\n", 4727 depth + 1, "", w->nid, res); 4728 ); 4729 return (res); 4730} 4731 4732/* 4733 * Erase trace path of the specified association. 4734 */ 4735static void 4736hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4737{ 4738 struct hdac_widget *w; 4739 int i; 4740 4741 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4742 w = hdac_widget_get(devinfo, i); 4743 if (w == NULL || w->enable == 0) 4744 continue; 4745 if (w->bindas == as) { 4746 if (seq >= 0) { 4747 w->bindseqmask &= ~(1 << seq); 4748 if (w->bindseqmask == 0) { 4749 w->bindas = -1; 4750 w->selconn = -1; 4751 } 4752 } else { 4753 w->bindas = -1; 4754 w->bindseqmask = 0; 4755 w->selconn = -1; 4756 } 4757 } 4758 } 4759} 4760 4761/* 4762 * Trace association path from DAC to output 4763 */ 4764static int 4765hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4766{ 4767 struct hdac_audio_as *ases = devinfo->function.audio.as; 4768 int i, hpredir; 4769 nid_t min, res; 4770 4771 /* Find next pin */ 4772 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4773 ; 4774 /* Check if there is no any left. If so - we succeded. */ 4775 if (i == 16) 4776 return (1); 4777 4778 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4779 min = 0; 4780 res = 0; 4781 do { 4782 HDA_BOOTHVERBOSE( 4783 device_printf(devinfo->codec->sc->dev, 4784 " Tracing pin %d with min nid %d", 4785 ases[as].pins[i], min); 4786 if (hpredir >= 0) 4787 printf(" and hpredir %d", hpredir); 4788 printf("\n"); 4789 ); 4790 /* Trace this pin taking min nid into account. */ 4791 res = hdac_audio_trace_dac(devinfo, as, i, 4792 ases[as].pins[i], hpredir, min, 0, 0); 4793 if (res == 0) { 4794 /* If we failed - return to previous and redo it. */ 4795 HDA_BOOTVERBOSE( 4796 device_printf(devinfo->codec->sc->dev, 4797 " Unable to trace pin %d seq %d with min " 4798 "nid %d", 4799 ases[as].pins[i], i, min); 4800 if (hpredir >= 0) 4801 printf(" and hpredir %d", hpredir); 4802 printf("\n"); 4803 ); 4804 return (0); 4805 } 4806 HDA_BOOTVERBOSE( 4807 device_printf(devinfo->codec->sc->dev, 4808 " Pin %d traced to DAC %d", 4809 ases[as].pins[i], res); 4810 if (hpredir >= 0) 4811 printf(" and hpredir %d", hpredir); 4812 if (ases[as].fakeredir) 4813 printf(" with fake redirection"); 4814 printf("\n"); 4815 ); 4816 /* Trace again to mark the path */ 4817 hdac_audio_trace_dac(devinfo, as, i, 4818 ases[as].pins[i], hpredir, min, res, 0); 4819 ases[as].dacs[i] = res; 4820 /* We succeded, so call next. */ 4821 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4822 return (1); 4823 /* If next failed, we should retry with next min */ 4824 hdac_audio_undo_trace(devinfo, as, i); 4825 ases[as].dacs[i] = 0; 4826 min = res + 1; 4827 } while (1); 4828} 4829 4830/* 4831 * Trace association path from input to ADC 4832 */ 4833static int 4834hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4835{ 4836 struct hdac_audio_as *ases = devinfo->function.audio.as; 4837 struct hdac_widget *w; 4838 int i, j, k; 4839 4840 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4841 w = hdac_widget_get(devinfo, j); 4842 if (w == NULL || w->enable == 0) 4843 continue; 4844 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4845 continue; 4846 if (w->bindas >= 0 && w->bindas != as) 4847 continue; 4848 4849 /* Find next pin */ 4850 for (i = 0; i < 16; i++) { 4851 if (ases[as].pins[i] == 0) 4852 continue; 4853 4854 HDA_BOOTHVERBOSE( 4855 device_printf(devinfo->codec->sc->dev, 4856 " Tracing pin %d to ADC %d\n", 4857 ases[as].pins[i], j); 4858 ); 4859 /* Trace this pin taking goal into account. */ 4860 if (hdac_audio_trace_adc(devinfo, as, i, 4861 ases[as].pins[i], j, 0) == 0) { 4862 /* If we failed - return to previous and redo it. */ 4863 HDA_BOOTVERBOSE( 4864 device_printf(devinfo->codec->sc->dev, 4865 " Unable to trace pin %d to ADC %d, undo traces\n", 4866 ases[as].pins[i], j); 4867 ); 4868 hdac_audio_undo_trace(devinfo, as, -1); 4869 for (k = 0; k < 16; k++) 4870 ases[as].dacs[k] = 0; 4871 break; 4872 } 4873 HDA_BOOTVERBOSE( 4874 device_printf(devinfo->codec->sc->dev, 4875 " Pin %d traced to ADC %d\n", 4876 ases[as].pins[i], j); 4877 ); 4878 ases[as].dacs[i] = j; 4879 } 4880 if (i == 16) 4881 return (1); 4882 } 4883 return (0); 4884} 4885 4886/* 4887 * Trace input monitor path from mixer to output association. 4888 */ 4889static int 4890hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4891{ 4892 struct hdac_audio_as *ases = devinfo->function.audio.as; 4893 struct hdac_widget *w, *wc; 4894 int i, j; 4895 nid_t res = 0; 4896 4897 if (depth > HDA_PARSE_MAXDEPTH) 4898 return (0); 4899 w = hdac_widget_get(devinfo, nid); 4900 if (w == NULL || w->enable == 0) 4901 return (0); 4902 HDA_BOOTHVERBOSE( 4903 device_printf(devinfo->codec->sc->dev, 4904 " %*stracing via nid %d\n", 4905 depth + 1, "", w->nid); 4906 ); 4907 /* Use only unused widgets */ 4908 if (depth > 0 && w->bindas != -1) { 4909 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4910 HDA_BOOTHVERBOSE( 4911 device_printf(devinfo->codec->sc->dev, 4912 " %*snid %d found output association %d\n", 4913 depth + 1, "", w->nid, w->bindas); 4914 ); 4915 return (1); 4916 } else { 4917 HDA_BOOTHVERBOSE( 4918 device_printf(devinfo->codec->sc->dev, 4919 " %*snid %d busy by input association %d\n", 4920 depth + 1, "", w->nid, w->bindas); 4921 ); 4922 return (0); 4923 } 4924 } 4925 4926 switch (w->type) { 4927 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4928 /* Do not traverse input. AD1988 has digital monitor 4929 for which we are not ready. */ 4930 break; 4931 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4932 if (depth > 0) 4933 break; 4934 /* Fall */ 4935 default: 4936 /* Try to find reachable ADCs with specified nid. */ 4937 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4938 wc = hdac_widget_get(devinfo, j); 4939 if (wc == NULL || wc->enable == 0) 4940 continue; 4941 for (i = 0; i < wc->nconns; i++) { 4942 if (wc->connsenable[i] == 0) 4943 continue; 4944 if (wc->conns[i] != nid) 4945 continue; 4946 if (hdac_audio_trace_to_out(devinfo, 4947 j, depth + 1) != 0) { 4948 res = 1; 4949 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4950 wc->selconn == -1) 4951 wc->selconn = i; 4952 } 4953 } 4954 } 4955 break; 4956 } 4957 if (res) 4958 w->bindas = -2; 4959 4960 HDA_BOOTHVERBOSE( 4961 device_printf(devinfo->codec->sc->dev, 4962 " %*snid %d returned %d\n", 4963 depth + 1, "", w->nid, res); 4964 ); 4965 return (res); 4966} 4967 4968/* 4969 * Trace extra associations (beeper, monitor) 4970 */ 4971static void 4972hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4973{ 4974 struct hdac_audio_as *as = devinfo->function.audio.as; 4975 struct hdac_widget *w; 4976 int j; 4977 4978 /* Input monitor */ 4979 /* Find mixer associated with input, but supplying signal 4980 for output associations. Hope it will be input monitor. */ 4981 HDA_BOOTVERBOSE( 4982 device_printf(devinfo->codec->sc->dev, 4983 "Tracing input monitor\n"); 4984 ); 4985 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4986 w = hdac_widget_get(devinfo, j); 4987 if (w == NULL || w->enable == 0) 4988 continue; 4989 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4990 continue; 4991 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 4992 continue; 4993 HDA_BOOTVERBOSE( 4994 device_printf(devinfo->codec->sc->dev, 4995 " Tracing nid %d to out\n", 4996 j); 4997 ); 4998 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 4999 HDA_BOOTVERBOSE( 5000 device_printf(devinfo->codec->sc->dev, 5001 " nid %d is input monitor\n", 5002 w->nid); 5003 ); 5004 w->pflags |= HDA_ADC_MONITOR; 5005 w->ossdev = SOUND_MIXER_IMIX; 5006 } 5007 } 5008 5009 /* Beeper */ 5010 HDA_BOOTVERBOSE( 5011 device_printf(devinfo->codec->sc->dev, 5012 "Tracing beeper\n"); 5013 ); 5014 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5015 w = hdac_widget_get(devinfo, j); 5016 if (w == NULL || w->enable == 0) 5017 continue; 5018 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5019 continue; 5020 HDA_BOOTHVERBOSE( 5021 device_printf(devinfo->codec->sc->dev, 5022 " Tracing nid %d to out\n", 5023 j); 5024 ); 5025 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5026 HDA_BOOTVERBOSE( 5027 device_printf(devinfo->codec->sc->dev, 5028 " nid %d traced to out\n", 5029 j); 5030 ); 5031 } 5032 w->bindas = -2; 5033 } 5034} 5035 5036/* 5037 * Bind assotiations to PCM channels 5038 */ 5039static void 5040hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5041{ 5042 struct hdac_softc *sc = devinfo->codec->sc; 5043 struct hdac_audio_as *as = devinfo->function.audio.as; 5044 int j, cnt = 0, free; 5045 5046 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5047 if (as[j].enable) 5048 cnt++; 5049 } 5050 if (sc->num_chans == 0) { 5051 sc->chans = (struct hdac_chan *)malloc( 5052 sizeof(struct hdac_chan) * cnt, 5053 M_HDAC, M_ZERO | M_NOWAIT); 5054 if (sc->chans == NULL) { 5055 device_printf(devinfo->codec->sc->dev, 5056 "Channels memory allocation failed!\n"); 5057 return; 5058 } 5059 } else { 5060 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5061 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5062 M_HDAC, M_ZERO | M_NOWAIT); 5063 if (sc->chans == NULL) { 5064 sc->num_chans = 0; 5065 device_printf(devinfo->codec->sc->dev, 5066 "Channels memory allocation failed!\n"); 5067 return; 5068 } 5069 } 5070 free = sc->num_chans; 5071 sc->num_chans += cnt; 5072 5073 for (j = free; j < free + cnt; j++) { 5074 devinfo->codec->sc->chans[j].devinfo = devinfo; 5075 devinfo->codec->sc->chans[j].as = -1; 5076 } 5077 5078 /* Assign associations in order of their numbers, */ 5079 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5080 if (as[j].enable == 0) 5081 continue; 5082 5083 as[j].chan = free; 5084 devinfo->codec->sc->chans[free].as = j; 5085 devinfo->codec->sc->chans[free].dir = 5086 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5087 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5088 free++; 5089 } 5090} 5091 5092static void 5093hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5094{ 5095 struct hdac_widget *w; 5096 int i; 5097 5098 /* Disable power and volume widgets. */ 5099 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5100 w = hdac_widget_get(devinfo, i); 5101 if (w == NULL || w->enable == 0) 5102 continue; 5103 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5104 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5105 w->enable = 0; 5106 HDA_BOOTHVERBOSE( 5107 device_printf(devinfo->codec->sc->dev, 5108 " Disabling nid %d due to it's" 5109 " non-audio type.\n", 5110 w->nid); 5111 ); 5112 } 5113 } 5114} 5115 5116static void 5117hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5118{ 5119 struct hdac_widget *w, *cw; 5120 struct hdac_audio_ctl *ctl; 5121 int done, found, i, j, k; 5122 5123 /* Disable useless pins. */ 5124 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5125 w = hdac_widget_get(devinfo, i); 5126 if (w == NULL || w->enable == 0) 5127 continue; 5128 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5129 if ((w->wclass.pin.config & 5130 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5131 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5132 w->enable = 0; 5133 HDA_BOOTHVERBOSE( 5134 device_printf(devinfo->codec->sc->dev, 5135 " Disabling pin nid %d due" 5136 " to None connectivity.\n", 5137 w->nid); 5138 ); 5139 } else if ((w->wclass.pin.config & 5140 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5141 w->enable = 0; 5142 HDA_BOOTHVERBOSE( 5143 device_printf(devinfo->codec->sc->dev, 5144 " Disabling unassociated" 5145 " pin nid %d.\n", 5146 w->nid); 5147 ); 5148 } 5149 } 5150 } 5151 do { 5152 done = 1; 5153 /* Disable and mute controls for disabled widgets. */ 5154 i = 0; 5155 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5156 if (ctl->enable == 0) 5157 continue; 5158 if (ctl->widget->enable == 0 || 5159 (ctl->childwidget != NULL && 5160 ctl->childwidget->enable == 0)) { 5161 ctl->forcemute = 1; 5162 ctl->muted = HDA_AMP_MUTE_ALL; 5163 ctl->left = 0; 5164 ctl->right = 0; 5165 ctl->enable = 0; 5166 if (ctl->ndir == HDA_CTL_IN) 5167 ctl->widget->connsenable[ctl->index] = 0; 5168 done = 0; 5169 HDA_BOOTHVERBOSE( 5170 device_printf(devinfo->codec->sc->dev, 5171 " Disabling ctl %d nid %d cnid %d due" 5172 " to disabled widget.\n", i, 5173 ctl->widget->nid, 5174 (ctl->childwidget != NULL)? 5175 ctl->childwidget->nid:-1); 5176 ); 5177 } 5178 } 5179 /* Disable useless widgets. */ 5180 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5181 w = hdac_widget_get(devinfo, i); 5182 if (w == NULL || w->enable == 0) 5183 continue; 5184 /* Disable inputs with disabled child widgets. */ 5185 for (j = 0; j < w->nconns; j++) { 5186 if (w->connsenable[j]) { 5187 cw = hdac_widget_get(devinfo, w->conns[j]); 5188 if (cw == NULL || cw->enable == 0) { 5189 w->connsenable[j] = 0; 5190 HDA_BOOTHVERBOSE( 5191 device_printf(devinfo->codec->sc->dev, 5192 " Disabling nid %d connection %d due" 5193 " to disabled child widget.\n", 5194 i, j); 5195 ); 5196 } 5197 } 5198 } 5199 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5200 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5201 continue; 5202 /* Disable mixers and selectors without inputs. */ 5203 found = 0; 5204 for (j = 0; j < w->nconns; j++) { 5205 if (w->connsenable[j]) { 5206 found = 1; 5207 break; 5208 } 5209 } 5210 if (found == 0) { 5211 w->enable = 0; 5212 done = 0; 5213 HDA_BOOTHVERBOSE( 5214 device_printf(devinfo->codec->sc->dev, 5215 " Disabling nid %d due to all it's" 5216 " inputs disabled.\n", w->nid); 5217 ); 5218 } 5219 /* Disable nodes without consumers. */ 5220 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5221 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5222 continue; 5223 found = 0; 5224 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5225 cw = hdac_widget_get(devinfo, k); 5226 if (cw == NULL || cw->enable == 0) 5227 continue; 5228 for (j = 0; j < cw->nconns; j++) { 5229 if (cw->connsenable[j] && cw->conns[j] == i) { 5230 found = 1; 5231 break; 5232 } 5233 } 5234 } 5235 if (found == 0) { 5236 w->enable = 0; 5237 done = 0; 5238 HDA_BOOTHVERBOSE( 5239 device_printf(devinfo->codec->sc->dev, 5240 " Disabling nid %d due to all it's" 5241 " consumers disabled.\n", w->nid); 5242 ); 5243 } 5244 } 5245 } while (done == 0); 5246 5247} 5248 5249static void 5250hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5251{ 5252 struct hdac_audio_as *as = devinfo->function.audio.as; 5253 struct hdac_widget *w, *cw; 5254 struct hdac_audio_ctl *ctl; 5255 int i, j, k; 5256 5257 /* Disable unassosiated widgets. */ 5258 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5259 w = hdac_widget_get(devinfo, i); 5260 if (w == NULL || w->enable == 0) 5261 continue; 5262 if (w->bindas == -1) { 5263 w->enable = 0; 5264 HDA_BOOTHVERBOSE( 5265 device_printf(devinfo->codec->sc->dev, 5266 " Disabling unassociated nid %d.\n", 5267 w->nid); 5268 ); 5269 } 5270 } 5271 /* Disable input connections on input pin and 5272 * output on output. */ 5273 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5274 w = hdac_widget_get(devinfo, i); 5275 if (w == NULL || w->enable == 0) 5276 continue; 5277 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5278 continue; 5279 if (w->bindas < 0) 5280 continue; 5281 if (as[w->bindas].dir == HDA_CTL_IN) { 5282 for (j = 0; j < w->nconns; j++) { 5283 if (w->connsenable[j] == 0) 5284 continue; 5285 w->connsenable[j] = 0; 5286 HDA_BOOTHVERBOSE( 5287 device_printf(devinfo->codec->sc->dev, 5288 " Disabling connection to input pin " 5289 "nid %d conn %d.\n", 5290 i, j); 5291 ); 5292 } 5293 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5294 HDA_CTL_IN, -1, 1); 5295 if (ctl && ctl->enable) { 5296 ctl->forcemute = 1; 5297 ctl->muted = HDA_AMP_MUTE_ALL; 5298 ctl->left = 0; 5299 ctl->right = 0; 5300 ctl->enable = 0; 5301 } 5302 } else { 5303 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5304 HDA_CTL_OUT, -1, 1); 5305 if (ctl && ctl->enable) { 5306 ctl->forcemute = 1; 5307 ctl->muted = HDA_AMP_MUTE_ALL; 5308 ctl->left = 0; 5309 ctl->right = 0; 5310 ctl->enable = 0; 5311 } 5312 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5313 cw = hdac_widget_get(devinfo, k); 5314 if (cw == NULL || cw->enable == 0) 5315 continue; 5316 for (j = 0; j < cw->nconns; j++) { 5317 if (cw->connsenable[j] && cw->conns[j] == i) { 5318 cw->connsenable[j] = 0; 5319 HDA_BOOTHVERBOSE( 5320 device_printf(devinfo->codec->sc->dev, 5321 " Disabling connection from output pin " 5322 "nid %d conn %d cnid %d.\n", 5323 k, j, i); 5324 ); 5325 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5326 cw->nconns > 1) 5327 continue; 5328 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5329 HDA_CTL_IN, j, 1); 5330 if (ctl && ctl->enable) { 5331 ctl->forcemute = 1; 5332 ctl->muted = HDA_AMP_MUTE_ALL; 5333 ctl->left = 0; 5334 ctl->right = 0; 5335 ctl->enable = 0; 5336 } 5337 } 5338 } 5339 } 5340 } 5341 } 5342} 5343 5344static void 5345hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5346{ 5347 struct hdac_audio_as *as = devinfo->function.audio.as; 5348 struct hdac_widget *w; 5349 int i, j; 5350 5351 /* On playback path we can safely disable all unseleted inputs. */ 5352 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5353 w = hdac_widget_get(devinfo, i); 5354 if (w == NULL || w->enable == 0) 5355 continue; 5356 if (w->nconns <= 1) 5357 continue; 5358 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5359 continue; 5360 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5361 continue; 5362 for (j = 0; j < w->nconns; j++) { 5363 if (w->connsenable[j] == 0) 5364 continue; 5365 if (w->selconn < 0 || w->selconn == j) 5366 continue; 5367 w->connsenable[j] = 0; 5368 HDA_BOOTHVERBOSE( 5369 device_printf(devinfo->codec->sc->dev, 5370 " Disabling unselected connection " 5371 "nid %d conn %d.\n", 5372 i, j); 5373 ); 5374 } 5375 } 5376} 5377 5378static void 5379hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5380{ 5381 struct hdac_widget *w, *cw; 5382 struct hdac_audio_ctl *ctl; 5383 int i, j; 5384 5385 /* Disable crossassociatement connections. */ 5386 /* ... using selectors */ 5387 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5388 w = hdac_widget_get(devinfo, i); 5389 if (w == NULL || w->enable == 0) 5390 continue; 5391 if (w->nconns <= 1) 5392 continue; 5393 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5394 continue; 5395 if (w->bindas == -2) 5396 continue; 5397 for (j = 0; j < w->nconns; j++) { 5398 if (w->connsenable[j] == 0) 5399 continue; 5400 cw = hdac_widget_get(devinfo, w->conns[j]); 5401 if (cw == NULL || w->enable == 0) 5402 continue; 5403 if (w->bindas == cw->bindas || cw->bindas == -2) 5404 continue; 5405 w->connsenable[j] = 0; 5406 HDA_BOOTHVERBOSE( 5407 device_printf(devinfo->codec->sc->dev, 5408 " Disabling crossassociatement connection " 5409 "nid %d conn %d cnid %d.\n", 5410 i, j, cw->nid); 5411 ); 5412 } 5413 } 5414 /* ... using controls */ 5415 i = 0; 5416 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5417 if (ctl->enable == 0 || ctl->childwidget == NULL) 5418 continue; 5419 if (ctl->widget->bindas == -2 || 5420 ctl->childwidget->bindas == -2) 5421 continue; 5422 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5423 ctl->forcemute = 1; 5424 ctl->muted = HDA_AMP_MUTE_ALL; 5425 ctl->left = 0; 5426 ctl->right = 0; 5427 ctl->enable = 0; 5428 if (ctl->ndir == HDA_CTL_IN) 5429 ctl->widget->connsenable[ctl->index] = 0; 5430 HDA_BOOTHVERBOSE( 5431 device_printf(devinfo->codec->sc->dev, 5432 " Disabling crossassociatement connection " 5433 "ctl %d nid %d cnid %d.\n", i, 5434 ctl->widget->nid, 5435 ctl->childwidget->nid); 5436 ); 5437 } 5438 } 5439 5440} 5441 5442#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5443 5444/* 5445 * Find controls to control amplification for source. 5446 */ 5447static int 5448hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5449 int ossdev, int ctlable, int depth, int need) 5450{ 5451 struct hdac_widget *w, *wc; 5452 struct hdac_audio_ctl *ctl; 5453 int i, j, conns = 0, rneed; 5454 5455 if (depth > HDA_PARSE_MAXDEPTH) 5456 return (need); 5457 5458 w = hdac_widget_get(devinfo, nid); 5459 if (w == NULL || w->enable == 0) 5460 return (need); 5461 5462 /* Count number of active inputs. */ 5463 if (depth > 0) { 5464 for (j = 0; j < w->nconns; j++) { 5465 if (w->connsenable[j]) 5466 conns++; 5467 } 5468 } 5469 5470 /* If this is not a first step - use input mixer. 5471 Pins have common input ctl so care must be taken. */ 5472 if (depth > 0 && ctlable && (conns == 1 || 5473 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5474 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5475 index, 1); 5476 if (ctl) { 5477 if (HDA_CTL_GIVE(ctl) & need) 5478 ctl->ossmask |= (1 << ossdev); 5479 else 5480 ctl->possmask |= (1 << ossdev); 5481 need &= ~HDA_CTL_GIVE(ctl); 5482 } 5483 } 5484 5485 /* If widget has own ossdev - not traverse it. 5486 It will be traversed on it's own. */ 5487 if (w->ossdev >= 0 && depth > 0) 5488 return (need); 5489 5490 /* We must not traverse pin */ 5491 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5492 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5493 depth > 0) 5494 return (need); 5495 5496 /* record that this widget exports such signal, */ 5497 w->ossmask |= (1 << ossdev); 5498 5499 /* If signals mixed, we can't assign controls farther. 5500 * Ignore this on depth zero. Caller must knows why. 5501 * Ignore this for static selectors if this input selected. 5502 */ 5503 if (conns > 1) 5504 ctlable = 0; 5505 5506 if (ctlable) { 5507 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5508 if (ctl) { 5509 if (HDA_CTL_GIVE(ctl) & need) 5510 ctl->ossmask |= (1 << ossdev); 5511 else 5512 ctl->possmask |= (1 << ossdev); 5513 need &= ~HDA_CTL_GIVE(ctl); 5514 } 5515 } 5516 5517 rneed = 0; 5518 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5519 wc = hdac_widget_get(devinfo, i); 5520 if (wc == NULL || wc->enable == 0) 5521 continue; 5522 for (j = 0; j < wc->nconns; j++) { 5523 if (wc->connsenable[j] && wc->conns[j] == nid) { 5524 rneed |= hdac_audio_ctl_source_amp(devinfo, 5525 wc->nid, j, ossdev, ctlable, depth + 1, need); 5526 } 5527 } 5528 } 5529 rneed &= need; 5530 5531 return (rneed); 5532} 5533 5534/* 5535 * Find controls to control amplification for destination. 5536 */ 5537static void 5538hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5539 int ossdev, int depth, int need) 5540{ 5541 struct hdac_audio_as *as = devinfo->function.audio.as; 5542 struct hdac_widget *w, *wc; 5543 struct hdac_audio_ctl *ctl; 5544 int i, j, consumers; 5545 5546 if (depth > HDA_PARSE_MAXDEPTH) 5547 return; 5548 5549 w = hdac_widget_get(devinfo, nid); 5550 if (w == NULL || w->enable == 0) 5551 return; 5552 5553 if (depth > 0) { 5554 /* If this node produce output for several consumers, 5555 we can't touch it. */ 5556 consumers = 0; 5557 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5558 wc = hdac_widget_get(devinfo, i); 5559 if (wc == NULL || wc->enable == 0) 5560 continue; 5561 for (j = 0; j < wc->nconns; j++) { 5562 if (wc->connsenable[j] && wc->conns[j] == nid) 5563 consumers++; 5564 } 5565 } 5566 /* The only exception is if real HP redirection is configured 5567 and this is a duplication point. 5568 XXX: Actually exception is not completely correct. 5569 XXX: Duplication point check is not perfect. */ 5570 if ((consumers == 2 && (w->bindas < 0 || 5571 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5572 (w->bindseqmask & (1 << 15)) == 0)) || 5573 consumers > 2) 5574 return; 5575 5576 /* Else use it's output mixer. */ 5577 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5578 HDA_CTL_OUT, -1, 1); 5579 if (ctl) { 5580 if (HDA_CTL_GIVE(ctl) & need) 5581 ctl->ossmask |= (1 << ossdev); 5582 else 5583 ctl->possmask |= (1 << ossdev); 5584 need &= ~HDA_CTL_GIVE(ctl); 5585 } 5586 } 5587 5588 /* We must not traverse pin */ 5589 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5590 depth > 0) 5591 return; 5592 5593 for (i = 0; i < w->nconns; i++) { 5594 int tneed = need; 5595 if (w->connsenable[i] == 0) 5596 continue; 5597 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5598 HDA_CTL_IN, i, 1); 5599 if (ctl) { 5600 if (HDA_CTL_GIVE(ctl) & tneed) 5601 ctl->ossmask |= (1 << ossdev); 5602 else 5603 ctl->possmask |= (1 << ossdev); 5604 tneed &= ~HDA_CTL_GIVE(ctl); 5605 } 5606 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5607 depth + 1, tneed); 5608 } 5609} 5610 5611/* 5612 * Assign OSS names to sound sources 5613 */ 5614static void 5615hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5616{ 5617 struct hdac_audio_as *as = devinfo->function.audio.as; 5618 struct hdac_widget *w; 5619 int i, j; 5620 int type = -1, use, used = 0; 5621 static const int types[7][13] = { 5622 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5623 SOUND_MIXER_LINE3, -1 }, /* line */ 5624 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5625 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5626 { SOUND_MIXER_CD, -1 }, /* cd */ 5627 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5628 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5629 -1 }, /* digital */ 5630 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5631 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5632 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5633 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5634 -1 } /* others */ 5635 }; 5636 5637 /* Surely known names */ 5638 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5639 w = hdac_widget_get(devinfo, i); 5640 if (w == NULL || w->enable == 0) 5641 continue; 5642 if (w->bindas == -1) 5643 continue; 5644 use = -1; 5645 switch (w->type) { 5646 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5647 if (as[w->bindas].dir == HDA_CTL_OUT) 5648 break; 5649 type = -1; 5650 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5651 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5652 type = 0; 5653 break; 5654 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5655 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5656 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5657 break; 5658 type = 1; 5659 break; 5660 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5661 type = 3; 5662 break; 5663 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5664 type = 4; 5665 break; 5666 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5667 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5668 type = 5; 5669 break; 5670 } 5671 if (type == -1) 5672 break; 5673 j = 0; 5674 while (types[type][j] >= 0 && 5675 (used & (1 << types[type][j])) != 0) { 5676 j++; 5677 } 5678 if (types[type][j] >= 0) 5679 use = types[type][j]; 5680 break; 5681 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5682 use = SOUND_MIXER_PCM; 5683 break; 5684 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5685 use = SOUND_MIXER_SPEAKER; 5686 break; 5687 default: 5688 break; 5689 } 5690 if (use >= 0) { 5691 w->ossdev = use; 5692 used |= (1 << use); 5693 } 5694 } 5695 /* Semi-known names */ 5696 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5697 w = hdac_widget_get(devinfo, i); 5698 if (w == NULL || w->enable == 0) 5699 continue; 5700 if (w->ossdev >= 0) 5701 continue; 5702 if (w->bindas == -1) 5703 continue; 5704 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5705 continue; 5706 if (as[w->bindas].dir == HDA_CTL_OUT) 5707 continue; 5708 type = -1; 5709 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5710 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5711 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5712 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5713 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5714 type = 0; 5715 break; 5716 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5717 type = 2; 5718 break; 5719 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5720 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5721 type = 5; 5722 break; 5723 } 5724 if (type == -1) 5725 break; 5726 j = 0; 5727 while (types[type][j] >= 0 && 5728 (used & (1 << types[type][j])) != 0) { 5729 j++; 5730 } 5731 if (types[type][j] >= 0) { 5732 w->ossdev = types[type][j]; 5733 used |= (1 << types[type][j]); 5734 } 5735 } 5736 /* Others */ 5737 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5738 w = hdac_widget_get(devinfo, i); 5739 if (w == NULL || w->enable == 0) 5740 continue; 5741 if (w->ossdev >= 0) 5742 continue; 5743 if (w->bindas == -1) 5744 continue; 5745 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5746 continue; 5747 if (as[w->bindas].dir == HDA_CTL_OUT) 5748 continue; 5749 j = 0; 5750 while (types[6][j] >= 0 && 5751 (used & (1 << types[6][j])) != 0) { 5752 j++; 5753 } 5754 if (types[6][j] >= 0) { 5755 w->ossdev = types[6][j]; 5756 used |= (1 << types[6][j]); 5757 } 5758 } 5759} 5760 5761static void 5762hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5763{ 5764 struct hdac_audio_as *as = devinfo->function.audio.as; 5765 int j, res; 5766 5767 /* Trace all associations in order of their numbers, */ 5768 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5769 if (as[j].enable == 0) 5770 continue; 5771 HDA_BOOTVERBOSE( 5772 device_printf(devinfo->codec->sc->dev, 5773 "Tracing association %d (%d)\n", j, as[j].index); 5774 ); 5775 if (as[j].dir == HDA_CTL_OUT) { 5776retry: 5777 res = hdac_audio_trace_as_out(devinfo, j, 0); 5778 if (res == 0 && as[j].hpredir >= 0 && 5779 as[j].fakeredir == 0) { 5780 /* If codec can't do analog HP redirection 5781 try to make it using one more DAC. */ 5782 as[j].fakeredir = 1; 5783 goto retry; 5784 } 5785 } else { 5786 res = hdac_audio_trace_as_in(devinfo, j); 5787 } 5788 if (res) { 5789 HDA_BOOTVERBOSE( 5790 device_printf(devinfo->codec->sc->dev, 5791 "Association %d (%d) trace succeded\n", 5792 j, as[j].index); 5793 ); 5794 } else { 5795 HDA_BOOTVERBOSE( 5796 device_printf(devinfo->codec->sc->dev, 5797 "Association %d (%d) trace failed\n", 5798 j, as[j].index); 5799 ); 5800 as[j].enable = 0; 5801 } 5802 } 5803 5804 /* Trace mixer and beeper pseudo associations. */ 5805 hdac_audio_trace_as_extra(devinfo); 5806} 5807 5808static void 5809hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5810{ 5811 struct hdac_audio_as *as = devinfo->function.audio.as; 5812 struct hdac_audio_ctl *ctl; 5813 struct hdac_widget *w; 5814 int i; 5815 5816 /* Assign mixers to the tree. */ 5817 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5818 w = hdac_widget_get(devinfo, i); 5819 if (w == NULL || w->enable == 0) 5820 continue; 5821 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5822 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5823 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5824 as[w->bindas].dir == HDA_CTL_IN)) { 5825 if (w->ossdev < 0) 5826 continue; 5827 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5828 w->ossdev, 1, 0, 1); 5829 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5830 if (w->ossdev < 0) 5831 continue; 5832 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5833 w->ossdev, 1, 0, 1)) { 5834 /* If we are unable to control input monitor 5835 as source - try to control it as destination. */ 5836 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5837 w->ossdev, 0, 1); 5838 } 5839 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5840 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5841 SOUND_MIXER_RECLEV, 0, 1); 5842 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5843 as[w->bindas].dir == HDA_CTL_OUT) { 5844 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5845 SOUND_MIXER_VOLUME, 0, 1); 5846 } 5847 } 5848 /* Treat unrequired as possible. */ 5849 i = 0; 5850 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5851 if (ctl->ossmask == 0) 5852 ctl->ossmask = ctl->possmask; 5853 } 5854} 5855 5856static void 5857hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5858{ 5859 struct hdac_audio_as *as = devinfo->function.audio.as; 5860 struct hdac_widget *w; 5861 uint32_t pincap; 5862 int i; 5863 5864 for (i = 0; i < devinfo->nodecnt; i++) { 5865 w = &devinfo->widget[i]; 5866 if (w == NULL) 5867 continue; 5868 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5869 continue; 5870 5871 pincap = w->wclass.pin.cap; 5872 5873 /* Disable everything. */ 5874 w->wclass.pin.ctrl &= ~( 5875 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5876 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5877 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5878 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5879 5880 if (w->enable == 0 || 5881 w->bindas < 0 || as[w->bindas].enable == 0) { 5882 /* Pin is unused so left it disabled. */ 5883 continue; 5884 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5885 /* Input pin, configure for input. */ 5886 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5887 w->wclass.pin.ctrl |= 5888 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5889 5890 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5891 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5892 w->wclass.pin.ctrl |= 5893 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5894 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5895 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5896 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5897 w->wclass.pin.ctrl |= 5898 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5899 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5900 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5901 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5902 w->wclass.pin.ctrl |= 5903 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5904 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5905 } else { 5906 /* Output pin, configure for output. */ 5907 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5908 w->wclass.pin.ctrl |= 5909 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5910 5911 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5912 (w->wclass.pin.config & 5913 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5914 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5915 w->wclass.pin.ctrl |= 5916 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5917 5918 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5919 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5920 w->wclass.pin.ctrl |= 5921 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5922 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5923 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5924 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5925 w->wclass.pin.ctrl |= 5926 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5927 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5928 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5929 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5930 w->wclass.pin.ctrl |= 5931 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5932 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5933 } 5934 } 5935} 5936 5937static void 5938hdac_audio_commit(struct hdac_devinfo *devinfo) 5939{ 5940 struct hdac_softc *sc = devinfo->codec->sc; 5941 struct hdac_widget *w; 5942 nid_t cad; 5943 uint32_t gdata, gmask, gdir; 5944 int commitgpio, numgpio; 5945 int i; 5946 5947 cad = devinfo->codec->cad; 5948 5949 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5950 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5951 0x7e7, 0), cad); 5952 5953 gdata = 0; 5954 gmask = 0; 5955 gdir = 0; 5956 commitgpio = 0; 5957 5958 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5959 devinfo->function.audio.gpio); 5960 5961 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5962 commitgpio = (numgpio > 0) ? 1 : 0; 5963 else { 5964 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5965 if (!(devinfo->function.audio.quirks & 5966 (1 << i))) 5967 continue; 5968 if (commitgpio == 0) { 5969 commitgpio = 1; 5970 HDA_BOOTVERBOSE( 5971 gdata = hdac_command(sc, 5972 HDA_CMD_GET_GPIO_DATA(cad, 5973 devinfo->nid), cad); 5974 gmask = hdac_command(sc, 5975 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5976 devinfo->nid), cad); 5977 gdir = hdac_command(sc, 5978 HDA_CMD_GET_GPIO_DIRECTION(cad, 5979 devinfo->nid), cad); 5980 device_printf(sc->dev, 5981 "GPIO init: data=0x%08x " 5982 "mask=0x%08x dir=0x%08x\n", 5983 gdata, gmask, gdir); 5984 gdata = 0; 5985 gmask = 0; 5986 gdir = 0; 5987 ); 5988 } 5989 gdata |= 1 << i; 5990 gmask |= 1 << i; 5991 gdir |= 1 << i; 5992 } 5993 } 5994 5995 if (commitgpio != 0) { 5996 HDA_BOOTVERBOSE( 5997 device_printf(sc->dev, 5998 "GPIO commit: data=0x%08x mask=0x%08x " 5999 "dir=0x%08x\n", 6000 gdata, gmask, gdir); 6001 ); 6002 hdac_command(sc, 6003 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6004 gmask), cad); 6005 hdac_command(sc, 6006 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6007 gdir), cad); 6008 hdac_command(sc, 6009 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6010 gdata), cad); 6011 } 6012 6013 for (i = 0; i < devinfo->nodecnt; i++) { 6014 w = &devinfo->widget[i]; 6015 if (w == NULL) 6016 continue; 6017 if (w->selconn == -1) 6018 w->selconn = 0; 6019 if (w->nconns > 0) 6020 hdac_widget_connection_select(w, w->selconn); 6021 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6022 hdac_command(sc, 6023 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6024 w->wclass.pin.ctrl), cad); 6025 } 6026 if (w->param.eapdbtl != HDAC_INVALID) { 6027 uint32_t val; 6028 6029 val = w->param.eapdbtl; 6030 if (devinfo->function.audio.quirks & 6031 HDA_QUIRK_EAPDINV) 6032 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6033 hdac_command(sc, 6034 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6035 val), cad); 6036 6037 } 6038 DELAY(1000); 6039 } 6040} 6041 6042static void 6043hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6044{ 6045 struct hdac_audio_ctl *ctl; 6046 int i, z; 6047 6048 i = 0; 6049 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6050 if (ctl->enable == 0) { 6051 /* Mute disabled controls. */ 6052 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6053 continue; 6054 } 6055 /* Init controls to 0dB amplification. */ 6056 z = ctl->offset; 6057 if (z > ctl->step) 6058 z = ctl->step; 6059 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6060 } 6061} 6062 6063static void 6064hdac_powerup(struct hdac_devinfo *devinfo) 6065{ 6066 struct hdac_softc *sc = devinfo->codec->sc; 6067 nid_t cad = devinfo->codec->cad; 6068 int i; 6069 6070 hdac_command(sc, 6071 HDA_CMD_SET_POWER_STATE(cad, 6072 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6073 cad); 6074 DELAY(100); 6075 6076 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6077 hdac_command(sc, 6078 HDA_CMD_SET_POWER_STATE(cad, 6079 i, HDA_CMD_POWER_STATE_D0), 6080 cad); 6081 } 6082 DELAY(1000); 6083} 6084 6085static int 6086hdac_pcmchannel_setup(struct hdac_chan *ch) 6087{ 6088 struct hdac_devinfo *devinfo = ch->devinfo; 6089 struct hdac_audio_as *as = devinfo->function.audio.as; 6090 struct hdac_widget *w; 6091 uint32_t cap, fmtcap, pcmcap; 6092 int i, j, ret, max; 6093 6094 ch->caps = hdac_caps; 6095 ch->caps.fmtlist = ch->fmtlist; 6096 ch->bit16 = 1; 6097 ch->bit32 = 0; 6098 ch->pcmrates[0] = 48000; 6099 ch->pcmrates[1] = 0; 6100 6101 ret = 0; 6102 fmtcap = devinfo->function.audio.supp_stream_formats; 6103 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6104 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6105 6106 for (i = 0; i < 16 && ret < max; i++) { 6107 /* Check as is correct */ 6108 if (ch->as < 0) 6109 break; 6110 /* Cound only present DACs */ 6111 if (as[ch->as].dacs[i] <= 0) 6112 continue; 6113 /* Ignore duplicates */ 6114 for (j = 0; j < ret; j++) { 6115 if (ch->io[j] == as[ch->as].dacs[i]) 6116 break; 6117 } 6118 if (j < ret) 6119 continue; 6120 6121 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6122 if (w == NULL || w->enable == 0) 6123 continue; 6124 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6125 continue; 6126 cap = w->param.supp_stream_formats; 6127 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6128 }*/ 6129 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6130 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6131 continue; 6132 /* Many codec does not declare AC3 support on SPDIF. 6133 I don't beleave that they doesn't support it! */ 6134 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6135 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6136 if (ret == 0) { 6137 fmtcap = cap; 6138 pcmcap = w->param.supp_pcm_size_rate; 6139 } else { 6140 fmtcap &= cap; 6141 pcmcap &= w->param.supp_pcm_size_rate; 6142 } 6143 ch->io[ret++] = as[ch->as].dacs[i]; 6144 } 6145 ch->io[ret] = -1; 6146 6147 ch->supp_stream_formats = fmtcap; 6148 ch->supp_pcm_size_rate = pcmcap; 6149 6150 /* 6151 * 8bit = 0 6152 * 16bit = 1 6153 * 20bit = 2 6154 * 24bit = 3 6155 * 32bit = 4 6156 */ 6157 if (ret > 0) { 6158 i = 0; 6159 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6160 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6161 ch->bit16 = 1; 6162 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6163 ch->bit16 = 0; 6164 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6165 ch->bit32 = 4; 6166 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6167 ch->bit32 = 3; 6168 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6169 ch->bit32 = 2; 6170 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6171 ch->fmtlist[i++] = AFMT_S16_LE; 6172 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6173 if (ch->bit32 > 0) { 6174 if (!(devinfo->function.audio.quirks & 6175 HDA_QUIRK_FORCESTEREO)) 6176 ch->fmtlist[i++] = AFMT_S32_LE; 6177 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6178 } 6179 } 6180 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6181 ch->fmtlist[i++] = AFMT_AC3; 6182 } 6183 ch->fmtlist[i] = 0; 6184 i = 0; 6185 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6186 ch->pcmrates[i++] = 8000; 6187 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6188 ch->pcmrates[i++] = 11025; 6189 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6190 ch->pcmrates[i++] = 16000; 6191 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6192 ch->pcmrates[i++] = 22050; 6193 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6194 ch->pcmrates[i++] = 32000; 6195 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6196 ch->pcmrates[i++] = 44100; 6197 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6198 ch->pcmrates[i++] = 48000; 6199 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6200 ch->pcmrates[i++] = 88200; 6201 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6202 ch->pcmrates[i++] = 96000; 6203 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6204 ch->pcmrates[i++] = 176400; 6205 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6206 ch->pcmrates[i++] = 192000; 6207 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6208 ch->pcmrates[i] = 0; 6209 if (i > 0) { 6210 ch->caps.minspeed = ch->pcmrates[0]; 6211 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6212 } 6213 } 6214 6215 return (ret); 6216} 6217 6218static void 6219hdac_create_pcms(struct hdac_devinfo *devinfo) 6220{ 6221 struct hdac_softc *sc = devinfo->codec->sc; 6222 struct hdac_audio_as *as = devinfo->function.audio.as; 6223 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6224 6225 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6226 if (as[i].enable == 0) 6227 continue; 6228 if (as[i].dir == HDA_CTL_IN) { 6229 if (as[i].digital) 6230 drdev++; 6231 else 6232 ardev++; 6233 } else { 6234 if (as[i].digital) 6235 dpdev++; 6236 else 6237 apdev++; 6238 } 6239 } 6240 devinfo->function.audio.num_devs = 6241 max(ardev, apdev) + max(drdev, dpdev); 6242 devinfo->function.audio.devs = 6243 (struct hdac_pcm_devinfo *)malloc( 6244 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6245 M_HDAC, M_ZERO | M_NOWAIT); 6246 if (devinfo->function.audio.devs == NULL) { 6247 device_printf(sc->dev, 6248 "Unable to allocate memory for devices\n"); 6249 return; 6250 } 6251 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6252 devinfo->function.audio.devs[i].index = i; 6253 devinfo->function.audio.devs[i].devinfo = devinfo; 6254 devinfo->function.audio.devs[i].play = -1; 6255 devinfo->function.audio.devs[i].rec = -1; 6256 devinfo->function.audio.devs[i].digital = 2; 6257 } 6258 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6259 if (as[i].enable == 0) 6260 continue; 6261 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6262 if (devinfo->function.audio.devs[j].digital != 2 && 6263 devinfo->function.audio.devs[j].digital != 6264 as[i].digital) 6265 continue; 6266 if (as[i].dir == HDA_CTL_IN) { 6267 if (devinfo->function.audio.devs[j].rec >= 0) 6268 continue; 6269 devinfo->function.audio.devs[j].rec 6270 = as[i].chan; 6271 } else { 6272 if (devinfo->function.audio.devs[j].play >= 0) 6273 continue; 6274 devinfo->function.audio.devs[j].play 6275 = as[i].chan; 6276 } 6277 sc->chans[as[i].chan].pdevinfo = 6278 &devinfo->function.audio.devs[j]; 6279 devinfo->function.audio.devs[j].digital = 6280 as[i].digital; 6281 break; 6282 } 6283 } 6284 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6285 struct hdac_pcm_devinfo *pdevinfo = 6286 &devinfo->function.audio.devs[i]; 6287 pdevinfo->dev = 6288 device_add_child(sc->dev, "pcm", -1); 6289 device_set_ivars(pdevinfo->dev, 6290 (void *)pdevinfo); 6291 } 6292} 6293 6294static void 6295hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6296{ 6297 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6298 struct hdac_audio_ctl *ctl; 6299 struct hdac_softc *sc = devinfo->codec->sc; 6300 char buf[64]; 6301 int i, j, printed; 6302 6303 if (flag == 0) { 6304 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6305 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6306 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6307 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6308 } 6309 6310 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6311 if ((flag & (1 << j)) == 0) 6312 continue; 6313 i = 0; 6314 printed = 0; 6315 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6316 if (ctl->enable == 0 || 6317 ctl->widget->enable == 0) 6318 continue; 6319 if (!((pdevinfo->play >= 0 && 6320 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6321 (pdevinfo->rec >= 0 && 6322 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6323 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6324 continue; 6325 if ((ctl->ossmask & (1 << j)) == 0) 6326 continue; 6327 6328 if (printed == 0) { 6329 device_printf(pdevinfo->dev, "\n"); 6330 if (banner != NULL) { 6331 device_printf(pdevinfo->dev, "%s", banner); 6332 } else { 6333 device_printf(pdevinfo->dev, "Unknown Ctl"); 6334 } 6335 printf(" (OSS: %s)\n", 6336 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6337 buf, sizeof(buf))); 6338 device_printf(pdevinfo->dev, " |\n"); 6339 printed = 1; 6340 } 6341 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6342 ctl->widget->nid, 6343 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6344 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6345 printf(" %2d): ", ctl->index); 6346 else 6347 printf("): "); 6348 if (ctl->step > 0) { 6349 printf("%+d/%+ddB (%d steps)%s\n", 6350 (0 - ctl->offset) * (ctl->size + 1) / 4, 6351 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6352 ctl->step + 1, 6353 ctl->mute?" + mute":""); 6354 } else 6355 printf("%s\n", ctl->mute?"mute":""); 6356 } 6357 } 6358} 6359 6360static void 6361hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6362{ 6363 uint32_t cap; 6364 6365 cap = fcap; 6366 if (cap != 0) { 6367 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6368 device_printf(dev, " "); 6369 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6370 printf(" AC3"); 6371 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6372 printf(" FLOAT32"); 6373 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6374 printf(" PCM"); 6375 printf("\n"); 6376 } 6377 cap = pcmcap; 6378 if (cap != 0) { 6379 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6380 device_printf(dev, " "); 6381 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6382 printf(" 8"); 6383 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6384 printf(" 16"); 6385 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6386 printf(" 20"); 6387 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6388 printf(" 24"); 6389 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6390 printf(" 32"); 6391 printf(" bits,"); 6392 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6393 printf(" 8"); 6394 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6395 printf(" 11"); 6396 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6397 printf(" 16"); 6398 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6399 printf(" 22"); 6400 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6401 printf(" 32"); 6402 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6403 printf(" 44"); 6404 printf(" 48"); 6405 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6406 printf(" 88"); 6407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6408 printf(" 96"); 6409 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6410 printf(" 176"); 6411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6412 printf(" 192"); 6413 printf(" KHz\n"); 6414 } 6415} 6416 6417static void 6418hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6419{ 6420 uint32_t pincap; 6421 6422 pincap = w->wclass.pin.cap; 6423 6424 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6425 device_printf(sc->dev, " "); 6426 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6427 printf(" ISC"); 6428 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6429 printf(" TRQD"); 6430 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6431 printf(" PDC"); 6432 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6433 printf(" HP"); 6434 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6435 printf(" OUT"); 6436 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6437 printf(" IN"); 6438 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6439 printf(" BAL"); 6440 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6441 printf(" VREF["); 6442 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6443 printf(" 50"); 6444 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6445 printf(" 80"); 6446 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6447 printf(" 100"); 6448 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6449 printf(" GROUND"); 6450 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6451 printf(" HIZ"); 6452 printf(" ]"); 6453 } 6454 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6455 printf(" EAPD"); 6456 printf("\n"); 6457 device_printf(sc->dev, " Pin config: 0x%08x\n", 6458 w->wclass.pin.config); 6459 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6460 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6461 printf(" HP"); 6462 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6463 printf(" IN"); 6464 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6465 printf(" OUT"); 6466 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6467 printf(" VREFs"); 6468 printf("\n"); 6469} 6470 6471static void 6472hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6473{ 6474 struct hdac_softc *sc = w->devinfo->codec->sc; 6475 6476 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6477 "jack %2d loc %2d color %7s misc %d%s\n", 6478 w->nid, conf, 6479 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6480 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6481 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6482 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6483 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6484 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6485 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6486 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6487 (w->enable == 0)?" [DISABLED]":""); 6488} 6489 6490static void 6491hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6492{ 6493 struct hdac_widget *w; 6494 int i; 6495 6496 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6497 w = hdac_widget_get(devinfo, i); 6498 if (w == NULL) 6499 continue; 6500 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6501 continue; 6502 hdac_dump_pin_config(w, w->wclass.pin.config); 6503 } 6504} 6505 6506static void 6507hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6508{ 6509 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6510 device_printf(sc->dev, " " 6511 "mute=%d step=%d size=%d offset=%d\n", 6512 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6513 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6514 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6515 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6516} 6517 6518static void 6519hdac_dump_nodes(struct hdac_devinfo *devinfo) 6520{ 6521 struct hdac_softc *sc = devinfo->codec->sc; 6522 static char *ossname[] = SOUND_DEVICE_NAMES; 6523 struct hdac_widget *w, *cw; 6524 char buf[64]; 6525 int i, j; 6526 6527 device_printf(sc->dev, "\n"); 6528 device_printf(sc->dev, "Default Parameter\n"); 6529 device_printf(sc->dev, "-----------------\n"); 6530 hdac_dump_audio_formats(sc->dev, 6531 devinfo->function.audio.supp_stream_formats, 6532 devinfo->function.audio.supp_pcm_size_rate); 6533 device_printf(sc->dev, " IN amp: 0x%08x\n", 6534 devinfo->function.audio.inamp_cap); 6535 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6536 devinfo->function.audio.outamp_cap); 6537 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6538 w = hdac_widget_get(devinfo, i); 6539 if (w == NULL) { 6540 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6541 continue; 6542 } 6543 device_printf(sc->dev, "\n"); 6544 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6545 (w->enable == 0) ? " [DISABLED]" : ""); 6546 device_printf(sc->dev, " Name: %s\n", w->name); 6547 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6548 w->param.widget_cap); 6549 if (w->param.widget_cap & 0x0ee1) { 6550 device_printf(sc->dev, " "); 6551 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6552 printf(" LRSWAP"); 6553 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6554 printf(" PWR"); 6555 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6556 printf(" DIGITAL"); 6557 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6558 printf(" UNSOL"); 6559 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6560 printf(" PROC"); 6561 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6562 printf(" STRIPE"); 6563 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6564 printf(" STEREO"); 6565 printf("\n"); 6566 } 6567 if (w->bindas != -1) { 6568 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6569 w->bindas, w->bindseqmask); 6570 } 6571 if (w->ossmask != 0 || w->ossdev >= 0) { 6572 device_printf(sc->dev, " OSS: %s", 6573 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6574 if (w->ossdev >= 0) 6575 printf(" (%s)", ossname[w->ossdev]); 6576 printf("\n"); 6577 } 6578 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6579 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6580 hdac_dump_audio_formats(sc->dev, 6581 w->param.supp_stream_formats, 6582 w->param.supp_pcm_size_rate); 6583 } else if (w->type == 6584 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6585 hdac_dump_pin(sc, w); 6586 if (w->param.eapdbtl != HDAC_INVALID) 6587 device_printf(sc->dev, " EAPD: 0x%08x\n", 6588 w->param.eapdbtl); 6589 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6590 w->param.outamp_cap != 0) 6591 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6592 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6593 w->param.inamp_cap != 0) 6594 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6595 if (w->nconns > 0) { 6596 device_printf(sc->dev, " connections: %d\n", w->nconns); 6597 device_printf(sc->dev, " |\n"); 6598 } 6599 for (j = 0; j < w->nconns; j++) { 6600 cw = hdac_widget_get(devinfo, w->conns[j]); 6601 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6602 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6603 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6604 if (cw == NULL) 6605 printf(" [UNKNOWN]"); 6606 else if (cw->enable == 0) 6607 printf(" [DISABLED]"); 6608 if (w->nconns > 1 && w->selconn == j && w->type != 6609 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6610 printf(" (selected)"); 6611 printf("\n"); 6612 } 6613 } 6614 6615} 6616 6617static void 6618hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6619{ 6620 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6621 struct hdac_widget *w, *cw; 6622 char buf[64]; 6623 int i, printed = 0; 6624 6625 if (depth > HDA_PARSE_MAXDEPTH) 6626 return; 6627 6628 w = hdac_widget_get(devinfo, nid); 6629 if (w == NULL || w->enable == 0) 6630 return; 6631 6632 if (depth == 0) 6633 device_printf(pdevinfo->dev, "%*s", 4, ""); 6634 else 6635 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6636 printf("nid=%d [%s]", w->nid, w->name); 6637 6638 if (depth > 0) { 6639 if (w->ossmask == 0) { 6640 printf("\n"); 6641 return; 6642 } 6643 printf(" [src: %s]", 6644 hdac_audio_ctl_ossmixer_mask2allname( 6645 w->ossmask, buf, sizeof(buf))); 6646 if (w->ossdev >= 0) { 6647 printf("\n"); 6648 return; 6649 } 6650 } 6651 printf("\n"); 6652 6653 for (i = 0; i < w->nconns; i++) { 6654 if (w->connsenable[i] == 0) 6655 continue; 6656 cw = hdac_widget_get(devinfo, w->conns[i]); 6657 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6658 continue; 6659 if (printed == 0) { 6660 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6661 printed = 1; 6662 } 6663 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6664 } 6665 6666} 6667 6668static void 6669hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6670{ 6671 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6672 struct hdac_softc *sc = devinfo->codec->sc; 6673 struct hdac_widget *w; 6674 int i, printed = 0; 6675 6676 if (pdevinfo->play < 0) 6677 return; 6678 6679 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6680 w = hdac_widget_get(devinfo, i); 6681 if (w == NULL || w->enable == 0) 6682 continue; 6683 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6684 continue; 6685 if (w->bindas != sc->chans[pdevinfo->play].as) 6686 continue; 6687 if (printed == 0) { 6688 printed = 1; 6689 device_printf(pdevinfo->dev, "\n"); 6690 device_printf(pdevinfo->dev, "Playback:\n"); 6691 } 6692 device_printf(pdevinfo->dev, "\n"); 6693 hdac_dump_dst_nid(pdevinfo, i, 0); 6694 } 6695} 6696 6697static void 6698hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6699{ 6700 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6701 struct hdac_softc *sc = devinfo->codec->sc; 6702 struct hdac_widget *w; 6703 int i; 6704 int printed = 0; 6705 6706 if (pdevinfo->rec < 0) 6707 return; 6708 6709 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6710 w = hdac_widget_get(devinfo, i); 6711 if (w == NULL || w->enable == 0) 6712 continue; 6713 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6714 continue; 6715 if (w->bindas != sc->chans[pdevinfo->rec].as) 6716 continue; 6717 if (printed == 0) { 6718 printed = 1; 6719 device_printf(pdevinfo->dev, "\n"); 6720 device_printf(pdevinfo->dev, "Record:\n"); 6721 } 6722 device_printf(pdevinfo->dev, "\n"); 6723 hdac_dump_dst_nid(pdevinfo, i, 0); 6724 } 6725} 6726 6727static void 6728hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6729{ 6730 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6731 struct hdac_widget *w; 6732 int i; 6733 int printed = 0; 6734 6735 if (pdevinfo->index != 0) 6736 return; 6737 6738 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6739 w = hdac_widget_get(devinfo, i); 6740 if (w == NULL || w->enable == 0) 6741 continue; 6742 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6743 continue; 6744 if (printed == 0) { 6745 printed = 1; 6746 device_printf(pdevinfo->dev, "\n"); 6747 device_printf(pdevinfo->dev, "Input Mix:\n"); 6748 } 6749 device_printf(pdevinfo->dev, "\n"); 6750 hdac_dump_dst_nid(pdevinfo, i, 0); 6751 } 6752} 6753 6754static void 6755hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6756{ 6757 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6758 nid_t *nids; 6759 int i; 6760 6761 if (pdevinfo->play >= 0) { 6762 i = pdevinfo->play; 6763 device_printf(pdevinfo->dev, "\n"); 6764 device_printf(pdevinfo->dev, "Playback:\n"); 6765 device_printf(pdevinfo->dev, "\n"); 6766 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6767 sc->chans[i].supp_pcm_size_rate); 6768 device_printf(pdevinfo->dev, " DAC:"); 6769 for (nids = sc->chans[i].io; *nids != -1; nids++) 6770 printf(" %d", *nids); 6771 printf("\n"); 6772 } 6773 if (pdevinfo->rec >= 0) { 6774 i = pdevinfo->rec; 6775 device_printf(pdevinfo->dev, "\n"); 6776 device_printf(pdevinfo->dev, "Record:\n"); 6777 device_printf(pdevinfo->dev, "\n"); 6778 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6779 sc->chans[i].supp_pcm_size_rate); 6780 device_printf(pdevinfo->dev, " ADC:"); 6781 for (nids = sc->chans[i].io; *nids != -1; nids++) 6782 printf(" %d", *nids); 6783 printf("\n"); 6784 } 6785} 6786 6787static void 6788hdac_release_resources(struct hdac_softc *sc) 6789{ 6790 int i, j; 6791 6792 if (sc == NULL) 6793 return; 6794 6795 hdac_lock(sc); 6796 sc->polling = 0; 6797 sc->poll_ival = 0; 6798 callout_stop(&sc->poll_hda); 6799 callout_stop(&sc->poll_hdac); 6800 callout_stop(&sc->poll_jack); 6801 hdac_reset(sc, 0); 6802 hdac_unlock(sc); 6803 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6804 callout_drain(&sc->poll_hda); 6805 callout_drain(&sc->poll_hdac); 6806 callout_drain(&sc->poll_jack); 6807 6808 hdac_irq_free(sc); 6809 6810 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6811 if (sc->codecs[i] == NULL) 6812 continue; 6813 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6814 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6815 if (sc->codecs[i]->fgs[j].node_type == 6816 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6817 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6818 M_HDAC); 6819 free(sc->codecs[i]->fgs[j].function.audio.as, 6820 M_HDAC); 6821 free(sc->codecs[i]->fgs[j].function.audio.devs, 6822 M_HDAC); 6823 } 6824 } 6825 free(sc->codecs[i]->fgs, M_HDAC); 6826 free(sc->codecs[i], M_HDAC); 6827 sc->codecs[i] = NULL; 6828 } 6829 6830 hdac_dma_free(sc, &sc->pos_dma); 6831 hdac_dma_free(sc, &sc->rirb_dma); 6832 hdac_dma_free(sc, &sc->corb_dma); 6833 for (i = 0; i < sc->num_chans; i++) { 6834 if (sc->chans[i].blkcnt > 0) 6835 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6836 } 6837 free(sc->chans, M_HDAC); 6838 if (sc->chan_dmat != NULL) { 6839 bus_dma_tag_destroy(sc->chan_dmat); 6840 sc->chan_dmat = NULL; 6841 } 6842 hdac_mem_free(sc); 6843 snd_mtxfree(sc->lock); 6844} 6845 6846/* This function surely going to make its way into upper level someday. */ 6847static void 6848hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6849{ 6850 const char *res = NULL; 6851 int i = 0, j, k, len, inv; 6852 6853 if (on != NULL) 6854 *on = 0; 6855 if (off != NULL) 6856 *off = 0; 6857 if (sc == NULL) 6858 return; 6859 if (resource_string_value(device_get_name(sc->dev), 6860 device_get_unit(sc->dev), "config", &res) != 0) 6861 return; 6862 if (!(res != NULL && strlen(res) > 0)) 6863 return; 6864 HDA_BOOTVERBOSE( 6865 device_printf(sc->dev, "HDA Config:"); 6866 ); 6867 for (;;) { 6868 while (res[i] != '\0' && 6869 (res[i] == ',' || isspace(res[i]) != 0)) 6870 i++; 6871 if (res[i] == '\0') { 6872 HDA_BOOTVERBOSE( 6873 printf("\n"); 6874 ); 6875 return; 6876 } 6877 j = i; 6878 while (res[j] != '\0' && 6879 !(res[j] == ',' || isspace(res[j]) != 0)) 6880 j++; 6881 len = j - i; 6882 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6883 inv = 2; 6884 else 6885 inv = 0; 6886 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6887 if (strncmp(res + i + inv, 6888 hdac_quirks_tab[k].key, len - inv) != 0) 6889 continue; 6890 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6891 break; 6892 HDA_BOOTVERBOSE( 6893 printf(" %s%s", (inv != 0) ? "no" : "", 6894 hdac_quirks_tab[k].key); 6895 ); 6896 if (inv == 0 && on != NULL) 6897 *on |= hdac_quirks_tab[k].value; 6898 else if (inv != 0 && off != NULL) 6899 *off |= hdac_quirks_tab[k].value; 6900 break; 6901 } 6902 i = j; 6903 } 6904} 6905 6906#ifdef SND_DYNSYSCTL 6907static int 6908sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6909{ 6910 struct hdac_softc *sc; 6911 device_t dev; 6912 uint32_t ctl; 6913 int err, val; 6914 6915 dev = oidp->oid_arg1; 6916 sc = device_get_softc(dev); 6917 if (sc == NULL) 6918 return (EINVAL); 6919 hdac_lock(sc); 6920 val = sc->polling; 6921 hdac_unlock(sc); 6922 err = sysctl_handle_int(oidp, &val, 0, req); 6923 6924 if (err != 0 || req->newptr == NULL) 6925 return (err); 6926 if (val < 0 || val > 1) 6927 return (EINVAL); 6928 6929 hdac_lock(sc); 6930 if (val != sc->polling) { 6931 if (val == 0) { 6932 callout_stop(&sc->poll_hda); 6933 callout_stop(&sc->poll_hdac); 6934 hdac_unlock(sc); 6935 callout_drain(&sc->poll_hda); 6936 callout_drain(&sc->poll_hdac); 6937 hdac_lock(sc); 6938 sc->polling = 0; 6939 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6940 ctl |= HDAC_INTCTL_GIE; 6941 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6942 } else { 6943 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6944 ctl &= ~HDAC_INTCTL_GIE; 6945 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6946 hdac_unlock(sc); 6947 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6948 hdac_lock(sc); 6949 sc->polling = 1; 6950 hdac_poll_reinit(sc); 6951 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6952 } 6953 } 6954 hdac_unlock(sc); 6955 6956 return (err); 6957} 6958 6959static int 6960sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6961{ 6962 struct hdac_softc *sc; 6963 device_t dev; 6964 int err, val; 6965 6966 dev = oidp->oid_arg1; 6967 sc = device_get_softc(dev); 6968 if (sc == NULL) 6969 return (EINVAL); 6970 hdac_lock(sc); 6971 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6972 hdac_unlock(sc); 6973 err = sysctl_handle_int(oidp, &val, 0, req); 6974 6975 if (err != 0 || req->newptr == NULL) 6976 return (err); 6977 6978 if (val < 1) 6979 val = 1; 6980 if (val > 5000) 6981 val = 5000; 6982 val = ((uint64_t)val * hz) / 1000; 6983 if (val < 1) 6984 val = 1; 6985 if (val > (hz * 5)) 6986 val = hz * 5; 6987 6988 hdac_lock(sc); 6989 sc->poll_ival = val; 6990 hdac_unlock(sc); 6991 6992 return (err); 6993} 6994 6995static int 6996sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6997{ 6998 struct hdac_softc *sc; 6999 struct hdac_codec *codec; 7000 struct hdac_devinfo *devinfo; 7001 struct hdac_widget *w; 7002 device_t dev; 7003 uint32_t res, pincap, delay; 7004 int codec_index, fg_index; 7005 int i, err, val; 7006 nid_t cad; 7007 7008 dev = oidp->oid_arg1; 7009 sc = device_get_softc(dev); 7010 if (sc == NULL) 7011 return (EINVAL); 7012 val = 0; 7013 err = sysctl_handle_int(oidp, &val, 0, req); 7014 if (err != 0 || req->newptr == NULL || val == 0) 7015 return (err); 7016 7017 /* XXX: Temporary. For debugging. */ 7018 if (val == 100) { 7019 hdac_suspend(dev); 7020 return (0); 7021 } else if (val == 101) { 7022 hdac_resume(dev); 7023 return (0); 7024 } 7025 7026 hdac_lock(sc); 7027 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7028 codec = sc->codecs[codec_index]; 7029 if (codec == NULL) 7030 continue; 7031 cad = codec->cad; 7032 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7033 devinfo = &codec->fgs[fg_index]; 7034 if (devinfo->node_type != 7035 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7036 continue; 7037 7038 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7039 codec_index, devinfo->nid); 7040 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7041 w = hdac_widget_get(devinfo, i); 7042 if (w == NULL || w->type != 7043 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7044 continue; 7045 hdac_dump_pin_config(w, w->wclass.pin.config); 7046 pincap = w->wclass.pin.cap; 7047 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7048 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7049 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7050 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7051 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7052 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7053 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7054 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7055 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7056 delay = 0; 7057 hdac_command(sc, 7058 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7059 do { 7060 res = hdac_command(sc, 7061 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7062 if (res != 0x7fffffff && res != 0xffffffff) 7063 break; 7064 DELAY(10); 7065 } while (++delay < 10000); 7066 } else { 7067 delay = 0; 7068 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7069 w->nid), cad); 7070 } 7071 printf(" Sense: 0x%08x", res); 7072 if (delay > 0) 7073 printf(" delay %dus", delay * 10); 7074 } 7075 printf("\n"); 7076 } 7077 device_printf(dev, 7078 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7079 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7080 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7081 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7082 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7083 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7084 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7085 device_printf(dev, " GPI:"); 7086 res = hdac_command(sc, 7087 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7088 printf(" data=0x%08x", res); 7089 res = hdac_command(sc, 7090 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7091 cad); 7092 printf(" wake=0x%08x", res); 7093 res = hdac_command(sc, 7094 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7095 cad); 7096 printf(" unsol=0x%08x", res); 7097 res = hdac_command(sc, 7098 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7099 printf(" sticky=0x%08x\n", res); 7100 } 7101 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7102 device_printf(dev, " GPO:"); 7103 res = hdac_command(sc, 7104 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7105 printf(" data=0x%08x\n", res); 7106 } 7107 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7108 device_printf(dev, "GPIO:"); 7109 res = hdac_command(sc, 7110 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7111 printf(" data=0x%08x", res); 7112 res = hdac_command(sc, 7113 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7114 printf(" enable=0x%08x", res); 7115 res = hdac_command(sc, 7116 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7117 printf(" direction=0x%08x\n", res); 7118 res = hdac_command(sc, 7119 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7120 device_printf(dev, " wake=0x%08x", res); 7121 res = hdac_command(sc, 7122 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7123 cad); 7124 printf(" unsol=0x%08x", res); 7125 res = hdac_command(sc, 7126 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7127 printf(" sticky=0x%08x\n", res); 7128 } 7129 } 7130 } 7131 hdac_unlock(sc); 7132 return (0); 7133} 7134#endif 7135 7136static void 7137hdac_attach2(void *arg) 7138{ 7139 struct hdac_codec *codec; 7140 struct hdac_softc *sc; 7141 struct hdac_audio_ctl *ctl; 7142 uint32_t quirks_on, quirks_off; 7143 int codec_index, fg_index; 7144 int i, dmaalloc = 0; 7145 struct hdac_devinfo *devinfo; 7146 7147 sc = (struct hdac_softc *)arg; 7148 7149 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7150 7151 HDA_BOOTHVERBOSE( 7152 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7153 quirks_on, quirks_off); 7154 ); 7155 7156 hdac_lock(sc); 7157 7158 /* Remove ourselves from the config hooks */ 7159 if (sc->intrhook.ich_func != NULL) { 7160 config_intrhook_disestablish(&sc->intrhook); 7161 sc->intrhook.ich_func = NULL; 7162 } 7163 7164 /* Start the corb and rirb engines */ 7165 HDA_BOOTHVERBOSE( 7166 device_printf(sc->dev, "Starting CORB Engine...\n"); 7167 ); 7168 hdac_corb_start(sc); 7169 HDA_BOOTHVERBOSE( 7170 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7171 ); 7172 hdac_rirb_start(sc); 7173 7174 HDA_BOOTHVERBOSE( 7175 device_printf(sc->dev, 7176 "Enabling controller interrupt...\n"); 7177 ); 7178 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7179 HDAC_GCTL_UNSOL); 7180 if (sc->polling == 0) { 7181 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7182 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7183 } else { 7184 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7185 } 7186 DELAY(1000); 7187 7188 HDA_BOOTHVERBOSE( 7189 device_printf(sc->dev, 7190 "Scanning HDA codecs ...\n"); 7191 ); 7192 hdac_scan_codecs(sc); 7193 7194 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7195 codec = sc->codecs[codec_index]; 7196 if (codec == NULL) 7197 continue; 7198 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7199 devinfo = &codec->fgs[fg_index]; 7200 HDA_BOOTVERBOSE( 7201 device_printf(sc->dev, "\n"); 7202 device_printf(sc->dev, 7203 "Processing %s FG cad=%d nid=%d...\n", 7204 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7205 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7206 "unknown", 7207 devinfo->codec->cad, devinfo->nid); 7208 ); 7209 if (devinfo->node_type != 7210 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7211 HDA_BOOTHVERBOSE( 7212 device_printf(sc->dev, 7213 "Powering down...\n"); 7214 ); 7215 hdac_command(sc, 7216 HDA_CMD_SET_POWER_STATE(codec->cad, 7217 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7218 codec->cad); 7219 continue; 7220 } 7221 7222 HDA_BOOTHVERBOSE( 7223 device_printf(sc->dev, "Powering up...\n"); 7224 ); 7225 hdac_powerup(devinfo); 7226 HDA_BOOTHVERBOSE( 7227 device_printf(sc->dev, "Parsing audio FG...\n"); 7228 ); 7229 hdac_audio_parse(devinfo); 7230 HDA_BOOTHVERBOSE( 7231 device_printf(sc->dev, "Parsing Ctls...\n"); 7232 ); 7233 hdac_audio_ctl_parse(devinfo); 7234 HDA_BOOTHVERBOSE( 7235 device_printf(sc->dev, "Parsing vendor patch...\n"); 7236 ); 7237 hdac_vendor_patch_parse(devinfo); 7238 devinfo->function.audio.quirks |= quirks_on; 7239 devinfo->function.audio.quirks &= ~quirks_off; 7240 7241 HDA_BOOTHVERBOSE( 7242 device_printf(sc->dev, "Disabling nonaudio...\n"); 7243 ); 7244 hdac_audio_disable_nonaudio(devinfo); 7245 HDA_BOOTHVERBOSE( 7246 device_printf(sc->dev, "Disabling useless...\n"); 7247 ); 7248 hdac_audio_disable_useless(devinfo); 7249 HDA_BOOTVERBOSE( 7250 device_printf(sc->dev, "Patched pins configuration:\n"); 7251 hdac_dump_pin_configs(devinfo); 7252 ); 7253 HDA_BOOTHVERBOSE( 7254 device_printf(sc->dev, "Parsing pin associations...\n"); 7255 ); 7256 hdac_audio_as_parse(devinfo); 7257 HDA_BOOTHVERBOSE( 7258 device_printf(sc->dev, "Building AFG tree...\n"); 7259 ); 7260 hdac_audio_build_tree(devinfo); 7261 HDA_BOOTHVERBOSE( 7262 device_printf(sc->dev, "Disabling unassociated " 7263 "widgets...\n"); 7264 ); 7265 hdac_audio_disable_unas(devinfo); 7266 HDA_BOOTHVERBOSE( 7267 device_printf(sc->dev, "Disabling nonselected " 7268 "inputs...\n"); 7269 ); 7270 hdac_audio_disable_notselected(devinfo); 7271 HDA_BOOTHVERBOSE( 7272 device_printf(sc->dev, "Disabling useless...\n"); 7273 ); 7274 hdac_audio_disable_useless(devinfo); 7275 HDA_BOOTHVERBOSE( 7276 device_printf(sc->dev, "Disabling " 7277 "crossassociatement connections...\n"); 7278 ); 7279 hdac_audio_disable_crossas(devinfo); 7280 HDA_BOOTHVERBOSE( 7281 device_printf(sc->dev, "Disabling useless...\n"); 7282 ); 7283 hdac_audio_disable_useless(devinfo); 7284 HDA_BOOTHVERBOSE( 7285 device_printf(sc->dev, "Binding associations to channels...\n"); 7286 ); 7287 hdac_audio_bind_as(devinfo); 7288 HDA_BOOTHVERBOSE( 7289 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7290 ); 7291 hdac_audio_assign_names(devinfo); 7292 HDA_BOOTHVERBOSE( 7293 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7294 ); 7295 hdac_audio_assign_mixers(devinfo); 7296 HDA_BOOTHVERBOSE( 7297 device_printf(sc->dev, "Preparing pin controls...\n"); 7298 ); 7299 hdac_audio_prepare_pin_ctrl(devinfo); 7300 HDA_BOOTHVERBOSE( 7301 device_printf(sc->dev, "AFG commit...\n"); 7302 ); 7303 hdac_audio_commit(devinfo); 7304 HDA_BOOTHVERBOSE( 7305 device_printf(sc->dev, "Ctls commit...\n"); 7306 ); 7307 hdac_audio_ctl_commit(devinfo); 7308 HDA_BOOTHVERBOSE( 7309 device_printf(sc->dev, "HP switch init...\n"); 7310 ); 7311 hdac_hp_switch_init(devinfo); 7312 7313 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7314 dmaalloc == 0) { 7315 if (hdac_dma_alloc(sc, &sc->pos_dma, 7316 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7317 HDA_BOOTVERBOSE( 7318 device_printf(sc->dev, "Failed to " 7319 "allocate DMA pos buffer " 7320 "(non-fatal)\n"); 7321 ); 7322 } else 7323 dmaalloc = 1; 7324 } 7325 7326 HDA_BOOTHVERBOSE( 7327 device_printf(sc->dev, "Creating PCM devices...\n"); 7328 ); 7329 hdac_create_pcms(devinfo); 7330 7331 HDA_BOOTVERBOSE( 7332 if (devinfo->function.audio.quirks != 0) { 7333 device_printf(sc->dev, "FG config/quirks:"); 7334 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7335 if ((devinfo->function.audio.quirks & 7336 hdac_quirks_tab[i].value) == 7337 hdac_quirks_tab[i].value) 7338 printf(" %s", hdac_quirks_tab[i].key); 7339 } 7340 printf("\n"); 7341 } 7342 7343 device_printf(sc->dev, "\n"); 7344 device_printf(sc->dev, "+-------------------+\n"); 7345 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7346 device_printf(sc->dev, "+-------------------+\n"); 7347 hdac_dump_nodes(devinfo); 7348 ); 7349 7350 HDA_BOOTHVERBOSE( 7351 device_printf(sc->dev, "\n"); 7352 device_printf(sc->dev, "+------------------------+\n"); 7353 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7354 device_printf(sc->dev, "+------------------------+\n"); 7355 device_printf(sc->dev, "\n"); 7356 i = 0; 7357 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7358 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7359 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7360 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7361 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7362 ctl->index); 7363 if (ctl->childwidget != NULL) 7364 printf(" cnid %3d", ctl->childwidget->nid); 7365 else 7366 printf(" "); 7367 printf(" ossmask=0x%08x\n", 7368 ctl->ossmask); 7369 device_printf(sc->dev, 7370 " mute: %d step: %3d size: %3d off: %3d%s\n", 7371 ctl->mute, ctl->step, ctl->size, ctl->offset, 7372 (ctl->enable == 0) ? " [DISABLED]" : 7373 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7374 } 7375 ); 7376 } 7377 } 7378 hdac_unlock(sc); 7379 7380 HDA_BOOTVERBOSE( 7381 device_printf(sc->dev, "\n"); 7382 ); 7383 7384 bus_generic_attach(sc->dev); 7385 7386#ifdef SND_DYNSYSCTL 7387 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7388 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7389 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7390 sysctl_hdac_polling, "I", "Enable polling mode"); 7391 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7392 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7393 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7394 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7395 "Controller/Jack Sense polling interval (1-1000 ms)"); 7396 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7397 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7398 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7399 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7400#endif 7401} 7402 7403/**************************************************************************** 7404 * int hdac_suspend(device_t) 7405 * 7406 * Suspend and power down HDA bus and codecs. 7407 ****************************************************************************/ 7408static int 7409hdac_suspend(device_t dev) 7410{ 7411 struct hdac_softc *sc; 7412 struct hdac_codec *codec; 7413 struct hdac_devinfo *devinfo; 7414 int codec_index, fg_index, i; 7415 7416 HDA_BOOTHVERBOSE( 7417 device_printf(dev, "Suspend...\n"); 7418 ); 7419 7420 sc = device_get_softc(dev); 7421 hdac_lock(sc); 7422 7423 HDA_BOOTHVERBOSE( 7424 device_printf(dev, "Stop streams...\n"); 7425 ); 7426 for (i = 0; i < sc->num_chans; i++) { 7427 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7428 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7429 hdac_channel_stop(sc, &sc->chans[i]); 7430 } 7431 } 7432 7433 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7434 codec = sc->codecs[codec_index]; 7435 if (codec == NULL) 7436 continue; 7437 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7438 devinfo = &codec->fgs[fg_index]; 7439 HDA_BOOTHVERBOSE( 7440 device_printf(dev, 7441 "Power down FG" 7442 " cad=%d nid=%d to the D3 state...\n", 7443 codec->cad, devinfo->nid); 7444 ); 7445 hdac_command(sc, 7446 HDA_CMD_SET_POWER_STATE(codec->cad, 7447 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7448 codec->cad); 7449 } 7450 } 7451 7452 HDA_BOOTHVERBOSE( 7453 device_printf(dev, "Reset controller...\n"); 7454 ); 7455 callout_stop(&sc->poll_hda); 7456 callout_stop(&sc->poll_hdac); 7457 callout_stop(&sc->poll_jack); 7458 hdac_reset(sc, 0); 7459 hdac_unlock(sc); 7460 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7461 callout_drain(&sc->poll_hda); 7462 callout_drain(&sc->poll_hdac); 7463 callout_drain(&sc->poll_jack); 7464 7465 HDA_BOOTHVERBOSE( 7466 device_printf(dev, "Suspend done\n"); 7467 ); 7468 7469 return (0); 7470} 7471 7472/**************************************************************************** 7473 * int hdac_resume(device_t) 7474 * 7475 * Powerup and restore HDA bus and codecs state. 7476 ****************************************************************************/ 7477static int 7478hdac_resume(device_t dev) 7479{ 7480 struct hdac_softc *sc; 7481 struct hdac_codec *codec; 7482 struct hdac_devinfo *devinfo; 7483 int codec_index, fg_index, i; 7484 7485 HDA_BOOTHVERBOSE( 7486 device_printf(dev, "Resume...\n"); 7487 ); 7488 7489 sc = device_get_softc(dev); 7490 hdac_lock(sc); 7491 7492 /* Quiesce everything */ 7493 HDA_BOOTHVERBOSE( 7494 device_printf(dev, "Reset controller...\n"); 7495 ); 7496 hdac_reset(sc, 1); 7497 7498 /* Initialize the CORB and RIRB */ 7499 hdac_corb_init(sc); 7500 hdac_rirb_init(sc); 7501 7502 /* Start the corb and rirb engines */ 7503 HDA_BOOTHVERBOSE( 7504 device_printf(dev, "Starting CORB Engine...\n"); 7505 ); 7506 hdac_corb_start(sc); 7507 HDA_BOOTHVERBOSE( 7508 device_printf(dev, "Starting RIRB Engine...\n"); 7509 ); 7510 hdac_rirb_start(sc); 7511 7512 HDA_BOOTHVERBOSE( 7513 device_printf(dev, 7514 "Enabling controller interrupt...\n"); 7515 ); 7516 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7517 HDAC_GCTL_UNSOL); 7518 if (sc->polling == 0) { 7519 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7520 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7521 } else { 7522 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7523 } 7524 DELAY(1000); 7525 7526 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7527 codec = sc->codecs[codec_index]; 7528 if (codec == NULL) 7529 continue; 7530 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7531 devinfo = &codec->fgs[fg_index]; 7532 if (devinfo->node_type != 7533 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7534 HDA_BOOTHVERBOSE( 7535 device_printf(dev, 7536 "Power down unsupported non-audio FG" 7537 " cad=%d nid=%d to the D3 state...\n", 7538 codec->cad, devinfo->nid); 7539 ); 7540 hdac_command(sc, 7541 HDA_CMD_SET_POWER_STATE(codec->cad, 7542 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7543 codec->cad); 7544 continue; 7545 } 7546 7547 HDA_BOOTHVERBOSE( 7548 device_printf(dev, 7549 "Power up audio FG cad=%d nid=%d...\n", 7550 devinfo->codec->cad, devinfo->nid); 7551 ); 7552 hdac_powerup(devinfo); 7553 HDA_BOOTHVERBOSE( 7554 device_printf(dev, "AFG commit...\n"); 7555 ); 7556 hdac_audio_commit(devinfo); 7557 HDA_BOOTHVERBOSE( 7558 device_printf(dev, "Ctls commit...\n"); 7559 ); 7560 hdac_audio_ctl_commit(devinfo); 7561 HDA_BOOTHVERBOSE( 7562 device_printf(dev, "HP switch init...\n"); 7563 ); 7564 hdac_hp_switch_init(devinfo); 7565 7566 hdac_unlock(sc); 7567 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7568 struct hdac_pcm_devinfo *pdevinfo = 7569 &devinfo->function.audio.devs[i]; 7570 HDA_BOOTHVERBOSE( 7571 device_printf(pdevinfo->dev, 7572 "OSS mixer reinitialization...\n"); 7573 ); 7574 if (mixer_reinit(pdevinfo->dev) == -1) 7575 device_printf(pdevinfo->dev, 7576 "unable to reinitialize the mixer\n"); 7577 } 7578 hdac_lock(sc); 7579 } 7580 } 7581 7582 HDA_BOOTHVERBOSE( 7583 device_printf(dev, "Start streams...\n"); 7584 ); 7585 for (i = 0; i < sc->num_chans; i++) { 7586 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7587 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7588 hdac_channel_start(sc, &sc->chans[i]); 7589 } 7590 } 7591 7592 hdac_unlock(sc); 7593 7594 HDA_BOOTHVERBOSE( 7595 device_printf(dev, "Resume done\n"); 7596 ); 7597 7598 return (0); 7599} 7600/**************************************************************************** 7601 * int hdac_detach(device_t) 7602 * 7603 * Detach and free up resources utilized by the hdac device. 7604 ****************************************************************************/ 7605static int 7606hdac_detach(device_t dev) 7607{ 7608 struct hdac_softc *sc; 7609 device_t *devlist; 7610 int i, devcount, error; 7611 7612 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7613 return (error); 7614 for (i = 0; i < devcount; i++) { 7615 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7616 free(devlist, M_TEMP); 7617 return (error); 7618 } 7619 } 7620 free(devlist, M_TEMP); 7621 7622 sc = device_get_softc(dev); 7623 hdac_release_resources(sc); 7624 7625 return (0); 7626} 7627 7628static int 7629hdac_print_child(device_t dev, device_t child) 7630{ 7631 struct hdac_pcm_devinfo *pdevinfo = 7632 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7633 int retval; 7634 7635 retval = bus_print_child_header(dev, child); 7636 retval += printf(" at cad %d nid %d", 7637 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7638 retval += bus_print_child_footer(dev, child); 7639 7640 return (retval); 7641} 7642 7643static device_method_t hdac_methods[] = { 7644 /* device interface */ 7645 DEVMETHOD(device_probe, hdac_probe), 7646 DEVMETHOD(device_attach, hdac_attach), 7647 DEVMETHOD(device_detach, hdac_detach), 7648 DEVMETHOD(device_suspend, hdac_suspend), 7649 DEVMETHOD(device_resume, hdac_resume), 7650 /* Bus interface */ 7651 DEVMETHOD(bus_print_child, hdac_print_child), 7652 { 0, 0 } 7653}; 7654 7655static driver_t hdac_driver = { 7656 "hdac", 7657 hdac_methods, 7658 sizeof(struct hdac_softc), 7659}; 7660 7661static devclass_t hdac_devclass; 7662 7663DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7664MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7665MODULE_VERSION(snd_hda, 1); 7666 7667static int 7668hdac_pcm_probe(device_t dev) 7669{ 7670 struct hdac_pcm_devinfo *pdevinfo = 7671 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7672 char buf[128]; 7673 7674 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7675 hdac_codec_name(pdevinfo->devinfo->codec), 7676 pdevinfo->index, 7677 pdevinfo->digital?"Digital":"Analog"); 7678 device_set_desc_copy(dev, buf); 7679 return (0); 7680} 7681 7682static int 7683hdac_pcm_attach(device_t dev) 7684{ 7685 struct hdac_pcm_devinfo *pdevinfo = 7686 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7687 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7688 char status[SND_STATUSLEN]; 7689 int i; 7690 7691 pdevinfo->chan_size = pcm_getbuffersize(dev, 7692 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7693 7694 HDA_BOOTVERBOSE( 7695 device_printf(dev, "+--------------------------------------+\n"); 7696 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7697 device_printf(dev, "+--------------------------------------+\n"); 7698 hdac_dump_pcmchannels(pdevinfo); 7699 device_printf(dev, "\n"); 7700 device_printf(dev, "+--------------------------------+\n"); 7701 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7702 device_printf(dev, "+--------------------------------+\n"); 7703 hdac_dump_dac(pdevinfo); 7704 hdac_dump_adc(pdevinfo); 7705 hdac_dump_mix(pdevinfo); 7706 device_printf(dev, "\n"); 7707 device_printf(dev, "+-------------------------+\n"); 7708 device_printf(dev, "| DUMPING Volume Controls |\n"); 7709 device_printf(dev, "+-------------------------+\n"); 7710 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7711 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7712 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7713 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7714 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7715 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7716 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7717 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7718 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7719 hdac_dump_ctls(pdevinfo, NULL, 0); 7720 device_printf(dev, "\n"); 7721 ); 7722 7723 if (resource_int_value(device_get_name(dev), 7724 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7725 i &= HDA_BLK_ALIGN; 7726 if (i < HDA_BLK_MIN) 7727 i = HDA_BLK_MIN; 7728 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7729 i = 0; 7730 while (pdevinfo->chan_blkcnt >> i) 7731 i++; 7732 pdevinfo->chan_blkcnt = 1 << (i - 1); 7733 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7734 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7735 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7736 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7737 } else 7738 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7739 7740 /* 7741 * We don't register interrupt handler with snd_setup_intr 7742 * in pcm device. Mark pcm device as MPSAFE manually. 7743 */ 7744 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7745 7746 HDA_BOOTHVERBOSE( 7747 device_printf(dev, "OSS mixer initialization...\n"); 7748 ); 7749 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7750 device_printf(dev, "Can't register mixer\n"); 7751 7752 HDA_BOOTHVERBOSE( 7753 device_printf(dev, "Registering PCM channels...\n"); 7754 ); 7755 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7756 (pdevinfo->rec >= 0)?1:0) != 0) 7757 device_printf(dev, "Can't register PCM\n"); 7758 7759 pdevinfo->registered++; 7760 7761 if (pdevinfo->play >= 0) 7762 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7763 if (pdevinfo->rec >= 0) 7764 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7765 7766 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7767 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7768 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7769 pcm_setstatus(dev, status); 7770 7771 return (0); 7772} 7773 7774static int 7775hdac_pcm_detach(device_t dev) 7776{ 7777 struct hdac_pcm_devinfo *pdevinfo = 7778 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7779 int err; 7780 7781 if (pdevinfo->registered > 0) { 7782 err = pcm_unregister(dev); 7783 if (err != 0) 7784 return (err); 7785 } 7786 7787 return (0); 7788} 7789 7790static device_method_t hdac_pcm_methods[] = { 7791 /* device interface */ 7792 DEVMETHOD(device_probe, hdac_pcm_probe), 7793 DEVMETHOD(device_attach, hdac_pcm_attach), 7794 DEVMETHOD(device_detach, hdac_pcm_detach), 7795 { 0, 0 } 7796}; 7797 7798static driver_t hdac_pcm_driver = { 7799 "pcm", 7800 hdac_pcm_methods, 7801 PCM_SOFTC_SIZE, 7802}; 7803 7804DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7805 7806