hdac.c revision 184483
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20081030_0115" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 184483 2008-10-30 17:54:20Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 166 167/* ATI */ 168#define ATI_VENDORID 0x1002 169#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 170#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 171#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 172 173/* VIA */ 174#define VIA_VENDORID 0x1106 175#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 176#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 177 178/* SiS */ 179#define SIS_VENDORID 0x1039 180#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 181#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 182 183/* OEM/subvendors */ 184 185/* Intel */ 186#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 187 188/* HP/Compaq */ 189#define HP_VENDORID 0x103c 190#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 191#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 192#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 193#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 194#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 195#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 196#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 197#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 198#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 199#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 200/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 201#define HP_NX6325_SUBVENDORX 0x103c30b0 202 203/* Dell */ 204#define DELL_VENDORID 0x1028 205#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 206#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 207#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 208#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 209#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 210#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 211#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 212#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 213 214/* Clevo */ 215#define CLEVO_VENDORID 0x1558 216#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 217#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 218 219/* Acer */ 220#define ACER_VENDORID 0x1025 221#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 222#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 223#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 224#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 225#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 226#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 227#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 228 229/* Asus */ 230#define ASUS_VENDORID 0x1043 231#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 232#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 233#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 234#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 235#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 236#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 237#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 238#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 239#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 240#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 241#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 242#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 243#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 244#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 245#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 246#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 247 248/* IBM / Lenovo */ 249#define IBM_VENDORID 0x1014 250#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 251#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 252 253/* Lenovo */ 254#define LENOVO_VENDORID 0x17aa 255#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 256#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 257#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 258#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 259 260/* Samsung */ 261#define SAMSUNG_VENDORID 0x144d 262#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 263#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 264 265/* Medion ? */ 266#define MEDION_VENDORID 0x161f 267#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 268#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 269 270/* Apple Computer Inc. */ 271#define APPLE_VENDORID 0x106b 272#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 273 274/* Sony */ 275#define SONY_VENDORID 0x104d 276#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 277#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 278 279/* 280 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 281 * instead of their own, which is beyond my comprehension 282 * (see HDA_CODEC_STAC9221 below). 283 */ 284#define APPLE_INTEL_MAC 0x76808384 285 286/* LG Electronics */ 287#define LG_VENDORID 0x1854 288#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 289#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 290 291/* Fujitsu Siemens */ 292#define FS_VENDORID 0x1734 293#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 294#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 295#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 296 297/* Fujitsu Limited */ 298#define FL_VENDORID 0x10cf 299#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 300#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 301#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 302 303/* Toshiba */ 304#define TOSHIBA_VENDORID 0x1179 305#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 306#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 307#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 308 309/* Micro-Star International (MSI) */ 310#define MSI_VENDORID 0x1462 311#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 312#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 313#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 314 315/* Giga-Byte Technology */ 316#define GB_VENDORID 0x1458 317#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 318#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 319 320/* Uniwill ? */ 321#define UNIWILL_VENDORID 0x1584 322#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 323#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 324 325 326/* Misc constants.. */ 327#define HDA_AMP_VOL_DEFAULT (-1) 328#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 329#define HDA_AMP_MUTE_NONE (0) 330#define HDA_AMP_MUTE_LEFT (1 << 0) 331#define HDA_AMP_MUTE_RIGHT (1 << 1) 332#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 333 334#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 335#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 336 337#define HDA_ADC_MONITOR (1 << 0) 338 339#define HDA_CTL_OUT 1 340#define HDA_CTL_IN 2 341 342#define HDA_GPIO_MAX 8 343/* 0 - 7 = GPIO , 8 = Flush */ 344#define HDA_QUIRK_GPIO0 (1 << 0) 345#define HDA_QUIRK_GPIO1 (1 << 1) 346#define HDA_QUIRK_GPIO2 (1 << 2) 347#define HDA_QUIRK_GPIO3 (1 << 3) 348#define HDA_QUIRK_GPIO4 (1 << 4) 349#define HDA_QUIRK_GPIO5 (1 << 5) 350#define HDA_QUIRK_GPIO6 (1 << 6) 351#define HDA_QUIRK_GPIO7 (1 << 7) 352#define HDA_QUIRK_GPIOFLUSH (1 << 8) 353 354/* 9 - 25 = anything else */ 355#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 356#define HDA_QUIRK_FIXEDRATE (1 << 10) 357#define HDA_QUIRK_FORCESTEREO (1 << 11) 358#define HDA_QUIRK_EAPDINV (1 << 12) 359#define HDA_QUIRK_DMAPOS (1 << 13) 360#define HDA_QUIRK_SENSEINV (1 << 14) 361 362/* 26 - 31 = vrefs */ 363#define HDA_QUIRK_IVREF50 (1 << 26) 364#define HDA_QUIRK_IVREF80 (1 << 27) 365#define HDA_QUIRK_IVREF100 (1 << 28) 366#define HDA_QUIRK_OVREF50 (1 << 29) 367#define HDA_QUIRK_OVREF80 (1 << 30) 368#define HDA_QUIRK_OVREF100 (1 << 31) 369 370#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 371 HDA_QUIRK_IVREF100) 372#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 373 HDA_QUIRK_OVREF100) 374#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 375 376#if __FreeBSD_version < 600000 377#define taskqueue_drain(...) 378#endif 379 380static const struct { 381 char *key; 382 uint32_t value; 383} hdac_quirks_tab[] = { 384 { "gpio0", HDA_QUIRK_GPIO0 }, 385 { "gpio1", HDA_QUIRK_GPIO1 }, 386 { "gpio2", HDA_QUIRK_GPIO2 }, 387 { "gpio3", HDA_QUIRK_GPIO3 }, 388 { "gpio4", HDA_QUIRK_GPIO4 }, 389 { "gpio5", HDA_QUIRK_GPIO5 }, 390 { "gpio6", HDA_QUIRK_GPIO6 }, 391 { "gpio7", HDA_QUIRK_GPIO7 }, 392 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 393 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 394 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 395 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 396 { "eapdinv", HDA_QUIRK_EAPDINV }, 397 { "dmapos", HDA_QUIRK_DMAPOS }, 398 { "senseinv", HDA_QUIRK_SENSEINV }, 399 { "ivref50", HDA_QUIRK_IVREF50 }, 400 { "ivref80", HDA_QUIRK_IVREF80 }, 401 { "ivref100", HDA_QUIRK_IVREF100 }, 402 { "ovref50", HDA_QUIRK_OVREF50 }, 403 { "ovref80", HDA_QUIRK_OVREF80 }, 404 { "ovref100", HDA_QUIRK_OVREF100 }, 405 { "ivref", HDA_QUIRK_IVREF }, 406 { "ovref", HDA_QUIRK_OVREF }, 407 { "vref", HDA_QUIRK_VREF }, 408}; 409#define HDAC_QUIRKS_TAB_LEN \ 410 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 411 412#define HDA_BDL_MIN 2 413#define HDA_BDL_MAX 256 414#define HDA_BDL_DEFAULT HDA_BDL_MIN 415 416#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 417#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 418 419#define HDA_BUFSZ_MIN 4096 420#define HDA_BUFSZ_MAX 65536 421#define HDA_BUFSZ_DEFAULT 16384 422 423#define HDA_PARSE_MAXDEPTH 10 424 425#define HDAC_UNSOLTAG_EVENT_HP 0x00 426 427MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 428 429const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 430 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 431 "White", "Other"}; 432 433const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 434 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 435 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 436 437const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 438 439/* Default */ 440static uint32_t hdac_fmt[] = { 441 AFMT_STEREO | AFMT_S16_LE, 442 0 443}; 444 445static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 446 447static const struct { 448 uint32_t model; 449 char *desc; 450} hdac_devices[] = { 451 { HDA_INTEL_82801F, "Intel 82801F" }, 452 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 453 { HDA_INTEL_82801G, "Intel 82801G" }, 454 { HDA_INTEL_82801H, "Intel 82801H" }, 455 { HDA_INTEL_82801I, "Intel 82801I" }, 456 { HDA_INTEL_82801J, "Intel 82801J" }, 457 { HDA_INTEL_SCH, "Intel SCH" }, 458 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 459 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 460 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 461 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 462 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 463 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 464 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 465 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 466 { HDA_ATI_SB450, "ATI SB450" }, 467 { HDA_ATI_SB600, "ATI SB600" }, 468 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 469 { HDA_SIS_966, "SiS 966" }, 470 /* Unknown */ 471 { HDA_INTEL_ALL, "Intel (Unknown)" }, 472 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 473 { HDA_ATI_ALL, "ATI (Unknown)" }, 474 { HDA_VIA_ALL, "VIA (Unknown)" }, 475 { HDA_SIS_ALL, "SiS (Unknown)" }, 476}; 477#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 478 479static const struct { 480 uint16_t vendor; 481 uint8_t reg; 482 uint8_t mask; 483 uint8_t enable; 484} hdac_pcie_snoop[] = { 485 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 486 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 487 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 488}; 489#define HDAC_PCIESNOOP_LEN \ 490 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 491 492static const struct { 493 uint32_t rate; 494 int valid; 495 uint16_t base; 496 uint16_t mul; 497 uint16_t div; 498} hda_rate_tab[] = { 499 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 500 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 501 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 502 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 503 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 504 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 505 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 506 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 507 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 508 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 509 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 510 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 511 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 512 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 513 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 514 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 515 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 516 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 517 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 518 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 519 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 520 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 521 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 522 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 523 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 524 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 525 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 526 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 527 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 528 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 529 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 530 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 531 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 532 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 533 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 534}; 535#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 536 537/* All codecs you can eat... */ 538#define HDA_CODEC_CONSTRUCT(vendor, id) \ 539 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 540 541/* Realtek */ 542#define REALTEK_VENDORID 0x10ec 543#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 544#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 545#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 546#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 547#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 548#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 549#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 550#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 551#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 552#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 553#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 554#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 555#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 556#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 557#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 558#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 559#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 560#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 561 562/* Analog Devices */ 563#define ANALOGDEVICES_VENDORID 0x11d4 564#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 565#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 566#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 567#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 568#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 569#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 570#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 571 572/* CMedia */ 573#define CMEDIA_VENDORID 0x434d 574#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 575#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 576 577/* Sigmatel */ 578#define SIGMATEL_VENDORID 0x8384 579#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 580#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 581#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 582#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 583#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 584#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 585#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 586#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 587#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 588#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 589#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 590#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 591#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 592#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 593#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 594#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 595#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 596#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 597#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 598#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 599#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 600#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 601#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 602#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 603#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 604#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 605#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 606#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 607#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 608#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 609#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 610#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 611#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 612#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 613#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 614#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 615#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 616#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 617#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 618#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 619 620/* IDT */ 621#define IDT_VENDORID 0x111d 622#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 623#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 624#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 625#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 626#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 627#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 628#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 629#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 630#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 631#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 632#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 633#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 634#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 635 636/* Silicon Image */ 637#define SII_VENDORID 0x1095 638#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 639 640/* Lucent/Agere */ 641#define AGERE_VENDORID 0x11c1 642#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 643 644/* 645 * Conexant 646 * 647 * Ok, the truth is, I don't have any idea at all whether 648 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 649 * place that tell me it is "Venice" is from its Windows driver INF. 650 * 651 * Venice - CX????? 652 * Waikiki - CX20551-22 653 */ 654#define CONEXANT_VENDORID 0x14f1 655#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 656#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 657#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 658 659/* VIA */ 660#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 661#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 662#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 663#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 664#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 665#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 666#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 667#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 668#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 669#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 670#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 671#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 672#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 673 674/* ATI */ 675#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 676 677/* NVIDIA */ 678#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 679 680/* INTEL */ 681#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 682 683/* Codecs */ 684static const struct { 685 uint32_t id; 686 char *name; 687} hdac_codecs[] = { 688 { HDA_CODEC_ALC260, "Realtek ALC260" }, 689 { HDA_CODEC_ALC262, "Realtek ALC262" }, 690 { HDA_CODEC_ALC267, "Realtek ALC267" }, 691 { HDA_CODEC_ALC268, "Realtek ALC268" }, 692 { HDA_CODEC_ALC269, "Realtek ALC269" }, 693 { HDA_CODEC_ALC272, "Realtek ALC272" }, 694 { HDA_CODEC_ALC660, "Realtek ALC660" }, 695 { HDA_CODEC_ALC662, "Realtek ALC662" }, 696 { HDA_CODEC_ALC663, "Realtek ALC663" }, 697 { HDA_CODEC_ALC861, "Realtek ALC861" }, 698 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 699 { HDA_CODEC_ALC880, "Realtek ALC880" }, 700 { HDA_CODEC_ALC882, "Realtek ALC882" }, 701 { HDA_CODEC_ALC883, "Realtek ALC883" }, 702 { HDA_CODEC_ALC885, "Realtek ALC885" }, 703 { HDA_CODEC_ALC888, "Realtek ALC888" }, 704 { HDA_CODEC_ALC889, "Realtek ALC889" }, 705 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 706 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 707 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 708 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 709 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 710 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 711 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 712 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 713 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 714 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 715 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 716 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 717 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 718 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 719 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 720 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 721 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 722 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 723 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 724 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 725 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 726 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 727 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 728 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 729 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 730 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 731 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 732 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 733 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 734 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 735 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 736 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 737 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 738 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 739 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 740 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 741 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 742 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 743 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 744 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 745 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 746 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 747 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 748 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 749 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 750 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 751 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 752 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 753 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 754 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 755 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 756 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 757 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 758 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 759 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 760 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 761 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 762 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 763 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 764 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 765 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 766 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 767 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 768 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 769 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 770 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 771 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 772 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 773 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 774 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 775 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 776 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 777 /* Unknown codec */ 778 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 779 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 780 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 781 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 782 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 783 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 784 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 785 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 786 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 787 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 788 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 789 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 790}; 791#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 792 793 794/**************************************************************************** 795 * Function prototypes 796 ****************************************************************************/ 797static void hdac_intr_handler(void *); 798static int hdac_reset(struct hdac_softc *, int); 799static int hdac_get_capabilities(struct hdac_softc *); 800static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 801static int hdac_dma_alloc(struct hdac_softc *, 802 struct hdac_dma *, bus_size_t); 803static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 804static int hdac_mem_alloc(struct hdac_softc *); 805static void hdac_mem_free(struct hdac_softc *); 806static int hdac_irq_alloc(struct hdac_softc *); 807static void hdac_irq_free(struct hdac_softc *); 808static void hdac_corb_init(struct hdac_softc *); 809static void hdac_rirb_init(struct hdac_softc *); 810static void hdac_corb_start(struct hdac_softc *); 811static void hdac_rirb_start(struct hdac_softc *); 812static void hdac_scan_codecs(struct hdac_softc *); 813static void hdac_probe_codec(struct hdac_codec *); 814static void hdac_probe_function(struct hdac_codec *, nid_t); 815static int hdac_pcmchannel_setup(struct hdac_chan *); 816 817static void hdac_attach2(void *); 818 819static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 820 uint32_t, int); 821static void hdac_command_send_internal(struct hdac_softc *, 822 struct hdac_command_list *, int); 823 824static int hdac_probe(device_t); 825static int hdac_attach(device_t); 826static int hdac_detach(device_t); 827static int hdac_suspend(device_t); 828static int hdac_resume(device_t); 829static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 830static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 831 uint32_t, int, int); 832static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 833 nid_t, int, int, int); 834static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 835 nid_t, nid_t, int, int, int, int, int, int); 836static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 837 838static int hdac_rirb_flush(struct hdac_softc *sc); 839static int hdac_unsolq_flush(struct hdac_softc *sc); 840 841static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 842 843#define hdac_command(a1, a2, a3) \ 844 hdac_command_sendone_internal(a1, a2, a3) 845 846#define hdac_codec_id(c) \ 847 ((uint32_t)((c == NULL) ? 0x00000000 : \ 848 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 849 ((uint32_t)(c)->device_id & 0x0000ffff)))) 850 851static char * 852hdac_codec_name(struct hdac_codec *codec) 853{ 854 uint32_t id; 855 int i; 856 857 id = hdac_codec_id(codec); 858 859 for (i = 0; i < HDAC_CODECS_LEN; i++) { 860 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 861 return (hdac_codecs[i].name); 862 } 863 864 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 865} 866 867static char * 868hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 869{ 870 static char *ossname[] = SOUND_DEVICE_NAMES; 871 int i, first = 1; 872 873 bzero(buf, len); 874 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 875 if (mask & (1 << i)) { 876 if (first == 0) 877 strlcat(buf, ", ", len); 878 strlcat(buf, ossname[i], len); 879 first = 0; 880 } 881 } 882 return (buf); 883} 884 885static struct hdac_audio_ctl * 886hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 887{ 888 if (devinfo == NULL || 889 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 890 index == NULL || devinfo->function.audio.ctl == NULL || 891 devinfo->function.audio.ctlcnt < 1 || 892 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 893 return (NULL); 894 return (&devinfo->function.audio.ctl[(*index)++]); 895} 896 897static struct hdac_audio_ctl * 898hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 899 int index, int cnt) 900{ 901 struct hdac_audio_ctl *ctl; 902 int i, found = 0; 903 904 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 905 return (NULL); 906 907 i = 0; 908 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 909 if (ctl->enable == 0) 910 continue; 911 if (ctl->widget->nid != nid) 912 continue; 913 if (dir && ctl->ndir != dir) 914 continue; 915 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 916 ctl->dir == ctl->ndir && ctl->index != index) 917 continue; 918 found++; 919 if (found == cnt || cnt <= 0) 920 return (ctl); 921 } 922 923 return (NULL); 924} 925 926/* 927 * Jack detection (Speaker/HP redirection) event handler. 928 */ 929static void 930hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 931{ 932 struct hdac_audio_as *as; 933 struct hdac_softc *sc; 934 struct hdac_widget *w; 935 struct hdac_audio_ctl *ctl; 936 uint32_t val, res; 937 int i, j; 938 nid_t cad; 939 940 if (devinfo == NULL || devinfo->codec == NULL || 941 devinfo->codec->sc == NULL) 942 return; 943 944 sc = devinfo->codec->sc; 945 cad = devinfo->codec->cad; 946 as = devinfo->function.audio.as; 947 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 948 if (as[i].hpredir < 0) 949 continue; 950 951 w = hdac_widget_get(devinfo, as[i].pins[15]); 952 if (w == NULL || w->enable == 0 || w->type != 953 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 954 continue; 955 956 res = hdac_command(sc, 957 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 958 959 HDA_BOOTVERBOSE( 960 device_printf(sc->dev, 961 "Pin sense: nid=%d res=0x%08x\n", 962 as[i].pins[15], res); 963 ); 964 965 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 966 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 967 res ^= 1; 968 969 /* (Un)Mute headphone pin. */ 970 ctl = hdac_audio_ctl_amp_get(devinfo, 971 as[i].pins[15], HDA_CTL_IN, -1, 1); 972 if (ctl != NULL && ctl->mute) { 973 /* If pin has muter - use it. */ 974 val = (res != 0) ? 0 : 1; 975 if (val != ctl->forcemute) { 976 ctl->forcemute = val; 977 hdac_audio_ctl_amp_set(ctl, 978 HDA_AMP_MUTE_DEFAULT, 979 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 980 } 981 } else { 982 /* If there is no muter - disable pin output. */ 983 w = hdac_widget_get(devinfo, as[i].pins[15]); 984 if (w != NULL && w->type == 985 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 986 if (res != 0) 987 val = w->wclass.pin.ctrl | 988 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 989 else 990 val = w->wclass.pin.ctrl & 991 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 992 if (val != w->wclass.pin.ctrl) { 993 w->wclass.pin.ctrl = val; 994 hdac_command(sc, 995 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 996 w->nid, w->wclass.pin.ctrl), cad); 997 } 998 } 999 } 1000 /* (Un)Mute other pins. */ 1001 for (j = 0; j < 15; j++) { 1002 if (as[i].pins[j] <= 0) 1003 continue; 1004 ctl = hdac_audio_ctl_amp_get(devinfo, 1005 as[i].pins[j], HDA_CTL_IN, -1, 1); 1006 if (ctl != NULL && ctl->mute) { 1007 /* If pin has muter - use it. */ 1008 val = (res != 0) ? 1 : 0; 1009 if (val == ctl->forcemute) 1010 continue; 1011 ctl->forcemute = val; 1012 hdac_audio_ctl_amp_set(ctl, 1013 HDA_AMP_MUTE_DEFAULT, 1014 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1015 continue; 1016 } 1017 /* If there is no muter - disable pin output. */ 1018 w = hdac_widget_get(devinfo, as[i].pins[j]); 1019 if (w != NULL && w->type == 1020 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1021 if (res != 0) 1022 val = w->wclass.pin.ctrl & 1023 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1024 else 1025 val = w->wclass.pin.ctrl | 1026 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1027 if (val != w->wclass.pin.ctrl) { 1028 w->wclass.pin.ctrl = val; 1029 hdac_command(sc, 1030 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1031 w->nid, w->wclass.pin.ctrl), cad); 1032 } 1033 } 1034 } 1035 } 1036} 1037 1038/* 1039 * Callback for poll based jack detection. 1040 */ 1041static void 1042hdac_jack_poll_callback(void *arg) 1043{ 1044 struct hdac_devinfo *devinfo = arg; 1045 struct hdac_softc *sc; 1046 1047 if (devinfo == NULL || devinfo->codec == NULL || 1048 devinfo->codec->sc == NULL) 1049 return; 1050 sc = devinfo->codec->sc; 1051 hdac_lock(sc); 1052 if (sc->poll_ival == 0) { 1053 hdac_unlock(sc); 1054 return; 1055 } 1056 hdac_hp_switch_handler(devinfo); 1057 callout_reset(&sc->poll_jack, sc->poll_ival, 1058 hdac_jack_poll_callback, devinfo); 1059 hdac_unlock(sc); 1060} 1061 1062/* 1063 * Jack detection initializer. 1064 */ 1065static void 1066hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1067{ 1068 struct hdac_softc *sc = devinfo->codec->sc; 1069 struct hdac_audio_as *as = devinfo->function.audio.as; 1070 struct hdac_widget *w; 1071 uint32_t id; 1072 int i, enable = 0, poll = 0; 1073 nid_t cad; 1074 1075 id = hdac_codec_id(devinfo->codec); 1076 cad = devinfo->codec->cad; 1077 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1078 if (as[i].hpredir < 0) 1079 continue; 1080 1081 w = hdac_widget_get(devinfo, as[i].pins[15]); 1082 if (w == NULL || w->enable == 0 || w->type != 1083 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1084 continue; 1085 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1086 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1087 device_printf(sc->dev, 1088 "No jack detection support at pin %d\n", 1089 as[i].pins[15]); 1090 continue; 1091 } 1092 enable = 1; 1093 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1094 hdac_command(sc, 1095 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1096 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1097 HDAC_UNSOLTAG_EVENT_HP), cad); 1098 } else 1099 poll = 1; 1100 HDA_BOOTVERBOSE( 1101 device_printf(sc->dev, 1102 "Enabling headphone/speaker " 1103 "audio routing switching:\n"); 1104 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1105 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1106 ); 1107 } 1108 if (enable) { 1109 hdac_hp_switch_handler(devinfo); 1110 if (poll) { 1111 callout_reset(&sc->poll_jack, 1, 1112 hdac_jack_poll_callback, devinfo); 1113 } 1114 } 1115} 1116 1117/* 1118 * Unsolicited messages handler. 1119 */ 1120static void 1121hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1122{ 1123 struct hdac_softc *sc; 1124 struct hdac_devinfo *devinfo = NULL; 1125 int i; 1126 1127 if (codec == NULL || codec->sc == NULL) 1128 return; 1129 1130 sc = codec->sc; 1131 1132 HDA_BOOTVERBOSE( 1133 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1134 ); 1135 1136 for (i = 0; i < codec->num_fgs; i++) { 1137 if (codec->fgs[i].node_type == 1138 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1139 devinfo = &codec->fgs[i]; 1140 break; 1141 } 1142 } 1143 1144 if (devinfo == NULL) 1145 return; 1146 1147 switch (tag) { 1148 case HDAC_UNSOLTAG_EVENT_HP: 1149 hdac_hp_switch_handler(devinfo); 1150 break; 1151 default: 1152 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1153 break; 1154 } 1155} 1156 1157static int 1158hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1159{ 1160 /* XXX to be removed */ 1161#ifdef HDAC_INTR_EXTRA 1162 uint32_t res; 1163#endif 1164 1165 if (!(ch->flags & HDAC_CHN_RUNNING)) 1166 return (0); 1167 1168 /* XXX to be removed */ 1169#ifdef HDAC_INTR_EXTRA 1170 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1171#endif 1172 1173 /* XXX to be removed */ 1174#ifdef HDAC_INTR_EXTRA 1175 HDA_BOOTVERBOSE( 1176 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1177 device_printf(ch->pdevinfo->dev, 1178 "PCMDIR_%s intr triggered beyond stream boundary:" 1179 "%08x\n", 1180 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1181 ); 1182#endif 1183 1184 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1185 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1186 1187 /* XXX to be removed */ 1188#ifdef HDAC_INTR_EXTRA 1189 if (res & HDAC_SDSTS_BCIS) { 1190#endif 1191 return (1); 1192 /* XXX to be removed */ 1193#ifdef HDAC_INTR_EXTRA 1194 } 1195#endif 1196 1197 return (0); 1198} 1199 1200/**************************************************************************** 1201 * void hdac_intr_handler(void *) 1202 * 1203 * Interrupt handler. Processes interrupts received from the hdac. 1204 ****************************************************************************/ 1205static void 1206hdac_intr_handler(void *context) 1207{ 1208 struct hdac_softc *sc; 1209 uint32_t intsts; 1210 uint8_t rirbsts; 1211 struct hdac_rirb *rirb_base; 1212 uint32_t trigger; 1213 int i; 1214 1215 sc = (struct hdac_softc *)context; 1216 1217 hdac_lock(sc); 1218 if (sc->polling != 0) { 1219 hdac_unlock(sc); 1220 return; 1221 } 1222 1223 /* Do we have anything to do? */ 1224 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1225 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1226 hdac_unlock(sc); 1227 return; 1228 } 1229 1230 trigger = 0; 1231 1232 /* Was this a controller interrupt? */ 1233 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1234 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1235 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1236 /* Get as many responses that we can */ 1237 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1238 HDAC_WRITE_1(&sc->mem, 1239 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1240 if (hdac_rirb_flush(sc) != 0) 1241 trigger |= HDAC_TRIGGER_UNSOL; 1242 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1243 } 1244 /* XXX to be removed */ 1245 /* Clear interrupt and exit */ 1246#ifdef HDAC_INTR_EXTRA 1247 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1248#endif 1249 } 1250 1251 if (intsts & HDAC_INTSTS_SIS_MASK) { 1252 for (i = 0; i < sc->num_chans; i++) { 1253 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1254 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1255 trigger |= (1 << i); 1256 } 1257 /* XXX to be removed */ 1258#ifdef HDAC_INTR_EXTRA 1259 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1260 HDAC_INTSTS_SIS_MASK); 1261#endif 1262 } 1263 1264 hdac_unlock(sc); 1265 1266 for (i = 0; i < sc->num_chans; i++) { 1267 if (trigger & (1 << i)) 1268 chn_intr(sc->chans[i].c); 1269 } 1270 if (trigger & HDAC_TRIGGER_UNSOL) 1271 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1272} 1273 1274/**************************************************************************** 1275 * int hdac_reset(hdac_softc *, int) 1276 * 1277 * Reset the hdac to a quiescent and known state. 1278 ****************************************************************************/ 1279static int 1280hdac_reset(struct hdac_softc *sc, int wakeup) 1281{ 1282 uint32_t gctl; 1283 int count, i; 1284 1285 /* 1286 * Stop all Streams DMA engine 1287 */ 1288 for (i = 0; i < sc->num_iss; i++) 1289 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1290 for (i = 0; i < sc->num_oss; i++) 1291 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1292 for (i = 0; i < sc->num_bss; i++) 1293 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1294 1295 /* 1296 * Stop Control DMA engines. 1297 */ 1298 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1299 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1300 1301 /* 1302 * Reset DMA position buffer. 1303 */ 1304 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1305 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1306 1307 /* 1308 * Reset the controller. The reset must remain asserted for 1309 * a minimum of 100us. 1310 */ 1311 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1312 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1313 count = 10000; 1314 do { 1315 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1316 if (!(gctl & HDAC_GCTL_CRST)) 1317 break; 1318 DELAY(10); 1319 } while (--count); 1320 if (gctl & HDAC_GCTL_CRST) { 1321 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1322 return (ENXIO); 1323 } 1324 1325 /* If wakeup is not requested - leave the controller in reset state. */ 1326 if (!wakeup) 1327 return (0); 1328 1329 DELAY(100); 1330 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1331 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1332 count = 10000; 1333 do { 1334 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1335 if (gctl & HDAC_GCTL_CRST) 1336 break; 1337 DELAY(10); 1338 } while (--count); 1339 if (!(gctl & HDAC_GCTL_CRST)) { 1340 device_printf(sc->dev, "Device stuck in reset\n"); 1341 return (ENXIO); 1342 } 1343 1344 /* 1345 * Wait for codecs to finish their own reset sequence. The delay here 1346 * should be of 250us but for some reasons, on it's not enough on my 1347 * computer. Let's use twice as much as necessary to make sure that 1348 * it's reset properly. 1349 */ 1350 DELAY(1000); 1351 1352 return (0); 1353} 1354 1355 1356/**************************************************************************** 1357 * int hdac_get_capabilities(struct hdac_softc *); 1358 * 1359 * Retreive the general capabilities of the hdac; 1360 * Number of Input Streams 1361 * Number of Output Streams 1362 * Number of bidirectional Streams 1363 * 64bit ready 1364 * CORB and RIRB sizes 1365 ****************************************************************************/ 1366static int 1367hdac_get_capabilities(struct hdac_softc *sc) 1368{ 1369 uint16_t gcap; 1370 uint8_t corbsize, rirbsize; 1371 1372 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1373 sc->num_iss = HDAC_GCAP_ISS(gcap); 1374 sc->num_oss = HDAC_GCAP_OSS(gcap); 1375 sc->num_bss = HDAC_GCAP_BSS(gcap); 1376 1377 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1378 1379 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1380 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1381 HDAC_CORBSIZE_CORBSZCAP_256) 1382 sc->corb_size = 256; 1383 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1384 HDAC_CORBSIZE_CORBSZCAP_16) 1385 sc->corb_size = 16; 1386 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1387 HDAC_CORBSIZE_CORBSZCAP_2) 1388 sc->corb_size = 2; 1389 else { 1390 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1391 __func__, corbsize); 1392 return (ENXIO); 1393 } 1394 1395 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1396 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1397 HDAC_RIRBSIZE_RIRBSZCAP_256) 1398 sc->rirb_size = 256; 1399 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1400 HDAC_RIRBSIZE_RIRBSZCAP_16) 1401 sc->rirb_size = 16; 1402 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1403 HDAC_RIRBSIZE_RIRBSZCAP_2) 1404 sc->rirb_size = 2; 1405 else { 1406 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1407 __func__, rirbsize); 1408 return (ENXIO); 1409 } 1410 1411 HDA_BOOTHVERBOSE( 1412 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1413 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1414 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1415 sc->num_iss, sc->num_oss, sc->num_bss); 1416 ); 1417 1418 return (0); 1419} 1420 1421 1422/**************************************************************************** 1423 * void hdac_dma_cb 1424 * 1425 * This function is called by bus_dmamap_load when the mapping has been 1426 * established. We just record the physical address of the mapping into 1427 * the struct hdac_dma passed in. 1428 ****************************************************************************/ 1429static void 1430hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1431{ 1432 struct hdac_dma *dma; 1433 1434 if (error == 0) { 1435 dma = (struct hdac_dma *)callback_arg; 1436 dma->dma_paddr = segs[0].ds_addr; 1437 } 1438} 1439 1440 1441/**************************************************************************** 1442 * int hdac_dma_alloc 1443 * 1444 * This function allocate and setup a dma region (struct hdac_dma). 1445 * It must be freed by a corresponding hdac_dma_free. 1446 ****************************************************************************/ 1447static int 1448hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1449{ 1450 bus_size_t roundsz; 1451 int result; 1452 int lowaddr; 1453 1454 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1455 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1456 BUS_SPACE_MAXADDR_32BIT; 1457 bzero(dma, sizeof(*dma)); 1458 1459 /* 1460 * Create a DMA tag 1461 */ 1462 result = bus_dma_tag_create(NULL, /* parent */ 1463 HDAC_DMA_ALIGNMENT, /* alignment */ 1464 0, /* boundary */ 1465 lowaddr, /* lowaddr */ 1466 BUS_SPACE_MAXADDR, /* highaddr */ 1467 NULL, /* filtfunc */ 1468 NULL, /* fistfuncarg */ 1469 roundsz, /* maxsize */ 1470 1, /* nsegments */ 1471 roundsz, /* maxsegsz */ 1472 0, /* flags */ 1473 NULL, /* lockfunc */ 1474 NULL, /* lockfuncarg */ 1475 &dma->dma_tag); /* dmat */ 1476 if (result != 0) { 1477 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1478 __func__, result); 1479 goto hdac_dma_alloc_fail; 1480 } 1481 1482 /* 1483 * Allocate DMA memory 1484 */ 1485 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1486 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1487 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1488 &dma->dma_map); 1489 if (result != 0) { 1490 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1491 __func__, result); 1492 goto hdac_dma_alloc_fail; 1493 } 1494 1495 dma->dma_size = roundsz; 1496 1497 /* 1498 * Map the memory 1499 */ 1500 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1501 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1502 if (result != 0 || dma->dma_paddr == 0) { 1503 if (result == 0) 1504 result = ENOMEM; 1505 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1506 __func__, result); 1507 goto hdac_dma_alloc_fail; 1508 } 1509 1510 HDA_BOOTHVERBOSE( 1511 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1512 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1513 ); 1514 1515 return (0); 1516 1517hdac_dma_alloc_fail: 1518 hdac_dma_free(sc, dma); 1519 1520 return (result); 1521} 1522 1523 1524/**************************************************************************** 1525 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1526 * 1527 * Free a struct dhac_dma that has been previously allocated via the 1528 * hdac_dma_alloc function. 1529 ****************************************************************************/ 1530static void 1531hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1532{ 1533 if (dma->dma_map != NULL) { 1534#if 0 1535 /* Flush caches */ 1536 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1537 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1538#endif 1539 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1540 } 1541 if (dma->dma_vaddr != NULL) { 1542 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1543 dma->dma_vaddr = NULL; 1544 } 1545 dma->dma_map = NULL; 1546 if (dma->dma_tag != NULL) { 1547 bus_dma_tag_destroy(dma->dma_tag); 1548 dma->dma_tag = NULL; 1549 } 1550 dma->dma_size = 0; 1551} 1552 1553/**************************************************************************** 1554 * int hdac_mem_alloc(struct hdac_softc *) 1555 * 1556 * Allocate all the bus resources necessary to speak with the physical 1557 * controller. 1558 ****************************************************************************/ 1559static int 1560hdac_mem_alloc(struct hdac_softc *sc) 1561{ 1562 struct hdac_mem *mem; 1563 1564 mem = &sc->mem; 1565 mem->mem_rid = PCIR_BAR(0); 1566 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1567 &mem->mem_rid, RF_ACTIVE); 1568 if (mem->mem_res == NULL) { 1569 device_printf(sc->dev, 1570 "%s: Unable to allocate memory resource\n", __func__); 1571 return (ENOMEM); 1572 } 1573 mem->mem_tag = rman_get_bustag(mem->mem_res); 1574 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1575 1576 return (0); 1577} 1578 1579/**************************************************************************** 1580 * void hdac_mem_free(struct hdac_softc *) 1581 * 1582 * Free up resources previously allocated by hdac_mem_alloc. 1583 ****************************************************************************/ 1584static void 1585hdac_mem_free(struct hdac_softc *sc) 1586{ 1587 struct hdac_mem *mem; 1588 1589 mem = &sc->mem; 1590 if (mem->mem_res != NULL) 1591 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1592 mem->mem_res); 1593 mem->mem_res = NULL; 1594} 1595 1596/**************************************************************************** 1597 * int hdac_irq_alloc(struct hdac_softc *) 1598 * 1599 * Allocate and setup the resources necessary for interrupt handling. 1600 ****************************************************************************/ 1601static int 1602hdac_irq_alloc(struct hdac_softc *sc) 1603{ 1604 struct hdac_irq *irq; 1605 int result; 1606 1607 irq = &sc->irq; 1608 irq->irq_rid = 0x0; 1609 1610#ifdef HDAC_MSI_ENABLED 1611 if ((sc->flags & HDAC_F_MSI) && 1612 (result = pci_msi_count(sc->dev)) == 1 && 1613 pci_alloc_msi(sc->dev, &result) == 0) 1614 irq->irq_rid = 0x1; 1615 else 1616#endif 1617 sc->flags &= ~HDAC_F_MSI; 1618 1619 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1620 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1621 if (irq->irq_res == NULL) { 1622 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1623 __func__); 1624 goto hdac_irq_alloc_fail; 1625 } 1626 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1627 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1628 if (result != 0) { 1629 device_printf(sc->dev, 1630 "%s: Unable to setup interrupt handler (%x)\n", 1631 __func__, result); 1632 goto hdac_irq_alloc_fail; 1633 } 1634 1635 return (0); 1636 1637hdac_irq_alloc_fail: 1638 hdac_irq_free(sc); 1639 1640 return (ENXIO); 1641} 1642 1643/**************************************************************************** 1644 * void hdac_irq_free(struct hdac_softc *) 1645 * 1646 * Free up resources previously allocated by hdac_irq_alloc. 1647 ****************************************************************************/ 1648static void 1649hdac_irq_free(struct hdac_softc *sc) 1650{ 1651 struct hdac_irq *irq; 1652 1653 irq = &sc->irq; 1654 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1655 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1656 if (irq->irq_res != NULL) 1657 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1658 irq->irq_res); 1659#ifdef HDAC_MSI_ENABLED 1660 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1661 pci_release_msi(sc->dev); 1662#endif 1663 irq->irq_handle = NULL; 1664 irq->irq_res = NULL; 1665 irq->irq_rid = 0x0; 1666} 1667 1668/**************************************************************************** 1669 * void hdac_corb_init(struct hdac_softc *) 1670 * 1671 * Initialize the corb registers for operations but do not start it up yet. 1672 * The CORB engine must not be running when this function is called. 1673 ****************************************************************************/ 1674static void 1675hdac_corb_init(struct hdac_softc *sc) 1676{ 1677 uint8_t corbsize; 1678 uint64_t corbpaddr; 1679 1680 /* Setup the CORB size. */ 1681 switch (sc->corb_size) { 1682 case 256: 1683 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1684 break; 1685 case 16: 1686 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1687 break; 1688 case 2: 1689 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1690 break; 1691 default: 1692 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1693 } 1694 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1695 1696 /* Setup the CORB Address in the hdac */ 1697 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1698 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1699 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1700 1701 /* Set the WP and RP */ 1702 sc->corb_wp = 0; 1703 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1704 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1705 /* 1706 * The HDA specification indicates that the CORBRPRST bit will always 1707 * read as zero. Unfortunately, it seems that at least the 82801G 1708 * doesn't reset the bit to zero, which stalls the corb engine. 1709 * manually reset the bit to zero before continuing. 1710 */ 1711 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1712 1713 /* Enable CORB error reporting */ 1714#if 0 1715 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1716#endif 1717} 1718 1719/**************************************************************************** 1720 * void hdac_rirb_init(struct hdac_softc *) 1721 * 1722 * Initialize the rirb registers for operations but do not start it up yet. 1723 * The RIRB engine must not be running when this function is called. 1724 ****************************************************************************/ 1725static void 1726hdac_rirb_init(struct hdac_softc *sc) 1727{ 1728 uint8_t rirbsize; 1729 uint64_t rirbpaddr; 1730 1731 /* Setup the RIRB size. */ 1732 switch (sc->rirb_size) { 1733 case 256: 1734 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1735 break; 1736 case 16: 1737 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1738 break; 1739 case 2: 1740 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1741 break; 1742 default: 1743 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1744 } 1745 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1746 1747 /* Setup the RIRB Address in the hdac */ 1748 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1749 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1750 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1751 1752 /* Setup the WP and RP */ 1753 sc->rirb_rp = 0; 1754 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1755 1756 /* Setup the interrupt threshold */ 1757 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1758 1759 /* Enable Overrun and response received reporting */ 1760#if 0 1761 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1762 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1763#else 1764 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1765#endif 1766 1767#if 0 1768 /* 1769 * Make sure that the Host CPU cache doesn't contain any dirty 1770 * cache lines that falls in the rirb. If I understood correctly, it 1771 * should be sufficient to do this only once as the rirb is purely 1772 * read-only from now on. 1773 */ 1774 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1775 BUS_DMASYNC_PREREAD); 1776#endif 1777} 1778 1779/**************************************************************************** 1780 * void hdac_corb_start(hdac_softc *) 1781 * 1782 * Startup the corb DMA engine 1783 ****************************************************************************/ 1784static void 1785hdac_corb_start(struct hdac_softc *sc) 1786{ 1787 uint32_t corbctl; 1788 1789 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1790 corbctl |= HDAC_CORBCTL_CORBRUN; 1791 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1792} 1793 1794/**************************************************************************** 1795 * void hdac_rirb_start(hdac_softc *) 1796 * 1797 * Startup the rirb DMA engine 1798 ****************************************************************************/ 1799static void 1800hdac_rirb_start(struct hdac_softc *sc) 1801{ 1802 uint32_t rirbctl; 1803 1804 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1805 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1806 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1807} 1808 1809 1810/**************************************************************************** 1811 * void hdac_scan_codecs(struct hdac_softc *, int) 1812 * 1813 * Scan the bus for available codecs, starting with num. 1814 ****************************************************************************/ 1815static void 1816hdac_scan_codecs(struct hdac_softc *sc) 1817{ 1818 struct hdac_codec *codec; 1819 int i; 1820 uint16_t statests; 1821 1822 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1823 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1824 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1825 /* We have found a codec. */ 1826 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1827 M_HDAC, M_ZERO | M_NOWAIT); 1828 if (codec == NULL) { 1829 device_printf(sc->dev, 1830 "Unable to allocate memory for codec\n"); 1831 continue; 1832 } 1833 codec->commands = NULL; 1834 codec->responses_received = 0; 1835 codec->verbs_sent = 0; 1836 codec->sc = sc; 1837 codec->cad = i; 1838 sc->codecs[i] = codec; 1839 hdac_probe_codec(codec); 1840 } 1841 } 1842 /* All codecs have been probed, now try to attach drivers to them */ 1843 /* bus_generic_attach(sc->dev); */ 1844} 1845 1846/**************************************************************************** 1847 * void hdac_probe_codec(struct hdac_softc *, int) 1848 * 1849 * Probe a the given codec_id for available function groups. 1850 ****************************************************************************/ 1851static void 1852hdac_probe_codec(struct hdac_codec *codec) 1853{ 1854 struct hdac_softc *sc = codec->sc; 1855 uint32_t vendorid, revisionid, subnode; 1856 int startnode; 1857 int endnode; 1858 int i; 1859 nid_t cad = codec->cad; 1860 1861 HDA_BOOTVERBOSE( 1862 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1863 ); 1864 vendorid = hdac_command(sc, 1865 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1866 cad); 1867 revisionid = hdac_command(sc, 1868 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1869 cad); 1870 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1871 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1872 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1873 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1874 1875 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1876 device_printf(sc->dev, "Codec #%d is not responding!" 1877 " Probing aborted.\n", cad); 1878 return; 1879 } 1880 1881 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1882 cad, hdac_codec_name(codec)); 1883 HDA_BOOTVERBOSE( 1884 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1885 hdac_codec_id(codec)); 1886 device_printf(sc->dev, " Vendor: 0x%04x\n", 1887 codec->vendor_id); 1888 device_printf(sc->dev, " Device: 0x%04x\n", 1889 codec->device_id); 1890 device_printf(sc->dev, " Revision: 0x%02x\n", 1891 codec->revision_id); 1892 device_printf(sc->dev, " Stepping: 0x%02x\n", 1893 codec->stepping_id); 1894 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1895 sc->pci_subvendor); 1896 ); 1897 subnode = hdac_command(sc, 1898 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1899 cad); 1900 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1901 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1902 1903 HDA_BOOTHVERBOSE( 1904 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1905 startnode, endnode); 1906 ); 1907 1908 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1909 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1910 if (codec->fgs == NULL) { 1911 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1912 __func__); 1913 return; 1914 } 1915 1916 for (i = startnode; i < endnode; i++) 1917 hdac_probe_function(codec, i); 1918 return; 1919} 1920 1921/* 1922 * Probe codec function and add it to the list. 1923 */ 1924static void 1925hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1926{ 1927 struct hdac_softc *sc = codec->sc; 1928 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1929 uint32_t fctgrptype; 1930 uint32_t res; 1931 nid_t cad = codec->cad; 1932 1933 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1934 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1935 1936 devinfo->nid = nid; 1937 devinfo->node_type = fctgrptype; 1938 devinfo->codec = codec; 1939 1940 res = hdac_command(sc, 1941 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1942 1943 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1944 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1945 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1946 1947 HDA_BOOTVERBOSE( 1948 device_printf(sc->dev, 1949 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1950 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1951 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1952 "unknown", nid, devinfo->startnode, devinfo->endnode, 1953 devinfo->nodecnt); 1954 ); 1955 1956 if (devinfo->nodecnt > 0) 1957 devinfo->widget = (struct hdac_widget *)malloc( 1958 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1959 M_NOWAIT | M_ZERO); 1960 else 1961 devinfo->widget = NULL; 1962 1963 if (devinfo->widget == NULL) { 1964 device_printf(sc->dev, "unable to allocate widgets!\n"); 1965 devinfo->endnode = devinfo->startnode; 1966 devinfo->nodecnt = 0; 1967 return; 1968 } 1969 1970 codec->num_fgs++; 1971} 1972 1973static void 1974hdac_widget_connection_parse(struct hdac_widget *w) 1975{ 1976 struct hdac_softc *sc = w->devinfo->codec->sc; 1977 uint32_t res; 1978 int i, j, max, ents, entnum; 1979 nid_t cad = w->devinfo->codec->cad; 1980 nid_t nid = w->nid; 1981 nid_t cnid, addcnid, prevcnid; 1982 1983 w->nconns = 0; 1984 1985 res = hdac_command(sc, 1986 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1987 1988 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1989 1990 if (ents < 1) 1991 return; 1992 1993 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1994 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1995 prevcnid = 0; 1996 1997#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1998#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1999#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2000#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2001#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2002 2003 for (i = 0; i < ents; i += entnum) { 2004 res = hdac_command(sc, 2005 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2006 for (j = 0; j < entnum; j++) { 2007 cnid = CONN_CNID(res, entnum, j); 2008 if (cnid == 0) { 2009 if (w->nconns < ents) 2010 device_printf(sc->dev, 2011 "%s: nid=%d WARNING: zero cnid " 2012 "entnum=%d j=%d index=%d " 2013 "entries=%d found=%d res=0x%08x\n", 2014 __func__, nid, entnum, j, i, 2015 ents, w->nconns, res); 2016 else 2017 goto getconns_out; 2018 } 2019 if (cnid < w->devinfo->startnode || 2020 cnid >= w->devinfo->endnode) { 2021 HDA_BOOTVERBOSE( 2022 device_printf(sc->dev, 2023 "GHOST: nid=%d j=%d " 2024 "entnum=%d index=%d res=0x%08x\n", 2025 nid, j, entnum, i, res); 2026 ); 2027 } 2028 if (CONN_RANGE(res, entnum, j) == 0) 2029 addcnid = cnid; 2030 else if (prevcnid == 0 || prevcnid >= cnid) { 2031 device_printf(sc->dev, 2032 "%s: WARNING: Invalid child range " 2033 "nid=%d index=%d j=%d entnum=%d " 2034 "prevcnid=%d cnid=%d res=0x%08x\n", 2035 __func__, nid, i, j, entnum, prevcnid, 2036 cnid, res); 2037 addcnid = cnid; 2038 } else 2039 addcnid = prevcnid + 1; 2040 while (addcnid <= cnid) { 2041 if (w->nconns > max) { 2042 device_printf(sc->dev, 2043 "Adding %d (nid=%d): " 2044 "Max connection reached! max=%d\n", 2045 addcnid, nid, max + 1); 2046 goto getconns_out; 2047 } 2048 w->connsenable[w->nconns] = 1; 2049 w->conns[w->nconns++] = addcnid++; 2050 } 2051 prevcnid = cnid; 2052 } 2053 } 2054 2055getconns_out: 2056 return; 2057} 2058 2059static uint32_t 2060hdac_widget_pin_patch(uint32_t config, const char *str) 2061{ 2062 char buf[256]; 2063 char *key, *value, *rest, *bad; 2064 int ival, i; 2065 2066 strlcpy(buf, str, sizeof(buf)); 2067 rest = buf; 2068 while ((key = strsep(&rest, "=")) != NULL) { 2069 value = strsep(&rest, " \t"); 2070 if (value == NULL) 2071 break; 2072 ival = strtol(value, &bad, 10); 2073 if (strcmp(key, "seq") == 0) { 2074 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2075 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2076 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2077 } else if (strcmp(key, "as") == 0) { 2078 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2079 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2080 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2081 } else if (strcmp(key, "misc") == 0) { 2082 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2083 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2084 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2085 } else if (strcmp(key, "color") == 0) { 2086 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2087 if (bad[0] == 0) { 2088 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2089 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2090 }; 2091 for (i = 0; i < 16; i++) { 2092 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2093 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2094 break; 2095 } 2096 } 2097 } else if (strcmp(key, "ctype") == 0) { 2098 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2099 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2100 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2101 } else if (strcmp(key, "device") == 0) { 2102 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2103 if (bad[0] == 0) { 2104 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2105 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2106 continue; 2107 }; 2108 for (i = 0; i < 16; i++) { 2109 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2110 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2111 break; 2112 } 2113 } 2114 } else if (strcmp(key, "loc") == 0) { 2115 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2116 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2117 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2118 } else if (strcmp(key, "conn") == 0) { 2119 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2120 if (bad[0] == 0) { 2121 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2122 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2123 continue; 2124 }; 2125 for (i = 0; i < 4; i++) { 2126 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2127 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2128 break; 2129 } 2130 } 2131 } 2132 } 2133 return (config); 2134} 2135 2136static uint32_t 2137hdac_widget_pin_getconfig(struct hdac_widget *w) 2138{ 2139 struct hdac_softc *sc; 2140 uint32_t config, orig, id; 2141 nid_t cad, nid; 2142 char buf[32]; 2143 const char *res = NULL, *patch = NULL; 2144 2145 sc = w->devinfo->codec->sc; 2146 cad = w->devinfo->codec->cad; 2147 nid = w->nid; 2148 id = hdac_codec_id(w->devinfo->codec); 2149 2150 config = hdac_command(sc, 2151 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2152 cad); 2153 orig = config; 2154 2155 HDA_BOOTVERBOSE( 2156 hdac_dump_pin_config(w, orig); 2157 ); 2158 2159 /* XXX: Old patches require complete review. 2160 * Now they may create more problem then solve due to 2161 * incorrect associations. 2162 */ 2163 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2164 switch (nid) { 2165 case 26: 2166 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2167 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2168 break; 2169 case 27: 2170 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2171 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2172 break; 2173 default: 2174 break; 2175 } 2176 } else if (id == HDA_CODEC_ALC880 && 2177 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2178 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2179 /* 2180 * Super broken BIOS 2181 */ 2182 switch (nid) { 2183 case 24: /* MIC1 */ 2184 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2185 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2186 break; 2187 case 25: /* XXX MIC2 */ 2188 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2189 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2190 break; 2191 case 26: /* LINE1 */ 2192 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2193 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2194 break; 2195 case 27: /* XXX LINE2 */ 2196 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2197 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2198 break; 2199 case 28: /* CD */ 2200 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2201 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2202 break; 2203 } 2204 } else if (id == HDA_CODEC_ALC883 && 2205 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2206 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2207 switch (nid) { 2208 case 25: 2209 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2210 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2211 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2212 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2213 break; 2214 case 28: 2215 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2216 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2217 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2218 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2219 break; 2220 } 2221 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2222 HP_V3000_SUBVENDOR) { 2223 switch (nid) { 2224 case 18: 2225 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2226 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2227 break; 2228 case 20: 2229 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2230 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2231 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2232 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2233 break; 2234 case 21: 2235 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2236 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2237 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2238 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2239 break; 2240 } 2241 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2242 HP_DV5000_SUBVENDOR) { 2243 switch (nid) { 2244 case 20: 2245 case 21: 2246 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2247 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2248 break; 2249 } 2250 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2251 ASUS_W6F_SUBVENDOR) { 2252 switch (nid) { 2253 case 11: 2254 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2255 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2256 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2257 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2258 break; 2259 case 12: 2260 case 14: 2261 case 16: 2262 case 31: 2263 case 32: 2264 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2265 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2266 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2267 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2268 break; 2269 case 15: 2270 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2271 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2272 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2273 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2274 break; 2275 } 2276 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2277 UNIWILL_9075_SUBVENDOR) { 2278 switch (nid) { 2279 case 15: 2280 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2281 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2282 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2283 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2284 break; 2285 } 2286 } 2287 2288 /* New patches */ 2289 if (id == HDA_CODEC_AD1986A && 2290 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2291 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2292 switch (nid) { 2293 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2294 patch = "device=Line-in as=8 seq=1"; 2295 break; 2296 case 29: 2297 patch = "device=Mic as=8 seq=2"; 2298 break; 2299 case 31: /* Lot of inputs configured with as=15 and unusable */ 2300 patch = "as=8 seq=3"; 2301 break; 2302 case 32: 2303 patch = "as=8 seq=4"; 2304 break; 2305 case 34: 2306 patch = "as=8 seq=5"; 2307 break; 2308 case 36: 2309 patch = "as=8 seq=6"; 2310 break; 2311 } 2312 } else if (id == HDA_CODEC_ALC260 && 2313 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2314 switch (nid) { 2315 case 16: 2316 patch = "seq=15 device=Headphones"; 2317 break; 2318 } 2319 } else if (id == HDA_CODEC_ALC268 && 2320 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2321 switch (nid) { 2322 case 28: 2323 patch = "device=CD conn=fixed"; 2324 break; 2325 } 2326 } 2327 2328 if (patch != NULL) 2329 config = hdac_widget_pin_patch(config, patch); 2330 2331 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2332 if (resource_string_value(device_get_name(sc->dev), 2333 device_get_unit(sc->dev), buf, &res) == 0) { 2334 if (strncmp(res, "0x", 2) == 0) { 2335 config = strtol(res + 2, NULL, 16); 2336 } else { 2337 config = hdac_widget_pin_patch(config, res); 2338 } 2339 } 2340 2341 HDA_BOOTVERBOSE( 2342 if (config != orig) 2343 device_printf(sc->dev, 2344 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2345 nid, orig, config); 2346 ); 2347 2348 return (config); 2349} 2350 2351static uint32_t 2352hdac_widget_pin_getcaps(struct hdac_widget *w) 2353{ 2354 struct hdac_softc *sc; 2355 uint32_t caps, orig, id; 2356 nid_t cad, nid; 2357 2358 sc = w->devinfo->codec->sc; 2359 cad = w->devinfo->codec->cad; 2360 nid = w->nid; 2361 id = hdac_codec_id(w->devinfo->codec); 2362 2363 caps = hdac_command(sc, 2364 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2365 orig = caps; 2366 2367 HDA_BOOTVERBOSE( 2368 if (caps != orig) 2369 device_printf(sc->dev, 2370 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2371 nid, orig, caps); 2372 ); 2373 2374 return (caps); 2375} 2376 2377static void 2378hdac_widget_pin_parse(struct hdac_widget *w) 2379{ 2380 struct hdac_softc *sc = w->devinfo->codec->sc; 2381 uint32_t config, pincap; 2382 const char *devstr, *connstr; 2383 nid_t cad = w->devinfo->codec->cad; 2384 nid_t nid = w->nid; 2385 2386 config = hdac_widget_pin_getconfig(w); 2387 w->wclass.pin.config = config; 2388 2389 pincap = hdac_widget_pin_getcaps(w); 2390 w->wclass.pin.cap = pincap; 2391 2392 w->wclass.pin.ctrl = hdac_command(sc, 2393 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2394 2395 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2396 w->param.eapdbtl = hdac_command(sc, 2397 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2398 w->param.eapdbtl &= 0x7; 2399 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2400 } else 2401 w->param.eapdbtl = HDAC_INVALID; 2402 2403 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2404 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2405 2406 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2408 2409 strlcat(w->name, ": ", sizeof(w->name)); 2410 strlcat(w->name, devstr, sizeof(w->name)); 2411 strlcat(w->name, " (", sizeof(w->name)); 2412 strlcat(w->name, connstr, sizeof(w->name)); 2413 strlcat(w->name, ")", sizeof(w->name)); 2414} 2415 2416static uint32_t 2417hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2418{ 2419 struct hdac_softc *sc; 2420 uint32_t caps, orig, id; 2421 nid_t cad, nid, beeper = -1; 2422 2423 sc = w->devinfo->codec->sc; 2424 cad = w->devinfo->codec->cad; 2425 nid = w->nid; 2426 id = hdac_codec_id(w->devinfo->codec); 2427 2428 caps = hdac_command(sc, 2429 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2430 cad); 2431 orig = caps; 2432 2433 /* On some codecs beeper is an input pin, but it is not recordable 2434 alone. Also most of BIOSes does not declare beeper pin. 2435 Change beeper pin node type to beeper to help parser. */ 2436 *waspin = 0; 2437 switch (id) { 2438 case HDA_CODEC_AD1988: 2439 case HDA_CODEC_AD1988B: 2440 beeper = 26; 2441 break; 2442 case HDA_CODEC_ALC260: 2443 beeper = 23; 2444 break; 2445 case HDA_CODEC_ALC262: 2446 case HDA_CODEC_ALC268: 2447 case HDA_CODEC_ALC880: 2448 case HDA_CODEC_ALC882: 2449 case HDA_CODEC_ALC883: 2450 case HDA_CODEC_ALC885: 2451 case HDA_CODEC_ALC888: 2452 case HDA_CODEC_ALC889: 2453 beeper = 29; 2454 break; 2455 } 2456 if (nid == beeper) { 2457 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2458 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2459 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2460 *waspin = 1; 2461 } 2462 2463 HDA_BOOTVERBOSE( 2464 if (caps != orig) { 2465 device_printf(sc->dev, 2466 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2467 nid, orig, caps); 2468 } 2469 ); 2470 2471 return (caps); 2472} 2473 2474static void 2475hdac_widget_parse(struct hdac_widget *w) 2476{ 2477 struct hdac_softc *sc = w->devinfo->codec->sc; 2478 uint32_t wcap, cap; 2479 char *typestr; 2480 nid_t cad = w->devinfo->codec->cad; 2481 nid_t nid = w->nid; 2482 2483 wcap = hdac_widget_getcaps(w, &w->waspin); 2484 2485 w->param.widget_cap = wcap; 2486 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2487 2488 switch (w->type) { 2489 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2490 typestr = "audio output"; 2491 break; 2492 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2493 typestr = "audio input"; 2494 break; 2495 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2496 typestr = "audio mixer"; 2497 break; 2498 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2499 typestr = "audio selector"; 2500 break; 2501 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2502 typestr = "pin"; 2503 break; 2504 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2505 typestr = "power widget"; 2506 break; 2507 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2508 typestr = "volume widget"; 2509 break; 2510 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2511 typestr = "beep widget"; 2512 break; 2513 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2514 typestr = "vendor widget"; 2515 break; 2516 default: 2517 typestr = "unknown type"; 2518 break; 2519 } 2520 2521 strlcpy(w->name, typestr, sizeof(w->name)); 2522 2523 hdac_widget_connection_parse(w); 2524 2525 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2526 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2527 w->param.outamp_cap = 2528 hdac_command(sc, 2529 HDA_CMD_GET_PARAMETER(cad, nid, 2530 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2531 else 2532 w->param.outamp_cap = 2533 w->devinfo->function.audio.outamp_cap; 2534 } else 2535 w->param.outamp_cap = 0; 2536 2537 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2538 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2539 w->param.inamp_cap = 2540 hdac_command(sc, 2541 HDA_CMD_GET_PARAMETER(cad, nid, 2542 HDA_PARAM_INPUT_AMP_CAP), cad); 2543 else 2544 w->param.inamp_cap = 2545 w->devinfo->function.audio.inamp_cap; 2546 } else 2547 w->param.inamp_cap = 0; 2548 2549 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2550 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2551 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2552 cap = hdac_command(sc, 2553 HDA_CMD_GET_PARAMETER(cad, nid, 2554 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2555 w->param.supp_stream_formats = (cap != 0) ? cap : 2556 w->devinfo->function.audio.supp_stream_formats; 2557 cap = hdac_command(sc, 2558 HDA_CMD_GET_PARAMETER(cad, nid, 2559 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2560 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2561 w->devinfo->function.audio.supp_pcm_size_rate; 2562 } else { 2563 w->param.supp_stream_formats = 2564 w->devinfo->function.audio.supp_stream_formats; 2565 w->param.supp_pcm_size_rate = 2566 w->devinfo->function.audio.supp_pcm_size_rate; 2567 } 2568 } else { 2569 w->param.supp_stream_formats = 0; 2570 w->param.supp_pcm_size_rate = 0; 2571 } 2572 2573 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2574 hdac_widget_pin_parse(w); 2575} 2576 2577static struct hdac_widget * 2578hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2579{ 2580 if (devinfo == NULL || devinfo->widget == NULL || 2581 nid < devinfo->startnode || nid >= devinfo->endnode) 2582 return (NULL); 2583 return (&devinfo->widget[nid - devinfo->startnode]); 2584} 2585 2586static __inline int 2587hda_poll_channel(struct hdac_chan *ch) 2588{ 2589 uint32_t sz, delta; 2590 volatile uint32_t ptr; 2591 2592 if (!(ch->flags & HDAC_CHN_RUNNING)) 2593 return (0); 2594 2595 sz = ch->blksz * ch->blkcnt; 2596 if (ch->dmapos != NULL) 2597 ptr = *(ch->dmapos); 2598 else 2599 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2600 ch->off + HDAC_SDLPIB); 2601 ch->ptr = ptr; 2602 ptr %= sz; 2603 ptr &= ~(ch->blksz - 1); 2604 delta = (sz + ptr - ch->prevptr) % sz; 2605 2606 if (delta < ch->blksz) 2607 return (0); 2608 2609 ch->prevptr = ptr; 2610 2611 return (1); 2612} 2613 2614static void 2615hda_poll_callback(void *arg) 2616{ 2617 struct hdac_softc *sc = arg; 2618 uint32_t trigger; 2619 int i, active = 0; 2620 2621 if (sc == NULL) 2622 return; 2623 2624 hdac_lock(sc); 2625 if (sc->polling == 0) { 2626 hdac_unlock(sc); 2627 return; 2628 } 2629 2630 trigger = 0; 2631 for (i = 0; i < sc->num_chans; i++) { 2632 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2633 continue; 2634 active = 1; 2635 if (hda_poll_channel(&sc->chans[i])) 2636 trigger |= (1 << i); 2637 } 2638 2639 /* XXX */ 2640 if (active) 2641 callout_reset(&sc->poll_hda, sc->poll_ticks, 2642 hda_poll_callback, sc); 2643 2644 hdac_unlock(sc); 2645 2646 for (i = 0; i < sc->num_chans; i++) { 2647 if (trigger & (1 << i)) 2648 chn_intr(sc->chans[i].c); 2649 } 2650} 2651 2652static int 2653hdac_rirb_flush(struct hdac_softc *sc) 2654{ 2655 struct hdac_rirb *rirb_base, *rirb; 2656 struct hdac_codec *codec; 2657 struct hdac_command_list *commands; 2658 nid_t cad; 2659 uint32_t resp; 2660 uint8_t rirbwp; 2661 int ret; 2662 2663 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2664 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2665#if 0 2666 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2667 BUS_DMASYNC_POSTREAD); 2668#endif 2669 2670 ret = 0; 2671 2672 while (sc->rirb_rp != rirbwp) { 2673 sc->rirb_rp++; 2674 sc->rirb_rp %= sc->rirb_size; 2675 rirb = &rirb_base[sc->rirb_rp]; 2676 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2677 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2678 sc->codecs[cad] == NULL) 2679 continue; 2680 resp = rirb->response; 2681 codec = sc->codecs[cad]; 2682 commands = codec->commands; 2683 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2684 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2685 ((resp >> 26) & 0xffff); 2686 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2687 } else if (commands != NULL && commands->num_commands > 0 && 2688 codec->responses_received < commands->num_commands) 2689 commands->responses[codec->responses_received++] = 2690 resp; 2691 ret++; 2692 } 2693 2694 return (ret); 2695} 2696 2697static int 2698hdac_unsolq_flush(struct hdac_softc *sc) 2699{ 2700 nid_t cad; 2701 uint32_t tag; 2702 int ret = 0; 2703 2704 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2705 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2706 while (sc->unsolq_rp != sc->unsolq_wp) { 2707 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2708 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2709 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2710 hdac_unsolicited_handler(sc->codecs[cad], tag); 2711 ret++; 2712 } 2713 sc->unsolq_st = HDAC_UNSOLQ_READY; 2714 } 2715 2716 return (ret); 2717} 2718 2719static void 2720hdac_poll_callback(void *arg) 2721{ 2722 struct hdac_softc *sc = arg; 2723 if (sc == NULL) 2724 return; 2725 2726 hdac_lock(sc); 2727 if (sc->polling == 0 || sc->poll_ival == 0) { 2728 hdac_unlock(sc); 2729 return; 2730 } 2731 if (hdac_rirb_flush(sc) != 0) 2732 hdac_unsolq_flush(sc); 2733 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2734 hdac_unlock(sc); 2735} 2736 2737static void 2738hdac_poll_reinit(struct hdac_softc *sc) 2739{ 2740 int i, pollticks, min = 1000000; 2741 struct hdac_chan *ch; 2742 2743 for (i = 0; i < sc->num_chans; i++) { 2744 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2745 continue; 2746 ch = &sc->chans[i]; 2747 pollticks = ((uint64_t)hz * ch->blksz) / 2748 ((uint64_t)sndbuf_getbps(ch->b) * 2749 sndbuf_getspd(ch->b)); 2750 pollticks >>= 1; 2751 if (pollticks > hz) 2752 pollticks = hz; 2753 if (pollticks < 1) { 2754 HDA_BOOTVERBOSE( 2755 device_printf(sc->dev, 2756 "%s: pollticks=%d < 1 !\n", 2757 __func__, pollticks); 2758 ); 2759 pollticks = 1; 2760 } 2761 if (min > pollticks) 2762 min = pollticks; 2763 } 2764 HDA_BOOTVERBOSE( 2765 device_printf(sc->dev, 2766 "%s: pollticks %d -> %d\n", 2767 __func__, sc->poll_ticks, min); 2768 ); 2769 sc->poll_ticks = min; 2770 if (min == 1000000) 2771 callout_stop(&sc->poll_hda); 2772 else 2773 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2774} 2775 2776static void 2777hdac_stream_stop(struct hdac_chan *ch) 2778{ 2779 struct hdac_softc *sc = ch->devinfo->codec->sc; 2780 uint32_t ctl; 2781 2782 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2783 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2784 HDAC_SDCTL_RUN); 2785 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2786 2787 ch->flags &= ~HDAC_CHN_RUNNING; 2788 2789 if (sc->polling != 0) 2790 hdac_poll_reinit(sc); 2791 2792 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2793 ctl &= ~(1 << (ch->off >> 5)); 2794 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2795} 2796 2797static void 2798hdac_stream_start(struct hdac_chan *ch) 2799{ 2800 struct hdac_softc *sc = ch->devinfo->codec->sc; 2801 uint32_t ctl; 2802 2803 ch->flags |= HDAC_CHN_RUNNING; 2804 2805 if (sc->polling != 0) 2806 hdac_poll_reinit(sc); 2807 2808 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2809 ctl |= 1 << (ch->off >> 5); 2810 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2811 2812 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2813 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2814 HDAC_SDCTL_RUN; 2815 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2816} 2817 2818static void 2819hdac_stream_reset(struct hdac_chan *ch) 2820{ 2821 struct hdac_softc *sc = ch->devinfo->codec->sc; 2822 int timeout = 1000; 2823 int to = timeout; 2824 uint32_t ctl; 2825 2826 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2827 ctl |= HDAC_SDCTL_SRST; 2828 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2829 do { 2830 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2831 if (ctl & HDAC_SDCTL_SRST) 2832 break; 2833 DELAY(10); 2834 } while (--to); 2835 if (!(ctl & HDAC_SDCTL_SRST)) { 2836 device_printf(sc->dev, "timeout in reset\n"); 2837 } 2838 ctl &= ~HDAC_SDCTL_SRST; 2839 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2840 to = timeout; 2841 do { 2842 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2843 if (!(ctl & HDAC_SDCTL_SRST)) 2844 break; 2845 DELAY(10); 2846 } while (--to); 2847 if (ctl & HDAC_SDCTL_SRST) 2848 device_printf(sc->dev, "can't reset!\n"); 2849} 2850 2851static void 2852hdac_stream_setid(struct hdac_chan *ch) 2853{ 2854 struct hdac_softc *sc = ch->devinfo->codec->sc; 2855 uint32_t ctl; 2856 2857 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2858 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2859 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2860 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2861} 2862 2863static void 2864hdac_bdl_setup(struct hdac_chan *ch) 2865{ 2866 struct hdac_softc *sc = ch->devinfo->codec->sc; 2867 struct hdac_bdle *bdle; 2868 uint64_t addr; 2869 uint32_t blksz, blkcnt; 2870 int i; 2871 2872 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2873 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2874 2875 blksz = ch->blksz; 2876 blkcnt = ch->blkcnt; 2877 2878 for (i = 0; i < blkcnt; i++, bdle++) { 2879 bdle->addrl = (uint32_t)addr; 2880 bdle->addrh = (uint32_t)(addr >> 32); 2881 bdle->len = blksz; 2882 bdle->ioc = 1; 2883 addr += blksz; 2884 } 2885 2886 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2887 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2888 addr = ch->bdl_dma.dma_paddr; 2889 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2890 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2891 if (ch->dmapos != NULL && 2892 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2893 addr = sc->pos_dma.dma_paddr; 2894 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2895 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2896 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2897 } 2898} 2899 2900static int 2901hdac_bdl_alloc(struct hdac_chan *ch) 2902{ 2903 struct hdac_softc *sc = ch->devinfo->codec->sc; 2904 int rc; 2905 2906 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2907 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2908 if (rc) { 2909 device_printf(sc->dev, "can't alloc bdl\n"); 2910 return (rc); 2911 } 2912 2913 return (0); 2914} 2915 2916static void 2917hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2918 int index, int lmute, int rmute, 2919 int left, int right, int dir) 2920{ 2921 uint16_t v = 0; 2922 2923 if (sc == NULL) 2924 return; 2925 2926 if (left != right || lmute != rmute) { 2927 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2928 (lmute << 7) | left; 2929 hdac_command(sc, 2930 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2931 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2932 (rmute << 7) | right; 2933 } else 2934 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2935 (lmute << 7) | left; 2936 2937 hdac_command(sc, 2938 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2939} 2940 2941static void 2942hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2943 int left, int right) 2944{ 2945 struct hdac_softc *sc; 2946 nid_t nid, cad; 2947 int lmute, rmute; 2948 2949 sc = ctl->widget->devinfo->codec->sc; 2950 cad = ctl->widget->devinfo->codec->cad; 2951 nid = ctl->widget->nid; 2952 2953 /* Save new values if valid. */ 2954 if (mute != HDA_AMP_MUTE_DEFAULT) 2955 ctl->muted = mute; 2956 if (left != HDA_AMP_VOL_DEFAULT) 2957 ctl->left = left; 2958 if (right != HDA_AMP_VOL_DEFAULT) 2959 ctl->right = right; 2960 /* Prepare effective values */ 2961 if (ctl->forcemute) { 2962 lmute = 1; 2963 rmute = 1; 2964 left = 0; 2965 right = 0; 2966 } else { 2967 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2968 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2969 left = ctl->left; 2970 right = ctl->right; 2971 } 2972 /* Apply effective values */ 2973 if (ctl->dir & HDA_CTL_OUT) 2974 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2975 lmute, rmute, left, right, 0); 2976 if (ctl->dir & HDA_CTL_IN) 2977 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2978 lmute, rmute, left, right, 1); 2979} 2980 2981static void 2982hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2983{ 2984 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2985 return; 2986 hdac_command(w->devinfo->codec->sc, 2987 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2988 w->nid, index), w->devinfo->codec->cad); 2989 w->selconn = index; 2990} 2991 2992 2993/**************************************************************************** 2994 * uint32_t hdac_command_sendone_internal 2995 * 2996 * Wrapper function that sends only one command to a given codec 2997 ****************************************************************************/ 2998static uint32_t 2999hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3000{ 3001 struct hdac_command_list cl; 3002 uint32_t response = HDAC_INVALID; 3003 3004 if (!hdac_lockowned(sc)) 3005 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3006 cl.num_commands = 1; 3007 cl.verbs = &verb; 3008 cl.responses = &response; 3009 3010 hdac_command_send_internal(sc, &cl, cad); 3011 3012 return (response); 3013} 3014 3015/**************************************************************************** 3016 * hdac_command_send_internal 3017 * 3018 * Send a command list to the codec via the corb. We queue as much verbs as 3019 * we can and msleep on the codec. When the interrupt get the responses 3020 * back from the rirb, it will wake us up so we can queue the remaining verbs 3021 * if any. 3022 ****************************************************************************/ 3023static void 3024hdac_command_send_internal(struct hdac_softc *sc, 3025 struct hdac_command_list *commands, nid_t cad) 3026{ 3027 struct hdac_codec *codec; 3028 int corbrp; 3029 uint32_t *corb; 3030 int timeout; 3031 int retry = 10; 3032 struct hdac_rirb *rirb_base; 3033 3034 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3035 commands->num_commands < 1) 3036 return; 3037 3038 codec = sc->codecs[cad]; 3039 codec->commands = commands; 3040 codec->responses_received = 0; 3041 codec->verbs_sent = 0; 3042 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3043 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3044 3045 do { 3046 if (codec->verbs_sent != commands->num_commands) { 3047 /* Queue as many verbs as possible */ 3048 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3049#if 0 3050 bus_dmamap_sync(sc->corb_dma.dma_tag, 3051 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3052#endif 3053 while (codec->verbs_sent != commands->num_commands && 3054 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3055 sc->corb_wp++; 3056 sc->corb_wp %= sc->corb_size; 3057 corb[sc->corb_wp] = 3058 commands->verbs[codec->verbs_sent++]; 3059 } 3060 3061 /* Send the verbs to the codecs */ 3062#if 0 3063 bus_dmamap_sync(sc->corb_dma.dma_tag, 3064 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3065#endif 3066 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3067 } 3068 3069 timeout = 1000; 3070 while (hdac_rirb_flush(sc) == 0 && --timeout) 3071 DELAY(10); 3072 } while ((codec->verbs_sent != commands->num_commands || 3073 codec->responses_received != commands->num_commands) && --retry); 3074 3075 if (retry == 0) 3076 device_printf(sc->dev, 3077 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3078 __func__, commands->num_commands, codec->verbs_sent, 3079 codec->responses_received); 3080 3081 codec->commands = NULL; 3082 codec->responses_received = 0; 3083 codec->verbs_sent = 0; 3084 3085 hdac_unsolq_flush(sc); 3086} 3087 3088 3089/**************************************************************************** 3090 * Device Methods 3091 ****************************************************************************/ 3092 3093/**************************************************************************** 3094 * int hdac_probe(device_t) 3095 * 3096 * Probe for the presence of an hdac. If none is found, check for a generic 3097 * match using the subclass of the device. 3098 ****************************************************************************/ 3099static int 3100hdac_probe(device_t dev) 3101{ 3102 int i, result; 3103 uint32_t model; 3104 uint16_t class, subclass; 3105 char desc[64]; 3106 3107 model = (uint32_t)pci_get_device(dev) << 16; 3108 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3109 class = pci_get_class(dev); 3110 subclass = pci_get_subclass(dev); 3111 3112 bzero(desc, sizeof(desc)); 3113 result = ENXIO; 3114 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3115 if (hdac_devices[i].model == model) { 3116 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3117 result = BUS_PROBE_DEFAULT; 3118 break; 3119 } 3120 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3121 class == PCIC_MULTIMEDIA && 3122 subclass == PCIS_MULTIMEDIA_HDA) { 3123 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3124 result = BUS_PROBE_GENERIC; 3125 break; 3126 } 3127 } 3128 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3129 subclass == PCIS_MULTIMEDIA_HDA) { 3130 strlcpy(desc, "Generic", sizeof(desc)); 3131 result = BUS_PROBE_GENERIC; 3132 } 3133 if (result != ENXIO) { 3134 strlcat(desc, " High Definition Audio Controller", 3135 sizeof(desc)); 3136 device_set_desc_copy(dev, desc); 3137 } 3138 3139 return (result); 3140} 3141 3142static void * 3143hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3144 struct pcm_channel *c, int dir) 3145{ 3146 struct hdac_pcm_devinfo *pdevinfo = data; 3147 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3148 struct hdac_softc *sc = devinfo->codec->sc; 3149 struct hdac_chan *ch; 3150 int i, ord = 0, chid; 3151 3152 hdac_lock(sc); 3153 3154 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3155 ch = &sc->chans[chid]; 3156 for (i = 0; i < sc->num_chans && i < chid; i++) { 3157 if (ch->dir == sc->chans[i].dir) 3158 ord++; 3159 } 3160 if (dir == PCMDIR_PLAY) { 3161 ch->off = (sc->num_iss + ord) << 5; 3162 } else { 3163 ch->off = ord << 5; 3164 } 3165 3166 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3167 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3168 ch->pcmrates[0] = 48000; 3169 ch->pcmrates[1] = 0; 3170 } 3171 if (sc->pos_dma.dma_vaddr != NULL) 3172 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3173 (sc->streamcnt * 8)); 3174 else 3175 ch->dmapos = NULL; 3176 ch->sid = ++sc->streamcnt; 3177 ch->dir = dir; 3178 ch->b = b; 3179 ch->c = c; 3180 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3181 ch->blkcnt = pdevinfo->chan_blkcnt; 3182 hdac_unlock(sc); 3183 3184 if (hdac_bdl_alloc(ch) != 0) { 3185 ch->blkcnt = 0; 3186 return (NULL); 3187 } 3188 3189 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3190 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3191 pdevinfo->chan_size) != 0) 3192 return (NULL); 3193 3194 return (ch); 3195} 3196 3197static int 3198hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3199{ 3200 struct hdac_chan *ch = data; 3201 int i; 3202 3203 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3204 if (format == ch->caps.fmtlist[i]) { 3205 ch->fmt = format; 3206 return (0); 3207 } 3208 } 3209 3210 return (EINVAL); 3211} 3212 3213static int 3214hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3215{ 3216 struct hdac_chan *ch = data; 3217 uint32_t spd = 0, threshold; 3218 int i; 3219 3220 for (i = 0; ch->pcmrates[i] != 0; i++) { 3221 spd = ch->pcmrates[i]; 3222 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3223 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3224 if (speed < threshold) 3225 break; 3226 } 3227 3228 if (spd == 0) /* impossible */ 3229 ch->spd = 48000; 3230 else 3231 ch->spd = spd; 3232 3233 return (ch->spd); 3234} 3235 3236static void 3237hdac_stream_setup(struct hdac_chan *ch) 3238{ 3239 struct hdac_softc *sc = ch->devinfo->codec->sc; 3240 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3241 struct hdac_widget *w; 3242 int i, chn, totalchn, c; 3243 nid_t cad = ch->devinfo->codec->cad; 3244 uint16_t fmt, dfmt; 3245 3246 HDA_BOOTHVERBOSE( 3247 device_printf(ch->pdevinfo->dev, 3248 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3249 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3250 ch->fmt, ch->spd); 3251 ); 3252 fmt = 0; 3253 if (ch->fmt & AFMT_S16_LE) 3254 fmt |= ch->bit16 << 4; 3255 else if (ch->fmt & AFMT_S32_LE) 3256 fmt |= ch->bit32 << 4; 3257 else 3258 fmt |= 1 << 4; 3259 3260 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3261 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3262 fmt |= hda_rate_tab[i].base; 3263 fmt |= hda_rate_tab[i].mul; 3264 fmt |= hda_rate_tab[i].div; 3265 break; 3266 } 3267 } 3268 3269 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3270 fmt |= 1; 3271 totalchn = 2; 3272 } else 3273 totalchn = 1; 3274 3275 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3276 3277 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3278 if (ch->fmt & AFMT_AC3) 3279 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3280 3281 chn = 0; 3282 for (i = 0; ch->io[i] != -1; i++) { 3283 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3284 if (w == NULL) 3285 continue; 3286 3287 if (as->hpredir >= 0 && i == as->pincnt) 3288 chn = 0; 3289 HDA_BOOTHVERBOSE( 3290 device_printf(ch->pdevinfo->dev, 3291 "PCMDIR_%s: Stream setup nid=%d: " 3292 "fmt=0x%04x, dfmt=0x%04x\n", 3293 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3294 ch->io[i], fmt, dfmt); 3295 ); 3296 hdac_command(sc, 3297 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3298 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3299 hdac_command(sc, 3300 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3301 cad); 3302 } 3303 /* If HP redirection is enabled, but failed to use same 3304 DAC make last DAC one to duplicate first one. */ 3305 if (as->hpredir >= 0 && i == as->pincnt) { 3306 c = (ch->sid << 4); 3307 } else if (chn >= totalchn) { 3308 /* This is until OSS will support multichannel. 3309 Should be: c = 0; to disable unused DAC */ 3310 c = (ch->sid << 4); 3311 }else { 3312 c = (ch->sid << 4) | chn; 3313 } 3314 hdac_command(sc, 3315 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3316 chn += 3317 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3318 2 : 1; 3319 } 3320} 3321 3322static int 3323hdac_channel_setfragments(kobj_t obj, void *data, 3324 uint32_t blksz, uint32_t blkcnt) 3325{ 3326 struct hdac_chan *ch = data; 3327 struct hdac_softc *sc = ch->devinfo->codec->sc; 3328 3329 blksz &= HDA_BLK_ALIGN; 3330 3331 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3332 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3333 if (blksz < HDA_BLK_MIN) 3334 blksz = HDA_BLK_MIN; 3335 if (blkcnt > HDA_BDL_MAX) 3336 blkcnt = HDA_BDL_MAX; 3337 if (blkcnt < HDA_BDL_MIN) 3338 blkcnt = HDA_BDL_MIN; 3339 3340 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3341 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3342 blkcnt >>= 1; 3343 else if ((blksz >> 1) >= HDA_BLK_MIN) 3344 blksz >>= 1; 3345 else 3346 break; 3347 } 3348 3349 if ((sndbuf_getblksz(ch->b) != blksz || 3350 sndbuf_getblkcnt(ch->b) != blkcnt) && 3351 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3352 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3353 __func__, blksz, blkcnt); 3354 3355 ch->blksz = sndbuf_getblksz(ch->b); 3356 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3357 3358 return (1); 3359} 3360 3361static int 3362hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3363{ 3364 struct hdac_chan *ch = data; 3365 3366 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3367 3368 return (ch->blksz); 3369} 3370 3371static void 3372hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3373{ 3374 struct hdac_devinfo *devinfo = ch->devinfo; 3375 struct hdac_widget *w; 3376 nid_t cad = devinfo->codec->cad; 3377 int i; 3378 3379 hdac_stream_stop(ch); 3380 3381 for (i = 0; ch->io[i] != -1; i++) { 3382 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3383 if (w == NULL) 3384 continue; 3385 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3386 hdac_command(sc, 3387 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3388 cad); 3389 } 3390 hdac_command(sc, 3391 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3392 0), cad); 3393 } 3394} 3395 3396static void 3397hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3398{ 3399 ch->ptr = 0; 3400 ch->prevptr = 0; 3401 hdac_stream_stop(ch); 3402 hdac_stream_reset(ch); 3403 hdac_bdl_setup(ch); 3404 hdac_stream_setid(ch); 3405 hdac_stream_setup(ch); 3406 hdac_stream_start(ch); 3407} 3408 3409static int 3410hdac_channel_trigger(kobj_t obj, void *data, int go) 3411{ 3412 struct hdac_chan *ch = data; 3413 struct hdac_softc *sc = ch->devinfo->codec->sc; 3414 3415 if (!PCMTRIG_COMMON(go)) 3416 return (0); 3417 3418 hdac_lock(sc); 3419 switch (go) { 3420 case PCMTRIG_START: 3421 hdac_channel_start(sc, ch); 3422 break; 3423 case PCMTRIG_STOP: 3424 case PCMTRIG_ABORT: 3425 hdac_channel_stop(sc, ch); 3426 break; 3427 default: 3428 break; 3429 } 3430 hdac_unlock(sc); 3431 3432 return (0); 3433} 3434 3435static int 3436hdac_channel_getptr(kobj_t obj, void *data) 3437{ 3438 struct hdac_chan *ch = data; 3439 struct hdac_softc *sc = ch->devinfo->codec->sc; 3440 uint32_t ptr; 3441 3442 hdac_lock(sc); 3443 if (sc->polling != 0) 3444 ptr = ch->ptr; 3445 else if (ch->dmapos != NULL) 3446 ptr = *(ch->dmapos); 3447 else 3448 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3449 hdac_unlock(sc); 3450 3451 /* 3452 * Round to available space and force 128 bytes aligment. 3453 */ 3454 ptr %= ch->blksz * ch->blkcnt; 3455 ptr &= HDA_BLK_ALIGN; 3456 3457 return (ptr); 3458} 3459 3460static struct pcmchan_caps * 3461hdac_channel_getcaps(kobj_t obj, void *data) 3462{ 3463 return (&((struct hdac_chan *)data)->caps); 3464} 3465 3466static kobj_method_t hdac_channel_methods[] = { 3467 KOBJMETHOD(channel_init, hdac_channel_init), 3468 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3469 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3470 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3471 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3472 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3473 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3474 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3475 { 0, 0 } 3476}; 3477CHANNEL_DECLARE(hdac_channel); 3478 3479static int 3480hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3481{ 3482 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3483 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3484 struct hdac_softc *sc = devinfo->codec->sc; 3485 struct hdac_widget *w, *cw; 3486 struct hdac_audio_ctl *ctl; 3487 uint32_t mask, recmask, id; 3488 int i, j, softpcmvol; 3489 3490 hdac_lock(sc); 3491 3492 /* Make sure that in case of soft volume it won't stay muted. */ 3493 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3494 pdevinfo->left[i] = 100; 3495 pdevinfo->right[i] = 100; 3496 } 3497 3498 mask = 0; 3499 recmask = 0; 3500 id = hdac_codec_id(devinfo->codec); 3501 3502 /* Declate EAPD as ogain control. */ 3503 if (pdevinfo->play >= 0) { 3504 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3505 w = hdac_widget_get(devinfo, i); 3506 if (w == NULL || w->enable == 0) 3507 continue; 3508 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3509 w->param.eapdbtl == HDAC_INVALID || 3510 w->bindas != sc->chans[pdevinfo->play].as) 3511 continue; 3512 mask |= SOUND_MASK_OGAIN; 3513 break; 3514 } 3515 } 3516 3517 /* Declare volume controls assigned to this association. */ 3518 i = 0; 3519 ctl = NULL; 3520 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3521 if (ctl->enable == 0) 3522 continue; 3523 if ((pdevinfo->play >= 0 && 3524 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3525 (pdevinfo->rec >= 0 && 3526 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3527 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3528 mask |= ctl->ossmask; 3529 } 3530 3531 /* Declare record sources available to this association. */ 3532 if (pdevinfo->rec >= 0) { 3533 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3534 for (i = 0; ch->io[i] != -1; i++) { 3535 w = hdac_widget_get(devinfo, ch->io[i]); 3536 if (w == NULL || w->enable == 0) 3537 continue; 3538 for (j = 0; j < w->nconns; j++) { 3539 if (w->connsenable[j] == 0) 3540 continue; 3541 cw = hdac_widget_get(devinfo, w->conns[j]); 3542 if (cw == NULL || cw->enable == 0) 3543 continue; 3544 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3545 cw->bindas != -2) 3546 continue; 3547 recmask |= cw->ossmask; 3548 } 3549 } 3550 } 3551 3552 /* Declare soft PCM and master volume if needed. */ 3553 if (pdevinfo->play >= 0) { 3554 ctl = NULL; 3555 if ((mask & SOUND_MASK_PCM) == 0 || 3556 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3557 softpcmvol = 1; 3558 mask |= SOUND_MASK_PCM; 3559 } else { 3560 softpcmvol = 0; 3561 i = 0; 3562 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3563 if (ctl->enable == 0) 3564 continue; 3565 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3566 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3567 continue; 3568 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3569 continue; 3570 if (ctl->step > 0) 3571 break; 3572 } 3573 } 3574 3575 if (softpcmvol == 1 || ctl == NULL) { 3576 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3577 HDA_BOOTVERBOSE( 3578 device_printf(pdevinfo->dev, 3579 "%s Soft PCM volume\n", 3580 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3581 ); 3582 } 3583 3584 if ((mask & SOUND_MASK_VOLUME) == 0) { 3585 mask |= SOUND_MASK_VOLUME; 3586 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3587 SOUND_MASK_PCM); 3588 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3589 SOUND_MIXER_NONE); 3590 HDA_BOOTVERBOSE( 3591 device_printf(pdevinfo->dev, 3592 "Forcing master volume with PCM\n"); 3593 ); 3594 } 3595 } 3596 3597 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3598 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3599 3600 mix_setrecdevs(m, recmask); 3601 mix_setdevs(m, mask); 3602 3603 hdac_unlock(sc); 3604 3605 return (0); 3606} 3607 3608static int 3609hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3610 unsigned left, unsigned right) 3611{ 3612 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3613 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3614 struct hdac_softc *sc = devinfo->codec->sc; 3615 struct hdac_widget *w; 3616 struct hdac_audio_ctl *ctl; 3617 uint32_t mute; 3618 int lvol, rvol; 3619 int i, j; 3620 3621 hdac_lock(sc); 3622 /* Save new values. */ 3623 pdevinfo->left[dev] = left; 3624 pdevinfo->right[dev] = right; 3625 3626 /* 'ogain' is the special case implemented with EAPD. */ 3627 if (dev == SOUND_MIXER_OGAIN) { 3628 uint32_t orig; 3629 w = NULL; 3630 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3631 w = hdac_widget_get(devinfo, i); 3632 if (w == NULL || w->enable == 0) 3633 continue; 3634 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3635 w->param.eapdbtl == HDAC_INVALID) 3636 continue; 3637 break; 3638 } 3639 if (i >= devinfo->endnode) { 3640 hdac_unlock(sc); 3641 return (-1); 3642 } 3643 orig = w->param.eapdbtl; 3644 if (left == 0) 3645 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3646 else 3647 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3648 if (orig != w->param.eapdbtl) { 3649 uint32_t val; 3650 3651 val = w->param.eapdbtl; 3652 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3653 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3654 hdac_command(sc, 3655 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3656 w->nid, val), devinfo->codec->cad); 3657 } 3658 hdac_unlock(sc); 3659 return (left | (left << 8)); 3660 } 3661 3662 /* Recalculate all controls related to this OSS device. */ 3663 i = 0; 3664 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3665 if (ctl->enable == 0 || 3666 !(ctl->ossmask & (1 << dev))) 3667 continue; 3668 if (!((pdevinfo->play >= 0 && 3669 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3670 (pdevinfo->rec >= 0 && 3671 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3672 ctl->widget->bindas == -2)) 3673 continue; 3674 3675 lvol = 100; 3676 rvol = 100; 3677 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3678 if (ctl->ossmask & (1 << j)) { 3679 lvol = lvol * pdevinfo->left[j] / 100; 3680 rvol = rvol * pdevinfo->right[j] / 100; 3681 } 3682 } 3683 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3684 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3685 lvol = (lvol * ctl->step + 50) / 100; 3686 rvol = (rvol * ctl->step + 50) / 100; 3687 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3688 } 3689 hdac_unlock(sc); 3690 3691 return (left | (right << 8)); 3692} 3693 3694/* 3695 * Commutate specified record source. 3696 */ 3697static uint32_t 3698hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3699{ 3700 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3701 struct hdac_widget *w, *cw; 3702 struct hdac_audio_ctl *ctl; 3703 char buf[64]; 3704 int i, muted; 3705 uint32_t res = 0; 3706 3707 if (depth > HDA_PARSE_MAXDEPTH) 3708 return (0); 3709 3710 w = hdac_widget_get(devinfo, nid); 3711 if (w == NULL || w->enable == 0) 3712 return (0); 3713 3714 for (i = 0; i < w->nconns; i++) { 3715 if (w->connsenable[i] == 0) 3716 continue; 3717 cw = hdac_widget_get(devinfo, w->conns[i]); 3718 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3719 continue; 3720 /* Call recursively to trace signal to it's source if needed. */ 3721 if ((src & cw->ossmask) != 0) { 3722 if (cw->ossdev < 0) { 3723 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3724 w->conns[i], depth + 1); 3725 } else { 3726 res |= cw->ossmask; 3727 } 3728 } 3729 /* We have two special cases: mixers and others (selectors). */ 3730 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3731 ctl = hdac_audio_ctl_amp_get(devinfo, 3732 w->nid, HDA_CTL_IN, i, 1); 3733 if (ctl == NULL) 3734 continue; 3735 /* If we have input control on this node mute them 3736 * according to requested sources. */ 3737 muted = (src & cw->ossmask) ? 0 : 1; 3738 if (muted != ctl->forcemute) { 3739 ctl->forcemute = muted; 3740 hdac_audio_ctl_amp_set(ctl, 3741 HDA_AMP_MUTE_DEFAULT, 3742 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3743 } 3744 HDA_BOOTHVERBOSE( 3745 device_printf(pdevinfo->dev, 3746 "Recsel (%s): nid %d source %d %s\n", 3747 hdac_audio_ctl_ossmixer_mask2allname( 3748 src, buf, sizeof(buf)), 3749 nid, i, muted?"mute":"unmute"); 3750 ); 3751 } else { 3752 if (w->nconns == 1) 3753 break; 3754 if ((src & cw->ossmask) == 0) 3755 continue; 3756 /* If we found requested source - select it and exit. */ 3757 hdac_widget_connection_select(w, i); 3758 HDA_BOOTHVERBOSE( 3759 device_printf(pdevinfo->dev, 3760 "Recsel (%s): nid %d source %d select\n", 3761 hdac_audio_ctl_ossmixer_mask2allname( 3762 src, buf, sizeof(buf)), 3763 nid, i); 3764 ); 3765 break; 3766 } 3767 } 3768 return (res); 3769} 3770 3771static uint32_t 3772hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3773{ 3774 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3775 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3776 struct hdac_widget *w; 3777 struct hdac_softc *sc = devinfo->codec->sc; 3778 struct hdac_chan *ch; 3779 int i; 3780 uint32_t ret = 0xffffffff; 3781 3782 hdac_lock(sc); 3783 3784 /* Commutate requested recsrc for each ADC. */ 3785 ch = &sc->chans[pdevinfo->rec]; 3786 for (i = 0; ch->io[i] != -1; i++) { 3787 w = hdac_widget_get(devinfo, ch->io[i]); 3788 if (w == NULL || w->enable == 0) 3789 continue; 3790 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3791 } 3792 3793 hdac_unlock(sc); 3794 3795 return ((ret == 0xffffffff)? 0 : ret); 3796} 3797 3798static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3799 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3800 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3801 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3802 { 0, 0 } 3803}; 3804MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3805 3806static void 3807hdac_unsolq_task(void *context, int pending) 3808{ 3809 struct hdac_softc *sc; 3810 3811 sc = (struct hdac_softc *)context; 3812 3813 hdac_lock(sc); 3814 hdac_unsolq_flush(sc); 3815 hdac_unlock(sc); 3816} 3817 3818/**************************************************************************** 3819 * int hdac_attach(device_t) 3820 * 3821 * Attach the device into the kernel. Interrupts usually won't be enabled 3822 * when this function is called. Setup everything that doesn't require 3823 * interrupts and defer probing of codecs until interrupts are enabled. 3824 ****************************************************************************/ 3825static int 3826hdac_attach(device_t dev) 3827{ 3828 struct hdac_softc *sc; 3829 int result; 3830 int i; 3831 uint16_t vendor; 3832 uint8_t v; 3833 3834 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3835 3836 sc = device_get_softc(dev); 3837 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3838 sc->dev = dev; 3839 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3840 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3841 vendor = pci_get_vendor(dev); 3842 3843 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3844 /* Screw nx6325 - subdevice/subvendor swapped */ 3845 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3846 } 3847 3848 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3849 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3850 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3851 3852 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3853 3854 sc->poll_ticks = 1000000; 3855 sc->poll_ival = HDAC_POLL_INTERVAL; 3856 if (resource_int_value(device_get_name(dev), 3857 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3858 sc->polling = 1; 3859 else 3860 sc->polling = 0; 3861 3862 result = bus_dma_tag_create(NULL, /* parent */ 3863 HDAC_DMA_ALIGNMENT, /* alignment */ 3864 0, /* boundary */ 3865 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3866 BUS_SPACE_MAXADDR, /* highaddr */ 3867 NULL, /* filtfunc */ 3868 NULL, /* fistfuncarg */ 3869 HDA_BUFSZ_MAX, /* maxsize */ 3870 1, /* nsegments */ 3871 HDA_BUFSZ_MAX, /* maxsegsz */ 3872 0, /* flags */ 3873 NULL, /* lockfunc */ 3874 NULL, /* lockfuncarg */ 3875 &sc->chan_dmat); /* dmat */ 3876 if (result != 0) { 3877 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3878 __func__, result); 3879 snd_mtxfree(sc->lock); 3880 free(sc, M_DEVBUF); 3881 return (ENXIO); 3882 } 3883 3884 3885 sc->hdabus = NULL; 3886 for (i = 0; i < HDAC_CODEC_MAX; i++) 3887 sc->codecs[i] = NULL; 3888 3889 pci_enable_busmaster(dev); 3890 3891 if (vendor == INTEL_VENDORID) { 3892 /* TCSEL -> TC0 */ 3893 v = pci_read_config(dev, 0x44, 1); 3894 pci_write_config(dev, 0x44, v & 0xf8, 1); 3895 HDA_BOOTHVERBOSE( 3896 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3897 pci_read_config(dev, 0x44, 1)); 3898 ); 3899 } 3900 3901#ifdef HDAC_MSI_ENABLED 3902 if (resource_int_value(device_get_name(dev), 3903 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3904 pci_msi_count(dev) == 1) 3905 sc->flags |= HDAC_F_MSI; 3906 else 3907#endif 3908 sc->flags &= ~HDAC_F_MSI; 3909 3910#if defined(__i386__) || defined(__amd64__) 3911 sc->flags |= HDAC_F_DMA_NOCACHE; 3912 3913 if (resource_int_value(device_get_name(dev), 3914 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3915#else 3916 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3917#endif 3918 /* 3919 * Try to enable PCIe snoop to avoid messing around with 3920 * uncacheable DMA attribute. Since PCIe snoop register 3921 * config is pretty much vendor specific, there are no 3922 * general solutions on how to enable it, forcing us (even 3923 * Microsoft) to enable uncacheable or write combined DMA 3924 * by default. 3925 * 3926 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3927 */ 3928 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3929 if (hdac_pcie_snoop[i].vendor != vendor) 3930 continue; 3931 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3932 if (hdac_pcie_snoop[i].reg == 0x00) 3933 break; 3934 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3935 if ((v & hdac_pcie_snoop[i].enable) == 3936 hdac_pcie_snoop[i].enable) 3937 break; 3938 v &= hdac_pcie_snoop[i].mask; 3939 v |= hdac_pcie_snoop[i].enable; 3940 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3941 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3942 if ((v & hdac_pcie_snoop[i].enable) != 3943 hdac_pcie_snoop[i].enable) { 3944 HDA_BOOTVERBOSE( 3945 device_printf(dev, 3946 "WARNING: Failed to enable PCIe " 3947 "snoop!\n"); 3948 ); 3949#if defined(__i386__) || defined(__amd64__) 3950 sc->flags |= HDAC_F_DMA_NOCACHE; 3951#endif 3952 } 3953 break; 3954 } 3955#if defined(__i386__) || defined(__amd64__) 3956 } 3957#endif 3958 3959 HDA_BOOTHVERBOSE( 3960 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3961 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3962 "Uncacheable" : "PCIe snoop", vendor); 3963 ); 3964 3965 /* Allocate resources */ 3966 result = hdac_mem_alloc(sc); 3967 if (result != 0) 3968 goto hdac_attach_fail; 3969 result = hdac_irq_alloc(sc); 3970 if (result != 0) 3971 goto hdac_attach_fail; 3972 3973 /* Get Capabilities */ 3974 result = hdac_get_capabilities(sc); 3975 if (result != 0) 3976 goto hdac_attach_fail; 3977 3978 /* Allocate CORB and RIRB dma memory */ 3979 result = hdac_dma_alloc(sc, &sc->corb_dma, 3980 sc->corb_size * sizeof(uint32_t)); 3981 if (result != 0) 3982 goto hdac_attach_fail; 3983 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3984 sc->rirb_size * sizeof(struct hdac_rirb)); 3985 if (result != 0) 3986 goto hdac_attach_fail; 3987 3988 /* Quiesce everything */ 3989 HDA_BOOTHVERBOSE( 3990 device_printf(dev, "Reset controller...\n"); 3991 ); 3992 hdac_reset(sc, 1); 3993 3994 /* Initialize the CORB and RIRB */ 3995 hdac_corb_init(sc); 3996 hdac_rirb_init(sc); 3997 3998 /* Defer remaining of initialization until interrupts are enabled */ 3999 sc->intrhook.ich_func = hdac_attach2; 4000 sc->intrhook.ich_arg = (void *)sc; 4001 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4002 sc->intrhook.ich_func = NULL; 4003 hdac_attach2((void *)sc); 4004 } 4005 4006 return (0); 4007 4008hdac_attach_fail: 4009 hdac_irq_free(sc); 4010 hdac_dma_free(sc, &sc->rirb_dma); 4011 hdac_dma_free(sc, &sc->corb_dma); 4012 hdac_mem_free(sc); 4013 snd_mtxfree(sc->lock); 4014 free(sc, M_DEVBUF); 4015 4016 return (ENXIO); 4017} 4018 4019static void 4020hdac_audio_parse(struct hdac_devinfo *devinfo) 4021{ 4022 struct hdac_codec *codec = devinfo->codec; 4023 struct hdac_softc *sc = codec->sc; 4024 struct hdac_widget *w; 4025 uint32_t res; 4026 int i; 4027 nid_t cad, nid; 4028 4029 cad = devinfo->codec->cad; 4030 nid = devinfo->nid; 4031 4032 res = hdac_command(sc, 4033 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4034 devinfo->function.audio.gpio = res; 4035 4036 HDA_BOOTVERBOSE( 4037 device_printf(sc->dev, "GPIO: 0x%08x " 4038 "NumGPIO=%d NumGPO=%d " 4039 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4040 devinfo->function.audio.gpio, 4041 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4042 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4043 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4044 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4045 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4046 ); 4047 4048 res = hdac_command(sc, 4049 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4050 cad); 4051 devinfo->function.audio.supp_stream_formats = res; 4052 4053 res = hdac_command(sc, 4054 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4055 cad); 4056 devinfo->function.audio.supp_pcm_size_rate = res; 4057 4058 res = hdac_command(sc, 4059 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4060 cad); 4061 devinfo->function.audio.outamp_cap = res; 4062 4063 res = hdac_command(sc, 4064 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4065 cad); 4066 devinfo->function.audio.inamp_cap = res; 4067 4068 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4069 w = hdac_widget_get(devinfo, i); 4070 if (w == NULL) 4071 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4072 else { 4073 w->devinfo = devinfo; 4074 w->nid = i; 4075 w->enable = 1; 4076 w->selconn = -1; 4077 w->pflags = 0; 4078 w->ossdev = -1; 4079 w->bindas = -1; 4080 w->param.eapdbtl = HDAC_INVALID; 4081 hdac_widget_parse(w); 4082 } 4083 } 4084} 4085 4086static void 4087hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4088{ 4089 struct hdac_softc *sc = devinfo->codec->sc; 4090 struct hdac_audio_ctl *ctls; 4091 struct hdac_widget *w, *cw; 4092 int i, j, cnt, max, ocap, icap; 4093 int mute, offset, step, size; 4094 4095 /* XXX This is redundant */ 4096 max = 0; 4097 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4098 w = hdac_widget_get(devinfo, i); 4099 if (w == NULL || w->enable == 0) 4100 continue; 4101 if (w->param.outamp_cap != 0) 4102 max++; 4103 if (w->param.inamp_cap != 0) { 4104 switch (w->type) { 4105 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4106 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4107 for (j = 0; j < w->nconns; j++) { 4108 cw = hdac_widget_get(devinfo, 4109 w->conns[j]); 4110 if (cw == NULL || cw->enable == 0) 4111 continue; 4112 max++; 4113 } 4114 break; 4115 default: 4116 max++; 4117 break; 4118 } 4119 } 4120 } 4121 4122 devinfo->function.audio.ctlcnt = max; 4123 4124 if (max < 1) 4125 return; 4126 4127 ctls = (struct hdac_audio_ctl *)malloc( 4128 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4129 4130 if (ctls == NULL) { 4131 /* Blekh! */ 4132 device_printf(sc->dev, "unable to allocate ctls!\n"); 4133 devinfo->function.audio.ctlcnt = 0; 4134 return; 4135 } 4136 4137 cnt = 0; 4138 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4139 if (cnt >= max) { 4140 device_printf(sc->dev, "%s: Ctl overflow!\n", 4141 __func__); 4142 break; 4143 } 4144 w = hdac_widget_get(devinfo, i); 4145 if (w == NULL || w->enable == 0) 4146 continue; 4147 ocap = w->param.outamp_cap; 4148 icap = w->param.inamp_cap; 4149 if (ocap != 0) { 4150 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4151 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4152 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4153 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4154 /*if (offset > step) { 4155 HDA_BOOTVERBOSE( 4156 device_printf(sc->dev, 4157 "BUGGY outamp: nid=%d " 4158 "[offset=%d > step=%d]\n", 4159 w->nid, offset, step); 4160 ); 4161 offset = step; 4162 }*/ 4163 ctls[cnt].enable = 1; 4164 ctls[cnt].widget = w; 4165 ctls[cnt].mute = mute; 4166 ctls[cnt].step = step; 4167 ctls[cnt].size = size; 4168 ctls[cnt].offset = offset; 4169 ctls[cnt].left = offset; 4170 ctls[cnt].right = offset; 4171 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4172 w->waspin) 4173 ctls[cnt].ndir = HDA_CTL_IN; 4174 else 4175 ctls[cnt].ndir = HDA_CTL_OUT; 4176 ctls[cnt++].dir = HDA_CTL_OUT; 4177 } 4178 4179 if (icap != 0) { 4180 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4181 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4182 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4183 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4184 /*if (offset > step) { 4185 HDA_BOOTVERBOSE( 4186 device_printf(sc->dev, 4187 "BUGGY inamp: nid=%d " 4188 "[offset=%d > step=%d]\n", 4189 w->nid, offset, step); 4190 ); 4191 offset = step; 4192 }*/ 4193 switch (w->type) { 4194 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4195 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4196 for (j = 0; j < w->nconns; j++) { 4197 if (cnt >= max) { 4198 device_printf(sc->dev, 4199 "%s: Ctl overflow!\n", 4200 __func__); 4201 break; 4202 } 4203 cw = hdac_widget_get(devinfo, 4204 w->conns[j]); 4205 if (cw == NULL || cw->enable == 0) 4206 continue; 4207 ctls[cnt].enable = 1; 4208 ctls[cnt].widget = w; 4209 ctls[cnt].childwidget = cw; 4210 ctls[cnt].index = j; 4211 ctls[cnt].mute = mute; 4212 ctls[cnt].step = step; 4213 ctls[cnt].size = size; 4214 ctls[cnt].offset = offset; 4215 ctls[cnt].left = offset; 4216 ctls[cnt].right = offset; 4217 ctls[cnt].ndir = HDA_CTL_IN; 4218 ctls[cnt++].dir = HDA_CTL_IN; 4219 } 4220 break; 4221 default: 4222 if (cnt >= max) { 4223 device_printf(sc->dev, 4224 "%s: Ctl overflow!\n", 4225 __func__); 4226 break; 4227 } 4228 ctls[cnt].enable = 1; 4229 ctls[cnt].widget = w; 4230 ctls[cnt].mute = mute; 4231 ctls[cnt].step = step; 4232 ctls[cnt].size = size; 4233 ctls[cnt].offset = offset; 4234 ctls[cnt].left = offset; 4235 ctls[cnt].right = offset; 4236 if (w->type == 4237 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4238 ctls[cnt].ndir = HDA_CTL_OUT; 4239 else 4240 ctls[cnt].ndir = HDA_CTL_IN; 4241 ctls[cnt++].dir = HDA_CTL_IN; 4242 break; 4243 } 4244 } 4245 } 4246 4247 devinfo->function.audio.ctl = ctls; 4248} 4249 4250static void 4251hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4252{ 4253 struct hdac_softc *sc = devinfo->codec->sc; 4254 struct hdac_audio_as *as; 4255 struct hdac_widget *w; 4256 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4257 4258 /* XXX This is redundant */ 4259 max = 0; 4260 for (j = 0; j < 16; j++) { 4261 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4262 w = hdac_widget_get(devinfo, i); 4263 if (w == NULL || w->enable == 0) 4264 continue; 4265 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4266 continue; 4267 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4268 != j) 4269 continue; 4270 max++; 4271 if (j != 15) /* There could be many 1-pin assocs #15 */ 4272 break; 4273 } 4274 } 4275 4276 devinfo->function.audio.ascnt = max; 4277 4278 if (max < 1) 4279 return; 4280 4281 as = (struct hdac_audio_as *)malloc( 4282 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4283 4284 if (as == NULL) { 4285 /* Blekh! */ 4286 device_printf(sc->dev, "unable to allocate assocs!\n"); 4287 devinfo->function.audio.ascnt = 0; 4288 return; 4289 } 4290 4291 for (i = 0; i < max; i++) { 4292 as[i].hpredir = -1; 4293 as[i].chan = -1; 4294 } 4295 4296 /* Scan associations skipping as=0. */ 4297 cnt = 0; 4298 for (j = 1; j < 16; j++) { 4299 first = 16; 4300 hpredir = 0; 4301 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4302 w = hdac_widget_get(devinfo, i); 4303 if (w == NULL || w->enable == 0) 4304 continue; 4305 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4306 continue; 4307 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4308 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4309 if (assoc != j) { 4310 continue; 4311 } 4312 KASSERT(cnt < max, 4313 ("%s: Associations owerflow (%d of %d)", 4314 __func__, cnt, max)); 4315 type = w->wclass.pin.config & 4316 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4317 /* Get pin direction. */ 4318 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4319 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4320 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4321 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4322 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4323 dir = HDA_CTL_OUT; 4324 else 4325 dir = HDA_CTL_IN; 4326 /* If this is a first pin - create new association. */ 4327 if (as[cnt].pincnt == 0) { 4328 as[cnt].enable = 1; 4329 as[cnt].index = j; 4330 as[cnt].dir = dir; 4331 } 4332 if (seq < first) 4333 first = seq; 4334 /* Check association correctness. */ 4335 if (as[cnt].pins[seq] != 0) { 4336 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4337 "in association %d! Disabling association.\n", 4338 __func__, seq, w->nid, j); 4339 as[cnt].enable = 0; 4340 } 4341 if (dir != as[cnt].dir) { 4342 device_printf(sc->dev, "%s: Pin %d has wrong " 4343 "direction for association %d! Disabling " 4344 "association.\n", 4345 __func__, w->nid, j); 4346 as[cnt].enable = 0; 4347 } 4348 /* Headphones with seq=15 may mean redirection. */ 4349 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4350 seq == 15) 4351 hpredir = 1; 4352 as[cnt].pins[seq] = w->nid; 4353 as[cnt].pincnt++; 4354 /* Association 15 is a multiple unassociated pins. */ 4355 if (j == 15) 4356 cnt++; 4357 } 4358 if (j != 15 && as[cnt].pincnt > 0) { 4359 if (hpredir && as[cnt].pincnt > 1) 4360 as[cnt].hpredir = first; 4361 cnt++; 4362 } 4363 } 4364 HDA_BOOTVERBOSE( 4365 device_printf(sc->dev, 4366 "%d associations found:\n", max); 4367 for (i = 0; i < max; i++) { 4368 device_printf(sc->dev, 4369 "Association %d (%d) %s%s:\n", 4370 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4371 as[i].enable?"":" (disabled)"); 4372 for (j = 0; j < 16; j++) { 4373 if (as[i].pins[j] == 0) 4374 continue; 4375 device_printf(sc->dev, 4376 " Pin nid=%d seq=%d\n", 4377 as[i].pins[j], j); 4378 } 4379 } 4380 ); 4381 4382 devinfo->function.audio.as = as; 4383} 4384 4385static const struct { 4386 uint32_t model; 4387 uint32_t id; 4388 uint32_t set, unset; 4389} hdac_quirks[] = { 4390 /* 4391 * XXX Force stereo quirk. Monoural recording / playback 4392 * on few codecs (especially ALC880) seems broken or 4393 * perhaps unsupported. 4394 */ 4395 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4396 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4397 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4398 HDA_QUIRK_GPIO0, 0 }, 4399 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4400 HDA_QUIRK_GPIO0, 0 }, 4401 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4402 HDA_QUIRK_GPIO0, 0 }, 4403 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4404 HDA_QUIRK_GPIO0, 0 }, 4405 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4406 HDA_QUIRK_GPIO0, 0 }, 4407 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4408 HDA_QUIRK_GPIO0, 0 }, 4409 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4410 HDA_QUIRK_EAPDINV, 0 }, 4411 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4412 HDA_QUIRK_EAPDINV, 0 }, 4413 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4414 HDA_QUIRK_OVREF, 0 }, 4415 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4416 HDA_QUIRK_OVREF, 0 }, 4417 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4418 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4419 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4420 HDA_QUIRK_GPIO1, 0 }, 4421 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4422 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4423 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4424 HDA_QUIRK_EAPDINV, 0 }, 4425 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4426 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4427 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4428 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4429 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4430 HDA_QUIRK_GPIO0, 0 }, 4431 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4432 HDA_QUIRK_GPIO2, 0 }, 4433 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4434 HDA_QUIRK_GPIO0, 0 }, 4435 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4436 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4437 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4438 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4439 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4440 0, HDA_QUIRK_FORCESTEREO } 4441}; 4442#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4443 4444static void 4445hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4446{ 4447 struct hdac_widget *w; 4448 uint32_t id, subvendor; 4449 int i; 4450 4451 id = hdac_codec_id(devinfo->codec); 4452 subvendor = devinfo->codec->sc->pci_subvendor; 4453 4454 /* 4455 * Quirks 4456 */ 4457 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4458 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4459 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4460 continue; 4461 if (hdac_quirks[i].set != 0) 4462 devinfo->function.audio.quirks |= 4463 hdac_quirks[i].set; 4464 if (hdac_quirks[i].unset != 0) 4465 devinfo->function.audio.quirks &= 4466 ~(hdac_quirks[i].unset); 4467 } 4468 4469 switch (id) { 4470 case HDA_CODEC_ALC883: 4471 /* 4472 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4473 * Clear vref cap for jack connectivity. 4474 */ 4475 w = hdac_widget_get(devinfo, 24); 4476 if (w != NULL && w->enable != 0 && w->type == 4477 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4478 (w->wclass.pin.config & 4479 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4480 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4481 w->wclass.pin.cap &= ~( 4482 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4483 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4484 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4485 w = hdac_widget_get(devinfo, 25); 4486 if (w != NULL && w->enable != 0 && w->type == 4487 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4488 (w->wclass.pin.config & 4489 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4490 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4491 w->wclass.pin.cap &= ~( 4492 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4493 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4494 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4495 /* 4496 * nid: 26 = Line-in, leave it alone. 4497 */ 4498 break; 4499 case HDA_CODEC_AD1986A: 4500 if (subvendor == ASUS_A8X_SUBVENDOR) { 4501 /* 4502 * This is just plain ridiculous.. There 4503 * are several A8 series that share the same 4504 * pci id but works differently (EAPD). 4505 */ 4506 w = hdac_widget_get(devinfo, 26); 4507 if (w != NULL && w->type == 4508 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4509 (w->wclass.pin.config & 4510 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4511 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4512 devinfo->function.audio.quirks &= 4513 ~HDA_QUIRK_EAPDINV; 4514 } 4515 break; 4516 case HDA_CODEC_AD1981HD: 4517 /* 4518 * This codec has very unusual design with several 4519 * points inappropriate for the present parser. 4520 */ 4521 /* Disable recording from mono playback mix. */ 4522 w = hdac_widget_get(devinfo, 21); 4523 if (w != NULL) 4524 w->connsenable[3] = 0; 4525 /* Disable rear to front mic mixer, use separately. */ 4526 w = hdac_widget_get(devinfo, 31); 4527 if (w != NULL) 4528 w->enable = 0; 4529 /* Disable playback mixer, use direct bypass. */ 4530 w = hdac_widget_get(devinfo, 14); 4531 if (w != NULL) 4532 w->enable = 0; 4533 break; 4534 } 4535} 4536 4537/* 4538 * Trace path from DAC to pin. 4539 */ 4540static nid_t 4541hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4542 int dupseq, int min, int only, int depth) 4543{ 4544 struct hdac_widget *w; 4545 int i, im = -1; 4546 nid_t m = 0, ret; 4547 4548 if (depth > HDA_PARSE_MAXDEPTH) 4549 return (0); 4550 w = hdac_widget_get(devinfo, nid); 4551 if (w == NULL || w->enable == 0) 4552 return (0); 4553 HDA_BOOTHVERBOSE( 4554 if (!only) { 4555 device_printf(devinfo->codec->sc->dev, 4556 " %*stracing via nid %d\n", 4557 depth + 1, "", w->nid); 4558 } 4559 ); 4560 /* Use only unused widgets */ 4561 if (w->bindas >= 0 && w->bindas != as) { 4562 HDA_BOOTHVERBOSE( 4563 if (!only) { 4564 device_printf(devinfo->codec->sc->dev, 4565 " %*snid %d busy by association %d\n", 4566 depth + 1, "", w->nid, w->bindas); 4567 } 4568 ); 4569 return (0); 4570 } 4571 if (dupseq < 0) { 4572 if (w->bindseqmask != 0) { 4573 HDA_BOOTHVERBOSE( 4574 if (!only) { 4575 device_printf(devinfo->codec->sc->dev, 4576 " %*snid %d busy by seqmask %x\n", 4577 depth + 1, "", w->nid, w->bindseqmask); 4578 } 4579 ); 4580 return (0); 4581 } 4582 } else { 4583 /* If this is headphones - allow duplicate first pin. */ 4584 if (w->bindseqmask != 0 && 4585 (w->bindseqmask & (1 << dupseq)) == 0) { 4586 HDA_BOOTHVERBOSE( 4587 device_printf(devinfo->codec->sc->dev, 4588 " %*snid %d busy by seqmask %x\n", 4589 depth + 1, "", w->nid, w->bindseqmask); 4590 ); 4591 return (0); 4592 } 4593 } 4594 4595 switch (w->type) { 4596 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4597 /* Do not traverse input. AD1988 has digital monitor 4598 for which we are not ready. */ 4599 break; 4600 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4601 /* If we are tracing HP take only dac of first pin. */ 4602 if ((only == 0 || only == w->nid) && 4603 (w->nid >= min) && (dupseq < 0 || w->nid == 4604 devinfo->function.audio.as[as].dacs[dupseq])) 4605 m = w->nid; 4606 break; 4607 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4608 if (depth > 0) 4609 break; 4610 /* Fall */ 4611 default: 4612 /* Find reachable DACs with smallest nid respecting constraints. */ 4613 for (i = 0; i < w->nconns; i++) { 4614 if (w->connsenable[i] == 0) 4615 continue; 4616 if (w->selconn != -1 && w->selconn != i) 4617 continue; 4618 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4619 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4620 if (m == 0 || ret < m) { 4621 m = ret; 4622 im = i; 4623 } 4624 if (only || dupseq >= 0) 4625 break; 4626 } 4627 } 4628 if (m && only && ((w->nconns > 1 && 4629 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4630 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4631 w->selconn = im; 4632 break; 4633 } 4634 if (m && only) { 4635 w->bindas = as; 4636 w->bindseqmask |= (1 << seq); 4637 } 4638 HDA_BOOTHVERBOSE( 4639 if (!only) { 4640 device_printf(devinfo->codec->sc->dev, 4641 " %*snid %d returned %d\n", 4642 depth + 1, "", w->nid, m); 4643 } 4644 ); 4645 return (m); 4646} 4647 4648/* 4649 * Trace path from widget to ADC. 4650 */ 4651static nid_t 4652hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4653 int only, int depth) 4654{ 4655 struct hdac_widget *w, *wc; 4656 int i, j; 4657 nid_t res = 0; 4658 4659 if (depth > HDA_PARSE_MAXDEPTH) 4660 return (0); 4661 w = hdac_widget_get(devinfo, nid); 4662 if (w == NULL || w->enable == 0) 4663 return (0); 4664 HDA_BOOTHVERBOSE( 4665 device_printf(devinfo->codec->sc->dev, 4666 " %*stracing via nid %d\n", 4667 depth + 1, "", w->nid); 4668 ); 4669 /* Use only unused widgets */ 4670 if (w->bindas >= 0 && w->bindas != as) { 4671 HDA_BOOTHVERBOSE( 4672 device_printf(devinfo->codec->sc->dev, 4673 " %*snid %d busy by association %d\n", 4674 depth + 1, "", w->nid, w->bindas); 4675 ); 4676 return (0); 4677 } 4678 4679 switch (w->type) { 4680 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4681 /* If we are tracing HP take only dac of first pin. */ 4682 if (only == w->nid) 4683 res = 1; 4684 break; 4685 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4686 if (depth > 0) 4687 break; 4688 /* Fall */ 4689 default: 4690 /* Try to find reachable ADCs with specified nid. */ 4691 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4692 wc = hdac_widget_get(devinfo, j); 4693 if (wc == NULL || wc->enable == 0) 4694 continue; 4695 for (i = 0; i < wc->nconns; i++) { 4696 if (wc->connsenable[i] == 0) 4697 continue; 4698 if (wc->conns[i] != nid) 4699 continue; 4700 if (hdac_audio_trace_adc(devinfo, as, seq, 4701 j, only, depth + 1) != 0) { 4702 res = 1; 4703 if (((wc->nconns > 1 && 4704 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4705 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4706 wc->selconn == -1) 4707 wc->selconn = i; 4708 } 4709 } 4710 } 4711 break; 4712 } 4713 if (res) { 4714 w->bindas = as; 4715 w->bindseqmask |= (1 << seq); 4716 } 4717 HDA_BOOTHVERBOSE( 4718 device_printf(devinfo->codec->sc->dev, 4719 " %*snid %d returned %d\n", 4720 depth + 1, "", w->nid, res); 4721 ); 4722 return (res); 4723} 4724 4725/* 4726 * Erase trace path of the specified association. 4727 */ 4728static void 4729hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4730{ 4731 struct hdac_widget *w; 4732 int i; 4733 4734 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4735 w = hdac_widget_get(devinfo, i); 4736 if (w == NULL || w->enable == 0) 4737 continue; 4738 if (w->bindas == as) { 4739 if (seq >= 0) { 4740 w->bindseqmask &= ~(1 << seq); 4741 if (w->bindseqmask == 0) { 4742 w->bindas = -1; 4743 w->selconn = -1; 4744 } 4745 } else { 4746 w->bindas = -1; 4747 w->bindseqmask = 0; 4748 w->selconn = -1; 4749 } 4750 } 4751 } 4752} 4753 4754/* 4755 * Trace association path from DAC to output 4756 */ 4757static int 4758hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4759{ 4760 struct hdac_audio_as *ases = devinfo->function.audio.as; 4761 int i, hpredir; 4762 nid_t min, res; 4763 4764 /* Find next pin */ 4765 for (i = seq; ases[as].pins[i] == 0 && i < 16; i++) 4766 ; 4767 /* Check if there is no any left. If so - we succeded. */ 4768 if (i == 16) 4769 return (1); 4770 4771 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4772 min = 0; 4773 res = 0; 4774 do { 4775 HDA_BOOTHVERBOSE( 4776 device_printf(devinfo->codec->sc->dev, 4777 " Tracing pin %d with min nid %d", 4778 ases[as].pins[i], min); 4779 if (hpredir >= 0) 4780 printf(" and hpredir %d", hpredir); 4781 printf("\n"); 4782 ); 4783 /* Trace this pin taking min nid into account. */ 4784 res = hdac_audio_trace_dac(devinfo, as, i, 4785 ases[as].pins[i], hpredir, min, 0, 0); 4786 if (res == 0) { 4787 /* If we failed - return to previous and redo it. */ 4788 HDA_BOOTVERBOSE( 4789 device_printf(devinfo->codec->sc->dev, 4790 " Unable to trace pin %d seq %d with min " 4791 "nid %d", 4792 ases[as].pins[i], i, min); 4793 if (hpredir >= 0) 4794 printf(" and hpredir %d", hpredir); 4795 printf("\n"); 4796 ); 4797 return (0); 4798 } 4799 HDA_BOOTVERBOSE( 4800 device_printf(devinfo->codec->sc->dev, 4801 " Pin %d traced to DAC %d", 4802 ases[as].pins[i], res); 4803 if (hpredir >= 0) 4804 printf(" and hpredir %d", hpredir); 4805 if (ases[as].fakeredir) 4806 printf(" with fake redirection"); 4807 printf("\n"); 4808 ); 4809 /* Trace again to mark the path */ 4810 hdac_audio_trace_dac(devinfo, as, i, 4811 ases[as].pins[i], hpredir, min, res, 0); 4812 ases[as].dacs[i] = res; 4813 /* We succeded, so call next. */ 4814 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4815 return (1); 4816 /* If next failed, we should retry with next min */ 4817 hdac_audio_undo_trace(devinfo, as, i); 4818 ases[as].dacs[i] = 0; 4819 min = res + 1; 4820 } while (1); 4821} 4822 4823/* 4824 * Trace association path from input to ADC 4825 */ 4826static int 4827hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4828{ 4829 struct hdac_audio_as *ases = devinfo->function.audio.as; 4830 struct hdac_widget *w; 4831 int i, j, k; 4832 4833 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4834 w = hdac_widget_get(devinfo, j); 4835 if (w == NULL || w->enable == 0) 4836 continue; 4837 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4838 continue; 4839 if (w->bindas >= 0 && w->bindas != as) 4840 continue; 4841 4842 /* Find next pin */ 4843 for (i = 0; i < 16; i++) { 4844 if (ases[as].pins[i] == 0) 4845 continue; 4846 4847 HDA_BOOTHVERBOSE( 4848 device_printf(devinfo->codec->sc->dev, 4849 " Tracing pin %d to ADC %d\n", 4850 ases[as].pins[i], j); 4851 ); 4852 /* Trace this pin taking goal into account. */ 4853 if (hdac_audio_trace_adc(devinfo, as, i, 4854 ases[as].pins[i], j, 0) == 0) { 4855 /* If we failed - return to previous and redo it. */ 4856 HDA_BOOTVERBOSE( 4857 device_printf(devinfo->codec->sc->dev, 4858 " Unable to trace pin %d to ADC %d, undo traces\n", 4859 ases[as].pins[i], j); 4860 ); 4861 hdac_audio_undo_trace(devinfo, as, -1); 4862 for (k = 0; k < 16; k++) 4863 ases[as].dacs[k] = 0; 4864 break; 4865 } 4866 HDA_BOOTVERBOSE( 4867 device_printf(devinfo->codec->sc->dev, 4868 " Pin %d traced to ADC %d\n", 4869 ases[as].pins[i], j); 4870 ); 4871 ases[as].dacs[i] = j; 4872 } 4873 if (i == 16) 4874 return (1); 4875 } 4876 return (0); 4877} 4878 4879/* 4880 * Trace input monitor path from mixer to output association. 4881 */ 4882static int 4883hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4884{ 4885 struct hdac_audio_as *ases = devinfo->function.audio.as; 4886 struct hdac_widget *w, *wc; 4887 int i, j; 4888 nid_t res = 0; 4889 4890 if (depth > HDA_PARSE_MAXDEPTH) 4891 return (0); 4892 w = hdac_widget_get(devinfo, nid); 4893 if (w == NULL || w->enable == 0) 4894 return (0); 4895 HDA_BOOTHVERBOSE( 4896 device_printf(devinfo->codec->sc->dev, 4897 " %*stracing via nid %d\n", 4898 depth + 1, "", w->nid); 4899 ); 4900 /* Use only unused widgets */ 4901 if (depth > 0 && w->bindas != -1) { 4902 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4903 HDA_BOOTHVERBOSE( 4904 device_printf(devinfo->codec->sc->dev, 4905 " %*snid %d found output association %d\n", 4906 depth + 1, "", w->nid, w->bindas); 4907 ); 4908 return (1); 4909 } else { 4910 HDA_BOOTHVERBOSE( 4911 device_printf(devinfo->codec->sc->dev, 4912 " %*snid %d busy by input association %d\n", 4913 depth + 1, "", w->nid, w->bindas); 4914 ); 4915 return (0); 4916 } 4917 } 4918 4919 switch (w->type) { 4920 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4921 /* Do not traverse input. AD1988 has digital monitor 4922 for which we are not ready. */ 4923 break; 4924 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4925 if (depth > 0) 4926 break; 4927 /* Fall */ 4928 default: 4929 /* Try to find reachable ADCs with specified nid. */ 4930 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4931 wc = hdac_widget_get(devinfo, j); 4932 if (wc == NULL || wc->enable == 0) 4933 continue; 4934 for (i = 0; i < wc->nconns; i++) { 4935 if (wc->connsenable[i] == 0) 4936 continue; 4937 if (wc->conns[i] != nid) 4938 continue; 4939 if (hdac_audio_trace_to_out(devinfo, 4940 j, depth + 1) != 0) { 4941 res = 1; 4942 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4943 wc->selconn == -1) 4944 wc->selconn = i; 4945 } 4946 } 4947 } 4948 break; 4949 } 4950 if (res) 4951 w->bindas = -2; 4952 4953 HDA_BOOTHVERBOSE( 4954 device_printf(devinfo->codec->sc->dev, 4955 " %*snid %d returned %d\n", 4956 depth + 1, "", w->nid, res); 4957 ); 4958 return (res); 4959} 4960 4961/* 4962 * Trace extra associations (beeper, monitor) 4963 */ 4964static void 4965hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4966{ 4967 struct hdac_audio_as *as = devinfo->function.audio.as; 4968 struct hdac_widget *w; 4969 int j; 4970 4971 /* Input monitor */ 4972 /* Find mixer associated with input, but supplying signal 4973 for output associations. Hope it will be input monitor. */ 4974 HDA_BOOTVERBOSE( 4975 device_printf(devinfo->codec->sc->dev, 4976 "Tracing input monitor\n"); 4977 ); 4978 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4979 w = hdac_widget_get(devinfo, j); 4980 if (w == NULL || w->enable == 0) 4981 continue; 4982 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4983 continue; 4984 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 4985 continue; 4986 HDA_BOOTVERBOSE( 4987 device_printf(devinfo->codec->sc->dev, 4988 " Tracing nid %d to out\n", 4989 j); 4990 ); 4991 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 4992 HDA_BOOTVERBOSE( 4993 device_printf(devinfo->codec->sc->dev, 4994 " nid %d is input monitor\n", 4995 w->nid); 4996 ); 4997 w->pflags |= HDA_ADC_MONITOR; 4998 w->ossdev = SOUND_MIXER_IMIX; 4999 } 5000 } 5001 5002 /* Beeper */ 5003 HDA_BOOTVERBOSE( 5004 device_printf(devinfo->codec->sc->dev, 5005 "Tracing beeper\n"); 5006 ); 5007 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5008 w = hdac_widget_get(devinfo, j); 5009 if (w == NULL || w->enable == 0) 5010 continue; 5011 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5012 continue; 5013 HDA_BOOTHVERBOSE( 5014 device_printf(devinfo->codec->sc->dev, 5015 " Tracing nid %d to out\n", 5016 j); 5017 ); 5018 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5019 HDA_BOOTVERBOSE( 5020 device_printf(devinfo->codec->sc->dev, 5021 " nid %d traced to out\n", 5022 j); 5023 ); 5024 } 5025 w->bindas = -2; 5026 } 5027} 5028 5029/* 5030 * Bind assotiations to PCM channels 5031 */ 5032static void 5033hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5034{ 5035 struct hdac_softc *sc = devinfo->codec->sc; 5036 struct hdac_audio_as *as = devinfo->function.audio.as; 5037 int j, cnt = 0, free; 5038 5039 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5040 if (as[j].enable) 5041 cnt++; 5042 } 5043 if (sc->num_chans == 0) { 5044 sc->chans = (struct hdac_chan *)malloc( 5045 sizeof(struct hdac_chan) * cnt, 5046 M_HDAC, M_ZERO | M_NOWAIT); 5047 if (sc->chans == NULL) { 5048 device_printf(devinfo->codec->sc->dev, 5049 "Channels memory allocation failed!\n"); 5050 return; 5051 } 5052 } else { 5053 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5054 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5055 M_HDAC, M_ZERO | M_NOWAIT); 5056 if (sc->chans == NULL) { 5057 sc->num_chans = 0; 5058 device_printf(devinfo->codec->sc->dev, 5059 "Channels memory allocation failed!\n"); 5060 return; 5061 } 5062 } 5063 free = sc->num_chans; 5064 sc->num_chans += cnt; 5065 5066 for (j = free; j < free + cnt; j++) { 5067 devinfo->codec->sc->chans[j].devinfo = devinfo; 5068 devinfo->codec->sc->chans[j].as = -1; 5069 } 5070 5071 /* Assign associations in order of their numbers, */ 5072 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5073 if (as[j].enable == 0) 5074 continue; 5075 5076 as[j].chan = free; 5077 devinfo->codec->sc->chans[free].as = j; 5078 if (as[j].dir == HDA_CTL_IN) { 5079 devinfo->codec->sc->chans[free].dir = PCMDIR_REC; 5080 devinfo->function.audio.reccnt++; 5081 } else { 5082 devinfo->codec->sc->chans[free].dir = PCMDIR_PLAY; 5083 devinfo->function.audio.playcnt++; 5084 } 5085 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5086 free++; 5087 } 5088} 5089 5090static void 5091hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5092{ 5093 struct hdac_widget *w; 5094 int i; 5095 5096 /* Disable power and volume widgets. */ 5097 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5098 w = hdac_widget_get(devinfo, i); 5099 if (w == NULL || w->enable == 0) 5100 continue; 5101 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5102 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5103 w->enable = 0; 5104 HDA_BOOTHVERBOSE( 5105 device_printf(devinfo->codec->sc->dev, 5106 " Disabling nid %d due to it's" 5107 " non-audio type.\n", 5108 w->nid); 5109 ); 5110 } 5111 } 5112} 5113 5114static void 5115hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5116{ 5117 struct hdac_widget *w, *cw; 5118 struct hdac_audio_ctl *ctl; 5119 int done, found, i, j, k; 5120 5121 /* Disable useless pins. */ 5122 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5123 w = hdac_widget_get(devinfo, i); 5124 if (w == NULL || w->enable == 0) 5125 continue; 5126 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5127 (w->wclass.pin.config & 5128 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5129 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5130 w->enable = 0; 5131 HDA_BOOTHVERBOSE( 5132 device_printf(devinfo->codec->sc->dev, 5133 " Disabling pin nid %d due" 5134 " to None connectivity.\n", 5135 w->nid); 5136 ); 5137 } 5138 } 5139 do { 5140 done = 1; 5141 /* Disable and mute controls for disabled widgets. */ 5142 i = 0; 5143 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5144 if (ctl->enable == 0) 5145 continue; 5146 if (ctl->widget->enable == 0 || 5147 (ctl->childwidget != NULL && 5148 ctl->childwidget->enable == 0)) { 5149 ctl->forcemute = 1; 5150 ctl->muted = HDA_AMP_MUTE_ALL; 5151 ctl->left = 0; 5152 ctl->right = 0; 5153 ctl->enable = 0; 5154 if (ctl->ndir == HDA_CTL_IN) 5155 ctl->widget->connsenable[ctl->index] = 0; 5156 done = 0; 5157 HDA_BOOTHVERBOSE( 5158 device_printf(devinfo->codec->sc->dev, 5159 " Disabling ctl %d nid %d cnid %d due" 5160 " to disabled widget.\n", i, 5161 ctl->widget->nid, 5162 (ctl->childwidget != NULL)? 5163 ctl->childwidget->nid:-1); 5164 ); 5165 } 5166 } 5167 /* Disable useless widgets. */ 5168 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5169 w = hdac_widget_get(devinfo, i); 5170 if (w == NULL || w->enable == 0) 5171 continue; 5172 /* Disable inputs with disabled child widgets. */ 5173 for (j = 0; j < w->nconns; j++) { 5174 if (w->connsenable[j]) { 5175 cw = hdac_widget_get(devinfo, w->conns[j]); 5176 if (cw == NULL || cw->enable == 0) { 5177 w->connsenable[j] = 0; 5178 HDA_BOOTHVERBOSE( 5179 device_printf(devinfo->codec->sc->dev, 5180 " Disabling nid %d connection %d due" 5181 " to disabled child widget.\n", 5182 i, j); 5183 ); 5184 } 5185 } 5186 } 5187 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5188 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5189 continue; 5190 /* Disable mixers and selectors without inputs. */ 5191 found = 0; 5192 for (j = 0; j < w->nconns; j++) { 5193 if (w->connsenable[j]) { 5194 found = 1; 5195 break; 5196 } 5197 } 5198 if (found == 0) { 5199 w->enable = 0; 5200 done = 0; 5201 HDA_BOOTHVERBOSE( 5202 device_printf(devinfo->codec->sc->dev, 5203 " Disabling nid %d due to all it's" 5204 " inputs disabled.\n", w->nid); 5205 ); 5206 } 5207 /* Disable nodes without consumers. */ 5208 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5209 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5210 continue; 5211 found = 0; 5212 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5213 cw = hdac_widget_get(devinfo, k); 5214 if (cw == NULL || cw->enable == 0) 5215 continue; 5216 for (j = 0; j < cw->nconns; j++) { 5217 if (cw->connsenable[j] && cw->conns[j] == i) { 5218 found = 1; 5219 break; 5220 } 5221 } 5222 } 5223 if (found == 0) { 5224 w->enable = 0; 5225 done = 0; 5226 HDA_BOOTHVERBOSE( 5227 device_printf(devinfo->codec->sc->dev, 5228 " Disabling nid %d due to all it's" 5229 " consumers disabled.\n", w->nid); 5230 ); 5231 } 5232 } 5233 } while (done == 0); 5234 5235} 5236 5237static void 5238hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5239{ 5240 struct hdac_audio_as *as = devinfo->function.audio.as; 5241 struct hdac_widget *w, *cw; 5242 struct hdac_audio_ctl *ctl; 5243 int i, j, k; 5244 5245 /* Disable unassosiated widgets. */ 5246 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5247 w = hdac_widget_get(devinfo, i); 5248 if (w == NULL || w->enable == 0) 5249 continue; 5250 if (w->bindas == -1) { 5251 w->enable = 0; 5252 HDA_BOOTHVERBOSE( 5253 device_printf(devinfo->codec->sc->dev, 5254 " Disabling unassociated nid %d.\n", 5255 w->nid); 5256 ); 5257 } 5258 } 5259 /* Disable input connections on input pin and 5260 * output on output. */ 5261 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5262 w = hdac_widget_get(devinfo, i); 5263 if (w == NULL || w->enable == 0) 5264 continue; 5265 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5266 continue; 5267 if (w->bindas < 0) 5268 continue; 5269 if (as[w->bindas].dir == HDA_CTL_IN) { 5270 for (j = 0; j < w->nconns; j++) { 5271 if (w->connsenable[j] == 0) 5272 continue; 5273 w->connsenable[j] = 0; 5274 HDA_BOOTHVERBOSE( 5275 device_printf(devinfo->codec->sc->dev, 5276 " Disabling connection to input pin " 5277 "nid %d conn %d.\n", 5278 i, j); 5279 ); 5280 } 5281 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5282 HDA_CTL_IN, -1, 1); 5283 if (ctl && ctl->enable) { 5284 ctl->forcemute = 1; 5285 ctl->muted = HDA_AMP_MUTE_ALL; 5286 ctl->left = 0; 5287 ctl->right = 0; 5288 ctl->enable = 0; 5289 } 5290 } else { 5291 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5292 HDA_CTL_OUT, -1, 1); 5293 if (ctl && ctl->enable) { 5294 ctl->forcemute = 1; 5295 ctl->muted = HDA_AMP_MUTE_ALL; 5296 ctl->left = 0; 5297 ctl->right = 0; 5298 ctl->enable = 0; 5299 } 5300 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5301 cw = hdac_widget_get(devinfo, k); 5302 if (cw == NULL || cw->enable == 0) 5303 continue; 5304 for (j = 0; j < cw->nconns; j++) { 5305 if (cw->connsenable[j] && cw->conns[j] == i) { 5306 cw->connsenable[j] = 0; 5307 HDA_BOOTHVERBOSE( 5308 device_printf(devinfo->codec->sc->dev, 5309 " Disabling connection from output pin " 5310 "nid %d conn %d cnid %d.\n", 5311 k, j, i); 5312 ); 5313 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5314 cw->nconns > 1) 5315 continue; 5316 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5317 HDA_CTL_IN, j, 1); 5318 if (ctl && ctl->enable) { 5319 ctl->forcemute = 1; 5320 ctl->muted = HDA_AMP_MUTE_ALL; 5321 ctl->left = 0; 5322 ctl->right = 0; 5323 ctl->enable = 0; 5324 } 5325 } 5326 } 5327 } 5328 } 5329 } 5330} 5331 5332static void 5333hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5334{ 5335 struct hdac_audio_as *as = devinfo->function.audio.as; 5336 struct hdac_widget *w; 5337 int i, j; 5338 5339 /* On playback path we can safely disable all unseleted inputs. */ 5340 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5341 w = hdac_widget_get(devinfo, i); 5342 if (w == NULL || w->enable == 0) 5343 continue; 5344 if (w->nconns <= 1) 5345 continue; 5346 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5347 continue; 5348 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5349 continue; 5350 for (j = 0; j < w->nconns; j++) { 5351 if (w->connsenable[j] == 0) 5352 continue; 5353 if (w->selconn < 0 || w->selconn == j) 5354 continue; 5355 w->connsenable[j] = 0; 5356 HDA_BOOTHVERBOSE( 5357 device_printf(devinfo->codec->sc->dev, 5358 " Disabling unselected connection " 5359 "nid %d conn %d.\n", 5360 i, j); 5361 ); 5362 } 5363 } 5364} 5365 5366static void 5367hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5368{ 5369 struct hdac_widget *w, *cw; 5370 struct hdac_audio_ctl *ctl; 5371 int i, j; 5372 5373 /* Disable crossassociatement connections. */ 5374 /* ... using selectors */ 5375 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5376 w = hdac_widget_get(devinfo, i); 5377 if (w == NULL || w->enable == 0) 5378 continue; 5379 if (w->nconns <= 1) 5380 continue; 5381 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5382 continue; 5383 if (w->bindas == -2) 5384 continue; 5385 for (j = 0; j < w->nconns; j++) { 5386 if (w->connsenable[j] == 0) 5387 continue; 5388 cw = hdac_widget_get(devinfo, w->conns[j]); 5389 if (cw == NULL || w->enable == 0) 5390 continue; 5391 if (w->bindas == cw->bindas || cw->bindas == -2) 5392 continue; 5393 w->connsenable[j] = 0; 5394 HDA_BOOTHVERBOSE( 5395 device_printf(devinfo->codec->sc->dev, 5396 " Disabling crossassociatement connection " 5397 "nid %d conn %d cnid %d.\n", 5398 i, j, cw->nid); 5399 ); 5400 } 5401 } 5402 /* ... using controls */ 5403 i = 0; 5404 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5405 if (ctl->enable == 0 || ctl->childwidget == NULL) 5406 continue; 5407 if (ctl->widget->bindas == -2 || 5408 ctl->childwidget->bindas == -2) 5409 continue; 5410 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5411 ctl->forcemute = 1; 5412 ctl->muted = HDA_AMP_MUTE_ALL; 5413 ctl->left = 0; 5414 ctl->right = 0; 5415 ctl->enable = 0; 5416 if (ctl->ndir == HDA_CTL_IN) 5417 ctl->widget->connsenable[ctl->index] = 0; 5418 HDA_BOOTHVERBOSE( 5419 device_printf(devinfo->codec->sc->dev, 5420 " Disabling crossassociatement connection " 5421 "ctl %d nid %d cnid %d.\n", i, 5422 ctl->widget->nid, 5423 ctl->childwidget->nid); 5424 ); 5425 } 5426 } 5427 5428} 5429 5430#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5431 5432/* 5433 * Find controls to control amplification for source. 5434 */ 5435static int 5436hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5437 int ossdev, int ctlable, int depth, int need) 5438{ 5439 struct hdac_widget *w, *wc; 5440 struct hdac_audio_ctl *ctl; 5441 int i, j, conns = 0, rneed; 5442 5443 if (depth > HDA_PARSE_MAXDEPTH) 5444 return (need); 5445 5446 w = hdac_widget_get(devinfo, nid); 5447 if (w == NULL || w->enable == 0) 5448 return (need); 5449 5450 /* Count number of active inputs. */ 5451 if (depth > 0) { 5452 for (j = 0; j < w->nconns; j++) { 5453 if (w->connsenable[j]) 5454 conns++; 5455 } 5456 } 5457 5458 /* If this is not a first step - use input mixer. 5459 Pins have common input ctl so care must be taken. */ 5460 if (depth > 0 && ctlable && (conns == 1 || 5461 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5462 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5463 index, 1); 5464 if (ctl) { 5465 if (HDA_CTL_GIVE(ctl) & need) 5466 ctl->ossmask |= (1 << ossdev); 5467 else 5468 ctl->possmask |= (1 << ossdev); 5469 need &= ~HDA_CTL_GIVE(ctl); 5470 } 5471 } 5472 5473 /* If widget has own ossdev - not traverse it. 5474 It will be traversed on it's own. */ 5475 if (w->ossdev >= 0 && depth > 0) 5476 return (need); 5477 5478 /* We must not traverse pin */ 5479 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5480 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5481 depth > 0) 5482 return (need); 5483 5484 /* record that this widget exports such signal, */ 5485 w->ossmask |= (1 << ossdev); 5486 5487 /* If signals mixed, we can't assign controls farther. 5488 * Ignore this on depth zero. Caller must knows why. 5489 * Ignore this for static selectors if this input selected. 5490 */ 5491 if (conns > 1) 5492 ctlable = 0; 5493 5494 if (ctlable) { 5495 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5496 if (ctl) { 5497 if (HDA_CTL_GIVE(ctl) & need) 5498 ctl->ossmask |= (1 << ossdev); 5499 else 5500 ctl->possmask |= (1 << ossdev); 5501 need &= ~HDA_CTL_GIVE(ctl); 5502 } 5503 } 5504 5505 rneed = 0; 5506 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5507 wc = hdac_widget_get(devinfo, i); 5508 if (wc == NULL || wc->enable == 0) 5509 continue; 5510 for (j = 0; j < wc->nconns; j++) { 5511 if (wc->connsenable[j] && wc->conns[j] == nid) { 5512 rneed |= hdac_audio_ctl_source_amp(devinfo, 5513 wc->nid, j, ossdev, ctlable, depth + 1, need); 5514 } 5515 } 5516 } 5517 rneed &= need; 5518 5519 return (rneed); 5520} 5521 5522/* 5523 * Find controls to control amplification for destination. 5524 */ 5525static void 5526hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5527 int ossdev, int depth, int need) 5528{ 5529 struct hdac_audio_as *as = devinfo->function.audio.as; 5530 struct hdac_widget *w, *wc; 5531 struct hdac_audio_ctl *ctl; 5532 int i, j, consumers; 5533 5534 if (depth > HDA_PARSE_MAXDEPTH) 5535 return; 5536 5537 w = hdac_widget_get(devinfo, nid); 5538 if (w == NULL || w->enable == 0) 5539 return; 5540 5541 if (depth > 0) { 5542 /* If this node produce output for several consumers, 5543 we can't touch it. */ 5544 consumers = 0; 5545 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5546 wc = hdac_widget_get(devinfo, i); 5547 if (wc == NULL || wc->enable == 0) 5548 continue; 5549 for (j = 0; j < wc->nconns; j++) { 5550 if (wc->connsenable[j] && wc->conns[j] == nid) 5551 consumers++; 5552 } 5553 } 5554 /* The only exception is if real HP redirection is configured 5555 and this is a duplication point. 5556 XXX: Actually exception is not completely correct. 5557 XXX: Duplication point check is not perfect. */ 5558 if ((consumers == 2 && (w->bindas < 0 || 5559 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5560 (w->bindseqmask & (1 << 15)) == 0)) || 5561 consumers > 2) 5562 return; 5563 5564 /* Else use it's output mixer. */ 5565 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5566 HDA_CTL_OUT, -1, 1); 5567 if (ctl) { 5568 if (HDA_CTL_GIVE(ctl) & need) 5569 ctl->ossmask |= (1 << ossdev); 5570 else 5571 ctl->possmask |= (1 << ossdev); 5572 need &= ~HDA_CTL_GIVE(ctl); 5573 } 5574 } 5575 5576 /* We must not traverse pin */ 5577 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5578 depth > 0) 5579 return; 5580 5581 for (i = 0; i < w->nconns; i++) { 5582 int tneed = need; 5583 if (w->connsenable[i] == 0) 5584 continue; 5585 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5586 HDA_CTL_IN, i, 1); 5587 if (ctl) { 5588 if (HDA_CTL_GIVE(ctl) & tneed) 5589 ctl->ossmask |= (1 << ossdev); 5590 else 5591 ctl->possmask |= (1 << ossdev); 5592 tneed &= ~HDA_CTL_GIVE(ctl); 5593 } 5594 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5595 depth + 1, tneed); 5596 } 5597} 5598 5599/* 5600 * Assign OSS names to sound sources 5601 */ 5602static void 5603hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5604{ 5605 struct hdac_audio_as *as = devinfo->function.audio.as; 5606 struct hdac_widget *w; 5607 int i, j; 5608 int type = -1, use, used = 0; 5609 static const int types[7][13] = { 5610 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5611 SOUND_MIXER_LINE3, -1 }, /* line */ 5612 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5613 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5614 { SOUND_MIXER_CD, -1 }, /* cd */ 5615 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5616 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5617 -1 }, /* digital */ 5618 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5619 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5620 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5621 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5622 -1 } /* others */ 5623 }; 5624 5625 /* Surely known names */ 5626 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5627 w = hdac_widget_get(devinfo, i); 5628 if (w == NULL || w->enable == 0) 5629 continue; 5630 if (w->bindas == -1) 5631 continue; 5632 use = -1; 5633 switch (w->type) { 5634 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5635 if (as[w->bindas].dir == HDA_CTL_OUT) 5636 break; 5637 type = -1; 5638 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5639 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5640 type = 0; 5641 break; 5642 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5643 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5644 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5645 break; 5646 type = 1; 5647 break; 5648 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5649 type = 3; 5650 break; 5651 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5652 type = 4; 5653 break; 5654 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5655 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5656 type = 5; 5657 break; 5658 } 5659 if (type == -1) 5660 break; 5661 j = 0; 5662 while (types[type][j] >= 0 && 5663 (used & (1 << types[type][j])) != 0) { 5664 j++; 5665 } 5666 if (types[type][j] >= 0) 5667 use = types[type][j]; 5668 break; 5669 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5670 use = SOUND_MIXER_PCM; 5671 break; 5672 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5673 use = SOUND_MIXER_SPEAKER; 5674 break; 5675 default: 5676 break; 5677 } 5678 if (use >= 0) { 5679 w->ossdev = use; 5680 used |= (1 << use); 5681 } 5682 } 5683 /* Semi-known names */ 5684 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5685 w = hdac_widget_get(devinfo, i); 5686 if (w == NULL || w->enable == 0) 5687 continue; 5688 if (w->ossdev >= 0) 5689 continue; 5690 if (w->bindas == -1) 5691 continue; 5692 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5693 continue; 5694 if (as[w->bindas].dir == HDA_CTL_OUT) 5695 continue; 5696 type = -1; 5697 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5698 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5699 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5700 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5701 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5702 type = 0; 5703 break; 5704 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5705 type = 2; 5706 break; 5707 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5708 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5709 type = 5; 5710 break; 5711 } 5712 if (type == -1) 5713 break; 5714 j = 0; 5715 while (types[type][j] >= 0 && 5716 (used & (1 << types[type][j])) != 0) { 5717 j++; 5718 } 5719 if (types[type][j] >= 0) { 5720 w->ossdev = types[type][j]; 5721 used |= (1 << types[type][j]); 5722 } 5723 } 5724 /* Others */ 5725 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5726 w = hdac_widget_get(devinfo, i); 5727 if (w == NULL || w->enable == 0) 5728 continue; 5729 if (w->ossdev >= 0) 5730 continue; 5731 if (w->bindas == -1) 5732 continue; 5733 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5734 continue; 5735 if (as[w->bindas].dir == HDA_CTL_OUT) 5736 continue; 5737 j = 0; 5738 while (types[6][j] >= 0 && 5739 (used & (1 << types[6][j])) != 0) { 5740 j++; 5741 } 5742 if (types[6][j] >= 0) { 5743 w->ossdev = types[6][j]; 5744 used |= (1 << types[6][j]); 5745 } 5746 } 5747} 5748 5749static void 5750hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5751{ 5752 struct hdac_audio_as *as = devinfo->function.audio.as; 5753 int j, res; 5754 5755 /* Trace all associations in order of their numbers, */ 5756 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5757 if (as[j].enable == 0) 5758 continue; 5759 HDA_BOOTVERBOSE( 5760 device_printf(devinfo->codec->sc->dev, 5761 "Tracing association %d (%d)\n", j, as[j].index); 5762 ); 5763 if (as[j].dir == HDA_CTL_OUT) { 5764retry: 5765 res = hdac_audio_trace_as_out(devinfo, j, 0); 5766 if (res == 0 && as[j].hpredir >= 0 && 5767 as[j].fakeredir == 0) { 5768 /* If codec can't do analog HP redirection 5769 try to make it using one more DAC. */ 5770 as[j].fakeredir = 1; 5771 goto retry; 5772 } 5773 } else { 5774 res = hdac_audio_trace_as_in(devinfo, j); 5775 } 5776 if (res) { 5777 HDA_BOOTVERBOSE( 5778 device_printf(devinfo->codec->sc->dev, 5779 "Association %d (%d) trace succeded\n", 5780 j, as[j].index); 5781 ); 5782 } else { 5783 HDA_BOOTVERBOSE( 5784 device_printf(devinfo->codec->sc->dev, 5785 "Association %d (%d) trace failed\n", 5786 j, as[j].index); 5787 ); 5788 as[j].enable = 0; 5789 } 5790 } 5791 5792 /* Trace mixer and beeper pseudo associations. */ 5793 hdac_audio_trace_as_extra(devinfo); 5794} 5795 5796static void 5797hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5798{ 5799 struct hdac_audio_as *as = devinfo->function.audio.as; 5800 struct hdac_audio_ctl *ctl; 5801 struct hdac_widget *w; 5802 int i; 5803 5804 /* Assign mixers to the tree. */ 5805 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5806 w = hdac_widget_get(devinfo, i); 5807 if (w == NULL || w->enable == 0) 5808 continue; 5809 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5810 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5811 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5812 as[w->bindas].dir == HDA_CTL_IN)) { 5813 if (w->ossdev < 0) 5814 continue; 5815 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5816 w->ossdev, 1, 0, 1); 5817 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5818 if (w->ossdev < 0) 5819 continue; 5820 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5821 w->ossdev, 1, 0, 1)) { 5822 /* If we are unable to control input monitor 5823 as source - try to control it as destination. */ 5824 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5825 w->ossdev, 0, 1); 5826 } 5827 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5828 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5829 SOUND_MIXER_RECLEV, 0, 1); 5830 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5831 as[w->bindas].dir == HDA_CTL_OUT) { 5832 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5833 SOUND_MIXER_VOLUME, 0, 1); 5834 } 5835 } 5836 /* Treat unrequired as possible. */ 5837 i = 0; 5838 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5839 if (ctl->ossmask == 0) 5840 ctl->ossmask = ctl->possmask; 5841 } 5842} 5843 5844static void 5845hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5846{ 5847 struct hdac_audio_as *as = devinfo->function.audio.as; 5848 struct hdac_widget *w; 5849 uint32_t pincap; 5850 int i; 5851 5852 for (i = 0; i < devinfo->nodecnt; i++) { 5853 w = &devinfo->widget[i]; 5854 if (w == NULL) 5855 continue; 5856 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5857 continue; 5858 5859 pincap = w->wclass.pin.cap; 5860 5861 /* Disable everything. */ 5862 w->wclass.pin.ctrl &= ~( 5863 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5864 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5865 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5866 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5867 5868 if (w->enable == 0 || 5869 w->bindas < 0 || as[w->bindas].enable == 0) { 5870 /* Pin is unused so left it disabled. */ 5871 continue; 5872 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5873 /* Input pin, configure for input. */ 5874 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5875 w->wclass.pin.ctrl |= 5876 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5877 5878 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5879 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5880 w->wclass.pin.ctrl |= 5881 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5882 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5883 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5884 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5885 w->wclass.pin.ctrl |= 5886 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5887 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5888 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5889 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5890 w->wclass.pin.ctrl |= 5891 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5892 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5893 } else { 5894 /* Output pin, configure for output. */ 5895 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5896 w->wclass.pin.ctrl |= 5897 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5898 5899 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5900 (w->wclass.pin.config & 5901 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5902 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5903 w->wclass.pin.ctrl |= 5904 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5905 5906 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5907 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5908 w->wclass.pin.ctrl |= 5909 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5910 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5911 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5912 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5913 w->wclass.pin.ctrl |= 5914 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5915 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5916 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5917 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5918 w->wclass.pin.ctrl |= 5919 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5920 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5921 } 5922 } 5923} 5924 5925static void 5926hdac_audio_commit(struct hdac_devinfo *devinfo) 5927{ 5928 struct hdac_softc *sc = devinfo->codec->sc; 5929 struct hdac_widget *w; 5930 nid_t cad; 5931 uint32_t gdata, gmask, gdir; 5932 int commitgpio, numgpio; 5933 int i; 5934 5935 cad = devinfo->codec->cad; 5936 5937 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5938 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5939 0x7e7, 0), cad); 5940 5941 gdata = 0; 5942 gmask = 0; 5943 gdir = 0; 5944 commitgpio = 0; 5945 5946 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5947 devinfo->function.audio.gpio); 5948 5949 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5950 commitgpio = (numgpio > 0) ? 1 : 0; 5951 else { 5952 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5953 if (!(devinfo->function.audio.quirks & 5954 (1 << i))) 5955 continue; 5956 if (commitgpio == 0) { 5957 commitgpio = 1; 5958 HDA_BOOTVERBOSE( 5959 gdata = hdac_command(sc, 5960 HDA_CMD_GET_GPIO_DATA(cad, 5961 devinfo->nid), cad); 5962 gmask = hdac_command(sc, 5963 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5964 devinfo->nid), cad); 5965 gdir = hdac_command(sc, 5966 HDA_CMD_GET_GPIO_DIRECTION(cad, 5967 devinfo->nid), cad); 5968 device_printf(sc->dev, 5969 "GPIO init: data=0x%08x " 5970 "mask=0x%08x dir=0x%08x\n", 5971 gdata, gmask, gdir); 5972 gdata = 0; 5973 gmask = 0; 5974 gdir = 0; 5975 ); 5976 } 5977 gdata |= 1 << i; 5978 gmask |= 1 << i; 5979 gdir |= 1 << i; 5980 } 5981 } 5982 5983 if (commitgpio != 0) { 5984 HDA_BOOTVERBOSE( 5985 device_printf(sc->dev, 5986 "GPIO commit: data=0x%08x mask=0x%08x " 5987 "dir=0x%08x\n", 5988 gdata, gmask, gdir); 5989 ); 5990 hdac_command(sc, 5991 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5992 gmask), cad); 5993 hdac_command(sc, 5994 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5995 gdir), cad); 5996 hdac_command(sc, 5997 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5998 gdata), cad); 5999 } 6000 6001 for (i = 0; i < devinfo->nodecnt; i++) { 6002 w = &devinfo->widget[i]; 6003 if (w == NULL) 6004 continue; 6005 if (w->selconn == -1) 6006 w->selconn = 0; 6007 if (w->nconns > 0) 6008 hdac_widget_connection_select(w, w->selconn); 6009 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6010 hdac_command(sc, 6011 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6012 w->wclass.pin.ctrl), cad); 6013 } 6014 if (w->param.eapdbtl != HDAC_INVALID) { 6015 uint32_t val; 6016 6017 val = w->param.eapdbtl; 6018 if (devinfo->function.audio.quirks & 6019 HDA_QUIRK_EAPDINV) 6020 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6021 hdac_command(sc, 6022 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6023 val), cad); 6024 6025 } 6026 DELAY(1000); 6027 } 6028} 6029 6030static void 6031hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6032{ 6033 struct hdac_audio_ctl *ctl; 6034 int i, z; 6035 6036 i = 0; 6037 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6038 if (ctl->enable == 0) { 6039 /* Mute disabled controls. */ 6040 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6041 continue; 6042 } 6043 /* Init controls to 0dB amplification. */ 6044 z = ctl->offset; 6045 if (z > ctl->step) 6046 z = ctl->step; 6047 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6048 } 6049} 6050 6051static void 6052hdac_powerup(struct hdac_devinfo *devinfo) 6053{ 6054 struct hdac_softc *sc = devinfo->codec->sc; 6055 nid_t cad = devinfo->codec->cad; 6056 int i; 6057 6058 hdac_command(sc, 6059 HDA_CMD_SET_POWER_STATE(cad, 6060 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6061 cad); 6062 DELAY(100); 6063 6064 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6065 hdac_command(sc, 6066 HDA_CMD_SET_POWER_STATE(cad, 6067 i, HDA_CMD_POWER_STATE_D0), 6068 cad); 6069 } 6070 DELAY(1000); 6071} 6072 6073static int 6074hdac_pcmchannel_setup(struct hdac_chan *ch) 6075{ 6076 struct hdac_devinfo *devinfo = ch->devinfo; 6077 struct hdac_audio_as *as = devinfo->function.audio.as; 6078 struct hdac_widget *w; 6079 uint32_t cap, fmtcap, pcmcap; 6080 int i, j, ret, max; 6081 6082 ch->caps = hdac_caps; 6083 ch->caps.fmtlist = ch->fmtlist; 6084 ch->bit16 = 1; 6085 ch->bit32 = 0; 6086 ch->pcmrates[0] = 48000; 6087 ch->pcmrates[1] = 0; 6088 6089 ret = 0; 6090 fmtcap = devinfo->function.audio.supp_stream_formats; 6091 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6092 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6093 6094 for (i = 0; i < 16 && ret < max; i++) { 6095 /* Check as is correct */ 6096 if (ch->as < 0) 6097 break; 6098 /* Cound only present DACs */ 6099 if (as[ch->as].dacs[i] <= 0) 6100 continue; 6101 /* Ignore duplicates */ 6102 for (j = 0; j < ret; j++) { 6103 if (ch->io[j] == as[ch->as].dacs[i]) 6104 break; 6105 } 6106 if (j < ret) 6107 continue; 6108 6109 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6110 if (w == NULL || w->enable == 0) 6111 continue; 6112 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6113 continue; 6114 cap = w->param.supp_stream_formats; 6115 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6116 }*/ 6117 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6118 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6119 continue; 6120 /* Many codec does not declare AC3 support on SPDIF. 6121 I don't beleave that they doesn't support it! */ 6122 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6123 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6124 if (ret == 0) { 6125 fmtcap = cap; 6126 pcmcap = w->param.supp_pcm_size_rate; 6127 } else { 6128 fmtcap &= cap; 6129 pcmcap &= w->param.supp_pcm_size_rate; 6130 } 6131 ch->io[ret++] = as[ch->as].dacs[i]; 6132 } 6133 ch->io[ret] = -1; 6134 6135 ch->supp_stream_formats = fmtcap; 6136 ch->supp_pcm_size_rate = pcmcap; 6137 6138 /* 6139 * 8bit = 0 6140 * 16bit = 1 6141 * 20bit = 2 6142 * 24bit = 3 6143 * 32bit = 4 6144 */ 6145 if (ret > 0) { 6146 i = 0; 6147 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6148 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6149 ch->bit16 = 1; 6150 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6151 ch->bit16 = 0; 6152 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6153 ch->bit32 = 4; 6154 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6155 ch->bit32 = 3; 6156 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6157 ch->bit32 = 2; 6158 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6159 ch->fmtlist[i++] = AFMT_S16_LE; 6160 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6161 if (ch->bit32 > 0) { 6162 if (!(devinfo->function.audio.quirks & 6163 HDA_QUIRK_FORCESTEREO)) 6164 ch->fmtlist[i++] = AFMT_S32_LE; 6165 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6166 } 6167 } 6168 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6169 ch->fmtlist[i++] = AFMT_AC3; 6170 } 6171 ch->fmtlist[i] = 0; 6172 i = 0; 6173 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6174 ch->pcmrates[i++] = 8000; 6175 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6176 ch->pcmrates[i++] = 11025; 6177 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6178 ch->pcmrates[i++] = 16000; 6179 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6180 ch->pcmrates[i++] = 22050; 6181 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6182 ch->pcmrates[i++] = 32000; 6183 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6184 ch->pcmrates[i++] = 44100; 6185 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6186 ch->pcmrates[i++] = 48000; 6187 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6188 ch->pcmrates[i++] = 88200; 6189 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6190 ch->pcmrates[i++] = 96000; 6191 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6192 ch->pcmrates[i++] = 176400; 6193 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6194 ch->pcmrates[i++] = 192000; 6195 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6196 ch->pcmrates[i] = 0; 6197 if (i > 0) { 6198 ch->caps.minspeed = ch->pcmrates[0]; 6199 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6200 } 6201 } 6202 6203 return (ret); 6204} 6205 6206static void 6207hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6208{ 6209 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6210 struct hdac_audio_ctl *ctl; 6211 struct hdac_softc *sc = devinfo->codec->sc; 6212 char buf[64]; 6213 int i, j, printed; 6214 6215 if (flag == 0) { 6216 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6217 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6218 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6219 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6220 } 6221 6222 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6223 if ((flag & (1 << j)) == 0) 6224 continue; 6225 i = 0; 6226 printed = 0; 6227 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6228 if (ctl->enable == 0 || 6229 ctl->widget->enable == 0) 6230 continue; 6231 if (!((pdevinfo->play >= 0 && 6232 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6233 (pdevinfo->rec >= 0 && 6234 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6235 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6236 continue; 6237 if ((ctl->ossmask & (1 << j)) == 0) 6238 continue; 6239 6240 if (printed == 0) { 6241 device_printf(pdevinfo->dev, "\n"); 6242 if (banner != NULL) { 6243 device_printf(pdevinfo->dev, "%s", banner); 6244 } else { 6245 device_printf(pdevinfo->dev, "Unknown Ctl"); 6246 } 6247 printf(" (OSS: %s)\n", 6248 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6249 buf, sizeof(buf))); 6250 device_printf(pdevinfo->dev, " |\n"); 6251 printed = 1; 6252 } 6253 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6254 ctl->widget->nid, 6255 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6256 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6257 printf(" %2d): ", ctl->index); 6258 else 6259 printf("): "); 6260 if (ctl->step > 0) { 6261 printf("%+d/%+ddB (%d steps)%s\n", 6262 (0 - ctl->offset) * (ctl->size + 1) / 4, 6263 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6264 ctl->step + 1, 6265 ctl->mute?" + mute":""); 6266 } else 6267 printf("%s\n", ctl->mute?"mute":""); 6268 } 6269 } 6270} 6271 6272static void 6273hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6274{ 6275 uint32_t cap; 6276 6277 cap = fcap; 6278 if (cap != 0) { 6279 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6280 device_printf(dev, " "); 6281 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6282 printf(" AC3"); 6283 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6284 printf(" FLOAT32"); 6285 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6286 printf(" PCM"); 6287 printf("\n"); 6288 } 6289 cap = pcmcap; 6290 if (cap != 0) { 6291 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6292 device_printf(dev, " "); 6293 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6294 printf(" 8"); 6295 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6296 printf(" 16"); 6297 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6298 printf(" 20"); 6299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6300 printf(" 24"); 6301 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6302 printf(" 32"); 6303 printf(" bits,"); 6304 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6305 printf(" 8"); 6306 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6307 printf(" 11"); 6308 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6309 printf(" 16"); 6310 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6311 printf(" 22"); 6312 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6313 printf(" 32"); 6314 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6315 printf(" 44"); 6316 printf(" 48"); 6317 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6318 printf(" 88"); 6319 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6320 printf(" 96"); 6321 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6322 printf(" 176"); 6323 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6324 printf(" 192"); 6325 printf(" KHz\n"); 6326 } 6327} 6328 6329static void 6330hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6331{ 6332 uint32_t pincap; 6333 6334 pincap = w->wclass.pin.cap; 6335 6336 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6337 device_printf(sc->dev, " "); 6338 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6339 printf(" ISC"); 6340 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6341 printf(" TRQD"); 6342 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6343 printf(" PDC"); 6344 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6345 printf(" HP"); 6346 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6347 printf(" OUT"); 6348 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6349 printf(" IN"); 6350 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6351 printf(" BAL"); 6352 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6353 printf(" VREF["); 6354 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6355 printf(" 50"); 6356 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6357 printf(" 80"); 6358 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6359 printf(" 100"); 6360 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6361 printf(" GROUND"); 6362 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6363 printf(" HIZ"); 6364 printf(" ]"); 6365 } 6366 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6367 printf(" EAPD"); 6368 printf("\n"); 6369 device_printf(sc->dev, " Pin config: 0x%08x\n", 6370 w->wclass.pin.config); 6371 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6372 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6373 printf(" HP"); 6374 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6375 printf(" IN"); 6376 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6377 printf(" OUT"); 6378 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6379 printf(" VREFs"); 6380 printf("\n"); 6381} 6382 6383static void 6384hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6385{ 6386 struct hdac_softc *sc = w->devinfo->codec->sc; 6387 6388 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6389 "jack %2d loc %2d color %7s misc %d%s\n", 6390 w->nid, conf, 6391 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6392 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6393 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6394 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6395 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6396 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6397 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6398 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6399 (w->enable == 0)?" [DISABLED]":""); 6400} 6401 6402static void 6403hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6404{ 6405 struct hdac_widget *w; 6406 int i; 6407 6408 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6409 w = hdac_widget_get(devinfo, i); 6410 if (w == NULL) 6411 continue; 6412 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6413 continue; 6414 hdac_dump_pin_config(w, w->wclass.pin.config); 6415 } 6416} 6417 6418static void 6419hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6420{ 6421 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6422 device_printf(sc->dev, " " 6423 "mute=%d step=%d size=%d offset=%d\n", 6424 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6425 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6426 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6427 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6428} 6429 6430static void 6431hdac_dump_nodes(struct hdac_devinfo *devinfo) 6432{ 6433 struct hdac_softc *sc = devinfo->codec->sc; 6434 static char *ossname[] = SOUND_DEVICE_NAMES; 6435 struct hdac_widget *w, *cw; 6436 char buf[64]; 6437 int i, j; 6438 6439 device_printf(sc->dev, "\n"); 6440 device_printf(sc->dev, "Default Parameter\n"); 6441 device_printf(sc->dev, "-----------------\n"); 6442 hdac_dump_audio_formats(sc->dev, 6443 devinfo->function.audio.supp_stream_formats, 6444 devinfo->function.audio.supp_pcm_size_rate); 6445 device_printf(sc->dev, " IN amp: 0x%08x\n", 6446 devinfo->function.audio.inamp_cap); 6447 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6448 devinfo->function.audio.outamp_cap); 6449 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6450 w = hdac_widget_get(devinfo, i); 6451 if (w == NULL) { 6452 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6453 continue; 6454 } 6455 device_printf(sc->dev, "\n"); 6456 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6457 (w->enable == 0) ? " [DISABLED]" : ""); 6458 device_printf(sc->dev, " Name: %s\n", w->name); 6459 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6460 w->param.widget_cap); 6461 if (w->param.widget_cap & 0x0ee1) { 6462 device_printf(sc->dev, " "); 6463 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6464 printf(" LRSWAP"); 6465 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6466 printf(" PWR"); 6467 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6468 printf(" DIGITAL"); 6469 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6470 printf(" UNSOL"); 6471 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6472 printf(" PROC"); 6473 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6474 printf(" STRIPE"); 6475 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6476 printf(" STEREO"); 6477 printf("\n"); 6478 } 6479 if (w->bindas != -1) { 6480 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6481 w->bindas, w->bindseqmask); 6482 } 6483 if (w->ossmask != 0 || w->ossdev >= 0) { 6484 device_printf(sc->dev, " OSS: %s", 6485 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6486 if (w->ossdev >= 0) 6487 printf(" (%s)", ossname[w->ossdev]); 6488 printf("\n"); 6489 } 6490 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6491 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6492 hdac_dump_audio_formats(sc->dev, 6493 w->param.supp_stream_formats, 6494 w->param.supp_pcm_size_rate); 6495 } else if (w->type == 6496 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6497 hdac_dump_pin(sc, w); 6498 if (w->param.eapdbtl != HDAC_INVALID) 6499 device_printf(sc->dev, " EAPD: 0x%08x\n", 6500 w->param.eapdbtl); 6501 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6502 w->param.outamp_cap != 0) 6503 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6504 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6505 w->param.inamp_cap != 0) 6506 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6507 if (w->nconns > 0) { 6508 device_printf(sc->dev, " connections: %d\n", w->nconns); 6509 device_printf(sc->dev, " |\n"); 6510 } 6511 for (j = 0; j < w->nconns; j++) { 6512 cw = hdac_widget_get(devinfo, w->conns[j]); 6513 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6514 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6515 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6516 if (cw == NULL) 6517 printf(" [UNKNOWN]"); 6518 else if (cw->enable == 0) 6519 printf(" [DISABLED]"); 6520 if (w->nconns > 1 && w->selconn == j && w->type != 6521 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6522 printf(" (selected)"); 6523 printf("\n"); 6524 } 6525 } 6526 6527} 6528 6529static void 6530hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6531{ 6532 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6533 struct hdac_widget *w, *cw; 6534 char buf[64]; 6535 int i, printed = 0; 6536 6537 if (depth > HDA_PARSE_MAXDEPTH) 6538 return; 6539 6540 w = hdac_widget_get(devinfo, nid); 6541 if (w == NULL || w->enable == 0) 6542 return; 6543 6544 if (depth == 0) 6545 device_printf(pdevinfo->dev, "%*s", 4, ""); 6546 else 6547 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6548 printf("nid=%d [%s]", w->nid, w->name); 6549 6550 if (depth > 0) { 6551 if (w->ossmask == 0) { 6552 printf("\n"); 6553 return; 6554 } 6555 printf(" [src: %s]", 6556 hdac_audio_ctl_ossmixer_mask2allname( 6557 w->ossmask, buf, sizeof(buf))); 6558 if (w->ossdev >= 0) { 6559 printf("\n"); 6560 return; 6561 } 6562 } 6563 printf("\n"); 6564 6565 for (i = 0; i < w->nconns; i++) { 6566 if (w->connsenable[i] == 0) 6567 continue; 6568 cw = hdac_widget_get(devinfo, w->conns[i]); 6569 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6570 continue; 6571 if (printed == 0) { 6572 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6573 printed = 1; 6574 } 6575 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6576 } 6577 6578} 6579 6580static void 6581hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6582{ 6583 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6584 struct hdac_softc *sc = devinfo->codec->sc; 6585 struct hdac_widget *w; 6586 int i, printed = 0; 6587 6588 if (pdevinfo->play < 0) 6589 return; 6590 6591 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6592 w = hdac_widget_get(devinfo, i); 6593 if (w == NULL || w->enable == 0) 6594 continue; 6595 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6596 continue; 6597 if (w->bindas != sc->chans[pdevinfo->play].as) 6598 continue; 6599 if (printed == 0) { 6600 printed = 1; 6601 device_printf(pdevinfo->dev, "\n"); 6602 device_printf(pdevinfo->dev, "Playback:\n"); 6603 } 6604 device_printf(pdevinfo->dev, "\n"); 6605 hdac_dump_dst_nid(pdevinfo, i, 0); 6606 } 6607} 6608 6609static void 6610hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6611{ 6612 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6613 struct hdac_softc *sc = devinfo->codec->sc; 6614 struct hdac_widget *w; 6615 int i; 6616 int printed = 0; 6617 6618 if (pdevinfo->rec < 0) 6619 return; 6620 6621 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6622 w = hdac_widget_get(devinfo, i); 6623 if (w == NULL || w->enable == 0) 6624 continue; 6625 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6626 continue; 6627 if (w->bindas != sc->chans[pdevinfo->rec].as) 6628 continue; 6629 if (printed == 0) { 6630 printed = 1; 6631 device_printf(pdevinfo->dev, "\n"); 6632 device_printf(pdevinfo->dev, "Record:\n"); 6633 } 6634 device_printf(pdevinfo->dev, "\n"); 6635 hdac_dump_dst_nid(pdevinfo, i, 0); 6636 } 6637} 6638 6639static void 6640hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6641{ 6642 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6643 struct hdac_widget *w; 6644 int i; 6645 int printed = 0; 6646 6647 if (pdevinfo->index != 0) 6648 return; 6649 6650 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6651 w = hdac_widget_get(devinfo, i); 6652 if (w == NULL || w->enable == 0) 6653 continue; 6654 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6655 continue; 6656 if (printed == 0) { 6657 printed = 1; 6658 device_printf(pdevinfo->dev, "\n"); 6659 device_printf(pdevinfo->dev, "Input Mix:\n"); 6660 } 6661 device_printf(pdevinfo->dev, "\n"); 6662 hdac_dump_dst_nid(pdevinfo, i, 0); 6663 } 6664} 6665 6666static void 6667hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6668{ 6669 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6670 nid_t *nids; 6671 int i; 6672 6673 if (pdevinfo->play >= 0) { 6674 i = pdevinfo->play; 6675 device_printf(pdevinfo->dev, "\n"); 6676 device_printf(pdevinfo->dev, "Playback:\n"); 6677 device_printf(pdevinfo->dev, "\n"); 6678 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6679 sc->chans[i].supp_pcm_size_rate); 6680 device_printf(pdevinfo->dev, " DAC:"); 6681 for (nids = sc->chans[i].io; *nids != -1; nids++) 6682 printf(" %d", *nids); 6683 printf("\n"); 6684 } 6685 if (pdevinfo->rec >= 0) { 6686 i = pdevinfo->rec; 6687 device_printf(pdevinfo->dev, "\n"); 6688 device_printf(pdevinfo->dev, "Record:\n"); 6689 device_printf(pdevinfo->dev, "\n"); 6690 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6691 sc->chans[i].supp_pcm_size_rate); 6692 device_printf(pdevinfo->dev, " ADC:"); 6693 for (nids = sc->chans[i].io; *nids != -1; nids++) 6694 printf(" %d", *nids); 6695 printf("\n"); 6696 } 6697} 6698 6699static void 6700hdac_release_resources(struct hdac_softc *sc) 6701{ 6702 int i, j; 6703 6704 if (sc == NULL) 6705 return; 6706 6707 hdac_lock(sc); 6708 sc->polling = 0; 6709 sc->poll_ival = 0; 6710 callout_stop(&sc->poll_hda); 6711 callout_stop(&sc->poll_hdac); 6712 callout_stop(&sc->poll_jack); 6713 hdac_reset(sc, 0); 6714 hdac_unlock(sc); 6715 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6716 callout_drain(&sc->poll_hda); 6717 callout_drain(&sc->poll_hdac); 6718 callout_drain(&sc->poll_jack); 6719 6720 hdac_irq_free(sc); 6721 6722 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6723 if (sc->codecs[i] == NULL) 6724 continue; 6725 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6726 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6727 if (sc->codecs[i]->fgs[j].node_type == 6728 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6729 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6730 M_HDAC); 6731 free(sc->codecs[i]->fgs[j].function.audio.as, 6732 M_HDAC); 6733 free(sc->codecs[i]->fgs[j].function.audio.devs, 6734 M_HDAC); 6735 } 6736 } 6737 free(sc->codecs[i]->fgs, M_HDAC); 6738 free(sc->codecs[i], M_HDAC); 6739 sc->codecs[i] = NULL; 6740 } 6741 6742 hdac_dma_free(sc, &sc->pos_dma); 6743 hdac_dma_free(sc, &sc->rirb_dma); 6744 hdac_dma_free(sc, &sc->corb_dma); 6745 for (i = 0; i < sc->num_chans; i++) { 6746 if (sc->chans[i].blkcnt > 0) 6747 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6748 } 6749 free(sc->chans, M_HDAC); 6750 if (sc->chan_dmat != NULL) { 6751 bus_dma_tag_destroy(sc->chan_dmat); 6752 sc->chan_dmat = NULL; 6753 } 6754 hdac_mem_free(sc); 6755 snd_mtxfree(sc->lock); 6756} 6757 6758/* This function surely going to make its way into upper level someday. */ 6759static void 6760hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6761{ 6762 const char *res = NULL; 6763 int i = 0, j, k, len, inv; 6764 6765 if (on != NULL) 6766 *on = 0; 6767 if (off != NULL) 6768 *off = 0; 6769 if (sc == NULL) 6770 return; 6771 if (resource_string_value(device_get_name(sc->dev), 6772 device_get_unit(sc->dev), "config", &res) != 0) 6773 return; 6774 if (!(res != NULL && strlen(res) > 0)) 6775 return; 6776 HDA_BOOTVERBOSE( 6777 device_printf(sc->dev, "HDA Config:"); 6778 ); 6779 for (;;) { 6780 while (res[i] != '\0' && 6781 (res[i] == ',' || isspace(res[i]) != 0)) 6782 i++; 6783 if (res[i] == '\0') { 6784 HDA_BOOTVERBOSE( 6785 printf("\n"); 6786 ); 6787 return; 6788 } 6789 j = i; 6790 while (res[j] != '\0' && 6791 !(res[j] == ',' || isspace(res[j]) != 0)) 6792 j++; 6793 len = j - i; 6794 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6795 inv = 2; 6796 else 6797 inv = 0; 6798 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6799 if (strncmp(res + i + inv, 6800 hdac_quirks_tab[k].key, len - inv) != 0) 6801 continue; 6802 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6803 break; 6804 HDA_BOOTVERBOSE( 6805 printf(" %s%s", (inv != 0) ? "no" : "", 6806 hdac_quirks_tab[k].key); 6807 ); 6808 if (inv == 0 && on != NULL) 6809 *on |= hdac_quirks_tab[k].value; 6810 else if (inv != 0 && off != NULL) 6811 *off |= hdac_quirks_tab[k].value; 6812 break; 6813 } 6814 i = j; 6815 } 6816} 6817 6818#ifdef SND_DYNSYSCTL 6819static int 6820sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6821{ 6822 struct hdac_softc *sc; 6823 device_t dev; 6824 uint32_t ctl; 6825 int err, val; 6826 6827 dev = oidp->oid_arg1; 6828 sc = device_get_softc(dev); 6829 if (sc == NULL) 6830 return (EINVAL); 6831 hdac_lock(sc); 6832 val = sc->polling; 6833 hdac_unlock(sc); 6834 err = sysctl_handle_int(oidp, &val, 0, req); 6835 6836 if (err != 0 || req->newptr == NULL) 6837 return (err); 6838 if (val < 0 || val > 1) 6839 return (EINVAL); 6840 6841 hdac_lock(sc); 6842 if (val != sc->polling) { 6843 if (val == 0) { 6844 callout_stop(&sc->poll_hda); 6845 callout_stop(&sc->poll_hdac); 6846 hdac_unlock(sc); 6847 callout_drain(&sc->poll_hda); 6848 callout_drain(&sc->poll_hdac); 6849 hdac_lock(sc); 6850 sc->polling = 0; 6851 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6852 ctl |= HDAC_INTCTL_GIE; 6853 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6854 } else { 6855 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6856 ctl &= ~HDAC_INTCTL_GIE; 6857 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6858 hdac_unlock(sc); 6859 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6860 hdac_lock(sc); 6861 sc->polling = 1; 6862 hdac_poll_reinit(sc); 6863 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6864 } 6865 } 6866 hdac_unlock(sc); 6867 6868 return (err); 6869} 6870 6871static int 6872sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6873{ 6874 struct hdac_softc *sc; 6875 device_t dev; 6876 int err, val; 6877 6878 dev = oidp->oid_arg1; 6879 sc = device_get_softc(dev); 6880 if (sc == NULL) 6881 return (EINVAL); 6882 hdac_lock(sc); 6883 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6884 hdac_unlock(sc); 6885 err = sysctl_handle_int(oidp, &val, 0, req); 6886 6887 if (err != 0 || req->newptr == NULL) 6888 return (err); 6889 6890 if (val < 1) 6891 val = 1; 6892 if (val > 5000) 6893 val = 5000; 6894 val = ((uint64_t)val * hz) / 1000; 6895 if (val < 1) 6896 val = 1; 6897 if (val > (hz * 5)) 6898 val = hz * 5; 6899 6900 hdac_lock(sc); 6901 sc->poll_ival = val; 6902 hdac_unlock(sc); 6903 6904 return (err); 6905} 6906 6907static int 6908sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6909{ 6910 struct hdac_softc *sc; 6911 struct hdac_codec *codec; 6912 struct hdac_devinfo *devinfo; 6913 struct hdac_widget *w; 6914 device_t dev; 6915 uint32_t res, pincap, delay; 6916 int codec_index, fg_index; 6917 int i, err, val; 6918 nid_t cad; 6919 6920 dev = oidp->oid_arg1; 6921 sc = device_get_softc(dev); 6922 if (sc == NULL) 6923 return (EINVAL); 6924 val = 0; 6925 err = sysctl_handle_int(oidp, &val, 0, req); 6926 if (err != 0 || req->newptr == NULL || val == 0) 6927 return (err); 6928 6929 /* XXX: Temporary. For debugging. */ 6930 if (val == 100) { 6931 hdac_suspend(dev); 6932 return (0); 6933 } else if (val == 101) { 6934 hdac_resume(dev); 6935 return (0); 6936 } 6937 6938 hdac_lock(sc); 6939 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 6940 codec = sc->codecs[codec_index]; 6941 if (codec == NULL) 6942 continue; 6943 cad = codec->cad; 6944 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 6945 devinfo = &codec->fgs[fg_index]; 6946 if (devinfo->node_type != 6947 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 6948 continue; 6949 6950 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 6951 codec_index, devinfo->nid); 6952 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6953 w = hdac_widget_get(devinfo, i); 6954 if (w == NULL || w->type != 6955 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6956 continue; 6957 hdac_dump_pin_config(w, w->wclass.pin.config); 6958 pincap = w->wclass.pin.cap; 6959 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 6960 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 6961 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 6962 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 6963 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 6964 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 6965 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6966 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 6967 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6968 delay = 0; 6969 hdac_command(sc, 6970 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6971 do { 6972 res = hdac_command(sc, 6973 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6974 if (res != 0x7fffffff && res != 0xffffffff) 6975 break; 6976 DELAY(10); 6977 } while (++delay < 10000); 6978 } else { 6979 delay = 0; 6980 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6981 w->nid), cad); 6982 } 6983 printf(" Sense: 0x%08x", res); 6984 if (delay > 0) 6985 printf(" delay %dus", delay * 10); 6986 } 6987 printf("\n"); 6988 } 6989 device_printf(dev, 6990 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6991 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6992 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6993 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6994 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6995 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6996 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6997 device_printf(dev, " GPI:"); 6998 res = hdac_command(sc, 6999 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7000 printf(" data=0x%08x", res); 7001 res = hdac_command(sc, 7002 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7003 cad); 7004 printf(" wake=0x%08x", res); 7005 res = hdac_command(sc, 7006 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7007 cad); 7008 printf(" unsol=0x%08x", res); 7009 res = hdac_command(sc, 7010 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7011 printf(" sticky=0x%08x\n", res); 7012 } 7013 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7014 device_printf(dev, " GPO:"); 7015 res = hdac_command(sc, 7016 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7017 printf(" data=0x%08x\n", res); 7018 } 7019 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7020 device_printf(dev, "GPIO:"); 7021 res = hdac_command(sc, 7022 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7023 printf(" data=0x%08x", res); 7024 res = hdac_command(sc, 7025 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7026 printf(" enable=0x%08x", res); 7027 res = hdac_command(sc, 7028 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7029 printf(" direction=0x%08x\n", res); 7030 res = hdac_command(sc, 7031 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7032 device_printf(dev, " wake=0x%08x", res); 7033 res = hdac_command(sc, 7034 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7035 cad); 7036 printf(" unsol=0x%08x", res); 7037 res = hdac_command(sc, 7038 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7039 printf(" sticky=0x%08x\n", res); 7040 } 7041 } 7042 } 7043 hdac_unlock(sc); 7044 return (0); 7045} 7046#endif 7047 7048static void 7049hdac_attach2(void *arg) 7050{ 7051 struct hdac_codec *codec; 7052 struct hdac_softc *sc; 7053 struct hdac_audio_ctl *ctl; 7054 uint32_t quirks_on, quirks_off; 7055 int codec_index, fg_index; 7056 int i, pdev, rdev, dmaalloc = 0; 7057 struct hdac_devinfo *devinfo; 7058 7059 sc = (struct hdac_softc *)arg; 7060 7061 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7062 7063 HDA_BOOTHVERBOSE( 7064 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7065 quirks_on, quirks_off); 7066 ); 7067 7068 hdac_lock(sc); 7069 7070 /* Remove ourselves from the config hooks */ 7071 if (sc->intrhook.ich_func != NULL) { 7072 config_intrhook_disestablish(&sc->intrhook); 7073 sc->intrhook.ich_func = NULL; 7074 } 7075 7076 /* Start the corb and rirb engines */ 7077 HDA_BOOTHVERBOSE( 7078 device_printf(sc->dev, "Starting CORB Engine...\n"); 7079 ); 7080 hdac_corb_start(sc); 7081 HDA_BOOTHVERBOSE( 7082 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7083 ); 7084 hdac_rirb_start(sc); 7085 7086 HDA_BOOTHVERBOSE( 7087 device_printf(sc->dev, 7088 "Enabling controller interrupt...\n"); 7089 ); 7090 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7091 HDAC_GCTL_UNSOL); 7092 if (sc->polling == 0) { 7093 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7094 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7095 } else { 7096 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7097 } 7098 DELAY(1000); 7099 7100 HDA_BOOTHVERBOSE( 7101 device_printf(sc->dev, 7102 "Scanning HDA codecs ...\n"); 7103 ); 7104 hdac_scan_codecs(sc); 7105 7106 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7107 codec = sc->codecs[codec_index]; 7108 if (codec == NULL) 7109 continue; 7110 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7111 devinfo = &codec->fgs[fg_index]; 7112 HDA_BOOTVERBOSE( 7113 device_printf(sc->dev, "\n"); 7114 device_printf(sc->dev, 7115 "Processing %s FG cad=%d nid=%d...\n", 7116 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7117 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7118 "unknown", 7119 devinfo->codec->cad, devinfo->nid); 7120 ); 7121 if (devinfo->node_type != 7122 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7123 HDA_BOOTHVERBOSE( 7124 device_printf(sc->dev, 7125 "Powering down...\n"); 7126 ); 7127 hdac_command(sc, 7128 HDA_CMD_SET_POWER_STATE(codec->cad, 7129 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7130 codec->cad); 7131 continue; 7132 } 7133 7134 HDA_BOOTHVERBOSE( 7135 device_printf(sc->dev, "Powering up...\n"); 7136 ); 7137 hdac_powerup(devinfo); 7138 HDA_BOOTHVERBOSE( 7139 device_printf(sc->dev, "Parsing audio FG...\n"); 7140 ); 7141 hdac_audio_parse(devinfo); 7142 HDA_BOOTHVERBOSE( 7143 device_printf(sc->dev, "Parsing Ctls...\n"); 7144 ); 7145 hdac_audio_ctl_parse(devinfo); 7146 HDA_BOOTHVERBOSE( 7147 device_printf(sc->dev, "Parsing vendor patch...\n"); 7148 ); 7149 hdac_vendor_patch_parse(devinfo); 7150 devinfo->function.audio.quirks |= quirks_on; 7151 devinfo->function.audio.quirks &= ~quirks_off; 7152 7153 HDA_BOOTHVERBOSE( 7154 device_printf(sc->dev, "Disabling nonaudio...\n"); 7155 ); 7156 hdac_audio_disable_nonaudio(devinfo); 7157 HDA_BOOTHVERBOSE( 7158 device_printf(sc->dev, "Disabling useless...\n"); 7159 ); 7160 hdac_audio_disable_useless(devinfo); 7161 HDA_BOOTVERBOSE( 7162 device_printf(sc->dev, "Patched pins configuration:\n"); 7163 hdac_dump_pin_configs(devinfo); 7164 ); 7165 HDA_BOOTHVERBOSE( 7166 device_printf(sc->dev, "Parsing pin associations...\n"); 7167 ); 7168 hdac_audio_as_parse(devinfo); 7169 HDA_BOOTHVERBOSE( 7170 device_printf(sc->dev, "Building AFG tree...\n"); 7171 ); 7172 hdac_audio_build_tree(devinfo); 7173 HDA_BOOTHVERBOSE( 7174 device_printf(sc->dev, "Disabling unassociated " 7175 "widgets...\n"); 7176 ); 7177 hdac_audio_disable_unas(devinfo); 7178 HDA_BOOTHVERBOSE( 7179 device_printf(sc->dev, "Disabling nonselected " 7180 "inputs...\n"); 7181 ); 7182 hdac_audio_disable_notselected(devinfo); 7183 HDA_BOOTHVERBOSE( 7184 device_printf(sc->dev, "Disabling useless...\n"); 7185 ); 7186 hdac_audio_disable_useless(devinfo); 7187 HDA_BOOTHVERBOSE( 7188 device_printf(sc->dev, "Disabling " 7189 "crossassociatement connections...\n"); 7190 ); 7191 hdac_audio_disable_crossas(devinfo); 7192 HDA_BOOTHVERBOSE( 7193 device_printf(sc->dev, "Disabling useless...\n"); 7194 ); 7195 hdac_audio_disable_useless(devinfo); 7196 HDA_BOOTHVERBOSE( 7197 device_printf(sc->dev, "Binding associations to channels...\n"); 7198 ); 7199 hdac_audio_bind_as(devinfo); 7200 HDA_BOOTHVERBOSE( 7201 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7202 ); 7203 hdac_audio_assign_names(devinfo); 7204 HDA_BOOTHVERBOSE( 7205 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7206 ); 7207 hdac_audio_assign_mixers(devinfo); 7208 HDA_BOOTHVERBOSE( 7209 device_printf(sc->dev, "Preparing pin controls...\n"); 7210 ); 7211 hdac_audio_prepare_pin_ctrl(devinfo); 7212 HDA_BOOTHVERBOSE( 7213 device_printf(sc->dev, "AFG commit...\n"); 7214 ); 7215 hdac_audio_commit(devinfo); 7216 HDA_BOOTHVERBOSE( 7217 device_printf(sc->dev, "Ctls commit...\n"); 7218 ); 7219 hdac_audio_ctl_commit(devinfo); 7220 HDA_BOOTHVERBOSE( 7221 device_printf(sc->dev, "HP switch init...\n"); 7222 ); 7223 hdac_hp_switch_init(devinfo); 7224 7225 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7226 dmaalloc == 0) { 7227 if (hdac_dma_alloc(sc, &sc->pos_dma, 7228 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7229 HDA_BOOTVERBOSE( 7230 device_printf(sc->dev, "Failed to " 7231 "allocate DMA pos buffer " 7232 "(non-fatal)\n"); 7233 ); 7234 } else 7235 dmaalloc = 1; 7236 } 7237 7238 i = devinfo->function.audio.playcnt; 7239 if (devinfo->function.audio.reccnt > i) 7240 i = devinfo->function.audio.reccnt; 7241 devinfo->function.audio.devs = 7242 (struct hdac_pcm_devinfo *)malloc( 7243 sizeof(struct hdac_pcm_devinfo) * i, 7244 M_HDAC, M_ZERO | M_NOWAIT); 7245 if (devinfo->function.audio.devs == NULL) { 7246 device_printf(sc->dev, 7247 "Unable to allocate memory for devices\n"); 7248 continue; 7249 } 7250 devinfo->function.audio.num_devs = i; 7251 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7252 devinfo->function.audio.devs[i].index = i; 7253 devinfo->function.audio.devs[i].devinfo = devinfo; 7254 devinfo->function.audio.devs[i].play = -1; 7255 devinfo->function.audio.devs[i].rec = -1; 7256 } 7257 pdev = 0; 7258 rdev = 0; 7259 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 7260 if (devinfo->function.audio.as[i].enable == 0) 7261 continue; 7262 if (devinfo->function.audio.as[i].dir == 7263 HDA_CTL_IN) { 7264 devinfo->function.audio.devs[rdev].rec 7265 = devinfo->function.audio.as[i].chan; 7266 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7267 &devinfo->function.audio.devs[rdev]; 7268 rdev++; 7269 } else { 7270 devinfo->function.audio.devs[pdev].play 7271 = devinfo->function.audio.as[i].chan; 7272 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7273 &devinfo->function.audio.devs[pdev]; 7274 pdev++; 7275 } 7276 } 7277 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7278 struct hdac_pcm_devinfo *pdevinfo = 7279 &devinfo->function.audio.devs[i]; 7280 pdevinfo->dev = 7281 device_add_child(sc->dev, "pcm", -1); 7282 device_set_ivars(pdevinfo->dev, 7283 (void *)pdevinfo); 7284 } 7285 7286 HDA_BOOTVERBOSE( 7287 if (devinfo->function.audio.quirks != 0) { 7288 device_printf(sc->dev, "FG config/quirks:"); 7289 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7290 if ((devinfo->function.audio.quirks & 7291 hdac_quirks_tab[i].value) == 7292 hdac_quirks_tab[i].value) 7293 printf(" %s", hdac_quirks_tab[i].key); 7294 } 7295 printf("\n"); 7296 } 7297 7298 device_printf(sc->dev, "\n"); 7299 device_printf(sc->dev, "+-------------------+\n"); 7300 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7301 device_printf(sc->dev, "+-------------------+\n"); 7302 hdac_dump_nodes(devinfo); 7303 ); 7304 7305 HDA_BOOTHVERBOSE( 7306 device_printf(sc->dev, "\n"); 7307 device_printf(sc->dev, "+------------------------+\n"); 7308 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7309 device_printf(sc->dev, "+------------------------+\n"); 7310 device_printf(sc->dev, "\n"); 7311 i = 0; 7312 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7313 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7314 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7315 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7316 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7317 ctl->index); 7318 if (ctl->childwidget != NULL) 7319 printf(" cnid %3d", ctl->childwidget->nid); 7320 else 7321 printf(" "); 7322 printf(" ossmask=0x%08x\n", 7323 ctl->ossmask); 7324 device_printf(sc->dev, 7325 " mute: %d step: %3d size: %3d off: %3d%s\n", 7326 ctl->mute, ctl->step, ctl->size, ctl->offset, 7327 (ctl->enable == 0) ? " [DISABLED]" : 7328 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7329 } 7330 ); 7331 } 7332 } 7333 hdac_unlock(sc); 7334 7335 HDA_BOOTVERBOSE( 7336 device_printf(sc->dev, "\n"); 7337 ); 7338 7339 bus_generic_attach(sc->dev); 7340 7341#ifdef SND_DYNSYSCTL 7342 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7343 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7344 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7345 sysctl_hdac_polling, "I", "Enable polling mode"); 7346 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7347 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7348 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7349 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7350 "Controller/Jack Sense polling interval (1-1000 ms)"); 7351 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7352 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7353 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7354 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7355#endif 7356} 7357 7358/**************************************************************************** 7359 * int hdac_suspend(device_t) 7360 * 7361 * Suspend and power down HDA bus and codecs. 7362 ****************************************************************************/ 7363static int 7364hdac_suspend(device_t dev) 7365{ 7366 struct hdac_softc *sc; 7367 struct hdac_codec *codec; 7368 struct hdac_devinfo *devinfo; 7369 int codec_index, fg_index, i; 7370 7371 HDA_BOOTHVERBOSE( 7372 device_printf(dev, "Suspend...\n"); 7373 ); 7374 7375 sc = device_get_softc(dev); 7376 hdac_lock(sc); 7377 7378 HDA_BOOTHVERBOSE( 7379 device_printf(dev, "Stop streams...\n"); 7380 ); 7381 for (i = 0; i < sc->num_chans; i++) { 7382 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7383 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7384 hdac_channel_stop(sc, &sc->chans[i]); 7385 } 7386 } 7387 7388 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7389 codec = sc->codecs[codec_index]; 7390 if (codec == NULL) 7391 continue; 7392 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7393 devinfo = &codec->fgs[fg_index]; 7394 HDA_BOOTHVERBOSE( 7395 device_printf(dev, 7396 "Power down FG" 7397 " cad=%d nid=%d to the D3 state...\n", 7398 codec->cad, devinfo->nid); 7399 ); 7400 hdac_command(sc, 7401 HDA_CMD_SET_POWER_STATE(codec->cad, 7402 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7403 codec->cad); 7404 } 7405 } 7406 7407 HDA_BOOTHVERBOSE( 7408 device_printf(dev, "Reset controller...\n"); 7409 ); 7410 callout_stop(&sc->poll_hda); 7411 callout_stop(&sc->poll_hdac); 7412 callout_stop(&sc->poll_jack); 7413 hdac_reset(sc, 0); 7414 hdac_unlock(sc); 7415 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7416 callout_drain(&sc->poll_hda); 7417 callout_drain(&sc->poll_hdac); 7418 callout_drain(&sc->poll_jack); 7419 7420 HDA_BOOTHVERBOSE( 7421 device_printf(dev, "Suspend done\n"); 7422 ); 7423 7424 return (0); 7425} 7426 7427/**************************************************************************** 7428 * int hdac_resume(device_t) 7429 * 7430 * Powerup and restore HDA bus and codecs state. 7431 ****************************************************************************/ 7432static int 7433hdac_resume(device_t dev) 7434{ 7435 struct hdac_softc *sc; 7436 struct hdac_codec *codec; 7437 struct hdac_devinfo *devinfo; 7438 int codec_index, fg_index, i; 7439 7440 HDA_BOOTHVERBOSE( 7441 device_printf(dev, "Resume...\n"); 7442 ); 7443 7444 sc = device_get_softc(dev); 7445 hdac_lock(sc); 7446 7447 /* Quiesce everything */ 7448 HDA_BOOTHVERBOSE( 7449 device_printf(dev, "Reset controller...\n"); 7450 ); 7451 hdac_reset(sc, 1); 7452 7453 /* Initialize the CORB and RIRB */ 7454 hdac_corb_init(sc); 7455 hdac_rirb_init(sc); 7456 7457 /* Start the corb and rirb engines */ 7458 HDA_BOOTHVERBOSE( 7459 device_printf(dev, "Starting CORB Engine...\n"); 7460 ); 7461 hdac_corb_start(sc); 7462 HDA_BOOTHVERBOSE( 7463 device_printf(dev, "Starting RIRB Engine...\n"); 7464 ); 7465 hdac_rirb_start(sc); 7466 7467 HDA_BOOTHVERBOSE( 7468 device_printf(dev, 7469 "Enabling controller interrupt...\n"); 7470 ); 7471 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7472 HDAC_GCTL_UNSOL); 7473 if (sc->polling == 0) { 7474 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7475 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7476 } else { 7477 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7478 } 7479 DELAY(1000); 7480 7481 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7482 codec = sc->codecs[codec_index]; 7483 if (codec == NULL) 7484 continue; 7485 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7486 devinfo = &codec->fgs[fg_index]; 7487 if (devinfo->node_type != 7488 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7489 HDA_BOOTHVERBOSE( 7490 device_printf(dev, 7491 "Power down unsupported non-audio FG" 7492 " cad=%d nid=%d to the D3 state...\n", 7493 codec->cad, devinfo->nid); 7494 ); 7495 hdac_command(sc, 7496 HDA_CMD_SET_POWER_STATE(codec->cad, 7497 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7498 codec->cad); 7499 continue; 7500 } 7501 7502 HDA_BOOTHVERBOSE( 7503 device_printf(dev, 7504 "Power up audio FG cad=%d nid=%d...\n", 7505 devinfo->codec->cad, devinfo->nid); 7506 ); 7507 hdac_powerup(devinfo); 7508 HDA_BOOTHVERBOSE( 7509 device_printf(dev, "AFG commit...\n"); 7510 ); 7511 hdac_audio_commit(devinfo); 7512 HDA_BOOTHVERBOSE( 7513 device_printf(dev, "Ctls commit...\n"); 7514 ); 7515 hdac_audio_ctl_commit(devinfo); 7516 HDA_BOOTHVERBOSE( 7517 device_printf(dev, "HP switch init...\n"); 7518 ); 7519 hdac_hp_switch_init(devinfo); 7520 7521 hdac_unlock(sc); 7522 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7523 struct hdac_pcm_devinfo *pdevinfo = 7524 &devinfo->function.audio.devs[i]; 7525 HDA_BOOTHVERBOSE( 7526 device_printf(pdevinfo->dev, 7527 "OSS mixer reinitialization...\n"); 7528 ); 7529 if (mixer_reinit(pdevinfo->dev) == -1) 7530 device_printf(pdevinfo->dev, 7531 "unable to reinitialize the mixer\n"); 7532 } 7533 hdac_lock(sc); 7534 } 7535 } 7536 7537 HDA_BOOTHVERBOSE( 7538 device_printf(dev, "Start streams...\n"); 7539 ); 7540 for (i = 0; i < sc->num_chans; i++) { 7541 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7542 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7543 hdac_channel_start(sc, &sc->chans[i]); 7544 } 7545 } 7546 7547 hdac_unlock(sc); 7548 7549 HDA_BOOTHVERBOSE( 7550 device_printf(dev, "Resume done\n"); 7551 ); 7552 7553 return (0); 7554} 7555/**************************************************************************** 7556 * int hdac_detach(device_t) 7557 * 7558 * Detach and free up resources utilized by the hdac device. 7559 ****************************************************************************/ 7560static int 7561hdac_detach(device_t dev) 7562{ 7563 struct hdac_softc *sc; 7564 device_t *devlist = NULL; 7565 int i, devcount; 7566 7567 sc = device_get_softc(dev); 7568 7569 device_get_children(dev, &devlist, &devcount); 7570 for (i = 0; devlist != NULL && i < devcount; i++) 7571 device_delete_child(dev, devlist[i]); 7572 if (devlist != NULL) 7573 free(devlist, M_TEMP); 7574 7575 hdac_release_resources(sc); 7576 7577 return (0); 7578} 7579 7580static int 7581hdac_print_child(device_t dev, device_t child) 7582{ 7583 struct hdac_pcm_devinfo *pdevinfo = 7584 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7585 int retval; 7586 7587 retval = bus_print_child_header(dev, child); 7588 retval += printf(" at cad %d nid %d", 7589 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7590 retval += bus_print_child_footer(dev, child); 7591 7592 return (retval); 7593} 7594 7595static device_method_t hdac_methods[] = { 7596 /* device interface */ 7597 DEVMETHOD(device_probe, hdac_probe), 7598 DEVMETHOD(device_attach, hdac_attach), 7599 DEVMETHOD(device_detach, hdac_detach), 7600 DEVMETHOD(device_suspend, hdac_suspend), 7601 DEVMETHOD(device_resume, hdac_resume), 7602 /* Bus interface */ 7603 DEVMETHOD(bus_print_child, hdac_print_child), 7604 { 0, 0 } 7605}; 7606 7607static driver_t hdac_driver = { 7608 "hdac", 7609 hdac_methods, 7610 sizeof(struct hdac_softc), 7611}; 7612 7613static devclass_t hdac_devclass; 7614 7615DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7616MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7617MODULE_VERSION(snd_hda, 1); 7618 7619static int 7620hdac_pcm_probe(device_t dev) 7621{ 7622 struct hdac_pcm_devinfo *pdevinfo = 7623 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7624 char buf[128]; 7625 7626 snprintf(buf, sizeof(buf), "HDA %s PCM #%d", 7627 hdac_codec_name(pdevinfo->devinfo->codec), 7628 pdevinfo->index); 7629 device_set_desc_copy(dev, buf); 7630 return (0); 7631} 7632 7633static int 7634hdac_pcm_attach(device_t dev) 7635{ 7636 struct hdac_pcm_devinfo *pdevinfo = 7637 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7638 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7639 char status[SND_STATUSLEN]; 7640 int i; 7641 7642 pdevinfo->chan_size = pcm_getbuffersize(dev, 7643 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7644 7645 HDA_BOOTVERBOSE( 7646 device_printf(dev, "+--------------------------------------+\n"); 7647 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7648 device_printf(dev, "+--------------------------------------+\n"); 7649 hdac_dump_pcmchannels(pdevinfo); 7650 device_printf(dev, "\n"); 7651 device_printf(dev, "+--------------------------------+\n"); 7652 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7653 device_printf(dev, "+--------------------------------+\n"); 7654 hdac_dump_dac(pdevinfo); 7655 hdac_dump_adc(pdevinfo); 7656 hdac_dump_mix(pdevinfo); 7657 device_printf(dev, "\n"); 7658 device_printf(dev, "+-------------------------+\n"); 7659 device_printf(dev, "| DUMPING Volume Controls |\n"); 7660 device_printf(dev, "+-------------------------+\n"); 7661 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7662 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7663 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7664 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7665 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7666 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7667 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7668 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7669 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7670 hdac_dump_ctls(pdevinfo, NULL, 0); 7671 device_printf(dev, "\n"); 7672 ); 7673 7674 if (resource_int_value(device_get_name(dev), 7675 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7676 i &= HDA_BLK_ALIGN; 7677 if (i < HDA_BLK_MIN) 7678 i = HDA_BLK_MIN; 7679 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7680 i = 0; 7681 while (pdevinfo->chan_blkcnt >> i) 7682 i++; 7683 pdevinfo->chan_blkcnt = 1 << (i - 1); 7684 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7685 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7686 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7687 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7688 } else 7689 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7690 7691 /* 7692 * We don't register interrupt handler with snd_setup_intr 7693 * in pcm device. Mark pcm device as MPSAFE manually. 7694 */ 7695 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7696 7697 HDA_BOOTHVERBOSE( 7698 device_printf(dev, "OSS mixer initialization...\n"); 7699 ); 7700 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7701 device_printf(dev, "Can't register mixer\n"); 7702 7703 HDA_BOOTHVERBOSE( 7704 device_printf(dev, "Registering PCM channels...\n"); 7705 ); 7706 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7707 (pdevinfo->rec >= 0)?1:0) != 0) 7708 device_printf(dev, "Can't register PCM\n"); 7709 7710 pdevinfo->registered++; 7711 7712 if (pdevinfo->play >= 0) 7713 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7714 if (pdevinfo->rec >= 0) 7715 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7716 7717 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7718 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7719 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7720 pcm_setstatus(dev, status); 7721 7722 return (0); 7723} 7724 7725static int 7726hdac_pcm_detach(device_t dev) 7727{ 7728 struct hdac_pcm_devinfo *pdevinfo = 7729 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7730 int err; 7731 7732 if (pdevinfo->registered > 0) { 7733 err = pcm_unregister(dev); 7734 if (err != 0) 7735 return (err); 7736 } 7737 7738 return (0); 7739} 7740 7741static device_method_t hdac_pcm_methods[] = { 7742 /* device interface */ 7743 DEVMETHOD(device_probe, hdac_pcm_probe), 7744 DEVMETHOD(device_attach, hdac_pcm_attach), 7745 DEVMETHOD(device_detach, hdac_pcm_detach), 7746 { 0, 0 } 7747}; 7748 7749static driver_t hdac_pcm_driver = { 7750 "pcm", 7751 hdac_pcm_methods, 7752 PCM_SOFTC_SIZE, 7753}; 7754 7755DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7756 7757