hdac.c revision 184254
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20081024_0114" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 184254 2008-10-25 08:31:20Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 166 167/* ATI */ 168#define ATI_VENDORID 0x1002 169#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 170#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 171#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 172 173/* VIA */ 174#define VIA_VENDORID 0x1106 175#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 176#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 177 178/* SiS */ 179#define SIS_VENDORID 0x1039 180#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 181#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 182 183/* OEM/subvendors */ 184 185/* Intel */ 186#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 187 188/* HP/Compaq */ 189#define HP_VENDORID 0x103c 190#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 191#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 192#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 193#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 194#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 195#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 196#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 197#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 198#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 199#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 200/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 201#define HP_NX6325_SUBVENDORX 0x103c30b0 202 203/* Dell */ 204#define DELL_VENDORID 0x1028 205#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 206#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 207#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 208#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 209#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 210#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 211#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 212 213/* Clevo */ 214#define CLEVO_VENDORID 0x1558 215#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 216#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 217 218/* Acer */ 219#define ACER_VENDORID 0x1025 220#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 221#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 222#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 223#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 224#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 225#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 226#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 227 228/* Asus */ 229#define ASUS_VENDORID 0x1043 230#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 231#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 232#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 233#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 234#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 235#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 236#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 237#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 238#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 239#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 240#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 241#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 242#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 243#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 244#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 245#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 246 247/* IBM / Lenovo */ 248#define IBM_VENDORID 0x1014 249#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 250#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 251 252/* Lenovo */ 253#define LENOVO_VENDORID 0x17aa 254#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 255#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 256#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 257#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 258 259/* Samsung */ 260#define SAMSUNG_VENDORID 0x144d 261#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 262#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 263 264/* Medion ? */ 265#define MEDION_VENDORID 0x161f 266#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 267#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 268 269/* Apple Computer Inc. */ 270#define APPLE_VENDORID 0x106b 271#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 272 273/* Sony */ 274#define SONY_VENDORID 0x104d 275#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 276#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 277 278/* 279 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 280 * instead of their own, which is beyond my comprehension 281 * (see HDA_CODEC_STAC9221 below). 282 */ 283#define APPLE_INTEL_MAC 0x76808384 284 285/* LG Electronics */ 286#define LG_VENDORID 0x1854 287#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 288#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 289 290/* Fujitsu Siemens */ 291#define FS_VENDORID 0x1734 292#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 293#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 294#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 295 296/* Fujitsu Limited */ 297#define FL_VENDORID 0x10cf 298#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 299#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 300#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 301 302/* Toshiba */ 303#define TOSHIBA_VENDORID 0x1179 304#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 305#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 306#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 307 308/* Micro-Star International (MSI) */ 309#define MSI_VENDORID 0x1462 310#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 311#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 312#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 313 314/* Giga-Byte Technology */ 315#define GB_VENDORID 0x1458 316#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 317#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 318 319/* Uniwill ? */ 320#define UNIWILL_VENDORID 0x1584 321#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 322#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 323 324 325/* Misc constants.. */ 326#define HDA_AMP_VOL_DEFAULT (-1) 327#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 328#define HDA_AMP_MUTE_NONE (0) 329#define HDA_AMP_MUTE_LEFT (1 << 0) 330#define HDA_AMP_MUTE_RIGHT (1 << 1) 331#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 332 333#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 334#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 335 336#define HDA_ADC_MONITOR (1 << 0) 337 338#define HDA_CTL_OUT 1 339#define HDA_CTL_IN 2 340 341#define HDA_GPIO_MAX 8 342/* 0 - 7 = GPIO , 8 = Flush */ 343#define HDA_QUIRK_GPIO0 (1 << 0) 344#define HDA_QUIRK_GPIO1 (1 << 1) 345#define HDA_QUIRK_GPIO2 (1 << 2) 346#define HDA_QUIRK_GPIO3 (1 << 3) 347#define HDA_QUIRK_GPIO4 (1 << 4) 348#define HDA_QUIRK_GPIO5 (1 << 5) 349#define HDA_QUIRK_GPIO6 (1 << 6) 350#define HDA_QUIRK_GPIO7 (1 << 7) 351#define HDA_QUIRK_GPIOFLUSH (1 << 8) 352 353/* 9 - 25 = anything else */ 354#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 355#define HDA_QUIRK_FIXEDRATE (1 << 10) 356#define HDA_QUIRK_FORCESTEREO (1 << 11) 357#define HDA_QUIRK_EAPDINV (1 << 12) 358#define HDA_QUIRK_DMAPOS (1 << 13) 359#define HDA_QUIRK_SENSEINV (1 << 14) 360 361/* 26 - 31 = vrefs */ 362#define HDA_QUIRK_IVREF50 (1 << 26) 363#define HDA_QUIRK_IVREF80 (1 << 27) 364#define HDA_QUIRK_IVREF100 (1 << 28) 365#define HDA_QUIRK_OVREF50 (1 << 29) 366#define HDA_QUIRK_OVREF80 (1 << 30) 367#define HDA_QUIRK_OVREF100 (1 << 31) 368 369#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 370 HDA_QUIRK_IVREF100) 371#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 372 HDA_QUIRK_OVREF100) 373#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 374 375#if __FreeBSD_version < 600000 376#define taskqueue_drain(...) 377#endif 378 379static const struct { 380 char *key; 381 uint32_t value; 382} hdac_quirks_tab[] = { 383 { "gpio0", HDA_QUIRK_GPIO0 }, 384 { "gpio1", HDA_QUIRK_GPIO1 }, 385 { "gpio2", HDA_QUIRK_GPIO2 }, 386 { "gpio3", HDA_QUIRK_GPIO3 }, 387 { "gpio4", HDA_QUIRK_GPIO4 }, 388 { "gpio5", HDA_QUIRK_GPIO5 }, 389 { "gpio6", HDA_QUIRK_GPIO6 }, 390 { "gpio7", HDA_QUIRK_GPIO7 }, 391 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 392 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 393 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 394 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 395 { "eapdinv", HDA_QUIRK_EAPDINV }, 396 { "dmapos", HDA_QUIRK_DMAPOS }, 397 { "senseinv", HDA_QUIRK_SENSEINV }, 398 { "ivref50", HDA_QUIRK_IVREF50 }, 399 { "ivref80", HDA_QUIRK_IVREF80 }, 400 { "ivref100", HDA_QUIRK_IVREF100 }, 401 { "ovref50", HDA_QUIRK_OVREF50 }, 402 { "ovref80", HDA_QUIRK_OVREF80 }, 403 { "ovref100", HDA_QUIRK_OVREF100 }, 404 { "ivref", HDA_QUIRK_IVREF }, 405 { "ovref", HDA_QUIRK_OVREF }, 406 { "vref", HDA_QUIRK_VREF }, 407}; 408#define HDAC_QUIRKS_TAB_LEN \ 409 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 410 411#define HDA_BDL_MIN 2 412#define HDA_BDL_MAX 256 413#define HDA_BDL_DEFAULT HDA_BDL_MIN 414 415#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 416#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 417 418#define HDA_BUFSZ_MIN 4096 419#define HDA_BUFSZ_MAX 65536 420#define HDA_BUFSZ_DEFAULT 16384 421 422#define HDA_PARSE_MAXDEPTH 10 423 424#define HDAC_UNSOLTAG_EVENT_HP 0x00 425 426MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 427 428const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 429 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 430 "White", "Other"}; 431 432const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 433 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 434 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 435 436const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 437 438/* Default */ 439static uint32_t hdac_fmt[] = { 440 AFMT_STEREO | AFMT_S16_LE, 441 0 442}; 443 444static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 445 446static const struct { 447 uint32_t model; 448 char *desc; 449} hdac_devices[] = { 450 { HDA_INTEL_82801F, "Intel 82801F" }, 451 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 452 { HDA_INTEL_82801G, "Intel 82801G" }, 453 { HDA_INTEL_82801H, "Intel 82801H" }, 454 { HDA_INTEL_82801I, "Intel 82801I" }, 455 { HDA_INTEL_82801J, "Intel 82801J" }, 456 { HDA_INTEL_SCH, "Intel SCH" }, 457 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 458 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 459 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 460 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 461 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 462 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 463 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 464 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 465 { HDA_ATI_SB450, "ATI SB450" }, 466 { HDA_ATI_SB600, "ATI SB600" }, 467 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 468 { HDA_SIS_966, "SiS 966" }, 469 /* Unknown */ 470 { HDA_INTEL_ALL, "Intel (Unknown)" }, 471 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 472 { HDA_ATI_ALL, "ATI (Unknown)" }, 473 { HDA_VIA_ALL, "VIA (Unknown)" }, 474 { HDA_SIS_ALL, "SiS (Unknown)" }, 475}; 476#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 477 478static const struct { 479 uint16_t vendor; 480 uint8_t reg; 481 uint8_t mask; 482 uint8_t enable; 483} hdac_pcie_snoop[] = { 484 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 485 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 486 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 487}; 488#define HDAC_PCIESNOOP_LEN \ 489 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 490 491static const struct { 492 uint32_t rate; 493 int valid; 494 uint16_t base; 495 uint16_t mul; 496 uint16_t div; 497} hda_rate_tab[] = { 498 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 499 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 500 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 501 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 502 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 503 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 504 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 505 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 506 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 507 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 508 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 509 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 510 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 511 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 512 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 513 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 514 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 515 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 516 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 517 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 518 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 519 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 520 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 521 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 522 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 523 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 524 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 525 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 526 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 527 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 528 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 529 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 530 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 531 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 532 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 533}; 534#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 535 536/* All codecs you can eat... */ 537#define HDA_CODEC_CONSTRUCT(vendor, id) \ 538 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 539 540/* Realtek */ 541#define REALTEK_VENDORID 0x10ec 542#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 543#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 544#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 545#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 546#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 547#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 548#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 549#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 550#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 551#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 552#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 553#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 554#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 555#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 556#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 557#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 558#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 559#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 560 561/* Analog Devices */ 562#define ANALOGDEVICES_VENDORID 0x11d4 563#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 564#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 565#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 566#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 567#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 568#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 569#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 570 571/* CMedia */ 572#define CMEDIA_VENDORID 0x434d 573#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 574#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 575 576/* Sigmatel */ 577#define SIGMATEL_VENDORID 0x8384 578#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 579#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 580#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 581#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 582#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 583#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 584#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 585#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 586#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 587#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 588#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 589#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 590#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 591#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 592#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 593#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 594#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 595#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 596#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 597#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 598#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 599#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 600#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 601#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 602#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 603#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 604#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 605#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 606#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 607#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 608#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 609#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 610#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 611#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 612#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 613#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 614#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 615#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 616#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 617#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 618 619/* IDT */ 620#define IDT_VENDORID 0x111d 621#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 622#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 623#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 624#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 625#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 626#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 627#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 628#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 629#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 630#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 631#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 632#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 633#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 634 635/* Silicon Image */ 636#define SII_VENDORID 0x1095 637#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 638 639/* Lucent/Agere */ 640#define AGERE_VENDORID 0x11c1 641#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 642 643/* 644 * Conexant 645 * 646 * Ok, the truth is, I don't have any idea at all whether 647 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 648 * place that tell me it is "Venice" is from its Windows driver INF. 649 * 650 * Venice - CX????? 651 * Waikiki - CX20551-22 652 */ 653#define CONEXANT_VENDORID 0x14f1 654#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 655#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 656#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 657 658/* VIA */ 659#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 660#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 661#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 662#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 663#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 664#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 665#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 666#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 667#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 668#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 669#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 670#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 671#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 672 673/* ATI */ 674#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 675 676/* NVIDIA */ 677#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 678 679/* INTEL */ 680#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 681 682/* Codecs */ 683static const struct { 684 uint32_t id; 685 char *name; 686} hdac_codecs[] = { 687 { HDA_CODEC_ALC260, "Realtek ALC260" }, 688 { HDA_CODEC_ALC262, "Realtek ALC262" }, 689 { HDA_CODEC_ALC267, "Realtek ALC267" }, 690 { HDA_CODEC_ALC268, "Realtek ALC268" }, 691 { HDA_CODEC_ALC269, "Realtek ALC269" }, 692 { HDA_CODEC_ALC272, "Realtek ALC272" }, 693 { HDA_CODEC_ALC660, "Realtek ALC660" }, 694 { HDA_CODEC_ALC662, "Realtek ALC662" }, 695 { HDA_CODEC_ALC663, "Realtek ALC663" }, 696 { HDA_CODEC_ALC861, "Realtek ALC861" }, 697 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 698 { HDA_CODEC_ALC880, "Realtek ALC880" }, 699 { HDA_CODEC_ALC882, "Realtek ALC882" }, 700 { HDA_CODEC_ALC883, "Realtek ALC883" }, 701 { HDA_CODEC_ALC885, "Realtek ALC885" }, 702 { HDA_CODEC_ALC888, "Realtek ALC888" }, 703 { HDA_CODEC_ALC889, "Realtek ALC889" }, 704 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 705 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 706 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 707 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 708 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 709 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 710 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 711 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 712 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 713 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 714 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 715 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 716 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 717 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 718 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 719 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 720 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 721 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 722 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 723 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 724 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 725 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 726 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 727 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 728 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 729 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 730 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 731 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 732 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 733 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 734 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 735 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 736 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 737 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 738 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 739 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 740 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 741 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 742 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 743 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 744 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 745 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 746 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 747 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 748 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 749 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 750 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 751 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 752 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 753 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 754 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 755 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 756 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 757 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 758 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 759 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 760 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 761 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 762 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 763 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 764 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 765 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 766 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 767 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 768 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 769 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 770 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 771 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 772 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 773 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 774 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 775 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 776 /* Unknown codec */ 777 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 778 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 779 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 780 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 781 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 782 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 783 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 784 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 785 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 786 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 787 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 788 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 789}; 790#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 791 792 793/**************************************************************************** 794 * Function prototypes 795 ****************************************************************************/ 796static void hdac_intr_handler(void *); 797static int hdac_reset(struct hdac_softc *, int); 798static int hdac_get_capabilities(struct hdac_softc *); 799static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 800static int hdac_dma_alloc(struct hdac_softc *, 801 struct hdac_dma *, bus_size_t); 802static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 803static int hdac_mem_alloc(struct hdac_softc *); 804static void hdac_mem_free(struct hdac_softc *); 805static int hdac_irq_alloc(struct hdac_softc *); 806static void hdac_irq_free(struct hdac_softc *); 807static void hdac_corb_init(struct hdac_softc *); 808static void hdac_rirb_init(struct hdac_softc *); 809static void hdac_corb_start(struct hdac_softc *); 810static void hdac_rirb_start(struct hdac_softc *); 811static void hdac_scan_codecs(struct hdac_softc *); 812static void hdac_probe_codec(struct hdac_codec *); 813static void hdac_probe_function(struct hdac_codec *, nid_t); 814static int hdac_pcmchannel_setup(struct hdac_chan *); 815 816static void hdac_attach2(void *); 817 818static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 819 uint32_t, int); 820static void hdac_command_send_internal(struct hdac_softc *, 821 struct hdac_command_list *, int); 822 823static int hdac_probe(device_t); 824static int hdac_attach(device_t); 825static int hdac_detach(device_t); 826static int hdac_suspend(device_t); 827static int hdac_resume(device_t); 828static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 829static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 830 uint32_t, int, int); 831static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 832 nid_t, int, int, int); 833static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 834 nid_t, nid_t, int, int, int, int, int, int); 835static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 836 837static int hdac_rirb_flush(struct hdac_softc *sc); 838static int hdac_unsolq_flush(struct hdac_softc *sc); 839 840static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 841 842#define hdac_command(a1, a2, a3) \ 843 hdac_command_sendone_internal(a1, a2, a3) 844 845#define hdac_codec_id(c) \ 846 ((uint32_t)((c == NULL) ? 0x00000000 : \ 847 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 848 ((uint32_t)(c)->device_id & 0x0000ffff)))) 849 850static char * 851hdac_codec_name(struct hdac_codec *codec) 852{ 853 uint32_t id; 854 int i; 855 856 id = hdac_codec_id(codec); 857 858 for (i = 0; i < HDAC_CODECS_LEN; i++) { 859 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 860 return (hdac_codecs[i].name); 861 } 862 863 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 864} 865 866static char * 867hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 868{ 869 static char *ossname[] = SOUND_DEVICE_NAMES; 870 int i, first = 1; 871 872 bzero(buf, len); 873 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 874 if (mask & (1 << i)) { 875 if (first == 0) 876 strlcat(buf, ", ", len); 877 strlcat(buf, ossname[i], len); 878 first = 0; 879 } 880 } 881 return (buf); 882} 883 884static struct hdac_audio_ctl * 885hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 886{ 887 if (devinfo == NULL || 888 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 889 index == NULL || devinfo->function.audio.ctl == NULL || 890 devinfo->function.audio.ctlcnt < 1 || 891 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 892 return (NULL); 893 return (&devinfo->function.audio.ctl[(*index)++]); 894} 895 896static struct hdac_audio_ctl * 897hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 898 int index, int cnt) 899{ 900 struct hdac_audio_ctl *ctl; 901 int i, found = 0; 902 903 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 904 return (NULL); 905 906 i = 0; 907 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 908 if (ctl->enable == 0) 909 continue; 910 if (ctl->widget->nid != nid) 911 continue; 912 if (dir && ctl->ndir != dir) 913 continue; 914 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 915 ctl->dir == ctl->ndir && ctl->index != index) 916 continue; 917 found++; 918 if (found == cnt || cnt <= 0) 919 return (ctl); 920 } 921 922 return (NULL); 923} 924 925/* 926 * Jack detection (Speaker/HP redirection) event handler. 927 */ 928static void 929hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 930{ 931 struct hdac_audio_as *as; 932 struct hdac_softc *sc; 933 struct hdac_widget *w; 934 struct hdac_audio_ctl *ctl; 935 uint32_t val, res; 936 int i, j; 937 nid_t cad; 938 939 if (devinfo == NULL || devinfo->codec == NULL || 940 devinfo->codec->sc == NULL) 941 return; 942 943 sc = devinfo->codec->sc; 944 cad = devinfo->codec->cad; 945 as = devinfo->function.audio.as; 946 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 947 if (as[i].hpredir < 0) 948 continue; 949 950 w = hdac_widget_get(devinfo, as[i].pins[15]); 951 if (w == NULL || w->enable == 0 || w->type != 952 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 953 continue; 954 955 res = hdac_command(sc, 956 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 957 958 HDA_BOOTVERBOSE( 959 device_printf(sc->dev, 960 "Pin sense: nid=%d res=0x%08x\n", 961 as[i].pins[15], res); 962 ); 963 964 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 965 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 966 res ^= 1; 967 968 /* (Un)Mute headphone pin. */ 969 ctl = hdac_audio_ctl_amp_get(devinfo, 970 as[i].pins[15], HDA_CTL_IN, -1, 1); 971 if (ctl != NULL && ctl->mute) { 972 /* If pin has muter - use it. */ 973 val = (res != 0) ? 0 : 1; 974 if (val != ctl->forcemute) { 975 ctl->forcemute = val; 976 hdac_audio_ctl_amp_set(ctl, 977 HDA_AMP_MUTE_DEFAULT, 978 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 979 } 980 } else { 981 /* If there is no muter - disable pin output. */ 982 w = hdac_widget_get(devinfo, as[i].pins[15]); 983 if (w != NULL && w->type == 984 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 985 if (res != 0) 986 val = w->wclass.pin.ctrl | 987 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 988 else 989 val = w->wclass.pin.ctrl & 990 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 991 if (val != w->wclass.pin.ctrl) { 992 w->wclass.pin.ctrl = val; 993 hdac_command(sc, 994 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 995 w->nid, w->wclass.pin.ctrl), cad); 996 } 997 } 998 } 999 /* (Un)Mute other pins. */ 1000 for (j = 0; j < 15; j++) { 1001 if (as[i].pins[j] <= 0) 1002 continue; 1003 ctl = hdac_audio_ctl_amp_get(devinfo, 1004 as[i].pins[j], HDA_CTL_IN, -1, 1); 1005 if (ctl != NULL && ctl->mute) { 1006 /* If pin has muter - use it. */ 1007 val = (res != 0) ? 1 : 0; 1008 if (val == ctl->forcemute) 1009 continue; 1010 ctl->forcemute = val; 1011 hdac_audio_ctl_amp_set(ctl, 1012 HDA_AMP_MUTE_DEFAULT, 1013 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1014 continue; 1015 } 1016 /* If there is no muter - disable pin output. */ 1017 w = hdac_widget_get(devinfo, as[i].pins[j]); 1018 if (w != NULL && w->type == 1019 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1020 if (res != 0) 1021 val = w->wclass.pin.ctrl & 1022 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1023 else 1024 val = w->wclass.pin.ctrl | 1025 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1026 if (val != w->wclass.pin.ctrl) { 1027 w->wclass.pin.ctrl = val; 1028 hdac_command(sc, 1029 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1030 w->nid, w->wclass.pin.ctrl), cad); 1031 } 1032 } 1033 } 1034 } 1035} 1036 1037/* 1038 * Callback for poll based jack detection. 1039 */ 1040static void 1041hdac_jack_poll_callback(void *arg) 1042{ 1043 struct hdac_devinfo *devinfo = arg; 1044 struct hdac_softc *sc; 1045 1046 if (devinfo == NULL || devinfo->codec == NULL || 1047 devinfo->codec->sc == NULL) 1048 return; 1049 sc = devinfo->codec->sc; 1050 hdac_lock(sc); 1051 if (sc->poll_ival == 0) { 1052 hdac_unlock(sc); 1053 return; 1054 } 1055 hdac_hp_switch_handler(devinfo); 1056 callout_reset(&sc->poll_jack, sc->poll_ival, 1057 hdac_jack_poll_callback, devinfo); 1058 hdac_unlock(sc); 1059} 1060 1061/* 1062 * Jack detection initializer. 1063 */ 1064static void 1065hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1066{ 1067 struct hdac_softc *sc = devinfo->codec->sc; 1068 struct hdac_audio_as *as = devinfo->function.audio.as; 1069 struct hdac_widget *w; 1070 uint32_t id; 1071 int i, enable = 0, poll = 0; 1072 nid_t cad; 1073 1074 id = hdac_codec_id(devinfo->codec); 1075 cad = devinfo->codec->cad; 1076 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1077 if (as[i].hpredir < 0) 1078 continue; 1079 1080 w = hdac_widget_get(devinfo, as[i].pins[15]); 1081 if (w == NULL || w->enable == 0 || w->type != 1082 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1083 continue; 1084 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1085 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1086 device_printf(sc->dev, 1087 "No jack detection support at pin %d\n", 1088 as[i].pins[15]); 1089 continue; 1090 } 1091 enable = 1; 1092 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1093 hdac_command(sc, 1094 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1095 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1096 HDAC_UNSOLTAG_EVENT_HP), cad); 1097 } else 1098 poll = 1; 1099 HDA_BOOTVERBOSE( 1100 device_printf(sc->dev, 1101 "Enabling headphone/speaker " 1102 "audio routing switching:\n"); 1103 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1104 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1105 ); 1106 } 1107 if (enable) { 1108 hdac_hp_switch_handler(devinfo); 1109 if (poll) { 1110 callout_reset(&sc->poll_jack, 1, 1111 hdac_jack_poll_callback, devinfo); 1112 } 1113 } 1114} 1115 1116/* 1117 * Unsolicited messages handler. 1118 */ 1119static void 1120hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1121{ 1122 struct hdac_softc *sc; 1123 struct hdac_devinfo *devinfo = NULL; 1124 int i; 1125 1126 if (codec == NULL || codec->sc == NULL) 1127 return; 1128 1129 sc = codec->sc; 1130 1131 HDA_BOOTVERBOSE( 1132 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1133 ); 1134 1135 for (i = 0; i < codec->num_fgs; i++) { 1136 if (codec->fgs[i].node_type == 1137 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1138 devinfo = &codec->fgs[i]; 1139 break; 1140 } 1141 } 1142 1143 if (devinfo == NULL) 1144 return; 1145 1146 switch (tag) { 1147 case HDAC_UNSOLTAG_EVENT_HP: 1148 hdac_hp_switch_handler(devinfo); 1149 break; 1150 default: 1151 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1152 break; 1153 } 1154} 1155 1156static int 1157hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1158{ 1159 /* XXX to be removed */ 1160#ifdef HDAC_INTR_EXTRA 1161 uint32_t res; 1162#endif 1163 1164 if (!(ch->flags & HDAC_CHN_RUNNING)) 1165 return (0); 1166 1167 /* XXX to be removed */ 1168#ifdef HDAC_INTR_EXTRA 1169 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1170#endif 1171 1172 /* XXX to be removed */ 1173#ifdef HDAC_INTR_EXTRA 1174 HDA_BOOTVERBOSE( 1175 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1176 device_printf(ch->pdevinfo->dev, 1177 "PCMDIR_%s intr triggered beyond stream boundary:" 1178 "%08x\n", 1179 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1180 ); 1181#endif 1182 1183 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1184 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1185 1186 /* XXX to be removed */ 1187#ifdef HDAC_INTR_EXTRA 1188 if (res & HDAC_SDSTS_BCIS) { 1189#endif 1190 return (1); 1191 /* XXX to be removed */ 1192#ifdef HDAC_INTR_EXTRA 1193 } 1194#endif 1195 1196 return (0); 1197} 1198 1199/**************************************************************************** 1200 * void hdac_intr_handler(void *) 1201 * 1202 * Interrupt handler. Processes interrupts received from the hdac. 1203 ****************************************************************************/ 1204static void 1205hdac_intr_handler(void *context) 1206{ 1207 struct hdac_softc *sc; 1208 uint32_t intsts; 1209 uint8_t rirbsts; 1210 struct hdac_rirb *rirb_base; 1211 uint32_t trigger; 1212 int i; 1213 1214 sc = (struct hdac_softc *)context; 1215 1216 hdac_lock(sc); 1217 if (sc->polling != 0) { 1218 hdac_unlock(sc); 1219 return; 1220 } 1221 1222 /* Do we have anything to do? */ 1223 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1224 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1225 hdac_unlock(sc); 1226 return; 1227 } 1228 1229 trigger = 0; 1230 1231 /* Was this a controller interrupt? */ 1232 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1233 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1234 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1235 /* Get as many responses that we can */ 1236 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1237 HDAC_WRITE_1(&sc->mem, 1238 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1239 if (hdac_rirb_flush(sc) != 0) 1240 trigger |= HDAC_TRIGGER_UNSOL; 1241 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1242 } 1243 /* XXX to be removed */ 1244 /* Clear interrupt and exit */ 1245#ifdef HDAC_INTR_EXTRA 1246 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1247#endif 1248 } 1249 1250 if (intsts & HDAC_INTSTS_SIS_MASK) { 1251 for (i = 0; i < sc->num_chans; i++) { 1252 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1253 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1254 trigger |= (1 << i); 1255 } 1256 /* XXX to be removed */ 1257#ifdef HDAC_INTR_EXTRA 1258 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1259 HDAC_INTSTS_SIS_MASK); 1260#endif 1261 } 1262 1263 hdac_unlock(sc); 1264 1265 for (i = 0; i < sc->num_chans; i++) { 1266 if (trigger & (1 << i)) 1267 chn_intr(sc->chans[i].c); 1268 } 1269 if (trigger & HDAC_TRIGGER_UNSOL) 1270 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1271} 1272 1273/**************************************************************************** 1274 * int hdac_reset(hdac_softc *, int) 1275 * 1276 * Reset the hdac to a quiescent and known state. 1277 ****************************************************************************/ 1278static int 1279hdac_reset(struct hdac_softc *sc, int wakeup) 1280{ 1281 uint32_t gctl; 1282 int count, i; 1283 1284 /* 1285 * Stop all Streams DMA engine 1286 */ 1287 for (i = 0; i < sc->num_iss; i++) 1288 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1289 for (i = 0; i < sc->num_oss; i++) 1290 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1291 for (i = 0; i < sc->num_bss; i++) 1292 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1293 1294 /* 1295 * Stop Control DMA engines. 1296 */ 1297 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1298 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1299 1300 /* 1301 * Reset DMA position buffer. 1302 */ 1303 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1304 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1305 1306 /* 1307 * Reset the controller. The reset must remain asserted for 1308 * a minimum of 100us. 1309 */ 1310 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1311 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1312 count = 10000; 1313 do { 1314 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1315 if (!(gctl & HDAC_GCTL_CRST)) 1316 break; 1317 DELAY(10); 1318 } while (--count); 1319 if (gctl & HDAC_GCTL_CRST) { 1320 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1321 return (ENXIO); 1322 } 1323 1324 /* If wakeup is not requested - leave the controller in reset state. */ 1325 if (!wakeup) 1326 return (0); 1327 1328 DELAY(100); 1329 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1330 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1331 count = 10000; 1332 do { 1333 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1334 if (gctl & HDAC_GCTL_CRST) 1335 break; 1336 DELAY(10); 1337 } while (--count); 1338 if (!(gctl & HDAC_GCTL_CRST)) { 1339 device_printf(sc->dev, "Device stuck in reset\n"); 1340 return (ENXIO); 1341 } 1342 1343 /* 1344 * Wait for codecs to finish their own reset sequence. The delay here 1345 * should be of 250us but for some reasons, on it's not enough on my 1346 * computer. Let's use twice as much as necessary to make sure that 1347 * it's reset properly. 1348 */ 1349 DELAY(1000); 1350 1351 return (0); 1352} 1353 1354 1355/**************************************************************************** 1356 * int hdac_get_capabilities(struct hdac_softc *); 1357 * 1358 * Retreive the general capabilities of the hdac; 1359 * Number of Input Streams 1360 * Number of Output Streams 1361 * Number of bidirectional Streams 1362 * 64bit ready 1363 * CORB and RIRB sizes 1364 ****************************************************************************/ 1365static int 1366hdac_get_capabilities(struct hdac_softc *sc) 1367{ 1368 uint16_t gcap; 1369 uint8_t corbsize, rirbsize; 1370 1371 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1372 sc->num_iss = HDAC_GCAP_ISS(gcap); 1373 sc->num_oss = HDAC_GCAP_OSS(gcap); 1374 sc->num_bss = HDAC_GCAP_BSS(gcap); 1375 1376 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1377 1378 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1379 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1380 HDAC_CORBSIZE_CORBSZCAP_256) 1381 sc->corb_size = 256; 1382 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1383 HDAC_CORBSIZE_CORBSZCAP_16) 1384 sc->corb_size = 16; 1385 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1386 HDAC_CORBSIZE_CORBSZCAP_2) 1387 sc->corb_size = 2; 1388 else { 1389 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1390 __func__, corbsize); 1391 return (ENXIO); 1392 } 1393 1394 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1395 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1396 HDAC_RIRBSIZE_RIRBSZCAP_256) 1397 sc->rirb_size = 256; 1398 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1399 HDAC_RIRBSIZE_RIRBSZCAP_16) 1400 sc->rirb_size = 16; 1401 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1402 HDAC_RIRBSIZE_RIRBSZCAP_2) 1403 sc->rirb_size = 2; 1404 else { 1405 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1406 __func__, rirbsize); 1407 return (ENXIO); 1408 } 1409 1410 HDA_BOOTHVERBOSE( 1411 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1412 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1413 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1414 sc->num_iss, sc->num_oss, sc->num_bss); 1415 ); 1416 1417 return (0); 1418} 1419 1420 1421/**************************************************************************** 1422 * void hdac_dma_cb 1423 * 1424 * This function is called by bus_dmamap_load when the mapping has been 1425 * established. We just record the physical address of the mapping into 1426 * the struct hdac_dma passed in. 1427 ****************************************************************************/ 1428static void 1429hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1430{ 1431 struct hdac_dma *dma; 1432 1433 if (error == 0) { 1434 dma = (struct hdac_dma *)callback_arg; 1435 dma->dma_paddr = segs[0].ds_addr; 1436 } 1437} 1438 1439 1440/**************************************************************************** 1441 * int hdac_dma_alloc 1442 * 1443 * This function allocate and setup a dma region (struct hdac_dma). 1444 * It must be freed by a corresponding hdac_dma_free. 1445 ****************************************************************************/ 1446static int 1447hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1448{ 1449 bus_size_t roundsz; 1450 int result; 1451 int lowaddr; 1452 1453 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1454 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1455 BUS_SPACE_MAXADDR_32BIT; 1456 bzero(dma, sizeof(*dma)); 1457 1458 /* 1459 * Create a DMA tag 1460 */ 1461 result = bus_dma_tag_create(NULL, /* parent */ 1462 HDAC_DMA_ALIGNMENT, /* alignment */ 1463 0, /* boundary */ 1464 lowaddr, /* lowaddr */ 1465 BUS_SPACE_MAXADDR, /* highaddr */ 1466 NULL, /* filtfunc */ 1467 NULL, /* fistfuncarg */ 1468 roundsz, /* maxsize */ 1469 1, /* nsegments */ 1470 roundsz, /* maxsegsz */ 1471 0, /* flags */ 1472 NULL, /* lockfunc */ 1473 NULL, /* lockfuncarg */ 1474 &dma->dma_tag); /* dmat */ 1475 if (result != 0) { 1476 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1477 __func__, result); 1478 goto hdac_dma_alloc_fail; 1479 } 1480 1481 /* 1482 * Allocate DMA memory 1483 */ 1484 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1485 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1486 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1487 &dma->dma_map); 1488 if (result != 0) { 1489 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1490 __func__, result); 1491 goto hdac_dma_alloc_fail; 1492 } 1493 1494 dma->dma_size = roundsz; 1495 1496 /* 1497 * Map the memory 1498 */ 1499 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1500 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1501 if (result != 0 || dma->dma_paddr == 0) { 1502 if (result == 0) 1503 result = ENOMEM; 1504 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1505 __func__, result); 1506 goto hdac_dma_alloc_fail; 1507 } 1508 1509 HDA_BOOTHVERBOSE( 1510 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1511 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1512 ); 1513 1514 return (0); 1515 1516hdac_dma_alloc_fail: 1517 hdac_dma_free(sc, dma); 1518 1519 return (result); 1520} 1521 1522 1523/**************************************************************************** 1524 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1525 * 1526 * Free a struct dhac_dma that has been previously allocated via the 1527 * hdac_dma_alloc function. 1528 ****************************************************************************/ 1529static void 1530hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1531{ 1532 if (dma->dma_map != NULL) { 1533#if 0 1534 /* Flush caches */ 1535 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1536 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1537#endif 1538 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1539 } 1540 if (dma->dma_vaddr != NULL) { 1541 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1542 dma->dma_vaddr = NULL; 1543 } 1544 dma->dma_map = NULL; 1545 if (dma->dma_tag != NULL) { 1546 bus_dma_tag_destroy(dma->dma_tag); 1547 dma->dma_tag = NULL; 1548 } 1549 dma->dma_size = 0; 1550} 1551 1552/**************************************************************************** 1553 * int hdac_mem_alloc(struct hdac_softc *) 1554 * 1555 * Allocate all the bus resources necessary to speak with the physical 1556 * controller. 1557 ****************************************************************************/ 1558static int 1559hdac_mem_alloc(struct hdac_softc *sc) 1560{ 1561 struct hdac_mem *mem; 1562 1563 mem = &sc->mem; 1564 mem->mem_rid = PCIR_BAR(0); 1565 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1566 &mem->mem_rid, RF_ACTIVE); 1567 if (mem->mem_res == NULL) { 1568 device_printf(sc->dev, 1569 "%s: Unable to allocate memory resource\n", __func__); 1570 return (ENOMEM); 1571 } 1572 mem->mem_tag = rman_get_bustag(mem->mem_res); 1573 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1574 1575 return (0); 1576} 1577 1578/**************************************************************************** 1579 * void hdac_mem_free(struct hdac_softc *) 1580 * 1581 * Free up resources previously allocated by hdac_mem_alloc. 1582 ****************************************************************************/ 1583static void 1584hdac_mem_free(struct hdac_softc *sc) 1585{ 1586 struct hdac_mem *mem; 1587 1588 mem = &sc->mem; 1589 if (mem->mem_res != NULL) 1590 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1591 mem->mem_res); 1592 mem->mem_res = NULL; 1593} 1594 1595/**************************************************************************** 1596 * int hdac_irq_alloc(struct hdac_softc *) 1597 * 1598 * Allocate and setup the resources necessary for interrupt handling. 1599 ****************************************************************************/ 1600static int 1601hdac_irq_alloc(struct hdac_softc *sc) 1602{ 1603 struct hdac_irq *irq; 1604 int result; 1605 1606 irq = &sc->irq; 1607 irq->irq_rid = 0x0; 1608 1609#ifdef HDAC_MSI_ENABLED 1610 if ((sc->flags & HDAC_F_MSI) && 1611 (result = pci_msi_count(sc->dev)) == 1 && 1612 pci_alloc_msi(sc->dev, &result) == 0) 1613 irq->irq_rid = 0x1; 1614 else 1615#endif 1616 sc->flags &= ~HDAC_F_MSI; 1617 1618 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1619 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1620 if (irq->irq_res == NULL) { 1621 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1622 __func__); 1623 goto hdac_irq_alloc_fail; 1624 } 1625 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1626 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1627 if (result != 0) { 1628 device_printf(sc->dev, 1629 "%s: Unable to setup interrupt handler (%x)\n", 1630 __func__, result); 1631 goto hdac_irq_alloc_fail; 1632 } 1633 1634 return (0); 1635 1636hdac_irq_alloc_fail: 1637 hdac_irq_free(sc); 1638 1639 return (ENXIO); 1640} 1641 1642/**************************************************************************** 1643 * void hdac_irq_free(struct hdac_softc *) 1644 * 1645 * Free up resources previously allocated by hdac_irq_alloc. 1646 ****************************************************************************/ 1647static void 1648hdac_irq_free(struct hdac_softc *sc) 1649{ 1650 struct hdac_irq *irq; 1651 1652 irq = &sc->irq; 1653 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1654 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1655 if (irq->irq_res != NULL) 1656 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1657 irq->irq_res); 1658#ifdef HDAC_MSI_ENABLED 1659 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1660 pci_release_msi(sc->dev); 1661#endif 1662 irq->irq_handle = NULL; 1663 irq->irq_res = NULL; 1664 irq->irq_rid = 0x0; 1665} 1666 1667/**************************************************************************** 1668 * void hdac_corb_init(struct hdac_softc *) 1669 * 1670 * Initialize the corb registers for operations but do not start it up yet. 1671 * The CORB engine must not be running when this function is called. 1672 ****************************************************************************/ 1673static void 1674hdac_corb_init(struct hdac_softc *sc) 1675{ 1676 uint8_t corbsize; 1677 uint64_t corbpaddr; 1678 1679 /* Setup the CORB size. */ 1680 switch (sc->corb_size) { 1681 case 256: 1682 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1683 break; 1684 case 16: 1685 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1686 break; 1687 case 2: 1688 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1689 break; 1690 default: 1691 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1692 } 1693 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1694 1695 /* Setup the CORB Address in the hdac */ 1696 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1697 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1698 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1699 1700 /* Set the WP and RP */ 1701 sc->corb_wp = 0; 1702 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1703 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1704 /* 1705 * The HDA specification indicates that the CORBRPRST bit will always 1706 * read as zero. Unfortunately, it seems that at least the 82801G 1707 * doesn't reset the bit to zero, which stalls the corb engine. 1708 * manually reset the bit to zero before continuing. 1709 */ 1710 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1711 1712 /* Enable CORB error reporting */ 1713#if 0 1714 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1715#endif 1716} 1717 1718/**************************************************************************** 1719 * void hdac_rirb_init(struct hdac_softc *) 1720 * 1721 * Initialize the rirb registers for operations but do not start it up yet. 1722 * The RIRB engine must not be running when this function is called. 1723 ****************************************************************************/ 1724static void 1725hdac_rirb_init(struct hdac_softc *sc) 1726{ 1727 uint8_t rirbsize; 1728 uint64_t rirbpaddr; 1729 1730 /* Setup the RIRB size. */ 1731 switch (sc->rirb_size) { 1732 case 256: 1733 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1734 break; 1735 case 16: 1736 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1737 break; 1738 case 2: 1739 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1740 break; 1741 default: 1742 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1743 } 1744 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1745 1746 /* Setup the RIRB Address in the hdac */ 1747 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1748 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1749 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1750 1751 /* Setup the WP and RP */ 1752 sc->rirb_rp = 0; 1753 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1754 1755 /* Setup the interrupt threshold */ 1756 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1757 1758 /* Enable Overrun and response received reporting */ 1759#if 0 1760 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1761 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1762#else 1763 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1764#endif 1765 1766#if 0 1767 /* 1768 * Make sure that the Host CPU cache doesn't contain any dirty 1769 * cache lines that falls in the rirb. If I understood correctly, it 1770 * should be sufficient to do this only once as the rirb is purely 1771 * read-only from now on. 1772 */ 1773 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1774 BUS_DMASYNC_PREREAD); 1775#endif 1776} 1777 1778/**************************************************************************** 1779 * void hdac_corb_start(hdac_softc *) 1780 * 1781 * Startup the corb DMA engine 1782 ****************************************************************************/ 1783static void 1784hdac_corb_start(struct hdac_softc *sc) 1785{ 1786 uint32_t corbctl; 1787 1788 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1789 corbctl |= HDAC_CORBCTL_CORBRUN; 1790 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1791} 1792 1793/**************************************************************************** 1794 * void hdac_rirb_start(hdac_softc *) 1795 * 1796 * Startup the rirb DMA engine 1797 ****************************************************************************/ 1798static void 1799hdac_rirb_start(struct hdac_softc *sc) 1800{ 1801 uint32_t rirbctl; 1802 1803 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1804 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1805 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1806} 1807 1808 1809/**************************************************************************** 1810 * void hdac_scan_codecs(struct hdac_softc *, int) 1811 * 1812 * Scan the bus for available codecs, starting with num. 1813 ****************************************************************************/ 1814static void 1815hdac_scan_codecs(struct hdac_softc *sc) 1816{ 1817 struct hdac_codec *codec; 1818 int i; 1819 uint16_t statests; 1820 1821 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1822 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1823 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1824 /* We have found a codec. */ 1825 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1826 M_HDAC, M_ZERO | M_NOWAIT); 1827 if (codec == NULL) { 1828 device_printf(sc->dev, 1829 "Unable to allocate memory for codec\n"); 1830 continue; 1831 } 1832 codec->commands = NULL; 1833 codec->responses_received = 0; 1834 codec->verbs_sent = 0; 1835 codec->sc = sc; 1836 codec->cad = i; 1837 sc->codecs[i] = codec; 1838 hdac_probe_codec(codec); 1839 } 1840 } 1841 /* All codecs have been probed, now try to attach drivers to them */ 1842 /* bus_generic_attach(sc->dev); */ 1843} 1844 1845/**************************************************************************** 1846 * void hdac_probe_codec(struct hdac_softc *, int) 1847 * 1848 * Probe a the given codec_id for available function groups. 1849 ****************************************************************************/ 1850static void 1851hdac_probe_codec(struct hdac_codec *codec) 1852{ 1853 struct hdac_softc *sc = codec->sc; 1854 uint32_t vendorid, revisionid, subnode; 1855 int startnode; 1856 int endnode; 1857 int i; 1858 nid_t cad = codec->cad; 1859 1860 HDA_BOOTVERBOSE( 1861 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1862 ); 1863 vendorid = hdac_command(sc, 1864 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1865 cad); 1866 revisionid = hdac_command(sc, 1867 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1868 cad); 1869 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1870 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1871 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1872 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1873 1874 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1875 device_printf(sc->dev, "Codec #%d is not responding!" 1876 " Probing aborted.\n", cad); 1877 return; 1878 } 1879 1880 device_printf(sc->dev, "HDA Codec #%d: %s\n", 1881 cad, hdac_codec_name(codec)); 1882 HDA_BOOTVERBOSE( 1883 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 1884 hdac_codec_id(codec)); 1885 device_printf(sc->dev, " Vendor: 0x%04x\n", 1886 codec->vendor_id); 1887 device_printf(sc->dev, " Device: 0x%04x\n", 1888 codec->device_id); 1889 device_printf(sc->dev, " Revision: 0x%02x\n", 1890 codec->revision_id); 1891 device_printf(sc->dev, " Stepping: 0x%02x\n", 1892 codec->stepping_id); 1893 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1894 sc->pci_subvendor); 1895 ); 1896 subnode = hdac_command(sc, 1897 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1898 cad); 1899 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1900 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1901 1902 HDA_BOOTHVERBOSE( 1903 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1904 startnode, endnode); 1905 ); 1906 1907 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1908 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1909 if (codec->fgs == NULL) { 1910 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1911 __func__); 1912 return; 1913 } 1914 1915 for (i = startnode; i < endnode; i++) 1916 hdac_probe_function(codec, i); 1917 return; 1918} 1919 1920/* 1921 * Probe codec function and add it to the list. 1922 */ 1923static void 1924hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1925{ 1926 struct hdac_softc *sc = codec->sc; 1927 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1928 uint32_t fctgrptype; 1929 uint32_t res; 1930 nid_t cad = codec->cad; 1931 1932 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1933 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1934 1935 devinfo->nid = nid; 1936 devinfo->node_type = fctgrptype; 1937 devinfo->codec = codec; 1938 1939 res = hdac_command(sc, 1940 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1941 1942 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1943 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1944 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1945 1946 HDA_BOOTVERBOSE( 1947 device_printf(sc->dev, 1948 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1949 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1950 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1951 "unknown", nid, devinfo->startnode, devinfo->endnode, 1952 devinfo->nodecnt); 1953 ); 1954 1955 if (devinfo->nodecnt > 0) 1956 devinfo->widget = (struct hdac_widget *)malloc( 1957 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1958 M_NOWAIT | M_ZERO); 1959 else 1960 devinfo->widget = NULL; 1961 1962 if (devinfo->widget == NULL) { 1963 device_printf(sc->dev, "unable to allocate widgets!\n"); 1964 devinfo->endnode = devinfo->startnode; 1965 devinfo->nodecnt = 0; 1966 return; 1967 } 1968 1969 codec->num_fgs++; 1970} 1971 1972static void 1973hdac_widget_connection_parse(struct hdac_widget *w) 1974{ 1975 struct hdac_softc *sc = w->devinfo->codec->sc; 1976 uint32_t res; 1977 int i, j, max, ents, entnum; 1978 nid_t cad = w->devinfo->codec->cad; 1979 nid_t nid = w->nid; 1980 nid_t cnid, addcnid, prevcnid; 1981 1982 w->nconns = 0; 1983 1984 res = hdac_command(sc, 1985 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1986 1987 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1988 1989 if (ents < 1) 1990 return; 1991 1992 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1993 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1994 prevcnid = 0; 1995 1996#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1997#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1998#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1999#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2000#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2001 2002 for (i = 0; i < ents; i += entnum) { 2003 res = hdac_command(sc, 2004 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2005 for (j = 0; j < entnum; j++) { 2006 cnid = CONN_CNID(res, entnum, j); 2007 if (cnid == 0) { 2008 if (w->nconns < ents) 2009 device_printf(sc->dev, 2010 "%s: nid=%d WARNING: zero cnid " 2011 "entnum=%d j=%d index=%d " 2012 "entries=%d found=%d res=0x%08x\n", 2013 __func__, nid, entnum, j, i, 2014 ents, w->nconns, res); 2015 else 2016 goto getconns_out; 2017 } 2018 if (cnid < w->devinfo->startnode || 2019 cnid >= w->devinfo->endnode) { 2020 HDA_BOOTVERBOSE( 2021 device_printf(sc->dev, 2022 "GHOST: nid=%d j=%d " 2023 "entnum=%d index=%d res=0x%08x\n", 2024 nid, j, entnum, i, res); 2025 ); 2026 } 2027 if (CONN_RANGE(res, entnum, j) == 0) 2028 addcnid = cnid; 2029 else if (prevcnid == 0 || prevcnid >= cnid) { 2030 device_printf(sc->dev, 2031 "%s: WARNING: Invalid child range " 2032 "nid=%d index=%d j=%d entnum=%d " 2033 "prevcnid=%d cnid=%d res=0x%08x\n", 2034 __func__, nid, i, j, entnum, prevcnid, 2035 cnid, res); 2036 addcnid = cnid; 2037 } else 2038 addcnid = prevcnid + 1; 2039 while (addcnid <= cnid) { 2040 if (w->nconns > max) { 2041 device_printf(sc->dev, 2042 "Adding %d (nid=%d): " 2043 "Max connection reached! max=%d\n", 2044 addcnid, nid, max + 1); 2045 goto getconns_out; 2046 } 2047 w->connsenable[w->nconns] = 1; 2048 w->conns[w->nconns++] = addcnid++; 2049 } 2050 prevcnid = cnid; 2051 } 2052 } 2053 2054getconns_out: 2055 return; 2056} 2057 2058static uint32_t 2059hdac_widget_pin_patch(uint32_t config, const char *str) 2060{ 2061 char buf[256]; 2062 char *key, *value, *rest, *bad; 2063 int ival, i; 2064 2065 strlcpy(buf, str, sizeof(buf)); 2066 rest = buf; 2067 while ((key = strsep(&rest, "=")) != NULL) { 2068 value = strsep(&rest, " \t"); 2069 if (value == NULL) 2070 break; 2071 ival = strtol(value, &bad, 10); 2072 if (strcmp(key, "seq") == 0) { 2073 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2074 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2075 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2076 } else if (strcmp(key, "as") == 0) { 2077 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2078 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2079 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2080 } else if (strcmp(key, "misc") == 0) { 2081 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2082 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2083 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2084 } else if (strcmp(key, "color") == 0) { 2085 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2086 if (bad[0] == 0) { 2087 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2088 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2089 }; 2090 for (i = 0; i < 16; i++) { 2091 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2092 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2093 break; 2094 } 2095 } 2096 } else if (strcmp(key, "ctype") == 0) { 2097 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2098 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2099 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2100 } else if (strcmp(key, "device") == 0) { 2101 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2102 if (bad[0] == 0) { 2103 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2104 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2105 continue; 2106 }; 2107 for (i = 0; i < 16; i++) { 2108 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2109 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2110 break; 2111 } 2112 } 2113 } else if (strcmp(key, "loc") == 0) { 2114 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2115 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2116 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2117 } else if (strcmp(key, "conn") == 0) { 2118 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2119 if (bad[0] == 0) { 2120 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2121 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2122 continue; 2123 }; 2124 for (i = 0; i < 4; i++) { 2125 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2126 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2127 break; 2128 } 2129 } 2130 } 2131 } 2132 return (config); 2133} 2134 2135static uint32_t 2136hdac_widget_pin_getconfig(struct hdac_widget *w) 2137{ 2138 struct hdac_softc *sc; 2139 uint32_t config, orig, id; 2140 nid_t cad, nid; 2141 char buf[32]; 2142 const char *res = NULL, *patch = NULL; 2143 2144 sc = w->devinfo->codec->sc; 2145 cad = w->devinfo->codec->cad; 2146 nid = w->nid; 2147 id = hdac_codec_id(w->devinfo->codec); 2148 2149 config = hdac_command(sc, 2150 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2151 cad); 2152 orig = config; 2153 2154 HDA_BOOTVERBOSE( 2155 hdac_dump_pin_config(w, orig); 2156 ); 2157 2158 /* XXX: Old patches require complete review. 2159 * Now they may create more problem then solve due to 2160 * incorrect associations. 2161 */ 2162 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2163 switch (nid) { 2164 case 26: 2165 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2166 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2167 break; 2168 case 27: 2169 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2170 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2171 break; 2172 default: 2173 break; 2174 } 2175 } else if (id == HDA_CODEC_ALC880 && 2176 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2177 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2178 /* 2179 * Super broken BIOS 2180 */ 2181 switch (nid) { 2182 case 24: /* MIC1 */ 2183 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2184 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2185 break; 2186 case 25: /* XXX MIC2 */ 2187 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2188 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2189 break; 2190 case 26: /* LINE1 */ 2191 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2192 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2193 break; 2194 case 27: /* XXX LINE2 */ 2195 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2196 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2197 break; 2198 case 28: /* CD */ 2199 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2200 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2201 break; 2202 } 2203 } else if (id == HDA_CODEC_ALC883 && 2204 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2205 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2206 switch (nid) { 2207 case 25: 2208 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2209 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2210 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2211 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2212 break; 2213 case 28: 2214 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2215 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2216 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2217 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2218 break; 2219 } 2220 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2221 HP_V3000_SUBVENDOR) { 2222 switch (nid) { 2223 case 18: 2224 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2225 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2226 break; 2227 case 20: 2228 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2229 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2230 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2231 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2232 break; 2233 case 21: 2234 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2235 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2236 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2237 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2238 break; 2239 } 2240 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2241 HP_DV5000_SUBVENDOR) { 2242 switch (nid) { 2243 case 20: 2244 case 21: 2245 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2246 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2247 break; 2248 } 2249 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2250 ASUS_W6F_SUBVENDOR) { 2251 switch (nid) { 2252 case 11: 2253 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2254 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2255 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2256 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2257 break; 2258 case 12: 2259 case 14: 2260 case 16: 2261 case 31: 2262 case 32: 2263 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2264 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2265 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2266 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2267 break; 2268 case 15: 2269 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2270 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2271 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2272 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2273 break; 2274 } 2275 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2276 UNIWILL_9075_SUBVENDOR) { 2277 switch (nid) { 2278 case 15: 2279 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2280 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2281 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2282 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2283 break; 2284 } 2285 } 2286 2287 /* New patches */ 2288 if (id == HDA_CODEC_AD1986A && 2289 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2290 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2291 switch (nid) { 2292 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2293 patch = "device=Line-in as=8 seq=1"; 2294 break; 2295 case 29: 2296 patch = "device=Mic as=8 seq=2"; 2297 break; 2298 case 31: /* Lot of inputs configured with as=15 and unusable */ 2299 patch = "as=8 seq=3"; 2300 break; 2301 case 32: 2302 patch = "as=8 seq=4"; 2303 break; 2304 case 34: 2305 patch = "as=8 seq=5"; 2306 break; 2307 case 36: 2308 patch = "as=8 seq=6"; 2309 break; 2310 } 2311 } else if (id == HDA_CODEC_ALC260 && 2312 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2313 switch (nid) { 2314 case 16: 2315 patch = "seq=15 device=Headphones"; 2316 break; 2317 } 2318 } else if (id == HDA_CODEC_ALC268 && 2319 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2320 switch (nid) { 2321 case 28: 2322 patch = "device=CD conn=fixed"; 2323 break; 2324 } 2325 } 2326 2327 if (patch != NULL) 2328 config = hdac_widget_pin_patch(config, patch); 2329 2330 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2331 if (resource_string_value(device_get_name(sc->dev), 2332 device_get_unit(sc->dev), buf, &res) == 0) { 2333 if (strncmp(res, "0x", 2) == 0) { 2334 config = strtol(res + 2, NULL, 16); 2335 } else { 2336 config = hdac_widget_pin_patch(config, res); 2337 } 2338 } 2339 2340 HDA_BOOTVERBOSE( 2341 if (config != orig) 2342 device_printf(sc->dev, 2343 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2344 nid, orig, config); 2345 ); 2346 2347 return (config); 2348} 2349 2350static uint32_t 2351hdac_widget_pin_getcaps(struct hdac_widget *w) 2352{ 2353 struct hdac_softc *sc; 2354 uint32_t caps, orig, id; 2355 nid_t cad, nid; 2356 2357 sc = w->devinfo->codec->sc; 2358 cad = w->devinfo->codec->cad; 2359 nid = w->nid; 2360 id = hdac_codec_id(w->devinfo->codec); 2361 2362 caps = hdac_command(sc, 2363 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2364 orig = caps; 2365 2366 HDA_BOOTVERBOSE( 2367 if (caps != orig) 2368 device_printf(sc->dev, 2369 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2370 nid, orig, caps); 2371 ); 2372 2373 return (caps); 2374} 2375 2376static void 2377hdac_widget_pin_parse(struct hdac_widget *w) 2378{ 2379 struct hdac_softc *sc = w->devinfo->codec->sc; 2380 uint32_t config, pincap; 2381 const char *devstr, *connstr; 2382 nid_t cad = w->devinfo->codec->cad; 2383 nid_t nid = w->nid; 2384 2385 config = hdac_widget_pin_getconfig(w); 2386 w->wclass.pin.config = config; 2387 2388 pincap = hdac_widget_pin_getcaps(w); 2389 w->wclass.pin.cap = pincap; 2390 2391 w->wclass.pin.ctrl = hdac_command(sc, 2392 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2393 2394 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2395 w->param.eapdbtl = hdac_command(sc, 2396 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2397 w->param.eapdbtl &= 0x7; 2398 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2399 } else 2400 w->param.eapdbtl = HDAC_INVALID; 2401 2402 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2403 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2404 2405 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2406 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2407 2408 strlcat(w->name, ": ", sizeof(w->name)); 2409 strlcat(w->name, devstr, sizeof(w->name)); 2410 strlcat(w->name, " (", sizeof(w->name)); 2411 strlcat(w->name, connstr, sizeof(w->name)); 2412 strlcat(w->name, ")", sizeof(w->name)); 2413} 2414 2415static uint32_t 2416hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2417{ 2418 struct hdac_softc *sc; 2419 uint32_t caps, orig, id; 2420 nid_t cad, nid, beeper = -1; 2421 2422 sc = w->devinfo->codec->sc; 2423 cad = w->devinfo->codec->cad; 2424 nid = w->nid; 2425 id = hdac_codec_id(w->devinfo->codec); 2426 2427 caps = hdac_command(sc, 2428 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2429 cad); 2430 orig = caps; 2431 2432 /* On some codecs beeper is an input pin, but it is not recordable 2433 alone. Also most of BIOSes does not declare beeper pin. 2434 Change beeper pin node type to beeper to help parser. */ 2435 *waspin = 0; 2436 switch (id) { 2437 case HDA_CODEC_AD1988: 2438 case HDA_CODEC_AD1988B: 2439 beeper = 26; 2440 break; 2441 case HDA_CODEC_ALC260: 2442 beeper = 23; 2443 break; 2444 case HDA_CODEC_ALC262: 2445 case HDA_CODEC_ALC268: 2446 case HDA_CODEC_ALC880: 2447 case HDA_CODEC_ALC882: 2448 case HDA_CODEC_ALC883: 2449 case HDA_CODEC_ALC885: 2450 case HDA_CODEC_ALC888: 2451 case HDA_CODEC_ALC889: 2452 beeper = 29; 2453 break; 2454 } 2455 if (nid == beeper) { 2456 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2457 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2458 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2459 *waspin = 1; 2460 } 2461 2462 HDA_BOOTVERBOSE( 2463 if (caps != orig) { 2464 device_printf(sc->dev, 2465 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2466 nid, orig, caps); 2467 } 2468 ); 2469 2470 return (caps); 2471} 2472 2473static void 2474hdac_widget_parse(struct hdac_widget *w) 2475{ 2476 struct hdac_softc *sc = w->devinfo->codec->sc; 2477 uint32_t wcap, cap; 2478 char *typestr; 2479 nid_t cad = w->devinfo->codec->cad; 2480 nid_t nid = w->nid; 2481 2482 wcap = hdac_widget_getcaps(w, &w->waspin); 2483 2484 w->param.widget_cap = wcap; 2485 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2486 2487 switch (w->type) { 2488 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2489 typestr = "audio output"; 2490 break; 2491 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2492 typestr = "audio input"; 2493 break; 2494 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2495 typestr = "audio mixer"; 2496 break; 2497 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2498 typestr = "audio selector"; 2499 break; 2500 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2501 typestr = "pin"; 2502 break; 2503 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2504 typestr = "power widget"; 2505 break; 2506 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2507 typestr = "volume widget"; 2508 break; 2509 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2510 typestr = "beep widget"; 2511 break; 2512 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2513 typestr = "vendor widget"; 2514 break; 2515 default: 2516 typestr = "unknown type"; 2517 break; 2518 } 2519 2520 strlcpy(w->name, typestr, sizeof(w->name)); 2521 2522 hdac_widget_connection_parse(w); 2523 2524 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2525 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2526 w->param.outamp_cap = 2527 hdac_command(sc, 2528 HDA_CMD_GET_PARAMETER(cad, nid, 2529 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2530 else 2531 w->param.outamp_cap = 2532 w->devinfo->function.audio.outamp_cap; 2533 } else 2534 w->param.outamp_cap = 0; 2535 2536 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2537 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2538 w->param.inamp_cap = 2539 hdac_command(sc, 2540 HDA_CMD_GET_PARAMETER(cad, nid, 2541 HDA_PARAM_INPUT_AMP_CAP), cad); 2542 else 2543 w->param.inamp_cap = 2544 w->devinfo->function.audio.inamp_cap; 2545 } else 2546 w->param.inamp_cap = 0; 2547 2548 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2549 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2550 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2551 cap = hdac_command(sc, 2552 HDA_CMD_GET_PARAMETER(cad, nid, 2553 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2554 w->param.supp_stream_formats = (cap != 0) ? cap : 2555 w->devinfo->function.audio.supp_stream_formats; 2556 cap = hdac_command(sc, 2557 HDA_CMD_GET_PARAMETER(cad, nid, 2558 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2559 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2560 w->devinfo->function.audio.supp_pcm_size_rate; 2561 } else { 2562 w->param.supp_stream_formats = 2563 w->devinfo->function.audio.supp_stream_formats; 2564 w->param.supp_pcm_size_rate = 2565 w->devinfo->function.audio.supp_pcm_size_rate; 2566 } 2567 } else { 2568 w->param.supp_stream_formats = 0; 2569 w->param.supp_pcm_size_rate = 0; 2570 } 2571 2572 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2573 hdac_widget_pin_parse(w); 2574} 2575 2576static struct hdac_widget * 2577hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2578{ 2579 if (devinfo == NULL || devinfo->widget == NULL || 2580 nid < devinfo->startnode || nid >= devinfo->endnode) 2581 return (NULL); 2582 return (&devinfo->widget[nid - devinfo->startnode]); 2583} 2584 2585static __inline int 2586hda_poll_channel(struct hdac_chan *ch) 2587{ 2588 uint32_t sz, delta; 2589 volatile uint32_t ptr; 2590 2591 if (!(ch->flags & HDAC_CHN_RUNNING)) 2592 return (0); 2593 2594 sz = ch->blksz * ch->blkcnt; 2595 if (ch->dmapos != NULL) 2596 ptr = *(ch->dmapos); 2597 else 2598 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2599 ch->off + HDAC_SDLPIB); 2600 ch->ptr = ptr; 2601 ptr %= sz; 2602 ptr &= ~(ch->blksz - 1); 2603 delta = (sz + ptr - ch->prevptr) % sz; 2604 2605 if (delta < ch->blksz) 2606 return (0); 2607 2608 ch->prevptr = ptr; 2609 2610 return (1); 2611} 2612 2613static void 2614hda_poll_callback(void *arg) 2615{ 2616 struct hdac_softc *sc = arg; 2617 uint32_t trigger; 2618 int i, active = 0; 2619 2620 if (sc == NULL) 2621 return; 2622 2623 hdac_lock(sc); 2624 if (sc->polling == 0) { 2625 hdac_unlock(sc); 2626 return; 2627 } 2628 2629 trigger = 0; 2630 for (i = 0; i < sc->num_chans; i++) { 2631 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2632 continue; 2633 active = 1; 2634 if (hda_poll_channel(&sc->chans[i])) 2635 trigger |= (1 << i); 2636 } 2637 2638 /* XXX */ 2639 if (active) 2640 callout_reset(&sc->poll_hda, sc->poll_ticks, 2641 hda_poll_callback, sc); 2642 2643 hdac_unlock(sc); 2644 2645 for (i = 0; i < sc->num_chans; i++) { 2646 if (trigger & (1 << i)) 2647 chn_intr(sc->chans[i].c); 2648 } 2649} 2650 2651static int 2652hdac_rirb_flush(struct hdac_softc *sc) 2653{ 2654 struct hdac_rirb *rirb_base, *rirb; 2655 struct hdac_codec *codec; 2656 struct hdac_command_list *commands; 2657 nid_t cad; 2658 uint32_t resp; 2659 uint8_t rirbwp; 2660 int ret; 2661 2662 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2663 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2664#if 0 2665 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2666 BUS_DMASYNC_POSTREAD); 2667#endif 2668 2669 ret = 0; 2670 2671 while (sc->rirb_rp != rirbwp) { 2672 sc->rirb_rp++; 2673 sc->rirb_rp %= sc->rirb_size; 2674 rirb = &rirb_base[sc->rirb_rp]; 2675 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2676 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2677 sc->codecs[cad] == NULL) 2678 continue; 2679 resp = rirb->response; 2680 codec = sc->codecs[cad]; 2681 commands = codec->commands; 2682 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2683 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2684 ((resp >> 26) & 0xffff); 2685 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2686 } else if (commands != NULL && commands->num_commands > 0 && 2687 codec->responses_received < commands->num_commands) 2688 commands->responses[codec->responses_received++] = 2689 resp; 2690 ret++; 2691 } 2692 2693 return (ret); 2694} 2695 2696static int 2697hdac_unsolq_flush(struct hdac_softc *sc) 2698{ 2699 nid_t cad; 2700 uint32_t tag; 2701 int ret = 0; 2702 2703 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2704 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2705 while (sc->unsolq_rp != sc->unsolq_wp) { 2706 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2707 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2708 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2709 hdac_unsolicited_handler(sc->codecs[cad], tag); 2710 ret++; 2711 } 2712 sc->unsolq_st = HDAC_UNSOLQ_READY; 2713 } 2714 2715 return (ret); 2716} 2717 2718static void 2719hdac_poll_callback(void *arg) 2720{ 2721 struct hdac_softc *sc = arg; 2722 if (sc == NULL) 2723 return; 2724 2725 hdac_lock(sc); 2726 if (sc->polling == 0 || sc->poll_ival == 0) { 2727 hdac_unlock(sc); 2728 return; 2729 } 2730 if (hdac_rirb_flush(sc) != 0) 2731 hdac_unsolq_flush(sc); 2732 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2733 hdac_unlock(sc); 2734} 2735 2736static void 2737hdac_poll_reinit(struct hdac_softc *sc) 2738{ 2739 int i, pollticks, min = 1000000; 2740 struct hdac_chan *ch; 2741 2742 for (i = 0; i < sc->num_chans; i++) { 2743 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2744 continue; 2745 ch = &sc->chans[i]; 2746 pollticks = ((uint64_t)hz * ch->blksz) / 2747 ((uint64_t)sndbuf_getbps(ch->b) * 2748 sndbuf_getspd(ch->b)); 2749 pollticks >>= 1; 2750 if (pollticks > hz) 2751 pollticks = hz; 2752 if (pollticks < 1) { 2753 HDA_BOOTVERBOSE( 2754 device_printf(sc->dev, 2755 "%s: pollticks=%d < 1 !\n", 2756 __func__, pollticks); 2757 ); 2758 pollticks = 1; 2759 } 2760 if (min > pollticks) 2761 min = pollticks; 2762 } 2763 HDA_BOOTVERBOSE( 2764 device_printf(sc->dev, 2765 "%s: pollticks %d -> %d\n", 2766 __func__, sc->poll_ticks, min); 2767 ); 2768 sc->poll_ticks = min; 2769 if (min == 1000000) 2770 callout_stop(&sc->poll_hda); 2771 else 2772 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2773} 2774 2775static void 2776hdac_stream_stop(struct hdac_chan *ch) 2777{ 2778 struct hdac_softc *sc = ch->devinfo->codec->sc; 2779 uint32_t ctl; 2780 2781 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2782 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2783 HDAC_SDCTL_RUN); 2784 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2785 2786 ch->flags &= ~HDAC_CHN_RUNNING; 2787 2788 if (sc->polling != 0) 2789 hdac_poll_reinit(sc); 2790 2791 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2792 ctl &= ~(1 << (ch->off >> 5)); 2793 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2794} 2795 2796static void 2797hdac_stream_start(struct hdac_chan *ch) 2798{ 2799 struct hdac_softc *sc = ch->devinfo->codec->sc; 2800 uint32_t ctl; 2801 2802 ch->flags |= HDAC_CHN_RUNNING; 2803 2804 if (sc->polling != 0) 2805 hdac_poll_reinit(sc); 2806 2807 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2808 ctl |= 1 << (ch->off >> 5); 2809 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2810 2811 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2812 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2813 HDAC_SDCTL_RUN; 2814 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2815} 2816 2817static void 2818hdac_stream_reset(struct hdac_chan *ch) 2819{ 2820 struct hdac_softc *sc = ch->devinfo->codec->sc; 2821 int timeout = 1000; 2822 int to = timeout; 2823 uint32_t ctl; 2824 2825 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2826 ctl |= HDAC_SDCTL_SRST; 2827 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2828 do { 2829 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2830 if (ctl & HDAC_SDCTL_SRST) 2831 break; 2832 DELAY(10); 2833 } while (--to); 2834 if (!(ctl & HDAC_SDCTL_SRST)) { 2835 device_printf(sc->dev, "timeout in reset\n"); 2836 } 2837 ctl &= ~HDAC_SDCTL_SRST; 2838 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2839 to = timeout; 2840 do { 2841 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2842 if (!(ctl & HDAC_SDCTL_SRST)) 2843 break; 2844 DELAY(10); 2845 } while (--to); 2846 if (ctl & HDAC_SDCTL_SRST) 2847 device_printf(sc->dev, "can't reset!\n"); 2848} 2849 2850static void 2851hdac_stream_setid(struct hdac_chan *ch) 2852{ 2853 struct hdac_softc *sc = ch->devinfo->codec->sc; 2854 uint32_t ctl; 2855 2856 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2857 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2858 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2859 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2860} 2861 2862static void 2863hdac_bdl_setup(struct hdac_chan *ch) 2864{ 2865 struct hdac_softc *sc = ch->devinfo->codec->sc; 2866 struct hdac_bdle *bdle; 2867 uint64_t addr; 2868 uint32_t blksz, blkcnt; 2869 int i; 2870 2871 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2872 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2873 2874 blksz = ch->blksz; 2875 blkcnt = ch->blkcnt; 2876 2877 for (i = 0; i < blkcnt; i++, bdle++) { 2878 bdle->addrl = (uint32_t)addr; 2879 bdle->addrh = (uint32_t)(addr >> 32); 2880 bdle->len = blksz; 2881 bdle->ioc = 1; 2882 addr += blksz; 2883 } 2884 2885 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2886 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2887 addr = ch->bdl_dma.dma_paddr; 2888 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2889 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2890 if (ch->dmapos != NULL && 2891 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2892 addr = sc->pos_dma.dma_paddr; 2893 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2894 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2895 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2896 } 2897} 2898 2899static int 2900hdac_bdl_alloc(struct hdac_chan *ch) 2901{ 2902 struct hdac_softc *sc = ch->devinfo->codec->sc; 2903 int rc; 2904 2905 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2906 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2907 if (rc) { 2908 device_printf(sc->dev, "can't alloc bdl\n"); 2909 return (rc); 2910 } 2911 2912 return (0); 2913} 2914 2915static void 2916hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2917 int index, int lmute, int rmute, 2918 int left, int right, int dir) 2919{ 2920 uint16_t v = 0; 2921 2922 if (sc == NULL) 2923 return; 2924 2925 if (left != right || lmute != rmute) { 2926 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2927 (lmute << 7) | left; 2928 hdac_command(sc, 2929 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2930 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2931 (rmute << 7) | right; 2932 } else 2933 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2934 (lmute << 7) | left; 2935 2936 hdac_command(sc, 2937 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2938} 2939 2940static void 2941hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2942 int left, int right) 2943{ 2944 struct hdac_softc *sc; 2945 nid_t nid, cad; 2946 int lmute, rmute; 2947 2948 sc = ctl->widget->devinfo->codec->sc; 2949 cad = ctl->widget->devinfo->codec->cad; 2950 nid = ctl->widget->nid; 2951 2952 /* Save new values if valid. */ 2953 if (mute != HDA_AMP_MUTE_DEFAULT) 2954 ctl->muted = mute; 2955 if (left != HDA_AMP_VOL_DEFAULT) 2956 ctl->left = left; 2957 if (right != HDA_AMP_VOL_DEFAULT) 2958 ctl->right = right; 2959 /* Prepare effective values */ 2960 if (ctl->forcemute) { 2961 lmute = 1; 2962 rmute = 1; 2963 left = 0; 2964 right = 0; 2965 } else { 2966 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2967 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2968 left = ctl->left; 2969 right = ctl->right; 2970 } 2971 /* Apply effective values */ 2972 if (ctl->dir & HDA_CTL_OUT) 2973 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2974 lmute, rmute, left, right, 0); 2975 if (ctl->dir & HDA_CTL_IN) 2976 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2977 lmute, rmute, left, right, 1); 2978} 2979 2980static void 2981hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2982{ 2983 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2984 return; 2985 hdac_command(w->devinfo->codec->sc, 2986 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2987 w->nid, index), w->devinfo->codec->cad); 2988 w->selconn = index; 2989} 2990 2991 2992/**************************************************************************** 2993 * uint32_t hdac_command_sendone_internal 2994 * 2995 * Wrapper function that sends only one command to a given codec 2996 ****************************************************************************/ 2997static uint32_t 2998hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2999{ 3000 struct hdac_command_list cl; 3001 uint32_t response = HDAC_INVALID; 3002 3003 if (!hdac_lockowned(sc)) 3004 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3005 cl.num_commands = 1; 3006 cl.verbs = &verb; 3007 cl.responses = &response; 3008 3009 hdac_command_send_internal(sc, &cl, cad); 3010 3011 return (response); 3012} 3013 3014/**************************************************************************** 3015 * hdac_command_send_internal 3016 * 3017 * Send a command list to the codec via the corb. We queue as much verbs as 3018 * we can and msleep on the codec. When the interrupt get the responses 3019 * back from the rirb, it will wake us up so we can queue the remaining verbs 3020 * if any. 3021 ****************************************************************************/ 3022static void 3023hdac_command_send_internal(struct hdac_softc *sc, 3024 struct hdac_command_list *commands, nid_t cad) 3025{ 3026 struct hdac_codec *codec; 3027 int corbrp; 3028 uint32_t *corb; 3029 int timeout; 3030 int retry = 10; 3031 struct hdac_rirb *rirb_base; 3032 3033 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3034 commands->num_commands < 1) 3035 return; 3036 3037 codec = sc->codecs[cad]; 3038 codec->commands = commands; 3039 codec->responses_received = 0; 3040 codec->verbs_sent = 0; 3041 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3042 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3043 3044 do { 3045 if (codec->verbs_sent != commands->num_commands) { 3046 /* Queue as many verbs as possible */ 3047 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3048#if 0 3049 bus_dmamap_sync(sc->corb_dma.dma_tag, 3050 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3051#endif 3052 while (codec->verbs_sent != commands->num_commands && 3053 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3054 sc->corb_wp++; 3055 sc->corb_wp %= sc->corb_size; 3056 corb[sc->corb_wp] = 3057 commands->verbs[codec->verbs_sent++]; 3058 } 3059 3060 /* Send the verbs to the codecs */ 3061#if 0 3062 bus_dmamap_sync(sc->corb_dma.dma_tag, 3063 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3064#endif 3065 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3066 } 3067 3068 timeout = 1000; 3069 while (hdac_rirb_flush(sc) == 0 && --timeout) 3070 DELAY(10); 3071 } while ((codec->verbs_sent != commands->num_commands || 3072 codec->responses_received != commands->num_commands) && --retry); 3073 3074 if (retry == 0) 3075 device_printf(sc->dev, 3076 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3077 __func__, commands->num_commands, codec->verbs_sent, 3078 codec->responses_received); 3079 3080 codec->commands = NULL; 3081 codec->responses_received = 0; 3082 codec->verbs_sent = 0; 3083 3084 hdac_unsolq_flush(sc); 3085} 3086 3087 3088/**************************************************************************** 3089 * Device Methods 3090 ****************************************************************************/ 3091 3092/**************************************************************************** 3093 * int hdac_probe(device_t) 3094 * 3095 * Probe for the presence of an hdac. If none is found, check for a generic 3096 * match using the subclass of the device. 3097 ****************************************************************************/ 3098static int 3099hdac_probe(device_t dev) 3100{ 3101 int i, result; 3102 uint32_t model; 3103 uint16_t class, subclass; 3104 char desc[64]; 3105 3106 model = (uint32_t)pci_get_device(dev) << 16; 3107 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3108 class = pci_get_class(dev); 3109 subclass = pci_get_subclass(dev); 3110 3111 bzero(desc, sizeof(desc)); 3112 result = ENXIO; 3113 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3114 if (hdac_devices[i].model == model) { 3115 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3116 result = BUS_PROBE_DEFAULT; 3117 break; 3118 } 3119 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3120 class == PCIC_MULTIMEDIA && 3121 subclass == PCIS_MULTIMEDIA_HDA) { 3122 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3123 result = BUS_PROBE_GENERIC; 3124 break; 3125 } 3126 } 3127 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3128 subclass == PCIS_MULTIMEDIA_HDA) { 3129 strlcpy(desc, "Generic", sizeof(desc)); 3130 result = BUS_PROBE_GENERIC; 3131 } 3132 if (result != ENXIO) { 3133 strlcat(desc, " High Definition Audio Controller", 3134 sizeof(desc)); 3135 device_set_desc_copy(dev, desc); 3136 } 3137 3138 return (result); 3139} 3140 3141static void * 3142hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3143 struct pcm_channel *c, int dir) 3144{ 3145 struct hdac_pcm_devinfo *pdevinfo = data; 3146 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3147 struct hdac_softc *sc = devinfo->codec->sc; 3148 struct hdac_chan *ch; 3149 int i, ord = 0, chid; 3150 3151 hdac_lock(sc); 3152 3153 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3154 ch = &sc->chans[chid]; 3155 for (i = 0; i < sc->num_chans && i < chid; i++) { 3156 if (ch->dir == sc->chans[i].dir) 3157 ord++; 3158 } 3159 if (dir == PCMDIR_PLAY) { 3160 ch->off = (sc->num_iss + ord) << 5; 3161 } else { 3162 ch->off = ord << 5; 3163 } 3164 3165 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3166 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3167 ch->pcmrates[0] = 48000; 3168 ch->pcmrates[1] = 0; 3169 } 3170 if (sc->pos_dma.dma_vaddr != NULL) 3171 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3172 (sc->streamcnt * 8)); 3173 else 3174 ch->dmapos = NULL; 3175 ch->sid = ++sc->streamcnt; 3176 ch->dir = dir; 3177 ch->b = b; 3178 ch->c = c; 3179 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3180 ch->blkcnt = pdevinfo->chan_blkcnt; 3181 hdac_unlock(sc); 3182 3183 if (hdac_bdl_alloc(ch) != 0) { 3184 ch->blkcnt = 0; 3185 return (NULL); 3186 } 3187 3188 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3189 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3190 pdevinfo->chan_size) != 0) 3191 return (NULL); 3192 3193 return (ch); 3194} 3195 3196static int 3197hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3198{ 3199 struct hdac_chan *ch = data; 3200 int i; 3201 3202 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3203 if (format == ch->caps.fmtlist[i]) { 3204 ch->fmt = format; 3205 return (0); 3206 } 3207 } 3208 3209 return (EINVAL); 3210} 3211 3212static int 3213hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3214{ 3215 struct hdac_chan *ch = data; 3216 uint32_t spd = 0, threshold; 3217 int i; 3218 3219 for (i = 0; ch->pcmrates[i] != 0; i++) { 3220 spd = ch->pcmrates[i]; 3221 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3222 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3223 if (speed < threshold) 3224 break; 3225 } 3226 3227 if (spd == 0) /* impossible */ 3228 ch->spd = 48000; 3229 else 3230 ch->spd = spd; 3231 3232 return (ch->spd); 3233} 3234 3235static void 3236hdac_stream_setup(struct hdac_chan *ch) 3237{ 3238 struct hdac_softc *sc = ch->devinfo->codec->sc; 3239 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3240 struct hdac_widget *w; 3241 int i, chn, totalchn, c; 3242 nid_t cad = ch->devinfo->codec->cad; 3243 uint16_t fmt, dfmt; 3244 3245 HDA_BOOTHVERBOSE( 3246 device_printf(ch->pdevinfo->dev, 3247 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3248 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3249 ch->fmt, ch->spd); 3250 ); 3251 fmt = 0; 3252 if (ch->fmt & AFMT_S16_LE) 3253 fmt |= ch->bit16 << 4; 3254 else if (ch->fmt & AFMT_S32_LE) 3255 fmt |= ch->bit32 << 4; 3256 else 3257 fmt |= 1 << 4; 3258 3259 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3260 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3261 fmt |= hda_rate_tab[i].base; 3262 fmt |= hda_rate_tab[i].mul; 3263 fmt |= hda_rate_tab[i].div; 3264 break; 3265 } 3266 } 3267 3268 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3269 fmt |= 1; 3270 totalchn = 2; 3271 } else 3272 totalchn = 1; 3273 3274 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3275 3276 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3277 if (ch->fmt & AFMT_AC3) 3278 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3279 3280 chn = 0; 3281 for (i = 0; ch->io[i] != -1; i++) { 3282 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3283 if (w == NULL) 3284 continue; 3285 3286 if (as->hpredir >= 0 && i == as->pincnt) 3287 chn = 0; 3288 HDA_BOOTHVERBOSE( 3289 device_printf(ch->pdevinfo->dev, 3290 "PCMDIR_%s: Stream setup nid=%d: " 3291 "fmt=0x%04x, dfmt=0x%04x\n", 3292 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3293 ch->io[i], fmt, dfmt); 3294 ); 3295 hdac_command(sc, 3296 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3297 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3298 hdac_command(sc, 3299 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3300 cad); 3301 } 3302 /* If HP redirection is enabled, but failed to use same 3303 DAC make last DAC one to duplicate first one. */ 3304 if (as->hpredir >= 0 && i == as->pincnt) { 3305 c = (ch->sid << 4); 3306 } else if (chn >= totalchn) { 3307 /* This is until OSS will support multichannel. 3308 Should be: c = 0; to disable unused DAC */ 3309 c = (ch->sid << 4); 3310 }else { 3311 c = (ch->sid << 4) | chn; 3312 } 3313 hdac_command(sc, 3314 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3315 chn += 3316 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3317 2 : 1; 3318 } 3319} 3320 3321static int 3322hdac_channel_setfragments(kobj_t obj, void *data, 3323 uint32_t blksz, uint32_t blkcnt) 3324{ 3325 struct hdac_chan *ch = data; 3326 struct hdac_softc *sc = ch->devinfo->codec->sc; 3327 3328 blksz &= HDA_BLK_ALIGN; 3329 3330 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3331 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3332 if (blksz < HDA_BLK_MIN) 3333 blksz = HDA_BLK_MIN; 3334 if (blkcnt > HDA_BDL_MAX) 3335 blkcnt = HDA_BDL_MAX; 3336 if (blkcnt < HDA_BDL_MIN) 3337 blkcnt = HDA_BDL_MIN; 3338 3339 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3340 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3341 blkcnt >>= 1; 3342 else if ((blksz >> 1) >= HDA_BLK_MIN) 3343 blksz >>= 1; 3344 else 3345 break; 3346 } 3347 3348 if ((sndbuf_getblksz(ch->b) != blksz || 3349 sndbuf_getblkcnt(ch->b) != blkcnt) && 3350 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3351 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3352 __func__, blksz, blkcnt); 3353 3354 ch->blksz = sndbuf_getblksz(ch->b); 3355 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3356 3357 return (1); 3358} 3359 3360static int 3361hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3362{ 3363 struct hdac_chan *ch = data; 3364 3365 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3366 3367 return (ch->blksz); 3368} 3369 3370static void 3371hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3372{ 3373 struct hdac_devinfo *devinfo = ch->devinfo; 3374 struct hdac_widget *w; 3375 nid_t cad = devinfo->codec->cad; 3376 int i; 3377 3378 hdac_stream_stop(ch); 3379 3380 for (i = 0; ch->io[i] != -1; i++) { 3381 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3382 if (w == NULL) 3383 continue; 3384 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3385 hdac_command(sc, 3386 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3387 cad); 3388 } 3389 hdac_command(sc, 3390 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3391 0), cad); 3392 } 3393} 3394 3395static void 3396hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3397{ 3398 ch->ptr = 0; 3399 ch->prevptr = 0; 3400 hdac_stream_stop(ch); 3401 hdac_stream_reset(ch); 3402 hdac_bdl_setup(ch); 3403 hdac_stream_setid(ch); 3404 hdac_stream_setup(ch); 3405 hdac_stream_start(ch); 3406} 3407 3408static int 3409hdac_channel_trigger(kobj_t obj, void *data, int go) 3410{ 3411 struct hdac_chan *ch = data; 3412 struct hdac_softc *sc = ch->devinfo->codec->sc; 3413 3414 if (!PCMTRIG_COMMON(go)) 3415 return (0); 3416 3417 hdac_lock(sc); 3418 switch (go) { 3419 case PCMTRIG_START: 3420 hdac_channel_start(sc, ch); 3421 break; 3422 case PCMTRIG_STOP: 3423 case PCMTRIG_ABORT: 3424 hdac_channel_stop(sc, ch); 3425 break; 3426 default: 3427 break; 3428 } 3429 hdac_unlock(sc); 3430 3431 return (0); 3432} 3433 3434static int 3435hdac_channel_getptr(kobj_t obj, void *data) 3436{ 3437 struct hdac_chan *ch = data; 3438 struct hdac_softc *sc = ch->devinfo->codec->sc; 3439 uint32_t ptr; 3440 3441 hdac_lock(sc); 3442 if (sc->polling != 0) 3443 ptr = ch->ptr; 3444 else if (ch->dmapos != NULL) 3445 ptr = *(ch->dmapos); 3446 else 3447 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3448 hdac_unlock(sc); 3449 3450 /* 3451 * Round to available space and force 128 bytes aligment. 3452 */ 3453 ptr %= ch->blksz * ch->blkcnt; 3454 ptr &= HDA_BLK_ALIGN; 3455 3456 return (ptr); 3457} 3458 3459static struct pcmchan_caps * 3460hdac_channel_getcaps(kobj_t obj, void *data) 3461{ 3462 return (&((struct hdac_chan *)data)->caps); 3463} 3464 3465static kobj_method_t hdac_channel_methods[] = { 3466 KOBJMETHOD(channel_init, hdac_channel_init), 3467 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3468 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3469 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3470 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3471 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3472 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3473 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3474 { 0, 0 } 3475}; 3476CHANNEL_DECLARE(hdac_channel); 3477 3478static int 3479hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3480{ 3481 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3482 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3483 struct hdac_softc *sc = devinfo->codec->sc; 3484 struct hdac_widget *w, *cw; 3485 struct hdac_audio_ctl *ctl; 3486 uint32_t mask, recmask, id; 3487 int i, j, softpcmvol; 3488 3489 hdac_lock(sc); 3490 3491 /* Make sure that in case of soft volume it won't stay muted. */ 3492 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3493 pdevinfo->left[i] = 100; 3494 pdevinfo->right[i] = 100; 3495 } 3496 3497 mask = 0; 3498 recmask = 0; 3499 id = hdac_codec_id(devinfo->codec); 3500 3501 /* Declate EAPD as ogain control. */ 3502 if (pdevinfo->play >= 0) { 3503 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3504 w = hdac_widget_get(devinfo, i); 3505 if (w == NULL || w->enable == 0) 3506 continue; 3507 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3508 w->param.eapdbtl == HDAC_INVALID || 3509 w->bindas != sc->chans[pdevinfo->play].as) 3510 continue; 3511 mask |= SOUND_MASK_OGAIN; 3512 break; 3513 } 3514 } 3515 3516 /* Declare volume controls assigned to this association. */ 3517 i = 0; 3518 ctl = NULL; 3519 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3520 if (ctl->enable == 0) 3521 continue; 3522 if ((pdevinfo->play >= 0 && 3523 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3524 (pdevinfo->rec >= 0 && 3525 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3526 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3527 mask |= ctl->ossmask; 3528 } 3529 3530 /* Declare record sources available to this association. */ 3531 if (pdevinfo->rec >= 0) { 3532 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3533 for (i = 0; ch->io[i] != -1; i++) { 3534 w = hdac_widget_get(devinfo, ch->io[i]); 3535 if (w == NULL || w->enable == 0) 3536 continue; 3537 for (j = 0; j < w->nconns; j++) { 3538 if (w->connsenable[j] == 0) 3539 continue; 3540 cw = hdac_widget_get(devinfo, w->conns[j]); 3541 if (cw == NULL || cw->enable == 0) 3542 continue; 3543 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3544 cw->bindas != -2) 3545 continue; 3546 recmask |= cw->ossmask; 3547 } 3548 } 3549 } 3550 3551 /* Declare soft PCM and master volume if needed. */ 3552 if (pdevinfo->play >= 0) { 3553 ctl = NULL; 3554 if ((mask & SOUND_MASK_PCM) == 0 || 3555 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3556 softpcmvol = 1; 3557 mask |= SOUND_MASK_PCM; 3558 } else { 3559 softpcmvol = 0; 3560 i = 0; 3561 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3562 if (ctl->enable == 0) 3563 continue; 3564 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3565 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3566 continue; 3567 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3568 continue; 3569 if (ctl->step > 0) 3570 break; 3571 } 3572 } 3573 3574 if (softpcmvol == 1 || ctl == NULL) { 3575 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3576 HDA_BOOTVERBOSE( 3577 device_printf(pdevinfo->dev, 3578 "%s Soft PCM volume\n", 3579 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3580 ); 3581 } 3582 3583 if ((mask & SOUND_MASK_VOLUME) == 0) { 3584 mask |= SOUND_MASK_VOLUME; 3585 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3586 SOUND_MASK_PCM); 3587 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3588 SOUND_MIXER_NONE); 3589 HDA_BOOTVERBOSE( 3590 device_printf(pdevinfo->dev, 3591 "Forcing master volume with PCM\n"); 3592 ); 3593 } 3594 } 3595 3596 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3597 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3598 3599 mix_setrecdevs(m, recmask); 3600 mix_setdevs(m, mask); 3601 3602 hdac_unlock(sc); 3603 3604 return (0); 3605} 3606 3607static int 3608hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3609 unsigned left, unsigned right) 3610{ 3611 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3612 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3613 struct hdac_softc *sc = devinfo->codec->sc; 3614 struct hdac_widget *w; 3615 struct hdac_audio_ctl *ctl; 3616 uint32_t mute; 3617 int lvol, rvol; 3618 int i, j; 3619 3620 hdac_lock(sc); 3621 /* Save new values. */ 3622 pdevinfo->left[dev] = left; 3623 pdevinfo->right[dev] = right; 3624 3625 /* 'ogain' is the special case implemented with EAPD. */ 3626 if (dev == SOUND_MIXER_OGAIN) { 3627 uint32_t orig; 3628 w = NULL; 3629 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3630 w = hdac_widget_get(devinfo, i); 3631 if (w == NULL || w->enable == 0) 3632 continue; 3633 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3634 w->param.eapdbtl == HDAC_INVALID) 3635 continue; 3636 break; 3637 } 3638 if (i >= devinfo->endnode) { 3639 hdac_unlock(sc); 3640 return (-1); 3641 } 3642 orig = w->param.eapdbtl; 3643 if (left == 0) 3644 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3645 else 3646 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3647 if (orig != w->param.eapdbtl) { 3648 uint32_t val; 3649 3650 val = w->param.eapdbtl; 3651 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3652 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3653 hdac_command(sc, 3654 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3655 w->nid, val), devinfo->codec->cad); 3656 } 3657 hdac_unlock(sc); 3658 return (left | (left << 8)); 3659 } 3660 3661 /* Recalculate all controls related to this OSS device. */ 3662 i = 0; 3663 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3664 if (ctl->enable == 0 || 3665 !(ctl->ossmask & (1 << dev))) 3666 continue; 3667 if (!((pdevinfo->play >= 0 && 3668 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3669 (pdevinfo->rec >= 0 && 3670 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3671 ctl->widget->bindas == -2)) 3672 continue; 3673 3674 lvol = 100; 3675 rvol = 100; 3676 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3677 if (ctl->ossmask & (1 << j)) { 3678 lvol = lvol * pdevinfo->left[j] / 100; 3679 rvol = rvol * pdevinfo->right[j] / 100; 3680 } 3681 } 3682 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3683 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3684 lvol = (lvol * ctl->step + 50) / 100; 3685 rvol = (rvol * ctl->step + 50) / 100; 3686 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3687 } 3688 hdac_unlock(sc); 3689 3690 return (left | (right << 8)); 3691} 3692 3693/* 3694 * Commutate specified record source. 3695 */ 3696static uint32_t 3697hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3698{ 3699 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3700 struct hdac_widget *w, *cw; 3701 struct hdac_audio_ctl *ctl; 3702 char buf[64]; 3703 int i, muted; 3704 uint32_t res = 0; 3705 3706 if (depth > HDA_PARSE_MAXDEPTH) 3707 return (0); 3708 3709 w = hdac_widget_get(devinfo, nid); 3710 if (w == NULL || w->enable == 0) 3711 return (0); 3712 3713 for (i = 0; i < w->nconns; i++) { 3714 if (w->connsenable[i] == 0) 3715 continue; 3716 cw = hdac_widget_get(devinfo, w->conns[i]); 3717 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3718 continue; 3719 /* Call recursively to trace signal to it's source if needed. */ 3720 if ((src & cw->ossmask) != 0) { 3721 if (cw->ossdev < 0) { 3722 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3723 w->conns[i], depth + 1); 3724 } else { 3725 res |= cw->ossmask; 3726 } 3727 } 3728 /* We have two special cases: mixers and others (selectors). */ 3729 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3730 ctl = hdac_audio_ctl_amp_get(devinfo, 3731 w->nid, HDA_CTL_IN, i, 1); 3732 if (ctl == NULL) 3733 continue; 3734 /* If we have input control on this node mute them 3735 * according to requested sources. */ 3736 muted = (src & cw->ossmask) ? 0 : 1; 3737 if (muted != ctl->forcemute) { 3738 ctl->forcemute = muted; 3739 hdac_audio_ctl_amp_set(ctl, 3740 HDA_AMP_MUTE_DEFAULT, 3741 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3742 } 3743 HDA_BOOTHVERBOSE( 3744 device_printf(pdevinfo->dev, 3745 "Recsel (%s): nid %d source %d %s\n", 3746 hdac_audio_ctl_ossmixer_mask2allname( 3747 src, buf, sizeof(buf)), 3748 nid, i, muted?"mute":"unmute"); 3749 ); 3750 } else { 3751 if (w->nconns == 1) 3752 break; 3753 if ((src & cw->ossmask) == 0) 3754 continue; 3755 /* If we found requested source - select it and exit. */ 3756 hdac_widget_connection_select(w, i); 3757 HDA_BOOTHVERBOSE( 3758 device_printf(pdevinfo->dev, 3759 "Recsel (%s): nid %d source %d select\n", 3760 hdac_audio_ctl_ossmixer_mask2allname( 3761 src, buf, sizeof(buf)), 3762 nid, i); 3763 ); 3764 break; 3765 } 3766 } 3767 return (res); 3768} 3769 3770static uint32_t 3771hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3772{ 3773 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3774 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3775 struct hdac_widget *w; 3776 struct hdac_softc *sc = devinfo->codec->sc; 3777 struct hdac_chan *ch; 3778 int i; 3779 uint32_t ret = 0xffffffff; 3780 3781 hdac_lock(sc); 3782 3783 /* Commutate requested recsrc for each ADC. */ 3784 ch = &sc->chans[pdevinfo->rec]; 3785 for (i = 0; ch->io[i] != -1; i++) { 3786 w = hdac_widget_get(devinfo, ch->io[i]); 3787 if (w == NULL || w->enable == 0) 3788 continue; 3789 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3790 } 3791 3792 hdac_unlock(sc); 3793 3794 return ((ret == 0xffffffff)? 0 : ret); 3795} 3796 3797static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3798 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3799 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3800 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3801 { 0, 0 } 3802}; 3803MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3804 3805static void 3806hdac_unsolq_task(void *context, int pending) 3807{ 3808 struct hdac_softc *sc; 3809 3810 sc = (struct hdac_softc *)context; 3811 3812 hdac_lock(sc); 3813 hdac_unsolq_flush(sc); 3814 hdac_unlock(sc); 3815} 3816 3817/**************************************************************************** 3818 * int hdac_attach(device_t) 3819 * 3820 * Attach the device into the kernel. Interrupts usually won't be enabled 3821 * when this function is called. Setup everything that doesn't require 3822 * interrupts and defer probing of codecs until interrupts are enabled. 3823 ****************************************************************************/ 3824static int 3825hdac_attach(device_t dev) 3826{ 3827 struct hdac_softc *sc; 3828 int result; 3829 int i; 3830 uint16_t vendor; 3831 uint8_t v; 3832 3833 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3834 3835 sc = device_get_softc(dev); 3836 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3837 sc->dev = dev; 3838 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3839 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3840 vendor = pci_get_vendor(dev); 3841 3842 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3843 /* Screw nx6325 - subdevice/subvendor swapped */ 3844 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3845 } 3846 3847 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3848 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3849 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3850 3851 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3852 3853 sc->poll_ticks = 1000000; 3854 sc->poll_ival = HDAC_POLL_INTERVAL; 3855 if (resource_int_value(device_get_name(dev), 3856 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3857 sc->polling = 1; 3858 else 3859 sc->polling = 0; 3860 3861 result = bus_dma_tag_create(NULL, /* parent */ 3862 HDAC_DMA_ALIGNMENT, /* alignment */ 3863 0, /* boundary */ 3864 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3865 BUS_SPACE_MAXADDR, /* highaddr */ 3866 NULL, /* filtfunc */ 3867 NULL, /* fistfuncarg */ 3868 HDA_BUFSZ_MAX, /* maxsize */ 3869 1, /* nsegments */ 3870 HDA_BUFSZ_MAX, /* maxsegsz */ 3871 0, /* flags */ 3872 NULL, /* lockfunc */ 3873 NULL, /* lockfuncarg */ 3874 &sc->chan_dmat); /* dmat */ 3875 if (result != 0) { 3876 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3877 __func__, result); 3878 snd_mtxfree(sc->lock); 3879 free(sc, M_DEVBUF); 3880 return (ENXIO); 3881 } 3882 3883 3884 sc->hdabus = NULL; 3885 for (i = 0; i < HDAC_CODEC_MAX; i++) 3886 sc->codecs[i] = NULL; 3887 3888 pci_enable_busmaster(dev); 3889 3890 if (vendor == INTEL_VENDORID) { 3891 /* TCSEL -> TC0 */ 3892 v = pci_read_config(dev, 0x44, 1); 3893 pci_write_config(dev, 0x44, v & 0xf8, 1); 3894 HDA_BOOTHVERBOSE( 3895 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3896 pci_read_config(dev, 0x44, 1)); 3897 ); 3898 } 3899 3900#ifdef HDAC_MSI_ENABLED 3901 if (resource_int_value(device_get_name(dev), 3902 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3903 pci_msi_count(dev) == 1) 3904 sc->flags |= HDAC_F_MSI; 3905 else 3906#endif 3907 sc->flags &= ~HDAC_F_MSI; 3908 3909#if defined(__i386__) || defined(__amd64__) 3910 sc->flags |= HDAC_F_DMA_NOCACHE; 3911 3912 if (resource_int_value(device_get_name(dev), 3913 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3914#else 3915 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3916#endif 3917 /* 3918 * Try to enable PCIe snoop to avoid messing around with 3919 * uncacheable DMA attribute. Since PCIe snoop register 3920 * config is pretty much vendor specific, there are no 3921 * general solutions on how to enable it, forcing us (even 3922 * Microsoft) to enable uncacheable or write combined DMA 3923 * by default. 3924 * 3925 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3926 */ 3927 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3928 if (hdac_pcie_snoop[i].vendor != vendor) 3929 continue; 3930 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3931 if (hdac_pcie_snoop[i].reg == 0x00) 3932 break; 3933 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3934 if ((v & hdac_pcie_snoop[i].enable) == 3935 hdac_pcie_snoop[i].enable) 3936 break; 3937 v &= hdac_pcie_snoop[i].mask; 3938 v |= hdac_pcie_snoop[i].enable; 3939 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3940 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3941 if ((v & hdac_pcie_snoop[i].enable) != 3942 hdac_pcie_snoop[i].enable) { 3943 HDA_BOOTVERBOSE( 3944 device_printf(dev, 3945 "WARNING: Failed to enable PCIe " 3946 "snoop!\n"); 3947 ); 3948#if defined(__i386__) || defined(__amd64__) 3949 sc->flags |= HDAC_F_DMA_NOCACHE; 3950#endif 3951 } 3952 break; 3953 } 3954#if defined(__i386__) || defined(__amd64__) 3955 } 3956#endif 3957 3958 HDA_BOOTHVERBOSE( 3959 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3960 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3961 "Uncacheable" : "PCIe snoop", vendor); 3962 ); 3963 3964 /* Allocate resources */ 3965 result = hdac_mem_alloc(sc); 3966 if (result != 0) 3967 goto hdac_attach_fail; 3968 result = hdac_irq_alloc(sc); 3969 if (result != 0) 3970 goto hdac_attach_fail; 3971 3972 /* Get Capabilities */ 3973 result = hdac_get_capabilities(sc); 3974 if (result != 0) 3975 goto hdac_attach_fail; 3976 3977 /* Allocate CORB and RIRB dma memory */ 3978 result = hdac_dma_alloc(sc, &sc->corb_dma, 3979 sc->corb_size * sizeof(uint32_t)); 3980 if (result != 0) 3981 goto hdac_attach_fail; 3982 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3983 sc->rirb_size * sizeof(struct hdac_rirb)); 3984 if (result != 0) 3985 goto hdac_attach_fail; 3986 3987 /* Quiesce everything */ 3988 HDA_BOOTHVERBOSE( 3989 device_printf(dev, "Reset controller...\n"); 3990 ); 3991 hdac_reset(sc, 1); 3992 3993 /* Initialize the CORB and RIRB */ 3994 hdac_corb_init(sc); 3995 hdac_rirb_init(sc); 3996 3997 /* Defer remaining of initialization until interrupts are enabled */ 3998 sc->intrhook.ich_func = hdac_attach2; 3999 sc->intrhook.ich_arg = (void *)sc; 4000 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4001 sc->intrhook.ich_func = NULL; 4002 hdac_attach2((void *)sc); 4003 } 4004 4005 return (0); 4006 4007hdac_attach_fail: 4008 hdac_irq_free(sc); 4009 hdac_dma_free(sc, &sc->rirb_dma); 4010 hdac_dma_free(sc, &sc->corb_dma); 4011 hdac_mem_free(sc); 4012 snd_mtxfree(sc->lock); 4013 free(sc, M_DEVBUF); 4014 4015 return (ENXIO); 4016} 4017 4018static void 4019hdac_audio_parse(struct hdac_devinfo *devinfo) 4020{ 4021 struct hdac_codec *codec = devinfo->codec; 4022 struct hdac_softc *sc = codec->sc; 4023 struct hdac_widget *w; 4024 uint32_t res; 4025 int i; 4026 nid_t cad, nid; 4027 4028 cad = devinfo->codec->cad; 4029 nid = devinfo->nid; 4030 4031 res = hdac_command(sc, 4032 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4033 devinfo->function.audio.gpio = res; 4034 4035 HDA_BOOTVERBOSE( 4036 device_printf(sc->dev, "GPIO: 0x%08x " 4037 "NumGPIO=%d NumGPO=%d " 4038 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4039 devinfo->function.audio.gpio, 4040 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4041 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4042 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4043 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4044 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4045 ); 4046 4047 res = hdac_command(sc, 4048 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4049 cad); 4050 devinfo->function.audio.supp_stream_formats = res; 4051 4052 res = hdac_command(sc, 4053 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4054 cad); 4055 devinfo->function.audio.supp_pcm_size_rate = res; 4056 4057 res = hdac_command(sc, 4058 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4059 cad); 4060 devinfo->function.audio.outamp_cap = res; 4061 4062 res = hdac_command(sc, 4063 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4064 cad); 4065 devinfo->function.audio.inamp_cap = res; 4066 4067 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4068 w = hdac_widget_get(devinfo, i); 4069 if (w == NULL) 4070 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4071 else { 4072 w->devinfo = devinfo; 4073 w->nid = i; 4074 w->enable = 1; 4075 w->selconn = -1; 4076 w->pflags = 0; 4077 w->ossdev = -1; 4078 w->bindas = -1; 4079 w->param.eapdbtl = HDAC_INVALID; 4080 hdac_widget_parse(w); 4081 } 4082 } 4083} 4084 4085static void 4086hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4087{ 4088 struct hdac_softc *sc = devinfo->codec->sc; 4089 struct hdac_audio_ctl *ctls; 4090 struct hdac_widget *w, *cw; 4091 int i, j, cnt, max, ocap, icap; 4092 int mute, offset, step, size; 4093 4094 /* XXX This is redundant */ 4095 max = 0; 4096 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4097 w = hdac_widget_get(devinfo, i); 4098 if (w == NULL || w->enable == 0) 4099 continue; 4100 if (w->param.outamp_cap != 0) 4101 max++; 4102 if (w->param.inamp_cap != 0) { 4103 switch (w->type) { 4104 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4105 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4106 for (j = 0; j < w->nconns; j++) { 4107 cw = hdac_widget_get(devinfo, 4108 w->conns[j]); 4109 if (cw == NULL || cw->enable == 0) 4110 continue; 4111 max++; 4112 } 4113 break; 4114 default: 4115 max++; 4116 break; 4117 } 4118 } 4119 } 4120 4121 devinfo->function.audio.ctlcnt = max; 4122 4123 if (max < 1) 4124 return; 4125 4126 ctls = (struct hdac_audio_ctl *)malloc( 4127 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4128 4129 if (ctls == NULL) { 4130 /* Blekh! */ 4131 device_printf(sc->dev, "unable to allocate ctls!\n"); 4132 devinfo->function.audio.ctlcnt = 0; 4133 return; 4134 } 4135 4136 cnt = 0; 4137 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4138 if (cnt >= max) { 4139 device_printf(sc->dev, "%s: Ctl overflow!\n", 4140 __func__); 4141 break; 4142 } 4143 w = hdac_widget_get(devinfo, i); 4144 if (w == NULL || w->enable == 0) 4145 continue; 4146 ocap = w->param.outamp_cap; 4147 icap = w->param.inamp_cap; 4148 if (ocap != 0) { 4149 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4150 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4151 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4152 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4153 /*if (offset > step) { 4154 HDA_BOOTVERBOSE( 4155 device_printf(sc->dev, 4156 "BUGGY outamp: nid=%d " 4157 "[offset=%d > step=%d]\n", 4158 w->nid, offset, step); 4159 ); 4160 offset = step; 4161 }*/ 4162 ctls[cnt].enable = 1; 4163 ctls[cnt].widget = w; 4164 ctls[cnt].mute = mute; 4165 ctls[cnt].step = step; 4166 ctls[cnt].size = size; 4167 ctls[cnt].offset = offset; 4168 ctls[cnt].left = offset; 4169 ctls[cnt].right = offset; 4170 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4171 w->waspin) 4172 ctls[cnt].ndir = HDA_CTL_IN; 4173 else 4174 ctls[cnt].ndir = HDA_CTL_OUT; 4175 ctls[cnt++].dir = HDA_CTL_OUT; 4176 } 4177 4178 if (icap != 0) { 4179 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4180 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4181 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4182 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4183 /*if (offset > step) { 4184 HDA_BOOTVERBOSE( 4185 device_printf(sc->dev, 4186 "BUGGY inamp: nid=%d " 4187 "[offset=%d > step=%d]\n", 4188 w->nid, offset, step); 4189 ); 4190 offset = step; 4191 }*/ 4192 switch (w->type) { 4193 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4194 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4195 for (j = 0; j < w->nconns; j++) { 4196 if (cnt >= max) { 4197 device_printf(sc->dev, 4198 "%s: Ctl overflow!\n", 4199 __func__); 4200 break; 4201 } 4202 cw = hdac_widget_get(devinfo, 4203 w->conns[j]); 4204 if (cw == NULL || cw->enable == 0) 4205 continue; 4206 ctls[cnt].enable = 1; 4207 ctls[cnt].widget = w; 4208 ctls[cnt].childwidget = cw; 4209 ctls[cnt].index = j; 4210 ctls[cnt].mute = mute; 4211 ctls[cnt].step = step; 4212 ctls[cnt].size = size; 4213 ctls[cnt].offset = offset; 4214 ctls[cnt].left = offset; 4215 ctls[cnt].right = offset; 4216 ctls[cnt].ndir = HDA_CTL_IN; 4217 ctls[cnt++].dir = HDA_CTL_IN; 4218 } 4219 break; 4220 default: 4221 if (cnt >= max) { 4222 device_printf(sc->dev, 4223 "%s: Ctl overflow!\n", 4224 __func__); 4225 break; 4226 } 4227 ctls[cnt].enable = 1; 4228 ctls[cnt].widget = w; 4229 ctls[cnt].mute = mute; 4230 ctls[cnt].step = step; 4231 ctls[cnt].size = size; 4232 ctls[cnt].offset = offset; 4233 ctls[cnt].left = offset; 4234 ctls[cnt].right = offset; 4235 if (w->type == 4236 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4237 ctls[cnt].ndir = HDA_CTL_OUT; 4238 else 4239 ctls[cnt].ndir = HDA_CTL_IN; 4240 ctls[cnt++].dir = HDA_CTL_IN; 4241 break; 4242 } 4243 } 4244 } 4245 4246 devinfo->function.audio.ctl = ctls; 4247} 4248 4249static void 4250hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4251{ 4252 struct hdac_softc *sc = devinfo->codec->sc; 4253 struct hdac_audio_as *as; 4254 struct hdac_widget *w; 4255 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4256 4257 /* XXX This is redundant */ 4258 max = 0; 4259 for (j = 0; j < 16; j++) { 4260 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4261 w = hdac_widget_get(devinfo, i); 4262 if (w == NULL || w->enable == 0) 4263 continue; 4264 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4265 continue; 4266 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4267 != j) 4268 continue; 4269 max++; 4270 if (j != 15) /* There could be many 1-pin assocs #15 */ 4271 break; 4272 } 4273 } 4274 4275 devinfo->function.audio.ascnt = max; 4276 4277 if (max < 1) 4278 return; 4279 4280 as = (struct hdac_audio_as *)malloc( 4281 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4282 4283 if (as == NULL) { 4284 /* Blekh! */ 4285 device_printf(sc->dev, "unable to allocate assocs!\n"); 4286 devinfo->function.audio.ascnt = 0; 4287 return; 4288 } 4289 4290 for (i = 0; i < max; i++) { 4291 as[i].hpredir = -1; 4292 as[i].chan = -1; 4293 } 4294 4295 /* Scan associations skipping as=0. */ 4296 cnt = 0; 4297 for (j = 1; j < 16; j++) { 4298 first = 16; 4299 hpredir = 0; 4300 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4301 w = hdac_widget_get(devinfo, i); 4302 if (w == NULL || w->enable == 0) 4303 continue; 4304 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4305 continue; 4306 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4307 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4308 if (assoc != j) { 4309 continue; 4310 } 4311 KASSERT(cnt < max, 4312 ("%s: Associations owerflow (%d of %d)", 4313 __func__, cnt, max)); 4314 type = w->wclass.pin.config & 4315 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4316 /* Get pin direction. */ 4317 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4318 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4319 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4320 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4321 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4322 dir = HDA_CTL_OUT; 4323 else 4324 dir = HDA_CTL_IN; 4325 /* If this is a first pin - create new association. */ 4326 if (as[cnt].pincnt == 0) { 4327 as[cnt].enable = 1; 4328 as[cnt].index = j; 4329 as[cnt].dir = dir; 4330 } 4331 if (seq < first) 4332 first = seq; 4333 /* Check association correctness. */ 4334 if (as[cnt].pins[seq] != 0) { 4335 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4336 "in association %d! Disabling association.\n", 4337 __func__, seq, w->nid, j); 4338 as[cnt].enable = 0; 4339 } 4340 if (dir != as[cnt].dir) { 4341 device_printf(sc->dev, "%s: Pin %d has wrong " 4342 "direction for association %d! Disabling " 4343 "association.\n", 4344 __func__, w->nid, j); 4345 as[cnt].enable = 0; 4346 } 4347 /* Headphones with seq=15 may mean redirection. */ 4348 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4349 seq == 15) 4350 hpredir = 1; 4351 as[cnt].pins[seq] = w->nid; 4352 as[cnt].pincnt++; 4353 /* Association 15 is a multiple unassociated pins. */ 4354 if (j == 15) 4355 cnt++; 4356 } 4357 if (j != 15 && as[cnt].pincnt > 0) { 4358 if (hpredir && as[cnt].pincnt > 1) 4359 as[cnt].hpredir = first; 4360 cnt++; 4361 } 4362 } 4363 HDA_BOOTVERBOSE( 4364 device_printf(sc->dev, 4365 "%d associations found:\n", max); 4366 for (i = 0; i < max; i++) { 4367 device_printf(sc->dev, 4368 "Association %d (%d) %s%s:\n", 4369 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4370 as[i].enable?"":" (disabled)"); 4371 for (j = 0; j < 16; j++) { 4372 if (as[i].pins[j] == 0) 4373 continue; 4374 device_printf(sc->dev, 4375 " Pin nid=%d seq=%d\n", 4376 as[i].pins[j], j); 4377 } 4378 } 4379 ); 4380 4381 devinfo->function.audio.as = as; 4382} 4383 4384static const struct { 4385 uint32_t model; 4386 uint32_t id; 4387 uint32_t set, unset; 4388} hdac_quirks[] = { 4389 /* 4390 * XXX Force stereo quirk. Monoural recording / playback 4391 * on few codecs (especially ALC880) seems broken or 4392 * perhaps unsupported. 4393 */ 4394 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4395 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4396 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4397 HDA_QUIRK_GPIO0, 0 }, 4398 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4399 HDA_QUIRK_GPIO0, 0 }, 4400 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4401 HDA_QUIRK_GPIO0, 0 }, 4402 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4403 HDA_QUIRK_GPIO0, 0 }, 4404 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4405 HDA_QUIRK_GPIO0, 0 }, 4406 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4407 HDA_QUIRK_GPIO0, 0 }, 4408 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4409 HDA_QUIRK_EAPDINV, 0 }, 4410 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4411 HDA_QUIRK_EAPDINV, 0 }, 4412 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4413 HDA_QUIRK_OVREF, 0 }, 4414 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4415 HDA_QUIRK_OVREF, 0 }, 4416 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4417 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4418 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4419 HDA_QUIRK_GPIO1, 0 }, 4420 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4421 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4422 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4423 HDA_QUIRK_EAPDINV, 0 }, 4424 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4425 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4426 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4427 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4428 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4429 HDA_QUIRK_GPIO0, 0 }, 4430 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4431 HDA_QUIRK_GPIO0, 0 }, 4432 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4433 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4434 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4435 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4436 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4437 0, HDA_QUIRK_FORCESTEREO } 4438}; 4439#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4440 4441static void 4442hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4443{ 4444 struct hdac_widget *w; 4445 uint32_t id, subvendor; 4446 int i; 4447 4448 id = hdac_codec_id(devinfo->codec); 4449 subvendor = devinfo->codec->sc->pci_subvendor; 4450 4451 /* 4452 * Quirks 4453 */ 4454 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4455 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4456 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4457 continue; 4458 if (hdac_quirks[i].set != 0) 4459 devinfo->function.audio.quirks |= 4460 hdac_quirks[i].set; 4461 if (hdac_quirks[i].unset != 0) 4462 devinfo->function.audio.quirks &= 4463 ~(hdac_quirks[i].unset); 4464 } 4465 4466 switch (id) { 4467 case HDA_CODEC_ALC883: 4468 /* 4469 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4470 * Clear vref cap for jack connectivity. 4471 */ 4472 w = hdac_widget_get(devinfo, 24); 4473 if (w != NULL && w->enable != 0 && w->type == 4474 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4475 (w->wclass.pin.config & 4476 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4477 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4478 w->wclass.pin.cap &= ~( 4479 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4480 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4481 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4482 w = hdac_widget_get(devinfo, 25); 4483 if (w != NULL && w->enable != 0 && w->type == 4484 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4485 (w->wclass.pin.config & 4486 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4487 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4488 w->wclass.pin.cap &= ~( 4489 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4490 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4491 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4492 /* 4493 * nid: 26 = Line-in, leave it alone. 4494 */ 4495 break; 4496 case HDA_CODEC_AD1986A: 4497 if (subvendor == ASUS_A8X_SUBVENDOR) { 4498 /* 4499 * This is just plain ridiculous.. There 4500 * are several A8 series that share the same 4501 * pci id but works differently (EAPD). 4502 */ 4503 w = hdac_widget_get(devinfo, 26); 4504 if (w != NULL && w->type == 4505 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4506 (w->wclass.pin.config & 4507 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4508 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4509 devinfo->function.audio.quirks &= 4510 ~HDA_QUIRK_EAPDINV; 4511 } 4512 break; 4513 case HDA_CODEC_AD1981HD: 4514 /* 4515 * This codec has very unusual design with several 4516 * points inappropriate for the present parser. 4517 */ 4518 /* Disable recording from mono playback mix. */ 4519 w = hdac_widget_get(devinfo, 21); 4520 if (w != NULL) 4521 w->connsenable[3] = 0; 4522 /* Disable rear to front mic mixer, use separately. */ 4523 w = hdac_widget_get(devinfo, 31); 4524 if (w != NULL) 4525 w->enable = 0; 4526 /* Disable playback mixer, use direct bypass. */ 4527 w = hdac_widget_get(devinfo, 14); 4528 if (w != NULL) 4529 w->enable = 0; 4530 break; 4531 } 4532} 4533 4534/* 4535 * Trace path from DAC to pin. 4536 */ 4537static nid_t 4538hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4539 int dupseq, int min, int only, int depth) 4540{ 4541 struct hdac_widget *w; 4542 int i, im = -1; 4543 nid_t m = 0, ret; 4544 4545 if (depth > HDA_PARSE_MAXDEPTH) 4546 return (0); 4547 w = hdac_widget_get(devinfo, nid); 4548 if (w == NULL || w->enable == 0) 4549 return (0); 4550 HDA_BOOTHVERBOSE( 4551 if (!only) { 4552 device_printf(devinfo->codec->sc->dev, 4553 " %*stracing via nid %d\n", 4554 depth + 1, "", w->nid); 4555 } 4556 ); 4557 /* Use only unused widgets */ 4558 if (w->bindas >= 0 && w->bindas != as) { 4559 HDA_BOOTHVERBOSE( 4560 if (!only) { 4561 device_printf(devinfo->codec->sc->dev, 4562 " %*snid %d busy by association %d\n", 4563 depth + 1, "", w->nid, w->bindas); 4564 } 4565 ); 4566 return (0); 4567 } 4568 if (dupseq < 0) { 4569 if (w->bindseqmask != 0) { 4570 HDA_BOOTHVERBOSE( 4571 if (!only) { 4572 device_printf(devinfo->codec->sc->dev, 4573 " %*snid %d busy by seqmask %x\n", 4574 depth + 1, "", w->nid, w->bindseqmask); 4575 } 4576 ); 4577 return (0); 4578 } 4579 } else { 4580 /* If this is headphones - allow duplicate first pin. */ 4581 if (w->bindseqmask != 0 && 4582 (w->bindseqmask & (1 << dupseq)) == 0) { 4583 HDA_BOOTHVERBOSE( 4584 device_printf(devinfo->codec->sc->dev, 4585 " %*snid %d busy by seqmask %x\n", 4586 depth + 1, "", w->nid, w->bindseqmask); 4587 ); 4588 return (0); 4589 } 4590 } 4591 4592 switch (w->type) { 4593 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4594 /* Do not traverse input. AD1988 has digital monitor 4595 for which we are not ready. */ 4596 break; 4597 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4598 /* If we are tracing HP take only dac of first pin. */ 4599 if ((only == 0 || only == w->nid) && 4600 (w->nid >= min) && (dupseq < 0 || w->nid == 4601 devinfo->function.audio.as[as].dacs[dupseq])) 4602 m = w->nid; 4603 break; 4604 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4605 if (depth > 0) 4606 break; 4607 /* Fall */ 4608 default: 4609 /* Find reachable DACs with smallest nid respecting constraints. */ 4610 for (i = 0; i < w->nconns; i++) { 4611 if (w->connsenable[i] == 0) 4612 continue; 4613 if (w->selconn != -1 && w->selconn != i) 4614 continue; 4615 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4616 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4617 if (m == 0 || ret < m) { 4618 m = ret; 4619 im = i; 4620 } 4621 if (only || dupseq >= 0) 4622 break; 4623 } 4624 } 4625 if (m && only && ((w->nconns > 1 && 4626 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4627 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4628 w->selconn = im; 4629 break; 4630 } 4631 if (m && only) { 4632 w->bindas = as; 4633 w->bindseqmask |= (1 << seq); 4634 } 4635 HDA_BOOTHVERBOSE( 4636 if (!only) { 4637 device_printf(devinfo->codec->sc->dev, 4638 " %*snid %d returned %d\n", 4639 depth + 1, "", w->nid, m); 4640 } 4641 ); 4642 return (m); 4643} 4644 4645/* 4646 * Trace path from widget to ADC. 4647 */ 4648static nid_t 4649hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4650 int only, int depth) 4651{ 4652 struct hdac_widget *w, *wc; 4653 int i, j; 4654 nid_t res = 0; 4655 4656 if (depth > HDA_PARSE_MAXDEPTH) 4657 return (0); 4658 w = hdac_widget_get(devinfo, nid); 4659 if (w == NULL || w->enable == 0) 4660 return (0); 4661 HDA_BOOTHVERBOSE( 4662 device_printf(devinfo->codec->sc->dev, 4663 " %*stracing via nid %d\n", 4664 depth + 1, "", w->nid); 4665 ); 4666 /* Use only unused widgets */ 4667 if (w->bindas >= 0 && w->bindas != as) { 4668 HDA_BOOTHVERBOSE( 4669 device_printf(devinfo->codec->sc->dev, 4670 " %*snid %d busy by association %d\n", 4671 depth + 1, "", w->nid, w->bindas); 4672 ); 4673 return (0); 4674 } 4675 4676 switch (w->type) { 4677 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4678 /* If we are tracing HP take only dac of first pin. */ 4679 if (only == w->nid) 4680 res = 1; 4681 break; 4682 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4683 if (depth > 0) 4684 break; 4685 /* Fall */ 4686 default: 4687 /* Try to find reachable ADCs with specified nid. */ 4688 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4689 wc = hdac_widget_get(devinfo, j); 4690 if (wc == NULL || wc->enable == 0) 4691 continue; 4692 for (i = 0; i < wc->nconns; i++) { 4693 if (wc->connsenable[i] == 0) 4694 continue; 4695 if (wc->conns[i] != nid) 4696 continue; 4697 if (hdac_audio_trace_adc(devinfo, as, seq, 4698 j, only, depth + 1) != 0) { 4699 res = 1; 4700 if (((wc->nconns > 1 && 4701 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4702 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4703 wc->selconn == -1) 4704 wc->selconn = i; 4705 } 4706 } 4707 } 4708 break; 4709 } 4710 if (res) { 4711 w->bindas = as; 4712 w->bindseqmask |= (1 << seq); 4713 } 4714 HDA_BOOTHVERBOSE( 4715 device_printf(devinfo->codec->sc->dev, 4716 " %*snid %d returned %d\n", 4717 depth + 1, "", w->nid, res); 4718 ); 4719 return (res); 4720} 4721 4722/* 4723 * Erase trace path of the specified association. 4724 */ 4725static void 4726hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4727{ 4728 struct hdac_widget *w; 4729 int i; 4730 4731 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4732 w = hdac_widget_get(devinfo, i); 4733 if (w == NULL || w->enable == 0) 4734 continue; 4735 if (w->bindas == as) { 4736 if (seq >= 0) { 4737 w->bindseqmask &= ~(1 << seq); 4738 if (w->bindseqmask == 0) { 4739 w->bindas = -1; 4740 w->selconn = -1; 4741 } 4742 } else { 4743 w->bindas = -1; 4744 w->bindseqmask = 0; 4745 w->selconn = -1; 4746 } 4747 } 4748 } 4749} 4750 4751/* 4752 * Trace association path from DAC to output 4753 */ 4754static int 4755hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4756{ 4757 struct hdac_audio_as *ases = devinfo->function.audio.as; 4758 int i, hpredir; 4759 nid_t min, res; 4760 4761 /* Find next pin */ 4762 for (i = seq; ases[as].pins[i] == 0 && i < 16; i++) 4763 ; 4764 /* Check if there is no any left. If so - we succeded. */ 4765 if (i == 16) 4766 return (1); 4767 4768 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4769 min = 0; 4770 res = 0; 4771 do { 4772 HDA_BOOTHVERBOSE( 4773 device_printf(devinfo->codec->sc->dev, 4774 " Tracing pin %d with min nid %d", 4775 ases[as].pins[i], min); 4776 if (hpredir >= 0) 4777 printf(" and hpredir %d", hpredir); 4778 printf("\n"); 4779 ); 4780 /* Trace this pin taking min nid into account. */ 4781 res = hdac_audio_trace_dac(devinfo, as, i, 4782 ases[as].pins[i], hpredir, min, 0, 0); 4783 if (res == 0) { 4784 /* If we failed - return to previous and redo it. */ 4785 HDA_BOOTVERBOSE( 4786 device_printf(devinfo->codec->sc->dev, 4787 " Unable to trace pin %d seq %d with min " 4788 "nid %d", 4789 ases[as].pins[i], i, min); 4790 if (hpredir >= 0) 4791 printf(" and hpredir %d", hpredir); 4792 printf("\n"); 4793 ); 4794 return (0); 4795 } 4796 HDA_BOOTVERBOSE( 4797 device_printf(devinfo->codec->sc->dev, 4798 " Pin %d traced to DAC %d", 4799 ases[as].pins[i], res); 4800 if (hpredir >= 0) 4801 printf(" and hpredir %d", hpredir); 4802 if (ases[as].fakeredir) 4803 printf(" with fake redirection"); 4804 printf("\n"); 4805 ); 4806 /* Trace again to mark the path */ 4807 hdac_audio_trace_dac(devinfo, as, i, 4808 ases[as].pins[i], hpredir, min, res, 0); 4809 ases[as].dacs[i] = res; 4810 /* We succeded, so call next. */ 4811 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4812 return (1); 4813 /* If next failed, we should retry with next min */ 4814 hdac_audio_undo_trace(devinfo, as, i); 4815 ases[as].dacs[i] = 0; 4816 min = res + 1; 4817 } while (1); 4818} 4819 4820/* 4821 * Trace association path from input to ADC 4822 */ 4823static int 4824hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4825{ 4826 struct hdac_audio_as *ases = devinfo->function.audio.as; 4827 struct hdac_widget *w; 4828 int i, j, k; 4829 4830 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4831 w = hdac_widget_get(devinfo, j); 4832 if (w == NULL || w->enable == 0) 4833 continue; 4834 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4835 continue; 4836 if (w->bindas >= 0 && w->bindas != as) 4837 continue; 4838 4839 /* Find next pin */ 4840 for (i = 0; i < 16; i++) { 4841 if (ases[as].pins[i] == 0) 4842 continue; 4843 4844 HDA_BOOTHVERBOSE( 4845 device_printf(devinfo->codec->sc->dev, 4846 " Tracing pin %d to ADC %d\n", 4847 ases[as].pins[i], j); 4848 ); 4849 /* Trace this pin taking goal into account. */ 4850 if (hdac_audio_trace_adc(devinfo, as, i, 4851 ases[as].pins[i], j, 0) == 0) { 4852 /* If we failed - return to previous and redo it. */ 4853 HDA_BOOTVERBOSE( 4854 device_printf(devinfo->codec->sc->dev, 4855 " Unable to trace pin %d to ADC %d, undo traces\n", 4856 ases[as].pins[i], j); 4857 ); 4858 hdac_audio_undo_trace(devinfo, as, -1); 4859 for (k = 0; k < 16; k++) 4860 ases[as].dacs[k] = 0; 4861 break; 4862 } 4863 HDA_BOOTVERBOSE( 4864 device_printf(devinfo->codec->sc->dev, 4865 " Pin %d traced to ADC %d\n", 4866 ases[as].pins[i], j); 4867 ); 4868 ases[as].dacs[i] = j; 4869 } 4870 if (i == 16) 4871 return (1); 4872 } 4873 return (0); 4874} 4875 4876/* 4877 * Trace input monitor path from mixer to output association. 4878 */ 4879static int 4880hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4881{ 4882 struct hdac_audio_as *ases = devinfo->function.audio.as; 4883 struct hdac_widget *w, *wc; 4884 int i, j; 4885 nid_t res = 0; 4886 4887 if (depth > HDA_PARSE_MAXDEPTH) 4888 return (0); 4889 w = hdac_widget_get(devinfo, nid); 4890 if (w == NULL || w->enable == 0) 4891 return (0); 4892 HDA_BOOTHVERBOSE( 4893 device_printf(devinfo->codec->sc->dev, 4894 " %*stracing via nid %d\n", 4895 depth + 1, "", w->nid); 4896 ); 4897 /* Use only unused widgets */ 4898 if (depth > 0 && w->bindas != -1) { 4899 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4900 HDA_BOOTHVERBOSE( 4901 device_printf(devinfo->codec->sc->dev, 4902 " %*snid %d found output association %d\n", 4903 depth + 1, "", w->nid, w->bindas); 4904 ); 4905 return (1); 4906 } else { 4907 HDA_BOOTHVERBOSE( 4908 device_printf(devinfo->codec->sc->dev, 4909 " %*snid %d busy by input association %d\n", 4910 depth + 1, "", w->nid, w->bindas); 4911 ); 4912 return (0); 4913 } 4914 } 4915 4916 switch (w->type) { 4917 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4918 /* Do not traverse input. AD1988 has digital monitor 4919 for which we are not ready. */ 4920 break; 4921 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4922 if (depth > 0) 4923 break; 4924 /* Fall */ 4925 default: 4926 /* Try to find reachable ADCs with specified nid. */ 4927 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4928 wc = hdac_widget_get(devinfo, j); 4929 if (wc == NULL || wc->enable == 0) 4930 continue; 4931 for (i = 0; i < wc->nconns; i++) { 4932 if (wc->connsenable[i] == 0) 4933 continue; 4934 if (wc->conns[i] != nid) 4935 continue; 4936 if (hdac_audio_trace_to_out(devinfo, 4937 j, depth + 1) != 0) { 4938 res = 1; 4939 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4940 wc->selconn == -1) 4941 wc->selconn = i; 4942 } 4943 } 4944 } 4945 break; 4946 } 4947 if (res) 4948 w->bindas = -2; 4949 4950 HDA_BOOTHVERBOSE( 4951 device_printf(devinfo->codec->sc->dev, 4952 " %*snid %d returned %d\n", 4953 depth + 1, "", w->nid, res); 4954 ); 4955 return (res); 4956} 4957 4958/* 4959 * Trace extra associations (beeper, monitor) 4960 */ 4961static void 4962hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4963{ 4964 struct hdac_audio_as *as = devinfo->function.audio.as; 4965 struct hdac_widget *w; 4966 int j; 4967 4968 /* Input monitor */ 4969 /* Find mixer associated with input, but supplying signal 4970 for output associations. Hope it will be input monitor. */ 4971 HDA_BOOTVERBOSE( 4972 device_printf(devinfo->codec->sc->dev, 4973 "Tracing input monitor\n"); 4974 ); 4975 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4976 w = hdac_widget_get(devinfo, j); 4977 if (w == NULL || w->enable == 0) 4978 continue; 4979 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4980 continue; 4981 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 4982 continue; 4983 HDA_BOOTVERBOSE( 4984 device_printf(devinfo->codec->sc->dev, 4985 " Tracing nid %d to out\n", 4986 j); 4987 ); 4988 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 4989 HDA_BOOTVERBOSE( 4990 device_printf(devinfo->codec->sc->dev, 4991 " nid %d is input monitor\n", 4992 w->nid); 4993 ); 4994 w->pflags |= HDA_ADC_MONITOR; 4995 w->ossdev = SOUND_MIXER_IMIX; 4996 } 4997 } 4998 4999 /* Beeper */ 5000 HDA_BOOTVERBOSE( 5001 device_printf(devinfo->codec->sc->dev, 5002 "Tracing beeper\n"); 5003 ); 5004 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5005 w = hdac_widget_get(devinfo, j); 5006 if (w == NULL || w->enable == 0) 5007 continue; 5008 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5009 continue; 5010 HDA_BOOTHVERBOSE( 5011 device_printf(devinfo->codec->sc->dev, 5012 " Tracing nid %d to out\n", 5013 j); 5014 ); 5015 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5016 HDA_BOOTVERBOSE( 5017 device_printf(devinfo->codec->sc->dev, 5018 " nid %d traced to out\n", 5019 j); 5020 ); 5021 } 5022 w->bindas = -2; 5023 } 5024} 5025 5026/* 5027 * Bind assotiations to PCM channels 5028 */ 5029static void 5030hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5031{ 5032 struct hdac_softc *sc = devinfo->codec->sc; 5033 struct hdac_audio_as *as = devinfo->function.audio.as; 5034 int j, cnt = 0, free; 5035 5036 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5037 if (as[j].enable) 5038 cnt++; 5039 } 5040 if (sc->num_chans == 0) { 5041 sc->chans = (struct hdac_chan *)malloc( 5042 sizeof(struct hdac_chan) * cnt, 5043 M_HDAC, M_ZERO | M_NOWAIT); 5044 if (sc->chans == NULL) { 5045 device_printf(devinfo->codec->sc->dev, 5046 "Channels memory allocation failed!\n"); 5047 return; 5048 } 5049 } else { 5050 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5051 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5052 M_HDAC, M_ZERO | M_NOWAIT); 5053 if (sc->chans == NULL) { 5054 sc->num_chans = 0; 5055 device_printf(devinfo->codec->sc->dev, 5056 "Channels memory allocation failed!\n"); 5057 return; 5058 } 5059 } 5060 free = sc->num_chans; 5061 sc->num_chans += cnt; 5062 5063 for (j = free; j < free + cnt; j++) { 5064 devinfo->codec->sc->chans[j].devinfo = devinfo; 5065 devinfo->codec->sc->chans[j].as = -1; 5066 } 5067 5068 /* Assign associations in order of their numbers, */ 5069 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5070 if (as[j].enable == 0) 5071 continue; 5072 5073 as[j].chan = free; 5074 devinfo->codec->sc->chans[free].as = j; 5075 if (as[j].dir == HDA_CTL_IN) { 5076 devinfo->codec->sc->chans[free].dir = PCMDIR_REC; 5077 devinfo->function.audio.reccnt++; 5078 } else { 5079 devinfo->codec->sc->chans[free].dir = PCMDIR_PLAY; 5080 devinfo->function.audio.playcnt++; 5081 } 5082 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5083 free++; 5084 } 5085} 5086 5087static void 5088hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5089{ 5090 struct hdac_widget *w; 5091 int i; 5092 5093 /* Disable power and volume widgets. */ 5094 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5095 w = hdac_widget_get(devinfo, i); 5096 if (w == NULL || w->enable == 0) 5097 continue; 5098 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5099 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5100 w->enable = 0; 5101 HDA_BOOTHVERBOSE( 5102 device_printf(devinfo->codec->sc->dev, 5103 " Disabling nid %d due to it's" 5104 " non-audio type.\n", 5105 w->nid); 5106 ); 5107 } 5108 } 5109} 5110 5111static void 5112hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5113{ 5114 struct hdac_widget *w, *cw; 5115 struct hdac_audio_ctl *ctl; 5116 int done, found, i, j, k; 5117 5118 /* Disable useless pins. */ 5119 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5120 w = hdac_widget_get(devinfo, i); 5121 if (w == NULL || w->enable == 0) 5122 continue; 5123 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5124 (w->wclass.pin.config & 5125 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5126 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5127 w->enable = 0; 5128 HDA_BOOTHVERBOSE( 5129 device_printf(devinfo->codec->sc->dev, 5130 " Disabling pin nid %d due" 5131 " to None connectivity.\n", 5132 w->nid); 5133 ); 5134 } 5135 } 5136 do { 5137 done = 1; 5138 /* Disable and mute controls for disabled widgets. */ 5139 i = 0; 5140 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5141 if (ctl->enable == 0) 5142 continue; 5143 if (ctl->widget->enable == 0 || 5144 (ctl->childwidget != NULL && 5145 ctl->childwidget->enable == 0)) { 5146 ctl->forcemute = 1; 5147 ctl->muted = HDA_AMP_MUTE_ALL; 5148 ctl->left = 0; 5149 ctl->right = 0; 5150 ctl->enable = 0; 5151 if (ctl->ndir == HDA_CTL_IN) 5152 ctl->widget->connsenable[ctl->index] = 0; 5153 done = 0; 5154 HDA_BOOTHVERBOSE( 5155 device_printf(devinfo->codec->sc->dev, 5156 " Disabling ctl %d nid %d cnid %d due" 5157 " to disabled widget.\n", i, 5158 ctl->widget->nid, 5159 (ctl->childwidget != NULL)? 5160 ctl->childwidget->nid:-1); 5161 ); 5162 } 5163 } 5164 /* Disable useless widgets. */ 5165 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5166 w = hdac_widget_get(devinfo, i); 5167 if (w == NULL || w->enable == 0) 5168 continue; 5169 /* Disable inputs with disabled child widgets. */ 5170 for (j = 0; j < w->nconns; j++) { 5171 if (w->connsenable[j]) { 5172 cw = hdac_widget_get(devinfo, w->conns[j]); 5173 if (cw == NULL || cw->enable == 0) { 5174 w->connsenable[j] = 0; 5175 HDA_BOOTHVERBOSE( 5176 device_printf(devinfo->codec->sc->dev, 5177 " Disabling nid %d connection %d due" 5178 " to disabled child widget.\n", 5179 i, j); 5180 ); 5181 } 5182 } 5183 } 5184 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5185 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5186 continue; 5187 /* Disable mixers and selectors without inputs. */ 5188 found = 0; 5189 for (j = 0; j < w->nconns; j++) { 5190 if (w->connsenable[j]) { 5191 found = 1; 5192 break; 5193 } 5194 } 5195 if (found == 0) { 5196 w->enable = 0; 5197 done = 0; 5198 HDA_BOOTHVERBOSE( 5199 device_printf(devinfo->codec->sc->dev, 5200 " Disabling nid %d due to all it's" 5201 " inputs disabled.\n", w->nid); 5202 ); 5203 } 5204 /* Disable nodes without consumers. */ 5205 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5206 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5207 continue; 5208 found = 0; 5209 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5210 cw = hdac_widget_get(devinfo, k); 5211 if (cw == NULL || cw->enable == 0) 5212 continue; 5213 for (j = 0; j < cw->nconns; j++) { 5214 if (cw->connsenable[j] && cw->conns[j] == i) { 5215 found = 1; 5216 break; 5217 } 5218 } 5219 } 5220 if (found == 0) { 5221 w->enable = 0; 5222 done = 0; 5223 HDA_BOOTHVERBOSE( 5224 device_printf(devinfo->codec->sc->dev, 5225 " Disabling nid %d due to all it's" 5226 " consumers disabled.\n", w->nid); 5227 ); 5228 } 5229 } 5230 } while (done == 0); 5231 5232} 5233 5234static void 5235hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5236{ 5237 struct hdac_audio_as *as = devinfo->function.audio.as; 5238 struct hdac_widget *w, *cw; 5239 struct hdac_audio_ctl *ctl; 5240 int i, j, k; 5241 5242 /* Disable unassosiated widgets. */ 5243 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5244 w = hdac_widget_get(devinfo, i); 5245 if (w == NULL || w->enable == 0) 5246 continue; 5247 if (w->bindas == -1) { 5248 w->enable = 0; 5249 HDA_BOOTHVERBOSE( 5250 device_printf(devinfo->codec->sc->dev, 5251 " Disabling unassociated nid %d.\n", 5252 w->nid); 5253 ); 5254 } 5255 } 5256 /* Disable input connections on input pin and 5257 * output on output. */ 5258 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5259 w = hdac_widget_get(devinfo, i); 5260 if (w == NULL || w->enable == 0) 5261 continue; 5262 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5263 continue; 5264 if (w->bindas < 0) 5265 continue; 5266 if (as[w->bindas].dir == HDA_CTL_IN) { 5267 for (j = 0; j < w->nconns; j++) { 5268 if (w->connsenable[j] == 0) 5269 continue; 5270 w->connsenable[j] = 0; 5271 HDA_BOOTHVERBOSE( 5272 device_printf(devinfo->codec->sc->dev, 5273 " Disabling connection to input pin " 5274 "nid %d conn %d.\n", 5275 i, j); 5276 ); 5277 } 5278 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5279 HDA_CTL_IN, -1, 1); 5280 if (ctl && ctl->enable) { 5281 ctl->forcemute = 1; 5282 ctl->muted = HDA_AMP_MUTE_ALL; 5283 ctl->left = 0; 5284 ctl->right = 0; 5285 ctl->enable = 0; 5286 } 5287 } else { 5288 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5289 HDA_CTL_OUT, -1, 1); 5290 if (ctl && ctl->enable) { 5291 ctl->forcemute = 1; 5292 ctl->muted = HDA_AMP_MUTE_ALL; 5293 ctl->left = 0; 5294 ctl->right = 0; 5295 ctl->enable = 0; 5296 } 5297 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5298 cw = hdac_widget_get(devinfo, k); 5299 if (cw == NULL || cw->enable == 0) 5300 continue; 5301 for (j = 0; j < cw->nconns; j++) { 5302 if (cw->connsenable[j] && cw->conns[j] == i) { 5303 cw->connsenable[j] = 0; 5304 HDA_BOOTHVERBOSE( 5305 device_printf(devinfo->codec->sc->dev, 5306 " Disabling connection from output pin " 5307 "nid %d conn %d cnid %d.\n", 5308 k, j, i); 5309 ); 5310 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5311 cw->nconns > 1) 5312 continue; 5313 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5314 HDA_CTL_IN, j, 1); 5315 if (ctl && ctl->enable) { 5316 ctl->forcemute = 1; 5317 ctl->muted = HDA_AMP_MUTE_ALL; 5318 ctl->left = 0; 5319 ctl->right = 0; 5320 ctl->enable = 0; 5321 } 5322 } 5323 } 5324 } 5325 } 5326 } 5327} 5328 5329static void 5330hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5331{ 5332 struct hdac_audio_as *as = devinfo->function.audio.as; 5333 struct hdac_widget *w; 5334 int i, j; 5335 5336 /* On playback path we can safely disable all unseleted inputs. */ 5337 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5338 w = hdac_widget_get(devinfo, i); 5339 if (w == NULL || w->enable == 0) 5340 continue; 5341 if (w->nconns <= 1) 5342 continue; 5343 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5344 continue; 5345 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5346 continue; 5347 for (j = 0; j < w->nconns; j++) { 5348 if (w->connsenable[j] == 0) 5349 continue; 5350 if (w->selconn < 0 || w->selconn == j) 5351 continue; 5352 w->connsenable[j] = 0; 5353 HDA_BOOTHVERBOSE( 5354 device_printf(devinfo->codec->sc->dev, 5355 " Disabling unselected connection " 5356 "nid %d conn %d.\n", 5357 i, j); 5358 ); 5359 } 5360 } 5361} 5362 5363static void 5364hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5365{ 5366 struct hdac_widget *w, *cw; 5367 struct hdac_audio_ctl *ctl; 5368 int i, j; 5369 5370 /* Disable crossassociatement connections. */ 5371 /* ... using selectors */ 5372 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5373 w = hdac_widget_get(devinfo, i); 5374 if (w == NULL || w->enable == 0) 5375 continue; 5376 if (w->nconns <= 1) 5377 continue; 5378 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5379 continue; 5380 if (w->bindas == -2) 5381 continue; 5382 for (j = 0; j < w->nconns; j++) { 5383 if (w->connsenable[j] == 0) 5384 continue; 5385 cw = hdac_widget_get(devinfo, w->conns[j]); 5386 if (cw == NULL || w->enable == 0) 5387 continue; 5388 if (w->bindas == cw->bindas || cw->bindas == -2) 5389 continue; 5390 w->connsenable[j] = 0; 5391 HDA_BOOTHVERBOSE( 5392 device_printf(devinfo->codec->sc->dev, 5393 " Disabling crossassociatement connection " 5394 "nid %d conn %d cnid %d.\n", 5395 i, j, cw->nid); 5396 ); 5397 } 5398 } 5399 /* ... using controls */ 5400 i = 0; 5401 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5402 if (ctl->enable == 0 || ctl->childwidget == NULL) 5403 continue; 5404 if (ctl->widget->bindas == -2 || 5405 ctl->childwidget->bindas == -2) 5406 continue; 5407 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5408 ctl->forcemute = 1; 5409 ctl->muted = HDA_AMP_MUTE_ALL; 5410 ctl->left = 0; 5411 ctl->right = 0; 5412 ctl->enable = 0; 5413 if (ctl->ndir == HDA_CTL_IN) 5414 ctl->widget->connsenable[ctl->index] = 0; 5415 HDA_BOOTHVERBOSE( 5416 device_printf(devinfo->codec->sc->dev, 5417 " Disabling crossassociatement connection " 5418 "ctl %d nid %d cnid %d.\n", i, 5419 ctl->widget->nid, 5420 ctl->childwidget->nid); 5421 ); 5422 } 5423 } 5424 5425} 5426 5427#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5428 5429/* 5430 * Find controls to control amplification for source. 5431 */ 5432static int 5433hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5434 int ossdev, int ctlable, int depth, int need) 5435{ 5436 struct hdac_widget *w, *wc; 5437 struct hdac_audio_ctl *ctl; 5438 int i, j, conns = 0, rneed; 5439 5440 if (depth > HDA_PARSE_MAXDEPTH) 5441 return (need); 5442 5443 w = hdac_widget_get(devinfo, nid); 5444 if (w == NULL || w->enable == 0) 5445 return (need); 5446 5447 /* Count number of active inputs. */ 5448 if (depth > 0) { 5449 for (j = 0; j < w->nconns; j++) { 5450 if (w->connsenable[j]) 5451 conns++; 5452 } 5453 } 5454 5455 /* If this is not a first step - use input mixer. 5456 Pins have common input ctl so care must be taken. */ 5457 if (depth > 0 && ctlable && (conns == 1 || 5458 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5459 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5460 index, 1); 5461 if (ctl) { 5462 if (HDA_CTL_GIVE(ctl) & need) 5463 ctl->ossmask |= (1 << ossdev); 5464 else 5465 ctl->possmask |= (1 << ossdev); 5466 need &= ~HDA_CTL_GIVE(ctl); 5467 } 5468 } 5469 5470 /* If widget has own ossdev - not traverse it. 5471 It will be traversed on it's own. */ 5472 if (w->ossdev >= 0 && depth > 0) 5473 return (need); 5474 5475 /* We must not traverse pin */ 5476 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5477 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5478 depth > 0) 5479 return (need); 5480 5481 /* record that this widget exports such signal, */ 5482 w->ossmask |= (1 << ossdev); 5483 5484 /* If signals mixed, we can't assign controls farther. 5485 * Ignore this on depth zero. Caller must knows why. 5486 * Ignore this for static selectors if this input selected. 5487 */ 5488 if (conns > 1) 5489 ctlable = 0; 5490 5491 if (ctlable) { 5492 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5493 if (ctl) { 5494 if (HDA_CTL_GIVE(ctl) & need) 5495 ctl->ossmask |= (1 << ossdev); 5496 else 5497 ctl->possmask |= (1 << ossdev); 5498 need &= ~HDA_CTL_GIVE(ctl); 5499 } 5500 } 5501 5502 rneed = 0; 5503 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5504 wc = hdac_widget_get(devinfo, i); 5505 if (wc == NULL || wc->enable == 0) 5506 continue; 5507 for (j = 0; j < wc->nconns; j++) { 5508 if (wc->connsenable[j] && wc->conns[j] == nid) { 5509 rneed |= hdac_audio_ctl_source_amp(devinfo, 5510 wc->nid, j, ossdev, ctlable, depth + 1, need); 5511 } 5512 } 5513 } 5514 rneed &= need; 5515 5516 return (rneed); 5517} 5518 5519/* 5520 * Find controls to control amplification for destination. 5521 */ 5522static void 5523hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5524 int ossdev, int depth, int need) 5525{ 5526 struct hdac_audio_as *as = devinfo->function.audio.as; 5527 struct hdac_widget *w, *wc; 5528 struct hdac_audio_ctl *ctl; 5529 int i, j, consumers; 5530 5531 if (depth > HDA_PARSE_MAXDEPTH) 5532 return; 5533 5534 w = hdac_widget_get(devinfo, nid); 5535 if (w == NULL || w->enable == 0) 5536 return; 5537 5538 if (depth > 0) { 5539 /* If this node produce output for several consumers, 5540 we can't touch it. */ 5541 consumers = 0; 5542 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5543 wc = hdac_widget_get(devinfo, i); 5544 if (wc == NULL || wc->enable == 0) 5545 continue; 5546 for (j = 0; j < wc->nconns; j++) { 5547 if (wc->connsenable[j] && wc->conns[j] == nid) 5548 consumers++; 5549 } 5550 } 5551 /* The only exception is if real HP redirection is configured 5552 and this is a duplication point. 5553 XXX: Actually exception is not completely correct. 5554 XXX: Duplication point check is not perfect. */ 5555 if ((consumers == 2 && (w->bindas < 0 || 5556 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5557 (w->bindseqmask & (1 << 15)) == 0)) || 5558 consumers > 2) 5559 return; 5560 5561 /* Else use it's output mixer. */ 5562 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5563 HDA_CTL_OUT, -1, 1); 5564 if (ctl) { 5565 if (HDA_CTL_GIVE(ctl) & need) 5566 ctl->ossmask |= (1 << ossdev); 5567 else 5568 ctl->possmask |= (1 << ossdev); 5569 need &= ~HDA_CTL_GIVE(ctl); 5570 } 5571 } 5572 5573 /* We must not traverse pin */ 5574 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5575 depth > 0) 5576 return; 5577 5578 for (i = 0; i < w->nconns; i++) { 5579 int tneed = need; 5580 if (w->connsenable[i] == 0) 5581 continue; 5582 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5583 HDA_CTL_IN, i, 1); 5584 if (ctl) { 5585 if (HDA_CTL_GIVE(ctl) & tneed) 5586 ctl->ossmask |= (1 << ossdev); 5587 else 5588 ctl->possmask |= (1 << ossdev); 5589 tneed &= ~HDA_CTL_GIVE(ctl); 5590 } 5591 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5592 depth + 1, tneed); 5593 } 5594} 5595 5596/* 5597 * Assign OSS names to sound sources 5598 */ 5599static void 5600hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5601{ 5602 struct hdac_audio_as *as = devinfo->function.audio.as; 5603 struct hdac_widget *w; 5604 int i, j; 5605 int type = -1, use, used = 0; 5606 static const int types[7][13] = { 5607 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5608 SOUND_MIXER_LINE3, -1 }, /* line */ 5609 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5610 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5611 { SOUND_MIXER_CD, -1 }, /* cd */ 5612 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5613 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5614 -1 }, /* digital */ 5615 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5616 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5617 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5618 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5619 -1 } /* others */ 5620 }; 5621 5622 /* Surely known names */ 5623 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5624 w = hdac_widget_get(devinfo, i); 5625 if (w == NULL || w->enable == 0) 5626 continue; 5627 if (w->bindas == -1) 5628 continue; 5629 use = -1; 5630 switch (w->type) { 5631 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5632 if (as[w->bindas].dir == HDA_CTL_OUT) 5633 break; 5634 type = -1; 5635 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5636 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5637 type = 0; 5638 break; 5639 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5640 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5641 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5642 break; 5643 type = 1; 5644 break; 5645 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5646 type = 3; 5647 break; 5648 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5649 type = 4; 5650 break; 5651 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5652 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5653 type = 5; 5654 break; 5655 } 5656 if (type == -1) 5657 break; 5658 j = 0; 5659 while (types[type][j] >= 0 && 5660 (used & (1 << types[type][j])) != 0) { 5661 j++; 5662 } 5663 if (types[type][j] >= 0) 5664 use = types[type][j]; 5665 break; 5666 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5667 use = SOUND_MIXER_PCM; 5668 break; 5669 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5670 use = SOUND_MIXER_SPEAKER; 5671 break; 5672 default: 5673 break; 5674 } 5675 if (use >= 0) { 5676 w->ossdev = use; 5677 used |= (1 << use); 5678 } 5679 } 5680 /* Semi-known names */ 5681 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5682 w = hdac_widget_get(devinfo, i); 5683 if (w == NULL || w->enable == 0) 5684 continue; 5685 if (w->ossdev >= 0) 5686 continue; 5687 if (w->bindas == -1) 5688 continue; 5689 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5690 continue; 5691 if (as[w->bindas].dir == HDA_CTL_OUT) 5692 continue; 5693 type = -1; 5694 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5695 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5696 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5697 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5698 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5699 type = 0; 5700 break; 5701 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5702 type = 2; 5703 break; 5704 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5705 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5706 type = 5; 5707 break; 5708 } 5709 if (type == -1) 5710 break; 5711 j = 0; 5712 while (types[type][j] >= 0 && 5713 (used & (1 << types[type][j])) != 0) { 5714 j++; 5715 } 5716 if (types[type][j] >= 0) { 5717 w->ossdev = types[type][j]; 5718 used |= (1 << types[type][j]); 5719 } 5720 } 5721 /* Others */ 5722 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5723 w = hdac_widget_get(devinfo, i); 5724 if (w == NULL || w->enable == 0) 5725 continue; 5726 if (w->ossdev >= 0) 5727 continue; 5728 if (w->bindas == -1) 5729 continue; 5730 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5731 continue; 5732 if (as[w->bindas].dir == HDA_CTL_OUT) 5733 continue; 5734 j = 0; 5735 while (types[6][j] >= 0 && 5736 (used & (1 << types[6][j])) != 0) { 5737 j++; 5738 } 5739 if (types[6][j] >= 0) { 5740 w->ossdev = types[6][j]; 5741 used |= (1 << types[6][j]); 5742 } 5743 } 5744} 5745 5746static void 5747hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5748{ 5749 struct hdac_audio_as *as = devinfo->function.audio.as; 5750 int j, res; 5751 5752 /* Trace all associations in order of their numbers, */ 5753 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5754 if (as[j].enable == 0) 5755 continue; 5756 HDA_BOOTVERBOSE( 5757 device_printf(devinfo->codec->sc->dev, 5758 "Tracing association %d (%d)\n", j, as[j].index); 5759 ); 5760 if (as[j].dir == HDA_CTL_OUT) { 5761retry: 5762 res = hdac_audio_trace_as_out(devinfo, j, 0); 5763 if (res == 0 && as[j].hpredir >= 0 && 5764 as[j].fakeredir == 0) { 5765 /* If codec can't do analog HP redirection 5766 try to make it using one more DAC. */ 5767 as[j].fakeredir = 1; 5768 goto retry; 5769 } 5770 } else { 5771 res = hdac_audio_trace_as_in(devinfo, j); 5772 } 5773 if (res) { 5774 HDA_BOOTVERBOSE( 5775 device_printf(devinfo->codec->sc->dev, 5776 "Association %d (%d) trace succeded\n", 5777 j, as[j].index); 5778 ); 5779 } else { 5780 HDA_BOOTVERBOSE( 5781 device_printf(devinfo->codec->sc->dev, 5782 "Association %d (%d) trace failed\n", 5783 j, as[j].index); 5784 ); 5785 as[j].enable = 0; 5786 } 5787 } 5788 5789 /* Trace mixer and beeper pseudo associations. */ 5790 hdac_audio_trace_as_extra(devinfo); 5791} 5792 5793static void 5794hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5795{ 5796 struct hdac_audio_as *as = devinfo->function.audio.as; 5797 struct hdac_audio_ctl *ctl; 5798 struct hdac_widget *w; 5799 int i; 5800 5801 /* Assign mixers to the tree. */ 5802 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5803 w = hdac_widget_get(devinfo, i); 5804 if (w == NULL || w->enable == 0) 5805 continue; 5806 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5807 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5808 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5809 as[w->bindas].dir == HDA_CTL_IN)) { 5810 if (w->ossdev < 0) 5811 continue; 5812 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5813 w->ossdev, 1, 0, 1); 5814 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5815 if (w->ossdev < 0) 5816 continue; 5817 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5818 w->ossdev, 1, 0, 1)) { 5819 /* If we are unable to control input monitor 5820 as source - try to control it as destination. */ 5821 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5822 w->ossdev, 0, 1); 5823 } 5824 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5825 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5826 SOUND_MIXER_RECLEV, 0, 1); 5827 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5828 as[w->bindas].dir == HDA_CTL_OUT) { 5829 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5830 SOUND_MIXER_VOLUME, 0, 1); 5831 } 5832 } 5833 /* Treat unrequired as possible. */ 5834 i = 0; 5835 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5836 if (ctl->ossmask == 0) 5837 ctl->ossmask = ctl->possmask; 5838 } 5839} 5840 5841static void 5842hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5843{ 5844 struct hdac_audio_as *as = devinfo->function.audio.as; 5845 struct hdac_widget *w; 5846 uint32_t pincap; 5847 int i; 5848 5849 for (i = 0; i < devinfo->nodecnt; i++) { 5850 w = &devinfo->widget[i]; 5851 if (w == NULL) 5852 continue; 5853 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5854 continue; 5855 5856 pincap = w->wclass.pin.cap; 5857 5858 /* Disable everything. */ 5859 w->wclass.pin.ctrl &= ~( 5860 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5861 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5862 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5863 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5864 5865 if (w->enable == 0 || 5866 w->bindas < 0 || as[w->bindas].enable == 0) { 5867 /* Pin is unused so left it disabled. */ 5868 continue; 5869 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5870 /* Input pin, configure for input. */ 5871 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5872 w->wclass.pin.ctrl |= 5873 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5874 5875 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5876 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5877 w->wclass.pin.ctrl |= 5878 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5879 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5880 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5881 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5882 w->wclass.pin.ctrl |= 5883 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5884 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5885 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5886 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5887 w->wclass.pin.ctrl |= 5888 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5889 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5890 } else { 5891 /* Output pin, configure for output. */ 5892 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5893 w->wclass.pin.ctrl |= 5894 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5895 5896 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5897 (w->wclass.pin.config & 5898 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5899 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5900 w->wclass.pin.ctrl |= 5901 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5902 5903 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5904 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5905 w->wclass.pin.ctrl |= 5906 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5907 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5908 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5909 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5910 w->wclass.pin.ctrl |= 5911 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5912 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5913 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5914 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5915 w->wclass.pin.ctrl |= 5916 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5917 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5918 } 5919 } 5920} 5921 5922static void 5923hdac_audio_commit(struct hdac_devinfo *devinfo) 5924{ 5925 struct hdac_softc *sc = devinfo->codec->sc; 5926 struct hdac_widget *w; 5927 nid_t cad; 5928 uint32_t gdata, gmask, gdir; 5929 int commitgpio, numgpio; 5930 int i; 5931 5932 cad = devinfo->codec->cad; 5933 5934 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5935 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5936 0x7e7, 0), cad); 5937 5938 gdata = 0; 5939 gmask = 0; 5940 gdir = 0; 5941 commitgpio = 0; 5942 5943 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5944 devinfo->function.audio.gpio); 5945 5946 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5947 commitgpio = (numgpio > 0) ? 1 : 0; 5948 else { 5949 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5950 if (!(devinfo->function.audio.quirks & 5951 (1 << i))) 5952 continue; 5953 if (commitgpio == 0) { 5954 commitgpio = 1; 5955 HDA_BOOTVERBOSE( 5956 gdata = hdac_command(sc, 5957 HDA_CMD_GET_GPIO_DATA(cad, 5958 devinfo->nid), cad); 5959 gmask = hdac_command(sc, 5960 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5961 devinfo->nid), cad); 5962 gdir = hdac_command(sc, 5963 HDA_CMD_GET_GPIO_DIRECTION(cad, 5964 devinfo->nid), cad); 5965 device_printf(sc->dev, 5966 "GPIO init: data=0x%08x " 5967 "mask=0x%08x dir=0x%08x\n", 5968 gdata, gmask, gdir); 5969 gdata = 0; 5970 gmask = 0; 5971 gdir = 0; 5972 ); 5973 } 5974 gdata |= 1 << i; 5975 gmask |= 1 << i; 5976 gdir |= 1 << i; 5977 } 5978 } 5979 5980 if (commitgpio != 0) { 5981 HDA_BOOTVERBOSE( 5982 device_printf(sc->dev, 5983 "GPIO commit: data=0x%08x mask=0x%08x " 5984 "dir=0x%08x\n", 5985 gdata, gmask, gdir); 5986 ); 5987 hdac_command(sc, 5988 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5989 gmask), cad); 5990 hdac_command(sc, 5991 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5992 gdir), cad); 5993 hdac_command(sc, 5994 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5995 gdata), cad); 5996 } 5997 5998 for (i = 0; i < devinfo->nodecnt; i++) { 5999 w = &devinfo->widget[i]; 6000 if (w == NULL) 6001 continue; 6002 if (w->selconn == -1) 6003 w->selconn = 0; 6004 if (w->nconns > 0) 6005 hdac_widget_connection_select(w, w->selconn); 6006 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6007 hdac_command(sc, 6008 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6009 w->wclass.pin.ctrl), cad); 6010 } 6011 if (w->param.eapdbtl != HDAC_INVALID) { 6012 uint32_t val; 6013 6014 val = w->param.eapdbtl; 6015 if (devinfo->function.audio.quirks & 6016 HDA_QUIRK_EAPDINV) 6017 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6018 hdac_command(sc, 6019 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6020 val), cad); 6021 6022 } 6023 DELAY(1000); 6024 } 6025} 6026 6027static void 6028hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6029{ 6030 struct hdac_audio_ctl *ctl; 6031 int i, z; 6032 6033 i = 0; 6034 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6035 if (ctl->enable == 0) { 6036 /* Mute disabled controls. */ 6037 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6038 continue; 6039 } 6040 /* Init controls to 0dB amplification. */ 6041 z = ctl->offset; 6042 if (z > ctl->step) 6043 z = ctl->step; 6044 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6045 } 6046} 6047 6048static void 6049hdac_powerup(struct hdac_devinfo *devinfo) 6050{ 6051 struct hdac_softc *sc = devinfo->codec->sc; 6052 nid_t cad = devinfo->codec->cad; 6053 int i; 6054 6055 hdac_command(sc, 6056 HDA_CMD_SET_POWER_STATE(cad, 6057 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6058 cad); 6059 DELAY(100); 6060 6061 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6062 hdac_command(sc, 6063 HDA_CMD_SET_POWER_STATE(cad, 6064 i, HDA_CMD_POWER_STATE_D0), 6065 cad); 6066 } 6067 DELAY(1000); 6068} 6069 6070static int 6071hdac_pcmchannel_setup(struct hdac_chan *ch) 6072{ 6073 struct hdac_devinfo *devinfo = ch->devinfo; 6074 struct hdac_audio_as *as = devinfo->function.audio.as; 6075 struct hdac_widget *w; 6076 uint32_t cap, fmtcap, pcmcap; 6077 int i, j, ret, max; 6078 6079 ch->caps = hdac_caps; 6080 ch->caps.fmtlist = ch->fmtlist; 6081 ch->bit16 = 1; 6082 ch->bit32 = 0; 6083 ch->pcmrates[0] = 48000; 6084 ch->pcmrates[1] = 0; 6085 6086 ret = 0; 6087 fmtcap = devinfo->function.audio.supp_stream_formats; 6088 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6089 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6090 6091 for (i = 0; i < 16 && ret < max; i++) { 6092 /* Check as is correct */ 6093 if (ch->as < 0) 6094 break; 6095 /* Cound only present DACs */ 6096 if (as[ch->as].dacs[i] <= 0) 6097 continue; 6098 /* Ignore duplicates */ 6099 for (j = 0; j < ret; j++) { 6100 if (ch->io[j] == as[ch->as].dacs[i]) 6101 break; 6102 } 6103 if (j < ret) 6104 continue; 6105 6106 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6107 if (w == NULL || w->enable == 0) 6108 continue; 6109 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6110 continue; 6111 cap = w->param.supp_stream_formats; 6112 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6113 }*/ 6114 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6115 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6116 continue; 6117 /* Many codec does not declare AC3 support on SPDIF. 6118 I don't beleave that they doesn't support it! */ 6119 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6120 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6121 if (ret == 0) { 6122 fmtcap = cap; 6123 pcmcap = w->param.supp_pcm_size_rate; 6124 } else { 6125 fmtcap &= cap; 6126 pcmcap &= w->param.supp_pcm_size_rate; 6127 } 6128 ch->io[ret++] = as[ch->as].dacs[i]; 6129 } 6130 ch->io[ret] = -1; 6131 6132 ch->supp_stream_formats = fmtcap; 6133 ch->supp_pcm_size_rate = pcmcap; 6134 6135 /* 6136 * 8bit = 0 6137 * 16bit = 1 6138 * 20bit = 2 6139 * 24bit = 3 6140 * 32bit = 4 6141 */ 6142 if (ret > 0) { 6143 i = 0; 6144 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6145 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6146 ch->bit16 = 1; 6147 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6148 ch->bit16 = 0; 6149 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6150 ch->bit32 = 4; 6151 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6152 ch->bit32 = 3; 6153 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6154 ch->bit32 = 2; 6155 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6156 ch->fmtlist[i++] = AFMT_S16_LE; 6157 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6158 if (ch->bit32 > 0) { 6159 if (!(devinfo->function.audio.quirks & 6160 HDA_QUIRK_FORCESTEREO)) 6161 ch->fmtlist[i++] = AFMT_S32_LE; 6162 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6163 } 6164 } 6165 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6166 ch->fmtlist[i++] = AFMT_AC3; 6167 } 6168 ch->fmtlist[i] = 0; 6169 i = 0; 6170 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6171 ch->pcmrates[i++] = 8000; 6172 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6173 ch->pcmrates[i++] = 11025; 6174 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6175 ch->pcmrates[i++] = 16000; 6176 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6177 ch->pcmrates[i++] = 22050; 6178 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6179 ch->pcmrates[i++] = 32000; 6180 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6181 ch->pcmrates[i++] = 44100; 6182 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6183 ch->pcmrates[i++] = 48000; 6184 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6185 ch->pcmrates[i++] = 88200; 6186 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6187 ch->pcmrates[i++] = 96000; 6188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6189 ch->pcmrates[i++] = 176400; 6190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6191 ch->pcmrates[i++] = 192000; 6192 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6193 ch->pcmrates[i] = 0; 6194 if (i > 0) { 6195 ch->caps.minspeed = ch->pcmrates[0]; 6196 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6197 } 6198 } 6199 6200 return (ret); 6201} 6202 6203static void 6204hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6205{ 6206 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6207 struct hdac_audio_ctl *ctl; 6208 struct hdac_softc *sc = devinfo->codec->sc; 6209 char buf[64]; 6210 int i, j, printed; 6211 6212 if (flag == 0) { 6213 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6214 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6215 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6216 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6217 } 6218 6219 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6220 if ((flag & (1 << j)) == 0) 6221 continue; 6222 i = 0; 6223 printed = 0; 6224 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6225 if (ctl->enable == 0 || 6226 ctl->widget->enable == 0) 6227 continue; 6228 if (!((pdevinfo->play >= 0 && 6229 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6230 (pdevinfo->rec >= 0 && 6231 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6232 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6233 continue; 6234 if ((ctl->ossmask & (1 << j)) == 0) 6235 continue; 6236 6237 if (printed == 0) { 6238 device_printf(pdevinfo->dev, "\n"); 6239 if (banner != NULL) { 6240 device_printf(pdevinfo->dev, "%s", banner); 6241 } else { 6242 device_printf(pdevinfo->dev, "Unknown Ctl"); 6243 } 6244 printf(" (OSS: %s)\n", 6245 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6246 buf, sizeof(buf))); 6247 device_printf(pdevinfo->dev, " |\n"); 6248 printed = 1; 6249 } 6250 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6251 ctl->widget->nid, 6252 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6253 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6254 printf(" %2d): ", ctl->index); 6255 else 6256 printf("): "); 6257 if (ctl->step > 0) { 6258 printf("%+d/%+ddB (%d steps)%s\n", 6259 (0 - ctl->offset) * (ctl->size + 1) / 4, 6260 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6261 ctl->step + 1, 6262 ctl->mute?" + mute":""); 6263 } else 6264 printf("%s\n", ctl->mute?"mute":""); 6265 } 6266 } 6267} 6268 6269static void 6270hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6271{ 6272 uint32_t cap; 6273 6274 cap = fcap; 6275 if (cap != 0) { 6276 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6277 device_printf(dev, " "); 6278 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6279 printf(" AC3"); 6280 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6281 printf(" FLOAT32"); 6282 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6283 printf(" PCM"); 6284 printf("\n"); 6285 } 6286 cap = pcmcap; 6287 if (cap != 0) { 6288 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6289 device_printf(dev, " "); 6290 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6291 printf(" 8"); 6292 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6293 printf(" 16"); 6294 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6295 printf(" 20"); 6296 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6297 printf(" 24"); 6298 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6299 printf(" 32"); 6300 printf(" bits,"); 6301 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6302 printf(" 8"); 6303 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6304 printf(" 11"); 6305 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6306 printf(" 16"); 6307 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6308 printf(" 22"); 6309 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6310 printf(" 32"); 6311 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6312 printf(" 44"); 6313 printf(" 48"); 6314 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6315 printf(" 88"); 6316 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6317 printf(" 96"); 6318 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6319 printf(" 176"); 6320 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6321 printf(" 192"); 6322 printf(" KHz\n"); 6323 } 6324} 6325 6326static void 6327hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6328{ 6329 uint32_t pincap; 6330 6331 pincap = w->wclass.pin.cap; 6332 6333 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6334 device_printf(sc->dev, " "); 6335 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6336 printf(" ISC"); 6337 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6338 printf(" TRQD"); 6339 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6340 printf(" PDC"); 6341 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6342 printf(" HP"); 6343 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6344 printf(" OUT"); 6345 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6346 printf(" IN"); 6347 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6348 printf(" BAL"); 6349 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6350 printf(" VREF["); 6351 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6352 printf(" 50"); 6353 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6354 printf(" 80"); 6355 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6356 printf(" 100"); 6357 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6358 printf(" GROUND"); 6359 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6360 printf(" HIZ"); 6361 printf(" ]"); 6362 } 6363 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6364 printf(" EAPD"); 6365 printf("\n"); 6366 device_printf(sc->dev, " Pin config: 0x%08x\n", 6367 w->wclass.pin.config); 6368 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6369 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6370 printf(" HP"); 6371 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6372 printf(" IN"); 6373 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6374 printf(" OUT"); 6375 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6376 printf(" VREFs"); 6377 printf("\n"); 6378} 6379 6380static void 6381hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6382{ 6383 struct hdac_softc *sc = w->devinfo->codec->sc; 6384 6385 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6386 "jack %2d loc %2d color %7s misc %d%s\n", 6387 w->nid, conf, 6388 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6389 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6390 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6391 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6392 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6393 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6394 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6395 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6396 (w->enable == 0)?" [DISABLED]":""); 6397} 6398 6399static void 6400hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6401{ 6402 struct hdac_widget *w; 6403 int i; 6404 6405 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6406 w = hdac_widget_get(devinfo, i); 6407 if (w == NULL) 6408 continue; 6409 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6410 continue; 6411 hdac_dump_pin_config(w, w->wclass.pin.config); 6412 } 6413} 6414 6415static void 6416hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6417{ 6418 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6419 device_printf(sc->dev, " " 6420 "mute=%d step=%d size=%d offset=%d\n", 6421 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6422 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6423 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6424 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6425} 6426 6427static void 6428hdac_dump_nodes(struct hdac_devinfo *devinfo) 6429{ 6430 struct hdac_softc *sc = devinfo->codec->sc; 6431 static char *ossname[] = SOUND_DEVICE_NAMES; 6432 struct hdac_widget *w, *cw; 6433 char buf[64]; 6434 int i, j; 6435 6436 device_printf(sc->dev, "\n"); 6437 device_printf(sc->dev, "Default Parameter\n"); 6438 device_printf(sc->dev, "-----------------\n"); 6439 hdac_dump_audio_formats(sc->dev, 6440 devinfo->function.audio.supp_stream_formats, 6441 devinfo->function.audio.supp_pcm_size_rate); 6442 device_printf(sc->dev, " IN amp: 0x%08x\n", 6443 devinfo->function.audio.inamp_cap); 6444 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6445 devinfo->function.audio.outamp_cap); 6446 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6447 w = hdac_widget_get(devinfo, i); 6448 if (w == NULL) { 6449 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6450 continue; 6451 } 6452 device_printf(sc->dev, "\n"); 6453 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6454 (w->enable == 0) ? " [DISABLED]" : ""); 6455 device_printf(sc->dev, " Name: %s\n", w->name); 6456 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6457 w->param.widget_cap); 6458 if (w->param.widget_cap & 0x0ee1) { 6459 device_printf(sc->dev, " "); 6460 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6461 printf(" LRSWAP"); 6462 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6463 printf(" PWR"); 6464 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6465 printf(" DIGITAL"); 6466 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6467 printf(" UNSOL"); 6468 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6469 printf(" PROC"); 6470 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6471 printf(" STRIPE"); 6472 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6473 printf(" STEREO"); 6474 printf("\n"); 6475 } 6476 if (w->bindas != -1) { 6477 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6478 w->bindas, w->bindseqmask); 6479 } 6480 if (w->ossmask != 0 || w->ossdev >= 0) { 6481 device_printf(sc->dev, " OSS: %s", 6482 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6483 if (w->ossdev >= 0) 6484 printf(" (%s)", ossname[w->ossdev]); 6485 printf("\n"); 6486 } 6487 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6488 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6489 hdac_dump_audio_formats(sc->dev, 6490 w->param.supp_stream_formats, 6491 w->param.supp_pcm_size_rate); 6492 } else if (w->type == 6493 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6494 hdac_dump_pin(sc, w); 6495 if (w->param.eapdbtl != HDAC_INVALID) 6496 device_printf(sc->dev, " EAPD: 0x%08x\n", 6497 w->param.eapdbtl); 6498 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6499 w->param.outamp_cap != 0) 6500 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6501 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6502 w->param.inamp_cap != 0) 6503 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6504 if (w->nconns > 0) { 6505 device_printf(sc->dev, " connections: %d\n", w->nconns); 6506 device_printf(sc->dev, " |\n"); 6507 } 6508 for (j = 0; j < w->nconns; j++) { 6509 cw = hdac_widget_get(devinfo, w->conns[j]); 6510 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6511 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6512 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6513 if (cw == NULL) 6514 printf(" [UNKNOWN]"); 6515 else if (cw->enable == 0) 6516 printf(" [DISABLED]"); 6517 if (w->nconns > 1 && w->selconn == j && w->type != 6518 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6519 printf(" (selected)"); 6520 printf("\n"); 6521 } 6522 } 6523 6524} 6525 6526static void 6527hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6528{ 6529 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6530 struct hdac_widget *w, *cw; 6531 char buf[64]; 6532 int i, printed = 0; 6533 6534 if (depth > HDA_PARSE_MAXDEPTH) 6535 return; 6536 6537 w = hdac_widget_get(devinfo, nid); 6538 if (w == NULL || w->enable == 0) 6539 return; 6540 6541 if (depth == 0) 6542 device_printf(pdevinfo->dev, "%*s", 4, ""); 6543 else 6544 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6545 printf("nid=%d [%s]", w->nid, w->name); 6546 6547 if (depth > 0) { 6548 if (w->ossmask == 0) { 6549 printf("\n"); 6550 return; 6551 } 6552 printf(" [src: %s]", 6553 hdac_audio_ctl_ossmixer_mask2allname( 6554 w->ossmask, buf, sizeof(buf))); 6555 if (w->ossdev >= 0) { 6556 printf("\n"); 6557 return; 6558 } 6559 } 6560 printf("\n"); 6561 6562 for (i = 0; i < w->nconns; i++) { 6563 if (w->connsenable[i] == 0) 6564 continue; 6565 cw = hdac_widget_get(devinfo, w->conns[i]); 6566 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6567 continue; 6568 if (printed == 0) { 6569 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6570 printed = 1; 6571 } 6572 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6573 } 6574 6575} 6576 6577static void 6578hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6579{ 6580 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6581 struct hdac_softc *sc = devinfo->codec->sc; 6582 struct hdac_widget *w; 6583 int i, printed = 0; 6584 6585 if (pdevinfo->play < 0) 6586 return; 6587 6588 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6589 w = hdac_widget_get(devinfo, i); 6590 if (w == NULL || w->enable == 0) 6591 continue; 6592 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6593 continue; 6594 if (w->bindas != sc->chans[pdevinfo->play].as) 6595 continue; 6596 if (printed == 0) { 6597 printed = 1; 6598 device_printf(pdevinfo->dev, "\n"); 6599 device_printf(pdevinfo->dev, "Playback:\n"); 6600 } 6601 device_printf(pdevinfo->dev, "\n"); 6602 hdac_dump_dst_nid(pdevinfo, i, 0); 6603 } 6604} 6605 6606static void 6607hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6608{ 6609 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6610 struct hdac_softc *sc = devinfo->codec->sc; 6611 struct hdac_widget *w; 6612 int i; 6613 int printed = 0; 6614 6615 if (pdevinfo->rec < 0) 6616 return; 6617 6618 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6619 w = hdac_widget_get(devinfo, i); 6620 if (w == NULL || w->enable == 0) 6621 continue; 6622 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6623 continue; 6624 if (w->bindas != sc->chans[pdevinfo->rec].as) 6625 continue; 6626 if (printed == 0) { 6627 printed = 1; 6628 device_printf(pdevinfo->dev, "\n"); 6629 device_printf(pdevinfo->dev, "Record:\n"); 6630 } 6631 device_printf(pdevinfo->dev, "\n"); 6632 hdac_dump_dst_nid(pdevinfo, i, 0); 6633 } 6634} 6635 6636static void 6637hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6638{ 6639 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6640 struct hdac_widget *w; 6641 int i; 6642 int printed = 0; 6643 6644 if (pdevinfo->index != 0) 6645 return; 6646 6647 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6648 w = hdac_widget_get(devinfo, i); 6649 if (w == NULL || w->enable == 0) 6650 continue; 6651 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6652 continue; 6653 if (printed == 0) { 6654 printed = 1; 6655 device_printf(pdevinfo->dev, "\n"); 6656 device_printf(pdevinfo->dev, "Input Mix:\n"); 6657 } 6658 device_printf(pdevinfo->dev, "\n"); 6659 hdac_dump_dst_nid(pdevinfo, i, 0); 6660 } 6661} 6662 6663static void 6664hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6665{ 6666 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6667 nid_t *nids; 6668 int i; 6669 6670 if (pdevinfo->play >= 0) { 6671 i = pdevinfo->play; 6672 device_printf(pdevinfo->dev, "\n"); 6673 device_printf(pdevinfo->dev, "Playback:\n"); 6674 device_printf(pdevinfo->dev, "\n"); 6675 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6676 sc->chans[i].supp_pcm_size_rate); 6677 device_printf(pdevinfo->dev, " DAC:"); 6678 for (nids = sc->chans[i].io; *nids != -1; nids++) 6679 printf(" %d", *nids); 6680 printf("\n"); 6681 } 6682 if (pdevinfo->rec >= 0) { 6683 i = pdevinfo->rec; 6684 device_printf(pdevinfo->dev, "\n"); 6685 device_printf(pdevinfo->dev, "Record:\n"); 6686 device_printf(pdevinfo->dev, "\n"); 6687 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6688 sc->chans[i].supp_pcm_size_rate); 6689 device_printf(pdevinfo->dev, " ADC:"); 6690 for (nids = sc->chans[i].io; *nids != -1; nids++) 6691 printf(" %d", *nids); 6692 printf("\n"); 6693 } 6694} 6695 6696static void 6697hdac_release_resources(struct hdac_softc *sc) 6698{ 6699 int i, j; 6700 6701 if (sc == NULL) 6702 return; 6703 6704 hdac_lock(sc); 6705 sc->polling = 0; 6706 sc->poll_ival = 0; 6707 callout_stop(&sc->poll_hda); 6708 callout_stop(&sc->poll_hdac); 6709 callout_stop(&sc->poll_jack); 6710 hdac_reset(sc, 0); 6711 hdac_unlock(sc); 6712 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6713 callout_drain(&sc->poll_hda); 6714 callout_drain(&sc->poll_hdac); 6715 callout_drain(&sc->poll_jack); 6716 6717 hdac_irq_free(sc); 6718 6719 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6720 if (sc->codecs[i] == NULL) 6721 continue; 6722 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6723 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6724 if (sc->codecs[i]->fgs[j].node_type == 6725 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6726 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6727 M_HDAC); 6728 free(sc->codecs[i]->fgs[j].function.audio.as, 6729 M_HDAC); 6730 free(sc->codecs[i]->fgs[j].function.audio.devs, 6731 M_HDAC); 6732 } 6733 } 6734 free(sc->codecs[i]->fgs, M_HDAC); 6735 free(sc->codecs[i], M_HDAC); 6736 sc->codecs[i] = NULL; 6737 } 6738 6739 hdac_dma_free(sc, &sc->pos_dma); 6740 hdac_dma_free(sc, &sc->rirb_dma); 6741 hdac_dma_free(sc, &sc->corb_dma); 6742 for (i = 0; i < sc->num_chans; i++) { 6743 if (sc->chans[i].blkcnt > 0) 6744 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6745 } 6746 free(sc->chans, M_HDAC); 6747 if (sc->chan_dmat != NULL) { 6748 bus_dma_tag_destroy(sc->chan_dmat); 6749 sc->chan_dmat = NULL; 6750 } 6751 hdac_mem_free(sc); 6752 snd_mtxfree(sc->lock); 6753} 6754 6755/* This function surely going to make its way into upper level someday. */ 6756static void 6757hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6758{ 6759 const char *res = NULL; 6760 int i = 0, j, k, len, inv; 6761 6762 if (on != NULL) 6763 *on = 0; 6764 if (off != NULL) 6765 *off = 0; 6766 if (sc == NULL) 6767 return; 6768 if (resource_string_value(device_get_name(sc->dev), 6769 device_get_unit(sc->dev), "config", &res) != 0) 6770 return; 6771 if (!(res != NULL && strlen(res) > 0)) 6772 return; 6773 HDA_BOOTVERBOSE( 6774 device_printf(sc->dev, "HDA Config:"); 6775 ); 6776 for (;;) { 6777 while (res[i] != '\0' && 6778 (res[i] == ',' || isspace(res[i]) != 0)) 6779 i++; 6780 if (res[i] == '\0') { 6781 HDA_BOOTVERBOSE( 6782 printf("\n"); 6783 ); 6784 return; 6785 } 6786 j = i; 6787 while (res[j] != '\0' && 6788 !(res[j] == ',' || isspace(res[j]) != 0)) 6789 j++; 6790 len = j - i; 6791 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6792 inv = 2; 6793 else 6794 inv = 0; 6795 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6796 if (strncmp(res + i + inv, 6797 hdac_quirks_tab[k].key, len - inv) != 0) 6798 continue; 6799 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6800 break; 6801 HDA_BOOTVERBOSE( 6802 printf(" %s%s", (inv != 0) ? "no" : "", 6803 hdac_quirks_tab[k].key); 6804 ); 6805 if (inv == 0 && on != NULL) 6806 *on |= hdac_quirks_tab[k].value; 6807 else if (inv != 0 && off != NULL) 6808 *off |= hdac_quirks_tab[k].value; 6809 break; 6810 } 6811 i = j; 6812 } 6813} 6814 6815#ifdef SND_DYNSYSCTL 6816static int 6817sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6818{ 6819 struct hdac_softc *sc; 6820 device_t dev; 6821 uint32_t ctl; 6822 int err, val; 6823 6824 dev = oidp->oid_arg1; 6825 sc = device_get_softc(dev); 6826 if (sc == NULL) 6827 return (EINVAL); 6828 hdac_lock(sc); 6829 val = sc->polling; 6830 hdac_unlock(sc); 6831 err = sysctl_handle_int(oidp, &val, 0, req); 6832 6833 if (err != 0 || req->newptr == NULL) 6834 return (err); 6835 if (val < 0 || val > 1) 6836 return (EINVAL); 6837 6838 hdac_lock(sc); 6839 if (val != sc->polling) { 6840 if (val == 0) { 6841 callout_stop(&sc->poll_hda); 6842 callout_stop(&sc->poll_hdac); 6843 hdac_unlock(sc); 6844 callout_drain(&sc->poll_hda); 6845 callout_drain(&sc->poll_hdac); 6846 hdac_lock(sc); 6847 sc->polling = 0; 6848 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6849 ctl |= HDAC_INTCTL_GIE; 6850 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6851 } else { 6852 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6853 ctl &= ~HDAC_INTCTL_GIE; 6854 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6855 hdac_unlock(sc); 6856 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6857 hdac_lock(sc); 6858 sc->polling = 1; 6859 hdac_poll_reinit(sc); 6860 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6861 } 6862 } 6863 hdac_unlock(sc); 6864 6865 return (err); 6866} 6867 6868static int 6869sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6870{ 6871 struct hdac_softc *sc; 6872 device_t dev; 6873 int err, val; 6874 6875 dev = oidp->oid_arg1; 6876 sc = device_get_softc(dev); 6877 if (sc == NULL) 6878 return (EINVAL); 6879 hdac_lock(sc); 6880 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6881 hdac_unlock(sc); 6882 err = sysctl_handle_int(oidp, &val, 0, req); 6883 6884 if (err != 0 || req->newptr == NULL) 6885 return (err); 6886 6887 if (val < 1) 6888 val = 1; 6889 if (val > 5000) 6890 val = 5000; 6891 val = ((uint64_t)val * hz) / 1000; 6892 if (val < 1) 6893 val = 1; 6894 if (val > (hz * 5)) 6895 val = hz * 5; 6896 6897 hdac_lock(sc); 6898 sc->poll_ival = val; 6899 hdac_unlock(sc); 6900 6901 return (err); 6902} 6903 6904static int 6905sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6906{ 6907 struct hdac_softc *sc; 6908 struct hdac_codec *codec; 6909 struct hdac_devinfo *devinfo; 6910 struct hdac_widget *w; 6911 device_t dev; 6912 uint32_t res, pincap, delay; 6913 int codec_index, fg_index; 6914 int i, err, val; 6915 nid_t cad; 6916 6917 dev = oidp->oid_arg1; 6918 sc = device_get_softc(dev); 6919 if (sc == NULL) 6920 return (EINVAL); 6921 val = 0; 6922 err = sysctl_handle_int(oidp, &val, 0, req); 6923 if (err != 0 || req->newptr == NULL || val == 0) 6924 return (err); 6925 6926 /* XXX: Temporary. For debugging. */ 6927 if (val == 100) { 6928 hdac_suspend(dev); 6929 return (0); 6930 } else if (val == 101) { 6931 hdac_resume(dev); 6932 return (0); 6933 } 6934 6935 hdac_lock(sc); 6936 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 6937 codec = sc->codecs[codec_index]; 6938 if (codec == NULL) 6939 continue; 6940 cad = codec->cad; 6941 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 6942 devinfo = &codec->fgs[fg_index]; 6943 if (devinfo->node_type != 6944 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 6945 continue; 6946 6947 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 6948 codec_index, devinfo->nid); 6949 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6950 w = hdac_widget_get(devinfo, i); 6951 if (w == NULL || w->type != 6952 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6953 continue; 6954 hdac_dump_pin_config(w, w->wclass.pin.config); 6955 pincap = w->wclass.pin.cap; 6956 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 6957 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 6958 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 6959 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 6960 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 6961 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 6962 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6963 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 6964 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6965 delay = 0; 6966 hdac_command(sc, 6967 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6968 do { 6969 res = hdac_command(sc, 6970 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6971 if (res != 0x7fffffff && res != 0xffffffff) 6972 break; 6973 DELAY(10); 6974 } while (++delay < 10000); 6975 } else { 6976 delay = 0; 6977 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6978 w->nid), cad); 6979 } 6980 printf(" Sense: 0x%08x", res); 6981 if (delay > 0) 6982 printf(" delay %dus", delay * 10); 6983 } 6984 printf("\n"); 6985 } 6986 device_printf(dev, 6987 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6988 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6989 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6990 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6991 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6992 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6993 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6994 device_printf(dev, " GPI:"); 6995 res = hdac_command(sc, 6996 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6997 printf(" data=0x%08x", res); 6998 res = hdac_command(sc, 6999 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7000 cad); 7001 printf(" wake=0x%08x", res); 7002 res = hdac_command(sc, 7003 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7004 cad); 7005 printf(" unsol=0x%08x", res); 7006 res = hdac_command(sc, 7007 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7008 printf(" sticky=0x%08x\n", res); 7009 } 7010 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7011 device_printf(dev, " GPO:"); 7012 res = hdac_command(sc, 7013 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7014 printf(" data=0x%08x\n", res); 7015 } 7016 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7017 device_printf(dev, "GPIO:"); 7018 res = hdac_command(sc, 7019 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7020 printf(" data=0x%08x", res); 7021 res = hdac_command(sc, 7022 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7023 printf(" enable=0x%08x", res); 7024 res = hdac_command(sc, 7025 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7026 printf(" direction=0x%08x\n", res); 7027 res = hdac_command(sc, 7028 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7029 device_printf(dev, " wake=0x%08x", res); 7030 res = hdac_command(sc, 7031 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7032 cad); 7033 printf(" unsol=0x%08x", res); 7034 res = hdac_command(sc, 7035 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7036 printf(" sticky=0x%08x\n", res); 7037 } 7038 } 7039 } 7040 hdac_unlock(sc); 7041 return (0); 7042} 7043#endif 7044 7045static void 7046hdac_attach2(void *arg) 7047{ 7048 struct hdac_codec *codec; 7049 struct hdac_softc *sc; 7050 struct hdac_audio_ctl *ctl; 7051 uint32_t quirks_on, quirks_off; 7052 int codec_index, fg_index; 7053 int i, pdev, rdev, dmaalloc = 0; 7054 struct hdac_devinfo *devinfo; 7055 7056 sc = (struct hdac_softc *)arg; 7057 7058 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7059 7060 HDA_BOOTHVERBOSE( 7061 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7062 quirks_on, quirks_off); 7063 ); 7064 7065 hdac_lock(sc); 7066 7067 /* Remove ourselves from the config hooks */ 7068 if (sc->intrhook.ich_func != NULL) { 7069 config_intrhook_disestablish(&sc->intrhook); 7070 sc->intrhook.ich_func = NULL; 7071 } 7072 7073 /* Start the corb and rirb engines */ 7074 HDA_BOOTHVERBOSE( 7075 device_printf(sc->dev, "Starting CORB Engine...\n"); 7076 ); 7077 hdac_corb_start(sc); 7078 HDA_BOOTHVERBOSE( 7079 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7080 ); 7081 hdac_rirb_start(sc); 7082 7083 HDA_BOOTHVERBOSE( 7084 device_printf(sc->dev, 7085 "Enabling controller interrupt...\n"); 7086 ); 7087 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7088 HDAC_GCTL_UNSOL); 7089 if (sc->polling == 0) { 7090 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7091 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7092 } else { 7093 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7094 } 7095 DELAY(1000); 7096 7097 HDA_BOOTHVERBOSE( 7098 device_printf(sc->dev, 7099 "Scanning HDA codecs ...\n"); 7100 ); 7101 hdac_scan_codecs(sc); 7102 7103 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7104 codec = sc->codecs[codec_index]; 7105 if (codec == NULL) 7106 continue; 7107 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7108 devinfo = &codec->fgs[fg_index]; 7109 HDA_BOOTVERBOSE( 7110 device_printf(sc->dev, "\n"); 7111 device_printf(sc->dev, 7112 "Processing %s FG cad=%d nid=%d...\n", 7113 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7114 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7115 "unknown", 7116 devinfo->codec->cad, devinfo->nid); 7117 ); 7118 if (devinfo->node_type != 7119 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7120 HDA_BOOTHVERBOSE( 7121 device_printf(sc->dev, 7122 "Powering down...\n"); 7123 ); 7124 hdac_command(sc, 7125 HDA_CMD_SET_POWER_STATE(codec->cad, 7126 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7127 codec->cad); 7128 continue; 7129 } 7130 7131 HDA_BOOTHVERBOSE( 7132 device_printf(sc->dev, "Powering up...\n"); 7133 ); 7134 hdac_powerup(devinfo); 7135 HDA_BOOTHVERBOSE( 7136 device_printf(sc->dev, "Parsing audio FG...\n"); 7137 ); 7138 hdac_audio_parse(devinfo); 7139 HDA_BOOTHVERBOSE( 7140 device_printf(sc->dev, "Parsing Ctls...\n"); 7141 ); 7142 hdac_audio_ctl_parse(devinfo); 7143 HDA_BOOTHVERBOSE( 7144 device_printf(sc->dev, "Parsing vendor patch...\n"); 7145 ); 7146 hdac_vendor_patch_parse(devinfo); 7147 devinfo->function.audio.quirks |= quirks_on; 7148 devinfo->function.audio.quirks &= ~quirks_off; 7149 7150 HDA_BOOTHVERBOSE( 7151 device_printf(sc->dev, "Disabling nonaudio...\n"); 7152 ); 7153 hdac_audio_disable_nonaudio(devinfo); 7154 HDA_BOOTHVERBOSE( 7155 device_printf(sc->dev, "Disabling useless...\n"); 7156 ); 7157 hdac_audio_disable_useless(devinfo); 7158 HDA_BOOTVERBOSE( 7159 device_printf(sc->dev, "Patched pins configuration:\n"); 7160 hdac_dump_pin_configs(devinfo); 7161 ); 7162 HDA_BOOTHVERBOSE( 7163 device_printf(sc->dev, "Parsing pin associations...\n"); 7164 ); 7165 hdac_audio_as_parse(devinfo); 7166 HDA_BOOTHVERBOSE( 7167 device_printf(sc->dev, "Building AFG tree...\n"); 7168 ); 7169 hdac_audio_build_tree(devinfo); 7170 HDA_BOOTHVERBOSE( 7171 device_printf(sc->dev, "Disabling unassociated " 7172 "widgets...\n"); 7173 ); 7174 hdac_audio_disable_unas(devinfo); 7175 HDA_BOOTHVERBOSE( 7176 device_printf(sc->dev, "Disabling nonselected " 7177 "inputs...\n"); 7178 ); 7179 hdac_audio_disable_notselected(devinfo); 7180 HDA_BOOTHVERBOSE( 7181 device_printf(sc->dev, "Disabling useless...\n"); 7182 ); 7183 hdac_audio_disable_useless(devinfo); 7184 HDA_BOOTHVERBOSE( 7185 device_printf(sc->dev, "Disabling " 7186 "crossassociatement connections...\n"); 7187 ); 7188 hdac_audio_disable_crossas(devinfo); 7189 HDA_BOOTHVERBOSE( 7190 device_printf(sc->dev, "Disabling useless...\n"); 7191 ); 7192 hdac_audio_disable_useless(devinfo); 7193 HDA_BOOTHVERBOSE( 7194 device_printf(sc->dev, "Binding associations to channels...\n"); 7195 ); 7196 hdac_audio_bind_as(devinfo); 7197 HDA_BOOTHVERBOSE( 7198 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7199 ); 7200 hdac_audio_assign_names(devinfo); 7201 HDA_BOOTHVERBOSE( 7202 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7203 ); 7204 hdac_audio_assign_mixers(devinfo); 7205 HDA_BOOTHVERBOSE( 7206 device_printf(sc->dev, "Preparing pin controls...\n"); 7207 ); 7208 hdac_audio_prepare_pin_ctrl(devinfo); 7209 HDA_BOOTHVERBOSE( 7210 device_printf(sc->dev, "AFG commit...\n"); 7211 ); 7212 hdac_audio_commit(devinfo); 7213 HDA_BOOTHVERBOSE( 7214 device_printf(sc->dev, "Ctls commit...\n"); 7215 ); 7216 hdac_audio_ctl_commit(devinfo); 7217 HDA_BOOTHVERBOSE( 7218 device_printf(sc->dev, "HP switch init...\n"); 7219 ); 7220 hdac_hp_switch_init(devinfo); 7221 7222 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7223 dmaalloc == 0) { 7224 if (hdac_dma_alloc(sc, &sc->pos_dma, 7225 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7226 HDA_BOOTVERBOSE( 7227 device_printf(sc->dev, "Failed to " 7228 "allocate DMA pos buffer " 7229 "(non-fatal)\n"); 7230 ); 7231 } else 7232 dmaalloc = 1; 7233 } 7234 7235 i = devinfo->function.audio.playcnt; 7236 if (devinfo->function.audio.reccnt > i) 7237 i = devinfo->function.audio.reccnt; 7238 devinfo->function.audio.devs = 7239 (struct hdac_pcm_devinfo *)malloc( 7240 sizeof(struct hdac_pcm_devinfo) * i, 7241 M_HDAC, M_ZERO | M_NOWAIT); 7242 if (devinfo->function.audio.devs == NULL) { 7243 device_printf(sc->dev, 7244 "Unable to allocate memory for devices\n"); 7245 continue; 7246 } 7247 devinfo->function.audio.num_devs = i; 7248 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7249 devinfo->function.audio.devs[i].index = i; 7250 devinfo->function.audio.devs[i].devinfo = devinfo; 7251 devinfo->function.audio.devs[i].play = -1; 7252 devinfo->function.audio.devs[i].rec = -1; 7253 } 7254 pdev = 0; 7255 rdev = 0; 7256 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 7257 if (devinfo->function.audio.as[i].enable == 0) 7258 continue; 7259 if (devinfo->function.audio.as[i].dir == 7260 HDA_CTL_IN) { 7261 devinfo->function.audio.devs[rdev].rec 7262 = devinfo->function.audio.as[i].chan; 7263 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7264 &devinfo->function.audio.devs[rdev]; 7265 rdev++; 7266 } else { 7267 devinfo->function.audio.devs[pdev].play 7268 = devinfo->function.audio.as[i].chan; 7269 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7270 &devinfo->function.audio.devs[pdev]; 7271 pdev++; 7272 } 7273 } 7274 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7275 struct hdac_pcm_devinfo *pdevinfo = 7276 &devinfo->function.audio.devs[i]; 7277 pdevinfo->dev = 7278 device_add_child(sc->dev, "pcm", -1); 7279 device_set_ivars(pdevinfo->dev, 7280 (void *)pdevinfo); 7281 } 7282 7283 HDA_BOOTVERBOSE( 7284 if (devinfo->function.audio.quirks != 0) { 7285 device_printf(sc->dev, "FG config/quirks:"); 7286 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7287 if ((devinfo->function.audio.quirks & 7288 hdac_quirks_tab[i].value) == 7289 hdac_quirks_tab[i].value) 7290 printf(" %s", hdac_quirks_tab[i].key); 7291 } 7292 printf("\n"); 7293 } 7294 7295 device_printf(sc->dev, "\n"); 7296 device_printf(sc->dev, "+-------------------+\n"); 7297 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7298 device_printf(sc->dev, "+-------------------+\n"); 7299 hdac_dump_nodes(devinfo); 7300 ); 7301 7302 HDA_BOOTHVERBOSE( 7303 device_printf(sc->dev, "\n"); 7304 device_printf(sc->dev, "+------------------------+\n"); 7305 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7306 device_printf(sc->dev, "+------------------------+\n"); 7307 device_printf(sc->dev, "\n"); 7308 i = 0; 7309 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7310 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7311 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7312 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7313 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7314 ctl->index); 7315 if (ctl->childwidget != NULL) 7316 printf(" cnid %3d", ctl->childwidget->nid); 7317 else 7318 printf(" "); 7319 printf(" ossmask=0x%08x\n", 7320 ctl->ossmask); 7321 device_printf(sc->dev, 7322 " mute: %d step: %3d size: %3d off: %3d%s\n", 7323 ctl->mute, ctl->step, ctl->size, ctl->offset, 7324 (ctl->enable == 0) ? " [DISABLED]" : 7325 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7326 } 7327 ); 7328 } 7329 } 7330 hdac_unlock(sc); 7331 7332 HDA_BOOTVERBOSE( 7333 device_printf(sc->dev, "\n"); 7334 ); 7335 7336 bus_generic_attach(sc->dev); 7337 7338#ifdef SND_DYNSYSCTL 7339 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7340 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7341 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7342 sysctl_hdac_polling, "I", "Enable polling mode"); 7343 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7344 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7345 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7346 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7347 "Controller/Jack Sense polling interval (1-1000 ms)"); 7348 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7349 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7350 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7351 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7352#endif 7353} 7354 7355/**************************************************************************** 7356 * int hdac_suspend(device_t) 7357 * 7358 * Suspend and power down HDA bus and codecs. 7359 ****************************************************************************/ 7360static int 7361hdac_suspend(device_t dev) 7362{ 7363 struct hdac_softc *sc; 7364 struct hdac_codec *codec; 7365 struct hdac_devinfo *devinfo; 7366 int codec_index, fg_index, i; 7367 7368 HDA_BOOTHVERBOSE( 7369 device_printf(dev, "Suspend...\n"); 7370 ); 7371 7372 sc = device_get_softc(dev); 7373 hdac_lock(sc); 7374 7375 HDA_BOOTHVERBOSE( 7376 device_printf(dev, "Stop streams...\n"); 7377 ); 7378 for (i = 0; i < sc->num_chans; i++) { 7379 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7380 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7381 hdac_channel_stop(sc, &sc->chans[i]); 7382 } 7383 } 7384 7385 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7386 codec = sc->codecs[codec_index]; 7387 if (codec == NULL) 7388 continue; 7389 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7390 devinfo = &codec->fgs[fg_index]; 7391 HDA_BOOTHVERBOSE( 7392 device_printf(dev, 7393 "Power down FG" 7394 " cad=%d nid=%d to the D3 state...\n", 7395 codec->cad, devinfo->nid); 7396 ); 7397 hdac_command(sc, 7398 HDA_CMD_SET_POWER_STATE(codec->cad, 7399 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7400 codec->cad); 7401 } 7402 } 7403 7404 HDA_BOOTHVERBOSE( 7405 device_printf(dev, "Reset controller...\n"); 7406 ); 7407 callout_stop(&sc->poll_hda); 7408 callout_stop(&sc->poll_hdac); 7409 callout_stop(&sc->poll_jack); 7410 hdac_reset(sc, 0); 7411 hdac_unlock(sc); 7412 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7413 callout_drain(&sc->poll_hda); 7414 callout_drain(&sc->poll_hdac); 7415 callout_drain(&sc->poll_jack); 7416 7417 HDA_BOOTHVERBOSE( 7418 device_printf(dev, "Suspend done\n"); 7419 ); 7420 7421 return (0); 7422} 7423 7424/**************************************************************************** 7425 * int hdac_resume(device_t) 7426 * 7427 * Powerup and restore HDA bus and codecs state. 7428 ****************************************************************************/ 7429static int 7430hdac_resume(device_t dev) 7431{ 7432 struct hdac_softc *sc; 7433 struct hdac_codec *codec; 7434 struct hdac_devinfo *devinfo; 7435 int codec_index, fg_index, i; 7436 7437 HDA_BOOTHVERBOSE( 7438 device_printf(dev, "Resume...\n"); 7439 ); 7440 7441 sc = device_get_softc(dev); 7442 hdac_lock(sc); 7443 7444 /* Quiesce everything */ 7445 HDA_BOOTHVERBOSE( 7446 device_printf(dev, "Reset controller...\n"); 7447 ); 7448 hdac_reset(sc, 1); 7449 7450 /* Initialize the CORB and RIRB */ 7451 hdac_corb_init(sc); 7452 hdac_rirb_init(sc); 7453 7454 /* Start the corb and rirb engines */ 7455 HDA_BOOTHVERBOSE( 7456 device_printf(dev, "Starting CORB Engine...\n"); 7457 ); 7458 hdac_corb_start(sc); 7459 HDA_BOOTHVERBOSE( 7460 device_printf(dev, "Starting RIRB Engine...\n"); 7461 ); 7462 hdac_rirb_start(sc); 7463 7464 HDA_BOOTHVERBOSE( 7465 device_printf(dev, 7466 "Enabling controller interrupt...\n"); 7467 ); 7468 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7469 HDAC_GCTL_UNSOL); 7470 if (sc->polling == 0) { 7471 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7472 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7473 } else { 7474 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7475 } 7476 DELAY(1000); 7477 7478 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7479 codec = sc->codecs[codec_index]; 7480 if (codec == NULL) 7481 continue; 7482 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7483 devinfo = &codec->fgs[fg_index]; 7484 if (devinfo->node_type != 7485 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7486 HDA_BOOTHVERBOSE( 7487 device_printf(dev, 7488 "Power down unsupported non-audio FG" 7489 " cad=%d nid=%d to the D3 state...\n", 7490 codec->cad, devinfo->nid); 7491 ); 7492 hdac_command(sc, 7493 HDA_CMD_SET_POWER_STATE(codec->cad, 7494 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7495 codec->cad); 7496 continue; 7497 } 7498 7499 HDA_BOOTHVERBOSE( 7500 device_printf(dev, 7501 "Power up audio FG cad=%d nid=%d...\n", 7502 devinfo->codec->cad, devinfo->nid); 7503 ); 7504 hdac_powerup(devinfo); 7505 HDA_BOOTHVERBOSE( 7506 device_printf(dev, "AFG commit...\n"); 7507 ); 7508 hdac_audio_commit(devinfo); 7509 HDA_BOOTHVERBOSE( 7510 device_printf(dev, "Ctls commit...\n"); 7511 ); 7512 hdac_audio_ctl_commit(devinfo); 7513 HDA_BOOTHVERBOSE( 7514 device_printf(dev, "HP switch init...\n"); 7515 ); 7516 hdac_hp_switch_init(devinfo); 7517 7518 hdac_unlock(sc); 7519 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7520 struct hdac_pcm_devinfo *pdevinfo = 7521 &devinfo->function.audio.devs[i]; 7522 HDA_BOOTHVERBOSE( 7523 device_printf(pdevinfo->dev, 7524 "OSS mixer reinitialization...\n"); 7525 ); 7526 if (mixer_reinit(pdevinfo->dev) == -1) 7527 device_printf(pdevinfo->dev, 7528 "unable to reinitialize the mixer\n"); 7529 } 7530 hdac_lock(sc); 7531 } 7532 } 7533 7534 HDA_BOOTHVERBOSE( 7535 device_printf(dev, "Start streams...\n"); 7536 ); 7537 for (i = 0; i < sc->num_chans; i++) { 7538 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7539 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7540 hdac_channel_start(sc, &sc->chans[i]); 7541 } 7542 } 7543 7544 hdac_unlock(sc); 7545 7546 HDA_BOOTHVERBOSE( 7547 device_printf(dev, "Resume done\n"); 7548 ); 7549 7550 return (0); 7551} 7552/**************************************************************************** 7553 * int hdac_detach(device_t) 7554 * 7555 * Detach and free up resources utilized by the hdac device. 7556 ****************************************************************************/ 7557static int 7558hdac_detach(device_t dev) 7559{ 7560 struct hdac_softc *sc; 7561 device_t *devlist = NULL; 7562 int i, devcount; 7563 7564 sc = device_get_softc(dev); 7565 7566 device_get_children(dev, &devlist, &devcount); 7567 for (i = 0; devlist != NULL && i < devcount; i++) 7568 device_delete_child(dev, devlist[i]); 7569 if (devlist != NULL) 7570 free(devlist, M_TEMP); 7571 7572 hdac_release_resources(sc); 7573 7574 return (0); 7575} 7576 7577static int 7578hdac_print_child(device_t dev, device_t child) 7579{ 7580 struct hdac_pcm_devinfo *pdevinfo = 7581 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7582 int retval; 7583 7584 retval = bus_print_child_header(dev, child); 7585 retval += printf(" at cad %d nid %d", 7586 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7587 retval += bus_print_child_footer(dev, child); 7588 7589 return (retval); 7590} 7591 7592static device_method_t hdac_methods[] = { 7593 /* device interface */ 7594 DEVMETHOD(device_probe, hdac_probe), 7595 DEVMETHOD(device_attach, hdac_attach), 7596 DEVMETHOD(device_detach, hdac_detach), 7597 DEVMETHOD(device_suspend, hdac_suspend), 7598 DEVMETHOD(device_resume, hdac_resume), 7599 /* Bus interface */ 7600 DEVMETHOD(bus_print_child, hdac_print_child), 7601 { 0, 0 } 7602}; 7603 7604static driver_t hdac_driver = { 7605 "hdac", 7606 hdac_methods, 7607 sizeof(struct hdac_softc), 7608}; 7609 7610static devclass_t hdac_devclass; 7611 7612DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7613MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7614MODULE_VERSION(snd_hda, 1); 7615 7616static int 7617hdac_pcm_probe(device_t dev) 7618{ 7619 struct hdac_pcm_devinfo *pdevinfo = 7620 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7621 char buf[128]; 7622 7623 snprintf(buf, sizeof(buf), "HDA %s PCM #%d", 7624 hdac_codec_name(pdevinfo->devinfo->codec), 7625 pdevinfo->index); 7626 device_set_desc_copy(dev, buf); 7627 return (0); 7628} 7629 7630static int 7631hdac_pcm_attach(device_t dev) 7632{ 7633 struct hdac_pcm_devinfo *pdevinfo = 7634 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7635 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7636 char status[SND_STATUSLEN]; 7637 int i; 7638 7639 pdevinfo->chan_size = pcm_getbuffersize(dev, 7640 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7641 7642 HDA_BOOTVERBOSE( 7643 device_printf(dev, "+--------------------------------------+\n"); 7644 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7645 device_printf(dev, "+--------------------------------------+\n"); 7646 hdac_dump_pcmchannels(pdevinfo); 7647 device_printf(dev, "\n"); 7648 device_printf(dev, "+--------------------------------+\n"); 7649 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7650 device_printf(dev, "+--------------------------------+\n"); 7651 hdac_dump_dac(pdevinfo); 7652 hdac_dump_adc(pdevinfo); 7653 hdac_dump_mix(pdevinfo); 7654 device_printf(dev, "\n"); 7655 device_printf(dev, "+-------------------------+\n"); 7656 device_printf(dev, "| DUMPING Volume Controls |\n"); 7657 device_printf(dev, "+-------------------------+\n"); 7658 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7659 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7660 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7661 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7662 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7663 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7664 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7665 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7666 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7667 hdac_dump_ctls(pdevinfo, NULL, 0); 7668 device_printf(dev, "\n"); 7669 ); 7670 7671 if (resource_int_value(device_get_name(dev), 7672 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7673 i &= HDA_BLK_ALIGN; 7674 if (i < HDA_BLK_MIN) 7675 i = HDA_BLK_MIN; 7676 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7677 i = 0; 7678 while (pdevinfo->chan_blkcnt >> i) 7679 i++; 7680 pdevinfo->chan_blkcnt = 1 << (i - 1); 7681 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7682 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7683 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7684 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7685 } else 7686 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7687 7688 /* 7689 * We don't register interrupt handler with snd_setup_intr 7690 * in pcm device. Mark pcm device as MPSAFE manually. 7691 */ 7692 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7693 7694 HDA_BOOTHVERBOSE( 7695 device_printf(dev, "OSS mixer initialization...\n"); 7696 ); 7697 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7698 device_printf(dev, "Can't register mixer\n"); 7699 7700 HDA_BOOTHVERBOSE( 7701 device_printf(dev, "Registering PCM channels...\n"); 7702 ); 7703 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7704 (pdevinfo->rec >= 0)?1:0) != 0) 7705 device_printf(dev, "Can't register PCM\n"); 7706 7707 pdevinfo->registered++; 7708 7709 if (pdevinfo->play >= 0) 7710 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7711 if (pdevinfo->rec >= 0) 7712 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7713 7714 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7715 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7716 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7717 pcm_setstatus(dev, status); 7718 7719 return (0); 7720} 7721 7722static int 7723hdac_pcm_detach(device_t dev) 7724{ 7725 struct hdac_pcm_devinfo *pdevinfo = 7726 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7727 int err; 7728 7729 if (pdevinfo->registered > 0) { 7730 err = pcm_unregister(dev); 7731 if (err != 0) 7732 return (err); 7733 } 7734 7735 return (0); 7736} 7737 7738static device_method_t hdac_pcm_methods[] = { 7739 /* device interface */ 7740 DEVMETHOD(device_probe, hdac_pcm_probe), 7741 DEVMETHOD(device_attach, hdac_pcm_attach), 7742 DEVMETHOD(device_detach, hdac_pcm_detach), 7743 { 0, 0 } 7744}; 7745 7746static driver_t hdac_pcm_driver = { 7747 "pcm", 7748 hdac_pcm_methods, 7749 PCM_SOFTC_SIZE, 7750}; 7751 7752DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7753 7754