hdac.c revision 183097
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20080916_0112" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 183097 2008-09-16 20:03:34Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 152 153/* Nvidia */ 154#define NVIDIA_VENDORID 0x10de 155#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 156#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 157#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 158#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 159#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 160#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 161#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 162#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 163#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 164 165/* ATI */ 166#define ATI_VENDORID 0x1002 167#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 168#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 169#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 170 171/* VIA */ 172#define VIA_VENDORID 0x1106 173#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 174#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 175 176/* SiS */ 177#define SIS_VENDORID 0x1039 178#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 179#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 180 181/* OEM/subvendors */ 182 183/* Intel */ 184#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 185 186/* HP/Compaq */ 187#define HP_VENDORID 0x103c 188#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 189#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 190#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 191#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 192#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 193#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 194#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 195#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 196#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 197#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 198/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 199#define HP_NX6325_SUBVENDORX 0x103c30b0 200 201/* Dell */ 202#define DELL_VENDORID 0x1028 203#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 204#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 205#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 206#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 207#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 208#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 209#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 210 211/* Clevo */ 212#define CLEVO_VENDORID 0x1558 213#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 214#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 215 216/* Acer */ 217#define ACER_VENDORID 0x1025 218#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 219#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 220#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 221#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 222#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 223#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 224#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 225 226/* Asus */ 227#define ASUS_VENDORID 0x1043 228#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 229#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 230#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 231#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 232#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 233#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 234#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 235#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 236#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 237#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 238#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 239#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 240#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 241#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 242#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 243#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 244 245/* IBM / Lenovo */ 246#define IBM_VENDORID 0x1014 247#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 248#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 249 250/* Lenovo */ 251#define LENOVO_VENDORID 0x17aa 252#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 253#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 254#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 255#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 256 257/* Samsung */ 258#define SAMSUNG_VENDORID 0x144d 259#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 260#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 261 262/* Medion ? */ 263#define MEDION_VENDORID 0x161f 264#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 265#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 266 267/* Apple Computer Inc. */ 268#define APPLE_VENDORID 0x106b 269#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 270 271/* Sony */ 272#define SONY_VENDORID 0x104d 273#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 274#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 275 276/* 277 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 278 * instead of their own, which is beyond my comprehension 279 * (see HDA_CODEC_STAC9221 below). 280 */ 281#define APPLE_INTEL_MAC 0x76808384 282 283/* LG Electronics */ 284#define LG_VENDORID 0x1854 285#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 286#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 287 288/* Fujitsu Siemens */ 289#define FS_VENDORID 0x1734 290#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 291#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 292#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 293 294/* Fujitsu Limited */ 295#define FL_VENDORID 0x10cf 296#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 297#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 298#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 299 300/* Toshiba */ 301#define TOSHIBA_VENDORID 0x1179 302#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 303#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 304#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 305 306/* Micro-Star International (MSI) */ 307#define MSI_VENDORID 0x1462 308#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 309#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 310#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 311 312/* Giga-Byte Technology */ 313#define GB_VENDORID 0x1458 314#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 315#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 316 317/* Uniwill ? */ 318#define UNIWILL_VENDORID 0x1584 319#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 320#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 321 322 323/* Misc constants.. */ 324#define HDA_AMP_VOL_DEFAULT (-1) 325#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 326#define HDA_AMP_MUTE_NONE (0) 327#define HDA_AMP_MUTE_LEFT (1 << 0) 328#define HDA_AMP_MUTE_RIGHT (1 << 1) 329#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 330 331#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 332#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 333 334#define HDA_ADC_MONITOR (1 << 0) 335 336#define HDA_CTL_OUT 1 337#define HDA_CTL_IN 2 338 339#define HDA_GPIO_MAX 8 340/* 0 - 7 = GPIO , 8 = Flush */ 341#define HDA_QUIRK_GPIO0 (1 << 0) 342#define HDA_QUIRK_GPIO1 (1 << 1) 343#define HDA_QUIRK_GPIO2 (1 << 2) 344#define HDA_QUIRK_GPIO3 (1 << 3) 345#define HDA_QUIRK_GPIO4 (1 << 4) 346#define HDA_QUIRK_GPIO5 (1 << 5) 347#define HDA_QUIRK_GPIO6 (1 << 6) 348#define HDA_QUIRK_GPIO7 (1 << 7) 349#define HDA_QUIRK_GPIOFLUSH (1 << 8) 350 351/* 9 - 25 = anything else */ 352#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 353#define HDA_QUIRK_FIXEDRATE (1 << 10) 354#define HDA_QUIRK_FORCESTEREO (1 << 11) 355#define HDA_QUIRK_EAPDINV (1 << 12) 356#define HDA_QUIRK_DMAPOS (1 << 13) 357#define HDA_QUIRK_SENSEINV (1 << 14) 358 359/* 26 - 31 = vrefs */ 360#define HDA_QUIRK_IVREF50 (1 << 26) 361#define HDA_QUIRK_IVREF80 (1 << 27) 362#define HDA_QUIRK_IVREF100 (1 << 28) 363#define HDA_QUIRK_OVREF50 (1 << 29) 364#define HDA_QUIRK_OVREF80 (1 << 30) 365#define HDA_QUIRK_OVREF100 (1 << 31) 366 367#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 368 HDA_QUIRK_IVREF100) 369#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 370 HDA_QUIRK_OVREF100) 371#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 372 373#if __FreeBSD_version < 600000 374#define taskqueue_drain(...) 375#endif 376 377static const struct { 378 char *key; 379 uint32_t value; 380} hdac_quirks_tab[] = { 381 { "gpio0", HDA_QUIRK_GPIO0 }, 382 { "gpio1", HDA_QUIRK_GPIO1 }, 383 { "gpio2", HDA_QUIRK_GPIO2 }, 384 { "gpio3", HDA_QUIRK_GPIO3 }, 385 { "gpio4", HDA_QUIRK_GPIO4 }, 386 { "gpio5", HDA_QUIRK_GPIO5 }, 387 { "gpio6", HDA_QUIRK_GPIO6 }, 388 { "gpio7", HDA_QUIRK_GPIO7 }, 389 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 390 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 391 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 392 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 393 { "eapdinv", HDA_QUIRK_EAPDINV }, 394 { "dmapos", HDA_QUIRK_DMAPOS }, 395 { "senseinv", HDA_QUIRK_SENSEINV }, 396 { "ivref50", HDA_QUIRK_IVREF50 }, 397 { "ivref80", HDA_QUIRK_IVREF80 }, 398 { "ivref100", HDA_QUIRK_IVREF100 }, 399 { "ovref50", HDA_QUIRK_OVREF50 }, 400 { "ovref80", HDA_QUIRK_OVREF80 }, 401 { "ovref100", HDA_QUIRK_OVREF100 }, 402 { "ivref", HDA_QUIRK_IVREF }, 403 { "ovref", HDA_QUIRK_OVREF }, 404 { "vref", HDA_QUIRK_VREF }, 405}; 406#define HDAC_QUIRKS_TAB_LEN \ 407 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 408 409#define HDA_BDL_MIN 2 410#define HDA_BDL_MAX 256 411#define HDA_BDL_DEFAULT HDA_BDL_MIN 412 413#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 414#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 415 416#define HDA_BUFSZ_MIN 4096 417#define HDA_BUFSZ_MAX 65536 418#define HDA_BUFSZ_DEFAULT 16384 419 420#define HDA_PARSE_MAXDEPTH 10 421 422#define HDAC_UNSOLTAG_EVENT_HP 0x00 423 424MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 425 426const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 427 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 428 "White", "Other"}; 429 430const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 431 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 432 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 433 434const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 435 436/* Default */ 437static uint32_t hdac_fmt[] = { 438 AFMT_STEREO | AFMT_S16_LE, 439 0 440}; 441 442static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 443 444static const struct { 445 uint32_t model; 446 char *desc; 447} hdac_devices[] = { 448 { HDA_INTEL_82801F, "Intel 82801F" }, 449 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 450 { HDA_INTEL_82801G, "Intel 82801G" }, 451 { HDA_INTEL_82801H, "Intel 82801H" }, 452 { HDA_INTEL_82801I, "Intel 82801I" }, 453 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 454 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 455 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 456 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 457 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 458 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 459 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 460 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 461 { HDA_ATI_SB450, "ATI SB450" }, 462 { HDA_ATI_SB600, "ATI SB600" }, 463 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 464 { HDA_SIS_966, "SiS 966" }, 465 /* Unknown */ 466 { HDA_INTEL_ALL, "Intel (Unknown)" }, 467 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 468 { HDA_ATI_ALL, "ATI (Unknown)" }, 469 { HDA_VIA_ALL, "VIA (Unknown)" }, 470 { HDA_SIS_ALL, "SiS (Unknown)" }, 471}; 472#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 473 474static const struct { 475 uint16_t vendor; 476 uint8_t reg; 477 uint8_t mask; 478 uint8_t enable; 479} hdac_pcie_snoop[] = { 480 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 481 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 482 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 483}; 484#define HDAC_PCIESNOOP_LEN \ 485 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 486 487static const struct { 488 uint32_t rate; 489 int valid; 490 uint16_t base; 491 uint16_t mul; 492 uint16_t div; 493} hda_rate_tab[] = { 494 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 495 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 496 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 497 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 498 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 499 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 500 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 501 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 502 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 503 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 504 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 505 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 506 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 507 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 508 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 509 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 510 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 511 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 512 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 513 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 514 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 515 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 516 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 517 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 518 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 519 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 520 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 521 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 522 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 523 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 524 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 525 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 526 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 527 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 528 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 529}; 530#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 531 532/* All codecs you can eat... */ 533#define HDA_CODEC_CONSTRUCT(vendor, id) \ 534 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 535 536/* Realtek */ 537#define REALTEK_VENDORID 0x10ec 538#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 539#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 540#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 541#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 542#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 543#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 544#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 545#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 546#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 547#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 548#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 549#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 550#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 551#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 552#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 553#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 554#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 555#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 556 557/* Analog Devices */ 558#define ANALOGDEVICES_VENDORID 0x11d4 559#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 560#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 561#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 562#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 563#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 564#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 565#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 566 567/* CMedia */ 568#define CMEDIA_VENDORID 0x434d 569#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 570#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 571 572/* Sigmatel */ 573#define SIGMATEL_VENDORID 0x8384 574#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 575#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 576#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 577#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 578#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 579#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 580#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 581#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 582#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 583#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 584#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 585#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 586#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 587#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 588#define HDA_CODEC_STAC9205 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 589#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 590 591/* Silicon Image */ 592#define SII_VENDORID 0x1095 593#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 594 595/* Lucent/Agere */ 596#define AGERE_VENDORID 0x11c1 597#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 598 599/* 600 * Conexant 601 * 602 * Ok, the truth is, I don't have any idea at all whether 603 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 604 * place that tell me it is "Venice" is from its Windows driver INF. 605 * 606 * Venice - CX????? 607 * Waikiki - CX20551-22 608 */ 609#define CONEXANT_VENDORID 0x14f1 610#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 611#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 612#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 613 614/* VIA */ 615#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 616#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 617#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 618#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 619#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 620#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 621#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 622#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 623#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 624#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 625#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 626#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 627#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 628 629/* ATI */ 630#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 631 632/* NVIDIA */ 633#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 634 635/* Codecs */ 636static const struct { 637 uint32_t id; 638 char *name; 639} hdac_codecs[] = { 640 { HDA_CODEC_ALC260, "Realtek ALC260" }, 641 { HDA_CODEC_ALC262, "Realtek ALC262" }, 642 { HDA_CODEC_ALC267, "Realtek ALC267" }, 643 { HDA_CODEC_ALC268, "Realtek ALC268" }, 644 { HDA_CODEC_ALC269, "Realtek ALC269" }, 645 { HDA_CODEC_ALC272, "Realtek ALC272" }, 646 { HDA_CODEC_ALC660, "Realtek ALC660" }, 647 { HDA_CODEC_ALC662, "Realtek ALC662" }, 648 { HDA_CODEC_ALC663, "Realtek ALC663" }, 649 { HDA_CODEC_ALC861, "Realtek ALC861" }, 650 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 651 { HDA_CODEC_ALC880, "Realtek ALC880" }, 652 { HDA_CODEC_ALC882, "Realtek ALC882" }, 653 { HDA_CODEC_ALC883, "Realtek ALC883" }, 654 { HDA_CODEC_ALC885, "Realtek ALC885" }, 655 { HDA_CODEC_ALC888, "Realtek ALC888" }, 656 { HDA_CODEC_ALC889, "Realtek ALC889" }, 657 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 658 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 659 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 660 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 661 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 662 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 663 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 664 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 665 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 666 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 667 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 668 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 669 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 670 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 671 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 672 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 673 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 674 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 675 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 676 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 677 { HDA_CODEC_STAC9205, "Sigmatel STAC9205" }, 678 { HDA_CODEC_STAC9872AK,"Sigmatel STAC9872AK" }, 679 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 680 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 681 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 682 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 683 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 684 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 685 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 686 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 687 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 688 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 689 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 690 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 691 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 692 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 693 /* Unknown codec */ 694 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 695 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 696 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 697 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 698 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 699 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 700 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 701 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 702 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 703 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 704}; 705#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 706 707 708/**************************************************************************** 709 * Function prototypes 710 ****************************************************************************/ 711static void hdac_intr_handler(void *); 712static int hdac_reset(struct hdac_softc *, int); 713static int hdac_get_capabilities(struct hdac_softc *); 714static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 715static int hdac_dma_alloc(struct hdac_softc *, 716 struct hdac_dma *, bus_size_t); 717static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 718static int hdac_mem_alloc(struct hdac_softc *); 719static void hdac_mem_free(struct hdac_softc *); 720static int hdac_irq_alloc(struct hdac_softc *); 721static void hdac_irq_free(struct hdac_softc *); 722static void hdac_corb_init(struct hdac_softc *); 723static void hdac_rirb_init(struct hdac_softc *); 724static void hdac_corb_start(struct hdac_softc *); 725static void hdac_rirb_start(struct hdac_softc *); 726static void hdac_scan_codecs(struct hdac_softc *); 727static void hdac_probe_codec(struct hdac_codec *); 728static void hdac_probe_function(struct hdac_codec *, nid_t); 729static int hdac_pcmchannel_setup(struct hdac_chan *); 730 731static void hdac_attach2(void *); 732 733static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 734 uint32_t, int); 735static void hdac_command_send_internal(struct hdac_softc *, 736 struct hdac_command_list *, int); 737 738static int hdac_probe(device_t); 739static int hdac_attach(device_t); 740static int hdac_detach(device_t); 741static int hdac_suspend(device_t); 742static int hdac_resume(device_t); 743static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 744static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 745 uint32_t, int, int); 746static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 747 nid_t, int, int, int); 748static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 749 nid_t, nid_t, int, int, int, int, int, int); 750static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 751 752static int hdac_rirb_flush(struct hdac_softc *sc); 753static int hdac_unsolq_flush(struct hdac_softc *sc); 754 755static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 756 757#define hdac_command(a1, a2, a3) \ 758 hdac_command_sendone_internal(a1, a2, a3) 759 760#define hdac_codec_id(c) \ 761 ((uint32_t)((c == NULL) ? 0x00000000 : \ 762 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 763 ((uint32_t)(c)->device_id & 0x0000ffff)))) 764 765static char * 766hdac_codec_name(struct hdac_codec *codec) 767{ 768 uint32_t id; 769 int i; 770 771 id = hdac_codec_id(codec); 772 773 for (i = 0; i < HDAC_CODECS_LEN; i++) { 774 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 775 return (hdac_codecs[i].name); 776 } 777 778 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 779} 780 781static char * 782hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 783{ 784 static char *ossname[] = SOUND_DEVICE_NAMES; 785 int i, first = 1; 786 787 bzero(buf, len); 788 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 789 if (mask & (1 << i)) { 790 if (first == 0) 791 strlcat(buf, ", ", len); 792 strlcat(buf, ossname[i], len); 793 first = 0; 794 } 795 } 796 return (buf); 797} 798 799static struct hdac_audio_ctl * 800hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 801{ 802 if (devinfo == NULL || 803 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 804 index == NULL || devinfo->function.audio.ctl == NULL || 805 devinfo->function.audio.ctlcnt < 1 || 806 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 807 return (NULL); 808 return (&devinfo->function.audio.ctl[(*index)++]); 809} 810 811static struct hdac_audio_ctl * 812hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 813 int index, int cnt) 814{ 815 struct hdac_audio_ctl *ctl; 816 int i, found = 0; 817 818 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 819 return (NULL); 820 821 i = 0; 822 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 823 if (ctl->enable == 0) 824 continue; 825 if (ctl->widget->nid != nid) 826 continue; 827 if (dir && ctl->ndir != dir) 828 continue; 829 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 830 ctl->dir == ctl->ndir && ctl->index != index) 831 continue; 832 found++; 833 if (found == cnt || cnt <= 0) 834 return (ctl); 835 } 836 837 return (NULL); 838} 839 840/* 841 * Jack detection (Speaker/HP redirection) event handler. 842 */ 843static void 844hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 845{ 846 struct hdac_audio_as *as; 847 struct hdac_softc *sc; 848 struct hdac_widget *w; 849 struct hdac_audio_ctl *ctl; 850 uint32_t val, res; 851 int i, j; 852 nid_t cad; 853 854 if (devinfo == NULL || devinfo->codec == NULL || 855 devinfo->codec->sc == NULL) 856 return; 857 858 sc = devinfo->codec->sc; 859 cad = devinfo->codec->cad; 860 as = devinfo->function.audio.as; 861 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 862 if (as[i].hpredir < 0) 863 continue; 864 865 w = hdac_widget_get(devinfo, as[i].pins[15]); 866 if (w == NULL || w->enable == 0 || w->type != 867 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 868 continue; 869 870 res = hdac_command(sc, 871 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 872 873 HDA_BOOTVERBOSE( 874 device_printf(sc->dev, 875 "Pin sense: nid=%d res=0x%08x\n", 876 as[i].pins[15], res); 877 ); 878 879 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 880 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 881 res ^= 1; 882 883 /* (Un)Mute headphone pin. */ 884 ctl = hdac_audio_ctl_amp_get(devinfo, 885 as[i].pins[15], HDA_CTL_IN, -1, 1); 886 if (ctl != NULL && ctl->mute) { 887 /* If pin has muter - use it. */ 888 val = (res != 0) ? 0 : 1; 889 if (val != ctl->forcemute) { 890 ctl->forcemute = val; 891 hdac_audio_ctl_amp_set(ctl, 892 HDA_AMP_MUTE_DEFAULT, 893 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 894 } 895 } else { 896 /* If there is no muter - disable pin output. */ 897 w = hdac_widget_get(devinfo, as[i].pins[15]); 898 if (w != NULL && w->type == 899 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 900 if (res != 0) 901 val = w->wclass.pin.ctrl | 902 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 903 else 904 val = w->wclass.pin.ctrl & 905 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 906 if (val != w->wclass.pin.ctrl) { 907 w->wclass.pin.ctrl = val; 908 hdac_command(sc, 909 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 910 w->nid, w->wclass.pin.ctrl), cad); 911 } 912 } 913 } 914 /* (Un)Mute other pins. */ 915 for (j = 0; j < 15; j++) { 916 if (as[i].pins[j] <= 0) 917 continue; 918 ctl = hdac_audio_ctl_amp_get(devinfo, 919 as[i].pins[j], HDA_CTL_IN, -1, 1); 920 if (ctl != NULL && ctl->mute) { 921 /* If pin has muter - use it. */ 922 val = (res != 0) ? 1 : 0; 923 if (val == ctl->forcemute) 924 continue; 925 ctl->forcemute = val; 926 hdac_audio_ctl_amp_set(ctl, 927 HDA_AMP_MUTE_DEFAULT, 928 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 929 continue; 930 } 931 /* If there is no muter - disable pin output. */ 932 w = hdac_widget_get(devinfo, as[i].pins[j]); 933 if (w != NULL && w->type == 934 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 935 if (res != 0) 936 val = w->wclass.pin.ctrl & 937 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 938 else 939 val = w->wclass.pin.ctrl | 940 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 941 if (val != w->wclass.pin.ctrl) { 942 w->wclass.pin.ctrl = val; 943 hdac_command(sc, 944 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 945 w->nid, w->wclass.pin.ctrl), cad); 946 } 947 } 948 } 949 } 950} 951 952/* 953 * Callback for poll based jack detection. 954 */ 955static void 956hdac_jack_poll_callback(void *arg) 957{ 958 struct hdac_devinfo *devinfo = arg; 959 struct hdac_softc *sc; 960 961 if (devinfo == NULL || devinfo->codec == NULL || 962 devinfo->codec->sc == NULL) 963 return; 964 sc = devinfo->codec->sc; 965 hdac_lock(sc); 966 if (sc->poll_ival == 0) { 967 hdac_unlock(sc); 968 return; 969 } 970 hdac_hp_switch_handler(devinfo); 971 callout_reset(&sc->poll_jack, sc->poll_ival, 972 hdac_jack_poll_callback, devinfo); 973 hdac_unlock(sc); 974} 975 976/* 977 * Jack detection initializer. 978 */ 979static void 980hdac_hp_switch_init(struct hdac_devinfo *devinfo) 981{ 982 struct hdac_softc *sc = devinfo->codec->sc; 983 struct hdac_audio_as *as = devinfo->function.audio.as; 984 struct hdac_widget *w; 985 uint32_t id; 986 int i, enable = 0, poll = 0; 987 nid_t cad; 988 989 id = hdac_codec_id(devinfo->codec); 990 cad = devinfo->codec->cad; 991 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 992 if (as[i].hpredir < 0) 993 continue; 994 995 w = hdac_widget_get(devinfo, as[i].pins[15]); 996 if (w == NULL || w->enable == 0 || w->type != 997 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 998 continue; 999 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1000 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1001 device_printf(sc->dev, 1002 "No jack detection support at pin %d\n", 1003 as[i].pins[15]); 1004 continue; 1005 } 1006 enable = 1; 1007 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1008 hdac_command(sc, 1009 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1010 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1011 HDAC_UNSOLTAG_EVENT_HP), cad); 1012 } else 1013 poll = 1; 1014 HDA_BOOTVERBOSE( 1015 device_printf(sc->dev, 1016 "Enabling headphone/speaker " 1017 "audio routing switching:\n"); 1018 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1019 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1020 ); 1021 } 1022 if (enable) { 1023 hdac_hp_switch_handler(devinfo); 1024 if (poll) { 1025 callout_reset(&sc->poll_jack, 1, 1026 hdac_jack_poll_callback, devinfo); 1027 } 1028 } 1029} 1030 1031/* 1032 * Unsolicited messages handler. 1033 */ 1034static void 1035hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1036{ 1037 struct hdac_softc *sc; 1038 struct hdac_devinfo *devinfo = NULL; 1039 int i; 1040 1041 if (codec == NULL || codec->sc == NULL) 1042 return; 1043 1044 sc = codec->sc; 1045 1046 HDA_BOOTVERBOSE( 1047 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1048 ); 1049 1050 for (i = 0; i < codec->num_fgs; i++) { 1051 if (codec->fgs[i].node_type == 1052 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1053 devinfo = &codec->fgs[i]; 1054 break; 1055 } 1056 } 1057 1058 if (devinfo == NULL) 1059 return; 1060 1061 switch (tag) { 1062 case HDAC_UNSOLTAG_EVENT_HP: 1063 hdac_hp_switch_handler(devinfo); 1064 break; 1065 default: 1066 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1067 break; 1068 } 1069} 1070 1071static int 1072hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1073{ 1074 /* XXX to be removed */ 1075#ifdef HDAC_INTR_EXTRA 1076 uint32_t res; 1077#endif 1078 1079 if (!(ch->flags & HDAC_CHN_RUNNING)) 1080 return (0); 1081 1082 /* XXX to be removed */ 1083#ifdef HDAC_INTR_EXTRA 1084 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1085#endif 1086 1087 /* XXX to be removed */ 1088#ifdef HDAC_INTR_EXTRA 1089 HDA_BOOTVERBOSE( 1090 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1091 device_printf(ch->pdevinfo->dev, 1092 "PCMDIR_%s intr triggered beyond stream boundary:" 1093 "%08x\n", 1094 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1095 ); 1096#endif 1097 1098 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1099 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1100 1101 /* XXX to be removed */ 1102#ifdef HDAC_INTR_EXTRA 1103 if (res & HDAC_SDSTS_BCIS) { 1104#endif 1105 return (1); 1106 /* XXX to be removed */ 1107#ifdef HDAC_INTR_EXTRA 1108 } 1109#endif 1110 1111 return (0); 1112} 1113 1114/**************************************************************************** 1115 * void hdac_intr_handler(void *) 1116 * 1117 * Interrupt handler. Processes interrupts received from the hdac. 1118 ****************************************************************************/ 1119static void 1120hdac_intr_handler(void *context) 1121{ 1122 struct hdac_softc *sc; 1123 uint32_t intsts; 1124 uint8_t rirbsts; 1125 struct hdac_rirb *rirb_base; 1126 uint32_t trigger; 1127 int i; 1128 1129 sc = (struct hdac_softc *)context; 1130 1131 hdac_lock(sc); 1132 if (sc->polling != 0) { 1133 hdac_unlock(sc); 1134 return; 1135 } 1136 1137 /* Do we have anything to do? */ 1138 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1139 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1140 hdac_unlock(sc); 1141 return; 1142 } 1143 1144 trigger = 0; 1145 1146 /* Was this a controller interrupt? */ 1147 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1148 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1149 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1150 /* Get as many responses that we can */ 1151 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1152 HDAC_WRITE_1(&sc->mem, 1153 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1154 if (hdac_rirb_flush(sc) != 0) 1155 trigger |= HDAC_TRIGGER_UNSOL; 1156 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1157 } 1158 /* XXX to be removed */ 1159 /* Clear interrupt and exit */ 1160#ifdef HDAC_INTR_EXTRA 1161 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1162#endif 1163 } 1164 1165 if (intsts & HDAC_INTSTS_SIS_MASK) { 1166 for (i = 0; i < sc->num_chans; i++) { 1167 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1168 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1169 trigger |= (1 << i); 1170 } 1171 /* XXX to be removed */ 1172#ifdef HDAC_INTR_EXTRA 1173 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1174 HDAC_INTSTS_SIS_MASK); 1175#endif 1176 } 1177 1178 hdac_unlock(sc); 1179 1180 for (i = 0; i < sc->num_chans; i++) { 1181 if (trigger & (1 << i)) 1182 chn_intr(sc->chans[i].c); 1183 } 1184 if (trigger & HDAC_TRIGGER_UNSOL) 1185 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1186} 1187 1188/**************************************************************************** 1189 * int hdac_reset(hdac_softc *, int) 1190 * 1191 * Reset the hdac to a quiescent and known state. 1192 ****************************************************************************/ 1193static int 1194hdac_reset(struct hdac_softc *sc, int wakeup) 1195{ 1196 uint32_t gctl; 1197 int count, i; 1198 1199 /* 1200 * Stop all Streams DMA engine 1201 */ 1202 for (i = 0; i < sc->num_iss; i++) 1203 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1204 for (i = 0; i < sc->num_oss; i++) 1205 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1206 for (i = 0; i < sc->num_bss; i++) 1207 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1208 1209 /* 1210 * Stop Control DMA engines. 1211 */ 1212 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1213 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1214 1215 /* 1216 * Reset DMA position buffer. 1217 */ 1218 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1219 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1220 1221 /* 1222 * Reset the controller. The reset must remain asserted for 1223 * a minimum of 100us. 1224 */ 1225 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1226 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1227 count = 10000; 1228 do { 1229 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1230 if (!(gctl & HDAC_GCTL_CRST)) 1231 break; 1232 DELAY(10); 1233 } while (--count); 1234 if (gctl & HDAC_GCTL_CRST) { 1235 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1236 return (ENXIO); 1237 } 1238 1239 /* If wakeup is not requested - leave the controller in reset state. */ 1240 if (!wakeup) 1241 return (0); 1242 1243 DELAY(100); 1244 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1245 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1246 count = 10000; 1247 do { 1248 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1249 if (gctl & HDAC_GCTL_CRST) 1250 break; 1251 DELAY(10); 1252 } while (--count); 1253 if (!(gctl & HDAC_GCTL_CRST)) { 1254 device_printf(sc->dev, "Device stuck in reset\n"); 1255 return (ENXIO); 1256 } 1257 1258 /* 1259 * Wait for codecs to finish their own reset sequence. The delay here 1260 * should be of 250us but for some reasons, on it's not enough on my 1261 * computer. Let's use twice as much as necessary to make sure that 1262 * it's reset properly. 1263 */ 1264 DELAY(1000); 1265 1266 return (0); 1267} 1268 1269 1270/**************************************************************************** 1271 * int hdac_get_capabilities(struct hdac_softc *); 1272 * 1273 * Retreive the general capabilities of the hdac; 1274 * Number of Input Streams 1275 * Number of Output Streams 1276 * Number of bidirectional Streams 1277 * 64bit ready 1278 * CORB and RIRB sizes 1279 ****************************************************************************/ 1280static int 1281hdac_get_capabilities(struct hdac_softc *sc) 1282{ 1283 uint16_t gcap; 1284 uint8_t corbsize, rirbsize; 1285 1286 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1287 sc->num_iss = HDAC_GCAP_ISS(gcap); 1288 sc->num_oss = HDAC_GCAP_OSS(gcap); 1289 sc->num_bss = HDAC_GCAP_BSS(gcap); 1290 1291 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1292 1293 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1294 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1295 HDAC_CORBSIZE_CORBSZCAP_256) 1296 sc->corb_size = 256; 1297 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1298 HDAC_CORBSIZE_CORBSZCAP_16) 1299 sc->corb_size = 16; 1300 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1301 HDAC_CORBSIZE_CORBSZCAP_2) 1302 sc->corb_size = 2; 1303 else { 1304 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1305 __func__, corbsize); 1306 return (ENXIO); 1307 } 1308 1309 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1310 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1311 HDAC_RIRBSIZE_RIRBSZCAP_256) 1312 sc->rirb_size = 256; 1313 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1314 HDAC_RIRBSIZE_RIRBSZCAP_16) 1315 sc->rirb_size = 16; 1316 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1317 HDAC_RIRBSIZE_RIRBSZCAP_2) 1318 sc->rirb_size = 2; 1319 else { 1320 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1321 __func__, rirbsize); 1322 return (ENXIO); 1323 } 1324 1325 HDA_BOOTHVERBOSE( 1326 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1327 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1328 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1329 sc->num_iss, sc->num_oss, sc->num_bss); 1330 ); 1331 1332 return (0); 1333} 1334 1335 1336/**************************************************************************** 1337 * void hdac_dma_cb 1338 * 1339 * This function is called by bus_dmamap_load when the mapping has been 1340 * established. We just record the physical address of the mapping into 1341 * the struct hdac_dma passed in. 1342 ****************************************************************************/ 1343static void 1344hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1345{ 1346 struct hdac_dma *dma; 1347 1348 if (error == 0) { 1349 dma = (struct hdac_dma *)callback_arg; 1350 dma->dma_paddr = segs[0].ds_addr; 1351 } 1352} 1353 1354 1355/**************************************************************************** 1356 * int hdac_dma_alloc 1357 * 1358 * This function allocate and setup a dma region (struct hdac_dma). 1359 * It must be freed by a corresponding hdac_dma_free. 1360 ****************************************************************************/ 1361static int 1362hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1363{ 1364 bus_size_t roundsz; 1365 int result; 1366 int lowaddr; 1367 1368 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1369 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1370 BUS_SPACE_MAXADDR_32BIT; 1371 bzero(dma, sizeof(*dma)); 1372 1373 /* 1374 * Create a DMA tag 1375 */ 1376 result = bus_dma_tag_create(NULL, /* parent */ 1377 HDAC_DMA_ALIGNMENT, /* alignment */ 1378 0, /* boundary */ 1379 lowaddr, /* lowaddr */ 1380 BUS_SPACE_MAXADDR, /* highaddr */ 1381 NULL, /* filtfunc */ 1382 NULL, /* fistfuncarg */ 1383 roundsz, /* maxsize */ 1384 1, /* nsegments */ 1385 roundsz, /* maxsegsz */ 1386 0, /* flags */ 1387 NULL, /* lockfunc */ 1388 NULL, /* lockfuncarg */ 1389 &dma->dma_tag); /* dmat */ 1390 if (result != 0) { 1391 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1392 __func__, result); 1393 goto hdac_dma_alloc_fail; 1394 } 1395 1396 /* 1397 * Allocate DMA memory 1398 */ 1399 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1400 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1401 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1402 &dma->dma_map); 1403 if (result != 0) { 1404 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1405 __func__, result); 1406 goto hdac_dma_alloc_fail; 1407 } 1408 1409 dma->dma_size = roundsz; 1410 1411 /* 1412 * Map the memory 1413 */ 1414 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1415 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1416 if (result != 0 || dma->dma_paddr == 0) { 1417 if (result == 0) 1418 result = ENOMEM; 1419 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1420 __func__, result); 1421 goto hdac_dma_alloc_fail; 1422 } 1423 1424 HDA_BOOTHVERBOSE( 1425 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1426 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1427 ); 1428 1429 return (0); 1430 1431hdac_dma_alloc_fail: 1432 hdac_dma_free(sc, dma); 1433 1434 return (result); 1435} 1436 1437 1438/**************************************************************************** 1439 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1440 * 1441 * Free a struct dhac_dma that has been previously allocated via the 1442 * hdac_dma_alloc function. 1443 ****************************************************************************/ 1444static void 1445hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1446{ 1447 if (dma->dma_map != NULL) { 1448#if 0 1449 /* Flush caches */ 1450 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1451 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1452#endif 1453 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1454 } 1455 if (dma->dma_vaddr != NULL) { 1456 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1457 dma->dma_vaddr = NULL; 1458 } 1459 dma->dma_map = NULL; 1460 if (dma->dma_tag != NULL) { 1461 bus_dma_tag_destroy(dma->dma_tag); 1462 dma->dma_tag = NULL; 1463 } 1464 dma->dma_size = 0; 1465} 1466 1467/**************************************************************************** 1468 * int hdac_mem_alloc(struct hdac_softc *) 1469 * 1470 * Allocate all the bus resources necessary to speak with the physical 1471 * controller. 1472 ****************************************************************************/ 1473static int 1474hdac_mem_alloc(struct hdac_softc *sc) 1475{ 1476 struct hdac_mem *mem; 1477 1478 mem = &sc->mem; 1479 mem->mem_rid = PCIR_BAR(0); 1480 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1481 &mem->mem_rid, RF_ACTIVE); 1482 if (mem->mem_res == NULL) { 1483 device_printf(sc->dev, 1484 "%s: Unable to allocate memory resource\n", __func__); 1485 return (ENOMEM); 1486 } 1487 mem->mem_tag = rman_get_bustag(mem->mem_res); 1488 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1489 1490 return (0); 1491} 1492 1493/**************************************************************************** 1494 * void hdac_mem_free(struct hdac_softc *) 1495 * 1496 * Free up resources previously allocated by hdac_mem_alloc. 1497 ****************************************************************************/ 1498static void 1499hdac_mem_free(struct hdac_softc *sc) 1500{ 1501 struct hdac_mem *mem; 1502 1503 mem = &sc->mem; 1504 if (mem->mem_res != NULL) 1505 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1506 mem->mem_res); 1507 mem->mem_res = NULL; 1508} 1509 1510/**************************************************************************** 1511 * int hdac_irq_alloc(struct hdac_softc *) 1512 * 1513 * Allocate and setup the resources necessary for interrupt handling. 1514 ****************************************************************************/ 1515static int 1516hdac_irq_alloc(struct hdac_softc *sc) 1517{ 1518 struct hdac_irq *irq; 1519 int result; 1520 1521 irq = &sc->irq; 1522 irq->irq_rid = 0x0; 1523 1524#ifdef HDAC_MSI_ENABLED 1525 if ((sc->flags & HDAC_F_MSI) && 1526 (result = pci_msi_count(sc->dev)) == 1 && 1527 pci_alloc_msi(sc->dev, &result) == 0) 1528 irq->irq_rid = 0x1; 1529 else 1530#endif 1531 sc->flags &= ~HDAC_F_MSI; 1532 1533 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1534 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1535 if (irq->irq_res == NULL) { 1536 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1537 __func__); 1538 goto hdac_irq_alloc_fail; 1539 } 1540 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1541 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1542 if (result != 0) { 1543 device_printf(sc->dev, 1544 "%s: Unable to setup interrupt handler (%x)\n", 1545 __func__, result); 1546 goto hdac_irq_alloc_fail; 1547 } 1548 1549 return (0); 1550 1551hdac_irq_alloc_fail: 1552 hdac_irq_free(sc); 1553 1554 return (ENXIO); 1555} 1556 1557/**************************************************************************** 1558 * void hdac_irq_free(struct hdac_softc *) 1559 * 1560 * Free up resources previously allocated by hdac_irq_alloc. 1561 ****************************************************************************/ 1562static void 1563hdac_irq_free(struct hdac_softc *sc) 1564{ 1565 struct hdac_irq *irq; 1566 1567 irq = &sc->irq; 1568 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1569 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1570 if (irq->irq_res != NULL) 1571 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1572 irq->irq_res); 1573#ifdef HDAC_MSI_ENABLED 1574 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1575 pci_release_msi(sc->dev); 1576#endif 1577 irq->irq_handle = NULL; 1578 irq->irq_res = NULL; 1579 irq->irq_rid = 0x0; 1580} 1581 1582/**************************************************************************** 1583 * void hdac_corb_init(struct hdac_softc *) 1584 * 1585 * Initialize the corb registers for operations but do not start it up yet. 1586 * The CORB engine must not be running when this function is called. 1587 ****************************************************************************/ 1588static void 1589hdac_corb_init(struct hdac_softc *sc) 1590{ 1591 uint8_t corbsize; 1592 uint64_t corbpaddr; 1593 1594 /* Setup the CORB size. */ 1595 switch (sc->corb_size) { 1596 case 256: 1597 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1598 break; 1599 case 16: 1600 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1601 break; 1602 case 2: 1603 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1604 break; 1605 default: 1606 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1607 } 1608 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1609 1610 /* Setup the CORB Address in the hdac */ 1611 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1612 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1613 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1614 1615 /* Set the WP and RP */ 1616 sc->corb_wp = 0; 1617 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1618 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1619 /* 1620 * The HDA specification indicates that the CORBRPRST bit will always 1621 * read as zero. Unfortunately, it seems that at least the 82801G 1622 * doesn't reset the bit to zero, which stalls the corb engine. 1623 * manually reset the bit to zero before continuing. 1624 */ 1625 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1626 1627 /* Enable CORB error reporting */ 1628#if 0 1629 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1630#endif 1631} 1632 1633/**************************************************************************** 1634 * void hdac_rirb_init(struct hdac_softc *) 1635 * 1636 * Initialize the rirb registers for operations but do not start it up yet. 1637 * The RIRB engine must not be running when this function is called. 1638 ****************************************************************************/ 1639static void 1640hdac_rirb_init(struct hdac_softc *sc) 1641{ 1642 uint8_t rirbsize; 1643 uint64_t rirbpaddr; 1644 1645 /* Setup the RIRB size. */ 1646 switch (sc->rirb_size) { 1647 case 256: 1648 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1649 break; 1650 case 16: 1651 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1652 break; 1653 case 2: 1654 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1655 break; 1656 default: 1657 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1658 } 1659 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1660 1661 /* Setup the RIRB Address in the hdac */ 1662 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1663 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1664 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1665 1666 /* Setup the WP and RP */ 1667 sc->rirb_rp = 0; 1668 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1669 1670 /* Setup the interrupt threshold */ 1671 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1672 1673 /* Enable Overrun and response received reporting */ 1674#if 0 1675 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1676 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1677#else 1678 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1679#endif 1680 1681#if 0 1682 /* 1683 * Make sure that the Host CPU cache doesn't contain any dirty 1684 * cache lines that falls in the rirb. If I understood correctly, it 1685 * should be sufficient to do this only once as the rirb is purely 1686 * read-only from now on. 1687 */ 1688 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1689 BUS_DMASYNC_PREREAD); 1690#endif 1691} 1692 1693/**************************************************************************** 1694 * void hdac_corb_start(hdac_softc *) 1695 * 1696 * Startup the corb DMA engine 1697 ****************************************************************************/ 1698static void 1699hdac_corb_start(struct hdac_softc *sc) 1700{ 1701 uint32_t corbctl; 1702 1703 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1704 corbctl |= HDAC_CORBCTL_CORBRUN; 1705 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1706} 1707 1708/**************************************************************************** 1709 * void hdac_rirb_start(hdac_softc *) 1710 * 1711 * Startup the rirb DMA engine 1712 ****************************************************************************/ 1713static void 1714hdac_rirb_start(struct hdac_softc *sc) 1715{ 1716 uint32_t rirbctl; 1717 1718 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1719 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1720 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1721} 1722 1723 1724/**************************************************************************** 1725 * void hdac_scan_codecs(struct hdac_softc *, int) 1726 * 1727 * Scan the bus for available codecs, starting with num. 1728 ****************************************************************************/ 1729static void 1730hdac_scan_codecs(struct hdac_softc *sc) 1731{ 1732 struct hdac_codec *codec; 1733 int i; 1734 uint16_t statests; 1735 1736 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1737 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1738 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1739 /* We have found a codec. */ 1740 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1741 M_HDAC, M_ZERO | M_NOWAIT); 1742 if (codec == NULL) { 1743 device_printf(sc->dev, 1744 "Unable to allocate memory for codec\n"); 1745 continue; 1746 } 1747 codec->commands = NULL; 1748 codec->responses_received = 0; 1749 codec->verbs_sent = 0; 1750 codec->sc = sc; 1751 codec->cad = i; 1752 sc->codecs[i] = codec; 1753 hdac_probe_codec(codec); 1754 } 1755 } 1756 /* All codecs have been probed, now try to attach drivers to them */ 1757 /* bus_generic_attach(sc->dev); */ 1758} 1759 1760/**************************************************************************** 1761 * void hdac_probe_codec(struct hdac_softc *, int) 1762 * 1763 * Probe a the given codec_id for available function groups. 1764 ****************************************************************************/ 1765static void 1766hdac_probe_codec(struct hdac_codec *codec) 1767{ 1768 struct hdac_softc *sc = codec->sc; 1769 uint32_t vendorid, revisionid, subnode; 1770 int startnode; 1771 int endnode; 1772 int i; 1773 nid_t cad = codec->cad; 1774 1775 HDA_BOOTVERBOSE( 1776 device_printf(sc->dev, "Probing codec %d...\n", cad); 1777 ); 1778 vendorid = hdac_command(sc, 1779 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1780 cad); 1781 revisionid = hdac_command(sc, 1782 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1783 cad); 1784 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1785 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1786 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1787 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1788 1789 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1790 device_printf(sc->dev, "Codec #%d is not responding!" 1791 " Probing aborted.\n", cad); 1792 return; 1793 } 1794 1795 device_printf(sc->dev, "<HDA Codec #%d: %s>\n", 1796 cad, hdac_codec_name(codec)); 1797 HDA_BOOTVERBOSE( 1798 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 1799 hdac_codec_id(codec)); 1800 device_printf(sc->dev, " Vendor: 0x%04x\n", 1801 codec->vendor_id); 1802 device_printf(sc->dev, " Device: 0x%04x\n", 1803 codec->device_id); 1804 device_printf(sc->dev, " Revision: 0x%02x\n", 1805 codec->revision_id); 1806 device_printf(sc->dev, " Stepping: 0x%02x\n", 1807 codec->stepping_id); 1808 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1809 sc->pci_subvendor); 1810 ); 1811 subnode = hdac_command(sc, 1812 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1813 cad); 1814 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1815 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1816 1817 HDA_BOOTHVERBOSE( 1818 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1819 startnode, endnode); 1820 ); 1821 1822 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1823 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1824 if (codec->fgs == NULL) { 1825 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1826 __func__); 1827 return; 1828 } 1829 1830 for (i = startnode; i < endnode; i++) 1831 hdac_probe_function(codec, i); 1832 return; 1833} 1834 1835/* 1836 * Probe codec function and add it to the list. 1837 */ 1838static void 1839hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1840{ 1841 struct hdac_softc *sc = codec->sc; 1842 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1843 uint32_t fctgrptype; 1844 uint32_t res; 1845 nid_t cad = codec->cad; 1846 1847 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1848 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1849 1850 devinfo->nid = nid; 1851 devinfo->node_type = fctgrptype; 1852 devinfo->codec = codec; 1853 1854 res = hdac_command(sc, 1855 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1856 1857 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1858 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1859 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1860 1861 HDA_BOOTVERBOSE( 1862 device_printf(sc->dev, 1863 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1864 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1865 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1866 "unknown", nid, devinfo->startnode, devinfo->endnode, 1867 devinfo->nodecnt); 1868 ); 1869 1870 if (devinfo->nodecnt > 0) 1871 devinfo->widget = (struct hdac_widget *)malloc( 1872 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1873 M_NOWAIT | M_ZERO); 1874 else 1875 devinfo->widget = NULL; 1876 1877 if (devinfo->widget == NULL) { 1878 device_printf(sc->dev, "unable to allocate widgets!\n"); 1879 devinfo->endnode = devinfo->startnode; 1880 devinfo->nodecnt = 0; 1881 return; 1882 } 1883 1884 codec->num_fgs++; 1885} 1886 1887static void 1888hdac_widget_connection_parse(struct hdac_widget *w) 1889{ 1890 struct hdac_softc *sc = w->devinfo->codec->sc; 1891 uint32_t res; 1892 int i, j, max, ents, entnum; 1893 nid_t cad = w->devinfo->codec->cad; 1894 nid_t nid = w->nid; 1895 nid_t cnid, addcnid, prevcnid; 1896 1897 w->nconns = 0; 1898 1899 res = hdac_command(sc, 1900 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1901 1902 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1903 1904 if (ents < 1) 1905 return; 1906 1907 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1908 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1909 prevcnid = 0; 1910 1911#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1912#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1913#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1914#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1915#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1916 1917 for (i = 0; i < ents; i += entnum) { 1918 res = hdac_command(sc, 1919 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1920 for (j = 0; j < entnum; j++) { 1921 cnid = CONN_CNID(res, entnum, j); 1922 if (cnid == 0) { 1923 if (w->nconns < ents) 1924 device_printf(sc->dev, 1925 "%s: nid=%d WARNING: zero cnid " 1926 "entnum=%d j=%d index=%d " 1927 "entries=%d found=%d res=0x%08x\n", 1928 __func__, nid, entnum, j, i, 1929 ents, w->nconns, res); 1930 else 1931 goto getconns_out; 1932 } 1933 if (cnid < w->devinfo->startnode || 1934 cnid >= w->devinfo->endnode) { 1935 HDA_BOOTVERBOSE( 1936 device_printf(sc->dev, 1937 "GHOST: nid=%d j=%d " 1938 "entnum=%d index=%d res=0x%08x\n", 1939 nid, j, entnum, i, res); 1940 ); 1941 } 1942 if (CONN_RANGE(res, entnum, j) == 0) 1943 addcnid = cnid; 1944 else if (prevcnid == 0 || prevcnid >= cnid) { 1945 device_printf(sc->dev, 1946 "%s: WARNING: Invalid child range " 1947 "nid=%d index=%d j=%d entnum=%d " 1948 "prevcnid=%d cnid=%d res=0x%08x\n", 1949 __func__, nid, i, j, entnum, prevcnid, 1950 cnid, res); 1951 addcnid = cnid; 1952 } else 1953 addcnid = prevcnid + 1; 1954 while (addcnid <= cnid) { 1955 if (w->nconns > max) { 1956 device_printf(sc->dev, 1957 "Adding %d (nid=%d): " 1958 "Max connection reached! max=%d\n", 1959 addcnid, nid, max + 1); 1960 goto getconns_out; 1961 } 1962 w->connsenable[w->nconns] = 1; 1963 w->conns[w->nconns++] = addcnid++; 1964 } 1965 prevcnid = cnid; 1966 } 1967 } 1968 1969getconns_out: 1970 return; 1971} 1972 1973static uint32_t 1974hdac_widget_pin_patch(uint32_t config, const char *str) 1975{ 1976 char buf[256]; 1977 char *key, *value, *rest, *bad; 1978 int ival, i; 1979 1980 strlcpy(buf, str, sizeof(buf)); 1981 rest = buf; 1982 while ((key = strsep(&rest, "=")) != NULL) { 1983 value = strsep(&rest, " \t"); 1984 if (value == NULL) 1985 break; 1986 ival = strtol(value, &bad, 10); 1987 if (strcmp(key, "seq") == 0) { 1988 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 1989 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 1990 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 1991 } else if (strcmp(key, "as") == 0) { 1992 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 1993 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 1994 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 1995 } else if (strcmp(key, "misc") == 0) { 1996 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 1997 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 1998 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 1999 } else if (strcmp(key, "color") == 0) { 2000 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2001 if (bad[0] == 0) { 2002 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2003 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2004 }; 2005 for (i = 0; i < 16; i++) { 2006 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2007 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2008 break; 2009 } 2010 } 2011 } else if (strcmp(key, "ctype") == 0) { 2012 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2013 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2014 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2015 } else if (strcmp(key, "device") == 0) { 2016 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2017 if (bad[0] == 0) { 2018 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2019 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2020 continue; 2021 }; 2022 for (i = 0; i < 16; i++) { 2023 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2024 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2025 break; 2026 } 2027 } 2028 } else if (strcmp(key, "loc") == 0) { 2029 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2030 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2031 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2032 } else if (strcmp(key, "conn") == 0) { 2033 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2034 if (bad[0] == 0) { 2035 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2036 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2037 continue; 2038 }; 2039 for (i = 0; i < 4; i++) { 2040 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2041 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2042 break; 2043 } 2044 } 2045 } 2046 } 2047 return (config); 2048} 2049 2050static uint32_t 2051hdac_widget_pin_getconfig(struct hdac_widget *w) 2052{ 2053 struct hdac_softc *sc; 2054 uint32_t config, orig, id; 2055 nid_t cad, nid; 2056 char buf[32]; 2057 const char *res = NULL, *patch = NULL; 2058 2059 sc = w->devinfo->codec->sc; 2060 cad = w->devinfo->codec->cad; 2061 nid = w->nid; 2062 id = hdac_codec_id(w->devinfo->codec); 2063 2064 config = hdac_command(sc, 2065 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2066 cad); 2067 orig = config; 2068 2069 HDA_BOOTVERBOSE( 2070 hdac_dump_pin_config(w, orig); 2071 ); 2072 2073 /* XXX: Old patches require complete review. 2074 * Now they may create more problem then solve due to 2075 * incorrect associations. 2076 */ 2077 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2078 switch (nid) { 2079 case 26: 2080 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2081 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2082 break; 2083 case 27: 2084 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2085 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2086 break; 2087 default: 2088 break; 2089 } 2090 } else if (id == HDA_CODEC_ALC880 && 2091 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2092 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2093 /* 2094 * Super broken BIOS 2095 */ 2096 switch (nid) { 2097 case 24: /* MIC1 */ 2098 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2099 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2100 break; 2101 case 25: /* XXX MIC2 */ 2102 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2103 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2104 break; 2105 case 26: /* LINE1 */ 2106 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2107 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2108 break; 2109 case 27: /* XXX LINE2 */ 2110 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2111 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2112 break; 2113 case 28: /* CD */ 2114 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2115 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2116 break; 2117 } 2118 } else if (id == HDA_CODEC_ALC883 && 2119 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2120 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2121 switch (nid) { 2122 case 25: 2123 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2124 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2125 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2126 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2127 break; 2128 case 28: 2129 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2130 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2131 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2132 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2133 break; 2134 } 2135 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2136 HP_V3000_SUBVENDOR) { 2137 switch (nid) { 2138 case 18: 2139 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2140 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2141 break; 2142 case 20: 2143 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2144 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2145 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2146 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2147 break; 2148 case 21: 2149 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2150 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2151 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2152 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2153 break; 2154 } 2155 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2156 HP_DV5000_SUBVENDOR) { 2157 switch (nid) { 2158 case 20: 2159 case 21: 2160 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2161 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2162 break; 2163 } 2164 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2165 ASUS_W6F_SUBVENDOR) { 2166 switch (nid) { 2167 case 11: 2168 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2169 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2170 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2171 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2172 break; 2173 case 12: 2174 case 14: 2175 case 16: 2176 case 31: 2177 case 32: 2178 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2179 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2180 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2181 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2182 break; 2183 case 15: 2184 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2185 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2186 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2187 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2188 break; 2189 } 2190 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2191 UNIWILL_9075_SUBVENDOR) { 2192 switch (nid) { 2193 case 15: 2194 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2195 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2196 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2197 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2198 break; 2199 } 2200 } 2201 2202 /* New patches */ 2203 if (id == HDA_CODEC_AD1986A && 2204 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2205 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2206 switch (nid) { 2207 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2208 patch = "device=Line-in as=8 seq=1"; 2209 break; 2210 case 29: 2211 patch = "device=Mic as=8 seq=2"; 2212 break; 2213 case 31: /* Lot of inputs configured with as=15 and unusable */ 2214 patch = "as=8 seq=3"; 2215 break; 2216 case 32: 2217 patch = "as=8 seq=4"; 2218 break; 2219 case 34: 2220 patch = "as=8 seq=5"; 2221 break; 2222 case 36: 2223 patch = "as=8 seq=6"; 2224 break; 2225 } 2226 } else if (id == HDA_CODEC_ALC260 && 2227 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2228 switch (nid) { 2229 case 16: 2230 patch = "seq=15 device=Headphones"; 2231 break; 2232 } 2233 } else if (id == HDA_CODEC_ALC268 && 2234 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2235 switch (nid) { 2236 case 28: 2237 patch = "device=CD conn=fixed"; 2238 break; 2239 } 2240 } 2241 2242 if (patch != NULL) 2243 config = hdac_widget_pin_patch(config, patch); 2244 2245 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2246 if (resource_string_value(device_get_name(sc->dev), 2247 device_get_unit(sc->dev), buf, &res) == 0) { 2248 if (strncmp(res, "0x", 2) == 0) { 2249 config = strtol(res + 2, NULL, 16); 2250 } else { 2251 config = hdac_widget_pin_patch(config, res); 2252 } 2253 } 2254 2255 HDA_BOOTVERBOSE( 2256 if (config != orig) 2257 device_printf(sc->dev, 2258 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2259 nid, orig, config); 2260 ); 2261 2262 return (config); 2263} 2264 2265static uint32_t 2266hdac_widget_pin_getcaps(struct hdac_widget *w) 2267{ 2268 struct hdac_softc *sc; 2269 uint32_t caps, orig, id; 2270 nid_t cad, nid; 2271 2272 sc = w->devinfo->codec->sc; 2273 cad = w->devinfo->codec->cad; 2274 nid = w->nid; 2275 id = hdac_codec_id(w->devinfo->codec); 2276 2277 caps = hdac_command(sc, 2278 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2279 orig = caps; 2280 2281 HDA_BOOTVERBOSE( 2282 if (caps != orig) 2283 device_printf(sc->dev, 2284 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2285 nid, orig, caps); 2286 ); 2287 2288 return (caps); 2289} 2290 2291static void 2292hdac_widget_pin_parse(struct hdac_widget *w) 2293{ 2294 struct hdac_softc *sc = w->devinfo->codec->sc; 2295 uint32_t config, pincap; 2296 const char *devstr, *connstr; 2297 nid_t cad = w->devinfo->codec->cad; 2298 nid_t nid = w->nid; 2299 2300 config = hdac_widget_pin_getconfig(w); 2301 w->wclass.pin.config = config; 2302 2303 pincap = hdac_widget_pin_getcaps(w); 2304 w->wclass.pin.cap = pincap; 2305 2306 w->wclass.pin.ctrl = hdac_command(sc, 2307 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2308 2309 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2310 w->param.eapdbtl = hdac_command(sc, 2311 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2312 w->param.eapdbtl &= 0x7; 2313 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2314 } else 2315 w->param.eapdbtl = HDAC_INVALID; 2316 2317 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2318 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2319 2320 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2321 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2322 2323 strlcat(w->name, ": ", sizeof(w->name)); 2324 strlcat(w->name, devstr, sizeof(w->name)); 2325 strlcat(w->name, " (", sizeof(w->name)); 2326 strlcat(w->name, connstr, sizeof(w->name)); 2327 strlcat(w->name, ")", sizeof(w->name)); 2328} 2329 2330static uint32_t 2331hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2332{ 2333 struct hdac_softc *sc; 2334 uint32_t caps, orig, id; 2335 nid_t cad, nid, beeper = -1; 2336 2337 sc = w->devinfo->codec->sc; 2338 cad = w->devinfo->codec->cad; 2339 nid = w->nid; 2340 id = hdac_codec_id(w->devinfo->codec); 2341 2342 caps = hdac_command(sc, 2343 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2344 cad); 2345 orig = caps; 2346 2347 /* On some codecs beeper is an input pin, but it is not recordable 2348 alone. Also most of BIOSes does not declare beeper pin. 2349 Change beeper pin node type to beeper to help parser. */ 2350 *waspin = 0; 2351 switch (id) { 2352 case HDA_CODEC_AD1988: 2353 case HDA_CODEC_AD1988B: 2354 beeper = 26; 2355 break; 2356 case HDA_CODEC_ALC260: 2357 beeper = 23; 2358 break; 2359 case HDA_CODEC_ALC262: 2360 case HDA_CODEC_ALC268: 2361 case HDA_CODEC_ALC880: 2362 case HDA_CODEC_ALC882: 2363 case HDA_CODEC_ALC883: 2364 case HDA_CODEC_ALC885: 2365 case HDA_CODEC_ALC888: 2366 case HDA_CODEC_ALC889: 2367 beeper = 29; 2368 break; 2369 } 2370 if (nid == beeper) { 2371 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2372 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2373 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2374 *waspin = 1; 2375 } 2376 2377 HDA_BOOTVERBOSE( 2378 if (caps != orig) { 2379 device_printf(sc->dev, 2380 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2381 nid, orig, caps); 2382 } 2383 ); 2384 2385 return (caps); 2386} 2387 2388static void 2389hdac_widget_parse(struct hdac_widget *w) 2390{ 2391 struct hdac_softc *sc = w->devinfo->codec->sc; 2392 uint32_t wcap, cap; 2393 char *typestr; 2394 nid_t cad = w->devinfo->codec->cad; 2395 nid_t nid = w->nid; 2396 2397 wcap = hdac_widget_getcaps(w, &w->waspin); 2398 2399 w->param.widget_cap = wcap; 2400 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2401 2402 switch (w->type) { 2403 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2404 typestr = "audio output"; 2405 break; 2406 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2407 typestr = "audio input"; 2408 break; 2409 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2410 typestr = "audio mixer"; 2411 break; 2412 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2413 typestr = "audio selector"; 2414 break; 2415 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2416 typestr = "pin"; 2417 break; 2418 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2419 typestr = "power widget"; 2420 break; 2421 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2422 typestr = "volume widget"; 2423 break; 2424 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2425 typestr = "beep widget"; 2426 break; 2427 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2428 typestr = "vendor widget"; 2429 break; 2430 default: 2431 typestr = "unknown type"; 2432 break; 2433 } 2434 2435 strlcpy(w->name, typestr, sizeof(w->name)); 2436 2437 hdac_widget_connection_parse(w); 2438 2439 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2440 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2441 w->param.outamp_cap = 2442 hdac_command(sc, 2443 HDA_CMD_GET_PARAMETER(cad, nid, 2444 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2445 else 2446 w->param.outamp_cap = 2447 w->devinfo->function.audio.outamp_cap; 2448 } else 2449 w->param.outamp_cap = 0; 2450 2451 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2452 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2453 w->param.inamp_cap = 2454 hdac_command(sc, 2455 HDA_CMD_GET_PARAMETER(cad, nid, 2456 HDA_PARAM_INPUT_AMP_CAP), cad); 2457 else 2458 w->param.inamp_cap = 2459 w->devinfo->function.audio.inamp_cap; 2460 } else 2461 w->param.inamp_cap = 0; 2462 2463 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2464 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2465 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2466 cap = hdac_command(sc, 2467 HDA_CMD_GET_PARAMETER(cad, nid, 2468 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2469 w->param.supp_stream_formats = (cap != 0) ? cap : 2470 w->devinfo->function.audio.supp_stream_formats; 2471 cap = hdac_command(sc, 2472 HDA_CMD_GET_PARAMETER(cad, nid, 2473 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2474 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2475 w->devinfo->function.audio.supp_pcm_size_rate; 2476 } else { 2477 w->param.supp_stream_formats = 2478 w->devinfo->function.audio.supp_stream_formats; 2479 w->param.supp_pcm_size_rate = 2480 w->devinfo->function.audio.supp_pcm_size_rate; 2481 } 2482 } else { 2483 w->param.supp_stream_formats = 0; 2484 w->param.supp_pcm_size_rate = 0; 2485 } 2486 2487 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2488 hdac_widget_pin_parse(w); 2489} 2490 2491static struct hdac_widget * 2492hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2493{ 2494 if (devinfo == NULL || devinfo->widget == NULL || 2495 nid < devinfo->startnode || nid >= devinfo->endnode) 2496 return (NULL); 2497 return (&devinfo->widget[nid - devinfo->startnode]); 2498} 2499 2500static __inline int 2501hda_poll_channel(struct hdac_chan *ch) 2502{ 2503 uint32_t sz, delta; 2504 volatile uint32_t ptr; 2505 2506 if (!(ch->flags & HDAC_CHN_RUNNING)) 2507 return (0); 2508 2509 sz = ch->blksz * ch->blkcnt; 2510 if (ch->dmapos != NULL) 2511 ptr = *(ch->dmapos); 2512 else 2513 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2514 ch->off + HDAC_SDLPIB); 2515 ch->ptr = ptr; 2516 ptr %= sz; 2517 ptr &= ~(ch->blksz - 1); 2518 delta = (sz + ptr - ch->prevptr) % sz; 2519 2520 if (delta < ch->blksz) 2521 return (0); 2522 2523 ch->prevptr = ptr; 2524 2525 return (1); 2526} 2527 2528static void 2529hda_poll_callback(void *arg) 2530{ 2531 struct hdac_softc *sc = arg; 2532 uint32_t trigger; 2533 int i, active = 0; 2534 2535 if (sc == NULL) 2536 return; 2537 2538 hdac_lock(sc); 2539 if (sc->polling == 0) { 2540 hdac_unlock(sc); 2541 return; 2542 } 2543 2544 trigger = 0; 2545 for (i = 0; i < sc->num_chans; i++) { 2546 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2547 continue; 2548 active = 1; 2549 if (hda_poll_channel(&sc->chans[i])) 2550 trigger |= (1 << i); 2551 } 2552 2553 /* XXX */ 2554 if (active) 2555 callout_reset(&sc->poll_hda, sc->poll_ticks, 2556 hda_poll_callback, sc); 2557 2558 hdac_unlock(sc); 2559 2560 for (i = 0; i < sc->num_chans; i++) { 2561 if (trigger & (1 << i)) 2562 chn_intr(sc->chans[i].c); 2563 } 2564} 2565 2566static int 2567hdac_rirb_flush(struct hdac_softc *sc) 2568{ 2569 struct hdac_rirb *rirb_base, *rirb; 2570 struct hdac_codec *codec; 2571 struct hdac_command_list *commands; 2572 nid_t cad; 2573 uint32_t resp; 2574 uint8_t rirbwp; 2575 int ret; 2576 2577 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2578 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2579#if 0 2580 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2581 BUS_DMASYNC_POSTREAD); 2582#endif 2583 2584 ret = 0; 2585 2586 while (sc->rirb_rp != rirbwp) { 2587 sc->rirb_rp++; 2588 sc->rirb_rp %= sc->rirb_size; 2589 rirb = &rirb_base[sc->rirb_rp]; 2590 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2591 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2592 sc->codecs[cad] == NULL) 2593 continue; 2594 resp = rirb->response; 2595 codec = sc->codecs[cad]; 2596 commands = codec->commands; 2597 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2598 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2599 ((resp >> 26) & 0xffff); 2600 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2601 } else if (commands != NULL && commands->num_commands > 0 && 2602 codec->responses_received < commands->num_commands) 2603 commands->responses[codec->responses_received++] = 2604 resp; 2605 ret++; 2606 } 2607 2608 return (ret); 2609} 2610 2611static int 2612hdac_unsolq_flush(struct hdac_softc *sc) 2613{ 2614 nid_t cad; 2615 uint32_t tag; 2616 int ret = 0; 2617 2618 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2619 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2620 while (sc->unsolq_rp != sc->unsolq_wp) { 2621 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2622 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2623 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2624 hdac_unsolicited_handler(sc->codecs[cad], tag); 2625 ret++; 2626 } 2627 sc->unsolq_st = HDAC_UNSOLQ_READY; 2628 } 2629 2630 return (ret); 2631} 2632 2633static void 2634hdac_poll_callback(void *arg) 2635{ 2636 struct hdac_softc *sc = arg; 2637 if (sc == NULL) 2638 return; 2639 2640 hdac_lock(sc); 2641 if (sc->polling == 0 || sc->poll_ival == 0) { 2642 hdac_unlock(sc); 2643 return; 2644 } 2645 if (hdac_rirb_flush(sc) != 0) 2646 hdac_unsolq_flush(sc); 2647 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2648 hdac_unlock(sc); 2649} 2650 2651static void 2652hdac_poll_reinit(struct hdac_softc *sc) 2653{ 2654 int i, pollticks, min = 1000000; 2655 struct hdac_chan *ch; 2656 2657 for (i = 0; i < sc->num_chans; i++) { 2658 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2659 continue; 2660 ch = &sc->chans[i]; 2661 pollticks = ((uint64_t)hz * ch->blksz) / 2662 ((uint64_t)sndbuf_getbps(ch->b) * 2663 sndbuf_getspd(ch->b)); 2664 pollticks >>= 1; 2665 if (pollticks > hz) 2666 pollticks = hz; 2667 if (pollticks < 1) { 2668 HDA_BOOTVERBOSE( 2669 device_printf(sc->dev, 2670 "%s: pollticks=%d < 1 !\n", 2671 __func__, pollticks); 2672 ); 2673 pollticks = 1; 2674 } 2675 if (min > pollticks) 2676 min = pollticks; 2677 } 2678 HDA_BOOTVERBOSE( 2679 device_printf(sc->dev, 2680 "%s: pollticks %d -> %d\n", 2681 __func__, sc->poll_ticks, min); 2682 ); 2683 sc->poll_ticks = min; 2684 if (min == 1000000) 2685 callout_stop(&sc->poll_hda); 2686 else 2687 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2688} 2689 2690static void 2691hdac_stream_stop(struct hdac_chan *ch) 2692{ 2693 struct hdac_softc *sc = ch->devinfo->codec->sc; 2694 uint32_t ctl; 2695 2696 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2697 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2698 HDAC_SDCTL_RUN); 2699 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2700 2701 ch->flags &= ~HDAC_CHN_RUNNING; 2702 2703 if (sc->polling != 0) 2704 hdac_poll_reinit(sc); 2705 2706 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2707 ctl &= ~(1 << (ch->off >> 5)); 2708 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2709} 2710 2711static void 2712hdac_stream_start(struct hdac_chan *ch) 2713{ 2714 struct hdac_softc *sc = ch->devinfo->codec->sc; 2715 uint32_t ctl; 2716 2717 ch->flags |= HDAC_CHN_RUNNING; 2718 2719 if (sc->polling != 0) 2720 hdac_poll_reinit(sc); 2721 2722 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2723 ctl |= 1 << (ch->off >> 5); 2724 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2725 2726 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2727 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2728 HDAC_SDCTL_RUN; 2729 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2730} 2731 2732static void 2733hdac_stream_reset(struct hdac_chan *ch) 2734{ 2735 struct hdac_softc *sc = ch->devinfo->codec->sc; 2736 int timeout = 1000; 2737 int to = timeout; 2738 uint32_t ctl; 2739 2740 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2741 ctl |= HDAC_SDCTL_SRST; 2742 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2743 do { 2744 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2745 if (ctl & HDAC_SDCTL_SRST) 2746 break; 2747 DELAY(10); 2748 } while (--to); 2749 if (!(ctl & HDAC_SDCTL_SRST)) { 2750 device_printf(sc->dev, "timeout in reset\n"); 2751 } 2752 ctl &= ~HDAC_SDCTL_SRST; 2753 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2754 to = timeout; 2755 do { 2756 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2757 if (!(ctl & HDAC_SDCTL_SRST)) 2758 break; 2759 DELAY(10); 2760 } while (--to); 2761 if (ctl & HDAC_SDCTL_SRST) 2762 device_printf(sc->dev, "can't reset!\n"); 2763} 2764 2765static void 2766hdac_stream_setid(struct hdac_chan *ch) 2767{ 2768 struct hdac_softc *sc = ch->devinfo->codec->sc; 2769 uint32_t ctl; 2770 2771 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2772 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2773 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2774 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2775} 2776 2777static void 2778hdac_bdl_setup(struct hdac_chan *ch) 2779{ 2780 struct hdac_softc *sc = ch->devinfo->codec->sc; 2781 struct hdac_bdle *bdle; 2782 uint64_t addr; 2783 uint32_t blksz, blkcnt; 2784 int i; 2785 2786 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2787 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2788 2789 blksz = ch->blksz; 2790 blkcnt = ch->blkcnt; 2791 2792 for (i = 0; i < blkcnt; i++, bdle++) { 2793 bdle->addrl = (uint32_t)addr; 2794 bdle->addrh = (uint32_t)(addr >> 32); 2795 bdle->len = blksz; 2796 bdle->ioc = 1; 2797 addr += blksz; 2798 } 2799 2800 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2801 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2802 addr = ch->bdl_dma.dma_paddr; 2803 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2804 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2805 if (ch->dmapos != NULL && 2806 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2807 addr = sc->pos_dma.dma_paddr; 2808 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2809 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2810 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2811 } 2812} 2813 2814static int 2815hdac_bdl_alloc(struct hdac_chan *ch) 2816{ 2817 struct hdac_softc *sc = ch->devinfo->codec->sc; 2818 int rc; 2819 2820 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2821 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2822 if (rc) { 2823 device_printf(sc->dev, "can't alloc bdl\n"); 2824 return (rc); 2825 } 2826 2827 return (0); 2828} 2829 2830static void 2831hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2832 int index, int lmute, int rmute, 2833 int left, int right, int dir) 2834{ 2835 uint16_t v = 0; 2836 2837 if (sc == NULL) 2838 return; 2839 2840 if (left != right || lmute != rmute) { 2841 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2842 (lmute << 7) | left; 2843 hdac_command(sc, 2844 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2845 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2846 (rmute << 7) | right; 2847 } else 2848 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2849 (lmute << 7) | left; 2850 2851 hdac_command(sc, 2852 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2853} 2854 2855static void 2856hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2857 int left, int right) 2858{ 2859 struct hdac_softc *sc; 2860 nid_t nid, cad; 2861 int lmute, rmute; 2862 2863 sc = ctl->widget->devinfo->codec->sc; 2864 cad = ctl->widget->devinfo->codec->cad; 2865 nid = ctl->widget->nid; 2866 2867 /* Save new values if valid. */ 2868 if (mute != HDA_AMP_MUTE_DEFAULT) 2869 ctl->muted = mute; 2870 if (left != HDA_AMP_VOL_DEFAULT) 2871 ctl->left = left; 2872 if (right != HDA_AMP_VOL_DEFAULT) 2873 ctl->right = right; 2874 /* Prepare effective values */ 2875 if (ctl->forcemute) { 2876 lmute = 1; 2877 rmute = 1; 2878 left = 0; 2879 right = 0; 2880 } else { 2881 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2882 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2883 left = ctl->left; 2884 right = ctl->right; 2885 } 2886 /* Apply effective values */ 2887 if (ctl->dir & HDA_CTL_OUT) 2888 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2889 lmute, rmute, left, right, 0); 2890 if (ctl->dir & HDA_CTL_IN) 2891 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2892 lmute, rmute, left, right, 1); 2893} 2894 2895static void 2896hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2897{ 2898 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2899 return; 2900 hdac_command(w->devinfo->codec->sc, 2901 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2902 w->nid, index), w->devinfo->codec->cad); 2903 w->selconn = index; 2904} 2905 2906 2907/**************************************************************************** 2908 * uint32_t hdac_command_sendone_internal 2909 * 2910 * Wrapper function that sends only one command to a given codec 2911 ****************************************************************************/ 2912static uint32_t 2913hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2914{ 2915 struct hdac_command_list cl; 2916 uint32_t response = HDAC_INVALID; 2917 2918 if (!hdac_lockowned(sc)) 2919 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2920 cl.num_commands = 1; 2921 cl.verbs = &verb; 2922 cl.responses = &response; 2923 2924 hdac_command_send_internal(sc, &cl, cad); 2925 2926 return (response); 2927} 2928 2929/**************************************************************************** 2930 * hdac_command_send_internal 2931 * 2932 * Send a command list to the codec via the corb. We queue as much verbs as 2933 * we can and msleep on the codec. When the interrupt get the responses 2934 * back from the rirb, it will wake us up so we can queue the remaining verbs 2935 * if any. 2936 ****************************************************************************/ 2937static void 2938hdac_command_send_internal(struct hdac_softc *sc, 2939 struct hdac_command_list *commands, nid_t cad) 2940{ 2941 struct hdac_codec *codec; 2942 int corbrp; 2943 uint32_t *corb; 2944 int timeout; 2945 int retry = 10; 2946 struct hdac_rirb *rirb_base; 2947 2948 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2949 commands->num_commands < 1) 2950 return; 2951 2952 codec = sc->codecs[cad]; 2953 codec->commands = commands; 2954 codec->responses_received = 0; 2955 codec->verbs_sent = 0; 2956 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2957 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2958 2959 do { 2960 if (codec->verbs_sent != commands->num_commands) { 2961 /* Queue as many verbs as possible */ 2962 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2963#if 0 2964 bus_dmamap_sync(sc->corb_dma.dma_tag, 2965 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2966#endif 2967 while (codec->verbs_sent != commands->num_commands && 2968 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2969 sc->corb_wp++; 2970 sc->corb_wp %= sc->corb_size; 2971 corb[sc->corb_wp] = 2972 commands->verbs[codec->verbs_sent++]; 2973 } 2974 2975 /* Send the verbs to the codecs */ 2976#if 0 2977 bus_dmamap_sync(sc->corb_dma.dma_tag, 2978 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2979#endif 2980 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2981 } 2982 2983 timeout = 1000; 2984 while (hdac_rirb_flush(sc) == 0 && --timeout) 2985 DELAY(10); 2986 } while ((codec->verbs_sent != commands->num_commands || 2987 codec->responses_received != commands->num_commands) && --retry); 2988 2989 if (retry == 0) 2990 device_printf(sc->dev, 2991 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2992 __func__, commands->num_commands, codec->verbs_sent, 2993 codec->responses_received); 2994 2995 codec->commands = NULL; 2996 codec->responses_received = 0; 2997 codec->verbs_sent = 0; 2998 2999 hdac_unsolq_flush(sc); 3000} 3001 3002 3003/**************************************************************************** 3004 * Device Methods 3005 ****************************************************************************/ 3006 3007/**************************************************************************** 3008 * int hdac_probe(device_t) 3009 * 3010 * Probe for the presence of an hdac. If none is found, check for a generic 3011 * match using the subclass of the device. 3012 ****************************************************************************/ 3013static int 3014hdac_probe(device_t dev) 3015{ 3016 int i, result; 3017 uint32_t model; 3018 uint16_t class, subclass; 3019 char desc[64]; 3020 3021 model = (uint32_t)pci_get_device(dev) << 16; 3022 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3023 class = pci_get_class(dev); 3024 subclass = pci_get_subclass(dev); 3025 3026 bzero(desc, sizeof(desc)); 3027 result = ENXIO; 3028 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3029 if (hdac_devices[i].model == model) { 3030 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3031 result = BUS_PROBE_DEFAULT; 3032 break; 3033 } 3034 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3035 class == PCIC_MULTIMEDIA && 3036 subclass == PCIS_MULTIMEDIA_HDA) { 3037 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3038 result = BUS_PROBE_GENERIC; 3039 break; 3040 } 3041 } 3042 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3043 subclass == PCIS_MULTIMEDIA_HDA) { 3044 strlcpy(desc, "Generic", sizeof(desc)); 3045 result = BUS_PROBE_GENERIC; 3046 } 3047 if (result != ENXIO) { 3048 strlcat(desc, " High Definition Audio Controller", 3049 sizeof(desc)); 3050 device_set_desc_copy(dev, desc); 3051 } 3052 3053 return (result); 3054} 3055 3056static void * 3057hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3058 struct pcm_channel *c, int dir) 3059{ 3060 struct hdac_pcm_devinfo *pdevinfo = data; 3061 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3062 struct hdac_softc *sc = devinfo->codec->sc; 3063 struct hdac_chan *ch; 3064 int i, ord = 0, chid; 3065 3066 hdac_lock(sc); 3067 3068 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3069 ch = &sc->chans[chid]; 3070 for (i = 0; i < sc->num_chans && i < chid; i++) { 3071 if (ch->dir == sc->chans[i].dir) 3072 ord++; 3073 } 3074 if (dir == PCMDIR_PLAY) { 3075 ch->off = (sc->num_iss + ord) << 5; 3076 } else { 3077 ch->off = ord << 5; 3078 } 3079 3080 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3081 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3082 ch->pcmrates[0] = 48000; 3083 ch->pcmrates[1] = 0; 3084 } 3085 if (sc->pos_dma.dma_vaddr != NULL) 3086 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3087 (sc->streamcnt * 8)); 3088 else 3089 ch->dmapos = NULL; 3090 ch->sid = ++sc->streamcnt; 3091 ch->dir = dir; 3092 ch->b = b; 3093 ch->c = c; 3094 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3095 ch->blkcnt = pdevinfo->chan_blkcnt; 3096 hdac_unlock(sc); 3097 3098 if (hdac_bdl_alloc(ch) != 0) { 3099 ch->blkcnt = 0; 3100 return (NULL); 3101 } 3102 3103 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3104 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3105 pdevinfo->chan_size) != 0) 3106 return (NULL); 3107 3108 return (ch); 3109} 3110 3111static int 3112hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3113{ 3114 struct hdac_chan *ch = data; 3115 int i; 3116 3117 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3118 if (format == ch->caps.fmtlist[i]) { 3119 ch->fmt = format; 3120 return (0); 3121 } 3122 } 3123 3124 return (EINVAL); 3125} 3126 3127static int 3128hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3129{ 3130 struct hdac_chan *ch = data; 3131 uint32_t spd = 0, threshold; 3132 int i; 3133 3134 for (i = 0; ch->pcmrates[i] != 0; i++) { 3135 spd = ch->pcmrates[i]; 3136 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3137 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3138 if (speed < threshold) 3139 break; 3140 } 3141 3142 if (spd == 0) /* impossible */ 3143 ch->spd = 48000; 3144 else 3145 ch->spd = spd; 3146 3147 return (ch->spd); 3148} 3149 3150static void 3151hdac_stream_setup(struct hdac_chan *ch) 3152{ 3153 struct hdac_softc *sc = ch->devinfo->codec->sc; 3154 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3155 struct hdac_widget *w; 3156 int i, chn, totalchn, c; 3157 nid_t cad = ch->devinfo->codec->cad; 3158 uint16_t fmt, dfmt; 3159 3160 HDA_BOOTHVERBOSE( 3161 device_printf(ch->pdevinfo->dev, 3162 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3163 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3164 ch->fmt, ch->spd); 3165 ); 3166 fmt = 0; 3167 if (ch->fmt & AFMT_S16_LE) 3168 fmt |= ch->bit16 << 4; 3169 else if (ch->fmt & AFMT_S32_LE) 3170 fmt |= ch->bit32 << 4; 3171 else 3172 fmt |= 1 << 4; 3173 3174 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3175 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3176 fmt |= hda_rate_tab[i].base; 3177 fmt |= hda_rate_tab[i].mul; 3178 fmt |= hda_rate_tab[i].div; 3179 break; 3180 } 3181 } 3182 3183 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3184 fmt |= 1; 3185 totalchn = 2; 3186 } else 3187 totalchn = 1; 3188 3189 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3190 3191 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3192 if (ch->fmt & AFMT_AC3) 3193 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3194 3195 chn = 0; 3196 for (i = 0; ch->io[i] != -1; i++) { 3197 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3198 if (w == NULL) 3199 continue; 3200 3201 if (as->hpredir >= 0 && i == as->pincnt) 3202 chn = 0; 3203 HDA_BOOTHVERBOSE( 3204 device_printf(ch->pdevinfo->dev, 3205 "PCMDIR_%s: Stream setup nid=%d: " 3206 "fmt=0x%04x, dfmt=0x%04x\n", 3207 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3208 ch->io[i], fmt, dfmt); 3209 ); 3210 hdac_command(sc, 3211 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3212 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3213 hdac_command(sc, 3214 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3215 cad); 3216 } 3217 /* If HP redirection is enabled, but failed to use same 3218 DAC make last DAC one to duplicate first one. */ 3219 if (as->hpredir >= 0 && i == as->pincnt) { 3220 c = (ch->sid << 4); 3221 } else if (chn >= totalchn) { 3222 /* This is until OSS will support multichannel. 3223 Should be: c = 0; to disable unused DAC */ 3224 c = (ch->sid << 4); 3225 }else { 3226 c = (ch->sid << 4) | chn; 3227 } 3228 hdac_command(sc, 3229 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3230 chn += 3231 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3232 2 : 1; 3233 } 3234} 3235 3236static int 3237hdac_channel_setfragments(kobj_t obj, void *data, 3238 uint32_t blksz, uint32_t blkcnt) 3239{ 3240 struct hdac_chan *ch = data; 3241 struct hdac_softc *sc = ch->devinfo->codec->sc; 3242 3243 blksz &= HDA_BLK_ALIGN; 3244 3245 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3246 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3247 if (blksz < HDA_BLK_MIN) 3248 blksz = HDA_BLK_MIN; 3249 if (blkcnt > HDA_BDL_MAX) 3250 blkcnt = HDA_BDL_MAX; 3251 if (blkcnt < HDA_BDL_MIN) 3252 blkcnt = HDA_BDL_MIN; 3253 3254 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3255 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3256 blkcnt >>= 1; 3257 else if ((blksz >> 1) >= HDA_BLK_MIN) 3258 blksz >>= 1; 3259 else 3260 break; 3261 } 3262 3263 if ((sndbuf_getblksz(ch->b) != blksz || 3264 sndbuf_getblkcnt(ch->b) != blkcnt) && 3265 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3266 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3267 __func__, blksz, blkcnt); 3268 3269 ch->blksz = sndbuf_getblksz(ch->b); 3270 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3271 3272 return (1); 3273} 3274 3275static int 3276hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3277{ 3278 struct hdac_chan *ch = data; 3279 3280 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3281 3282 return (ch->blksz); 3283} 3284 3285static void 3286hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3287{ 3288 struct hdac_devinfo *devinfo = ch->devinfo; 3289 struct hdac_widget *w; 3290 nid_t cad = devinfo->codec->cad; 3291 int i; 3292 3293 hdac_stream_stop(ch); 3294 3295 for (i = 0; ch->io[i] != -1; i++) { 3296 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3297 if (w == NULL) 3298 continue; 3299 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3300 hdac_command(sc, 3301 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3302 cad); 3303 } 3304 hdac_command(sc, 3305 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3306 0), cad); 3307 } 3308} 3309 3310static void 3311hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3312{ 3313 ch->ptr = 0; 3314 ch->prevptr = 0; 3315 hdac_stream_stop(ch); 3316 hdac_stream_reset(ch); 3317 hdac_bdl_setup(ch); 3318 hdac_stream_setid(ch); 3319 hdac_stream_setup(ch); 3320 hdac_stream_start(ch); 3321} 3322 3323static int 3324hdac_channel_trigger(kobj_t obj, void *data, int go) 3325{ 3326 struct hdac_chan *ch = data; 3327 struct hdac_softc *sc = ch->devinfo->codec->sc; 3328 3329 if (!PCMTRIG_COMMON(go)) 3330 return (0); 3331 3332 hdac_lock(sc); 3333 switch (go) { 3334 case PCMTRIG_START: 3335 hdac_channel_start(sc, ch); 3336 break; 3337 case PCMTRIG_STOP: 3338 case PCMTRIG_ABORT: 3339 hdac_channel_stop(sc, ch); 3340 break; 3341 default: 3342 break; 3343 } 3344 hdac_unlock(sc); 3345 3346 return (0); 3347} 3348 3349static int 3350hdac_channel_getptr(kobj_t obj, void *data) 3351{ 3352 struct hdac_chan *ch = data; 3353 struct hdac_softc *sc = ch->devinfo->codec->sc; 3354 uint32_t ptr; 3355 3356 hdac_lock(sc); 3357 if (sc->polling != 0) 3358 ptr = ch->ptr; 3359 else if (ch->dmapos != NULL) 3360 ptr = *(ch->dmapos); 3361 else 3362 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3363 hdac_unlock(sc); 3364 3365 /* 3366 * Round to available space and force 128 bytes aligment. 3367 */ 3368 ptr %= ch->blksz * ch->blkcnt; 3369 ptr &= HDA_BLK_ALIGN; 3370 3371 return (ptr); 3372} 3373 3374static struct pcmchan_caps * 3375hdac_channel_getcaps(kobj_t obj, void *data) 3376{ 3377 return (&((struct hdac_chan *)data)->caps); 3378} 3379 3380static kobj_method_t hdac_channel_methods[] = { 3381 KOBJMETHOD(channel_init, hdac_channel_init), 3382 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3383 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3384 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3385 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3386 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3387 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3388 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3389 { 0, 0 } 3390}; 3391CHANNEL_DECLARE(hdac_channel); 3392 3393static int 3394hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3395{ 3396 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3397 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3398 struct hdac_softc *sc = devinfo->codec->sc; 3399 struct hdac_widget *w, *cw; 3400 struct hdac_audio_ctl *ctl; 3401 uint32_t mask, recmask, id; 3402 int i, j, softpcmvol; 3403 3404 hdac_lock(sc); 3405 3406 /* Make sure that in case of soft volume it won't stay muted. */ 3407 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3408 pdevinfo->left[i] = 100; 3409 pdevinfo->right[i] = 100; 3410 } 3411 3412 mask = 0; 3413 recmask = 0; 3414 id = hdac_codec_id(devinfo->codec); 3415 3416 /* Declate EAPD as ogain control. */ 3417 if (pdevinfo->play >= 0) { 3418 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3419 w = hdac_widget_get(devinfo, i); 3420 if (w == NULL || w->enable == 0) 3421 continue; 3422 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3423 w->param.eapdbtl == HDAC_INVALID || 3424 w->bindas != sc->chans[pdevinfo->play].as) 3425 continue; 3426 mask |= SOUND_MASK_OGAIN; 3427 break; 3428 } 3429 } 3430 3431 /* Declare volume controls assigned to this association. */ 3432 i = 0; 3433 ctl = NULL; 3434 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3435 if (ctl->enable == 0) 3436 continue; 3437 if ((pdevinfo->play >= 0 && 3438 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3439 (pdevinfo->rec >= 0 && 3440 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3441 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3442 mask |= ctl->ossmask; 3443 } 3444 3445 /* Declare record sources available to this association. */ 3446 if (pdevinfo->rec >= 0) { 3447 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3448 for (i = 0; ch->io[i] != -1; i++) { 3449 w = hdac_widget_get(devinfo, ch->io[i]); 3450 if (w == NULL || w->enable == 0) 3451 continue; 3452 for (j = 0; j < w->nconns; j++) { 3453 if (w->connsenable[j] == 0) 3454 continue; 3455 cw = hdac_widget_get(devinfo, w->conns[j]); 3456 if (cw == NULL || cw->enable == 0) 3457 continue; 3458 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3459 cw->bindas != -2) 3460 continue; 3461 recmask |= cw->ossmask; 3462 } 3463 } 3464 } 3465 3466 /* Declare soft PCM and master volume if needed. */ 3467 if (pdevinfo->play >= 0) { 3468 ctl = NULL; 3469 if ((mask & SOUND_MASK_PCM) == 0 || 3470 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3471 softpcmvol = 1; 3472 mask |= SOUND_MASK_PCM; 3473 } else { 3474 softpcmvol = 0; 3475 i = 0; 3476 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3477 if (ctl->enable == 0) 3478 continue; 3479 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3480 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3481 continue; 3482 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3483 continue; 3484 if (ctl->step > 0) 3485 break; 3486 } 3487 } 3488 3489 if (softpcmvol == 1 || ctl == NULL) { 3490 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3491 HDA_BOOTVERBOSE( 3492 device_printf(pdevinfo->dev, 3493 "%s Soft PCM volume\n", 3494 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3495 ); 3496 } 3497 3498 if ((mask & SOUND_MASK_VOLUME) == 0) { 3499 mask |= SOUND_MASK_VOLUME; 3500 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3501 SOUND_MASK_PCM); 3502 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3503 SOUND_MIXER_NONE); 3504 HDA_BOOTVERBOSE( 3505 device_printf(pdevinfo->dev, 3506 "Forcing master volume with PCM\n"); 3507 ); 3508 } 3509 } 3510 3511 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3512 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3513 3514 mix_setrecdevs(m, recmask); 3515 mix_setdevs(m, mask); 3516 3517 hdac_unlock(sc); 3518 3519 return (0); 3520} 3521 3522static int 3523hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3524 unsigned left, unsigned right) 3525{ 3526 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3527 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3528 struct hdac_softc *sc = devinfo->codec->sc; 3529 struct hdac_widget *w; 3530 struct hdac_audio_ctl *ctl; 3531 uint32_t mute; 3532 int lvol, rvol; 3533 int i, j; 3534 3535 hdac_lock(sc); 3536 /* Save new values. */ 3537 pdevinfo->left[dev] = left; 3538 pdevinfo->right[dev] = right; 3539 3540 /* 'ogain' is the special case implemented with EAPD. */ 3541 if (dev == SOUND_MIXER_OGAIN) { 3542 uint32_t orig; 3543 w = NULL; 3544 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3545 w = hdac_widget_get(devinfo, i); 3546 if (w == NULL || w->enable == 0) 3547 continue; 3548 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3549 w->param.eapdbtl == HDAC_INVALID) 3550 continue; 3551 break; 3552 } 3553 if (i >= devinfo->endnode) { 3554 hdac_unlock(sc); 3555 return (-1); 3556 } 3557 orig = w->param.eapdbtl; 3558 if (left == 0) 3559 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3560 else 3561 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3562 if (orig != w->param.eapdbtl) { 3563 uint32_t val; 3564 3565 val = w->param.eapdbtl; 3566 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3567 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3568 hdac_command(sc, 3569 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3570 w->nid, val), devinfo->codec->cad); 3571 } 3572 hdac_unlock(sc); 3573 return (left | (left << 8)); 3574 } 3575 3576 /* Recalculate all controls related to this OSS device. */ 3577 i = 0; 3578 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3579 if (ctl->enable == 0 || 3580 !(ctl->ossmask & (1 << dev))) 3581 continue; 3582 if (!((pdevinfo->play >= 0 && 3583 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3584 (pdevinfo->rec >= 0 && 3585 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3586 ctl->widget->bindas == -2)) 3587 continue; 3588 3589 lvol = 100; 3590 rvol = 100; 3591 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3592 if (ctl->ossmask & (1 << j)) { 3593 lvol = lvol * pdevinfo->left[j] / 100; 3594 rvol = rvol * pdevinfo->right[j] / 100; 3595 } 3596 } 3597 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3598 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3599 lvol = (lvol * ctl->step + 50) / 100; 3600 rvol = (rvol * ctl->step + 50) / 100; 3601 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3602 } 3603 hdac_unlock(sc); 3604 3605 return (left | (right << 8)); 3606} 3607 3608/* 3609 * Commutate specified record source. 3610 */ 3611static uint32_t 3612hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3613{ 3614 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3615 struct hdac_widget *w, *cw; 3616 struct hdac_audio_ctl *ctl; 3617 char buf[64]; 3618 int i, muted; 3619 uint32_t res = 0; 3620 3621 if (depth > HDA_PARSE_MAXDEPTH) 3622 return (0); 3623 3624 w = hdac_widget_get(devinfo, nid); 3625 if (w == NULL || w->enable == 0) 3626 return (0); 3627 3628 for (i = 0; i < w->nconns; i++) { 3629 if (w->connsenable[i] == 0) 3630 continue; 3631 cw = hdac_widget_get(devinfo, w->conns[i]); 3632 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3633 continue; 3634 /* Call recursively to trace signal to it's source if needed. */ 3635 if ((src & cw->ossmask) != 0) { 3636 if (cw->ossdev < 0) { 3637 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3638 w->conns[i], depth + 1); 3639 } else { 3640 res |= cw->ossmask; 3641 } 3642 } 3643 /* We have two special cases: mixers and others (selectors). */ 3644 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3645 ctl = hdac_audio_ctl_amp_get(devinfo, 3646 w->nid, HDA_CTL_IN, i, 1); 3647 if (ctl == NULL) 3648 continue; 3649 /* If we have input control on this node mute them 3650 * according to requested sources. */ 3651 muted = (src & cw->ossmask) ? 0 : 1; 3652 if (muted != ctl->forcemute) { 3653 ctl->forcemute = muted; 3654 hdac_audio_ctl_amp_set(ctl, 3655 HDA_AMP_MUTE_DEFAULT, 3656 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3657 } 3658 HDA_BOOTHVERBOSE( 3659 device_printf(pdevinfo->dev, 3660 "Recsel (%s): nid %d source %d %s\n", 3661 hdac_audio_ctl_ossmixer_mask2allname( 3662 src, buf, sizeof(buf)), 3663 nid, i, muted?"mute":"unmute"); 3664 ); 3665 } else { 3666 if (w->nconns == 1) 3667 break; 3668 if ((src & cw->ossmask) == 0) 3669 continue; 3670 /* If we found requested source - select it and exit. */ 3671 hdac_widget_connection_select(w, i); 3672 HDA_BOOTHVERBOSE( 3673 device_printf(pdevinfo->dev, 3674 "Recsel (%s): nid %d source %d select\n", 3675 hdac_audio_ctl_ossmixer_mask2allname( 3676 src, buf, sizeof(buf)), 3677 nid, i); 3678 ); 3679 break; 3680 } 3681 } 3682 return (res); 3683} 3684 3685static uint32_t 3686hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3687{ 3688 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3689 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3690 struct hdac_widget *w; 3691 struct hdac_softc *sc = devinfo->codec->sc; 3692 struct hdac_chan *ch; 3693 int i; 3694 uint32_t ret = 0xffffffff; 3695 3696 hdac_lock(sc); 3697 3698 /* Commutate requested recsrc for each ADC. */ 3699 ch = &sc->chans[pdevinfo->rec]; 3700 for (i = 0; ch->io[i] != -1; i++) { 3701 w = hdac_widget_get(devinfo, ch->io[i]); 3702 if (w == NULL || w->enable == 0) 3703 continue; 3704 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3705 } 3706 3707 hdac_unlock(sc); 3708 3709 return ((ret == 0xffffffff)? 0 : ret); 3710} 3711 3712static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3713 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3714 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3715 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3716 { 0, 0 } 3717}; 3718MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3719 3720static void 3721hdac_unsolq_task(void *context, int pending) 3722{ 3723 struct hdac_softc *sc; 3724 3725 sc = (struct hdac_softc *)context; 3726 3727 hdac_lock(sc); 3728 hdac_unsolq_flush(sc); 3729 hdac_unlock(sc); 3730} 3731 3732/**************************************************************************** 3733 * int hdac_attach(device_t) 3734 * 3735 * Attach the device into the kernel. Interrupts usually won't be enabled 3736 * when this function is called. Setup everything that doesn't require 3737 * interrupts and defer probing of codecs until interrupts are enabled. 3738 ****************************************************************************/ 3739static int 3740hdac_attach(device_t dev) 3741{ 3742 struct hdac_softc *sc; 3743 int result; 3744 int i; 3745 uint16_t vendor; 3746 uint8_t v; 3747 3748 device_printf(dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 3749 3750 sc = device_get_softc(dev); 3751 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3752 sc->dev = dev; 3753 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3754 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3755 vendor = pci_get_vendor(dev); 3756 3757 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3758 /* Screw nx6325 - subdevice/subvendor swapped */ 3759 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3760 } 3761 3762 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3763 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3764 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3765 3766 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3767 3768 sc->poll_ticks = 1000000; 3769 sc->poll_ival = HDAC_POLL_INTERVAL; 3770 if (resource_int_value(device_get_name(dev), 3771 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3772 sc->polling = 1; 3773 else 3774 sc->polling = 0; 3775 3776 result = bus_dma_tag_create(NULL, /* parent */ 3777 HDAC_DMA_ALIGNMENT, /* alignment */ 3778 0, /* boundary */ 3779 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3780 BUS_SPACE_MAXADDR, /* highaddr */ 3781 NULL, /* filtfunc */ 3782 NULL, /* fistfuncarg */ 3783 HDA_BUFSZ_MAX, /* maxsize */ 3784 1, /* nsegments */ 3785 HDA_BUFSZ_MAX, /* maxsegsz */ 3786 0, /* flags */ 3787 NULL, /* lockfunc */ 3788 NULL, /* lockfuncarg */ 3789 &sc->chan_dmat); /* dmat */ 3790 if (result != 0) { 3791 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3792 __func__, result); 3793 snd_mtxfree(sc->lock); 3794 free(sc, M_DEVBUF); 3795 return (ENXIO); 3796 } 3797 3798 3799 sc->hdabus = NULL; 3800 for (i = 0; i < HDAC_CODEC_MAX; i++) 3801 sc->codecs[i] = NULL; 3802 3803 pci_enable_busmaster(dev); 3804 3805 if (vendor == INTEL_VENDORID) { 3806 /* TCSEL -> TC0 */ 3807 v = pci_read_config(dev, 0x44, 1); 3808 pci_write_config(dev, 0x44, v & 0xf8, 1); 3809 HDA_BOOTHVERBOSE( 3810 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3811 pci_read_config(dev, 0x44, 1)); 3812 ); 3813 } 3814 3815#ifdef HDAC_MSI_ENABLED 3816 if (resource_int_value(device_get_name(dev), 3817 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3818 pci_msi_count(dev) == 1) 3819 sc->flags |= HDAC_F_MSI; 3820 else 3821#endif 3822 sc->flags &= ~HDAC_F_MSI; 3823 3824#if defined(__i386__) || defined(__amd64__) 3825 sc->flags |= HDAC_F_DMA_NOCACHE; 3826 3827 if (resource_int_value(device_get_name(dev), 3828 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3829#else 3830 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3831#endif 3832 /* 3833 * Try to enable PCIe snoop to avoid messing around with 3834 * uncacheable DMA attribute. Since PCIe snoop register 3835 * config is pretty much vendor specific, there are no 3836 * general solutions on how to enable it, forcing us (even 3837 * Microsoft) to enable uncacheable or write combined DMA 3838 * by default. 3839 * 3840 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3841 */ 3842 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3843 if (hdac_pcie_snoop[i].vendor != vendor) 3844 continue; 3845 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3846 if (hdac_pcie_snoop[i].reg == 0x00) 3847 break; 3848 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3849 if ((v & hdac_pcie_snoop[i].enable) == 3850 hdac_pcie_snoop[i].enable) 3851 break; 3852 v &= hdac_pcie_snoop[i].mask; 3853 v |= hdac_pcie_snoop[i].enable; 3854 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3855 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3856 if ((v & hdac_pcie_snoop[i].enable) != 3857 hdac_pcie_snoop[i].enable) { 3858 HDA_BOOTVERBOSE( 3859 device_printf(dev, 3860 "WARNING: Failed to enable PCIe " 3861 "snoop!\n"); 3862 ); 3863#if defined(__i386__) || defined(__amd64__) 3864 sc->flags |= HDAC_F_DMA_NOCACHE; 3865#endif 3866 } 3867 break; 3868 } 3869#if defined(__i386__) || defined(__amd64__) 3870 } 3871#endif 3872 3873 HDA_BOOTHVERBOSE( 3874 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3875 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3876 "Uncacheable" : "PCIe snoop", vendor); 3877 ); 3878 3879 /* Allocate resources */ 3880 result = hdac_mem_alloc(sc); 3881 if (result != 0) 3882 goto hdac_attach_fail; 3883 result = hdac_irq_alloc(sc); 3884 if (result != 0) 3885 goto hdac_attach_fail; 3886 3887 /* Get Capabilities */ 3888 result = hdac_get_capabilities(sc); 3889 if (result != 0) 3890 goto hdac_attach_fail; 3891 3892 /* Allocate CORB and RIRB dma memory */ 3893 result = hdac_dma_alloc(sc, &sc->corb_dma, 3894 sc->corb_size * sizeof(uint32_t)); 3895 if (result != 0) 3896 goto hdac_attach_fail; 3897 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3898 sc->rirb_size * sizeof(struct hdac_rirb)); 3899 if (result != 0) 3900 goto hdac_attach_fail; 3901 3902 /* Quiesce everything */ 3903 HDA_BOOTHVERBOSE( 3904 device_printf(dev, "Reset controller...\n"); 3905 ); 3906 hdac_reset(sc, 1); 3907 3908 /* Initialize the CORB and RIRB */ 3909 hdac_corb_init(sc); 3910 hdac_rirb_init(sc); 3911 3912 /* Defer remaining of initialization until interrupts are enabled */ 3913 sc->intrhook.ich_func = hdac_attach2; 3914 sc->intrhook.ich_arg = (void *)sc; 3915 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3916 sc->intrhook.ich_func = NULL; 3917 hdac_attach2((void *)sc); 3918 } 3919 3920 return (0); 3921 3922hdac_attach_fail: 3923 hdac_irq_free(sc); 3924 hdac_dma_free(sc, &sc->rirb_dma); 3925 hdac_dma_free(sc, &sc->corb_dma); 3926 hdac_mem_free(sc); 3927 snd_mtxfree(sc->lock); 3928 free(sc, M_DEVBUF); 3929 3930 return (ENXIO); 3931} 3932 3933static void 3934hdac_audio_parse(struct hdac_devinfo *devinfo) 3935{ 3936 struct hdac_codec *codec = devinfo->codec; 3937 struct hdac_softc *sc = codec->sc; 3938 struct hdac_widget *w; 3939 uint32_t res; 3940 int i; 3941 nid_t cad, nid; 3942 3943 cad = devinfo->codec->cad; 3944 nid = devinfo->nid; 3945 3946 res = hdac_command(sc, 3947 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3948 devinfo->function.audio.gpio = res; 3949 3950 HDA_BOOTVERBOSE( 3951 device_printf(sc->dev, "GPIO: 0x%08x " 3952 "NumGPIO=%d NumGPO=%d " 3953 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3954 devinfo->function.audio.gpio, 3955 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3956 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3957 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3958 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3959 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3960 ); 3961 3962 res = hdac_command(sc, 3963 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3964 cad); 3965 devinfo->function.audio.supp_stream_formats = res; 3966 3967 res = hdac_command(sc, 3968 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3969 cad); 3970 devinfo->function.audio.supp_pcm_size_rate = res; 3971 3972 res = hdac_command(sc, 3973 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3974 cad); 3975 devinfo->function.audio.outamp_cap = res; 3976 3977 res = hdac_command(sc, 3978 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3979 cad); 3980 devinfo->function.audio.inamp_cap = res; 3981 3982 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3983 w = hdac_widget_get(devinfo, i); 3984 if (w == NULL) 3985 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3986 else { 3987 w->devinfo = devinfo; 3988 w->nid = i; 3989 w->enable = 1; 3990 w->selconn = -1; 3991 w->pflags = 0; 3992 w->ossdev = -1; 3993 w->bindas = -1; 3994 w->param.eapdbtl = HDAC_INVALID; 3995 hdac_widget_parse(w); 3996 } 3997 } 3998} 3999 4000static void 4001hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4002{ 4003 struct hdac_softc *sc = devinfo->codec->sc; 4004 struct hdac_audio_ctl *ctls; 4005 struct hdac_widget *w, *cw; 4006 int i, j, cnt, max, ocap, icap; 4007 int mute, offset, step, size; 4008 4009 /* XXX This is redundant */ 4010 max = 0; 4011 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4012 w = hdac_widget_get(devinfo, i); 4013 if (w == NULL || w->enable == 0) 4014 continue; 4015 if (w->param.outamp_cap != 0) 4016 max++; 4017 if (w->param.inamp_cap != 0) { 4018 switch (w->type) { 4019 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4020 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4021 for (j = 0; j < w->nconns; j++) { 4022 cw = hdac_widget_get(devinfo, 4023 w->conns[j]); 4024 if (cw == NULL || cw->enable == 0) 4025 continue; 4026 max++; 4027 } 4028 break; 4029 default: 4030 max++; 4031 break; 4032 } 4033 } 4034 } 4035 4036 devinfo->function.audio.ctlcnt = max; 4037 4038 if (max < 1) 4039 return; 4040 4041 ctls = (struct hdac_audio_ctl *)malloc( 4042 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4043 4044 if (ctls == NULL) { 4045 /* Blekh! */ 4046 device_printf(sc->dev, "unable to allocate ctls!\n"); 4047 devinfo->function.audio.ctlcnt = 0; 4048 return; 4049 } 4050 4051 cnt = 0; 4052 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4053 if (cnt >= max) { 4054 device_printf(sc->dev, "%s: Ctl overflow!\n", 4055 __func__); 4056 break; 4057 } 4058 w = hdac_widget_get(devinfo, i); 4059 if (w == NULL || w->enable == 0) 4060 continue; 4061 ocap = w->param.outamp_cap; 4062 icap = w->param.inamp_cap; 4063 if (ocap != 0) { 4064 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4065 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4066 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4067 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4068 /*if (offset > step) { 4069 HDA_BOOTVERBOSE( 4070 device_printf(sc->dev, 4071 "BUGGY outamp: nid=%d " 4072 "[offset=%d > step=%d]\n", 4073 w->nid, offset, step); 4074 ); 4075 offset = step; 4076 }*/ 4077 ctls[cnt].enable = 1; 4078 ctls[cnt].widget = w; 4079 ctls[cnt].mute = mute; 4080 ctls[cnt].step = step; 4081 ctls[cnt].size = size; 4082 ctls[cnt].offset = offset; 4083 ctls[cnt].left = offset; 4084 ctls[cnt].right = offset; 4085 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4086 w->waspin) 4087 ctls[cnt].ndir = HDA_CTL_IN; 4088 else 4089 ctls[cnt].ndir = HDA_CTL_OUT; 4090 ctls[cnt++].dir = HDA_CTL_OUT; 4091 } 4092 4093 if (icap != 0) { 4094 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4095 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4096 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4097 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4098 /*if (offset > step) { 4099 HDA_BOOTVERBOSE( 4100 device_printf(sc->dev, 4101 "BUGGY inamp: nid=%d " 4102 "[offset=%d > step=%d]\n", 4103 w->nid, offset, step); 4104 ); 4105 offset = step; 4106 }*/ 4107 switch (w->type) { 4108 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4109 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4110 for (j = 0; j < w->nconns; j++) { 4111 if (cnt >= max) { 4112 device_printf(sc->dev, 4113 "%s: Ctl overflow!\n", 4114 __func__); 4115 break; 4116 } 4117 cw = hdac_widget_get(devinfo, 4118 w->conns[j]); 4119 if (cw == NULL || cw->enable == 0) 4120 continue; 4121 ctls[cnt].enable = 1; 4122 ctls[cnt].widget = w; 4123 ctls[cnt].childwidget = cw; 4124 ctls[cnt].index = j; 4125 ctls[cnt].mute = mute; 4126 ctls[cnt].step = step; 4127 ctls[cnt].size = size; 4128 ctls[cnt].offset = offset; 4129 ctls[cnt].left = offset; 4130 ctls[cnt].right = offset; 4131 ctls[cnt].ndir = HDA_CTL_IN; 4132 ctls[cnt++].dir = HDA_CTL_IN; 4133 } 4134 break; 4135 default: 4136 if (cnt >= max) { 4137 device_printf(sc->dev, 4138 "%s: Ctl overflow!\n", 4139 __func__); 4140 break; 4141 } 4142 ctls[cnt].enable = 1; 4143 ctls[cnt].widget = w; 4144 ctls[cnt].mute = mute; 4145 ctls[cnt].step = step; 4146 ctls[cnt].size = size; 4147 ctls[cnt].offset = offset; 4148 ctls[cnt].left = offset; 4149 ctls[cnt].right = offset; 4150 if (w->type == 4151 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4152 ctls[cnt].ndir = HDA_CTL_OUT; 4153 else 4154 ctls[cnt].ndir = HDA_CTL_IN; 4155 ctls[cnt++].dir = HDA_CTL_IN; 4156 break; 4157 } 4158 } 4159 } 4160 4161 devinfo->function.audio.ctl = ctls; 4162} 4163 4164static void 4165hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4166{ 4167 struct hdac_softc *sc = devinfo->codec->sc; 4168 struct hdac_audio_as *as; 4169 struct hdac_widget *w; 4170 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4171 4172 /* XXX This is redundant */ 4173 max = 0; 4174 for (j = 0; j < 16; j++) { 4175 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4176 w = hdac_widget_get(devinfo, i); 4177 if (w == NULL || w->enable == 0) 4178 continue; 4179 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4180 continue; 4181 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4182 != j) 4183 continue; 4184 max++; 4185 if (j != 15) /* There could be many 1-pin assocs #15 */ 4186 break; 4187 } 4188 } 4189 4190 devinfo->function.audio.ascnt = max; 4191 4192 if (max < 1) 4193 return; 4194 4195 as = (struct hdac_audio_as *)malloc( 4196 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4197 4198 if (as == NULL) { 4199 /* Blekh! */ 4200 device_printf(sc->dev, "unable to allocate assocs!\n"); 4201 devinfo->function.audio.ascnt = 0; 4202 return; 4203 } 4204 4205 for (i = 0; i < max; i++) { 4206 as[i].hpredir = -1; 4207 as[i].chan = -1; 4208 } 4209 4210 /* Scan associations skipping as=0. */ 4211 cnt = 0; 4212 for (j = 1; j < 16; j++) { 4213 first = 16; 4214 hpredir = 0; 4215 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4216 w = hdac_widget_get(devinfo, i); 4217 if (w == NULL || w->enable == 0) 4218 continue; 4219 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4220 continue; 4221 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4222 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4223 if (assoc != j) { 4224 continue; 4225 } 4226 KASSERT(cnt < max, 4227 ("%s: Associations owerflow (%d of %d)", 4228 __func__, cnt, max)); 4229 type = w->wclass.pin.config & 4230 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4231 /* Get pin direction. */ 4232 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4233 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4234 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4235 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4236 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4237 dir = HDA_CTL_OUT; 4238 else 4239 dir = HDA_CTL_IN; 4240 /* If this is a first pin - create new association. */ 4241 if (as[cnt].pincnt == 0) { 4242 as[cnt].enable = 1; 4243 as[cnt].index = j; 4244 as[cnt].dir = dir; 4245 } 4246 if (seq < first) 4247 first = seq; 4248 /* Check association correctness. */ 4249 if (as[cnt].pins[seq] != 0) { 4250 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4251 "in association %d! Disabling association.\n", 4252 __func__, seq, w->nid, j); 4253 as[cnt].enable = 0; 4254 } 4255 if (dir != as[cnt].dir) { 4256 device_printf(sc->dev, "%s: Pin %d has wrong " 4257 "direction for association %d! Disabling " 4258 "association.\n", 4259 __func__, w->nid, j); 4260 as[cnt].enable = 0; 4261 } 4262 /* Headphones with seq=15 may mean redirection. */ 4263 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4264 seq == 15) 4265 hpredir = 1; 4266 as[cnt].pins[seq] = w->nid; 4267 as[cnt].pincnt++; 4268 /* Association 15 is a multiple unassociated pins. */ 4269 if (j == 15) 4270 cnt++; 4271 } 4272 if (j != 15 && as[cnt].pincnt > 0) { 4273 if (hpredir && as[cnt].pincnt > 1) 4274 as[cnt].hpredir = first; 4275 cnt++; 4276 } 4277 } 4278 HDA_BOOTVERBOSE( 4279 device_printf(sc->dev, 4280 "%d associations found:\n", max); 4281 for (i = 0; i < max; i++) { 4282 device_printf(sc->dev, 4283 "Association %d (%d) %s%s:\n", 4284 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4285 as[i].enable?"":" (disabled)"); 4286 for (j = 0; j < 16; j++) { 4287 if (as[i].pins[j] == 0) 4288 continue; 4289 device_printf(sc->dev, 4290 " Pin nid=%d seq=%d\n", 4291 as[i].pins[j], j); 4292 } 4293 } 4294 ); 4295 4296 devinfo->function.audio.as = as; 4297} 4298 4299static const struct { 4300 uint32_t model; 4301 uint32_t id; 4302 uint32_t set, unset; 4303} hdac_quirks[] = { 4304 /* 4305 * XXX Force stereo quirk. Monoural recording / playback 4306 * on few codecs (especially ALC880) seems broken or 4307 * perhaps unsupported. 4308 */ 4309 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4310 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4311 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4312 HDA_QUIRK_GPIO0, 0 }, 4313 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4314 HDA_QUIRK_GPIO0, 0 }, 4315 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4316 HDA_QUIRK_GPIO0, 0 }, 4317 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4318 HDA_QUIRK_GPIO0, 0 }, 4319 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4320 HDA_QUIRK_GPIO0, 0 }, 4321 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4322 HDA_QUIRK_GPIO0, 0 }, 4323 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4324 HDA_QUIRK_EAPDINV, 0 }, 4325 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4326 HDA_QUIRK_EAPDINV, 0 }, 4327 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4328 HDA_QUIRK_OVREF, 0 }, 4329 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4330 HDA_QUIRK_OVREF, 0 }, 4331 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4332 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4333 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4334 HDA_QUIRK_GPIO1, 0 }, 4335 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4336 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4337 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4338 HDA_QUIRK_EAPDINV, 0 }, 4339 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4340 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4341 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4342 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4343 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205, 4344 HDA_QUIRK_GPIO0, 0 }, 4345 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205, 4346 HDA_QUIRK_GPIO0, 0 }, 4347 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4348 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4349 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4350 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4351 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4352 0, HDA_QUIRK_FORCESTEREO } 4353}; 4354#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4355 4356static void 4357hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4358{ 4359 struct hdac_widget *w; 4360 uint32_t id, subvendor; 4361 int i; 4362 4363 id = hdac_codec_id(devinfo->codec); 4364 subvendor = devinfo->codec->sc->pci_subvendor; 4365 4366 /* 4367 * Quirks 4368 */ 4369 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4370 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4371 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4372 continue; 4373 if (hdac_quirks[i].set != 0) 4374 devinfo->function.audio.quirks |= 4375 hdac_quirks[i].set; 4376 if (hdac_quirks[i].unset != 0) 4377 devinfo->function.audio.quirks &= 4378 ~(hdac_quirks[i].unset); 4379 } 4380 4381 switch (id) { 4382 case HDA_CODEC_ALC883: 4383 /* 4384 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4385 * Clear vref cap for jack connectivity. 4386 */ 4387 w = hdac_widget_get(devinfo, 24); 4388 if (w != NULL && w->enable != 0 && w->type == 4389 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4390 (w->wclass.pin.config & 4391 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4392 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4393 w->wclass.pin.cap &= ~( 4394 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4395 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4396 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4397 w = hdac_widget_get(devinfo, 25); 4398 if (w != NULL && w->enable != 0 && w->type == 4399 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4400 (w->wclass.pin.config & 4401 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4402 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4403 w->wclass.pin.cap &= ~( 4404 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4405 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4406 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4407 /* 4408 * nid: 26 = Line-in, leave it alone. 4409 */ 4410 break; 4411 case HDA_CODEC_AD1986A: 4412 if (subvendor == ASUS_A8X_SUBVENDOR) { 4413 /* 4414 * This is just plain ridiculous.. There 4415 * are several A8 series that share the same 4416 * pci id but works differently (EAPD). 4417 */ 4418 w = hdac_widget_get(devinfo, 26); 4419 if (w != NULL && w->type == 4420 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4421 (w->wclass.pin.config & 4422 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4423 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4424 devinfo->function.audio.quirks &= 4425 ~HDA_QUIRK_EAPDINV; 4426 } 4427 break; 4428 } 4429} 4430 4431/* 4432 * Trace path from DAC to pin. 4433 */ 4434static nid_t 4435hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4436 int dupseq, int min, int only, int depth) 4437{ 4438 struct hdac_widget *w; 4439 int i, im = -1; 4440 nid_t m = 0, ret; 4441 4442 if (depth > HDA_PARSE_MAXDEPTH) 4443 return (0); 4444 w = hdac_widget_get(devinfo, nid); 4445 if (w == NULL || w->enable == 0) 4446 return (0); 4447 HDA_BOOTHVERBOSE( 4448 if (!only) { 4449 device_printf(devinfo->codec->sc->dev, 4450 " %*stracing via nid %d\n", 4451 depth + 1, "", w->nid); 4452 } 4453 ); 4454 /* Use only unused widgets */ 4455 if (w->bindas >= 0 && w->bindas != as) { 4456 HDA_BOOTHVERBOSE( 4457 if (!only) { 4458 device_printf(devinfo->codec->sc->dev, 4459 " %*snid %d busy by association %d\n", 4460 depth + 1, "", w->nid, w->bindas); 4461 } 4462 ); 4463 return (0); 4464 } 4465 if (dupseq < 0) { 4466 if (w->bindseqmask != 0) { 4467 HDA_BOOTHVERBOSE( 4468 if (!only) { 4469 device_printf(devinfo->codec->sc->dev, 4470 " %*snid %d busy by seqmask %x\n", 4471 depth + 1, "", w->nid, w->bindseqmask); 4472 } 4473 ); 4474 return (0); 4475 } 4476 } else { 4477 /* If this is headphones - allow duplicate first pin. */ 4478 if (w->bindseqmask != 0 && 4479 (w->bindseqmask & (1 << dupseq)) == 0) { 4480 HDA_BOOTHVERBOSE( 4481 device_printf(devinfo->codec->sc->dev, 4482 " %*snid %d busy by seqmask %x\n", 4483 depth + 1, "", w->nid, w->bindseqmask); 4484 ); 4485 return (0); 4486 } 4487 } 4488 4489 switch (w->type) { 4490 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4491 /* Do not traverse input. AD1988 has digital monitor 4492 for which we are not ready. */ 4493 break; 4494 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4495 /* If we are tracing HP take only dac of first pin. */ 4496 if ((only == 0 || only == w->nid) && 4497 (w->nid >= min) && (dupseq < 0 || w->nid == 4498 devinfo->function.audio.as[as].dacs[dupseq])) 4499 m = w->nid; 4500 break; 4501 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4502 if (depth > 0) 4503 break; 4504 /* Fall */ 4505 default: 4506 /* Find reachable DACs with smallest nid respecting constraints. */ 4507 for (i = 0; i < w->nconns; i++) { 4508 if (w->connsenable[i] == 0) 4509 continue; 4510 if (w->selconn != -1 && w->selconn != i) 4511 continue; 4512 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4513 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4514 if (m == 0 || ret < m) { 4515 m = ret; 4516 im = i; 4517 } 4518 if (only || dupseq >= 0) 4519 break; 4520 } 4521 } 4522 if (m && only && ((w->nconns > 1 && 4523 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4524 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4525 w->selconn = im; 4526 break; 4527 } 4528 if (m && only) { 4529 w->bindas = as; 4530 w->bindseqmask |= (1 << seq); 4531 } 4532 HDA_BOOTHVERBOSE( 4533 if (!only) { 4534 device_printf(devinfo->codec->sc->dev, 4535 " %*snid %d returned %d\n", 4536 depth + 1, "", w->nid, m); 4537 } 4538 ); 4539 return (m); 4540} 4541 4542/* 4543 * Trace path from widget to ADC. 4544 */ 4545static nid_t 4546hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4547 int only, int depth) 4548{ 4549 struct hdac_widget *w, *wc; 4550 int i, j; 4551 nid_t res = 0; 4552 4553 if (depth > HDA_PARSE_MAXDEPTH) 4554 return (0); 4555 w = hdac_widget_get(devinfo, nid); 4556 if (w == NULL || w->enable == 0) 4557 return (0); 4558 HDA_BOOTHVERBOSE( 4559 device_printf(devinfo->codec->sc->dev, 4560 " %*stracing via nid %d\n", 4561 depth + 1, "", w->nid); 4562 ); 4563 /* Use only unused widgets */ 4564 if (w->bindas >= 0 && w->bindas != as) { 4565 HDA_BOOTHVERBOSE( 4566 device_printf(devinfo->codec->sc->dev, 4567 " %*snid %d busy by association %d\n", 4568 depth + 1, "", w->nid, w->bindas); 4569 ); 4570 return (0); 4571 } 4572 4573 switch (w->type) { 4574 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4575 /* If we are tracing HP take only dac of first pin. */ 4576 if (only == w->nid) 4577 res = 1; 4578 break; 4579 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4580 if (depth > 0) 4581 break; 4582 /* Fall */ 4583 default: 4584 /* Try to find reachable ADCs with specified nid. */ 4585 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4586 wc = hdac_widget_get(devinfo, j); 4587 if (wc == NULL || wc->enable == 0) 4588 continue; 4589 for (i = 0; i < wc->nconns; i++) { 4590 if (wc->connsenable[i] == 0) 4591 continue; 4592 if (wc->conns[i] != nid) 4593 continue; 4594 if (hdac_audio_trace_adc(devinfo, as, seq, 4595 j, only, depth + 1) != 0) { 4596 res = 1; 4597 if (((wc->nconns > 1 && 4598 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4599 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4600 wc->selconn == -1) 4601 wc->selconn = i; 4602 } 4603 } 4604 } 4605 break; 4606 } 4607 if (res) { 4608 w->bindas = as; 4609 w->bindseqmask |= (1 << seq); 4610 } 4611 HDA_BOOTHVERBOSE( 4612 device_printf(devinfo->codec->sc->dev, 4613 " %*snid %d returned %d\n", 4614 depth + 1, "", w->nid, res); 4615 ); 4616 return (res); 4617} 4618 4619/* 4620 * Erase trace path of the specified association. 4621 */ 4622static void 4623hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4624{ 4625 struct hdac_widget *w; 4626 int i; 4627 4628 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4629 w = hdac_widget_get(devinfo, i); 4630 if (w == NULL || w->enable == 0) 4631 continue; 4632 if (w->bindas == as) { 4633 if (seq >= 0) { 4634 w->bindseqmask &= ~(1 << seq); 4635 if (w->bindseqmask == 0) { 4636 w->bindas = -1; 4637 w->selconn = -1; 4638 } 4639 } else { 4640 w->bindas = -1; 4641 w->bindseqmask = 0; 4642 w->selconn = -1; 4643 } 4644 } 4645 } 4646} 4647 4648/* 4649 * Trace association path from DAC to output 4650 */ 4651static int 4652hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4653{ 4654 struct hdac_audio_as *ases = devinfo->function.audio.as; 4655 int i, hpredir; 4656 nid_t min, res; 4657 4658 /* Find next pin */ 4659 for (i = seq; ases[as].pins[i] == 0 && i < 16; i++) 4660 ; 4661 /* Check if there is no any left. If so - we succeded. */ 4662 if (i == 16) 4663 return (1); 4664 4665 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4666 min = 0; 4667 res = 0; 4668 do { 4669 HDA_BOOTHVERBOSE( 4670 device_printf(devinfo->codec->sc->dev, 4671 " Tracing pin %d with min nid %d", 4672 ases[as].pins[i], min); 4673 if (hpredir >= 0) 4674 printf(" and hpredir %d", hpredir); 4675 printf("\n"); 4676 ); 4677 /* Trace this pin taking min nid into account. */ 4678 res = hdac_audio_trace_dac(devinfo, as, i, 4679 ases[as].pins[i], hpredir, min, 0, 0); 4680 if (res == 0) { 4681 /* If we failed - return to previous and redo it. */ 4682 HDA_BOOTVERBOSE( 4683 device_printf(devinfo->codec->sc->dev, 4684 " Unable to trace pin %d seq %d with min " 4685 "nid %d", 4686 ases[as].pins[i], i, min); 4687 if (hpredir >= 0) 4688 printf(" and hpredir %d", hpredir); 4689 printf("\n"); 4690 ); 4691 return (0); 4692 } 4693 HDA_BOOTVERBOSE( 4694 device_printf(devinfo->codec->sc->dev, 4695 " Pin %d traced to DAC %d", 4696 ases[as].pins[i], res); 4697 if (hpredir >= 0) 4698 printf(" and hpredir %d", hpredir); 4699 if (ases[as].fakeredir) 4700 printf(" with fake redirection"); 4701 printf("\n"); 4702 ); 4703 /* Trace again to mark the path */ 4704 hdac_audio_trace_dac(devinfo, as, i, 4705 ases[as].pins[i], hpredir, min, res, 0); 4706 ases[as].dacs[i] = res; 4707 /* We succeded, so call next. */ 4708 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4709 return (1); 4710 /* If next failed, we should retry with next min */ 4711 hdac_audio_undo_trace(devinfo, as, i); 4712 ases[as].dacs[i] = 0; 4713 min = res + 1; 4714 } while (1); 4715} 4716 4717/* 4718 * Trace association path from input to ADC 4719 */ 4720static int 4721hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4722{ 4723 struct hdac_audio_as *ases = devinfo->function.audio.as; 4724 struct hdac_widget *w; 4725 int i, j, k; 4726 4727 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4728 w = hdac_widget_get(devinfo, j); 4729 if (w == NULL || w->enable == 0) 4730 continue; 4731 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4732 continue; 4733 if (w->bindas >= 0 && w->bindas != as) 4734 continue; 4735 4736 /* Find next pin */ 4737 for (i = 0; i < 16; i++) { 4738 if (ases[as].pins[i] == 0) 4739 continue; 4740 4741 HDA_BOOTHVERBOSE( 4742 device_printf(devinfo->codec->sc->dev, 4743 " Tracing pin %d to ADC %d\n", 4744 ases[as].pins[i], j); 4745 ); 4746 /* Trace this pin taking goal into account. */ 4747 if (hdac_audio_trace_adc(devinfo, as, i, 4748 ases[as].pins[i], j, 0) == 0) { 4749 /* If we failed - return to previous and redo it. */ 4750 HDA_BOOTVERBOSE( 4751 device_printf(devinfo->codec->sc->dev, 4752 " Unable to trace pin %d to ADC %d, undo traces\n", 4753 ases[as].pins[i], j); 4754 ); 4755 hdac_audio_undo_trace(devinfo, as, -1); 4756 for (k = 0; k < 16; k++) 4757 ases[as].dacs[k] = 0; 4758 break; 4759 } 4760 HDA_BOOTVERBOSE( 4761 device_printf(devinfo->codec->sc->dev, 4762 " Pin %d traced to ADC %d\n", 4763 ases[as].pins[i], j); 4764 ); 4765 ases[as].dacs[i] = j; 4766 } 4767 if (i == 16) 4768 return (1); 4769 } 4770 return (0); 4771} 4772 4773/* 4774 * Trace input monitor path from mixer to output association. 4775 */ 4776static int 4777hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4778{ 4779 struct hdac_audio_as *ases = devinfo->function.audio.as; 4780 struct hdac_widget *w, *wc; 4781 int i, j; 4782 nid_t res = 0; 4783 4784 if (depth > HDA_PARSE_MAXDEPTH) 4785 return (0); 4786 w = hdac_widget_get(devinfo, nid); 4787 if (w == NULL || w->enable == 0) 4788 return (0); 4789 HDA_BOOTHVERBOSE( 4790 device_printf(devinfo->codec->sc->dev, 4791 " %*stracing via nid %d\n", 4792 depth + 1, "", w->nid); 4793 ); 4794 /* Use only unused widgets */ 4795 if (depth > 0 && w->bindas != -1) { 4796 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4797 HDA_BOOTHVERBOSE( 4798 device_printf(devinfo->codec->sc->dev, 4799 " %*snid %d found output association %d\n", 4800 depth + 1, "", w->nid, w->bindas); 4801 ); 4802 return (1); 4803 } else { 4804 HDA_BOOTHVERBOSE( 4805 device_printf(devinfo->codec->sc->dev, 4806 " %*snid %d busy by input association %d\n", 4807 depth + 1, "", w->nid, w->bindas); 4808 ); 4809 return (0); 4810 } 4811 } 4812 4813 switch (w->type) { 4814 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4815 /* Do not traverse input. AD1988 has digital monitor 4816 for which we are not ready. */ 4817 break; 4818 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4819 if (depth > 0) 4820 break; 4821 /* Fall */ 4822 default: 4823 /* Try to find reachable ADCs with specified nid. */ 4824 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4825 wc = hdac_widget_get(devinfo, j); 4826 if (wc == NULL || wc->enable == 0) 4827 continue; 4828 for (i = 0; i < wc->nconns; i++) { 4829 if (wc->connsenable[i] == 0) 4830 continue; 4831 if (wc->conns[i] != nid) 4832 continue; 4833 if (hdac_audio_trace_to_out(devinfo, 4834 j, depth + 1) != 0) { 4835 res = 1; 4836 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4837 wc->selconn == -1) 4838 wc->selconn = i; 4839 } 4840 } 4841 } 4842 break; 4843 } 4844 if (res) 4845 w->bindas = -2; 4846 4847 HDA_BOOTHVERBOSE( 4848 device_printf(devinfo->codec->sc->dev, 4849 " %*snid %d returned %d\n", 4850 depth + 1, "", w->nid, res); 4851 ); 4852 return (res); 4853} 4854 4855/* 4856 * Trace extra associations (beeper, monitor) 4857 */ 4858static void 4859hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4860{ 4861 struct hdac_audio_as *as = devinfo->function.audio.as; 4862 struct hdac_widget *w; 4863 int j; 4864 4865 /* Input monitor */ 4866 /* Find mixer associated with input, but supplying signal 4867 for output associations. Hope it will be input monitor. */ 4868 HDA_BOOTVERBOSE( 4869 device_printf(devinfo->codec->sc->dev, 4870 "Tracing input monitor\n"); 4871 ); 4872 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4873 w = hdac_widget_get(devinfo, j); 4874 if (w == NULL || w->enable == 0) 4875 continue; 4876 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4877 continue; 4878 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 4879 continue; 4880 HDA_BOOTVERBOSE( 4881 device_printf(devinfo->codec->sc->dev, 4882 " Tracing nid %d to out\n", 4883 j); 4884 ); 4885 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 4886 HDA_BOOTVERBOSE( 4887 device_printf(devinfo->codec->sc->dev, 4888 " nid %d is input monitor\n", 4889 w->nid); 4890 ); 4891 w->pflags |= HDA_ADC_MONITOR; 4892 w->ossdev = SOUND_MIXER_IMIX; 4893 } 4894 } 4895 4896 /* Beeper */ 4897 HDA_BOOTVERBOSE( 4898 device_printf(devinfo->codec->sc->dev, 4899 "Tracing beeper\n"); 4900 ); 4901 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4902 w = hdac_widget_get(devinfo, j); 4903 if (w == NULL || w->enable == 0) 4904 continue; 4905 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 4906 continue; 4907 HDA_BOOTHVERBOSE( 4908 device_printf(devinfo->codec->sc->dev, 4909 " Tracing nid %d to out\n", 4910 j); 4911 ); 4912 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 4913 HDA_BOOTVERBOSE( 4914 device_printf(devinfo->codec->sc->dev, 4915 " nid %d traced to out\n", 4916 j); 4917 ); 4918 } 4919 w->bindas = -2; 4920 } 4921} 4922 4923/* 4924 * Bind assotiations to PCM channels 4925 */ 4926static void 4927hdac_audio_bind_as(struct hdac_devinfo *devinfo) 4928{ 4929 struct hdac_softc *sc = devinfo->codec->sc; 4930 struct hdac_audio_as *as = devinfo->function.audio.as; 4931 int j, cnt = 0, free; 4932 4933 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 4934 if (as[j].enable) 4935 cnt++; 4936 } 4937 if (sc->num_chans == 0) { 4938 sc->chans = (struct hdac_chan *)malloc( 4939 sizeof(struct hdac_chan) * cnt, 4940 M_HDAC, M_ZERO | M_NOWAIT); 4941 if (sc->chans == NULL) { 4942 device_printf(devinfo->codec->sc->dev, 4943 "Channels memory allocation failed!\n"); 4944 return; 4945 } 4946 } else { 4947 sc->chans = (struct hdac_chan *)realloc(sc->chans, 4948 sizeof(struct hdac_chan) * cnt, 4949 M_HDAC, M_ZERO | M_NOWAIT); 4950 if (sc->chans == NULL) { 4951 sc->num_chans = 0; 4952 device_printf(devinfo->codec->sc->dev, 4953 "Channels memory allocation failed!\n"); 4954 return; 4955 } 4956 } 4957 free = sc->num_chans; 4958 sc->num_chans += cnt; 4959 4960 for (j = free; j < free + cnt; j++) { 4961 devinfo->codec->sc->chans[j].devinfo = devinfo; 4962 devinfo->codec->sc->chans[j].as = -1; 4963 } 4964 4965 /* Assign associations in order of their numbers, */ 4966 free = 0; 4967 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 4968 if (as[j].enable == 0) 4969 continue; 4970 4971 as[j].chan = free; 4972 devinfo->codec->sc->chans[free].as = j; 4973 if (as[j].dir == HDA_CTL_IN) { 4974 devinfo->codec->sc->chans[free].dir = PCMDIR_REC; 4975 devinfo->function.audio.reccnt++; 4976 } else { 4977 devinfo->codec->sc->chans[free].dir = PCMDIR_PLAY; 4978 devinfo->function.audio.playcnt++; 4979 } 4980 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 4981 free++; 4982 } 4983} 4984 4985static void 4986hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 4987{ 4988 struct hdac_widget *w; 4989 int i; 4990 4991 /* Disable power and volume widgets. */ 4992 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4993 w = hdac_widget_get(devinfo, i); 4994 if (w == NULL || w->enable == 0) 4995 continue; 4996 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 4997 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 4998 w->enable = 0; 4999 HDA_BOOTHVERBOSE( 5000 device_printf(devinfo->codec->sc->dev, 5001 " Disabling nid %d due to it's" 5002 " non-audio type.\n", 5003 w->nid); 5004 ); 5005 } 5006 } 5007} 5008 5009static void 5010hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5011{ 5012 struct hdac_widget *w, *cw; 5013 struct hdac_audio_ctl *ctl; 5014 int done, found, i, j, k; 5015 5016 /* Disable useless pins. */ 5017 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5018 w = hdac_widget_get(devinfo, i); 5019 if (w == NULL || w->enable == 0) 5020 continue; 5021 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5022 (w->wclass.pin.config & 5023 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5024 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5025 w->enable = 0; 5026 HDA_BOOTHVERBOSE( 5027 device_printf(devinfo->codec->sc->dev, 5028 " Disabling pin nid %d due" 5029 " to None connectivity.\n", 5030 w->nid); 5031 ); 5032 } 5033 } 5034 do { 5035 done = 1; 5036 /* Disable and mute controls for disabled widgets. */ 5037 i = 0; 5038 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5039 if (ctl->enable == 0) 5040 continue; 5041 if (ctl->widget->enable == 0 || 5042 (ctl->childwidget != NULL && 5043 ctl->childwidget->enable == 0)) { 5044 ctl->forcemute = 1; 5045 ctl->muted = HDA_AMP_MUTE_ALL; 5046 ctl->left = 0; 5047 ctl->right = 0; 5048 ctl->enable = 0; 5049 if (ctl->ndir == HDA_CTL_IN) 5050 ctl->widget->connsenable[ctl->index] = 0; 5051 done = 0; 5052 HDA_BOOTHVERBOSE( 5053 device_printf(devinfo->codec->sc->dev, 5054 " Disabling ctl %d nid %d cnid %d due" 5055 " to disabled widget.\n", i, 5056 ctl->widget->nid, 5057 (ctl->childwidget != NULL)? 5058 ctl->childwidget->nid:-1); 5059 ); 5060 } 5061 } 5062 /* Disable useless widgets. */ 5063 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5064 w = hdac_widget_get(devinfo, i); 5065 if (w == NULL || w->enable == 0) 5066 continue; 5067 /* Disable inputs with disabled child widgets. */ 5068 for (j = 0; j < w->nconns; j++) { 5069 if (w->connsenable[j]) { 5070 cw = hdac_widget_get(devinfo, w->conns[j]); 5071 if (cw == NULL || cw->enable == 0) { 5072 w->connsenable[j] = 0; 5073 HDA_BOOTHVERBOSE( 5074 device_printf(devinfo->codec->sc->dev, 5075 " Disabling nid %d connection %d due" 5076 " to disabled child widget.\n", 5077 i, j); 5078 ); 5079 } 5080 } 5081 } 5082 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5083 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5084 continue; 5085 /* Disable mixers and selectors without inputs. */ 5086 found = 0; 5087 for (j = 0; j < w->nconns; j++) { 5088 if (w->connsenable[j]) { 5089 found = 1; 5090 break; 5091 } 5092 } 5093 if (found == 0) { 5094 w->enable = 0; 5095 done = 0; 5096 HDA_BOOTHVERBOSE( 5097 device_printf(devinfo->codec->sc->dev, 5098 " Disabling nid %d due to all it's" 5099 " inputs disabled.\n", w->nid); 5100 ); 5101 } 5102 /* Disable nodes without consumers. */ 5103 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5104 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5105 continue; 5106 found = 0; 5107 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5108 cw = hdac_widget_get(devinfo, k); 5109 if (cw == NULL || cw->enable == 0) 5110 continue; 5111 for (j = 0; j < cw->nconns; j++) { 5112 if (cw->connsenable[j] && cw->conns[j] == i) { 5113 found = 1; 5114 break; 5115 } 5116 } 5117 } 5118 if (found == 0) { 5119 w->enable = 0; 5120 done = 0; 5121 HDA_BOOTHVERBOSE( 5122 device_printf(devinfo->codec->sc->dev, 5123 " Disabling nid %d due to all it's" 5124 " consumers disabled.\n", w->nid); 5125 ); 5126 } 5127 } 5128 } while (done == 0); 5129 5130} 5131 5132static void 5133hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5134{ 5135 struct hdac_audio_as *as = devinfo->function.audio.as; 5136 struct hdac_widget *w, *cw; 5137 struct hdac_audio_ctl *ctl; 5138 int i, j, k; 5139 5140 /* Disable unassosiated widgets. */ 5141 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5142 w = hdac_widget_get(devinfo, i); 5143 if (w == NULL || w->enable == 0) 5144 continue; 5145 if (w->bindas == -1) { 5146 w->enable = 0; 5147 HDA_BOOTHVERBOSE( 5148 device_printf(devinfo->codec->sc->dev, 5149 " Disabling unassociated nid %d.\n", 5150 w->nid); 5151 ); 5152 } 5153 } 5154 /* Disable input connections on input pin and 5155 * output on output. */ 5156 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5157 w = hdac_widget_get(devinfo, i); 5158 if (w == NULL || w->enable == 0) 5159 continue; 5160 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5161 continue; 5162 if (w->bindas < 0) 5163 continue; 5164 if (as[w->bindas].dir == HDA_CTL_IN) { 5165 for (j = 0; j < w->nconns; j++) { 5166 if (w->connsenable[j] == 0) 5167 continue; 5168 w->connsenable[j] = 0; 5169 HDA_BOOTHVERBOSE( 5170 device_printf(devinfo->codec->sc->dev, 5171 " Disabling connection to input pin " 5172 "nid %d conn %d.\n", 5173 i, j); 5174 ); 5175 } 5176 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5177 HDA_CTL_IN, -1, 1); 5178 if (ctl && ctl->enable) { 5179 ctl->forcemute = 1; 5180 ctl->muted = HDA_AMP_MUTE_ALL; 5181 ctl->left = 0; 5182 ctl->right = 0; 5183 ctl->enable = 0; 5184 } 5185 } else { 5186 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5187 HDA_CTL_OUT, -1, 1); 5188 if (ctl && ctl->enable) { 5189 ctl->forcemute = 1; 5190 ctl->muted = HDA_AMP_MUTE_ALL; 5191 ctl->left = 0; 5192 ctl->right = 0; 5193 ctl->enable = 0; 5194 } 5195 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5196 cw = hdac_widget_get(devinfo, k); 5197 if (cw == NULL || cw->enable == 0) 5198 continue; 5199 for (j = 0; j < cw->nconns; j++) { 5200 if (cw->connsenable[j] && cw->conns[j] == i) { 5201 cw->connsenable[j] = 0; 5202 HDA_BOOTHVERBOSE( 5203 device_printf(devinfo->codec->sc->dev, 5204 " Disabling connection from output pin " 5205 "nid %d conn %d cnid %d.\n", 5206 k, j, i); 5207 ); 5208 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5209 cw->nconns > 1) 5210 continue; 5211 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5212 HDA_CTL_IN, j, 1); 5213 if (ctl && ctl->enable) { 5214 ctl->forcemute = 1; 5215 ctl->muted = HDA_AMP_MUTE_ALL; 5216 ctl->left = 0; 5217 ctl->right = 0; 5218 ctl->enable = 0; 5219 } 5220 } 5221 } 5222 } 5223 } 5224 } 5225} 5226 5227static void 5228hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5229{ 5230 struct hdac_audio_as *as = devinfo->function.audio.as; 5231 struct hdac_widget *w; 5232 int i, j; 5233 5234 /* On playback path we can safely disable all unseleted inputs. */ 5235 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5236 w = hdac_widget_get(devinfo, i); 5237 if (w == NULL || w->enable == 0) 5238 continue; 5239 if (w->nconns <= 1) 5240 continue; 5241 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5242 continue; 5243 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5244 continue; 5245 for (j = 0; j < w->nconns; j++) { 5246 if (w->connsenable[j] == 0) 5247 continue; 5248 if (w->selconn < 0 || w->selconn == j) 5249 continue; 5250 w->connsenable[j] = 0; 5251 HDA_BOOTHVERBOSE( 5252 device_printf(devinfo->codec->sc->dev, 5253 " Disabling unselected connection " 5254 "nid %d conn %d.\n", 5255 i, j); 5256 ); 5257 } 5258 } 5259} 5260 5261static void 5262hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5263{ 5264 struct hdac_widget *w, *cw; 5265 struct hdac_audio_ctl *ctl; 5266 int i, j; 5267 5268 /* Disable crossassociatement connections. */ 5269 /* ... using selectors */ 5270 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5271 w = hdac_widget_get(devinfo, i); 5272 if (w == NULL || w->enable == 0) 5273 continue; 5274 if (w->nconns <= 1) 5275 continue; 5276 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5277 continue; 5278 if (w->bindas == -2) 5279 continue; 5280 for (j = 0; j < w->nconns; j++) { 5281 if (w->connsenable[j] == 0) 5282 continue; 5283 cw = hdac_widget_get(devinfo, w->conns[j]); 5284 if (cw == NULL || w->enable == 0) 5285 continue; 5286 if (w->bindas == cw->bindas || cw->bindas == -2) 5287 continue; 5288 w->connsenable[j] = 0; 5289 HDA_BOOTHVERBOSE( 5290 device_printf(devinfo->codec->sc->dev, 5291 " Disabling crossassociatement connection " 5292 "nid %d conn %d cnid %d.\n", 5293 i, j, cw->nid); 5294 ); 5295 } 5296 } 5297 /* ... using controls */ 5298 i = 0; 5299 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5300 if (ctl->enable == 0 || ctl->childwidget == NULL) 5301 continue; 5302 if (ctl->widget->bindas == -2 || 5303 ctl->childwidget->bindas == -2) 5304 continue; 5305 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5306 ctl->forcemute = 1; 5307 ctl->muted = HDA_AMP_MUTE_ALL; 5308 ctl->left = 0; 5309 ctl->right = 0; 5310 ctl->enable = 0; 5311 if (ctl->ndir == HDA_CTL_IN) 5312 ctl->widget->connsenable[ctl->index] = 0; 5313 HDA_BOOTHVERBOSE( 5314 device_printf(devinfo->codec->sc->dev, 5315 " Disabling crossassociatement connection " 5316 "ctl %d nid %d cnid %d.\n", i, 5317 ctl->widget->nid, 5318 ctl->childwidget->nid); 5319 ); 5320 } 5321 } 5322 5323} 5324 5325#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5326 5327/* 5328 * Find controls to control amplification for source. 5329 */ 5330static int 5331hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5332 int ossdev, int ctlable, int depth, int need) 5333{ 5334 struct hdac_widget *w, *wc; 5335 struct hdac_audio_ctl *ctl; 5336 int i, j, conns = 0, rneed; 5337 5338 if (depth > HDA_PARSE_MAXDEPTH) 5339 return (need); 5340 5341 w = hdac_widget_get(devinfo, nid); 5342 if (w == NULL || w->enable == 0) 5343 return (need); 5344 5345 /* Count number of active inputs. */ 5346 if (depth > 0) { 5347 for (j = 0; j < w->nconns; j++) { 5348 if (w->connsenable[j]) 5349 conns++; 5350 } 5351 } 5352 5353 /* If this is not a first step - use input mixer. 5354 Pins have common input ctl so care must be taken. */ 5355 if (depth > 0 && ctlable && (conns == 1 || 5356 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5357 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5358 index, 1); 5359 if (ctl) { 5360 if (HDA_CTL_GIVE(ctl) & need) 5361 ctl->ossmask |= (1 << ossdev); 5362 else 5363 ctl->possmask |= (1 << ossdev); 5364 need &= ~HDA_CTL_GIVE(ctl); 5365 } 5366 } 5367 5368 /* If widget has own ossdev - not traverse it. 5369 It will be traversed on it's own. */ 5370 if (w->ossdev >= 0 && depth > 0) 5371 return (need); 5372 5373 /* We must not traverse pin */ 5374 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5375 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5376 depth > 0) 5377 return (need); 5378 5379 /* record that this widget exports such signal, */ 5380 w->ossmask |= (1 << ossdev); 5381 5382 /* If signals mixed, we can't assign controls farther. 5383 * Ignore this on depth zero. Caller must knows why. 5384 * Ignore this for static selectors if this input selected. 5385 */ 5386 if (conns > 1) 5387 ctlable = 0; 5388 5389 if (ctlable) { 5390 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5391 if (ctl) { 5392 if (HDA_CTL_GIVE(ctl) & need) 5393 ctl->ossmask |= (1 << ossdev); 5394 else 5395 ctl->possmask |= (1 << ossdev); 5396 need &= ~HDA_CTL_GIVE(ctl); 5397 } 5398 } 5399 5400 rneed = 0; 5401 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5402 wc = hdac_widget_get(devinfo, i); 5403 if (wc == NULL || wc->enable == 0) 5404 continue; 5405 for (j = 0; j < wc->nconns; j++) { 5406 if (wc->connsenable[j] && wc->conns[j] == nid) { 5407 rneed |= hdac_audio_ctl_source_amp(devinfo, 5408 wc->nid, j, ossdev, ctlable, depth + 1, need); 5409 } 5410 } 5411 } 5412 rneed &= need; 5413 5414 return (rneed); 5415} 5416 5417/* 5418 * Find controls to control amplification for destination. 5419 */ 5420static void 5421hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5422 int ossdev, int depth, int need) 5423{ 5424 struct hdac_audio_as *as = devinfo->function.audio.as; 5425 struct hdac_widget *w, *wc; 5426 struct hdac_audio_ctl *ctl; 5427 int i, j, consumers; 5428 5429 if (depth > HDA_PARSE_MAXDEPTH) 5430 return; 5431 5432 w = hdac_widget_get(devinfo, nid); 5433 if (w == NULL || w->enable == 0) 5434 return; 5435 5436 if (depth > 0) { 5437 /* If this node produce output for several consumers, 5438 we can't touch it. */ 5439 consumers = 0; 5440 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5441 wc = hdac_widget_get(devinfo, i); 5442 if (wc == NULL || wc->enable == 0) 5443 continue; 5444 for (j = 0; j < wc->nconns; j++) { 5445 if (wc->connsenable[j] && wc->conns[j] == nid) 5446 consumers++; 5447 } 5448 } 5449 /* The only exception is if real HP redirection is configured 5450 and this is a duplication point. 5451 XXX: Actually exception is not completely correct. 5452 XXX: Duplication point check is not perfect. */ 5453 if ((consumers == 2 && (w->bindas < 0 || 5454 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5455 (w->bindseqmask & (1 << 15)) == 0)) || 5456 consumers > 2) 5457 return; 5458 5459 /* Else use it's output mixer. */ 5460 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5461 HDA_CTL_OUT, -1, 1); 5462 if (ctl) { 5463 if (HDA_CTL_GIVE(ctl) & need) 5464 ctl->ossmask |= (1 << ossdev); 5465 else 5466 ctl->possmask |= (1 << ossdev); 5467 need &= ~HDA_CTL_GIVE(ctl); 5468 } 5469 } 5470 5471 /* We must not traverse pin */ 5472 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5473 depth > 0) 5474 return; 5475 5476 for (i = 0; i < w->nconns; i++) { 5477 int tneed = need; 5478 if (w->connsenable[i] == 0) 5479 continue; 5480 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5481 HDA_CTL_IN, i, 1); 5482 if (ctl) { 5483 if (HDA_CTL_GIVE(ctl) & tneed) 5484 ctl->ossmask |= (1 << ossdev); 5485 else 5486 ctl->possmask |= (1 << ossdev); 5487 tneed &= ~HDA_CTL_GIVE(ctl); 5488 } 5489 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5490 depth + 1, tneed); 5491 } 5492} 5493 5494/* 5495 * Assign OSS names to sound sources 5496 */ 5497static void 5498hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5499{ 5500 struct hdac_audio_as *as = devinfo->function.audio.as; 5501 struct hdac_widget *w; 5502 int i, j; 5503 int type = -1, use, used = 0; 5504 static const int types[7][13] = { 5505 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5506 SOUND_MIXER_LINE3, -1 }, /* line */ 5507 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5508 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5509 { SOUND_MIXER_CD, -1 }, /* cd */ 5510 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5511 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5512 -1 }, /* digital */ 5513 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5514 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5515 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5516 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5517 -1 } /* others */ 5518 }; 5519 5520 /* Surely known names */ 5521 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5522 w = hdac_widget_get(devinfo, i); 5523 if (w == NULL || w->enable == 0) 5524 continue; 5525 if (w->bindas == -1) 5526 continue; 5527 use = -1; 5528 switch (w->type) { 5529 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5530 if (as[w->bindas].dir == HDA_CTL_OUT) 5531 break; 5532 type = -1; 5533 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5534 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5535 type = 0; 5536 break; 5537 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5538 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5539 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5540 break; 5541 type = 1; 5542 break; 5543 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5544 type = 3; 5545 break; 5546 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5547 type = 4; 5548 break; 5549 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5550 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5551 type = 5; 5552 break; 5553 } 5554 if (type == -1) 5555 break; 5556 j = 0; 5557 while (types[type][j] >= 0 && 5558 (used & (1 << types[type][j])) != 0) { 5559 j++; 5560 } 5561 if (types[type][j] >= 0) 5562 use = types[type][j]; 5563 break; 5564 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5565 use = SOUND_MIXER_PCM; 5566 break; 5567 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5568 use = SOUND_MIXER_SPEAKER; 5569 break; 5570 default: 5571 break; 5572 } 5573 if (use >= 0) { 5574 w->ossdev = use; 5575 used |= (1 << use); 5576 } 5577 } 5578 /* Semi-known names */ 5579 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5580 w = hdac_widget_get(devinfo, i); 5581 if (w == NULL || w->enable == 0) 5582 continue; 5583 if (w->ossdev >= 0) 5584 continue; 5585 if (w->bindas == -1) 5586 continue; 5587 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5588 continue; 5589 if (as[w->bindas].dir == HDA_CTL_OUT) 5590 continue; 5591 type = -1; 5592 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5593 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5594 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5595 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5596 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5597 type = 0; 5598 break; 5599 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5600 type = 2; 5601 break; 5602 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5603 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5604 type = 5; 5605 break; 5606 } 5607 if (type == -1) 5608 break; 5609 j = 0; 5610 while (types[type][j] >= 0 && 5611 (used & (1 << types[type][j])) != 0) { 5612 j++; 5613 } 5614 if (types[type][j] >= 0) { 5615 w->ossdev = types[type][j]; 5616 used |= (1 << types[type][j]); 5617 } 5618 } 5619 /* Others */ 5620 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5621 w = hdac_widget_get(devinfo, i); 5622 if (w == NULL || w->enable == 0) 5623 continue; 5624 if (w->ossdev >= 0) 5625 continue; 5626 if (w->bindas == -1) 5627 continue; 5628 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5629 continue; 5630 if (as[w->bindas].dir == HDA_CTL_OUT) 5631 continue; 5632 j = 0; 5633 while (types[6][j] >= 0 && 5634 (used & (1 << types[6][j])) != 0) { 5635 j++; 5636 } 5637 if (types[6][j] >= 0) { 5638 w->ossdev = types[6][j]; 5639 used |= (1 << types[6][j]); 5640 } 5641 } 5642} 5643 5644static void 5645hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5646{ 5647 struct hdac_audio_as *as = devinfo->function.audio.as; 5648 int j, res; 5649 5650 /* Trace all associations in order of their numbers, */ 5651 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5652 if (as[j].enable == 0) 5653 continue; 5654 HDA_BOOTVERBOSE( 5655 device_printf(devinfo->codec->sc->dev, 5656 "Tracing association %d (%d)\n", j, as[j].index); 5657 ); 5658 if (as[j].dir == HDA_CTL_OUT) { 5659retry: 5660 res = hdac_audio_trace_as_out(devinfo, j, 0); 5661 if (res == 0 && as[j].hpredir >= 0 && 5662 as[j].fakeredir == 0) { 5663 /* If codec can't do analog HP redirection 5664 try to make it using one more DAC. */ 5665 as[j].fakeredir = 1; 5666 goto retry; 5667 } 5668 } else { 5669 res = hdac_audio_trace_as_in(devinfo, j); 5670 } 5671 if (res) { 5672 HDA_BOOTVERBOSE( 5673 device_printf(devinfo->codec->sc->dev, 5674 "Association %d (%d) trace succeded\n", 5675 j, as[j].index); 5676 ); 5677 } else { 5678 HDA_BOOTVERBOSE( 5679 device_printf(devinfo->codec->sc->dev, 5680 "Association %d (%d) trace failed\n", 5681 j, as[j].index); 5682 ); 5683 as[j].enable = 0; 5684 } 5685 } 5686 5687 /* Trace mixer and beeper pseudo associations. */ 5688 hdac_audio_trace_as_extra(devinfo); 5689} 5690 5691static void 5692hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5693{ 5694 struct hdac_audio_as *as = devinfo->function.audio.as; 5695 struct hdac_audio_ctl *ctl; 5696 struct hdac_widget *w; 5697 int i; 5698 5699 /* Assign mixers to the tree. */ 5700 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5701 w = hdac_widget_get(devinfo, i); 5702 if (w == NULL || w->enable == 0) 5703 continue; 5704 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5705 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5706 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5707 as[w->bindas].dir == HDA_CTL_IN)) { 5708 if (w->ossdev < 0) 5709 continue; 5710 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5711 w->ossdev, 1, 0, 1); 5712 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5713 if (w->ossdev < 0) 5714 continue; 5715 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5716 w->ossdev, 1, 0, 1)) { 5717 /* If we are unable to control input monitor 5718 as source - try to control it as destination. */ 5719 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5720 w->ossdev, 0, 1); 5721 } 5722 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5723 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5724 SOUND_MIXER_RECLEV, 0, 1); 5725 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5726 as[w->bindas].dir == HDA_CTL_OUT) { 5727 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5728 SOUND_MIXER_VOLUME, 0, 1); 5729 } 5730 } 5731 /* Treat unrequired as possible. */ 5732 i = 0; 5733 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5734 if (ctl->ossmask == 0) 5735 ctl->ossmask = ctl->possmask; 5736 } 5737} 5738 5739static void 5740hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5741{ 5742 struct hdac_audio_as *as = devinfo->function.audio.as; 5743 struct hdac_widget *w; 5744 uint32_t pincap; 5745 int i; 5746 5747 for (i = 0; i < devinfo->nodecnt; i++) { 5748 w = &devinfo->widget[i]; 5749 if (w == NULL) 5750 continue; 5751 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5752 continue; 5753 5754 pincap = w->wclass.pin.cap; 5755 5756 /* Disable everything. */ 5757 w->wclass.pin.ctrl &= ~( 5758 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5759 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5760 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5761 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5762 5763 if (w->enable == 0 || 5764 w->bindas < 0 || as[w->bindas].enable == 0) { 5765 /* Pin is unused so left it disabled. */ 5766 continue; 5767 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5768 /* Input pin, configure for input. */ 5769 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5770 w->wclass.pin.ctrl |= 5771 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5772 5773 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5774 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5775 w->wclass.pin.ctrl |= 5776 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5777 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5778 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5779 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5780 w->wclass.pin.ctrl |= 5781 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5782 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5783 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5784 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5785 w->wclass.pin.ctrl |= 5786 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5787 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5788 } else { 5789 /* Output pin, configure for output. */ 5790 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5791 w->wclass.pin.ctrl |= 5792 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5793 5794 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5795 (w->wclass.pin.config & 5796 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5797 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5798 w->wclass.pin.ctrl |= 5799 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5800 5801 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5802 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5803 w->wclass.pin.ctrl |= 5804 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5805 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5806 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5807 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5808 w->wclass.pin.ctrl |= 5809 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5810 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5811 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5812 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5813 w->wclass.pin.ctrl |= 5814 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5815 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5816 } 5817 } 5818} 5819 5820static void 5821hdac_audio_commit(struct hdac_devinfo *devinfo) 5822{ 5823 struct hdac_softc *sc = devinfo->codec->sc; 5824 struct hdac_widget *w; 5825 nid_t cad; 5826 uint32_t gdata, gmask, gdir; 5827 int commitgpio, numgpio; 5828 int i; 5829 5830 cad = devinfo->codec->cad; 5831 5832 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5833 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5834 0x7e7, 0), cad); 5835 5836 gdata = 0; 5837 gmask = 0; 5838 gdir = 0; 5839 commitgpio = 0; 5840 5841 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5842 devinfo->function.audio.gpio); 5843 5844 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5845 commitgpio = (numgpio > 0) ? 1 : 0; 5846 else { 5847 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5848 if (!(devinfo->function.audio.quirks & 5849 (1 << i))) 5850 continue; 5851 if (commitgpio == 0) { 5852 commitgpio = 1; 5853 HDA_BOOTVERBOSE( 5854 gdata = hdac_command(sc, 5855 HDA_CMD_GET_GPIO_DATA(cad, 5856 devinfo->nid), cad); 5857 gmask = hdac_command(sc, 5858 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5859 devinfo->nid), cad); 5860 gdir = hdac_command(sc, 5861 HDA_CMD_GET_GPIO_DIRECTION(cad, 5862 devinfo->nid), cad); 5863 device_printf(sc->dev, 5864 "GPIO init: data=0x%08x " 5865 "mask=0x%08x dir=0x%08x\n", 5866 gdata, gmask, gdir); 5867 gdata = 0; 5868 gmask = 0; 5869 gdir = 0; 5870 ); 5871 } 5872 gdata |= 1 << i; 5873 gmask |= 1 << i; 5874 gdir |= 1 << i; 5875 } 5876 } 5877 5878 if (commitgpio != 0) { 5879 HDA_BOOTVERBOSE( 5880 device_printf(sc->dev, 5881 "GPIO commit: data=0x%08x mask=0x%08x " 5882 "dir=0x%08x\n", 5883 gdata, gmask, gdir); 5884 ); 5885 hdac_command(sc, 5886 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5887 gmask), cad); 5888 hdac_command(sc, 5889 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5890 gdir), cad); 5891 hdac_command(sc, 5892 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5893 gdata), cad); 5894 } 5895 5896 for (i = 0; i < devinfo->nodecnt; i++) { 5897 w = &devinfo->widget[i]; 5898 if (w == NULL) 5899 continue; 5900 if (w->selconn == -1) 5901 w->selconn = 0; 5902 if (w->nconns > 0) 5903 hdac_widget_connection_select(w, w->selconn); 5904 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5905 hdac_command(sc, 5906 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5907 w->wclass.pin.ctrl), cad); 5908 } 5909 if (w->param.eapdbtl != HDAC_INVALID) { 5910 uint32_t val; 5911 5912 val = w->param.eapdbtl; 5913 if (devinfo->function.audio.quirks & 5914 HDA_QUIRK_EAPDINV) 5915 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5916 hdac_command(sc, 5917 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5918 val), cad); 5919 5920 } 5921 DELAY(1000); 5922 } 5923} 5924 5925static void 5926hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5927{ 5928 struct hdac_audio_ctl *ctl; 5929 int i, z; 5930 5931 i = 0; 5932 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5933 if (ctl->enable == 0) { 5934 /* Mute disabled controls. */ 5935 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 5936 continue; 5937 } 5938 /* Init controls to 0dB amplification. */ 5939 z = ctl->offset; 5940 if (z > ctl->step) 5941 z = ctl->step; 5942 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 5943 } 5944} 5945 5946static void 5947hdac_powerup(struct hdac_devinfo *devinfo) 5948{ 5949 struct hdac_softc *sc = devinfo->codec->sc; 5950 nid_t cad = devinfo->codec->cad; 5951 int i; 5952 5953 hdac_command(sc, 5954 HDA_CMD_SET_POWER_STATE(cad, 5955 devinfo->nid, HDA_CMD_POWER_STATE_D0), 5956 cad); 5957 DELAY(100); 5958 5959 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5960 hdac_command(sc, 5961 HDA_CMD_SET_POWER_STATE(cad, 5962 i, HDA_CMD_POWER_STATE_D0), 5963 cad); 5964 } 5965 DELAY(1000); 5966} 5967 5968static int 5969hdac_pcmchannel_setup(struct hdac_chan *ch) 5970{ 5971 struct hdac_devinfo *devinfo = ch->devinfo; 5972 struct hdac_audio_as *as = devinfo->function.audio.as; 5973 struct hdac_widget *w; 5974 uint32_t cap, fmtcap, pcmcap; 5975 int i, j, ret, max; 5976 5977 ch->caps = hdac_caps; 5978 ch->caps.fmtlist = ch->fmtlist; 5979 ch->bit16 = 1; 5980 ch->bit32 = 0; 5981 ch->pcmrates[0] = 48000; 5982 ch->pcmrates[1] = 0; 5983 5984 ret = 0; 5985 fmtcap = devinfo->function.audio.supp_stream_formats; 5986 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5987 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5988 5989 for (i = 0; i < 16 && ret < max; i++) { 5990 /* Check as is correct */ 5991 if (ch->as < 0) 5992 break; 5993 /* Cound only present DACs */ 5994 if (as[ch->as].dacs[i] <= 0) 5995 continue; 5996 /* Ignore duplicates */ 5997 for (j = 0; j < ret; j++) { 5998 if (ch->io[j] == as[ch->as].dacs[i]) 5999 break; 6000 } 6001 if (j < ret) 6002 continue; 6003 6004 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6005 if (w == NULL || w->enable == 0) 6006 continue; 6007 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6008 continue; 6009 cap = w->param.supp_stream_formats; 6010 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6011 }*/ 6012 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6013 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6014 continue; 6015 /* Many codec does not declare AC3 support on SPDIF. 6016 I don't beleave that they doesn't support it! */ 6017 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6018 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6019 if (ret == 0) { 6020 fmtcap = cap; 6021 pcmcap = w->param.supp_pcm_size_rate; 6022 } else { 6023 fmtcap &= cap; 6024 pcmcap &= w->param.supp_pcm_size_rate; 6025 } 6026 ch->io[ret++] = as[ch->as].dacs[i]; 6027 } 6028 ch->io[ret] = -1; 6029 6030 ch->supp_stream_formats = fmtcap; 6031 ch->supp_pcm_size_rate = pcmcap; 6032 6033 /* 6034 * 8bit = 0 6035 * 16bit = 1 6036 * 20bit = 2 6037 * 24bit = 3 6038 * 32bit = 4 6039 */ 6040 if (ret > 0) { 6041 i = 0; 6042 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6043 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6044 ch->bit16 = 1; 6045 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6046 ch->bit16 = 0; 6047 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6048 ch->bit32 = 4; 6049 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6050 ch->bit32 = 3; 6051 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6052 ch->bit32 = 2; 6053 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6054 ch->fmtlist[i++] = AFMT_S16_LE; 6055 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6056 if (ch->bit32 > 0) { 6057 if (!(devinfo->function.audio.quirks & 6058 HDA_QUIRK_FORCESTEREO)) 6059 ch->fmtlist[i++] = AFMT_S32_LE; 6060 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6061 } 6062 } 6063 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6064 ch->fmtlist[i++] = AFMT_AC3; 6065 } 6066 ch->fmtlist[i] = 0; 6067 i = 0; 6068 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6069 ch->pcmrates[i++] = 8000; 6070 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6071 ch->pcmrates[i++] = 11025; 6072 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6073 ch->pcmrates[i++] = 16000; 6074 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6075 ch->pcmrates[i++] = 22050; 6076 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6077 ch->pcmrates[i++] = 32000; 6078 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6079 ch->pcmrates[i++] = 44100; 6080 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6081 ch->pcmrates[i++] = 48000; 6082 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6083 ch->pcmrates[i++] = 88200; 6084 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6085 ch->pcmrates[i++] = 96000; 6086 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6087 ch->pcmrates[i++] = 176400; 6088 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6089 ch->pcmrates[i++] = 192000; 6090 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6091 ch->pcmrates[i] = 0; 6092 if (i > 0) { 6093 ch->caps.minspeed = ch->pcmrates[0]; 6094 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6095 } 6096 } 6097 6098 return (ret); 6099} 6100 6101static void 6102hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6103{ 6104 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6105 struct hdac_audio_ctl *ctl; 6106 struct hdac_softc *sc = devinfo->codec->sc; 6107 char buf[64]; 6108 int i, j, printed; 6109 6110 if (flag == 0) { 6111 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6112 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6113 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6114 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6115 } 6116 6117 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6118 if ((flag & (1 << j)) == 0) 6119 continue; 6120 i = 0; 6121 printed = 0; 6122 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6123 if (ctl->enable == 0 || 6124 ctl->widget->enable == 0) 6125 continue; 6126 if (!((pdevinfo->play >= 0 && 6127 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6128 (pdevinfo->rec >= 0 && 6129 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6130 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6131 continue; 6132 if ((ctl->ossmask & (1 << j)) == 0) 6133 continue; 6134 6135 if (printed == 0) { 6136 device_printf(pdevinfo->dev, "\n"); 6137 if (banner != NULL) { 6138 device_printf(pdevinfo->dev, "%s", banner); 6139 } else { 6140 device_printf(pdevinfo->dev, "Unknown Ctl"); 6141 } 6142 printf(" (OSS: %s)\n", 6143 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6144 buf, sizeof(buf))); 6145 device_printf(pdevinfo->dev, " |\n"); 6146 printed = 1; 6147 } 6148 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6149 ctl->widget->nid, 6150 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6151 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6152 printf(" %2d): ", ctl->index); 6153 else 6154 printf("): "); 6155 if (ctl->step > 0) { 6156 printf("%+d/%+ddB (%d steps)%s\n", 6157 (0 - ctl->offset) * (ctl->size + 1) / 4, 6158 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6159 ctl->step + 1, 6160 ctl->mute?" + mute":""); 6161 } else 6162 printf("%s\n", ctl->mute?"mute":""); 6163 } 6164 } 6165} 6166 6167static void 6168hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6169{ 6170 uint32_t cap; 6171 6172 cap = fcap; 6173 if (cap != 0) { 6174 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6175 device_printf(dev, " "); 6176 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6177 printf(" AC3"); 6178 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6179 printf(" FLOAT32"); 6180 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6181 printf(" PCM"); 6182 printf("\n"); 6183 } 6184 cap = pcmcap; 6185 if (cap != 0) { 6186 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6187 device_printf(dev, " "); 6188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6189 printf(" 8"); 6190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6191 printf(" 16"); 6192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6193 printf(" 20"); 6194 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6195 printf(" 24"); 6196 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6197 printf(" 32"); 6198 printf(" bits,"); 6199 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6200 printf(" 8"); 6201 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6202 printf(" 11"); 6203 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6204 printf(" 16"); 6205 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6206 printf(" 22"); 6207 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6208 printf(" 32"); 6209 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6210 printf(" 44"); 6211 printf(" 48"); 6212 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6213 printf(" 88"); 6214 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6215 printf(" 96"); 6216 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6217 printf(" 176"); 6218 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6219 printf(" 192"); 6220 printf(" KHz\n"); 6221 } 6222} 6223 6224static void 6225hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6226{ 6227 uint32_t pincap; 6228 6229 pincap = w->wclass.pin.cap; 6230 6231 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6232 device_printf(sc->dev, " "); 6233 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6234 printf(" ISC"); 6235 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6236 printf(" TRQD"); 6237 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6238 printf(" PDC"); 6239 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6240 printf(" HP"); 6241 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6242 printf(" OUT"); 6243 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6244 printf(" IN"); 6245 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6246 printf(" BAL"); 6247 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6248 printf(" VREF["); 6249 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6250 printf(" 50"); 6251 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6252 printf(" 80"); 6253 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6254 printf(" 100"); 6255 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6256 printf(" GROUND"); 6257 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6258 printf(" HIZ"); 6259 printf(" ]"); 6260 } 6261 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6262 printf(" EAPD"); 6263 printf("\n"); 6264 device_printf(sc->dev, " Pin config: 0x%08x\n", 6265 w->wclass.pin.config); 6266 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6267 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6268 printf(" HP"); 6269 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6270 printf(" IN"); 6271 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6272 printf(" OUT"); 6273 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6274 printf(" VREFs"); 6275 printf("\n"); 6276} 6277 6278static void 6279hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6280{ 6281 struct hdac_softc *sc = w->devinfo->codec->sc; 6282 6283 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6284 "jack %2d loc %2d color %7s misc %d%s\n", 6285 w->nid, conf, 6286 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6287 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6288 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6289 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6290 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6291 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6292 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6293 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6294 (w->enable == 0)?" [DISABLED]":""); 6295} 6296 6297static void 6298hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6299{ 6300 struct hdac_widget *w; 6301 int i; 6302 6303 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6304 w = hdac_widget_get(devinfo, i); 6305 if (w == NULL) 6306 continue; 6307 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6308 continue; 6309 hdac_dump_pin_config(w, w->wclass.pin.config); 6310 } 6311} 6312 6313static void 6314hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6315{ 6316 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6317 device_printf(sc->dev, " " 6318 "mute=%d step=%d size=%d offset=%d\n", 6319 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6320 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6321 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6322 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6323} 6324 6325static void 6326hdac_dump_nodes(struct hdac_devinfo *devinfo) 6327{ 6328 struct hdac_softc *sc = devinfo->codec->sc; 6329 static char *ossname[] = SOUND_DEVICE_NAMES; 6330 struct hdac_widget *w, *cw; 6331 char buf[64]; 6332 int i, j; 6333 6334 device_printf(sc->dev, "\n"); 6335 device_printf(sc->dev, "Default Parameter\n"); 6336 device_printf(sc->dev, "-----------------\n"); 6337 hdac_dump_audio_formats(sc->dev, 6338 devinfo->function.audio.supp_stream_formats, 6339 devinfo->function.audio.supp_pcm_size_rate); 6340 device_printf(sc->dev, " IN amp: 0x%08x\n", 6341 devinfo->function.audio.inamp_cap); 6342 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6343 devinfo->function.audio.outamp_cap); 6344 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6345 w = hdac_widget_get(devinfo, i); 6346 if (w == NULL) { 6347 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6348 continue; 6349 } 6350 device_printf(sc->dev, "\n"); 6351 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6352 (w->enable == 0) ? " [DISABLED]" : ""); 6353 device_printf(sc->dev, " Name: %s\n", w->name); 6354 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6355 w->param.widget_cap); 6356 if (w->param.widget_cap & 0x0ee1) { 6357 device_printf(sc->dev, " "); 6358 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6359 printf(" LRSWAP"); 6360 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6361 printf(" PWR"); 6362 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6363 printf(" DIGITAL"); 6364 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6365 printf(" UNSOL"); 6366 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6367 printf(" PROC"); 6368 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6369 printf(" STRIPE"); 6370 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6371 printf(" STEREO"); 6372 printf("\n"); 6373 } 6374 if (w->bindas != -1) { 6375 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6376 w->bindas, w->bindseqmask); 6377 } 6378 if (w->ossmask != 0 || w->ossdev >= 0) { 6379 device_printf(sc->dev, " OSS: %s", 6380 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6381 if (w->ossdev >= 0) 6382 printf(" (%s)", ossname[w->ossdev]); 6383 printf("\n"); 6384 } 6385 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6386 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6387 hdac_dump_audio_formats(sc->dev, 6388 w->param.supp_stream_formats, 6389 w->param.supp_pcm_size_rate); 6390 } else if (w->type == 6391 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6392 hdac_dump_pin(sc, w); 6393 if (w->param.eapdbtl != HDAC_INVALID) 6394 device_printf(sc->dev, " EAPD: 0x%08x\n", 6395 w->param.eapdbtl); 6396 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6397 w->param.outamp_cap != 0) 6398 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6399 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6400 w->param.inamp_cap != 0) 6401 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6402 if (w->nconns > 0) { 6403 device_printf(sc->dev, " connections: %d\n", w->nconns); 6404 device_printf(sc->dev, " |\n"); 6405 } 6406 for (j = 0; j < w->nconns; j++) { 6407 cw = hdac_widget_get(devinfo, w->conns[j]); 6408 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6409 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6410 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6411 if (cw == NULL) 6412 printf(" [UNKNOWN]"); 6413 else if (cw->enable == 0) 6414 printf(" [DISABLED]"); 6415 if (w->nconns > 1 && w->selconn == j && w->type != 6416 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6417 printf(" (selected)"); 6418 printf("\n"); 6419 } 6420 } 6421 6422} 6423 6424static void 6425hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6426{ 6427 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6428 struct hdac_widget *w, *cw; 6429 char buf[64]; 6430 int i, printed = 0; 6431 6432 if (depth > HDA_PARSE_MAXDEPTH) 6433 return; 6434 6435 w = hdac_widget_get(devinfo, nid); 6436 if (w == NULL || w->enable == 0) 6437 return; 6438 6439 if (depth == 0) 6440 device_printf(pdevinfo->dev, "%*s", 4, ""); 6441 else 6442 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6443 printf("nid=%d [%s]", w->nid, w->name); 6444 6445 if (depth > 0) { 6446 if (w->ossmask == 0) { 6447 printf("\n"); 6448 return; 6449 } 6450 printf(" [src: %s]", 6451 hdac_audio_ctl_ossmixer_mask2allname( 6452 w->ossmask, buf, sizeof(buf))); 6453 if (w->ossdev >= 0) { 6454 printf("\n"); 6455 return; 6456 } 6457 } 6458 printf("\n"); 6459 6460 for (i = 0; i < w->nconns; i++) { 6461 if (w->connsenable[i] == 0) 6462 continue; 6463 cw = hdac_widget_get(devinfo, w->conns[i]); 6464 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6465 continue; 6466 if (printed == 0) { 6467 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6468 printed = 1; 6469 } 6470 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6471 } 6472 6473} 6474 6475static void 6476hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6477{ 6478 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6479 struct hdac_softc *sc = devinfo->codec->sc; 6480 struct hdac_widget *w; 6481 int i, printed = 0; 6482 6483 if (pdevinfo->play < 0) 6484 return; 6485 6486 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6487 w = hdac_widget_get(devinfo, i); 6488 if (w == NULL || w->enable == 0) 6489 continue; 6490 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6491 continue; 6492 if (w->bindas != sc->chans[pdevinfo->play].as) 6493 continue; 6494 if (printed == 0) { 6495 printed = 1; 6496 device_printf(pdevinfo->dev, "\n"); 6497 device_printf(pdevinfo->dev, "Playback:\n"); 6498 } 6499 device_printf(pdevinfo->dev, "\n"); 6500 hdac_dump_dst_nid(pdevinfo, i, 0); 6501 } 6502} 6503 6504static void 6505hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6506{ 6507 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6508 struct hdac_softc *sc = devinfo->codec->sc; 6509 struct hdac_widget *w; 6510 int i; 6511 int printed = 0; 6512 6513 if (pdevinfo->rec < 0) 6514 return; 6515 6516 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6517 w = hdac_widget_get(devinfo, i); 6518 if (w == NULL || w->enable == 0) 6519 continue; 6520 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6521 continue; 6522 if (w->bindas != sc->chans[pdevinfo->rec].as) 6523 continue; 6524 if (printed == 0) { 6525 printed = 1; 6526 device_printf(pdevinfo->dev, "\n"); 6527 device_printf(pdevinfo->dev, "Record:\n"); 6528 } 6529 device_printf(pdevinfo->dev, "\n"); 6530 hdac_dump_dst_nid(pdevinfo, i, 0); 6531 } 6532} 6533 6534static void 6535hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6536{ 6537 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6538 struct hdac_widget *w; 6539 int i; 6540 int printed = 0; 6541 6542 if (pdevinfo->index != 0) 6543 return; 6544 6545 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6546 w = hdac_widget_get(devinfo, i); 6547 if (w == NULL || w->enable == 0) 6548 continue; 6549 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6550 continue; 6551 if (printed == 0) { 6552 printed = 1; 6553 device_printf(pdevinfo->dev, "\n"); 6554 device_printf(pdevinfo->dev, "Input Mix:\n"); 6555 } 6556 device_printf(pdevinfo->dev, "\n"); 6557 hdac_dump_dst_nid(pdevinfo, i, 0); 6558 } 6559} 6560 6561static void 6562hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6563{ 6564 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6565 nid_t *nids; 6566 int i; 6567 6568 if (pdevinfo->play >= 0) { 6569 i = pdevinfo->play; 6570 device_printf(pdevinfo->dev, "\n"); 6571 device_printf(pdevinfo->dev, "Playback:\n"); 6572 device_printf(pdevinfo->dev, "\n"); 6573 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6574 sc->chans[i].supp_pcm_size_rate); 6575 device_printf(pdevinfo->dev, " DAC:"); 6576 for (nids = sc->chans[i].io; *nids != -1; nids++) 6577 printf(" %d", *nids); 6578 printf("\n"); 6579 } 6580 if (pdevinfo->rec >= 0) { 6581 i = pdevinfo->rec; 6582 device_printf(pdevinfo->dev, "\n"); 6583 device_printf(pdevinfo->dev, "Record:\n"); 6584 device_printf(pdevinfo->dev, "\n"); 6585 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6586 sc->chans[i].supp_pcm_size_rate); 6587 device_printf(pdevinfo->dev, " ADC:"); 6588 for (nids = sc->chans[i].io; *nids != -1; nids++) 6589 printf(" %d", *nids); 6590 printf("\n"); 6591 } 6592} 6593 6594static void 6595hdac_release_resources(struct hdac_softc *sc) 6596{ 6597 int i, j; 6598 6599 if (sc == NULL) 6600 return; 6601 6602 hdac_lock(sc); 6603 sc->polling = 0; 6604 sc->poll_ival = 0; 6605 callout_stop(&sc->poll_hda); 6606 callout_stop(&sc->poll_hdac); 6607 callout_stop(&sc->poll_jack); 6608 hdac_reset(sc, 0); 6609 hdac_unlock(sc); 6610 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6611 callout_drain(&sc->poll_hda); 6612 callout_drain(&sc->poll_hdac); 6613 callout_drain(&sc->poll_jack); 6614 6615 hdac_irq_free(sc); 6616 6617 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6618 if (sc->codecs[i] == NULL) 6619 continue; 6620 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6621 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6622 if (sc->codecs[i]->fgs[j].node_type == 6623 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6624 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6625 M_HDAC); 6626 free(sc->codecs[i]->fgs[j].function.audio.as, 6627 M_HDAC); 6628 free(sc->codecs[i]->fgs[j].function.audio.devs, 6629 M_HDAC); 6630 } 6631 } 6632 free(sc->codecs[i]->fgs, M_HDAC); 6633 free(sc->codecs[i], M_HDAC); 6634 sc->codecs[i] = NULL; 6635 } 6636 6637 hdac_dma_free(sc, &sc->pos_dma); 6638 hdac_dma_free(sc, &sc->rirb_dma); 6639 hdac_dma_free(sc, &sc->corb_dma); 6640 for (i = 0; i < sc->num_chans; i++) { 6641 if (sc->chans[i].blkcnt > 0) 6642 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6643 } 6644 free(sc->chans, M_HDAC); 6645 if (sc->chan_dmat != NULL) { 6646 bus_dma_tag_destroy(sc->chan_dmat); 6647 sc->chan_dmat = NULL; 6648 } 6649 hdac_mem_free(sc); 6650 snd_mtxfree(sc->lock); 6651} 6652 6653/* This function surely going to make its way into upper level someday. */ 6654static void 6655hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6656{ 6657 const char *res = NULL; 6658 int i = 0, j, k, len, inv; 6659 6660 if (on != NULL) 6661 *on = 0; 6662 if (off != NULL) 6663 *off = 0; 6664 if (sc == NULL) 6665 return; 6666 if (resource_string_value(device_get_name(sc->dev), 6667 device_get_unit(sc->dev), "config", &res) != 0) 6668 return; 6669 if (!(res != NULL && strlen(res) > 0)) 6670 return; 6671 HDA_BOOTVERBOSE( 6672 device_printf(sc->dev, "HDA Config:"); 6673 ); 6674 for (;;) { 6675 while (res[i] != '\0' && 6676 (res[i] == ',' || isspace(res[i]) != 0)) 6677 i++; 6678 if (res[i] == '\0') { 6679 HDA_BOOTVERBOSE( 6680 printf("\n"); 6681 ); 6682 return; 6683 } 6684 j = i; 6685 while (res[j] != '\0' && 6686 !(res[j] == ',' || isspace(res[j]) != 0)) 6687 j++; 6688 len = j - i; 6689 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6690 inv = 2; 6691 else 6692 inv = 0; 6693 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6694 if (strncmp(res + i + inv, 6695 hdac_quirks_tab[k].key, len - inv) != 0) 6696 continue; 6697 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6698 break; 6699 HDA_BOOTVERBOSE( 6700 printf(" %s%s", (inv != 0) ? "no" : "", 6701 hdac_quirks_tab[k].key); 6702 ); 6703 if (inv == 0 && on != NULL) 6704 *on |= hdac_quirks_tab[k].value; 6705 else if (inv != 0 && off != NULL) 6706 *off |= hdac_quirks_tab[k].value; 6707 break; 6708 } 6709 i = j; 6710 } 6711} 6712 6713#ifdef SND_DYNSYSCTL 6714static int 6715sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6716{ 6717 struct hdac_softc *sc; 6718 device_t dev; 6719 uint32_t ctl; 6720 int err, val; 6721 6722 dev = oidp->oid_arg1; 6723 sc = device_get_softc(dev); 6724 if (sc == NULL) 6725 return (EINVAL); 6726 hdac_lock(sc); 6727 val = sc->polling; 6728 hdac_unlock(sc); 6729 err = sysctl_handle_int(oidp, &val, 0, req); 6730 6731 if (err != 0 || req->newptr == NULL) 6732 return (err); 6733 if (val < 0 || val > 1) 6734 return (EINVAL); 6735 6736 hdac_lock(sc); 6737 if (val != sc->polling) { 6738 if (val == 0) { 6739 callout_stop(&sc->poll_hda); 6740 callout_stop(&sc->poll_hdac); 6741 hdac_unlock(sc); 6742 callout_drain(&sc->poll_hda); 6743 callout_drain(&sc->poll_hdac); 6744 hdac_lock(sc); 6745 sc->polling = 0; 6746 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6747 ctl |= HDAC_INTCTL_GIE; 6748 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6749 } else { 6750 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6751 ctl &= ~HDAC_INTCTL_GIE; 6752 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6753 hdac_unlock(sc); 6754 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6755 hdac_lock(sc); 6756 sc->polling = 1; 6757 hdac_poll_reinit(sc); 6758 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6759 } 6760 } 6761 hdac_unlock(sc); 6762 6763 return (err); 6764} 6765 6766static int 6767sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6768{ 6769 struct hdac_softc *sc; 6770 device_t dev; 6771 int err, val; 6772 6773 dev = oidp->oid_arg1; 6774 sc = device_get_softc(dev); 6775 if (sc == NULL) 6776 return (EINVAL); 6777 hdac_lock(sc); 6778 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6779 hdac_unlock(sc); 6780 err = sysctl_handle_int(oidp, &val, 0, req); 6781 6782 if (err != 0 || req->newptr == NULL) 6783 return (err); 6784 6785 if (val < 1) 6786 val = 1; 6787 if (val > 5000) 6788 val = 5000; 6789 val = ((uint64_t)val * hz) / 1000; 6790 if (val < 1) 6791 val = 1; 6792 if (val > (hz * 5)) 6793 val = hz * 5; 6794 6795 hdac_lock(sc); 6796 sc->poll_ival = val; 6797 hdac_unlock(sc); 6798 6799 return (err); 6800} 6801 6802static int 6803sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6804{ 6805 struct hdac_softc *sc; 6806 struct hdac_codec *codec; 6807 struct hdac_devinfo *devinfo; 6808 struct hdac_widget *w; 6809 device_t dev; 6810 uint32_t res, pincap, delay; 6811 int codec_index, fg_index; 6812 int i, err, val; 6813 nid_t cad; 6814 6815 dev = oidp->oid_arg1; 6816 sc = device_get_softc(dev); 6817 if (sc == NULL) 6818 return (EINVAL); 6819 val = 0; 6820 err = sysctl_handle_int(oidp, &val, 0, req); 6821 if (err != 0 || req->newptr == NULL || val == 0) 6822 return (err); 6823 6824 /* XXX: Temporary. For debugging. */ 6825 if (val == 100) { 6826 hdac_suspend(dev); 6827 return (0); 6828 } else if (val == 101) { 6829 hdac_resume(dev); 6830 return (0); 6831 } 6832 6833 hdac_lock(sc); 6834 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 6835 codec = sc->codecs[codec_index]; 6836 if (codec == NULL) 6837 continue; 6838 cad = codec->cad; 6839 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 6840 devinfo = &codec->fgs[fg_index]; 6841 if (devinfo->node_type != 6842 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 6843 continue; 6844 6845 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 6846 codec_index, devinfo->nid); 6847 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6848 w = hdac_widget_get(devinfo, i); 6849 if (w == NULL || w->type != 6850 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6851 continue; 6852 hdac_dump_pin_config(w, w->wclass.pin.config); 6853 pincap = w->wclass.pin.cap; 6854 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 6855 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 6856 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 6857 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 6858 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 6859 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 6860 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6861 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 6862 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6863 delay = 0; 6864 hdac_command(sc, 6865 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6866 do { 6867 res = hdac_command(sc, 6868 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6869 if (res != 0x7fffffff && res != 0xffffffff) 6870 break; 6871 DELAY(10); 6872 } while (++delay < 10000); 6873 } else { 6874 delay = 0; 6875 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6876 w->nid), cad); 6877 } 6878 printf(" Sense: 0x%08x", res); 6879 if (delay > 0) 6880 printf(" delay %dus", delay * 10); 6881 } 6882 printf("\n"); 6883 } 6884 device_printf(dev, 6885 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6886 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6887 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6888 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6889 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6890 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6891 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6892 device_printf(dev, " GPI:"); 6893 res = hdac_command(sc, 6894 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6895 printf(" data=0x%08x", res); 6896 res = hdac_command(sc, 6897 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6898 cad); 6899 printf(" wake=0x%08x", res); 6900 res = hdac_command(sc, 6901 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6902 cad); 6903 printf(" unsol=0x%08x", res); 6904 res = hdac_command(sc, 6905 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6906 printf(" sticky=0x%08x\n", res); 6907 } 6908 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6909 device_printf(dev, " GPO:"); 6910 res = hdac_command(sc, 6911 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6912 printf(" data=0x%08x\n", res); 6913 } 6914 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6915 device_printf(dev, "GPIO:"); 6916 res = hdac_command(sc, 6917 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6918 printf(" data=0x%08x", res); 6919 res = hdac_command(sc, 6920 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6921 printf(" enable=0x%08x", res); 6922 res = hdac_command(sc, 6923 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6924 printf(" direction=0x%08x\n", res); 6925 res = hdac_command(sc, 6926 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6927 device_printf(dev, " wake=0x%08x", res); 6928 res = hdac_command(sc, 6929 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6930 cad); 6931 printf(" unsol=0x%08x", res); 6932 res = hdac_command(sc, 6933 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6934 printf(" sticky=0x%08x\n", res); 6935 } 6936 } 6937 } 6938 hdac_unlock(sc); 6939 return (0); 6940} 6941#endif 6942 6943static void 6944hdac_attach2(void *arg) 6945{ 6946 struct hdac_codec *codec; 6947 struct hdac_softc *sc; 6948 struct hdac_audio_ctl *ctl; 6949 uint32_t quirks_on, quirks_off; 6950 int codec_index, fg_index; 6951 int i, pdev, rdev, dmaalloc = 0; 6952 struct hdac_devinfo *devinfo; 6953 6954 sc = (struct hdac_softc *)arg; 6955 6956 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6957 6958 HDA_BOOTHVERBOSE( 6959 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 6960 quirks_on, quirks_off); 6961 ); 6962 6963 hdac_lock(sc); 6964 6965 /* Remove ourselves from the config hooks */ 6966 if (sc->intrhook.ich_func != NULL) { 6967 config_intrhook_disestablish(&sc->intrhook); 6968 sc->intrhook.ich_func = NULL; 6969 } 6970 6971 /* Start the corb and rirb engines */ 6972 HDA_BOOTHVERBOSE( 6973 device_printf(sc->dev, "Starting CORB Engine...\n"); 6974 ); 6975 hdac_corb_start(sc); 6976 HDA_BOOTHVERBOSE( 6977 device_printf(sc->dev, "Starting RIRB Engine...\n"); 6978 ); 6979 hdac_rirb_start(sc); 6980 6981 HDA_BOOTHVERBOSE( 6982 device_printf(sc->dev, 6983 "Enabling controller interrupt...\n"); 6984 ); 6985 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6986 HDAC_GCTL_UNSOL); 6987 if (sc->polling == 0) { 6988 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6989 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6990 } else { 6991 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6992 } 6993 DELAY(1000); 6994 6995 HDA_BOOTHVERBOSE( 6996 device_printf(sc->dev, 6997 "Scanning HDA codecs ...\n"); 6998 ); 6999 hdac_scan_codecs(sc); 7000 7001 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7002 codec = sc->codecs[codec_index]; 7003 if (codec == NULL) 7004 continue; 7005 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7006 devinfo = &codec->fgs[fg_index]; 7007 HDA_BOOTVERBOSE( 7008 device_printf(sc->dev, "\n"); 7009 device_printf(sc->dev, 7010 "Processing %s FG cad=%d nid=%d...\n", 7011 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7012 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7013 "unknown", 7014 devinfo->codec->cad, devinfo->nid); 7015 ); 7016 if (devinfo->node_type != 7017 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7018 HDA_BOOTHVERBOSE( 7019 device_printf(sc->dev, 7020 "Powering down...\n"); 7021 ); 7022 hdac_command(sc, 7023 HDA_CMD_SET_POWER_STATE(codec->cad, 7024 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7025 codec->cad); 7026 continue; 7027 } 7028 7029 HDA_BOOTHVERBOSE( 7030 device_printf(sc->dev, "Powering up...\n"); 7031 ); 7032 hdac_powerup(devinfo); 7033 HDA_BOOTHVERBOSE( 7034 device_printf(sc->dev, "Parsing audio FG...\n"); 7035 ); 7036 hdac_audio_parse(devinfo); 7037 HDA_BOOTHVERBOSE( 7038 device_printf(sc->dev, "Parsing Ctls...\n"); 7039 ); 7040 hdac_audio_ctl_parse(devinfo); 7041 HDA_BOOTHVERBOSE( 7042 device_printf(sc->dev, "Parsing vendor patch...\n"); 7043 ); 7044 hdac_vendor_patch_parse(devinfo); 7045 devinfo->function.audio.quirks |= quirks_on; 7046 devinfo->function.audio.quirks &= ~quirks_off; 7047 7048 HDA_BOOTHVERBOSE( 7049 device_printf(sc->dev, "Disabling nonaudio...\n"); 7050 ); 7051 hdac_audio_disable_nonaudio(devinfo); 7052 HDA_BOOTHVERBOSE( 7053 device_printf(sc->dev, "Disabling useless...\n"); 7054 ); 7055 hdac_audio_disable_useless(devinfo); 7056 HDA_BOOTVERBOSE( 7057 device_printf(sc->dev, "Patched pins configuration:\n"); 7058 hdac_dump_pin_configs(devinfo); 7059 ); 7060 HDA_BOOTHVERBOSE( 7061 device_printf(sc->dev, "Parsing pin associations...\n"); 7062 ); 7063 hdac_audio_as_parse(devinfo); 7064 HDA_BOOTHVERBOSE( 7065 device_printf(sc->dev, "Building AFG tree...\n"); 7066 ); 7067 hdac_audio_build_tree(devinfo); 7068 HDA_BOOTHVERBOSE( 7069 device_printf(sc->dev, "Disabling unassociated " 7070 "widgets...\n"); 7071 ); 7072 hdac_audio_disable_unas(devinfo); 7073 HDA_BOOTHVERBOSE( 7074 device_printf(sc->dev, "Disabling nonselected " 7075 "inputs...\n"); 7076 ); 7077 hdac_audio_disable_notselected(devinfo); 7078 HDA_BOOTHVERBOSE( 7079 device_printf(sc->dev, "Disabling useless...\n"); 7080 ); 7081 hdac_audio_disable_useless(devinfo); 7082 HDA_BOOTHVERBOSE( 7083 device_printf(sc->dev, "Disabling " 7084 "crossassociatement connections...\n"); 7085 ); 7086 hdac_audio_disable_crossas(devinfo); 7087 HDA_BOOTHVERBOSE( 7088 device_printf(sc->dev, "Disabling useless...\n"); 7089 ); 7090 hdac_audio_disable_useless(devinfo); 7091 HDA_BOOTHVERBOSE( 7092 device_printf(sc->dev, "Binding associations to channels...\n"); 7093 ); 7094 hdac_audio_bind_as(devinfo); 7095 HDA_BOOTHVERBOSE( 7096 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7097 ); 7098 hdac_audio_assign_names(devinfo); 7099 HDA_BOOTHVERBOSE( 7100 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7101 ); 7102 hdac_audio_assign_mixers(devinfo); 7103 HDA_BOOTHVERBOSE( 7104 device_printf(sc->dev, "Preparing pin controls...\n"); 7105 ); 7106 hdac_audio_prepare_pin_ctrl(devinfo); 7107 HDA_BOOTHVERBOSE( 7108 device_printf(sc->dev, "AFG commit...\n"); 7109 ); 7110 hdac_audio_commit(devinfo); 7111 HDA_BOOTHVERBOSE( 7112 device_printf(sc->dev, "Ctls commit...\n"); 7113 ); 7114 hdac_audio_ctl_commit(devinfo); 7115 HDA_BOOTHVERBOSE( 7116 device_printf(sc->dev, "HP switch init...\n"); 7117 ); 7118 hdac_hp_switch_init(devinfo); 7119 7120 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7121 dmaalloc == 0) { 7122 if (hdac_dma_alloc(sc, &sc->pos_dma, 7123 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7124 HDA_BOOTVERBOSE( 7125 device_printf(sc->dev, "Failed to " 7126 "allocate DMA pos buffer " 7127 "(non-fatal)\n"); 7128 ); 7129 } else 7130 dmaalloc = 1; 7131 } 7132 7133 i = devinfo->function.audio.playcnt; 7134 if (devinfo->function.audio.reccnt > i) 7135 i = devinfo->function.audio.reccnt; 7136 devinfo->function.audio.devs = 7137 (struct hdac_pcm_devinfo *)malloc( 7138 sizeof(struct hdac_pcm_devinfo) * i, 7139 M_HDAC, M_ZERO | M_NOWAIT); 7140 if (devinfo->function.audio.devs == NULL) { 7141 device_printf(sc->dev, 7142 "Unable to allocate memory for devices\n"); 7143 continue; 7144 } 7145 devinfo->function.audio.num_devs = i; 7146 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7147 devinfo->function.audio.devs[i].index = i; 7148 devinfo->function.audio.devs[i].devinfo = devinfo; 7149 devinfo->function.audio.devs[i].play = -1; 7150 devinfo->function.audio.devs[i].rec = -1; 7151 } 7152 pdev = 0; 7153 rdev = 0; 7154 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 7155 if (devinfo->function.audio.as[i].enable == 0) 7156 continue; 7157 if (devinfo->function.audio.as[i].dir == 7158 HDA_CTL_IN) { 7159 devinfo->function.audio.devs[rdev].rec 7160 = devinfo->function.audio.as[i].chan; 7161 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7162 &devinfo->function.audio.devs[rdev]; 7163 rdev++; 7164 } else { 7165 devinfo->function.audio.devs[pdev].play 7166 = devinfo->function.audio.as[i].chan; 7167 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7168 &devinfo->function.audio.devs[pdev]; 7169 pdev++; 7170 } 7171 } 7172 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7173 struct hdac_pcm_devinfo *pdevinfo = 7174 &devinfo->function.audio.devs[i]; 7175 pdevinfo->dev = 7176 device_add_child(sc->dev, "pcm", -1); 7177 device_set_ivars(pdevinfo->dev, 7178 (void *)pdevinfo); 7179 } 7180 7181 HDA_BOOTVERBOSE( 7182 if (devinfo->function.audio.quirks != 0) { 7183 device_printf(sc->dev, "FG config/quirks:"); 7184 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7185 if ((devinfo->function.audio.quirks & 7186 hdac_quirks_tab[i].value) == 7187 hdac_quirks_tab[i].value) 7188 printf(" %s", hdac_quirks_tab[i].key); 7189 } 7190 printf("\n"); 7191 } 7192 7193 device_printf(sc->dev, "\n"); 7194 device_printf(sc->dev, "+-------------------+\n"); 7195 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7196 device_printf(sc->dev, "+-------------------+\n"); 7197 hdac_dump_nodes(devinfo); 7198 ); 7199 7200 HDA_BOOTHVERBOSE( 7201 device_printf(sc->dev, "\n"); 7202 device_printf(sc->dev, "+------------------------+\n"); 7203 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7204 device_printf(sc->dev, "+------------------------+\n"); 7205 device_printf(sc->dev, "\n"); 7206 i = 0; 7207 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7208 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7209 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7210 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7211 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7212 ctl->index); 7213 if (ctl->childwidget != NULL) 7214 printf(" cnid %3d", ctl->childwidget->nid); 7215 else 7216 printf(" "); 7217 printf(" ossmask=0x%08x\n", 7218 ctl->ossmask); 7219 device_printf(sc->dev, 7220 " mute: %d step: %3d size: %3d off: %3d%s\n", 7221 ctl->mute, ctl->step, ctl->size, ctl->offset, 7222 (ctl->enable == 0) ? " [DISABLED]" : 7223 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7224 } 7225 ); 7226 } 7227 } 7228 hdac_unlock(sc); 7229 7230 HDA_BOOTVERBOSE( 7231 device_printf(sc->dev, "\n"); 7232 ); 7233 7234 bus_generic_attach(sc->dev); 7235 7236#ifdef SND_DYNSYSCTL 7237 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7238 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7239 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7240 sysctl_hdac_polling, "I", "Enable polling mode"); 7241 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7242 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7243 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7244 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7245 "Controller/Jack Sense polling interval (1-1000 ms)"); 7246 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7247 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7248 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7249 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7250#endif 7251} 7252 7253/**************************************************************************** 7254 * int hdac_suspend(device_t) 7255 * 7256 * Suspend and power down HDA bus and codecs. 7257 ****************************************************************************/ 7258static int 7259hdac_suspend(device_t dev) 7260{ 7261 struct hdac_softc *sc; 7262 struct hdac_codec *codec; 7263 struct hdac_devinfo *devinfo; 7264 int codec_index, fg_index, i; 7265 7266 HDA_BOOTHVERBOSE( 7267 device_printf(dev, "Suspend...\n"); 7268 ); 7269 7270 sc = device_get_softc(dev); 7271 hdac_lock(sc); 7272 7273 HDA_BOOTHVERBOSE( 7274 device_printf(dev, "Stop streams...\n"); 7275 ); 7276 for (i = 0; i < sc->num_chans; i++) { 7277 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7278 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7279 hdac_channel_stop(sc, &sc->chans[i]); 7280 } 7281 } 7282 7283 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7284 codec = sc->codecs[codec_index]; 7285 if (codec == NULL) 7286 continue; 7287 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7288 devinfo = &codec->fgs[fg_index]; 7289 HDA_BOOTHVERBOSE( 7290 device_printf(dev, 7291 "Power down FG" 7292 " cad=%d nid=%d to the D3 state...\n", 7293 codec->cad, devinfo->nid); 7294 ); 7295 hdac_command(sc, 7296 HDA_CMD_SET_POWER_STATE(codec->cad, 7297 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7298 codec->cad); 7299 } 7300 } 7301 7302 HDA_BOOTHVERBOSE( 7303 device_printf(dev, "Reset controller...\n"); 7304 ); 7305 callout_stop(&sc->poll_hda); 7306 callout_stop(&sc->poll_hdac); 7307 callout_stop(&sc->poll_jack); 7308 hdac_reset(sc, 0); 7309 hdac_unlock(sc); 7310 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7311 callout_drain(&sc->poll_hda); 7312 callout_drain(&sc->poll_hdac); 7313 callout_drain(&sc->poll_jack); 7314 7315 HDA_BOOTHVERBOSE( 7316 device_printf(dev, "Suspend done\n"); 7317 ); 7318 7319 return (0); 7320} 7321 7322/**************************************************************************** 7323 * int hdac_resume(device_t) 7324 * 7325 * Powerup and restore HDA bus and codecs state. 7326 ****************************************************************************/ 7327static int 7328hdac_resume(device_t dev) 7329{ 7330 struct hdac_softc *sc; 7331 struct hdac_codec *codec; 7332 struct hdac_devinfo *devinfo; 7333 int codec_index, fg_index, i; 7334 7335 HDA_BOOTHVERBOSE( 7336 device_printf(dev, "Resume...\n"); 7337 ); 7338 7339 sc = device_get_softc(dev); 7340 hdac_lock(sc); 7341 7342 /* Quiesce everything */ 7343 HDA_BOOTHVERBOSE( 7344 device_printf(dev, "Reset controller...\n"); 7345 ); 7346 hdac_reset(sc, 1); 7347 7348 /* Initialize the CORB and RIRB */ 7349 hdac_corb_init(sc); 7350 hdac_rirb_init(sc); 7351 7352 /* Start the corb and rirb engines */ 7353 HDA_BOOTHVERBOSE( 7354 device_printf(dev, "Starting CORB Engine...\n"); 7355 ); 7356 hdac_corb_start(sc); 7357 HDA_BOOTHVERBOSE( 7358 device_printf(dev, "Starting RIRB Engine...\n"); 7359 ); 7360 hdac_rirb_start(sc); 7361 7362 HDA_BOOTHVERBOSE( 7363 device_printf(dev, 7364 "Enabling controller interrupt...\n"); 7365 ); 7366 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7367 HDAC_GCTL_UNSOL); 7368 if (sc->polling == 0) { 7369 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7370 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7371 } else { 7372 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7373 } 7374 DELAY(1000); 7375 7376 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7377 codec = sc->codecs[codec_index]; 7378 if (codec == NULL) 7379 continue; 7380 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7381 devinfo = &codec->fgs[fg_index]; 7382 if (devinfo->node_type != 7383 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7384 HDA_BOOTHVERBOSE( 7385 device_printf(dev, 7386 "Power down unsupported non-audio FG" 7387 " cad=%d nid=%d to the D3 state...\n", 7388 codec->cad, devinfo->nid); 7389 ); 7390 hdac_command(sc, 7391 HDA_CMD_SET_POWER_STATE(codec->cad, 7392 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7393 codec->cad); 7394 continue; 7395 } 7396 7397 HDA_BOOTHVERBOSE( 7398 device_printf(dev, 7399 "Power up audio FG cad=%d nid=%d...\n", 7400 devinfo->codec->cad, devinfo->nid); 7401 ); 7402 hdac_powerup(devinfo); 7403 HDA_BOOTHVERBOSE( 7404 device_printf(dev, "AFG commit...\n"); 7405 ); 7406 hdac_audio_commit(devinfo); 7407 HDA_BOOTHVERBOSE( 7408 device_printf(dev, "Ctls commit...\n"); 7409 ); 7410 hdac_audio_ctl_commit(devinfo); 7411 HDA_BOOTHVERBOSE( 7412 device_printf(dev, "HP switch init...\n"); 7413 ); 7414 hdac_hp_switch_init(devinfo); 7415 7416 hdac_unlock(sc); 7417 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7418 struct hdac_pcm_devinfo *pdevinfo = 7419 &devinfo->function.audio.devs[i]; 7420 HDA_BOOTHVERBOSE( 7421 device_printf(pdevinfo->dev, 7422 "OSS mixer reinitialization...\n"); 7423 ); 7424 if (mixer_reinit(pdevinfo->dev) == -1) 7425 device_printf(pdevinfo->dev, 7426 "unable to reinitialize the mixer\n"); 7427 } 7428 hdac_lock(sc); 7429 } 7430 } 7431 7432 HDA_BOOTHVERBOSE( 7433 device_printf(dev, "Start streams...\n"); 7434 ); 7435 for (i = 0; i < sc->num_chans; i++) { 7436 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7437 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7438 hdac_channel_start(sc, &sc->chans[i]); 7439 } 7440 } 7441 7442 hdac_unlock(sc); 7443 7444 HDA_BOOTHVERBOSE( 7445 device_printf(dev, "Resume done\n"); 7446 ); 7447 7448 return (0); 7449} 7450/**************************************************************************** 7451 * int hdac_detach(device_t) 7452 * 7453 * Detach and free up resources utilized by the hdac device. 7454 ****************************************************************************/ 7455static int 7456hdac_detach(device_t dev) 7457{ 7458 struct hdac_softc *sc; 7459 device_t *devlist = NULL; 7460 int i, devcount; 7461 7462 sc = device_get_softc(dev); 7463 7464 device_get_children(dev, &devlist, &devcount); 7465 for (i = 0; devlist != NULL && i < devcount; i++) 7466 device_delete_child(dev, devlist[i]); 7467 if (devlist != NULL) 7468 free(devlist, M_TEMP); 7469 7470 hdac_release_resources(sc); 7471 7472 return (0); 7473} 7474 7475static device_method_t hdac_methods[] = { 7476 /* device interface */ 7477 DEVMETHOD(device_probe, hdac_probe), 7478 DEVMETHOD(device_attach, hdac_attach), 7479 DEVMETHOD(device_detach, hdac_detach), 7480 DEVMETHOD(device_suspend, hdac_suspend), 7481 DEVMETHOD(device_resume, hdac_resume), 7482 { 0, 0 } 7483}; 7484 7485static driver_t hdac_driver = { 7486 "hdac", 7487 hdac_methods, 7488 sizeof(struct hdac_softc), 7489}; 7490 7491static devclass_t hdac_devclass; 7492 7493DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7494MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7495MODULE_VERSION(snd_hda, 1); 7496 7497static int 7498hdac_pcm_probe(device_t dev) 7499{ 7500 struct hdac_pcm_devinfo *pdevinfo = 7501 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7502 char buf[128]; 7503 7504 snprintf(buf, sizeof(buf), "HDA codec #%d %s PCM #%d", 7505 pdevinfo->devinfo->codec->cad, 7506 hdac_codec_name(pdevinfo->devinfo->codec), 7507 pdevinfo->index); 7508 device_set_desc_copy(dev, buf); 7509 return (0); 7510} 7511 7512static int 7513hdac_pcm_attach(device_t dev) 7514{ 7515 struct hdac_pcm_devinfo *pdevinfo = 7516 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7517 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7518 char status[SND_STATUSLEN]; 7519 int i; 7520 7521 pdevinfo->chan_size = pcm_getbuffersize(dev, 7522 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7523 7524 HDA_BOOTVERBOSE( 7525 device_printf(dev, "+--------------------------------------+\n"); 7526 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7527 device_printf(dev, "+--------------------------------------+\n"); 7528 hdac_dump_pcmchannels(pdevinfo); 7529 device_printf(dev, "\n"); 7530 device_printf(dev, "+--------------------------------+\n"); 7531 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7532 device_printf(dev, "+--------------------------------+\n"); 7533 hdac_dump_dac(pdevinfo); 7534 hdac_dump_adc(pdevinfo); 7535 hdac_dump_mix(pdevinfo); 7536 device_printf(dev, "\n"); 7537 device_printf(dev, "+-------------------------+\n"); 7538 device_printf(dev, "| DUMPING Volume Controls |\n"); 7539 device_printf(dev, "+-------------------------+\n"); 7540 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7541 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7542 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7543 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7544 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7545 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7546 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7547 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7548 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7549 hdac_dump_ctls(pdevinfo, NULL, 0); 7550 device_printf(dev, "\n"); 7551 ); 7552 7553 if (resource_int_value(device_get_name(dev), 7554 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7555 i &= HDA_BLK_ALIGN; 7556 if (i < HDA_BLK_MIN) 7557 i = HDA_BLK_MIN; 7558 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7559 i = 0; 7560 while (pdevinfo->chan_blkcnt >> i) 7561 i++; 7562 pdevinfo->chan_blkcnt = 1 << (i - 1); 7563 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7564 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7565 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7566 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7567 } else 7568 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7569 7570 /* 7571 * We don't register interrupt handler with snd_setup_intr 7572 * in pcm device. Mark pcm device as MPSAFE manually. 7573 */ 7574 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7575 7576 HDA_BOOTHVERBOSE( 7577 device_printf(dev, "OSS mixer initialization...\n"); 7578 ); 7579 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7580 device_printf(dev, "Can't register mixer\n"); 7581 7582 HDA_BOOTHVERBOSE( 7583 device_printf(dev, "Registering PCM channels...\n"); 7584 ); 7585 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7586 (pdevinfo->rec >= 0)?1:0) != 0) 7587 device_printf(dev, "Can't register PCM\n"); 7588 7589 pdevinfo->registered++; 7590 7591 if (pdevinfo->play >= 0) 7592 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7593 if (pdevinfo->rec >= 0) 7594 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7595 7596 snprintf(status, SND_STATUSLEN, "at %s cad %d %s [%s]", 7597 device_get_nameunit(sc->dev), pdevinfo->devinfo->codec->cad, 7598 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 7599 pcm_setstatus(dev, status); 7600 7601 return (0); 7602} 7603 7604static int 7605hdac_pcm_detach(device_t dev) 7606{ 7607 struct hdac_pcm_devinfo *pdevinfo = 7608 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7609 int err; 7610 7611 if (pdevinfo->registered > 0) { 7612 err = pcm_unregister(dev); 7613 if (err != 0) 7614 return (err); 7615 } 7616 7617 return (0); 7618} 7619 7620static device_method_t hdac_pcm_methods[] = { 7621 /* device interface */ 7622 DEVMETHOD(device_probe, hdac_pcm_probe), 7623 DEVMETHOD(device_attach, hdac_pcm_attach), 7624 DEVMETHOD(device_detach, hdac_pcm_detach), 7625 { 0, 0 } 7626}; 7627 7628static driver_t hdac_pcm_driver = { 7629 "pcm", 7630 hdac_pcm_methods, 7631 PCM_SOFTC_SIZE, 7632}; 7633 7634DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7635 7636