hdac.c revision 183024
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20080913_0111" 87#define HDA_WIDGET_PARSER_REV 2 88 89SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 183024 2008-09-14 17:37:34Z mav $"); 90 91#define HDA_BOOTVERBOSE(stmt) do { \ 92 if (bootverbose != 0 || snd_verbose > 3) { \ 93 stmt \ 94 } \ 95} while(0) 96 97#if 1 98#undef HDAC_INTR_EXTRA 99#define HDAC_INTR_EXTRA 1 100#endif 101 102#define hdac_lock(sc) snd_mtxlock((sc)->lock) 103#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 104#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 105#define hdac_lockowned(sc) mtx_owned((sc)->lock) 106 107#undef HDAC_MSI_ENABLED 108#if __FreeBSD_version >= 700026 || \ 109 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 110#define HDAC_MSI_ENABLED 1 111#endif 112 113#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 114#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 115 (fl) == 0xffffffff || \ 116 (((fl) & 0xffff0000) == 0xffff0000 && \ 117 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 118 (((fl) & 0x0000ffff) == 0x0000ffff && \ 119 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 120#define HDA_MATCH_ALL 0xffffffff 121#define HDAC_INVALID 0xffffffff 122 123/* Default controller / jack sense poll: 250ms */ 124#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 125 126/* 127 * Make room for possible 4096 playback/record channels, in 100 years to come. 128 */ 129#define HDAC_TRIGGER_NONE 0x00000000 130#define HDAC_TRIGGER_PLAY 0x00000fff 131#define HDAC_TRIGGER_REC 0x00fff000 132#define HDAC_TRIGGER_UNSOL 0x80000000 133 134#define HDA_MODEL_CONSTRUCT(vendor, model) \ 135 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 136 137/* Controller models */ 138 139/* Intel */ 140#define INTEL_VENDORID 0x8086 141#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 142#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 143#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 144#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 145#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 146#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 147 148/* Nvidia */ 149#define NVIDIA_VENDORID 0x10de 150#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 151#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 152#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 153#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 154#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 155#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 156#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 157#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 158#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 159 160/* ATI */ 161#define ATI_VENDORID 0x1002 162#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 163#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 164#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 165 166/* VIA */ 167#define VIA_VENDORID 0x1106 168#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 169#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 170 171/* SiS */ 172#define SIS_VENDORID 0x1039 173#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 174#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 175 176/* OEM/subvendors */ 177 178/* Intel */ 179#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 180 181/* HP/Compaq */ 182#define HP_VENDORID 0x103c 183#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 184#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 185#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 186#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 187#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 188#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 189#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 190#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 191#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 192#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 193/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 194#define HP_NX6325_SUBVENDORX 0x103c30b0 195 196/* Dell */ 197#define DELL_VENDORID 0x1028 198#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 199#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 200#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 201#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 202#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 203#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 204#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 205 206/* Clevo */ 207#define CLEVO_VENDORID 0x1558 208#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 209#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 210 211/* Acer */ 212#define ACER_VENDORID 0x1025 213#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 214#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 215#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 216#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 217#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 218#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 219#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 220 221/* Asus */ 222#define ASUS_VENDORID 0x1043 223#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 224#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 225#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 226#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 227#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 228#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 229#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 230#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 231#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 232#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 233#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 234#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 235#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 236#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 237#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 238#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 239 240/* IBM / Lenovo */ 241#define IBM_VENDORID 0x1014 242#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 243#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 244 245/* Lenovo */ 246#define LENOVO_VENDORID 0x17aa 247#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 248#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 249#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 250#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 251 252/* Samsung */ 253#define SAMSUNG_VENDORID 0x144d 254#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 255#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 256 257/* Medion ? */ 258#define MEDION_VENDORID 0x161f 259#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 260#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 261 262/* Apple Computer Inc. */ 263#define APPLE_VENDORID 0x106b 264#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 265 266/* Sony */ 267#define SONY_VENDORID 0x104d 268#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 269#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 270 271/* 272 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 273 * instead of their own, which is beyond my comprehension 274 * (see HDA_CODEC_STAC9221 below). 275 */ 276#define APPLE_INTEL_MAC 0x76808384 277 278/* LG Electronics */ 279#define LG_VENDORID 0x1854 280#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 281#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 282 283/* Fujitsu Siemens */ 284#define FS_VENDORID 0x1734 285#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 286#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 287#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 288 289/* Fujitsu Limited */ 290#define FL_VENDORID 0x10cf 291#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 292#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 293#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 294 295/* Toshiba */ 296#define TOSHIBA_VENDORID 0x1179 297#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 298#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 299#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 300 301/* Micro-Star International (MSI) */ 302#define MSI_VENDORID 0x1462 303#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 304#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 305#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 306 307/* Giga-Byte Technology */ 308#define GB_VENDORID 0x1458 309#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 310#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 311 312/* Uniwill ? */ 313#define UNIWILL_VENDORID 0x1584 314#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 315#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 316 317 318/* Misc constants.. */ 319#define HDA_AMP_VOL_DEFAULT (-1) 320#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 321#define HDA_AMP_MUTE_NONE (0) 322#define HDA_AMP_MUTE_LEFT (1 << 0) 323#define HDA_AMP_MUTE_RIGHT (1 << 1) 324#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 325 326#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 327#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 328 329#define HDA_ADC_MONITOR (1 << 0) 330 331#define HDA_CTL_OUT 1 332#define HDA_CTL_IN 2 333 334#define HDA_GPIO_MAX 8 335/* 0 - 7 = GPIO , 8 = Flush */ 336#define HDA_QUIRK_GPIO0 (1 << 0) 337#define HDA_QUIRK_GPIO1 (1 << 1) 338#define HDA_QUIRK_GPIO2 (1 << 2) 339#define HDA_QUIRK_GPIO3 (1 << 3) 340#define HDA_QUIRK_GPIO4 (1 << 4) 341#define HDA_QUIRK_GPIO5 (1 << 5) 342#define HDA_QUIRK_GPIO6 (1 << 6) 343#define HDA_QUIRK_GPIO7 (1 << 7) 344#define HDA_QUIRK_GPIOFLUSH (1 << 8) 345 346/* 9 - 25 = anything else */ 347#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 348#define HDA_QUIRK_FIXEDRATE (1 << 10) 349#define HDA_QUIRK_FORCESTEREO (1 << 11) 350#define HDA_QUIRK_EAPDINV (1 << 12) 351#define HDA_QUIRK_DMAPOS (1 << 13) 352#define HDA_QUIRK_SENSEINV (1 << 14) 353 354/* 26 - 31 = vrefs */ 355#define HDA_QUIRK_IVREF50 (1 << 26) 356#define HDA_QUIRK_IVREF80 (1 << 27) 357#define HDA_QUIRK_IVREF100 (1 << 28) 358#define HDA_QUIRK_OVREF50 (1 << 29) 359#define HDA_QUIRK_OVREF80 (1 << 30) 360#define HDA_QUIRK_OVREF100 (1 << 31) 361 362#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 363 HDA_QUIRK_IVREF100) 364#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 365 HDA_QUIRK_OVREF100) 366#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 367 368#if __FreeBSD_version < 600000 369#define taskqueue_drain(...) 370#endif 371 372static const struct { 373 char *key; 374 uint32_t value; 375} hdac_quirks_tab[] = { 376 { "gpio0", HDA_QUIRK_GPIO0 }, 377 { "gpio1", HDA_QUIRK_GPIO1 }, 378 { "gpio2", HDA_QUIRK_GPIO2 }, 379 { "gpio3", HDA_QUIRK_GPIO3 }, 380 { "gpio4", HDA_QUIRK_GPIO4 }, 381 { "gpio5", HDA_QUIRK_GPIO5 }, 382 { "gpio6", HDA_QUIRK_GPIO6 }, 383 { "gpio7", HDA_QUIRK_GPIO7 }, 384 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 385 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 386 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 387 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 388 { "eapdinv", HDA_QUIRK_EAPDINV }, 389 { "dmapos", HDA_QUIRK_DMAPOS }, 390 { "senseinv", HDA_QUIRK_SENSEINV }, 391 { "ivref50", HDA_QUIRK_IVREF50 }, 392 { "ivref80", HDA_QUIRK_IVREF80 }, 393 { "ivref100", HDA_QUIRK_IVREF100 }, 394 { "ovref50", HDA_QUIRK_OVREF50 }, 395 { "ovref80", HDA_QUIRK_OVREF80 }, 396 { "ovref100", HDA_QUIRK_OVREF100 }, 397 { "ivref", HDA_QUIRK_IVREF }, 398 { "ovref", HDA_QUIRK_OVREF }, 399 { "vref", HDA_QUIRK_VREF }, 400}; 401#define HDAC_QUIRKS_TAB_LEN \ 402 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 403 404#define HDA_BDL_MIN 2 405#define HDA_BDL_MAX 256 406#define HDA_BDL_DEFAULT HDA_BDL_MIN 407 408#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 409#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 410 411#define HDA_BUFSZ_MIN 4096 412#define HDA_BUFSZ_MAX 65536 413#define HDA_BUFSZ_DEFAULT 16384 414 415#define HDA_PARSE_MAXDEPTH 10 416 417#define HDAC_UNSOLTAG_EVENT_HP 0x00 418 419MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 420 421const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 422 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 423 "White", "Other"}; 424 425const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 426 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 427 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 428 429const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 430 431/* Default */ 432static uint32_t hdac_fmt[] = { 433 AFMT_STEREO | AFMT_S16_LE, 434 0 435}; 436 437static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 438 439static const struct { 440 uint32_t model; 441 char *desc; 442} hdac_devices[] = { 443 { HDA_INTEL_82801F, "Intel 82801F" }, 444 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 445 { HDA_INTEL_82801G, "Intel 82801G" }, 446 { HDA_INTEL_82801H, "Intel 82801H" }, 447 { HDA_INTEL_82801I, "Intel 82801I" }, 448 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 449 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 450 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 451 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 452 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 453 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 454 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 455 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 456 { HDA_ATI_SB450, "ATI SB450" }, 457 { HDA_ATI_SB600, "ATI SB600" }, 458 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 459 { HDA_SIS_966, "SiS 966" }, 460 /* Unknown */ 461 { HDA_INTEL_ALL, "Intel (Unknown)" }, 462 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 463 { HDA_ATI_ALL, "ATI (Unknown)" }, 464 { HDA_VIA_ALL, "VIA (Unknown)" }, 465 { HDA_SIS_ALL, "SiS (Unknown)" }, 466}; 467#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 468 469static const struct { 470 uint16_t vendor; 471 uint8_t reg; 472 uint8_t mask; 473 uint8_t enable; 474} hdac_pcie_snoop[] = { 475 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 476 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 477 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 478}; 479#define HDAC_PCIESNOOP_LEN \ 480 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 481 482static const struct { 483 uint32_t rate; 484 int valid; 485 uint16_t base; 486 uint16_t mul; 487 uint16_t div; 488} hda_rate_tab[] = { 489 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 490 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 491 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 492 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 493 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 494 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 495 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 496 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 497 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 498 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 499 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 500 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 501 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 502 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 503 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 504 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 505 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 506 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 507 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 508 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 509 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 510 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 511 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 512 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 513 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 514 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 515 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 516 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 517 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 518 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 519 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 520 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 521 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 522 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 523 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 524}; 525#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 526 527/* All codecs you can eat... */ 528#define HDA_CODEC_CONSTRUCT(vendor, id) \ 529 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 530 531/* Realtek */ 532#define REALTEK_VENDORID 0x10ec 533#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 534#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 535#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 536#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 537#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 538#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 539#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 540#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 541#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 542#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 543#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 544#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 545#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 546#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 547#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 548#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 549#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 550 551/* Analog Devices */ 552#define ANALOGDEVICES_VENDORID 0x11d4 553#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 554#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 555#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 556#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 557#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 558#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 559#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 560 561/* CMedia */ 562#define CMEDIA_VENDORID 0x434d 563#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 564#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 565 566/* Sigmatel */ 567#define SIGMATEL_VENDORID 0x8384 568#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 569#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 570#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 571#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 572#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 573#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 574#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 575#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 576#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 577#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 578#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 579#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 580#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 581#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 582#define HDA_CODEC_STAC9205 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 583#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 584 585/* Silicon Image */ 586#define SII_VENDORID 0x1095 587#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 588 589/* Lucent/Agere */ 590#define AGERE_VENDORID 0x11c1 591#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 592 593/* 594 * Conexant 595 * 596 * Ok, the truth is, I don't have any idea at all whether 597 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 598 * place that tell me it is "Venice" is from its Windows driver INF. 599 * 600 * Venice - CX????? 601 * Waikiki - CX20551-22 602 */ 603#define CONEXANT_VENDORID 0x14f1 604#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 605#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 606#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 607 608/* VIA */ 609#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 610#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 611#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 612#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 613#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 614#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 615#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 616#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 617#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 618#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 619#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 620#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 621#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 622 623/* ATI */ 624#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 625 626/* NVIDIA */ 627#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 628 629/* Codecs */ 630static const struct { 631 uint32_t id; 632 char *name; 633} hdac_codecs[] = { 634 { HDA_CODEC_ALC260, "Realtek ALC260" }, 635 { HDA_CODEC_ALC262, "Realtek ALC262" }, 636 { HDA_CODEC_ALC267, "Realtek ALC267" }, 637 { HDA_CODEC_ALC268, "Realtek ALC268" }, 638 { HDA_CODEC_ALC269, "Realtek ALC269" }, 639 { HDA_CODEC_ALC272, "Realtek ALC272" }, 640 { HDA_CODEC_ALC660, "Realtek ALC660" }, 641 { HDA_CODEC_ALC662, "Realtek ALC662" }, 642 { HDA_CODEC_ALC663, "Realtek ALC663" }, 643 { HDA_CODEC_ALC861, "Realtek ALC861" }, 644 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 645 { HDA_CODEC_ALC880, "Realtek ALC880" }, 646 { HDA_CODEC_ALC882, "Realtek ALC882" }, 647 { HDA_CODEC_ALC883, "Realtek ALC883" }, 648 { HDA_CODEC_ALC885, "Realtek ALC885" }, 649 { HDA_CODEC_ALC888, "Realtek ALC888" }, 650 { HDA_CODEC_ALC889, "Realtek ALC889" }, 651 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 652 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 653 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 654 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 655 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 656 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 657 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 658 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 659 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 660 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 661 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 662 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 663 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 664 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 665 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 666 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 667 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 668 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 669 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 670 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 671 { HDA_CODEC_STAC9205, "Sigmatel STAC9205" }, 672 { HDA_CODEC_STAC9872AK,"Sigmatel STAC9872AK" }, 673 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 674 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 675 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 676 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 677 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 678 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 679 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 680 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 681 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 682 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 683 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 684 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 685 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 686 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 687 /* Unknown codec */ 688 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 689 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 690 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 691 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 692 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 693 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 694 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 695 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 696 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 697 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 698}; 699#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 700 701 702/**************************************************************************** 703 * Function prototypes 704 ****************************************************************************/ 705static void hdac_intr_handler(void *); 706static int hdac_reset(struct hdac_softc *, int); 707static int hdac_get_capabilities(struct hdac_softc *); 708static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 709static int hdac_dma_alloc(struct hdac_softc *, 710 struct hdac_dma *, bus_size_t); 711static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 712static int hdac_mem_alloc(struct hdac_softc *); 713static void hdac_mem_free(struct hdac_softc *); 714static int hdac_irq_alloc(struct hdac_softc *); 715static void hdac_irq_free(struct hdac_softc *); 716static void hdac_corb_init(struct hdac_softc *); 717static void hdac_rirb_init(struct hdac_softc *); 718static void hdac_corb_start(struct hdac_softc *); 719static void hdac_rirb_start(struct hdac_softc *); 720static void hdac_scan_codecs(struct hdac_softc *); 721static void hdac_probe_codec(struct hdac_codec *); 722static void hdac_probe_function(struct hdac_codec *, nid_t); 723static int hdac_pcmchannel_setup(struct hdac_chan *); 724 725static void hdac_attach2(void *); 726 727static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 728 uint32_t, int); 729static void hdac_command_send_internal(struct hdac_softc *, 730 struct hdac_command_list *, int); 731 732static int hdac_probe(device_t); 733static int hdac_attach(device_t); 734static int hdac_detach(device_t); 735static int hdac_suspend(device_t); 736static int hdac_resume(device_t); 737static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 738static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 739 uint32_t, int, int); 740static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 741 nid_t, int, int, int); 742static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 743 nid_t, nid_t, int, int, int, int, int, int); 744static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 745 746static int hdac_rirb_flush(struct hdac_softc *sc); 747static int hdac_unsolq_flush(struct hdac_softc *sc); 748 749static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 750 751#define hdac_command(a1, a2, a3) \ 752 hdac_command_sendone_internal(a1, a2, a3) 753 754#define hdac_codec_id(c) \ 755 ((uint32_t)((c == NULL) ? 0x00000000 : \ 756 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 757 ((uint32_t)(c)->device_id & 0x0000ffff)))) 758 759static char * 760hdac_codec_name(struct hdac_codec *codec) 761{ 762 uint32_t id; 763 int i; 764 765 id = hdac_codec_id(codec); 766 767 for (i = 0; i < HDAC_CODECS_LEN; i++) { 768 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 769 return (hdac_codecs[i].name); 770 } 771 772 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 773} 774 775static char * 776hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 777{ 778 static char *ossname[] = SOUND_DEVICE_NAMES; 779 int i, first = 1; 780 781 bzero(buf, len); 782 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 783 if (mask & (1 << i)) { 784 if (first == 0) 785 strlcat(buf, ", ", len); 786 strlcat(buf, ossname[i], len); 787 first = 0; 788 } 789 } 790 return (buf); 791} 792 793static struct hdac_audio_ctl * 794hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 795{ 796 if (devinfo == NULL || 797 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 798 index == NULL || devinfo->function.audio.ctl == NULL || 799 devinfo->function.audio.ctlcnt < 1 || 800 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 801 return (NULL); 802 return (&devinfo->function.audio.ctl[(*index)++]); 803} 804 805static struct hdac_audio_ctl * 806hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 807 int index, int cnt) 808{ 809 struct hdac_audio_ctl *ctl; 810 int i, found = 0; 811 812 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 813 return (NULL); 814 815 i = 0; 816 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 817 if (ctl->enable == 0) 818 continue; 819 if (ctl->widget->nid != nid) 820 continue; 821 if (dir && ctl->ndir != dir) 822 continue; 823 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 824 ctl->dir == ctl->ndir && ctl->index != index) 825 continue; 826 found++; 827 if (found == cnt || cnt <= 0) 828 return (ctl); 829 } 830 831 return (NULL); 832} 833 834/* 835 * Jack detection (Speaker/HP redirection) event handler. 836 */ 837static void 838hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 839{ 840 struct hdac_audio_as *as; 841 struct hdac_softc *sc; 842 struct hdac_widget *w; 843 struct hdac_audio_ctl *ctl; 844 uint32_t val, res; 845 int i, j; 846 nid_t cad; 847 848 if (devinfo == NULL || devinfo->codec == NULL || 849 devinfo->codec->sc == NULL) 850 return; 851 852 sc = devinfo->codec->sc; 853 cad = devinfo->codec->cad; 854 as = devinfo->function.audio.as; 855 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 856 if (as[i].hpredir < 0) 857 continue; 858 859 w = hdac_widget_get(devinfo, as[i].pins[15]); 860 if (w == NULL || w->enable == 0 || w->type != 861 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 862 continue; 863 864 res = hdac_command(sc, 865 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 866 867 HDA_BOOTVERBOSE( 868 device_printf(sc->dev, 869 "Pin sense: nid=%d res=0x%08x\n", 870 as[i].pins[15], res); 871 ); 872 873 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 874 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 875 res ^= 1; 876 877 /* (Un)Mute headphone pin. */ 878 ctl = hdac_audio_ctl_amp_get(devinfo, 879 as[i].pins[15], HDA_CTL_IN, -1, 1); 880 if (ctl != NULL && ctl->mute) { 881 /* If pin has muter - use it. */ 882 val = (res != 0) ? 0 : 1; 883 if (val != ctl->forcemute) { 884 ctl->forcemute = val; 885 hdac_audio_ctl_amp_set(ctl, 886 HDA_AMP_MUTE_DEFAULT, 887 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 888 } 889 } else { 890 /* If there is no muter - disable pin output. */ 891 w = hdac_widget_get(devinfo, as[i].pins[15]); 892 if (w != NULL && w->type == 893 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 894 if (res != 0) 895 val = w->wclass.pin.ctrl | 896 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 897 else 898 val = w->wclass.pin.ctrl & 899 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 900 if (val != w->wclass.pin.ctrl) { 901 w->wclass.pin.ctrl = val; 902 hdac_command(sc, 903 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 904 w->nid, w->wclass.pin.ctrl), cad); 905 } 906 } 907 } 908 /* (Un)Mute other pins. */ 909 for (j = 0; j < 15; j++) { 910 if (as[i].pins[j] <= 0) 911 continue; 912 ctl = hdac_audio_ctl_amp_get(devinfo, 913 as[i].pins[j], HDA_CTL_IN, -1, 1); 914 if (ctl != NULL && ctl->mute) { 915 /* If pin has muter - use it. */ 916 val = (res != 0) ? 1 : 0; 917 if (val == ctl->forcemute) 918 continue; 919 ctl->forcemute = val; 920 hdac_audio_ctl_amp_set(ctl, 921 HDA_AMP_MUTE_DEFAULT, 922 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 923 continue; 924 } 925 /* If there is no muter - disable pin output. */ 926 w = hdac_widget_get(devinfo, as[i].pins[j]); 927 if (w != NULL && w->type == 928 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 929 if (res != 0) 930 val = w->wclass.pin.ctrl & 931 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 932 else 933 val = w->wclass.pin.ctrl | 934 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 935 if (val != w->wclass.pin.ctrl) { 936 w->wclass.pin.ctrl = val; 937 hdac_command(sc, 938 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 939 w->nid, w->wclass.pin.ctrl), cad); 940 } 941 } 942 } 943 } 944} 945 946/* 947 * Callback for poll based jack detection. 948 */ 949static void 950hdac_jack_poll_callback(void *arg) 951{ 952 struct hdac_devinfo *devinfo = arg; 953 struct hdac_softc *sc; 954 955 if (devinfo == NULL || devinfo->codec == NULL || 956 devinfo->codec->sc == NULL) 957 return; 958 sc = devinfo->codec->sc; 959 hdac_lock(sc); 960 if (sc->poll_ival == 0) { 961 hdac_unlock(sc); 962 return; 963 } 964 hdac_hp_switch_handler(devinfo); 965 callout_reset(&sc->poll_jack, sc->poll_ival, 966 hdac_jack_poll_callback, devinfo); 967 hdac_unlock(sc); 968} 969 970/* 971 * Jack detection initializer. 972 */ 973static void 974hdac_hp_switch_init(struct hdac_devinfo *devinfo) 975{ 976 struct hdac_softc *sc = devinfo->codec->sc; 977 struct hdac_audio_as *as = devinfo->function.audio.as; 978 struct hdac_widget *w; 979 uint32_t id; 980 int i, enable = 0, poll = 0; 981 nid_t cad; 982 983 id = hdac_codec_id(devinfo->codec); 984 cad = devinfo->codec->cad; 985 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 986 if (as[i].hpredir < 0) 987 continue; 988 989 w = hdac_widget_get(devinfo, as[i].pins[15]); 990 if (w == NULL || w->enable == 0 || w->type != 991 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 992 continue; 993 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 994 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 995 device_printf(sc->dev, 996 "No jack detection support at pin %d\n", 997 as[i].pins[15]); 998 continue; 999 } 1000 enable = 1; 1001 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1002 hdac_command(sc, 1003 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1004 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1005 HDAC_UNSOLTAG_EVENT_HP), cad); 1006 } else 1007 poll = 1; 1008 HDA_BOOTVERBOSE( 1009 device_printf(sc->dev, 1010 "Enabling headphone/speaker " 1011 "audio routing switching:\n"); 1012 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1013 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1014 ); 1015 } 1016 if (enable) { 1017 hdac_hp_switch_handler(devinfo); 1018 if (poll) { 1019 callout_reset(&sc->poll_jack, 1, 1020 hdac_jack_poll_callback, devinfo); 1021 } 1022 } 1023} 1024 1025/* 1026 * Unsolicited messages handler. 1027 */ 1028static void 1029hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1030{ 1031 struct hdac_softc *sc; 1032 struct hdac_devinfo *devinfo = NULL; 1033 int i; 1034 1035 if (codec == NULL || codec->sc == NULL) 1036 return; 1037 1038 sc = codec->sc; 1039 1040 HDA_BOOTVERBOSE( 1041 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1042 ); 1043 1044 for (i = 0; i < codec->num_fgs; i++) { 1045 if (codec->fgs[i].node_type == 1046 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1047 devinfo = &codec->fgs[i]; 1048 break; 1049 } 1050 } 1051 1052 if (devinfo == NULL) 1053 return; 1054 1055 switch (tag) { 1056 case HDAC_UNSOLTAG_EVENT_HP: 1057 hdac_hp_switch_handler(devinfo); 1058 break; 1059 default: 1060 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1061 break; 1062 } 1063} 1064 1065static int 1066hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1067{ 1068 /* XXX to be removed */ 1069#ifdef HDAC_INTR_EXTRA 1070 uint32_t res; 1071#endif 1072 1073 if (!(ch->flags & HDAC_CHN_RUNNING)) 1074 return (0); 1075 1076 /* XXX to be removed */ 1077#ifdef HDAC_INTR_EXTRA 1078 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1079#endif 1080 1081 /* XXX to be removed */ 1082#ifdef HDAC_INTR_EXTRA 1083 HDA_BOOTVERBOSE( 1084 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1085 device_printf(ch->pdevinfo->dev, 1086 "PCMDIR_%s intr triggered beyond stream boundary:" 1087 "%08x\n", 1088 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1089 ); 1090#endif 1091 1092 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1093 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1094 1095 /* XXX to be removed */ 1096#ifdef HDAC_INTR_EXTRA 1097 if (res & HDAC_SDSTS_BCIS) { 1098#endif 1099 return (1); 1100 /* XXX to be removed */ 1101#ifdef HDAC_INTR_EXTRA 1102 } 1103#endif 1104 1105 return (0); 1106} 1107 1108/**************************************************************************** 1109 * void hdac_intr_handler(void *) 1110 * 1111 * Interrupt handler. Processes interrupts received from the hdac. 1112 ****************************************************************************/ 1113static void 1114hdac_intr_handler(void *context) 1115{ 1116 struct hdac_softc *sc; 1117 uint32_t intsts; 1118 uint8_t rirbsts; 1119 struct hdac_rirb *rirb_base; 1120 uint32_t trigger; 1121 int i; 1122 1123 sc = (struct hdac_softc *)context; 1124 1125 hdac_lock(sc); 1126 if (sc->polling != 0) { 1127 hdac_unlock(sc); 1128 return; 1129 } 1130 1131 /* Do we have anything to do? */ 1132 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1133 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1134 hdac_unlock(sc); 1135 return; 1136 } 1137 1138 trigger = 0; 1139 1140 /* Was this a controller interrupt? */ 1141 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1142 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1143 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1144 /* Get as many responses that we can */ 1145 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1146 HDAC_WRITE_1(&sc->mem, 1147 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1148 if (hdac_rirb_flush(sc) != 0) 1149 trigger |= HDAC_TRIGGER_UNSOL; 1150 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1151 } 1152 /* XXX to be removed */ 1153 /* Clear interrupt and exit */ 1154#ifdef HDAC_INTR_EXTRA 1155 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1156#endif 1157 } 1158 1159 if (intsts & HDAC_INTSTS_SIS_MASK) { 1160 for (i = 0; i < sc->num_chans; i++) { 1161 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1162 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1163 trigger |= (1 << i); 1164 } 1165 /* XXX to be removed */ 1166#ifdef HDAC_INTR_EXTRA 1167 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1168 HDAC_INTSTS_SIS_MASK); 1169#endif 1170 } 1171 1172 hdac_unlock(sc); 1173 1174 for (i = 0; i < sc->num_chans; i++) { 1175 if (trigger & (1 << i)) 1176 chn_intr(sc->chans[i].c); 1177 } 1178 if (trigger & HDAC_TRIGGER_UNSOL) 1179 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1180} 1181 1182/**************************************************************************** 1183 * int hdac_reset(hdac_softc *, int) 1184 * 1185 * Reset the hdac to a quiescent and known state. 1186 ****************************************************************************/ 1187static int 1188hdac_reset(struct hdac_softc *sc, int wakeup) 1189{ 1190 uint32_t gctl; 1191 int count, i; 1192 1193 /* 1194 * Stop all Streams DMA engine 1195 */ 1196 for (i = 0; i < sc->num_iss; i++) 1197 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1198 for (i = 0; i < sc->num_oss; i++) 1199 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1200 for (i = 0; i < sc->num_bss; i++) 1201 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1202 1203 /* 1204 * Stop Control DMA engines. 1205 */ 1206 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1207 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1208 1209 /* 1210 * Reset DMA position buffer. 1211 */ 1212 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1213 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1214 1215 /* 1216 * Reset the controller. The reset must remain asserted for 1217 * a minimum of 100us. 1218 */ 1219 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1220 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1221 count = 10000; 1222 do { 1223 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1224 if (!(gctl & HDAC_GCTL_CRST)) 1225 break; 1226 DELAY(10); 1227 } while (--count); 1228 if (gctl & HDAC_GCTL_CRST) { 1229 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1230 return (ENXIO); 1231 } 1232 1233 /* If wakeup is not requested - leave the controller in reset state. */ 1234 if (!wakeup) 1235 return (0); 1236 1237 DELAY(100); 1238 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1239 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1240 count = 10000; 1241 do { 1242 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1243 if (gctl & HDAC_GCTL_CRST) 1244 break; 1245 DELAY(10); 1246 } while (--count); 1247 if (!(gctl & HDAC_GCTL_CRST)) { 1248 device_printf(sc->dev, "Device stuck in reset\n"); 1249 return (ENXIO); 1250 } 1251 1252 /* 1253 * Wait for codecs to finish their own reset sequence. The delay here 1254 * should be of 250us but for some reasons, on it's not enough on my 1255 * computer. Let's use twice as much as necessary to make sure that 1256 * it's reset properly. 1257 */ 1258 DELAY(1000); 1259 1260 return (0); 1261} 1262 1263 1264/**************************************************************************** 1265 * int hdac_get_capabilities(struct hdac_softc *); 1266 * 1267 * Retreive the general capabilities of the hdac; 1268 * Number of Input Streams 1269 * Number of Output Streams 1270 * Number of bidirectional Streams 1271 * 64bit ready 1272 * CORB and RIRB sizes 1273 ****************************************************************************/ 1274static int 1275hdac_get_capabilities(struct hdac_softc *sc) 1276{ 1277 uint16_t gcap; 1278 uint8_t corbsize, rirbsize; 1279 1280 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1281 sc->num_iss = HDAC_GCAP_ISS(gcap); 1282 sc->num_oss = HDAC_GCAP_OSS(gcap); 1283 sc->num_bss = HDAC_GCAP_BSS(gcap); 1284 1285 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1286 1287 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1288 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1289 HDAC_CORBSIZE_CORBSZCAP_256) 1290 sc->corb_size = 256; 1291 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1292 HDAC_CORBSIZE_CORBSZCAP_16) 1293 sc->corb_size = 16; 1294 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1295 HDAC_CORBSIZE_CORBSZCAP_2) 1296 sc->corb_size = 2; 1297 else { 1298 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1299 __func__, corbsize); 1300 return (ENXIO); 1301 } 1302 1303 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1304 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1305 HDAC_RIRBSIZE_RIRBSZCAP_256) 1306 sc->rirb_size = 256; 1307 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1308 HDAC_RIRBSIZE_RIRBSZCAP_16) 1309 sc->rirb_size = 16; 1310 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1311 HDAC_RIRBSIZE_RIRBSZCAP_2) 1312 sc->rirb_size = 2; 1313 else { 1314 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1315 __func__, rirbsize); 1316 return (ENXIO); 1317 } 1318 1319 HDA_BOOTVERBOSE( 1320 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1321 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1322 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1323 sc->num_iss, sc->num_oss, sc->num_bss); 1324 ); 1325 1326 return (0); 1327} 1328 1329 1330/**************************************************************************** 1331 * void hdac_dma_cb 1332 * 1333 * This function is called by bus_dmamap_load when the mapping has been 1334 * established. We just record the physical address of the mapping into 1335 * the struct hdac_dma passed in. 1336 ****************************************************************************/ 1337static void 1338hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1339{ 1340 struct hdac_dma *dma; 1341 1342 if (error == 0) { 1343 dma = (struct hdac_dma *)callback_arg; 1344 dma->dma_paddr = segs[0].ds_addr; 1345 } 1346} 1347 1348 1349/**************************************************************************** 1350 * int hdac_dma_alloc 1351 * 1352 * This function allocate and setup a dma region (struct hdac_dma). 1353 * It must be freed by a corresponding hdac_dma_free. 1354 ****************************************************************************/ 1355static int 1356hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1357{ 1358 bus_size_t roundsz; 1359 int result; 1360 int lowaddr; 1361 1362 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1363 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1364 BUS_SPACE_MAXADDR_32BIT; 1365 bzero(dma, sizeof(*dma)); 1366 1367 /* 1368 * Create a DMA tag 1369 */ 1370 result = bus_dma_tag_create(NULL, /* parent */ 1371 HDAC_DMA_ALIGNMENT, /* alignment */ 1372 0, /* boundary */ 1373 lowaddr, /* lowaddr */ 1374 BUS_SPACE_MAXADDR, /* highaddr */ 1375 NULL, /* filtfunc */ 1376 NULL, /* fistfuncarg */ 1377 roundsz, /* maxsize */ 1378 1, /* nsegments */ 1379 roundsz, /* maxsegsz */ 1380 0, /* flags */ 1381 NULL, /* lockfunc */ 1382 NULL, /* lockfuncarg */ 1383 &dma->dma_tag); /* dmat */ 1384 if (result != 0) { 1385 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1386 __func__, result); 1387 goto hdac_dma_alloc_fail; 1388 } 1389 1390 /* 1391 * Allocate DMA memory 1392 */ 1393 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1394 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1395 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1396 &dma->dma_map); 1397 if (result != 0) { 1398 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1399 __func__, result); 1400 goto hdac_dma_alloc_fail; 1401 } 1402 1403 dma->dma_size = roundsz; 1404 1405 /* 1406 * Map the memory 1407 */ 1408 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1409 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1410 if (result != 0 || dma->dma_paddr == 0) { 1411 if (result == 0) 1412 result = ENOMEM; 1413 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1414 __func__, result); 1415 goto hdac_dma_alloc_fail; 1416 } 1417 1418 HDA_BOOTVERBOSE( 1419 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1420 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1421 ); 1422 1423 return (0); 1424 1425hdac_dma_alloc_fail: 1426 hdac_dma_free(sc, dma); 1427 1428 return (result); 1429} 1430 1431 1432/**************************************************************************** 1433 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1434 * 1435 * Free a struct dhac_dma that has been previously allocated via the 1436 * hdac_dma_alloc function. 1437 ****************************************************************************/ 1438static void 1439hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1440{ 1441 if (dma->dma_map != NULL) { 1442#if 0 1443 /* Flush caches */ 1444 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1445 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1446#endif 1447 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1448 } 1449 if (dma->dma_vaddr != NULL) { 1450 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1451 dma->dma_vaddr = NULL; 1452 } 1453 dma->dma_map = NULL; 1454 if (dma->dma_tag != NULL) { 1455 bus_dma_tag_destroy(dma->dma_tag); 1456 dma->dma_tag = NULL; 1457 } 1458 dma->dma_size = 0; 1459} 1460 1461/**************************************************************************** 1462 * int hdac_mem_alloc(struct hdac_softc *) 1463 * 1464 * Allocate all the bus resources necessary to speak with the physical 1465 * controller. 1466 ****************************************************************************/ 1467static int 1468hdac_mem_alloc(struct hdac_softc *sc) 1469{ 1470 struct hdac_mem *mem; 1471 1472 mem = &sc->mem; 1473 mem->mem_rid = PCIR_BAR(0); 1474 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1475 &mem->mem_rid, RF_ACTIVE); 1476 if (mem->mem_res == NULL) { 1477 device_printf(sc->dev, 1478 "%s: Unable to allocate memory resource\n", __func__); 1479 return (ENOMEM); 1480 } 1481 mem->mem_tag = rman_get_bustag(mem->mem_res); 1482 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1483 1484 return (0); 1485} 1486 1487/**************************************************************************** 1488 * void hdac_mem_free(struct hdac_softc *) 1489 * 1490 * Free up resources previously allocated by hdac_mem_alloc. 1491 ****************************************************************************/ 1492static void 1493hdac_mem_free(struct hdac_softc *sc) 1494{ 1495 struct hdac_mem *mem; 1496 1497 mem = &sc->mem; 1498 if (mem->mem_res != NULL) 1499 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1500 mem->mem_res); 1501 mem->mem_res = NULL; 1502} 1503 1504/**************************************************************************** 1505 * int hdac_irq_alloc(struct hdac_softc *) 1506 * 1507 * Allocate and setup the resources necessary for interrupt handling. 1508 ****************************************************************************/ 1509static int 1510hdac_irq_alloc(struct hdac_softc *sc) 1511{ 1512 struct hdac_irq *irq; 1513 int result; 1514 1515 irq = &sc->irq; 1516 irq->irq_rid = 0x0; 1517 1518#ifdef HDAC_MSI_ENABLED 1519 if ((sc->flags & HDAC_F_MSI) && 1520 (result = pci_msi_count(sc->dev)) == 1 && 1521 pci_alloc_msi(sc->dev, &result) == 0) 1522 irq->irq_rid = 0x1; 1523 else 1524#endif 1525 sc->flags &= ~HDAC_F_MSI; 1526 1527 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1528 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1529 if (irq->irq_res == NULL) { 1530 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1531 __func__); 1532 goto hdac_irq_alloc_fail; 1533 } 1534 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1535 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1536 if (result != 0) { 1537 device_printf(sc->dev, 1538 "%s: Unable to setup interrupt handler (%x)\n", 1539 __func__, result); 1540 goto hdac_irq_alloc_fail; 1541 } 1542 1543 return (0); 1544 1545hdac_irq_alloc_fail: 1546 hdac_irq_free(sc); 1547 1548 return (ENXIO); 1549} 1550 1551/**************************************************************************** 1552 * void hdac_irq_free(struct hdac_softc *) 1553 * 1554 * Free up resources previously allocated by hdac_irq_alloc. 1555 ****************************************************************************/ 1556static void 1557hdac_irq_free(struct hdac_softc *sc) 1558{ 1559 struct hdac_irq *irq; 1560 1561 irq = &sc->irq; 1562 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1563 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1564 if (irq->irq_res != NULL) 1565 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1566 irq->irq_res); 1567#ifdef HDAC_MSI_ENABLED 1568 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1569 pci_release_msi(sc->dev); 1570#endif 1571 irq->irq_handle = NULL; 1572 irq->irq_res = NULL; 1573 irq->irq_rid = 0x0; 1574} 1575 1576/**************************************************************************** 1577 * void hdac_corb_init(struct hdac_softc *) 1578 * 1579 * Initialize the corb registers for operations but do not start it up yet. 1580 * The CORB engine must not be running when this function is called. 1581 ****************************************************************************/ 1582static void 1583hdac_corb_init(struct hdac_softc *sc) 1584{ 1585 uint8_t corbsize; 1586 uint64_t corbpaddr; 1587 1588 /* Setup the CORB size. */ 1589 switch (sc->corb_size) { 1590 case 256: 1591 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1592 break; 1593 case 16: 1594 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1595 break; 1596 case 2: 1597 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1598 break; 1599 default: 1600 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1601 } 1602 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1603 1604 /* Setup the CORB Address in the hdac */ 1605 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1606 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1607 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1608 1609 /* Set the WP and RP */ 1610 sc->corb_wp = 0; 1611 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1612 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1613 /* 1614 * The HDA specification indicates that the CORBRPRST bit will always 1615 * read as zero. Unfortunately, it seems that at least the 82801G 1616 * doesn't reset the bit to zero, which stalls the corb engine. 1617 * manually reset the bit to zero before continuing. 1618 */ 1619 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1620 1621 /* Enable CORB error reporting */ 1622#if 0 1623 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1624#endif 1625} 1626 1627/**************************************************************************** 1628 * void hdac_rirb_init(struct hdac_softc *) 1629 * 1630 * Initialize the rirb registers for operations but do not start it up yet. 1631 * The RIRB engine must not be running when this function is called. 1632 ****************************************************************************/ 1633static void 1634hdac_rirb_init(struct hdac_softc *sc) 1635{ 1636 uint8_t rirbsize; 1637 uint64_t rirbpaddr; 1638 1639 /* Setup the RIRB size. */ 1640 switch (sc->rirb_size) { 1641 case 256: 1642 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1643 break; 1644 case 16: 1645 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1646 break; 1647 case 2: 1648 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1649 break; 1650 default: 1651 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1652 } 1653 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1654 1655 /* Setup the RIRB Address in the hdac */ 1656 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1657 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1658 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1659 1660 /* Setup the WP and RP */ 1661 sc->rirb_rp = 0; 1662 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1663 1664 /* Setup the interrupt threshold */ 1665 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1666 1667 /* Enable Overrun and response received reporting */ 1668#if 0 1669 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1670 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1671#else 1672 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1673#endif 1674 1675#if 0 1676 /* 1677 * Make sure that the Host CPU cache doesn't contain any dirty 1678 * cache lines that falls in the rirb. If I understood correctly, it 1679 * should be sufficient to do this only once as the rirb is purely 1680 * read-only from now on. 1681 */ 1682 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1683 BUS_DMASYNC_PREREAD); 1684#endif 1685} 1686 1687/**************************************************************************** 1688 * void hdac_corb_start(hdac_softc *) 1689 * 1690 * Startup the corb DMA engine 1691 ****************************************************************************/ 1692static void 1693hdac_corb_start(struct hdac_softc *sc) 1694{ 1695 uint32_t corbctl; 1696 1697 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1698 corbctl |= HDAC_CORBCTL_CORBRUN; 1699 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1700} 1701 1702/**************************************************************************** 1703 * void hdac_rirb_start(hdac_softc *) 1704 * 1705 * Startup the rirb DMA engine 1706 ****************************************************************************/ 1707static void 1708hdac_rirb_start(struct hdac_softc *sc) 1709{ 1710 uint32_t rirbctl; 1711 1712 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1713 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1714 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1715} 1716 1717 1718/**************************************************************************** 1719 * void hdac_scan_codecs(struct hdac_softc *, int) 1720 * 1721 * Scan the bus for available codecs, starting with num. 1722 ****************************************************************************/ 1723static void 1724hdac_scan_codecs(struct hdac_softc *sc) 1725{ 1726 struct hdac_codec *codec; 1727 int i; 1728 uint16_t statests; 1729 1730 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1731 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1732 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1733 /* We have found a codec. */ 1734 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1735 M_HDAC, M_ZERO | M_NOWAIT); 1736 if (codec == NULL) { 1737 device_printf(sc->dev, 1738 "Unable to allocate memory for codec\n"); 1739 continue; 1740 } 1741 codec->commands = NULL; 1742 codec->responses_received = 0; 1743 codec->verbs_sent = 0; 1744 codec->sc = sc; 1745 codec->cad = i; 1746 sc->codecs[i] = codec; 1747 hdac_probe_codec(codec); 1748 } 1749 } 1750 /* All codecs have been probed, now try to attach drivers to them */ 1751 /* bus_generic_attach(sc->dev); */ 1752} 1753 1754/**************************************************************************** 1755 * void hdac_probe_codec(struct hdac_softc *, int) 1756 * 1757 * Probe a the given codec_id for available function groups. 1758 ****************************************************************************/ 1759static void 1760hdac_probe_codec(struct hdac_codec *codec) 1761{ 1762 struct hdac_softc *sc = codec->sc; 1763 uint32_t vendorid, revisionid, subnode; 1764 int startnode; 1765 int endnode; 1766 int i; 1767 nid_t cad = codec->cad; 1768 1769 HDA_BOOTVERBOSE( 1770 device_printf(sc->dev, "Probing codec %d...\n", cad); 1771 ); 1772 vendorid = hdac_command(sc, 1773 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1774 cad); 1775 revisionid = hdac_command(sc, 1776 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1777 cad); 1778 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1779 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1780 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1781 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1782 1783 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1784 device_printf(sc->dev, "Codec #%d is not responding!" 1785 " Probing aborted.\n", cad); 1786 return; 1787 } 1788 1789 device_printf(sc->dev, "<HDA Codec #%d: %s>\n", 1790 cad, hdac_codec_name(codec)); 1791 HDA_BOOTVERBOSE( 1792 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 1793 hdac_codec_id(codec)); 1794 device_printf(sc->dev, " Vendor: 0x%04x\n", 1795 codec->vendor_id); 1796 device_printf(sc->dev, " Device: 0x%04x\n", 1797 codec->device_id); 1798 device_printf(sc->dev, " Revision: 0x%02x\n", 1799 codec->revision_id); 1800 device_printf(sc->dev, " Stepping: 0x%02x\n", 1801 codec->stepping_id); 1802 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1803 sc->pci_subvendor); 1804 ); 1805 subnode = hdac_command(sc, 1806 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1807 cad); 1808 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1809 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1810 1811 HDA_BOOTVERBOSE( 1812 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1813 startnode, endnode); 1814 ); 1815 1816 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1817 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1818 if (codec->fgs == NULL) { 1819 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 1820 __func__); 1821 return; 1822 } 1823 1824 for (i = startnode; i < endnode; i++) 1825 hdac_probe_function(codec, i); 1826 return; 1827} 1828 1829/* 1830 * Probe codec function and add it to the list. 1831 */ 1832static void 1833hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1834{ 1835 struct hdac_softc *sc = codec->sc; 1836 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1837 uint32_t fctgrptype; 1838 uint32_t res; 1839 nid_t cad = codec->cad; 1840 1841 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1842 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1843 1844 devinfo->nid = nid; 1845 devinfo->node_type = fctgrptype; 1846 devinfo->codec = codec; 1847 1848 res = hdac_command(sc, 1849 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1850 1851 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1852 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1853 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1854 1855 HDA_BOOTVERBOSE( 1856 device_printf(sc->dev, 1857 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1858 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1859 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1860 "unknown", nid, devinfo->startnode, devinfo->endnode, 1861 devinfo->nodecnt); 1862 ); 1863 1864 if (devinfo->nodecnt > 0) 1865 devinfo->widget = (struct hdac_widget *)malloc( 1866 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1867 M_NOWAIT | M_ZERO); 1868 else 1869 devinfo->widget = NULL; 1870 1871 if (devinfo->widget == NULL) { 1872 device_printf(sc->dev, "unable to allocate widgets!\n"); 1873 devinfo->endnode = devinfo->startnode; 1874 devinfo->nodecnt = 0; 1875 return; 1876 } 1877 1878 codec->num_fgs++; 1879} 1880 1881static void 1882hdac_widget_connection_parse(struct hdac_widget *w) 1883{ 1884 struct hdac_softc *sc = w->devinfo->codec->sc; 1885 uint32_t res; 1886 int i, j, max, ents, entnum; 1887 nid_t cad = w->devinfo->codec->cad; 1888 nid_t nid = w->nid; 1889 nid_t cnid, addcnid, prevcnid; 1890 1891 w->nconns = 0; 1892 1893 res = hdac_command(sc, 1894 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1895 1896 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1897 1898 if (ents < 1) 1899 return; 1900 1901 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1902 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1903 prevcnid = 0; 1904 1905#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1906#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1907#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1908#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1909#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1910 1911 for (i = 0; i < ents; i += entnum) { 1912 res = hdac_command(sc, 1913 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1914 for (j = 0; j < entnum; j++) { 1915 cnid = CONN_CNID(res, entnum, j); 1916 if (cnid == 0) { 1917 if (w->nconns < ents) 1918 device_printf(sc->dev, 1919 "%s: nid=%d WARNING: zero cnid " 1920 "entnum=%d j=%d index=%d " 1921 "entries=%d found=%d res=0x%08x\n", 1922 __func__, nid, entnum, j, i, 1923 ents, w->nconns, res); 1924 else 1925 goto getconns_out; 1926 } 1927 if (cnid < w->devinfo->startnode || 1928 cnid >= w->devinfo->endnode) { 1929 HDA_BOOTVERBOSE( 1930 device_printf(sc->dev, 1931 "GHOST: nid=%d j=%d " 1932 "entnum=%d index=%d res=0x%08x\n", 1933 nid, j, entnum, i, res); 1934 ); 1935 } 1936 if (CONN_RANGE(res, entnum, j) == 0) 1937 addcnid = cnid; 1938 else if (prevcnid == 0 || prevcnid >= cnid) { 1939 device_printf(sc->dev, 1940 "%s: WARNING: Invalid child range " 1941 "nid=%d index=%d j=%d entnum=%d " 1942 "prevcnid=%d cnid=%d res=0x%08x\n", 1943 __func__, nid, i, j, entnum, prevcnid, 1944 cnid, res); 1945 addcnid = cnid; 1946 } else 1947 addcnid = prevcnid + 1; 1948 while (addcnid <= cnid) { 1949 if (w->nconns > max) { 1950 device_printf(sc->dev, 1951 "Adding %d (nid=%d): " 1952 "Max connection reached! max=%d\n", 1953 addcnid, nid, max + 1); 1954 goto getconns_out; 1955 } 1956 w->connsenable[w->nconns] = 1; 1957 w->conns[w->nconns++] = addcnid++; 1958 } 1959 prevcnid = cnid; 1960 } 1961 } 1962 1963getconns_out: 1964 return; 1965} 1966 1967static uint32_t 1968hdac_widget_pin_patch(uint32_t config, const char *str) 1969{ 1970 char buf[256]; 1971 char *key, *value, *rest, *bad; 1972 int ival, i; 1973 1974 strlcpy(buf, str, sizeof(buf)); 1975 rest = buf; 1976 while ((key = strsep(&rest, "=")) != NULL) { 1977 value = strsep(&rest, " \t"); 1978 if (value == NULL) 1979 break; 1980 ival = strtol(value, &bad, 10); 1981 if (strcmp(key, "seq") == 0) { 1982 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 1983 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 1984 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 1985 } else if (strcmp(key, "as") == 0) { 1986 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 1987 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 1988 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 1989 } else if (strcmp(key, "misc") == 0) { 1990 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 1991 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 1992 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 1993 } else if (strcmp(key, "color") == 0) { 1994 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 1995 if (bad[0] == 0) { 1996 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 1997 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 1998 }; 1999 for (i = 0; i < 16; i++) { 2000 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2001 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2002 break; 2003 } 2004 } 2005 } else if (strcmp(key, "ctype") == 0) { 2006 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2007 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2008 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2009 } else if (strcmp(key, "device") == 0) { 2010 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2011 if (bad[0] == 0) { 2012 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2013 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2014 continue; 2015 }; 2016 for (i = 0; i < 16; i++) { 2017 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2018 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2019 break; 2020 } 2021 } 2022 } else if (strcmp(key, "loc") == 0) { 2023 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2024 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2025 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2026 } else if (strcmp(key, "conn") == 0) { 2027 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2028 if (bad[0] == 0) { 2029 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2030 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2031 continue; 2032 }; 2033 for (i = 0; i < 4; i++) { 2034 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2035 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2036 break; 2037 } 2038 } 2039 } 2040 } 2041 return (config); 2042} 2043 2044static uint32_t 2045hdac_widget_pin_getconfig(struct hdac_widget *w) 2046{ 2047 struct hdac_softc *sc; 2048 uint32_t config, orig, id; 2049 nid_t cad, nid; 2050 char buf[32]; 2051 const char *res = NULL, *patch = NULL; 2052 2053 sc = w->devinfo->codec->sc; 2054 cad = w->devinfo->codec->cad; 2055 nid = w->nid; 2056 id = hdac_codec_id(w->devinfo->codec); 2057 2058 config = hdac_command(sc, 2059 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2060 cad); 2061 orig = config; 2062 2063 HDA_BOOTVERBOSE( 2064 hdac_dump_pin_config(w, orig); 2065 ); 2066 2067 /* XXX: Old patches require complete review. 2068 * Now they may create more problem then solve due to 2069 * incorrect associations. 2070 */ 2071 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2072 switch (nid) { 2073 case 26: 2074 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2075 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2076 break; 2077 case 27: 2078 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2079 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2080 break; 2081 default: 2082 break; 2083 } 2084 } else if (id == HDA_CODEC_ALC880 && 2085 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2086 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2087 /* 2088 * Super broken BIOS 2089 */ 2090 switch (nid) { 2091 case 24: /* MIC1 */ 2092 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2093 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2094 break; 2095 case 25: /* XXX MIC2 */ 2096 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2097 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2098 break; 2099 case 26: /* LINE1 */ 2100 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2101 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2102 break; 2103 case 27: /* XXX LINE2 */ 2104 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2105 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2106 break; 2107 case 28: /* CD */ 2108 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2109 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2110 break; 2111 } 2112 } else if (id == HDA_CODEC_ALC883 && 2113 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2114 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2115 switch (nid) { 2116 case 25: 2117 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2118 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2119 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2120 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2121 break; 2122 case 28: 2123 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2124 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2125 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2126 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2127 break; 2128 } 2129 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2130 HP_V3000_SUBVENDOR) { 2131 switch (nid) { 2132 case 18: 2133 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2134 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2135 break; 2136 case 20: 2137 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2138 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2139 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2140 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2141 break; 2142 case 21: 2143 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2144 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2145 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2146 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2147 break; 2148 } 2149 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2150 HP_DV5000_SUBVENDOR) { 2151 switch (nid) { 2152 case 20: 2153 case 21: 2154 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2155 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2156 break; 2157 } 2158 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2159 ASUS_W6F_SUBVENDOR) { 2160 switch (nid) { 2161 case 11: 2162 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2163 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2164 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2165 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2166 break; 2167 case 12: 2168 case 14: 2169 case 16: 2170 case 31: 2171 case 32: 2172 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2173 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2174 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2175 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2176 break; 2177 case 15: 2178 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2179 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2180 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2181 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2182 break; 2183 } 2184 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2185 UNIWILL_9075_SUBVENDOR) { 2186 switch (nid) { 2187 case 15: 2188 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2189 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2190 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2191 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2192 break; 2193 } 2194 } 2195 2196 /* New patches */ 2197 if (id == HDA_CODEC_AD1986A && 2198 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2199 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2200 switch (nid) { 2201 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2202 patch = "device=Line-in as=8 seq=1"; 2203 break; 2204 case 29: 2205 patch = "device=Mic as=8 seq=2"; 2206 break; 2207 case 31: /* Lot of inputs configured with as=15 and unusable */ 2208 patch = "as=8 seq=3"; 2209 break; 2210 case 32: 2211 patch = "as=8 seq=4"; 2212 break; 2213 case 34: 2214 patch = "as=8 seq=5"; 2215 break; 2216 case 36: 2217 patch = "as=8 seq=6"; 2218 break; 2219 } 2220 } else if (id == HDA_CODEC_ALC260 && 2221 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2222 switch (nid) { 2223 case 16: 2224 patch = "seq=15 device=Headphones"; 2225 break; 2226 } 2227 } else if (id == HDA_CODEC_ALC268 && 2228 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2229 switch (nid) { 2230 case 28: 2231 patch = "device=CD conn=fixed"; 2232 break; 2233 } 2234 } 2235 2236 if (patch != NULL) 2237 config = hdac_widget_pin_patch(config, patch); 2238 2239 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2240 if (resource_string_value(device_get_name(sc->dev), 2241 device_get_unit(sc->dev), buf, &res) == 0) { 2242 if (strncmp(res, "0x", 2) == 0) { 2243 config = strtol(res + 2, NULL, 16); 2244 } else { 2245 config = hdac_widget_pin_patch(config, res); 2246 } 2247 } 2248 2249 HDA_BOOTVERBOSE( 2250 if (config != orig) 2251 device_printf(sc->dev, 2252 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2253 nid, orig, config); 2254 ); 2255 2256 return (config); 2257} 2258 2259static uint32_t 2260hdac_widget_pin_getcaps(struct hdac_widget *w) 2261{ 2262 struct hdac_softc *sc; 2263 uint32_t caps, orig, id; 2264 nid_t cad, nid; 2265 2266 sc = w->devinfo->codec->sc; 2267 cad = w->devinfo->codec->cad; 2268 nid = w->nid; 2269 id = hdac_codec_id(w->devinfo->codec); 2270 2271 caps = hdac_command(sc, 2272 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2273 orig = caps; 2274 2275 HDA_BOOTVERBOSE( 2276 if (caps != orig) 2277 device_printf(sc->dev, 2278 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2279 nid, orig, caps); 2280 ); 2281 2282 return (caps); 2283} 2284 2285static void 2286hdac_widget_pin_parse(struct hdac_widget *w) 2287{ 2288 struct hdac_softc *sc = w->devinfo->codec->sc; 2289 uint32_t config, pincap; 2290 const char *devstr, *connstr; 2291 nid_t cad = w->devinfo->codec->cad; 2292 nid_t nid = w->nid; 2293 2294 config = hdac_widget_pin_getconfig(w); 2295 w->wclass.pin.config = config; 2296 2297 pincap = hdac_widget_pin_getcaps(w); 2298 w->wclass.pin.cap = pincap; 2299 2300 w->wclass.pin.ctrl = hdac_command(sc, 2301 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2302 2303 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2304 w->param.eapdbtl = hdac_command(sc, 2305 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2306 w->param.eapdbtl &= 0x7; 2307 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2308 } else 2309 w->param.eapdbtl = HDAC_INVALID; 2310 2311 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2312 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2313 2314 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2315 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2316 2317 strlcat(w->name, ": ", sizeof(w->name)); 2318 strlcat(w->name, devstr, sizeof(w->name)); 2319 strlcat(w->name, " (", sizeof(w->name)); 2320 strlcat(w->name, connstr, sizeof(w->name)); 2321 strlcat(w->name, ")", sizeof(w->name)); 2322} 2323 2324static uint32_t 2325hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2326{ 2327 struct hdac_softc *sc; 2328 uint32_t caps, orig, id; 2329 nid_t cad, nid, beeper = -1; 2330 2331 sc = w->devinfo->codec->sc; 2332 cad = w->devinfo->codec->cad; 2333 nid = w->nid; 2334 id = hdac_codec_id(w->devinfo->codec); 2335 2336 caps = hdac_command(sc, 2337 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2338 cad); 2339 orig = caps; 2340 2341 /* On some codecs beeper is an input pin, but it is not recordable 2342 alone. Also most of BIOSes does not declare beeper pin. 2343 Change beeper pin node type to beeper to help parser. */ 2344 *waspin = 0; 2345 switch (id) { 2346 case HDA_CODEC_AD1988: 2347 case HDA_CODEC_AD1988B: 2348 beeper = 26; 2349 break; 2350 case HDA_CODEC_ALC260: 2351 beeper = 23; 2352 break; 2353 case HDA_CODEC_ALC262: 2354 case HDA_CODEC_ALC268: 2355 case HDA_CODEC_ALC880: 2356 case HDA_CODEC_ALC882: 2357 case HDA_CODEC_ALC883: 2358 case HDA_CODEC_ALC885: 2359 case HDA_CODEC_ALC888: 2360 case HDA_CODEC_ALC889: 2361 beeper = 29; 2362 break; 2363 } 2364 if (nid == beeper) { 2365 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2366 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2367 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2368 *waspin = 1; 2369 } 2370 2371 HDA_BOOTVERBOSE( 2372 if (caps != orig) { 2373 device_printf(sc->dev, 2374 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2375 nid, orig, caps); 2376 } 2377 ); 2378 2379 return (caps); 2380} 2381 2382static void 2383hdac_widget_parse(struct hdac_widget *w) 2384{ 2385 struct hdac_softc *sc = w->devinfo->codec->sc; 2386 uint32_t wcap, cap; 2387 char *typestr; 2388 nid_t cad = w->devinfo->codec->cad; 2389 nid_t nid = w->nid; 2390 2391 wcap = hdac_widget_getcaps(w, &w->waspin); 2392 2393 w->param.widget_cap = wcap; 2394 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2395 2396 switch (w->type) { 2397 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2398 typestr = "audio output"; 2399 break; 2400 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2401 typestr = "audio input"; 2402 break; 2403 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2404 typestr = "audio mixer"; 2405 break; 2406 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2407 typestr = "audio selector"; 2408 break; 2409 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2410 typestr = "pin"; 2411 break; 2412 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2413 typestr = "power widget"; 2414 break; 2415 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2416 typestr = "volume widget"; 2417 break; 2418 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2419 typestr = "beep widget"; 2420 break; 2421 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2422 typestr = "vendor widget"; 2423 break; 2424 default: 2425 typestr = "unknown type"; 2426 break; 2427 } 2428 2429 strlcpy(w->name, typestr, sizeof(w->name)); 2430 2431 hdac_widget_connection_parse(w); 2432 2433 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2434 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2435 w->param.outamp_cap = 2436 hdac_command(sc, 2437 HDA_CMD_GET_PARAMETER(cad, nid, 2438 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2439 else 2440 w->param.outamp_cap = 2441 w->devinfo->function.audio.outamp_cap; 2442 } else 2443 w->param.outamp_cap = 0; 2444 2445 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2446 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2447 w->param.inamp_cap = 2448 hdac_command(sc, 2449 HDA_CMD_GET_PARAMETER(cad, nid, 2450 HDA_PARAM_INPUT_AMP_CAP), cad); 2451 else 2452 w->param.inamp_cap = 2453 w->devinfo->function.audio.inamp_cap; 2454 } else 2455 w->param.inamp_cap = 0; 2456 2457 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2458 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2459 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2460 cap = hdac_command(sc, 2461 HDA_CMD_GET_PARAMETER(cad, nid, 2462 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2463 w->param.supp_stream_formats = (cap != 0) ? cap : 2464 w->devinfo->function.audio.supp_stream_formats; 2465 cap = hdac_command(sc, 2466 HDA_CMD_GET_PARAMETER(cad, nid, 2467 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2468 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2469 w->devinfo->function.audio.supp_pcm_size_rate; 2470 } else { 2471 w->param.supp_stream_formats = 2472 w->devinfo->function.audio.supp_stream_formats; 2473 w->param.supp_pcm_size_rate = 2474 w->devinfo->function.audio.supp_pcm_size_rate; 2475 } 2476 } else { 2477 w->param.supp_stream_formats = 0; 2478 w->param.supp_pcm_size_rate = 0; 2479 } 2480 2481 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2482 hdac_widget_pin_parse(w); 2483} 2484 2485static struct hdac_widget * 2486hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2487{ 2488 if (devinfo == NULL || devinfo->widget == NULL || 2489 nid < devinfo->startnode || nid >= devinfo->endnode) 2490 return (NULL); 2491 return (&devinfo->widget[nid - devinfo->startnode]); 2492} 2493 2494static __inline int 2495hda_poll_channel(struct hdac_chan *ch) 2496{ 2497 uint32_t sz, delta; 2498 volatile uint32_t ptr; 2499 2500 if (!(ch->flags & HDAC_CHN_RUNNING)) 2501 return (0); 2502 2503 sz = ch->blksz * ch->blkcnt; 2504 if (ch->dmapos != NULL) 2505 ptr = *(ch->dmapos); 2506 else 2507 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2508 ch->off + HDAC_SDLPIB); 2509 ch->ptr = ptr; 2510 ptr %= sz; 2511 ptr &= ~(ch->blksz - 1); 2512 delta = (sz + ptr - ch->prevptr) % sz; 2513 2514 if (delta < ch->blksz) 2515 return (0); 2516 2517 ch->prevptr = ptr; 2518 2519 return (1); 2520} 2521 2522static void 2523hda_poll_callback(void *arg) 2524{ 2525 struct hdac_softc *sc = arg; 2526 uint32_t trigger; 2527 int i, active = 0; 2528 2529 if (sc == NULL) 2530 return; 2531 2532 hdac_lock(sc); 2533 if (sc->polling == 0) { 2534 hdac_unlock(sc); 2535 return; 2536 } 2537 2538 trigger = 0; 2539 for (i = 0; i < sc->num_chans; i++) { 2540 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2541 continue; 2542 active = 1; 2543 if (hda_poll_channel(&sc->chans[i])) 2544 trigger |= (1 << i); 2545 } 2546 2547 /* XXX */ 2548 if (active) 2549 callout_reset(&sc->poll_hda, sc->poll_ticks, 2550 hda_poll_callback, sc); 2551 2552 hdac_unlock(sc); 2553 2554 for (i = 0; i < sc->num_chans; i++) { 2555 if (trigger & (1 << i)) 2556 chn_intr(sc->chans[i].c); 2557 } 2558} 2559 2560static int 2561hdac_rirb_flush(struct hdac_softc *sc) 2562{ 2563 struct hdac_rirb *rirb_base, *rirb; 2564 struct hdac_codec *codec; 2565 struct hdac_command_list *commands; 2566 nid_t cad; 2567 uint32_t resp; 2568 uint8_t rirbwp; 2569 int ret; 2570 2571 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2572 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2573#if 0 2574 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2575 BUS_DMASYNC_POSTREAD); 2576#endif 2577 2578 ret = 0; 2579 2580 while (sc->rirb_rp != rirbwp) { 2581 sc->rirb_rp++; 2582 sc->rirb_rp %= sc->rirb_size; 2583 rirb = &rirb_base[sc->rirb_rp]; 2584 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2585 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2586 sc->codecs[cad] == NULL) 2587 continue; 2588 resp = rirb->response; 2589 codec = sc->codecs[cad]; 2590 commands = codec->commands; 2591 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2592 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2593 ((resp >> 26) & 0xffff); 2594 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2595 } else if (commands != NULL && commands->num_commands > 0 && 2596 codec->responses_received < commands->num_commands) 2597 commands->responses[codec->responses_received++] = 2598 resp; 2599 ret++; 2600 } 2601 2602 return (ret); 2603} 2604 2605static int 2606hdac_unsolq_flush(struct hdac_softc *sc) 2607{ 2608 nid_t cad; 2609 uint32_t tag; 2610 int ret = 0; 2611 2612 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2613 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2614 while (sc->unsolq_rp != sc->unsolq_wp) { 2615 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2616 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2617 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2618 hdac_unsolicited_handler(sc->codecs[cad], tag); 2619 ret++; 2620 } 2621 sc->unsolq_st = HDAC_UNSOLQ_READY; 2622 } 2623 2624 return (ret); 2625} 2626 2627static void 2628hdac_poll_callback(void *arg) 2629{ 2630 struct hdac_softc *sc = arg; 2631 if (sc == NULL) 2632 return; 2633 2634 hdac_lock(sc); 2635 if (sc->polling == 0 || sc->poll_ival == 0) { 2636 hdac_unlock(sc); 2637 return; 2638 } 2639 if (hdac_rirb_flush(sc) != 0) 2640 hdac_unsolq_flush(sc); 2641 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2642 hdac_unlock(sc); 2643} 2644 2645static void 2646hdac_poll_reinit(struct hdac_softc *sc) 2647{ 2648 int i, pollticks, min = 1000000; 2649 struct hdac_chan *ch; 2650 2651 for (i = 0; i < sc->num_chans; i++) { 2652 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2653 continue; 2654 ch = &sc->chans[i]; 2655 pollticks = ((uint64_t)hz * ch->blksz) / 2656 ((uint64_t)sndbuf_getbps(ch->b) * 2657 sndbuf_getspd(ch->b)); 2658 pollticks >>= 1; 2659 if (pollticks > hz) 2660 pollticks = hz; 2661 if (pollticks < 1) { 2662 HDA_BOOTVERBOSE( 2663 device_printf(sc->dev, 2664 "%s: pollticks=%d < 1 !\n", 2665 __func__, pollticks); 2666 ); 2667 pollticks = 1; 2668 } 2669 if (min > pollticks) 2670 min = pollticks; 2671 } 2672 HDA_BOOTVERBOSE( 2673 device_printf(sc->dev, 2674 "%s: pollticks %d -> %d\n", 2675 __func__, sc->poll_ticks, min); 2676 ); 2677 sc->poll_ticks = min; 2678 if (min == 1000000) 2679 callout_stop(&sc->poll_hda); 2680 else 2681 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2682} 2683 2684static void 2685hdac_stream_stop(struct hdac_chan *ch) 2686{ 2687 struct hdac_softc *sc = ch->devinfo->codec->sc; 2688 uint32_t ctl; 2689 2690 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2691 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2692 HDAC_SDCTL_RUN); 2693 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2694 2695 ch->flags &= ~HDAC_CHN_RUNNING; 2696 2697 if (sc->polling != 0) 2698 hdac_poll_reinit(sc); 2699 2700 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2701 ctl &= ~(1 << (ch->off >> 5)); 2702 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2703} 2704 2705static void 2706hdac_stream_start(struct hdac_chan *ch) 2707{ 2708 struct hdac_softc *sc = ch->devinfo->codec->sc; 2709 uint32_t ctl; 2710 2711 ch->flags |= HDAC_CHN_RUNNING; 2712 2713 if (sc->polling != 0) 2714 hdac_poll_reinit(sc); 2715 2716 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2717 ctl |= 1 << (ch->off >> 5); 2718 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2719 2720 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2721 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2722 HDAC_SDCTL_RUN; 2723 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2724} 2725 2726static void 2727hdac_stream_reset(struct hdac_chan *ch) 2728{ 2729 struct hdac_softc *sc = ch->devinfo->codec->sc; 2730 int timeout = 1000; 2731 int to = timeout; 2732 uint32_t ctl; 2733 2734 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2735 ctl |= HDAC_SDCTL_SRST; 2736 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2737 do { 2738 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2739 if (ctl & HDAC_SDCTL_SRST) 2740 break; 2741 DELAY(10); 2742 } while (--to); 2743 if (!(ctl & HDAC_SDCTL_SRST)) { 2744 device_printf(sc->dev, "timeout in reset\n"); 2745 } 2746 ctl &= ~HDAC_SDCTL_SRST; 2747 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2748 to = timeout; 2749 do { 2750 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2751 if (!(ctl & HDAC_SDCTL_SRST)) 2752 break; 2753 DELAY(10); 2754 } while (--to); 2755 if (ctl & HDAC_SDCTL_SRST) 2756 device_printf(sc->dev, "can't reset!\n"); 2757} 2758 2759static void 2760hdac_stream_setid(struct hdac_chan *ch) 2761{ 2762 struct hdac_softc *sc = ch->devinfo->codec->sc; 2763 uint32_t ctl; 2764 2765 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2766 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2767 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2768 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2769} 2770 2771static void 2772hdac_bdl_setup(struct hdac_chan *ch) 2773{ 2774 struct hdac_softc *sc = ch->devinfo->codec->sc; 2775 struct hdac_bdle *bdle; 2776 uint64_t addr; 2777 uint32_t blksz, blkcnt; 2778 int i; 2779 2780 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2781 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2782 2783 blksz = ch->blksz; 2784 blkcnt = ch->blkcnt; 2785 2786 for (i = 0; i < blkcnt; i++, bdle++) { 2787 bdle->addrl = (uint32_t)addr; 2788 bdle->addrh = (uint32_t)(addr >> 32); 2789 bdle->len = blksz; 2790 bdle->ioc = 1; 2791 addr += blksz; 2792 } 2793 2794 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2795 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2796 addr = ch->bdl_dma.dma_paddr; 2797 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2798 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2799 if (ch->dmapos != NULL && 2800 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2801 addr = sc->pos_dma.dma_paddr; 2802 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2803 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2804 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2805 } 2806} 2807 2808static int 2809hdac_bdl_alloc(struct hdac_chan *ch) 2810{ 2811 struct hdac_softc *sc = ch->devinfo->codec->sc; 2812 int rc; 2813 2814 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2815 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2816 if (rc) { 2817 device_printf(sc->dev, "can't alloc bdl\n"); 2818 return (rc); 2819 } 2820 2821 return (0); 2822} 2823 2824static void 2825hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2826 int index, int lmute, int rmute, 2827 int left, int right, int dir) 2828{ 2829 uint16_t v = 0; 2830 2831 if (sc == NULL) 2832 return; 2833 2834 if (left != right || lmute != rmute) { 2835 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2836 (lmute << 7) | left; 2837 hdac_command(sc, 2838 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2839 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2840 (rmute << 7) | right; 2841 } else 2842 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2843 (lmute << 7) | left; 2844 2845 hdac_command(sc, 2846 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2847} 2848 2849static void 2850hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2851 int left, int right) 2852{ 2853 struct hdac_softc *sc; 2854 nid_t nid, cad; 2855 int lmute, rmute; 2856 2857 sc = ctl->widget->devinfo->codec->sc; 2858 cad = ctl->widget->devinfo->codec->cad; 2859 nid = ctl->widget->nid; 2860 2861 /* Save new values if valid. */ 2862 if (mute != HDA_AMP_MUTE_DEFAULT) 2863 ctl->muted = mute; 2864 if (left != HDA_AMP_VOL_DEFAULT) 2865 ctl->left = left; 2866 if (right != HDA_AMP_VOL_DEFAULT) 2867 ctl->right = right; 2868 /* Prepare effective values */ 2869 if (ctl->forcemute) { 2870 lmute = 1; 2871 rmute = 1; 2872 left = 0; 2873 right = 0; 2874 } else { 2875 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2876 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2877 left = ctl->left; 2878 right = ctl->right; 2879 } 2880 /* Apply effective values */ 2881 if (ctl->dir & HDA_CTL_OUT) 2882 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2883 lmute, rmute, left, right, 0); 2884 if (ctl->dir & HDA_CTL_IN) 2885 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2886 lmute, rmute, left, right, 1); 2887} 2888 2889static void 2890hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2891{ 2892 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2893 return; 2894 hdac_command(w->devinfo->codec->sc, 2895 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2896 w->nid, index), w->devinfo->codec->cad); 2897 w->selconn = index; 2898} 2899 2900 2901/**************************************************************************** 2902 * uint32_t hdac_command_sendone_internal 2903 * 2904 * Wrapper function that sends only one command to a given codec 2905 ****************************************************************************/ 2906static uint32_t 2907hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2908{ 2909 struct hdac_command_list cl; 2910 uint32_t response = HDAC_INVALID; 2911 2912 if (!hdac_lockowned(sc)) 2913 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2914 cl.num_commands = 1; 2915 cl.verbs = &verb; 2916 cl.responses = &response; 2917 2918 hdac_command_send_internal(sc, &cl, cad); 2919 2920 return (response); 2921} 2922 2923/**************************************************************************** 2924 * hdac_command_send_internal 2925 * 2926 * Send a command list to the codec via the corb. We queue as much verbs as 2927 * we can and msleep on the codec. When the interrupt get the responses 2928 * back from the rirb, it will wake us up so we can queue the remaining verbs 2929 * if any. 2930 ****************************************************************************/ 2931static void 2932hdac_command_send_internal(struct hdac_softc *sc, 2933 struct hdac_command_list *commands, nid_t cad) 2934{ 2935 struct hdac_codec *codec; 2936 int corbrp; 2937 uint32_t *corb; 2938 int timeout; 2939 int retry = 10; 2940 struct hdac_rirb *rirb_base; 2941 2942 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2943 commands->num_commands < 1) 2944 return; 2945 2946 codec = sc->codecs[cad]; 2947 codec->commands = commands; 2948 codec->responses_received = 0; 2949 codec->verbs_sent = 0; 2950 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2951 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2952 2953 do { 2954 if (codec->verbs_sent != commands->num_commands) { 2955 /* Queue as many verbs as possible */ 2956 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2957#if 0 2958 bus_dmamap_sync(sc->corb_dma.dma_tag, 2959 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2960#endif 2961 while (codec->verbs_sent != commands->num_commands && 2962 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2963 sc->corb_wp++; 2964 sc->corb_wp %= sc->corb_size; 2965 corb[sc->corb_wp] = 2966 commands->verbs[codec->verbs_sent++]; 2967 } 2968 2969 /* Send the verbs to the codecs */ 2970#if 0 2971 bus_dmamap_sync(sc->corb_dma.dma_tag, 2972 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2973#endif 2974 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2975 } 2976 2977 timeout = 1000; 2978 while (hdac_rirb_flush(sc) == 0 && --timeout) 2979 DELAY(10); 2980 } while ((codec->verbs_sent != commands->num_commands || 2981 codec->responses_received != commands->num_commands) && --retry); 2982 2983 if (retry == 0) 2984 device_printf(sc->dev, 2985 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2986 __func__, commands->num_commands, codec->verbs_sent, 2987 codec->responses_received); 2988 2989 codec->commands = NULL; 2990 codec->responses_received = 0; 2991 codec->verbs_sent = 0; 2992 2993 hdac_unsolq_flush(sc); 2994} 2995 2996 2997/**************************************************************************** 2998 * Device Methods 2999 ****************************************************************************/ 3000 3001/**************************************************************************** 3002 * int hdac_probe(device_t) 3003 * 3004 * Probe for the presence of an hdac. If none is found, check for a generic 3005 * match using the subclass of the device. 3006 ****************************************************************************/ 3007static int 3008hdac_probe(device_t dev) 3009{ 3010 int i, result; 3011 uint32_t model; 3012 uint16_t class, subclass; 3013 char desc[64]; 3014 3015 model = (uint32_t)pci_get_device(dev) << 16; 3016 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3017 class = pci_get_class(dev); 3018 subclass = pci_get_subclass(dev); 3019 3020 bzero(desc, sizeof(desc)); 3021 result = ENXIO; 3022 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3023 if (hdac_devices[i].model == model) { 3024 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3025 result = BUS_PROBE_DEFAULT; 3026 break; 3027 } 3028 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3029 class == PCIC_MULTIMEDIA && 3030 subclass == PCIS_MULTIMEDIA_HDA) { 3031 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3032 result = BUS_PROBE_GENERIC; 3033 break; 3034 } 3035 } 3036 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3037 subclass == PCIS_MULTIMEDIA_HDA) { 3038 strlcpy(desc, "Generic", sizeof(desc)); 3039 result = BUS_PROBE_GENERIC; 3040 } 3041 if (result != ENXIO) { 3042 strlcat(desc, " High Definition Audio Controller", 3043 sizeof(desc)); 3044 device_set_desc_copy(dev, desc); 3045 } 3046 3047 return (result); 3048} 3049 3050static void * 3051hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3052 struct pcm_channel *c, int dir) 3053{ 3054 struct hdac_pcm_devinfo *pdevinfo = data; 3055 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3056 struct hdac_softc *sc = devinfo->codec->sc; 3057 struct hdac_chan *ch; 3058 int i, ord = 0, chid; 3059 3060 hdac_lock(sc); 3061 3062 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3063 ch = &sc->chans[chid]; 3064 for (i = 0; i < sc->num_chans && i < chid; i++) { 3065 if (ch->dir == sc->chans[i].dir) 3066 ord++; 3067 } 3068 if (dir == PCMDIR_PLAY) { 3069 ch->off = (sc->num_iss + ord) << 5; 3070 } else { 3071 ch->off = ord << 5; 3072 } 3073 3074 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3075 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3076 ch->pcmrates[0] = 48000; 3077 ch->pcmrates[1] = 0; 3078 } 3079 if (sc->pos_dma.dma_vaddr != NULL) 3080 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3081 (sc->streamcnt * 8)); 3082 else 3083 ch->dmapos = NULL; 3084 ch->sid = ++sc->streamcnt; 3085 ch->dir = dir; 3086 ch->b = b; 3087 ch->c = c; 3088 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3089 ch->blkcnt = pdevinfo->chan_blkcnt; 3090 hdac_unlock(sc); 3091 3092 if (hdac_bdl_alloc(ch) != 0) { 3093 ch->blkcnt = 0; 3094 return (NULL); 3095 } 3096 3097 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3098 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3099 pdevinfo->chan_size) != 0) 3100 return (NULL); 3101 3102 return (ch); 3103} 3104 3105static int 3106hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3107{ 3108 struct hdac_chan *ch = data; 3109 int i; 3110 3111 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3112 if (format == ch->caps.fmtlist[i]) { 3113 ch->fmt = format; 3114 return (0); 3115 } 3116 } 3117 3118 return (EINVAL); 3119} 3120 3121static int 3122hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3123{ 3124 struct hdac_chan *ch = data; 3125 uint32_t spd = 0, threshold; 3126 int i; 3127 3128 for (i = 0; ch->pcmrates[i] != 0; i++) { 3129 spd = ch->pcmrates[i]; 3130 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3131 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3132 if (speed < threshold) 3133 break; 3134 } 3135 3136 if (spd == 0) /* impossible */ 3137 ch->spd = 48000; 3138 else 3139 ch->spd = spd; 3140 3141 return (ch->spd); 3142} 3143 3144static void 3145hdac_stream_setup(struct hdac_chan *ch) 3146{ 3147 struct hdac_softc *sc = ch->devinfo->codec->sc; 3148 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3149 struct hdac_widget *w; 3150 int i, chn, totalchn, c; 3151 nid_t cad = ch->devinfo->codec->cad; 3152 uint16_t fmt, dfmt; 3153 3154 HDA_BOOTVERBOSE( 3155 device_printf(ch->pdevinfo->dev, 3156 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3157 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3158 ch->fmt, ch->spd); 3159 ); 3160 fmt = 0; 3161 if (ch->fmt & AFMT_S16_LE) 3162 fmt |= ch->bit16 << 4; 3163 else if (ch->fmt & AFMT_S32_LE) 3164 fmt |= ch->bit32 << 4; 3165 else 3166 fmt |= 1 << 4; 3167 3168 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3169 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3170 fmt |= hda_rate_tab[i].base; 3171 fmt |= hda_rate_tab[i].mul; 3172 fmt |= hda_rate_tab[i].div; 3173 break; 3174 } 3175 } 3176 3177 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3178 fmt |= 1; 3179 totalchn = 2; 3180 } else 3181 totalchn = 1; 3182 3183 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3184 3185 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3186 if (ch->fmt & AFMT_AC3) 3187 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3188 3189 chn = 0; 3190 for (i = 0; ch->io[i] != -1; i++) { 3191 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3192 if (w == NULL) 3193 continue; 3194 3195 if (as->hpredir >= 0 && i == as->pincnt) 3196 chn = 0; 3197 HDA_BOOTVERBOSE( 3198 device_printf(ch->pdevinfo->dev, 3199 "PCMDIR_%s: Stream setup nid=%d: " 3200 "fmt=0x%04x, dfmt=0x%04x\n", 3201 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3202 ch->io[i], fmt, dfmt); 3203 ); 3204 hdac_command(sc, 3205 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3206 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3207 hdac_command(sc, 3208 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3209 cad); 3210 } 3211 /* If HP redirection is enabled, but failed to use same 3212 DAC make last DAC one to duplicate first one. */ 3213 if (as->hpredir >= 0 && i == as->pincnt) { 3214 c = (ch->sid << 4); 3215 } else if (chn >= totalchn) { 3216 /* This is until OSS will support multichannel. 3217 Should be: c = 0; to disable unused DAC */ 3218 c = (ch->sid << 4); 3219 }else { 3220 c = (ch->sid << 4) | chn; 3221 } 3222 hdac_command(sc, 3223 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3224 chn += 3225 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3226 2 : 1; 3227 } 3228} 3229 3230static int 3231hdac_channel_setfragments(kobj_t obj, void *data, 3232 uint32_t blksz, uint32_t blkcnt) 3233{ 3234 struct hdac_chan *ch = data; 3235 struct hdac_softc *sc = ch->devinfo->codec->sc; 3236 3237 blksz &= HDA_BLK_ALIGN; 3238 3239 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3240 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3241 if (blksz < HDA_BLK_MIN) 3242 blksz = HDA_BLK_MIN; 3243 if (blkcnt > HDA_BDL_MAX) 3244 blkcnt = HDA_BDL_MAX; 3245 if (blkcnt < HDA_BDL_MIN) 3246 blkcnt = HDA_BDL_MIN; 3247 3248 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3249 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3250 blkcnt >>= 1; 3251 else if ((blksz >> 1) >= HDA_BLK_MIN) 3252 blksz >>= 1; 3253 else 3254 break; 3255 } 3256 3257 if ((sndbuf_getblksz(ch->b) != blksz || 3258 sndbuf_getblkcnt(ch->b) != blkcnt) && 3259 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3260 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3261 __func__, blksz, blkcnt); 3262 3263 ch->blksz = sndbuf_getblksz(ch->b); 3264 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3265 3266 return (1); 3267} 3268 3269static int 3270hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3271{ 3272 struct hdac_chan *ch = data; 3273 3274 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3275 3276 return (ch->blksz); 3277} 3278 3279static void 3280hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3281{ 3282 struct hdac_devinfo *devinfo = ch->devinfo; 3283 struct hdac_widget *w; 3284 nid_t cad = devinfo->codec->cad; 3285 int i; 3286 3287 hdac_stream_stop(ch); 3288 3289 for (i = 0; ch->io[i] != -1; i++) { 3290 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3291 if (w == NULL) 3292 continue; 3293 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3294 hdac_command(sc, 3295 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3296 cad); 3297 } 3298 hdac_command(sc, 3299 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3300 0), cad); 3301 } 3302} 3303 3304static void 3305hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3306{ 3307 ch->ptr = 0; 3308 ch->prevptr = 0; 3309 hdac_stream_stop(ch); 3310 hdac_stream_reset(ch); 3311 hdac_bdl_setup(ch); 3312 hdac_stream_setid(ch); 3313 hdac_stream_setup(ch); 3314 hdac_stream_start(ch); 3315} 3316 3317static int 3318hdac_channel_trigger(kobj_t obj, void *data, int go) 3319{ 3320 struct hdac_chan *ch = data; 3321 struct hdac_softc *sc = ch->devinfo->codec->sc; 3322 3323 if (!PCMTRIG_COMMON(go)) 3324 return (0); 3325 3326 hdac_lock(sc); 3327 switch (go) { 3328 case PCMTRIG_START: 3329 hdac_channel_start(sc, ch); 3330 break; 3331 case PCMTRIG_STOP: 3332 case PCMTRIG_ABORT: 3333 hdac_channel_stop(sc, ch); 3334 break; 3335 default: 3336 break; 3337 } 3338 hdac_unlock(sc); 3339 3340 return (0); 3341} 3342 3343static int 3344hdac_channel_getptr(kobj_t obj, void *data) 3345{ 3346 struct hdac_chan *ch = data; 3347 struct hdac_softc *sc = ch->devinfo->codec->sc; 3348 uint32_t ptr; 3349 3350 hdac_lock(sc); 3351 if (sc->polling != 0) 3352 ptr = ch->ptr; 3353 else if (ch->dmapos != NULL) 3354 ptr = *(ch->dmapos); 3355 else 3356 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3357 hdac_unlock(sc); 3358 3359 /* 3360 * Round to available space and force 128 bytes aligment. 3361 */ 3362 ptr %= ch->blksz * ch->blkcnt; 3363 ptr &= HDA_BLK_ALIGN; 3364 3365 return (ptr); 3366} 3367 3368static struct pcmchan_caps * 3369hdac_channel_getcaps(kobj_t obj, void *data) 3370{ 3371 return (&((struct hdac_chan *)data)->caps); 3372} 3373 3374static kobj_method_t hdac_channel_methods[] = { 3375 KOBJMETHOD(channel_init, hdac_channel_init), 3376 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3377 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3378 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3379 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3380 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3381 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3382 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3383 { 0, 0 } 3384}; 3385CHANNEL_DECLARE(hdac_channel); 3386 3387static int 3388hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3389{ 3390 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3391 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3392 struct hdac_softc *sc = devinfo->codec->sc; 3393 struct hdac_widget *w, *cw; 3394 struct hdac_audio_ctl *ctl; 3395 uint32_t mask, recmask, id; 3396 int i, j, softpcmvol; 3397 3398 hdac_lock(sc); 3399 3400 /* Make sure that in case of soft volume it won't stay muted. */ 3401 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3402 pdevinfo->left[i] = 100; 3403 pdevinfo->right[i] = 100; 3404 } 3405 3406 mask = 0; 3407 recmask = 0; 3408 id = hdac_codec_id(devinfo->codec); 3409 3410 /* Declate EAPD as ogain control. */ 3411 if (pdevinfo->play >= 0) { 3412 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3413 w = hdac_widget_get(devinfo, i); 3414 if (w == NULL || w->enable == 0) 3415 continue; 3416 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3417 w->param.eapdbtl == HDAC_INVALID || 3418 w->bindas != sc->chans[pdevinfo->play].as) 3419 continue; 3420 mask |= SOUND_MASK_OGAIN; 3421 break; 3422 } 3423 } 3424 3425 /* Declare volume controls assigned to this association. */ 3426 i = 0; 3427 ctl = NULL; 3428 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3429 if (ctl->enable == 0) 3430 continue; 3431 if ((pdevinfo->play >= 0 && 3432 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3433 (pdevinfo->rec >= 0 && 3434 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3435 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3436 mask |= ctl->ossmask; 3437 } 3438 3439 /* Declare record sources available to this association. */ 3440 if (pdevinfo->rec >= 0) { 3441 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3442 for (i = 0; ch->io[i] != -1; i++) { 3443 w = hdac_widget_get(devinfo, ch->io[i]); 3444 if (w == NULL || w->enable == 0) 3445 continue; 3446 for (j = 0; j < w->nconns; j++) { 3447 if (w->connsenable[j] == 0) 3448 continue; 3449 cw = hdac_widget_get(devinfo, w->conns[j]); 3450 if (cw == NULL || cw->enable == 0) 3451 continue; 3452 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3453 cw->bindas != -2) 3454 continue; 3455 recmask |= cw->ossmask; 3456 } 3457 } 3458 } 3459 3460 /* Declare soft PCM and master volume if needed. */ 3461 if (pdevinfo->play >= 0) { 3462 ctl = NULL; 3463 if ((mask & SOUND_MASK_PCM) == 0 || 3464 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3465 softpcmvol = 1; 3466 mask |= SOUND_MASK_PCM; 3467 } else { 3468 softpcmvol = 0; 3469 i = 0; 3470 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3471 if (ctl->enable == 0) 3472 continue; 3473 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3474 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3475 continue; 3476 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3477 continue; 3478 if (ctl->step > 0) 3479 break; 3480 } 3481 } 3482 3483 if (softpcmvol == 1 || ctl == NULL) { 3484 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3485 HDA_BOOTVERBOSE( 3486 device_printf(pdevinfo->dev, 3487 "%s Soft PCM volume\n", 3488 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3489 ); 3490 } 3491 3492 if ((mask & SOUND_MASK_VOLUME) == 0) { 3493 mask |= SOUND_MASK_VOLUME; 3494 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3495 SOUND_MASK_PCM); 3496 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3497 SOUND_MIXER_NONE); 3498 HDA_BOOTVERBOSE( 3499 device_printf(pdevinfo->dev, 3500 "Forcing master volume with PCM\n"); 3501 ); 3502 } 3503 } 3504 3505 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3506 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3507 3508 mix_setrecdevs(m, recmask); 3509 mix_setdevs(m, mask); 3510 3511 hdac_unlock(sc); 3512 3513 return (0); 3514} 3515 3516static int 3517hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3518 unsigned left, unsigned right) 3519{ 3520 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3521 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3522 struct hdac_softc *sc = devinfo->codec->sc; 3523 struct hdac_widget *w; 3524 struct hdac_audio_ctl *ctl; 3525 uint32_t mute; 3526 int lvol, rvol; 3527 int i, j; 3528 3529 hdac_lock(sc); 3530 /* Save new values. */ 3531 pdevinfo->left[dev] = left; 3532 pdevinfo->right[dev] = right; 3533 3534 /* 'ogain' is the special case implemented with EAPD. */ 3535 if (dev == SOUND_MIXER_OGAIN) { 3536 uint32_t orig; 3537 w = NULL; 3538 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3539 w = hdac_widget_get(devinfo, i); 3540 if (w == NULL || w->enable == 0) 3541 continue; 3542 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3543 w->param.eapdbtl == HDAC_INVALID) 3544 continue; 3545 break; 3546 } 3547 if (i >= devinfo->endnode) { 3548 hdac_unlock(sc); 3549 return (-1); 3550 } 3551 orig = w->param.eapdbtl; 3552 if (left == 0) 3553 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3554 else 3555 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3556 if (orig != w->param.eapdbtl) { 3557 uint32_t val; 3558 3559 val = w->param.eapdbtl; 3560 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3561 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3562 hdac_command(sc, 3563 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3564 w->nid, val), devinfo->codec->cad); 3565 } 3566 hdac_unlock(sc); 3567 return (left | (left << 8)); 3568 } 3569 3570 /* Recalculate all controls related to this OSS device. */ 3571 i = 0; 3572 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3573 if (ctl->enable == 0 || 3574 !(ctl->ossmask & (1 << dev))) 3575 continue; 3576 if (!((pdevinfo->play >= 0 && 3577 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3578 (pdevinfo->rec >= 0 && 3579 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3580 ctl->widget->bindas == -2)) 3581 continue; 3582 3583 lvol = 100; 3584 rvol = 100; 3585 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3586 if (ctl->ossmask & (1 << j)) { 3587 lvol = lvol * pdevinfo->left[j] / 100; 3588 rvol = rvol * pdevinfo->right[j] / 100; 3589 } 3590 } 3591 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3592 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3593 lvol = (lvol * ctl->step + 50) / 100; 3594 rvol = (rvol * ctl->step + 50) / 100; 3595 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3596 } 3597 hdac_unlock(sc); 3598 3599 return (left | (right << 8)); 3600} 3601 3602/* 3603 * Commutate specified record source. 3604 */ 3605static uint32_t 3606hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3607{ 3608 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3609 struct hdac_widget *w, *cw; 3610 struct hdac_audio_ctl *ctl; 3611 char buf[64]; 3612 int i, muted; 3613 uint32_t res = 0; 3614 3615 if (depth > HDA_PARSE_MAXDEPTH) 3616 return (0); 3617 3618 w = hdac_widget_get(devinfo, nid); 3619 if (w == NULL || w->enable == 0) 3620 return (0); 3621 3622 for (i = 0; i < w->nconns; i++) { 3623 if (w->connsenable[i] == 0) 3624 continue; 3625 cw = hdac_widget_get(devinfo, w->conns[i]); 3626 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3627 continue; 3628 /* Call recursively to trace signal to it's source if needed. */ 3629 if ((src & cw->ossmask) != 0) { 3630 if (cw->ossdev < 0) { 3631 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3632 w->conns[i], depth + 1); 3633 } else { 3634 res |= cw->ossmask; 3635 } 3636 } 3637 /* We have two special cases: mixers and others (selectors). */ 3638 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3639 ctl = hdac_audio_ctl_amp_get(devinfo, 3640 w->nid, HDA_CTL_IN, i, 1); 3641 if (ctl == NULL) 3642 continue; 3643 /* If we have input control on this node mute them 3644 * according to requested sources. */ 3645 muted = (src & cw->ossmask) ? 0 : 1; 3646 if (muted != ctl->forcemute) { 3647 ctl->forcemute = muted; 3648 hdac_audio_ctl_amp_set(ctl, 3649 HDA_AMP_MUTE_DEFAULT, 3650 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3651 } 3652 HDA_BOOTVERBOSE( 3653 device_printf(pdevinfo->dev, 3654 "Recsel (%s): nid %d source %d %s\n", 3655 hdac_audio_ctl_ossmixer_mask2allname( 3656 src, buf, sizeof(buf)), 3657 nid, i, muted?"mute":"unmute"); 3658 ); 3659 } else { 3660 if (w->nconns == 1) 3661 break; 3662 if ((src & cw->ossmask) == 0) 3663 continue; 3664 /* If we found requested source - select it and exit. */ 3665 hdac_widget_connection_select(w, i); 3666 HDA_BOOTVERBOSE( 3667 device_printf(pdevinfo->dev, 3668 "Recsel (%s): nid %d source %d select\n", 3669 hdac_audio_ctl_ossmixer_mask2allname( 3670 src, buf, sizeof(buf)), 3671 nid, i); 3672 ); 3673 break; 3674 } 3675 } 3676 return (res); 3677} 3678 3679static uint32_t 3680hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3681{ 3682 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3683 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3684 struct hdac_widget *w; 3685 struct hdac_softc *sc = devinfo->codec->sc; 3686 struct hdac_chan *ch; 3687 int i; 3688 uint32_t ret = 0xffffffff; 3689 3690 hdac_lock(sc); 3691 3692 /* Commutate requested recsrc for each ADC. */ 3693 ch = &sc->chans[pdevinfo->rec]; 3694 for (i = 0; ch->io[i] != -1; i++) { 3695 w = hdac_widget_get(devinfo, ch->io[i]); 3696 if (w == NULL || w->enable == 0) 3697 continue; 3698 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3699 } 3700 3701 hdac_unlock(sc); 3702 3703 return ((ret == 0xffffffff)? 0 : ret); 3704} 3705 3706static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3707 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3708 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3709 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3710 { 0, 0 } 3711}; 3712MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3713 3714static void 3715hdac_unsolq_task(void *context, int pending) 3716{ 3717 struct hdac_softc *sc; 3718 3719 sc = (struct hdac_softc *)context; 3720 3721 hdac_lock(sc); 3722 hdac_unsolq_flush(sc); 3723 hdac_unlock(sc); 3724} 3725 3726/**************************************************************************** 3727 * int hdac_attach(device_t) 3728 * 3729 * Attach the device into the kernel. Interrupts usually won't be enabled 3730 * when this function is called. Setup everything that doesn't require 3731 * interrupts and defer probing of codecs until interrupts are enabled. 3732 ****************************************************************************/ 3733static int 3734hdac_attach(device_t dev) 3735{ 3736 struct hdac_softc *sc; 3737 int result; 3738 int i; 3739 uint16_t vendor; 3740 uint8_t v; 3741 3742 device_printf(dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 3743 3744 sc = device_get_softc(dev); 3745 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3746 sc->dev = dev; 3747 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3748 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3749 vendor = pci_get_vendor(dev); 3750 3751 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3752 /* Screw nx6325 - subdevice/subvendor swapped */ 3753 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3754 } 3755 3756 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3757 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3758 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3759 3760 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3761 3762 sc->poll_ticks = 1000000; 3763 sc->poll_ival = HDAC_POLL_INTERVAL; 3764 if (resource_int_value(device_get_name(dev), 3765 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3766 sc->polling = 1; 3767 else 3768 sc->polling = 0; 3769 3770 result = bus_dma_tag_create(NULL, /* parent */ 3771 HDAC_DMA_ALIGNMENT, /* alignment */ 3772 0, /* boundary */ 3773 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3774 BUS_SPACE_MAXADDR, /* highaddr */ 3775 NULL, /* filtfunc */ 3776 NULL, /* fistfuncarg */ 3777 HDA_BUFSZ_MAX, /* maxsize */ 3778 1, /* nsegments */ 3779 HDA_BUFSZ_MAX, /* maxsegsz */ 3780 0, /* flags */ 3781 NULL, /* lockfunc */ 3782 NULL, /* lockfuncarg */ 3783 &sc->chan_dmat); /* dmat */ 3784 if (result != 0) { 3785 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3786 __func__, result); 3787 snd_mtxfree(sc->lock); 3788 free(sc, M_DEVBUF); 3789 return (ENXIO); 3790 } 3791 3792 3793 sc->hdabus = NULL; 3794 for (i = 0; i < HDAC_CODEC_MAX; i++) 3795 sc->codecs[i] = NULL; 3796 3797 pci_enable_busmaster(dev); 3798 3799 if (vendor == INTEL_VENDORID) { 3800 /* TCSEL -> TC0 */ 3801 v = pci_read_config(dev, 0x44, 1); 3802 pci_write_config(dev, 0x44, v & 0xf8, 1); 3803 HDA_BOOTVERBOSE( 3804 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3805 pci_read_config(dev, 0x44, 1)); 3806 ); 3807 } 3808 3809#ifdef HDAC_MSI_ENABLED 3810 if (resource_int_value(device_get_name(dev), 3811 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3812 pci_msi_count(dev) == 1) 3813 sc->flags |= HDAC_F_MSI; 3814 else 3815#endif 3816 sc->flags &= ~HDAC_F_MSI; 3817 3818#if defined(__i386__) || defined(__amd64__) 3819 sc->flags |= HDAC_F_DMA_NOCACHE; 3820 3821 if (resource_int_value(device_get_name(dev), 3822 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3823#else 3824 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3825#endif 3826 /* 3827 * Try to enable PCIe snoop to avoid messing around with 3828 * uncacheable DMA attribute. Since PCIe snoop register 3829 * config is pretty much vendor specific, there are no 3830 * general solutions on how to enable it, forcing us (even 3831 * Microsoft) to enable uncacheable or write combined DMA 3832 * by default. 3833 * 3834 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3835 */ 3836 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3837 if (hdac_pcie_snoop[i].vendor != vendor) 3838 continue; 3839 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3840 if (hdac_pcie_snoop[i].reg == 0x00) 3841 break; 3842 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3843 if ((v & hdac_pcie_snoop[i].enable) == 3844 hdac_pcie_snoop[i].enable) 3845 break; 3846 v &= hdac_pcie_snoop[i].mask; 3847 v |= hdac_pcie_snoop[i].enable; 3848 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3849 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3850 if ((v & hdac_pcie_snoop[i].enable) != 3851 hdac_pcie_snoop[i].enable) { 3852 HDA_BOOTVERBOSE( 3853 device_printf(dev, 3854 "WARNING: Failed to enable PCIe " 3855 "snoop!\n"); 3856 ); 3857#if defined(__i386__) || defined(__amd64__) 3858 sc->flags |= HDAC_F_DMA_NOCACHE; 3859#endif 3860 } 3861 break; 3862 } 3863#if defined(__i386__) || defined(__amd64__) 3864 } 3865#endif 3866 3867 HDA_BOOTVERBOSE( 3868 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3869 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3870 "Uncacheable" : "PCIe snoop", vendor); 3871 ); 3872 3873 /* Allocate resources */ 3874 result = hdac_mem_alloc(sc); 3875 if (result != 0) 3876 goto hdac_attach_fail; 3877 result = hdac_irq_alloc(sc); 3878 if (result != 0) 3879 goto hdac_attach_fail; 3880 3881 /* Get Capabilities */ 3882 result = hdac_get_capabilities(sc); 3883 if (result != 0) 3884 goto hdac_attach_fail; 3885 3886 /* Allocate CORB and RIRB dma memory */ 3887 result = hdac_dma_alloc(sc, &sc->corb_dma, 3888 sc->corb_size * sizeof(uint32_t)); 3889 if (result != 0) 3890 goto hdac_attach_fail; 3891 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3892 sc->rirb_size * sizeof(struct hdac_rirb)); 3893 if (result != 0) 3894 goto hdac_attach_fail; 3895 3896 /* Quiesce everything */ 3897 HDA_BOOTVERBOSE( 3898 device_printf(dev, "Reset controller...\n"); 3899 ); 3900 hdac_reset(sc, 1); 3901 3902 /* Initialize the CORB and RIRB */ 3903 hdac_corb_init(sc); 3904 hdac_rirb_init(sc); 3905 3906 /* Defer remaining of initialization until interrupts are enabled */ 3907 sc->intrhook.ich_func = hdac_attach2; 3908 sc->intrhook.ich_arg = (void *)sc; 3909 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3910 sc->intrhook.ich_func = NULL; 3911 hdac_attach2((void *)sc); 3912 } 3913 3914 return (0); 3915 3916hdac_attach_fail: 3917 hdac_irq_free(sc); 3918 hdac_dma_free(sc, &sc->rirb_dma); 3919 hdac_dma_free(sc, &sc->corb_dma); 3920 hdac_mem_free(sc); 3921 snd_mtxfree(sc->lock); 3922 free(sc, M_DEVBUF); 3923 3924 return (ENXIO); 3925} 3926 3927static void 3928hdac_audio_parse(struct hdac_devinfo *devinfo) 3929{ 3930 struct hdac_codec *codec = devinfo->codec; 3931 struct hdac_softc *sc = codec->sc; 3932 struct hdac_widget *w; 3933 uint32_t res; 3934 int i; 3935 nid_t cad, nid; 3936 3937 cad = devinfo->codec->cad; 3938 nid = devinfo->nid; 3939 3940 res = hdac_command(sc, 3941 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3942 devinfo->function.audio.gpio = res; 3943 3944 HDA_BOOTVERBOSE( 3945 device_printf(sc->dev, " GPIO: 0x%08x\n", 3946 devinfo->function.audio.gpio); 3947 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3948 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3949 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3950 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3951 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3952 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3953 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3954 ); 3955 3956 res = hdac_command(sc, 3957 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3958 cad); 3959 devinfo->function.audio.supp_stream_formats = res; 3960 3961 res = hdac_command(sc, 3962 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3963 cad); 3964 devinfo->function.audio.supp_pcm_size_rate = res; 3965 3966 res = hdac_command(sc, 3967 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3968 cad); 3969 devinfo->function.audio.outamp_cap = res; 3970 3971 res = hdac_command(sc, 3972 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3973 cad); 3974 devinfo->function.audio.inamp_cap = res; 3975 3976 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3977 w = hdac_widget_get(devinfo, i); 3978 if (w == NULL) 3979 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3980 else { 3981 w->devinfo = devinfo; 3982 w->nid = i; 3983 w->enable = 1; 3984 w->selconn = -1; 3985 w->pflags = 0; 3986 w->ossdev = -1; 3987 w->bindas = -1; 3988 w->param.eapdbtl = HDAC_INVALID; 3989 hdac_widget_parse(w); 3990 } 3991 } 3992} 3993 3994static void 3995hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3996{ 3997 struct hdac_softc *sc = devinfo->codec->sc; 3998 struct hdac_audio_ctl *ctls; 3999 struct hdac_widget *w, *cw; 4000 int i, j, cnt, max, ocap, icap; 4001 int mute, offset, step, size; 4002 4003 /* XXX This is redundant */ 4004 max = 0; 4005 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4006 w = hdac_widget_get(devinfo, i); 4007 if (w == NULL || w->enable == 0) 4008 continue; 4009 if (w->param.outamp_cap != 0) 4010 max++; 4011 if (w->param.inamp_cap != 0) { 4012 switch (w->type) { 4013 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4014 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4015 for (j = 0; j < w->nconns; j++) { 4016 cw = hdac_widget_get(devinfo, 4017 w->conns[j]); 4018 if (cw == NULL || cw->enable == 0) 4019 continue; 4020 max++; 4021 } 4022 break; 4023 default: 4024 max++; 4025 break; 4026 } 4027 } 4028 } 4029 4030 devinfo->function.audio.ctlcnt = max; 4031 4032 if (max < 1) 4033 return; 4034 4035 ctls = (struct hdac_audio_ctl *)malloc( 4036 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4037 4038 if (ctls == NULL) { 4039 /* Blekh! */ 4040 device_printf(sc->dev, "unable to allocate ctls!\n"); 4041 devinfo->function.audio.ctlcnt = 0; 4042 return; 4043 } 4044 4045 cnt = 0; 4046 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4047 if (cnt >= max) { 4048 device_printf(sc->dev, "%s: Ctl overflow!\n", 4049 __func__); 4050 break; 4051 } 4052 w = hdac_widget_get(devinfo, i); 4053 if (w == NULL || w->enable == 0) 4054 continue; 4055 ocap = w->param.outamp_cap; 4056 icap = w->param.inamp_cap; 4057 if (ocap != 0) { 4058 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4059 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4060 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4061 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4062 /*if (offset > step) { 4063 HDA_BOOTVERBOSE( 4064 device_printf(sc->dev, 4065 "BUGGY outamp: nid=%d " 4066 "[offset=%d > step=%d]\n", 4067 w->nid, offset, step); 4068 ); 4069 offset = step; 4070 }*/ 4071 ctls[cnt].enable = 1; 4072 ctls[cnt].widget = w; 4073 ctls[cnt].mute = mute; 4074 ctls[cnt].step = step; 4075 ctls[cnt].size = size; 4076 ctls[cnt].offset = offset; 4077 ctls[cnt].left = offset; 4078 ctls[cnt].right = offset; 4079 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4080 w->waspin) 4081 ctls[cnt].ndir = HDA_CTL_IN; 4082 else 4083 ctls[cnt].ndir = HDA_CTL_OUT; 4084 ctls[cnt++].dir = HDA_CTL_OUT; 4085 } 4086 4087 if (icap != 0) { 4088 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4089 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4090 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4091 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4092 /*if (offset > step) { 4093 HDA_BOOTVERBOSE( 4094 device_printf(sc->dev, 4095 "BUGGY inamp: nid=%d " 4096 "[offset=%d > step=%d]\n", 4097 w->nid, offset, step); 4098 ); 4099 offset = step; 4100 }*/ 4101 switch (w->type) { 4102 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4103 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4104 for (j = 0; j < w->nconns; j++) { 4105 if (cnt >= max) { 4106 device_printf(sc->dev, 4107 "%s: Ctl overflow!\n", 4108 __func__); 4109 break; 4110 } 4111 cw = hdac_widget_get(devinfo, 4112 w->conns[j]); 4113 if (cw == NULL || cw->enable == 0) 4114 continue; 4115 ctls[cnt].enable = 1; 4116 ctls[cnt].widget = w; 4117 ctls[cnt].childwidget = cw; 4118 ctls[cnt].index = j; 4119 ctls[cnt].mute = mute; 4120 ctls[cnt].step = step; 4121 ctls[cnt].size = size; 4122 ctls[cnt].offset = offset; 4123 ctls[cnt].left = offset; 4124 ctls[cnt].right = offset; 4125 ctls[cnt].ndir = HDA_CTL_IN; 4126 ctls[cnt++].dir = HDA_CTL_IN; 4127 } 4128 break; 4129 default: 4130 if (cnt >= max) { 4131 device_printf(sc->dev, 4132 "%s: Ctl overflow!\n", 4133 __func__); 4134 break; 4135 } 4136 ctls[cnt].enable = 1; 4137 ctls[cnt].widget = w; 4138 ctls[cnt].mute = mute; 4139 ctls[cnt].step = step; 4140 ctls[cnt].size = size; 4141 ctls[cnt].offset = offset; 4142 ctls[cnt].left = offset; 4143 ctls[cnt].right = offset; 4144 if (w->type == 4145 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4146 ctls[cnt].ndir = HDA_CTL_OUT; 4147 else 4148 ctls[cnt].ndir = HDA_CTL_IN; 4149 ctls[cnt++].dir = HDA_CTL_IN; 4150 break; 4151 } 4152 } 4153 } 4154 4155 devinfo->function.audio.ctl = ctls; 4156} 4157 4158static void 4159hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4160{ 4161 struct hdac_softc *sc = devinfo->codec->sc; 4162 struct hdac_audio_as *as; 4163 struct hdac_widget *w; 4164 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4165 4166 /* XXX This is redundant */ 4167 max = 0; 4168 for (j = 0; j < 16; j++) { 4169 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4170 w = hdac_widget_get(devinfo, i); 4171 if (w == NULL || w->enable == 0) 4172 continue; 4173 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4174 continue; 4175 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4176 != j) 4177 continue; 4178 max++; 4179 if (j != 15) /* There could be many 1-pin assocs #15 */ 4180 break; 4181 } 4182 } 4183 4184 devinfo->function.audio.ascnt = max; 4185 4186 if (max < 1) 4187 return; 4188 4189 as = (struct hdac_audio_as *)malloc( 4190 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4191 4192 if (as == NULL) { 4193 /* Blekh! */ 4194 device_printf(sc->dev, "unable to allocate assocs!\n"); 4195 devinfo->function.audio.ascnt = 0; 4196 return; 4197 } 4198 4199 for (i = 0; i < max; i++) { 4200 as[i].hpredir = -1; 4201 as[i].chan = -1; 4202 } 4203 4204 /* Scan associations skipping as=0. */ 4205 cnt = 0; 4206 for (j = 1; j < 16; j++) { 4207 first = 16; 4208 hpredir = 0; 4209 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4210 w = hdac_widget_get(devinfo, i); 4211 if (w == NULL || w->enable == 0) 4212 continue; 4213 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4214 continue; 4215 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4216 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4217 if (assoc != j) { 4218 continue; 4219 } 4220 KASSERT(cnt < max, 4221 ("%s: Associations owerflow (%d of %d)", 4222 __func__, cnt, max)); 4223 type = w->wclass.pin.config & 4224 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4225 /* Get pin direction. */ 4226 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4227 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4228 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4229 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4230 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4231 dir = HDA_CTL_OUT; 4232 else 4233 dir = HDA_CTL_IN; 4234 /* If this is a first pin - create new association. */ 4235 if (as[cnt].pincnt == 0) { 4236 as[cnt].enable = 1; 4237 as[cnt].index = j; 4238 as[cnt].dir = dir; 4239 } 4240 if (seq < first) 4241 first = seq; 4242 /* Check association correctness. */ 4243 if (as[cnt].pins[seq] != 0) { 4244 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4245 "in association %d! Disabling association.\n", 4246 __func__, seq, w->nid, j); 4247 as[cnt].enable = 0; 4248 } 4249 if (dir != as[cnt].dir) { 4250 device_printf(sc->dev, "%s: Pin %d has wrong " 4251 "direction for association %d! Disabling " 4252 "association.\n", 4253 __func__, w->nid, j); 4254 as[cnt].enable = 0; 4255 } 4256 /* Headphones with seq=15 may mean redirection. */ 4257 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4258 seq == 15) 4259 hpredir = 1; 4260 as[cnt].pins[seq] = w->nid; 4261 as[cnt].pincnt++; 4262 /* Association 15 is a multiple unassociated pins. */ 4263 if (j == 15) 4264 cnt++; 4265 } 4266 if (j != 15 && as[cnt].pincnt > 0) { 4267 if (hpredir && as[cnt].pincnt > 1) 4268 as[cnt].hpredir = first; 4269 cnt++; 4270 } 4271 } 4272 HDA_BOOTVERBOSE( 4273 device_printf(sc->dev, 4274 "%d associations found\n", max); 4275 for (i = 0; i < max; i++) { 4276 device_printf(sc->dev, 4277 "Association %d (%d) %s%s:\n", 4278 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4279 as[i].enable?"":" (disabled)"); 4280 for (j = 0; j < 16; j++) { 4281 if (as[i].pins[j] == 0) 4282 continue; 4283 device_printf(sc->dev, 4284 " Pin nid=%d seq=%d\n", 4285 as[i].pins[j], j); 4286 } 4287 } 4288 ); 4289 4290 devinfo->function.audio.as = as; 4291} 4292 4293static const struct { 4294 uint32_t model; 4295 uint32_t id; 4296 uint32_t set, unset; 4297} hdac_quirks[] = { 4298 /* 4299 * XXX Force stereo quirk. Monoural recording / playback 4300 * on few codecs (especially ALC880) seems broken or 4301 * perhaps unsupported. 4302 */ 4303 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4304 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4305 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4306 HDA_QUIRK_GPIO0, 0 }, 4307 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4308 HDA_QUIRK_GPIO0, 0 }, 4309 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4310 HDA_QUIRK_GPIO0, 0 }, 4311 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4312 HDA_QUIRK_GPIO0, 0 }, 4313 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4314 HDA_QUIRK_GPIO0, 0 }, 4315 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4316 HDA_QUIRK_GPIO0, 0 }, 4317 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4318 HDA_QUIRK_EAPDINV, 0 }, 4319 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4320 HDA_QUIRK_EAPDINV, 0 }, 4321 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4322 HDA_QUIRK_OVREF, 0 }, 4323 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4324 HDA_QUIRK_OVREF, 0 }, 4325 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4326 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4327 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4328 HDA_QUIRK_GPIO1, 0 }, 4329 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4330 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4331 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4332 HDA_QUIRK_EAPDINV, 0 }, 4333 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4334 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4335 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4336 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4337 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205, 4338 HDA_QUIRK_GPIO0, 0 }, 4339 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205, 4340 HDA_QUIRK_GPIO0, 0 }, 4341 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4342 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4343 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4344 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4345 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4346 0, HDA_QUIRK_FORCESTEREO } 4347}; 4348#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4349 4350static void 4351hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4352{ 4353 struct hdac_widget *w; 4354 uint32_t id, subvendor; 4355 int i; 4356 4357 id = hdac_codec_id(devinfo->codec); 4358 subvendor = devinfo->codec->sc->pci_subvendor; 4359 4360 /* 4361 * Quirks 4362 */ 4363 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4364 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4365 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4366 continue; 4367 if (hdac_quirks[i].set != 0) 4368 devinfo->function.audio.quirks |= 4369 hdac_quirks[i].set; 4370 if (hdac_quirks[i].unset != 0) 4371 devinfo->function.audio.quirks &= 4372 ~(hdac_quirks[i].unset); 4373 } 4374 4375 switch (id) { 4376 case HDA_CODEC_ALC883: 4377 /* 4378 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4379 * Clear vref cap for jack connectivity. 4380 */ 4381 w = hdac_widget_get(devinfo, 24); 4382 if (w != NULL && w->enable != 0 && w->type == 4383 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4384 (w->wclass.pin.config & 4385 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4386 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4387 w->wclass.pin.cap &= ~( 4388 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4389 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4390 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4391 w = hdac_widget_get(devinfo, 25); 4392 if (w != NULL && w->enable != 0 && w->type == 4393 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4394 (w->wclass.pin.config & 4395 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4396 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4397 w->wclass.pin.cap &= ~( 4398 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4399 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4400 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4401 /* 4402 * nid: 26 = Line-in, leave it alone. 4403 */ 4404 break; 4405 case HDA_CODEC_AD1986A: 4406 if (subvendor == ASUS_A8X_SUBVENDOR) { 4407 /* 4408 * This is just plain ridiculous.. There 4409 * are several A8 series that share the same 4410 * pci id but works differently (EAPD). 4411 */ 4412 w = hdac_widget_get(devinfo, 26); 4413 if (w != NULL && w->type == 4414 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4415 (w->wclass.pin.config & 4416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4417 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4418 devinfo->function.audio.quirks &= 4419 ~HDA_QUIRK_EAPDINV; 4420 } 4421 break; 4422 } 4423} 4424 4425/* 4426 * Trace path from DAC to pin. 4427 */ 4428static nid_t 4429hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4430 int dupseq, int min, int only, int depth) 4431{ 4432 struct hdac_widget *w; 4433 int i, im = -1; 4434 nid_t m = 0, ret; 4435 4436 if (depth > HDA_PARSE_MAXDEPTH) 4437 return (0); 4438 w = hdac_widget_get(devinfo, nid); 4439 if (w == NULL || w->enable == 0) 4440 return (0); 4441 HDA_BOOTVERBOSE( 4442 if (!only) { 4443 device_printf(devinfo->codec->sc->dev, 4444 " %*stracing via nid %d\n", 4445 depth + 1, "", w->nid); 4446 } 4447 ); 4448 /* Use only unused widgets */ 4449 if (w->bindas >= 0 && w->bindas != as) { 4450 HDA_BOOTVERBOSE( 4451 if (!only) { 4452 device_printf(devinfo->codec->sc->dev, 4453 " %*snid %d busy by association %d\n", 4454 depth + 1, "", w->nid, w->bindas); 4455 } 4456 ); 4457 return (0); 4458 } 4459 if (dupseq < 0) { 4460 if (w->bindseqmask != 0) { 4461 HDA_BOOTVERBOSE( 4462 if (!only) { 4463 device_printf(devinfo->codec->sc->dev, 4464 " %*snid %d busy by seqmask %x\n", 4465 depth + 1, "", w->nid, w->bindseqmask); 4466 } 4467 ); 4468 return (0); 4469 } 4470 } else { 4471 /* If this is headphones - allow duplicate first pin. */ 4472 if (w->bindseqmask != 0 && 4473 (w->bindseqmask & (1 << dupseq)) == 0) { 4474 HDA_BOOTVERBOSE( 4475 device_printf(devinfo->codec->sc->dev, 4476 " %*snid %d busy by seqmask %x\n", 4477 depth + 1, "", w->nid, w->bindseqmask); 4478 ); 4479 return (0); 4480 } 4481 } 4482 4483 switch (w->type) { 4484 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4485 /* Do not traverse input. AD1988 has digital monitor 4486 for which we are not ready. */ 4487 break; 4488 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4489 /* If we are tracing HP take only dac of first pin. */ 4490 if ((only == 0 || only == w->nid) && 4491 (w->nid >= min) && (dupseq < 0 || w->nid == 4492 devinfo->function.audio.as[as].dacs[dupseq])) 4493 m = w->nid; 4494 break; 4495 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4496 if (depth > 0) 4497 break; 4498 /* Fall */ 4499 default: 4500 /* Find reachable DACs with smallest nid respecting constraints. */ 4501 for (i = 0; i < w->nconns; i++) { 4502 if (w->connsenable[i] == 0) 4503 continue; 4504 if (w->selconn != -1 && w->selconn != i) 4505 continue; 4506 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4507 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4508 if (m == 0 || ret < m) { 4509 m = ret; 4510 im = i; 4511 } 4512 if (only || dupseq >= 0) 4513 break; 4514 } 4515 } 4516 if (m && only && ((w->nconns > 1 && 4517 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4518 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4519 w->selconn = im; 4520 break; 4521 } 4522 if (m && only) { 4523 w->bindas = as; 4524 w->bindseqmask |= (1 << seq); 4525 } 4526 HDA_BOOTVERBOSE( 4527 if (!only) { 4528 device_printf(devinfo->codec->sc->dev, 4529 " %*snid %d returned %d\n", 4530 depth + 1, "", w->nid, m); 4531 } 4532 ); 4533 return (m); 4534} 4535 4536/* 4537 * Trace path from widget to ADC. 4538 */ 4539static nid_t 4540hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4541 int only, int depth) 4542{ 4543 struct hdac_widget *w, *wc; 4544 int i, j; 4545 nid_t res = 0; 4546 4547 if (depth > HDA_PARSE_MAXDEPTH) 4548 return (0); 4549 w = hdac_widget_get(devinfo, nid); 4550 if (w == NULL || w->enable == 0) 4551 return (0); 4552 HDA_BOOTVERBOSE( 4553 device_printf(devinfo->codec->sc->dev, 4554 " %*stracing via nid %d\n", 4555 depth + 1, "", w->nid); 4556 ); 4557 /* Use only unused widgets */ 4558 if (w->bindas >= 0 && w->bindas != as) { 4559 HDA_BOOTVERBOSE( 4560 device_printf(devinfo->codec->sc->dev, 4561 " %*snid %d busy by association %d\n", 4562 depth + 1, "", w->nid, w->bindas); 4563 ); 4564 return (0); 4565 } 4566 4567 switch (w->type) { 4568 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4569 /* If we are tracing HP take only dac of first pin. */ 4570 if (only == w->nid) 4571 res = 1; 4572 break; 4573 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4574 if (depth > 0) 4575 break; 4576 /* Fall */ 4577 default: 4578 /* Try to find reachable ADCs with specified nid. */ 4579 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4580 wc = hdac_widget_get(devinfo, j); 4581 if (wc == NULL || wc->enable == 0) 4582 continue; 4583 for (i = 0; i < wc->nconns; i++) { 4584 if (wc->connsenable[i] == 0) 4585 continue; 4586 if (wc->conns[i] != nid) 4587 continue; 4588 if (hdac_audio_trace_adc(devinfo, as, seq, 4589 j, only, depth + 1) != 0) { 4590 res = 1; 4591 if (((wc->nconns > 1 && 4592 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4593 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4594 wc->selconn == -1) 4595 wc->selconn = i; 4596 } 4597 } 4598 } 4599 break; 4600 } 4601 if (res) { 4602 w->bindas = as; 4603 w->bindseqmask |= (1 << seq); 4604 } 4605 HDA_BOOTVERBOSE( 4606 device_printf(devinfo->codec->sc->dev, 4607 " %*snid %d returned %d\n", 4608 depth + 1, "", w->nid, res); 4609 ); 4610 return (res); 4611} 4612 4613/* 4614 * Erase trace path of the specified association. 4615 */ 4616static void 4617hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4618{ 4619 struct hdac_widget *w; 4620 int i; 4621 4622 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4623 w = hdac_widget_get(devinfo, i); 4624 if (w == NULL || w->enable == 0) 4625 continue; 4626 if (w->bindas == as) { 4627 if (seq >= 0) { 4628 w->bindseqmask &= ~(1 << seq); 4629 if (w->bindseqmask == 0) { 4630 w->bindas = -1; 4631 w->selconn = -1; 4632 } 4633 } else { 4634 w->bindas = -1; 4635 w->bindseqmask = 0; 4636 w->selconn = -1; 4637 } 4638 } 4639 } 4640} 4641 4642/* 4643 * Trace association path from DAC to output 4644 */ 4645static int 4646hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4647{ 4648 struct hdac_audio_as *ases = devinfo->function.audio.as; 4649 int i, hpredir; 4650 nid_t min, res; 4651 4652 /* Find next pin */ 4653 for (i = seq; ases[as].pins[i] == 0 && i < 16; i++) 4654 ; 4655 /* Check if there is no any left. If so - we succeded. */ 4656 if (i == 16) 4657 return (1); 4658 4659 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4660 min = 0; 4661 res = 0; 4662 do { 4663 HDA_BOOTVERBOSE( 4664 device_printf(devinfo->codec->sc->dev, 4665 " Tracing pin %d with min nid %d", 4666 ases[as].pins[i], min); 4667 if (hpredir >= 0) 4668 printf(" and hpredir %d\n", hpredir); 4669 else 4670 printf("\n"); 4671 ); 4672 /* Trace this pin taking min nid into account. */ 4673 res = hdac_audio_trace_dac(devinfo, as, i, 4674 ases[as].pins[i], hpredir, min, 0, 0); 4675 if (res == 0) { 4676 /* If we failed - return to previous and redo it. */ 4677 HDA_BOOTVERBOSE( 4678 device_printf(devinfo->codec->sc->dev, 4679 " Unable to trace pin %d seq %d with min " 4680 "nid %d hpredir %d\n", 4681 ases[as].pins[i], i, min, hpredir); 4682 ); 4683 return (0); 4684 } 4685 HDA_BOOTVERBOSE( 4686 device_printf(devinfo->codec->sc->dev, 4687 " Pin %d traced to DAC %d%s\n", 4688 ases[as].pins[i], res, 4689 ases[as].fakeredir?" with fake redirection":""); 4690 ); 4691 /* Trace again to mark the path */ 4692 hdac_audio_trace_dac(devinfo, as, i, 4693 ases[as].pins[i], hpredir, min, res, 0); 4694 ases[as].dacs[i] = res; 4695 /* We succeded, so call next. */ 4696 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4697 return (1); 4698 /* If next failed, we should retry with next min */ 4699 hdac_audio_undo_trace(devinfo, as, i); 4700 ases[as].dacs[i] = 0; 4701 min = res + 1; 4702 } while (1); 4703} 4704 4705/* 4706 * Trace association path from input to ADC 4707 */ 4708static int 4709hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4710{ 4711 struct hdac_audio_as *ases = devinfo->function.audio.as; 4712 struct hdac_widget *w; 4713 int i, j, k; 4714 4715 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4716 w = hdac_widget_get(devinfo, j); 4717 if (w == NULL || w->enable == 0) 4718 continue; 4719 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4720 continue; 4721 if (w->bindas >= 0 && w->bindas != as) 4722 continue; 4723 4724 /* Find next pin */ 4725 for (i = 0; i < 16; i++) { 4726 if (ases[as].pins[i] == 0) 4727 continue; 4728 4729 HDA_BOOTVERBOSE( 4730 device_printf(devinfo->codec->sc->dev, 4731 " Tracing pin %d to ADC %d\n", 4732 ases[as].pins[i], j); 4733 ); 4734 /* Trace this pin taking goal into account. */ 4735 if (hdac_audio_trace_adc(devinfo, as, i, 4736 ases[as].pins[i], j, 0) == 0) { 4737 /* If we failed - return to previous and redo it. */ 4738 HDA_BOOTVERBOSE( 4739 device_printf(devinfo->codec->sc->dev, 4740 " Unable to trace pin %d to ADC %d\n", 4741 ases[as].pins[i], j); 4742 ); 4743 hdac_audio_undo_trace(devinfo, as, -1); 4744 for (k = 0; k < 16; k++) 4745 ases[as].dacs[k] = 0; 4746 break; 4747 } 4748 HDA_BOOTVERBOSE( 4749 device_printf(devinfo->codec->sc->dev, 4750 " Traced to ADC %d\n", 4751 j); 4752 ); 4753 ases[as].dacs[i] = j; 4754 } 4755 if (i == 16) 4756 return (1); 4757 } 4758 return (0); 4759} 4760 4761/* 4762 * Trace input monitor path from mixer to output association. 4763 */ 4764static nid_t 4765hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4766{ 4767 struct hdac_audio_as *ases = devinfo->function.audio.as; 4768 struct hdac_widget *w, *wc; 4769 int i, j; 4770 nid_t res = 0; 4771 4772 if (depth > HDA_PARSE_MAXDEPTH) 4773 return (0); 4774 w = hdac_widget_get(devinfo, nid); 4775 if (w == NULL || w->enable == 0) 4776 return (0); 4777 HDA_BOOTVERBOSE( 4778 device_printf(devinfo->codec->sc->dev, 4779 " %*stracing via nid %d\n", 4780 depth + 1, "", w->nid); 4781 ); 4782 /* Use only unused widgets */ 4783 if (depth > 0 && w->bindas != -1) { 4784 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4785 HDA_BOOTVERBOSE( 4786 device_printf(devinfo->codec->sc->dev, 4787 " %*snid %d found output association %d\n", 4788 depth + 1, "", w->nid, w->bindas); 4789 ); 4790 return (1); 4791 } else { 4792 HDA_BOOTVERBOSE( 4793 device_printf(devinfo->codec->sc->dev, 4794 " %*snid %d busy by input association %d\n", 4795 depth + 1, "", w->nid, w->bindas); 4796 ); 4797 return (0); 4798 } 4799 } 4800 4801 switch (w->type) { 4802 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4803 /* Do not traverse input. AD1988 has digital monitor 4804 for which we are not ready. */ 4805 break; 4806 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4807 if (depth > 0) 4808 break; 4809 /* Fall */ 4810 default: 4811 /* Try to find reachable ADCs with specified nid. */ 4812 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4813 wc = hdac_widget_get(devinfo, j); 4814 if (wc == NULL || wc->enable == 0) 4815 continue; 4816 for (i = 0; i < wc->nconns; i++) { 4817 if (wc->connsenable[i] == 0) 4818 continue; 4819 if (wc->conns[i] != nid) 4820 continue; 4821 if (hdac_audio_trace_to_out(devinfo, 4822 j, depth + 1) != 0) { 4823 res = 1; 4824 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4825 wc->selconn == -1) 4826 wc->selconn = i; 4827 } 4828 } 4829 } 4830 break; 4831 } 4832 if (res) 4833 w->bindas = -2; 4834 4835 HDA_BOOTVERBOSE( 4836 device_printf(devinfo->codec->sc->dev, 4837 " %*snid %d returned %d\n", 4838 depth + 1, "", w->nid, res); 4839 ); 4840 return (res); 4841} 4842 4843/* 4844 * Trace extra associations (beeper, monitor) 4845 */ 4846static void 4847hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4848{ 4849 struct hdac_audio_as *as = devinfo->function.audio.as; 4850 struct hdac_widget *w; 4851 int j; 4852 4853 /* Input monitor */ 4854 /* Find mixer associated with input, but supplying signal 4855 for output associations. Hope it will be input monitor. */ 4856 HDA_BOOTVERBOSE( 4857 device_printf(devinfo->codec->sc->dev, 4858 "Tracing input monitor\n"); 4859 ); 4860 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4861 w = hdac_widget_get(devinfo, j); 4862 if (w == NULL || w->enable == 0) 4863 continue; 4864 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4865 continue; 4866 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 4867 continue; 4868 HDA_BOOTVERBOSE( 4869 device_printf(devinfo->codec->sc->dev, 4870 " Tracing nid %d to out\n", 4871 j); 4872 ); 4873 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 4874 HDA_BOOTVERBOSE( 4875 device_printf(devinfo->codec->sc->dev, 4876 " nid %d is input monitor\n", 4877 w->nid); 4878 ); 4879 w->pflags |= HDA_ADC_MONITOR; 4880 w->ossdev = SOUND_MIXER_IMIX; 4881 } 4882 } 4883 4884 /* Beeper */ 4885 HDA_BOOTVERBOSE( 4886 device_printf(devinfo->codec->sc->dev, 4887 "Tracing beeper\n"); 4888 ); 4889 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4890 w = hdac_widget_get(devinfo, j); 4891 if (w == NULL || w->enable == 0) 4892 continue; 4893 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 4894 continue; 4895 HDA_BOOTVERBOSE( 4896 device_printf(devinfo->codec->sc->dev, 4897 " Tracing nid %d to out\n", 4898 j); 4899 ); 4900 hdac_audio_trace_to_out(devinfo, w->nid, 0); 4901 w->bindas = -2; 4902 } 4903} 4904 4905/* 4906 * Bind assotiations to PCM channels 4907 */ 4908static void 4909hdac_audio_bind_as(struct hdac_devinfo *devinfo) 4910{ 4911 struct hdac_softc *sc = devinfo->codec->sc; 4912 struct hdac_audio_as *as = devinfo->function.audio.as; 4913 int j, cnt = 0, free; 4914 4915 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 4916 if (as[j].enable) 4917 cnt++; 4918 } 4919 if (sc->num_chans == 0) { 4920 sc->chans = (struct hdac_chan *)malloc( 4921 sizeof(struct hdac_chan) * cnt, 4922 M_HDAC, M_ZERO | M_NOWAIT); 4923 if (sc->chans == NULL) { 4924 device_printf(devinfo->codec->sc->dev, 4925 "Channels memory allocation failed!\n"); 4926 return; 4927 } 4928 } else { 4929 sc->chans = (struct hdac_chan *)realloc(sc->chans, 4930 sizeof(struct hdac_chan) * cnt, 4931 M_HDAC, M_ZERO | M_NOWAIT); 4932 if (sc->chans == NULL) { 4933 sc->num_chans = 0; 4934 device_printf(devinfo->codec->sc->dev, 4935 "Channels memory allocation failed!\n"); 4936 return; 4937 } 4938 } 4939 free = sc->num_chans; 4940 sc->num_chans += cnt; 4941 4942 for (j = free; j < free + cnt; j++) { 4943 devinfo->codec->sc->chans[j].devinfo = devinfo; 4944 devinfo->codec->sc->chans[j].as = -1; 4945 } 4946 4947 /* Assign associations in order of their numbers, */ 4948 free = 0; 4949 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 4950 if (as[j].enable == 0) 4951 continue; 4952 4953 as[j].chan = free; 4954 devinfo->codec->sc->chans[free].as = j; 4955 if (as[j].dir == HDA_CTL_IN) { 4956 devinfo->codec->sc->chans[free].dir = PCMDIR_REC; 4957 devinfo->function.audio.reccnt++; 4958 } else { 4959 devinfo->codec->sc->chans[free].dir = PCMDIR_PLAY; 4960 devinfo->function.audio.playcnt++; 4961 } 4962 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 4963 free++; 4964 } 4965} 4966 4967static void 4968hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 4969{ 4970 struct hdac_widget *w; 4971 int i; 4972 4973 /* Disable power and volume widgets. */ 4974 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4975 w = hdac_widget_get(devinfo, i); 4976 if (w == NULL || w->enable == 0) 4977 continue; 4978 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 4979 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 4980 w->enable = 0; 4981 HDA_BOOTVERBOSE( 4982 device_printf(devinfo->codec->sc->dev, 4983 " Disabling nid %d due to it's" 4984 " non-audio type.\n", 4985 w->nid); 4986 ); 4987 } 4988 } 4989} 4990 4991static void 4992hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 4993{ 4994 struct hdac_widget *w, *cw; 4995 struct hdac_audio_ctl *ctl; 4996 int done, found, i, j, k; 4997 4998 /* Disable useless pins. */ 4999 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5000 w = hdac_widget_get(devinfo, i); 5001 if (w == NULL || w->enable == 0) 5002 continue; 5003 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5004 (w->wclass.pin.config & 5005 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5006 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5007 w->enable = 0; 5008 HDA_BOOTVERBOSE( 5009 device_printf(devinfo->codec->sc->dev, 5010 " Disabling pin nid %d due" 5011 " to None connectivity.\n", 5012 w->nid); 5013 ); 5014 } 5015 } 5016 do { 5017 done = 1; 5018 /* Disable and mute controls for disabled widgets. */ 5019 i = 0; 5020 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5021 if (ctl->enable == 0) 5022 continue; 5023 if (ctl->widget->enable == 0 || 5024 (ctl->childwidget != NULL && 5025 ctl->childwidget->enable == 0)) { 5026 ctl->forcemute = 1; 5027 ctl->muted = HDA_AMP_MUTE_ALL; 5028 ctl->left = 0; 5029 ctl->right = 0; 5030 ctl->enable = 0; 5031 if (ctl->ndir == HDA_CTL_IN) 5032 ctl->widget->connsenable[ctl->index] = 0; 5033 done = 0; 5034 HDA_BOOTVERBOSE( 5035 device_printf(devinfo->codec->sc->dev, 5036 " Disabling ctl %d nid %d cnid %d due" 5037 " to disabled widget.\n", i, 5038 ctl->widget->nid, 5039 (ctl->childwidget != NULL)? 5040 ctl->childwidget->nid:-1); 5041 ); 5042 } 5043 } 5044 /* Disable useless widgets. */ 5045 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5046 w = hdac_widget_get(devinfo, i); 5047 if (w == NULL || w->enable == 0) 5048 continue; 5049 /* Disable inputs with disabled child widgets. */ 5050 for (j = 0; j < w->nconns; j++) { 5051 if (w->connsenable[j]) { 5052 cw = hdac_widget_get(devinfo, w->conns[j]); 5053 if (cw == NULL || cw->enable == 0) { 5054 w->connsenable[j] = 0; 5055 HDA_BOOTVERBOSE( 5056 device_printf(devinfo->codec->sc->dev, 5057 " Disabling nid %d connection %d due" 5058 " to disabled child widget.\n", 5059 i, j); 5060 ); 5061 } 5062 } 5063 } 5064 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5065 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5066 continue; 5067 /* Disable mixers and selectors without inputs. */ 5068 found = 0; 5069 for (j = 0; j < w->nconns; j++) { 5070 if (w->connsenable[j]) { 5071 found = 1; 5072 break; 5073 } 5074 } 5075 if (found == 0) { 5076 w->enable = 0; 5077 done = 0; 5078 HDA_BOOTVERBOSE( 5079 device_printf(devinfo->codec->sc->dev, 5080 " Disabling nid %d due to all it's" 5081 " inputs disabled.\n", w->nid); 5082 ); 5083 } 5084 /* Disable nodes without consumers. */ 5085 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5086 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5087 continue; 5088 found = 0; 5089 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5090 cw = hdac_widget_get(devinfo, k); 5091 if (cw == NULL || cw->enable == 0) 5092 continue; 5093 for (j = 0; j < cw->nconns; j++) { 5094 if (cw->connsenable[j] && cw->conns[j] == i) { 5095 found = 1; 5096 break; 5097 } 5098 } 5099 } 5100 if (found == 0) { 5101 w->enable = 0; 5102 done = 0; 5103 HDA_BOOTVERBOSE( 5104 device_printf(devinfo->codec->sc->dev, 5105 " Disabling nid %d due to all it's" 5106 " consumers disabled.\n", w->nid); 5107 ); 5108 } 5109 } 5110 } while (done == 0); 5111 5112} 5113 5114static void 5115hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5116{ 5117 struct hdac_audio_as *as = devinfo->function.audio.as; 5118 struct hdac_widget *w, *cw; 5119 struct hdac_audio_ctl *ctl; 5120 int i, j, k; 5121 5122 /* Disable unassosiated widgets. */ 5123 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5124 w = hdac_widget_get(devinfo, i); 5125 if (w == NULL || w->enable == 0) 5126 continue; 5127 if (w->bindas == -1) { 5128 w->enable = 0; 5129 HDA_BOOTVERBOSE( 5130 device_printf(devinfo->codec->sc->dev, 5131 " Disabling unassociated nid %d.\n", 5132 w->nid); 5133 ); 5134 } 5135 } 5136 /* Disable input connections on input pin and 5137 * output on output. */ 5138 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5139 w = hdac_widget_get(devinfo, i); 5140 if (w == NULL || w->enable == 0) 5141 continue; 5142 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5143 continue; 5144 if (w->bindas < 0) 5145 continue; 5146 if (as[w->bindas].dir == HDA_CTL_IN) { 5147 for (j = 0; j < w->nconns; j++) { 5148 if (w->connsenable[j] == 0) 5149 continue; 5150 w->connsenable[j] = 0; 5151 HDA_BOOTVERBOSE( 5152 device_printf(devinfo->codec->sc->dev, 5153 " Disabling connection to input pin " 5154 "nid %d conn %d.\n", 5155 i, j); 5156 ); 5157 } 5158 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5159 HDA_CTL_IN, -1, 1); 5160 if (ctl && ctl->enable) { 5161 ctl->forcemute = 1; 5162 ctl->muted = HDA_AMP_MUTE_ALL; 5163 ctl->left = 0; 5164 ctl->right = 0; 5165 ctl->enable = 0; 5166 } 5167 } else { 5168 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5169 HDA_CTL_OUT, -1, 1); 5170 if (ctl && ctl->enable) { 5171 ctl->forcemute = 1; 5172 ctl->muted = HDA_AMP_MUTE_ALL; 5173 ctl->left = 0; 5174 ctl->right = 0; 5175 ctl->enable = 0; 5176 } 5177 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5178 cw = hdac_widget_get(devinfo, k); 5179 if (cw == NULL || cw->enable == 0) 5180 continue; 5181 for (j = 0; j < cw->nconns; j++) { 5182 if (cw->connsenable[j] && cw->conns[j] == i) { 5183 cw->connsenable[j] = 0; 5184 HDA_BOOTVERBOSE( 5185 device_printf(devinfo->codec->sc->dev, 5186 " Disabling connection from output pin " 5187 "nid %d conn %d cnid %d.\n", 5188 k, j, i); 5189 ); 5190 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5191 cw->nconns > 1) 5192 continue; 5193 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5194 HDA_CTL_IN, j, 1); 5195 if (ctl && ctl->enable) { 5196 ctl->forcemute = 1; 5197 ctl->muted = HDA_AMP_MUTE_ALL; 5198 ctl->left = 0; 5199 ctl->right = 0; 5200 ctl->enable = 0; 5201 } 5202 } 5203 } 5204 } 5205 } 5206 } 5207} 5208 5209static void 5210hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5211{ 5212 struct hdac_audio_as *as = devinfo->function.audio.as; 5213 struct hdac_widget *w; 5214 int i, j; 5215 5216 /* On playback path we can safely disable all unseleted inputs. */ 5217 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5218 w = hdac_widget_get(devinfo, i); 5219 if (w == NULL || w->enable == 0) 5220 continue; 5221 if (w->nconns <= 1) 5222 continue; 5223 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5224 continue; 5225 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5226 continue; 5227 for (j = 0; j < w->nconns; j++) { 5228 if (w->connsenable[j] == 0) 5229 continue; 5230 if (w->selconn < 0 || w->selconn == j) 5231 continue; 5232 w->connsenable[j] = 0; 5233 HDA_BOOTVERBOSE( 5234 device_printf(devinfo->codec->sc->dev, 5235 " Disabling unselected connection " 5236 "nid %d conn %d.\n", 5237 i, j); 5238 ); 5239 } 5240 } 5241} 5242 5243static void 5244hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5245{ 5246 struct hdac_widget *w, *cw; 5247 struct hdac_audio_ctl *ctl; 5248 int i, j; 5249 5250 /* Disable crossassociatement connections. */ 5251 /* ... using selectors */ 5252 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5253 w = hdac_widget_get(devinfo, i); 5254 if (w == NULL || w->enable == 0) 5255 continue; 5256 if (w->nconns <= 1) 5257 continue; 5258 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5259 continue; 5260 if (w->bindas == -2) 5261 continue; 5262 for (j = 0; j < w->nconns; j++) { 5263 if (w->connsenable[j] == 0) 5264 continue; 5265 cw = hdac_widget_get(devinfo, w->conns[j]); 5266 if (cw == NULL || w->enable == 0) 5267 continue; 5268 if (w->bindas == cw->bindas || cw->bindas == -2) 5269 continue; 5270 w->connsenable[j] = 0; 5271 HDA_BOOTVERBOSE( 5272 device_printf(devinfo->codec->sc->dev, 5273 " Disabling crossassociatement connection " 5274 "nid %d conn %d cnid %d.\n", 5275 i, j, cw->nid); 5276 ); 5277 } 5278 } 5279 /* ... using controls */ 5280 i = 0; 5281 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5282 if (ctl->enable == 0 || ctl->childwidget == NULL) 5283 continue; 5284 if (ctl->widget->bindas == -2 || 5285 ctl->childwidget->bindas == -2) 5286 continue; 5287 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5288 ctl->forcemute = 1; 5289 ctl->muted = HDA_AMP_MUTE_ALL; 5290 ctl->left = 0; 5291 ctl->right = 0; 5292 ctl->enable = 0; 5293 if (ctl->ndir == HDA_CTL_IN) 5294 ctl->widget->connsenable[ctl->index] = 0; 5295 HDA_BOOTVERBOSE( 5296 device_printf(devinfo->codec->sc->dev, 5297 " Disabling crossassociatement connection " 5298 "ctl %d nid %d cnid %d.\n", i, 5299 ctl->widget->nid, 5300 ctl->childwidget->nid); 5301 ); 5302 } 5303 } 5304 5305} 5306 5307#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5308 5309/* 5310 * Find controls to control amplification for source. 5311 */ 5312static int 5313hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5314 int ossdev, int ctlable, int depth, int need) 5315{ 5316 struct hdac_widget *w, *wc; 5317 struct hdac_audio_ctl *ctl; 5318 int i, j, conns = 0, rneed; 5319 5320 if (depth > HDA_PARSE_MAXDEPTH) 5321 return (need); 5322 5323 w = hdac_widget_get(devinfo, nid); 5324 if (w == NULL || w->enable == 0) 5325 return (need); 5326 5327 /* Count number of active inputs. */ 5328 if (depth > 0) { 5329 for (j = 0; j < w->nconns; j++) { 5330 if (w->connsenable[j]) 5331 conns++; 5332 } 5333 } 5334 5335 /* If this is not a first step - use input mixer. 5336 Pins have common input ctl so care must be taken. */ 5337 if (depth > 0 && ctlable && (conns == 1 || 5338 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5339 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5340 index, 1); 5341 if (ctl) { 5342 if (HDA_CTL_GIVE(ctl) & need) 5343 ctl->ossmask |= (1 << ossdev); 5344 else 5345 ctl->possmask |= (1 << ossdev); 5346 need &= ~HDA_CTL_GIVE(ctl); 5347 } 5348 } 5349 5350 /* If widget has own ossdev - not traverse it. 5351 It will be traversed on it's own. */ 5352 if (w->ossdev >= 0 && depth > 0) 5353 return (need); 5354 5355 /* We must not traverse pin */ 5356 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5357 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5358 depth > 0) 5359 return (need); 5360 5361 /* record that this widget exports such signal, */ 5362 w->ossmask |= (1 << ossdev); 5363 5364 /* If signals mixed, we can't assign controls farther. 5365 * Ignore this on depth zero. Caller must knows why. 5366 * Ignore this for static selectors if this input selected. 5367 */ 5368 if (conns > 1) 5369 ctlable = 0; 5370 5371 if (ctlable) { 5372 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5373 if (ctl) { 5374 if (HDA_CTL_GIVE(ctl) & need) 5375 ctl->ossmask |= (1 << ossdev); 5376 else 5377 ctl->possmask |= (1 << ossdev); 5378 need &= ~HDA_CTL_GIVE(ctl); 5379 } 5380 } 5381 5382 rneed = 0; 5383 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5384 wc = hdac_widget_get(devinfo, i); 5385 if (wc == NULL || wc->enable == 0) 5386 continue; 5387 for (j = 0; j < wc->nconns; j++) { 5388 if (wc->connsenable[j] && wc->conns[j] == nid) { 5389 rneed |= hdac_audio_ctl_source_amp(devinfo, 5390 wc->nid, j, ossdev, ctlable, depth + 1, need); 5391 } 5392 } 5393 } 5394 rneed &= need; 5395 5396 return (rneed); 5397} 5398 5399/* 5400 * Find controls to control amplification for destination. 5401 */ 5402static void 5403hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5404 int ossdev, int depth, int need) 5405{ 5406 struct hdac_audio_as *as = devinfo->function.audio.as; 5407 struct hdac_widget *w, *wc; 5408 struct hdac_audio_ctl *ctl; 5409 int i, j, consumers; 5410 5411 if (depth > HDA_PARSE_MAXDEPTH) 5412 return; 5413 5414 w = hdac_widget_get(devinfo, nid); 5415 if (w == NULL || w->enable == 0) 5416 return; 5417 5418 if (depth > 0) { 5419 /* If this node produce output for several consumers, 5420 we can't touch it. */ 5421 consumers = 0; 5422 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5423 wc = hdac_widget_get(devinfo, i); 5424 if (wc == NULL || wc->enable == 0) 5425 continue; 5426 for (j = 0; j < wc->nconns; j++) { 5427 if (wc->connsenable[j] && wc->conns[j] == nid) 5428 consumers++; 5429 } 5430 } 5431 /* The only exception is if real HP redirection is configured 5432 and this is a duplication point. 5433 XXX: Actually exception is not completely correct. 5434 XXX: Duplication point check is not perfect. */ 5435 if ((consumers == 2 && (w->bindas < 0 || 5436 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5437 (w->bindseqmask & (1 << 15)) == 0)) || 5438 consumers > 2) 5439 return; 5440 5441 /* Else use it's output mixer. */ 5442 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5443 HDA_CTL_OUT, -1, 1); 5444 if (ctl) { 5445 if (HDA_CTL_GIVE(ctl) & need) 5446 ctl->ossmask |= (1 << ossdev); 5447 else 5448 ctl->possmask |= (1 << ossdev); 5449 need &= ~HDA_CTL_GIVE(ctl); 5450 } 5451 } 5452 5453 /* We must not traverse pin */ 5454 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5455 depth > 0) 5456 return; 5457 5458 for (i = 0; i < w->nconns; i++) { 5459 int tneed = need; 5460 if (w->connsenable[i] == 0) 5461 continue; 5462 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5463 HDA_CTL_IN, i, 1); 5464 if (ctl) { 5465 if (HDA_CTL_GIVE(ctl) & tneed) 5466 ctl->ossmask |= (1 << ossdev); 5467 else 5468 ctl->possmask |= (1 << ossdev); 5469 tneed &= ~HDA_CTL_GIVE(ctl); 5470 } 5471 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5472 depth + 1, tneed); 5473 } 5474} 5475 5476/* 5477 * Assign OSS names to sound sources 5478 */ 5479static void 5480hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5481{ 5482 struct hdac_audio_as *as = devinfo->function.audio.as; 5483 struct hdac_widget *w; 5484 int i, j; 5485 int type = -1, use, used = 0; 5486 static const int types[7][13] = { 5487 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5488 SOUND_MIXER_LINE3, -1 }, /* line */ 5489 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5490 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5491 { SOUND_MIXER_CD, -1 }, /* cd */ 5492 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5493 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5494 -1 }, /* digital */ 5495 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5496 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5497 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5498 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5499 -1 } /* others */ 5500 }; 5501 5502 /* Surely known names */ 5503 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5504 w = hdac_widget_get(devinfo, i); 5505 if (w == NULL || w->enable == 0) 5506 continue; 5507 if (w->bindas == -1) 5508 continue; 5509 use = -1; 5510 switch (w->type) { 5511 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5512 if (as[w->bindas].dir == HDA_CTL_OUT) 5513 break; 5514 type = -1; 5515 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5516 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5517 type = 0; 5518 break; 5519 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5520 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5521 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5522 break; 5523 type = 1; 5524 break; 5525 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5526 type = 3; 5527 break; 5528 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5529 type = 4; 5530 break; 5531 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5532 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5533 type = 5; 5534 break; 5535 } 5536 if (type == -1) 5537 break; 5538 j = 0; 5539 while (types[type][j] >= 0 && 5540 (used & (1 << types[type][j])) != 0) { 5541 j++; 5542 } 5543 if (types[type][j] >= 0) 5544 use = types[type][j]; 5545 break; 5546 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5547 use = SOUND_MIXER_PCM; 5548 break; 5549 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5550 use = SOUND_MIXER_SPEAKER; 5551 break; 5552 default: 5553 break; 5554 } 5555 if (use >= 0) { 5556 w->ossdev = use; 5557 used |= (1 << use); 5558 } 5559 } 5560 /* Semi-known names */ 5561 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5562 w = hdac_widget_get(devinfo, i); 5563 if (w == NULL || w->enable == 0) 5564 continue; 5565 if (w->ossdev >= 0) 5566 continue; 5567 if (w->bindas == -1) 5568 continue; 5569 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5570 continue; 5571 if (as[w->bindas].dir == HDA_CTL_OUT) 5572 continue; 5573 type = -1; 5574 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5575 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5576 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5577 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5578 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5579 type = 0; 5580 break; 5581 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5582 type = 2; 5583 break; 5584 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5585 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5586 type = 5; 5587 break; 5588 } 5589 if (type == -1) 5590 break; 5591 j = 0; 5592 while (types[type][j] >= 0 && 5593 (used & (1 << types[type][j])) != 0) { 5594 j++; 5595 } 5596 if (types[type][j] >= 0) { 5597 w->ossdev = types[type][j]; 5598 used |= (1 << types[type][j]); 5599 } 5600 } 5601 /* Others */ 5602 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5603 w = hdac_widget_get(devinfo, i); 5604 if (w == NULL || w->enable == 0) 5605 continue; 5606 if (w->ossdev >= 0) 5607 continue; 5608 if (w->bindas == -1) 5609 continue; 5610 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5611 continue; 5612 if (as[w->bindas].dir == HDA_CTL_OUT) 5613 continue; 5614 j = 0; 5615 while (types[6][j] >= 0 && 5616 (used & (1 << types[6][j])) != 0) { 5617 j++; 5618 } 5619 if (types[6][j] >= 0) { 5620 w->ossdev = types[6][j]; 5621 used |= (1 << types[6][j]); 5622 } 5623 } 5624} 5625 5626static void 5627hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5628{ 5629 struct hdac_audio_as *as = devinfo->function.audio.as; 5630 int j, res; 5631 5632 HDA_BOOTVERBOSE( 5633 device_printf(devinfo->codec->sc->dev, 5634 "HWiP: HDA Widget Parser - Revision %d\n", 5635 HDA_WIDGET_PARSER_REV); 5636 ); 5637 5638 /* Trace all associations in order of their numbers, */ 5639 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5640 if (as[j].enable == 0) 5641 continue; 5642 HDA_BOOTVERBOSE( 5643 device_printf(devinfo->codec->sc->dev, 5644 "Tracing association %d (%d)\n", j, as[j].index); 5645 ); 5646 if (as[j].dir == HDA_CTL_OUT) { 5647retry: 5648 res = hdac_audio_trace_as_out(devinfo, j, 0); 5649 if (res == 0 && as[j].hpredir >= 0 && 5650 as[j].fakeredir == 0) { 5651 /* If codec can't do analog HP redirection 5652 try to make it using one more DAC. */ 5653 as[j].fakeredir = 1; 5654 goto retry; 5655 } 5656 } else { 5657 res = hdac_audio_trace_as_in(devinfo, j); 5658 } 5659 if (res) { 5660 HDA_BOOTVERBOSE( 5661 device_printf(devinfo->codec->sc->dev, 5662 "Association %d (%d) trace succeded\n", 5663 j, as[j].index); 5664 ); 5665 } else { 5666 HDA_BOOTVERBOSE( 5667 device_printf(devinfo->codec->sc->dev, 5668 "Association %d (%d) trace failed\n", 5669 j, as[j].index); 5670 ); 5671 as[j].enable = 0; 5672 } 5673 } 5674 5675 /* Trace mixer and beeper pseudo associations. */ 5676 hdac_audio_trace_as_extra(devinfo); 5677} 5678 5679static void 5680hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5681{ 5682 struct hdac_audio_as *as = devinfo->function.audio.as; 5683 struct hdac_audio_ctl *ctl; 5684 struct hdac_widget *w; 5685 int i; 5686 5687 /* Assign mixers to the tree. */ 5688 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5689 w = hdac_widget_get(devinfo, i); 5690 if (w == NULL || w->enable == 0) 5691 continue; 5692 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5693 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5694 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5695 as[w->bindas].dir == HDA_CTL_IN)) { 5696 if (w->ossdev < 0) 5697 continue; 5698 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5699 w->ossdev, 1, 0, 1); 5700 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5701 if (w->ossdev < 0) 5702 continue; 5703 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5704 w->ossdev, 1, 0, 1)) { 5705 /* If we are unable to control input monitor 5706 as source - try to control it as destination. */ 5707 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5708 w->ossdev, 0, 1); 5709 } 5710 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5711 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5712 SOUND_MIXER_RECLEV, 0, 1); 5713 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5714 as[w->bindas].dir == HDA_CTL_OUT) { 5715 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5716 SOUND_MIXER_VOLUME, 0, 1); 5717 } 5718 } 5719 /* Treat unrequired as possible. */ 5720 i = 0; 5721 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5722 if (ctl->ossmask == 0) 5723 ctl->ossmask = ctl->possmask; 5724 } 5725} 5726 5727static void 5728hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5729{ 5730 struct hdac_audio_as *as = devinfo->function.audio.as; 5731 struct hdac_widget *w; 5732 uint32_t pincap; 5733 int i; 5734 5735 for (i = 0; i < devinfo->nodecnt; i++) { 5736 w = &devinfo->widget[i]; 5737 if (w == NULL) 5738 continue; 5739 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5740 continue; 5741 5742 pincap = w->wclass.pin.cap; 5743 5744 /* Disable everything. */ 5745 w->wclass.pin.ctrl &= ~( 5746 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5747 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5748 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5749 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5750 5751 if (w->enable == 0 || 5752 w->bindas < 0 || as[w->bindas].enable == 0) { 5753 /* Pin is unused so left it disabled. */ 5754 continue; 5755 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5756 /* Input pin, configure for input. */ 5757 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5758 w->wclass.pin.ctrl |= 5759 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5760 5761 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5762 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5763 w->wclass.pin.ctrl |= 5764 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5765 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5766 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5767 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5768 w->wclass.pin.ctrl |= 5769 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5770 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5771 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5772 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5773 w->wclass.pin.ctrl |= 5774 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5775 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5776 } else { 5777 /* Output pin, configure for output. */ 5778 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5779 w->wclass.pin.ctrl |= 5780 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5781 5782 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5783 (w->wclass.pin.config & 5784 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5785 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5786 w->wclass.pin.ctrl |= 5787 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5788 5789 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5790 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5791 w->wclass.pin.ctrl |= 5792 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5793 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5794 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5795 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5796 w->wclass.pin.ctrl |= 5797 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5798 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5799 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5800 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5801 w->wclass.pin.ctrl |= 5802 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5803 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5804 } 5805 } 5806} 5807 5808static void 5809hdac_audio_commit(struct hdac_devinfo *devinfo) 5810{ 5811 struct hdac_softc *sc = devinfo->codec->sc; 5812 struct hdac_widget *w; 5813 nid_t cad; 5814 uint32_t gdata, gmask, gdir; 5815 int commitgpio, numgpio; 5816 int i; 5817 5818 cad = devinfo->codec->cad; 5819 5820 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5821 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5822 0x7e7, 0), cad); 5823 5824 gdata = 0; 5825 gmask = 0; 5826 gdir = 0; 5827 commitgpio = 0; 5828 5829 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5830 devinfo->function.audio.gpio); 5831 5832 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5833 commitgpio = (numgpio > 0) ? 1 : 0; 5834 else { 5835 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5836 if (!(devinfo->function.audio.quirks & 5837 (1 << i))) 5838 continue; 5839 if (commitgpio == 0) { 5840 commitgpio = 1; 5841 HDA_BOOTVERBOSE( 5842 gdata = hdac_command(sc, 5843 HDA_CMD_GET_GPIO_DATA(cad, 5844 devinfo->nid), cad); 5845 gmask = hdac_command(sc, 5846 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5847 devinfo->nid), cad); 5848 gdir = hdac_command(sc, 5849 HDA_CMD_GET_GPIO_DIRECTION(cad, 5850 devinfo->nid), cad); 5851 device_printf(sc->dev, 5852 "GPIO init: data=0x%08x " 5853 "mask=0x%08x dir=0x%08x\n", 5854 gdata, gmask, gdir); 5855 gdata = 0; 5856 gmask = 0; 5857 gdir = 0; 5858 ); 5859 } 5860 gdata |= 1 << i; 5861 gmask |= 1 << i; 5862 gdir |= 1 << i; 5863 } 5864 } 5865 5866 if (commitgpio != 0) { 5867 HDA_BOOTVERBOSE( 5868 device_printf(sc->dev, 5869 "GPIO commit: data=0x%08x mask=0x%08x " 5870 "dir=0x%08x\n", 5871 gdata, gmask, gdir); 5872 ); 5873 hdac_command(sc, 5874 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5875 gmask), cad); 5876 hdac_command(sc, 5877 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5878 gdir), cad); 5879 hdac_command(sc, 5880 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5881 gdata), cad); 5882 } 5883 5884 for (i = 0; i < devinfo->nodecnt; i++) { 5885 w = &devinfo->widget[i]; 5886 if (w == NULL) 5887 continue; 5888 if (w->selconn == -1) 5889 w->selconn = 0; 5890 if (w->nconns > 0) 5891 hdac_widget_connection_select(w, w->selconn); 5892 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5893 hdac_command(sc, 5894 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5895 w->wclass.pin.ctrl), cad); 5896 } 5897 if (w->param.eapdbtl != HDAC_INVALID) { 5898 uint32_t val; 5899 5900 val = w->param.eapdbtl; 5901 if (devinfo->function.audio.quirks & 5902 HDA_QUIRK_EAPDINV) 5903 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5904 hdac_command(sc, 5905 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5906 val), cad); 5907 5908 } 5909 DELAY(1000); 5910 } 5911} 5912 5913static void 5914hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5915{ 5916 struct hdac_audio_ctl *ctl; 5917 int i, z; 5918 5919 i = 0; 5920 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5921 if (ctl->enable == 0) { 5922 /* Mute disabled controls. */ 5923 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 5924 continue; 5925 } 5926 /* Init controls to 0dB amplification. */ 5927 z = ctl->offset; 5928 if (z > ctl->step) 5929 z = ctl->step; 5930 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 5931 } 5932} 5933 5934static void 5935hdac_powerup(struct hdac_devinfo *devinfo) 5936{ 5937 struct hdac_softc *sc = devinfo->codec->sc; 5938 nid_t cad = devinfo->codec->cad; 5939 int i; 5940 5941 hdac_command(sc, 5942 HDA_CMD_SET_POWER_STATE(cad, 5943 devinfo->nid, HDA_CMD_POWER_STATE_D0), 5944 cad); 5945 DELAY(100); 5946 5947 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5948 hdac_command(sc, 5949 HDA_CMD_SET_POWER_STATE(cad, 5950 i, HDA_CMD_POWER_STATE_D0), 5951 cad); 5952 } 5953 DELAY(1000); 5954} 5955 5956static int 5957hdac_pcmchannel_setup(struct hdac_chan *ch) 5958{ 5959 struct hdac_devinfo *devinfo = ch->devinfo; 5960 struct hdac_audio_as *as = devinfo->function.audio.as; 5961 struct hdac_widget *w; 5962 uint32_t cap, fmtcap, pcmcap; 5963 int i, j, ret, max; 5964 5965 ch->caps = hdac_caps; 5966 ch->caps.fmtlist = ch->fmtlist; 5967 ch->bit16 = 1; 5968 ch->bit32 = 0; 5969 ch->pcmrates[0] = 48000; 5970 ch->pcmrates[1] = 0; 5971 5972 ret = 0; 5973 fmtcap = devinfo->function.audio.supp_stream_formats; 5974 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5975 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5976 5977 for (i = 0; i < 16 && ret < max; i++) { 5978 /* Check as is correct */ 5979 if (ch->as < 0) 5980 break; 5981 /* Cound only present DACs */ 5982 if (as[ch->as].dacs[i] <= 0) 5983 continue; 5984 /* Ignore duplicates */ 5985 for (j = 0; j < ret; j++) { 5986 if (ch->io[j] == as[ch->as].dacs[i]) 5987 break; 5988 } 5989 if (j < ret) 5990 continue; 5991 5992 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 5993 if (w == NULL || w->enable == 0) 5994 continue; 5995 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 5996 continue; 5997 cap = w->param.supp_stream_formats; 5998 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5999 }*/ 6000 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6001 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6002 continue; 6003 /* Many codec does not declare AC3 support on SPDIF. 6004 I don't beleave that they doesn't support it! */ 6005 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6006 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6007 if (ret == 0) { 6008 fmtcap = cap; 6009 pcmcap = w->param.supp_pcm_size_rate; 6010 } else { 6011 fmtcap &= cap; 6012 pcmcap &= w->param.supp_pcm_size_rate; 6013 } 6014 ch->io[ret++] = as[ch->as].dacs[i]; 6015 } 6016 ch->io[ret] = -1; 6017 6018 ch->supp_stream_formats = fmtcap; 6019 ch->supp_pcm_size_rate = pcmcap; 6020 6021 /* 6022 * 8bit = 0 6023 * 16bit = 1 6024 * 20bit = 2 6025 * 24bit = 3 6026 * 32bit = 4 6027 */ 6028 if (ret > 0) { 6029 i = 0; 6030 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6031 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6032 ch->bit16 = 1; 6033 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6034 ch->bit16 = 0; 6035 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6036 ch->bit32 = 4; 6037 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6038 ch->bit32 = 3; 6039 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6040 ch->bit32 = 2; 6041 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6042 ch->fmtlist[i++] = AFMT_S16_LE; 6043 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6044 if (ch->bit32 > 0) { 6045 if (!(devinfo->function.audio.quirks & 6046 HDA_QUIRK_FORCESTEREO)) 6047 ch->fmtlist[i++] = AFMT_S32_LE; 6048 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6049 } 6050 } 6051 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6052 ch->fmtlist[i++] = AFMT_AC3; 6053 } 6054 ch->fmtlist[i] = 0; 6055 i = 0; 6056 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6057 ch->pcmrates[i++] = 8000; 6058 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6059 ch->pcmrates[i++] = 11025; 6060 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6061 ch->pcmrates[i++] = 16000; 6062 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6063 ch->pcmrates[i++] = 22050; 6064 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6065 ch->pcmrates[i++] = 32000; 6066 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6067 ch->pcmrates[i++] = 44100; 6068 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6069 ch->pcmrates[i++] = 48000; 6070 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6071 ch->pcmrates[i++] = 88200; 6072 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6073 ch->pcmrates[i++] = 96000; 6074 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6075 ch->pcmrates[i++] = 176400; 6076 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6077 ch->pcmrates[i++] = 192000; 6078 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6079 ch->pcmrates[i] = 0; 6080 if (i > 0) { 6081 ch->caps.minspeed = ch->pcmrates[0]; 6082 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6083 } 6084 } 6085 6086 return (ret); 6087} 6088 6089static void 6090hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6091{ 6092 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6093 struct hdac_audio_ctl *ctl; 6094 struct hdac_softc *sc = devinfo->codec->sc; 6095 char buf[64]; 6096 int i, j, printed; 6097 6098 if (flag == 0) { 6099 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6100 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6101 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6102 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6103 } 6104 6105 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6106 if ((flag & (1 << j)) == 0) 6107 continue; 6108 i = 0; 6109 printed = 0; 6110 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6111 if (ctl->enable == 0 || 6112 ctl->widget->enable == 0) 6113 continue; 6114 if (!((pdevinfo->play >= 0 && 6115 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6116 (pdevinfo->rec >= 0 && 6117 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6118 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6119 continue; 6120 if ((ctl->ossmask & (1 << j)) == 0) 6121 continue; 6122 6123 if (printed == 0) { 6124 device_printf(pdevinfo->dev, "\n"); 6125 if (banner != NULL) { 6126 device_printf(pdevinfo->dev, "%s", banner); 6127 } else { 6128 device_printf(pdevinfo->dev, "Unknown Ctl"); 6129 } 6130 printf(" (OSS: %s)\n", 6131 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6132 buf, sizeof(buf))); 6133 device_printf(pdevinfo->dev, " |\n"); 6134 printed = 1; 6135 } 6136 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6137 ctl->widget->nid, 6138 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6139 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6140 printf(" %2d): ", ctl->index); 6141 else 6142 printf("): "); 6143 if (ctl->step > 0) { 6144 printf("%+d/%+ddB (%d steps)%s\n", 6145 (0 - ctl->offset) * (ctl->size + 1) / 4, 6146 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6147 ctl->step + 1, 6148 ctl->mute?" + mute":""); 6149 } else 6150 printf("%s\n", ctl->mute?"mute":""); 6151 } 6152 } 6153} 6154 6155static void 6156hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6157{ 6158 uint32_t cap; 6159 6160 cap = fcap; 6161 if (cap != 0) { 6162 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6163 device_printf(dev, " Format:"); 6164 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6165 printf(" AC3"); 6166 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6167 printf(" FLOAT32"); 6168 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6169 printf(" PCM"); 6170 printf("\n"); 6171 } 6172 cap = pcmcap; 6173 if (cap != 0) { 6174 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6175 device_printf(dev, " PCM size:"); 6176 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6177 printf(" 8"); 6178 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6179 printf(" 16"); 6180 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6181 printf(" 20"); 6182 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6183 printf(" 24"); 6184 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6185 printf(" 32"); 6186 printf("\n"); 6187 device_printf(dev, " PCM rate:"); 6188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6189 printf(" 8"); 6190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6191 printf(" 11"); 6192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6193 printf(" 16"); 6194 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6195 printf(" 22"); 6196 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6197 printf(" 32"); 6198 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6199 printf(" 44"); 6200 printf(" 48"); 6201 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6202 printf(" 88"); 6203 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6204 printf(" 96"); 6205 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6206 printf(" 176"); 6207 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6208 printf(" 192"); 6209 printf("\n"); 6210 } 6211} 6212 6213static void 6214hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6215{ 6216 uint32_t pincap, wcap; 6217 6218 pincap = w->wclass.pin.cap; 6219 wcap = w->param.widget_cap; 6220 6221 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6222 device_printf(sc->dev, " "); 6223 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6224 printf(" ISC"); 6225 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6226 printf(" TRQD"); 6227 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6228 printf(" PDC"); 6229 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6230 printf(" HP"); 6231 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6232 printf(" OUT"); 6233 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6234 printf(" IN"); 6235 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6236 printf(" BAL"); 6237 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6238 printf(" VREF["); 6239 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6240 printf(" 50"); 6241 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6242 printf(" 80"); 6243 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6244 printf(" 100"); 6245 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6246 printf(" GROUND"); 6247 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6248 printf(" HIZ"); 6249 printf(" ]"); 6250 } 6251 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6252 printf(" EAPD"); 6253 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 6254 printf(" : UNSOL"); 6255 printf("\n"); 6256 device_printf(sc->dev, " Pin config: 0x%08x\n", 6257 w->wclass.pin.config); 6258 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6259 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6260 printf(" HP"); 6261 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6262 printf(" IN"); 6263 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6264 printf(" OUT"); 6265 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6266 printf(" VREFs"); 6267 printf("\n"); 6268} 6269 6270static void 6271hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6272{ 6273 struct hdac_softc *sc = w->devinfo->codec->sc; 6274 6275 device_printf(sc->dev, "nid %d 0x%08x as %2d seq %2d %13s %5s " 6276 "jack %2d loc %2d color %7s misc %d%s\n", 6277 w->nid, conf, 6278 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6279 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6280 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6281 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6282 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6283 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6284 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6285 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6286 (w->enable == 0)?" [DISABLED]":""); 6287} 6288 6289static void 6290hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6291{ 6292 struct hdac_widget *w; 6293 int i; 6294 6295 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6296 w = hdac_widget_get(devinfo, i); 6297 if (w == NULL) 6298 continue; 6299 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6300 continue; 6301 hdac_dump_pin_config(w, w->wclass.pin.config); 6302 } 6303} 6304 6305static void 6306hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6307{ 6308 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6309 device_printf(sc->dev, " " 6310 "mute=%d step=%d size=%d offset=%d\n", 6311 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6312 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6313 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6314 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6315} 6316 6317static void 6318hdac_dump_nodes(struct hdac_devinfo *devinfo) 6319{ 6320 struct hdac_softc *sc = devinfo->codec->sc; 6321 static char *ossname[] = SOUND_DEVICE_NAMES; 6322 struct hdac_widget *w, *cw; 6323 char buf[64]; 6324 int i, j; 6325 6326 device_printf(sc->dev, "\n"); 6327 device_printf(sc->dev, "Default Parameter\n"); 6328 device_printf(sc->dev, "-----------------\n"); 6329 hdac_dump_audio_formats(sc->dev, 6330 devinfo->function.audio.supp_stream_formats, 6331 devinfo->function.audio.supp_pcm_size_rate); 6332 device_printf(sc->dev, " IN amp: 0x%08x\n", 6333 devinfo->function.audio.inamp_cap); 6334 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6335 devinfo->function.audio.outamp_cap); 6336 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6337 w = hdac_widget_get(devinfo, i); 6338 if (w == NULL) { 6339 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6340 continue; 6341 } 6342 device_printf(sc->dev, "\n"); 6343 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 6344 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 6345 "DIGITAL" : "ANALOG", 6346 (w->enable == 0) ? " [DISABLED]" : ""); 6347 device_printf(sc->dev, " name: %s\n", w->name); 6348 device_printf(sc->dev, " widget_cap: 0x%08x\n", 6349 w->param.widget_cap); 6350 device_printf(sc->dev, " Parse flags: 0x%x\n", 6351 w->pflags); 6352 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6353 w->bindas, w->bindseqmask); 6354 device_printf(sc->dev, " OSS: %s", 6355 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6356 if (w->ossdev >= 0) 6357 printf(" (%s)", ossname[w->ossdev]); 6358 printf("\n"); 6359 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6360 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6361 hdac_dump_audio_formats(sc->dev, 6362 w->param.supp_stream_formats, 6363 w->param.supp_pcm_size_rate); 6364 } else if (w->type == 6365 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6366 hdac_dump_pin(sc, w); 6367 if (w->param.eapdbtl != HDAC_INVALID) 6368 device_printf(sc->dev, " EAPD: 0x%08x\n", 6369 w->param.eapdbtl); 6370 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6371 w->param.outamp_cap != 0) 6372 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6373 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6374 w->param.inamp_cap != 0) 6375 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6376 device_printf(sc->dev, " connections: %d\n", w->nconns); 6377 if (w->nconns > 0) 6378 device_printf(sc->dev, " |\n"); 6379 for (j = 0; j < w->nconns; j++) { 6380 cw = hdac_widget_get(devinfo, w->conns[j]); 6381 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6382 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6383 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6384 if (cw == NULL) 6385 printf(" [UNKNOWN]"); 6386 else if (cw->enable == 0) 6387 printf(" [DISABLED]"); 6388 if (w->nconns > 1 && w->selconn == j && w->type != 6389 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6390 printf(" (selected)"); 6391 printf("\n"); 6392 } 6393 } 6394 6395} 6396 6397static void 6398hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6399{ 6400 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6401 struct hdac_widget *w, *cw; 6402 char buf[64]; 6403 int i, printed = 0; 6404 6405 if (depth > HDA_PARSE_MAXDEPTH) 6406 return; 6407 6408 w = hdac_widget_get(devinfo, nid); 6409 if (w == NULL || w->enable == 0) 6410 return; 6411 6412 if (depth == 0) 6413 device_printf(pdevinfo->dev, "%*s", 4, ""); 6414 else 6415 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6416 printf("nid=%d [%s]", w->nid, w->name); 6417 6418 if (depth > 0) { 6419 if (w->ossmask == 0) { 6420 printf("\n"); 6421 return; 6422 } 6423 printf(" [src: %s]", 6424 hdac_audio_ctl_ossmixer_mask2allname( 6425 w->ossmask, buf, sizeof(buf))); 6426 if (w->ossdev >= 0) { 6427 printf("\n"); 6428 return; 6429 } 6430 } 6431 printf("\n"); 6432 6433 for (i = 0; i < w->nconns; i++) { 6434 if (w->connsenable[i] == 0) 6435 continue; 6436 cw = hdac_widget_get(devinfo, w->conns[i]); 6437 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6438 continue; 6439 if (printed == 0) { 6440 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6441 printed = 1; 6442 } 6443 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6444 } 6445 6446} 6447 6448static void 6449hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6450{ 6451 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6452 struct hdac_softc *sc = devinfo->codec->sc; 6453 struct hdac_widget *w; 6454 int i, printed = 0; 6455 6456 if (pdevinfo->play < 0) 6457 return; 6458 6459 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6460 w = hdac_widget_get(devinfo, i); 6461 if (w == NULL || w->enable == 0) 6462 continue; 6463 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6464 continue; 6465 if (w->bindas != sc->chans[pdevinfo->play].as) 6466 continue; 6467 if (printed == 0) { 6468 printed = 1; 6469 device_printf(pdevinfo->dev, "\n"); 6470 device_printf(pdevinfo->dev, "Playback:\n"); 6471 } 6472 device_printf(pdevinfo->dev, "\n"); 6473 hdac_dump_dst_nid(pdevinfo, i, 0); 6474 } 6475} 6476 6477static void 6478hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6479{ 6480 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6481 struct hdac_softc *sc = devinfo->codec->sc; 6482 struct hdac_widget *w; 6483 int i; 6484 int printed = 0; 6485 6486 if (pdevinfo->rec < 0) 6487 return; 6488 6489 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6490 w = hdac_widget_get(devinfo, i); 6491 if (w == NULL || w->enable == 0) 6492 continue; 6493 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6494 continue; 6495 if (w->bindas != sc->chans[pdevinfo->rec].as) 6496 continue; 6497 if (printed == 0) { 6498 printed = 1; 6499 device_printf(pdevinfo->dev, "\n"); 6500 device_printf(pdevinfo->dev, "Record:\n"); 6501 } 6502 device_printf(pdevinfo->dev, "\n"); 6503 hdac_dump_dst_nid(pdevinfo, i, 0); 6504 } 6505} 6506 6507static void 6508hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6509{ 6510 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6511 struct hdac_widget *w; 6512 int i; 6513 int printed = 0; 6514 6515 if (pdevinfo->index != 0) 6516 return; 6517 6518 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6519 w = hdac_widget_get(devinfo, i); 6520 if (w == NULL || w->enable == 0) 6521 continue; 6522 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6523 continue; 6524 if (printed == 0) { 6525 printed = 1; 6526 device_printf(pdevinfo->dev, "\n"); 6527 device_printf(pdevinfo->dev, "Input Mix:\n"); 6528 } 6529 device_printf(pdevinfo->dev, "\n"); 6530 hdac_dump_dst_nid(pdevinfo, i, 0); 6531 } 6532} 6533 6534static void 6535hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6536{ 6537 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6538 nid_t *nids; 6539 int i; 6540 6541 if (pdevinfo->play >= 0) { 6542 i = pdevinfo->play; 6543 device_printf(pdevinfo->dev, "\n"); 6544 device_printf(pdevinfo->dev, "Playback:\n"); 6545 device_printf(pdevinfo->dev, "\n"); 6546 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6547 sc->chans[i].supp_pcm_size_rate); 6548 device_printf(pdevinfo->dev, " DAC:"); 6549 for (nids = sc->chans[i].io; *nids != -1; nids++) 6550 printf(" %d", *nids); 6551 printf("\n"); 6552 } 6553 if (pdevinfo->rec >= 0) { 6554 i = pdevinfo->rec; 6555 device_printf(pdevinfo->dev, "\n"); 6556 device_printf(pdevinfo->dev, "Record:\n"); 6557 device_printf(pdevinfo->dev, "\n"); 6558 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6559 sc->chans[i].supp_pcm_size_rate); 6560 device_printf(pdevinfo->dev, " ADC:"); 6561 for (nids = sc->chans[i].io; *nids != -1; nids++) 6562 printf(" %d", *nids); 6563 printf("\n"); 6564 } 6565} 6566 6567static void 6568hdac_release_resources(struct hdac_softc *sc) 6569{ 6570 int i, j; 6571 6572 if (sc == NULL) 6573 return; 6574 6575 hdac_lock(sc); 6576 sc->polling = 0; 6577 sc->poll_ival = 0; 6578 callout_stop(&sc->poll_hda); 6579 callout_stop(&sc->poll_hdac); 6580 callout_stop(&sc->poll_jack); 6581 hdac_reset(sc, 0); 6582 hdac_unlock(sc); 6583 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6584 callout_drain(&sc->poll_hda); 6585 callout_drain(&sc->poll_hdac); 6586 callout_drain(&sc->poll_jack); 6587 6588 hdac_irq_free(sc); 6589 6590 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6591 if (sc->codecs[i] == NULL) 6592 continue; 6593 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6594 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6595 if (sc->codecs[i]->fgs[j].node_type == 6596 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6597 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6598 M_HDAC); 6599 free(sc->codecs[i]->fgs[j].function.audio.as, 6600 M_HDAC); 6601 free(sc->codecs[i]->fgs[j].function.audio.devs, 6602 M_HDAC); 6603 } 6604 } 6605 free(sc->codecs[i]->fgs, M_HDAC); 6606 free(sc->codecs[i], M_HDAC); 6607 sc->codecs[i] = NULL; 6608 } 6609 6610 hdac_dma_free(sc, &sc->pos_dma); 6611 hdac_dma_free(sc, &sc->rirb_dma); 6612 hdac_dma_free(sc, &sc->corb_dma); 6613 for (i = 0; i < sc->num_chans; i++) { 6614 if (sc->chans[i].blkcnt > 0) 6615 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6616 } 6617 free(sc->chans, M_HDAC); 6618 if (sc->chan_dmat != NULL) { 6619 bus_dma_tag_destroy(sc->chan_dmat); 6620 sc->chan_dmat = NULL; 6621 } 6622 hdac_mem_free(sc); 6623 snd_mtxfree(sc->lock); 6624} 6625 6626/* This function surely going to make its way into upper level someday. */ 6627static void 6628hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6629{ 6630 const char *res = NULL; 6631 int i = 0, j, k, len, inv; 6632 6633 if (on != NULL) 6634 *on = 0; 6635 if (off != NULL) 6636 *off = 0; 6637 if (sc == NULL) 6638 return; 6639 if (resource_string_value(device_get_name(sc->dev), 6640 device_get_unit(sc->dev), "config", &res) != 0) 6641 return; 6642 if (!(res != NULL && strlen(res) > 0)) 6643 return; 6644 HDA_BOOTVERBOSE( 6645 device_printf(sc->dev, "HDA Config:"); 6646 ); 6647 for (;;) { 6648 while (res[i] != '\0' && 6649 (res[i] == ',' || isspace(res[i]) != 0)) 6650 i++; 6651 if (res[i] == '\0') { 6652 HDA_BOOTVERBOSE( 6653 printf("\n"); 6654 ); 6655 return; 6656 } 6657 j = i; 6658 while (res[j] != '\0' && 6659 !(res[j] == ',' || isspace(res[j]) != 0)) 6660 j++; 6661 len = j - i; 6662 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6663 inv = 2; 6664 else 6665 inv = 0; 6666 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6667 if (strncmp(res + i + inv, 6668 hdac_quirks_tab[k].key, len - inv) != 0) 6669 continue; 6670 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6671 break; 6672 HDA_BOOTVERBOSE( 6673 printf(" %s%s", (inv != 0) ? "no" : "", 6674 hdac_quirks_tab[k].key); 6675 ); 6676 if (inv == 0 && on != NULL) 6677 *on |= hdac_quirks_tab[k].value; 6678 else if (inv != 0 && off != NULL) 6679 *off |= hdac_quirks_tab[k].value; 6680 break; 6681 } 6682 i = j; 6683 } 6684} 6685 6686#ifdef SND_DYNSYSCTL 6687static int 6688sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6689{ 6690 struct hdac_softc *sc; 6691 device_t dev; 6692 uint32_t ctl; 6693 int err, val; 6694 6695 dev = oidp->oid_arg1; 6696 sc = device_get_softc(dev); 6697 if (sc == NULL) 6698 return (EINVAL); 6699 hdac_lock(sc); 6700 val = sc->polling; 6701 hdac_unlock(sc); 6702 err = sysctl_handle_int(oidp, &val, 0, req); 6703 6704 if (err != 0 || req->newptr == NULL) 6705 return (err); 6706 if (val < 0 || val > 1) 6707 return (EINVAL); 6708 6709 hdac_lock(sc); 6710 if (val != sc->polling) { 6711 if (val == 0) { 6712 callout_stop(&sc->poll_hda); 6713 callout_stop(&sc->poll_hdac); 6714 hdac_unlock(sc); 6715 callout_drain(&sc->poll_hda); 6716 callout_drain(&sc->poll_hdac); 6717 hdac_lock(sc); 6718 sc->polling = 0; 6719 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6720 ctl |= HDAC_INTCTL_GIE; 6721 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6722 } else { 6723 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6724 ctl &= ~HDAC_INTCTL_GIE; 6725 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6726 hdac_unlock(sc); 6727 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6728 hdac_lock(sc); 6729 sc->polling = 1; 6730 hdac_poll_reinit(sc); 6731 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6732 } 6733 } 6734 hdac_unlock(sc); 6735 6736 return (err); 6737} 6738 6739static int 6740sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6741{ 6742 struct hdac_softc *sc; 6743 device_t dev; 6744 int err, val; 6745 6746 dev = oidp->oid_arg1; 6747 sc = device_get_softc(dev); 6748 if (sc == NULL) 6749 return (EINVAL); 6750 hdac_lock(sc); 6751 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6752 hdac_unlock(sc); 6753 err = sysctl_handle_int(oidp, &val, 0, req); 6754 6755 if (err != 0 || req->newptr == NULL) 6756 return (err); 6757 6758 if (val < 1) 6759 val = 1; 6760 if (val > 5000) 6761 val = 5000; 6762 val = ((uint64_t)val * hz) / 1000; 6763 if (val < 1) 6764 val = 1; 6765 if (val > (hz * 5)) 6766 val = hz * 5; 6767 6768 hdac_lock(sc); 6769 sc->poll_ival = val; 6770 hdac_unlock(sc); 6771 6772 return (err); 6773} 6774 6775static int 6776sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6777{ 6778 struct hdac_softc *sc; 6779 struct hdac_codec *codec; 6780 struct hdac_devinfo *devinfo; 6781 struct hdac_widget *w; 6782 device_t dev; 6783 uint32_t res, pincap, delay; 6784 int codec_index, fg_index; 6785 int i, err, val; 6786 nid_t cad; 6787 6788 dev = oidp->oid_arg1; 6789 sc = device_get_softc(dev); 6790 if (sc == NULL) 6791 return (EINVAL); 6792 val = 0; 6793 err = sysctl_handle_int(oidp, &val, 0, req); 6794 if (err != 0 || req->newptr == NULL || val == 0) 6795 return (err); 6796 6797 /* XXX: Temporary. For debugging. */ 6798 if (val == 100) { 6799 hdac_suspend(dev); 6800 return (0); 6801 } else if (val == 101) { 6802 hdac_resume(dev); 6803 return (0); 6804 } 6805 6806 hdac_lock(sc); 6807 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 6808 codec = sc->codecs[codec_index]; 6809 if (codec == NULL) 6810 continue; 6811 cad = codec->cad; 6812 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 6813 devinfo = &codec->fgs[fg_index]; 6814 if (devinfo->node_type != 6815 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 6816 continue; 6817 6818 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 6819 codec_index, devinfo->nid); 6820 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6821 w = hdac_widget_get(devinfo, i); 6822 if (w == NULL || w->type != 6823 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6824 continue; 6825 hdac_dump_pin_config(w, w->wclass.pin.config); 6826 pincap = w->wclass.pin.cap; 6827 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 6828 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 6829 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 6830 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 6831 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 6832 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 6833 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6834 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 6835 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6836 delay = 0; 6837 hdac_command(sc, 6838 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6839 do { 6840 res = hdac_command(sc, 6841 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6842 if (res != 0x7fffffff && res != 0xffffffff) 6843 break; 6844 DELAY(10); 6845 } while (++delay < 10000); 6846 } else { 6847 delay = 0; 6848 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6849 w->nid), cad); 6850 } 6851 printf(" Sense: 0x%08x", res); 6852 if (delay > 0) 6853 printf(" delay %dus", delay * 10); 6854 } 6855 printf("\n"); 6856 } 6857 device_printf(dev, 6858 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6859 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6860 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6861 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6862 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6863 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6864 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6865 device_printf(dev, " GPI:"); 6866 res = hdac_command(sc, 6867 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6868 printf(" data=0x%08x", res); 6869 res = hdac_command(sc, 6870 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6871 cad); 6872 printf(" wake=0x%08x", res); 6873 res = hdac_command(sc, 6874 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6875 cad); 6876 printf(" unsol=0x%08x", res); 6877 res = hdac_command(sc, 6878 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6879 printf(" sticky=0x%08x\n", res); 6880 } 6881 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6882 device_printf(dev, " GPO:"); 6883 res = hdac_command(sc, 6884 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6885 printf(" data=0x%08x\n", res); 6886 } 6887 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6888 device_printf(dev, "GPIO:"); 6889 res = hdac_command(sc, 6890 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6891 printf(" data=0x%08x", res); 6892 res = hdac_command(sc, 6893 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6894 printf(" enable=0x%08x", res); 6895 res = hdac_command(sc, 6896 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6897 printf(" direction=0x%08x\n", res); 6898 res = hdac_command(sc, 6899 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6900 device_printf(dev, " wake=0x%08x", res); 6901 res = hdac_command(sc, 6902 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6903 cad); 6904 printf(" unsol=0x%08x", res); 6905 res = hdac_command(sc, 6906 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6907 printf(" sticky=0x%08x\n", res); 6908 } 6909 } 6910 } 6911 hdac_unlock(sc); 6912 return (0); 6913} 6914#endif 6915 6916static void 6917hdac_attach2(void *arg) 6918{ 6919 struct hdac_codec *codec; 6920 struct hdac_softc *sc; 6921 struct hdac_audio_ctl *ctl; 6922 uint32_t quirks_on, quirks_off; 6923 int codec_index, fg_index; 6924 int i, pdev, rdev, dmaalloc = 0; 6925 struct hdac_devinfo *devinfo; 6926 6927 sc = (struct hdac_softc *)arg; 6928 6929 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6930 6931 HDA_BOOTVERBOSE( 6932 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 6933 quirks_on, quirks_off); 6934 ); 6935 6936 hdac_lock(sc); 6937 6938 /* Remove ourselves from the config hooks */ 6939 if (sc->intrhook.ich_func != NULL) { 6940 config_intrhook_disestablish(&sc->intrhook); 6941 sc->intrhook.ich_func = NULL; 6942 } 6943 6944 /* Start the corb and rirb engines */ 6945 HDA_BOOTVERBOSE( 6946 device_printf(sc->dev, "Starting CORB Engine...\n"); 6947 ); 6948 hdac_corb_start(sc); 6949 HDA_BOOTVERBOSE( 6950 device_printf(sc->dev, "Starting RIRB Engine...\n"); 6951 ); 6952 hdac_rirb_start(sc); 6953 6954 HDA_BOOTVERBOSE( 6955 device_printf(sc->dev, 6956 "Enabling controller interrupt...\n"); 6957 ); 6958 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6959 HDAC_GCTL_UNSOL); 6960 if (sc->polling == 0) { 6961 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6962 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6963 } else { 6964 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6965 } 6966 DELAY(1000); 6967 6968 HDA_BOOTVERBOSE( 6969 device_printf(sc->dev, 6970 "Scanning HDA codecs ...\n"); 6971 ); 6972 hdac_scan_codecs(sc); 6973 6974 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 6975 codec = sc->codecs[codec_index]; 6976 if (codec == NULL) 6977 continue; 6978 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 6979 devinfo = &codec->fgs[fg_index]; 6980 HDA_BOOTVERBOSE( 6981 device_printf(sc->dev, "\n"); 6982 ); 6983 if (devinfo->node_type != 6984 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6985 HDA_BOOTVERBOSE( 6986 device_printf(sc->dev, 6987 "Power down unsupported non-audio FG" 6988 " cad=%d nid=%d to the D3 state...\n", 6989 codec->cad, devinfo->nid); 6990 ); 6991 hdac_command(sc, 6992 HDA_CMD_SET_POWER_STATE(codec->cad, 6993 devinfo->nid, HDA_CMD_POWER_STATE_D3), 6994 codec->cad); 6995 continue; 6996 } 6997 6998 HDA_BOOTVERBOSE( 6999 device_printf(sc->dev, 7000 "Power up audio FG cad=%d nid=%d...\n", 7001 devinfo->codec->cad, devinfo->nid); 7002 ); 7003 hdac_powerup(devinfo); 7004 HDA_BOOTVERBOSE( 7005 device_printf(sc->dev, "Parsing audio FG...\n"); 7006 ); 7007 hdac_audio_parse(devinfo); 7008 HDA_BOOTVERBOSE( 7009 device_printf(sc->dev, "Parsing Ctls...\n"); 7010 ); 7011 hdac_audio_ctl_parse(devinfo); 7012 HDA_BOOTVERBOSE( 7013 device_printf(sc->dev, "Parsing vendor patch...\n"); 7014 ); 7015 hdac_vendor_patch_parse(devinfo); 7016 devinfo->function.audio.quirks |= quirks_on; 7017 devinfo->function.audio.quirks &= ~quirks_off; 7018 7019 HDA_BOOTVERBOSE( 7020 device_printf(sc->dev, "Disabling nonaudio...\n"); 7021 ); 7022 hdac_audio_disable_nonaudio(devinfo); 7023 HDA_BOOTVERBOSE( 7024 device_printf(sc->dev, "Disabling useless...\n"); 7025 ); 7026 hdac_audio_disable_useless(devinfo); 7027 HDA_BOOTVERBOSE( 7028 device_printf(sc->dev, "Patched pins configuration:\n"); 7029 hdac_dump_pin_configs(devinfo); 7030 device_printf(sc->dev, "Parsing pin associations...\n"); 7031 ); 7032 hdac_audio_as_parse(devinfo); 7033 HDA_BOOTVERBOSE( 7034 device_printf(sc->dev, "Building AFG tree...\n"); 7035 ); 7036 hdac_audio_build_tree(devinfo); 7037 HDA_BOOTVERBOSE( 7038 device_printf(sc->dev, "Disabling unassociated " 7039 "widgets...\n"); 7040 ); 7041 hdac_audio_disable_unas(devinfo); 7042 HDA_BOOTVERBOSE( 7043 device_printf(sc->dev, "Disabling nonselected " 7044 "inputs...\n"); 7045 ); 7046 hdac_audio_disable_notselected(devinfo); 7047 HDA_BOOTVERBOSE( 7048 device_printf(sc->dev, "Disabling useless...\n"); 7049 ); 7050 hdac_audio_disable_useless(devinfo); 7051 HDA_BOOTVERBOSE( 7052 device_printf(sc->dev, "Disabling " 7053 "crossassociatement connections...\n"); 7054 ); 7055 hdac_audio_disable_crossas(devinfo); 7056 HDA_BOOTVERBOSE( 7057 device_printf(sc->dev, "Disabling useless...\n"); 7058 ); 7059 hdac_audio_disable_useless(devinfo); 7060 HDA_BOOTVERBOSE( 7061 device_printf(sc->dev, "Binding associations to channels...\n"); 7062 ); 7063 hdac_audio_bind_as(devinfo); 7064 HDA_BOOTVERBOSE( 7065 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7066 ); 7067 hdac_audio_assign_names(devinfo); 7068 HDA_BOOTVERBOSE( 7069 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7070 ); 7071 hdac_audio_assign_mixers(devinfo); 7072 HDA_BOOTVERBOSE( 7073 device_printf(sc->dev, "Preparing pin controls...\n"); 7074 ); 7075 hdac_audio_prepare_pin_ctrl(devinfo); 7076 HDA_BOOTVERBOSE( 7077 device_printf(sc->dev, "AFG commit...\n"); 7078 ); 7079 hdac_audio_commit(devinfo); 7080 HDA_BOOTVERBOSE( 7081 device_printf(sc->dev, "Ctls commit...\n"); 7082 ); 7083 hdac_audio_ctl_commit(devinfo); 7084 HDA_BOOTVERBOSE( 7085 device_printf(sc->dev, "HP switch init...\n"); 7086 ); 7087 hdac_hp_switch_init(devinfo); 7088 7089 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7090 dmaalloc == 0) { 7091 if (hdac_dma_alloc(sc, &sc->pos_dma, 7092 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7093 HDA_BOOTVERBOSE( 7094 device_printf(sc->dev, "Failed to " 7095 "allocate DMA pos buffer " 7096 "(non-fatal)\n"); 7097 ); 7098 } else 7099 dmaalloc = 1; 7100 } 7101 7102 i = devinfo->function.audio.playcnt; 7103 if (devinfo->function.audio.reccnt > i) 7104 i = devinfo->function.audio.reccnt; 7105 devinfo->function.audio.devs = 7106 (struct hdac_pcm_devinfo *)malloc( 7107 sizeof(struct hdac_pcm_devinfo) * i, 7108 M_HDAC, M_ZERO | M_NOWAIT); 7109 if (devinfo->function.audio.devs == NULL) { 7110 device_printf(sc->dev, 7111 "Unable to allocate memory for devices\n"); 7112 continue; 7113 } 7114 devinfo->function.audio.num_devs = i; 7115 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7116 devinfo->function.audio.devs[i].index = i; 7117 devinfo->function.audio.devs[i].devinfo = devinfo; 7118 devinfo->function.audio.devs[i].play = -1; 7119 devinfo->function.audio.devs[i].rec = -1; 7120 } 7121 pdev = 0; 7122 rdev = 0; 7123 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 7124 if (devinfo->function.audio.as[i].enable == 0) 7125 continue; 7126 if (devinfo->function.audio.as[i].dir == 7127 HDA_CTL_IN) { 7128 devinfo->function.audio.devs[rdev].rec 7129 = devinfo->function.audio.as[i].chan; 7130 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7131 &devinfo->function.audio.devs[rdev]; 7132 rdev++; 7133 } else { 7134 devinfo->function.audio.devs[pdev].play 7135 = devinfo->function.audio.as[i].chan; 7136 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7137 &devinfo->function.audio.devs[pdev]; 7138 pdev++; 7139 } 7140 } 7141 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7142 struct hdac_pcm_devinfo *pdevinfo = 7143 &devinfo->function.audio.devs[i]; 7144 pdevinfo->dev = 7145 device_add_child(sc->dev, "pcm", -1); 7146 device_set_ivars(pdevinfo->dev, 7147 (void *)pdevinfo); 7148 } 7149 7150 HDA_BOOTVERBOSE( 7151 if (devinfo->function.audio.quirks != 0) { 7152 device_printf(sc->dev, "\n"); 7153 device_printf(sc->dev, "HDA config/quirks:"); 7154 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7155 if ((devinfo->function.audio.quirks & 7156 hdac_quirks_tab[i].value) == 7157 hdac_quirks_tab[i].value) 7158 printf(" %s", hdac_quirks_tab[i].key); 7159 } 7160 printf("\n"); 7161 } 7162 7163 device_printf(sc->dev, "\n"); 7164 device_printf(sc->dev, "+-------------------+\n"); 7165 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7166 device_printf(sc->dev, "+-------------------+\n"); 7167 hdac_dump_nodes(devinfo); 7168 7169 device_printf(sc->dev, "\n"); 7170 device_printf(sc->dev, "+------------------------+\n"); 7171 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7172 device_printf(sc->dev, "+------------------------+\n"); 7173 device_printf(sc->dev, "\n"); 7174 i = 0; 7175 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7176 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7177 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7178 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7179 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7180 ctl->index); 7181 if (ctl->childwidget != NULL) 7182 printf(" cnid %3d", ctl->childwidget->nid); 7183 else 7184 printf(" "); 7185 printf(" ossmask=0x%08x\n", 7186 ctl->ossmask); 7187 device_printf(sc->dev, 7188 " mute: %d step: %3d size: %3d off: %3d%s\n", 7189 ctl->mute, ctl->step, ctl->size, ctl->offset, 7190 (ctl->enable == 0) ? " [DISABLED]" : 7191 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7192 } 7193 ); 7194 } 7195 } 7196 hdac_unlock(sc); 7197 7198 HDA_BOOTVERBOSE( 7199 device_printf(sc->dev, "\n"); 7200 ); 7201 7202 bus_generic_attach(sc->dev); 7203 7204#ifdef SND_DYNSYSCTL 7205 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7206 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7207 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7208 sysctl_hdac_polling, "I", "Enable polling mode"); 7209 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7210 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7211 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7212 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7213 "Controller/Jack Sense polling interval (1-1000 ms)"); 7214 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7215 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7216 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7217 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7218#endif 7219} 7220 7221/**************************************************************************** 7222 * int hdac_suspend(device_t) 7223 * 7224 * Suspend and power down HDA bus and codecs. 7225 ****************************************************************************/ 7226static int 7227hdac_suspend(device_t dev) 7228{ 7229 struct hdac_softc *sc; 7230 struct hdac_codec *codec; 7231 struct hdac_devinfo *devinfo; 7232 int codec_index, fg_index, i; 7233 7234 HDA_BOOTVERBOSE( 7235 device_printf(dev, "Suspend...\n"); 7236 ); 7237 7238 sc = device_get_softc(dev); 7239 hdac_lock(sc); 7240 7241 HDA_BOOTVERBOSE( 7242 device_printf(dev, "Stop streams...\n"); 7243 ); 7244 for (i = 0; i < sc->num_chans; i++) { 7245 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7246 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7247 hdac_channel_stop(sc, &sc->chans[i]); 7248 } 7249 } 7250 7251 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7252 codec = sc->codecs[codec_index]; 7253 if (codec == NULL) 7254 continue; 7255 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7256 devinfo = &codec->fgs[fg_index]; 7257 HDA_BOOTVERBOSE( 7258 device_printf(dev, 7259 "Power down FG" 7260 " cad=%d nid=%d to the D3 state...\n", 7261 codec->cad, devinfo->nid); 7262 ); 7263 hdac_command(sc, 7264 HDA_CMD_SET_POWER_STATE(codec->cad, 7265 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7266 codec->cad); 7267 } 7268 } 7269 7270 HDA_BOOTVERBOSE( 7271 device_printf(dev, "Reset controller...\n"); 7272 ); 7273 callout_stop(&sc->poll_hda); 7274 callout_stop(&sc->poll_hdac); 7275 callout_stop(&sc->poll_jack); 7276 hdac_reset(sc, 0); 7277 hdac_unlock(sc); 7278 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7279 callout_drain(&sc->poll_hda); 7280 callout_drain(&sc->poll_hdac); 7281 callout_drain(&sc->poll_jack); 7282 7283 HDA_BOOTVERBOSE( 7284 device_printf(dev, "Suspend done\n"); 7285 ); 7286 7287 return (0); 7288} 7289 7290/**************************************************************************** 7291 * int hdac_resume(device_t) 7292 * 7293 * Powerup and restore HDA bus and codecs state. 7294 ****************************************************************************/ 7295static int 7296hdac_resume(device_t dev) 7297{ 7298 struct hdac_softc *sc; 7299 struct hdac_codec *codec; 7300 struct hdac_devinfo *devinfo; 7301 int codec_index, fg_index, i; 7302 7303 HDA_BOOTVERBOSE( 7304 device_printf(dev, "Resume...\n"); 7305 ); 7306 7307 sc = device_get_softc(dev); 7308 hdac_lock(sc); 7309 7310 /* Quiesce everything */ 7311 HDA_BOOTVERBOSE( 7312 device_printf(dev, "Reset controller...\n"); 7313 ); 7314 hdac_reset(sc, 1); 7315 7316 /* Initialize the CORB and RIRB */ 7317 hdac_corb_init(sc); 7318 hdac_rirb_init(sc); 7319 7320 /* Start the corb and rirb engines */ 7321 HDA_BOOTVERBOSE( 7322 device_printf(dev, "Starting CORB Engine...\n"); 7323 ); 7324 hdac_corb_start(sc); 7325 HDA_BOOTVERBOSE( 7326 device_printf(dev, "Starting RIRB Engine...\n"); 7327 ); 7328 hdac_rirb_start(sc); 7329 7330 HDA_BOOTVERBOSE( 7331 device_printf(dev, 7332 "Enabling controller interrupt...\n"); 7333 ); 7334 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7335 HDAC_GCTL_UNSOL); 7336 if (sc->polling == 0) { 7337 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7338 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7339 } else { 7340 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7341 } 7342 DELAY(1000); 7343 7344 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7345 codec = sc->codecs[codec_index]; 7346 if (codec == NULL) 7347 continue; 7348 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7349 devinfo = &codec->fgs[fg_index]; 7350 if (devinfo->node_type != 7351 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7352 HDA_BOOTVERBOSE( 7353 device_printf(dev, 7354 "Power down unsupported non-audio FG" 7355 " cad=%d nid=%d to the D3 state...\n", 7356 codec->cad, devinfo->nid); 7357 ); 7358 hdac_command(sc, 7359 HDA_CMD_SET_POWER_STATE(codec->cad, 7360 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7361 codec->cad); 7362 continue; 7363 } 7364 7365 HDA_BOOTVERBOSE( 7366 device_printf(dev, 7367 "Power up audio FG cad=%d nid=%d...\n", 7368 devinfo->codec->cad, devinfo->nid); 7369 ); 7370 hdac_powerup(devinfo); 7371 HDA_BOOTVERBOSE( 7372 device_printf(dev, "AFG commit...\n"); 7373 ); 7374 hdac_audio_commit(devinfo); 7375 HDA_BOOTVERBOSE( 7376 device_printf(dev, "Ctls commit...\n"); 7377 ); 7378 hdac_audio_ctl_commit(devinfo); 7379 HDA_BOOTVERBOSE( 7380 device_printf(dev, "HP switch init...\n"); 7381 ); 7382 hdac_hp_switch_init(devinfo); 7383 7384 hdac_unlock(sc); 7385 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7386 struct hdac_pcm_devinfo *pdevinfo = 7387 &devinfo->function.audio.devs[i]; 7388 HDA_BOOTVERBOSE( 7389 device_printf(pdevinfo->dev, 7390 "OSS mixer reinitialization...\n"); 7391 ); 7392 if (mixer_reinit(pdevinfo->dev) == -1) 7393 device_printf(pdevinfo->dev, 7394 "unable to reinitialize the mixer\n"); 7395 } 7396 hdac_lock(sc); 7397 } 7398 } 7399 7400 HDA_BOOTVERBOSE( 7401 device_printf(dev, "Start streams...\n"); 7402 ); 7403 for (i = 0; i < sc->num_chans; i++) { 7404 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7405 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7406 hdac_channel_start(sc, &sc->chans[i]); 7407 } 7408 } 7409 7410 hdac_unlock(sc); 7411 7412 HDA_BOOTVERBOSE( 7413 device_printf(dev, "Resume done\n"); 7414 ); 7415 7416 return (0); 7417} 7418/**************************************************************************** 7419 * int hdac_detach(device_t) 7420 * 7421 * Detach and free up resources utilized by the hdac device. 7422 ****************************************************************************/ 7423static int 7424hdac_detach(device_t dev) 7425{ 7426 struct hdac_softc *sc; 7427 device_t *devlist = NULL; 7428 int i, devcount; 7429 7430 sc = device_get_softc(dev); 7431 7432 device_get_children(dev, &devlist, &devcount); 7433 for (i = 0; devlist != NULL && i < devcount; i++) 7434 device_delete_child(dev, devlist[i]); 7435 if (devlist != NULL) 7436 free(devlist, M_TEMP); 7437 7438 hdac_release_resources(sc); 7439 7440 return (0); 7441} 7442 7443static device_method_t hdac_methods[] = { 7444 /* device interface */ 7445 DEVMETHOD(device_probe, hdac_probe), 7446 DEVMETHOD(device_attach, hdac_attach), 7447 DEVMETHOD(device_detach, hdac_detach), 7448 DEVMETHOD(device_suspend, hdac_suspend), 7449 DEVMETHOD(device_resume, hdac_resume), 7450 { 0, 0 } 7451}; 7452 7453static driver_t hdac_driver = { 7454 "hdac", 7455 hdac_methods, 7456 sizeof(struct hdac_softc), 7457}; 7458 7459static devclass_t hdac_devclass; 7460 7461DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7462MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7463MODULE_VERSION(snd_hda, 1); 7464 7465static int 7466hdac_pcm_probe(device_t dev) 7467{ 7468 struct hdac_pcm_devinfo *pdevinfo = 7469 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7470 char buf[128]; 7471 7472 snprintf(buf, sizeof(buf), "HDA codec #%d %s PCM #%d", 7473 pdevinfo->devinfo->codec->cad, 7474 hdac_codec_name(pdevinfo->devinfo->codec), 7475 pdevinfo->index); 7476 device_set_desc_copy(dev, buf); 7477 return (0); 7478} 7479 7480static int 7481hdac_pcm_attach(device_t dev) 7482{ 7483 struct hdac_pcm_devinfo *pdevinfo = 7484 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7485 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7486 char status[SND_STATUSLEN]; 7487 int i; 7488 7489 pdevinfo->chan_size = pcm_getbuffersize(dev, 7490 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7491 7492 HDA_BOOTVERBOSE( 7493 device_printf(dev, "+--------------------------------------+\n"); 7494 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7495 device_printf(dev, "+--------------------------------------+\n"); 7496 hdac_dump_pcmchannels(pdevinfo); 7497 device_printf(dev, "\n"); 7498 device_printf(dev, "+--------------------------------+\n"); 7499 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7500 device_printf(dev, "+--------------------------------+\n"); 7501 hdac_dump_dac(pdevinfo); 7502 hdac_dump_adc(pdevinfo); 7503 hdac_dump_mix(pdevinfo); 7504 device_printf(dev, "\n"); 7505 device_printf(dev, "+-------------------------+\n"); 7506 device_printf(dev, "| DUMPING Volume Controls |\n"); 7507 device_printf(dev, "+-------------------------+\n"); 7508 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7509 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7510 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7511 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7512 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7513 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7514 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7515 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7516 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7517 hdac_dump_ctls(pdevinfo, NULL, 0); 7518 device_printf(dev, "\n"); 7519 ); 7520 7521 if (resource_int_value(device_get_name(dev), 7522 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7523 i &= HDA_BLK_ALIGN; 7524 if (i < HDA_BLK_MIN) 7525 i = HDA_BLK_MIN; 7526 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7527 i = 0; 7528 while (pdevinfo->chan_blkcnt >> i) 7529 i++; 7530 pdevinfo->chan_blkcnt = 1 << (i - 1); 7531 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7532 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7533 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7534 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7535 } else 7536 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7537 7538 /* 7539 * We don't register interrupt handler with snd_setup_intr 7540 * in pcm device. Mark pcm device as MPSAFE manually. 7541 */ 7542 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7543 7544 HDA_BOOTVERBOSE( 7545 device_printf(dev, "OSS mixer initialization...\n"); 7546 ); 7547 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7548 device_printf(dev, "Can't register mixer\n"); 7549 7550 HDA_BOOTVERBOSE( 7551 device_printf(dev, "Registering PCM channels...\n"); 7552 ); 7553 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7554 (pdevinfo->rec >= 0)?1:0) != 0) 7555 device_printf(dev, "Can't register PCM\n"); 7556 7557 pdevinfo->registered++; 7558 7559 if (pdevinfo->play >= 0) 7560 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7561 if (pdevinfo->rec >= 0) 7562 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7563 7564 snprintf(status, SND_STATUSLEN, "at %s cad %d %s [%s]", 7565 device_get_nameunit(sc->dev), pdevinfo->devinfo->codec->cad, 7566 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 7567 pcm_setstatus(dev, status); 7568 7569 return (0); 7570} 7571 7572static int 7573hdac_pcm_detach(device_t dev) 7574{ 7575 struct hdac_pcm_devinfo *pdevinfo = 7576 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7577 int err; 7578 7579 if (pdevinfo->registered > 0) { 7580 err = pcm_unregister(dev); 7581 if (err != 0) 7582 return (err); 7583 } 7584 7585 return (0); 7586} 7587 7588static device_method_t hdac_pcm_methods[] = { 7589 /* device interface */ 7590 DEVMETHOD(device_probe, hdac_pcm_probe), 7591 DEVMETHOD(device_attach, hdac_pcm_attach), 7592 DEVMETHOD(device_detach, hdac_pcm_detach), 7593 { 0, 0 } 7594}; 7595 7596static driver_t hdac_pcm_driver = { 7597 "pcm", 7598 hdac_pcm_methods, 7599 PCM_SOFTC_SIZE, 7600}; 7601 7602DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7603 7604