hdac.c revision 182999
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20080913_0111" 87#define HDA_WIDGET_PARSER_REV 2 88 89SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 182999 2008-09-13 16:56:03Z mav $"); 90 91#define HDA_BOOTVERBOSE(stmt) do { \ 92 if (bootverbose != 0 || snd_verbose > 3) { \ 93 stmt \ 94 } \ 95} while(0) 96 97#if 1 98#undef HDAC_INTR_EXTRA 99#define HDAC_INTR_EXTRA 1 100#endif 101 102#define hdac_lock(sc) snd_mtxlock((sc)->lock) 103#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 104#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 105#define hdac_lockowned(sc) mtx_owned((sc)->lock) 106 107#undef HDAC_MSI_ENABLED 108#if __FreeBSD_version >= 700026 || \ 109 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 110#define HDAC_MSI_ENABLED 1 111#endif 112 113#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 114#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 115 (fl) == 0xffffffff || \ 116 (((fl) & 0xffff0000) == 0xffff0000 && \ 117 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 118 (((fl) & 0x0000ffff) == 0x0000ffff && \ 119 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 120#define HDA_MATCH_ALL 0xffffffff 121#define HDAC_INVALID 0xffffffff 122 123/* Default controller / jack sense poll: 250ms */ 124#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 125 126/* 127 * Make room for possible 4096 playback/record channels, in 100 years to come. 128 */ 129#define HDAC_TRIGGER_NONE 0x00000000 130#define HDAC_TRIGGER_PLAY 0x00000fff 131#define HDAC_TRIGGER_REC 0x00fff000 132#define HDAC_TRIGGER_UNSOL 0x80000000 133 134#define HDA_MODEL_CONSTRUCT(vendor, model) \ 135 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 136 137/* Controller models */ 138 139/* Intel */ 140#define INTEL_VENDORID 0x8086 141#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 142#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 143#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 144#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 145#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 146#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 147 148/* Nvidia */ 149#define NVIDIA_VENDORID 0x10de 150#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 151#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 152#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 153#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 154#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 155#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 156#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 157#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 158#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 159 160/* ATI */ 161#define ATI_VENDORID 0x1002 162#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 163#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 164#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 165 166/* VIA */ 167#define VIA_VENDORID 0x1106 168#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 169#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 170 171/* SiS */ 172#define SIS_VENDORID 0x1039 173#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 174#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 175 176/* OEM/subvendors */ 177 178/* Intel */ 179#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 180 181/* HP/Compaq */ 182#define HP_VENDORID 0x103c 183#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 184#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 185#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 186#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 187#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 188#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 189#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 190#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 191#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 192#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 193/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 194#define HP_NX6325_SUBVENDORX 0x103c30b0 195 196/* Dell */ 197#define DELL_VENDORID 0x1028 198#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 199#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 200#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 201#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 202#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 203#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 204#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 205 206/* Clevo */ 207#define CLEVO_VENDORID 0x1558 208#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 209#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 210 211/* Acer */ 212#define ACER_VENDORID 0x1025 213#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 214#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 215#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 216#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 217#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 218#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 219#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 220 221/* Asus */ 222#define ASUS_VENDORID 0x1043 223#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 224#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 225#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 226#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 227#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 228#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 229#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 230#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 231#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 232#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 233#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 234#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 235#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 236#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 237#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 238#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 239 240/* IBM / Lenovo */ 241#define IBM_VENDORID 0x1014 242#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 243#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 244 245/* Lenovo */ 246#define LENOVO_VENDORID 0x17aa 247#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 248#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 249#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 250#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 251 252/* Samsung */ 253#define SAMSUNG_VENDORID 0x144d 254#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 255#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 256 257/* Medion ? */ 258#define MEDION_VENDORID 0x161f 259#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 260#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 261 262/* Apple Computer Inc. */ 263#define APPLE_VENDORID 0x106b 264#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 265 266/* Sony */ 267#define SONY_VENDORID 0x104d 268#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 269#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 270 271/* 272 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 273 * instead of their own, which is beyond my comprehension 274 * (see HDA_CODEC_STAC9221 below). 275 */ 276#define APPLE_INTEL_MAC 0x76808384 277 278/* LG Electronics */ 279#define LG_VENDORID 0x1854 280#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 281#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 282 283/* Fujitsu Siemens */ 284#define FS_VENDORID 0x1734 285#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 286#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 287#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 288 289/* Fujitsu Limited */ 290#define FL_VENDORID 0x10cf 291#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 292#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 293#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 294 295/* Toshiba */ 296#define TOSHIBA_VENDORID 0x1179 297#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 298#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 299#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 300 301/* Micro-Star International (MSI) */ 302#define MSI_VENDORID 0x1462 303#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 304#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 305#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 306 307/* Giga-Byte Technology */ 308#define GB_VENDORID 0x1458 309#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 310#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 311 312/* Uniwill ? */ 313#define UNIWILL_VENDORID 0x1584 314#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 315#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 316 317 318/* Misc constants.. */ 319#define HDA_AMP_VOL_DEFAULT (-1) 320#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 321#define HDA_AMP_MUTE_NONE (0) 322#define HDA_AMP_MUTE_LEFT (1 << 0) 323#define HDA_AMP_MUTE_RIGHT (1 << 1) 324#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 325 326#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 327#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 328 329#define HDA_ADC_MONITOR (1 << 0) 330 331#define HDA_CTL_OUT 1 332#define HDA_CTL_IN 2 333 334#define HDA_GPIO_MAX 8 335/* 0 - 7 = GPIO , 8 = Flush */ 336#define HDA_QUIRK_GPIO0 (1 << 0) 337#define HDA_QUIRK_GPIO1 (1 << 1) 338#define HDA_QUIRK_GPIO2 (1 << 2) 339#define HDA_QUIRK_GPIO3 (1 << 3) 340#define HDA_QUIRK_GPIO4 (1 << 4) 341#define HDA_QUIRK_GPIO5 (1 << 5) 342#define HDA_QUIRK_GPIO6 (1 << 6) 343#define HDA_QUIRK_GPIO7 (1 << 7) 344#define HDA_QUIRK_GPIOFLUSH (1 << 8) 345 346/* 9 - 25 = anything else */ 347#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 348#define HDA_QUIRK_FIXEDRATE (1 << 10) 349#define HDA_QUIRK_FORCESTEREO (1 << 11) 350#define HDA_QUIRK_EAPDINV (1 << 12) 351#define HDA_QUIRK_DMAPOS (1 << 13) 352#define HDA_QUIRK_SENSEINV (1 << 14) 353 354/* 26 - 31 = vrefs */ 355#define HDA_QUIRK_IVREF50 (1 << 26) 356#define HDA_QUIRK_IVREF80 (1 << 27) 357#define HDA_QUIRK_IVREF100 (1 << 28) 358#define HDA_QUIRK_OVREF50 (1 << 29) 359#define HDA_QUIRK_OVREF80 (1 << 30) 360#define HDA_QUIRK_OVREF100 (1 << 31) 361 362#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 363 HDA_QUIRK_IVREF100) 364#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 365 HDA_QUIRK_OVREF100) 366#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 367 368#if __FreeBSD_version < 600000 369#define taskqueue_drain(...) 370#endif 371 372static const struct { 373 char *key; 374 uint32_t value; 375} hdac_quirks_tab[] = { 376 { "gpio0", HDA_QUIRK_GPIO0 }, 377 { "gpio1", HDA_QUIRK_GPIO1 }, 378 { "gpio2", HDA_QUIRK_GPIO2 }, 379 { "gpio3", HDA_QUIRK_GPIO3 }, 380 { "gpio4", HDA_QUIRK_GPIO4 }, 381 { "gpio5", HDA_QUIRK_GPIO5 }, 382 { "gpio6", HDA_QUIRK_GPIO6 }, 383 { "gpio7", HDA_QUIRK_GPIO7 }, 384 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 385 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 386 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 387 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 388 { "eapdinv", HDA_QUIRK_EAPDINV }, 389 { "dmapos", HDA_QUIRK_DMAPOS }, 390 { "senseinv", HDA_QUIRK_SENSEINV }, 391 { "ivref50", HDA_QUIRK_IVREF50 }, 392 { "ivref80", HDA_QUIRK_IVREF80 }, 393 { "ivref100", HDA_QUIRK_IVREF100 }, 394 { "ovref50", HDA_QUIRK_OVREF50 }, 395 { "ovref80", HDA_QUIRK_OVREF80 }, 396 { "ovref100", HDA_QUIRK_OVREF100 }, 397 { "ivref", HDA_QUIRK_IVREF }, 398 { "ovref", HDA_QUIRK_OVREF }, 399 { "vref", HDA_QUIRK_VREF }, 400}; 401#define HDAC_QUIRKS_TAB_LEN \ 402 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 403 404#define HDA_BDL_MIN 2 405#define HDA_BDL_MAX 256 406#define HDA_BDL_DEFAULT HDA_BDL_MIN 407 408#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 409#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 410 411#define HDA_BUFSZ_MIN 4096 412#define HDA_BUFSZ_MAX 65536 413#define HDA_BUFSZ_DEFAULT 16384 414 415#define HDA_PARSE_MAXDEPTH 10 416 417#define HDAC_UNSOLTAG_EVENT_HP 0x00 418 419MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 420 421const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 422 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 423 "White", "Other"}; 424 425const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 426 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 427 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 428 429const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 430 431/* Default */ 432static uint32_t hdac_fmt[] = { 433 AFMT_STEREO | AFMT_S16_LE, 434 0 435}; 436 437static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 438 439static const struct { 440 uint32_t model; 441 char *desc; 442} hdac_devices[] = { 443 { HDA_INTEL_82801F, "Intel 82801F" }, 444 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 445 { HDA_INTEL_82801G, "Intel 82801G" }, 446 { HDA_INTEL_82801H, "Intel 82801H" }, 447 { HDA_INTEL_82801I, "Intel 82801I" }, 448 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 449 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 450 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 451 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 452 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 453 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 454 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 455 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 456 { HDA_ATI_SB450, "ATI SB450" }, 457 { HDA_ATI_SB600, "ATI SB600" }, 458 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 459 { HDA_SIS_966, "SiS 966" }, 460 /* Unknown */ 461 { HDA_INTEL_ALL, "Intel (Unknown)" }, 462 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 463 { HDA_ATI_ALL, "ATI (Unknown)" }, 464 { HDA_VIA_ALL, "VIA (Unknown)" }, 465 { HDA_SIS_ALL, "SiS (Unknown)" }, 466}; 467#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 468 469static const struct { 470 uint16_t vendor; 471 uint8_t reg; 472 uint8_t mask; 473 uint8_t enable; 474} hdac_pcie_snoop[] = { 475 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 476 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 477 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 478}; 479#define HDAC_PCIESNOOP_LEN \ 480 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 481 482static const struct { 483 uint32_t rate; 484 int valid; 485 uint16_t base; 486 uint16_t mul; 487 uint16_t div; 488} hda_rate_tab[] = { 489 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 490 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 491 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 492 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 493 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 494 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 495 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 496 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 497 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 498 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 499 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 500 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 501 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 502 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 503 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 504 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 505 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 506 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 507 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 508 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 509 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 510 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 511 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 512 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 513 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 514 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 515 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 516 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 517 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 518 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 519 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 520 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 521 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 522 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 523 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 524}; 525#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 526 527/* All codecs you can eat... */ 528#define HDA_CODEC_CONSTRUCT(vendor, id) \ 529 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 530 531/* Realtek */ 532#define REALTEK_VENDORID 0x10ec 533#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 534#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 535#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 536#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 537#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 538#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 539#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 540#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 541#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 542#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 543#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 544#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 545#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 546 547/* Analog Devices */ 548#define ANALOGDEVICES_VENDORID 0x11d4 549#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 550#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 551#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 552#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 553#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 554#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 555#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 556 557/* CMedia */ 558#define CMEDIA_VENDORID 0x434d 559#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 560#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 561 562/* Sigmatel */ 563#define SIGMATEL_VENDORID 0x8384 564#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 565#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 566#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 567#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 568#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 569#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 570#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 571#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 572#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 573#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 574#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 575#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 576#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 577#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 578#define HDA_CODEC_STAC9205 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 579#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 580 581/* Silicon Image */ 582#define SII_VENDORID 0x1095 583#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 584 585/* Lucent/Agere */ 586#define AGERE_VENDORID 0x11c1 587#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 588 589/* 590 * Conexant 591 * 592 * Ok, the truth is, I don't have any idea at all whether 593 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 594 * place that tell me it is "Venice" is from its Windows driver INF. 595 * 596 * Venice - CX????? 597 * Waikiki - CX20551-22 598 */ 599#define CONEXANT_VENDORID 0x14f1 600#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 601#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 602#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 603 604/* VIA */ 605#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 606#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 607#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 608#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 609#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 610#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 611#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 612#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 613#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 614#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 615#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 616#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 617#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 618 619/* ATI */ 620#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 621 622/* NVIDIA */ 623#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 624 625/* Codecs */ 626static const struct { 627 uint32_t id; 628 char *name; 629} hdac_codecs[] = { 630 { HDA_CODEC_ALC260, "Realtek ALC260" }, 631 { HDA_CODEC_ALC262, "Realtek ALC262" }, 632 { HDA_CODEC_ALC268, "Realtek ALC268" }, 633 { HDA_CODEC_ALC660, "Realtek ALC660" }, 634 { HDA_CODEC_ALC861, "Realtek ALC861" }, 635 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 636 { HDA_CODEC_ALC880, "Realtek ALC880" }, 637 { HDA_CODEC_ALC882, "Realtek ALC882" }, 638 { HDA_CODEC_ALC883, "Realtek ALC883" }, 639 { HDA_CODEC_ALC885, "Realtek ALC885" }, 640 { HDA_CODEC_ALC888, "Realtek ALC888" }, 641 { HDA_CODEC_ALC889, "Realtek ALC889" }, 642 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 643 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 644 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 645 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 646 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 647 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 648 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 649 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 650 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 651 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 652 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 653 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 654 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 655 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 656 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 657 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 658 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 659 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 660 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 661 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 662 { HDA_CODEC_STAC9205, "Sigmatel STAC9205" }, 663 { HDA_CODEC_STAC9872AK,"Sigmatel STAC9872AK" }, 664 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 665 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 666 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 667 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 668 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 669 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 670 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 671 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 672 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 673 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 674 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 675 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 676 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 677 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 678 /* Unknown codec */ 679 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 680 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 681 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 682 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 683 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 684 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 685 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 686 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 687 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 688 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 689}; 690#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 691 692 693/**************************************************************************** 694 * Function prototypes 695 ****************************************************************************/ 696static void hdac_intr_handler(void *); 697static int hdac_reset(struct hdac_softc *, int); 698static int hdac_get_capabilities(struct hdac_softc *); 699static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 700static int hdac_dma_alloc(struct hdac_softc *, 701 struct hdac_dma *, bus_size_t); 702static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 703static int hdac_mem_alloc(struct hdac_softc *); 704static void hdac_mem_free(struct hdac_softc *); 705static int hdac_irq_alloc(struct hdac_softc *); 706static void hdac_irq_free(struct hdac_softc *); 707static void hdac_corb_init(struct hdac_softc *); 708static void hdac_rirb_init(struct hdac_softc *); 709static void hdac_corb_start(struct hdac_softc *); 710static void hdac_rirb_start(struct hdac_softc *); 711static void hdac_scan_codecs(struct hdac_softc *); 712static void hdac_probe_codec(struct hdac_codec *); 713static void hdac_probe_function(struct hdac_codec *, nid_t); 714static int hdac_pcmchannel_setup(struct hdac_chan *); 715 716static void hdac_attach2(void *); 717 718static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 719 uint32_t, int); 720static void hdac_command_send_internal(struct hdac_softc *, 721 struct hdac_command_list *, int); 722 723static int hdac_probe(device_t); 724static int hdac_attach(device_t); 725static int hdac_detach(device_t); 726static int hdac_suspend(device_t); 727static int hdac_resume(device_t); 728static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 729static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 730 uint32_t, int, int); 731static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 732 nid_t, int, int, int); 733static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 734 nid_t, nid_t, int, int, int, int, int, int); 735static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 736 737static int hdac_rirb_flush(struct hdac_softc *sc); 738static int hdac_unsolq_flush(struct hdac_softc *sc); 739 740static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 741 742#define hdac_command(a1, a2, a3) \ 743 hdac_command_sendone_internal(a1, a2, a3) 744 745#define hdac_codec_id(c) \ 746 ((uint32_t)((c == NULL) ? 0x00000000 : \ 747 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 748 ((uint32_t)(c)->device_id & 0x0000ffff)))) 749 750static char * 751hdac_codec_name(struct hdac_codec *codec) 752{ 753 uint32_t id; 754 int i; 755 756 id = hdac_codec_id(codec); 757 758 for (i = 0; i < HDAC_CODECS_LEN; i++) { 759 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 760 return (hdac_codecs[i].name); 761 } 762 763 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 764} 765 766static char * 767hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 768{ 769 static char *ossname[] = SOUND_DEVICE_NAMES; 770 int i, first = 1; 771 772 bzero(buf, len); 773 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 774 if (mask & (1 << i)) { 775 if (first == 0) 776 strlcat(buf, ", ", len); 777 strlcat(buf, ossname[i], len); 778 first = 0; 779 } 780 } 781 return (buf); 782} 783 784static struct hdac_audio_ctl * 785hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 786{ 787 if (devinfo == NULL || 788 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 789 index == NULL || devinfo->function.audio.ctl == NULL || 790 devinfo->function.audio.ctlcnt < 1 || 791 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 792 return (NULL); 793 return (&devinfo->function.audio.ctl[(*index)++]); 794} 795 796static struct hdac_audio_ctl * 797hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 798 int index, int cnt) 799{ 800 struct hdac_audio_ctl *ctl; 801 int i, found = 0; 802 803 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 804 return (NULL); 805 806 i = 0; 807 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 808 if (ctl->enable == 0) 809 continue; 810 if (ctl->widget->nid != nid) 811 continue; 812 if (dir && ctl->ndir != dir) 813 continue; 814 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 815 ctl->dir == ctl->ndir && ctl->index != index) 816 continue; 817 found++; 818 if (found == cnt || cnt <= 0) 819 return (ctl); 820 } 821 822 return (NULL); 823} 824 825/* 826 * Jack detection (Speaker/HP redirection) event handler. 827 */ 828static void 829hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 830{ 831 struct hdac_audio_as *as; 832 struct hdac_softc *sc; 833 struct hdac_widget *w; 834 struct hdac_audio_ctl *ctl; 835 uint32_t val, res; 836 int i, j; 837 nid_t cad; 838 839 if (devinfo == NULL || devinfo->codec == NULL || 840 devinfo->codec->sc == NULL) 841 return; 842 843 sc = devinfo->codec->sc; 844 cad = devinfo->codec->cad; 845 as = devinfo->function.audio.as; 846 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 847 if (as[i].hpredir < 0) 848 continue; 849 850 w = hdac_widget_get(devinfo, as[i].pins[15]); 851 if (w == NULL || w->enable == 0 || w->type != 852 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 853 continue; 854 855 res = hdac_command(sc, 856 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 857 858 HDA_BOOTVERBOSE( 859 device_printf(sc->dev, 860 "Pin sense: nid=%d res=0x%08x\n", 861 as[i].pins[15], res); 862 ); 863 864 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 865 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 866 res ^= 1; 867 868 /* (Un)Mute headphone pin. */ 869 ctl = hdac_audio_ctl_amp_get(devinfo, 870 as[i].pins[15], HDA_CTL_IN, -1, 1); 871 if (ctl != NULL && ctl->mute) { 872 /* If pin has muter - use it. */ 873 val = (res != 0) ? 0 : 1; 874 if (val != ctl->forcemute) { 875 ctl->forcemute = val; 876 hdac_audio_ctl_amp_set(ctl, 877 HDA_AMP_MUTE_DEFAULT, 878 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 879 } 880 } else { 881 /* If there is no muter - disable pin output. */ 882 w = hdac_widget_get(devinfo, as[i].pins[15]); 883 if (w != NULL && w->type == 884 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 885 if (res != 0) 886 val = w->wclass.pin.ctrl | 887 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 888 else 889 val = w->wclass.pin.ctrl & 890 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 891 if (val != w->wclass.pin.ctrl) { 892 w->wclass.pin.ctrl = val; 893 hdac_command(sc, 894 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 895 w->nid, w->wclass.pin.ctrl), cad); 896 } 897 } 898 } 899 /* (Un)Mute other pins. */ 900 for (j = 0; j < 15; j++) { 901 if (as[i].pins[j] <= 0) 902 continue; 903 ctl = hdac_audio_ctl_amp_get(devinfo, 904 as[i].pins[j], HDA_CTL_IN, -1, 1); 905 if (ctl != NULL && ctl->mute) { 906 /* If pin has muter - use it. */ 907 val = (res != 0) ? 1 : 0; 908 if (val == ctl->forcemute) 909 continue; 910 ctl->forcemute = val; 911 hdac_audio_ctl_amp_set(ctl, 912 HDA_AMP_MUTE_DEFAULT, 913 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 914 continue; 915 } 916 /* If there is no muter - disable pin output. */ 917 w = hdac_widget_get(devinfo, as[i].pins[j]); 918 if (w != NULL && w->type == 919 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 920 if (res != 0) 921 val = w->wclass.pin.ctrl & 922 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 923 else 924 val = w->wclass.pin.ctrl | 925 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 926 if (val != w->wclass.pin.ctrl) { 927 w->wclass.pin.ctrl = val; 928 hdac_command(sc, 929 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 930 w->nid, w->wclass.pin.ctrl), cad); 931 } 932 } 933 } 934 } 935} 936 937/* 938 * Callback for poll based jack detection. 939 */ 940static void 941hdac_jack_poll_callback(void *arg) 942{ 943 struct hdac_devinfo *devinfo = arg; 944 struct hdac_softc *sc; 945 946 if (devinfo == NULL || devinfo->codec == NULL || 947 devinfo->codec->sc == NULL) 948 return; 949 sc = devinfo->codec->sc; 950 hdac_lock(sc); 951 if (sc->poll_ival == 0) { 952 hdac_unlock(sc); 953 return; 954 } 955 hdac_hp_switch_handler(devinfo); 956 callout_reset(&sc->poll_jack, sc->poll_ival, 957 hdac_jack_poll_callback, devinfo); 958 hdac_unlock(sc); 959} 960 961/* 962 * Jack detection initializer. 963 */ 964static void 965hdac_hp_switch_init(struct hdac_devinfo *devinfo) 966{ 967 struct hdac_softc *sc = devinfo->codec->sc; 968 struct hdac_audio_as *as = devinfo->function.audio.as; 969 struct hdac_widget *w; 970 uint32_t id; 971 int i, enable = 0, poll = 0; 972 nid_t cad; 973 974 id = hdac_codec_id(devinfo->codec); 975 cad = devinfo->codec->cad; 976 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 977 if (as[i].hpredir < 0) 978 continue; 979 980 w = hdac_widget_get(devinfo, as[i].pins[15]); 981 if (w == NULL || w->enable == 0 || w->type != 982 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 983 continue; 984 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 985 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 986 device_printf(sc->dev, 987 "No jack detection support at pin %d\n", 988 as[i].pins[15]); 989 continue; 990 } 991 enable = 1; 992 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 993 hdac_command(sc, 994 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 995 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 996 HDAC_UNSOLTAG_EVENT_HP), cad); 997 } else 998 poll = 1; 999 HDA_BOOTVERBOSE( 1000 device_printf(sc->dev, 1001 "Enabling headphone/speaker " 1002 "audio routing switching:\n"); 1003 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1004 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1005 ); 1006 } 1007 if (enable) { 1008 hdac_hp_switch_handler(devinfo); 1009 if (poll) { 1010 callout_reset(&sc->poll_jack, 1, 1011 hdac_jack_poll_callback, devinfo); 1012 } 1013 } 1014} 1015 1016/* 1017 * Unsolicited messages handler. 1018 */ 1019static void 1020hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1021{ 1022 struct hdac_softc *sc; 1023 struct hdac_devinfo *devinfo = NULL; 1024 int i; 1025 1026 if (codec == NULL || codec->sc == NULL) 1027 return; 1028 1029 sc = codec->sc; 1030 1031 HDA_BOOTVERBOSE( 1032 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1033 ); 1034 1035 for (i = 0; i < codec->num_fgs; i++) { 1036 if (codec->fgs[i].node_type == 1037 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1038 devinfo = &codec->fgs[i]; 1039 break; 1040 } 1041 } 1042 1043 if (devinfo == NULL) 1044 return; 1045 1046 switch (tag) { 1047 case HDAC_UNSOLTAG_EVENT_HP: 1048 hdac_hp_switch_handler(devinfo); 1049 break; 1050 default: 1051 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1052 break; 1053 } 1054} 1055 1056static int 1057hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1058{ 1059 /* XXX to be removed */ 1060#ifdef HDAC_INTR_EXTRA 1061 uint32_t res; 1062#endif 1063 1064 if (!(ch->flags & HDAC_CHN_RUNNING)) 1065 return (0); 1066 1067 /* XXX to be removed */ 1068#ifdef HDAC_INTR_EXTRA 1069 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1070#endif 1071 1072 /* XXX to be removed */ 1073#ifdef HDAC_INTR_EXTRA 1074 HDA_BOOTVERBOSE( 1075 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1076 device_printf(ch->pdevinfo->dev, 1077 "PCMDIR_%s intr triggered beyond stream boundary:" 1078 "%08x\n", 1079 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1080 ); 1081#endif 1082 1083 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1084 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1085 1086 /* XXX to be removed */ 1087#ifdef HDAC_INTR_EXTRA 1088 if (res & HDAC_SDSTS_BCIS) { 1089#endif 1090 return (1); 1091 /* XXX to be removed */ 1092#ifdef HDAC_INTR_EXTRA 1093 } 1094#endif 1095 1096 return (0); 1097} 1098 1099/**************************************************************************** 1100 * void hdac_intr_handler(void *) 1101 * 1102 * Interrupt handler. Processes interrupts received from the hdac. 1103 ****************************************************************************/ 1104static void 1105hdac_intr_handler(void *context) 1106{ 1107 struct hdac_softc *sc; 1108 uint32_t intsts; 1109 uint8_t rirbsts; 1110 struct hdac_rirb *rirb_base; 1111 uint32_t trigger; 1112 int i; 1113 1114 sc = (struct hdac_softc *)context; 1115 1116 hdac_lock(sc); 1117 if (sc->polling != 0) { 1118 hdac_unlock(sc); 1119 return; 1120 } 1121 1122 /* Do we have anything to do? */ 1123 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1124 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1125 hdac_unlock(sc); 1126 return; 1127 } 1128 1129 trigger = 0; 1130 1131 /* Was this a controller interrupt? */ 1132 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1133 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1134 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1135 /* Get as many responses that we can */ 1136 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1137 HDAC_WRITE_1(&sc->mem, 1138 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1139 if (hdac_rirb_flush(sc) != 0) 1140 trigger |= HDAC_TRIGGER_UNSOL; 1141 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1142 } 1143 /* XXX to be removed */ 1144 /* Clear interrupt and exit */ 1145#ifdef HDAC_INTR_EXTRA 1146 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1147#endif 1148 } 1149 1150 if (intsts & HDAC_INTSTS_SIS_MASK) { 1151 for (i = 0; i < sc->num_chans; i++) { 1152 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1153 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1154 trigger |= (1 << i); 1155 } 1156 /* XXX to be removed */ 1157#ifdef HDAC_INTR_EXTRA 1158 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1159 HDAC_INTSTS_SIS_MASK); 1160#endif 1161 } 1162 1163 hdac_unlock(sc); 1164 1165 for (i = 0; i < sc->num_chans; i++) { 1166 if (trigger & (1 << i)) 1167 chn_intr(sc->chans[i].c); 1168 } 1169 if (trigger & HDAC_TRIGGER_UNSOL) 1170 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1171} 1172 1173/**************************************************************************** 1174 * int hdac_reset(hdac_softc *, int) 1175 * 1176 * Reset the hdac to a quiescent and known state. 1177 ****************************************************************************/ 1178static int 1179hdac_reset(struct hdac_softc *sc, int wakeup) 1180{ 1181 uint32_t gctl; 1182 int count, i; 1183 1184 /* 1185 * Stop all Streams DMA engine 1186 */ 1187 for (i = 0; i < sc->num_iss; i++) 1188 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1189 for (i = 0; i < sc->num_oss; i++) 1190 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1191 for (i = 0; i < sc->num_bss; i++) 1192 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1193 1194 /* 1195 * Stop Control DMA engines. 1196 */ 1197 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1198 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1199 1200 /* 1201 * Reset DMA position buffer. 1202 */ 1203 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1204 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1205 1206 /* 1207 * Reset the controller. The reset must remain asserted for 1208 * a minimum of 100us. 1209 */ 1210 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1211 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1212 count = 10000; 1213 do { 1214 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1215 if (!(gctl & HDAC_GCTL_CRST)) 1216 break; 1217 DELAY(10); 1218 } while (--count); 1219 if (gctl & HDAC_GCTL_CRST) { 1220 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1221 return (ENXIO); 1222 } 1223 1224 /* If wakeup is not requested - leave the controller in reset state. */ 1225 if (!wakeup) 1226 return (0); 1227 1228 DELAY(100); 1229 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1230 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1231 count = 10000; 1232 do { 1233 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1234 if (gctl & HDAC_GCTL_CRST) 1235 break; 1236 DELAY(10); 1237 } while (--count); 1238 if (!(gctl & HDAC_GCTL_CRST)) { 1239 device_printf(sc->dev, "Device stuck in reset\n"); 1240 return (ENXIO); 1241 } 1242 1243 /* 1244 * Wait for codecs to finish their own reset sequence. The delay here 1245 * should be of 250us but for some reasons, on it's not enough on my 1246 * computer. Let's use twice as much as necessary to make sure that 1247 * it's reset properly. 1248 */ 1249 DELAY(1000); 1250 1251 return (0); 1252} 1253 1254 1255/**************************************************************************** 1256 * int hdac_get_capabilities(struct hdac_softc *); 1257 * 1258 * Retreive the general capabilities of the hdac; 1259 * Number of Input Streams 1260 * Number of Output Streams 1261 * Number of bidirectional Streams 1262 * 64bit ready 1263 * CORB and RIRB sizes 1264 ****************************************************************************/ 1265static int 1266hdac_get_capabilities(struct hdac_softc *sc) 1267{ 1268 uint16_t gcap; 1269 uint8_t corbsize, rirbsize; 1270 1271 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1272 sc->num_iss = HDAC_GCAP_ISS(gcap); 1273 sc->num_oss = HDAC_GCAP_OSS(gcap); 1274 sc->num_bss = HDAC_GCAP_BSS(gcap); 1275 1276 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1277 1278 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1279 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1280 HDAC_CORBSIZE_CORBSZCAP_256) 1281 sc->corb_size = 256; 1282 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1283 HDAC_CORBSIZE_CORBSZCAP_16) 1284 sc->corb_size = 16; 1285 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1286 HDAC_CORBSIZE_CORBSZCAP_2) 1287 sc->corb_size = 2; 1288 else { 1289 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1290 __func__, corbsize); 1291 return (ENXIO); 1292 } 1293 1294 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1295 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1296 HDAC_RIRBSIZE_RIRBSZCAP_256) 1297 sc->rirb_size = 256; 1298 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1299 HDAC_RIRBSIZE_RIRBSZCAP_16) 1300 sc->rirb_size = 16; 1301 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1302 HDAC_RIRBSIZE_RIRBSZCAP_2) 1303 sc->rirb_size = 2; 1304 else { 1305 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1306 __func__, rirbsize); 1307 return (ENXIO); 1308 } 1309 1310 HDA_BOOTVERBOSE( 1311 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1312 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1313 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1314 sc->num_iss, sc->num_oss, sc->num_bss); 1315 ); 1316 1317 return (0); 1318} 1319 1320 1321/**************************************************************************** 1322 * void hdac_dma_cb 1323 * 1324 * This function is called by bus_dmamap_load when the mapping has been 1325 * established. We just record the physical address of the mapping into 1326 * the struct hdac_dma passed in. 1327 ****************************************************************************/ 1328static void 1329hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1330{ 1331 struct hdac_dma *dma; 1332 1333 if (error == 0) { 1334 dma = (struct hdac_dma *)callback_arg; 1335 dma->dma_paddr = segs[0].ds_addr; 1336 } 1337} 1338 1339 1340/**************************************************************************** 1341 * int hdac_dma_alloc 1342 * 1343 * This function allocate and setup a dma region (struct hdac_dma). 1344 * It must be freed by a corresponding hdac_dma_free. 1345 ****************************************************************************/ 1346static int 1347hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1348{ 1349 bus_size_t roundsz; 1350 int result; 1351 int lowaddr; 1352 1353 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1354 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1355 BUS_SPACE_MAXADDR_32BIT; 1356 bzero(dma, sizeof(*dma)); 1357 1358 /* 1359 * Create a DMA tag 1360 */ 1361 result = bus_dma_tag_create(NULL, /* parent */ 1362 HDAC_DMA_ALIGNMENT, /* alignment */ 1363 0, /* boundary */ 1364 lowaddr, /* lowaddr */ 1365 BUS_SPACE_MAXADDR, /* highaddr */ 1366 NULL, /* filtfunc */ 1367 NULL, /* fistfuncarg */ 1368 roundsz, /* maxsize */ 1369 1, /* nsegments */ 1370 roundsz, /* maxsegsz */ 1371 0, /* flags */ 1372 NULL, /* lockfunc */ 1373 NULL, /* lockfuncarg */ 1374 &dma->dma_tag); /* dmat */ 1375 if (result != 0) { 1376 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1377 __func__, result); 1378 goto hdac_dma_alloc_fail; 1379 } 1380 1381 /* 1382 * Allocate DMA memory 1383 */ 1384 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1385 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1386 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1387 &dma->dma_map); 1388 if (result != 0) { 1389 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1390 __func__, result); 1391 goto hdac_dma_alloc_fail; 1392 } 1393 1394 dma->dma_size = roundsz; 1395 1396 /* 1397 * Map the memory 1398 */ 1399 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1400 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1401 if (result != 0 || dma->dma_paddr == 0) { 1402 if (result == 0) 1403 result = ENOMEM; 1404 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1405 __func__, result); 1406 goto hdac_dma_alloc_fail; 1407 } 1408 1409 HDA_BOOTVERBOSE( 1410 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1411 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1412 ); 1413 1414 return (0); 1415 1416hdac_dma_alloc_fail: 1417 hdac_dma_free(sc, dma); 1418 1419 return (result); 1420} 1421 1422 1423/**************************************************************************** 1424 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1425 * 1426 * Free a struct dhac_dma that has been previously allocated via the 1427 * hdac_dma_alloc function. 1428 ****************************************************************************/ 1429static void 1430hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1431{ 1432 if (dma->dma_map != NULL) { 1433#if 0 1434 /* Flush caches */ 1435 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1436 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1437#endif 1438 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1439 } 1440 if (dma->dma_vaddr != NULL) { 1441 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1442 dma->dma_vaddr = NULL; 1443 } 1444 dma->dma_map = NULL; 1445 if (dma->dma_tag != NULL) { 1446 bus_dma_tag_destroy(dma->dma_tag); 1447 dma->dma_tag = NULL; 1448 } 1449 dma->dma_size = 0; 1450} 1451 1452/**************************************************************************** 1453 * int hdac_mem_alloc(struct hdac_softc *) 1454 * 1455 * Allocate all the bus resources necessary to speak with the physical 1456 * controller. 1457 ****************************************************************************/ 1458static int 1459hdac_mem_alloc(struct hdac_softc *sc) 1460{ 1461 struct hdac_mem *mem; 1462 1463 mem = &sc->mem; 1464 mem->mem_rid = PCIR_BAR(0); 1465 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1466 &mem->mem_rid, RF_ACTIVE); 1467 if (mem->mem_res == NULL) { 1468 device_printf(sc->dev, 1469 "%s: Unable to allocate memory resource\n", __func__); 1470 return (ENOMEM); 1471 } 1472 mem->mem_tag = rman_get_bustag(mem->mem_res); 1473 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1474 1475 return (0); 1476} 1477 1478/**************************************************************************** 1479 * void hdac_mem_free(struct hdac_softc *) 1480 * 1481 * Free up resources previously allocated by hdac_mem_alloc. 1482 ****************************************************************************/ 1483static void 1484hdac_mem_free(struct hdac_softc *sc) 1485{ 1486 struct hdac_mem *mem; 1487 1488 mem = &sc->mem; 1489 if (mem->mem_res != NULL) 1490 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1491 mem->mem_res); 1492 mem->mem_res = NULL; 1493} 1494 1495/**************************************************************************** 1496 * int hdac_irq_alloc(struct hdac_softc *) 1497 * 1498 * Allocate and setup the resources necessary for interrupt handling. 1499 ****************************************************************************/ 1500static int 1501hdac_irq_alloc(struct hdac_softc *sc) 1502{ 1503 struct hdac_irq *irq; 1504 int result; 1505 1506 irq = &sc->irq; 1507 irq->irq_rid = 0x0; 1508 1509#ifdef HDAC_MSI_ENABLED 1510 if ((sc->flags & HDAC_F_MSI) && 1511 (result = pci_msi_count(sc->dev)) == 1 && 1512 pci_alloc_msi(sc->dev, &result) == 0) 1513 irq->irq_rid = 0x1; 1514 else 1515#endif 1516 sc->flags &= ~HDAC_F_MSI; 1517 1518 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1519 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1520 if (irq->irq_res == NULL) { 1521 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1522 __func__); 1523 goto hdac_irq_alloc_fail; 1524 } 1525 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1526 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1527 if (result != 0) { 1528 device_printf(sc->dev, 1529 "%s: Unable to setup interrupt handler (%x)\n", 1530 __func__, result); 1531 goto hdac_irq_alloc_fail; 1532 } 1533 1534 return (0); 1535 1536hdac_irq_alloc_fail: 1537 hdac_irq_free(sc); 1538 1539 return (ENXIO); 1540} 1541 1542/**************************************************************************** 1543 * void hdac_irq_free(struct hdac_softc *) 1544 * 1545 * Free up resources previously allocated by hdac_irq_alloc. 1546 ****************************************************************************/ 1547static void 1548hdac_irq_free(struct hdac_softc *sc) 1549{ 1550 struct hdac_irq *irq; 1551 1552 irq = &sc->irq; 1553 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1554 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1555 if (irq->irq_res != NULL) 1556 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1557 irq->irq_res); 1558#ifdef HDAC_MSI_ENABLED 1559 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1560 pci_release_msi(sc->dev); 1561#endif 1562 irq->irq_handle = NULL; 1563 irq->irq_res = NULL; 1564 irq->irq_rid = 0x0; 1565} 1566 1567/**************************************************************************** 1568 * void hdac_corb_init(struct hdac_softc *) 1569 * 1570 * Initialize the corb registers for operations but do not start it up yet. 1571 * The CORB engine must not be running when this function is called. 1572 ****************************************************************************/ 1573static void 1574hdac_corb_init(struct hdac_softc *sc) 1575{ 1576 uint8_t corbsize; 1577 uint64_t corbpaddr; 1578 1579 /* Setup the CORB size. */ 1580 switch (sc->corb_size) { 1581 case 256: 1582 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1583 break; 1584 case 16: 1585 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1586 break; 1587 case 2: 1588 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1589 break; 1590 default: 1591 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1592 } 1593 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1594 1595 /* Setup the CORB Address in the hdac */ 1596 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1597 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1598 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1599 1600 /* Set the WP and RP */ 1601 sc->corb_wp = 0; 1602 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1603 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1604 /* 1605 * The HDA specification indicates that the CORBRPRST bit will always 1606 * read as zero. Unfortunately, it seems that at least the 82801G 1607 * doesn't reset the bit to zero, which stalls the corb engine. 1608 * manually reset the bit to zero before continuing. 1609 */ 1610 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1611 1612 /* Enable CORB error reporting */ 1613#if 0 1614 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1615#endif 1616} 1617 1618/**************************************************************************** 1619 * void hdac_rirb_init(struct hdac_softc *) 1620 * 1621 * Initialize the rirb registers for operations but do not start it up yet. 1622 * The RIRB engine must not be running when this function is called. 1623 ****************************************************************************/ 1624static void 1625hdac_rirb_init(struct hdac_softc *sc) 1626{ 1627 uint8_t rirbsize; 1628 uint64_t rirbpaddr; 1629 1630 /* Setup the RIRB size. */ 1631 switch (sc->rirb_size) { 1632 case 256: 1633 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1634 break; 1635 case 16: 1636 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1637 break; 1638 case 2: 1639 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1640 break; 1641 default: 1642 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1643 } 1644 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1645 1646 /* Setup the RIRB Address in the hdac */ 1647 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1648 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1649 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1650 1651 /* Setup the WP and RP */ 1652 sc->rirb_rp = 0; 1653 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1654 1655 /* Setup the interrupt threshold */ 1656 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1657 1658 /* Enable Overrun and response received reporting */ 1659#if 0 1660 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1661 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1662#else 1663 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1664#endif 1665 1666#if 0 1667 /* 1668 * Make sure that the Host CPU cache doesn't contain any dirty 1669 * cache lines that falls in the rirb. If I understood correctly, it 1670 * should be sufficient to do this only once as the rirb is purely 1671 * read-only from now on. 1672 */ 1673 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1674 BUS_DMASYNC_PREREAD); 1675#endif 1676} 1677 1678/**************************************************************************** 1679 * void hdac_corb_start(hdac_softc *) 1680 * 1681 * Startup the corb DMA engine 1682 ****************************************************************************/ 1683static void 1684hdac_corb_start(struct hdac_softc *sc) 1685{ 1686 uint32_t corbctl; 1687 1688 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1689 corbctl |= HDAC_CORBCTL_CORBRUN; 1690 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1691} 1692 1693/**************************************************************************** 1694 * void hdac_rirb_start(hdac_softc *) 1695 * 1696 * Startup the rirb DMA engine 1697 ****************************************************************************/ 1698static void 1699hdac_rirb_start(struct hdac_softc *sc) 1700{ 1701 uint32_t rirbctl; 1702 1703 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1704 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1705 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1706} 1707 1708 1709/**************************************************************************** 1710 * void hdac_scan_codecs(struct hdac_softc *, int) 1711 * 1712 * Scan the bus for available codecs, starting with num. 1713 ****************************************************************************/ 1714static void 1715hdac_scan_codecs(struct hdac_softc *sc) 1716{ 1717 struct hdac_codec *codec; 1718 int i; 1719 uint16_t statests; 1720 1721 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1722 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1723 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1724 /* We have found a codec. */ 1725 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1726 M_HDAC, M_ZERO | M_NOWAIT); 1727 if (codec == NULL) { 1728 device_printf(sc->dev, 1729 "Unable to allocate memory for codec\n"); 1730 continue; 1731 } 1732 codec->commands = NULL; 1733 codec->responses_received = 0; 1734 codec->verbs_sent = 0; 1735 codec->sc = sc; 1736 codec->cad = i; 1737 sc->codecs[i] = codec; 1738 hdac_probe_codec(codec); 1739 } 1740 } 1741 /* All codecs have been probed, now try to attach drivers to them */ 1742 /* bus_generic_attach(sc->dev); */ 1743} 1744 1745/**************************************************************************** 1746 * void hdac_probe_codec(struct hdac_softc *, int) 1747 * 1748 * Probe a the given codec_id for available function groups. 1749 ****************************************************************************/ 1750static void 1751hdac_probe_codec(struct hdac_codec *codec) 1752{ 1753 struct hdac_softc *sc = codec->sc; 1754 uint32_t vendorid, revisionid, subnode; 1755 int startnode; 1756 int endnode; 1757 int i; 1758 nid_t cad = codec->cad; 1759 1760 HDA_BOOTVERBOSE( 1761 device_printf(sc->dev, "Probing codec %d...\n", cad); 1762 ); 1763 vendorid = hdac_command(sc, 1764 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1765 cad); 1766 revisionid = hdac_command(sc, 1767 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1768 cad); 1769 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1770 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1771 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1772 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1773 1774 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 1775 device_printf(sc->dev, "Codec #%d is not responding!" 1776 " Probing aborted.\n", cad); 1777 return; 1778 } 1779 1780 device_printf(sc->dev, "<HDA Codec #%d: %s>\n", 1781 cad, hdac_codec_name(codec)); 1782 HDA_BOOTVERBOSE( 1783 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 1784 hdac_codec_id(codec)); 1785 device_printf(sc->dev, " Vendor: 0x%04x\n", 1786 codec->vendor_id); 1787 device_printf(sc->dev, " Device: 0x%04x\n", 1788 codec->device_id); 1789 device_printf(sc->dev, " Revision: 0x%02x\n", 1790 codec->revision_id); 1791 device_printf(sc->dev, " Stepping: 0x%02x\n", 1792 codec->stepping_id); 1793 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 1794 sc->pci_subvendor); 1795 ); 1796 subnode = hdac_command(sc, 1797 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1798 cad); 1799 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1800 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1801 1802 HDA_BOOTVERBOSE( 1803 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 1804 startnode, endnode); 1805 ); 1806 1807 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 1808 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 1809 if (codec->fgs == NULL) { 1810 device_printf(sc->dev, "%s: Unable to allocate functiom groups\n", 1811 __func__); 1812 return; 1813 } 1814 1815 for (i = startnode; i < endnode; i++) 1816 hdac_probe_function(codec, i); 1817 return; 1818} 1819 1820/* 1821 * Probe codec function and add it to the list. 1822 */ 1823static void 1824hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1825{ 1826 struct hdac_softc *sc = codec->sc; 1827 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 1828 uint32_t fctgrptype; 1829 uint32_t res; 1830 nid_t cad = codec->cad; 1831 1832 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1833 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1834 1835 devinfo->nid = nid; 1836 devinfo->node_type = fctgrptype; 1837 devinfo->codec = codec; 1838 1839 res = hdac_command(sc, 1840 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 1841 1842 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 1843 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 1844 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 1845 1846 HDA_BOOTVERBOSE( 1847 device_printf(sc->dev, 1848 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 1849 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 1850 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 1851 "unknown", nid, devinfo->startnode, devinfo->endnode, 1852 devinfo->nodecnt); 1853 ); 1854 1855 if (devinfo->nodecnt > 0) 1856 devinfo->widget = (struct hdac_widget *)malloc( 1857 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 1858 M_NOWAIT | M_ZERO); 1859 else 1860 devinfo->widget = NULL; 1861 1862 if (devinfo->widget == NULL) { 1863 device_printf(sc->dev, "unable to allocate widgets!\n"); 1864 devinfo->endnode = devinfo->startnode; 1865 devinfo->nodecnt = 0; 1866 return; 1867 } 1868 1869 codec->num_fgs++; 1870} 1871 1872static void 1873hdac_widget_connection_parse(struct hdac_widget *w) 1874{ 1875 struct hdac_softc *sc = w->devinfo->codec->sc; 1876 uint32_t res; 1877 int i, j, max, ents, entnum; 1878 nid_t cad = w->devinfo->codec->cad; 1879 nid_t nid = w->nid; 1880 nid_t cnid, addcnid, prevcnid; 1881 1882 w->nconns = 0; 1883 1884 res = hdac_command(sc, 1885 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1886 1887 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1888 1889 if (ents < 1) 1890 return; 1891 1892 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1893 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1894 prevcnid = 0; 1895 1896#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1897#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1898#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1899#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1900#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1901 1902 for (i = 0; i < ents; i += entnum) { 1903 res = hdac_command(sc, 1904 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1905 for (j = 0; j < entnum; j++) { 1906 cnid = CONN_CNID(res, entnum, j); 1907 if (cnid == 0) { 1908 if (w->nconns < ents) 1909 device_printf(sc->dev, 1910 "%s: nid=%d WARNING: zero cnid " 1911 "entnum=%d j=%d index=%d " 1912 "entries=%d found=%d res=0x%08x\n", 1913 __func__, nid, entnum, j, i, 1914 ents, w->nconns, res); 1915 else 1916 goto getconns_out; 1917 } 1918 if (cnid < w->devinfo->startnode || 1919 cnid >= w->devinfo->endnode) { 1920 HDA_BOOTVERBOSE( 1921 device_printf(sc->dev, 1922 "GHOST: nid=%d j=%d " 1923 "entnum=%d index=%d res=0x%08x\n", 1924 nid, j, entnum, i, res); 1925 ); 1926 } 1927 if (CONN_RANGE(res, entnum, j) == 0) 1928 addcnid = cnid; 1929 else if (prevcnid == 0 || prevcnid >= cnid) { 1930 device_printf(sc->dev, 1931 "%s: WARNING: Invalid child range " 1932 "nid=%d index=%d j=%d entnum=%d " 1933 "prevcnid=%d cnid=%d res=0x%08x\n", 1934 __func__, nid, i, j, entnum, prevcnid, 1935 cnid, res); 1936 addcnid = cnid; 1937 } else 1938 addcnid = prevcnid + 1; 1939 while (addcnid <= cnid) { 1940 if (w->nconns > max) { 1941 device_printf(sc->dev, 1942 "Adding %d (nid=%d): " 1943 "Max connection reached! max=%d\n", 1944 addcnid, nid, max + 1); 1945 goto getconns_out; 1946 } 1947 w->connsenable[w->nconns] = 1; 1948 w->conns[w->nconns++] = addcnid++; 1949 } 1950 prevcnid = cnid; 1951 } 1952 } 1953 1954getconns_out: 1955 return; 1956} 1957 1958static uint32_t 1959hdac_widget_pin_patch(uint32_t config, const char *str) 1960{ 1961 char buf[256]; 1962 char *key, *value, *rest, *bad; 1963 int ival, i; 1964 1965 strlcpy(buf, str, sizeof(buf)); 1966 rest = buf; 1967 while ((key = strsep(&rest, "=")) != NULL) { 1968 value = strsep(&rest, " \t"); 1969 if (value == NULL) 1970 break; 1971 ival = strtol(value, &bad, 10); 1972 if (strcmp(key, "seq") == 0) { 1973 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 1974 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 1975 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 1976 } else if (strcmp(key, "as") == 0) { 1977 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 1978 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 1979 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 1980 } else if (strcmp(key, "misc") == 0) { 1981 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 1982 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 1983 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 1984 } else if (strcmp(key, "color") == 0) { 1985 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 1986 if (bad[0] == 0) { 1987 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 1988 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 1989 }; 1990 for (i = 0; i < 16; i++) { 1991 if (strcasecmp(HDA_COLORS[i], value) == 0) { 1992 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 1993 break; 1994 } 1995 } 1996 } else if (strcmp(key, "ctype") == 0) { 1997 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 1998 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 1999 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2000 } else if (strcmp(key, "device") == 0) { 2001 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2002 if (bad[0] == 0) { 2003 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2004 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2005 continue; 2006 }; 2007 for (i = 0; i < 16; i++) { 2008 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2009 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2010 break; 2011 } 2012 } 2013 } else if (strcmp(key, "loc") == 0) { 2014 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2015 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2016 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2017 } else if (strcmp(key, "conn") == 0) { 2018 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2019 if (bad[0] == 0) { 2020 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2021 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2022 continue; 2023 }; 2024 for (i = 0; i < 4; i++) { 2025 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2026 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2027 break; 2028 } 2029 } 2030 } 2031 } 2032 return (config); 2033} 2034 2035static uint32_t 2036hdac_widget_pin_getconfig(struct hdac_widget *w) 2037{ 2038 struct hdac_softc *sc; 2039 uint32_t config, orig, id; 2040 nid_t cad, nid; 2041 char buf[32]; 2042 const char *res = NULL, *patch = NULL; 2043 2044 sc = w->devinfo->codec->sc; 2045 cad = w->devinfo->codec->cad; 2046 nid = w->nid; 2047 id = hdac_codec_id(w->devinfo->codec); 2048 2049 config = hdac_command(sc, 2050 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2051 cad); 2052 orig = config; 2053 2054 HDA_BOOTVERBOSE( 2055 hdac_dump_pin_config(w, orig); 2056 ); 2057 2058 /* XXX: Old patches require complete review. 2059 * Now they may create more problem then solve due to 2060 * incorrect associations. 2061 */ 2062 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2063 switch (nid) { 2064 case 26: 2065 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2066 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2067 break; 2068 case 27: 2069 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2070 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2071 break; 2072 default: 2073 break; 2074 } 2075 } else if (id == HDA_CODEC_ALC880 && 2076 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2077 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2078 /* 2079 * Super broken BIOS 2080 */ 2081 switch (nid) { 2082 case 24: /* MIC1 */ 2083 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2084 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2085 break; 2086 case 25: /* XXX MIC2 */ 2087 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2088 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2089 break; 2090 case 26: /* LINE1 */ 2091 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2092 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2093 break; 2094 case 27: /* XXX LINE2 */ 2095 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2096 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2097 break; 2098 case 28: /* CD */ 2099 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2100 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2101 break; 2102 } 2103 } else if (id == HDA_CODEC_ALC883 && 2104 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2105 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2106 switch (nid) { 2107 case 25: 2108 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2109 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2110 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2111 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2112 break; 2113 case 28: 2114 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2115 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2116 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2117 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2118 break; 2119 } 2120 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2121 HP_V3000_SUBVENDOR) { 2122 switch (nid) { 2123 case 18: 2124 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2125 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2126 break; 2127 case 20: 2128 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2129 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2130 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2131 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2132 break; 2133 case 21: 2134 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2135 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2136 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2137 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2138 break; 2139 } 2140 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2141 HP_DV5000_SUBVENDOR) { 2142 switch (nid) { 2143 case 20: 2144 case 21: 2145 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2146 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2147 break; 2148 } 2149 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2150 ASUS_W6F_SUBVENDOR) { 2151 switch (nid) { 2152 case 11: 2153 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2154 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2155 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2156 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2157 break; 2158 case 12: 2159 case 14: 2160 case 16: 2161 case 31: 2162 case 32: 2163 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2164 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2165 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2166 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2167 break; 2168 case 15: 2169 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2170 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2171 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2172 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2173 break; 2174 } 2175 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2176 UNIWILL_9075_SUBVENDOR) { 2177 switch (nid) { 2178 case 15: 2179 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2180 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2181 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2182 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2183 break; 2184 } 2185 } 2186 2187 /* New patches */ 2188 if (id == HDA_CODEC_AD1986A && 2189 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2190 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2191 switch (nid) { 2192 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2193 patch = "device=Line-in as=8 seq=1"; 2194 break; 2195 case 29: 2196 patch = "device=Mic as=8 seq=2"; 2197 break; 2198 case 31: /* Lot of inputs configured with as=15 and unusable */ 2199 patch = "as=8 seq=3"; 2200 break; 2201 case 32: 2202 patch = "as=8 seq=4"; 2203 break; 2204 case 34: 2205 patch = "as=8 seq=5"; 2206 break; 2207 case 36: 2208 patch = "as=8 seq=6"; 2209 break; 2210 } 2211 } else if (id == HDA_CODEC_ALC260 && 2212 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2213 switch (nid) { 2214 case 16: 2215 patch = "seq=15 device=Headphones"; 2216 break; 2217 } 2218 } else if (id == HDA_CODEC_ALC268 && 2219 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2220 switch (nid) { 2221 case 28: 2222 patch = "device=CD conn=fixed"; 2223 break; 2224 } 2225 } 2226 2227 if (patch != NULL) 2228 config = hdac_widget_pin_patch(config, patch); 2229 2230 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2231 if (resource_string_value(device_get_name(sc->dev), 2232 device_get_unit(sc->dev), buf, &res) == 0) { 2233 if (strncmp(res, "0x", 2) == 0) { 2234 config = strtol(res + 2, NULL, 16); 2235 } else { 2236 config = hdac_widget_pin_patch(config, res); 2237 } 2238 } 2239 2240 HDA_BOOTVERBOSE( 2241 if (config != orig) 2242 device_printf(sc->dev, 2243 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2244 nid, orig, config); 2245 ); 2246 2247 return (config); 2248} 2249 2250static uint32_t 2251hdac_widget_pin_getcaps(struct hdac_widget *w) 2252{ 2253 struct hdac_softc *sc; 2254 uint32_t caps, orig, id; 2255 nid_t cad, nid; 2256 2257 sc = w->devinfo->codec->sc; 2258 cad = w->devinfo->codec->cad; 2259 nid = w->nid; 2260 id = hdac_codec_id(w->devinfo->codec); 2261 2262 caps = hdac_command(sc, 2263 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2264 orig = caps; 2265 2266 HDA_BOOTVERBOSE( 2267 if (caps != orig) 2268 device_printf(sc->dev, 2269 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2270 nid, orig, caps); 2271 ); 2272 2273 return (caps); 2274} 2275 2276static void 2277hdac_widget_pin_parse(struct hdac_widget *w) 2278{ 2279 struct hdac_softc *sc = w->devinfo->codec->sc; 2280 uint32_t config, pincap; 2281 const char *devstr, *connstr; 2282 nid_t cad = w->devinfo->codec->cad; 2283 nid_t nid = w->nid; 2284 2285 config = hdac_widget_pin_getconfig(w); 2286 w->wclass.pin.config = config; 2287 2288 pincap = hdac_widget_pin_getcaps(w); 2289 w->wclass.pin.cap = pincap; 2290 2291 w->wclass.pin.ctrl = hdac_command(sc, 2292 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2293 2294 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2295 w->param.eapdbtl = hdac_command(sc, 2296 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2297 w->param.eapdbtl &= 0x7; 2298 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2299 } else 2300 w->param.eapdbtl = HDAC_INVALID; 2301 2302 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2303 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2304 2305 connstr = HDA_CONNS[(config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2306 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT]; 2307 2308 strlcat(w->name, ": ", sizeof(w->name)); 2309 strlcat(w->name, devstr, sizeof(w->name)); 2310 strlcat(w->name, " (", sizeof(w->name)); 2311 strlcat(w->name, connstr, sizeof(w->name)); 2312 strlcat(w->name, ")", sizeof(w->name)); 2313} 2314 2315static uint32_t 2316hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2317{ 2318 struct hdac_softc *sc; 2319 uint32_t caps, orig, id; 2320 nid_t cad, nid, beeper = -1; 2321 2322 sc = w->devinfo->codec->sc; 2323 cad = w->devinfo->codec->cad; 2324 nid = w->nid; 2325 id = hdac_codec_id(w->devinfo->codec); 2326 2327 caps = hdac_command(sc, 2328 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2329 cad); 2330 orig = caps; 2331 2332 /* On some codecs beeper is an input pin, but it is not recordable 2333 alone. Also most of BIOSes does not declare beeper pin. 2334 Change beeper pin node type to beeper to help parser. */ 2335 *waspin = 0; 2336 switch (id) { 2337 case HDA_CODEC_AD1988: 2338 case HDA_CODEC_AD1988B: 2339 beeper = 26; 2340 break; 2341 case HDA_CODEC_ALC260: 2342 beeper = 23; 2343 break; 2344 case HDA_CODEC_ALC262: 2345 case HDA_CODEC_ALC268: 2346 case HDA_CODEC_ALC880: 2347 case HDA_CODEC_ALC882: 2348 case HDA_CODEC_ALC883: 2349 case HDA_CODEC_ALC885: 2350 case HDA_CODEC_ALC888: 2351 case HDA_CODEC_ALC889: 2352 beeper = 29; 2353 break; 2354 } 2355 if (nid == beeper) { 2356 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2357 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2358 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2359 *waspin = 1; 2360 } 2361 2362 HDA_BOOTVERBOSE( 2363 if (caps != orig) { 2364 device_printf(sc->dev, 2365 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2366 nid, orig, caps); 2367 } 2368 ); 2369 2370 return (caps); 2371} 2372 2373static void 2374hdac_widget_parse(struct hdac_widget *w) 2375{ 2376 struct hdac_softc *sc = w->devinfo->codec->sc; 2377 uint32_t wcap, cap; 2378 char *typestr; 2379 nid_t cad = w->devinfo->codec->cad; 2380 nid_t nid = w->nid; 2381 2382 wcap = hdac_widget_getcaps(w, &w->waspin); 2383 2384 w->param.widget_cap = wcap; 2385 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2386 2387 switch (w->type) { 2388 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2389 typestr = "audio output"; 2390 break; 2391 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2392 typestr = "audio input"; 2393 break; 2394 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2395 typestr = "audio mixer"; 2396 break; 2397 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2398 typestr = "audio selector"; 2399 break; 2400 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2401 typestr = "pin"; 2402 break; 2403 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2404 typestr = "power widget"; 2405 break; 2406 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2407 typestr = "volume widget"; 2408 break; 2409 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2410 typestr = "beep widget"; 2411 break; 2412 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2413 typestr = "vendor widget"; 2414 break; 2415 default: 2416 typestr = "unknown type"; 2417 break; 2418 } 2419 2420 strlcpy(w->name, typestr, sizeof(w->name)); 2421 2422 hdac_widget_connection_parse(w); 2423 2424 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2425 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2426 w->param.outamp_cap = 2427 hdac_command(sc, 2428 HDA_CMD_GET_PARAMETER(cad, nid, 2429 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2430 else 2431 w->param.outamp_cap = 2432 w->devinfo->function.audio.outamp_cap; 2433 } else 2434 w->param.outamp_cap = 0; 2435 2436 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2437 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2438 w->param.inamp_cap = 2439 hdac_command(sc, 2440 HDA_CMD_GET_PARAMETER(cad, nid, 2441 HDA_PARAM_INPUT_AMP_CAP), cad); 2442 else 2443 w->param.inamp_cap = 2444 w->devinfo->function.audio.inamp_cap; 2445 } else 2446 w->param.inamp_cap = 0; 2447 2448 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2449 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2450 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2451 cap = hdac_command(sc, 2452 HDA_CMD_GET_PARAMETER(cad, nid, 2453 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2454 w->param.supp_stream_formats = (cap != 0) ? cap : 2455 w->devinfo->function.audio.supp_stream_formats; 2456 cap = hdac_command(sc, 2457 HDA_CMD_GET_PARAMETER(cad, nid, 2458 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2459 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2460 w->devinfo->function.audio.supp_pcm_size_rate; 2461 } else { 2462 w->param.supp_stream_formats = 2463 w->devinfo->function.audio.supp_stream_formats; 2464 w->param.supp_pcm_size_rate = 2465 w->devinfo->function.audio.supp_pcm_size_rate; 2466 } 2467 } else { 2468 w->param.supp_stream_formats = 0; 2469 w->param.supp_pcm_size_rate = 0; 2470 } 2471 2472 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2473 hdac_widget_pin_parse(w); 2474} 2475 2476static struct hdac_widget * 2477hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2478{ 2479 if (devinfo == NULL || devinfo->widget == NULL || 2480 nid < devinfo->startnode || nid >= devinfo->endnode) 2481 return (NULL); 2482 return (&devinfo->widget[nid - devinfo->startnode]); 2483} 2484 2485static __inline int 2486hda_poll_channel(struct hdac_chan *ch) 2487{ 2488 uint32_t sz, delta; 2489 volatile uint32_t ptr; 2490 2491 if (!(ch->flags & HDAC_CHN_RUNNING)) 2492 return (0); 2493 2494 sz = ch->blksz * ch->blkcnt; 2495 if (ch->dmapos != NULL) 2496 ptr = *(ch->dmapos); 2497 else 2498 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2499 ch->off + HDAC_SDLPIB); 2500 ch->ptr = ptr; 2501 ptr %= sz; 2502 ptr &= ~(ch->blksz - 1); 2503 delta = (sz + ptr - ch->prevptr) % sz; 2504 2505 if (delta < ch->blksz) 2506 return (0); 2507 2508 ch->prevptr = ptr; 2509 2510 return (1); 2511} 2512 2513static void 2514hda_poll_callback(void *arg) 2515{ 2516 struct hdac_softc *sc = arg; 2517 uint32_t trigger; 2518 int i, active = 0; 2519 2520 if (sc == NULL) 2521 return; 2522 2523 hdac_lock(sc); 2524 if (sc->polling == 0) { 2525 hdac_unlock(sc); 2526 return; 2527 } 2528 2529 trigger = 0; 2530 for (i = 0; i < sc->num_chans; i++) { 2531 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2532 continue; 2533 active = 1; 2534 if (hda_poll_channel(&sc->chans[i])) 2535 trigger |= (1 << i); 2536 } 2537 2538 /* XXX */ 2539 if (active) 2540 callout_reset(&sc->poll_hda, sc->poll_ticks, 2541 hda_poll_callback, sc); 2542 2543 hdac_unlock(sc); 2544 2545 for (i = 0; i < sc->num_chans; i++) { 2546 if (trigger & (1 << i)) 2547 chn_intr(sc->chans[i].c); 2548 } 2549} 2550 2551static int 2552hdac_rirb_flush(struct hdac_softc *sc) 2553{ 2554 struct hdac_rirb *rirb_base, *rirb; 2555 struct hdac_codec *codec; 2556 struct hdac_command_list *commands; 2557 nid_t cad; 2558 uint32_t resp; 2559 uint8_t rirbwp; 2560 int ret; 2561 2562 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2563 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2564#if 0 2565 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2566 BUS_DMASYNC_POSTREAD); 2567#endif 2568 2569 ret = 0; 2570 2571 while (sc->rirb_rp != rirbwp) { 2572 sc->rirb_rp++; 2573 sc->rirb_rp %= sc->rirb_size; 2574 rirb = &rirb_base[sc->rirb_rp]; 2575 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2576 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2577 sc->codecs[cad] == NULL) 2578 continue; 2579 resp = rirb->response; 2580 codec = sc->codecs[cad]; 2581 commands = codec->commands; 2582 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2583 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2584 ((resp >> 26) & 0xffff); 2585 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2586 } else if (commands != NULL && commands->num_commands > 0 && 2587 codec->responses_received < commands->num_commands) 2588 commands->responses[codec->responses_received++] = 2589 resp; 2590 ret++; 2591 } 2592 2593 return (ret); 2594} 2595 2596static int 2597hdac_unsolq_flush(struct hdac_softc *sc) 2598{ 2599 nid_t cad; 2600 uint32_t tag; 2601 int ret = 0; 2602 2603 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2604 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2605 while (sc->unsolq_rp != sc->unsolq_wp) { 2606 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2607 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2608 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2609 hdac_unsolicited_handler(sc->codecs[cad], tag); 2610 ret++; 2611 } 2612 sc->unsolq_st = HDAC_UNSOLQ_READY; 2613 } 2614 2615 return (ret); 2616} 2617 2618static void 2619hdac_poll_callback(void *arg) 2620{ 2621 struct hdac_softc *sc = arg; 2622 if (sc == NULL) 2623 return; 2624 2625 hdac_lock(sc); 2626 if (sc->polling == 0 || sc->poll_ival == 0) { 2627 hdac_unlock(sc); 2628 return; 2629 } 2630 if (hdac_rirb_flush(sc) != 0) 2631 hdac_unsolq_flush(sc); 2632 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2633 hdac_unlock(sc); 2634} 2635 2636static void 2637hdac_poll_reinit(struct hdac_softc *sc) 2638{ 2639 int i, pollticks, min = 1000000; 2640 struct hdac_chan *ch; 2641 2642 for (i = 0; i < sc->num_chans; i++) { 2643 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2644 continue; 2645 ch = &sc->chans[i]; 2646 pollticks = ((uint64_t)hz * ch->blksz) / 2647 ((uint64_t)sndbuf_getbps(ch->b) * 2648 sndbuf_getspd(ch->b)); 2649 pollticks >>= 1; 2650 if (pollticks > hz) 2651 pollticks = hz; 2652 if (pollticks < 1) { 2653 HDA_BOOTVERBOSE( 2654 device_printf(sc->dev, 2655 "%s: pollticks=%d < 1 !\n", 2656 __func__, pollticks); 2657 ); 2658 pollticks = 1; 2659 } 2660 if (min > pollticks) 2661 min = pollticks; 2662 } 2663 HDA_BOOTVERBOSE( 2664 device_printf(sc->dev, 2665 "%s: pollticks %d -> %d\n", 2666 __func__, sc->poll_ticks, min); 2667 ); 2668 sc->poll_ticks = min; 2669 if (min == 1000000) 2670 callout_stop(&sc->poll_hda); 2671 else 2672 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2673} 2674 2675static void 2676hdac_stream_stop(struct hdac_chan *ch) 2677{ 2678 struct hdac_softc *sc = ch->devinfo->codec->sc; 2679 uint32_t ctl; 2680 2681 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2682 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2683 HDAC_SDCTL_RUN); 2684 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2685 2686 ch->flags &= ~HDAC_CHN_RUNNING; 2687 2688 if (sc->polling != 0) 2689 hdac_poll_reinit(sc); 2690 2691 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2692 ctl &= ~(1 << (ch->off >> 5)); 2693 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2694} 2695 2696static void 2697hdac_stream_start(struct hdac_chan *ch) 2698{ 2699 struct hdac_softc *sc = ch->devinfo->codec->sc; 2700 uint32_t ctl; 2701 2702 ch->flags |= HDAC_CHN_RUNNING; 2703 2704 if (sc->polling != 0) 2705 hdac_poll_reinit(sc); 2706 2707 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2708 ctl |= 1 << (ch->off >> 5); 2709 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2710 2711 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2712 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2713 HDAC_SDCTL_RUN; 2714 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2715} 2716 2717static void 2718hdac_stream_reset(struct hdac_chan *ch) 2719{ 2720 struct hdac_softc *sc = ch->devinfo->codec->sc; 2721 int timeout = 1000; 2722 int to = timeout; 2723 uint32_t ctl; 2724 2725 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2726 ctl |= HDAC_SDCTL_SRST; 2727 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2728 do { 2729 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2730 if (ctl & HDAC_SDCTL_SRST) 2731 break; 2732 DELAY(10); 2733 } while (--to); 2734 if (!(ctl & HDAC_SDCTL_SRST)) { 2735 device_printf(sc->dev, "timeout in reset\n"); 2736 } 2737 ctl &= ~HDAC_SDCTL_SRST; 2738 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2739 to = timeout; 2740 do { 2741 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2742 if (!(ctl & HDAC_SDCTL_SRST)) 2743 break; 2744 DELAY(10); 2745 } while (--to); 2746 if (ctl & HDAC_SDCTL_SRST) 2747 device_printf(sc->dev, "can't reset!\n"); 2748} 2749 2750static void 2751hdac_stream_setid(struct hdac_chan *ch) 2752{ 2753 struct hdac_softc *sc = ch->devinfo->codec->sc; 2754 uint32_t ctl; 2755 2756 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2757 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2758 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2759 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2760} 2761 2762static void 2763hdac_bdl_setup(struct hdac_chan *ch) 2764{ 2765 struct hdac_softc *sc = ch->devinfo->codec->sc; 2766 struct hdac_bdle *bdle; 2767 uint64_t addr; 2768 uint32_t blksz, blkcnt; 2769 int i; 2770 2771 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2772 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2773 2774 blksz = ch->blksz; 2775 blkcnt = ch->blkcnt; 2776 2777 for (i = 0; i < blkcnt; i++, bdle++) { 2778 bdle->addrl = (uint32_t)addr; 2779 bdle->addrh = (uint32_t)(addr >> 32); 2780 bdle->len = blksz; 2781 bdle->ioc = 1; 2782 addr += blksz; 2783 } 2784 2785 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2786 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2787 addr = ch->bdl_dma.dma_paddr; 2788 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2789 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2790 if (ch->dmapos != NULL && 2791 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2792 addr = sc->pos_dma.dma_paddr; 2793 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2794 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2795 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2796 } 2797} 2798 2799static int 2800hdac_bdl_alloc(struct hdac_chan *ch) 2801{ 2802 struct hdac_softc *sc = ch->devinfo->codec->sc; 2803 int rc; 2804 2805 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2806 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2807 if (rc) { 2808 device_printf(sc->dev, "can't alloc bdl\n"); 2809 return (rc); 2810 } 2811 2812 return (0); 2813} 2814 2815static void 2816hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2817 int index, int lmute, int rmute, 2818 int left, int right, int dir) 2819{ 2820 uint16_t v = 0; 2821 2822 if (sc == NULL) 2823 return; 2824 2825 if (left != right || lmute != rmute) { 2826 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2827 (lmute << 7) | left; 2828 hdac_command(sc, 2829 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2830 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2831 (rmute << 7) | right; 2832 } else 2833 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2834 (lmute << 7) | left; 2835 2836 hdac_command(sc, 2837 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2838} 2839 2840static void 2841hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2842 int left, int right) 2843{ 2844 struct hdac_softc *sc; 2845 nid_t nid, cad; 2846 int lmute, rmute; 2847 2848 sc = ctl->widget->devinfo->codec->sc; 2849 cad = ctl->widget->devinfo->codec->cad; 2850 nid = ctl->widget->nid; 2851 2852 /* Save new values if valid. */ 2853 if (mute != HDA_AMP_MUTE_DEFAULT) 2854 ctl->muted = mute; 2855 if (left != HDA_AMP_VOL_DEFAULT) 2856 ctl->left = left; 2857 if (right != HDA_AMP_VOL_DEFAULT) 2858 ctl->right = right; 2859 /* Prepare effective values */ 2860 if (ctl->forcemute) { 2861 lmute = 1; 2862 rmute = 1; 2863 left = 0; 2864 right = 0; 2865 } else { 2866 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2867 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2868 left = ctl->left; 2869 right = ctl->right; 2870 } 2871 /* Apply effective values */ 2872 if (ctl->dir & HDA_CTL_OUT) 2873 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2874 lmute, rmute, left, right, 0); 2875 if (ctl->dir & HDA_CTL_IN) 2876 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2877 lmute, rmute, left, right, 1); 2878} 2879 2880static void 2881hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2882{ 2883 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2884 return; 2885 hdac_command(w->devinfo->codec->sc, 2886 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2887 w->nid, index), w->devinfo->codec->cad); 2888 w->selconn = index; 2889} 2890 2891 2892/**************************************************************************** 2893 * uint32_t hdac_command_sendone_internal 2894 * 2895 * Wrapper function that sends only one command to a given codec 2896 ****************************************************************************/ 2897static uint32_t 2898hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2899{ 2900 struct hdac_command_list cl; 2901 uint32_t response = HDAC_INVALID; 2902 2903 if (!hdac_lockowned(sc)) 2904 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2905 cl.num_commands = 1; 2906 cl.verbs = &verb; 2907 cl.responses = &response; 2908 2909 hdac_command_send_internal(sc, &cl, cad); 2910 2911 return (response); 2912} 2913 2914/**************************************************************************** 2915 * hdac_command_send_internal 2916 * 2917 * Send a command list to the codec via the corb. We queue as much verbs as 2918 * we can and msleep on the codec. When the interrupt get the responses 2919 * back from the rirb, it will wake us up so we can queue the remaining verbs 2920 * if any. 2921 ****************************************************************************/ 2922static void 2923hdac_command_send_internal(struct hdac_softc *sc, 2924 struct hdac_command_list *commands, nid_t cad) 2925{ 2926 struct hdac_codec *codec; 2927 int corbrp; 2928 uint32_t *corb; 2929 int timeout; 2930 int retry = 10; 2931 struct hdac_rirb *rirb_base; 2932 2933 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2934 commands->num_commands < 1) 2935 return; 2936 2937 codec = sc->codecs[cad]; 2938 codec->commands = commands; 2939 codec->responses_received = 0; 2940 codec->verbs_sent = 0; 2941 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2942 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2943 2944 do { 2945 if (codec->verbs_sent != commands->num_commands) { 2946 /* Queue as many verbs as possible */ 2947 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2948#if 0 2949 bus_dmamap_sync(sc->corb_dma.dma_tag, 2950 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2951#endif 2952 while (codec->verbs_sent != commands->num_commands && 2953 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2954 sc->corb_wp++; 2955 sc->corb_wp %= sc->corb_size; 2956 corb[sc->corb_wp] = 2957 commands->verbs[codec->verbs_sent++]; 2958 } 2959 2960 /* Send the verbs to the codecs */ 2961#if 0 2962 bus_dmamap_sync(sc->corb_dma.dma_tag, 2963 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2964#endif 2965 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2966 } 2967 2968 timeout = 1000; 2969 while (hdac_rirb_flush(sc) == 0 && --timeout) 2970 DELAY(10); 2971 } while ((codec->verbs_sent != commands->num_commands || 2972 codec->responses_received != commands->num_commands) && --retry); 2973 2974 if (retry == 0) 2975 device_printf(sc->dev, 2976 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2977 __func__, commands->num_commands, codec->verbs_sent, 2978 codec->responses_received); 2979 2980 codec->commands = NULL; 2981 codec->responses_received = 0; 2982 codec->verbs_sent = 0; 2983 2984 hdac_unsolq_flush(sc); 2985} 2986 2987 2988/**************************************************************************** 2989 * Device Methods 2990 ****************************************************************************/ 2991 2992/**************************************************************************** 2993 * int hdac_probe(device_t) 2994 * 2995 * Probe for the presence of an hdac. If none is found, check for a generic 2996 * match using the subclass of the device. 2997 ****************************************************************************/ 2998static int 2999hdac_probe(device_t dev) 3000{ 3001 int i, result; 3002 uint32_t model; 3003 uint16_t class, subclass; 3004 char desc[64]; 3005 3006 model = (uint32_t)pci_get_device(dev) << 16; 3007 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3008 class = pci_get_class(dev); 3009 subclass = pci_get_subclass(dev); 3010 3011 bzero(desc, sizeof(desc)); 3012 result = ENXIO; 3013 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3014 if (hdac_devices[i].model == model) { 3015 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3016 result = BUS_PROBE_DEFAULT; 3017 break; 3018 } 3019 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3020 class == PCIC_MULTIMEDIA && 3021 subclass == PCIS_MULTIMEDIA_HDA) { 3022 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3023 result = BUS_PROBE_GENERIC; 3024 break; 3025 } 3026 } 3027 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3028 subclass == PCIS_MULTIMEDIA_HDA) { 3029 strlcpy(desc, "Generic", sizeof(desc)); 3030 result = BUS_PROBE_GENERIC; 3031 } 3032 if (result != ENXIO) { 3033 strlcat(desc, " High Definition Audio Controller", 3034 sizeof(desc)); 3035 device_set_desc_copy(dev, desc); 3036 } 3037 3038 return (result); 3039} 3040 3041static void * 3042hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3043 struct pcm_channel *c, int dir) 3044{ 3045 struct hdac_pcm_devinfo *pdevinfo = data; 3046 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3047 struct hdac_softc *sc = devinfo->codec->sc; 3048 struct hdac_chan *ch; 3049 int i, ord = 0, chid; 3050 3051 hdac_lock(sc); 3052 3053 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3054 ch = &sc->chans[chid]; 3055 for (i = 0; i < sc->num_chans && i < chid; i++) { 3056 if (ch->dir == sc->chans[i].dir) 3057 ord++; 3058 } 3059 if (dir == PCMDIR_PLAY) { 3060 ch->off = (sc->num_iss + ord) << 5; 3061 } else { 3062 ch->off = ord << 5; 3063 } 3064 3065 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3066 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3067 ch->pcmrates[0] = 48000; 3068 ch->pcmrates[1] = 0; 3069 } 3070 if (sc->pos_dma.dma_vaddr != NULL) 3071 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3072 (sc->streamcnt * 8)); 3073 else 3074 ch->dmapos = NULL; 3075 ch->sid = ++sc->streamcnt; 3076 ch->dir = dir; 3077 ch->b = b; 3078 ch->c = c; 3079 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3080 ch->blkcnt = pdevinfo->chan_blkcnt; 3081 hdac_unlock(sc); 3082 3083 if (hdac_bdl_alloc(ch) != 0) { 3084 ch->blkcnt = 0; 3085 return (NULL); 3086 } 3087 3088 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3089 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3090 pdevinfo->chan_size) != 0) 3091 return (NULL); 3092 3093 return (ch); 3094} 3095 3096static int 3097hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3098{ 3099 struct hdac_chan *ch = data; 3100 int i; 3101 3102 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3103 if (format == ch->caps.fmtlist[i]) { 3104 ch->fmt = format; 3105 return (0); 3106 } 3107 } 3108 3109 return (EINVAL); 3110} 3111 3112static int 3113hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3114{ 3115 struct hdac_chan *ch = data; 3116 uint32_t spd = 0, threshold; 3117 int i; 3118 3119 for (i = 0; ch->pcmrates[i] != 0; i++) { 3120 spd = ch->pcmrates[i]; 3121 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3122 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3123 if (speed < threshold) 3124 break; 3125 } 3126 3127 if (spd == 0) /* impossible */ 3128 ch->spd = 48000; 3129 else 3130 ch->spd = spd; 3131 3132 return (ch->spd); 3133} 3134 3135static void 3136hdac_stream_setup(struct hdac_chan *ch) 3137{ 3138 struct hdac_softc *sc = ch->devinfo->codec->sc; 3139 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3140 struct hdac_widget *w; 3141 int i, chn, totalchn, c; 3142 nid_t cad = ch->devinfo->codec->cad; 3143 uint16_t fmt, dfmt; 3144 3145 HDA_BOOTVERBOSE( 3146 device_printf(ch->pdevinfo->dev, 3147 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3148 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3149 ch->fmt, ch->spd); 3150 ); 3151 fmt = 0; 3152 if (ch->fmt & AFMT_S16_LE) 3153 fmt |= ch->bit16 << 4; 3154 else if (ch->fmt & AFMT_S32_LE) 3155 fmt |= ch->bit32 << 4; 3156 else 3157 fmt |= 1 << 4; 3158 3159 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3160 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3161 fmt |= hda_rate_tab[i].base; 3162 fmt |= hda_rate_tab[i].mul; 3163 fmt |= hda_rate_tab[i].div; 3164 break; 3165 } 3166 } 3167 3168 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3169 fmt |= 1; 3170 totalchn = 2; 3171 } else 3172 totalchn = 1; 3173 3174 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3175 3176 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3177 if (ch->fmt & AFMT_AC3) 3178 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3179 3180 chn = 0; 3181 for (i = 0; ch->io[i] != -1; i++) { 3182 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3183 if (w == NULL) 3184 continue; 3185 3186 if (as->hpredir >= 0 && i == as->pincnt) 3187 chn = 0; 3188 HDA_BOOTVERBOSE( 3189 device_printf(ch->pdevinfo->dev, 3190 "PCMDIR_%s: Stream setup nid=%d: " 3191 "fmt=0x%04x, dfmt=0x%04x\n", 3192 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3193 ch->io[i], fmt, dfmt); 3194 ); 3195 hdac_command(sc, 3196 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3197 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3198 hdac_command(sc, 3199 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3200 cad); 3201 } 3202 /* If HP redirection is enabled, but failed to use same 3203 DAC make last DAC one to duplicate first one. */ 3204 if (as->hpredir >= 0 && i == as->pincnt) { 3205 c = (ch->sid << 4); 3206 } else if (chn >= totalchn) { 3207 /* This is until OSS will support multichannel. 3208 Should be: c = 0; to disable unused DAC */ 3209 c = (ch->sid << 4); 3210 }else { 3211 c = (ch->sid << 4) | chn; 3212 } 3213 hdac_command(sc, 3214 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3215 chn += 3216 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3217 2 : 1; 3218 } 3219} 3220 3221static int 3222hdac_channel_setfragments(kobj_t obj, void *data, 3223 uint32_t blksz, uint32_t blkcnt) 3224{ 3225 struct hdac_chan *ch = data; 3226 struct hdac_softc *sc = ch->devinfo->codec->sc; 3227 3228 blksz &= HDA_BLK_ALIGN; 3229 3230 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3231 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3232 if (blksz < HDA_BLK_MIN) 3233 blksz = HDA_BLK_MIN; 3234 if (blkcnt > HDA_BDL_MAX) 3235 blkcnt = HDA_BDL_MAX; 3236 if (blkcnt < HDA_BDL_MIN) 3237 blkcnt = HDA_BDL_MIN; 3238 3239 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3240 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3241 blkcnt >>= 1; 3242 else if ((blksz >> 1) >= HDA_BLK_MIN) 3243 blksz >>= 1; 3244 else 3245 break; 3246 } 3247 3248 if ((sndbuf_getblksz(ch->b) != blksz || 3249 sndbuf_getblkcnt(ch->b) != blkcnt) && 3250 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3251 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3252 __func__, blksz, blkcnt); 3253 3254 ch->blksz = sndbuf_getblksz(ch->b); 3255 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3256 3257 return (1); 3258} 3259 3260static int 3261hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3262{ 3263 struct hdac_chan *ch = data; 3264 3265 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3266 3267 return (ch->blksz); 3268} 3269 3270static void 3271hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3272{ 3273 struct hdac_devinfo *devinfo = ch->devinfo; 3274 struct hdac_widget *w; 3275 nid_t cad = devinfo->codec->cad; 3276 int i; 3277 3278 hdac_stream_stop(ch); 3279 3280 for (i = 0; ch->io[i] != -1; i++) { 3281 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3282 if (w == NULL) 3283 continue; 3284 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3285 hdac_command(sc, 3286 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3287 cad); 3288 } 3289 hdac_command(sc, 3290 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3291 0), cad); 3292 } 3293} 3294 3295static void 3296hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3297{ 3298 ch->ptr = 0; 3299 ch->prevptr = 0; 3300 hdac_stream_stop(ch); 3301 hdac_stream_reset(ch); 3302 hdac_bdl_setup(ch); 3303 hdac_stream_setid(ch); 3304 hdac_stream_setup(ch); 3305 hdac_stream_start(ch); 3306} 3307 3308static int 3309hdac_channel_trigger(kobj_t obj, void *data, int go) 3310{ 3311 struct hdac_chan *ch = data; 3312 struct hdac_softc *sc = ch->devinfo->codec->sc; 3313 3314 if (!PCMTRIG_COMMON(go)) 3315 return (0); 3316 3317 hdac_lock(sc); 3318 switch (go) { 3319 case PCMTRIG_START: 3320 hdac_channel_start(sc, ch); 3321 break; 3322 case PCMTRIG_STOP: 3323 case PCMTRIG_ABORT: 3324 hdac_channel_stop(sc, ch); 3325 break; 3326 default: 3327 break; 3328 } 3329 hdac_unlock(sc); 3330 3331 return (0); 3332} 3333 3334static int 3335hdac_channel_getptr(kobj_t obj, void *data) 3336{ 3337 struct hdac_chan *ch = data; 3338 struct hdac_softc *sc = ch->devinfo->codec->sc; 3339 uint32_t ptr; 3340 3341 hdac_lock(sc); 3342 if (sc->polling != 0) 3343 ptr = ch->ptr; 3344 else if (ch->dmapos != NULL) 3345 ptr = *(ch->dmapos); 3346 else 3347 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3348 hdac_unlock(sc); 3349 3350 /* 3351 * Round to available space and force 128 bytes aligment. 3352 */ 3353 ptr %= ch->blksz * ch->blkcnt; 3354 ptr &= HDA_BLK_ALIGN; 3355 3356 return (ptr); 3357} 3358 3359static struct pcmchan_caps * 3360hdac_channel_getcaps(kobj_t obj, void *data) 3361{ 3362 return (&((struct hdac_chan *)data)->caps); 3363} 3364 3365static kobj_method_t hdac_channel_methods[] = { 3366 KOBJMETHOD(channel_init, hdac_channel_init), 3367 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3368 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3369 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3370 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3371 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3372 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3373 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3374 { 0, 0 } 3375}; 3376CHANNEL_DECLARE(hdac_channel); 3377 3378static int 3379hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3380{ 3381 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3382 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3383 struct hdac_softc *sc = devinfo->codec->sc; 3384 struct hdac_widget *w, *cw; 3385 struct hdac_audio_ctl *ctl; 3386 uint32_t mask, recmask, id; 3387 int i, j, softpcmvol; 3388 3389 hdac_lock(sc); 3390 3391 /* Make sure that in case of soft volume it won't stay muted. */ 3392 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3393 pdevinfo->left[i] = 100; 3394 pdevinfo->right[i] = 100; 3395 } 3396 3397 mask = 0; 3398 recmask = 0; 3399 id = hdac_codec_id(devinfo->codec); 3400 3401 /* Declate EAPD as ogain control. */ 3402 if (pdevinfo->play >= 0) { 3403 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3404 w = hdac_widget_get(devinfo, i); 3405 if (w == NULL || w->enable == 0) 3406 continue; 3407 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3408 w->param.eapdbtl == HDAC_INVALID || 3409 w->bindas != sc->chans[pdevinfo->play].as) 3410 continue; 3411 mask |= SOUND_MASK_OGAIN; 3412 break; 3413 } 3414 } 3415 3416 /* Declare volume controls assigned to this association. */ 3417 i = 0; 3418 ctl = NULL; 3419 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3420 if (ctl->enable == 0) 3421 continue; 3422 if ((pdevinfo->play >= 0 && 3423 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3424 (pdevinfo->rec >= 0 && 3425 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3426 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3427 mask |= ctl->ossmask; 3428 } 3429 3430 /* Declare record sources available to this association. */ 3431 if (pdevinfo->rec >= 0) { 3432 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3433 for (i = 0; ch->io[i] != -1; i++) { 3434 w = hdac_widget_get(devinfo, ch->io[i]); 3435 if (w == NULL || w->enable == 0) 3436 continue; 3437 for (j = 0; j < w->nconns; j++) { 3438 if (w->connsenable[j] == 0) 3439 continue; 3440 cw = hdac_widget_get(devinfo, w->conns[j]); 3441 if (cw == NULL || cw->enable == 0) 3442 continue; 3443 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3444 cw->bindas != -2) 3445 continue; 3446 recmask |= cw->ossmask; 3447 } 3448 } 3449 } 3450 3451 /* Declare soft PCM and master volume if needed. */ 3452 if (pdevinfo->play >= 0) { 3453 ctl = NULL; 3454 if ((mask & SOUND_MASK_PCM) == 0 || 3455 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3456 softpcmvol = 1; 3457 mask |= SOUND_MASK_PCM; 3458 } else { 3459 softpcmvol = 0; 3460 i = 0; 3461 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3462 if (ctl->enable == 0) 3463 continue; 3464 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3465 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3466 continue; 3467 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3468 continue; 3469 if (ctl->step > 0) 3470 break; 3471 } 3472 } 3473 3474 if (softpcmvol == 1 || ctl == NULL) { 3475 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3476 HDA_BOOTVERBOSE( 3477 device_printf(pdevinfo->dev, 3478 "%s Soft PCM volume\n", 3479 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3480 ); 3481 } 3482 3483 if ((mask & SOUND_MASK_VOLUME) == 0) { 3484 mask |= SOUND_MASK_VOLUME; 3485 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3486 SOUND_MASK_PCM); 3487 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3488 SOUND_MIXER_NONE); 3489 HDA_BOOTVERBOSE( 3490 device_printf(pdevinfo->dev, 3491 "Forcing master volume with PCM\n"); 3492 ); 3493 } 3494 } 3495 3496 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3497 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3498 3499 mix_setrecdevs(m, recmask); 3500 mix_setdevs(m, mask); 3501 3502 hdac_unlock(sc); 3503 3504 return (0); 3505} 3506 3507static int 3508hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3509 unsigned left, unsigned right) 3510{ 3511 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3512 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3513 struct hdac_softc *sc = devinfo->codec->sc; 3514 struct hdac_widget *w; 3515 struct hdac_audio_ctl *ctl; 3516 uint32_t mute; 3517 int lvol, rvol; 3518 int i, j; 3519 3520 hdac_lock(sc); 3521 /* Save new values. */ 3522 pdevinfo->left[dev] = left; 3523 pdevinfo->right[dev] = right; 3524 3525 /* 'ogain' is the special case implemented with EAPD. */ 3526 if (dev == SOUND_MIXER_OGAIN) { 3527 uint32_t orig; 3528 w = NULL; 3529 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3530 w = hdac_widget_get(devinfo, i); 3531 if (w == NULL || w->enable == 0) 3532 continue; 3533 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3534 w->param.eapdbtl == HDAC_INVALID) 3535 continue; 3536 break; 3537 } 3538 if (i >= devinfo->endnode) { 3539 hdac_unlock(sc); 3540 return (-1); 3541 } 3542 orig = w->param.eapdbtl; 3543 if (left == 0) 3544 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3545 else 3546 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3547 if (orig != w->param.eapdbtl) { 3548 uint32_t val; 3549 3550 val = w->param.eapdbtl; 3551 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3552 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3553 hdac_command(sc, 3554 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3555 w->nid, val), devinfo->codec->cad); 3556 } 3557 hdac_unlock(sc); 3558 return (left | (left << 8)); 3559 } 3560 3561 /* Recalculate all controls related to this OSS device. */ 3562 i = 0; 3563 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3564 if (ctl->enable == 0 || 3565 !(ctl->ossmask & (1 << dev))) 3566 continue; 3567 if (!((pdevinfo->play >= 0 && 3568 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3569 (pdevinfo->rec >= 0 && 3570 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3571 ctl->widget->bindas == -2)) 3572 continue; 3573 3574 lvol = 100; 3575 rvol = 100; 3576 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3577 if (ctl->ossmask & (1 << j)) { 3578 lvol = lvol * pdevinfo->left[j] / 100; 3579 rvol = rvol * pdevinfo->right[j] / 100; 3580 } 3581 } 3582 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3583 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3584 lvol = (lvol * ctl->step + 50) / 100; 3585 rvol = (rvol * ctl->step + 50) / 100; 3586 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3587 } 3588 hdac_unlock(sc); 3589 3590 return (left | (right << 8)); 3591} 3592 3593/* 3594 * Commutate specified record source. 3595 */ 3596static uint32_t 3597hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3598{ 3599 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3600 struct hdac_widget *w, *cw; 3601 struct hdac_audio_ctl *ctl; 3602 char buf[64]; 3603 int i, muted; 3604 uint32_t res = 0; 3605 3606 if (depth > HDA_PARSE_MAXDEPTH) 3607 return (0); 3608 3609 w = hdac_widget_get(devinfo, nid); 3610 if (w == NULL || w->enable == 0) 3611 return (0); 3612 3613 for (i = 0; i < w->nconns; i++) { 3614 if (w->connsenable[i] == 0) 3615 continue; 3616 cw = hdac_widget_get(devinfo, w->conns[i]); 3617 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3618 continue; 3619 /* Call recursively to trace signal to it's source if needed. */ 3620 if ((src & cw->ossmask) != 0) { 3621 if (cw->ossdev < 0) { 3622 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3623 w->conns[i], depth + 1); 3624 } else { 3625 res |= cw->ossmask; 3626 } 3627 } 3628 /* We have two special cases: mixers and others (selectors). */ 3629 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3630 ctl = hdac_audio_ctl_amp_get(devinfo, 3631 w->nid, HDA_CTL_IN, i, 1); 3632 if (ctl == NULL) 3633 continue; 3634 /* If we have input control on this node mute them 3635 * according to requested sources. */ 3636 muted = (src & cw->ossmask) ? 0 : 1; 3637 if (muted != ctl->forcemute) { 3638 ctl->forcemute = muted; 3639 hdac_audio_ctl_amp_set(ctl, 3640 HDA_AMP_MUTE_DEFAULT, 3641 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3642 } 3643 HDA_BOOTVERBOSE( 3644 device_printf(pdevinfo->dev, 3645 "Recsel (%s): nid %d source %d %s\n", 3646 hdac_audio_ctl_ossmixer_mask2allname( 3647 src, buf, sizeof(buf)), 3648 nid, i, muted?"mute":"unmute"); 3649 ); 3650 } else { 3651 if (w->nconns == 1) 3652 break; 3653 if ((src & cw->ossmask) == 0) 3654 continue; 3655 /* If we found requested source - select it and exit. */ 3656 hdac_widget_connection_select(w, i); 3657 HDA_BOOTVERBOSE( 3658 device_printf(pdevinfo->dev, 3659 "Recsel (%s): nid %d source %d select\n", 3660 hdac_audio_ctl_ossmixer_mask2allname( 3661 src, buf, sizeof(buf)), 3662 nid, i); 3663 ); 3664 break; 3665 } 3666 } 3667 return (res); 3668} 3669 3670static uint32_t 3671hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3672{ 3673 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3674 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3675 struct hdac_widget *w; 3676 struct hdac_softc *sc = devinfo->codec->sc; 3677 struct hdac_chan *ch; 3678 int i; 3679 uint32_t ret = 0xffffffff; 3680 3681 hdac_lock(sc); 3682 3683 /* Commutate requested recsrc for each ADC. */ 3684 ch = &sc->chans[pdevinfo->rec]; 3685 for (i = 0; ch->io[i] != -1; i++) { 3686 w = hdac_widget_get(devinfo, ch->io[i]); 3687 if (w == NULL || w->enable == 0) 3688 continue; 3689 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3690 } 3691 3692 hdac_unlock(sc); 3693 3694 return ((ret == 0xffffffff)? 0 : ret); 3695} 3696 3697static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3698 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3699 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3700 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3701 { 0, 0 } 3702}; 3703MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3704 3705static void 3706hdac_unsolq_task(void *context, int pending) 3707{ 3708 struct hdac_softc *sc; 3709 3710 sc = (struct hdac_softc *)context; 3711 3712 hdac_lock(sc); 3713 hdac_unsolq_flush(sc); 3714 hdac_unlock(sc); 3715} 3716 3717/**************************************************************************** 3718 * int hdac_attach(device_t) 3719 * 3720 * Attach the device into the kernel. Interrupts usually won't be enabled 3721 * when this function is called. Setup everything that doesn't require 3722 * interrupts and defer probing of codecs until interrupts are enabled. 3723 ****************************************************************************/ 3724static int 3725hdac_attach(device_t dev) 3726{ 3727 struct hdac_softc *sc; 3728 int result; 3729 int i; 3730 uint16_t vendor; 3731 uint8_t v; 3732 3733 device_printf(dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 3734 3735 sc = device_get_softc(dev); 3736 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3737 sc->dev = dev; 3738 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3739 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3740 vendor = pci_get_vendor(dev); 3741 3742 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3743 /* Screw nx6325 - subdevice/subvendor swapped */ 3744 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3745 } 3746 3747 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3748 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3749 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3750 3751 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3752 3753 sc->poll_ticks = 1000000; 3754 sc->poll_ival = HDAC_POLL_INTERVAL; 3755 if (resource_int_value(device_get_name(dev), 3756 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3757 sc->polling = 1; 3758 else 3759 sc->polling = 0; 3760 3761 result = bus_dma_tag_create(NULL, /* parent */ 3762 HDAC_DMA_ALIGNMENT, /* alignment */ 3763 0, /* boundary */ 3764 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3765 BUS_SPACE_MAXADDR, /* highaddr */ 3766 NULL, /* filtfunc */ 3767 NULL, /* fistfuncarg */ 3768 HDA_BUFSZ_MAX, /* maxsize */ 3769 1, /* nsegments */ 3770 HDA_BUFSZ_MAX, /* maxsegsz */ 3771 0, /* flags */ 3772 NULL, /* lockfunc */ 3773 NULL, /* lockfuncarg */ 3774 &sc->chan_dmat); /* dmat */ 3775 if (result != 0) { 3776 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3777 __func__, result); 3778 snd_mtxfree(sc->lock); 3779 free(sc, M_DEVBUF); 3780 return (ENXIO); 3781 } 3782 3783 3784 sc->hdabus = NULL; 3785 for (i = 0; i < HDAC_CODEC_MAX; i++) 3786 sc->codecs[i] = NULL; 3787 3788 pci_enable_busmaster(dev); 3789 3790 if (vendor == INTEL_VENDORID) { 3791 /* TCSEL -> TC0 */ 3792 v = pci_read_config(dev, 0x44, 1); 3793 pci_write_config(dev, 0x44, v & 0xf8, 1); 3794 HDA_BOOTVERBOSE( 3795 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3796 pci_read_config(dev, 0x44, 1)); 3797 ); 3798 } 3799 3800#ifdef HDAC_MSI_ENABLED 3801 if (resource_int_value(device_get_name(dev), 3802 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3803 pci_msi_count(dev) == 1) 3804 sc->flags |= HDAC_F_MSI; 3805 else 3806#endif 3807 sc->flags &= ~HDAC_F_MSI; 3808 3809#if defined(__i386__) || defined(__amd64__) 3810 sc->flags |= HDAC_F_DMA_NOCACHE; 3811 3812 if (resource_int_value(device_get_name(dev), 3813 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3814#else 3815 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3816#endif 3817 /* 3818 * Try to enable PCIe snoop to avoid messing around with 3819 * uncacheable DMA attribute. Since PCIe snoop register 3820 * config is pretty much vendor specific, there are no 3821 * general solutions on how to enable it, forcing us (even 3822 * Microsoft) to enable uncacheable or write combined DMA 3823 * by default. 3824 * 3825 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3826 */ 3827 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3828 if (hdac_pcie_snoop[i].vendor != vendor) 3829 continue; 3830 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3831 if (hdac_pcie_snoop[i].reg == 0x00) 3832 break; 3833 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3834 if ((v & hdac_pcie_snoop[i].enable) == 3835 hdac_pcie_snoop[i].enable) 3836 break; 3837 v &= hdac_pcie_snoop[i].mask; 3838 v |= hdac_pcie_snoop[i].enable; 3839 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3840 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3841 if ((v & hdac_pcie_snoop[i].enable) != 3842 hdac_pcie_snoop[i].enable) { 3843 HDA_BOOTVERBOSE( 3844 device_printf(dev, 3845 "WARNING: Failed to enable PCIe " 3846 "snoop!\n"); 3847 ); 3848#if defined(__i386__) || defined(__amd64__) 3849 sc->flags |= HDAC_F_DMA_NOCACHE; 3850#endif 3851 } 3852 break; 3853 } 3854#if defined(__i386__) || defined(__amd64__) 3855 } 3856#endif 3857 3858 HDA_BOOTVERBOSE( 3859 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3860 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3861 "Uncacheable" : "PCIe snoop", vendor); 3862 ); 3863 3864 /* Allocate resources */ 3865 result = hdac_mem_alloc(sc); 3866 if (result != 0) 3867 goto hdac_attach_fail; 3868 result = hdac_irq_alloc(sc); 3869 if (result != 0) 3870 goto hdac_attach_fail; 3871 3872 /* Get Capabilities */ 3873 result = hdac_get_capabilities(sc); 3874 if (result != 0) 3875 goto hdac_attach_fail; 3876 3877 /* Allocate CORB and RIRB dma memory */ 3878 result = hdac_dma_alloc(sc, &sc->corb_dma, 3879 sc->corb_size * sizeof(uint32_t)); 3880 if (result != 0) 3881 goto hdac_attach_fail; 3882 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3883 sc->rirb_size * sizeof(struct hdac_rirb)); 3884 if (result != 0) 3885 goto hdac_attach_fail; 3886 3887 /* Quiesce everything */ 3888 HDA_BOOTVERBOSE( 3889 device_printf(dev, "Reset controller...\n"); 3890 ); 3891 hdac_reset(sc, 1); 3892 3893 /* Initialize the CORB and RIRB */ 3894 hdac_corb_init(sc); 3895 hdac_rirb_init(sc); 3896 3897 /* Defer remaining of initialization until interrupts are enabled */ 3898 sc->intrhook.ich_func = hdac_attach2; 3899 sc->intrhook.ich_arg = (void *)sc; 3900 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3901 sc->intrhook.ich_func = NULL; 3902 hdac_attach2((void *)sc); 3903 } 3904 3905 return (0); 3906 3907hdac_attach_fail: 3908 hdac_irq_free(sc); 3909 hdac_dma_free(sc, &sc->rirb_dma); 3910 hdac_dma_free(sc, &sc->corb_dma); 3911 hdac_mem_free(sc); 3912 snd_mtxfree(sc->lock); 3913 free(sc, M_DEVBUF); 3914 3915 return (ENXIO); 3916} 3917 3918static void 3919hdac_audio_parse(struct hdac_devinfo *devinfo) 3920{ 3921 struct hdac_codec *codec = devinfo->codec; 3922 struct hdac_softc *sc = codec->sc; 3923 struct hdac_widget *w; 3924 uint32_t res; 3925 int i; 3926 nid_t cad, nid; 3927 3928 cad = devinfo->codec->cad; 3929 nid = devinfo->nid; 3930 3931 res = hdac_command(sc, 3932 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3933 devinfo->function.audio.gpio = res; 3934 3935 HDA_BOOTVERBOSE( 3936 device_printf(sc->dev, " GPIO: 0x%08x\n", 3937 devinfo->function.audio.gpio); 3938 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3939 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3940 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3941 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3942 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3943 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3944 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3945 ); 3946 3947 res = hdac_command(sc, 3948 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3949 cad); 3950 devinfo->function.audio.supp_stream_formats = res; 3951 3952 res = hdac_command(sc, 3953 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3954 cad); 3955 devinfo->function.audio.supp_pcm_size_rate = res; 3956 3957 res = hdac_command(sc, 3958 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3959 cad); 3960 devinfo->function.audio.outamp_cap = res; 3961 3962 res = hdac_command(sc, 3963 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3964 cad); 3965 devinfo->function.audio.inamp_cap = res; 3966 3967 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3968 w = hdac_widget_get(devinfo, i); 3969 if (w == NULL) 3970 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3971 else { 3972 w->devinfo = devinfo; 3973 w->nid = i; 3974 w->enable = 1; 3975 w->selconn = -1; 3976 w->pflags = 0; 3977 w->ossdev = -1; 3978 w->bindas = -1; 3979 w->param.eapdbtl = HDAC_INVALID; 3980 hdac_widget_parse(w); 3981 } 3982 } 3983} 3984 3985static void 3986hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3987{ 3988 struct hdac_softc *sc = devinfo->codec->sc; 3989 struct hdac_audio_ctl *ctls; 3990 struct hdac_widget *w, *cw; 3991 int i, j, cnt, max, ocap, icap; 3992 int mute, offset, step, size; 3993 3994 /* XXX This is redundant */ 3995 max = 0; 3996 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3997 w = hdac_widget_get(devinfo, i); 3998 if (w == NULL || w->enable == 0) 3999 continue; 4000 if (w->param.outamp_cap != 0) 4001 max++; 4002 if (w->param.inamp_cap != 0) { 4003 switch (w->type) { 4004 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4005 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4006 for (j = 0; j < w->nconns; j++) { 4007 cw = hdac_widget_get(devinfo, 4008 w->conns[j]); 4009 if (cw == NULL || cw->enable == 0) 4010 continue; 4011 max++; 4012 } 4013 break; 4014 default: 4015 max++; 4016 break; 4017 } 4018 } 4019 } 4020 4021 devinfo->function.audio.ctlcnt = max; 4022 4023 if (max < 1) 4024 return; 4025 4026 ctls = (struct hdac_audio_ctl *)malloc( 4027 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4028 4029 if (ctls == NULL) { 4030 /* Blekh! */ 4031 device_printf(sc->dev, "unable to allocate ctls!\n"); 4032 devinfo->function.audio.ctlcnt = 0; 4033 return; 4034 } 4035 4036 cnt = 0; 4037 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4038 if (cnt >= max) { 4039 device_printf(sc->dev, "%s: Ctl overflow!\n", 4040 __func__); 4041 break; 4042 } 4043 w = hdac_widget_get(devinfo, i); 4044 if (w == NULL || w->enable == 0) 4045 continue; 4046 ocap = w->param.outamp_cap; 4047 icap = w->param.inamp_cap; 4048 if (ocap != 0) { 4049 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4050 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4051 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4052 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4053 /*if (offset > step) { 4054 HDA_BOOTVERBOSE( 4055 device_printf(sc->dev, 4056 "BUGGY outamp: nid=%d " 4057 "[offset=%d > step=%d]\n", 4058 w->nid, offset, step); 4059 ); 4060 offset = step; 4061 }*/ 4062 ctls[cnt].enable = 1; 4063 ctls[cnt].widget = w; 4064 ctls[cnt].mute = mute; 4065 ctls[cnt].step = step; 4066 ctls[cnt].size = size; 4067 ctls[cnt].offset = offset; 4068 ctls[cnt].left = offset; 4069 ctls[cnt].right = offset; 4070 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4071 w->waspin) 4072 ctls[cnt].ndir = HDA_CTL_IN; 4073 else 4074 ctls[cnt].ndir = HDA_CTL_OUT; 4075 ctls[cnt++].dir = HDA_CTL_OUT; 4076 } 4077 4078 if (icap != 0) { 4079 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4080 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4081 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4082 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4083 /*if (offset > step) { 4084 HDA_BOOTVERBOSE( 4085 device_printf(sc->dev, 4086 "BUGGY inamp: nid=%d " 4087 "[offset=%d > step=%d]\n", 4088 w->nid, offset, step); 4089 ); 4090 offset = step; 4091 }*/ 4092 switch (w->type) { 4093 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4094 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4095 for (j = 0; j < w->nconns; j++) { 4096 if (cnt >= max) { 4097 device_printf(sc->dev, 4098 "%s: Ctl overflow!\n", 4099 __func__); 4100 break; 4101 } 4102 cw = hdac_widget_get(devinfo, 4103 w->conns[j]); 4104 if (cw == NULL || cw->enable == 0) 4105 continue; 4106 ctls[cnt].enable = 1; 4107 ctls[cnt].widget = w; 4108 ctls[cnt].childwidget = cw; 4109 ctls[cnt].index = j; 4110 ctls[cnt].mute = mute; 4111 ctls[cnt].step = step; 4112 ctls[cnt].size = size; 4113 ctls[cnt].offset = offset; 4114 ctls[cnt].left = offset; 4115 ctls[cnt].right = offset; 4116 ctls[cnt].ndir = HDA_CTL_IN; 4117 ctls[cnt++].dir = HDA_CTL_IN; 4118 } 4119 break; 4120 default: 4121 if (cnt >= max) { 4122 device_printf(sc->dev, 4123 "%s: Ctl overflow!\n", 4124 __func__); 4125 break; 4126 } 4127 ctls[cnt].enable = 1; 4128 ctls[cnt].widget = w; 4129 ctls[cnt].mute = mute; 4130 ctls[cnt].step = step; 4131 ctls[cnt].size = size; 4132 ctls[cnt].offset = offset; 4133 ctls[cnt].left = offset; 4134 ctls[cnt].right = offset; 4135 if (w->type == 4136 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4137 ctls[cnt].ndir = HDA_CTL_OUT; 4138 else 4139 ctls[cnt].ndir = HDA_CTL_IN; 4140 ctls[cnt++].dir = HDA_CTL_IN; 4141 break; 4142 } 4143 } 4144 } 4145 4146 devinfo->function.audio.ctl = ctls; 4147} 4148 4149static void 4150hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4151{ 4152 struct hdac_softc *sc = devinfo->codec->sc; 4153 struct hdac_audio_as *as; 4154 struct hdac_widget *w; 4155 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4156 4157 /* XXX This is redundant */ 4158 max = 0; 4159 for (j = 0; j < 16; j++) { 4160 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4161 w = hdac_widget_get(devinfo, i); 4162 if (w == NULL || w->enable == 0) 4163 continue; 4164 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4165 continue; 4166 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4167 != j) 4168 continue; 4169 max++; 4170 if (j != 15) /* There could be many 1-pin assocs #15 */ 4171 break; 4172 } 4173 } 4174 4175 devinfo->function.audio.ascnt = max; 4176 4177 if (max < 1) 4178 return; 4179 4180 as = (struct hdac_audio_as *)malloc( 4181 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4182 4183 if (as == NULL) { 4184 /* Blekh! */ 4185 device_printf(sc->dev, "unable to allocate assocs!\n"); 4186 devinfo->function.audio.ascnt = 0; 4187 return; 4188 } 4189 4190 for (i = 0; i < max; i++) { 4191 as[i].hpredir = -1; 4192 as[i].chan = -1; 4193 } 4194 4195 /* Scan associations skipping as=0. */ 4196 cnt = 0; 4197 for (j = 1; j < 16; j++) { 4198 first = 16; 4199 hpredir = 0; 4200 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4201 w = hdac_widget_get(devinfo, i); 4202 if (w == NULL || w->enable == 0) 4203 continue; 4204 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4205 continue; 4206 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4207 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4208 if (assoc != j) { 4209 continue; 4210 } 4211 KASSERT(cnt < max, 4212 ("%s: Associations owerflow (%d of %d)", 4213 __func__, cnt, max)); 4214 type = w->wclass.pin.config & 4215 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4216 /* Get pin direction. */ 4217 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4218 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4219 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4220 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4221 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4222 dir = HDA_CTL_OUT; 4223 else 4224 dir = HDA_CTL_IN; 4225 /* If this is a first pin - create new association. */ 4226 if (as[cnt].pincnt == 0) { 4227 as[cnt].enable = 1; 4228 as[cnt].index = j; 4229 as[cnt].dir = dir; 4230 } 4231 if (seq < first) 4232 first = seq; 4233 /* Check association correctness. */ 4234 if (as[cnt].pins[seq] != 0) { 4235 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4236 "in association %d! Disabling association.\n", 4237 __func__, seq, w->nid, j); 4238 as[cnt].enable = 0; 4239 } 4240 if (dir != as[cnt].dir) { 4241 device_printf(sc->dev, "%s: Pin %d has wrong " 4242 "direction for association %d! Disabling " 4243 "association.\n", 4244 __func__, w->nid, j); 4245 as[cnt].enable = 0; 4246 } 4247 /* Headphones with seq=15 may mean redirection. */ 4248 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4249 seq == 15) 4250 hpredir = 1; 4251 as[cnt].pins[seq] = w->nid; 4252 as[cnt].pincnt++; 4253 /* Association 15 is a multiple unassociated pins. */ 4254 if (j == 15) 4255 cnt++; 4256 } 4257 if (j != 15 && as[cnt].pincnt > 0) { 4258 if (hpredir && as[cnt].pincnt > 1) 4259 as[cnt].hpredir = first; 4260 cnt++; 4261 } 4262 } 4263 HDA_BOOTVERBOSE( 4264 device_printf(sc->dev, 4265 "%d associations found\n", max); 4266 for (i = 0; i < max; i++) { 4267 device_printf(sc->dev, 4268 "Association %d (%d) %s%s:\n", 4269 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4270 as[i].enable?"":" (disabled)"); 4271 for (j = 0; j < 16; j++) { 4272 if (as[i].pins[j] == 0) 4273 continue; 4274 device_printf(sc->dev, 4275 " Pin nid=%d seq=%d\n", 4276 as[i].pins[j], j); 4277 } 4278 } 4279 ); 4280 4281 devinfo->function.audio.as = as; 4282} 4283 4284static const struct { 4285 uint32_t model; 4286 uint32_t id; 4287 uint32_t set, unset; 4288} hdac_quirks[] = { 4289 /* 4290 * XXX Force stereo quirk. Monoural recording / playback 4291 * on few codecs (especially ALC880) seems broken or 4292 * perhaps unsupported. 4293 */ 4294 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4295 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4296 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4297 HDA_QUIRK_GPIO0, 0 }, 4298 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4299 HDA_QUIRK_GPIO0, 0 }, 4300 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4301 HDA_QUIRK_GPIO0, 0 }, 4302 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4303 HDA_QUIRK_GPIO0, 0 }, 4304 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4305 HDA_QUIRK_GPIO0, 0 }, 4306 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4307 HDA_QUIRK_GPIO0, 0 }, 4308 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4309 HDA_QUIRK_EAPDINV, 0 }, 4310 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4311 HDA_QUIRK_EAPDINV, 0 }, 4312 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4313 HDA_QUIRK_OVREF, 0 }, 4314 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4315 HDA_QUIRK_OVREF, 0 }, 4316 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4317 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4318 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4319 HDA_QUIRK_GPIO1, 0 }, 4320 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4321 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4322 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4323 HDA_QUIRK_EAPDINV, 0 }, 4324 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4325 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4326 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4327 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4328 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205, 4329 HDA_QUIRK_GPIO0, 0 }, 4330 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205, 4331 HDA_QUIRK_GPIO0, 0 }, 4332 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4333 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4334 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4335 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4336 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4337 0, HDA_QUIRK_FORCESTEREO } 4338}; 4339#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4340 4341static void 4342hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4343{ 4344 struct hdac_widget *w; 4345 uint32_t id, subvendor; 4346 int i; 4347 4348 id = hdac_codec_id(devinfo->codec); 4349 subvendor = devinfo->codec->sc->pci_subvendor; 4350 4351 /* 4352 * Quirks 4353 */ 4354 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4355 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4356 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4357 continue; 4358 if (hdac_quirks[i].set != 0) 4359 devinfo->function.audio.quirks |= 4360 hdac_quirks[i].set; 4361 if (hdac_quirks[i].unset != 0) 4362 devinfo->function.audio.quirks &= 4363 ~(hdac_quirks[i].unset); 4364 } 4365 4366 switch (id) { 4367 case HDA_CODEC_ALC883: 4368 /* 4369 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4370 * Clear vref cap for jack connectivity. 4371 */ 4372 w = hdac_widget_get(devinfo, 24); 4373 if (w != NULL && w->enable != 0 && w->type == 4374 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4375 (w->wclass.pin.config & 4376 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4377 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4378 w->wclass.pin.cap &= ~( 4379 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4380 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4381 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4382 w = hdac_widget_get(devinfo, 25); 4383 if (w != NULL && w->enable != 0 && w->type == 4384 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4385 (w->wclass.pin.config & 4386 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4387 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4388 w->wclass.pin.cap &= ~( 4389 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4390 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4391 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4392 /* 4393 * nid: 26 = Line-in, leave it alone. 4394 */ 4395 break; 4396 case HDA_CODEC_AD1986A: 4397 if (subvendor == ASUS_A8X_SUBVENDOR) { 4398 /* 4399 * This is just plain ridiculous.. There 4400 * are several A8 series that share the same 4401 * pci id but works differently (EAPD). 4402 */ 4403 w = hdac_widget_get(devinfo, 26); 4404 if (w != NULL && w->type == 4405 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4406 (w->wclass.pin.config & 4407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4408 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4409 devinfo->function.audio.quirks &= 4410 ~HDA_QUIRK_EAPDINV; 4411 } 4412 break; 4413 } 4414} 4415 4416/* 4417 * Trace path from DAC to pin. 4418 */ 4419static nid_t 4420hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4421 int dupseq, int min, int only, int depth) 4422{ 4423 struct hdac_widget *w; 4424 int i, im = -1; 4425 nid_t m = 0, ret; 4426 4427 if (depth > HDA_PARSE_MAXDEPTH) 4428 return (0); 4429 w = hdac_widget_get(devinfo, nid); 4430 if (w == NULL || w->enable == 0) 4431 return (0); 4432 HDA_BOOTVERBOSE( 4433 if (!only) { 4434 device_printf(devinfo->codec->sc->dev, 4435 " %*stracing via nid %d\n", 4436 depth + 1, "", w->nid); 4437 } 4438 ); 4439 /* Use only unused widgets */ 4440 if (w->bindas >= 0 && w->bindas != as) { 4441 HDA_BOOTVERBOSE( 4442 if (!only) { 4443 device_printf(devinfo->codec->sc->dev, 4444 " %*snid %d busy by association %d\n", 4445 depth + 1, "", w->nid, w->bindas); 4446 } 4447 ); 4448 return (0); 4449 } 4450 if (dupseq < 0) { 4451 if (w->bindseqmask != 0) { 4452 HDA_BOOTVERBOSE( 4453 if (!only) { 4454 device_printf(devinfo->codec->sc->dev, 4455 " %*snid %d busy by seqmask %x\n", 4456 depth + 1, "", w->nid, w->bindseqmask); 4457 } 4458 ); 4459 return (0); 4460 } 4461 } else { 4462 /* If this is headphones - allow duplicate first pin. */ 4463 if (w->bindseqmask != 0 && 4464 (w->bindseqmask & (1 << dupseq)) == 0) { 4465 HDA_BOOTVERBOSE( 4466 device_printf(devinfo->codec->sc->dev, 4467 " %*snid %d busy by seqmask %x\n", 4468 depth + 1, "", w->nid, w->bindseqmask); 4469 ); 4470 return (0); 4471 } 4472 } 4473 4474 switch (w->type) { 4475 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4476 /* Do not traverse input. AD1988 has digital monitor 4477 for which we are not ready. */ 4478 break; 4479 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4480 /* If we are tracing HP take only dac of first pin. */ 4481 if ((only == 0 || only == w->nid) && 4482 (w->nid >= min) && (dupseq < 0 || w->nid == 4483 devinfo->function.audio.as[as].dacs[dupseq])) 4484 m = w->nid; 4485 break; 4486 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4487 if (depth > 0) 4488 break; 4489 /* Fall */ 4490 default: 4491 /* Find reachable DACs with smallest nid respecting constraints. */ 4492 for (i = 0; i < w->nconns; i++) { 4493 if (w->connsenable[i] == 0) 4494 continue; 4495 if (w->selconn != -1 && w->selconn != i) 4496 continue; 4497 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4498 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4499 if (m == 0 || ret < m) { 4500 m = ret; 4501 im = i; 4502 } 4503 if (only || dupseq >= 0) 4504 break; 4505 } 4506 } 4507 if (m && only && ((w->nconns > 1 && 4508 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4509 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4510 w->selconn = im; 4511 break; 4512 } 4513 if (m && only) { 4514 w->bindas = as; 4515 w->bindseqmask |= (1 << seq); 4516 } 4517 HDA_BOOTVERBOSE( 4518 if (!only) { 4519 device_printf(devinfo->codec->sc->dev, 4520 " %*snid %d returned %d\n", 4521 depth + 1, "", w->nid, m); 4522 } 4523 ); 4524 return (m); 4525} 4526 4527/* 4528 * Trace path from widget to ADC. 4529 */ 4530static nid_t 4531hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4532 int only, int depth) 4533{ 4534 struct hdac_widget *w, *wc; 4535 int i, j; 4536 nid_t res = 0; 4537 4538 if (depth > HDA_PARSE_MAXDEPTH) 4539 return (0); 4540 w = hdac_widget_get(devinfo, nid); 4541 if (w == NULL || w->enable == 0) 4542 return (0); 4543 HDA_BOOTVERBOSE( 4544 device_printf(devinfo->codec->sc->dev, 4545 " %*stracing via nid %d\n", 4546 depth + 1, "", w->nid); 4547 ); 4548 /* Use only unused widgets */ 4549 if (w->bindas >= 0 && w->bindas != as) { 4550 HDA_BOOTVERBOSE( 4551 device_printf(devinfo->codec->sc->dev, 4552 " %*snid %d busy by association %d\n", 4553 depth + 1, "", w->nid, w->bindas); 4554 ); 4555 return (0); 4556 } 4557 4558 switch (w->type) { 4559 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4560 /* If we are tracing HP take only dac of first pin. */ 4561 if (only == w->nid) 4562 res = 1; 4563 break; 4564 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4565 if (depth > 0) 4566 break; 4567 /* Fall */ 4568 default: 4569 /* Try to find reachable ADCs with specified nid. */ 4570 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4571 wc = hdac_widget_get(devinfo, j); 4572 if (wc == NULL || wc->enable == 0) 4573 continue; 4574 for (i = 0; i < wc->nconns; i++) { 4575 if (wc->connsenable[i] == 0) 4576 continue; 4577 if (wc->conns[i] != nid) 4578 continue; 4579 if (hdac_audio_trace_adc(devinfo, as, seq, 4580 j, only, depth + 1) != 0) { 4581 res = 1; 4582 if (((wc->nconns > 1 && 4583 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4584 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4585 wc->selconn == -1) 4586 wc->selconn = i; 4587 } 4588 } 4589 } 4590 break; 4591 } 4592 if (res) { 4593 w->bindas = as; 4594 w->bindseqmask |= (1 << seq); 4595 } 4596 HDA_BOOTVERBOSE( 4597 device_printf(devinfo->codec->sc->dev, 4598 " %*snid %d returned %d\n", 4599 depth + 1, "", w->nid, res); 4600 ); 4601 return (res); 4602} 4603 4604/* 4605 * Erase trace path of the specified association. 4606 */ 4607static void 4608hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4609{ 4610 struct hdac_widget *w; 4611 int i; 4612 4613 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4614 w = hdac_widget_get(devinfo, i); 4615 if (w == NULL || w->enable == 0) 4616 continue; 4617 if (w->bindas == as) { 4618 if (seq >= 0) { 4619 w->bindseqmask &= ~(1 << seq); 4620 if (w->bindseqmask == 0) { 4621 w->bindas = -1; 4622 w->selconn = -1; 4623 } 4624 } else { 4625 w->bindas = -1; 4626 w->bindseqmask = 0; 4627 w->selconn = -1; 4628 } 4629 } 4630 } 4631} 4632 4633/* 4634 * Trace association path from DAC to output 4635 */ 4636static int 4637hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4638{ 4639 struct hdac_audio_as *ases = devinfo->function.audio.as; 4640 int i, hpredir; 4641 nid_t min, res; 4642 4643 /* Find next pin */ 4644 for (i = seq; ases[as].pins[i] == 0 && i < 16; i++) 4645 ; 4646 /* Check if there is no any left. If so - we succeded. */ 4647 if (i == 16) 4648 return (1); 4649 4650 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4651 min = 0; 4652 res = 0; 4653 do { 4654 HDA_BOOTVERBOSE( 4655 device_printf(devinfo->codec->sc->dev, 4656 " Tracing pin %d with min nid %d", 4657 ases[as].pins[i], min); 4658 if (hpredir >= 0) 4659 printf(" and hpredir %d\n", hpredir); 4660 else 4661 printf("\n"); 4662 ); 4663 /* Trace this pin taking min nid into account. */ 4664 res = hdac_audio_trace_dac(devinfo, as, i, 4665 ases[as].pins[i], hpredir, min, 0, 0); 4666 if (res == 0) { 4667 /* If we failed - return to previous and redo it. */ 4668 HDA_BOOTVERBOSE( 4669 device_printf(devinfo->codec->sc->dev, 4670 " Unable to trace pin %d seq %d with min " 4671 "nid %d hpredir %d\n", 4672 ases[as].pins[i], i, min, hpredir); 4673 ); 4674 return (0); 4675 } 4676 HDA_BOOTVERBOSE( 4677 device_printf(devinfo->codec->sc->dev, 4678 " Pin %d traced to DAC %d%s\n", 4679 ases[as].pins[i], res, 4680 ases[as].fakeredir?" with fake redirection":""); 4681 ); 4682 /* Trace again to mark the path */ 4683 hdac_audio_trace_dac(devinfo, as, i, 4684 ases[as].pins[i], hpredir, min, res, 0); 4685 ases[as].dacs[i] = res; 4686 /* We succeded, so call next. */ 4687 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4688 return (1); 4689 /* If next failed, we should retry with next min */ 4690 hdac_audio_undo_trace(devinfo, as, i); 4691 ases[as].dacs[i] = 0; 4692 min = res + 1; 4693 } while (1); 4694} 4695 4696/* 4697 * Trace association path from input to ADC 4698 */ 4699static int 4700hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 4701{ 4702 struct hdac_audio_as *ases = devinfo->function.audio.as; 4703 struct hdac_widget *w; 4704 int i, j, k; 4705 4706 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4707 w = hdac_widget_get(devinfo, j); 4708 if (w == NULL || w->enable == 0) 4709 continue; 4710 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4711 continue; 4712 if (w->bindas >= 0 && w->bindas != as) 4713 continue; 4714 4715 /* Find next pin */ 4716 for (i = 0; i < 16; i++) { 4717 if (ases[as].pins[i] == 0) 4718 continue; 4719 4720 HDA_BOOTVERBOSE( 4721 device_printf(devinfo->codec->sc->dev, 4722 " Tracing pin %d to ADC %d\n", 4723 ases[as].pins[i], j); 4724 ); 4725 /* Trace this pin taking goal into account. */ 4726 if (hdac_audio_trace_adc(devinfo, as, i, 4727 ases[as].pins[i], j, 0) == 0) { 4728 /* If we failed - return to previous and redo it. */ 4729 HDA_BOOTVERBOSE( 4730 device_printf(devinfo->codec->sc->dev, 4731 " Unable to trace pin %d to ADC %d\n", 4732 ases[as].pins[i], j); 4733 ); 4734 hdac_audio_undo_trace(devinfo, as, -1); 4735 for (k = 0; k < 16; k++) 4736 ases[as].dacs[k] = 0; 4737 break; 4738 } 4739 HDA_BOOTVERBOSE( 4740 device_printf(devinfo->codec->sc->dev, 4741 " Traced to ADC %d\n", 4742 j); 4743 ); 4744 ases[as].dacs[i] = j; 4745 } 4746 if (i == 16) 4747 return (1); 4748 } 4749 return (0); 4750} 4751 4752/* 4753 * Trace input monitor path from mixer to output association. 4754 */ 4755static nid_t 4756hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4757{ 4758 struct hdac_audio_as *ases = devinfo->function.audio.as; 4759 struct hdac_widget *w, *wc; 4760 int i, j; 4761 nid_t res = 0; 4762 4763 if (depth > HDA_PARSE_MAXDEPTH) 4764 return (0); 4765 w = hdac_widget_get(devinfo, nid); 4766 if (w == NULL || w->enable == 0) 4767 return (0); 4768 HDA_BOOTVERBOSE( 4769 device_printf(devinfo->codec->sc->dev, 4770 " %*stracing via nid %d\n", 4771 depth + 1, "", w->nid); 4772 ); 4773 /* Use only unused widgets */ 4774 if (depth > 0 && w->bindas != -1) { 4775 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 4776 HDA_BOOTVERBOSE( 4777 device_printf(devinfo->codec->sc->dev, 4778 " %*snid %d found output association %d\n", 4779 depth + 1, "", w->nid, w->bindas); 4780 ); 4781 return (1); 4782 } else { 4783 HDA_BOOTVERBOSE( 4784 device_printf(devinfo->codec->sc->dev, 4785 " %*snid %d busy by input association %d\n", 4786 depth + 1, "", w->nid, w->bindas); 4787 ); 4788 return (0); 4789 } 4790 } 4791 4792 switch (w->type) { 4793 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4794 /* Do not traverse input. AD1988 has digital monitor 4795 for which we are not ready. */ 4796 break; 4797 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4798 if (depth > 0) 4799 break; 4800 /* Fall */ 4801 default: 4802 /* Try to find reachable ADCs with specified nid. */ 4803 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4804 wc = hdac_widget_get(devinfo, j); 4805 if (wc == NULL || wc->enable == 0) 4806 continue; 4807 for (i = 0; i < wc->nconns; i++) { 4808 if (wc->connsenable[i] == 0) 4809 continue; 4810 if (wc->conns[i] != nid) 4811 continue; 4812 if (hdac_audio_trace_to_out(devinfo, 4813 j, depth + 1) != 0) { 4814 res = 1; 4815 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4816 wc->selconn == -1) 4817 wc->selconn = i; 4818 } 4819 } 4820 } 4821 break; 4822 } 4823 if (res) 4824 w->bindas = -2; 4825 4826 HDA_BOOTVERBOSE( 4827 device_printf(devinfo->codec->sc->dev, 4828 " %*snid %d returned %d\n", 4829 depth + 1, "", w->nid, res); 4830 ); 4831 return (res); 4832} 4833 4834/* 4835 * Trace extra associations (beeper, monitor) 4836 */ 4837static void 4838hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 4839{ 4840 struct hdac_audio_as *as = devinfo->function.audio.as; 4841 struct hdac_widget *w; 4842 int j; 4843 4844 /* Input monitor */ 4845 /* Find mixer associated with input, but supplying signal 4846 for output associations. Hope it will be input monitor. */ 4847 HDA_BOOTVERBOSE( 4848 device_printf(devinfo->codec->sc->dev, 4849 "Tracing input monitor\n"); 4850 ); 4851 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4852 w = hdac_widget_get(devinfo, j); 4853 if (w == NULL || w->enable == 0) 4854 continue; 4855 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4856 continue; 4857 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 4858 continue; 4859 HDA_BOOTVERBOSE( 4860 device_printf(devinfo->codec->sc->dev, 4861 " Tracing nid %d to out\n", 4862 j); 4863 ); 4864 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 4865 HDA_BOOTVERBOSE( 4866 device_printf(devinfo->codec->sc->dev, 4867 " nid %d is input monitor\n", 4868 w->nid); 4869 ); 4870 w->pflags |= HDA_ADC_MONITOR; 4871 w->ossdev = SOUND_MIXER_IMIX; 4872 } 4873 } 4874 4875 /* Beeper */ 4876 HDA_BOOTVERBOSE( 4877 device_printf(devinfo->codec->sc->dev, 4878 "Tracing beeper\n"); 4879 ); 4880 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4881 w = hdac_widget_get(devinfo, j); 4882 if (w == NULL || w->enable == 0) 4883 continue; 4884 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 4885 continue; 4886 HDA_BOOTVERBOSE( 4887 device_printf(devinfo->codec->sc->dev, 4888 " Tracing nid %d to out\n", 4889 j); 4890 ); 4891 hdac_audio_trace_to_out(devinfo, w->nid, 0); 4892 w->bindas = -2; 4893 } 4894} 4895 4896/* 4897 * Bind assotiations to PCM channels 4898 */ 4899static void 4900hdac_audio_bind_as(struct hdac_devinfo *devinfo) 4901{ 4902 struct hdac_softc *sc = devinfo->codec->sc; 4903 struct hdac_audio_as *as = devinfo->function.audio.as; 4904 int j, cnt = 0, free; 4905 4906 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 4907 if (as[j].enable) 4908 cnt++; 4909 } 4910 if (sc->num_chans == 0) { 4911 sc->chans = (struct hdac_chan *)malloc( 4912 sizeof(struct hdac_chan) * cnt, 4913 M_HDAC, M_ZERO | M_NOWAIT); 4914 if (sc->chans == NULL) { 4915 device_printf(devinfo->codec->sc->dev, 4916 "Channels memory allocation failed!\n"); 4917 return; 4918 } 4919 } else { 4920 sc->chans = (struct hdac_chan *)realloc(sc->chans, 4921 sizeof(struct hdac_chan) * cnt, 4922 M_HDAC, M_ZERO | M_NOWAIT); 4923 if (sc->chans == NULL) { 4924 sc->num_chans = 0; 4925 device_printf(devinfo->codec->sc->dev, 4926 "Channels memory allocation failed!\n"); 4927 return; 4928 } 4929 } 4930 free = sc->num_chans; 4931 sc->num_chans += cnt; 4932 4933 for (j = free; j < free + cnt; j++) { 4934 devinfo->codec->sc->chans[j].devinfo = devinfo; 4935 devinfo->codec->sc->chans[j].as = -1; 4936 } 4937 4938 /* Assign associations in order of their numbers, */ 4939 free = 0; 4940 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 4941 if (as[j].enable == 0) 4942 continue; 4943 4944 as[j].chan = free; 4945 devinfo->codec->sc->chans[free].as = j; 4946 if (as[j].dir == HDA_CTL_IN) { 4947 devinfo->codec->sc->chans[free].dir = PCMDIR_REC; 4948 devinfo->function.audio.reccnt++; 4949 } else { 4950 devinfo->codec->sc->chans[free].dir = PCMDIR_PLAY; 4951 devinfo->function.audio.playcnt++; 4952 } 4953 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 4954 free++; 4955 } 4956} 4957 4958static void 4959hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 4960{ 4961 struct hdac_widget *w; 4962 int i; 4963 4964 /* Disable power and volume widgets. */ 4965 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4966 w = hdac_widget_get(devinfo, i); 4967 if (w == NULL || w->enable == 0) 4968 continue; 4969 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 4970 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 4971 w->enable = 0; 4972 HDA_BOOTVERBOSE( 4973 device_printf(devinfo->codec->sc->dev, 4974 " Disabling nid %d due to it's" 4975 " non-audio type.\n", 4976 w->nid); 4977 ); 4978 } 4979 } 4980} 4981 4982static void 4983hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 4984{ 4985 struct hdac_widget *w, *cw; 4986 struct hdac_audio_ctl *ctl; 4987 int done, found, i, j, k; 4988 4989 /* Disable useless pins. */ 4990 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4991 w = hdac_widget_get(devinfo, i); 4992 if (w == NULL || w->enable == 0) 4993 continue; 4994 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4995 (w->wclass.pin.config & 4996 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4997 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 4998 w->enable = 0; 4999 HDA_BOOTVERBOSE( 5000 device_printf(devinfo->codec->sc->dev, 5001 " Disabling pin nid %d due" 5002 " to None connectivity.\n", 5003 w->nid); 5004 ); 5005 } 5006 } 5007 do { 5008 done = 1; 5009 /* Disable and mute controls for disabled widgets. */ 5010 i = 0; 5011 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5012 if (ctl->enable == 0) 5013 continue; 5014 if (ctl->widget->enable == 0 || 5015 (ctl->childwidget != NULL && 5016 ctl->childwidget->enable == 0)) { 5017 ctl->forcemute = 1; 5018 ctl->muted = HDA_AMP_MUTE_ALL; 5019 ctl->left = 0; 5020 ctl->right = 0; 5021 ctl->enable = 0; 5022 if (ctl->ndir == HDA_CTL_IN) 5023 ctl->widget->connsenable[ctl->index] = 0; 5024 done = 0; 5025 HDA_BOOTVERBOSE( 5026 device_printf(devinfo->codec->sc->dev, 5027 " Disabling ctl %d nid %d cnid %d due" 5028 " to disabled widget.\n", i, 5029 ctl->widget->nid, 5030 (ctl->childwidget != NULL)? 5031 ctl->childwidget->nid:-1); 5032 ); 5033 } 5034 } 5035 /* Disable useless widgets. */ 5036 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5037 w = hdac_widget_get(devinfo, i); 5038 if (w == NULL || w->enable == 0) 5039 continue; 5040 /* Disable inputs with disabled child widgets. */ 5041 for (j = 0; j < w->nconns; j++) { 5042 if (w->connsenable[j]) { 5043 cw = hdac_widget_get(devinfo, w->conns[j]); 5044 if (cw == NULL || cw->enable == 0) { 5045 w->connsenable[j] = 0; 5046 HDA_BOOTVERBOSE( 5047 device_printf(devinfo->codec->sc->dev, 5048 " Disabling nid %d connection %d due" 5049 " to disabled child widget.\n", 5050 i, j); 5051 ); 5052 } 5053 } 5054 } 5055 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5056 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5057 continue; 5058 /* Disable mixers and selectors without inputs. */ 5059 found = 0; 5060 for (j = 0; j < w->nconns; j++) { 5061 if (w->connsenable[j]) { 5062 found = 1; 5063 break; 5064 } 5065 } 5066 if (found == 0) { 5067 w->enable = 0; 5068 done = 0; 5069 HDA_BOOTVERBOSE( 5070 device_printf(devinfo->codec->sc->dev, 5071 " Disabling nid %d due to all it's" 5072 " inputs disabled.\n", w->nid); 5073 ); 5074 } 5075 /* Disable nodes without consumers. */ 5076 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5077 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5078 continue; 5079 found = 0; 5080 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5081 cw = hdac_widget_get(devinfo, k); 5082 if (cw == NULL || cw->enable == 0) 5083 continue; 5084 for (j = 0; j < cw->nconns; j++) { 5085 if (cw->connsenable[j] && cw->conns[j] == i) { 5086 found = 1; 5087 break; 5088 } 5089 } 5090 } 5091 if (found == 0) { 5092 w->enable = 0; 5093 done = 0; 5094 HDA_BOOTVERBOSE( 5095 device_printf(devinfo->codec->sc->dev, 5096 " Disabling nid %d due to all it's" 5097 " consumers disabled.\n", w->nid); 5098 ); 5099 } 5100 } 5101 } while (done == 0); 5102 5103} 5104 5105static void 5106hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5107{ 5108 struct hdac_audio_as *as = devinfo->function.audio.as; 5109 struct hdac_widget *w, *cw; 5110 struct hdac_audio_ctl *ctl; 5111 int i, j, k; 5112 5113 /* Disable unassosiated widgets. */ 5114 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5115 w = hdac_widget_get(devinfo, i); 5116 if (w == NULL || w->enable == 0) 5117 continue; 5118 if (w->bindas == -1) { 5119 w->enable = 0; 5120 HDA_BOOTVERBOSE( 5121 device_printf(devinfo->codec->sc->dev, 5122 " Disabling unassociated nid %d.\n", 5123 w->nid); 5124 ); 5125 } 5126 } 5127 /* Disable input connections on input pin and 5128 * output on output. */ 5129 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5130 w = hdac_widget_get(devinfo, i); 5131 if (w == NULL || w->enable == 0) 5132 continue; 5133 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5134 continue; 5135 if (w->bindas < 0) 5136 continue; 5137 if (as[w->bindas].dir == HDA_CTL_IN) { 5138 for (j = 0; j < w->nconns; j++) { 5139 if (w->connsenable[j] == 0) 5140 continue; 5141 w->connsenable[j] = 0; 5142 HDA_BOOTVERBOSE( 5143 device_printf(devinfo->codec->sc->dev, 5144 " Disabling connection to input pin " 5145 "nid %d conn %d.\n", 5146 i, j); 5147 ); 5148 } 5149 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5150 HDA_CTL_IN, -1, 1); 5151 if (ctl && ctl->enable) { 5152 ctl->forcemute = 1; 5153 ctl->muted = HDA_AMP_MUTE_ALL; 5154 ctl->left = 0; 5155 ctl->right = 0; 5156 ctl->enable = 0; 5157 } 5158 } else { 5159 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5160 HDA_CTL_OUT, -1, 1); 5161 if (ctl && ctl->enable) { 5162 ctl->forcemute = 1; 5163 ctl->muted = HDA_AMP_MUTE_ALL; 5164 ctl->left = 0; 5165 ctl->right = 0; 5166 ctl->enable = 0; 5167 } 5168 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5169 cw = hdac_widget_get(devinfo, k); 5170 if (cw == NULL || cw->enable == 0) 5171 continue; 5172 for (j = 0; j < cw->nconns; j++) { 5173 if (cw->connsenable[j] && cw->conns[j] == i) { 5174 cw->connsenable[j] = 0; 5175 HDA_BOOTVERBOSE( 5176 device_printf(devinfo->codec->sc->dev, 5177 " Disabling connection from output pin " 5178 "nid %d conn %d cnid %d.\n", 5179 k, j, i); 5180 ); 5181 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5182 cw->nconns > 1) 5183 continue; 5184 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5185 HDA_CTL_IN, j, 1); 5186 if (ctl && ctl->enable) { 5187 ctl->forcemute = 1; 5188 ctl->muted = HDA_AMP_MUTE_ALL; 5189 ctl->left = 0; 5190 ctl->right = 0; 5191 ctl->enable = 0; 5192 } 5193 } 5194 } 5195 } 5196 } 5197 } 5198} 5199 5200static void 5201hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5202{ 5203 struct hdac_audio_as *as = devinfo->function.audio.as; 5204 struct hdac_widget *w; 5205 int i, j; 5206 5207 /* On playback path we can safely disable all unseleted inputs. */ 5208 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5209 w = hdac_widget_get(devinfo, i); 5210 if (w == NULL || w->enable == 0) 5211 continue; 5212 if (w->nconns <= 1) 5213 continue; 5214 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5215 continue; 5216 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5217 continue; 5218 for (j = 0; j < w->nconns; j++) { 5219 if (w->connsenable[j] == 0) 5220 continue; 5221 if (w->selconn < 0 || w->selconn == j) 5222 continue; 5223 w->connsenable[j] = 0; 5224 HDA_BOOTVERBOSE( 5225 device_printf(devinfo->codec->sc->dev, 5226 " Disabling unselected connection " 5227 "nid %d conn %d.\n", 5228 i, j); 5229 ); 5230 } 5231 } 5232} 5233 5234static void 5235hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5236{ 5237 struct hdac_widget *w, *cw; 5238 struct hdac_audio_ctl *ctl; 5239 int i, j; 5240 5241 /* Disable crossassociatement connections. */ 5242 /* ... using selectors */ 5243 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5244 w = hdac_widget_get(devinfo, i); 5245 if (w == NULL || w->enable == 0) 5246 continue; 5247 if (w->nconns <= 1) 5248 continue; 5249 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5250 continue; 5251 if (w->bindas == -2) 5252 continue; 5253 for (j = 0; j < w->nconns; j++) { 5254 if (w->connsenable[j] == 0) 5255 continue; 5256 cw = hdac_widget_get(devinfo, w->conns[j]); 5257 if (cw == NULL || w->enable == 0) 5258 continue; 5259 if (w->bindas == cw->bindas || cw->bindas == -2) 5260 continue; 5261 w->connsenable[j] = 0; 5262 HDA_BOOTVERBOSE( 5263 device_printf(devinfo->codec->sc->dev, 5264 " Disabling crossassociatement connection " 5265 "nid %d conn %d cnid %d.\n", 5266 i, j, cw->nid); 5267 ); 5268 } 5269 } 5270 /* ... using controls */ 5271 i = 0; 5272 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5273 if (ctl->enable == 0 || ctl->childwidget == NULL) 5274 continue; 5275 if (ctl->widget->bindas == -2 || 5276 ctl->childwidget->bindas == -2) 5277 continue; 5278 if (ctl->widget->bindas != ctl->childwidget->bindas) { 5279 ctl->forcemute = 1; 5280 ctl->muted = HDA_AMP_MUTE_ALL; 5281 ctl->left = 0; 5282 ctl->right = 0; 5283 ctl->enable = 0; 5284 if (ctl->ndir == HDA_CTL_IN) 5285 ctl->widget->connsenable[ctl->index] = 0; 5286 HDA_BOOTVERBOSE( 5287 device_printf(devinfo->codec->sc->dev, 5288 " Disabling crossassociatement connection " 5289 "ctl %d nid %d cnid %d.\n", i, 5290 ctl->widget->nid, 5291 ctl->childwidget->nid); 5292 ); 5293 } 5294 } 5295 5296} 5297 5298#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5299 5300/* 5301 * Find controls to control amplification for source. 5302 */ 5303static int 5304hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5305 int ossdev, int ctlable, int depth, int need) 5306{ 5307 struct hdac_widget *w, *wc; 5308 struct hdac_audio_ctl *ctl; 5309 int i, j, conns = 0, rneed; 5310 5311 if (depth > HDA_PARSE_MAXDEPTH) 5312 return (need); 5313 5314 w = hdac_widget_get(devinfo, nid); 5315 if (w == NULL || w->enable == 0) 5316 return (need); 5317 5318 /* Count number of active inputs. */ 5319 if (depth > 0) { 5320 for (j = 0; j < w->nconns; j++) { 5321 if (w->connsenable[j]) 5322 conns++; 5323 } 5324 } 5325 5326 /* If this is not a first step - use input mixer. 5327 Pins have common input ctl so care must be taken. */ 5328 if (depth > 0 && ctlable && (conns == 1 || 5329 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5330 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5331 index, 1); 5332 if (ctl) { 5333 if (HDA_CTL_GIVE(ctl) & need) 5334 ctl->ossmask |= (1 << ossdev); 5335 else 5336 ctl->possmask |= (1 << ossdev); 5337 need &= ~HDA_CTL_GIVE(ctl); 5338 } 5339 } 5340 5341 /* If widget has own ossdev - not traverse it. 5342 It will be traversed on it's own. */ 5343 if (w->ossdev >= 0 && depth > 0) 5344 return (need); 5345 5346 /* We must not traverse pin */ 5347 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5348 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5349 depth > 0) 5350 return (need); 5351 5352 /* record that this widget exports such signal, */ 5353 w->ossmask |= (1 << ossdev); 5354 5355 /* If signals mixed, we can't assign controls farther. 5356 * Ignore this on depth zero. Caller must knows why. 5357 * Ignore this for static selectors if this input selected. 5358 */ 5359 if (conns > 1) 5360 ctlable = 0; 5361 5362 if (ctlable) { 5363 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5364 if (ctl) { 5365 if (HDA_CTL_GIVE(ctl) & need) 5366 ctl->ossmask |= (1 << ossdev); 5367 else 5368 ctl->possmask |= (1 << ossdev); 5369 need &= ~HDA_CTL_GIVE(ctl); 5370 } 5371 } 5372 5373 rneed = 0; 5374 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5375 wc = hdac_widget_get(devinfo, i); 5376 if (wc == NULL || wc->enable == 0) 5377 continue; 5378 for (j = 0; j < wc->nconns; j++) { 5379 if (wc->connsenable[j] && wc->conns[j] == nid) { 5380 rneed |= hdac_audio_ctl_source_amp(devinfo, 5381 wc->nid, j, ossdev, ctlable, depth + 1, need); 5382 } 5383 } 5384 } 5385 rneed &= need; 5386 5387 return (rneed); 5388} 5389 5390/* 5391 * Find controls to control amplification for destination. 5392 */ 5393static void 5394hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5395 int ossdev, int depth, int need) 5396{ 5397 struct hdac_audio_as *as = devinfo->function.audio.as; 5398 struct hdac_widget *w, *wc; 5399 struct hdac_audio_ctl *ctl; 5400 int i, j, consumers; 5401 5402 if (depth > HDA_PARSE_MAXDEPTH) 5403 return; 5404 5405 w = hdac_widget_get(devinfo, nid); 5406 if (w == NULL || w->enable == 0) 5407 return; 5408 5409 if (depth > 0) { 5410 /* If this node produce output for several consumers, 5411 we can't touch it. */ 5412 consumers = 0; 5413 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5414 wc = hdac_widget_get(devinfo, i); 5415 if (wc == NULL || wc->enable == 0) 5416 continue; 5417 for (j = 0; j < wc->nconns; j++) { 5418 if (wc->connsenable[j] && wc->conns[j] == nid) 5419 consumers++; 5420 } 5421 } 5422 /* The only exception is if real HP redirection is configured 5423 and this is a duplication point. 5424 XXX: Actually exception is not completely correct. 5425 XXX: Duplication point check is not perfect. */ 5426 if ((consumers == 2 && (w->bindas < 0 || 5427 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5428 (w->bindseqmask & (1 << 15)) == 0)) || 5429 consumers > 2) 5430 return; 5431 5432 /* Else use it's output mixer. */ 5433 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5434 HDA_CTL_OUT, -1, 1); 5435 if (ctl) { 5436 if (HDA_CTL_GIVE(ctl) & need) 5437 ctl->ossmask |= (1 << ossdev); 5438 else 5439 ctl->possmask |= (1 << ossdev); 5440 need &= ~HDA_CTL_GIVE(ctl); 5441 } 5442 } 5443 5444 /* We must not traverse pin */ 5445 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5446 depth > 0) 5447 return; 5448 5449 for (i = 0; i < w->nconns; i++) { 5450 int tneed = need; 5451 if (w->connsenable[i] == 0) 5452 continue; 5453 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5454 HDA_CTL_IN, i, 1); 5455 if (ctl) { 5456 if (HDA_CTL_GIVE(ctl) & tneed) 5457 ctl->ossmask |= (1 << ossdev); 5458 else 5459 ctl->possmask |= (1 << ossdev); 5460 tneed &= ~HDA_CTL_GIVE(ctl); 5461 } 5462 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5463 depth + 1, tneed); 5464 } 5465} 5466 5467/* 5468 * Assign OSS names to sound sources 5469 */ 5470static void 5471hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5472{ 5473 struct hdac_audio_as *as = devinfo->function.audio.as; 5474 struct hdac_widget *w; 5475 int i, j; 5476 int type = -1, use, used = 0; 5477 static const int types[7][13] = { 5478 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5479 SOUND_MIXER_LINE3, -1 }, /* line */ 5480 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5481 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5482 { SOUND_MIXER_CD, -1 }, /* cd */ 5483 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5484 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5485 -1 }, /* digital */ 5486 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5487 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5488 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5489 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5490 -1 } /* others */ 5491 }; 5492 5493 /* Surely known names */ 5494 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5495 w = hdac_widget_get(devinfo, i); 5496 if (w == NULL || w->enable == 0) 5497 continue; 5498 if (w->bindas == -1) 5499 continue; 5500 use = -1; 5501 switch (w->type) { 5502 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5503 if (as[w->bindas].dir == HDA_CTL_OUT) 5504 break; 5505 type = -1; 5506 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5507 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5508 type = 0; 5509 break; 5510 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5511 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5512 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5513 break; 5514 type = 1; 5515 break; 5516 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5517 type = 3; 5518 break; 5519 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5520 type = 4; 5521 break; 5522 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5523 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5524 type = 5; 5525 break; 5526 } 5527 if (type == -1) 5528 break; 5529 j = 0; 5530 while (types[type][j] >= 0 && 5531 (used & (1 << types[type][j])) != 0) { 5532 j++; 5533 } 5534 if (types[type][j] >= 0) 5535 use = types[type][j]; 5536 break; 5537 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5538 use = SOUND_MIXER_PCM; 5539 break; 5540 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5541 use = SOUND_MIXER_SPEAKER; 5542 break; 5543 default: 5544 break; 5545 } 5546 if (use >= 0) { 5547 w->ossdev = use; 5548 used |= (1 << use); 5549 } 5550 } 5551 /* Semi-known names */ 5552 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5553 w = hdac_widget_get(devinfo, i); 5554 if (w == NULL || w->enable == 0) 5555 continue; 5556 if (w->ossdev >= 0) 5557 continue; 5558 if (w->bindas == -1) 5559 continue; 5560 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5561 continue; 5562 if (as[w->bindas].dir == HDA_CTL_OUT) 5563 continue; 5564 type = -1; 5565 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5566 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5567 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5568 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5569 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5570 type = 0; 5571 break; 5572 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5573 type = 2; 5574 break; 5575 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5576 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5577 type = 5; 5578 break; 5579 } 5580 if (type == -1) 5581 break; 5582 j = 0; 5583 while (types[type][j] >= 0 && 5584 (used & (1 << types[type][j])) != 0) { 5585 j++; 5586 } 5587 if (types[type][j] >= 0) { 5588 w->ossdev = types[type][j]; 5589 used |= (1 << types[type][j]); 5590 } 5591 } 5592 /* Others */ 5593 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5594 w = hdac_widget_get(devinfo, i); 5595 if (w == NULL || w->enable == 0) 5596 continue; 5597 if (w->ossdev >= 0) 5598 continue; 5599 if (w->bindas == -1) 5600 continue; 5601 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5602 continue; 5603 if (as[w->bindas].dir == HDA_CTL_OUT) 5604 continue; 5605 j = 0; 5606 while (types[6][j] >= 0 && 5607 (used & (1 << types[6][j])) != 0) { 5608 j++; 5609 } 5610 if (types[6][j] >= 0) { 5611 w->ossdev = types[6][j]; 5612 used |= (1 << types[6][j]); 5613 } 5614 } 5615} 5616 5617static void 5618hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5619{ 5620 struct hdac_audio_as *as = devinfo->function.audio.as; 5621 int j, res; 5622 5623 HDA_BOOTVERBOSE( 5624 device_printf(devinfo->codec->sc->dev, 5625 "HWiP: HDA Widget Parser - Revision %d\n", 5626 HDA_WIDGET_PARSER_REV); 5627 ); 5628 5629 /* Trace all associations in order of their numbers, */ 5630 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5631 if (as[j].enable == 0) 5632 continue; 5633 HDA_BOOTVERBOSE( 5634 device_printf(devinfo->codec->sc->dev, 5635 "Tracing association %d (%d)\n", j, as[j].index); 5636 ); 5637 if (as[j].dir == HDA_CTL_OUT) { 5638retry: 5639 res = hdac_audio_trace_as_out(devinfo, j, 0); 5640 if (res == 0 && as[j].hpredir >= 0 && 5641 as[j].fakeredir == 0) { 5642 /* If codec can't do analog HP redirection 5643 try to make it using one more DAC. */ 5644 as[j].fakeredir = 1; 5645 goto retry; 5646 } 5647 } else { 5648 res = hdac_audio_trace_as_in(devinfo, j); 5649 } 5650 if (res) { 5651 HDA_BOOTVERBOSE( 5652 device_printf(devinfo->codec->sc->dev, 5653 "Association %d (%d) trace succeded\n", 5654 j, as[j].index); 5655 ); 5656 } else { 5657 HDA_BOOTVERBOSE( 5658 device_printf(devinfo->codec->sc->dev, 5659 "Association %d (%d) trace failed\n", 5660 j, as[j].index); 5661 ); 5662 as[j].enable = 0; 5663 } 5664 } 5665 5666 /* Trace mixer and beeper pseudo associations. */ 5667 hdac_audio_trace_as_extra(devinfo); 5668} 5669 5670static void 5671hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5672{ 5673 struct hdac_audio_as *as = devinfo->function.audio.as; 5674 struct hdac_audio_ctl *ctl; 5675 struct hdac_widget *w; 5676 int i; 5677 5678 /* Assign mixers to the tree. */ 5679 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5680 w = hdac_widget_get(devinfo, i); 5681 if (w == NULL || w->enable == 0) 5682 continue; 5683 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5684 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5685 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5686 as[w->bindas].dir == HDA_CTL_IN)) { 5687 if (w->ossdev < 0) 5688 continue; 5689 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5690 w->ossdev, 1, 0, 1); 5691 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 5692 if (w->ossdev < 0) 5693 continue; 5694 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 5695 w->ossdev, 1, 0, 1)) { 5696 /* If we are unable to control input monitor 5697 as source - try to control it as destination. */ 5698 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5699 w->ossdev, 0, 1); 5700 } 5701 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5702 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5703 SOUND_MIXER_RECLEV, 0, 1); 5704 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5705 as[w->bindas].dir == HDA_CTL_OUT) { 5706 hdac_audio_ctl_dest_amp(devinfo, w->nid, 5707 SOUND_MIXER_VOLUME, 0, 1); 5708 } 5709 } 5710 /* Treat unrequired as possible. */ 5711 i = 0; 5712 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5713 if (ctl->ossmask == 0) 5714 ctl->ossmask = ctl->possmask; 5715 } 5716} 5717 5718static void 5719hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 5720{ 5721 struct hdac_audio_as *as = devinfo->function.audio.as; 5722 struct hdac_widget *w; 5723 uint32_t pincap; 5724 int i; 5725 5726 for (i = 0; i < devinfo->nodecnt; i++) { 5727 w = &devinfo->widget[i]; 5728 if (w == NULL) 5729 continue; 5730 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5731 continue; 5732 5733 pincap = w->wclass.pin.cap; 5734 5735 /* Disable everything. */ 5736 w->wclass.pin.ctrl &= ~( 5737 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5738 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5739 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5740 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5741 5742 if (w->enable == 0 || 5743 w->bindas < 0 || as[w->bindas].enable == 0) { 5744 /* Pin is unused so left it disabled. */ 5745 continue; 5746 } else if (as[w->bindas].dir == HDA_CTL_IN) { 5747 /* Input pin, configure for input. */ 5748 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5749 w->wclass.pin.ctrl |= 5750 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5751 5752 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5753 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5754 w->wclass.pin.ctrl |= 5755 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5756 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5757 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5758 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5759 w->wclass.pin.ctrl |= 5760 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5761 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5762 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5763 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5764 w->wclass.pin.ctrl |= 5765 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5766 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5767 } else { 5768 /* Output pin, configure for output. */ 5769 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5770 w->wclass.pin.ctrl |= 5771 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 5772 5773 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 5774 (w->wclass.pin.config & 5775 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 5776 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5777 w->wclass.pin.ctrl |= 5778 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5779 5780 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5781 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5782 w->wclass.pin.ctrl |= 5783 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5784 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5785 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5786 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5787 w->wclass.pin.ctrl |= 5788 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5789 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5790 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5791 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5792 w->wclass.pin.ctrl |= 5793 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5794 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5795 } 5796 } 5797} 5798 5799static void 5800hdac_audio_commit(struct hdac_devinfo *devinfo) 5801{ 5802 struct hdac_softc *sc = devinfo->codec->sc; 5803 struct hdac_widget *w; 5804 nid_t cad; 5805 uint32_t gdata, gmask, gdir; 5806 int commitgpio, numgpio; 5807 int i; 5808 5809 cad = devinfo->codec->cad; 5810 5811 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5812 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5813 0x7e7, 0), cad); 5814 5815 gdata = 0; 5816 gmask = 0; 5817 gdir = 0; 5818 commitgpio = 0; 5819 5820 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5821 devinfo->function.audio.gpio); 5822 5823 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5824 commitgpio = (numgpio > 0) ? 1 : 0; 5825 else { 5826 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5827 if (!(devinfo->function.audio.quirks & 5828 (1 << i))) 5829 continue; 5830 if (commitgpio == 0) { 5831 commitgpio = 1; 5832 HDA_BOOTVERBOSE( 5833 gdata = hdac_command(sc, 5834 HDA_CMD_GET_GPIO_DATA(cad, 5835 devinfo->nid), cad); 5836 gmask = hdac_command(sc, 5837 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5838 devinfo->nid), cad); 5839 gdir = hdac_command(sc, 5840 HDA_CMD_GET_GPIO_DIRECTION(cad, 5841 devinfo->nid), cad); 5842 device_printf(sc->dev, 5843 "GPIO init: data=0x%08x " 5844 "mask=0x%08x dir=0x%08x\n", 5845 gdata, gmask, gdir); 5846 gdata = 0; 5847 gmask = 0; 5848 gdir = 0; 5849 ); 5850 } 5851 gdata |= 1 << i; 5852 gmask |= 1 << i; 5853 gdir |= 1 << i; 5854 } 5855 } 5856 5857 if (commitgpio != 0) { 5858 HDA_BOOTVERBOSE( 5859 device_printf(sc->dev, 5860 "GPIO commit: data=0x%08x mask=0x%08x " 5861 "dir=0x%08x\n", 5862 gdata, gmask, gdir); 5863 ); 5864 hdac_command(sc, 5865 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5866 gmask), cad); 5867 hdac_command(sc, 5868 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5869 gdir), cad); 5870 hdac_command(sc, 5871 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5872 gdata), cad); 5873 } 5874 5875 for (i = 0; i < devinfo->nodecnt; i++) { 5876 w = &devinfo->widget[i]; 5877 if (w == NULL) 5878 continue; 5879 if (w->selconn == -1) 5880 w->selconn = 0; 5881 if (w->nconns > 0) 5882 hdac_widget_connection_select(w, w->selconn); 5883 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5884 hdac_command(sc, 5885 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5886 w->wclass.pin.ctrl), cad); 5887 } 5888 if (w->param.eapdbtl != HDAC_INVALID) { 5889 uint32_t val; 5890 5891 val = w->param.eapdbtl; 5892 if (devinfo->function.audio.quirks & 5893 HDA_QUIRK_EAPDINV) 5894 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5895 hdac_command(sc, 5896 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5897 val), cad); 5898 5899 } 5900 DELAY(1000); 5901 } 5902} 5903 5904static void 5905hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5906{ 5907 struct hdac_audio_ctl *ctl; 5908 int i, z; 5909 5910 i = 0; 5911 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5912 if (ctl->enable == 0) { 5913 /* Mute disabled controls. */ 5914 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 5915 continue; 5916 } 5917 /* Init controls to 0dB amplification. */ 5918 z = ctl->offset; 5919 if (z > ctl->step) 5920 z = ctl->step; 5921 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 5922 } 5923} 5924 5925static void 5926hdac_powerup(struct hdac_devinfo *devinfo) 5927{ 5928 struct hdac_softc *sc = devinfo->codec->sc; 5929 nid_t cad = devinfo->codec->cad; 5930 int i; 5931 5932 hdac_command(sc, 5933 HDA_CMD_SET_POWER_STATE(cad, 5934 devinfo->nid, HDA_CMD_POWER_STATE_D0), 5935 cad); 5936 DELAY(100); 5937 5938 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5939 hdac_command(sc, 5940 HDA_CMD_SET_POWER_STATE(cad, 5941 i, HDA_CMD_POWER_STATE_D0), 5942 cad); 5943 } 5944 DELAY(1000); 5945} 5946 5947static int 5948hdac_pcmchannel_setup(struct hdac_chan *ch) 5949{ 5950 struct hdac_devinfo *devinfo = ch->devinfo; 5951 struct hdac_audio_as *as = devinfo->function.audio.as; 5952 struct hdac_widget *w; 5953 uint32_t cap, fmtcap, pcmcap; 5954 int i, j, ret, max; 5955 5956 ch->caps = hdac_caps; 5957 ch->caps.fmtlist = ch->fmtlist; 5958 ch->bit16 = 1; 5959 ch->bit32 = 0; 5960 ch->pcmrates[0] = 48000; 5961 ch->pcmrates[1] = 0; 5962 5963 ret = 0; 5964 fmtcap = devinfo->function.audio.supp_stream_formats; 5965 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5966 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5967 5968 for (i = 0; i < 16 && ret < max; i++) { 5969 /* Check as is correct */ 5970 if (ch->as < 0) 5971 break; 5972 /* Cound only present DACs */ 5973 if (as[ch->as].dacs[i] <= 0) 5974 continue; 5975 /* Ignore duplicates */ 5976 for (j = 0; j < ret; j++) { 5977 if (ch->io[j] == as[ch->as].dacs[i]) 5978 break; 5979 } 5980 if (j < ret) 5981 continue; 5982 5983 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 5984 if (w == NULL || w->enable == 0) 5985 continue; 5986 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 5987 continue; 5988 cap = w->param.supp_stream_formats; 5989 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5990 }*/ 5991 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 5992 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5993 continue; 5994 /* Many codec does not declare AC3 support on SPDIF. 5995 I don't beleave that they doesn't support it! */ 5996 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5997 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 5998 if (ret == 0) { 5999 fmtcap = cap; 6000 pcmcap = w->param.supp_pcm_size_rate; 6001 } else { 6002 fmtcap &= cap; 6003 pcmcap &= w->param.supp_pcm_size_rate; 6004 } 6005 ch->io[ret++] = as[ch->as].dacs[i]; 6006 } 6007 ch->io[ret] = -1; 6008 6009 ch->supp_stream_formats = fmtcap; 6010 ch->supp_pcm_size_rate = pcmcap; 6011 6012 /* 6013 * 8bit = 0 6014 * 16bit = 1 6015 * 20bit = 2 6016 * 24bit = 3 6017 * 32bit = 4 6018 */ 6019 if (ret > 0) { 6020 i = 0; 6021 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6022 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6023 ch->bit16 = 1; 6024 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6025 ch->bit16 = 0; 6026 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6027 ch->bit32 = 4; 6028 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6029 ch->bit32 = 3; 6030 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6031 ch->bit32 = 2; 6032 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6033 ch->fmtlist[i++] = AFMT_S16_LE; 6034 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6035 if (ch->bit32 > 0) { 6036 if (!(devinfo->function.audio.quirks & 6037 HDA_QUIRK_FORCESTEREO)) 6038 ch->fmtlist[i++] = AFMT_S32_LE; 6039 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6040 } 6041 } 6042 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6043 ch->fmtlist[i++] = AFMT_AC3; 6044 } 6045 ch->fmtlist[i] = 0; 6046 i = 0; 6047 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6048 ch->pcmrates[i++] = 8000; 6049 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6050 ch->pcmrates[i++] = 11025; 6051 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6052 ch->pcmrates[i++] = 16000; 6053 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6054 ch->pcmrates[i++] = 22050; 6055 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6056 ch->pcmrates[i++] = 32000; 6057 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6058 ch->pcmrates[i++] = 44100; 6059 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6060 ch->pcmrates[i++] = 48000; 6061 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6062 ch->pcmrates[i++] = 88200; 6063 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6064 ch->pcmrates[i++] = 96000; 6065 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6066 ch->pcmrates[i++] = 176400; 6067 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6068 ch->pcmrates[i++] = 192000; 6069 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6070 ch->pcmrates[i] = 0; 6071 if (i > 0) { 6072 ch->caps.minspeed = ch->pcmrates[0]; 6073 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6074 } 6075 } 6076 6077 return (ret); 6078} 6079 6080static void 6081hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6082{ 6083 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6084 struct hdac_audio_ctl *ctl; 6085 struct hdac_softc *sc = devinfo->codec->sc; 6086 char buf[64]; 6087 int i, j, printed; 6088 6089 if (flag == 0) { 6090 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6091 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6092 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6093 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6094 } 6095 6096 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6097 if ((flag & (1 << j)) == 0) 6098 continue; 6099 i = 0; 6100 printed = 0; 6101 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6102 if (ctl->enable == 0 || 6103 ctl->widget->enable == 0) 6104 continue; 6105 if (!((pdevinfo->play >= 0 && 6106 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6107 (pdevinfo->rec >= 0 && 6108 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6109 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6110 continue; 6111 if ((ctl->ossmask & (1 << j)) == 0) 6112 continue; 6113 6114 if (printed == 0) { 6115 device_printf(pdevinfo->dev, "\n"); 6116 if (banner != NULL) { 6117 device_printf(pdevinfo->dev, "%s", banner); 6118 } else { 6119 device_printf(pdevinfo->dev, "Unknown Ctl"); 6120 } 6121 printf(" (OSS: %s)\n", 6122 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6123 buf, sizeof(buf))); 6124 device_printf(pdevinfo->dev, " |\n"); 6125 printed = 1; 6126 } 6127 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6128 ctl->widget->nid, 6129 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6130 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6131 printf(" %2d): ", ctl->index); 6132 else 6133 printf("): "); 6134 if (ctl->step > 0) { 6135 printf("%+d/%+ddB (%d steps)%s\n", 6136 (0 - ctl->offset) * (ctl->size + 1) / 4, 6137 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6138 ctl->step + 1, 6139 ctl->mute?" + mute":""); 6140 } else 6141 printf("%s\n", ctl->mute?"mute":""); 6142 } 6143 } 6144} 6145 6146static void 6147hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6148{ 6149 uint32_t cap; 6150 6151 cap = fcap; 6152 if (cap != 0) { 6153 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6154 device_printf(dev, " Format:"); 6155 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6156 printf(" AC3"); 6157 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6158 printf(" FLOAT32"); 6159 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6160 printf(" PCM"); 6161 printf("\n"); 6162 } 6163 cap = pcmcap; 6164 if (cap != 0) { 6165 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6166 device_printf(dev, " PCM size:"); 6167 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6168 printf(" 8"); 6169 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6170 printf(" 16"); 6171 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6172 printf(" 20"); 6173 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6174 printf(" 24"); 6175 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6176 printf(" 32"); 6177 printf("\n"); 6178 device_printf(dev, " PCM rate:"); 6179 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6180 printf(" 8"); 6181 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6182 printf(" 11"); 6183 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6184 printf(" 16"); 6185 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6186 printf(" 22"); 6187 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6188 printf(" 32"); 6189 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6190 printf(" 44"); 6191 printf(" 48"); 6192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6193 printf(" 88"); 6194 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6195 printf(" 96"); 6196 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6197 printf(" 176"); 6198 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6199 printf(" 192"); 6200 printf("\n"); 6201 } 6202} 6203 6204static void 6205hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6206{ 6207 uint32_t pincap, wcap; 6208 6209 pincap = w->wclass.pin.cap; 6210 wcap = w->param.widget_cap; 6211 6212 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6213 device_printf(sc->dev, " "); 6214 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6215 printf(" ISC"); 6216 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6217 printf(" TRQD"); 6218 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6219 printf(" PDC"); 6220 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6221 printf(" HP"); 6222 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6223 printf(" OUT"); 6224 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6225 printf(" IN"); 6226 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6227 printf(" BAL"); 6228 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6229 printf(" VREF["); 6230 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6231 printf(" 50"); 6232 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6233 printf(" 80"); 6234 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6235 printf(" 100"); 6236 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6237 printf(" GROUND"); 6238 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6239 printf(" HIZ"); 6240 printf(" ]"); 6241 } 6242 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6243 printf(" EAPD"); 6244 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 6245 printf(" : UNSOL"); 6246 printf("\n"); 6247 device_printf(sc->dev, " Pin config: 0x%08x\n", 6248 w->wclass.pin.config); 6249 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6250 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6251 printf(" HP"); 6252 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6253 printf(" IN"); 6254 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6255 printf(" OUT"); 6256 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6257 printf(" VREFs"); 6258 printf("\n"); 6259} 6260 6261static void 6262hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6263{ 6264 struct hdac_softc *sc = w->devinfo->codec->sc; 6265 6266 device_printf(sc->dev, "nid %d 0x%08x as %2d seq %2d %13s %5s " 6267 "jack %2d loc %2d color %7s misc %d%s\n", 6268 w->nid, conf, 6269 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6270 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6271 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6272 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6273 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6274 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6275 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6276 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6277 (w->enable == 0)?" [DISABLED]":""); 6278} 6279 6280static void 6281hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6282{ 6283 struct hdac_widget *w; 6284 int i; 6285 6286 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6287 w = hdac_widget_get(devinfo, i); 6288 if (w == NULL) 6289 continue; 6290 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6291 continue; 6292 hdac_dump_pin_config(w, w->wclass.pin.config); 6293 } 6294} 6295 6296static void 6297hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6298{ 6299 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6300 device_printf(sc->dev, " " 6301 "mute=%d step=%d size=%d offset=%d\n", 6302 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6303 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6304 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6305 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6306} 6307 6308static void 6309hdac_dump_nodes(struct hdac_devinfo *devinfo) 6310{ 6311 struct hdac_softc *sc = devinfo->codec->sc; 6312 static char *ossname[] = SOUND_DEVICE_NAMES; 6313 struct hdac_widget *w, *cw; 6314 char buf[64]; 6315 int i, j; 6316 6317 device_printf(sc->dev, "\n"); 6318 device_printf(sc->dev, "Default Parameter\n"); 6319 device_printf(sc->dev, "-----------------\n"); 6320 hdac_dump_audio_formats(sc->dev, 6321 devinfo->function.audio.supp_stream_formats, 6322 devinfo->function.audio.supp_pcm_size_rate); 6323 device_printf(sc->dev, " IN amp: 0x%08x\n", 6324 devinfo->function.audio.inamp_cap); 6325 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6326 devinfo->function.audio.outamp_cap); 6327 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6328 w = hdac_widget_get(devinfo, i); 6329 if (w == NULL) { 6330 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6331 continue; 6332 } 6333 device_printf(sc->dev, "\n"); 6334 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 6335 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 6336 "DIGITAL" : "ANALOG", 6337 (w->enable == 0) ? " [DISABLED]" : ""); 6338 device_printf(sc->dev, " name: %s\n", w->name); 6339 device_printf(sc->dev, " widget_cap: 0x%08x\n", 6340 w->param.widget_cap); 6341 device_printf(sc->dev, " Parse flags: 0x%x\n", 6342 w->pflags); 6343 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6344 w->bindas, w->bindseqmask); 6345 device_printf(sc->dev, " OSS: %s", 6346 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6347 if (w->ossdev >= 0) 6348 printf(" (%s)", ossname[w->ossdev]); 6349 printf("\n"); 6350 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6351 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6352 hdac_dump_audio_formats(sc->dev, 6353 w->param.supp_stream_formats, 6354 w->param.supp_pcm_size_rate); 6355 } else if (w->type == 6356 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6357 hdac_dump_pin(sc, w); 6358 if (w->param.eapdbtl != HDAC_INVALID) 6359 device_printf(sc->dev, " EAPD: 0x%08x\n", 6360 w->param.eapdbtl); 6361 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6362 w->param.outamp_cap != 0) 6363 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6364 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6365 w->param.inamp_cap != 0) 6366 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6367 device_printf(sc->dev, " connections: %d\n", w->nconns); 6368 if (w->nconns > 0) 6369 device_printf(sc->dev, " |\n"); 6370 for (j = 0; j < w->nconns; j++) { 6371 cw = hdac_widget_get(devinfo, w->conns[j]); 6372 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6373 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6374 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6375 if (cw == NULL) 6376 printf(" [UNKNOWN]"); 6377 else if (cw->enable == 0) 6378 printf(" [DISABLED]"); 6379 if (w->nconns > 1 && w->selconn == j && w->type != 6380 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6381 printf(" (selected)"); 6382 printf("\n"); 6383 } 6384 } 6385 6386} 6387 6388static void 6389hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6390{ 6391 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6392 struct hdac_widget *w, *cw; 6393 char buf[64]; 6394 int i, printed = 0; 6395 6396 if (depth > HDA_PARSE_MAXDEPTH) 6397 return; 6398 6399 w = hdac_widget_get(devinfo, nid); 6400 if (w == NULL || w->enable == 0) 6401 return; 6402 6403 if (depth == 0) 6404 device_printf(pdevinfo->dev, "%*s", 4, ""); 6405 else 6406 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6407 printf("nid=%d [%s]", w->nid, w->name); 6408 6409 if (depth > 0) { 6410 if (w->ossmask == 0) { 6411 printf("\n"); 6412 return; 6413 } 6414 printf(" [src: %s]", 6415 hdac_audio_ctl_ossmixer_mask2allname( 6416 w->ossmask, buf, sizeof(buf))); 6417 if (w->ossdev >= 0) { 6418 printf("\n"); 6419 return; 6420 } 6421 } 6422 printf("\n"); 6423 6424 for (i = 0; i < w->nconns; i++) { 6425 if (w->connsenable[i] == 0) 6426 continue; 6427 cw = hdac_widget_get(devinfo, w->conns[i]); 6428 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6429 continue; 6430 if (printed == 0) { 6431 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6432 printed = 1; 6433 } 6434 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6435 } 6436 6437} 6438 6439static void 6440hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6441{ 6442 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6443 struct hdac_softc *sc = devinfo->codec->sc; 6444 struct hdac_widget *w; 6445 int i, printed = 0; 6446 6447 if (pdevinfo->play < 0) 6448 return; 6449 6450 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6451 w = hdac_widget_get(devinfo, i); 6452 if (w == NULL || w->enable == 0) 6453 continue; 6454 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6455 continue; 6456 if (w->bindas != sc->chans[pdevinfo->play].as) 6457 continue; 6458 if (printed == 0) { 6459 printed = 1; 6460 device_printf(pdevinfo->dev, "\n"); 6461 device_printf(pdevinfo->dev, "Playback:\n"); 6462 } 6463 device_printf(pdevinfo->dev, "\n"); 6464 hdac_dump_dst_nid(pdevinfo, i, 0); 6465 } 6466} 6467 6468static void 6469hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6470{ 6471 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6472 struct hdac_softc *sc = devinfo->codec->sc; 6473 struct hdac_widget *w; 6474 int i; 6475 int printed = 0; 6476 6477 if (pdevinfo->rec < 0) 6478 return; 6479 6480 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6481 w = hdac_widget_get(devinfo, i); 6482 if (w == NULL || w->enable == 0) 6483 continue; 6484 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6485 continue; 6486 if (w->bindas != sc->chans[pdevinfo->rec].as) 6487 continue; 6488 if (printed == 0) { 6489 printed = 1; 6490 device_printf(pdevinfo->dev, "\n"); 6491 device_printf(pdevinfo->dev, "Record:\n"); 6492 } 6493 device_printf(pdevinfo->dev, "\n"); 6494 hdac_dump_dst_nid(pdevinfo, i, 0); 6495 } 6496} 6497 6498static void 6499hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6500{ 6501 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6502 struct hdac_widget *w; 6503 int i; 6504 int printed = 0; 6505 6506 if (pdevinfo->index != 0) 6507 return; 6508 6509 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6510 w = hdac_widget_get(devinfo, i); 6511 if (w == NULL || w->enable == 0) 6512 continue; 6513 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6514 continue; 6515 if (printed == 0) { 6516 printed = 1; 6517 device_printf(pdevinfo->dev, "\n"); 6518 device_printf(pdevinfo->dev, "Input Mix:\n"); 6519 } 6520 device_printf(pdevinfo->dev, "\n"); 6521 hdac_dump_dst_nid(pdevinfo, i, 0); 6522 } 6523} 6524 6525static void 6526hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6527{ 6528 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6529 nid_t *nids; 6530 int i; 6531 6532 if (pdevinfo->play >= 0) { 6533 i = pdevinfo->play; 6534 device_printf(pdevinfo->dev, "\n"); 6535 device_printf(pdevinfo->dev, "Playback:\n"); 6536 device_printf(pdevinfo->dev, "\n"); 6537 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6538 sc->chans[i].supp_pcm_size_rate); 6539 device_printf(pdevinfo->dev, " DAC:"); 6540 for (nids = sc->chans[i].io; *nids != -1; nids++) 6541 printf(" %d", *nids); 6542 printf("\n"); 6543 } 6544 if (pdevinfo->rec >= 0) { 6545 i = pdevinfo->rec; 6546 device_printf(pdevinfo->dev, "\n"); 6547 device_printf(pdevinfo->dev, "Record:\n"); 6548 device_printf(pdevinfo->dev, "\n"); 6549 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6550 sc->chans[i].supp_pcm_size_rate); 6551 device_printf(pdevinfo->dev, " ADC:"); 6552 for (nids = sc->chans[i].io; *nids != -1; nids++) 6553 printf(" %d", *nids); 6554 printf("\n"); 6555 } 6556} 6557 6558static void 6559hdac_release_resources(struct hdac_softc *sc) 6560{ 6561 int i, j; 6562 6563 if (sc == NULL) 6564 return; 6565 6566 hdac_lock(sc); 6567 sc->polling = 0; 6568 sc->poll_ival = 0; 6569 callout_stop(&sc->poll_hda); 6570 callout_stop(&sc->poll_hdac); 6571 callout_stop(&sc->poll_jack); 6572 hdac_reset(sc, 0); 6573 hdac_unlock(sc); 6574 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6575 callout_drain(&sc->poll_hda); 6576 callout_drain(&sc->poll_hdac); 6577 callout_drain(&sc->poll_jack); 6578 6579 hdac_irq_free(sc); 6580 6581 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6582 if (sc->codecs[i] == NULL) 6583 continue; 6584 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6585 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6586 if (sc->codecs[i]->fgs[j].node_type == 6587 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6588 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6589 M_HDAC); 6590 free(sc->codecs[i]->fgs[j].function.audio.as, 6591 M_HDAC); 6592 free(sc->codecs[i]->fgs[j].function.audio.devs, 6593 M_HDAC); 6594 } 6595 } 6596 free(sc->codecs[i]->fgs, M_HDAC); 6597 free(sc->codecs[i], M_HDAC); 6598 sc->codecs[i] = NULL; 6599 } 6600 6601 hdac_dma_free(sc, &sc->pos_dma); 6602 hdac_dma_free(sc, &sc->rirb_dma); 6603 hdac_dma_free(sc, &sc->corb_dma); 6604 for (i = 0; i < sc->num_chans; i++) { 6605 if (sc->chans[i].blkcnt > 0) 6606 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 6607 } 6608 free(sc->chans, M_HDAC); 6609 if (sc->chan_dmat != NULL) { 6610 bus_dma_tag_destroy(sc->chan_dmat); 6611 sc->chan_dmat = NULL; 6612 } 6613 hdac_mem_free(sc); 6614 snd_mtxfree(sc->lock); 6615} 6616 6617/* This function surely going to make its way into upper level someday. */ 6618static void 6619hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 6620{ 6621 const char *res = NULL; 6622 int i = 0, j, k, len, inv; 6623 6624 if (on != NULL) 6625 *on = 0; 6626 if (off != NULL) 6627 *off = 0; 6628 if (sc == NULL) 6629 return; 6630 if (resource_string_value(device_get_name(sc->dev), 6631 device_get_unit(sc->dev), "config", &res) != 0) 6632 return; 6633 if (!(res != NULL && strlen(res) > 0)) 6634 return; 6635 HDA_BOOTVERBOSE( 6636 device_printf(sc->dev, "HDA Config:"); 6637 ); 6638 for (;;) { 6639 while (res[i] != '\0' && 6640 (res[i] == ',' || isspace(res[i]) != 0)) 6641 i++; 6642 if (res[i] == '\0') { 6643 HDA_BOOTVERBOSE( 6644 printf("\n"); 6645 ); 6646 return; 6647 } 6648 j = i; 6649 while (res[j] != '\0' && 6650 !(res[j] == ',' || isspace(res[j]) != 0)) 6651 j++; 6652 len = j - i; 6653 if (len > 2 && strncmp(res + i, "no", 2) == 0) 6654 inv = 2; 6655 else 6656 inv = 0; 6657 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 6658 if (strncmp(res + i + inv, 6659 hdac_quirks_tab[k].key, len - inv) != 0) 6660 continue; 6661 if (len - inv != strlen(hdac_quirks_tab[k].key)) 6662 break; 6663 HDA_BOOTVERBOSE( 6664 printf(" %s%s", (inv != 0) ? "no" : "", 6665 hdac_quirks_tab[k].key); 6666 ); 6667 if (inv == 0 && on != NULL) 6668 *on |= hdac_quirks_tab[k].value; 6669 else if (inv != 0 && off != NULL) 6670 *off |= hdac_quirks_tab[k].value; 6671 break; 6672 } 6673 i = j; 6674 } 6675} 6676 6677#ifdef SND_DYNSYSCTL 6678static int 6679sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 6680{ 6681 struct hdac_softc *sc; 6682 device_t dev; 6683 uint32_t ctl; 6684 int err, val; 6685 6686 dev = oidp->oid_arg1; 6687 sc = device_get_softc(dev); 6688 if (sc == NULL) 6689 return (EINVAL); 6690 hdac_lock(sc); 6691 val = sc->polling; 6692 hdac_unlock(sc); 6693 err = sysctl_handle_int(oidp, &val, 0, req); 6694 6695 if (err != 0 || req->newptr == NULL) 6696 return (err); 6697 if (val < 0 || val > 1) 6698 return (EINVAL); 6699 6700 hdac_lock(sc); 6701 if (val != sc->polling) { 6702 if (val == 0) { 6703 callout_stop(&sc->poll_hda); 6704 callout_stop(&sc->poll_hdac); 6705 hdac_unlock(sc); 6706 callout_drain(&sc->poll_hda); 6707 callout_drain(&sc->poll_hdac); 6708 hdac_lock(sc); 6709 sc->polling = 0; 6710 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6711 ctl |= HDAC_INTCTL_GIE; 6712 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6713 } else { 6714 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 6715 ctl &= ~HDAC_INTCTL_GIE; 6716 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 6717 hdac_unlock(sc); 6718 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6719 hdac_lock(sc); 6720 sc->polling = 1; 6721 hdac_poll_reinit(sc); 6722 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6723 } 6724 } 6725 hdac_unlock(sc); 6726 6727 return (err); 6728} 6729 6730static int 6731sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6732{ 6733 struct hdac_softc *sc; 6734 device_t dev; 6735 int err, val; 6736 6737 dev = oidp->oid_arg1; 6738 sc = device_get_softc(dev); 6739 if (sc == NULL) 6740 return (EINVAL); 6741 hdac_lock(sc); 6742 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6743 hdac_unlock(sc); 6744 err = sysctl_handle_int(oidp, &val, 0, req); 6745 6746 if (err != 0 || req->newptr == NULL) 6747 return (err); 6748 6749 if (val < 1) 6750 val = 1; 6751 if (val > 5000) 6752 val = 5000; 6753 val = ((uint64_t)val * hz) / 1000; 6754 if (val < 1) 6755 val = 1; 6756 if (val > (hz * 5)) 6757 val = hz * 5; 6758 6759 hdac_lock(sc); 6760 sc->poll_ival = val; 6761 hdac_unlock(sc); 6762 6763 return (err); 6764} 6765 6766static int 6767sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6768{ 6769 struct hdac_softc *sc; 6770 struct hdac_codec *codec; 6771 struct hdac_devinfo *devinfo; 6772 struct hdac_widget *w; 6773 device_t dev; 6774 uint32_t res, pincap, delay; 6775 int codec_index, fg_index; 6776 int i, err, val; 6777 nid_t cad; 6778 6779 dev = oidp->oid_arg1; 6780 sc = device_get_softc(dev); 6781 if (sc == NULL) 6782 return (EINVAL); 6783 val = 0; 6784 err = sysctl_handle_int(oidp, &val, 0, req); 6785 if (err != 0 || req->newptr == NULL || val == 0) 6786 return (err); 6787 6788 /* XXX: Temporary. For debugging. */ 6789 if (val == 100) { 6790 hdac_suspend(dev); 6791 return (0); 6792 } else if (val == 101) { 6793 hdac_resume(dev); 6794 return (0); 6795 } 6796 6797 hdac_lock(sc); 6798 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 6799 codec = sc->codecs[codec_index]; 6800 if (codec == NULL) 6801 continue; 6802 cad = codec->cad; 6803 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 6804 devinfo = &codec->fgs[fg_index]; 6805 if (devinfo->node_type != 6806 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 6807 continue; 6808 6809 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 6810 codec_index, devinfo->nid); 6811 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6812 w = hdac_widget_get(devinfo, i); 6813 if (w == NULL || w->type != 6814 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6815 continue; 6816 hdac_dump_pin_config(w, w->wclass.pin.config); 6817 pincap = w->wclass.pin.cap; 6818 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 6819 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 6820 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 6821 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 6822 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 6823 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 6824 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6825 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 6826 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6827 delay = 0; 6828 hdac_command(sc, 6829 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6830 do { 6831 res = hdac_command(sc, 6832 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6833 if (res != 0x7fffffff && res != 0xffffffff) 6834 break; 6835 DELAY(10); 6836 } while (++delay < 10000); 6837 } else { 6838 delay = 0; 6839 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6840 w->nid), cad); 6841 } 6842 printf(" Sense: 0x%08x", res); 6843 if (delay > 0) 6844 printf(" delay %dus", delay * 10); 6845 } 6846 printf("\n"); 6847 } 6848 device_printf(dev, 6849 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6850 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6851 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6852 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6853 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6854 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6855 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6856 device_printf(dev, " GPI:"); 6857 res = hdac_command(sc, 6858 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6859 printf(" data=0x%08x", res); 6860 res = hdac_command(sc, 6861 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6862 cad); 6863 printf(" wake=0x%08x", res); 6864 res = hdac_command(sc, 6865 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6866 cad); 6867 printf(" unsol=0x%08x", res); 6868 res = hdac_command(sc, 6869 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6870 printf(" sticky=0x%08x\n", res); 6871 } 6872 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6873 device_printf(dev, " GPO:"); 6874 res = hdac_command(sc, 6875 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6876 printf(" data=0x%08x\n", res); 6877 } 6878 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6879 device_printf(dev, "GPIO:"); 6880 res = hdac_command(sc, 6881 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6882 printf(" data=0x%08x", res); 6883 res = hdac_command(sc, 6884 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6885 printf(" enable=0x%08x", res); 6886 res = hdac_command(sc, 6887 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6888 printf(" direction=0x%08x\n", res); 6889 res = hdac_command(sc, 6890 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6891 device_printf(dev, " wake=0x%08x", res); 6892 res = hdac_command(sc, 6893 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6894 cad); 6895 printf(" unsol=0x%08x", res); 6896 res = hdac_command(sc, 6897 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6898 printf(" sticky=0x%08x\n", res); 6899 } 6900 } 6901 } 6902 hdac_unlock(sc); 6903 return (0); 6904} 6905#endif 6906 6907static void 6908hdac_attach2(void *arg) 6909{ 6910 struct hdac_codec *codec; 6911 struct hdac_softc *sc; 6912 struct hdac_audio_ctl *ctl; 6913 uint32_t quirks_on, quirks_off; 6914 int codec_index, fg_index; 6915 int i, pdev, rdev, dmaalloc = 0; 6916 struct hdac_devinfo *devinfo; 6917 6918 sc = (struct hdac_softc *)arg; 6919 6920 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6921 6922 HDA_BOOTVERBOSE( 6923 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 6924 quirks_on, quirks_off); 6925 ); 6926 6927 hdac_lock(sc); 6928 6929 /* Remove ourselves from the config hooks */ 6930 if (sc->intrhook.ich_func != NULL) { 6931 config_intrhook_disestablish(&sc->intrhook); 6932 sc->intrhook.ich_func = NULL; 6933 } 6934 6935 /* Start the corb and rirb engines */ 6936 HDA_BOOTVERBOSE( 6937 device_printf(sc->dev, "Starting CORB Engine...\n"); 6938 ); 6939 hdac_corb_start(sc); 6940 HDA_BOOTVERBOSE( 6941 device_printf(sc->dev, "Starting RIRB Engine...\n"); 6942 ); 6943 hdac_rirb_start(sc); 6944 6945 HDA_BOOTVERBOSE( 6946 device_printf(sc->dev, 6947 "Enabling controller interrupt...\n"); 6948 ); 6949 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6950 HDAC_GCTL_UNSOL); 6951 if (sc->polling == 0) { 6952 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6953 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6954 } else { 6955 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6956 } 6957 DELAY(1000); 6958 6959 HDA_BOOTVERBOSE( 6960 device_printf(sc->dev, 6961 "Scanning HDA codecs ...\n"); 6962 ); 6963 hdac_scan_codecs(sc); 6964 6965 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 6966 codec = sc->codecs[codec_index]; 6967 if (codec == NULL) 6968 continue; 6969 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 6970 devinfo = &codec->fgs[fg_index]; 6971 device_printf(sc->dev, "\n"); 6972 if (devinfo->node_type != 6973 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6974 HDA_BOOTVERBOSE( 6975 device_printf(sc->dev, 6976 "Power down unsupported non-audio FG" 6977 " cad=%d nid=%d to the D3 state...\n", 6978 codec->cad, devinfo->nid); 6979 ); 6980 hdac_command(sc, 6981 HDA_CMD_SET_POWER_STATE(codec->cad, 6982 devinfo->nid, HDA_CMD_POWER_STATE_D3), 6983 codec->cad); 6984 continue; 6985 } 6986 6987 HDA_BOOTVERBOSE( 6988 device_printf(sc->dev, 6989 "Power up audio FG cad=%d nid=%d...\n", 6990 devinfo->codec->cad, devinfo->nid); 6991 ); 6992 hdac_powerup(devinfo); 6993 HDA_BOOTVERBOSE( 6994 device_printf(sc->dev, "Parsing audio FG...\n"); 6995 ); 6996 hdac_audio_parse(devinfo); 6997 HDA_BOOTVERBOSE( 6998 device_printf(sc->dev, "Parsing Ctls...\n"); 6999 ); 7000 hdac_audio_ctl_parse(devinfo); 7001 HDA_BOOTVERBOSE( 7002 device_printf(sc->dev, "Parsing vendor patch...\n"); 7003 ); 7004 hdac_vendor_patch_parse(devinfo); 7005 devinfo->function.audio.quirks |= quirks_on; 7006 devinfo->function.audio.quirks &= ~quirks_off; 7007 7008 HDA_BOOTVERBOSE( 7009 device_printf(sc->dev, "Disabling nonaudio...\n"); 7010 ); 7011 hdac_audio_disable_nonaudio(devinfo); 7012 HDA_BOOTVERBOSE( 7013 device_printf(sc->dev, "Disabling useless...\n"); 7014 ); 7015 hdac_audio_disable_useless(devinfo); 7016 HDA_BOOTVERBOSE( 7017 device_printf(sc->dev, "Patched pins configuration:\n"); 7018 hdac_dump_pin_configs(devinfo); 7019 device_printf(sc->dev, "Parsing pin associations...\n"); 7020 ); 7021 hdac_audio_as_parse(devinfo); 7022 HDA_BOOTVERBOSE( 7023 device_printf(sc->dev, "Building AFG tree...\n"); 7024 ); 7025 hdac_audio_build_tree(devinfo); 7026 HDA_BOOTVERBOSE( 7027 device_printf(sc->dev, "Disabling unassociated " 7028 "widgets...\n"); 7029 ); 7030 hdac_audio_disable_unas(devinfo); 7031 HDA_BOOTVERBOSE( 7032 device_printf(sc->dev, "Disabling nonselected " 7033 "inputs...\n"); 7034 ); 7035 hdac_audio_disable_notselected(devinfo); 7036 HDA_BOOTVERBOSE( 7037 device_printf(sc->dev, "Disabling useless...\n"); 7038 ); 7039 hdac_audio_disable_useless(devinfo); 7040 HDA_BOOTVERBOSE( 7041 device_printf(sc->dev, "Disabling " 7042 "crossassociatement connections...\n"); 7043 ); 7044 hdac_audio_disable_crossas(devinfo); 7045 HDA_BOOTVERBOSE( 7046 device_printf(sc->dev, "Disabling useless...\n"); 7047 ); 7048 hdac_audio_disable_useless(devinfo); 7049 HDA_BOOTVERBOSE( 7050 device_printf(sc->dev, "Binding associations to channels...\n"); 7051 ); 7052 hdac_audio_bind_as(devinfo); 7053 HDA_BOOTVERBOSE( 7054 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7055 ); 7056 hdac_audio_assign_names(devinfo); 7057 HDA_BOOTVERBOSE( 7058 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7059 ); 7060 hdac_audio_assign_mixers(devinfo); 7061 HDA_BOOTVERBOSE( 7062 device_printf(sc->dev, "Preparing pin controls...\n"); 7063 ); 7064 hdac_audio_prepare_pin_ctrl(devinfo); 7065 HDA_BOOTVERBOSE( 7066 device_printf(sc->dev, "AFG commit...\n"); 7067 ); 7068 hdac_audio_commit(devinfo); 7069 HDA_BOOTVERBOSE( 7070 device_printf(sc->dev, "Ctls commit...\n"); 7071 ); 7072 hdac_audio_ctl_commit(devinfo); 7073 HDA_BOOTVERBOSE( 7074 device_printf(sc->dev, "HP switch init...\n"); 7075 ); 7076 hdac_hp_switch_init(devinfo); 7077 7078 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7079 dmaalloc == 0) { 7080 if (hdac_dma_alloc(sc, &sc->pos_dma, 7081 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7082 HDA_BOOTVERBOSE( 7083 device_printf(sc->dev, "Failed to " 7084 "allocate DMA pos buffer " 7085 "(non-fatal)\n"); 7086 ); 7087 } else 7088 dmaalloc = 1; 7089 } 7090 7091 i = devinfo->function.audio.playcnt; 7092 if (devinfo->function.audio.reccnt > i) 7093 i = devinfo->function.audio.reccnt; 7094 devinfo->function.audio.devs = 7095 (struct hdac_pcm_devinfo *)malloc( 7096 sizeof(struct hdac_pcm_devinfo) * i, 7097 M_HDAC, M_ZERO | M_NOWAIT); 7098 if (devinfo->function.audio.devs == NULL) { 7099 device_printf(sc->dev, 7100 "Unable to allocate memory for devices\n"); 7101 continue; 7102 } 7103 devinfo->function.audio.num_devs = i; 7104 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7105 devinfo->function.audio.devs[i].index = i; 7106 devinfo->function.audio.devs[i].devinfo = devinfo; 7107 devinfo->function.audio.devs[i].play = -1; 7108 devinfo->function.audio.devs[i].rec = -1; 7109 } 7110 pdev = 0; 7111 rdev = 0; 7112 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 7113 if (devinfo->function.audio.as[i].enable == 0) 7114 continue; 7115 if (devinfo->function.audio.as[i].dir == 7116 HDA_CTL_IN) { 7117 devinfo->function.audio.devs[rdev].rec 7118 = devinfo->function.audio.as[i].chan; 7119 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7120 &devinfo->function.audio.devs[rdev]; 7121 rdev++; 7122 } else { 7123 devinfo->function.audio.devs[pdev].play 7124 = devinfo->function.audio.as[i].chan; 7125 sc->chans[devinfo->function.audio.as[i].chan].pdevinfo = 7126 &devinfo->function.audio.devs[pdev]; 7127 pdev++; 7128 } 7129 } 7130 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7131 struct hdac_pcm_devinfo *pdevinfo = 7132 &devinfo->function.audio.devs[i]; 7133 pdevinfo->dev = 7134 device_add_child(sc->dev, "pcm", -1); 7135 device_set_ivars(pdevinfo->dev, 7136 (void *)pdevinfo); 7137 } 7138 7139 HDA_BOOTVERBOSE( 7140 if (devinfo->function.audio.quirks != 0) { 7141 device_printf(sc->dev, "\n"); 7142 device_printf(sc->dev, "HDA config/quirks:"); 7143 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7144 if ((devinfo->function.audio.quirks & 7145 hdac_quirks_tab[i].value) == 7146 hdac_quirks_tab[i].value) 7147 printf(" %s", hdac_quirks_tab[i].key); 7148 } 7149 printf("\n"); 7150 } 7151 7152 device_printf(sc->dev, "\n"); 7153 device_printf(sc->dev, "+-------------------+\n"); 7154 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7155 device_printf(sc->dev, "+-------------------+\n"); 7156 hdac_dump_nodes(devinfo); 7157 7158 device_printf(sc->dev, "\n"); 7159 device_printf(sc->dev, "+------------------------+\n"); 7160 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7161 device_printf(sc->dev, "+------------------------+\n"); 7162 device_printf(sc->dev, "\n"); 7163 i = 0; 7164 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7165 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7166 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7167 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7168 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7169 ctl->index); 7170 if (ctl->childwidget != NULL) 7171 printf(" cnid %3d", ctl->childwidget->nid); 7172 else 7173 printf(" "); 7174 printf(" ossmask=0x%08x\n", 7175 ctl->ossmask); 7176 device_printf(sc->dev, 7177 " mute: %d step: %3d size: %3d off: %3d%s\n", 7178 ctl->mute, ctl->step, ctl->size, ctl->offset, 7179 (ctl->enable == 0) ? " [DISABLED]" : 7180 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7181 } 7182 ); 7183 } 7184 } 7185 hdac_unlock(sc); 7186 7187 HDA_BOOTVERBOSE( 7188 device_printf(sc->dev, "\n"); 7189 ); 7190 7191 bus_generic_attach(sc->dev); 7192 7193#ifdef SND_DYNSYSCTL 7194 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7195 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7196 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7197 sysctl_hdac_polling, "I", "Enable polling mode"); 7198 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7199 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7200 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7201 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7202 "Controller/Jack Sense polling interval (1-1000 ms)"); 7203 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7204 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7205 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7206 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7207#endif 7208} 7209 7210/**************************************************************************** 7211 * int hdac_suspend(device_t) 7212 * 7213 * Suspend and power down HDA bus and codecs. 7214 ****************************************************************************/ 7215static int 7216hdac_suspend(device_t dev) 7217{ 7218 struct hdac_softc *sc; 7219 struct hdac_codec *codec; 7220 struct hdac_devinfo *devinfo; 7221 int codec_index, fg_index, i; 7222 7223 HDA_BOOTVERBOSE( 7224 device_printf(dev, "Suspend...\n"); 7225 ); 7226 7227 sc = device_get_softc(dev); 7228 hdac_lock(sc); 7229 7230 HDA_BOOTVERBOSE( 7231 device_printf(dev, "Stop streams...\n"); 7232 ); 7233 for (i = 0; i < sc->num_chans; i++) { 7234 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7235 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7236 hdac_channel_stop(sc, &sc->chans[i]); 7237 } 7238 } 7239 7240 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7241 codec = sc->codecs[codec_index]; 7242 if (codec == NULL) 7243 continue; 7244 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7245 devinfo = &codec->fgs[fg_index]; 7246 HDA_BOOTVERBOSE( 7247 device_printf(dev, 7248 "Power down FG" 7249 " cad=%d nid=%d to the D3 state...\n", 7250 codec->cad, devinfo->nid); 7251 ); 7252 hdac_command(sc, 7253 HDA_CMD_SET_POWER_STATE(codec->cad, 7254 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7255 codec->cad); 7256 } 7257 } 7258 7259 HDA_BOOTVERBOSE( 7260 device_printf(dev, "Reset controller...\n"); 7261 ); 7262 callout_stop(&sc->poll_hda); 7263 callout_stop(&sc->poll_hdac); 7264 callout_stop(&sc->poll_jack); 7265 hdac_reset(sc, 0); 7266 hdac_unlock(sc); 7267 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7268 callout_drain(&sc->poll_hda); 7269 callout_drain(&sc->poll_hdac); 7270 callout_drain(&sc->poll_jack); 7271 7272 HDA_BOOTVERBOSE( 7273 device_printf(dev, "Suspend done\n"); 7274 ); 7275 7276 return (0); 7277} 7278 7279/**************************************************************************** 7280 * int hdac_resume(device_t) 7281 * 7282 * Powerup and restore HDA bus and codecs state. 7283 ****************************************************************************/ 7284static int 7285hdac_resume(device_t dev) 7286{ 7287 struct hdac_softc *sc; 7288 struct hdac_codec *codec; 7289 struct hdac_devinfo *devinfo; 7290 int codec_index, fg_index, i; 7291 7292 HDA_BOOTVERBOSE( 7293 device_printf(dev, "Resume...\n"); 7294 ); 7295 7296 sc = device_get_softc(dev); 7297 hdac_lock(sc); 7298 7299 /* Quiesce everything */ 7300 HDA_BOOTVERBOSE( 7301 device_printf(dev, "Reset controller...\n"); 7302 ); 7303 hdac_reset(sc, 1); 7304 7305 /* Initialize the CORB and RIRB */ 7306 hdac_corb_init(sc); 7307 hdac_rirb_init(sc); 7308 7309 /* Start the corb and rirb engines */ 7310 HDA_BOOTVERBOSE( 7311 device_printf(dev, "Starting CORB Engine...\n"); 7312 ); 7313 hdac_corb_start(sc); 7314 HDA_BOOTVERBOSE( 7315 device_printf(dev, "Starting RIRB Engine...\n"); 7316 ); 7317 hdac_rirb_start(sc); 7318 7319 HDA_BOOTVERBOSE( 7320 device_printf(dev, 7321 "Enabling controller interrupt...\n"); 7322 ); 7323 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7324 HDAC_GCTL_UNSOL); 7325 if (sc->polling == 0) { 7326 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7327 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7328 } else { 7329 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7330 } 7331 DELAY(1000); 7332 7333 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7334 codec = sc->codecs[codec_index]; 7335 if (codec == NULL) 7336 continue; 7337 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7338 devinfo = &codec->fgs[fg_index]; 7339 if (devinfo->node_type != 7340 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7341 HDA_BOOTVERBOSE( 7342 device_printf(dev, 7343 "Power down unsupported non-audio FG" 7344 " cad=%d nid=%d to the D3 state...\n", 7345 codec->cad, devinfo->nid); 7346 ); 7347 hdac_command(sc, 7348 HDA_CMD_SET_POWER_STATE(codec->cad, 7349 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7350 codec->cad); 7351 continue; 7352 } 7353 7354 HDA_BOOTVERBOSE( 7355 device_printf(dev, 7356 "Power up audio FG cad=%d nid=%d...\n", 7357 devinfo->codec->cad, devinfo->nid); 7358 ); 7359 hdac_powerup(devinfo); 7360 HDA_BOOTVERBOSE( 7361 device_printf(dev, "AFG commit...\n"); 7362 ); 7363 hdac_audio_commit(devinfo); 7364 HDA_BOOTVERBOSE( 7365 device_printf(dev, "Ctls commit...\n"); 7366 ); 7367 hdac_audio_ctl_commit(devinfo); 7368 HDA_BOOTVERBOSE( 7369 device_printf(dev, "HP switch init...\n"); 7370 ); 7371 hdac_hp_switch_init(devinfo); 7372 7373 hdac_unlock(sc); 7374 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7375 struct hdac_pcm_devinfo *pdevinfo = 7376 &devinfo->function.audio.devs[i]; 7377 HDA_BOOTVERBOSE( 7378 device_printf(pdevinfo->dev, 7379 "OSS mixer reinitialization...\n"); 7380 ); 7381 if (mixer_reinit(pdevinfo->dev) == -1) 7382 device_printf(pdevinfo->dev, 7383 "unable to reinitialize the mixer\n"); 7384 } 7385 hdac_lock(sc); 7386 } 7387 } 7388 7389 HDA_BOOTVERBOSE( 7390 device_printf(dev, "Start streams...\n"); 7391 ); 7392 for (i = 0; i < sc->num_chans; i++) { 7393 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7394 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7395 hdac_channel_start(sc, &sc->chans[i]); 7396 } 7397 } 7398 7399 hdac_unlock(sc); 7400 7401 HDA_BOOTVERBOSE( 7402 device_printf(dev, "Resume done\n"); 7403 ); 7404 7405 return (0); 7406} 7407/**************************************************************************** 7408 * int hdac_detach(device_t) 7409 * 7410 * Detach and free up resources utilized by the hdac device. 7411 ****************************************************************************/ 7412static int 7413hdac_detach(device_t dev) 7414{ 7415 struct hdac_softc *sc; 7416 device_t *devlist = NULL; 7417 int i, devcount; 7418 7419 sc = device_get_softc(dev); 7420 7421 device_get_children(dev, &devlist, &devcount); 7422 for (i = 0; devlist != NULL && i < devcount; i++) 7423 device_delete_child(dev, devlist[i]); 7424 if (devlist != NULL) 7425 free(devlist, M_TEMP); 7426 7427 hdac_release_resources(sc); 7428 7429 return (0); 7430} 7431 7432static device_method_t hdac_methods[] = { 7433 /* device interface */ 7434 DEVMETHOD(device_probe, hdac_probe), 7435 DEVMETHOD(device_attach, hdac_attach), 7436 DEVMETHOD(device_detach, hdac_detach), 7437 DEVMETHOD(device_suspend, hdac_suspend), 7438 DEVMETHOD(device_resume, hdac_resume), 7439 { 0, 0 } 7440}; 7441 7442static driver_t hdac_driver = { 7443 "hdac", 7444 hdac_methods, 7445 sizeof(struct hdac_softc), 7446}; 7447 7448static devclass_t hdac_devclass; 7449 7450DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7451MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7452MODULE_VERSION(snd_hda, 1); 7453 7454static int 7455hdac_pcm_probe(device_t dev) 7456{ 7457 struct hdac_pcm_devinfo *pdevinfo = 7458 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7459 char buf[128]; 7460 7461 snprintf(buf, sizeof(buf), "HDA codec #%d %s PCM #%d", 7462 pdevinfo->devinfo->codec->cad, 7463 hdac_codec_name(pdevinfo->devinfo->codec), 7464 pdevinfo->index); 7465 device_set_desc_copy(dev, buf); 7466 return (0); 7467} 7468 7469static int 7470hdac_pcm_attach(device_t dev) 7471{ 7472 struct hdac_pcm_devinfo *pdevinfo = 7473 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7474 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7475 char status[SND_STATUSLEN]; 7476 int i; 7477 7478 pdevinfo->chan_size = pcm_getbuffersize(dev, 7479 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7480 7481 HDA_BOOTVERBOSE( 7482 device_printf(dev, "+--------------------------------------+\n"); 7483 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7484 device_printf(dev, "+--------------------------------------+\n"); 7485 hdac_dump_pcmchannels(pdevinfo); 7486 device_printf(dev, "\n"); 7487 device_printf(dev, "+--------------------------------+\n"); 7488 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7489 device_printf(dev, "+--------------------------------+\n"); 7490 hdac_dump_dac(pdevinfo); 7491 hdac_dump_adc(pdevinfo); 7492 hdac_dump_mix(pdevinfo); 7493 device_printf(dev, "\n"); 7494 device_printf(dev, "+-------------------------+\n"); 7495 device_printf(dev, "| DUMPING Volume Controls |\n"); 7496 device_printf(dev, "+-------------------------+\n"); 7497 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7498 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7499 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7500 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7501 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7502 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7503 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7504 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7505 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7506 hdac_dump_ctls(pdevinfo, NULL, 0); 7507 device_printf(dev, "\n"); 7508 ); 7509 7510 if (resource_int_value(device_get_name(dev), 7511 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7512 i &= HDA_BLK_ALIGN; 7513 if (i < HDA_BLK_MIN) 7514 i = HDA_BLK_MIN; 7515 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7516 i = 0; 7517 while (pdevinfo->chan_blkcnt >> i) 7518 i++; 7519 pdevinfo->chan_blkcnt = 1 << (i - 1); 7520 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7521 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7522 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7523 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7524 } else 7525 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7526 7527 /* 7528 * We don't register interrupt handler with snd_setup_intr 7529 * in pcm device. Mark pcm device as MPSAFE manually. 7530 */ 7531 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7532 7533 HDA_BOOTVERBOSE( 7534 device_printf(dev, "OSS mixer initialization...\n"); 7535 ); 7536 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7537 device_printf(dev, "Can't register mixer\n"); 7538 7539 HDA_BOOTVERBOSE( 7540 device_printf(dev, "Registering PCM channels...\n"); 7541 ); 7542 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7543 (pdevinfo->rec >= 0)?1:0) != 0) 7544 device_printf(dev, "Can't register PCM\n"); 7545 7546 pdevinfo->registered++; 7547 7548 if (pdevinfo->play >= 0) 7549 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7550 if (pdevinfo->rec >= 0) 7551 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7552 7553 snprintf(status, SND_STATUSLEN, "at %s cad %d %s [%s]", 7554 device_get_nameunit(sc->dev), pdevinfo->devinfo->codec->cad, 7555 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 7556 pcm_setstatus(dev, status); 7557 7558 return (0); 7559} 7560 7561static int 7562hdac_pcm_detach(device_t dev) 7563{ 7564 struct hdac_pcm_devinfo *pdevinfo = 7565 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7566 int err; 7567 7568 if (pdevinfo->registered > 0) { 7569 err = pcm_unregister(dev); 7570 if (err != 0) 7571 return (err); 7572 } 7573 7574 return (0); 7575} 7576 7577static device_method_t hdac_pcm_methods[] = { 7578 /* device interface */ 7579 DEVMETHOD(device_probe, hdac_pcm_probe), 7580 DEVMETHOD(device_attach, hdac_pcm_attach), 7581 DEVMETHOD(device_detach, hdac_pcm_detach), 7582 { 0, 0 } 7583}; 7584 7585static driver_t hdac_pcm_driver = { 7586 "pcm", 7587 hdac_pcm_methods, 7588 PCM_SOFTC_SIZE, 7589}; 7590 7591DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7592 7593