hdac.c revision 180532
1280862Sandrew/*- 2280862Sandrew * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3280862Sandrew * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4280862Sandrew * All rights reserved. 5280862Sandrew * 6280862Sandrew * Redistribution and use in source and binary forms, with or without 7280862Sandrew * modification, are permitted provided that the following conditions 8280862Sandrew * are met: 9280862Sandrew * 1. Redistributions of source code must retain the above copyright 10280862Sandrew * notice, this list of conditions and the following disclaimer. 11280862Sandrew * 2. Redistributions in binary form must reproduce the above copyright 12280862Sandrew * notice, this list of conditions and the following disclaimer in the 13280862Sandrew * documentation and/or other materials provided with the distribution. 14280862Sandrew * 15280862Sandrew * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16280862Sandrew * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17280862Sandrew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18280862Sandrew * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19280862Sandrew * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20280862Sandrew * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21280862Sandrew * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22280862Sandrew * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23280862Sandrew * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24280862Sandrew * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25280862Sandrew * SUCH DAMAGE. 26280862Sandrew */ 27280862Sandrew 28280862Sandrew/* 29280862Sandrew * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30280862Sandrew * that this driver still in its early stage, and possible of rewrite are 31280862Sandrew * pretty much guaranteed. There are supposedly several distinct parent/child 32280862Sandrew * busses to make this "perfect", but as for now and for the sake of 33280862Sandrew * simplicity, everything is gobble up within single source. 34280862Sandrew * 35280862Sandrew * List of subsys: 36280862Sandrew * 1) HDA Controller support 37280862Sandrew * 2) HDA Codecs support, which may include 38280862Sandrew * - HDA 39280862Sandrew * - Modem 40280862Sandrew * - HDMI 41280862Sandrew * 3) Widget parser - the real magic of why this driver works on so 42280862Sandrew * many hardwares with minimal vendor specific quirk. The original 43280862Sandrew * parser was written using Ruby and can be found at 44280862Sandrew * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45280862Sandrew * ruby parser take the verbose dmesg dump as its input. Refer to 46280862Sandrew * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47280862Sandrew * interesting documents, especially UAA (Universal Audio Architecture). 48280862Sandrew * 4) Possible vendor specific support. 49280862Sandrew * (snd_hda_intel, snd_hda_ati, etc..) 50280862Sandrew * 51280862Sandrew * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52280862Sandrew * Compaq V3000 with Conexant HDA. 53280862Sandrew * 54280862Sandrew * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55280862Sandrew * * * 56280862Sandrew * * This driver is a collaborative effort made by: * 57280862Sandrew * * * 58280862Sandrew * * Stephane E. Potvin <sepotvin@videotron.ca> * 59280862Sandrew * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60280862Sandrew * * Wesley Morgan <morganw@chemikals.org> * 61280862Sandrew * * Daniel Eischen <deischen@FreeBSD.org> * 62280862Sandrew * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63280862Sandrew * * Ariff Abdullah <ariff@FreeBSD.org> * 64280862Sandrew * * * 65280862Sandrew * * ....and various people from freebsd-multimedia@FreeBSD.org * 66280862Sandrew * * * 67280862Sandrew * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68280862Sandrew */ 69280862Sandrew 70280862Sandrew#include <dev/sound/pcm/sound.h> 71280862Sandrew#include <dev/pci/pcireg.h> 72280862Sandrew#include <dev/pci/pcivar.h> 73280862Sandrew 74280862Sandrew#include <sys/ctype.h> 75280862Sandrew#include <sys/taskqueue.h> 76280862Sandrew 77280862Sandrew#include <dev/sound/pci/hda/hdac_private.h> 78280862Sandrew#include <dev/sound/pci/hda/hdac_reg.h> 79280862Sandrew#include <dev/sound/pci/hda/hda_reg.h> 80280862Sandrew#include <dev/sound/pci/hda/hdac.h> 81280862Sandrew 82280862Sandrew#include "mixer_if.h" 83 84#define HDA_DRV_TEST_REV "20080420_0052" 85#define HDA_WIDGET_PARSER_REV 1 86 87SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 180532 2008-07-15 02:34:44Z delphij $"); 88 89#define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93} while(0) 94 95#if 1 96#undef HDAC_INTR_EXTRA 97#define HDAC_INTR_EXTRA 1 98#endif 99 100#define hdac_lock(sc) snd_mtxlock((sc)->lock) 101#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103#define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105#undef HDAC_MSI_ENABLED 106#if __FreeBSD_version >= 700026 || \ 107 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 108#define HDAC_MSI_ENABLED 1 109#endif 110 111#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 112#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 113 (fl) == 0xffffffff || \ 114 (((fl) & 0xffff0000) == 0xffff0000 && \ 115 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 116 (((fl) & 0x0000ffff) == 0x0000ffff && \ 117 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 118#define HDA_MATCH_ALL 0xffffffff 119#define HDAC_INVALID 0xffffffff 120 121/* Default controller / jack sense poll: 250ms */ 122#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 123 124/* 125 * Make room for possible 4096 playback/record channels, in 100 years to come. 126 */ 127#define HDAC_TRIGGER_NONE 0x00000000 128#define HDAC_TRIGGER_PLAY 0x00000fff 129#define HDAC_TRIGGER_REC 0x00fff000 130#define HDAC_TRIGGER_UNSOL 0x80000000 131 132#define HDA_MODEL_CONSTRUCT(vendor, model) \ 133 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 134 135/* Controller models */ 136 137/* Intel */ 138#define INTEL_VENDORID 0x8086 139#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 140#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 141#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 142#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 143#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 144#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 145 146/* Nvidia */ 147#define NVIDIA_VENDORID 0x10de 148#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 149#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 150#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 151#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 152#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 153#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 154#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 155#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 156#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 157 158/* ATI */ 159#define ATI_VENDORID 0x1002 160#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 161#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 162#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 163 164/* VIA */ 165#define VIA_VENDORID 0x1106 166#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 167#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 168 169/* SiS */ 170#define SIS_VENDORID 0x1039 171#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 172#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 173 174/* OEM/subvendors */ 175 176/* Intel */ 177#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 178 179/* HP/Compaq */ 180#define HP_VENDORID 0x103c 181#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 182#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 183#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 184#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 185#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 186#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 187#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 188#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 189#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 190#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 191/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 192#define HP_NX6325_SUBVENDORX 0x103c30b0 193 194/* Dell */ 195#define DELL_VENDORID 0x1028 196#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 197#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 198#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 199#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 200#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 201#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 202#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 203 204/* Clevo */ 205#define CLEVO_VENDORID 0x1558 206#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 207#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 208 209/* Acer */ 210#define ACER_VENDORID 0x1025 211#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 212#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 213#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 214#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 215#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 216 217/* Asus */ 218#define ASUS_VENDORID 0x1043 219#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 220#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 221#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 222#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 223#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 224#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 225#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 226#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 227#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 228#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 229#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 230#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 231#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 232#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 233#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 234#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 235 236/* IBM / Lenovo */ 237#define IBM_VENDORID 0x1014 238#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 239#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 240 241/* Lenovo */ 242#define LENOVO_VENDORID 0x17aa 243#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 244#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 245#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 246 247/* Samsung */ 248#define SAMSUNG_VENDORID 0x144d 249#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 250#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 251 252/* Medion ? */ 253#define MEDION_VENDORID 0x161f 254#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 255#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 256 257/* Apple Computer Inc. */ 258#define APPLE_VENDORID 0x106b 259#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 260 261/* 262 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 263 * instead of their own, which is beyond my comprehension 264 * (see HDA_CODEC_STAC9221 below). 265 */ 266#define APPLE_INTEL_MAC 0x76808384 267 268/* LG Electronics */ 269#define LG_VENDORID 0x1854 270#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 271#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 272 273/* Fujitsu Siemens */ 274#define FS_VENDORID 0x1734 275#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 276#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 277#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 278 279/* Fujitsu Limited */ 280#define FL_VENDORID 0x10cf 281#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 282#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 283 284/* Toshiba */ 285#define TOSHIBA_VENDORID 0x1179 286#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 287#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 288#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 289 290/* Micro-Star International (MSI) */ 291#define MSI_VENDORID 0x1462 292#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 293#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 294#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 295 296/* Giga-Byte Technology */ 297#define GB_VENDORID 0x1458 298#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 299#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 300 301/* Uniwill ? */ 302#define UNIWILL_VENDORID 0x1584 303#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 304#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 305 306 307/* Misc constants.. */ 308#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 309#define HDA_AMP_MUTE_NONE (0) 310#define HDA_AMP_MUTE_LEFT (1 << 0) 311#define HDA_AMP_MUTE_RIGHT (1 << 1) 312#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 313 314#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 315#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 316 317#define HDA_DAC_PATH (1 << 0) 318#define HDA_ADC_PATH (1 << 1) 319#define HDA_ADC_RECSEL (1 << 2) 320 321#define HDA_DAC_LOCKED (1 << 3) 322#define HDA_ADC_LOCKED (1 << 4) 323 324#define HDA_CTL_OUT (1 << 0) 325#define HDA_CTL_IN (1 << 1) 326#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 327 328#define HDA_GPIO_MAX 8 329/* 0 - 7 = GPIO , 8 = Flush */ 330#define HDA_QUIRK_GPIO0 (1 << 0) 331#define HDA_QUIRK_GPIO1 (1 << 1) 332#define HDA_QUIRK_GPIO2 (1 << 2) 333#define HDA_QUIRK_GPIO3 (1 << 3) 334#define HDA_QUIRK_GPIO4 (1 << 4) 335#define HDA_QUIRK_GPIO5 (1 << 5) 336#define HDA_QUIRK_GPIO6 (1 << 6) 337#define HDA_QUIRK_GPIO7 (1 << 7) 338#define HDA_QUIRK_GPIOFLUSH (1 << 8) 339 340/* 9 - 25 = anything else */ 341#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 342#define HDA_QUIRK_FIXEDRATE (1 << 10) 343#define HDA_QUIRK_FORCESTEREO (1 << 11) 344#define HDA_QUIRK_EAPDINV (1 << 12) 345#define HDA_QUIRK_DMAPOS (1 << 13) 346 347/* 26 - 31 = vrefs */ 348#define HDA_QUIRK_IVREF50 (1 << 26) 349#define HDA_QUIRK_IVREF80 (1 << 27) 350#define HDA_QUIRK_IVREF100 (1 << 28) 351#define HDA_QUIRK_OVREF50 (1 << 29) 352#define HDA_QUIRK_OVREF80 (1 << 30) 353#define HDA_QUIRK_OVREF100 (1 << 31) 354 355#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 356 HDA_QUIRK_IVREF100) 357#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 358 HDA_QUIRK_OVREF100) 359#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 360 361#define SOUND_MASK_SKIP (1 << 30) 362#define SOUND_MASK_DISABLE (1 << 31) 363 364#if __FreeBSD_version < 600000 365#define taskqueue_drain(...) 366#endif 367 368static const struct { 369 char *key; 370 uint32_t value; 371} hdac_quirks_tab[] = { 372 { "gpio0", HDA_QUIRK_GPIO0 }, 373 { "gpio1", HDA_QUIRK_GPIO1 }, 374 { "gpio2", HDA_QUIRK_GPIO2 }, 375 { "gpio3", HDA_QUIRK_GPIO3 }, 376 { "gpio4", HDA_QUIRK_GPIO4 }, 377 { "gpio5", HDA_QUIRK_GPIO5 }, 378 { "gpio6", HDA_QUIRK_GPIO6 }, 379 { "gpio7", HDA_QUIRK_GPIO7 }, 380 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 381 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 382 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 383 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 384 { "eapdinv", HDA_QUIRK_EAPDINV }, 385 { "dmapos", HDA_QUIRK_DMAPOS }, 386 { "ivref50", HDA_QUIRK_IVREF50 }, 387 { "ivref80", HDA_QUIRK_IVREF80 }, 388 { "ivref100", HDA_QUIRK_IVREF100 }, 389 { "ovref50", HDA_QUIRK_OVREF50 }, 390 { "ovref80", HDA_QUIRK_OVREF80 }, 391 { "ovref100", HDA_QUIRK_OVREF100 }, 392 { "ivref", HDA_QUIRK_IVREF }, 393 { "ovref", HDA_QUIRK_OVREF }, 394 { "vref", HDA_QUIRK_VREF }, 395}; 396#define HDAC_QUIRKS_TAB_LEN \ 397 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 398 399#define HDA_BDL_MIN 2 400#define HDA_BDL_MAX 256 401#define HDA_BDL_DEFAULT HDA_BDL_MIN 402 403#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 404#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 405 406#define HDA_BUFSZ_MIN 4096 407#define HDA_BUFSZ_MAX 65536 408#define HDA_BUFSZ_DEFAULT 16384 409 410#define HDA_PARSE_MAXDEPTH 10 411 412#define HDAC_UNSOLTAG_EVENT_HP 0x00 413#define HDAC_UNSOLTAG_EVENT_TEST 0x01 414 415MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 416 417enum { 418 HDA_PARSE_MIXER, 419 HDA_PARSE_DIRECT 420}; 421 422/* Default */ 423static uint32_t hdac_fmt[] = { 424 AFMT_STEREO | AFMT_S16_LE, 425 0 426}; 427 428static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 429 430static const struct { 431 uint32_t model; 432 char *desc; 433} hdac_devices[] = { 434 { HDA_INTEL_82801F, "Intel 82801F" }, 435 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 436 { HDA_INTEL_82801G, "Intel 82801G" }, 437 { HDA_INTEL_82801H, "Intel 82801H" }, 438 { HDA_INTEL_82801I, "Intel 82801I" }, 439 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 440 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 441 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 442 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 443 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 444 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 445 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 446 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 447 { HDA_ATI_SB450, "ATI SB450" }, 448 { HDA_ATI_SB600, "ATI SB600" }, 449 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 450 { HDA_SIS_966, "SiS 966" }, 451 /* Unknown */ 452 { HDA_INTEL_ALL, "Intel (Unknown)" }, 453 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 454 { HDA_ATI_ALL, "ATI (Unknown)" }, 455 { HDA_VIA_ALL, "VIA (Unknown)" }, 456 { HDA_SIS_ALL, "SiS (Unknown)" }, 457}; 458#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 459 460static const struct { 461 uint16_t vendor; 462 uint8_t reg; 463 uint8_t mask; 464 uint8_t enable; 465} hdac_pcie_snoop[] = { 466 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 467 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 468 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 469}; 470#define HDAC_PCIESNOOP_LEN \ 471 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 472 473static const struct { 474 uint32_t rate; 475 int valid; 476 uint16_t base; 477 uint16_t mul; 478 uint16_t div; 479} hda_rate_tab[] = { 480 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 481 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 482 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 483 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 484 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 485 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 486 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 487 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 488 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 489 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 490 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 491 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 492 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 493 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 494 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 495 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 496 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 497 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 498 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 499 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 500 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 501 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 502 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 503 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 504 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 505 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 506 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 507 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 508 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 509 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 510 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 511 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 512 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 513 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 514 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 515}; 516#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 517 518/* All codecs you can eat... */ 519#define HDA_CODEC_CONSTRUCT(vendor, id) \ 520 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 521 522/* Realtek */ 523#define REALTEK_VENDORID 0x10ec 524#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 525#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 526#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 527#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 528#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 529#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 530#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 531#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 532#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 533#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 534#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 535#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 536 537/* Analog Devices */ 538#define ANALOGDEVICES_VENDORID 0x11d4 539#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 540#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 541#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 542#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 543#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 544#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 545#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 546 547/* CMedia */ 548#define CMEDIA_VENDORID 0x434d 549#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 550#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 551 552/* Sigmatel */ 553#define SIGMATEL_VENDORID 0x8384 554#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 555#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 556#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 557#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 558#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 559#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 560#define HDA_CODEC_STAC9205 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 561#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 562#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 563 564/* 565 * Conexant 566 * 567 * Ok, the truth is, I don't have any idea at all whether 568 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 569 * place that tell me it is "Venice" is from its Windows driver INF. 570 * 571 * Venice - CX????? 572 * Waikiki - CX20551-22 573 */ 574#define CONEXANT_VENDORID 0x14f1 575#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 576#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 577#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 578 579/* VIA */ 580#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 581#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 582#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 583#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 584#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 585#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 586#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 587#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 588#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 589#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 590#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 591#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 592#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 593 594 595/* Codecs */ 596static const struct { 597 uint32_t id; 598 char *name; 599} hdac_codecs[] = { 600 { HDA_CODEC_ALC260, "Realtek ALC260" }, 601 { HDA_CODEC_ALC262, "Realtek ALC262" }, 602 { HDA_CODEC_ALC268, "Realtek ALC268" }, 603 { HDA_CODEC_ALC660, "Realtek ALC660" }, 604 { HDA_CODEC_ALC861, "Realtek ALC861" }, 605 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 606 { HDA_CODEC_ALC880, "Realtek ALC880" }, 607 { HDA_CODEC_ALC882, "Realtek ALC882" }, 608 { HDA_CODEC_ALC883, "Realtek ALC883" }, 609 { HDA_CODEC_ALC885, "Realtek ALC885" }, 610 { HDA_CODEC_ALC888, "Realtek ALC888" }, 611 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 612 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 613 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 614 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 615 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 616 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 617 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 618 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 619 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 620 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 621 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 622 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 623 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 624 { HDA_CODEC_STAC9205, "Sigmatel STAC9205" }, 625 { HDA_CODEC_STAC9872AK,"Sigmatel STAC9872AK" }, 626 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 627 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 628 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 629 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 630 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 631 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 632 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 633 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 634 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 635 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 636 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 637 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 638 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 639 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 640 /* Unknown codec */ 641 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 642 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 643 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 644 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 645 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 646 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 647}; 648#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 649 650enum { 651 HDAC_HP_SWITCH_CTL, 652 HDAC_HP_SWITCH_CTRL, 653 HDAC_HP_SWITCH_DEBUG 654}; 655 656static const struct { 657 uint32_t model; 658 uint32_t id; 659 int type; 660 int inverted; 661 int polling; 662 int execsense; 663 nid_t hpnid; 664 nid_t spkrnid[8]; 665 nid_t eapdnid; 666} hdac_hp_switch[] = { 667 /* Specific OEM models */ 668 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 669 0, 0, -1, 17, { 16, -1 }, 16 }, 670 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 671 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 672 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 673 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 674 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 675 0, 0, -1, 6, { 5, -1 }, 5 }, 676 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 677 0, 0, -1, 6, { 5, -1 }, 5 }, 678 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 679 0, 0, -1, 6, { 5, -1 }, 5 }, 680 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 681 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 682 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 683 0, 0, -1, 6, { 5, -1 }, -1 }, 684 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 685 0, 0, -1, 27, { 20, -1 }, -1 }, 686 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 687 0, 0, -1, 13, { 14, -1 }, -1 }, 688 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 689 0, 0, -1, 13, { 14, -1 }, -1 }, 690 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 691 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 692 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205, HDAC_HP_SWITCH_CTRL, 693 0, 0, -1, 10, { 13, -1 }, -1 }, 694 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205, HDAC_HP_SWITCH_CTRL, 695 0, 0, -1, 10, { 13, -1 }, -1 }, 696 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 697 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 698 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 699 0, 0, -1, 10, { 13, -1 }, -1 }, 700 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 701 1, 0, -1, 26, { 27, -1 }, -1 }, 702 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 703 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 704 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 705 0, 0, -1, 27, { 20, -1 }, -1 }, 706 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 707 0, 0, -1, 20, { 21, -1 }, -1 }, 708 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 709 0, 0, -1, 20, { 21, -1 }, -1 }, 710 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 711 0, 0, -1, 20, { 21, -1 }, -1 }, 712 { ACER_A4710_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 713 0, 0, -1, 20, { 21, -1 }, -1 }, 714 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 715 0, 0, -1, 20, { 21, -1 }, -1 }, 716 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 717 0, 0, -1, 20, { 27, -1 }, -1 }, 718 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 719 0, 0, -1, 20, { 27, -1 }, -1 }, 720 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 721 0, 0, -1, 20, { 21, -1 }, -1 }, 722 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 723 0, 0, -1, 20, { 16, -1 }, -1 }, 724 /* 725 * All models that at least come from the same vendor with 726 * simmilar codec. 727 */ 728 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 729 0, 0, -1, 17, { 16, -1 }, 16 }, 730 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 731 0, 0, -1, 6, { 5, -1 }, 5 }, 732 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 733 0, 0, -1, 6, { 5, -1 }, -1 }, 734 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 735 0, 0, -1, 13, { 14, -1 }, -1 }, 736#if 0 737 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 738 1, 0, -1, 26, { 27, -1 }, -1 }, 739 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 740 0, 0, -1, 20, { 21, -1 }, -1 }, 741#endif 742}; 743#define HDAC_HP_SWITCH_LEN \ 744 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 745 746static const struct { 747 uint32_t model; 748 uint32_t id; 749 nid_t eapdnid; 750 int hp_switch; 751} hdac_eapd_switch[] = { 752 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 753 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 754 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 755}; 756#define HDAC_EAPD_SWITCH_LEN \ 757 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 758 759/**************************************************************************** 760 * Function prototypes 761 ****************************************************************************/ 762static void hdac_intr_handler(void *); 763static int hdac_reset(struct hdac_softc *); 764static int hdac_get_capabilities(struct hdac_softc *); 765static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 766static int hdac_dma_alloc(struct hdac_softc *, 767 struct hdac_dma *, bus_size_t); 768static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 769static int hdac_mem_alloc(struct hdac_softc *); 770static void hdac_mem_free(struct hdac_softc *); 771static int hdac_irq_alloc(struct hdac_softc *); 772static void hdac_irq_free(struct hdac_softc *); 773static void hdac_corb_init(struct hdac_softc *); 774static void hdac_rirb_init(struct hdac_softc *); 775static void hdac_corb_start(struct hdac_softc *); 776static void hdac_rirb_start(struct hdac_softc *); 777static void hdac_scan_codecs(struct hdac_softc *, int); 778static int hdac_probe_codec(struct hdac_codec *); 779static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 780static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 781 782static void hdac_attach2(void *); 783 784static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 785 uint32_t, int); 786static void hdac_command_send_internal(struct hdac_softc *, 787 struct hdac_command_list *, int); 788 789static int hdac_probe(device_t); 790static int hdac_attach(device_t); 791static int hdac_detach(device_t); 792static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 793static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 794 uint32_t, int, int); 795static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 796 nid_t, int, int); 797static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 798 nid_t, nid_t, int, int, int, int, int, int); 799static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 800static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 801 802static int hdac_rirb_flush(struct hdac_softc *sc); 803static int hdac_unsolq_flush(struct hdac_softc *sc); 804 805#define hdac_command(a1, a2, a3) \ 806 hdac_command_sendone_internal(a1, a2, a3) 807 808#define hdac_codec_id(d) \ 809 ((uint32_t)((d == NULL) ? 0x00000000 : \ 810 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 811 ((uint32_t)(d)->device_id & 0x0000ffff)))) 812 813static char * 814hdac_codec_name(struct hdac_devinfo *devinfo) 815{ 816 uint32_t id; 817 int i; 818 819 id = hdac_codec_id(devinfo); 820 821 for (i = 0; i < HDAC_CODECS_LEN; i++) { 822 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 823 return (hdac_codecs[i].name); 824 } 825 826 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 827} 828 829static char * 830hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 831{ 832 static char *ossname[] = SOUND_DEVICE_NAMES; 833 static char *unknown = "???"; 834 int i; 835 836 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 837 if (devmask & (1 << i)) 838 return (ossname[i]); 839 } 840 return (unknown); 841} 842 843static void 844hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 845{ 846 static char *ossname[] = SOUND_DEVICE_NAMES; 847 int i, first = 1; 848 849 bzero(buf, len); 850 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 851 if (mask & (1 << i)) { 852 if (first == 0) 853 strlcat(buf, ", ", len); 854 strlcat(buf, ossname[i], len); 855 first = 0; 856 } 857 } 858} 859 860static struct hdac_audio_ctl * 861hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 862{ 863 if (devinfo == NULL || 864 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 865 index == NULL || devinfo->function.audio.ctl == NULL || 866 devinfo->function.audio.ctlcnt < 1 || 867 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 868 return (NULL); 869 return (&devinfo->function.audio.ctl[(*index)++]); 870} 871 872static struct hdac_audio_ctl * 873hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 874 int index, int cnt) 875{ 876 struct hdac_audio_ctl *ctl, *retctl = NULL; 877 int i, at, atindex, found = 0; 878 879 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 880 return (NULL); 881 882 at = cnt; 883 if (at == 0) 884 at = 1; 885 else if (at < 0) 886 at = -1; 887 atindex = index; 888 if (atindex < 0) 889 atindex = -1; 890 891 i = 0; 892 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 893 if (ctl->enable == 0 || ctl->widget == NULL) 894 continue; 895 if (!(ctl->widget->nid == nid && (atindex == -1 || 896 ctl->index == atindex))) 897 continue; 898 found++; 899 if (found == cnt) 900 return (ctl); 901 retctl = ctl; 902 } 903 904 return ((at == -1) ? retctl : NULL); 905} 906 907static void 908hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 909{ 910 struct hdac_softc *sc; 911 struct hdac_widget *w; 912 struct hdac_audio_ctl *ctl; 913 uint32_t val, id, res; 914 int i = 0, j, timeout, forcemute; 915 nid_t cad; 916 917 if (devinfo == NULL || devinfo->codec == NULL || 918 devinfo->codec->sc == NULL) 919 return; 920 921 sc = devinfo->codec->sc; 922 cad = devinfo->codec->cad; 923 id = hdac_codec_id(devinfo); 924 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 925 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 926 sc->pci_subvendor) && 927 hdac_hp_switch[i].id == id) 928 break; 929 } 930 931 if (i >= HDAC_HP_SWITCH_LEN) 932 return; 933 934 forcemute = 0; 935 if (hdac_hp_switch[i].eapdnid != -1) { 936 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 937 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 938 forcemute = (w->param.eapdbtl & 939 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 940 } 941 942 if (hdac_hp_switch[i].execsense != -1) 943 hdac_command(sc, 944 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 945 hdac_hp_switch[i].execsense), cad); 946 947 timeout = 10000; 948 do { 949 res = hdac_command(sc, 950 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 951 cad); 952 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 953 break; 954 DELAY(10); 955 } while (--timeout != 0); 956 957 HDA_BOOTVERBOSE( 958 device_printf(sc->dev, 959 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 960 hdac_hp_switch[i].hpnid, timeout, res); 961 ); 962 963 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 964 res ^= hdac_hp_switch[i].inverted; 965 966 switch (hdac_hp_switch[i].type) { 967 case HDAC_HP_SWITCH_CTL: 968 ctl = hdac_audio_ctl_amp_get(devinfo, 969 hdac_hp_switch[i].hpnid, 0, 1); 970 if (ctl != NULL) { 971 val = (res != 0 && forcemute == 0) ? 972 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 973 if (val != ctl->muted) { 974 ctl->muted = val; 975 hdac_audio_ctl_amp_set(ctl, 976 HDA_AMP_MUTE_DEFAULT, ctl->left, 977 ctl->right); 978 } 979 } 980 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 981 ctl = hdac_audio_ctl_amp_get(devinfo, 982 hdac_hp_switch[i].spkrnid[j], 0, 1); 983 if (ctl == NULL) 984 continue; 985 val = (res != 0 || forcemute == 1) ? 986 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 987 if (val == ctl->muted) 988 continue; 989 ctl->muted = val; 990 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 991 ctl->left, ctl->right); 992 } 993 break; 994 case HDAC_HP_SWITCH_CTRL: 995 if (res != 0) { 996 /* HP in */ 997 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 998 if (w != NULL && w->type == 999 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1000 if (forcemute == 0) 1001 val = w->wclass.pin.ctrl | 1002 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1003 else 1004 val = w->wclass.pin.ctrl & 1005 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1006 if (val != w->wclass.pin.ctrl) { 1007 w->wclass.pin.ctrl = val; 1008 hdac_command(sc, 1009 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1010 w->nid, w->wclass.pin.ctrl), cad); 1011 } 1012 } 1013 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1014 w = hdac_widget_get(devinfo, 1015 hdac_hp_switch[i].spkrnid[j]); 1016 if (w == NULL || w->type != 1017 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1018 continue; 1019 val = w->wclass.pin.ctrl & 1020 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1021 if (val == w->wclass.pin.ctrl) 1022 continue; 1023 w->wclass.pin.ctrl = val; 1024 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1025 cad, w->nid, w->wclass.pin.ctrl), cad); 1026 } 1027 } else { 1028 /* HP out */ 1029 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1030 if (w != NULL && w->type == 1031 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1032 val = w->wclass.pin.ctrl & 1033 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1034 if (val != w->wclass.pin.ctrl) { 1035 w->wclass.pin.ctrl = val; 1036 hdac_command(sc, 1037 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1038 w->nid, w->wclass.pin.ctrl), cad); 1039 } 1040 } 1041 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1042 w = hdac_widget_get(devinfo, 1043 hdac_hp_switch[i].spkrnid[j]); 1044 if (w == NULL || w->type != 1045 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1046 continue; 1047 if (forcemute == 0) 1048 val = w->wclass.pin.ctrl | 1049 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1050 else 1051 val = w->wclass.pin.ctrl & 1052 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1053 if (val == w->wclass.pin.ctrl) 1054 continue; 1055 w->wclass.pin.ctrl = val; 1056 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1057 cad, w->nid, w->wclass.pin.ctrl), cad); 1058 } 1059 } 1060 break; 1061 case HDAC_HP_SWITCH_DEBUG: 1062 if (hdac_hp_switch[i].execsense != -1) 1063 hdac_command(sc, 1064 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1065 hdac_hp_switch[i].execsense), cad); 1066 res = hdac_command(sc, 1067 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1068 device_printf(sc->dev, 1069 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1070 hdac_hp_switch[i].hpnid, res); 1071 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1072 w = hdac_widget_get(devinfo, 1073 hdac_hp_switch[i].spkrnid[j]); 1074 if (w == NULL || w->type != 1075 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1076 continue; 1077 if (hdac_hp_switch[i].execsense != -1) 1078 hdac_command(sc, 1079 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1080 hdac_hp_switch[i].execsense), cad); 1081 res = hdac_command(sc, 1082 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1083 device_printf(sc->dev, 1084 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1085 j + 1, w->nid, res); 1086 } 1087 break; 1088 default: 1089 break; 1090 } 1091} 1092 1093static void 1094hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1095{ 1096 struct hdac_softc *sc; 1097 struct hdac_devinfo *devinfo = NULL; 1098 device_t *devlist = NULL; 1099 int devcount, i; 1100 1101 if (codec == NULL || codec->sc == NULL) 1102 return; 1103 1104 sc = codec->sc; 1105 1106 HDA_BOOTVERBOSE( 1107 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1108 ); 1109 1110 device_get_children(sc->dev, &devlist, &devcount); 1111 for (i = 0; devlist != NULL && i < devcount; i++) { 1112 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1113 if (devinfo != NULL && devinfo->node_type == 1114 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1115 devinfo->codec != NULL && 1116 devinfo->codec->cad == codec->cad) { 1117 break; 1118 } else 1119 devinfo = NULL; 1120 } 1121 if (devlist != NULL) 1122 free(devlist, M_TEMP); 1123 1124 if (devinfo == NULL) 1125 return; 1126 1127 switch (tag) { 1128 case HDAC_UNSOLTAG_EVENT_HP: 1129 hdac_hp_switch_handler(devinfo); 1130 break; 1131 case HDAC_UNSOLTAG_EVENT_TEST: 1132 device_printf(sc->dev, "Unsol Test!\n"); 1133 break; 1134 default: 1135 break; 1136 } 1137} 1138 1139static int 1140hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1141{ 1142 /* XXX to be removed */ 1143#ifdef HDAC_INTR_EXTRA 1144 uint32_t res; 1145#endif 1146 1147 if (!(ch->flags & HDAC_CHN_RUNNING)) 1148 return (0); 1149 1150 /* XXX to be removed */ 1151#ifdef HDAC_INTR_EXTRA 1152 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1153#endif 1154 1155 /* XXX to be removed */ 1156#ifdef HDAC_INTR_EXTRA 1157 HDA_BOOTVERBOSE( 1158 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1159 device_printf(sc->dev, 1160 "PCMDIR_%s intr triggered beyond stream boundary:" 1161 "%08x\n", 1162 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1163 ); 1164#endif 1165 1166 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1167 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1168 1169 /* XXX to be removed */ 1170#ifdef HDAC_INTR_EXTRA 1171 if (res & HDAC_SDSTS_BCIS) { 1172#endif 1173 return (1); 1174 /* XXX to be removed */ 1175#ifdef HDAC_INTR_EXTRA 1176 } 1177#endif 1178 1179 return (0); 1180} 1181 1182/**************************************************************************** 1183 * void hdac_intr_handler(void *) 1184 * 1185 * Interrupt handler. Processes interrupts received from the hdac. 1186 ****************************************************************************/ 1187static void 1188hdac_intr_handler(void *context) 1189{ 1190 struct hdac_softc *sc; 1191 uint32_t intsts; 1192 uint8_t rirbsts; 1193 struct hdac_rirb *rirb_base; 1194 uint32_t trigger; 1195 1196 sc = (struct hdac_softc *)context; 1197 1198 hdac_lock(sc); 1199 if (sc->polling != 0) { 1200 hdac_unlock(sc); 1201 return; 1202 } 1203 1204 /* Do we have anything to do? */ 1205 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1206 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1207 hdac_unlock(sc); 1208 return; 1209 } 1210 1211 trigger = 0; 1212 1213 /* Was this a controller interrupt? */ 1214 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1215 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1216 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1217 /* Get as many responses that we can */ 1218 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1219 HDAC_WRITE_1(&sc->mem, 1220 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1221 if (hdac_rirb_flush(sc) != 0) 1222 trigger |= HDAC_TRIGGER_UNSOL; 1223 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1224 } 1225 /* XXX to be removed */ 1226 /* Clear interrupt and exit */ 1227#ifdef HDAC_INTR_EXTRA 1228 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1229#endif 1230 } 1231 1232 if (intsts & HDAC_INTSTS_SIS_MASK) { 1233 if ((intsts & (1 << sc->num_iss)) && 1234 hdac_stream_intr(sc, &sc->play) != 0) 1235 trigger |= HDAC_TRIGGER_PLAY; 1236 if ((intsts & (1 << 0)) && 1237 hdac_stream_intr(sc, &sc->rec) != 0) 1238 trigger |= HDAC_TRIGGER_REC; 1239 /* XXX to be removed */ 1240#ifdef HDAC_INTR_EXTRA 1241 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1242 HDAC_INTSTS_SIS_MASK); 1243#endif 1244 } 1245 1246 hdac_unlock(sc); 1247 1248 if (trigger & HDAC_TRIGGER_PLAY) 1249 chn_intr(sc->play.c); 1250 if (trigger & HDAC_TRIGGER_REC) 1251 chn_intr(sc->rec.c); 1252 if (trigger & HDAC_TRIGGER_UNSOL) 1253 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1254} 1255 1256/**************************************************************************** 1257 * int hdac_reset(hdac_softc *) 1258 * 1259 * Reset the hdac to a quiescent and known state. 1260 ****************************************************************************/ 1261static int 1262hdac_reset(struct hdac_softc *sc) 1263{ 1264 uint32_t gctl; 1265 int count, i; 1266 1267 /* 1268 * Stop all Streams DMA engine 1269 */ 1270 for (i = 0; i < sc->num_iss; i++) 1271 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1272 for (i = 0; i < sc->num_oss; i++) 1273 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1274 for (i = 0; i < sc->num_bss; i++) 1275 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1276 1277 /* 1278 * Stop Control DMA engines. 1279 */ 1280 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1281 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1282 1283 /* 1284 * Reset DMA position buffer. 1285 */ 1286 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1287 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1288 1289 /* 1290 * Reset the controller. The reset must remain asserted for 1291 * a minimum of 100us. 1292 */ 1293 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1294 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1295 count = 10000; 1296 do { 1297 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1298 if (!(gctl & HDAC_GCTL_CRST)) 1299 break; 1300 DELAY(10); 1301 } while (--count); 1302 if (gctl & HDAC_GCTL_CRST) { 1303 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1304 return (ENXIO); 1305 } 1306 DELAY(100); 1307 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1308 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1309 count = 10000; 1310 do { 1311 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1312 if (gctl & HDAC_GCTL_CRST) 1313 break; 1314 DELAY(10); 1315 } while (--count); 1316 if (!(gctl & HDAC_GCTL_CRST)) { 1317 device_printf(sc->dev, "Device stuck in reset\n"); 1318 return (ENXIO); 1319 } 1320 1321 /* 1322 * Wait for codecs to finish their own reset sequence. The delay here 1323 * should be of 250us but for some reasons, on it's not enough on my 1324 * computer. Let's use twice as much as necessary to make sure that 1325 * it's reset properly. 1326 */ 1327 DELAY(1000); 1328 1329 return (0); 1330} 1331 1332 1333/**************************************************************************** 1334 * int hdac_get_capabilities(struct hdac_softc *); 1335 * 1336 * Retreive the general capabilities of the hdac; 1337 * Number of Input Streams 1338 * Number of Output Streams 1339 * Number of bidirectional Streams 1340 * 64bit ready 1341 * CORB and RIRB sizes 1342 ****************************************************************************/ 1343static int 1344hdac_get_capabilities(struct hdac_softc *sc) 1345{ 1346 uint16_t gcap; 1347 uint8_t corbsize, rirbsize; 1348 1349 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1350 sc->num_iss = HDAC_GCAP_ISS(gcap); 1351 sc->num_oss = HDAC_GCAP_OSS(gcap); 1352 sc->num_bss = HDAC_GCAP_BSS(gcap); 1353 1354 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1355 1356 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1357 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1358 HDAC_CORBSIZE_CORBSZCAP_256) 1359 sc->corb_size = 256; 1360 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1361 HDAC_CORBSIZE_CORBSZCAP_16) 1362 sc->corb_size = 16; 1363 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1364 HDAC_CORBSIZE_CORBSZCAP_2) 1365 sc->corb_size = 2; 1366 else { 1367 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1368 __func__, corbsize); 1369 return (ENXIO); 1370 } 1371 1372 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1373 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1374 HDAC_RIRBSIZE_RIRBSZCAP_256) 1375 sc->rirb_size = 256; 1376 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1377 HDAC_RIRBSIZE_RIRBSZCAP_16) 1378 sc->rirb_size = 16; 1379 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1380 HDAC_RIRBSIZE_RIRBSZCAP_2) 1381 sc->rirb_size = 2; 1382 else { 1383 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1384 __func__, rirbsize); 1385 return (ENXIO); 1386 } 1387 1388 return (0); 1389} 1390 1391 1392/**************************************************************************** 1393 * void hdac_dma_cb 1394 * 1395 * This function is called by bus_dmamap_load when the mapping has been 1396 * established. We just record the physical address of the mapping into 1397 * the struct hdac_dma passed in. 1398 ****************************************************************************/ 1399static void 1400hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1401{ 1402 struct hdac_dma *dma; 1403 1404 if (error == 0) { 1405 dma = (struct hdac_dma *)callback_arg; 1406 dma->dma_paddr = segs[0].ds_addr; 1407 } 1408} 1409 1410 1411/**************************************************************************** 1412 * int hdac_dma_alloc 1413 * 1414 * This function allocate and setup a dma region (struct hdac_dma). 1415 * It must be freed by a corresponding hdac_dma_free. 1416 ****************************************************************************/ 1417static int 1418hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1419{ 1420 bus_size_t roundsz; 1421 int result; 1422 int lowaddr; 1423 1424 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1425 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1426 BUS_SPACE_MAXADDR_32BIT; 1427 bzero(dma, sizeof(*dma)); 1428 1429 /* 1430 * Create a DMA tag 1431 */ 1432 result = bus_dma_tag_create(NULL, /* parent */ 1433 HDAC_DMA_ALIGNMENT, /* alignment */ 1434 0, /* boundary */ 1435 lowaddr, /* lowaddr */ 1436 BUS_SPACE_MAXADDR, /* highaddr */ 1437 NULL, /* filtfunc */ 1438 NULL, /* fistfuncarg */ 1439 roundsz, /* maxsize */ 1440 1, /* nsegments */ 1441 roundsz, /* maxsegsz */ 1442 0, /* flags */ 1443 NULL, /* lockfunc */ 1444 NULL, /* lockfuncarg */ 1445 &dma->dma_tag); /* dmat */ 1446 if (result != 0) { 1447 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1448 __func__, result); 1449 goto hdac_dma_alloc_fail; 1450 } 1451 1452 /* 1453 * Allocate DMA memory 1454 */ 1455 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1456 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1457 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1458 &dma->dma_map); 1459 if (result != 0) { 1460 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1461 __func__, result); 1462 goto hdac_dma_alloc_fail; 1463 } 1464 1465 dma->dma_size = roundsz; 1466 1467 /* 1468 * Map the memory 1469 */ 1470 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1471 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1472 if (result != 0 || dma->dma_paddr == 0) { 1473 if (result == 0) 1474 result = ENOMEM; 1475 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1476 __func__, result); 1477 goto hdac_dma_alloc_fail; 1478 } 1479 1480 HDA_BOOTVERBOSE( 1481 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1482 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1483 ); 1484 1485 return (0); 1486 1487hdac_dma_alloc_fail: 1488 hdac_dma_free(sc, dma); 1489 1490 return (result); 1491} 1492 1493 1494/**************************************************************************** 1495 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1496 * 1497 * Free a struct dhac_dma that has been previously allocated via the 1498 * hdac_dma_alloc function. 1499 ****************************************************************************/ 1500static void 1501hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1502{ 1503 if (dma->dma_map != NULL) { 1504#if 0 1505 /* Flush caches */ 1506 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1507 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1508#endif 1509 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1510 } 1511 if (dma->dma_vaddr != NULL) { 1512 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1513 dma->dma_vaddr = NULL; 1514 } 1515 dma->dma_map = NULL; 1516 if (dma->dma_tag != NULL) { 1517 bus_dma_tag_destroy(dma->dma_tag); 1518 dma->dma_tag = NULL; 1519 } 1520 dma->dma_size = 0; 1521} 1522 1523/**************************************************************************** 1524 * int hdac_mem_alloc(struct hdac_softc *) 1525 * 1526 * Allocate all the bus resources necessary to speak with the physical 1527 * controller. 1528 ****************************************************************************/ 1529static int 1530hdac_mem_alloc(struct hdac_softc *sc) 1531{ 1532 struct hdac_mem *mem; 1533 1534 mem = &sc->mem; 1535 mem->mem_rid = PCIR_BAR(0); 1536 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1537 &mem->mem_rid, RF_ACTIVE); 1538 if (mem->mem_res == NULL) { 1539 device_printf(sc->dev, 1540 "%s: Unable to allocate memory resource\n", __func__); 1541 return (ENOMEM); 1542 } 1543 mem->mem_tag = rman_get_bustag(mem->mem_res); 1544 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1545 1546 return (0); 1547} 1548 1549/**************************************************************************** 1550 * void hdac_mem_free(struct hdac_softc *) 1551 * 1552 * Free up resources previously allocated by hdac_mem_alloc. 1553 ****************************************************************************/ 1554static void 1555hdac_mem_free(struct hdac_softc *sc) 1556{ 1557 struct hdac_mem *mem; 1558 1559 mem = &sc->mem; 1560 if (mem->mem_res != NULL) 1561 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1562 mem->mem_res); 1563 mem->mem_res = NULL; 1564} 1565 1566/**************************************************************************** 1567 * int hdac_irq_alloc(struct hdac_softc *) 1568 * 1569 * Allocate and setup the resources necessary for interrupt handling. 1570 ****************************************************************************/ 1571static int 1572hdac_irq_alloc(struct hdac_softc *sc) 1573{ 1574 struct hdac_irq *irq; 1575 int result; 1576 1577 irq = &sc->irq; 1578 irq->irq_rid = 0x0; 1579 1580#ifdef HDAC_MSI_ENABLED 1581 if ((sc->flags & HDAC_F_MSI) && 1582 (result = pci_msi_count(sc->dev)) == 1 && 1583 pci_alloc_msi(sc->dev, &result) == 0) 1584 irq->irq_rid = 0x1; 1585 else 1586#endif 1587 sc->flags &= ~HDAC_F_MSI; 1588 1589 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1590 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1591 if (irq->irq_res == NULL) { 1592 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1593 __func__); 1594 goto hdac_irq_alloc_fail; 1595 } 1596 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1597 hdac_intr_handler, sc, &irq->irq_handle); 1598 if (result != 0) { 1599 device_printf(sc->dev, 1600 "%s: Unable to setup interrupt handler (%x)\n", 1601 __func__, result); 1602 goto hdac_irq_alloc_fail; 1603 } 1604 1605 return (0); 1606 1607hdac_irq_alloc_fail: 1608 hdac_irq_free(sc); 1609 1610 return (ENXIO); 1611} 1612 1613/**************************************************************************** 1614 * void hdac_irq_free(struct hdac_softc *) 1615 * 1616 * Free up resources previously allocated by hdac_irq_alloc. 1617 ****************************************************************************/ 1618static void 1619hdac_irq_free(struct hdac_softc *sc) 1620{ 1621 struct hdac_irq *irq; 1622 1623 irq = &sc->irq; 1624 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1625 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1626 if (irq->irq_res != NULL) 1627 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1628 irq->irq_res); 1629#ifdef HDAC_MSI_ENABLED 1630 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1631 pci_release_msi(sc->dev); 1632#endif 1633 irq->irq_handle = NULL; 1634 irq->irq_res = NULL; 1635 irq->irq_rid = 0x0; 1636} 1637 1638/**************************************************************************** 1639 * void hdac_corb_init(struct hdac_softc *) 1640 * 1641 * Initialize the corb registers for operations but do not start it up yet. 1642 * The CORB engine must not be running when this function is called. 1643 ****************************************************************************/ 1644static void 1645hdac_corb_init(struct hdac_softc *sc) 1646{ 1647 uint8_t corbsize; 1648 uint64_t corbpaddr; 1649 1650 /* Setup the CORB size. */ 1651 switch (sc->corb_size) { 1652 case 256: 1653 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1654 break; 1655 case 16: 1656 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1657 break; 1658 case 2: 1659 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1660 break; 1661 default: 1662 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1663 } 1664 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1665 1666 /* Setup the CORB Address in the hdac */ 1667 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1668 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1669 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1670 1671 /* Set the WP and RP */ 1672 sc->corb_wp = 0; 1673 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1674 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1675 /* 1676 * The HDA specification indicates that the CORBRPRST bit will always 1677 * read as zero. Unfortunately, it seems that at least the 82801G 1678 * doesn't reset the bit to zero, which stalls the corb engine. 1679 * manually reset the bit to zero before continuing. 1680 */ 1681 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1682 1683 /* Enable CORB error reporting */ 1684#if 0 1685 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1686#endif 1687} 1688 1689/**************************************************************************** 1690 * void hdac_rirb_init(struct hdac_softc *) 1691 * 1692 * Initialize the rirb registers for operations but do not start it up yet. 1693 * The RIRB engine must not be running when this function is called. 1694 ****************************************************************************/ 1695static void 1696hdac_rirb_init(struct hdac_softc *sc) 1697{ 1698 uint8_t rirbsize; 1699 uint64_t rirbpaddr; 1700 1701 /* Setup the RIRB size. */ 1702 switch (sc->rirb_size) { 1703 case 256: 1704 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1705 break; 1706 case 16: 1707 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1708 break; 1709 case 2: 1710 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1711 break; 1712 default: 1713 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1714 } 1715 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1716 1717 /* Setup the RIRB Address in the hdac */ 1718 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1719 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1720 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1721 1722 /* Setup the WP and RP */ 1723 sc->rirb_rp = 0; 1724 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1725 1726 if (sc->polling == 0) { 1727 /* Setup the interrupt threshold */ 1728 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1729 1730 /* Enable Overrun and response received reporting */ 1731#if 0 1732 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1733 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1734#else 1735 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1736#endif 1737 } 1738 1739#if 0 1740 /* 1741 * Make sure that the Host CPU cache doesn't contain any dirty 1742 * cache lines that falls in the rirb. If I understood correctly, it 1743 * should be sufficient to do this only once as the rirb is purely 1744 * read-only from now on. 1745 */ 1746 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1747 BUS_DMASYNC_PREREAD); 1748#endif 1749} 1750 1751/**************************************************************************** 1752 * void hdac_corb_start(hdac_softc *) 1753 * 1754 * Startup the corb DMA engine 1755 ****************************************************************************/ 1756static void 1757hdac_corb_start(struct hdac_softc *sc) 1758{ 1759 uint32_t corbctl; 1760 1761 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1762 corbctl |= HDAC_CORBCTL_CORBRUN; 1763 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1764} 1765 1766/**************************************************************************** 1767 * void hdac_rirb_start(hdac_softc *) 1768 * 1769 * Startup the rirb DMA engine 1770 ****************************************************************************/ 1771static void 1772hdac_rirb_start(struct hdac_softc *sc) 1773{ 1774 uint32_t rirbctl; 1775 1776 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1777 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1778 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1779} 1780 1781 1782/**************************************************************************** 1783 * void hdac_scan_codecs(struct hdac_softc *, int) 1784 * 1785 * Scan the bus for available codecs, starting with num. 1786 ****************************************************************************/ 1787static void 1788hdac_scan_codecs(struct hdac_softc *sc, int num) 1789{ 1790 struct hdac_codec *codec; 1791 int i; 1792 uint16_t statests; 1793 1794 if (num < 0) 1795 num = 0; 1796 if (num >= HDAC_CODEC_MAX) 1797 num = HDAC_CODEC_MAX - 1; 1798 1799 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1800 for (i = num; i < HDAC_CODEC_MAX; i++) { 1801 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1802 /* We have found a codec. */ 1803 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1804 M_HDAC, M_ZERO | M_NOWAIT); 1805 if (codec == NULL) { 1806 device_printf(sc->dev, 1807 "Unable to allocate memory for codec\n"); 1808 continue; 1809 } 1810 codec->commands = NULL; 1811 codec->responses_received = 0; 1812 codec->verbs_sent = 0; 1813 codec->sc = sc; 1814 codec->cad = i; 1815 sc->codecs[i] = codec; 1816 if (hdac_probe_codec(codec) != 0) 1817 break; 1818 } 1819 } 1820 /* All codecs have been probed, now try to attach drivers to them */ 1821 /* bus_generic_attach(sc->dev); */ 1822} 1823 1824/**************************************************************************** 1825 * void hdac_probe_codec(struct hdac_softc *, int) 1826 * 1827 * Probe a the given codec_id for available function groups. 1828 ****************************************************************************/ 1829static int 1830hdac_probe_codec(struct hdac_codec *codec) 1831{ 1832 struct hdac_softc *sc = codec->sc; 1833 struct hdac_devinfo *devinfo; 1834 uint32_t vendorid, revisionid, subnode; 1835 int startnode; 1836 int endnode; 1837 int i; 1838 nid_t cad = codec->cad; 1839 1840 HDA_BOOTVERBOSE( 1841 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1842 ); 1843 vendorid = hdac_command(sc, 1844 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1845 cad); 1846 revisionid = hdac_command(sc, 1847 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1848 cad); 1849 subnode = hdac_command(sc, 1850 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1851 cad); 1852 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1853 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1854 1855 HDA_BOOTVERBOSE( 1856 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1857 startnode, endnode); 1858 ); 1859 for (i = startnode; i < endnode; i++) { 1860 devinfo = hdac_probe_function(codec, i); 1861 if (devinfo != NULL) { 1862 /* XXX Ignore other FG. */ 1863 devinfo->vendor_id = 1864 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1865 devinfo->device_id = 1866 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1867 devinfo->revision_id = 1868 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1869 devinfo->stepping_id = 1870 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1871 HDA_BOOTVERBOSE( 1872 device_printf(sc->dev, 1873 "HDA_DEBUG: \tFound AFG nid=%d " 1874 "[startnode=%d endnode=%d]\n", 1875 devinfo->nid, startnode, endnode); 1876 ); 1877 return (1); 1878 } 1879 } 1880 1881 HDA_BOOTVERBOSE( 1882 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1883 ); 1884 return (0); 1885} 1886 1887static struct hdac_devinfo * 1888hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1889{ 1890 struct hdac_softc *sc = codec->sc; 1891 struct hdac_devinfo *devinfo; 1892 uint32_t fctgrptype; 1893 nid_t cad = codec->cad; 1894 1895 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1896 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1897 1898 /* XXX For now, ignore other FG. */ 1899 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1900 return (NULL); 1901 1902 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1903 M_NOWAIT | M_ZERO); 1904 if (devinfo == NULL) { 1905 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1906 __func__); 1907 return (NULL); 1908 } 1909 1910 devinfo->nid = nid; 1911 devinfo->node_type = fctgrptype; 1912 devinfo->codec = codec; 1913 1914 hdac_add_child(sc, devinfo); 1915 1916 return (devinfo); 1917} 1918 1919static void 1920hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1921{ 1922 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1923 device_set_ivars(devinfo->dev, (void *)devinfo); 1924 /* XXX - Print more information when booting verbose??? */ 1925} 1926 1927static void 1928hdac_widget_connection_parse(struct hdac_widget *w) 1929{ 1930 struct hdac_softc *sc = w->devinfo->codec->sc; 1931 uint32_t res; 1932 int i, j, max, ents, entnum; 1933 nid_t cad = w->devinfo->codec->cad; 1934 nid_t nid = w->nid; 1935 nid_t cnid, addcnid, prevcnid; 1936 1937 w->nconns = 0; 1938 1939 res = hdac_command(sc, 1940 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1941 1942 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1943 1944 if (ents < 1) 1945 return; 1946 1947 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1948 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1949 prevcnid = 0; 1950 1951#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1952#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1953#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1954#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1955#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1956 1957 for (i = 0; i < ents; i += entnum) { 1958 res = hdac_command(sc, 1959 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1960 for (j = 0; j < entnum; j++) { 1961 cnid = CONN_CNID(res, entnum, j); 1962 if (cnid == 0) { 1963 if (w->nconns < ents) 1964 device_printf(sc->dev, 1965 "%s: nid=%d WARNING: zero cnid " 1966 "entnum=%d j=%d index=%d " 1967 "entries=%d found=%d res=0x%08x\n", 1968 __func__, nid, entnum, j, i, 1969 ents, w->nconns, res); 1970 else 1971 goto getconns_out; 1972 } 1973 if (cnid < w->devinfo->startnode || 1974 cnid >= w->devinfo->endnode) { 1975 HDA_BOOTVERBOSE( 1976 device_printf(sc->dev, 1977 "%s: GHOST: nid=%d j=%d " 1978 "entnum=%d index=%d res=0x%08x\n", 1979 __func__, nid, j, entnum, i, res); 1980 ); 1981 } 1982 if (CONN_RANGE(res, entnum, j) == 0) 1983 addcnid = cnid; 1984 else if (prevcnid == 0 || prevcnid >= cnid) { 1985 device_printf(sc->dev, 1986 "%s: WARNING: Invalid child range " 1987 "nid=%d index=%d j=%d entnum=%d " 1988 "prevcnid=%d cnid=%d res=0x%08x\n", 1989 __func__, nid, i, j, entnum, prevcnid, 1990 cnid, res); 1991 addcnid = cnid; 1992 } else 1993 addcnid = prevcnid + 1; 1994 while (addcnid <= cnid) { 1995 if (w->nconns > max) { 1996 device_printf(sc->dev, 1997 "%s: nid=%d: Adding %d: " 1998 "Max connection reached! max=%d\n", 1999 __func__, nid, addcnid, max + 1); 2000 goto getconns_out; 2001 } 2002 w->conns[w->nconns++] = addcnid++; 2003 } 2004 prevcnid = cnid; 2005 } 2006 } 2007 2008getconns_out: 2009 HDA_BOOTVERBOSE( 2010 device_printf(sc->dev, 2011 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 2012 __func__, nid, ents, w->nconns); 2013 ); 2014 return; 2015} 2016 2017static uint32_t 2018hdac_widget_pin_getconfig(struct hdac_widget *w) 2019{ 2020 struct hdac_softc *sc; 2021 uint32_t config, orig, id; 2022 nid_t cad, nid; 2023 2024 sc = w->devinfo->codec->sc; 2025 cad = w->devinfo->codec->cad; 2026 nid = w->nid; 2027 id = hdac_codec_id(w->devinfo); 2028 2029 config = hdac_command(sc, 2030 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2031 cad); 2032 orig = config; 2033 2034 /* 2035 * XXX REWRITE!!!! Don't argue! 2036 */ 2037 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2038 switch (nid) { 2039 case 26: 2040 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2041 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2042 break; 2043 case 27: 2044 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2045 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2046 break; 2047 default: 2048 break; 2049 } 2050 } else if (id == HDA_CODEC_ALC880 && 2051 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2052 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2053 /* 2054 * Super broken BIOS 2055 */ 2056 switch (nid) { 2057 case 20: 2058 break; 2059 case 21: 2060 break; 2061 case 22: 2062 break; 2063 case 23: 2064 break; 2065 case 24: /* MIC1 */ 2066 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2067 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2068 break; 2069 case 25: /* XXX MIC2 */ 2070 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2071 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2072 break; 2073 case 26: /* LINE1 */ 2074 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2075 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2076 break; 2077 case 27: /* XXX LINE2 */ 2078 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2079 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2080 break; 2081 case 28: /* CD */ 2082 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2083 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2084 break; 2085 case 30: 2086 break; 2087 case 31: 2088 break; 2089 default: 2090 break; 2091 } 2092 } else if (id == HDA_CODEC_ALC883 && 2093 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2094 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2095 switch (nid) { 2096 case 25: 2097 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2098 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2099 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2100 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2101 break; 2102 case 28: 2103 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2104 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2105 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2106 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2107 break; 2108 default: 2109 break; 2110 } 2111 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2112 HP_V3000_SUBVENDOR) { 2113 switch (nid) { 2114 case 18: 2115 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2116 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2117 break; 2118 case 20: 2119 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2120 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2121 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2122 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2123 break; 2124 case 21: 2125 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2126 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2127 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2128 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2129 break; 2130 default: 2131 break; 2132 } 2133 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2134 HP_DV5000_SUBVENDOR) { 2135 switch (nid) { 2136 case 20: 2137 case 21: 2138 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2139 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2140 break; 2141 default: 2142 break; 2143 } 2144 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2145 ASUS_W6F_SUBVENDOR) { 2146 switch (nid) { 2147 case 11: 2148 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2149 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2150 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2151 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2152 break; 2153 case 12: 2154 case 14: 2155 case 16: 2156 case 31: 2157 case 32: 2158 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2159 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2160 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2161 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2162 break; 2163 case 15: 2164 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2165 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2166 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2167 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2168 break; 2169 default: 2170 break; 2171 } 2172 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2173 UNIWILL_9075_SUBVENDOR) { 2174 switch (nid) { 2175 case 15: 2176 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2177 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2178 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2179 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2180 break; 2181 default: 2182 break; 2183 } 2184 } else if (id == HDA_CODEC_AD1986A && 2185 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2186 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2187 switch (nid) { 2188 case 28: /* LINE */ 2189 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2190 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2191 break; 2192 case 29: /* MIC */ 2193 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2194 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2195 break; 2196 default: 2197 break; 2198 } 2199 } else if (id == HDA_CODEC_ALC268 && 2200 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2201 switch (nid) { 2202 case 28: 2203 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2204 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2205 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2206 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2207 break; 2208 default: 2209 break; 2210 } 2211 } 2212 2213 HDA_BOOTVERBOSE( 2214 if (config != orig) 2215 device_printf(sc->dev, 2216 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2217 nid, orig, config); 2218 ); 2219 2220 return (config); 2221} 2222 2223static uint32_t 2224hdac_widget_pin_getcaps(struct hdac_widget *w) 2225{ 2226 struct hdac_softc *sc; 2227 uint32_t caps, orig, id; 2228 nid_t cad, nid; 2229 2230 sc = w->devinfo->codec->sc; 2231 cad = w->devinfo->codec->cad; 2232 nid = w->nid; 2233 id = hdac_codec_id(w->devinfo); 2234 2235 caps = hdac_command(sc, 2236 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2237 orig = caps; 2238 2239 HDA_BOOTVERBOSE( 2240 if (caps != orig) 2241 device_printf(sc->dev, 2242 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2243 nid, orig, caps); 2244 ); 2245 2246 return (caps); 2247} 2248 2249static void 2250hdac_widget_pin_parse(struct hdac_widget *w) 2251{ 2252 struct hdac_softc *sc = w->devinfo->codec->sc; 2253 uint32_t config, pincap; 2254 char *devstr, *connstr; 2255 nid_t cad = w->devinfo->codec->cad; 2256 nid_t nid = w->nid; 2257 2258 config = hdac_widget_pin_getconfig(w); 2259 w->wclass.pin.config = config; 2260 2261 pincap = hdac_widget_pin_getcaps(w); 2262 w->wclass.pin.cap = pincap; 2263 2264 w->wclass.pin.ctrl = hdac_command(sc, 2265 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2266 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2267 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2268 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2269 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2270 2271 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2272 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2273 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2274 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2275 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2276 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2277 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2278 w->param.eapdbtl = hdac_command(sc, 2279 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2280 w->param.eapdbtl &= 0x7; 2281 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2282 } else 2283 w->param.eapdbtl = HDAC_INVALID; 2284 2285 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2286 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2287 devstr = "line out"; 2288 break; 2289 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2290 devstr = "speaker"; 2291 break; 2292 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2293 devstr = "headphones out"; 2294 break; 2295 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2296 devstr = "CD"; 2297 break; 2298 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2299 devstr = "SPDIF out"; 2300 break; 2301 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2302 devstr = "digital (other) out"; 2303 break; 2304 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2305 devstr = "modem, line side"; 2306 break; 2307 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2308 devstr = "modem, handset side"; 2309 break; 2310 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2311 devstr = "line in"; 2312 break; 2313 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2314 devstr = "AUX"; 2315 break; 2316 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2317 devstr = "Mic in"; 2318 break; 2319 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2320 devstr = "telephony"; 2321 break; 2322 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2323 devstr = "SPDIF in"; 2324 break; 2325 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2326 devstr = "digital (other) in"; 2327 break; 2328 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2329 devstr = "other"; 2330 break; 2331 default: 2332 devstr = "unknown"; 2333 break; 2334 } 2335 2336 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2337 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2338 connstr = "jack"; 2339 break; 2340 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2341 connstr = "none"; 2342 break; 2343 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2344 connstr = "fixed"; 2345 break; 2346 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2347 connstr = "jack / fixed"; 2348 break; 2349 default: 2350 connstr = "unknown"; 2351 break; 2352 } 2353 2354 strlcat(w->name, ": ", sizeof(w->name)); 2355 strlcat(w->name, devstr, sizeof(w->name)); 2356 strlcat(w->name, " (", sizeof(w->name)); 2357 strlcat(w->name, connstr, sizeof(w->name)); 2358 strlcat(w->name, ")", sizeof(w->name)); 2359} 2360 2361static void 2362hdac_widget_parse(struct hdac_widget *w) 2363{ 2364 struct hdac_softc *sc = w->devinfo->codec->sc; 2365 uint32_t wcap, cap; 2366 char *typestr; 2367 nid_t cad = w->devinfo->codec->cad; 2368 nid_t nid = w->nid; 2369 2370 wcap = hdac_command(sc, 2371 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2372 cad); 2373 w->param.widget_cap = wcap; 2374 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2375 2376 switch (w->type) { 2377 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2378 typestr = "audio output"; 2379 break; 2380 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2381 typestr = "audio input"; 2382 break; 2383 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2384 typestr = "audio mixer"; 2385 break; 2386 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2387 typestr = "audio selector"; 2388 break; 2389 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2390 typestr = "pin"; 2391 break; 2392 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2393 typestr = "power widget"; 2394 break; 2395 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2396 typestr = "volume widget"; 2397 break; 2398 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2399 typestr = "beep widget"; 2400 break; 2401 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2402 typestr = "vendor widget"; 2403 break; 2404 default: 2405 typestr = "unknown type"; 2406 break; 2407 } 2408 2409 strlcpy(w->name, typestr, sizeof(w->name)); 2410 2411 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2412 hdac_command(sc, 2413 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2414 cad); 2415 DELAY(1000); 2416 } 2417 2418 hdac_widget_connection_parse(w); 2419 2420 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2421 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2422 w->param.outamp_cap = 2423 hdac_command(sc, 2424 HDA_CMD_GET_PARAMETER(cad, nid, 2425 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2426 else 2427 w->param.outamp_cap = 2428 w->devinfo->function.audio.outamp_cap; 2429 } else 2430 w->param.outamp_cap = 0; 2431 2432 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2433 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2434 w->param.inamp_cap = 2435 hdac_command(sc, 2436 HDA_CMD_GET_PARAMETER(cad, nid, 2437 HDA_PARAM_INPUT_AMP_CAP), cad); 2438 else 2439 w->param.inamp_cap = 2440 w->devinfo->function.audio.inamp_cap; 2441 } else 2442 w->param.inamp_cap = 0; 2443 2444 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2445 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2446 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2447 cap = hdac_command(sc, 2448 HDA_CMD_GET_PARAMETER(cad, nid, 2449 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2450 w->param.supp_stream_formats = (cap != 0) ? cap : 2451 w->devinfo->function.audio.supp_stream_formats; 2452 cap = hdac_command(sc, 2453 HDA_CMD_GET_PARAMETER(cad, nid, 2454 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2455 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2456 w->devinfo->function.audio.supp_pcm_size_rate; 2457 } else { 2458 w->param.supp_stream_formats = 2459 w->devinfo->function.audio.supp_stream_formats; 2460 w->param.supp_pcm_size_rate = 2461 w->devinfo->function.audio.supp_pcm_size_rate; 2462 } 2463 } else { 2464 w->param.supp_stream_formats = 0; 2465 w->param.supp_pcm_size_rate = 0; 2466 } 2467 2468 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2469 hdac_widget_pin_parse(w); 2470} 2471 2472static struct hdac_widget * 2473hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2474{ 2475 if (devinfo == NULL || devinfo->widget == NULL || 2476 nid < devinfo->startnode || nid >= devinfo->endnode) 2477 return (NULL); 2478 return (&devinfo->widget[nid - devinfo->startnode]); 2479} 2480 2481static __inline int 2482hda_poll_channel(struct hdac_chan *ch) 2483{ 2484 uint32_t sz, delta; 2485 volatile uint32_t ptr; 2486 2487 if (!(ch->flags & HDAC_CHN_RUNNING)) 2488 return (0); 2489 2490 sz = ch->blksz * ch->blkcnt; 2491 if (ch->dmapos != NULL) 2492 ptr = *(ch->dmapos); 2493 else 2494 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2495 ch->off + HDAC_SDLPIB); 2496 ch->ptr = ptr; 2497 ptr %= sz; 2498 ptr &= ~(ch->blksz - 1); 2499 delta = (sz + ptr - ch->prevptr) % sz; 2500 2501 if (delta < ch->blksz) 2502 return (0); 2503 2504 ch->prevptr = ptr; 2505 2506 return (1); 2507} 2508 2509#define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2510 HDAC_CHN_RUNNING) 2511 2512static void 2513hda_poll_callback(void *arg) 2514{ 2515 struct hdac_softc *sc = arg; 2516 uint32_t trigger; 2517 2518 if (sc == NULL) 2519 return; 2520 2521 hdac_lock(sc); 2522 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2523 hdac_unlock(sc); 2524 return; 2525 } 2526 2527 trigger = 0; 2528 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2529 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2530 2531 /* XXX */ 2532 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2533 hda_poll_callback, sc); 2534 2535 hdac_unlock(sc); 2536 2537 if (trigger & HDAC_TRIGGER_PLAY) 2538 chn_intr(sc->play.c); 2539 if (trigger & HDAC_TRIGGER_REC) 2540 chn_intr(sc->rec.c); 2541} 2542 2543static int 2544hdac_rirb_flush(struct hdac_softc *sc) 2545{ 2546 struct hdac_rirb *rirb_base, *rirb; 2547 struct hdac_codec *codec; 2548 struct hdac_command_list *commands; 2549 nid_t cad; 2550 uint32_t resp; 2551 uint8_t rirbwp; 2552 int ret; 2553 2554 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2555 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2556#if 0 2557 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2558 BUS_DMASYNC_POSTREAD); 2559#endif 2560 2561 ret = 0; 2562 2563 while (sc->rirb_rp != rirbwp) { 2564 sc->rirb_rp++; 2565 sc->rirb_rp %= sc->rirb_size; 2566 rirb = &rirb_base[sc->rirb_rp]; 2567 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2568 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2569 sc->codecs[cad] == NULL) 2570 continue; 2571 resp = rirb->response; 2572 codec = sc->codecs[cad]; 2573 commands = codec->commands; 2574 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2575 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2576 ((resp >> 26) & 0xffff); 2577 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2578 } else if (commands != NULL && commands->num_commands > 0 && 2579 codec->responses_received < commands->num_commands) 2580 commands->responses[codec->responses_received++] = 2581 resp; 2582 ret++; 2583 } 2584 2585 return (ret); 2586} 2587 2588static int 2589hdac_unsolq_flush(struct hdac_softc *sc) 2590{ 2591 nid_t cad; 2592 uint32_t tag; 2593 int ret = 0; 2594 2595 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2596 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2597 while (sc->unsolq_rp != sc->unsolq_wp) { 2598 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2599 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2600 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2601 hdac_unsolicited_handler(sc->codecs[cad], tag); 2602 ret++; 2603 } 2604 sc->unsolq_st = HDAC_UNSOLQ_READY; 2605 } 2606 2607 return (ret); 2608} 2609 2610static void 2611hdac_poll_callback(void *arg) 2612{ 2613 struct hdac_softc *sc = arg; 2614 if (sc == NULL) 2615 return; 2616 2617 hdac_lock(sc); 2618 if (sc->polling == 0 || sc->poll_ival == 0) { 2619 hdac_unlock(sc); 2620 return; 2621 } 2622 if (hdac_rirb_flush(sc) != 0) 2623 hdac_unsolq_flush(sc); 2624 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2625 hdac_unlock(sc); 2626} 2627 2628static void 2629hdac_stream_stop(struct hdac_chan *ch) 2630{ 2631 struct hdac_softc *sc = ch->devinfo->codec->sc; 2632 uint32_t ctl; 2633 2634 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2635 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2636 HDAC_SDCTL_RUN); 2637 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2638 2639 ch->flags &= ~HDAC_CHN_RUNNING; 2640 2641 if (sc->polling != 0) { 2642 int pollticks; 2643 2644 if (hda_chan_active(sc) == 0) { 2645 callout_stop(&sc->poll_hda); 2646 sc->poll_ticks = 1; 2647 } else { 2648 if (sc->play.flags & HDAC_CHN_RUNNING) 2649 ch = &sc->play; 2650 else 2651 ch = &sc->rec; 2652 pollticks = ((uint64_t)hz * ch->blksz) / 2653 ((uint64_t)sndbuf_getbps(ch->b) * 2654 sndbuf_getspd(ch->b)); 2655 pollticks >>= 2; 2656 if (pollticks > hz) 2657 pollticks = hz; 2658 if (pollticks < 1) { 2659 HDA_BOOTVERBOSE( 2660 device_printf(sc->dev, 2661 "%s: pollticks=%d < 1 !\n", 2662 __func__, pollticks); 2663 ); 2664 pollticks = 1; 2665 } 2666 if (pollticks > sc->poll_ticks) { 2667 HDA_BOOTVERBOSE( 2668 device_printf(sc->dev, 2669 "%s: pollticks %d -> %d\n", 2670 __func__, sc->poll_ticks, 2671 pollticks); 2672 ); 2673 sc->poll_ticks = pollticks; 2674 callout_reset(&sc->poll_hda, 1, 2675 hda_poll_callback, sc); 2676 } 2677 } 2678 } else { 2679 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2680 ctl &= ~(1 << (ch->off >> 5)); 2681 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2682 } 2683} 2684 2685static void 2686hdac_stream_start(struct hdac_chan *ch) 2687{ 2688 struct hdac_softc *sc = ch->devinfo->codec->sc; 2689 uint32_t ctl; 2690 2691 if (sc->polling != 0) { 2692 int pollticks; 2693 2694 pollticks = ((uint64_t)hz * ch->blksz) / 2695 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2696 pollticks >>= 2; 2697 if (pollticks > hz) 2698 pollticks = hz; 2699 if (pollticks < 1) { 2700 HDA_BOOTVERBOSE( 2701 device_printf(sc->dev, 2702 "%s: pollticks=%d < 1 !\n", 2703 __func__, pollticks); 2704 ); 2705 pollticks = 1; 2706 } 2707 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2708 HDA_BOOTVERBOSE( 2709 if (hda_chan_active(sc) == 0) { 2710 device_printf(sc->dev, 2711 "%s: pollticks=%d\n", 2712 __func__, pollticks); 2713 } else { 2714 device_printf(sc->dev, 2715 "%s: pollticks %d -> %d\n", 2716 __func__, sc->poll_ticks, 2717 pollticks); 2718 } 2719 ); 2720 sc->poll_ticks = pollticks; 2721 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2722 sc); 2723 } 2724 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2725 ctl |= HDAC_SDCTL_RUN; 2726 } else { 2727 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2728 ctl |= 1 << (ch->off >> 5); 2729 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2730 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2731 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2732 HDAC_SDCTL_RUN; 2733 } 2734 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2735 2736 ch->flags |= HDAC_CHN_RUNNING; 2737} 2738 2739static void 2740hdac_stream_reset(struct hdac_chan *ch) 2741{ 2742 struct hdac_softc *sc = ch->devinfo->codec->sc; 2743 int timeout = 1000; 2744 int to = timeout; 2745 uint32_t ctl; 2746 2747 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2748 ctl |= HDAC_SDCTL_SRST; 2749 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2750 do { 2751 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2752 if (ctl & HDAC_SDCTL_SRST) 2753 break; 2754 DELAY(10); 2755 } while (--to); 2756 if (!(ctl & HDAC_SDCTL_SRST)) { 2757 device_printf(sc->dev, "timeout in reset\n"); 2758 } 2759 ctl &= ~HDAC_SDCTL_SRST; 2760 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2761 to = timeout; 2762 do { 2763 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2764 if (!(ctl & HDAC_SDCTL_SRST)) 2765 break; 2766 DELAY(10); 2767 } while (--to); 2768 if (ctl & HDAC_SDCTL_SRST) 2769 device_printf(sc->dev, "can't reset!\n"); 2770} 2771 2772static void 2773hdac_stream_setid(struct hdac_chan *ch) 2774{ 2775 struct hdac_softc *sc = ch->devinfo->codec->sc; 2776 uint32_t ctl; 2777 2778 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2779 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2780 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2781 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2782} 2783 2784static void 2785hdac_bdl_setup(struct hdac_chan *ch) 2786{ 2787 struct hdac_softc *sc = ch->devinfo->codec->sc; 2788 struct hdac_bdle *bdle; 2789 uint64_t addr; 2790 uint32_t blksz, blkcnt; 2791 int i; 2792 2793 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2794 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2795 2796 if (sc->polling != 0) { 2797 blksz = ch->blksz * ch->blkcnt; 2798 blkcnt = 1; 2799 } else { 2800 blksz = ch->blksz; 2801 blkcnt = ch->blkcnt; 2802 } 2803 2804 for (i = 0; i < blkcnt; i++, bdle++) { 2805 bdle->addrl = (uint32_t)addr; 2806 bdle->addrh = (uint32_t)(addr >> 32); 2807 bdle->len = blksz; 2808 bdle->ioc = 1 ^ sc->polling; 2809 addr += blksz; 2810 } 2811 2812 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2813 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2814 addr = ch->bdl_dma.dma_paddr; 2815 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2816 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2817 if (ch->dmapos != NULL && 2818 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2819 addr = sc->pos_dma.dma_paddr; 2820 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2821 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2822 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2823 } 2824} 2825 2826static int 2827hdac_bdl_alloc(struct hdac_chan *ch) 2828{ 2829 struct hdac_softc *sc = ch->devinfo->codec->sc; 2830 int rc; 2831 2832 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2833 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2834 if (rc) { 2835 device_printf(sc->dev, "can't alloc bdl\n"); 2836 return (rc); 2837 } 2838 2839 return (0); 2840} 2841 2842static void 2843hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2844 int index, int lmute, int rmute, 2845 int left, int right, int dir) 2846{ 2847 uint16_t v = 0; 2848 2849 if (sc == NULL) 2850 return; 2851 2852 if (left != right || lmute != rmute) { 2853 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2854 (lmute << 7) | left; 2855 hdac_command(sc, 2856 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2857 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2858 (rmute << 7) | right; 2859 } else 2860 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2861 (lmute << 7) | left; 2862 2863 hdac_command(sc, 2864 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2865} 2866 2867static void 2868hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2869 int left, int right) 2870{ 2871 struct hdac_softc *sc; 2872 nid_t nid, cad; 2873 int lmute, rmute; 2874 2875 if (ctl == NULL || ctl->widget == NULL || 2876 ctl->widget->devinfo == NULL || 2877 ctl->widget->devinfo->codec == NULL || 2878 ctl->widget->devinfo->codec->sc == NULL) 2879 return; 2880 2881 sc = ctl->widget->devinfo->codec->sc; 2882 cad = ctl->widget->devinfo->codec->cad; 2883 nid = ctl->widget->nid; 2884 2885 if (mute == HDA_AMP_MUTE_DEFAULT) { 2886 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2887 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2888 } else { 2889 lmute = HDA_AMP_LEFT_MUTED(mute); 2890 rmute = HDA_AMP_RIGHT_MUTED(mute); 2891 } 2892 2893 if (ctl->dir & HDA_CTL_OUT) 2894 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2895 lmute, rmute, left, right, 0); 2896 if (ctl->dir & HDA_CTL_IN) 2897 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2898 lmute, rmute, left, right, 1); 2899 ctl->left = left; 2900 ctl->right = right; 2901} 2902 2903static void 2904hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2905{ 2906 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2907 return; 2908 hdac_command(w->devinfo->codec->sc, 2909 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2910 w->nid, index), w->devinfo->codec->cad); 2911 w->selconn = index; 2912} 2913 2914 2915/**************************************************************************** 2916 * uint32_t hdac_command_sendone_internal 2917 * 2918 * Wrapper function that sends only one command to a given codec 2919 ****************************************************************************/ 2920static uint32_t 2921hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2922{ 2923 struct hdac_command_list cl; 2924 uint32_t response = HDAC_INVALID; 2925 2926 if (!hdac_lockowned(sc)) 2927 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2928 cl.num_commands = 1; 2929 cl.verbs = &verb; 2930 cl.responses = &response; 2931 2932 hdac_command_send_internal(sc, &cl, cad); 2933 2934 return (response); 2935} 2936 2937/**************************************************************************** 2938 * hdac_command_send_internal 2939 * 2940 * Send a command list to the codec via the corb. We queue as much verbs as 2941 * we can and msleep on the codec. When the interrupt get the responses 2942 * back from the rirb, it will wake us up so we can queue the remaining verbs 2943 * if any. 2944 ****************************************************************************/ 2945static void 2946hdac_command_send_internal(struct hdac_softc *sc, 2947 struct hdac_command_list *commands, nid_t cad) 2948{ 2949 struct hdac_codec *codec; 2950 int corbrp; 2951 uint32_t *corb; 2952 int timeout; 2953 int retry = 10; 2954 struct hdac_rirb *rirb_base; 2955 2956 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2957 commands->num_commands < 1) 2958 return; 2959 2960 codec = sc->codecs[cad]; 2961 codec->commands = commands; 2962 codec->responses_received = 0; 2963 codec->verbs_sent = 0; 2964 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2965 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2966 2967 do { 2968 if (codec->verbs_sent != commands->num_commands) { 2969 /* Queue as many verbs as possible */ 2970 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2971#if 0 2972 bus_dmamap_sync(sc->corb_dma.dma_tag, 2973 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2974#endif 2975 while (codec->verbs_sent != commands->num_commands && 2976 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2977 sc->corb_wp++; 2978 sc->corb_wp %= sc->corb_size; 2979 corb[sc->corb_wp] = 2980 commands->verbs[codec->verbs_sent++]; 2981 } 2982 2983 /* Send the verbs to the codecs */ 2984#if 0 2985 bus_dmamap_sync(sc->corb_dma.dma_tag, 2986 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2987#endif 2988 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2989 } 2990 2991 timeout = 1000; 2992 while (hdac_rirb_flush(sc) == 0 && --timeout) 2993 DELAY(10); 2994 } while ((codec->verbs_sent != commands->num_commands || 2995 codec->responses_received != commands->num_commands) && --retry); 2996 2997 if (retry == 0) 2998 device_printf(sc->dev, 2999 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3000 __func__, commands->num_commands, codec->verbs_sent, 3001 codec->responses_received); 3002 3003 codec->commands = NULL; 3004 codec->responses_received = 0; 3005 codec->verbs_sent = 0; 3006 3007 hdac_unsolq_flush(sc); 3008} 3009 3010 3011/**************************************************************************** 3012 * Device Methods 3013 ****************************************************************************/ 3014 3015/**************************************************************************** 3016 * int hdac_probe(device_t) 3017 * 3018 * Probe for the presence of an hdac. If none is found, check for a generic 3019 * match using the subclass of the device. 3020 ****************************************************************************/ 3021static int 3022hdac_probe(device_t dev) 3023{ 3024 int i, result; 3025 uint32_t model; 3026 uint16_t class, subclass; 3027 char desc[64]; 3028 3029 model = (uint32_t)pci_get_device(dev) << 16; 3030 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3031 class = pci_get_class(dev); 3032 subclass = pci_get_subclass(dev); 3033 3034 bzero(desc, sizeof(desc)); 3035 result = ENXIO; 3036 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3037 if (hdac_devices[i].model == model) { 3038 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3039 result = BUS_PROBE_DEFAULT; 3040 break; 3041 } 3042 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3043 class == PCIC_MULTIMEDIA && 3044 subclass == PCIS_MULTIMEDIA_HDA) { 3045 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3046 result = BUS_PROBE_GENERIC; 3047 break; 3048 } 3049 } 3050 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3051 subclass == PCIS_MULTIMEDIA_HDA) { 3052 strlcpy(desc, "Generic", sizeof(desc)); 3053 result = BUS_PROBE_GENERIC; 3054 } 3055 if (result != ENXIO) { 3056 strlcat(desc, " High Definition Audio Controller", 3057 sizeof(desc)); 3058 device_set_desc_copy(dev, desc); 3059 } 3060 3061 return (result); 3062} 3063 3064static void * 3065hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3066 struct pcm_channel *c, int dir) 3067{ 3068 struct hdac_devinfo *devinfo = data; 3069 struct hdac_softc *sc = devinfo->codec->sc; 3070 struct hdac_chan *ch; 3071 3072 hdac_lock(sc); 3073 if (dir == PCMDIR_PLAY) { 3074 ch = &sc->play; 3075 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3076 devinfo->function.audio.playcnt++; 3077 } else { 3078 ch = &sc->rec; 3079 ch->off = devinfo->function.audio.reccnt << 5; 3080 devinfo->function.audio.reccnt++; 3081 } 3082 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3083 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3084 ch->pcmrates[0] = 48000; 3085 ch->pcmrates[1] = 0; 3086 } 3087 if (sc->pos_dma.dma_vaddr != NULL) 3088 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3089 (sc->streamcnt * 8)); 3090 else 3091 ch->dmapos = NULL; 3092 ch->sid = ++sc->streamcnt; 3093 ch->dir = dir; 3094 ch->b = b; 3095 ch->c = c; 3096 ch->devinfo = devinfo; 3097 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3098 ch->blkcnt = sc->chan_blkcnt; 3099 hdac_unlock(sc); 3100 3101 if (hdac_bdl_alloc(ch) != 0) { 3102 ch->blkcnt = 0; 3103 return (NULL); 3104 } 3105 3106 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3107 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3108 sc->chan_size) != 0) 3109 return (NULL); 3110 3111 return (ch); 3112} 3113 3114static int 3115hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3116{ 3117 struct hdac_chan *ch = data; 3118 int i; 3119 3120 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3121 if (format == ch->caps.fmtlist[i]) { 3122 ch->fmt = format; 3123 return (0); 3124 } 3125 } 3126 3127 return (EINVAL); 3128} 3129 3130static int 3131hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3132{ 3133 struct hdac_chan *ch = data; 3134 uint32_t spd = 0, threshold; 3135 int i; 3136 3137 for (i = 0; ch->pcmrates[i] != 0; i++) { 3138 spd = ch->pcmrates[i]; 3139 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3140 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3141 if (speed < threshold) 3142 break; 3143 } 3144 3145 if (spd == 0) /* impossible */ 3146 ch->spd = 48000; 3147 else 3148 ch->spd = spd; 3149 3150 return (ch->spd); 3151} 3152 3153static void 3154hdac_stream_setup(struct hdac_chan *ch) 3155{ 3156 struct hdac_softc *sc = ch->devinfo->codec->sc; 3157 struct hdac_widget *w; 3158 int i, chn, totalchn; 3159 nid_t cad = ch->devinfo->codec->cad; 3160 uint16_t fmt; 3161 3162 fmt = 0; 3163 if (ch->fmt & AFMT_S16_LE) 3164 fmt |= ch->bit16 << 4; 3165 else if (ch->fmt & AFMT_S32_LE) 3166 fmt |= ch->bit32 << 4; 3167 else 3168 fmt |= 1 << 4; 3169 3170 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3171 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3172 fmt |= hda_rate_tab[i].base; 3173 fmt |= hda_rate_tab[i].mul; 3174 fmt |= hda_rate_tab[i].div; 3175 break; 3176 } 3177 } 3178 3179 if (ch->fmt & AFMT_STEREO) { 3180 fmt |= 1; 3181 totalchn = 2; 3182 } else 3183 totalchn = 1; 3184 3185 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3186 3187 chn = 0; 3188 for (i = 0; ch->io[i] != -1; i++) { 3189 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3190 if (w == NULL) 3191 continue; 3192 HDA_BOOTVERBOSE( 3193 device_printf(sc->dev, 3194 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3195 "fmt=0x%08x\n", 3196 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3197 ch->io[i], fmt); 3198 ); 3199 hdac_command(sc, 3200 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3201 if (ch->dir == PCMDIR_REC) 3202 hdac_command(sc, 3203 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3204 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), 3205 cad); 3206 else 3207 hdac_command(sc, 3208 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3209 ch->sid << 4), cad); 3210 chn += 3211 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3212 2 : 1; 3213 } 3214} 3215 3216static int 3217hdac_channel_setfragments(kobj_t obj, void *data, 3218 uint32_t blksz, uint32_t blkcnt) 3219{ 3220 struct hdac_chan *ch = data; 3221 struct hdac_softc *sc = ch->devinfo->codec->sc; 3222 3223 blksz &= HDA_BLK_ALIGN; 3224 3225 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3226 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3227 if (blksz < HDA_BLK_MIN) 3228 blksz = HDA_BLK_MIN; 3229 if (blkcnt > HDA_BDL_MAX) 3230 blkcnt = HDA_BDL_MAX; 3231 if (blkcnt < HDA_BDL_MIN) 3232 blkcnt = HDA_BDL_MIN; 3233 3234 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3235 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3236 blkcnt >>= 1; 3237 else if ((blksz >> 1) >= HDA_BLK_MIN) 3238 blksz >>= 1; 3239 else 3240 break; 3241 } 3242 3243 if ((sndbuf_getblksz(ch->b) != blksz || 3244 sndbuf_getblkcnt(ch->b) != blkcnt) && 3245 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3246 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3247 __func__, blksz, blkcnt); 3248 3249 ch->blksz = sndbuf_getblksz(ch->b); 3250 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3251 3252 return (1); 3253} 3254 3255static int 3256hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3257{ 3258 struct hdac_chan *ch = data; 3259 struct hdac_softc *sc = ch->devinfo->codec->sc; 3260 3261 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3262 3263 return (ch->blksz); 3264} 3265 3266static void 3267hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3268{ 3269 struct hdac_devinfo *devinfo = ch->devinfo; 3270 nid_t cad = devinfo->codec->cad; 3271 int i; 3272 3273 hdac_stream_stop(ch); 3274 3275 for (i = 0; ch->io[i] != -1; i++) { 3276 hdac_command(sc, 3277 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3278 0), cad); 3279 } 3280} 3281 3282static void 3283hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3284{ 3285 ch->ptr = 0; 3286 ch->prevptr = 0; 3287 hdac_stream_stop(ch); 3288 hdac_stream_reset(ch); 3289 hdac_bdl_setup(ch); 3290 hdac_stream_setid(ch); 3291 hdac_stream_setup(ch); 3292 hdac_stream_start(ch); 3293} 3294 3295static int 3296hdac_channel_trigger(kobj_t obj, void *data, int go) 3297{ 3298 struct hdac_chan *ch = data; 3299 struct hdac_softc *sc = ch->devinfo->codec->sc; 3300 3301 if (!PCMTRIG_COMMON(go)) 3302 return (0); 3303 3304 hdac_lock(sc); 3305 switch (go) { 3306 case PCMTRIG_START: 3307 hdac_channel_start(sc, ch); 3308 break; 3309 case PCMTRIG_STOP: 3310 case PCMTRIG_ABORT: 3311 hdac_channel_stop(sc, ch); 3312 break; 3313 default: 3314 break; 3315 } 3316 hdac_unlock(sc); 3317 3318 return (0); 3319} 3320 3321static int 3322hdac_channel_getptr(kobj_t obj, void *data) 3323{ 3324 struct hdac_chan *ch = data; 3325 struct hdac_softc *sc = ch->devinfo->codec->sc; 3326 uint32_t ptr; 3327 3328 hdac_lock(sc); 3329 if (sc->polling != 0) 3330 ptr = ch->ptr; 3331 else if (ch->dmapos != NULL) 3332 ptr = *(ch->dmapos); 3333 else 3334 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3335 hdac_unlock(sc); 3336 3337 /* 3338 * Round to available space and force 128 bytes aligment. 3339 */ 3340 ptr %= ch->blksz * ch->blkcnt; 3341 ptr &= HDA_BLK_ALIGN; 3342 3343 return (ptr); 3344} 3345 3346static struct pcmchan_caps * 3347hdac_channel_getcaps(kobj_t obj, void *data) 3348{ 3349 return (&((struct hdac_chan *)data)->caps); 3350} 3351 3352static kobj_method_t hdac_channel_methods[] = { 3353 KOBJMETHOD(channel_init, hdac_channel_init), 3354 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3355 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3356 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3357 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3358 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3359 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3360 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3361 { 0, 0 } 3362}; 3363CHANNEL_DECLARE(hdac_channel); 3364 3365static void 3366hdac_jack_poll_callback(void *arg) 3367{ 3368 struct hdac_devinfo *devinfo = arg; 3369 struct hdac_softc *sc; 3370 3371 if (devinfo == NULL || devinfo->codec == NULL || 3372 devinfo->codec->sc == NULL) 3373 return; 3374 sc = devinfo->codec->sc; 3375 hdac_lock(sc); 3376 if (sc->poll_ival == 0) { 3377 hdac_unlock(sc); 3378 return; 3379 } 3380 hdac_hp_switch_handler(devinfo); 3381 callout_reset(&sc->poll_jack, sc->poll_ival, 3382 hdac_jack_poll_callback, devinfo); 3383 hdac_unlock(sc); 3384} 3385 3386static int 3387hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3388{ 3389 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3390 struct hdac_softc *sc = devinfo->codec->sc; 3391 struct hdac_widget *w, *cw; 3392 struct hdac_audio_ctl *ctl; 3393 uint32_t mask, recmask, id; 3394 int i, j, softpcmvol; 3395 nid_t cad; 3396 3397 hdac_lock(sc); 3398 3399 mask = 0; 3400 recmask = 0; 3401 3402 id = hdac_codec_id(devinfo); 3403 cad = devinfo->codec->cad; 3404 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3405 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3406 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3407 continue; 3408 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3409 if (w == NULL || w->enable == 0 || w->type != 3410 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3411 continue; 3412 if (hdac_hp_switch[i].polling != 0) 3413 callout_reset(&sc->poll_jack, 1, 3414 hdac_jack_poll_callback, devinfo); 3415 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3416 hdac_command(sc, 3417 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3418 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3419 HDAC_UNSOLTAG_EVENT_HP), cad); 3420 else 3421 continue; 3422 hdac_hp_switch_handler(devinfo); 3423 HDA_BOOTVERBOSE( 3424 device_printf(sc->dev, 3425 "HDA_DEBUG: Enabling headphone/speaker " 3426 "audio routing switching:\n"); 3427 device_printf(sc->dev, 3428 "HDA_DEBUG: \tindex=%d nid=%d " 3429 "pci_subvendor=0x%08x " 3430 "codec=0x%08x [%s]\n", 3431 i, w->nid, sc->pci_subvendor, id, 3432 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3433 "UNSOL"); 3434 ); 3435 break; 3436 } 3437 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3438 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3439 sc->pci_subvendor) && 3440 hdac_eapd_switch[i].id == id)) 3441 continue; 3442 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3443 if (w == NULL || w->enable == 0) 3444 break; 3445 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3446 w->param.eapdbtl == HDAC_INVALID) 3447 break; 3448 mask |= SOUND_MASK_OGAIN; 3449 break; 3450 } 3451 3452 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3453 w = hdac_widget_get(devinfo, i); 3454 if (w == NULL || w->enable == 0) 3455 continue; 3456 mask |= w->ctlflags; 3457 if (!(w->pflags & HDA_ADC_RECSEL)) 3458 continue; 3459 for (j = 0; j < w->nconns; j++) { 3460 cw = hdac_widget_get(devinfo, w->conns[j]); 3461 if (cw == NULL || cw->enable == 0) 3462 continue; 3463 recmask |= cw->ctlflags; 3464 } 3465 } 3466 3467 if (!(mask & SOUND_MASK_PCM)) { 3468 softpcmvol = 1; 3469 mask |= SOUND_MASK_PCM; 3470 } else 3471 softpcmvol = (devinfo->function.audio.quirks & 3472 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3473 3474 i = 0; 3475 ctl = NULL; 3476 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3477 if (ctl->widget == NULL || ctl->enable == 0) 3478 continue; 3479 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3480 continue; 3481 if (ctl->step > 0) 3482 break; 3483 } 3484 3485 if (softpcmvol == 1 || ctl == NULL) { 3486 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3487 HDA_BOOTVERBOSE( 3488 device_printf(sc->dev, 3489 "HDA_DEBUG: %s Soft PCM volume\n", 3490 (softpcmvol == 1) ? 3491 "Forcing" : "Enabling"); 3492 ); 3493 i = 0; 3494 /* 3495 * XXX Temporary quirk for STAC9220, until the parser 3496 * become smarter. 3497 */ 3498 if (id == HDA_CODEC_STAC9220) { 3499 mask |= SOUND_MASK_VOLUME; 3500 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3501 NULL) { 3502 if (ctl->widget == NULL || ctl->enable == 0) 3503 continue; 3504 if (ctl->widget->nid == 11 && ctl->index == 0) { 3505 ctl->ossmask = SOUND_MASK_VOLUME; 3506 ctl->ossval = 100 | (100 << 8); 3507 } else 3508 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3509 } 3510 } else if (id == HDA_CODEC_STAC9221) { 3511 mask |= SOUND_MASK_VOLUME; 3512 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3513 NULL) { 3514 if (ctl->widget == NULL) 3515 continue; 3516 if (ctl->widget->type == 3517 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3518 ctl->index == 0 && (ctl->widget->nid == 2 || 3519 ctl->widget->enable != 0)) { 3520 ctl->enable = 1; 3521 ctl->ossmask = SOUND_MASK_VOLUME; 3522 ctl->ossval = 100 | (100 << 8); 3523 } else if (ctl->enable == 0) 3524 continue; 3525 else 3526 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3527 } 3528 } else { 3529 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3530 SOUND_MASK_PCM); 3531 if (!(mask & SOUND_MASK_VOLUME)) 3532 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3533 SOUND_MIXER_NONE); 3534 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3535 NULL) { 3536 if (ctl->widget == NULL || ctl->enable == 0) 3537 continue; 3538 if (!HDA_FLAG_MATCH(ctl->ossmask, 3539 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3540 continue; 3541 if (!(ctl->mute == 1 && ctl->step == 0)) 3542 ctl->enable = 0; 3543 } 3544 } 3545 } 3546 3547 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3548 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3549 SOUND_MASK_OGAIN); 3550 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3551 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3552 3553 mix_setrecdevs(m, recmask); 3554 mix_setdevs(m, mask); 3555 3556 hdac_unlock(sc); 3557 3558 return (0); 3559} 3560 3561static int 3562hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3563 unsigned left, unsigned right) 3564{ 3565 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3566 struct hdac_softc *sc = devinfo->codec->sc; 3567 struct hdac_widget *w; 3568 struct hdac_audio_ctl *ctl; 3569 uint32_t id, mute; 3570 int lvol, rvol, mlvol, mrvol; 3571 int i = 0; 3572 3573 hdac_lock(sc); 3574 if (dev == SOUND_MIXER_OGAIN) { 3575 uint32_t orig; 3576 /*if (left != right || !(left == 0 || left == 1)) { 3577 hdac_unlock(sc); 3578 return (-1); 3579 }*/ 3580 id = hdac_codec_id(devinfo); 3581 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3582 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3583 sc->pci_subvendor) && 3584 hdac_eapd_switch[i].id == id) 3585 break; 3586 } 3587 if (i >= HDAC_EAPD_SWITCH_LEN) { 3588 hdac_unlock(sc); 3589 return (-1); 3590 } 3591 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3592 if (w == NULL || 3593 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3594 w->param.eapdbtl == HDAC_INVALID) { 3595 hdac_unlock(sc); 3596 return (-1); 3597 } 3598 orig = w->param.eapdbtl; 3599 if (left == 0) 3600 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3601 else 3602 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3603 if (orig != w->param.eapdbtl) { 3604 uint32_t val; 3605 3606 if (hdac_eapd_switch[i].hp_switch != 0) 3607 hdac_hp_switch_handler(devinfo); 3608 val = w->param.eapdbtl; 3609 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3610 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3611 hdac_command(sc, 3612 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3613 w->nid, val), devinfo->codec->cad); 3614 } 3615 hdac_unlock(sc); 3616 return (left | (left << 8)); 3617 } 3618 if (dev == SOUND_MIXER_VOLUME) 3619 devinfo->function.audio.mvol = left | (right << 8); 3620 3621 mlvol = devinfo->function.audio.mvol & 0x7f; 3622 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3623 lvol = 0; 3624 rvol = 0; 3625 3626 i = 0; 3627 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3628 if (ctl->widget == NULL || ctl->enable == 0 || 3629 !(ctl->ossmask & (1 << dev))) 3630 continue; 3631 switch (dev) { 3632 case SOUND_MIXER_VOLUME: 3633 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3634 lvol = (lvol * ctl->step) / 100; 3635 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3636 rvol = (rvol * ctl->step) / 100; 3637 break; 3638 default: 3639 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3640 lvol = (left * mlvol) / 100; 3641 lvol = (lvol * ctl->step) / 100; 3642 rvol = (right * mrvol) / 100; 3643 rvol = (rvol * ctl->step) / 100; 3644 } else { 3645 lvol = (left * ctl->step) / 100; 3646 rvol = (right * ctl->step) / 100; 3647 } 3648 ctl->ossval = left | (right << 8); 3649 break; 3650 } 3651 mute = 0; 3652 if (ctl->step < 1) { 3653 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3654 (ctl->muted & HDA_AMP_MUTE_LEFT); 3655 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3656 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3657 } else { 3658 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3659 (ctl->muted & HDA_AMP_MUTE_LEFT); 3660 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3661 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3662 } 3663 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3664 } 3665 hdac_unlock(sc); 3666 3667 return (left | (right << 8)); 3668} 3669 3670static int 3671hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3672{ 3673 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3674 struct hdac_widget *w, *cw; 3675 struct hdac_softc *sc = devinfo->codec->sc; 3676 uint32_t ret = src, target; 3677 int i, j; 3678 3679 target = 0; 3680 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3681 if (src & (1 << i)) { 3682 target = 1 << i; 3683 break; 3684 } 3685 } 3686 3687 hdac_lock(sc); 3688 3689 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3690 w = hdac_widget_get(devinfo, i); 3691 if (w == NULL || w->enable == 0) 3692 continue; 3693 if (!(w->pflags & HDA_ADC_RECSEL)) 3694 continue; 3695 for (j = 0; j < w->nconns; j++) { 3696 cw = hdac_widget_get(devinfo, w->conns[j]); 3697 if (cw == NULL || cw->enable == 0) 3698 continue; 3699 if ((target == SOUND_MASK_VOLUME && 3700 cw->type != 3701 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3702 (target != SOUND_MASK_VOLUME && 3703 cw->type == 3704 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3705 continue; 3706 if (cw->ctlflags & target) { 3707 if (!(w->pflags & HDA_ADC_LOCKED)) 3708 hdac_widget_connection_select(w, j); 3709 ret = target; 3710 j += w->nconns; 3711 } 3712 } 3713 } 3714 3715 hdac_unlock(sc); 3716 3717 return (ret); 3718} 3719 3720static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3721 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3722 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3723 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3724 { 0, 0 } 3725}; 3726MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3727 3728static void 3729hdac_unsolq_task(void *context, int pending) 3730{ 3731 struct hdac_softc *sc; 3732 3733 sc = (struct hdac_softc *)context; 3734 3735 hdac_lock(sc); 3736 hdac_unsolq_flush(sc); 3737 hdac_unlock(sc); 3738} 3739 3740/**************************************************************************** 3741 * int hdac_attach(device_t) 3742 * 3743 * Attach the device into the kernel. Interrupts usually won't be enabled 3744 * when this function is called. Setup everything that doesn't require 3745 * interrupts and defer probing of codecs until interrupts are enabled. 3746 ****************************************************************************/ 3747static int 3748hdac_attach(device_t dev) 3749{ 3750 struct hdac_softc *sc; 3751 int result; 3752 int i; 3753 uint16_t vendor; 3754 uint8_t v; 3755 3756 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3757 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3758 sc->dev = dev; 3759 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3760 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3761 vendor = pci_get_vendor(dev); 3762 3763 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3764 /* Screw nx6325 - subdevice/subvendor swapped */ 3765 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3766 } 3767 3768 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3769 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3770 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3771 3772 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3773 3774 sc->poll_ticks = 1; 3775 sc->poll_ival = HDAC_POLL_INTERVAL; 3776 if (resource_int_value(device_get_name(dev), 3777 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3778 sc->polling = 1; 3779 else 3780 sc->polling = 0; 3781 3782 sc->chan_size = pcm_getbuffersize(dev, 3783 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3784 3785 if (resource_int_value(device_get_name(dev), 3786 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3787 i &= HDA_BLK_ALIGN; 3788 if (i < HDA_BLK_MIN) 3789 i = HDA_BLK_MIN; 3790 sc->chan_blkcnt = sc->chan_size / i; 3791 i = 0; 3792 while (sc->chan_blkcnt >> i) 3793 i++; 3794 sc->chan_blkcnt = 1 << (i - 1); 3795 if (sc->chan_blkcnt < HDA_BDL_MIN) 3796 sc->chan_blkcnt = HDA_BDL_MIN; 3797 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3798 sc->chan_blkcnt = HDA_BDL_MAX; 3799 } else 3800 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3801 3802 result = bus_dma_tag_create(NULL, /* parent */ 3803 HDAC_DMA_ALIGNMENT, /* alignment */ 3804 0, /* boundary */ 3805 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3806 BUS_SPACE_MAXADDR, /* highaddr */ 3807 NULL, /* filtfunc */ 3808 NULL, /* fistfuncarg */ 3809 sc->chan_size, /* maxsize */ 3810 1, /* nsegments */ 3811 sc->chan_size, /* maxsegsz */ 3812 0, /* flags */ 3813 NULL, /* lockfunc */ 3814 NULL, /* lockfuncarg */ 3815 &sc->chan_dmat); /* dmat */ 3816 if (result != 0) { 3817 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3818 __func__, result); 3819 snd_mtxfree(sc->lock); 3820 free(sc, M_DEVBUF); 3821 return (ENXIO); 3822 } 3823 3824 3825 sc->hdabus = NULL; 3826 for (i = 0; i < HDAC_CODEC_MAX; i++) 3827 sc->codecs[i] = NULL; 3828 3829 pci_enable_busmaster(dev); 3830 3831 if (vendor == INTEL_VENDORID) { 3832 /* TCSEL -> TC0 */ 3833 v = pci_read_config(dev, 0x44, 1); 3834 pci_write_config(dev, 0x44, v & 0xf8, 1); 3835 HDA_BOOTVERBOSE( 3836 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3837 pci_read_config(dev, 0x44, 1)); 3838 ); 3839 } 3840 3841#ifdef HDAC_MSI_ENABLED 3842 if (resource_int_value(device_get_name(dev), 3843 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3844 pci_msi_count(dev) == 1) 3845 sc->flags |= HDAC_F_MSI; 3846 else 3847#endif 3848 sc->flags &= ~HDAC_F_MSI; 3849 3850#if defined(__i386__) || defined(__amd64__) 3851 sc->flags |= HDAC_F_DMA_NOCACHE; 3852 3853 if (resource_int_value(device_get_name(dev), 3854 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3855#else 3856 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3857#endif 3858 /* 3859 * Try to enable PCIe snoop to avoid messing around with 3860 * uncacheable DMA attribute. Since PCIe snoop register 3861 * config is pretty much vendor specific, there are no 3862 * general solutions on how to enable it, forcing us (even 3863 * Microsoft) to enable uncacheable or write combined DMA 3864 * by default. 3865 * 3866 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3867 */ 3868 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3869 if (hdac_pcie_snoop[i].vendor != vendor) 3870 continue; 3871 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3872 if (hdac_pcie_snoop[i].reg == 0x00) 3873 break; 3874 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3875 if ((v & hdac_pcie_snoop[i].enable) == 3876 hdac_pcie_snoop[i].enable) 3877 break; 3878 v &= hdac_pcie_snoop[i].mask; 3879 v |= hdac_pcie_snoop[i].enable; 3880 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3881 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3882 if ((v & hdac_pcie_snoop[i].enable) != 3883 hdac_pcie_snoop[i].enable) { 3884 HDA_BOOTVERBOSE( 3885 device_printf(dev, 3886 "WARNING: Failed to enable PCIe " 3887 "snoop!\n"); 3888 ); 3889#if defined(__i386__) || defined(__amd64__) 3890 sc->flags |= HDAC_F_DMA_NOCACHE; 3891#endif 3892 } 3893 break; 3894 } 3895#if defined(__i386__) || defined(__amd64__) 3896 } 3897#endif 3898 3899 HDA_BOOTVERBOSE( 3900 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3901 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3902 "Uncacheable" : "PCIe snoop", vendor); 3903 ); 3904 3905 /* Allocate resources */ 3906 result = hdac_mem_alloc(sc); 3907 if (result != 0) 3908 goto hdac_attach_fail; 3909 result = hdac_irq_alloc(sc); 3910 if (result != 0) 3911 goto hdac_attach_fail; 3912 3913 /* Get Capabilities */ 3914 result = hdac_get_capabilities(sc); 3915 if (result != 0) 3916 goto hdac_attach_fail; 3917 3918 /* Allocate CORB and RIRB dma memory */ 3919 result = hdac_dma_alloc(sc, &sc->corb_dma, 3920 sc->corb_size * sizeof(uint32_t)); 3921 if (result != 0) 3922 goto hdac_attach_fail; 3923 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3924 sc->rirb_size * sizeof(struct hdac_rirb)); 3925 if (result != 0) 3926 goto hdac_attach_fail; 3927 3928 /* Quiesce everything */ 3929 hdac_reset(sc); 3930 3931 /* Initialize the CORB and RIRB */ 3932 hdac_corb_init(sc); 3933 hdac_rirb_init(sc); 3934 3935 /* Defer remaining of initialization until interrupts are enabled */ 3936 sc->intrhook.ich_func = hdac_attach2; 3937 sc->intrhook.ich_arg = (void *)sc; 3938 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3939 sc->intrhook.ich_func = NULL; 3940 hdac_attach2((void *)sc); 3941 } 3942 3943 return (0); 3944 3945hdac_attach_fail: 3946 hdac_irq_free(sc); 3947 hdac_dma_free(sc, &sc->rirb_dma); 3948 hdac_dma_free(sc, &sc->corb_dma); 3949 hdac_mem_free(sc); 3950 snd_mtxfree(sc->lock); 3951 free(sc, M_DEVBUF); 3952 3953 return (ENXIO); 3954} 3955 3956static void 3957hdac_audio_parse(struct hdac_devinfo *devinfo) 3958{ 3959 struct hdac_softc *sc = devinfo->codec->sc; 3960 struct hdac_widget *w; 3961 uint32_t res; 3962 int i; 3963 nid_t cad, nid; 3964 3965 cad = devinfo->codec->cad; 3966 nid = devinfo->nid; 3967 3968 hdac_command(sc, 3969 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3970 3971 DELAY(100); 3972 3973 res = hdac_command(sc, 3974 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3975 3976 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3977 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3978 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3979 3980 res = hdac_command(sc, 3981 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3982 devinfo->function.audio.gpio = res; 3983 3984 HDA_BOOTVERBOSE( 3985 device_printf(sc->dev, " Vendor: 0x%08x\n", 3986 devinfo->vendor_id); 3987 device_printf(sc->dev, " Device: 0x%08x\n", 3988 devinfo->device_id); 3989 device_printf(sc->dev, " Revision: 0x%08x\n", 3990 devinfo->revision_id); 3991 device_printf(sc->dev, " Stepping: 0x%08x\n", 3992 devinfo->stepping_id); 3993 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3994 sc->pci_subvendor); 3995 device_printf(sc->dev, " Nodes: start=%d " 3996 "endnode=%d total=%d\n", 3997 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3998 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3999 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 4000 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 4001 sc->num_iss, sc->num_oss, sc->num_bss); 4002 device_printf(sc->dev, " GPIO: 0x%08x\n", 4003 devinfo->function.audio.gpio); 4004 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 4005 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4006 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4007 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4008 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4009 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4010 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4011 ); 4012 4013 res = hdac_command(sc, 4014 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4015 cad); 4016 devinfo->function.audio.supp_stream_formats = res; 4017 4018 res = hdac_command(sc, 4019 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4020 cad); 4021 devinfo->function.audio.supp_pcm_size_rate = res; 4022 4023 res = hdac_command(sc, 4024 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4025 cad); 4026 devinfo->function.audio.outamp_cap = res; 4027 4028 res = hdac_command(sc, 4029 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4030 cad); 4031 devinfo->function.audio.inamp_cap = res; 4032 4033 if (devinfo->nodecnt > 0) 4034 devinfo->widget = (struct hdac_widget *)malloc( 4035 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 4036 M_NOWAIT | M_ZERO); 4037 else 4038 devinfo->widget = NULL; 4039 4040 if (devinfo->widget == NULL) { 4041 device_printf(sc->dev, "unable to allocate widgets!\n"); 4042 devinfo->endnode = devinfo->startnode; 4043 devinfo->nodecnt = 0; 4044 return; 4045 } 4046 4047 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4048 w = hdac_widget_get(devinfo, i); 4049 if (w == NULL) 4050 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4051 else { 4052 w->devinfo = devinfo; 4053 w->nid = i; 4054 w->enable = 1; 4055 w->selconn = -1; 4056 w->pflags = 0; 4057 w->ctlflags = 0; 4058 w->param.eapdbtl = HDAC_INVALID; 4059 hdac_widget_parse(w); 4060 } 4061 } 4062} 4063 4064static void 4065hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4066{ 4067 struct hdac_softc *sc = devinfo->codec->sc; 4068 struct hdac_audio_ctl *ctls; 4069 struct hdac_widget *w, *cw; 4070 int i, j, cnt, max, ocap, icap; 4071 int mute, offset, step, size; 4072 4073 /* XXX This is redundant */ 4074 max = 0; 4075 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4076 w = hdac_widget_get(devinfo, i); 4077 if (w == NULL || w->enable == 0) 4078 continue; 4079 if (w->param.outamp_cap != 0) 4080 max++; 4081 if (w->param.inamp_cap != 0) { 4082 switch (w->type) { 4083 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4084 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4085 for (j = 0; j < w->nconns; j++) { 4086 cw = hdac_widget_get(devinfo, 4087 w->conns[j]); 4088 if (cw == NULL || cw->enable == 0) 4089 continue; 4090 max++; 4091 } 4092 break; 4093 default: 4094 max++; 4095 break; 4096 } 4097 } 4098 } 4099 4100 devinfo->function.audio.ctlcnt = max; 4101 4102 if (max < 1) 4103 return; 4104 4105 ctls = (struct hdac_audio_ctl *)malloc( 4106 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4107 4108 if (ctls == NULL) { 4109 /* Blekh! */ 4110 device_printf(sc->dev, "unable to allocate ctls!\n"); 4111 devinfo->function.audio.ctlcnt = 0; 4112 return; 4113 } 4114 4115 cnt = 0; 4116 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4117 if (cnt >= max) { 4118 device_printf(sc->dev, "%s: Ctl overflow!\n", 4119 __func__); 4120 break; 4121 } 4122 w = hdac_widget_get(devinfo, i); 4123 if (w == NULL || w->enable == 0) 4124 continue; 4125 ocap = w->param.outamp_cap; 4126 icap = w->param.inamp_cap; 4127 if (ocap != 0) { 4128 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4129 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4130 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4131 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4132 /*if (offset > step) { 4133 HDA_BOOTVERBOSE( 4134 device_printf(sc->dev, 4135 "HDA_DEBUG: BUGGY outamp: nid=%d " 4136 "[offset=%d > step=%d]\n", 4137 w->nid, offset, step); 4138 ); 4139 offset = step; 4140 }*/ 4141 ctls[cnt].enable = 1; 4142 ctls[cnt].widget = w; 4143 ctls[cnt].mute = mute; 4144 ctls[cnt].step = step; 4145 ctls[cnt].size = size; 4146 ctls[cnt].offset = offset; 4147 ctls[cnt].left = offset; 4148 ctls[cnt].right = offset; 4149 ctls[cnt++].dir = HDA_CTL_OUT; 4150 } 4151 4152 if (icap != 0) { 4153 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4154 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4155 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4156 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4157 /*if (offset > step) { 4158 HDA_BOOTVERBOSE( 4159 device_printf(sc->dev, 4160 "HDA_DEBUG: BUGGY inamp: nid=%d " 4161 "[offset=%d > step=%d]\n", 4162 w->nid, offset, step); 4163 ); 4164 offset = step; 4165 }*/ 4166 switch (w->type) { 4167 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4168 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4169 for (j = 0; j < w->nconns; j++) { 4170 if (cnt >= max) { 4171 device_printf(sc->dev, 4172 "%s: Ctl overflow!\n", 4173 __func__); 4174 break; 4175 } 4176 cw = hdac_widget_get(devinfo, 4177 w->conns[j]); 4178 if (cw == NULL || cw->enable == 0) 4179 continue; 4180 ctls[cnt].enable = 1; 4181 ctls[cnt].widget = w; 4182 ctls[cnt].childwidget = cw; 4183 ctls[cnt].index = j; 4184 ctls[cnt].mute = mute; 4185 ctls[cnt].step = step; 4186 ctls[cnt].size = size; 4187 ctls[cnt].offset = offset; 4188 ctls[cnt].left = offset; 4189 ctls[cnt].right = offset; 4190 ctls[cnt++].dir = HDA_CTL_IN; 4191 } 4192 break; 4193 default: 4194 if (cnt >= max) { 4195 device_printf(sc->dev, 4196 "%s: Ctl overflow!\n", 4197 __func__); 4198 break; 4199 } 4200 ctls[cnt].enable = 1; 4201 ctls[cnt].widget = w; 4202 ctls[cnt].mute = mute; 4203 ctls[cnt].step = step; 4204 ctls[cnt].size = size; 4205 ctls[cnt].offset = offset; 4206 ctls[cnt].left = offset; 4207 ctls[cnt].right = offset; 4208 ctls[cnt++].dir = HDA_CTL_IN; 4209 break; 4210 } 4211 } 4212 } 4213 4214 devinfo->function.audio.ctl = ctls; 4215} 4216 4217static const struct { 4218 uint32_t model; 4219 uint32_t id; 4220 uint32_t set, unset; 4221} hdac_quirks[] = { 4222 /* 4223 * XXX Force stereo quirk. Monoural recording / playback 4224 * on few codecs (especially ALC880) seems broken or 4225 * perhaps unsupported. 4226 */ 4227 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4228 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4229 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4230 HDA_QUIRK_GPIO0, 0 }, 4231 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4232 HDA_QUIRK_GPIO0, 0 }, 4233 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4234 HDA_QUIRK_GPIO0, 0 }, 4235 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4236 HDA_QUIRK_GPIO0, 0 }, 4237 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4238 HDA_QUIRK_GPIO0, 0 }, 4239 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4240 HDA_QUIRK_GPIO0, 0 }, 4241 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4242 HDA_QUIRK_EAPDINV, 0 }, 4243 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4244 HDA_QUIRK_EAPDINV, 0 }, 4245 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4246 HDA_QUIRK_OVREF, 0 }, 4247 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4248 HDA_QUIRK_OVREF, 0 }, 4249 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4250 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4251 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4252 HDA_QUIRK_GPIO1, 0 }, 4253 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4254 HDA_QUIRK_EAPDINV, 0 }, 4255 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4256 HDA_QUIRK_EAPDINV, 0 }, 4257 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4258 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4259 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4260 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4261 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205, 4262 HDA_QUIRK_GPIO0, 0 }, 4263 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205, 4264 HDA_QUIRK_GPIO0, 0 }, 4265 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4266 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4267 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4268 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4269 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4270 0, HDA_QUIRK_FORCESTEREO }, 4271 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4272 HDA_QUIRK_SOFTPCMVOL, 0 } 4273}; 4274#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4275 4276static void 4277hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4278{ 4279 struct hdac_widget *w; 4280 struct hdac_audio_ctl *ctl; 4281 uint32_t id, subvendor; 4282 int i; 4283 4284 id = hdac_codec_id(devinfo); 4285 subvendor = devinfo->codec->sc->pci_subvendor; 4286 4287 /* 4288 * Quirks 4289 */ 4290 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4291 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4292 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4293 continue; 4294 if (hdac_quirks[i].set != 0) 4295 devinfo->function.audio.quirks |= 4296 hdac_quirks[i].set; 4297 if (hdac_quirks[i].unset != 0) 4298 devinfo->function.audio.quirks &= 4299 ~(hdac_quirks[i].unset); 4300 } 4301 4302 switch (id) { 4303 case HDA_CODEC_ALC260: 4304 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4305 w = hdac_widget_get(devinfo, i); 4306 if (w == NULL || w->enable == 0) 4307 continue; 4308 if (w->type != 4309 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4310 continue; 4311 if (w->nid != 5) 4312 w->enable = 0; 4313 } 4314 if (subvendor == HP_XW4300_SUBVENDOR) { 4315 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4316 if (ctl != NULL && ctl->widget != NULL) { 4317 ctl->ossmask = SOUND_MASK_SPEAKER; 4318 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4319 } 4320 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4321 if (ctl != NULL && ctl->widget != NULL) { 4322 ctl->ossmask = SOUND_MASK_SPEAKER; 4323 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4324 } 4325 } else if (subvendor == HP_3010_SUBVENDOR) { 4326 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4327 if (ctl != NULL && ctl->widget != NULL) { 4328 ctl->ossmask = SOUND_MASK_SPEAKER; 4329 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4330 } 4331 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4332 if (ctl != NULL && ctl->widget != NULL) { 4333 ctl->ossmask = SOUND_MASK_SPEAKER; 4334 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4335 } 4336 } 4337 break; 4338 case HDA_CODEC_ALC262: 4339 if (subvendor == HP_DC7700S_SUBVENDOR) { 4340 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4341 if (ctl != NULL && ctl->widget != NULL) { 4342 ctl->ossmask = SOUND_MASK_PHONEOUT; 4343 ctl->widget->ctlflags |= SOUND_MASK_PHONEOUT; 4344 } 4345 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4346 if (ctl != NULL && ctl->widget != NULL) { 4347 ctl->ossmask = SOUND_MASK_SPEAKER; 4348 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4349 } 4350 } else if (subvendor == HP_DC7700_SUBVENDOR) { 4351 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4352 if (ctl != NULL && ctl->widget != NULL) { 4353 ctl->ossmask = SOUND_MASK_SPEAKER; 4354 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4355 } 4356 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4357 if (ctl != NULL && ctl->widget != NULL) { 4358 ctl->ossmask = SOUND_MASK_SPEAKER; 4359 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4360 } 4361 } 4362 break; 4363 case HDA_CODEC_ALC268: 4364 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) { 4365 w = hdac_widget_get(devinfo, 29); 4366 if (w != NULL) { 4367 w->enable = 1; 4368 w->type = 4369 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4370 w->param.widget_cap &= 4371 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4372 w->param.widget_cap |= 4373 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4374 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4375 strlcpy(w->name, "beep widget", sizeof(w->name)); 4376 } 4377 } 4378 break; 4379 case HDA_CODEC_ALC861: 4380 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4381 if (ctl != NULL) 4382 ctl->muted = HDA_AMP_MUTE_ALL; 4383 break; 4384 case HDA_CODEC_ALC880: 4385 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4386 w = hdac_widget_get(devinfo, i); 4387 if (w == NULL || w->enable == 0) 4388 continue; 4389 if (w->type == 4390 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4391 w->nid != 9 && w->nid != 29) { 4392 w->enable = 0; 4393 } else if (w->type != 4394 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4395 w->nid == 29) { 4396 w->type = 4397 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4398 w->param.widget_cap &= 4399 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4400 w->param.widget_cap |= 4401 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4402 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4403 strlcpy(w->name, "beep widget", sizeof(w->name)); 4404 } 4405 } 4406 break; 4407 case HDA_CODEC_ALC883: 4408 /* 4409 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4410 * Clear vref cap for jack connectivity. 4411 */ 4412 w = hdac_widget_get(devinfo, 24); 4413 if (w != NULL && w->enable != 0 && w->type == 4414 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4415 (w->wclass.pin.config & 4416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4417 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4418 w->wclass.pin.cap &= ~( 4419 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4420 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4421 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4422 w = hdac_widget_get(devinfo, 25); 4423 if (w != NULL && w->enable != 0 && w->type == 4424 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4425 (w->wclass.pin.config & 4426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4427 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4428 w->wclass.pin.cap &= ~( 4429 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4430 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4431 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4432 /* 4433 * nid: 26 = Line-in, leave it alone. 4434 */ 4435 break; 4436 case HDA_CODEC_AD1981HD: 4437 w = hdac_widget_get(devinfo, 11); 4438 if (w != NULL && w->enable != 0 && w->nconns > 3) 4439 w->selconn = 3; 4440 if (subvendor == IBM_M52_SUBVENDOR) { 4441 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4442 if (ctl != NULL) 4443 ctl->ossmask = SOUND_MASK_SPEAKER; 4444 } 4445 break; 4446 case HDA_CODEC_AD1986A: 4447 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4448 w = hdac_widget_get(devinfo, i); 4449 if (w == NULL || w->enable == 0) 4450 continue; 4451 if (w->type != 4452 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4453 continue; 4454 if (w->nid != 3) 4455 w->enable = 0; 4456 } 4457 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4458 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4459 /* nid 28 is mic, nid 29 is line-in */ 4460 w = hdac_widget_get(devinfo, 15); 4461 if (w != NULL) 4462 w->selconn = 2; 4463 w = hdac_widget_get(devinfo, 16); 4464 if (w != NULL) 4465 w->selconn = 1; 4466 } else if (subvendor == ASUS_A8X_SUBVENDOR) { 4467 /* 4468 * This is just plain ridiculous.. There 4469 * are several A8 series that share the same 4470 * pci id but works differently (EAPD). 4471 */ 4472 w = hdac_widget_get(devinfo, 26); 4473 if (w != NULL && w->type == 4474 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4475 (w->wclass.pin.config & 4476 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4477 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4478 devinfo->function.audio.quirks &= 4479 ~HDA_QUIRK_EAPDINV; 4480 } 4481 break; 4482 case HDA_CODEC_AD1988: 4483 case HDA_CODEC_AD1988B: 4484 /*w = hdac_widget_get(devinfo, 12); 4485 if (w != NULL) { 4486 w->selconn = 1; 4487 w->pflags |= HDA_ADC_LOCKED; 4488 } 4489 w = hdac_widget_get(devinfo, 13); 4490 if (w != NULL) { 4491 w->selconn = 4; 4492 w->pflags |= HDA_ADC_LOCKED; 4493 } 4494 w = hdac_widget_get(devinfo, 14); 4495 if (w != NULL) { 4496 w->selconn = 2; 4497 w->pflags |= HDA_ADC_LOCKED; 4498 }*/ 4499 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4500 if (ctl != NULL) { 4501 ctl->ossmask = SOUND_MASK_IGAIN; 4502 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4503 } 4504 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4505 if (ctl != NULL) { 4506 ctl->ossmask = SOUND_MASK_IGAIN; 4507 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4508 } 4509 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4510 if (ctl != NULL) { 4511 ctl->ossmask = SOUND_MASK_IGAIN; 4512 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4513 } 4514 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4515 if (ctl != NULL) { 4516 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4517 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4518 } 4519 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4520 if (ctl != NULL) { 4521 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4522 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4523 } 4524 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4525 if (ctl != NULL) { 4526 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4527 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4528 } 4529 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4530 if (ctl != NULL) { 4531 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4532 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4533 } 4534 break; 4535 case HDA_CODEC_STAC9205: 4536 if ((subvendor == DELL_V1500_SUBVENDOR) || 4537 (subvendor == DELL_D630_SUBVENDOR)) { 4538 w = hdac_widget_get(devinfo, 29); 4539 if (w != NULL) 4540 w->selconn = 1; 4541 w = hdac_widget_get(devinfo, 30); 4542 if (w != NULL) 4543 w->selconn = 1; 4544 } 4545 break; 4546 case HDA_CODEC_STAC9221: 4547 /* 4548 * Dell XPS M1210 need all DACs for each output jacks 4549 */ 4550 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4551 break; 4552 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4553 w = hdac_widget_get(devinfo, i); 4554 if (w == NULL || w->enable == 0) 4555 continue; 4556 if (w->type != 4557 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4558 continue; 4559 if (w->nid != 2) 4560 w->enable = 0; 4561 } 4562 break; 4563 case HDA_CODEC_STAC9221D: 4564 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4565 w = hdac_widget_get(devinfo, i); 4566 if (w == NULL || w->enable == 0) 4567 continue; 4568 if (w->type == 4569 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4570 w->nid != 6) 4571 w->enable = 0; 4572 4573 } 4574 break; 4575 case HDA_CODEC_STAC9227: 4576 w = hdac_widget_get(devinfo, 8); 4577 if (w != NULL) 4578 w->enable = 0; 4579 w = hdac_widget_get(devinfo, 9); 4580 if (w != NULL) 4581 w->enable = 0; 4582 break; 4583 case HDA_CODEC_CXWAIKIKI: 4584 if (subvendor == HP_DV5000_SUBVENDOR) { 4585 w = hdac_widget_get(devinfo, 27); 4586 if (w != NULL) 4587 w->enable = 0; 4588 } 4589 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4590 if (ctl != NULL) 4591 ctl->ossmask = SOUND_MASK_SKIP; 4592 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4593 if (ctl != NULL && ctl->childwidget != NULL && 4594 ctl->childwidget->enable != 0) { 4595 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4596 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4597 } 4598 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4599 if (ctl != NULL && ctl->childwidget != NULL && 4600 ctl->childwidget->enable != 0) { 4601 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4602 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4603 } 4604 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4605 if (ctl != NULL && ctl->childwidget != NULL && 4606 ctl->childwidget->enable != 0) { 4607 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4608 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4609 } 4610 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4611 if (ctl != NULL) { 4612 ctl->ossmask = SOUND_MASK_SKIP; 4613 /* XXX mixer \=rec mic broken.. why?!? */ 4614 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4615 } 4616 break; 4617 default: 4618 break; 4619 } 4620} 4621 4622static int 4623hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4624{ 4625 int *dev = &devinfo->function.audio.ossidx; 4626 4627 while (*dev < SOUND_MIXER_NRDEVICES) { 4628 switch (*dev) { 4629 case SOUND_MIXER_VOLUME: 4630 case SOUND_MIXER_BASS: 4631 case SOUND_MIXER_TREBLE: 4632 case SOUND_MIXER_PCM: 4633 case SOUND_MIXER_SPEAKER: 4634 case SOUND_MIXER_LINE: 4635 case SOUND_MIXER_MIC: 4636 case SOUND_MIXER_CD: 4637 case SOUND_MIXER_RECLEV: 4638 case SOUND_MIXER_IGAIN: 4639 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4640 (*dev)++; 4641 break; 4642 default: 4643 return (*dev)++; 4644 break; 4645 } 4646 } 4647 4648 return (-1); 4649} 4650 4651static int 4652hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4653{ 4654 struct hdac_widget *w; 4655 int i, ret = 0; 4656 4657 if (depth > HDA_PARSE_MAXDEPTH) 4658 return (0); 4659 w = hdac_widget_get(devinfo, nid); 4660 if (w == NULL || w->enable == 0) 4661 return (0); 4662 switch (w->type) { 4663 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4664 w->pflags |= HDA_DAC_PATH; 4665 ret = 1; 4666 break; 4667 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4668 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4669 for (i = 0; i < w->nconns; i++) { 4670 if (hdac_widget_find_dac_path(devinfo, 4671 w->conns[i], depth + 1) != 0) { 4672 if (w->selconn == -1) 4673 w->selconn = i; 4674 ret = 1; 4675 w->pflags |= HDA_DAC_PATH; 4676 } 4677 } 4678 break; 4679 default: 4680 break; 4681 } 4682 return (ret); 4683} 4684 4685static int 4686hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4687{ 4688 struct hdac_widget *w; 4689 int i, conndev, ret = 0; 4690 4691 if (depth > HDA_PARSE_MAXDEPTH) 4692 return (0); 4693 w = hdac_widget_get(devinfo, nid); 4694 if (w == NULL || w->enable == 0) 4695 return (0); 4696 switch (w->type) { 4697 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4698 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4699 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4700 for (i = 0; i < w->nconns; i++) { 4701 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4702 depth + 1) != 0) { 4703 if (w->selconn == -1) 4704 w->selconn = i; 4705 w->pflags |= HDA_ADC_PATH; 4706 ret = 1; 4707 } 4708 } 4709 break; 4710 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4711 conndev = w->wclass.pin.config & 4712 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4713 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4714 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4715 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4716 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4717 w->pflags |= HDA_ADC_PATH; 4718 ret = 1; 4719 } 4720 break; 4721 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4722 if (w->pflags & HDA_DAC_PATH) { 4723 w->pflags |= HDA_ADC_PATH; 4724 ret = 1; 4725 } 4726 break;*/ 4727 default: 4728 break; 4729 } 4730 return (ret); 4731} 4732 4733static uint32_t 4734hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4735 nid_t nid, nid_t pnid, int index, int depth) 4736{ 4737 struct hdac_widget *w, *pw; 4738 struct hdac_audio_ctl *ctl; 4739 uint32_t fl = 0; 4740 int i, ossdev, conndev, strategy; 4741 4742 if (depth > HDA_PARSE_MAXDEPTH) 4743 return (0); 4744 4745 w = hdac_widget_get(devinfo, nid); 4746 if (w == NULL || w->enable == 0) 4747 return (0); 4748 4749 pw = hdac_widget_get(devinfo, pnid); 4750 strategy = devinfo->function.audio.parsing_strategy; 4751 4752 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4753 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4754 for (i = 0; i < w->nconns; i++) { 4755 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4756 w->nid, i, depth + 1); 4757 } 4758 w->ctlflags |= fl; 4759 return (fl); 4760 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4761 (w->pflags & HDA_DAC_PATH)) { 4762 i = 0; 4763 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4764 if (ctl->enable == 0 || ctl->widget == NULL) 4765 continue; 4766 /* XXX This should be compressed! */ 4767 if (((ctl->widget->nid == w->nid) || 4768 (ctl->widget->nid == pnid && ctl->index == index && 4769 (ctl->dir & HDA_CTL_IN)) || 4770 (ctl->widget->nid == pnid && pw != NULL && 4771 pw->type == 4772 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4773 (pw->nconns < 2 || pw->selconn == index || 4774 pw->selconn == -1) && 4775 (ctl->dir & HDA_CTL_OUT)) || 4776 (strategy == HDA_PARSE_DIRECT && 4777 ctl->widget->nid == w->nid)) && 4778 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4779 /*if (pw != NULL && pw->selconn == -1) 4780 pw->selconn = index; 4781 fl |= SOUND_MASK_VOLUME; 4782 fl |= SOUND_MASK_PCM; 4783 ctl->ossmask |= SOUND_MASK_VOLUME; 4784 ctl->ossmask |= SOUND_MASK_PCM; 4785 ctl->ossdev = SOUND_MIXER_PCM;*/ 4786 if (!(w->ctlflags & SOUND_MASK_PCM) || 4787 (pw != NULL && 4788 !(pw->ctlflags & SOUND_MASK_PCM))) { 4789 fl |= SOUND_MASK_VOLUME; 4790 fl |= SOUND_MASK_PCM; 4791 ctl->ossmask |= SOUND_MASK_VOLUME; 4792 ctl->ossmask |= SOUND_MASK_PCM; 4793 ctl->ossdev = SOUND_MIXER_PCM; 4794 w->ctlflags |= SOUND_MASK_VOLUME; 4795 w->ctlflags |= SOUND_MASK_PCM; 4796 if (pw != NULL) { 4797 if (pw->selconn == -1) 4798 pw->selconn = index; 4799 pw->ctlflags |= 4800 SOUND_MASK_VOLUME; 4801 pw->ctlflags |= 4802 SOUND_MASK_PCM; 4803 } 4804 } 4805 } 4806 } 4807 w->ctlflags |= fl; 4808 return (fl); 4809 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4810 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4811 (w->pflags & HDA_ADC_PATH)) { 4812 conndev = w->wclass.pin.config & 4813 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4814 i = 0; 4815 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4816 if (ctl->enable == 0 || ctl->widget == NULL) 4817 continue; 4818 /* XXX This should be compressed! */ 4819 if (((ctl->widget->nid == pnid && ctl->index == index && 4820 (ctl->dir & HDA_CTL_IN)) || 4821 (ctl->widget->nid == pnid && pw != NULL && 4822 pw->type == 4823 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4824 (pw->nconns < 2 || pw->selconn == index || 4825 pw->selconn == -1) && 4826 (ctl->dir & HDA_CTL_OUT)) || 4827 (strategy == HDA_PARSE_DIRECT && 4828 ctl->widget->nid == w->nid)) && 4829 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4830 if (pw != NULL && pw->selconn == -1) 4831 pw->selconn = index; 4832 ossdev = 0; 4833 switch (conndev) { 4834 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4835 ossdev = SOUND_MIXER_MIC; 4836 break; 4837 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4838 ossdev = SOUND_MIXER_LINE; 4839 break; 4840 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4841 ossdev = SOUND_MIXER_CD; 4842 break; 4843 default: 4844 ossdev = 4845 hdac_audio_ctl_ossmixer_getnextdev( 4846 devinfo); 4847 if (ossdev < 0) 4848 ossdev = 0; 4849 break; 4850 } 4851 if (strategy == HDA_PARSE_MIXER) { 4852 fl |= SOUND_MASK_VOLUME; 4853 ctl->ossmask |= SOUND_MASK_VOLUME; 4854 } 4855 fl |= 1 << ossdev; 4856 ctl->ossmask |= 1 << ossdev; 4857 ctl->ossdev = ossdev; 4858 } 4859 } 4860 w->ctlflags |= fl; 4861 return (fl); 4862 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4863 i = 0; 4864 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4865 if (ctl->enable == 0 || ctl->widget == NULL) 4866 continue; 4867 /* XXX This should be compressed! */ 4868 if (((ctl->widget->nid == pnid && ctl->index == index && 4869 (ctl->dir & HDA_CTL_IN)) || 4870 (ctl->widget->nid == pnid && pw != NULL && 4871 pw->type == 4872 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4873 (pw->nconns < 2 || pw->selconn == index || 4874 pw->selconn == -1) && 4875 (ctl->dir & HDA_CTL_OUT)) || 4876 (strategy == HDA_PARSE_DIRECT && 4877 ctl->widget->nid == w->nid)) && 4878 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4879 if (pw != NULL && pw->selconn == -1) 4880 pw->selconn = index; 4881 fl |= SOUND_MASK_VOLUME; 4882 fl |= SOUND_MASK_SPEAKER; 4883 ctl->ossmask |= SOUND_MASK_VOLUME; 4884 ctl->ossmask |= SOUND_MASK_SPEAKER; 4885 ctl->ossdev = SOUND_MIXER_SPEAKER; 4886 } 4887 } 4888 w->ctlflags |= fl; 4889 return (fl); 4890 } 4891 return (0); 4892} 4893 4894static uint32_t 4895hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4896{ 4897 struct hdac_widget *w, *cw; 4898 struct hdac_audio_ctl *ctl; 4899 uint32_t fl; 4900 int i; 4901 4902 if (depth > HDA_PARSE_MAXDEPTH) 4903 return (0); 4904 4905 w = hdac_widget_get(devinfo, nid); 4906 if (w == NULL || w->enable == 0) 4907 return (0); 4908 /*if (!(w->pflags & HDA_ADC_PATH)) 4909 return (0); 4910 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4911 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4912 return (0);*/ 4913 i = 0; 4914 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4915 if (ctl->enable == 0 || ctl->widget == NULL) 4916 continue; 4917 if (ctl->widget->nid == nid) { 4918 ctl->ossmask |= SOUND_MASK_RECLEV; 4919 w->ctlflags |= SOUND_MASK_RECLEV; 4920 return (SOUND_MASK_RECLEV); 4921 } 4922 } 4923 for (i = 0; i < w->nconns; i++) { 4924 cw = hdac_widget_get(devinfo, w->conns[i]); 4925 if (cw == NULL || cw->enable == 0) 4926 continue; 4927 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4928 continue; 4929 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4930 if (fl != 0) { 4931 cw->ctlflags |= fl; 4932 w->ctlflags |= fl; 4933 return (fl); 4934 } 4935 } 4936 return (0); 4937} 4938 4939static int 4940hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4941{ 4942 struct hdac_widget *w, *cw; 4943 int i, child = 0; 4944 4945 if (depth > HDA_PARSE_MAXDEPTH) 4946 return (0); 4947 4948 w = hdac_widget_get(devinfo, nid); 4949 if (w == NULL || w->enable == 0) 4950 return (0); 4951 /*if (!(w->pflags & HDA_ADC_PATH)) 4952 return (0); 4953 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4954 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4955 return (0);*/ 4956 /* XXX weak! */ 4957 for (i = 0; i < w->nconns; i++) { 4958 cw = hdac_widget_get(devinfo, w->conns[i]); 4959 if (cw == NULL) 4960 continue; 4961 if (++child > 1) { 4962 w->pflags |= HDA_ADC_RECSEL; 4963 return (1); 4964 } 4965 } 4966 for (i = 0; i < w->nconns; i++) { 4967 if (hdac_audio_ctl_recsel_build(devinfo, 4968 w->conns[i], depth + 1) != 0) 4969 return (1); 4970 } 4971 return (0); 4972} 4973 4974static int 4975hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4976{ 4977 struct hdac_widget *w, *cw; 4978 int i, j, conndev, found_dac = 0; 4979 int strategy; 4980 4981 strategy = devinfo->function.audio.parsing_strategy; 4982 4983 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4984 w = hdac_widget_get(devinfo, i); 4985 if (w == NULL || w->enable == 0) 4986 continue; 4987 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4988 continue; 4989 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4990 continue; 4991 conndev = w->wclass.pin.config & 4992 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4993 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4994 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4995 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4996 continue; 4997 for (j = 0; j < w->nconns; j++) { 4998 cw = hdac_widget_get(devinfo, w->conns[j]); 4999 if (cw == NULL || cw->enable == 0) 5000 continue; 5001 if (strategy == HDA_PARSE_MIXER && !(cw->type == 5002 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 5003 cw->type == 5004 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5005 continue; 5006 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 5007 != 0) { 5008 if (w->selconn == -1) 5009 w->selconn = j; 5010 w->pflags |= HDA_DAC_PATH; 5011 found_dac++; 5012 } 5013 } 5014 } 5015 5016 return (found_dac); 5017} 5018 5019static void 5020hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5021{ 5022 struct hdac_widget *w; 5023 struct hdac_audio_ctl *ctl; 5024 int i, j, dacs, strategy; 5025 5026 /* Construct DAC path */ 5027 strategy = HDA_PARSE_MIXER; 5028 devinfo->function.audio.parsing_strategy = strategy; 5029 HDA_BOOTVERBOSE( 5030 device_printf(devinfo->codec->sc->dev, 5031 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 5032 HDA_WIDGET_PARSER_REV); 5033 ); 5034 dacs = hdac_audio_build_tree_strategy(devinfo); 5035 if (dacs == 0) { 5036 HDA_BOOTVERBOSE( 5037 device_printf(devinfo->codec->sc->dev, 5038 "HDA_DEBUG: HWiP: 0 DAC path found! " 5039 "Retrying parser " 5040 "using HDA_PARSE_DIRECT strategy.\n"); 5041 ); 5042 strategy = HDA_PARSE_DIRECT; 5043 devinfo->function.audio.parsing_strategy = strategy; 5044 dacs = hdac_audio_build_tree_strategy(devinfo); 5045 } 5046 5047 HDA_BOOTVERBOSE( 5048 device_printf(devinfo->codec->sc->dev, 5049 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 5050 "strategy.\n", 5051 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 5052 ); 5053 5054 /* Construct ADC path */ 5055 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5056 w = hdac_widget_get(devinfo, i); 5057 if (w == NULL || w->enable == 0) 5058 continue; 5059 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5060 continue; 5061 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 5062 } 5063 5064 /* Output mixers */ 5065 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5066 w = hdac_widget_get(devinfo, i); 5067 if (w == NULL || w->enable == 0) 5068 continue; 5069 if ((strategy == HDA_PARSE_MIXER && 5070 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 5071 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 5072 && (w->pflags & HDA_DAC_PATH)) || 5073 (strategy == HDA_PARSE_DIRECT && (w->pflags & 5074 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 5075 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 5076 w->nid, devinfo->startnode - 1, 0, 0); 5077 } else if (w->type == 5078 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 5079 j = 0; 5080 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 5081 NULL) { 5082 if (ctl->enable == 0 || ctl->widget == NULL) 5083 continue; 5084 if (ctl->widget->nid != w->nid) 5085 continue; 5086 ctl->ossmask |= SOUND_MASK_VOLUME; 5087 ctl->ossmask |= SOUND_MASK_SPEAKER; 5088 ctl->ossdev = SOUND_MIXER_SPEAKER; 5089 w->ctlflags |= SOUND_MASK_VOLUME; 5090 w->ctlflags |= SOUND_MASK_SPEAKER; 5091 } 5092 } 5093 } 5094 5095 /* Input mixers (rec) */ 5096 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5097 w = hdac_widget_get(devinfo, i); 5098 if (w == NULL || w->enable == 0) 5099 continue; 5100 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 5101 w->pflags & HDA_ADC_PATH)) 5102 continue; 5103 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 5104 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 5105 } 5106} 5107 5108#define HDA_COMMIT_CONN (1 << 0) 5109#define HDA_COMMIT_CTRL (1 << 1) 5110#define HDA_COMMIT_EAPD (1 << 2) 5111#define HDA_COMMIT_GPIO (1 << 3) 5112#define HDA_COMMIT_MISC (1 << 4) 5113#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5114 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5115 5116static void 5117hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5118{ 5119 struct hdac_softc *sc = devinfo->codec->sc; 5120 struct hdac_widget *w; 5121 nid_t cad; 5122 int i; 5123 5124 if (!(cfl & HDA_COMMIT_ALL)) 5125 return; 5126 5127 cad = devinfo->codec->cad; 5128 5129 if ((cfl & HDA_COMMIT_MISC)) { 5130 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5131 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5132 0x7e7, 0), cad); 5133 } 5134 5135 if (cfl & HDA_COMMIT_GPIO) { 5136 uint32_t gdata, gmask, gdir; 5137 int commitgpio, numgpio; 5138 5139 gdata = 0; 5140 gmask = 0; 5141 gdir = 0; 5142 commitgpio = 0; 5143 5144 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5145 devinfo->function.audio.gpio); 5146 5147 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5148 commitgpio = (numgpio > 0) ? 1 : 0; 5149 else { 5150 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5151 if (!(devinfo->function.audio.quirks & 5152 (1 << i))) 5153 continue; 5154 if (commitgpio == 0) { 5155 commitgpio = 1; 5156 HDA_BOOTVERBOSE( 5157 gdata = hdac_command(sc, 5158 HDA_CMD_GET_GPIO_DATA(cad, 5159 devinfo->nid), cad); 5160 gmask = hdac_command(sc, 5161 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5162 devinfo->nid), cad); 5163 gdir = hdac_command(sc, 5164 HDA_CMD_GET_GPIO_DIRECTION(cad, 5165 devinfo->nid), cad); 5166 device_printf(sc->dev, 5167 "GPIO init: data=0x%08x " 5168 "mask=0x%08x dir=0x%08x\n", 5169 gdata, gmask, gdir); 5170 gdata = 0; 5171 gmask = 0; 5172 gdir = 0; 5173 ); 5174 } 5175 gdata |= 1 << i; 5176 gmask |= 1 << i; 5177 gdir |= 1 << i; 5178 } 5179 } 5180 5181 if (commitgpio != 0) { 5182 HDA_BOOTVERBOSE( 5183 device_printf(sc->dev, 5184 "GPIO commit: data=0x%08x mask=0x%08x " 5185 "dir=0x%08x\n", 5186 gdata, gmask, gdir); 5187 ); 5188 hdac_command(sc, 5189 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5190 gmask), cad); 5191 hdac_command(sc, 5192 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5193 gdir), cad); 5194 hdac_command(sc, 5195 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5196 gdata), cad); 5197 } 5198 } 5199 5200 for (i = 0; i < devinfo->nodecnt; i++) { 5201 w = &devinfo->widget[i]; 5202 if (w == NULL || w->enable == 0) 5203 continue; 5204 if (cfl & HDA_COMMIT_CONN) { 5205 if (w->selconn == -1) 5206 w->selconn = 0; 5207 if (w->nconns > 0) 5208 hdac_widget_connection_select(w, w->selconn); 5209 } 5210 if ((cfl & HDA_COMMIT_CTRL) && 5211 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5212 uint32_t pincap; 5213 5214 pincap = w->wclass.pin.cap; 5215 5216 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5217 (HDA_DAC_PATH | HDA_ADC_PATH)) 5218 device_printf(sc->dev, "WARNING: node %d " 5219 "participate both for DAC/ADC!\n", w->nid); 5220 if (w->pflags & HDA_DAC_PATH) { 5221 w->wclass.pin.ctrl &= 5222 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5223 if ((w->wclass.pin.config & 5224 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5225 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5226 w->wclass.pin.ctrl &= 5227 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5228 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5229 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5230 w->wclass.pin.ctrl |= 5231 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5232 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5233 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5234 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5235 w->wclass.pin.ctrl |= 5236 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5237 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5238 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5239 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5240 w->wclass.pin.ctrl |= 5241 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5242 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5243 } else if (w->pflags & HDA_ADC_PATH) { 5244 w->wclass.pin.ctrl &= 5245 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5246 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5247 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5248 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5249 w->wclass.pin.ctrl |= 5250 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5251 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5252 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5253 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5254 w->wclass.pin.ctrl |= 5255 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5256 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5257 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5258 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5259 w->wclass.pin.ctrl |= 5260 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5261 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5262 } else 5263 w->wclass.pin.ctrl &= ~( 5264 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5265 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5266 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5267 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5268 hdac_command(sc, 5269 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5270 w->wclass.pin.ctrl), cad); 5271 } 5272 if ((cfl & HDA_COMMIT_EAPD) && 5273 w->param.eapdbtl != HDAC_INVALID) { 5274 uint32_t val; 5275 5276 val = w->param.eapdbtl; 5277 if (devinfo->function.audio.quirks & 5278 HDA_QUIRK_EAPDINV) 5279 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5280 hdac_command(sc, 5281 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5282 val), cad); 5283 5284 } 5285 DELAY(1000); 5286 } 5287} 5288 5289static void 5290hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5291{ 5292 struct hdac_softc *sc = devinfo->codec->sc; 5293 struct hdac_audio_ctl *ctl; 5294 int i; 5295 5296 devinfo->function.audio.mvol = 100 | (100 << 8); 5297 i = 0; 5298 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5299 if (ctl->enable == 0 || ctl->widget == NULL) { 5300 HDA_BOOTVERBOSE( 5301 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5302 i, (ctl->widget != NULL) ? 5303 ctl->widget->nid : -1); 5304 if (ctl->childwidget != NULL) 5305 printf(" childnid=%d", 5306 ctl->childwidget->nid); 5307 if (ctl->widget == NULL) 5308 printf(" NULL WIDGET!"); 5309 printf(" DISABLED\n"); 5310 ); 5311 continue; 5312 } 5313 HDA_BOOTVERBOSE( 5314 if (ctl->ossmask == 0) { 5315 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5316 i, ctl->widget->nid); 5317 if (ctl->childwidget != NULL) 5318 printf(" childnid=%d", 5319 ctl->childwidget->nid); 5320 printf(" Bind to NONE\n"); 5321 } 5322 ); 5323 if (ctl->step > 0) { 5324 ctl->ossval = (ctl->left * 100) / ctl->step; 5325 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5326 } else 5327 ctl->ossval = 0; 5328 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5329 ctl->left, ctl->right); 5330 } 5331} 5332 5333static int 5334hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5335{ 5336 struct hdac_chan *ch; 5337 struct hdac_widget *w; 5338 uint32_t cap, fmtcap, pcmcap, path; 5339 int i, type, ret, max; 5340 5341 if (dir == PCMDIR_PLAY) { 5342 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5343 ch = &devinfo->codec->sc->play; 5344 path = HDA_DAC_PATH; 5345 } else { 5346 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5347 ch = &devinfo->codec->sc->rec; 5348 path = HDA_ADC_PATH; 5349 } 5350 5351 ch->caps = hdac_caps; 5352 ch->caps.fmtlist = ch->fmtlist; 5353 ch->bit16 = 1; 5354 ch->bit32 = 0; 5355 ch->pcmrates[0] = 48000; 5356 ch->pcmrates[1] = 0; 5357 5358 ret = 0; 5359 fmtcap = devinfo->function.audio.supp_stream_formats; 5360 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5361 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5362 5363 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5364 w = hdac_widget_get(devinfo, i); 5365 if (w == NULL || w->enable == 0 || w->type != type || 5366 !(w->pflags & path)) 5367 continue; 5368 cap = w->param.widget_cap; 5369 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5370 continue;*/ 5371 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5372 continue; 5373 cap = w->param.supp_stream_formats; 5374 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5375 } 5376 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5377 }*/ 5378 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5379 continue; 5380 if (ret == 0) { 5381 fmtcap = w->param.supp_stream_formats; 5382 pcmcap = w->param.supp_pcm_size_rate; 5383 } else { 5384 fmtcap &= w->param.supp_stream_formats; 5385 pcmcap &= w->param.supp_pcm_size_rate; 5386 } 5387 ch->io[ret++] = i; 5388 } 5389 ch->io[ret] = -1; 5390 5391 ch->supp_stream_formats = fmtcap; 5392 ch->supp_pcm_size_rate = pcmcap; 5393 5394 /* 5395 * 8bit = 0 5396 * 16bit = 1 5397 * 20bit = 2 5398 * 24bit = 3 5399 * 32bit = 4 5400 */ 5401 if (ret > 0) { 5402 cap = pcmcap; 5403 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5404 ch->bit16 = 1; 5405 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5406 ch->bit16 = 0; 5407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5408 ch->bit32 = 4; 5409 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5410 ch->bit32 = 3; 5411 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5412 ch->bit32 = 2; 5413 i = 0; 5414 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5415 ch->fmtlist[i++] = AFMT_S16_LE; 5416 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5417 if (ch->bit32 > 0) { 5418 if (!(devinfo->function.audio.quirks & 5419 HDA_QUIRK_FORCESTEREO)) 5420 ch->fmtlist[i++] = AFMT_S32_LE; 5421 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5422 } 5423 ch->fmtlist[i] = 0; 5424 i = 0; 5425 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5426 ch->pcmrates[i++] = 8000; 5427 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5428 ch->pcmrates[i++] = 11025; 5429 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5430 ch->pcmrates[i++] = 16000; 5431 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5432 ch->pcmrates[i++] = 22050; 5433 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5434 ch->pcmrates[i++] = 32000; 5435 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5436 ch->pcmrates[i++] = 44100; 5437 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5438 ch->pcmrates[i++] = 48000; 5439 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5440 ch->pcmrates[i++] = 88200; 5441 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5442 ch->pcmrates[i++] = 96000; 5443 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5444 ch->pcmrates[i++] = 176400; 5445 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5446 ch->pcmrates[i++] = 192000; 5447 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5448 ch->pcmrates[i] = 0; 5449 if (i > 0) { 5450 ch->caps.minspeed = ch->pcmrates[0]; 5451 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5452 } 5453 } 5454 5455 return (ret); 5456} 5457 5458static void 5459hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5460{ 5461 struct hdac_audio_ctl *ctl; 5462 struct hdac_softc *sc = devinfo->codec->sc; 5463 int i; 5464 uint32_t fl = 0; 5465 5466 5467 if (flag == 0) { 5468 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5469 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5470 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5471 } 5472 5473 i = 0; 5474 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5475 if (ctl->enable == 0 || ctl->widget == NULL || 5476 ctl->widget->enable == 0 || (ctl->ossmask & 5477 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5478 continue; 5479 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5480 (flag != 0 && (ctl->ossmask & flag))) { 5481 if (banner != NULL) { 5482 device_printf(sc->dev, "\n"); 5483 device_printf(sc->dev, "%s\n", banner); 5484 } 5485 goto hdac_ctl_dump_it_all; 5486 } 5487 } 5488 5489 return; 5490 5491hdac_ctl_dump_it_all: 5492 i = 0; 5493 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5494 if (ctl->enable == 0 || ctl->widget == NULL || 5495 ctl->widget->enable == 0) 5496 continue; 5497 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5498 (flag != 0 && (ctl->ossmask & flag)))) 5499 continue; 5500 if (flag == 0) { 5501 device_printf(sc->dev, "\n"); 5502 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5503 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5504 } 5505 device_printf(sc->dev, " |\n"); 5506 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5507 ctl->widget->nid, ctl->index); 5508 if (ctl->childwidget != NULL) 5509 printf("(nid: %2d) ", ctl->childwidget->nid); 5510 else 5511 printf(" "); 5512 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5513 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5514 ctl->ossmask); 5515 } 5516} 5517 5518static void 5519hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5520{ 5521 uint32_t cap; 5522 5523 cap = fcap; 5524 if (cap != 0) { 5525 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5526 device_printf(sc->dev, " Format:"); 5527 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5528 printf(" AC3"); 5529 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5530 printf(" FLOAT32"); 5531 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5532 printf(" PCM"); 5533 printf("\n"); 5534 } 5535 cap = pcmcap; 5536 if (cap != 0) { 5537 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5538 device_printf(sc->dev, " PCM size:"); 5539 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5540 printf(" 8"); 5541 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5542 printf(" 16"); 5543 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5544 printf(" 20"); 5545 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5546 printf(" 24"); 5547 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5548 printf(" 32"); 5549 printf("\n"); 5550 device_printf(sc->dev, " PCM rate:"); 5551 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5552 printf(" 8"); 5553 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5554 printf(" 11"); 5555 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5556 printf(" 16"); 5557 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5558 printf(" 22"); 5559 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5560 printf(" 32"); 5561 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5562 printf(" 44"); 5563 printf(" 48"); 5564 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5565 printf(" 88"); 5566 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5567 printf(" 96"); 5568 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5569 printf(" 176"); 5570 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5571 printf(" 192"); 5572 printf("\n"); 5573 } 5574} 5575 5576static void 5577hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5578{ 5579 uint32_t pincap, wcap; 5580 5581 pincap = w->wclass.pin.cap; 5582 wcap = w->param.widget_cap; 5583 5584 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5585 device_printf(sc->dev, " "); 5586 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5587 printf(" ISC"); 5588 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5589 printf(" TRQD"); 5590 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5591 printf(" PDC"); 5592 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5593 printf(" HP"); 5594 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5595 printf(" OUT"); 5596 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5597 printf(" IN"); 5598 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5599 printf(" BAL"); 5600 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5601 printf(" VREF["); 5602 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5603 printf(" 50"); 5604 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5605 printf(" 80"); 5606 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5607 printf(" 100"); 5608 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5609 printf(" GROUND"); 5610 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5611 printf(" HIZ"); 5612 printf(" ]"); 5613 } 5614 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5615 printf(" EAPD"); 5616 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5617 printf(" : UNSOL"); 5618 printf("\n"); 5619 device_printf(sc->dev, " Pin config: 0x%08x\n", 5620 w->wclass.pin.config); 5621 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5622 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5623 printf(" HP"); 5624 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5625 printf(" IN"); 5626 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5627 printf(" OUT"); 5628 printf("\n"); 5629} 5630 5631static void 5632hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5633{ 5634 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5635 device_printf(sc->dev, " " 5636 "mute=%d step=%d size=%d offset=%d\n", 5637 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5638 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5639 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5640 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5641} 5642 5643static void 5644hdac_dump_nodes(struct hdac_devinfo *devinfo) 5645{ 5646 struct hdac_softc *sc = devinfo->codec->sc; 5647 struct hdac_widget *w, *cw; 5648 int i, j; 5649 5650 device_printf(sc->dev, "\n"); 5651 device_printf(sc->dev, "Default Parameter\n"); 5652 device_printf(sc->dev, "-----------------\n"); 5653 hdac_dump_audio_formats(sc, 5654 devinfo->function.audio.supp_stream_formats, 5655 devinfo->function.audio.supp_pcm_size_rate); 5656 device_printf(sc->dev, " IN amp: 0x%08x\n", 5657 devinfo->function.audio.inamp_cap); 5658 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5659 devinfo->function.audio.outamp_cap); 5660 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5661 w = hdac_widget_get(devinfo, i); 5662 if (w == NULL) { 5663 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5664 continue; 5665 } 5666 device_printf(sc->dev, "\n"); 5667 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5668 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5669 "DIGITAL" : "ANALOG", 5670 (w->enable == 0) ? " [DISABLED]" : ""); 5671 device_printf(sc->dev, " name: %s\n", w->name); 5672 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5673 w->param.widget_cap); 5674 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5675 w->pflags); 5676 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5677 w->ctlflags); 5678 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5679 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5680 hdac_dump_audio_formats(sc, 5681 w->param.supp_stream_formats, 5682 w->param.supp_pcm_size_rate); 5683 } else if (w->type == 5684 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5685 hdac_dump_pin(sc, w); 5686 if (w->param.eapdbtl != HDAC_INVALID) 5687 device_printf(sc->dev, " EAPD: 0x%08x\n", 5688 w->param.eapdbtl); 5689 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5690 w->param.outamp_cap != 0) 5691 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5692 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5693 w->param.inamp_cap != 0) 5694 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5695 device_printf(sc->dev, " connections: %d\n", w->nconns); 5696 for (j = 0; j < w->nconns; j++) { 5697 cw = hdac_widget_get(devinfo, w->conns[j]); 5698 device_printf(sc->dev, " |\n"); 5699 device_printf(sc->dev, " + <- nid=%d [%s]", 5700 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5701 if (cw == NULL) 5702 printf(" [UNKNOWN]"); 5703 else if (cw->enable == 0) 5704 printf(" [DISABLED]"); 5705 if (w->nconns > 1 && w->selconn == j && w->type != 5706 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5707 printf(" (selected)"); 5708 printf("\n"); 5709 } 5710 } 5711 5712} 5713 5714static int 5715hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5716{ 5717 struct hdac_widget *w, *cw; 5718 struct hdac_softc *sc = devinfo->codec->sc; 5719 int i; 5720 5721 if (depth > HDA_PARSE_MAXDEPTH) 5722 return (0); 5723 5724 w = hdac_widget_get(devinfo, nid); 5725 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5726 return (0); 5727 5728 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5729 device_printf(sc->dev, "\n"); 5730 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5731 device_printf(sc->dev, " ^\n"); 5732 device_printf(sc->dev, " |\n"); 5733 device_printf(sc->dev, " +-----<------+\n"); 5734 } else { 5735 device_printf(sc->dev, " ^\n"); 5736 device_printf(sc->dev, " |\n"); 5737 device_printf(sc->dev, " "); 5738 printf(" nid=%d [%s]\n", w->nid, w->name); 5739 } 5740 5741 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5742 return (1); 5743 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5744 for (i = 0; i < w->nconns; i++) { 5745 cw = hdac_widget_get(devinfo, w->conns[i]); 5746 if (cw == NULL || cw->enable == 0 || cw->type == 5747 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5748 continue; 5749 if (hdac_dump_dac_internal(devinfo, cw->nid, 5750 depth + 1) != 0) 5751 return (1); 5752 } 5753 } else if ((w->type == 5754 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5755 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5756 w->selconn > -1 && w->selconn < w->nconns) { 5757 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5758 depth + 1) != 0) 5759 return (1); 5760 } 5761 5762 return (0); 5763} 5764 5765static void 5766hdac_dump_dac(struct hdac_devinfo *devinfo) 5767{ 5768 struct hdac_widget *w; 5769 struct hdac_softc *sc = devinfo->codec->sc; 5770 int i, printed = 0; 5771 5772 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5773 w = hdac_widget_get(devinfo, i); 5774 if (w == NULL || w->enable == 0) 5775 continue; 5776 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5777 !(w->pflags & HDA_DAC_PATH)) 5778 continue; 5779 if (printed == 0) { 5780 printed = 1; 5781 device_printf(sc->dev, "\n"); 5782 device_printf(sc->dev, "Playback path:\n"); 5783 } 5784 hdac_dump_dac_internal(devinfo, w->nid, 0); 5785 } 5786} 5787 5788static void 5789hdac_dump_adc(struct hdac_devinfo *devinfo) 5790{ 5791 struct hdac_widget *w, *cw; 5792 struct hdac_softc *sc = devinfo->codec->sc; 5793 int i, j; 5794 int printed = 0; 5795 char ossdevs[256]; 5796 5797 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5798 w = hdac_widget_get(devinfo, i); 5799 if (w == NULL || w->enable == 0) 5800 continue; 5801 if (!(w->pflags & HDA_ADC_RECSEL)) 5802 continue; 5803 if (printed == 0) { 5804 printed = 1; 5805 device_printf(sc->dev, "\n"); 5806 device_printf(sc->dev, "Recording sources:\n"); 5807 } 5808 device_printf(sc->dev, "\n"); 5809 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5810 for (j = 0; j < w->nconns; j++) { 5811 cw = hdac_widget_get(devinfo, w->conns[j]); 5812 if (cw == NULL || cw->enable == 0) 5813 continue; 5814 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5815 ossdevs, sizeof(ossdevs)); 5816 device_printf(sc->dev, " |\n"); 5817 device_printf(sc->dev, " + <- nid=%d [%s]", 5818 cw->nid, cw->name); 5819 if (strlen(ossdevs) > 0) { 5820 printf(" [recsrc: %s]", ossdevs); 5821 } 5822 printf("\n"); 5823 } 5824 } 5825} 5826 5827static void 5828hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5829{ 5830 nid_t *nids; 5831 5832 if (pcnt > 0) { 5833 device_printf(sc->dev, "\n"); 5834 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5835 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5836 sc->play.supp_pcm_size_rate); 5837 device_printf(sc->dev, " DAC:"); 5838 for (nids = sc->play.io; *nids != -1; nids++) 5839 printf(" %d", *nids); 5840 printf("\n"); 5841 } 5842 5843 if (rcnt > 0) { 5844 device_printf(sc->dev, "\n"); 5845 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5846 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5847 sc->rec.supp_pcm_size_rate); 5848 device_printf(sc->dev, " ADC:"); 5849 for (nids = sc->rec.io; *nids != -1; nids++) 5850 printf(" %d", *nids); 5851 printf("\n"); 5852 } 5853} 5854 5855static void 5856hdac_release_resources(struct hdac_softc *sc) 5857{ 5858 struct hdac_devinfo *devinfo = NULL; 5859 device_t *devlist = NULL; 5860 int i, devcount; 5861 5862 if (sc == NULL) 5863 return; 5864 5865 hdac_lock(sc); 5866 sc->polling = 0; 5867 sc->poll_ival = 0; 5868 callout_stop(&sc->poll_hda); 5869 callout_stop(&sc->poll_hdac); 5870 callout_stop(&sc->poll_jack); 5871 hdac_reset(sc); 5872 hdac_unlock(sc); 5873 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5874 callout_drain(&sc->poll_hda); 5875 callout_drain(&sc->poll_hdac); 5876 callout_drain(&sc->poll_jack); 5877 5878 hdac_irq_free(sc); 5879 5880 device_get_children(sc->dev, &devlist, &devcount); 5881 for (i = 0; devlist != NULL && i < devcount; i++) { 5882 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5883 if (devinfo == NULL) 5884 continue; 5885 if (devinfo->widget != NULL) 5886 free(devinfo->widget, M_HDAC); 5887 if (devinfo->node_type == 5888 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5889 devinfo->function.audio.ctl != NULL) 5890 free(devinfo->function.audio.ctl, M_HDAC); 5891 free(devinfo, M_HDAC); 5892 device_delete_child(sc->dev, devlist[i]); 5893 } 5894 if (devlist != NULL) 5895 free(devlist, M_TEMP); 5896 5897 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5898 if (sc->codecs[i] != NULL) 5899 free(sc->codecs[i], M_HDAC); 5900 sc->codecs[i] = NULL; 5901 } 5902 5903 hdac_dma_free(sc, &sc->pos_dma); 5904 hdac_dma_free(sc, &sc->rirb_dma); 5905 hdac_dma_free(sc, &sc->corb_dma); 5906 if (sc->play.blkcnt > 0) 5907 hdac_dma_free(sc, &sc->play.bdl_dma); 5908 if (sc->rec.blkcnt > 0) 5909 hdac_dma_free(sc, &sc->rec.bdl_dma); 5910 if (sc->chan_dmat != NULL) { 5911 bus_dma_tag_destroy(sc->chan_dmat); 5912 sc->chan_dmat = NULL; 5913 } 5914 hdac_mem_free(sc); 5915 snd_mtxfree(sc->lock); 5916 free(sc, M_DEVBUF); 5917} 5918 5919/* This function surely going to make its way into upper level someday. */ 5920static void 5921hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5922{ 5923 const char *res = NULL; 5924 int i = 0, j, k, len, inv; 5925 5926 if (on != NULL) 5927 *on = 0; 5928 if (off != NULL) 5929 *off = 0; 5930 if (sc == NULL) 5931 return; 5932 if (resource_string_value(device_get_name(sc->dev), 5933 device_get_unit(sc->dev), "config", &res) != 0) 5934 return; 5935 if (!(res != NULL && strlen(res) > 0)) 5936 return; 5937 HDA_BOOTVERBOSE( 5938 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5939 ); 5940 for (;;) { 5941 while (res[i] != '\0' && 5942 (res[i] == ',' || isspace(res[i]) != 0)) 5943 i++; 5944 if (res[i] == '\0') { 5945 HDA_BOOTVERBOSE( 5946 printf("\n"); 5947 ); 5948 return; 5949 } 5950 j = i; 5951 while (res[j] != '\0' && 5952 !(res[j] == ',' || isspace(res[j]) != 0)) 5953 j++; 5954 len = j - i; 5955 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5956 inv = 2; 5957 else 5958 inv = 0; 5959 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5960 if (strncmp(res + i + inv, 5961 hdac_quirks_tab[k].key, len - inv) != 0) 5962 continue; 5963 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5964 break; 5965 HDA_BOOTVERBOSE( 5966 printf(" %s%s", (inv != 0) ? "no" : "", 5967 hdac_quirks_tab[k].key); 5968 ); 5969 if (inv == 0 && on != NULL) 5970 *on |= hdac_quirks_tab[k].value; 5971 else if (inv != 0 && off != NULL) 5972 *off |= hdac_quirks_tab[k].value; 5973 break; 5974 } 5975 i = j; 5976 } 5977} 5978 5979#ifdef SND_DYNSYSCTL 5980static int 5981sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5982{ 5983 struct hdac_softc *sc; 5984 struct hdac_devinfo *devinfo; 5985 device_t dev; 5986 uint32_t ctl; 5987 int err, val; 5988 5989 dev = oidp->oid_arg1; 5990 devinfo = pcm_getdevinfo(dev); 5991 if (devinfo == NULL || devinfo->codec == NULL || 5992 devinfo->codec->sc == NULL) 5993 return (EINVAL); 5994 sc = devinfo->codec->sc; 5995 hdac_lock(sc); 5996 val = sc->polling; 5997 hdac_unlock(sc); 5998 err = sysctl_handle_int(oidp, &val, 0, req); 5999 6000 if (err != 0 || req->newptr == NULL) 6001 return (err); 6002 if (val < 0 || val > 1) 6003 return (EINVAL); 6004 6005 hdac_lock(sc); 6006 if (val != sc->polling) { 6007 if (hda_chan_active(sc) != 0) 6008 err = EBUSY; 6009 else if (val == 0) { 6010 callout_stop(&sc->poll_hdac); 6011 hdac_unlock(sc); 6012 callout_drain(&sc->poll_hdac); 6013 hdac_lock(sc); 6014 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 6015 sc->rirb_size / 2); 6016 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 6017 ctl |= HDAC_RIRBCTL_RINTCTL; 6018 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 6019 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6020 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6021 sc->polling = 0; 6022 DELAY(1000); 6023 } else { 6024 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 6025 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 6026 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 6027 ctl &= ~HDAC_RIRBCTL_RINTCTL; 6028 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 6029 hdac_unlock(sc); 6030 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6031 hdac_lock(sc); 6032 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 6033 sc); 6034 sc->polling = 1; 6035 DELAY(1000); 6036 } 6037 } 6038 hdac_unlock(sc); 6039 6040 return (err); 6041} 6042 6043static int 6044sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 6045{ 6046 struct hdac_softc *sc; 6047 struct hdac_devinfo *devinfo; 6048 device_t dev; 6049 int err, val; 6050 6051 dev = oidp->oid_arg1; 6052 devinfo = pcm_getdevinfo(dev); 6053 if (devinfo == NULL || devinfo->codec == NULL || 6054 devinfo->codec->sc == NULL) 6055 return (EINVAL); 6056 sc = devinfo->codec->sc; 6057 hdac_lock(sc); 6058 val = ((uint64_t)sc->poll_ival * 1000) / hz; 6059 hdac_unlock(sc); 6060 err = sysctl_handle_int(oidp, &val, 0, req); 6061 6062 if (err != 0 || req->newptr == NULL) 6063 return (err); 6064 6065 if (val < 1) 6066 val = 1; 6067 if (val > 5000) 6068 val = 5000; 6069 val = ((uint64_t)val * hz) / 1000; 6070 if (val < 1) 6071 val = 1; 6072 if (val > (hz * 5)) 6073 val = hz * 5; 6074 6075 hdac_lock(sc); 6076 sc->poll_ival = val; 6077 hdac_unlock(sc); 6078 6079 return (err); 6080} 6081 6082#ifdef SND_DEBUG 6083static int 6084sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6085{ 6086 struct hdac_softc *sc; 6087 struct hdac_devinfo *devinfo; 6088 struct hdac_widget *w; 6089 device_t dev; 6090 uint32_t res, pincap, timeout; 6091 int i, err, val; 6092 nid_t cad; 6093 6094 dev = oidp->oid_arg1; 6095 devinfo = pcm_getdevinfo(dev); 6096 if (devinfo == NULL || devinfo->codec == NULL || 6097 devinfo->codec->sc == NULL) 6098 return (EINVAL); 6099 val = 0; 6100 err = sysctl_handle_int(oidp, &val, 0, req); 6101 if (err != 0 || req->newptr == NULL || val == 0) 6102 return (err); 6103 sc = devinfo->codec->sc; 6104 cad = devinfo->codec->cad; 6105 hdac_lock(sc); 6106 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6107 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6108 w = hdac_widget_get(devinfo, i); 6109 if (w == NULL || w->type != 6110 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6111 continue; 6112 pincap = w->wclass.pin.cap; 6113 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6114 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6115 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6116 timeout = 10000; 6117 hdac_command(sc, 6118 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6119 do { 6120 res = hdac_command(sc, 6121 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6122 if (res != 0x7fffffff) 6123 break; 6124 DELAY(10); 6125 } while (--timeout != 0); 6126 } else { 6127 timeout = -1; 6128 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6129 w->nid), cad); 6130 } 6131 device_printf(dev, 6132 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6133 w->nid, timeout, res, 6134 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6135 } 6136 device_printf(dev, 6137 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6138 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6139 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6140 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6141 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6142 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6143 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6144 device_printf(dev, " GPI:"); 6145 res = hdac_command(sc, 6146 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6147 printf(" data=0x%08x", res); 6148 res = hdac_command(sc, 6149 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6150 cad); 6151 printf(" wake=0x%08x", res); 6152 res = hdac_command(sc, 6153 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6154 cad); 6155 printf(" unsol=0x%08x", res); 6156 res = hdac_command(sc, 6157 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6158 printf(" sticky=0x%08x\n", res); 6159 } 6160 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6161 device_printf(dev, " GPO:"); 6162 res = hdac_command(sc, 6163 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6164 printf(" data=0x%08x\n", res); 6165 } 6166 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6167 device_printf(dev, "GPI0:"); 6168 res = hdac_command(sc, 6169 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6170 printf(" data=0x%08x", res); 6171 res = hdac_command(sc, 6172 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6173 printf(" enable=0x%08x", res); 6174 res = hdac_command(sc, 6175 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6176 printf(" direction=0x%08x\n", res); 6177 res = hdac_command(sc, 6178 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6179 device_printf(dev, " wake=0x%08x", res); 6180 res = hdac_command(sc, 6181 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6182 cad); 6183 printf(" unsol=0x%08x", res); 6184 res = hdac_command(sc, 6185 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6186 printf(" sticky=0x%08x\n", res); 6187 } 6188 hdac_unlock(sc); 6189 return (0); 6190} 6191#endif 6192#endif 6193 6194static void 6195hdac_attach2(void *arg) 6196{ 6197 struct hdac_softc *sc; 6198 struct hdac_widget *w; 6199 struct hdac_audio_ctl *ctl; 6200 uint32_t quirks_on, quirks_off; 6201 int pcnt, rcnt, codec_index; 6202 int i; 6203 char status[SND_STATUSLEN]; 6204 device_t *devlist = NULL; 6205 int devcount; 6206 struct hdac_devinfo *devinfo = NULL; 6207 6208 sc = (struct hdac_softc *)arg; 6209 6210 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6211 6212 HDA_BOOTVERBOSE( 6213 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6214 quirks_on, quirks_off); 6215 ); 6216 6217 if (resource_int_value(device_get_name(sc->dev), 6218 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6219 switch (sc->pci_subvendor) { 6220 case GB_G33S2H_SUBVENDOR: 6221 codec_index = 2; 6222 break; 6223 default: 6224 codec_index = 0; 6225 break; 6226 } 6227 } 6228 6229 hdac_lock(sc); 6230 6231 /* Remove ourselves from the config hooks */ 6232 if (sc->intrhook.ich_func != NULL) { 6233 config_intrhook_disestablish(&sc->intrhook); 6234 sc->intrhook.ich_func = NULL; 6235 } 6236 6237 /* Start the corb and rirb engines */ 6238 HDA_BOOTVERBOSE( 6239 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6240 ); 6241 hdac_corb_start(sc); 6242 HDA_BOOTVERBOSE( 6243 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6244 ); 6245 hdac_rirb_start(sc); 6246 6247 HDA_BOOTVERBOSE( 6248 device_printf(sc->dev, 6249 "HDA_DEBUG: Enabling controller interrupt...\n"); 6250 ); 6251 if (sc->polling == 0) 6252 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6253 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6254 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6255 HDAC_GCTL_UNSOL); 6256 6257 DELAY(1000); 6258 6259 HDA_BOOTVERBOSE( 6260 device_printf(sc->dev, 6261 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6262 codec_index); 6263 ); 6264 hdac_scan_codecs(sc, codec_index); 6265 6266 device_get_children(sc->dev, &devlist, &devcount); 6267 for (i = 0; devlist != NULL && i < devcount; i++) { 6268 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6269 if (devinfo != NULL && devinfo->node_type == 6270 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6271 break; 6272 } else 6273 devinfo = NULL; 6274 } 6275 if (devlist != NULL) 6276 free(devlist, M_TEMP); 6277 6278 if (devinfo == NULL) { 6279 hdac_unlock(sc); 6280 device_printf(sc->dev, "Audio Function Group not found!\n"); 6281 hdac_release_resources(sc); 6282 return; 6283 } 6284 6285 HDA_BOOTVERBOSE( 6286 device_printf(sc->dev, 6287 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6288 devinfo->nid, devinfo->codec->cad); 6289 ); 6290 hdac_audio_parse(devinfo); 6291 HDA_BOOTVERBOSE( 6292 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6293 ); 6294 hdac_audio_ctl_parse(devinfo); 6295 HDA_BOOTVERBOSE( 6296 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6297 ); 6298 hdac_vendor_patch_parse(devinfo); 6299 if (quirks_on != 0) 6300 devinfo->function.audio.quirks |= quirks_on; 6301 if (quirks_off != 0) 6302 devinfo->function.audio.quirks &= ~quirks_off; 6303 6304 /* XXX Disable all DIGITAL path. */ 6305 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6306 w = hdac_widget_get(devinfo, i); 6307 if (w == NULL) 6308 continue; 6309 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6310 w->enable = 0; 6311 continue; 6312 } 6313 /* XXX Disable useless pin ? */ 6314 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6315 (w->wclass.pin.config & 6316 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6317 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6318 w->enable = 0; 6319 } 6320 i = 0; 6321 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6322 if (ctl->widget == NULL) 6323 continue; 6324 if (ctl->ossmask & SOUND_MASK_DISABLE) 6325 ctl->enable = 0; 6326 w = ctl->widget; 6327 if (w->enable == 0 || 6328 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6329 ctl->enable = 0; 6330 w = ctl->childwidget; 6331 if (w == NULL) 6332 continue; 6333 if (w->enable == 0 || 6334 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6335 ctl->enable = 0; 6336 } 6337 6338 HDA_BOOTVERBOSE( 6339 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6340 ); 6341 hdac_audio_build_tree(devinfo); 6342 6343 i = 0; 6344 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6345 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6346 ctl->ossmask = 0; 6347 } 6348 HDA_BOOTVERBOSE( 6349 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6350 ); 6351 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6352 HDA_BOOTVERBOSE( 6353 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6354 ); 6355 hdac_audio_ctl_commit(devinfo); 6356 6357 HDA_BOOTVERBOSE( 6358 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6359 ); 6360 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6361 HDA_BOOTVERBOSE( 6362 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6363 ); 6364 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6365 6366 hdac_unlock(sc); 6367 HDA_BOOTVERBOSE( 6368 device_printf(sc->dev, 6369 "HDA_DEBUG: OSS mixer initialization...\n"); 6370 ); 6371 6372 /* 6373 * There is no point of return after this. If the driver failed, 6374 * so be it. Let the detach procedure do all the cleanup. 6375 */ 6376 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6377 device_printf(sc->dev, "Can't register mixer\n"); 6378 6379 if (pcnt > 0) 6380 pcnt = 1; 6381 if (rcnt > 0) 6382 rcnt = 1; 6383 6384 HDA_BOOTVERBOSE( 6385 device_printf(sc->dev, 6386 "HDA_DEBUG: Registering PCM channels...\n"); 6387 ); 6388 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6389 device_printf(sc->dev, "Can't register PCM\n"); 6390 6391 sc->registered++; 6392 6393 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6394 hdac_dma_alloc(sc, &sc->pos_dma, 6395 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6396 HDA_BOOTVERBOSE( 6397 device_printf(sc->dev, 6398 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6399 ); 6400 } 6401 6402 for (i = 0; i < pcnt; i++) 6403 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6404 for (i = 0; i < rcnt; i++) 6405 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6406 6407#ifdef SND_DYNSYSCTL 6408 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6409 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6410 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6411 sysctl_hdac_polling, "I", "Enable polling mode"); 6412 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6413 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6414 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6415 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6416 "Controller/Jack Sense polling interval (1-1000 ms)"); 6417#ifdef SND_DEBUG 6418 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6419 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6420 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6421 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6422#endif 6423#endif 6424 6425 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6426 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6427 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6428 pcm_setstatus(sc->dev, status); 6429 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6430 HDA_BOOTVERBOSE( 6431 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6432 hdac_codec_id(devinfo)); 6433 ); 6434 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6435 HDA_DRV_TEST_REV); 6436 6437 HDA_BOOTVERBOSE( 6438 if (devinfo->function.audio.quirks != 0) { 6439 device_printf(sc->dev, "\n"); 6440 device_printf(sc->dev, "HDA config/quirks:"); 6441 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6442 if ((devinfo->function.audio.quirks & 6443 hdac_quirks_tab[i].value) == 6444 hdac_quirks_tab[i].value) 6445 printf(" %s", hdac_quirks_tab[i].key); 6446 } 6447 printf("\n"); 6448 } 6449 device_printf(sc->dev, "\n"); 6450 device_printf(sc->dev, "+-------------------+\n"); 6451 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6452 device_printf(sc->dev, "+-------------------+\n"); 6453 hdac_dump_nodes(devinfo); 6454 device_printf(sc->dev, "\n"); 6455 device_printf(sc->dev, "+------------------------+\n"); 6456 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6457 device_printf(sc->dev, "+------------------------+\n"); 6458 device_printf(sc->dev, "\n"); 6459 i = 0; 6460 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6461 device_printf(sc->dev, "%3d: nid=%d", i, 6462 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6463 if (ctl->childwidget != NULL) 6464 printf(" cnid=%d", ctl->childwidget->nid); 6465 printf(" dir=0x%x index=%d " 6466 "ossmask=0x%08x ossdev=%d%s\n", 6467 ctl->dir, ctl->index, 6468 ctl->ossmask, ctl->ossdev, 6469 (ctl->enable == 0) ? " [DISABLED]" : ""); 6470 } 6471 device_printf(sc->dev, "\n"); 6472 device_printf(sc->dev, "+-----------------------------------+\n"); 6473 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6474 device_printf(sc->dev, "+-----------------------------------+\n"); 6475 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6476 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6477 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6478 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6479 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6480 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6481 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6482 hdac_dump_ctls(devinfo, NULL, 0); 6483 hdac_dump_dac(devinfo); 6484 hdac_dump_adc(devinfo); 6485 device_printf(sc->dev, "\n"); 6486 device_printf(sc->dev, "+--------------------------------------+\n"); 6487 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6488 device_printf(sc->dev, "+--------------------------------------+\n"); 6489 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6490 ); 6491 6492 if (sc->polling != 0) { 6493 hdac_lock(sc); 6494 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6495 hdac_unlock(sc); 6496 } 6497} 6498 6499/**************************************************************************** 6500 * int hdac_detach(device_t) 6501 * 6502 * Detach and free up resources utilized by the hdac device. 6503 ****************************************************************************/ 6504static int 6505hdac_detach(device_t dev) 6506{ 6507 struct hdac_softc *sc = NULL; 6508 struct hdac_devinfo *devinfo = NULL; 6509 int err; 6510 6511 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6512 if (devinfo != NULL && devinfo->codec != NULL) 6513 sc = devinfo->codec->sc; 6514 if (sc == NULL) 6515 return (0); 6516 6517 if (sc->registered > 0) { 6518 err = pcm_unregister(dev); 6519 if (err != 0) 6520 return (err); 6521 } 6522 6523 hdac_release_resources(sc); 6524 6525 return (0); 6526} 6527 6528static device_method_t hdac_methods[] = { 6529 /* device interface */ 6530 DEVMETHOD(device_probe, hdac_probe), 6531 DEVMETHOD(device_attach, hdac_attach), 6532 DEVMETHOD(device_detach, hdac_detach), 6533 { 0, 0 } 6534}; 6535 6536static driver_t hdac_driver = { 6537 "pcm", 6538 hdac_methods, 6539 PCM_SOFTC_SIZE, 6540}; 6541 6542DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6543MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6544MODULE_VERSION(snd_hda, 1); 6545