hdac.c revision 174578
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sys/ctype.h> 75#include <sys/taskqueue.h> 76 77#include <dev/sound/pci/hda/hdac_private.h> 78#include <dev/sound/pci/hda/hdac_reg.h> 79#include <dev/sound/pci/hda/hda_reg.h> 80#include <dev/sound/pci/hda/hdac.h> 81 82#include "mixer_if.h" 83 84#define HDA_DRV_TEST_REV "20071129_0050" 85#define HDA_WIDGET_PARSER_REV 1 86 87SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 174578 2007-12-13 15:44:53Z ariff $"); 88 89#define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93} while(0) 94 95#if 1 96#undef HDAC_INTR_EXTRA 97#define HDAC_INTR_EXTRA 1 98#endif 99 100#define hdac_lock(sc) snd_mtxlock((sc)->lock) 101#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103#define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 106#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 107 (fl) == 0xffffffff || \ 108 (((fl) & 0xffff0000) == 0xffff0000 && \ 109 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 110 (((fl) & 0x0000ffff) == 0x0000ffff && \ 111 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 112#define HDA_MATCH_ALL 0xffffffff 113#define HDAC_INVALID 0xffffffff 114 115/* Default controller / jack sense poll: 250ms */ 116#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 117 118/* 119 * Make room for possible 4096 playback/record channels, in 100 years to come. 120 */ 121#define HDAC_TRIGGER_NONE 0x00000000 122#define HDAC_TRIGGER_PLAY 0x00000fff 123#define HDAC_TRIGGER_REC 0x00fff000 124#define HDAC_TRIGGER_UNSOL 0x80000000 125 126#define HDA_MODEL_CONSTRUCT(vendor, model) \ 127 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 128 129/* Controller models */ 130 131/* Intel */ 132#define INTEL_VENDORID 0x8086 133#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 134#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 135#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 136#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 137#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 138#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 139 140/* Nvidia */ 141#define NVIDIA_VENDORID 0x10de 142#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 143#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 144#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 145#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 146#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 147#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 148#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 149#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 150#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 151 152/* ATI */ 153#define ATI_VENDORID 0x1002 154#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 155#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 156#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 157 158/* VIA */ 159#define VIA_VENDORID 0x1106 160#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 161#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 162 163/* SiS */ 164#define SIS_VENDORID 0x1039 165#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 166#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 167 168/* OEM/subvendors */ 169 170/* Intel */ 171#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 172 173/* HP/Compaq */ 174#define HP_VENDORID 0x103c 175#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 176#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 177#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 178#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 179#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 180#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 181#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 182#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 183#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 184/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 185#define HP_NX6325_SUBVENDORX 0x103c30b0 186 187/* Dell */ 188#define DELL_VENDORID 0x1028 189#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 190#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 191#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 192#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 193#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 194 195/* Clevo */ 196#define CLEVO_VENDORID 0x1558 197#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 198#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 199 200/* Acer */ 201#define ACER_VENDORID 0x1025 202#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 203#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 204#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 205#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 206#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 207 208/* Asus */ 209#define ASUS_VENDORID 0x1043 210#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 211#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 212#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 213#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 214#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 215#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 216#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 217#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 218#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 219#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 220#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 221#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 222#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 223#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 224#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 225 226/* IBM / Lenovo */ 227#define IBM_VENDORID 0x1014 228#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 229#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 230 231/* Lenovo */ 232#define LENOVO_VENDORID 0x17aa 233#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 234#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 235#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 236 237/* Samsung */ 238#define SAMSUNG_VENDORID 0x144d 239#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 240#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 241 242/* Medion ? */ 243#define MEDION_VENDORID 0x161f 244#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 245#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 246 247/* Apple Computer Inc. */ 248#define APPLE_VENDORID 0x106b 249#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 250 251/* 252 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 253 * instead of their own, which is beyond my comprehension 254 * (see HDA_CODEC_STAC9221 below). 255 */ 256#define APPLE_INTEL_MAC 0x76808384 257 258/* LG Electronics */ 259#define LG_VENDORID 0x1854 260#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 261#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 262 263/* Fujitsu Siemens */ 264#define FS_VENDORID 0x1734 265#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 266#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 267#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 268 269/* Fujitsu Limited */ 270#define FL_VENDORID 0x10cf 271#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 272#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 273 274/* Toshiba */ 275#define TOSHIBA_VENDORID 0x1179 276#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 277#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 278#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 279 280/* Micro-Star International (MSI) */ 281#define MSI_VENDORID 0x1462 282#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 283#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 284#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 285 286/* Giga-Byte Technology */ 287#define GB_VENDORID 0x1458 288#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 289#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 290 291/* Uniwill ? */ 292#define UNIWILL_VENDORID 0x1584 293#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 294#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 295 296 297/* Misc constants.. */ 298#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 299#define HDA_AMP_MUTE_NONE (0) 300#define HDA_AMP_MUTE_LEFT (1 << 0) 301#define HDA_AMP_MUTE_RIGHT (1 << 1) 302#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 303 304#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 305#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 306 307#define HDA_DAC_PATH (1 << 0) 308#define HDA_ADC_PATH (1 << 1) 309#define HDA_ADC_RECSEL (1 << 2) 310 311#define HDA_DAC_LOCKED (1 << 3) 312#define HDA_ADC_LOCKED (1 << 4) 313 314#define HDA_CTL_OUT (1 << 0) 315#define HDA_CTL_IN (1 << 1) 316#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 317 318#define HDA_GPIO_MAX 8 319/* 0 - 7 = GPIO , 8 = Flush */ 320#define HDA_QUIRK_GPIO0 (1 << 0) 321#define HDA_QUIRK_GPIO1 (1 << 1) 322#define HDA_QUIRK_GPIO2 (1 << 2) 323#define HDA_QUIRK_GPIO3 (1 << 3) 324#define HDA_QUIRK_GPIO4 (1 << 4) 325#define HDA_QUIRK_GPIO5 (1 << 5) 326#define HDA_QUIRK_GPIO6 (1 << 6) 327#define HDA_QUIRK_GPIO7 (1 << 7) 328#define HDA_QUIRK_GPIOFLUSH (1 << 8) 329 330/* 9 - 25 = anything else */ 331#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 332#define HDA_QUIRK_FIXEDRATE (1 << 10) 333#define HDA_QUIRK_FORCESTEREO (1 << 11) 334#define HDA_QUIRK_EAPDINV (1 << 12) 335#define HDA_QUIRK_DMAPOS (1 << 13) 336 337/* 26 - 31 = vrefs */ 338#define HDA_QUIRK_IVREF50 (1 << 26) 339#define HDA_QUIRK_IVREF80 (1 << 27) 340#define HDA_QUIRK_IVREF100 (1 << 28) 341#define HDA_QUIRK_OVREF50 (1 << 29) 342#define HDA_QUIRK_OVREF80 (1 << 30) 343#define HDA_QUIRK_OVREF100 (1 << 31) 344 345#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 346 HDA_QUIRK_IVREF100) 347#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 348 HDA_QUIRK_OVREF100) 349#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 350 351#define SOUND_MASK_SKIP (1 << 30) 352#define SOUND_MASK_DISABLE (1 << 31) 353 354#if __FreeBSD_version < 600000 355#define taskqueue_drain(...) 356#endif 357 358static const struct { 359 char *key; 360 uint32_t value; 361} hdac_quirks_tab[] = { 362 { "gpio0", HDA_QUIRK_GPIO0 }, 363 { "gpio1", HDA_QUIRK_GPIO1 }, 364 { "gpio2", HDA_QUIRK_GPIO2 }, 365 { "gpio3", HDA_QUIRK_GPIO3 }, 366 { "gpio4", HDA_QUIRK_GPIO4 }, 367 { "gpio5", HDA_QUIRK_GPIO5 }, 368 { "gpio6", HDA_QUIRK_GPIO6 }, 369 { "gpio7", HDA_QUIRK_GPIO7 }, 370 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 371 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 372 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 373 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 374 { "eapdinv", HDA_QUIRK_EAPDINV }, 375 { "dmapos", HDA_QUIRK_DMAPOS }, 376 { "ivref50", HDA_QUIRK_IVREF50 }, 377 { "ivref80", HDA_QUIRK_IVREF80 }, 378 { "ivref100", HDA_QUIRK_IVREF100 }, 379 { "ovref50", HDA_QUIRK_OVREF50 }, 380 { "ovref80", HDA_QUIRK_OVREF80 }, 381 { "ovref100", HDA_QUIRK_OVREF100 }, 382 { "ivref", HDA_QUIRK_IVREF }, 383 { "ovref", HDA_QUIRK_OVREF }, 384 { "vref", HDA_QUIRK_VREF }, 385}; 386#define HDAC_QUIRKS_TAB_LEN \ 387 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 388 389#define HDA_BDL_MIN 2 390#define HDA_BDL_MAX 256 391#define HDA_BDL_DEFAULT HDA_BDL_MIN 392 393#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 394#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 395 396#define HDA_BUFSZ_MIN 4096 397#define HDA_BUFSZ_MAX 65536 398#define HDA_BUFSZ_DEFAULT 16384 399 400#define HDA_PARSE_MAXDEPTH 10 401 402#define HDAC_UNSOLTAG_EVENT_HP 0x00 403#define HDAC_UNSOLTAG_EVENT_TEST 0x01 404 405MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 406 407enum { 408 HDA_PARSE_MIXER, 409 HDA_PARSE_DIRECT 410}; 411 412/* Default */ 413static uint32_t hdac_fmt[] = { 414 AFMT_STEREO | AFMT_S16_LE, 415 0 416}; 417 418static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 419 420static const struct { 421 uint32_t model; 422 char *desc; 423} hdac_devices[] = { 424 { HDA_INTEL_82801F, "Intel 82801F" }, 425 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 426 { HDA_INTEL_82801G, "Intel 82801G" }, 427 { HDA_INTEL_82801H, "Intel 82801H" }, 428 { HDA_INTEL_82801I, "Intel 82801I" }, 429 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 430 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 431 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 432 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 433 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 434 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 435 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 436 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 437 { HDA_ATI_SB450, "ATI SB450" }, 438 { HDA_ATI_SB600, "ATI SB600" }, 439 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 440 { HDA_SIS_966, "SiS 966" }, 441 /* Unknown */ 442 { HDA_INTEL_ALL, "Intel (Unknown)" }, 443 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 444 { HDA_ATI_ALL, "ATI (Unknown)" }, 445 { HDA_VIA_ALL, "VIA (Unknown)" }, 446 { HDA_SIS_ALL, "SiS (Unknown)" }, 447}; 448#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 449 450static const struct { 451 uint16_t vendor; 452 uint8_t reg; 453 uint8_t mask; 454 uint8_t enable; 455} hdac_pcie_snoop[] = { 456 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 457 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 458 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 459}; 460#define HDAC_PCIESNOOP_LEN \ 461 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 462 463static const struct { 464 uint32_t rate; 465 int valid; 466 uint16_t base; 467 uint16_t mul; 468 uint16_t div; 469} hda_rate_tab[] = { 470 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 471 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 472 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 473 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 474 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 475 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 476 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 477 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 478 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 479 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 480 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 481 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 482 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 483 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 484 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 485 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 486 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 487 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 488 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 489 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 490 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 491 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 492 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 493 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 494 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 495 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 496 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 497 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 498 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 499 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 500 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 501 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 502 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 503 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 504 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 505}; 506#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 507 508/* All codecs you can eat... */ 509#define HDA_CODEC_CONSTRUCT(vendor, id) \ 510 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 511 512/* Realtek */ 513#define REALTEK_VENDORID 0x10ec 514#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 515#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 516#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 517#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 518#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 519#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 520#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 521#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 522#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 523#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 524#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 525#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 526 527/* Analog Devices */ 528#define ANALOGDEVICES_VENDORID 0x11d4 529#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 530#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 531#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 532#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 533#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 534#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 535#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 536 537/* CMedia */ 538#define CMEDIA_VENDORID 0x434d 539#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 540#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 541 542/* Sigmatel */ 543#define SIGMATEL_VENDORID 0x8384 544#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 545#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 546#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 547#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 548#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 549#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 550#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 551 552/* 553 * Conexant 554 * 555 * Ok, the truth is, I don't have any idea at all whether 556 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 557 * place that tell me it is "Venice" is from its Windows driver INF. 558 * 559 * Venice - CX????? 560 * Waikiki - CX20551-22 561 */ 562#define CONEXANT_VENDORID 0x14f1 563#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 564#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 565#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 566 567/* VIA */ 568#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 569#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 570#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 571#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 572#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 573#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 574#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 575#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 576#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 577#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 578#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 579#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 580#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 581 582 583/* Codecs */ 584static const struct { 585 uint32_t id; 586 char *name; 587} hdac_codecs[] = { 588 { HDA_CODEC_ALC260, "Realtek ALC260" }, 589 { HDA_CODEC_ALC262, "Realtek ALC262" }, 590 { HDA_CODEC_ALC268, "Realtek ALC268" }, 591 { HDA_CODEC_ALC660, "Realtek ALC660" }, 592 { HDA_CODEC_ALC861, "Realtek ALC861" }, 593 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 594 { HDA_CODEC_ALC880, "Realtek ALC880" }, 595 { HDA_CODEC_ALC882, "Realtek ALC882" }, 596 { HDA_CODEC_ALC883, "Realtek ALC883" }, 597 { HDA_CODEC_ALC885, "Realtek ALC885" }, 598 { HDA_CODEC_ALC888, "Realtek ALC888" }, 599 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 600 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 601 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 602 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 603 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 604 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 605 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 606 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 607 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 608 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 609 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 610 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 611 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 612 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 613 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 614 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 615 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 616 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 617 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 618 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 619 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 620 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 621 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 622 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 623 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 624 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 625 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 626 /* Unknown codec */ 627 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 628 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 629 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 630 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 631 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 632 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 633}; 634#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 635 636enum { 637 HDAC_HP_SWITCH_CTL, 638 HDAC_HP_SWITCH_CTRL, 639 HDAC_HP_SWITCH_DEBUG 640}; 641 642static const struct { 643 uint32_t model; 644 uint32_t id; 645 int type; 646 int inverted; 647 int polling; 648 int execsense; 649 nid_t hpnid; 650 nid_t spkrnid[8]; 651 nid_t eapdnid; 652} hdac_hp_switch[] = { 653 /* Specific OEM models */ 654 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 655 0, 0, -1, 17, { 16, -1 }, 16 }, 656 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 657 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 658 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 659 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 660 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 661 0, 0, -1, 6, { 5, -1 }, 5 }, 662 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 663 0, 0, -1, 6, { 5, -1 }, 5 }, 664 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 665 0, 0, -1, 6, { 5, -1 }, 5 }, 666 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 667 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 668 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 669 0, 0, -1, 6, { 5, -1 }, -1 }, 670 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 671 0, 0, -1, 27, { 20, -1 }, -1 }, 672 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 673 0, 0, -1, 13, { 14, -1 }, -1 }, 674 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 675 0, 0, -1, 13, { 14, -1 }, -1 }, 676 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 677 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 678 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 679 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 680 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 681 0, 0, -1, 10, { 13, -1 }, -1 }, 682 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 683 1, 0, -1, 26, { 27, -1 }, -1 }, 684 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 685 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 686 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 687 0, 0, -1, 27, { 20, -1 }, -1 }, 688 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 689 0, 0, -1, 20, { 21, -1 }, -1 }, 690 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 691 0, 0, -1, 20, { 21, -1 }, -1 }, 692 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 693 0, 0, -1, 20, { 21, -1 }, -1 }, 694 { ACER_A4710_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 695 0, 0, -1, 20, { 21, -1 }, -1 }, 696 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 697 0, 0, -1, 20, { 21, -1 }, -1 }, 698 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 699 0, 0, -1, 20, { 27, -1 }, -1 }, 700 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 701 0, 0, -1, 20, { 27, -1 }, -1 }, 702 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 703 0, 0, -1, 20, { 21, -1 }, -1 }, 704 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 705 0, 0, -1, 20, { 16, -1 }, -1 }, 706 /* 707 * All models that at least come from the same vendor with 708 * simmilar codec. 709 */ 710 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 711 0, 0, -1, 17, { 16, -1 }, 16 }, 712 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 713 0, 0, -1, 6, { 5, -1 }, 5 }, 714 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 715 0, 0, -1, 6, { 5, -1 }, -1 }, 716 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 717 0, 0, -1, 13, { 14, -1 }, -1 }, 718#if 0 719 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 720 1, 0, -1, 26, { 27, -1 }, -1 }, 721 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 722 0, 0, -1, 20, { 21, -1 }, -1 }, 723#endif 724}; 725#define HDAC_HP_SWITCH_LEN \ 726 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 727 728static const struct { 729 uint32_t model; 730 uint32_t id; 731 nid_t eapdnid; 732 int hp_switch; 733} hdac_eapd_switch[] = { 734 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 735 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 736 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 737}; 738#define HDAC_EAPD_SWITCH_LEN \ 739 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 740 741/**************************************************************************** 742 * Function prototypes 743 ****************************************************************************/ 744static void hdac_intr_handler(void *); 745static int hdac_reset(struct hdac_softc *); 746static int hdac_get_capabilities(struct hdac_softc *); 747static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 748static int hdac_dma_alloc(struct hdac_softc *, 749 struct hdac_dma *, bus_size_t); 750static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 751static int hdac_mem_alloc(struct hdac_softc *); 752static void hdac_mem_free(struct hdac_softc *); 753static int hdac_irq_alloc(struct hdac_softc *); 754static void hdac_irq_free(struct hdac_softc *); 755static void hdac_corb_init(struct hdac_softc *); 756static void hdac_rirb_init(struct hdac_softc *); 757static void hdac_corb_start(struct hdac_softc *); 758static void hdac_rirb_start(struct hdac_softc *); 759static void hdac_scan_codecs(struct hdac_softc *, int); 760static int hdac_probe_codec(struct hdac_codec *); 761static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 762static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 763 764static void hdac_attach2(void *); 765 766static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 767 uint32_t, int); 768static void hdac_command_send_internal(struct hdac_softc *, 769 struct hdac_command_list *, int); 770 771static int hdac_probe(device_t); 772static int hdac_attach(device_t); 773static int hdac_detach(device_t); 774static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 775static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 776 uint32_t, int, int); 777static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 778 nid_t, int, int); 779static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 780 nid_t, nid_t, int, int, int, int, int, int); 781static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 782static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 783 784static int hdac_rirb_flush(struct hdac_softc *sc); 785static int hdac_unsolq_flush(struct hdac_softc *sc); 786 787#define hdac_command(a1, a2, a3) \ 788 hdac_command_sendone_internal(a1, a2, a3) 789 790#define hdac_codec_id(d) \ 791 ((uint32_t)((d == NULL) ? 0x00000000 : \ 792 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 793 ((uint32_t)(d)->device_id & 0x0000ffff)))) 794 795static char * 796hdac_codec_name(struct hdac_devinfo *devinfo) 797{ 798 uint32_t id; 799 int i; 800 801 id = hdac_codec_id(devinfo); 802 803 for (i = 0; i < HDAC_CODECS_LEN; i++) { 804 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 805 return (hdac_codecs[i].name); 806 } 807 808 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 809} 810 811static char * 812hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 813{ 814 static char *ossname[] = SOUND_DEVICE_NAMES; 815 static char *unknown = "???"; 816 int i; 817 818 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 819 if (devmask & (1 << i)) 820 return (ossname[i]); 821 } 822 return (unknown); 823} 824 825static void 826hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 827{ 828 static char *ossname[] = SOUND_DEVICE_NAMES; 829 int i, first = 1; 830 831 bzero(buf, len); 832 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 833 if (mask & (1 << i)) { 834 if (first == 0) 835 strlcat(buf, ", ", len); 836 strlcat(buf, ossname[i], len); 837 first = 0; 838 } 839 } 840} 841 842static struct hdac_audio_ctl * 843hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 844{ 845 if (devinfo == NULL || 846 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 847 index == NULL || devinfo->function.audio.ctl == NULL || 848 devinfo->function.audio.ctlcnt < 1 || 849 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 850 return (NULL); 851 return (&devinfo->function.audio.ctl[(*index)++]); 852} 853 854static struct hdac_audio_ctl * 855hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 856 int index, int cnt) 857{ 858 struct hdac_audio_ctl *ctl, *retctl = NULL; 859 int i, at, atindex, found = 0; 860 861 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 862 return (NULL); 863 864 at = cnt; 865 if (at == 0) 866 at = 1; 867 else if (at < 0) 868 at = -1; 869 atindex = index; 870 if (atindex < 0) 871 atindex = -1; 872 873 i = 0; 874 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 875 if (ctl->enable == 0 || ctl->widget == NULL) 876 continue; 877 if (!(ctl->widget->nid == nid && (atindex == -1 || 878 ctl->index == atindex))) 879 continue; 880 found++; 881 if (found == cnt) 882 return (ctl); 883 retctl = ctl; 884 } 885 886 return ((at == -1) ? retctl : NULL); 887} 888 889static void 890hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 891{ 892 struct hdac_softc *sc; 893 struct hdac_widget *w; 894 struct hdac_audio_ctl *ctl; 895 uint32_t val, id, res; 896 int i = 0, j, timeout, forcemute; 897 nid_t cad; 898 899 if (devinfo == NULL || devinfo->codec == NULL || 900 devinfo->codec->sc == NULL) 901 return; 902 903 sc = devinfo->codec->sc; 904 cad = devinfo->codec->cad; 905 id = hdac_codec_id(devinfo); 906 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 907 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 908 sc->pci_subvendor) && 909 hdac_hp_switch[i].id == id) 910 break; 911 } 912 913 if (i >= HDAC_HP_SWITCH_LEN) 914 return; 915 916 forcemute = 0; 917 if (hdac_hp_switch[i].eapdnid != -1) { 918 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 919 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 920 forcemute = (w->param.eapdbtl & 921 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 922 } 923 924 if (hdac_hp_switch[i].execsense != -1) 925 hdac_command(sc, 926 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 927 hdac_hp_switch[i].execsense), cad); 928 929 timeout = 10000; 930 do { 931 res = hdac_command(sc, 932 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 933 cad); 934 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 935 break; 936 DELAY(10); 937 } while (--timeout != 0); 938 939 HDA_BOOTVERBOSE( 940 device_printf(sc->dev, 941 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 942 hdac_hp_switch[i].hpnid, timeout, res); 943 ); 944 945 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 946 res ^= hdac_hp_switch[i].inverted; 947 948 switch (hdac_hp_switch[i].type) { 949 case HDAC_HP_SWITCH_CTL: 950 ctl = hdac_audio_ctl_amp_get(devinfo, 951 hdac_hp_switch[i].hpnid, 0, 1); 952 if (ctl != NULL) { 953 val = (res != 0 && forcemute == 0) ? 954 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 955 if (val != ctl->muted) { 956 ctl->muted = val; 957 hdac_audio_ctl_amp_set(ctl, 958 HDA_AMP_MUTE_DEFAULT, ctl->left, 959 ctl->right); 960 } 961 } 962 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 963 ctl = hdac_audio_ctl_amp_get(devinfo, 964 hdac_hp_switch[i].spkrnid[j], 0, 1); 965 if (ctl == NULL) 966 continue; 967 val = (res != 0 || forcemute == 1) ? 968 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 969 if (val == ctl->muted) 970 continue; 971 ctl->muted = val; 972 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 973 ctl->left, ctl->right); 974 } 975 break; 976 case HDAC_HP_SWITCH_CTRL: 977 if (res != 0) { 978 /* HP in */ 979 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 980 if (w != NULL && w->type == 981 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 982 if (forcemute == 0) 983 val = w->wclass.pin.ctrl | 984 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 985 else 986 val = w->wclass.pin.ctrl & 987 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 988 if (val != w->wclass.pin.ctrl) { 989 w->wclass.pin.ctrl = val; 990 hdac_command(sc, 991 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 992 w->nid, w->wclass.pin.ctrl), cad); 993 } 994 } 995 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 996 w = hdac_widget_get(devinfo, 997 hdac_hp_switch[i].spkrnid[j]); 998 if (w == NULL || w->type != 999 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1000 continue; 1001 val = w->wclass.pin.ctrl & 1002 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1003 if (val == w->wclass.pin.ctrl) 1004 continue; 1005 w->wclass.pin.ctrl = val; 1006 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1007 cad, w->nid, w->wclass.pin.ctrl), cad); 1008 } 1009 } else { 1010 /* HP out */ 1011 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1012 if (w != NULL && w->type == 1013 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1014 val = w->wclass.pin.ctrl & 1015 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1016 if (val != w->wclass.pin.ctrl) { 1017 w->wclass.pin.ctrl = val; 1018 hdac_command(sc, 1019 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1020 w->nid, w->wclass.pin.ctrl), cad); 1021 } 1022 } 1023 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1024 w = hdac_widget_get(devinfo, 1025 hdac_hp_switch[i].spkrnid[j]); 1026 if (w == NULL || w->type != 1027 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1028 continue; 1029 if (forcemute == 0) 1030 val = w->wclass.pin.ctrl | 1031 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1032 else 1033 val = w->wclass.pin.ctrl & 1034 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1035 if (val == w->wclass.pin.ctrl) 1036 continue; 1037 w->wclass.pin.ctrl = val; 1038 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1039 cad, w->nid, w->wclass.pin.ctrl), cad); 1040 } 1041 } 1042 break; 1043 case HDAC_HP_SWITCH_DEBUG: 1044 if (hdac_hp_switch[i].execsense != -1) 1045 hdac_command(sc, 1046 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1047 hdac_hp_switch[i].execsense), cad); 1048 res = hdac_command(sc, 1049 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1050 device_printf(sc->dev, 1051 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1052 hdac_hp_switch[i].hpnid, res); 1053 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1054 w = hdac_widget_get(devinfo, 1055 hdac_hp_switch[i].spkrnid[j]); 1056 if (w == NULL || w->type != 1057 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1058 continue; 1059 if (hdac_hp_switch[i].execsense != -1) 1060 hdac_command(sc, 1061 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1062 hdac_hp_switch[i].execsense), cad); 1063 res = hdac_command(sc, 1064 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1065 device_printf(sc->dev, 1066 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1067 j + 1, w->nid, res); 1068 } 1069 break; 1070 default: 1071 break; 1072 } 1073} 1074 1075static void 1076hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1077{ 1078 struct hdac_softc *sc; 1079 struct hdac_devinfo *devinfo = NULL; 1080 device_t *devlist = NULL; 1081 int devcount, i; 1082 1083 if (codec == NULL || codec->sc == NULL) 1084 return; 1085 1086 sc = codec->sc; 1087 1088 HDA_BOOTVERBOSE( 1089 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1090 ); 1091 1092 device_get_children(sc->dev, &devlist, &devcount); 1093 for (i = 0; devlist != NULL && i < devcount; i++) { 1094 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1095 if (devinfo != NULL && devinfo->node_type == 1096 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1097 devinfo->codec != NULL && 1098 devinfo->codec->cad == codec->cad) { 1099 break; 1100 } else 1101 devinfo = NULL; 1102 } 1103 if (devlist != NULL) 1104 free(devlist, M_TEMP); 1105 1106 if (devinfo == NULL) 1107 return; 1108 1109 switch (tag) { 1110 case HDAC_UNSOLTAG_EVENT_HP: 1111 hdac_hp_switch_handler(devinfo); 1112 break; 1113 case HDAC_UNSOLTAG_EVENT_TEST: 1114 device_printf(sc->dev, "Unsol Test!\n"); 1115 break; 1116 default: 1117 break; 1118 } 1119} 1120 1121static int 1122hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1123{ 1124 /* XXX to be removed */ 1125#ifdef HDAC_INTR_EXTRA 1126 uint32_t res; 1127#endif 1128 1129 if (!(ch->flags & HDAC_CHN_RUNNING)) 1130 return (0); 1131 1132 /* XXX to be removed */ 1133#ifdef HDAC_INTR_EXTRA 1134 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1135#endif 1136 1137 /* XXX to be removed */ 1138#ifdef HDAC_INTR_EXTRA 1139 HDA_BOOTVERBOSE( 1140 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1141 device_printf(sc->dev, 1142 "PCMDIR_%s intr triggered beyond stream boundary:" 1143 "%08x\n", 1144 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1145 ); 1146#endif 1147 1148 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1149 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1150 1151 /* XXX to be removed */ 1152#ifdef HDAC_INTR_EXTRA 1153 if (res & HDAC_SDSTS_BCIS) { 1154#endif 1155 return (1); 1156 /* XXX to be removed */ 1157#ifdef HDAC_INTR_EXTRA 1158 } 1159#endif 1160 1161 return (0); 1162} 1163 1164/**************************************************************************** 1165 * void hdac_intr_handler(void *) 1166 * 1167 * Interrupt handler. Processes interrupts received from the hdac. 1168 ****************************************************************************/ 1169static void 1170hdac_intr_handler(void *context) 1171{ 1172 struct hdac_softc *sc; 1173 uint32_t intsts; 1174 uint8_t rirbsts; 1175 struct hdac_rirb *rirb_base; 1176 uint32_t trigger; 1177 1178 sc = (struct hdac_softc *)context; 1179 1180 hdac_lock(sc); 1181 if (sc->polling != 0) { 1182 hdac_unlock(sc); 1183 return; 1184 } 1185 1186 /* Do we have anything to do? */ 1187 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1188 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1189 hdac_unlock(sc); 1190 return; 1191 } 1192 1193 trigger = 0; 1194 1195 /* Was this a controller interrupt? */ 1196 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1197 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1198 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1199 /* Get as many responses that we can */ 1200 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1201 HDAC_WRITE_1(&sc->mem, 1202 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1203 if (hdac_rirb_flush(sc) != 0) 1204 trigger |= HDAC_TRIGGER_UNSOL; 1205 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1206 } 1207 /* XXX to be removed */ 1208 /* Clear interrupt and exit */ 1209#ifdef HDAC_INTR_EXTRA 1210 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1211#endif 1212 } 1213 1214 if (intsts & HDAC_INTSTS_SIS_MASK) { 1215 if ((intsts & (1 << sc->num_iss)) && 1216 hdac_stream_intr(sc, &sc->play) != 0) 1217 trigger |= HDAC_TRIGGER_PLAY; 1218 if ((intsts & (1 << 0)) && 1219 hdac_stream_intr(sc, &sc->rec) != 0) 1220 trigger |= HDAC_TRIGGER_REC; 1221 /* XXX to be removed */ 1222#ifdef HDAC_INTR_EXTRA 1223 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1224 HDAC_INTSTS_SIS_MASK); 1225#endif 1226 } 1227 1228 hdac_unlock(sc); 1229 1230 if (trigger & HDAC_TRIGGER_PLAY) 1231 chn_intr(sc->play.c); 1232 if (trigger & HDAC_TRIGGER_REC) 1233 chn_intr(sc->rec.c); 1234 if (trigger & HDAC_TRIGGER_UNSOL) 1235 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1236} 1237 1238/**************************************************************************** 1239 * int hdac_reset(hdac_softc *) 1240 * 1241 * Reset the hdac to a quiescent and known state. 1242 ****************************************************************************/ 1243static int 1244hdac_reset(struct hdac_softc *sc) 1245{ 1246 uint32_t gctl; 1247 int count, i; 1248 1249 /* 1250 * Stop all Streams DMA engine 1251 */ 1252 for (i = 0; i < sc->num_iss; i++) 1253 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1254 for (i = 0; i < sc->num_oss; i++) 1255 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1256 for (i = 0; i < sc->num_bss; i++) 1257 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1258 1259 /* 1260 * Stop Control DMA engines. 1261 */ 1262 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1263 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1264 1265 /* 1266 * Reset DMA position buffer. 1267 */ 1268 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1269 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1270 1271 /* 1272 * Reset the controller. The reset must remain asserted for 1273 * a minimum of 100us. 1274 */ 1275 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1276 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1277 count = 10000; 1278 do { 1279 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1280 if (!(gctl & HDAC_GCTL_CRST)) 1281 break; 1282 DELAY(10); 1283 } while (--count); 1284 if (gctl & HDAC_GCTL_CRST) { 1285 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1286 return (ENXIO); 1287 } 1288 DELAY(100); 1289 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1290 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1291 count = 10000; 1292 do { 1293 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1294 if (gctl & HDAC_GCTL_CRST) 1295 break; 1296 DELAY(10); 1297 } while (--count); 1298 if (!(gctl & HDAC_GCTL_CRST)) { 1299 device_printf(sc->dev, "Device stuck in reset\n"); 1300 return (ENXIO); 1301 } 1302 1303 /* 1304 * Wait for codecs to finish their own reset sequence. The delay here 1305 * should be of 250us but for some reasons, on it's not enough on my 1306 * computer. Let's use twice as much as necessary to make sure that 1307 * it's reset properly. 1308 */ 1309 DELAY(1000); 1310 1311 return (0); 1312} 1313 1314 1315/**************************************************************************** 1316 * int hdac_get_capabilities(struct hdac_softc *); 1317 * 1318 * Retreive the general capabilities of the hdac; 1319 * Number of Input Streams 1320 * Number of Output Streams 1321 * Number of bidirectional Streams 1322 * 64bit ready 1323 * CORB and RIRB sizes 1324 ****************************************************************************/ 1325static int 1326hdac_get_capabilities(struct hdac_softc *sc) 1327{ 1328 uint16_t gcap; 1329 uint8_t corbsize, rirbsize; 1330 1331 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1332 sc->num_iss = HDAC_GCAP_ISS(gcap); 1333 sc->num_oss = HDAC_GCAP_OSS(gcap); 1334 sc->num_bss = HDAC_GCAP_BSS(gcap); 1335 1336 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1337 1338 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1339 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1340 HDAC_CORBSIZE_CORBSZCAP_256) 1341 sc->corb_size = 256; 1342 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1343 HDAC_CORBSIZE_CORBSZCAP_16) 1344 sc->corb_size = 16; 1345 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1346 HDAC_CORBSIZE_CORBSZCAP_2) 1347 sc->corb_size = 2; 1348 else { 1349 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1350 __func__, corbsize); 1351 return (ENXIO); 1352 } 1353 1354 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1355 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1356 HDAC_RIRBSIZE_RIRBSZCAP_256) 1357 sc->rirb_size = 256; 1358 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1359 HDAC_RIRBSIZE_RIRBSZCAP_16) 1360 sc->rirb_size = 16; 1361 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1362 HDAC_RIRBSIZE_RIRBSZCAP_2) 1363 sc->rirb_size = 2; 1364 else { 1365 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1366 __func__, rirbsize); 1367 return (ENXIO); 1368 } 1369 1370 return (0); 1371} 1372 1373 1374/**************************************************************************** 1375 * void hdac_dma_cb 1376 * 1377 * This function is called by bus_dmamap_load when the mapping has been 1378 * established. We just record the physical address of the mapping into 1379 * the struct hdac_dma passed in. 1380 ****************************************************************************/ 1381static void 1382hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1383{ 1384 struct hdac_dma *dma; 1385 1386 if (error == 0) { 1387 dma = (struct hdac_dma *)callback_arg; 1388 dma->dma_paddr = segs[0].ds_addr; 1389 } 1390} 1391 1392 1393/**************************************************************************** 1394 * int hdac_dma_alloc 1395 * 1396 * This function allocate and setup a dma region (struct hdac_dma). 1397 * It must be freed by a corresponding hdac_dma_free. 1398 ****************************************************************************/ 1399static int 1400hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1401{ 1402 bus_size_t roundsz; 1403 int result; 1404 int lowaddr; 1405 1406 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1407 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1408 BUS_SPACE_MAXADDR_32BIT; 1409 bzero(dma, sizeof(*dma)); 1410 1411 /* 1412 * Create a DMA tag 1413 */ 1414 result = bus_dma_tag_create(NULL, /* parent */ 1415 HDAC_DMA_ALIGNMENT, /* alignment */ 1416 0, /* boundary */ 1417 lowaddr, /* lowaddr */ 1418 BUS_SPACE_MAXADDR, /* highaddr */ 1419 NULL, /* filtfunc */ 1420 NULL, /* fistfuncarg */ 1421 roundsz, /* maxsize */ 1422 1, /* nsegments */ 1423 roundsz, /* maxsegsz */ 1424 0, /* flags */ 1425 NULL, /* lockfunc */ 1426 NULL, /* lockfuncarg */ 1427 &dma->dma_tag); /* dmat */ 1428 if (result != 0) { 1429 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1430 __func__, result); 1431 goto hdac_dma_alloc_fail; 1432 } 1433 1434 /* 1435 * Allocate DMA memory 1436 */ 1437 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1438 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1439 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1440 &dma->dma_map); 1441 if (result != 0) { 1442 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1443 __func__, result); 1444 goto hdac_dma_alloc_fail; 1445 } 1446 1447 dma->dma_size = roundsz; 1448 1449 /* 1450 * Map the memory 1451 */ 1452 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1453 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1454 if (result != 0 || dma->dma_paddr == 0) { 1455 if (result == 0) 1456 result = ENOMEM; 1457 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1458 __func__, result); 1459 goto hdac_dma_alloc_fail; 1460 } 1461 1462 HDA_BOOTVERBOSE( 1463 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1464 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1465 ); 1466 1467 return (0); 1468 1469hdac_dma_alloc_fail: 1470 hdac_dma_free(sc, dma); 1471 1472 return (result); 1473} 1474 1475 1476/**************************************************************************** 1477 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1478 * 1479 * Free a struct dhac_dma that has been previously allocated via the 1480 * hdac_dma_alloc function. 1481 ****************************************************************************/ 1482static void 1483hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1484{ 1485 if (dma->dma_map != NULL) { 1486#if 0 1487 /* Flush caches */ 1488 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1489 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1490#endif 1491 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1492 } 1493 if (dma->dma_vaddr != NULL) { 1494 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1495 dma->dma_vaddr = NULL; 1496 } 1497 dma->dma_map = NULL; 1498 if (dma->dma_tag != NULL) { 1499 bus_dma_tag_destroy(dma->dma_tag); 1500 dma->dma_tag = NULL; 1501 } 1502 dma->dma_size = 0; 1503} 1504 1505/**************************************************************************** 1506 * int hdac_mem_alloc(struct hdac_softc *) 1507 * 1508 * Allocate all the bus resources necessary to speak with the physical 1509 * controller. 1510 ****************************************************************************/ 1511static int 1512hdac_mem_alloc(struct hdac_softc *sc) 1513{ 1514 struct hdac_mem *mem; 1515 1516 mem = &sc->mem; 1517 mem->mem_rid = PCIR_BAR(0); 1518 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1519 &mem->mem_rid, RF_ACTIVE); 1520 if (mem->mem_res == NULL) { 1521 device_printf(sc->dev, 1522 "%s: Unable to allocate memory resource\n", __func__); 1523 return (ENOMEM); 1524 } 1525 mem->mem_tag = rman_get_bustag(mem->mem_res); 1526 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1527 1528 return (0); 1529} 1530 1531/**************************************************************************** 1532 * void hdac_mem_free(struct hdac_softc *) 1533 * 1534 * Free up resources previously allocated by hdac_mem_alloc. 1535 ****************************************************************************/ 1536static void 1537hdac_mem_free(struct hdac_softc *sc) 1538{ 1539 struct hdac_mem *mem; 1540 1541 mem = &sc->mem; 1542 if (mem->mem_res != NULL) 1543 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1544 mem->mem_res); 1545 mem->mem_res = NULL; 1546} 1547 1548/**************************************************************************** 1549 * int hdac_irq_alloc(struct hdac_softc *) 1550 * 1551 * Allocate and setup the resources necessary for interrupt handling. 1552 ****************************************************************************/ 1553static int 1554hdac_irq_alloc(struct hdac_softc *sc) 1555{ 1556 struct hdac_irq *irq; 1557 int result; 1558 1559 irq = &sc->irq; 1560 irq->irq_rid = 0x0; 1561 1562#if __FreeBSD_version >= 602106 1563 if ((sc->flags & HDAC_F_MSI) && 1564 (result = pci_msi_count(sc->dev)) == 1 && 1565 pci_alloc_msi(sc->dev, &result) == 0) 1566 irq->irq_rid = 0x1; 1567 else 1568#endif 1569 sc->flags &= ~HDAC_F_MSI; 1570 1571 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1572 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1573 if (irq->irq_res == NULL) { 1574 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1575 __func__); 1576 goto hdac_irq_alloc_fail; 1577 } 1578 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1579 hdac_intr_handler, sc, &irq->irq_handle); 1580 if (result != 0) { 1581 device_printf(sc->dev, 1582 "%s: Unable to setup interrupt handler (%x)\n", 1583 __func__, result); 1584 goto hdac_irq_alloc_fail; 1585 } 1586 1587 return (0); 1588 1589hdac_irq_alloc_fail: 1590 hdac_irq_free(sc); 1591 1592 return (ENXIO); 1593} 1594 1595/**************************************************************************** 1596 * void hdac_irq_free(struct hdac_softc *) 1597 * 1598 * Free up resources previously allocated by hdac_irq_alloc. 1599 ****************************************************************************/ 1600static void 1601hdac_irq_free(struct hdac_softc *sc) 1602{ 1603 struct hdac_irq *irq; 1604 1605 irq = &sc->irq; 1606 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1607 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1608 if (irq->irq_res != NULL) 1609 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1610 irq->irq_res); 1611#if __FreeBSD_version >= 602106 1612 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1613 pci_release_msi(sc->dev); 1614#endif 1615 irq->irq_handle = NULL; 1616 irq->irq_res = NULL; 1617 irq->irq_rid = 0x0; 1618} 1619 1620/**************************************************************************** 1621 * void hdac_corb_init(struct hdac_softc *) 1622 * 1623 * Initialize the corb registers for operations but do not start it up yet. 1624 * The CORB engine must not be running when this function is called. 1625 ****************************************************************************/ 1626static void 1627hdac_corb_init(struct hdac_softc *sc) 1628{ 1629 uint8_t corbsize; 1630 uint64_t corbpaddr; 1631 1632 /* Setup the CORB size. */ 1633 switch (sc->corb_size) { 1634 case 256: 1635 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1636 break; 1637 case 16: 1638 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1639 break; 1640 case 2: 1641 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1642 break; 1643 default: 1644 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1645 } 1646 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1647 1648 /* Setup the CORB Address in the hdac */ 1649 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1650 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1651 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1652 1653 /* Set the WP and RP */ 1654 sc->corb_wp = 0; 1655 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1656 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1657 /* 1658 * The HDA specification indicates that the CORBRPRST bit will always 1659 * read as zero. Unfortunately, it seems that at least the 82801G 1660 * doesn't reset the bit to zero, which stalls the corb engine. 1661 * manually reset the bit to zero before continuing. 1662 */ 1663 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1664 1665 /* Enable CORB error reporting */ 1666#if 0 1667 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1668#endif 1669} 1670 1671/**************************************************************************** 1672 * void hdac_rirb_init(struct hdac_softc *) 1673 * 1674 * Initialize the rirb registers for operations but do not start it up yet. 1675 * The RIRB engine must not be running when this function is called. 1676 ****************************************************************************/ 1677static void 1678hdac_rirb_init(struct hdac_softc *sc) 1679{ 1680 uint8_t rirbsize; 1681 uint64_t rirbpaddr; 1682 1683 /* Setup the RIRB size. */ 1684 switch (sc->rirb_size) { 1685 case 256: 1686 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1687 break; 1688 case 16: 1689 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1690 break; 1691 case 2: 1692 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1693 break; 1694 default: 1695 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1696 } 1697 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1698 1699 /* Setup the RIRB Address in the hdac */ 1700 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1701 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1702 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1703 1704 /* Setup the WP and RP */ 1705 sc->rirb_rp = 0; 1706 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1707 1708 if (sc->polling == 0) { 1709 /* Setup the interrupt threshold */ 1710 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1711 1712 /* Enable Overrun and response received reporting */ 1713#if 0 1714 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1715 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1716#else 1717 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1718#endif 1719 } 1720 1721#if 0 1722 /* 1723 * Make sure that the Host CPU cache doesn't contain any dirty 1724 * cache lines that falls in the rirb. If I understood correctly, it 1725 * should be sufficient to do this only once as the rirb is purely 1726 * read-only from now on. 1727 */ 1728 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1729 BUS_DMASYNC_PREREAD); 1730#endif 1731} 1732 1733/**************************************************************************** 1734 * void hdac_corb_start(hdac_softc *) 1735 * 1736 * Startup the corb DMA engine 1737 ****************************************************************************/ 1738static void 1739hdac_corb_start(struct hdac_softc *sc) 1740{ 1741 uint32_t corbctl; 1742 1743 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1744 corbctl |= HDAC_CORBCTL_CORBRUN; 1745 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1746} 1747 1748/**************************************************************************** 1749 * void hdac_rirb_start(hdac_softc *) 1750 * 1751 * Startup the rirb DMA engine 1752 ****************************************************************************/ 1753static void 1754hdac_rirb_start(struct hdac_softc *sc) 1755{ 1756 uint32_t rirbctl; 1757 1758 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1759 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1760 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1761} 1762 1763 1764/**************************************************************************** 1765 * void hdac_scan_codecs(struct hdac_softc *, int) 1766 * 1767 * Scan the bus for available codecs, starting with num. 1768 ****************************************************************************/ 1769static void 1770hdac_scan_codecs(struct hdac_softc *sc, int num) 1771{ 1772 struct hdac_codec *codec; 1773 int i; 1774 uint16_t statests; 1775 1776 if (num < 0) 1777 num = 0; 1778 if (num >= HDAC_CODEC_MAX) 1779 num = HDAC_CODEC_MAX - 1; 1780 1781 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1782 for (i = num; i < HDAC_CODEC_MAX; i++) { 1783 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1784 /* We have found a codec. */ 1785 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1786 M_HDAC, M_ZERO | M_NOWAIT); 1787 if (codec == NULL) { 1788 device_printf(sc->dev, 1789 "Unable to allocate memory for codec\n"); 1790 continue; 1791 } 1792 codec->commands = NULL; 1793 codec->responses_received = 0; 1794 codec->verbs_sent = 0; 1795 codec->sc = sc; 1796 codec->cad = i; 1797 sc->codecs[i] = codec; 1798 if (hdac_probe_codec(codec) != 0) 1799 break; 1800 } 1801 } 1802 /* All codecs have been probed, now try to attach drivers to them */ 1803 /* bus_generic_attach(sc->dev); */ 1804} 1805 1806/**************************************************************************** 1807 * void hdac_probe_codec(struct hdac_softc *, int) 1808 * 1809 * Probe a the given codec_id for available function groups. 1810 ****************************************************************************/ 1811static int 1812hdac_probe_codec(struct hdac_codec *codec) 1813{ 1814 struct hdac_softc *sc = codec->sc; 1815 struct hdac_devinfo *devinfo; 1816 uint32_t vendorid, revisionid, subnode; 1817 int startnode; 1818 int endnode; 1819 int i; 1820 nid_t cad = codec->cad; 1821 1822 HDA_BOOTVERBOSE( 1823 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1824 ); 1825 vendorid = hdac_command(sc, 1826 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1827 cad); 1828 revisionid = hdac_command(sc, 1829 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1830 cad); 1831 subnode = hdac_command(sc, 1832 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1833 cad); 1834 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1835 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1836 1837 HDA_BOOTVERBOSE( 1838 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1839 startnode, endnode); 1840 ); 1841 for (i = startnode; i < endnode; i++) { 1842 devinfo = hdac_probe_function(codec, i); 1843 if (devinfo != NULL) { 1844 /* XXX Ignore other FG. */ 1845 devinfo->vendor_id = 1846 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1847 devinfo->device_id = 1848 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1849 devinfo->revision_id = 1850 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1851 devinfo->stepping_id = 1852 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1853 HDA_BOOTVERBOSE( 1854 device_printf(sc->dev, 1855 "HDA_DEBUG: \tFound AFG nid=%d " 1856 "[startnode=%d endnode=%d]\n", 1857 devinfo->nid, startnode, endnode); 1858 ); 1859 return (1); 1860 } 1861 } 1862 1863 HDA_BOOTVERBOSE( 1864 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1865 ); 1866 return (0); 1867} 1868 1869static struct hdac_devinfo * 1870hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1871{ 1872 struct hdac_softc *sc = codec->sc; 1873 struct hdac_devinfo *devinfo; 1874 uint32_t fctgrptype; 1875 nid_t cad = codec->cad; 1876 1877 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1878 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1879 1880 /* XXX For now, ignore other FG. */ 1881 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1882 return (NULL); 1883 1884 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1885 M_NOWAIT | M_ZERO); 1886 if (devinfo == NULL) { 1887 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1888 __func__); 1889 return (NULL); 1890 } 1891 1892 devinfo->nid = nid; 1893 devinfo->node_type = fctgrptype; 1894 devinfo->codec = codec; 1895 1896 hdac_add_child(sc, devinfo); 1897 1898 return (devinfo); 1899} 1900 1901static void 1902hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1903{ 1904 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1905 device_set_ivars(devinfo->dev, (void *)devinfo); 1906 /* XXX - Print more information when booting verbose??? */ 1907} 1908 1909static void 1910hdac_widget_connection_parse(struct hdac_widget *w) 1911{ 1912 struct hdac_softc *sc = w->devinfo->codec->sc; 1913 uint32_t res; 1914 int i, j, max, ents, entnum; 1915 nid_t cad = w->devinfo->codec->cad; 1916 nid_t nid = w->nid; 1917 nid_t cnid, addcnid, prevcnid; 1918 1919 w->nconns = 0; 1920 1921 res = hdac_command(sc, 1922 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1923 1924 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1925 1926 if (ents < 1) 1927 return; 1928 1929 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1930 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1931 prevcnid = 0; 1932 1933#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1934#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1935#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1936#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1937#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1938 1939 for (i = 0; i < ents; i += entnum) { 1940 res = hdac_command(sc, 1941 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1942 for (j = 0; j < entnum; j++) { 1943 cnid = CONN_CNID(res, entnum, j); 1944 if (cnid == 0) { 1945 if (w->nconns < ents) 1946 device_printf(sc->dev, 1947 "%s: nid=%d WARNING: zero cnid " 1948 "entnum=%d j=%d index=%d " 1949 "entries=%d found=%d res=0x%08x\n", 1950 __func__, nid, entnum, j, i, 1951 ents, w->nconns, res); 1952 else 1953 goto getconns_out; 1954 } 1955 if (cnid < w->devinfo->startnode || 1956 cnid >= w->devinfo->endnode) { 1957 HDA_BOOTVERBOSE( 1958 device_printf(sc->dev, 1959 "%s: GHOST: nid=%d j=%d " 1960 "entnum=%d index=%d res=0x%08x\n", 1961 __func__, nid, j, entnum, i, res); 1962 ); 1963 } 1964 if (CONN_RANGE(res, entnum, j) == 0) 1965 addcnid = cnid; 1966 else if (prevcnid == 0 || prevcnid >= cnid) { 1967 device_printf(sc->dev, 1968 "%s: WARNING: Invalid child range " 1969 "nid=%d index=%d j=%d entnum=%d " 1970 "prevcnid=%d cnid=%d res=0x%08x\n", 1971 __func__, nid, i, j, entnum, prevcnid, 1972 cnid, res); 1973 addcnid = cnid; 1974 } else 1975 addcnid = prevcnid + 1; 1976 while (addcnid <= cnid) { 1977 if (w->nconns > max) { 1978 device_printf(sc->dev, 1979 "%s: nid=%d: Adding %d: " 1980 "Max connection reached! max=%d\n", 1981 __func__, nid, addcnid, max + 1); 1982 goto getconns_out; 1983 } 1984 w->conns[w->nconns++] = addcnid++; 1985 } 1986 prevcnid = cnid; 1987 } 1988 } 1989 1990getconns_out: 1991 HDA_BOOTVERBOSE( 1992 device_printf(sc->dev, 1993 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1994 __func__, nid, ents, w->nconns); 1995 ); 1996 return; 1997} 1998 1999static uint32_t 2000hdac_widget_pin_getconfig(struct hdac_widget *w) 2001{ 2002 struct hdac_softc *sc; 2003 uint32_t config, orig, id; 2004 nid_t cad, nid; 2005 2006 sc = w->devinfo->codec->sc; 2007 cad = w->devinfo->codec->cad; 2008 nid = w->nid; 2009 id = hdac_codec_id(w->devinfo); 2010 2011 config = hdac_command(sc, 2012 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2013 cad); 2014 orig = config; 2015 2016 /* 2017 * XXX REWRITE!!!! Don't argue! 2018 */ 2019 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2020 switch (nid) { 2021 case 26: 2022 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2023 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2024 break; 2025 case 27: 2026 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2027 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2028 break; 2029 default: 2030 break; 2031 } 2032 } else if (id == HDA_CODEC_ALC880 && 2033 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2034 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2035 /* 2036 * Super broken BIOS 2037 */ 2038 switch (nid) { 2039 case 20: 2040 break; 2041 case 21: 2042 break; 2043 case 22: 2044 break; 2045 case 23: 2046 break; 2047 case 24: /* MIC1 */ 2048 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2049 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2050 break; 2051 case 25: /* XXX MIC2 */ 2052 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2053 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2054 break; 2055 case 26: /* LINE1 */ 2056 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2057 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2058 break; 2059 case 27: /* XXX LINE2 */ 2060 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2061 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2062 break; 2063 case 28: /* CD */ 2064 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2065 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2066 break; 2067 case 30: 2068 break; 2069 case 31: 2070 break; 2071 default: 2072 break; 2073 } 2074 } else if (id == HDA_CODEC_ALC883 && 2075 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2076 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2077 switch (nid) { 2078 case 25: 2079 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2080 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2081 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2082 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2083 break; 2084 case 28: 2085 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2086 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2087 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2088 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2089 break; 2090 default: 2091 break; 2092 } 2093 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2094 HP_V3000_SUBVENDOR) { 2095 switch (nid) { 2096 case 18: 2097 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2098 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2099 break; 2100 case 20: 2101 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2102 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2103 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2104 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2105 break; 2106 case 21: 2107 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2108 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2109 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2110 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2111 break; 2112 default: 2113 break; 2114 } 2115 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2116 HP_DV5000_SUBVENDOR) { 2117 switch (nid) { 2118 case 20: 2119 case 21: 2120 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2121 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2122 break; 2123 default: 2124 break; 2125 } 2126 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2127 ASUS_W6F_SUBVENDOR) { 2128 switch (nid) { 2129 case 11: 2130 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2131 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2132 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2133 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2134 break; 2135 case 15: 2136 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2137 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2138 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2139 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2140 break; 2141 default: 2142 break; 2143 } 2144 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2145 UNIWILL_9075_SUBVENDOR) { 2146 switch (nid) { 2147 case 15: 2148 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2149 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2150 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2151 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2152 break; 2153 default: 2154 break; 2155 } 2156 } else if (id == HDA_CODEC_AD1986A && 2157 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2158 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2159 switch (nid) { 2160 case 28: /* LINE */ 2161 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2162 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2163 break; 2164 case 29: /* MIC */ 2165 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2166 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2167 break; 2168 default: 2169 break; 2170 } 2171 } else if (id == HDA_CODEC_ALC268 && 2172 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2173 switch (nid) { 2174 case 28: 2175 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2176 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2177 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2178 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2179 break; 2180 default: 2181 break; 2182 } 2183 } 2184 2185 HDA_BOOTVERBOSE( 2186 if (config != orig) 2187 device_printf(sc->dev, 2188 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2189 nid, orig, config); 2190 ); 2191 2192 return (config); 2193} 2194 2195static uint32_t 2196hdac_widget_pin_getcaps(struct hdac_widget *w) 2197{ 2198 struct hdac_softc *sc; 2199 uint32_t caps, orig, id; 2200 nid_t cad, nid; 2201 2202 sc = w->devinfo->codec->sc; 2203 cad = w->devinfo->codec->cad; 2204 nid = w->nid; 2205 id = hdac_codec_id(w->devinfo); 2206 2207 caps = hdac_command(sc, 2208 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2209 orig = caps; 2210 2211 HDA_BOOTVERBOSE( 2212 if (caps != orig) 2213 device_printf(sc->dev, 2214 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2215 nid, orig, caps); 2216 ); 2217 2218 return (caps); 2219} 2220 2221static void 2222hdac_widget_pin_parse(struct hdac_widget *w) 2223{ 2224 struct hdac_softc *sc = w->devinfo->codec->sc; 2225 uint32_t config, pincap; 2226 char *devstr, *connstr; 2227 nid_t cad = w->devinfo->codec->cad; 2228 nid_t nid = w->nid; 2229 2230 config = hdac_widget_pin_getconfig(w); 2231 w->wclass.pin.config = config; 2232 2233 pincap = hdac_widget_pin_getcaps(w); 2234 w->wclass.pin.cap = pincap; 2235 2236 w->wclass.pin.ctrl = hdac_command(sc, 2237 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2238 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2239 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2240 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2241 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2242 2243 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2244 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2245 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2246 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2247 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2248 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2249 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2250 w->param.eapdbtl = hdac_command(sc, 2251 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2252 w->param.eapdbtl &= 0x7; 2253 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2254 } else 2255 w->param.eapdbtl = HDAC_INVALID; 2256 2257 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2258 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2259 devstr = "line out"; 2260 break; 2261 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2262 devstr = "speaker"; 2263 break; 2264 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2265 devstr = "headphones out"; 2266 break; 2267 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2268 devstr = "CD"; 2269 break; 2270 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2271 devstr = "SPDIF out"; 2272 break; 2273 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2274 devstr = "digital (other) out"; 2275 break; 2276 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2277 devstr = "modem, line side"; 2278 break; 2279 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2280 devstr = "modem, handset side"; 2281 break; 2282 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2283 devstr = "line in"; 2284 break; 2285 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2286 devstr = "AUX"; 2287 break; 2288 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2289 devstr = "Mic in"; 2290 break; 2291 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2292 devstr = "telephony"; 2293 break; 2294 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2295 devstr = "SPDIF in"; 2296 break; 2297 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2298 devstr = "digital (other) in"; 2299 break; 2300 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2301 devstr = "other"; 2302 break; 2303 default: 2304 devstr = "unknown"; 2305 break; 2306 } 2307 2308 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2309 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2310 connstr = "jack"; 2311 break; 2312 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2313 connstr = "none"; 2314 break; 2315 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2316 connstr = "fixed"; 2317 break; 2318 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2319 connstr = "jack / fixed"; 2320 break; 2321 default: 2322 connstr = "unknown"; 2323 break; 2324 } 2325 2326 strlcat(w->name, ": ", sizeof(w->name)); 2327 strlcat(w->name, devstr, sizeof(w->name)); 2328 strlcat(w->name, " (", sizeof(w->name)); 2329 strlcat(w->name, connstr, sizeof(w->name)); 2330 strlcat(w->name, ")", sizeof(w->name)); 2331} 2332 2333static void 2334hdac_widget_parse(struct hdac_widget *w) 2335{ 2336 struct hdac_softc *sc = w->devinfo->codec->sc; 2337 uint32_t wcap, cap; 2338 char *typestr; 2339 nid_t cad = w->devinfo->codec->cad; 2340 nid_t nid = w->nid; 2341 2342 wcap = hdac_command(sc, 2343 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2344 cad); 2345 w->param.widget_cap = wcap; 2346 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2347 2348 switch (w->type) { 2349 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2350 typestr = "audio output"; 2351 break; 2352 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2353 typestr = "audio input"; 2354 break; 2355 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2356 typestr = "audio mixer"; 2357 break; 2358 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2359 typestr = "audio selector"; 2360 break; 2361 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2362 typestr = "pin"; 2363 break; 2364 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2365 typestr = "power widget"; 2366 break; 2367 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2368 typestr = "volume widget"; 2369 break; 2370 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2371 typestr = "beep widget"; 2372 break; 2373 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2374 typestr = "vendor widget"; 2375 break; 2376 default: 2377 typestr = "unknown type"; 2378 break; 2379 } 2380 2381 strlcpy(w->name, typestr, sizeof(w->name)); 2382 2383 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2384 hdac_command(sc, 2385 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2386 cad); 2387 DELAY(1000); 2388 } 2389 2390 hdac_widget_connection_parse(w); 2391 2392 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2393 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2394 w->param.outamp_cap = 2395 hdac_command(sc, 2396 HDA_CMD_GET_PARAMETER(cad, nid, 2397 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2398 else 2399 w->param.outamp_cap = 2400 w->devinfo->function.audio.outamp_cap; 2401 } else 2402 w->param.outamp_cap = 0; 2403 2404 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2405 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2406 w->param.inamp_cap = 2407 hdac_command(sc, 2408 HDA_CMD_GET_PARAMETER(cad, nid, 2409 HDA_PARAM_INPUT_AMP_CAP), cad); 2410 else 2411 w->param.inamp_cap = 2412 w->devinfo->function.audio.inamp_cap; 2413 } else 2414 w->param.inamp_cap = 0; 2415 2416 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2417 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2418 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2419 cap = hdac_command(sc, 2420 HDA_CMD_GET_PARAMETER(cad, nid, 2421 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2422 w->param.supp_stream_formats = (cap != 0) ? cap : 2423 w->devinfo->function.audio.supp_stream_formats; 2424 cap = hdac_command(sc, 2425 HDA_CMD_GET_PARAMETER(cad, nid, 2426 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2427 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2428 w->devinfo->function.audio.supp_pcm_size_rate; 2429 } else { 2430 w->param.supp_stream_formats = 2431 w->devinfo->function.audio.supp_stream_formats; 2432 w->param.supp_pcm_size_rate = 2433 w->devinfo->function.audio.supp_pcm_size_rate; 2434 } 2435 } else { 2436 w->param.supp_stream_formats = 0; 2437 w->param.supp_pcm_size_rate = 0; 2438 } 2439 2440 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2441 hdac_widget_pin_parse(w); 2442} 2443 2444static struct hdac_widget * 2445hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2446{ 2447 if (devinfo == NULL || devinfo->widget == NULL || 2448 nid < devinfo->startnode || nid >= devinfo->endnode) 2449 return (NULL); 2450 return (&devinfo->widget[nid - devinfo->startnode]); 2451} 2452 2453static __inline int 2454hda_poll_channel(struct hdac_chan *ch) 2455{ 2456 uint32_t sz, delta; 2457 volatile uint32_t ptr; 2458 2459 if (!(ch->flags & HDAC_CHN_RUNNING)) 2460 return (0); 2461 2462 sz = ch->blksz * ch->blkcnt; 2463 if (ch->dmapos != NULL) 2464 ptr = *(ch->dmapos); 2465 else 2466 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2467 ch->off + HDAC_SDLPIB); 2468 ch->ptr = ptr; 2469 ptr %= sz; 2470 ptr &= ~(ch->blksz - 1); 2471 delta = (sz + ptr - ch->prevptr) % sz; 2472 2473 if (delta < ch->blksz) 2474 return (0); 2475 2476 ch->prevptr = ptr; 2477 2478 return (1); 2479} 2480 2481#define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2482 HDAC_CHN_RUNNING) 2483 2484static void 2485hda_poll_callback(void *arg) 2486{ 2487 struct hdac_softc *sc = arg; 2488 uint32_t trigger; 2489 2490 if (sc == NULL) 2491 return; 2492 2493 hdac_lock(sc); 2494 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2495 hdac_unlock(sc); 2496 return; 2497 } 2498 2499 trigger = 0; 2500 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2501 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2502 2503 /* XXX */ 2504 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2505 hda_poll_callback, sc); 2506 2507 hdac_unlock(sc); 2508 2509 if (trigger & HDAC_TRIGGER_PLAY) 2510 chn_intr(sc->play.c); 2511 if (trigger & HDAC_TRIGGER_REC) 2512 chn_intr(sc->rec.c); 2513} 2514 2515static int 2516hdac_rirb_flush(struct hdac_softc *sc) 2517{ 2518 struct hdac_rirb *rirb_base, *rirb; 2519 struct hdac_codec *codec; 2520 struct hdac_command_list *commands; 2521 nid_t cad; 2522 uint32_t resp; 2523 uint8_t rirbwp; 2524 int ret; 2525 2526 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2527 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2528#if 0 2529 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2530 BUS_DMASYNC_POSTREAD); 2531#endif 2532 2533 ret = 0; 2534 2535 while (sc->rirb_rp != rirbwp) { 2536 sc->rirb_rp++; 2537 sc->rirb_rp %= sc->rirb_size; 2538 rirb = &rirb_base[sc->rirb_rp]; 2539 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2540 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2541 sc->codecs[cad] == NULL) 2542 continue; 2543 resp = rirb->response; 2544 codec = sc->codecs[cad]; 2545 commands = codec->commands; 2546 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2547 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2548 ((resp >> 26) & 0xffff); 2549 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2550 } else if (commands != NULL && commands->num_commands > 0 && 2551 codec->responses_received < commands->num_commands) 2552 commands->responses[codec->responses_received++] = 2553 resp; 2554 ret++; 2555 } 2556 2557 return (ret); 2558} 2559 2560static int 2561hdac_unsolq_flush(struct hdac_softc *sc) 2562{ 2563 nid_t cad; 2564 uint32_t tag; 2565 int ret = 0; 2566 2567 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2568 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2569 while (sc->unsolq_rp != sc->unsolq_wp) { 2570 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2571 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2572 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2573 hdac_unsolicited_handler(sc->codecs[cad], tag); 2574 ret++; 2575 } 2576 sc->unsolq_st = HDAC_UNSOLQ_READY; 2577 } 2578 2579 return (ret); 2580} 2581 2582static void 2583hdac_poll_callback(void *arg) 2584{ 2585 struct hdac_softc *sc = arg; 2586 if (sc == NULL) 2587 return; 2588 2589 hdac_lock(sc); 2590 if (sc->polling == 0 || sc->poll_ival == 0) { 2591 hdac_unlock(sc); 2592 return; 2593 } 2594 if (hdac_rirb_flush(sc) != 0) 2595 hdac_unsolq_flush(sc); 2596 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2597 hdac_unlock(sc); 2598} 2599 2600static void 2601hdac_stream_stop(struct hdac_chan *ch) 2602{ 2603 struct hdac_softc *sc = ch->devinfo->codec->sc; 2604 uint32_t ctl; 2605 2606 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2607 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2608 HDAC_SDCTL_RUN); 2609 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2610 2611 ch->flags &= ~HDAC_CHN_RUNNING; 2612 2613 if (sc->polling != 0) { 2614 int pollticks; 2615 2616 if (hda_chan_active(sc) == 0) { 2617 callout_stop(&sc->poll_hda); 2618 sc->poll_ticks = 1; 2619 } else { 2620 if (sc->play.flags & HDAC_CHN_RUNNING) 2621 ch = &sc->play; 2622 else 2623 ch = &sc->rec; 2624 pollticks = ((uint64_t)hz * ch->blksz) / 2625 ((uint64_t)sndbuf_getbps(ch->b) * 2626 sndbuf_getspd(ch->b)); 2627 pollticks >>= 2; 2628 if (pollticks > hz) 2629 pollticks = hz; 2630 if (pollticks < 1) { 2631 HDA_BOOTVERBOSE( 2632 device_printf(sc->dev, 2633 "%s: pollticks=%d < 1 !\n", 2634 __func__, pollticks); 2635 ); 2636 pollticks = 1; 2637 } 2638 if (pollticks > sc->poll_ticks) { 2639 HDA_BOOTVERBOSE( 2640 device_printf(sc->dev, 2641 "%s: pollticks %d -> %d\n", 2642 __func__, sc->poll_ticks, 2643 pollticks); 2644 ); 2645 sc->poll_ticks = pollticks; 2646 callout_reset(&sc->poll_hda, 1, 2647 hda_poll_callback, sc); 2648 } 2649 } 2650 } else { 2651 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2652 ctl &= ~(1 << (ch->off >> 5)); 2653 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2654 } 2655} 2656 2657static void 2658hdac_stream_start(struct hdac_chan *ch) 2659{ 2660 struct hdac_softc *sc = ch->devinfo->codec->sc; 2661 uint32_t ctl; 2662 2663 if (sc->polling != 0) { 2664 int pollticks; 2665 2666 pollticks = ((uint64_t)hz * ch->blksz) / 2667 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2668 pollticks >>= 2; 2669 if (pollticks > hz) 2670 pollticks = hz; 2671 if (pollticks < 1) { 2672 HDA_BOOTVERBOSE( 2673 device_printf(sc->dev, 2674 "%s: pollticks=%d < 1 !\n", 2675 __func__, pollticks); 2676 ); 2677 pollticks = 1; 2678 } 2679 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2680 HDA_BOOTVERBOSE( 2681 if (hda_chan_active(sc) == 0) { 2682 device_printf(sc->dev, 2683 "%s: pollticks=%d\n", 2684 __func__, pollticks); 2685 } else { 2686 device_printf(sc->dev, 2687 "%s: pollticks %d -> %d\n", 2688 __func__, sc->poll_ticks, 2689 pollticks); 2690 } 2691 ); 2692 sc->poll_ticks = pollticks; 2693 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2694 sc); 2695 } 2696 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2697 ctl |= HDAC_SDCTL_RUN; 2698 } else { 2699 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2700 ctl |= 1 << (ch->off >> 5); 2701 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2702 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2703 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2704 HDAC_SDCTL_RUN; 2705 } 2706 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2707 2708 ch->flags |= HDAC_CHN_RUNNING; 2709} 2710 2711static void 2712hdac_stream_reset(struct hdac_chan *ch) 2713{ 2714 struct hdac_softc *sc = ch->devinfo->codec->sc; 2715 int timeout = 1000; 2716 int to = timeout; 2717 uint32_t ctl; 2718 2719 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2720 ctl |= HDAC_SDCTL_SRST; 2721 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2722 do { 2723 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2724 if (ctl & HDAC_SDCTL_SRST) 2725 break; 2726 DELAY(10); 2727 } while (--to); 2728 if (!(ctl & HDAC_SDCTL_SRST)) { 2729 device_printf(sc->dev, "timeout in reset\n"); 2730 } 2731 ctl &= ~HDAC_SDCTL_SRST; 2732 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2733 to = timeout; 2734 do { 2735 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2736 if (!(ctl & HDAC_SDCTL_SRST)) 2737 break; 2738 DELAY(10); 2739 } while (--to); 2740 if (ctl & HDAC_SDCTL_SRST) 2741 device_printf(sc->dev, "can't reset!\n"); 2742} 2743 2744static void 2745hdac_stream_setid(struct hdac_chan *ch) 2746{ 2747 struct hdac_softc *sc = ch->devinfo->codec->sc; 2748 uint32_t ctl; 2749 2750 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2751 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2752 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2753 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2754} 2755 2756static void 2757hdac_bdl_setup(struct hdac_chan *ch) 2758{ 2759 struct hdac_softc *sc = ch->devinfo->codec->sc; 2760 struct hdac_bdle *bdle; 2761 uint64_t addr; 2762 uint32_t blksz, blkcnt; 2763 int i; 2764 2765 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2766 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2767 2768 if (sc->polling != 0) { 2769 blksz = ch->blksz * ch->blkcnt; 2770 blkcnt = 1; 2771 } else { 2772 blksz = ch->blksz; 2773 blkcnt = ch->blkcnt; 2774 } 2775 2776 for (i = 0; i < blkcnt; i++, bdle++) { 2777 bdle->addrl = (uint32_t)addr; 2778 bdle->addrh = (uint32_t)(addr >> 32); 2779 bdle->len = blksz; 2780 bdle->ioc = 1 ^ sc->polling; 2781 addr += blksz; 2782 } 2783 2784 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2785 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2786 addr = ch->bdl_dma.dma_paddr; 2787 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2788 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2789 if (ch->dmapos != NULL && 2790 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2791 addr = sc->pos_dma.dma_paddr; 2792 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2793 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2794 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2795 } 2796} 2797 2798static int 2799hdac_bdl_alloc(struct hdac_chan *ch) 2800{ 2801 struct hdac_softc *sc = ch->devinfo->codec->sc; 2802 int rc; 2803 2804 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2805 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2806 if (rc) { 2807 device_printf(sc->dev, "can't alloc bdl\n"); 2808 return (rc); 2809 } 2810 2811 return (0); 2812} 2813 2814static void 2815hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2816 int index, int lmute, int rmute, 2817 int left, int right, int dir) 2818{ 2819 uint16_t v = 0; 2820 2821 if (sc == NULL) 2822 return; 2823 2824 if (left != right || lmute != rmute) { 2825 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2826 (lmute << 7) | left; 2827 hdac_command(sc, 2828 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2829 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2830 (rmute << 7) | right; 2831 } else 2832 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2833 (lmute << 7) | left; 2834 2835 hdac_command(sc, 2836 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2837} 2838 2839static void 2840hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2841 int left, int right) 2842{ 2843 struct hdac_softc *sc; 2844 nid_t nid, cad; 2845 int lmute, rmute; 2846 2847 if (ctl == NULL || ctl->widget == NULL || 2848 ctl->widget->devinfo == NULL || 2849 ctl->widget->devinfo->codec == NULL || 2850 ctl->widget->devinfo->codec->sc == NULL) 2851 return; 2852 2853 sc = ctl->widget->devinfo->codec->sc; 2854 cad = ctl->widget->devinfo->codec->cad; 2855 nid = ctl->widget->nid; 2856 2857 if (mute == HDA_AMP_MUTE_DEFAULT) { 2858 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2859 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2860 } else { 2861 lmute = HDA_AMP_LEFT_MUTED(mute); 2862 rmute = HDA_AMP_RIGHT_MUTED(mute); 2863 } 2864 2865 if (ctl->dir & HDA_CTL_OUT) 2866 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2867 lmute, rmute, left, right, 0); 2868 if (ctl->dir & HDA_CTL_IN) 2869 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2870 lmute, rmute, left, right, 1); 2871 ctl->left = left; 2872 ctl->right = right; 2873} 2874 2875static void 2876hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2877{ 2878 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2879 return; 2880 hdac_command(w->devinfo->codec->sc, 2881 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2882 w->nid, index), w->devinfo->codec->cad); 2883 w->selconn = index; 2884} 2885 2886 2887/**************************************************************************** 2888 * uint32_t hdac_command_sendone_internal 2889 * 2890 * Wrapper function that sends only one command to a given codec 2891 ****************************************************************************/ 2892static uint32_t 2893hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2894{ 2895 struct hdac_command_list cl; 2896 uint32_t response = HDAC_INVALID; 2897 2898 if (!hdac_lockowned(sc)) 2899 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2900 cl.num_commands = 1; 2901 cl.verbs = &verb; 2902 cl.responses = &response; 2903 2904 hdac_command_send_internal(sc, &cl, cad); 2905 2906 return (response); 2907} 2908 2909/**************************************************************************** 2910 * hdac_command_send_internal 2911 * 2912 * Send a command list to the codec via the corb. We queue as much verbs as 2913 * we can and msleep on the codec. When the interrupt get the responses 2914 * back from the rirb, it will wake us up so we can queue the remaining verbs 2915 * if any. 2916 ****************************************************************************/ 2917static void 2918hdac_command_send_internal(struct hdac_softc *sc, 2919 struct hdac_command_list *commands, nid_t cad) 2920{ 2921 struct hdac_codec *codec; 2922 int corbrp; 2923 uint32_t *corb; 2924 int timeout; 2925 int retry = 10; 2926 struct hdac_rirb *rirb_base; 2927 2928 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2929 commands->num_commands < 1) 2930 return; 2931 2932 codec = sc->codecs[cad]; 2933 codec->commands = commands; 2934 codec->responses_received = 0; 2935 codec->verbs_sent = 0; 2936 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2937 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2938 2939 do { 2940 if (codec->verbs_sent != commands->num_commands) { 2941 /* Queue as many verbs as possible */ 2942 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2943#if 0 2944 bus_dmamap_sync(sc->corb_dma.dma_tag, 2945 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2946#endif 2947 while (codec->verbs_sent != commands->num_commands && 2948 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2949 sc->corb_wp++; 2950 sc->corb_wp %= sc->corb_size; 2951 corb[sc->corb_wp] = 2952 commands->verbs[codec->verbs_sent++]; 2953 } 2954 2955 /* Send the verbs to the codecs */ 2956#if 0 2957 bus_dmamap_sync(sc->corb_dma.dma_tag, 2958 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2959#endif 2960 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2961 } 2962 2963 timeout = 1000; 2964 while (hdac_rirb_flush(sc) == 0 && --timeout) 2965 DELAY(10); 2966 } while ((codec->verbs_sent != commands->num_commands || 2967 codec->responses_received != commands->num_commands) && --retry); 2968 2969 if (retry == 0) 2970 device_printf(sc->dev, 2971 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2972 __func__, commands->num_commands, codec->verbs_sent, 2973 codec->responses_received); 2974 2975 codec->commands = NULL; 2976 codec->responses_received = 0; 2977 codec->verbs_sent = 0; 2978 2979 hdac_unsolq_flush(sc); 2980} 2981 2982 2983/**************************************************************************** 2984 * Device Methods 2985 ****************************************************************************/ 2986 2987/**************************************************************************** 2988 * int hdac_probe(device_t) 2989 * 2990 * Probe for the presence of an hdac. If none is found, check for a generic 2991 * match using the subclass of the device. 2992 ****************************************************************************/ 2993static int 2994hdac_probe(device_t dev) 2995{ 2996 int i, result; 2997 uint32_t model; 2998 uint16_t class, subclass; 2999 char desc[64]; 3000 3001 model = (uint32_t)pci_get_device(dev) << 16; 3002 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3003 class = pci_get_class(dev); 3004 subclass = pci_get_subclass(dev); 3005 3006 bzero(desc, sizeof(desc)); 3007 result = ENXIO; 3008 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3009 if (hdac_devices[i].model == model) { 3010 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3011 result = BUS_PROBE_DEFAULT; 3012 break; 3013 } 3014 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3015 class == PCIC_MULTIMEDIA && 3016 subclass == PCIS_MULTIMEDIA_HDA) { 3017 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3018 result = BUS_PROBE_GENERIC; 3019 break; 3020 } 3021 } 3022 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3023 subclass == PCIS_MULTIMEDIA_HDA) { 3024 strlcpy(desc, "Generic", sizeof(desc)); 3025 result = BUS_PROBE_GENERIC; 3026 } 3027 if (result != ENXIO) { 3028 strlcat(desc, " High Definition Audio Controller", 3029 sizeof(desc)); 3030 device_set_desc_copy(dev, desc); 3031 } 3032 3033 return (result); 3034} 3035 3036static void * 3037hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3038 struct pcm_channel *c, int dir) 3039{ 3040 struct hdac_devinfo *devinfo = data; 3041 struct hdac_softc *sc = devinfo->codec->sc; 3042 struct hdac_chan *ch; 3043 3044 hdac_lock(sc); 3045 if (dir == PCMDIR_PLAY) { 3046 ch = &sc->play; 3047 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3048 devinfo->function.audio.playcnt++; 3049 } else { 3050 ch = &sc->rec; 3051 ch->off = devinfo->function.audio.reccnt << 5; 3052 devinfo->function.audio.reccnt++; 3053 } 3054 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3055 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3056 ch->pcmrates[0] = 48000; 3057 ch->pcmrates[1] = 0; 3058 } 3059 if (sc->pos_dma.dma_vaddr != NULL) 3060 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3061 (sc->streamcnt * 8)); 3062 else 3063 ch->dmapos = NULL; 3064 ch->sid = ++sc->streamcnt; 3065 ch->dir = dir; 3066 ch->b = b; 3067 ch->c = c; 3068 ch->devinfo = devinfo; 3069 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3070 ch->blkcnt = sc->chan_blkcnt; 3071 hdac_unlock(sc); 3072 3073 if (hdac_bdl_alloc(ch) != 0) { 3074 ch->blkcnt = 0; 3075 return (NULL); 3076 } 3077 3078 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3079 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3080 sc->chan_size) != 0) 3081 return (NULL); 3082 3083 return (ch); 3084} 3085 3086static int 3087hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3088{ 3089 struct hdac_chan *ch = data; 3090 int i; 3091 3092 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3093 if (format == ch->caps.fmtlist[i]) { 3094 ch->fmt = format; 3095 return (0); 3096 } 3097 } 3098 3099 return (EINVAL); 3100} 3101 3102static int 3103hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3104{ 3105 struct hdac_chan *ch = data; 3106 uint32_t spd = 0, threshold; 3107 int i; 3108 3109 for (i = 0; ch->pcmrates[i] != 0; i++) { 3110 spd = ch->pcmrates[i]; 3111 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3112 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3113 if (speed < threshold) 3114 break; 3115 } 3116 3117 if (spd == 0) /* impossible */ 3118 ch->spd = 48000; 3119 else 3120 ch->spd = spd; 3121 3122 return (ch->spd); 3123} 3124 3125static void 3126hdac_stream_setup(struct hdac_chan *ch) 3127{ 3128 struct hdac_softc *sc = ch->devinfo->codec->sc; 3129 struct hdac_widget *w; 3130 int i, chn, totalchn; 3131 nid_t cad = ch->devinfo->codec->cad; 3132 uint16_t fmt; 3133 3134 fmt = 0; 3135 if (ch->fmt & AFMT_S16_LE) 3136 fmt |= ch->bit16 << 4; 3137 else if (ch->fmt & AFMT_S32_LE) 3138 fmt |= ch->bit32 << 4; 3139 else 3140 fmt |= 1 << 4; 3141 3142 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3143 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3144 fmt |= hda_rate_tab[i].base; 3145 fmt |= hda_rate_tab[i].mul; 3146 fmt |= hda_rate_tab[i].div; 3147 break; 3148 } 3149 } 3150 3151 if (ch->fmt & AFMT_STEREO) { 3152 fmt |= 1; 3153 totalchn = 2; 3154 } else 3155 totalchn = 1; 3156 3157 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3158 3159 chn = 0; 3160 for (i = 0; ch->io[i] != -1; i++) { 3161 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3162 if (w == NULL) 3163 continue; 3164 HDA_BOOTVERBOSE( 3165 device_printf(sc->dev, 3166 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3167 "fmt=0x%08x\n", 3168 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3169 ch->io[i], fmt); 3170 ); 3171 hdac_command(sc, 3172 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3173 if (ch->dir == PCMDIR_REC) 3174 hdac_command(sc, 3175 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3176 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), 3177 cad); 3178 else 3179 hdac_command(sc, 3180 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3181 ch->sid << 4), cad); 3182 chn += 3183 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3184 2 : 1; 3185 } 3186} 3187 3188static int 3189hdac_channel_setfragments(kobj_t obj, void *data, 3190 uint32_t blksz, uint32_t blkcnt) 3191{ 3192 struct hdac_chan *ch = data; 3193 struct hdac_softc *sc = ch->devinfo->codec->sc; 3194 3195 blksz &= HDA_BLK_ALIGN; 3196 3197 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3198 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3199 if (blksz < HDA_BLK_MIN) 3200 blksz = HDA_BLK_MIN; 3201 if (blkcnt > HDA_BDL_MAX) 3202 blkcnt = HDA_BDL_MAX; 3203 if (blkcnt < HDA_BDL_MIN) 3204 blkcnt = HDA_BDL_MIN; 3205 3206 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3207 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3208 blkcnt >>= 1; 3209 else if ((blksz >> 1) >= HDA_BLK_MIN) 3210 blksz >>= 1; 3211 else 3212 break; 3213 } 3214 3215 if ((sndbuf_getblksz(ch->b) != blksz || 3216 sndbuf_getblkcnt(ch->b) != blkcnt) && 3217 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3218 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3219 __func__, blksz, blkcnt); 3220 3221 ch->blksz = sndbuf_getblksz(ch->b); 3222 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3223 3224 return (1); 3225} 3226 3227static int 3228hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3229{ 3230 struct hdac_chan *ch = data; 3231 struct hdac_softc *sc = ch->devinfo->codec->sc; 3232 3233 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3234 3235 return (ch->blksz); 3236} 3237 3238static void 3239hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3240{ 3241 struct hdac_devinfo *devinfo = ch->devinfo; 3242 nid_t cad = devinfo->codec->cad; 3243 int i; 3244 3245 hdac_stream_stop(ch); 3246 3247 for (i = 0; ch->io[i] != -1; i++) { 3248 hdac_command(sc, 3249 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3250 0), cad); 3251 } 3252} 3253 3254static void 3255hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3256{ 3257 ch->ptr = 0; 3258 ch->prevptr = 0; 3259 hdac_stream_stop(ch); 3260 hdac_stream_reset(ch); 3261 hdac_bdl_setup(ch); 3262 hdac_stream_setid(ch); 3263 hdac_stream_setup(ch); 3264 hdac_stream_start(ch); 3265} 3266 3267static int 3268hdac_channel_trigger(kobj_t obj, void *data, int go) 3269{ 3270 struct hdac_chan *ch = data; 3271 struct hdac_softc *sc = ch->devinfo->codec->sc; 3272 3273 if (!PCMTRIG_COMMON(go)) 3274 return (0); 3275 3276 hdac_lock(sc); 3277 switch (go) { 3278 case PCMTRIG_START: 3279 hdac_channel_start(sc, ch); 3280 break; 3281 case PCMTRIG_STOP: 3282 case PCMTRIG_ABORT: 3283 hdac_channel_stop(sc, ch); 3284 break; 3285 default: 3286 break; 3287 } 3288 hdac_unlock(sc); 3289 3290 return (0); 3291} 3292 3293static int 3294hdac_channel_getptr(kobj_t obj, void *data) 3295{ 3296 struct hdac_chan *ch = data; 3297 struct hdac_softc *sc = ch->devinfo->codec->sc; 3298 uint32_t ptr; 3299 3300 hdac_lock(sc); 3301 if (sc->polling != 0) 3302 ptr = ch->ptr; 3303 else if (ch->dmapos != NULL) 3304 ptr = *(ch->dmapos); 3305 else 3306 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3307 hdac_unlock(sc); 3308 3309 /* 3310 * Round to available space and force 128 bytes aligment. 3311 */ 3312 ptr %= ch->blksz * ch->blkcnt; 3313 ptr &= HDA_BLK_ALIGN; 3314 3315 return (ptr); 3316} 3317 3318static struct pcmchan_caps * 3319hdac_channel_getcaps(kobj_t obj, void *data) 3320{ 3321 return (&((struct hdac_chan *)data)->caps); 3322} 3323 3324static kobj_method_t hdac_channel_methods[] = { 3325 KOBJMETHOD(channel_init, hdac_channel_init), 3326 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3327 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3328 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3329 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3330 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3331 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3332 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3333 { 0, 0 } 3334}; 3335CHANNEL_DECLARE(hdac_channel); 3336 3337static void 3338hdac_jack_poll_callback(void *arg) 3339{ 3340 struct hdac_devinfo *devinfo = arg; 3341 struct hdac_softc *sc; 3342 3343 if (devinfo == NULL || devinfo->codec == NULL || 3344 devinfo->codec->sc == NULL) 3345 return; 3346 sc = devinfo->codec->sc; 3347 hdac_lock(sc); 3348 if (sc->poll_ival == 0) { 3349 hdac_unlock(sc); 3350 return; 3351 } 3352 hdac_hp_switch_handler(devinfo); 3353 callout_reset(&sc->poll_jack, sc->poll_ival, 3354 hdac_jack_poll_callback, devinfo); 3355 hdac_unlock(sc); 3356} 3357 3358static int 3359hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3360{ 3361 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3362 struct hdac_softc *sc = devinfo->codec->sc; 3363 struct hdac_widget *w, *cw; 3364 struct hdac_audio_ctl *ctl; 3365 uint32_t mask, recmask, id; 3366 int i, j, softpcmvol; 3367 nid_t cad; 3368 3369 hdac_lock(sc); 3370 3371 mask = 0; 3372 recmask = 0; 3373 3374 id = hdac_codec_id(devinfo); 3375 cad = devinfo->codec->cad; 3376 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3377 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3378 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3379 continue; 3380 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3381 if (w == NULL || w->enable == 0 || w->type != 3382 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3383 continue; 3384 if (hdac_hp_switch[i].polling != 0) 3385 callout_reset(&sc->poll_jack, 1, 3386 hdac_jack_poll_callback, devinfo); 3387 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3388 hdac_command(sc, 3389 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3390 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3391 HDAC_UNSOLTAG_EVENT_HP), cad); 3392 else 3393 continue; 3394 hdac_hp_switch_handler(devinfo); 3395 HDA_BOOTVERBOSE( 3396 device_printf(sc->dev, 3397 "HDA_DEBUG: Enabling headphone/speaker " 3398 "audio routing switching:\n"); 3399 device_printf(sc->dev, 3400 "HDA_DEBUG: \tindex=%d nid=%d " 3401 "pci_subvendor=0x%08x " 3402 "codec=0x%08x [%s]\n", 3403 i, w->nid, sc->pci_subvendor, id, 3404 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3405 "UNSOL"); 3406 ); 3407 break; 3408 } 3409 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3410 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3411 sc->pci_subvendor) && 3412 hdac_eapd_switch[i].id == id)) 3413 continue; 3414 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3415 if (w == NULL || w->enable == 0) 3416 break; 3417 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3418 w->param.eapdbtl == HDAC_INVALID) 3419 break; 3420 mask |= SOUND_MASK_OGAIN; 3421 break; 3422 } 3423 3424 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3425 w = hdac_widget_get(devinfo, i); 3426 if (w == NULL || w->enable == 0) 3427 continue; 3428 mask |= w->ctlflags; 3429 if (!(w->pflags & HDA_ADC_RECSEL)) 3430 continue; 3431 for (j = 0; j < w->nconns; j++) { 3432 cw = hdac_widget_get(devinfo, w->conns[j]); 3433 if (cw == NULL || cw->enable == 0) 3434 continue; 3435 recmask |= cw->ctlflags; 3436 } 3437 } 3438 3439 if (!(mask & SOUND_MASK_PCM)) { 3440 softpcmvol = 1; 3441 mask |= SOUND_MASK_PCM; 3442 } else 3443 softpcmvol = (devinfo->function.audio.quirks & 3444 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3445 3446 i = 0; 3447 ctl = NULL; 3448 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3449 if (ctl->widget == NULL || ctl->enable == 0) 3450 continue; 3451 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3452 continue; 3453 if (ctl->step > 0) 3454 break; 3455 } 3456 3457 if (softpcmvol == 1 || ctl == NULL) { 3458 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3459 HDA_BOOTVERBOSE( 3460 device_printf(sc->dev, 3461 "HDA_DEBUG: %s Soft PCM volume\n", 3462 (softpcmvol == 1) ? 3463 "Forcing" : "Enabling"); 3464 ); 3465 i = 0; 3466 /* 3467 * XXX Temporary quirk for STAC9220, until the parser 3468 * become smarter. 3469 */ 3470 if (id == HDA_CODEC_STAC9220) { 3471 mask |= SOUND_MASK_VOLUME; 3472 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3473 NULL) { 3474 if (ctl->widget == NULL || ctl->enable == 0) 3475 continue; 3476 if (ctl->widget->nid == 11 && ctl->index == 0) { 3477 ctl->ossmask = SOUND_MASK_VOLUME; 3478 ctl->ossval = 100 | (100 << 8); 3479 } else 3480 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3481 } 3482 } else if (id == HDA_CODEC_STAC9221) { 3483 mask |= SOUND_MASK_VOLUME; 3484 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3485 NULL) { 3486 if (ctl->widget == NULL) 3487 continue; 3488 if (ctl->widget->type == 3489 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3490 ctl->index == 0 && (ctl->widget->nid == 2 || 3491 ctl->widget->enable != 0)) { 3492 ctl->enable = 1; 3493 ctl->ossmask = SOUND_MASK_VOLUME; 3494 ctl->ossval = 100 | (100 << 8); 3495 } else if (ctl->enable == 0) 3496 continue; 3497 else 3498 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3499 } 3500 } else { 3501 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3502 SOUND_MASK_PCM); 3503 if (!(mask & SOUND_MASK_VOLUME)) 3504 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3505 SOUND_MIXER_NONE); 3506 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3507 NULL) { 3508 if (ctl->widget == NULL || ctl->enable == 0) 3509 continue; 3510 if (!HDA_FLAG_MATCH(ctl->ossmask, 3511 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3512 continue; 3513 if (!(ctl->mute == 1 && ctl->step == 0)) 3514 ctl->enable = 0; 3515 } 3516 } 3517 } 3518 3519 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3520 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3521 SOUND_MASK_OGAIN); 3522 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3523 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3524 3525 mix_setrecdevs(m, recmask); 3526 mix_setdevs(m, mask); 3527 3528 hdac_unlock(sc); 3529 3530 return (0); 3531} 3532 3533static int 3534hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3535 unsigned left, unsigned right) 3536{ 3537 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3538 struct hdac_softc *sc = devinfo->codec->sc; 3539 struct hdac_widget *w; 3540 struct hdac_audio_ctl *ctl; 3541 uint32_t id, mute; 3542 int lvol, rvol, mlvol, mrvol; 3543 int i = 0; 3544 3545 hdac_lock(sc); 3546 if (dev == SOUND_MIXER_OGAIN) { 3547 uint32_t orig; 3548 /*if (left != right || !(left == 0 || left == 1)) { 3549 hdac_unlock(sc); 3550 return (-1); 3551 }*/ 3552 id = hdac_codec_id(devinfo); 3553 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3554 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3555 sc->pci_subvendor) && 3556 hdac_eapd_switch[i].id == id) 3557 break; 3558 } 3559 if (i >= HDAC_EAPD_SWITCH_LEN) { 3560 hdac_unlock(sc); 3561 return (-1); 3562 } 3563 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3564 if (w == NULL || 3565 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3566 w->param.eapdbtl == HDAC_INVALID) { 3567 hdac_unlock(sc); 3568 return (-1); 3569 } 3570 orig = w->param.eapdbtl; 3571 if (left == 0) 3572 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3573 else 3574 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3575 if (orig != w->param.eapdbtl) { 3576 uint32_t val; 3577 3578 if (hdac_eapd_switch[i].hp_switch != 0) 3579 hdac_hp_switch_handler(devinfo); 3580 val = w->param.eapdbtl; 3581 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3582 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3583 hdac_command(sc, 3584 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3585 w->nid, val), devinfo->codec->cad); 3586 } 3587 hdac_unlock(sc); 3588 return (left | (left << 8)); 3589 } 3590 if (dev == SOUND_MIXER_VOLUME) 3591 devinfo->function.audio.mvol = left | (right << 8); 3592 3593 mlvol = devinfo->function.audio.mvol & 0x7f; 3594 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3595 lvol = 0; 3596 rvol = 0; 3597 3598 i = 0; 3599 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3600 if (ctl->widget == NULL || ctl->enable == 0 || 3601 !(ctl->ossmask & (1 << dev))) 3602 continue; 3603 switch (dev) { 3604 case SOUND_MIXER_VOLUME: 3605 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3606 lvol = (lvol * ctl->step) / 100; 3607 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3608 rvol = (rvol * ctl->step) / 100; 3609 break; 3610 default: 3611 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3612 lvol = (left * mlvol) / 100; 3613 lvol = (lvol * ctl->step) / 100; 3614 rvol = (right * mrvol) / 100; 3615 rvol = (rvol * ctl->step) / 100; 3616 } else { 3617 lvol = (left * ctl->step) / 100; 3618 rvol = (right * ctl->step) / 100; 3619 } 3620 ctl->ossval = left | (right << 8); 3621 break; 3622 } 3623 mute = 0; 3624 if (ctl->step < 1) { 3625 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3626 (ctl->muted & HDA_AMP_MUTE_LEFT); 3627 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3628 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3629 } else { 3630 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3631 (ctl->muted & HDA_AMP_MUTE_LEFT); 3632 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3633 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3634 } 3635 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3636 } 3637 hdac_unlock(sc); 3638 3639 return (left | (right << 8)); 3640} 3641 3642static int 3643hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3644{ 3645 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3646 struct hdac_widget *w, *cw; 3647 struct hdac_softc *sc = devinfo->codec->sc; 3648 uint32_t ret = src, target; 3649 int i, j; 3650 3651 target = 0; 3652 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3653 if (src & (1 << i)) { 3654 target = 1 << i; 3655 break; 3656 } 3657 } 3658 3659 hdac_lock(sc); 3660 3661 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3662 w = hdac_widget_get(devinfo, i); 3663 if (w == NULL || w->enable == 0) 3664 continue; 3665 if (!(w->pflags & HDA_ADC_RECSEL)) 3666 continue; 3667 for (j = 0; j < w->nconns; j++) { 3668 cw = hdac_widget_get(devinfo, w->conns[j]); 3669 if (cw == NULL || cw->enable == 0) 3670 continue; 3671 if ((target == SOUND_MASK_VOLUME && 3672 cw->type != 3673 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3674 (target != SOUND_MASK_VOLUME && 3675 cw->type == 3676 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3677 continue; 3678 if (cw->ctlflags & target) { 3679 if (!(w->pflags & HDA_ADC_LOCKED)) 3680 hdac_widget_connection_select(w, j); 3681 ret = target; 3682 j += w->nconns; 3683 } 3684 } 3685 } 3686 3687 hdac_unlock(sc); 3688 3689 return (ret); 3690} 3691 3692static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3693 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3694 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3695 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3696 { 0, 0 } 3697}; 3698MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3699 3700static void 3701hdac_unsolq_task(void *context, int pending) 3702{ 3703 struct hdac_softc *sc; 3704 3705 sc = (struct hdac_softc *)context; 3706 3707 hdac_lock(sc); 3708 hdac_unsolq_flush(sc); 3709 hdac_unlock(sc); 3710} 3711 3712/**************************************************************************** 3713 * int hdac_attach(device_t) 3714 * 3715 * Attach the device into the kernel. Interrupts usually won't be enabled 3716 * when this function is called. Setup everything that doesn't require 3717 * interrupts and defer probing of codecs until interrupts are enabled. 3718 ****************************************************************************/ 3719static int 3720hdac_attach(device_t dev) 3721{ 3722 struct hdac_softc *sc; 3723 int result; 3724 int i; 3725 uint16_t vendor; 3726 uint8_t v; 3727 3728 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3729 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3730 sc->dev = dev; 3731 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3732 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3733 vendor = pci_get_vendor(dev); 3734 3735 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3736 /* Screw nx6325 - subdevice/subvendor swapped */ 3737 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3738 } 3739 3740 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3741 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3742 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3743 3744 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3745 3746 sc->poll_ticks = 1; 3747 sc->poll_ival = HDAC_POLL_INTERVAL; 3748 if (resource_int_value(device_get_name(dev), 3749 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3750 sc->polling = 1; 3751 else 3752 sc->polling = 0; 3753 3754 sc->chan_size = pcm_getbuffersize(dev, 3755 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3756 3757 if (resource_int_value(device_get_name(dev), 3758 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3759 i &= HDA_BLK_ALIGN; 3760 if (i < HDA_BLK_MIN) 3761 i = HDA_BLK_MIN; 3762 sc->chan_blkcnt = sc->chan_size / i; 3763 i = 0; 3764 while (sc->chan_blkcnt >> i) 3765 i++; 3766 sc->chan_blkcnt = 1 << (i - 1); 3767 if (sc->chan_blkcnt < HDA_BDL_MIN) 3768 sc->chan_blkcnt = HDA_BDL_MIN; 3769 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3770 sc->chan_blkcnt = HDA_BDL_MAX; 3771 } else 3772 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3773 3774 result = bus_dma_tag_create(NULL, /* parent */ 3775 HDAC_DMA_ALIGNMENT, /* alignment */ 3776 0, /* boundary */ 3777 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3778 BUS_SPACE_MAXADDR, /* highaddr */ 3779 NULL, /* filtfunc */ 3780 NULL, /* fistfuncarg */ 3781 sc->chan_size, /* maxsize */ 3782 1, /* nsegments */ 3783 sc->chan_size, /* maxsegsz */ 3784 0, /* flags */ 3785 NULL, /* lockfunc */ 3786 NULL, /* lockfuncarg */ 3787 &sc->chan_dmat); /* dmat */ 3788 if (result != 0) { 3789 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3790 __func__, result); 3791 snd_mtxfree(sc->lock); 3792 free(sc, M_DEVBUF); 3793 return (ENXIO); 3794 } 3795 3796 3797 sc->hdabus = NULL; 3798 for (i = 0; i < HDAC_CODEC_MAX; i++) 3799 sc->codecs[i] = NULL; 3800 3801 pci_enable_busmaster(dev); 3802 3803 if (vendor == INTEL_VENDORID) { 3804 /* TCSEL -> TC0 */ 3805 v = pci_read_config(dev, 0x44, 1); 3806 pci_write_config(dev, 0x44, v & 0xf8, 1); 3807 HDA_BOOTVERBOSE( 3808 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3809 pci_read_config(dev, 0x44, 1)); 3810 ); 3811 } 3812 3813#if __FreeBSD_version >= 602106 3814 if (resource_int_value(device_get_name(dev), 3815 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3816 pci_msi_count(dev) == 1) 3817 sc->flags |= HDAC_F_MSI; 3818 else 3819#endif 3820 sc->flags &= ~HDAC_F_MSI; 3821 3822#if defined(__i386__) || defined(__amd64__) 3823 sc->flags |= HDAC_F_DMA_NOCACHE; 3824 3825 if (resource_int_value(device_get_name(dev), 3826 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3827#else 3828 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3829#endif 3830 /* 3831 * Try to enable PCIe snoop to avoid messing around with 3832 * uncacheable DMA attribute. Since PCIe snoop register 3833 * config is pretty much vendor specific, there are no 3834 * general solutions on how to enable it, forcing us (even 3835 * Microsoft) to enable uncacheable or write combined DMA 3836 * by default. 3837 * 3838 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3839 */ 3840 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3841 if (hdac_pcie_snoop[i].vendor != vendor) 3842 continue; 3843 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3844 if (hdac_pcie_snoop[i].reg == 0x00) 3845 break; 3846 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3847 if ((v & hdac_pcie_snoop[i].enable) == 3848 hdac_pcie_snoop[i].enable) 3849 break; 3850 v &= hdac_pcie_snoop[i].mask; 3851 v |= hdac_pcie_snoop[i].enable; 3852 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3853 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3854 if ((v & hdac_pcie_snoop[i].enable) != 3855 hdac_pcie_snoop[i].enable) { 3856 HDA_BOOTVERBOSE( 3857 device_printf(dev, 3858 "WARNING: Failed to enable PCIe " 3859 "snoop!\n"); 3860 ); 3861#if defined(__i386__) || defined(__amd64__) 3862 sc->flags |= HDAC_F_DMA_NOCACHE; 3863#endif 3864 } 3865 break; 3866 } 3867#if defined(__i386__) || defined(__amd64__) 3868 } 3869#endif 3870 3871 HDA_BOOTVERBOSE( 3872 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3873 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3874 "Uncacheable" : "PCIe snoop", vendor); 3875 ); 3876 3877 /* Allocate resources */ 3878 result = hdac_mem_alloc(sc); 3879 if (result != 0) 3880 goto hdac_attach_fail; 3881 result = hdac_irq_alloc(sc); 3882 if (result != 0) 3883 goto hdac_attach_fail; 3884 3885 /* Get Capabilities */ 3886 result = hdac_get_capabilities(sc); 3887 if (result != 0) 3888 goto hdac_attach_fail; 3889 3890 /* Allocate CORB and RIRB dma memory */ 3891 result = hdac_dma_alloc(sc, &sc->corb_dma, 3892 sc->corb_size * sizeof(uint32_t)); 3893 if (result != 0) 3894 goto hdac_attach_fail; 3895 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3896 sc->rirb_size * sizeof(struct hdac_rirb)); 3897 if (result != 0) 3898 goto hdac_attach_fail; 3899 3900 /* Quiesce everything */ 3901 hdac_reset(sc); 3902 3903 /* Initialize the CORB and RIRB */ 3904 hdac_corb_init(sc); 3905 hdac_rirb_init(sc); 3906 3907 /* Defer remaining of initialization until interrupts are enabled */ 3908 sc->intrhook.ich_func = hdac_attach2; 3909 sc->intrhook.ich_arg = (void *)sc; 3910 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3911 sc->intrhook.ich_func = NULL; 3912 hdac_attach2((void *)sc); 3913 } 3914 3915 return (0); 3916 3917hdac_attach_fail: 3918 hdac_irq_free(sc); 3919 hdac_dma_free(sc, &sc->rirb_dma); 3920 hdac_dma_free(sc, &sc->corb_dma); 3921 hdac_mem_free(sc); 3922 snd_mtxfree(sc->lock); 3923 free(sc, M_DEVBUF); 3924 3925 return (ENXIO); 3926} 3927 3928static void 3929hdac_audio_parse(struct hdac_devinfo *devinfo) 3930{ 3931 struct hdac_softc *sc = devinfo->codec->sc; 3932 struct hdac_widget *w; 3933 uint32_t res; 3934 int i; 3935 nid_t cad, nid; 3936 3937 cad = devinfo->codec->cad; 3938 nid = devinfo->nid; 3939 3940 hdac_command(sc, 3941 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3942 3943 DELAY(100); 3944 3945 res = hdac_command(sc, 3946 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3947 3948 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3949 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3950 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3951 3952 res = hdac_command(sc, 3953 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3954 devinfo->function.audio.gpio = res; 3955 3956 HDA_BOOTVERBOSE( 3957 device_printf(sc->dev, " Vendor: 0x%08x\n", 3958 devinfo->vendor_id); 3959 device_printf(sc->dev, " Device: 0x%08x\n", 3960 devinfo->device_id); 3961 device_printf(sc->dev, " Revision: 0x%08x\n", 3962 devinfo->revision_id); 3963 device_printf(sc->dev, " Stepping: 0x%08x\n", 3964 devinfo->stepping_id); 3965 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3966 sc->pci_subvendor); 3967 device_printf(sc->dev, " Nodes: start=%d " 3968 "endnode=%d total=%d\n", 3969 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3970 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3971 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3972 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3973 sc->num_iss, sc->num_oss, sc->num_bss); 3974 device_printf(sc->dev, " GPIO: 0x%08x\n", 3975 devinfo->function.audio.gpio); 3976 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3977 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3978 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3979 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3980 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3981 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3982 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3983 ); 3984 3985 res = hdac_command(sc, 3986 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3987 cad); 3988 devinfo->function.audio.supp_stream_formats = res; 3989 3990 res = hdac_command(sc, 3991 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3992 cad); 3993 devinfo->function.audio.supp_pcm_size_rate = res; 3994 3995 res = hdac_command(sc, 3996 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3997 cad); 3998 devinfo->function.audio.outamp_cap = res; 3999 4000 res = hdac_command(sc, 4001 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4002 cad); 4003 devinfo->function.audio.inamp_cap = res; 4004 4005 if (devinfo->nodecnt > 0) 4006 devinfo->widget = (struct hdac_widget *)malloc( 4007 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 4008 M_NOWAIT | M_ZERO); 4009 else 4010 devinfo->widget = NULL; 4011 4012 if (devinfo->widget == NULL) { 4013 device_printf(sc->dev, "unable to allocate widgets!\n"); 4014 devinfo->endnode = devinfo->startnode; 4015 devinfo->nodecnt = 0; 4016 return; 4017 } 4018 4019 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4020 w = hdac_widget_get(devinfo, i); 4021 if (w == NULL) 4022 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4023 else { 4024 w->devinfo = devinfo; 4025 w->nid = i; 4026 w->enable = 1; 4027 w->selconn = -1; 4028 w->pflags = 0; 4029 w->ctlflags = 0; 4030 w->param.eapdbtl = HDAC_INVALID; 4031 hdac_widget_parse(w); 4032 } 4033 } 4034} 4035 4036static void 4037hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4038{ 4039 struct hdac_softc *sc = devinfo->codec->sc; 4040 struct hdac_audio_ctl *ctls; 4041 struct hdac_widget *w, *cw; 4042 int i, j, cnt, max, ocap, icap; 4043 int mute, offset, step, size; 4044 4045 /* XXX This is redundant */ 4046 max = 0; 4047 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4048 w = hdac_widget_get(devinfo, i); 4049 if (w == NULL || w->enable == 0) 4050 continue; 4051 if (w->param.outamp_cap != 0) 4052 max++; 4053 if (w->param.inamp_cap != 0) { 4054 switch (w->type) { 4055 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4056 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4057 for (j = 0; j < w->nconns; j++) { 4058 cw = hdac_widget_get(devinfo, 4059 w->conns[j]); 4060 if (cw == NULL || cw->enable == 0) 4061 continue; 4062 max++; 4063 } 4064 break; 4065 default: 4066 max++; 4067 break; 4068 } 4069 } 4070 } 4071 4072 devinfo->function.audio.ctlcnt = max; 4073 4074 if (max < 1) 4075 return; 4076 4077 ctls = (struct hdac_audio_ctl *)malloc( 4078 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4079 4080 if (ctls == NULL) { 4081 /* Blekh! */ 4082 device_printf(sc->dev, "unable to allocate ctls!\n"); 4083 devinfo->function.audio.ctlcnt = 0; 4084 return; 4085 } 4086 4087 cnt = 0; 4088 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4089 if (cnt >= max) { 4090 device_printf(sc->dev, "%s: Ctl overflow!\n", 4091 __func__); 4092 break; 4093 } 4094 w = hdac_widget_get(devinfo, i); 4095 if (w == NULL || w->enable == 0) 4096 continue; 4097 ocap = w->param.outamp_cap; 4098 icap = w->param.inamp_cap; 4099 if (ocap != 0) { 4100 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4101 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4102 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4103 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4104 /*if (offset > step) { 4105 HDA_BOOTVERBOSE( 4106 device_printf(sc->dev, 4107 "HDA_DEBUG: BUGGY outamp: nid=%d " 4108 "[offset=%d > step=%d]\n", 4109 w->nid, offset, step); 4110 ); 4111 offset = step; 4112 }*/ 4113 ctls[cnt].enable = 1; 4114 ctls[cnt].widget = w; 4115 ctls[cnt].mute = mute; 4116 ctls[cnt].step = step; 4117 ctls[cnt].size = size; 4118 ctls[cnt].offset = offset; 4119 ctls[cnt].left = offset; 4120 ctls[cnt].right = offset; 4121 ctls[cnt++].dir = HDA_CTL_OUT; 4122 } 4123 4124 if (icap != 0) { 4125 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4126 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4127 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4128 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4129 /*if (offset > step) { 4130 HDA_BOOTVERBOSE( 4131 device_printf(sc->dev, 4132 "HDA_DEBUG: BUGGY inamp: nid=%d " 4133 "[offset=%d > step=%d]\n", 4134 w->nid, offset, step); 4135 ); 4136 offset = step; 4137 }*/ 4138 switch (w->type) { 4139 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4140 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4141 for (j = 0; j < w->nconns; j++) { 4142 if (cnt >= max) { 4143 device_printf(sc->dev, 4144 "%s: Ctl overflow!\n", 4145 __func__); 4146 break; 4147 } 4148 cw = hdac_widget_get(devinfo, 4149 w->conns[j]); 4150 if (cw == NULL || cw->enable == 0) 4151 continue; 4152 ctls[cnt].enable = 1; 4153 ctls[cnt].widget = w; 4154 ctls[cnt].childwidget = cw; 4155 ctls[cnt].index = j; 4156 ctls[cnt].mute = mute; 4157 ctls[cnt].step = step; 4158 ctls[cnt].size = size; 4159 ctls[cnt].offset = offset; 4160 ctls[cnt].left = offset; 4161 ctls[cnt].right = offset; 4162 ctls[cnt++].dir = HDA_CTL_IN; 4163 } 4164 break; 4165 default: 4166 if (cnt >= max) { 4167 device_printf(sc->dev, 4168 "%s: Ctl overflow!\n", 4169 __func__); 4170 break; 4171 } 4172 ctls[cnt].enable = 1; 4173 ctls[cnt].widget = w; 4174 ctls[cnt].mute = mute; 4175 ctls[cnt].step = step; 4176 ctls[cnt].size = size; 4177 ctls[cnt].offset = offset; 4178 ctls[cnt].left = offset; 4179 ctls[cnt].right = offset; 4180 ctls[cnt++].dir = HDA_CTL_IN; 4181 break; 4182 } 4183 } 4184 } 4185 4186 devinfo->function.audio.ctl = ctls; 4187} 4188 4189static const struct { 4190 uint32_t model; 4191 uint32_t id; 4192 uint32_t set, unset; 4193} hdac_quirks[] = { 4194 /* 4195 * XXX Force stereo quirk. Monoural recording / playback 4196 * on few codecs (especially ALC880) seems broken or 4197 * perhaps unsupported. 4198 */ 4199 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4200 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4201 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4202 HDA_QUIRK_GPIO0, 0 }, 4203 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4204 HDA_QUIRK_GPIO0, 0 }, 4205 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4206 HDA_QUIRK_GPIO0, 0 }, 4207 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4208 HDA_QUIRK_GPIO0, 0 }, 4209 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4210 HDA_QUIRK_GPIO0, 0 }, 4211 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4212 HDA_QUIRK_EAPDINV, 0 }, 4213 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4214 HDA_QUIRK_EAPDINV, 0 }, 4215 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4216 HDA_QUIRK_OVREF, 0 }, 4217 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4218 HDA_QUIRK_OVREF, 0 }, 4219 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4220 HDA_QUIRK_OVREF, 0 }, 4221 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4222 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4223 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4224 HDA_QUIRK_GPIO1, 0 }, 4225 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4226 HDA_QUIRK_EAPDINV, 0 }, 4227 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4228 HDA_QUIRK_EAPDINV, 0 }, 4229 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4230 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4231 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4232 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4233 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4234 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4235 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4236 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4237 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4238 0, HDA_QUIRK_FORCESTEREO }, 4239 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4240 HDA_QUIRK_SOFTPCMVOL, 0 } 4241}; 4242#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4243 4244static void 4245hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4246{ 4247 struct hdac_widget *w; 4248 struct hdac_audio_ctl *ctl; 4249 uint32_t id, subvendor; 4250 int i; 4251 4252 id = hdac_codec_id(devinfo); 4253 subvendor = devinfo->codec->sc->pci_subvendor; 4254 4255 /* 4256 * Quirks 4257 */ 4258 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4259 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4260 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4261 continue; 4262 if (hdac_quirks[i].set != 0) 4263 devinfo->function.audio.quirks |= 4264 hdac_quirks[i].set; 4265 if (hdac_quirks[i].unset != 0) 4266 devinfo->function.audio.quirks &= 4267 ~(hdac_quirks[i].unset); 4268 } 4269 4270 switch (id) { 4271 case HDA_CODEC_ALC260: 4272 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4273 w = hdac_widget_get(devinfo, i); 4274 if (w == NULL || w->enable == 0) 4275 continue; 4276 if (w->type != 4277 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4278 continue; 4279 if (w->nid != 5) 4280 w->enable = 0; 4281 } 4282 if (subvendor == HP_XW4300_SUBVENDOR) { 4283 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4284 if (ctl != NULL && ctl->widget != NULL) { 4285 ctl->ossmask = SOUND_MASK_SPEAKER; 4286 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4287 } 4288 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4289 if (ctl != NULL && ctl->widget != NULL) { 4290 ctl->ossmask = SOUND_MASK_SPEAKER; 4291 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4292 } 4293 } else if (subvendor == HP_3010_SUBVENDOR) { 4294 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4295 if (ctl != NULL && ctl->widget != NULL) { 4296 ctl->ossmask = SOUND_MASK_SPEAKER; 4297 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4298 } 4299 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4300 if (ctl != NULL && ctl->widget != NULL) { 4301 ctl->ossmask = SOUND_MASK_SPEAKER; 4302 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4303 } 4304 } 4305 break; 4306 case HDA_CODEC_ALC262: 4307 if (subvendor == HP_DC7700_SUBVENDOR) { 4308 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4309 if (ctl != NULL && ctl->widget != NULL) { 4310 ctl->ossmask = SOUND_MASK_SPEAKER; 4311 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4312 } 4313 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4314 if (ctl != NULL && ctl->widget != NULL) { 4315 ctl->ossmask = SOUND_MASK_SPEAKER; 4316 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4317 } 4318 } 4319 break; 4320 case HDA_CODEC_ALC268: 4321 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) { 4322 w = hdac_widget_get(devinfo, 29); 4323 if (w != NULL) { 4324 w->enable = 1; 4325 w->type = 4326 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4327 w->param.widget_cap &= 4328 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4329 w->param.widget_cap |= 4330 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4331 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4332 strlcpy(w->name, "beep widget", sizeof(w->name)); 4333 } 4334 } 4335 break; 4336 case HDA_CODEC_ALC861: 4337 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4338 if (ctl != NULL) 4339 ctl->muted = HDA_AMP_MUTE_ALL; 4340 break; 4341 case HDA_CODEC_ALC880: 4342 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4343 w = hdac_widget_get(devinfo, i); 4344 if (w == NULL || w->enable == 0) 4345 continue; 4346 if (w->type == 4347 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4348 w->nid != 9 && w->nid != 29) { 4349 w->enable = 0; 4350 } else if (w->type != 4351 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4352 w->nid == 29) { 4353 w->type = 4354 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4355 w->param.widget_cap &= 4356 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4357 w->param.widget_cap |= 4358 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4359 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4360 strlcpy(w->name, "beep widget", sizeof(w->name)); 4361 } 4362 } 4363 break; 4364 case HDA_CODEC_ALC883: 4365 /* 4366 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4367 * Clear vref cap for jack connectivity. 4368 */ 4369 w = hdac_widget_get(devinfo, 24); 4370 if (w != NULL && w->enable != 0 && w->type == 4371 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4372 (w->wclass.pin.config & 4373 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4374 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4375 w->wclass.pin.cap &= ~( 4376 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4377 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4378 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4379 w = hdac_widget_get(devinfo, 25); 4380 if (w != NULL && w->enable != 0 && w->type == 4381 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4382 (w->wclass.pin.config & 4383 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4384 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4385 w->wclass.pin.cap &= ~( 4386 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4387 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4388 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4389 /* 4390 * nid: 26 = Line-in, leave it alone. 4391 */ 4392 break; 4393 case HDA_CODEC_AD1981HD: 4394 w = hdac_widget_get(devinfo, 11); 4395 if (w != NULL && w->enable != 0 && w->nconns > 3) 4396 w->selconn = 3; 4397 if (subvendor == IBM_M52_SUBVENDOR) { 4398 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4399 if (ctl != NULL) 4400 ctl->ossmask = SOUND_MASK_SPEAKER; 4401 } 4402 break; 4403 case HDA_CODEC_AD1986A: 4404 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4405 w = hdac_widget_get(devinfo, i); 4406 if (w == NULL || w->enable == 0) 4407 continue; 4408 if (w->type != 4409 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4410 continue; 4411 if (w->nid != 3) 4412 w->enable = 0; 4413 } 4414 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4415 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4416 /* nid 28 is mic, nid 29 is line-in */ 4417 w = hdac_widget_get(devinfo, 15); 4418 if (w != NULL) 4419 w->selconn = 2; 4420 w = hdac_widget_get(devinfo, 16); 4421 if (w != NULL) 4422 w->selconn = 1; 4423 } 4424 break; 4425 case HDA_CODEC_AD1988: 4426 case HDA_CODEC_AD1988B: 4427 /*w = hdac_widget_get(devinfo, 12); 4428 if (w != NULL) { 4429 w->selconn = 1; 4430 w->pflags |= HDA_ADC_LOCKED; 4431 } 4432 w = hdac_widget_get(devinfo, 13); 4433 if (w != NULL) { 4434 w->selconn = 4; 4435 w->pflags |= HDA_ADC_LOCKED; 4436 } 4437 w = hdac_widget_get(devinfo, 14); 4438 if (w != NULL) { 4439 w->selconn = 2; 4440 w->pflags |= HDA_ADC_LOCKED; 4441 }*/ 4442 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4443 if (ctl != NULL) { 4444 ctl->ossmask = SOUND_MASK_IGAIN; 4445 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4446 } 4447 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4448 if (ctl != NULL) { 4449 ctl->ossmask = SOUND_MASK_IGAIN; 4450 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4451 } 4452 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4453 if (ctl != NULL) { 4454 ctl->ossmask = SOUND_MASK_IGAIN; 4455 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4456 } 4457 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4458 if (ctl != NULL) { 4459 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4460 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4461 } 4462 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4463 if (ctl != NULL) { 4464 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4465 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4466 } 4467 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4468 if (ctl != NULL) { 4469 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4470 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4471 } 4472 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4473 if (ctl != NULL) { 4474 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4475 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4476 } 4477 break; 4478 case HDA_CODEC_STAC9221: 4479 /* 4480 * Dell XPS M1210 need all DACs for each output jacks 4481 */ 4482 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4483 break; 4484 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4485 w = hdac_widget_get(devinfo, i); 4486 if (w == NULL || w->enable == 0) 4487 continue; 4488 if (w->type != 4489 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4490 continue; 4491 if (w->nid != 2) 4492 w->enable = 0; 4493 } 4494 break; 4495 case HDA_CODEC_STAC9221D: 4496 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4497 w = hdac_widget_get(devinfo, i); 4498 if (w == NULL || w->enable == 0) 4499 continue; 4500 if (w->type == 4501 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4502 w->nid != 6) 4503 w->enable = 0; 4504 4505 } 4506 break; 4507 case HDA_CODEC_STAC9227: 4508 w = hdac_widget_get(devinfo, 8); 4509 if (w != NULL) 4510 w->enable = 0; 4511 w = hdac_widget_get(devinfo, 9); 4512 if (w != NULL) 4513 w->enable = 0; 4514 break; 4515 case HDA_CODEC_CXWAIKIKI: 4516 if (subvendor == HP_DV5000_SUBVENDOR) { 4517 w = hdac_widget_get(devinfo, 27); 4518 if (w != NULL) 4519 w->enable = 0; 4520 } 4521 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4522 if (ctl != NULL) 4523 ctl->ossmask = SOUND_MASK_SKIP; 4524 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4525 if (ctl != NULL && ctl->childwidget != NULL && 4526 ctl->childwidget->enable != 0) { 4527 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4528 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4529 } 4530 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4531 if (ctl != NULL && ctl->childwidget != NULL && 4532 ctl->childwidget->enable != 0) { 4533 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4534 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4535 } 4536 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4537 if (ctl != NULL && ctl->childwidget != NULL && 4538 ctl->childwidget->enable != 0) { 4539 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4540 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4541 } 4542 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4543 if (ctl != NULL) { 4544 ctl->ossmask = SOUND_MASK_SKIP; 4545 /* XXX mixer \=rec mic broken.. why?!? */ 4546 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4547 } 4548 break; 4549 default: 4550 break; 4551 } 4552} 4553 4554static int 4555hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4556{ 4557 int *dev = &devinfo->function.audio.ossidx; 4558 4559 while (*dev < SOUND_MIXER_NRDEVICES) { 4560 switch (*dev) { 4561 case SOUND_MIXER_VOLUME: 4562 case SOUND_MIXER_BASS: 4563 case SOUND_MIXER_TREBLE: 4564 case SOUND_MIXER_PCM: 4565 case SOUND_MIXER_SPEAKER: 4566 case SOUND_MIXER_LINE: 4567 case SOUND_MIXER_MIC: 4568 case SOUND_MIXER_CD: 4569 case SOUND_MIXER_RECLEV: 4570 case SOUND_MIXER_IGAIN: 4571 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4572 (*dev)++; 4573 break; 4574 default: 4575 return (*dev)++; 4576 break; 4577 } 4578 } 4579 4580 return (-1); 4581} 4582 4583static int 4584hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4585{ 4586 struct hdac_widget *w; 4587 int i, ret = 0; 4588 4589 if (depth > HDA_PARSE_MAXDEPTH) 4590 return (0); 4591 w = hdac_widget_get(devinfo, nid); 4592 if (w == NULL || w->enable == 0) 4593 return (0); 4594 switch (w->type) { 4595 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4596 w->pflags |= HDA_DAC_PATH; 4597 ret = 1; 4598 break; 4599 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4600 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4601 for (i = 0; i < w->nconns; i++) { 4602 if (hdac_widget_find_dac_path(devinfo, 4603 w->conns[i], depth + 1) != 0) { 4604 if (w->selconn == -1) 4605 w->selconn = i; 4606 ret = 1; 4607 w->pflags |= HDA_DAC_PATH; 4608 } 4609 } 4610 break; 4611 default: 4612 break; 4613 } 4614 return (ret); 4615} 4616 4617static int 4618hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4619{ 4620 struct hdac_widget *w; 4621 int i, conndev, ret = 0; 4622 4623 if (depth > HDA_PARSE_MAXDEPTH) 4624 return (0); 4625 w = hdac_widget_get(devinfo, nid); 4626 if (w == NULL || w->enable == 0) 4627 return (0); 4628 switch (w->type) { 4629 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4630 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4631 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4632 for (i = 0; i < w->nconns; i++) { 4633 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4634 depth + 1) != 0) { 4635 if (w->selconn == -1) 4636 w->selconn = i; 4637 w->pflags |= HDA_ADC_PATH; 4638 ret = 1; 4639 } 4640 } 4641 break; 4642 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4643 conndev = w->wclass.pin.config & 4644 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4645 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4646 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4647 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4648 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4649 w->pflags |= HDA_ADC_PATH; 4650 ret = 1; 4651 } 4652 break; 4653 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4654 if (w->pflags & HDA_DAC_PATH) { 4655 w->pflags |= HDA_ADC_PATH; 4656 ret = 1; 4657 } 4658 break;*/ 4659 default: 4660 break; 4661 } 4662 return (ret); 4663} 4664 4665static uint32_t 4666hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4667 nid_t nid, nid_t pnid, int index, int depth) 4668{ 4669 struct hdac_widget *w, *pw; 4670 struct hdac_audio_ctl *ctl; 4671 uint32_t fl = 0; 4672 int i, ossdev, conndev, strategy; 4673 4674 if (depth > HDA_PARSE_MAXDEPTH) 4675 return (0); 4676 4677 w = hdac_widget_get(devinfo, nid); 4678 if (w == NULL || w->enable == 0) 4679 return (0); 4680 4681 pw = hdac_widget_get(devinfo, pnid); 4682 strategy = devinfo->function.audio.parsing_strategy; 4683 4684 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4685 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4686 for (i = 0; i < w->nconns; i++) { 4687 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4688 w->nid, i, depth + 1); 4689 } 4690 w->ctlflags |= fl; 4691 return (fl); 4692 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4693 (w->pflags & HDA_DAC_PATH)) { 4694 i = 0; 4695 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4696 if (ctl->enable == 0 || ctl->widget == NULL) 4697 continue; 4698 /* XXX This should be compressed! */ 4699 if (((ctl->widget->nid == w->nid) || 4700 (ctl->widget->nid == pnid && ctl->index == index && 4701 (ctl->dir & HDA_CTL_IN)) || 4702 (ctl->widget->nid == pnid && pw != NULL && 4703 pw->type == 4704 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4705 (pw->nconns < 2 || pw->selconn == index || 4706 pw->selconn == -1) && 4707 (ctl->dir & HDA_CTL_OUT)) || 4708 (strategy == HDA_PARSE_DIRECT && 4709 ctl->widget->nid == w->nid)) && 4710 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4711 /*if (pw != NULL && pw->selconn == -1) 4712 pw->selconn = index; 4713 fl |= SOUND_MASK_VOLUME; 4714 fl |= SOUND_MASK_PCM; 4715 ctl->ossmask |= SOUND_MASK_VOLUME; 4716 ctl->ossmask |= SOUND_MASK_PCM; 4717 ctl->ossdev = SOUND_MIXER_PCM;*/ 4718 if (!(w->ctlflags & SOUND_MASK_PCM) || 4719 (pw != NULL && 4720 !(pw->ctlflags & SOUND_MASK_PCM))) { 4721 fl |= SOUND_MASK_VOLUME; 4722 fl |= SOUND_MASK_PCM; 4723 ctl->ossmask |= SOUND_MASK_VOLUME; 4724 ctl->ossmask |= SOUND_MASK_PCM; 4725 ctl->ossdev = SOUND_MIXER_PCM; 4726 w->ctlflags |= SOUND_MASK_VOLUME; 4727 w->ctlflags |= SOUND_MASK_PCM; 4728 if (pw != NULL) { 4729 if (pw->selconn == -1) 4730 pw->selconn = index; 4731 pw->ctlflags |= 4732 SOUND_MASK_VOLUME; 4733 pw->ctlflags |= 4734 SOUND_MASK_PCM; 4735 } 4736 } 4737 } 4738 } 4739 w->ctlflags |= fl; 4740 return (fl); 4741 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4742 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4743 (w->pflags & HDA_ADC_PATH)) { 4744 conndev = w->wclass.pin.config & 4745 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4746 i = 0; 4747 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4748 if (ctl->enable == 0 || ctl->widget == NULL) 4749 continue; 4750 /* XXX This should be compressed! */ 4751 if (((ctl->widget->nid == pnid && ctl->index == index && 4752 (ctl->dir & HDA_CTL_IN)) || 4753 (ctl->widget->nid == pnid && pw != NULL && 4754 pw->type == 4755 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4756 (pw->nconns < 2 || pw->selconn == index || 4757 pw->selconn == -1) && 4758 (ctl->dir & HDA_CTL_OUT)) || 4759 (strategy == HDA_PARSE_DIRECT && 4760 ctl->widget->nid == w->nid)) && 4761 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4762 if (pw != NULL && pw->selconn == -1) 4763 pw->selconn = index; 4764 ossdev = 0; 4765 switch (conndev) { 4766 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4767 ossdev = SOUND_MIXER_MIC; 4768 break; 4769 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4770 ossdev = SOUND_MIXER_LINE; 4771 break; 4772 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4773 ossdev = SOUND_MIXER_CD; 4774 break; 4775 default: 4776 ossdev = 4777 hdac_audio_ctl_ossmixer_getnextdev( 4778 devinfo); 4779 if (ossdev < 0) 4780 ossdev = 0; 4781 break; 4782 } 4783 if (strategy == HDA_PARSE_MIXER) { 4784 fl |= SOUND_MASK_VOLUME; 4785 ctl->ossmask |= SOUND_MASK_VOLUME; 4786 } 4787 fl |= 1 << ossdev; 4788 ctl->ossmask |= 1 << ossdev; 4789 ctl->ossdev = ossdev; 4790 } 4791 } 4792 w->ctlflags |= fl; 4793 return (fl); 4794 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4795 i = 0; 4796 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4797 if (ctl->enable == 0 || ctl->widget == NULL) 4798 continue; 4799 /* XXX This should be compressed! */ 4800 if (((ctl->widget->nid == pnid && ctl->index == index && 4801 (ctl->dir & HDA_CTL_IN)) || 4802 (ctl->widget->nid == pnid && pw != NULL && 4803 pw->type == 4804 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4805 (pw->nconns < 2 || pw->selconn == index || 4806 pw->selconn == -1) && 4807 (ctl->dir & HDA_CTL_OUT)) || 4808 (strategy == HDA_PARSE_DIRECT && 4809 ctl->widget->nid == w->nid)) && 4810 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4811 if (pw != NULL && pw->selconn == -1) 4812 pw->selconn = index; 4813 fl |= SOUND_MASK_VOLUME; 4814 fl |= SOUND_MASK_SPEAKER; 4815 ctl->ossmask |= SOUND_MASK_VOLUME; 4816 ctl->ossmask |= SOUND_MASK_SPEAKER; 4817 ctl->ossdev = SOUND_MIXER_SPEAKER; 4818 } 4819 } 4820 w->ctlflags |= fl; 4821 return (fl); 4822 } 4823 return (0); 4824} 4825 4826static uint32_t 4827hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4828{ 4829 struct hdac_widget *w, *cw; 4830 struct hdac_audio_ctl *ctl; 4831 uint32_t fl; 4832 int i; 4833 4834 if (depth > HDA_PARSE_MAXDEPTH) 4835 return (0); 4836 4837 w = hdac_widget_get(devinfo, nid); 4838 if (w == NULL || w->enable == 0) 4839 return (0); 4840 /*if (!(w->pflags & HDA_ADC_PATH)) 4841 return (0); 4842 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4843 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4844 return (0);*/ 4845 i = 0; 4846 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4847 if (ctl->enable == 0 || ctl->widget == NULL) 4848 continue; 4849 if (ctl->widget->nid == nid) { 4850 ctl->ossmask |= SOUND_MASK_RECLEV; 4851 w->ctlflags |= SOUND_MASK_RECLEV; 4852 return (SOUND_MASK_RECLEV); 4853 } 4854 } 4855 for (i = 0; i < w->nconns; i++) { 4856 cw = hdac_widget_get(devinfo, w->conns[i]); 4857 if (cw == NULL || cw->enable == 0) 4858 continue; 4859 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4860 continue; 4861 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4862 if (fl != 0) { 4863 cw->ctlflags |= fl; 4864 w->ctlflags |= fl; 4865 return (fl); 4866 } 4867 } 4868 return (0); 4869} 4870 4871static int 4872hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4873{ 4874 struct hdac_widget *w, *cw; 4875 int i, child = 0; 4876 4877 if (depth > HDA_PARSE_MAXDEPTH) 4878 return (0); 4879 4880 w = hdac_widget_get(devinfo, nid); 4881 if (w == NULL || w->enable == 0) 4882 return (0); 4883 /*if (!(w->pflags & HDA_ADC_PATH)) 4884 return (0); 4885 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4886 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4887 return (0);*/ 4888 /* XXX weak! */ 4889 for (i = 0; i < w->nconns; i++) { 4890 cw = hdac_widget_get(devinfo, w->conns[i]); 4891 if (cw == NULL) 4892 continue; 4893 if (++child > 1) { 4894 w->pflags |= HDA_ADC_RECSEL; 4895 return (1); 4896 } 4897 } 4898 for (i = 0; i < w->nconns; i++) { 4899 if (hdac_audio_ctl_recsel_build(devinfo, 4900 w->conns[i], depth + 1) != 0) 4901 return (1); 4902 } 4903 return (0); 4904} 4905 4906static int 4907hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4908{ 4909 struct hdac_widget *w, *cw; 4910 int i, j, conndev, found_dac = 0; 4911 int strategy; 4912 4913 strategy = devinfo->function.audio.parsing_strategy; 4914 4915 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4916 w = hdac_widget_get(devinfo, i); 4917 if (w == NULL || w->enable == 0) 4918 continue; 4919 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4920 continue; 4921 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4922 continue; 4923 conndev = w->wclass.pin.config & 4924 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4925 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4926 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4927 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4928 continue; 4929 for (j = 0; j < w->nconns; j++) { 4930 cw = hdac_widget_get(devinfo, w->conns[j]); 4931 if (cw == NULL || cw->enable == 0) 4932 continue; 4933 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4934 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4935 cw->type == 4936 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4937 continue; 4938 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4939 != 0) { 4940 if (w->selconn == -1) 4941 w->selconn = j; 4942 w->pflags |= HDA_DAC_PATH; 4943 found_dac++; 4944 } 4945 } 4946 } 4947 4948 return (found_dac); 4949} 4950 4951static void 4952hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4953{ 4954 struct hdac_widget *w; 4955 struct hdac_audio_ctl *ctl; 4956 int i, j, dacs, strategy; 4957 4958 /* Construct DAC path */ 4959 strategy = HDA_PARSE_MIXER; 4960 devinfo->function.audio.parsing_strategy = strategy; 4961 HDA_BOOTVERBOSE( 4962 device_printf(devinfo->codec->sc->dev, 4963 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4964 HDA_WIDGET_PARSER_REV); 4965 ); 4966 dacs = hdac_audio_build_tree_strategy(devinfo); 4967 if (dacs == 0) { 4968 HDA_BOOTVERBOSE( 4969 device_printf(devinfo->codec->sc->dev, 4970 "HDA_DEBUG: HWiP: 0 DAC path found! " 4971 "Retrying parser " 4972 "using HDA_PARSE_DIRECT strategy.\n"); 4973 ); 4974 strategy = HDA_PARSE_DIRECT; 4975 devinfo->function.audio.parsing_strategy = strategy; 4976 dacs = hdac_audio_build_tree_strategy(devinfo); 4977 } 4978 4979 HDA_BOOTVERBOSE( 4980 device_printf(devinfo->codec->sc->dev, 4981 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4982 "strategy.\n", 4983 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4984 ); 4985 4986 /* Construct ADC path */ 4987 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4988 w = hdac_widget_get(devinfo, i); 4989 if (w == NULL || w->enable == 0) 4990 continue; 4991 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4992 continue; 4993 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4994 } 4995 4996 /* Output mixers */ 4997 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4998 w = hdac_widget_get(devinfo, i); 4999 if (w == NULL || w->enable == 0) 5000 continue; 5001 if ((strategy == HDA_PARSE_MIXER && 5002 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 5003 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 5004 && (w->pflags & HDA_DAC_PATH)) || 5005 (strategy == HDA_PARSE_DIRECT && (w->pflags & 5006 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 5007 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 5008 w->nid, devinfo->startnode - 1, 0, 0); 5009 } else if (w->type == 5010 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 5011 j = 0; 5012 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 5013 NULL) { 5014 if (ctl->enable == 0 || ctl->widget == NULL) 5015 continue; 5016 if (ctl->widget->nid != w->nid) 5017 continue; 5018 ctl->ossmask |= SOUND_MASK_VOLUME; 5019 ctl->ossmask |= SOUND_MASK_SPEAKER; 5020 ctl->ossdev = SOUND_MIXER_SPEAKER; 5021 w->ctlflags |= SOUND_MASK_VOLUME; 5022 w->ctlflags |= SOUND_MASK_SPEAKER; 5023 } 5024 } 5025 } 5026 5027 /* Input mixers (rec) */ 5028 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5029 w = hdac_widget_get(devinfo, i); 5030 if (w == NULL || w->enable == 0) 5031 continue; 5032 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 5033 w->pflags & HDA_ADC_PATH)) 5034 continue; 5035 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 5036 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 5037 } 5038} 5039 5040#define HDA_COMMIT_CONN (1 << 0) 5041#define HDA_COMMIT_CTRL (1 << 1) 5042#define HDA_COMMIT_EAPD (1 << 2) 5043#define HDA_COMMIT_GPIO (1 << 3) 5044#define HDA_COMMIT_MISC (1 << 4) 5045#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5046 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5047 5048static void 5049hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5050{ 5051 struct hdac_softc *sc = devinfo->codec->sc; 5052 struct hdac_widget *w; 5053 nid_t cad; 5054 int i; 5055 5056 if (!(cfl & HDA_COMMIT_ALL)) 5057 return; 5058 5059 cad = devinfo->codec->cad; 5060 5061 if ((cfl & HDA_COMMIT_MISC)) { 5062 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5063 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5064 0x7e7, 0), cad); 5065 } 5066 5067 if (cfl & HDA_COMMIT_GPIO) { 5068 uint32_t gdata, gmask, gdir; 5069 int commitgpio, numgpio; 5070 5071 gdata = 0; 5072 gmask = 0; 5073 gdir = 0; 5074 commitgpio = 0; 5075 5076 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5077 devinfo->function.audio.gpio); 5078 5079 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5080 commitgpio = (numgpio > 0) ? 1 : 0; 5081 else { 5082 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5083 if (!(devinfo->function.audio.quirks & 5084 (1 << i))) 5085 continue; 5086 if (commitgpio == 0) { 5087 commitgpio = 1; 5088 HDA_BOOTVERBOSE( 5089 gdata = hdac_command(sc, 5090 HDA_CMD_GET_GPIO_DATA(cad, 5091 devinfo->nid), cad); 5092 gmask = hdac_command(sc, 5093 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5094 devinfo->nid), cad); 5095 gdir = hdac_command(sc, 5096 HDA_CMD_GET_GPIO_DIRECTION(cad, 5097 devinfo->nid), cad); 5098 device_printf(sc->dev, 5099 "GPIO init: data=0x%08x " 5100 "mask=0x%08x dir=0x%08x\n", 5101 gdata, gmask, gdir); 5102 gdata = 0; 5103 gmask = 0; 5104 gdir = 0; 5105 ); 5106 } 5107 gdata |= 1 << i; 5108 gmask |= 1 << i; 5109 gdir |= 1 << i; 5110 } 5111 } 5112 5113 if (commitgpio != 0) { 5114 HDA_BOOTVERBOSE( 5115 device_printf(sc->dev, 5116 "GPIO commit: data=0x%08x mask=0x%08x " 5117 "dir=0x%08x\n", 5118 gdata, gmask, gdir); 5119 ); 5120 hdac_command(sc, 5121 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5122 gmask), cad); 5123 hdac_command(sc, 5124 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5125 gdir), cad); 5126 hdac_command(sc, 5127 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5128 gdata), cad); 5129 } 5130 } 5131 5132 for (i = 0; i < devinfo->nodecnt; i++) { 5133 w = &devinfo->widget[i]; 5134 if (w == NULL || w->enable == 0) 5135 continue; 5136 if (cfl & HDA_COMMIT_CONN) { 5137 if (w->selconn == -1) 5138 w->selconn = 0; 5139 if (w->nconns > 0) 5140 hdac_widget_connection_select(w, w->selconn); 5141 } 5142 if ((cfl & HDA_COMMIT_CTRL) && 5143 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5144 uint32_t pincap; 5145 5146 pincap = w->wclass.pin.cap; 5147 5148 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5149 (HDA_DAC_PATH | HDA_ADC_PATH)) 5150 device_printf(sc->dev, "WARNING: node %d " 5151 "participate both for DAC/ADC!\n", w->nid); 5152 if (w->pflags & HDA_DAC_PATH) { 5153 w->wclass.pin.ctrl &= 5154 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5155 if ((w->wclass.pin.config & 5156 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5157 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5158 w->wclass.pin.ctrl &= 5159 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5160 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5161 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5162 w->wclass.pin.ctrl |= 5163 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5164 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5165 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5166 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5167 w->wclass.pin.ctrl |= 5168 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5169 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5170 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5171 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5172 w->wclass.pin.ctrl |= 5173 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5174 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5175 } else if (w->pflags & HDA_ADC_PATH) { 5176 w->wclass.pin.ctrl &= 5177 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5178 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5179 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5180 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5181 w->wclass.pin.ctrl |= 5182 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5183 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5184 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5185 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5186 w->wclass.pin.ctrl |= 5187 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5188 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5189 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5190 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5191 w->wclass.pin.ctrl |= 5192 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5193 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5194 } else 5195 w->wclass.pin.ctrl &= ~( 5196 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5197 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5198 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5199 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5200 hdac_command(sc, 5201 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5202 w->wclass.pin.ctrl), cad); 5203 } 5204 if ((cfl & HDA_COMMIT_EAPD) && 5205 w->param.eapdbtl != HDAC_INVALID) { 5206 uint32_t val; 5207 5208 val = w->param.eapdbtl; 5209 if (devinfo->function.audio.quirks & 5210 HDA_QUIRK_EAPDINV) 5211 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5212 hdac_command(sc, 5213 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5214 val), cad); 5215 5216 } 5217 DELAY(1000); 5218 } 5219} 5220 5221static void 5222hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5223{ 5224 struct hdac_softc *sc = devinfo->codec->sc; 5225 struct hdac_audio_ctl *ctl; 5226 int i; 5227 5228 devinfo->function.audio.mvol = 100 | (100 << 8); 5229 i = 0; 5230 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5231 if (ctl->enable == 0 || ctl->widget == NULL) { 5232 HDA_BOOTVERBOSE( 5233 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5234 i, (ctl->widget != NULL) ? 5235 ctl->widget->nid : -1); 5236 if (ctl->childwidget != NULL) 5237 printf(" childnid=%d", 5238 ctl->childwidget->nid); 5239 if (ctl->widget == NULL) 5240 printf(" NULL WIDGET!"); 5241 printf(" DISABLED\n"); 5242 ); 5243 continue; 5244 } 5245 HDA_BOOTVERBOSE( 5246 if (ctl->ossmask == 0) { 5247 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5248 i, ctl->widget->nid); 5249 if (ctl->childwidget != NULL) 5250 printf(" childnid=%d", 5251 ctl->childwidget->nid); 5252 printf(" Bind to NONE\n"); 5253 } 5254 ); 5255 if (ctl->step > 0) { 5256 ctl->ossval = (ctl->left * 100) / ctl->step; 5257 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5258 } else 5259 ctl->ossval = 0; 5260 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5261 ctl->left, ctl->right); 5262 } 5263} 5264 5265static int 5266hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5267{ 5268 struct hdac_chan *ch; 5269 struct hdac_widget *w; 5270 uint32_t cap, fmtcap, pcmcap, path; 5271 int i, type, ret, max; 5272 5273 if (dir == PCMDIR_PLAY) { 5274 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5275 ch = &devinfo->codec->sc->play; 5276 path = HDA_DAC_PATH; 5277 } else { 5278 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5279 ch = &devinfo->codec->sc->rec; 5280 path = HDA_ADC_PATH; 5281 } 5282 5283 ch->caps = hdac_caps; 5284 ch->caps.fmtlist = ch->fmtlist; 5285 ch->bit16 = 1; 5286 ch->bit32 = 0; 5287 ch->pcmrates[0] = 48000; 5288 ch->pcmrates[1] = 0; 5289 5290 ret = 0; 5291 fmtcap = devinfo->function.audio.supp_stream_formats; 5292 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5293 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5294 5295 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5296 w = hdac_widget_get(devinfo, i); 5297 if (w == NULL || w->enable == 0 || w->type != type || 5298 !(w->pflags & path)) 5299 continue; 5300 cap = w->param.widget_cap; 5301 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5302 continue;*/ 5303 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5304 continue; 5305 cap = w->param.supp_stream_formats; 5306 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5307 } 5308 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5309 }*/ 5310 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5311 continue; 5312 if (ret == 0) { 5313 fmtcap = w->param.supp_stream_formats; 5314 pcmcap = w->param.supp_pcm_size_rate; 5315 } else { 5316 fmtcap &= w->param.supp_stream_formats; 5317 pcmcap &= w->param.supp_pcm_size_rate; 5318 } 5319 ch->io[ret++] = i; 5320 } 5321 ch->io[ret] = -1; 5322 5323 ch->supp_stream_formats = fmtcap; 5324 ch->supp_pcm_size_rate = pcmcap; 5325 5326 /* 5327 * 8bit = 0 5328 * 16bit = 1 5329 * 20bit = 2 5330 * 24bit = 3 5331 * 32bit = 4 5332 */ 5333 if (ret > 0) { 5334 cap = pcmcap; 5335 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5336 ch->bit16 = 1; 5337 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5338 ch->bit16 = 0; 5339 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5340 ch->bit32 = 4; 5341 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5342 ch->bit32 = 3; 5343 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5344 ch->bit32 = 2; 5345 i = 0; 5346 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5347 ch->fmtlist[i++] = AFMT_S16_LE; 5348 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5349 if (ch->bit32 > 0) { 5350 if (!(devinfo->function.audio.quirks & 5351 HDA_QUIRK_FORCESTEREO)) 5352 ch->fmtlist[i++] = AFMT_S32_LE; 5353 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5354 } 5355 ch->fmtlist[i] = 0; 5356 i = 0; 5357 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5358 ch->pcmrates[i++] = 8000; 5359 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5360 ch->pcmrates[i++] = 11025; 5361 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5362 ch->pcmrates[i++] = 16000; 5363 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5364 ch->pcmrates[i++] = 22050; 5365 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5366 ch->pcmrates[i++] = 32000; 5367 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5368 ch->pcmrates[i++] = 44100; 5369 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5370 ch->pcmrates[i++] = 48000; 5371 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5372 ch->pcmrates[i++] = 88200; 5373 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5374 ch->pcmrates[i++] = 96000; 5375 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5376 ch->pcmrates[i++] = 176400; 5377 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5378 ch->pcmrates[i++] = 192000; 5379 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5380 ch->pcmrates[i] = 0; 5381 if (i > 0) { 5382 ch->caps.minspeed = ch->pcmrates[0]; 5383 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5384 } 5385 } 5386 5387 return (ret); 5388} 5389 5390static void 5391hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5392{ 5393 struct hdac_audio_ctl *ctl; 5394 struct hdac_softc *sc = devinfo->codec->sc; 5395 int i; 5396 uint32_t fl = 0; 5397 5398 5399 if (flag == 0) { 5400 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5401 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5402 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5403 } 5404 5405 i = 0; 5406 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5407 if (ctl->enable == 0 || ctl->widget == NULL || 5408 ctl->widget->enable == 0 || (ctl->ossmask & 5409 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5410 continue; 5411 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5412 (flag != 0 && (ctl->ossmask & flag))) { 5413 if (banner != NULL) { 5414 device_printf(sc->dev, "\n"); 5415 device_printf(sc->dev, "%s\n", banner); 5416 } 5417 goto hdac_ctl_dump_it_all; 5418 } 5419 } 5420 5421 return; 5422 5423hdac_ctl_dump_it_all: 5424 i = 0; 5425 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5426 if (ctl->enable == 0 || ctl->widget == NULL || 5427 ctl->widget->enable == 0) 5428 continue; 5429 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5430 (flag != 0 && (ctl->ossmask & flag)))) 5431 continue; 5432 if (flag == 0) { 5433 device_printf(sc->dev, "\n"); 5434 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5435 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5436 } 5437 device_printf(sc->dev, " |\n"); 5438 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5439 ctl->widget->nid, ctl->index); 5440 if (ctl->childwidget != NULL) 5441 printf("(nid: %2d) ", ctl->childwidget->nid); 5442 else 5443 printf(" "); 5444 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5445 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5446 ctl->ossmask); 5447 } 5448} 5449 5450static void 5451hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5452{ 5453 uint32_t cap; 5454 5455 cap = fcap; 5456 if (cap != 0) { 5457 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5458 device_printf(sc->dev, " Format:"); 5459 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5460 printf(" AC3"); 5461 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5462 printf(" FLOAT32"); 5463 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5464 printf(" PCM"); 5465 printf("\n"); 5466 } 5467 cap = pcmcap; 5468 if (cap != 0) { 5469 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5470 device_printf(sc->dev, " PCM size:"); 5471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5472 printf(" 8"); 5473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5474 printf(" 16"); 5475 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5476 printf(" 20"); 5477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5478 printf(" 24"); 5479 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5480 printf(" 32"); 5481 printf("\n"); 5482 device_printf(sc->dev, " PCM rate:"); 5483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5484 printf(" 8"); 5485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5486 printf(" 11"); 5487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5488 printf(" 16"); 5489 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5490 printf(" 22"); 5491 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5492 printf(" 32"); 5493 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5494 printf(" 44"); 5495 printf(" 48"); 5496 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5497 printf(" 88"); 5498 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5499 printf(" 96"); 5500 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5501 printf(" 176"); 5502 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5503 printf(" 192"); 5504 printf("\n"); 5505 } 5506} 5507 5508static void 5509hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5510{ 5511 uint32_t pincap, wcap; 5512 5513 pincap = w->wclass.pin.cap; 5514 wcap = w->param.widget_cap; 5515 5516 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5517 device_printf(sc->dev, " "); 5518 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5519 printf(" ISC"); 5520 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5521 printf(" TRQD"); 5522 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5523 printf(" PDC"); 5524 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5525 printf(" HP"); 5526 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5527 printf(" OUT"); 5528 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5529 printf(" IN"); 5530 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5531 printf(" BAL"); 5532 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5533 printf(" VREF["); 5534 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5535 printf(" 50"); 5536 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5537 printf(" 80"); 5538 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5539 printf(" 100"); 5540 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5541 printf(" GROUND"); 5542 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5543 printf(" HIZ"); 5544 printf(" ]"); 5545 } 5546 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5547 printf(" EAPD"); 5548 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5549 printf(" : UNSOL"); 5550 printf("\n"); 5551 device_printf(sc->dev, " Pin config: 0x%08x\n", 5552 w->wclass.pin.config); 5553 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5554 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5555 printf(" HP"); 5556 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5557 printf(" IN"); 5558 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5559 printf(" OUT"); 5560 printf("\n"); 5561} 5562 5563static void 5564hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5565{ 5566 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5567 device_printf(sc->dev, " " 5568 "mute=%d step=%d size=%d offset=%d\n", 5569 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5570 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5571 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5572 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5573} 5574 5575static void 5576hdac_dump_nodes(struct hdac_devinfo *devinfo) 5577{ 5578 struct hdac_softc *sc = devinfo->codec->sc; 5579 struct hdac_widget *w, *cw; 5580 int i, j; 5581 5582 device_printf(sc->dev, "\n"); 5583 device_printf(sc->dev, "Default Parameter\n"); 5584 device_printf(sc->dev, "-----------------\n"); 5585 hdac_dump_audio_formats(sc, 5586 devinfo->function.audio.supp_stream_formats, 5587 devinfo->function.audio.supp_pcm_size_rate); 5588 device_printf(sc->dev, " IN amp: 0x%08x\n", 5589 devinfo->function.audio.inamp_cap); 5590 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5591 devinfo->function.audio.outamp_cap); 5592 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5593 w = hdac_widget_get(devinfo, i); 5594 if (w == NULL) { 5595 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5596 continue; 5597 } 5598 device_printf(sc->dev, "\n"); 5599 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5600 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5601 "DIGITAL" : "ANALOG", 5602 (w->enable == 0) ? " [DISABLED]" : ""); 5603 device_printf(sc->dev, " name: %s\n", w->name); 5604 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5605 w->param.widget_cap); 5606 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5607 w->pflags); 5608 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5609 w->ctlflags); 5610 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5611 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5612 hdac_dump_audio_formats(sc, 5613 w->param.supp_stream_formats, 5614 w->param.supp_pcm_size_rate); 5615 } else if (w->type == 5616 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5617 hdac_dump_pin(sc, w); 5618 if (w->param.eapdbtl != HDAC_INVALID) 5619 device_printf(sc->dev, " EAPD: 0x%08x\n", 5620 w->param.eapdbtl); 5621 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5622 w->param.outamp_cap != 0) 5623 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5624 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5625 w->param.inamp_cap != 0) 5626 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5627 device_printf(sc->dev, " connections: %d\n", w->nconns); 5628 for (j = 0; j < w->nconns; j++) { 5629 cw = hdac_widget_get(devinfo, w->conns[j]); 5630 device_printf(sc->dev, " |\n"); 5631 device_printf(sc->dev, " + <- nid=%d [%s]", 5632 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5633 if (cw == NULL) 5634 printf(" [UNKNOWN]"); 5635 else if (cw->enable == 0) 5636 printf(" [DISABLED]"); 5637 if (w->nconns > 1 && w->selconn == j && w->type != 5638 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5639 printf(" (selected)"); 5640 printf("\n"); 5641 } 5642 } 5643 5644} 5645 5646static int 5647hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5648{ 5649 struct hdac_widget *w, *cw; 5650 struct hdac_softc *sc = devinfo->codec->sc; 5651 int i; 5652 5653 if (depth > HDA_PARSE_MAXDEPTH) 5654 return (0); 5655 5656 w = hdac_widget_get(devinfo, nid); 5657 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5658 return (0); 5659 5660 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5661 device_printf(sc->dev, "\n"); 5662 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5663 device_printf(sc->dev, " ^\n"); 5664 device_printf(sc->dev, " |\n"); 5665 device_printf(sc->dev, " +-----<------+\n"); 5666 } else { 5667 device_printf(sc->dev, " ^\n"); 5668 device_printf(sc->dev, " |\n"); 5669 device_printf(sc->dev, " "); 5670 printf(" nid=%d [%s]\n", w->nid, w->name); 5671 } 5672 5673 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5674 return (1); 5675 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5676 for (i = 0; i < w->nconns; i++) { 5677 cw = hdac_widget_get(devinfo, w->conns[i]); 5678 if (cw == NULL || cw->enable == 0 || cw->type == 5679 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5680 continue; 5681 if (hdac_dump_dac_internal(devinfo, cw->nid, 5682 depth + 1) != 0) 5683 return (1); 5684 } 5685 } else if ((w->type == 5686 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5687 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5688 w->selconn > -1 && w->selconn < w->nconns) { 5689 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5690 depth + 1) != 0) 5691 return (1); 5692 } 5693 5694 return (0); 5695} 5696 5697static void 5698hdac_dump_dac(struct hdac_devinfo *devinfo) 5699{ 5700 struct hdac_widget *w; 5701 struct hdac_softc *sc = devinfo->codec->sc; 5702 int i, printed = 0; 5703 5704 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5705 w = hdac_widget_get(devinfo, i); 5706 if (w == NULL || w->enable == 0) 5707 continue; 5708 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5709 !(w->pflags & HDA_DAC_PATH)) 5710 continue; 5711 if (printed == 0) { 5712 printed = 1; 5713 device_printf(sc->dev, "\n"); 5714 device_printf(sc->dev, "Playback path:\n"); 5715 } 5716 hdac_dump_dac_internal(devinfo, w->nid, 0); 5717 } 5718} 5719 5720static void 5721hdac_dump_adc(struct hdac_devinfo *devinfo) 5722{ 5723 struct hdac_widget *w, *cw; 5724 struct hdac_softc *sc = devinfo->codec->sc; 5725 int i, j; 5726 int printed = 0; 5727 char ossdevs[256]; 5728 5729 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5730 w = hdac_widget_get(devinfo, i); 5731 if (w == NULL || w->enable == 0) 5732 continue; 5733 if (!(w->pflags & HDA_ADC_RECSEL)) 5734 continue; 5735 if (printed == 0) { 5736 printed = 1; 5737 device_printf(sc->dev, "\n"); 5738 device_printf(sc->dev, "Recording sources:\n"); 5739 } 5740 device_printf(sc->dev, "\n"); 5741 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5742 for (j = 0; j < w->nconns; j++) { 5743 cw = hdac_widget_get(devinfo, w->conns[j]); 5744 if (cw == NULL || cw->enable == 0) 5745 continue; 5746 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5747 ossdevs, sizeof(ossdevs)); 5748 device_printf(sc->dev, " |\n"); 5749 device_printf(sc->dev, " + <- nid=%d [%s]", 5750 cw->nid, cw->name); 5751 if (strlen(ossdevs) > 0) { 5752 printf(" [recsrc: %s]", ossdevs); 5753 } 5754 printf("\n"); 5755 } 5756 } 5757} 5758 5759static void 5760hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5761{ 5762 nid_t *nids; 5763 5764 if (pcnt > 0) { 5765 device_printf(sc->dev, "\n"); 5766 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5767 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5768 sc->play.supp_pcm_size_rate); 5769 device_printf(sc->dev, " DAC:"); 5770 for (nids = sc->play.io; *nids != -1; nids++) 5771 printf(" %d", *nids); 5772 printf("\n"); 5773 } 5774 5775 if (rcnt > 0) { 5776 device_printf(sc->dev, "\n"); 5777 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5778 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5779 sc->rec.supp_pcm_size_rate); 5780 device_printf(sc->dev, " ADC:"); 5781 for (nids = sc->rec.io; *nids != -1; nids++) 5782 printf(" %d", *nids); 5783 printf("\n"); 5784 } 5785} 5786 5787static void 5788hdac_release_resources(struct hdac_softc *sc) 5789{ 5790 struct hdac_devinfo *devinfo = NULL; 5791 device_t *devlist = NULL; 5792 int i, devcount; 5793 5794 if (sc == NULL) 5795 return; 5796 5797 hdac_lock(sc); 5798 sc->polling = 0; 5799 sc->poll_ival = 0; 5800 callout_stop(&sc->poll_hda); 5801 callout_stop(&sc->poll_hdac); 5802 callout_stop(&sc->poll_jack); 5803 hdac_reset(sc); 5804 hdac_unlock(sc); 5805 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5806 callout_drain(&sc->poll_hda); 5807 callout_drain(&sc->poll_hdac); 5808 callout_drain(&sc->poll_jack); 5809 5810 hdac_irq_free(sc); 5811 5812 device_get_children(sc->dev, &devlist, &devcount); 5813 for (i = 0; devlist != NULL && i < devcount; i++) { 5814 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5815 if (devinfo == NULL) 5816 continue; 5817 if (devinfo->widget != NULL) 5818 free(devinfo->widget, M_HDAC); 5819 if (devinfo->node_type == 5820 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5821 devinfo->function.audio.ctl != NULL) 5822 free(devinfo->function.audio.ctl, M_HDAC); 5823 free(devinfo, M_HDAC); 5824 device_delete_child(sc->dev, devlist[i]); 5825 } 5826 if (devlist != NULL) 5827 free(devlist, M_TEMP); 5828 5829 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5830 if (sc->codecs[i] != NULL) 5831 free(sc->codecs[i], M_HDAC); 5832 sc->codecs[i] = NULL; 5833 } 5834 5835 hdac_dma_free(sc, &sc->pos_dma); 5836 hdac_dma_free(sc, &sc->rirb_dma); 5837 hdac_dma_free(sc, &sc->corb_dma); 5838 if (sc->play.blkcnt > 0) 5839 hdac_dma_free(sc, &sc->play.bdl_dma); 5840 if (sc->rec.blkcnt > 0) 5841 hdac_dma_free(sc, &sc->rec.bdl_dma); 5842 if (sc->chan_dmat != NULL) { 5843 bus_dma_tag_destroy(sc->chan_dmat); 5844 sc->chan_dmat = NULL; 5845 } 5846 hdac_mem_free(sc); 5847 snd_mtxfree(sc->lock); 5848 free(sc, M_DEVBUF); 5849} 5850 5851/* This function surely going to make its way into upper level someday. */ 5852static void 5853hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5854{ 5855 const char *res = NULL; 5856 int i = 0, j, k, len, inv; 5857 5858 if (on != NULL) 5859 *on = 0; 5860 if (off != NULL) 5861 *off = 0; 5862 if (sc == NULL) 5863 return; 5864 if (resource_string_value(device_get_name(sc->dev), 5865 device_get_unit(sc->dev), "config", &res) != 0) 5866 return; 5867 if (!(res != NULL && strlen(res) > 0)) 5868 return; 5869 HDA_BOOTVERBOSE( 5870 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5871 ); 5872 for (;;) { 5873 while (res[i] != '\0' && 5874 (res[i] == ',' || isspace(res[i]) != 0)) 5875 i++; 5876 if (res[i] == '\0') { 5877 HDA_BOOTVERBOSE( 5878 printf("\n"); 5879 ); 5880 return; 5881 } 5882 j = i; 5883 while (res[j] != '\0' && 5884 !(res[j] == ',' || isspace(res[j]) != 0)) 5885 j++; 5886 len = j - i; 5887 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5888 inv = 2; 5889 else 5890 inv = 0; 5891 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5892 if (strncmp(res + i + inv, 5893 hdac_quirks_tab[k].key, len - inv) != 0) 5894 continue; 5895 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5896 break; 5897 HDA_BOOTVERBOSE( 5898 printf(" %s%s", (inv != 0) ? "no" : "", 5899 hdac_quirks_tab[k].key); 5900 ); 5901 if (inv == 0 && on != NULL) 5902 *on |= hdac_quirks_tab[k].value; 5903 else if (inv != 0 && off != NULL) 5904 *off |= hdac_quirks_tab[k].value; 5905 break; 5906 } 5907 i = j; 5908 } 5909} 5910 5911#ifdef SND_DYNSYSCTL 5912static int 5913sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5914{ 5915 struct hdac_softc *sc; 5916 struct hdac_devinfo *devinfo; 5917 device_t dev; 5918 uint32_t ctl; 5919 int err, val; 5920 5921 dev = oidp->oid_arg1; 5922 devinfo = pcm_getdevinfo(dev); 5923 if (devinfo == NULL || devinfo->codec == NULL || 5924 devinfo->codec->sc == NULL) 5925 return (EINVAL); 5926 sc = devinfo->codec->sc; 5927 hdac_lock(sc); 5928 val = sc->polling; 5929 hdac_unlock(sc); 5930 err = sysctl_handle_int(oidp, &val, 0, req); 5931 5932 if (err != 0 || req->newptr == NULL) 5933 return (err); 5934 if (val < 0 || val > 1) 5935 return (EINVAL); 5936 5937 hdac_lock(sc); 5938 if (val != sc->polling) { 5939 if (hda_chan_active(sc) != 0) 5940 err = EBUSY; 5941 else if (val == 0) { 5942 callout_stop(&sc->poll_hdac); 5943 hdac_unlock(sc); 5944 callout_drain(&sc->poll_hdac); 5945 hdac_lock(sc); 5946 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5947 sc->rirb_size / 2); 5948 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5949 ctl |= HDAC_RIRBCTL_RINTCTL; 5950 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5951 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5952 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5953 sc->polling = 0; 5954 DELAY(1000); 5955 } else { 5956 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5957 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5958 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5959 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5960 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5961 hdac_unlock(sc); 5962 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5963 hdac_lock(sc); 5964 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5965 sc); 5966 sc->polling = 1; 5967 DELAY(1000); 5968 } 5969 } 5970 hdac_unlock(sc); 5971 5972 return (err); 5973} 5974 5975static int 5976sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5977{ 5978 struct hdac_softc *sc; 5979 struct hdac_devinfo *devinfo; 5980 device_t dev; 5981 int err, val; 5982 5983 dev = oidp->oid_arg1; 5984 devinfo = pcm_getdevinfo(dev); 5985 if (devinfo == NULL || devinfo->codec == NULL || 5986 devinfo->codec->sc == NULL) 5987 return (EINVAL); 5988 sc = devinfo->codec->sc; 5989 hdac_lock(sc); 5990 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5991 hdac_unlock(sc); 5992 err = sysctl_handle_int(oidp, &val, 0, req); 5993 5994 if (err != 0 || req->newptr == NULL) 5995 return (err); 5996 5997 if (val < 1) 5998 val = 1; 5999 if (val > 5000) 6000 val = 5000; 6001 val = ((uint64_t)val * hz) / 1000; 6002 if (val < 1) 6003 val = 1; 6004 if (val > (hz * 5)) 6005 val = hz * 5; 6006 6007 hdac_lock(sc); 6008 sc->poll_ival = val; 6009 hdac_unlock(sc); 6010 6011 return (err); 6012} 6013 6014#ifdef SND_DEBUG 6015static int 6016sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6017{ 6018 struct hdac_softc *sc; 6019 struct hdac_devinfo *devinfo; 6020 struct hdac_widget *w; 6021 device_t dev; 6022 uint32_t res, pincap, timeout; 6023 int i, err, val; 6024 nid_t cad; 6025 6026 dev = oidp->oid_arg1; 6027 devinfo = pcm_getdevinfo(dev); 6028 if (devinfo == NULL || devinfo->codec == NULL || 6029 devinfo->codec->sc == NULL) 6030 return (EINVAL); 6031 val = 0; 6032 err = sysctl_handle_int(oidp, &val, 0, req); 6033 if (err != 0 || req->newptr == NULL || val == 0) 6034 return (err); 6035 sc = devinfo->codec->sc; 6036 cad = devinfo->codec->cad; 6037 hdac_lock(sc); 6038 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6039 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6040 w = hdac_widget_get(devinfo, i); 6041 if (w == NULL || w->type != 6042 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6043 continue; 6044 pincap = w->wclass.pin.cap; 6045 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6046 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6047 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6048 timeout = 10000; 6049 hdac_command(sc, 6050 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6051 do { 6052 res = hdac_command(sc, 6053 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6054 if (res != 0x7fffffff) 6055 break; 6056 DELAY(10); 6057 } while (--timeout != 0); 6058 } else { 6059 timeout = -1; 6060 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6061 w->nid), cad); 6062 } 6063 device_printf(dev, 6064 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6065 w->nid, timeout, res, 6066 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6067 } 6068 device_printf(dev, 6069 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6070 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6071 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6072 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6073 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6074 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6075 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6076 device_printf(dev, " GPI:"); 6077 res = hdac_command(sc, 6078 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6079 printf(" data=0x%08x", res); 6080 res = hdac_command(sc, 6081 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6082 cad); 6083 printf(" wake=0x%08x", res); 6084 res = hdac_command(sc, 6085 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6086 cad); 6087 printf(" unsol=0x%08x", res); 6088 res = hdac_command(sc, 6089 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6090 printf(" sticky=0x%08x\n", res); 6091 } 6092 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6093 device_printf(dev, " GPO:"); 6094 res = hdac_command(sc, 6095 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6096 printf(" data=0x%08x\n", res); 6097 } 6098 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6099 device_printf(dev, "GPI0:"); 6100 res = hdac_command(sc, 6101 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6102 printf(" data=0x%08x", res); 6103 res = hdac_command(sc, 6104 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6105 printf(" enable=0x%08x", res); 6106 res = hdac_command(sc, 6107 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6108 printf(" direction=0x%08x\n", res); 6109 res = hdac_command(sc, 6110 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6111 device_printf(dev, " wake=0x%08x", res); 6112 res = hdac_command(sc, 6113 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6114 cad); 6115 printf(" unsol=0x%08x", res); 6116 res = hdac_command(sc, 6117 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6118 printf(" sticky=0x%08x\n", res); 6119 } 6120 hdac_unlock(sc); 6121 return (0); 6122} 6123#endif 6124#endif 6125 6126static void 6127hdac_attach2(void *arg) 6128{ 6129 struct hdac_softc *sc; 6130 struct hdac_widget *w; 6131 struct hdac_audio_ctl *ctl; 6132 uint32_t quirks_on, quirks_off; 6133 int pcnt, rcnt, codec_index; 6134 int i; 6135 char status[SND_STATUSLEN]; 6136 device_t *devlist = NULL; 6137 int devcount; 6138 struct hdac_devinfo *devinfo = NULL; 6139 6140 sc = (struct hdac_softc *)arg; 6141 6142 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6143 6144 HDA_BOOTVERBOSE( 6145 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6146 quirks_on, quirks_off); 6147 ); 6148 6149 if (resource_int_value(device_get_name(sc->dev), 6150 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6151 switch (sc->pci_subvendor) { 6152 case GB_G33S2H_SUBVENDOR: 6153 codec_index = 2; 6154 break; 6155 default: 6156 codec_index = 0; 6157 break; 6158 } 6159 } 6160 6161 hdac_lock(sc); 6162 6163 /* Remove ourselves from the config hooks */ 6164 if (sc->intrhook.ich_func != NULL) { 6165 config_intrhook_disestablish(&sc->intrhook); 6166 sc->intrhook.ich_func = NULL; 6167 } 6168 6169 /* Start the corb and rirb engines */ 6170 HDA_BOOTVERBOSE( 6171 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6172 ); 6173 hdac_corb_start(sc); 6174 HDA_BOOTVERBOSE( 6175 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6176 ); 6177 hdac_rirb_start(sc); 6178 6179 HDA_BOOTVERBOSE( 6180 device_printf(sc->dev, 6181 "HDA_DEBUG: Enabling controller interrupt...\n"); 6182 ); 6183 if (sc->polling == 0) 6184 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6185 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6186 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6187 HDAC_GCTL_UNSOL); 6188 6189 DELAY(1000); 6190 6191 HDA_BOOTVERBOSE( 6192 device_printf(sc->dev, 6193 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6194 codec_index); 6195 ); 6196 hdac_scan_codecs(sc, codec_index); 6197 6198 device_get_children(sc->dev, &devlist, &devcount); 6199 for (i = 0; devlist != NULL && i < devcount; i++) { 6200 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6201 if (devinfo != NULL && devinfo->node_type == 6202 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6203 break; 6204 } else 6205 devinfo = NULL; 6206 } 6207 if (devlist != NULL) 6208 free(devlist, M_TEMP); 6209 6210 if (devinfo == NULL) { 6211 hdac_unlock(sc); 6212 device_printf(sc->dev, "Audio Function Group not found!\n"); 6213 hdac_release_resources(sc); 6214 return; 6215 } 6216 6217 HDA_BOOTVERBOSE( 6218 device_printf(sc->dev, 6219 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6220 devinfo->nid, devinfo->codec->cad); 6221 ); 6222 hdac_audio_parse(devinfo); 6223 HDA_BOOTVERBOSE( 6224 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6225 ); 6226 hdac_audio_ctl_parse(devinfo); 6227 HDA_BOOTVERBOSE( 6228 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6229 ); 6230 hdac_vendor_patch_parse(devinfo); 6231 if (quirks_on != 0) 6232 devinfo->function.audio.quirks |= quirks_on; 6233 if (quirks_off != 0) 6234 devinfo->function.audio.quirks &= ~quirks_off; 6235 6236 /* XXX Disable all DIGITAL path. */ 6237 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6238 w = hdac_widget_get(devinfo, i); 6239 if (w == NULL) 6240 continue; 6241 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6242 w->enable = 0; 6243 continue; 6244 } 6245 /* XXX Disable useless pin ? */ 6246 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6247 (w->wclass.pin.config & 6248 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6249 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6250 w->enable = 0; 6251 } 6252 i = 0; 6253 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6254 if (ctl->widget == NULL) 6255 continue; 6256 if (ctl->ossmask & SOUND_MASK_DISABLE) 6257 ctl->enable = 0; 6258 w = ctl->widget; 6259 if (w->enable == 0 || 6260 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6261 ctl->enable = 0; 6262 w = ctl->childwidget; 6263 if (w == NULL) 6264 continue; 6265 if (w->enable == 0 || 6266 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6267 ctl->enable = 0; 6268 } 6269 6270 HDA_BOOTVERBOSE( 6271 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6272 ); 6273 hdac_audio_build_tree(devinfo); 6274 6275 i = 0; 6276 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6277 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6278 ctl->ossmask = 0; 6279 } 6280 HDA_BOOTVERBOSE( 6281 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6282 ); 6283 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6284 HDA_BOOTVERBOSE( 6285 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6286 ); 6287 hdac_audio_ctl_commit(devinfo); 6288 6289 HDA_BOOTVERBOSE( 6290 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6291 ); 6292 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6293 HDA_BOOTVERBOSE( 6294 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6295 ); 6296 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6297 6298 hdac_unlock(sc); 6299 HDA_BOOTVERBOSE( 6300 device_printf(sc->dev, 6301 "HDA_DEBUG: OSS mixer initialization...\n"); 6302 ); 6303 6304 /* 6305 * There is no point of return after this. If the driver failed, 6306 * so be it. Let the detach procedure do all the cleanup. 6307 */ 6308 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6309 device_printf(sc->dev, "Can't register mixer\n"); 6310 6311 if (pcnt > 0) 6312 pcnt = 1; 6313 if (rcnt > 0) 6314 rcnt = 1; 6315 6316 HDA_BOOTVERBOSE( 6317 device_printf(sc->dev, 6318 "HDA_DEBUG: Registering PCM channels...\n"); 6319 ); 6320 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6321 device_printf(sc->dev, "Can't register PCM\n"); 6322 6323 sc->registered++; 6324 6325 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6326 hdac_dma_alloc(sc, &sc->pos_dma, 6327 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6328 HDA_BOOTVERBOSE( 6329 device_printf(sc->dev, 6330 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6331 ); 6332 } 6333 6334 for (i = 0; i < pcnt; i++) 6335 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6336 for (i = 0; i < rcnt; i++) 6337 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6338 6339#ifdef SND_DYNSYSCTL 6340 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6341 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6342 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6343 sysctl_hdac_polling, "I", "Enable polling mode"); 6344 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6345 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6346 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6347 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6348 "Controller/Jack Sense polling interval (1-1000 ms)"); 6349#ifdef SND_DEBUG 6350 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6351 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6352 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6353 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6354#endif 6355#endif 6356 6357 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6358 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6359 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6360 pcm_setstatus(sc->dev, status); 6361 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6362 HDA_BOOTVERBOSE( 6363 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6364 hdac_codec_id(devinfo)); 6365 ); 6366 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6367 HDA_DRV_TEST_REV); 6368 6369 HDA_BOOTVERBOSE( 6370 if (devinfo->function.audio.quirks != 0) { 6371 device_printf(sc->dev, "\n"); 6372 device_printf(sc->dev, "HDA config/quirks:"); 6373 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6374 if ((devinfo->function.audio.quirks & 6375 hdac_quirks_tab[i].value) == 6376 hdac_quirks_tab[i].value) 6377 printf(" %s", hdac_quirks_tab[i].key); 6378 } 6379 printf("\n"); 6380 } 6381 device_printf(sc->dev, "\n"); 6382 device_printf(sc->dev, "+-------------------+\n"); 6383 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6384 device_printf(sc->dev, "+-------------------+\n"); 6385 hdac_dump_nodes(devinfo); 6386 device_printf(sc->dev, "\n"); 6387 device_printf(sc->dev, "+------------------------+\n"); 6388 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6389 device_printf(sc->dev, "+------------------------+\n"); 6390 device_printf(sc->dev, "\n"); 6391 i = 0; 6392 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6393 device_printf(sc->dev, "%3d: nid=%d", i, 6394 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6395 if (ctl->childwidget != NULL) 6396 printf(" cnid=%d", ctl->childwidget->nid); 6397 printf(" dir=0x%x index=%d " 6398 "ossmask=0x%08x ossdev=%d%s\n", 6399 ctl->dir, ctl->index, 6400 ctl->ossmask, ctl->ossdev, 6401 (ctl->enable == 0) ? " [DISABLED]" : ""); 6402 } 6403 device_printf(sc->dev, "\n"); 6404 device_printf(sc->dev, "+-----------------------------------+\n"); 6405 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6406 device_printf(sc->dev, "+-----------------------------------+\n"); 6407 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6408 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6409 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6410 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6411 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6412 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6413 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6414 hdac_dump_ctls(devinfo, NULL, 0); 6415 hdac_dump_dac(devinfo); 6416 hdac_dump_adc(devinfo); 6417 device_printf(sc->dev, "\n"); 6418 device_printf(sc->dev, "+--------------------------------------+\n"); 6419 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6420 device_printf(sc->dev, "+--------------------------------------+\n"); 6421 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6422 ); 6423 6424 if (sc->polling != 0) { 6425 hdac_lock(sc); 6426 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6427 hdac_unlock(sc); 6428 } 6429} 6430 6431/**************************************************************************** 6432 * int hdac_detach(device_t) 6433 * 6434 * Detach and free up resources utilized by the hdac device. 6435 ****************************************************************************/ 6436static int 6437hdac_detach(device_t dev) 6438{ 6439 struct hdac_softc *sc = NULL; 6440 struct hdac_devinfo *devinfo = NULL; 6441 int err; 6442 6443 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6444 if (devinfo != NULL && devinfo->codec != NULL) 6445 sc = devinfo->codec->sc; 6446 if (sc == NULL) 6447 return (0); 6448 6449 if (sc->registered > 0) { 6450 err = pcm_unregister(dev); 6451 if (err != 0) 6452 return (err); 6453 } 6454 6455 hdac_release_resources(sc); 6456 6457 return (0); 6458} 6459 6460static device_method_t hdac_methods[] = { 6461 /* device interface */ 6462 DEVMETHOD(device_probe, hdac_probe), 6463 DEVMETHOD(device_attach, hdac_attach), 6464 DEVMETHOD(device_detach, hdac_detach), 6465 { 0, 0 } 6466}; 6467 6468static driver_t hdac_driver = { 6469 "pcm", 6470 hdac_methods, 6471 PCM_SOFTC_SIZE, 6472}; 6473 6474DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6475MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6476MODULE_VERSION(snd_hda, 1); 6477