hdac.c revision 174025
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sys/ctype.h> 75#include <sys/taskqueue.h> 76 77#include <dev/sound/pci/hda/hdac_private.h> 78#include <dev/sound/pci/hda/hdac_reg.h> 79#include <dev/sound/pci/hda/hda_reg.h> 80#include <dev/sound/pci/hda/hdac.h> 81 82#include "mixer_if.h" 83 84#define HDA_DRV_TEST_REV "20071129_0050" 85#define HDA_WIDGET_PARSER_REV 1 86 87SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 174025 2007-11-28 15:27:22Z ariff $"); 88 89#define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93} while(0) 94 95#if 1 96#undef HDAC_INTR_EXTRA 97#define HDAC_INTR_EXTRA 1 98#endif 99 100#define hdac_lock(sc) snd_mtxlock((sc)->lock) 101#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103#define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 106#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 107 (fl) == 0xffffffff || \ 108 (((fl) & 0xffff0000) == 0xffff0000 && \ 109 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 110 (((fl) & 0x0000ffff) == 0x0000ffff && \ 111 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 112#define HDA_MATCH_ALL 0xffffffff 113#define HDAC_INVALID 0xffffffff 114 115/* Default controller / jack sense poll: 250ms */ 116#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 117 118/* 119 * Make room for possible 4096 playback/record channels, in 100 years to come. 120 */ 121#define HDAC_TRIGGER_NONE 0x00000000 122#define HDAC_TRIGGER_PLAY 0x00000fff 123#define HDAC_TRIGGER_REC 0x00fff000 124#define HDAC_TRIGGER_UNSOL 0x80000000 125 126#define HDA_MODEL_CONSTRUCT(vendor, model) \ 127 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 128 129/* Controller models */ 130 131/* Intel */ 132#define INTEL_VENDORID 0x8086 133#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 134#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 135#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 136#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 137#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 138#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 139 140/* Nvidia */ 141#define NVIDIA_VENDORID 0x10de 142#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 143#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 144#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 145#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 146#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 147#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 148#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 149#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 150#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 151 152/* ATI */ 153#define ATI_VENDORID 0x1002 154#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 155#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 156#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 157 158/* VIA */ 159#define VIA_VENDORID 0x1106 160#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 161#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 162 163/* SiS */ 164#define SIS_VENDORID 0x1039 165#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 166#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 167 168/* OEM/subvendors */ 169 170/* Intel */ 171#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 172 173/* HP/Compaq */ 174#define HP_VENDORID 0x103c 175#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 176#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 177#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 178#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 179#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 180#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 181#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 182#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 183#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 184/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 185#define HP_NX6325_SUBVENDORX 0x103c30b0 186 187/* Dell */ 188#define DELL_VENDORID 0x1028 189#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 190#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 191#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 192#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 193#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 194 195/* Clevo */ 196#define CLEVO_VENDORID 0x1558 197#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 198#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 199 200/* Acer */ 201#define ACER_VENDORID 0x1025 202#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 203#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 204#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 205#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 206 207/* Asus */ 208#define ASUS_VENDORID 0x1043 209#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 210#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 211#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 212#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 213#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 214#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 215#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 216#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 217#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 218#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 219#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 220#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 221#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 222#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 223#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 224 225/* IBM / Lenovo */ 226#define IBM_VENDORID 0x1014 227#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 228#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 229 230/* Lenovo */ 231#define LENOVO_VENDORID 0x17aa 232#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 233#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 234#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 235 236/* Samsung */ 237#define SAMSUNG_VENDORID 0x144d 238#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 239#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 240 241/* Medion ? */ 242#define MEDION_VENDORID 0x161f 243#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 244#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 245 246/* Apple Computer Inc. */ 247#define APPLE_VENDORID 0x106b 248#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 249 250/* 251 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 252 * instead of their own, which is beyond my comprehension 253 * (see HDA_CODEC_STAC9221 below). 254 */ 255#define APPLE_INTEL_MAC 0x76808384 256 257/* LG Electronics */ 258#define LG_VENDORID 0x1854 259#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 260#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 261 262/* Fujitsu Siemens */ 263#define FS_VENDORID 0x1734 264#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 265#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 266#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 267 268/* Fujitsu Limited */ 269#define FL_VENDORID 0x10cf 270#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 271#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 272 273/* Toshiba */ 274#define TOSHIBA_VENDORID 0x1179 275#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 276#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 277#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 278 279/* Micro-Star International (MSI) */ 280#define MSI_VENDORID 0x1462 281#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 282#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 283#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 284 285/* Giga-Byte Technology */ 286#define GB_VENDORID 0x1458 287#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 288#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 289 290/* Uniwill ? */ 291#define UNIWILL_VENDORID 0x1584 292#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 293#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 294 295 296/* Misc constants.. */ 297#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 298#define HDA_AMP_MUTE_NONE (0) 299#define HDA_AMP_MUTE_LEFT (1 << 0) 300#define HDA_AMP_MUTE_RIGHT (1 << 1) 301#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 302 303#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 304#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 305 306#define HDA_DAC_PATH (1 << 0) 307#define HDA_ADC_PATH (1 << 1) 308#define HDA_ADC_RECSEL (1 << 2) 309 310#define HDA_DAC_LOCKED (1 << 3) 311#define HDA_ADC_LOCKED (1 << 4) 312 313#define HDA_CTL_OUT (1 << 0) 314#define HDA_CTL_IN (1 << 1) 315#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 316 317#define HDA_GPIO_MAX 8 318/* 0 - 7 = GPIO , 8 = Flush */ 319#define HDA_QUIRK_GPIO0 (1 << 0) 320#define HDA_QUIRK_GPIO1 (1 << 1) 321#define HDA_QUIRK_GPIO2 (1 << 2) 322#define HDA_QUIRK_GPIO3 (1 << 3) 323#define HDA_QUIRK_GPIO4 (1 << 4) 324#define HDA_QUIRK_GPIO5 (1 << 5) 325#define HDA_QUIRK_GPIO6 (1 << 6) 326#define HDA_QUIRK_GPIO7 (1 << 7) 327#define HDA_QUIRK_GPIOFLUSH (1 << 8) 328 329/* 9 - 25 = anything else */ 330#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 331#define HDA_QUIRK_FIXEDRATE (1 << 10) 332#define HDA_QUIRK_FORCESTEREO (1 << 11) 333#define HDA_QUIRK_EAPDINV (1 << 12) 334#define HDA_QUIRK_DMAPOS (1 << 13) 335 336/* 26 - 31 = vrefs */ 337#define HDA_QUIRK_IVREF50 (1 << 26) 338#define HDA_QUIRK_IVREF80 (1 << 27) 339#define HDA_QUIRK_IVREF100 (1 << 28) 340#define HDA_QUIRK_OVREF50 (1 << 29) 341#define HDA_QUIRK_OVREF80 (1 << 30) 342#define HDA_QUIRK_OVREF100 (1 << 31) 343 344#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 345 HDA_QUIRK_IVREF100) 346#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 347 HDA_QUIRK_OVREF100) 348#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 349 350#define SOUND_MASK_SKIP (1 << 30) 351#define SOUND_MASK_DISABLE (1 << 31) 352 353#if __FreeBSD_version < 600000 354#define taskqueue_drain(...) 355#endif 356 357static const struct { 358 char *key; 359 uint32_t value; 360} hdac_quirks_tab[] = { 361 { "gpio0", HDA_QUIRK_GPIO0 }, 362 { "gpio1", HDA_QUIRK_GPIO1 }, 363 { "gpio2", HDA_QUIRK_GPIO2 }, 364 { "gpio3", HDA_QUIRK_GPIO3 }, 365 { "gpio4", HDA_QUIRK_GPIO4 }, 366 { "gpio5", HDA_QUIRK_GPIO5 }, 367 { "gpio6", HDA_QUIRK_GPIO6 }, 368 { "gpio7", HDA_QUIRK_GPIO7 }, 369 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 370 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 371 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 372 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 373 { "eapdinv", HDA_QUIRK_EAPDINV }, 374 { "dmapos", HDA_QUIRK_DMAPOS }, 375 { "ivref50", HDA_QUIRK_IVREF50 }, 376 { "ivref80", HDA_QUIRK_IVREF80 }, 377 { "ivref100", HDA_QUIRK_IVREF100 }, 378 { "ovref50", HDA_QUIRK_OVREF50 }, 379 { "ovref80", HDA_QUIRK_OVREF80 }, 380 { "ovref100", HDA_QUIRK_OVREF100 }, 381 { "ivref", HDA_QUIRK_IVREF }, 382 { "ovref", HDA_QUIRK_OVREF }, 383 { "vref", HDA_QUIRK_VREF }, 384}; 385#define HDAC_QUIRKS_TAB_LEN \ 386 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 387 388#define HDA_BDL_MIN 2 389#define HDA_BDL_MAX 256 390#define HDA_BDL_DEFAULT HDA_BDL_MIN 391 392#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 393#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 394 395#define HDA_BUFSZ_MIN 4096 396#define HDA_BUFSZ_MAX 65536 397#define HDA_BUFSZ_DEFAULT 16384 398 399#define HDA_PARSE_MAXDEPTH 10 400 401#define HDAC_UNSOLTAG_EVENT_HP 0x00 402#define HDAC_UNSOLTAG_EVENT_TEST 0x01 403 404MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 405 406enum { 407 HDA_PARSE_MIXER, 408 HDA_PARSE_DIRECT 409}; 410 411/* Default */ 412static uint32_t hdac_fmt[] = { 413 AFMT_STEREO | AFMT_S16_LE, 414 0 415}; 416 417static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 418 419static const struct { 420 uint32_t model; 421 char *desc; 422} hdac_devices[] = { 423 { HDA_INTEL_82801F, "Intel 82801F" }, 424 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 425 { HDA_INTEL_82801G, "Intel 82801G" }, 426 { HDA_INTEL_82801H, "Intel 82801H" }, 427 { HDA_INTEL_82801I, "Intel 82801I" }, 428 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 429 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 430 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 431 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 432 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 433 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 434 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 435 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 436 { HDA_ATI_SB450, "ATI SB450" }, 437 { HDA_ATI_SB600, "ATI SB600" }, 438 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 439 { HDA_SIS_966, "SiS 966" }, 440 /* Unknown */ 441 { HDA_INTEL_ALL, "Intel (Unknown)" }, 442 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 443 { HDA_ATI_ALL, "ATI (Unknown)" }, 444 { HDA_VIA_ALL, "VIA (Unknown)" }, 445 { HDA_SIS_ALL, "SiS (Unknown)" }, 446}; 447#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 448 449static const struct { 450 uint16_t vendor; 451 uint8_t reg; 452 uint8_t mask; 453 uint8_t enable; 454} hdac_pcie_snoop[] = { 455 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 456 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 457 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 458}; 459#define HDAC_PCIESNOOP_LEN \ 460 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 461 462static const struct { 463 uint32_t rate; 464 int valid; 465 uint16_t base; 466 uint16_t mul; 467 uint16_t div; 468} hda_rate_tab[] = { 469 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 470 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 471 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 472 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 473 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 474 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 475 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 476 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 477 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 478 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 479 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 480 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 481 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 482 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 483 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 484 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 485 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 486 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 487 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 488 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 489 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 490 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 491 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 492 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 493 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 494 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 495 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 496 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 497 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 498 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 499 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 500 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 501 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 502 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 503 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 504}; 505#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 506 507/* All codecs you can eat... */ 508#define HDA_CODEC_CONSTRUCT(vendor, id) \ 509 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 510 511/* Realtek */ 512#define REALTEK_VENDORID 0x10ec 513#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 514#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 515#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 516#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 517#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 518#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 519#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 520#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 521#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 522#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 523#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 524#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 525 526/* Analog Devices */ 527#define ANALOGDEVICES_VENDORID 0x11d4 528#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 529#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 530#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 531#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 532#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 533#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 534#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 535 536/* CMedia */ 537#define CMEDIA_VENDORID 0x434d 538#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 539#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 540 541/* Sigmatel */ 542#define SIGMATEL_VENDORID 0x8384 543#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 544#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 545#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 546#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 547#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 548#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 549#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 550 551/* 552 * Conexant 553 * 554 * Ok, the truth is, I don't have any idea at all whether 555 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 556 * place that tell me it is "Venice" is from its Windows driver INF. 557 * 558 * Venice - CX????? 559 * Waikiki - CX20551-22 560 */ 561#define CONEXANT_VENDORID 0x14f1 562#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 563#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 564#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 565 566/* VIA */ 567#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 568#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 569#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 570#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 571#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 572#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 573#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 574#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 575#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 576#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 577#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 578#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 579#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 580 581 582/* Codecs */ 583static const struct { 584 uint32_t id; 585 char *name; 586} hdac_codecs[] = { 587 { HDA_CODEC_ALC260, "Realtek ALC260" }, 588 { HDA_CODEC_ALC262, "Realtek ALC262" }, 589 { HDA_CODEC_ALC268, "Realtek ALC268" }, 590 { HDA_CODEC_ALC660, "Realtek ALC660" }, 591 { HDA_CODEC_ALC861, "Realtek ALC861" }, 592 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 593 { HDA_CODEC_ALC880, "Realtek ALC880" }, 594 { HDA_CODEC_ALC882, "Realtek ALC882" }, 595 { HDA_CODEC_ALC883, "Realtek ALC883" }, 596 { HDA_CODEC_ALC885, "Realtek ALC885" }, 597 { HDA_CODEC_ALC888, "Realtek ALC888" }, 598 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 599 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 600 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 601 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 602 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 603 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 604 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 605 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 606 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 607 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 608 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 609 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 610 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 611 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 612 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 613 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 614 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 615 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 616 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 617 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 618 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 619 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 620 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 621 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 622 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 623 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 624 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 625 /* Unknown codec */ 626 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 627 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 628 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 629 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 630 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 631 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 632}; 633#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 634 635enum { 636 HDAC_HP_SWITCH_CTL, 637 HDAC_HP_SWITCH_CTRL, 638 HDAC_HP_SWITCH_DEBUG 639}; 640 641static const struct { 642 uint32_t model; 643 uint32_t id; 644 int type; 645 int inverted; 646 int polling; 647 int execsense; 648 nid_t hpnid; 649 nid_t spkrnid[8]; 650 nid_t eapdnid; 651} hdac_hp_switch[] = { 652 /* Specific OEM models */ 653 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 654 0, 0, -1, 17, { 16, -1 }, 16 }, 655 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 656 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 657 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 658 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 659 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 660 0, 0, -1, 6, { 5, -1 }, 5 }, 661 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 662 0, 0, -1, 6, { 5, -1 }, 5 }, 663 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 664 0, 0, -1, 6, { 5, -1 }, 5 }, 665 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 666 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 667 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 668 0, 0, -1, 6, { 5, -1 }, -1 }, 669 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 670 0, 0, -1, 27, { 20, -1 }, -1 }, 671 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 672 0, 0, -1, 13, { 14, -1 }, -1 }, 673 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 674 0, 0, -1, 13, { 14, -1 }, -1 }, 675 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 676 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 677 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 678 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 679 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 680 0, 0, -1, 10, { 13, -1 }, -1 }, 681 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 682 1, 0, -1, 26, { 27, -1 }, -1 }, 683 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 684 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 685 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 686 0, 0, -1, 27, { 20, -1 }, -1 }, 687 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 688 0, 0, -1, 20, { 21, -1 }, -1 }, 689 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 690 0, 0, -1, 20, { 21, -1 }, -1 }, 691 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 692 0, 0, -1, 20, { 21, -1 }, -1 }, 693 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 694 0, 0, -1, 20, { 21, -1 }, -1 }, 695 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 696 0, 0, -1, 20, { 27, -1 }, -1 }, 697 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 698 0, 0, -1, 20, { 27, -1 }, -1 }, 699 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 700 0, 0, -1, 20, { 21, -1 }, -1 }, 701 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 702 0, 0, -1, 20, { 16, -1 }, -1 }, 703 /* 704 * All models that at least come from the same vendor with 705 * simmilar codec. 706 */ 707 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 708 0, 0, -1, 17, { 16, -1 }, 16 }, 709 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 710 0, 0, -1, 6, { 5, -1 }, 5 }, 711 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 712 0, 0, -1, 6, { 5, -1 }, -1 }, 713 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 714 0, 0, -1, 13, { 14, -1 }, -1 }, 715#if 0 716 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 717 1, 0, -1, 26, { 27, -1 }, -1 }, 718 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 719 0, 0, -1, 20, { 21, -1 }, -1 }, 720#endif 721}; 722#define HDAC_HP_SWITCH_LEN \ 723 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 724 725static const struct { 726 uint32_t model; 727 uint32_t id; 728 nid_t eapdnid; 729 int hp_switch; 730} hdac_eapd_switch[] = { 731 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 732 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 733 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 734}; 735#define HDAC_EAPD_SWITCH_LEN \ 736 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 737 738/**************************************************************************** 739 * Function prototypes 740 ****************************************************************************/ 741static void hdac_intr_handler(void *); 742static int hdac_reset(struct hdac_softc *); 743static int hdac_get_capabilities(struct hdac_softc *); 744static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 745static int hdac_dma_alloc(struct hdac_softc *, 746 struct hdac_dma *, bus_size_t); 747static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 748static int hdac_mem_alloc(struct hdac_softc *); 749static void hdac_mem_free(struct hdac_softc *); 750static int hdac_irq_alloc(struct hdac_softc *); 751static void hdac_irq_free(struct hdac_softc *); 752static void hdac_corb_init(struct hdac_softc *); 753static void hdac_rirb_init(struct hdac_softc *); 754static void hdac_corb_start(struct hdac_softc *); 755static void hdac_rirb_start(struct hdac_softc *); 756static void hdac_scan_codecs(struct hdac_softc *, int); 757static int hdac_probe_codec(struct hdac_codec *); 758static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 759static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 760 761static void hdac_attach2(void *); 762 763static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 764 uint32_t, int); 765static void hdac_command_send_internal(struct hdac_softc *, 766 struct hdac_command_list *, int); 767 768static int hdac_probe(device_t); 769static int hdac_attach(device_t); 770static int hdac_detach(device_t); 771static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 772static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 773 uint32_t, int, int); 774static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 775 nid_t, int, int); 776static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 777 nid_t, nid_t, int, int, int, int, int, int); 778static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 779static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 780 781static int hdac_rirb_flush(struct hdac_softc *sc); 782static int hdac_unsolq_flush(struct hdac_softc *sc); 783 784#define hdac_command(a1, a2, a3) \ 785 hdac_command_sendone_internal(a1, a2, a3) 786 787#define hdac_codec_id(d) \ 788 ((uint32_t)((d == NULL) ? 0x00000000 : \ 789 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 790 ((uint32_t)(d)->device_id & 0x0000ffff)))) 791 792static char * 793hdac_codec_name(struct hdac_devinfo *devinfo) 794{ 795 uint32_t id; 796 int i; 797 798 id = hdac_codec_id(devinfo); 799 800 for (i = 0; i < HDAC_CODECS_LEN; i++) { 801 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 802 return (hdac_codecs[i].name); 803 } 804 805 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 806} 807 808static char * 809hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 810{ 811 static char *ossname[] = SOUND_DEVICE_NAMES; 812 static char *unknown = "???"; 813 int i; 814 815 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 816 if (devmask & (1 << i)) 817 return (ossname[i]); 818 } 819 return (unknown); 820} 821 822static void 823hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 824{ 825 static char *ossname[] = SOUND_DEVICE_NAMES; 826 int i, first = 1; 827 828 bzero(buf, len); 829 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 830 if (mask & (1 << i)) { 831 if (first == 0) 832 strlcat(buf, ", ", len); 833 strlcat(buf, ossname[i], len); 834 first = 0; 835 } 836 } 837} 838 839static struct hdac_audio_ctl * 840hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 841{ 842 if (devinfo == NULL || 843 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 844 index == NULL || devinfo->function.audio.ctl == NULL || 845 devinfo->function.audio.ctlcnt < 1 || 846 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 847 return (NULL); 848 return (&devinfo->function.audio.ctl[(*index)++]); 849} 850 851static struct hdac_audio_ctl * 852hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 853 int index, int cnt) 854{ 855 struct hdac_audio_ctl *ctl, *retctl = NULL; 856 int i, at, atindex, found = 0; 857 858 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 859 return (NULL); 860 861 at = cnt; 862 if (at == 0) 863 at = 1; 864 else if (at < 0) 865 at = -1; 866 atindex = index; 867 if (atindex < 0) 868 atindex = -1; 869 870 i = 0; 871 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 872 if (ctl->enable == 0 || ctl->widget == NULL) 873 continue; 874 if (!(ctl->widget->nid == nid && (atindex == -1 || 875 ctl->index == atindex))) 876 continue; 877 found++; 878 if (found == cnt) 879 return (ctl); 880 retctl = ctl; 881 } 882 883 return ((at == -1) ? retctl : NULL); 884} 885 886static void 887hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 888{ 889 struct hdac_softc *sc; 890 struct hdac_widget *w; 891 struct hdac_audio_ctl *ctl; 892 uint32_t val, id, res; 893 int i = 0, j, timeout, forcemute; 894 nid_t cad; 895 896 if (devinfo == NULL || devinfo->codec == NULL || 897 devinfo->codec->sc == NULL) 898 return; 899 900 sc = devinfo->codec->sc; 901 cad = devinfo->codec->cad; 902 id = hdac_codec_id(devinfo); 903 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 904 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 905 sc->pci_subvendor) && 906 hdac_hp_switch[i].id == id) 907 break; 908 } 909 910 if (i >= HDAC_HP_SWITCH_LEN) 911 return; 912 913 forcemute = 0; 914 if (hdac_hp_switch[i].eapdnid != -1) { 915 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 916 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 917 forcemute = (w->param.eapdbtl & 918 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 919 } 920 921 if (hdac_hp_switch[i].execsense != -1) 922 hdac_command(sc, 923 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 924 hdac_hp_switch[i].execsense), cad); 925 926 timeout = 10000; 927 do { 928 res = hdac_command(sc, 929 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 930 cad); 931 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 932 break; 933 DELAY(10); 934 } while (--timeout != 0); 935 936 HDA_BOOTVERBOSE( 937 device_printf(sc->dev, 938 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 939 hdac_hp_switch[i].hpnid, timeout, res); 940 ); 941 942 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 943 res ^= hdac_hp_switch[i].inverted; 944 945 switch (hdac_hp_switch[i].type) { 946 case HDAC_HP_SWITCH_CTL: 947 ctl = hdac_audio_ctl_amp_get(devinfo, 948 hdac_hp_switch[i].hpnid, 0, 1); 949 if (ctl != NULL) { 950 val = (res != 0 && forcemute == 0) ? 951 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 952 if (val != ctl->muted) { 953 ctl->muted = val; 954 hdac_audio_ctl_amp_set(ctl, 955 HDA_AMP_MUTE_DEFAULT, ctl->left, 956 ctl->right); 957 } 958 } 959 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 960 ctl = hdac_audio_ctl_amp_get(devinfo, 961 hdac_hp_switch[i].spkrnid[j], 0, 1); 962 if (ctl == NULL) 963 continue; 964 val = (res != 0 || forcemute == 1) ? 965 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 966 if (val == ctl->muted) 967 continue; 968 ctl->muted = val; 969 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 970 ctl->left, ctl->right); 971 } 972 break; 973 case HDAC_HP_SWITCH_CTRL: 974 if (res != 0) { 975 /* HP in */ 976 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 977 if (w != NULL && w->type == 978 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 979 if (forcemute == 0) 980 val = w->wclass.pin.ctrl | 981 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 982 else 983 val = w->wclass.pin.ctrl & 984 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 985 if (val != w->wclass.pin.ctrl) { 986 w->wclass.pin.ctrl = val; 987 hdac_command(sc, 988 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 989 w->nid, w->wclass.pin.ctrl), cad); 990 } 991 } 992 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 993 w = hdac_widget_get(devinfo, 994 hdac_hp_switch[i].spkrnid[j]); 995 if (w == NULL || w->type != 996 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 997 continue; 998 val = w->wclass.pin.ctrl & 999 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1000 if (val == w->wclass.pin.ctrl) 1001 continue; 1002 w->wclass.pin.ctrl = val; 1003 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1004 cad, w->nid, w->wclass.pin.ctrl), cad); 1005 } 1006 } else { 1007 /* HP out */ 1008 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1009 if (w != NULL && w->type == 1010 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1011 val = w->wclass.pin.ctrl & 1012 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1013 if (val != w->wclass.pin.ctrl) { 1014 w->wclass.pin.ctrl = val; 1015 hdac_command(sc, 1016 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1017 w->nid, w->wclass.pin.ctrl), cad); 1018 } 1019 } 1020 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1021 w = hdac_widget_get(devinfo, 1022 hdac_hp_switch[i].spkrnid[j]); 1023 if (w == NULL || w->type != 1024 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1025 continue; 1026 if (forcemute == 0) 1027 val = w->wclass.pin.ctrl | 1028 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1029 else 1030 val = w->wclass.pin.ctrl & 1031 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1032 if (val == w->wclass.pin.ctrl) 1033 continue; 1034 w->wclass.pin.ctrl = val; 1035 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1036 cad, w->nid, w->wclass.pin.ctrl), cad); 1037 } 1038 } 1039 break; 1040 case HDAC_HP_SWITCH_DEBUG: 1041 if (hdac_hp_switch[i].execsense != -1) 1042 hdac_command(sc, 1043 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1044 hdac_hp_switch[i].execsense), cad); 1045 res = hdac_command(sc, 1046 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1047 device_printf(sc->dev, 1048 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1049 hdac_hp_switch[i].hpnid, res); 1050 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1051 w = hdac_widget_get(devinfo, 1052 hdac_hp_switch[i].spkrnid[j]); 1053 if (w == NULL || w->type != 1054 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1055 continue; 1056 if (hdac_hp_switch[i].execsense != -1) 1057 hdac_command(sc, 1058 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1059 hdac_hp_switch[i].execsense), cad); 1060 res = hdac_command(sc, 1061 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1062 device_printf(sc->dev, 1063 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1064 j + 1, w->nid, res); 1065 } 1066 break; 1067 default: 1068 break; 1069 } 1070} 1071 1072static void 1073hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1074{ 1075 struct hdac_softc *sc; 1076 struct hdac_devinfo *devinfo = NULL; 1077 device_t *devlist = NULL; 1078 int devcount, i; 1079 1080 if (codec == NULL || codec->sc == NULL) 1081 return; 1082 1083 sc = codec->sc; 1084 1085 HDA_BOOTVERBOSE( 1086 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1087 ); 1088 1089 device_get_children(sc->dev, &devlist, &devcount); 1090 for (i = 0; devlist != NULL && i < devcount; i++) { 1091 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1092 if (devinfo != NULL && devinfo->node_type == 1093 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1094 devinfo->codec != NULL && 1095 devinfo->codec->cad == codec->cad) { 1096 break; 1097 } else 1098 devinfo = NULL; 1099 } 1100 if (devlist != NULL) 1101 free(devlist, M_TEMP); 1102 1103 if (devinfo == NULL) 1104 return; 1105 1106 switch (tag) { 1107 case HDAC_UNSOLTAG_EVENT_HP: 1108 hdac_hp_switch_handler(devinfo); 1109 break; 1110 case HDAC_UNSOLTAG_EVENT_TEST: 1111 device_printf(sc->dev, "Unsol Test!\n"); 1112 break; 1113 default: 1114 break; 1115 } 1116} 1117 1118static int 1119hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1120{ 1121 /* XXX to be removed */ 1122#ifdef HDAC_INTR_EXTRA 1123 uint32_t res; 1124#endif 1125 1126 if (!(ch->flags & HDAC_CHN_RUNNING)) 1127 return (0); 1128 1129 /* XXX to be removed */ 1130#ifdef HDAC_INTR_EXTRA 1131 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1132#endif 1133 1134 /* XXX to be removed */ 1135#ifdef HDAC_INTR_EXTRA 1136 HDA_BOOTVERBOSE( 1137 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1138 device_printf(sc->dev, 1139 "PCMDIR_%s intr triggered beyond stream boundary:" 1140 "%08x\n", 1141 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1142 ); 1143#endif 1144 1145 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1146 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1147 1148 /* XXX to be removed */ 1149#ifdef HDAC_INTR_EXTRA 1150 if (res & HDAC_SDSTS_BCIS) { 1151#endif 1152 return (1); 1153 /* XXX to be removed */ 1154#ifdef HDAC_INTR_EXTRA 1155 } 1156#endif 1157 1158 return (0); 1159} 1160 1161/**************************************************************************** 1162 * void hdac_intr_handler(void *) 1163 * 1164 * Interrupt handler. Processes interrupts received from the hdac. 1165 ****************************************************************************/ 1166static void 1167hdac_intr_handler(void *context) 1168{ 1169 struct hdac_softc *sc; 1170 uint32_t intsts; 1171 uint8_t rirbsts; 1172 struct hdac_rirb *rirb_base; 1173 uint32_t trigger; 1174 1175 sc = (struct hdac_softc *)context; 1176 1177 hdac_lock(sc); 1178 if (sc->polling != 0) { 1179 hdac_unlock(sc); 1180 return; 1181 } 1182 1183 /* Do we have anything to do? */ 1184 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1185 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1186 hdac_unlock(sc); 1187 return; 1188 } 1189 1190 trigger = 0; 1191 1192 /* Was this a controller interrupt? */ 1193 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1194 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1195 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1196 /* Get as many responses that we can */ 1197 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1198 HDAC_WRITE_1(&sc->mem, 1199 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1200 if (hdac_rirb_flush(sc) != 0) 1201 trigger |= HDAC_TRIGGER_UNSOL; 1202 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1203 } 1204 /* XXX to be removed */ 1205 /* Clear interrupt and exit */ 1206#ifdef HDAC_INTR_EXTRA 1207 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1208#endif 1209 } 1210 1211 if (intsts & HDAC_INTSTS_SIS_MASK) { 1212 if ((intsts & (1 << sc->num_iss)) && 1213 hdac_stream_intr(sc, &sc->play) != 0) 1214 trigger |= HDAC_TRIGGER_PLAY; 1215 if ((intsts & (1 << 0)) && 1216 hdac_stream_intr(sc, &sc->rec) != 0) 1217 trigger |= HDAC_TRIGGER_REC; 1218 /* XXX to be removed */ 1219#ifdef HDAC_INTR_EXTRA 1220 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1221 HDAC_INTSTS_SIS_MASK); 1222#endif 1223 } 1224 1225 hdac_unlock(sc); 1226 1227 if (trigger & HDAC_TRIGGER_PLAY) 1228 chn_intr(sc->play.c); 1229 if (trigger & HDAC_TRIGGER_REC) 1230 chn_intr(sc->rec.c); 1231 if (trigger & HDAC_TRIGGER_UNSOL) 1232 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1233} 1234 1235/**************************************************************************** 1236 * int hdac_reset(hdac_softc *) 1237 * 1238 * Reset the hdac to a quiescent and known state. 1239 ****************************************************************************/ 1240static int 1241hdac_reset(struct hdac_softc *sc) 1242{ 1243 uint32_t gctl; 1244 int count, i; 1245 1246 /* 1247 * Stop all Streams DMA engine 1248 */ 1249 for (i = 0; i < sc->num_iss; i++) 1250 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1251 for (i = 0; i < sc->num_oss; i++) 1252 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1253 for (i = 0; i < sc->num_bss; i++) 1254 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1255 1256 /* 1257 * Stop Control DMA engines. 1258 */ 1259 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1260 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1261 1262 /* 1263 * Reset DMA position buffer. 1264 */ 1265 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1266 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1267 1268 /* 1269 * Reset the controller. The reset must remain asserted for 1270 * a minimum of 100us. 1271 */ 1272 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1273 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1274 count = 10000; 1275 do { 1276 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1277 if (!(gctl & HDAC_GCTL_CRST)) 1278 break; 1279 DELAY(10); 1280 } while (--count); 1281 if (gctl & HDAC_GCTL_CRST) { 1282 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1283 return (ENXIO); 1284 } 1285 DELAY(100); 1286 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1287 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1288 count = 10000; 1289 do { 1290 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1291 if (gctl & HDAC_GCTL_CRST) 1292 break; 1293 DELAY(10); 1294 } while (--count); 1295 if (!(gctl & HDAC_GCTL_CRST)) { 1296 device_printf(sc->dev, "Device stuck in reset\n"); 1297 return (ENXIO); 1298 } 1299 1300 /* 1301 * Wait for codecs to finish their own reset sequence. The delay here 1302 * should be of 250us but for some reasons, on it's not enough on my 1303 * computer. Let's use twice as much as necessary to make sure that 1304 * it's reset properly. 1305 */ 1306 DELAY(1000); 1307 1308 return (0); 1309} 1310 1311 1312/**************************************************************************** 1313 * int hdac_get_capabilities(struct hdac_softc *); 1314 * 1315 * Retreive the general capabilities of the hdac; 1316 * Number of Input Streams 1317 * Number of Output Streams 1318 * Number of bidirectional Streams 1319 * 64bit ready 1320 * CORB and RIRB sizes 1321 ****************************************************************************/ 1322static int 1323hdac_get_capabilities(struct hdac_softc *sc) 1324{ 1325 uint16_t gcap; 1326 uint8_t corbsize, rirbsize; 1327 1328 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1329 sc->num_iss = HDAC_GCAP_ISS(gcap); 1330 sc->num_oss = HDAC_GCAP_OSS(gcap); 1331 sc->num_bss = HDAC_GCAP_BSS(gcap); 1332 1333 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1334 1335 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1336 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1337 HDAC_CORBSIZE_CORBSZCAP_256) 1338 sc->corb_size = 256; 1339 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1340 HDAC_CORBSIZE_CORBSZCAP_16) 1341 sc->corb_size = 16; 1342 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1343 HDAC_CORBSIZE_CORBSZCAP_2) 1344 sc->corb_size = 2; 1345 else { 1346 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1347 __func__, corbsize); 1348 return (ENXIO); 1349 } 1350 1351 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1352 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1353 HDAC_RIRBSIZE_RIRBSZCAP_256) 1354 sc->rirb_size = 256; 1355 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1356 HDAC_RIRBSIZE_RIRBSZCAP_16) 1357 sc->rirb_size = 16; 1358 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1359 HDAC_RIRBSIZE_RIRBSZCAP_2) 1360 sc->rirb_size = 2; 1361 else { 1362 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1363 __func__, rirbsize); 1364 return (ENXIO); 1365 } 1366 1367 return (0); 1368} 1369 1370 1371/**************************************************************************** 1372 * void hdac_dma_cb 1373 * 1374 * This function is called by bus_dmamap_load when the mapping has been 1375 * established. We just record the physical address of the mapping into 1376 * the struct hdac_dma passed in. 1377 ****************************************************************************/ 1378static void 1379hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1380{ 1381 struct hdac_dma *dma; 1382 1383 if (error == 0) { 1384 dma = (struct hdac_dma *)callback_arg; 1385 dma->dma_paddr = segs[0].ds_addr; 1386 } 1387} 1388 1389 1390/**************************************************************************** 1391 * int hdac_dma_alloc 1392 * 1393 * This function allocate and setup a dma region (struct hdac_dma). 1394 * It must be freed by a corresponding hdac_dma_free. 1395 ****************************************************************************/ 1396static int 1397hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1398{ 1399 bus_size_t roundsz; 1400 int result; 1401 int lowaddr; 1402 1403 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1404 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1405 BUS_SPACE_MAXADDR_32BIT; 1406 bzero(dma, sizeof(*dma)); 1407 1408 /* 1409 * Create a DMA tag 1410 */ 1411 result = bus_dma_tag_create(NULL, /* parent */ 1412 HDAC_DMA_ALIGNMENT, /* alignment */ 1413 0, /* boundary */ 1414 lowaddr, /* lowaddr */ 1415 BUS_SPACE_MAXADDR, /* highaddr */ 1416 NULL, /* filtfunc */ 1417 NULL, /* fistfuncarg */ 1418 roundsz, /* maxsize */ 1419 1, /* nsegments */ 1420 roundsz, /* maxsegsz */ 1421 0, /* flags */ 1422 NULL, /* lockfunc */ 1423 NULL, /* lockfuncarg */ 1424 &dma->dma_tag); /* dmat */ 1425 if (result != 0) { 1426 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1427 __func__, result); 1428 goto hdac_dma_alloc_fail; 1429 } 1430 1431 /* 1432 * Allocate DMA memory 1433 */ 1434 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1435 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1436 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1437 &dma->dma_map); 1438 if (result != 0) { 1439 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1440 __func__, result); 1441 goto hdac_dma_alloc_fail; 1442 } 1443 1444 dma->dma_size = roundsz; 1445 1446 /* 1447 * Map the memory 1448 */ 1449 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1450 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1451 if (result != 0 || dma->dma_paddr == 0) { 1452 if (result == 0) 1453 result = ENOMEM; 1454 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1455 __func__, result); 1456 goto hdac_dma_alloc_fail; 1457 } 1458 1459 HDA_BOOTVERBOSE( 1460 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1461 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1462 ); 1463 1464 return (0); 1465 1466hdac_dma_alloc_fail: 1467 hdac_dma_free(sc, dma); 1468 1469 return (result); 1470} 1471 1472 1473/**************************************************************************** 1474 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1475 * 1476 * Free a struct dhac_dma that has been previously allocated via the 1477 * hdac_dma_alloc function. 1478 ****************************************************************************/ 1479static void 1480hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1481{ 1482 if (dma->dma_map != NULL) { 1483#if 0 1484 /* Flush caches */ 1485 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1487#endif 1488 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1489 } 1490 if (dma->dma_vaddr != NULL) { 1491 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1492 dma->dma_vaddr = NULL; 1493 } 1494 dma->dma_map = NULL; 1495 if (dma->dma_tag != NULL) { 1496 bus_dma_tag_destroy(dma->dma_tag); 1497 dma->dma_tag = NULL; 1498 } 1499 dma->dma_size = 0; 1500} 1501 1502/**************************************************************************** 1503 * int hdac_mem_alloc(struct hdac_softc *) 1504 * 1505 * Allocate all the bus resources necessary to speak with the physical 1506 * controller. 1507 ****************************************************************************/ 1508static int 1509hdac_mem_alloc(struct hdac_softc *sc) 1510{ 1511 struct hdac_mem *mem; 1512 1513 mem = &sc->mem; 1514 mem->mem_rid = PCIR_BAR(0); 1515 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1516 &mem->mem_rid, RF_ACTIVE); 1517 if (mem->mem_res == NULL) { 1518 device_printf(sc->dev, 1519 "%s: Unable to allocate memory resource\n", __func__); 1520 return (ENOMEM); 1521 } 1522 mem->mem_tag = rman_get_bustag(mem->mem_res); 1523 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1524 1525 return (0); 1526} 1527 1528/**************************************************************************** 1529 * void hdac_mem_free(struct hdac_softc *) 1530 * 1531 * Free up resources previously allocated by hdac_mem_alloc. 1532 ****************************************************************************/ 1533static void 1534hdac_mem_free(struct hdac_softc *sc) 1535{ 1536 struct hdac_mem *mem; 1537 1538 mem = &sc->mem; 1539 if (mem->mem_res != NULL) 1540 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1541 mem->mem_res); 1542 mem->mem_res = NULL; 1543} 1544 1545/**************************************************************************** 1546 * int hdac_irq_alloc(struct hdac_softc *) 1547 * 1548 * Allocate and setup the resources necessary for interrupt handling. 1549 ****************************************************************************/ 1550static int 1551hdac_irq_alloc(struct hdac_softc *sc) 1552{ 1553 struct hdac_irq *irq; 1554 int result; 1555 1556 irq = &sc->irq; 1557 irq->irq_rid = 0x0; 1558 1559#if __FreeBSD_version >= 602106 1560 if ((sc->flags & HDAC_F_MSI) && 1561 (result = pci_msi_count(sc->dev)) == 1 && 1562 pci_alloc_msi(sc->dev, &result) == 0) 1563 irq->irq_rid = 0x1; 1564 else 1565#endif 1566 sc->flags &= ~HDAC_F_MSI; 1567 1568 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1569 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1570 if (irq->irq_res == NULL) { 1571 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1572 __func__); 1573 goto hdac_irq_alloc_fail; 1574 } 1575 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1576 hdac_intr_handler, sc, &irq->irq_handle); 1577 if (result != 0) { 1578 device_printf(sc->dev, 1579 "%s: Unable to setup interrupt handler (%x)\n", 1580 __func__, result); 1581 goto hdac_irq_alloc_fail; 1582 } 1583 1584 return (0); 1585 1586hdac_irq_alloc_fail: 1587 hdac_irq_free(sc); 1588 1589 return (ENXIO); 1590} 1591 1592/**************************************************************************** 1593 * void hdac_irq_free(struct hdac_softc *) 1594 * 1595 * Free up resources previously allocated by hdac_irq_alloc. 1596 ****************************************************************************/ 1597static void 1598hdac_irq_free(struct hdac_softc *sc) 1599{ 1600 struct hdac_irq *irq; 1601 1602 irq = &sc->irq; 1603 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1604 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1605 if (irq->irq_res != NULL) 1606 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1607 irq->irq_res); 1608#if __FreeBSD_version >= 602106 1609 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1610 pci_release_msi(sc->dev); 1611#endif 1612 irq->irq_handle = NULL; 1613 irq->irq_res = NULL; 1614 irq->irq_rid = 0x0; 1615} 1616 1617/**************************************************************************** 1618 * void hdac_corb_init(struct hdac_softc *) 1619 * 1620 * Initialize the corb registers for operations but do not start it up yet. 1621 * The CORB engine must not be running when this function is called. 1622 ****************************************************************************/ 1623static void 1624hdac_corb_init(struct hdac_softc *sc) 1625{ 1626 uint8_t corbsize; 1627 uint64_t corbpaddr; 1628 1629 /* Setup the CORB size. */ 1630 switch (sc->corb_size) { 1631 case 256: 1632 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1633 break; 1634 case 16: 1635 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1636 break; 1637 case 2: 1638 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1639 break; 1640 default: 1641 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1642 } 1643 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1644 1645 /* Setup the CORB Address in the hdac */ 1646 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1647 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1648 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1649 1650 /* Set the WP and RP */ 1651 sc->corb_wp = 0; 1652 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1653 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1654 /* 1655 * The HDA specification indicates that the CORBRPRST bit will always 1656 * read as zero. Unfortunately, it seems that at least the 82801G 1657 * doesn't reset the bit to zero, which stalls the corb engine. 1658 * manually reset the bit to zero before continuing. 1659 */ 1660 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1661 1662 /* Enable CORB error reporting */ 1663#if 0 1664 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1665#endif 1666} 1667 1668/**************************************************************************** 1669 * void hdac_rirb_init(struct hdac_softc *) 1670 * 1671 * Initialize the rirb registers for operations but do not start it up yet. 1672 * The RIRB engine must not be running when this function is called. 1673 ****************************************************************************/ 1674static void 1675hdac_rirb_init(struct hdac_softc *sc) 1676{ 1677 uint8_t rirbsize; 1678 uint64_t rirbpaddr; 1679 1680 /* Setup the RIRB size. */ 1681 switch (sc->rirb_size) { 1682 case 256: 1683 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1684 break; 1685 case 16: 1686 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1687 break; 1688 case 2: 1689 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1690 break; 1691 default: 1692 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1693 } 1694 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1695 1696 /* Setup the RIRB Address in the hdac */ 1697 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1698 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1699 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1700 1701 /* Setup the WP and RP */ 1702 sc->rirb_rp = 0; 1703 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1704 1705 if (sc->polling == 0) { 1706 /* Setup the interrupt threshold */ 1707 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1708 1709 /* Enable Overrun and response received reporting */ 1710#if 0 1711 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1712 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1713#else 1714 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1715#endif 1716 } 1717 1718#if 0 1719 /* 1720 * Make sure that the Host CPU cache doesn't contain any dirty 1721 * cache lines that falls in the rirb. If I understood correctly, it 1722 * should be sufficient to do this only once as the rirb is purely 1723 * read-only from now on. 1724 */ 1725 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1726 BUS_DMASYNC_PREREAD); 1727#endif 1728} 1729 1730/**************************************************************************** 1731 * void hdac_corb_start(hdac_softc *) 1732 * 1733 * Startup the corb DMA engine 1734 ****************************************************************************/ 1735static void 1736hdac_corb_start(struct hdac_softc *sc) 1737{ 1738 uint32_t corbctl; 1739 1740 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1741 corbctl |= HDAC_CORBCTL_CORBRUN; 1742 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1743} 1744 1745/**************************************************************************** 1746 * void hdac_rirb_start(hdac_softc *) 1747 * 1748 * Startup the rirb DMA engine 1749 ****************************************************************************/ 1750static void 1751hdac_rirb_start(struct hdac_softc *sc) 1752{ 1753 uint32_t rirbctl; 1754 1755 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1756 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1757 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1758} 1759 1760 1761/**************************************************************************** 1762 * void hdac_scan_codecs(struct hdac_softc *, int) 1763 * 1764 * Scan the bus for available codecs, starting with num. 1765 ****************************************************************************/ 1766static void 1767hdac_scan_codecs(struct hdac_softc *sc, int num) 1768{ 1769 struct hdac_codec *codec; 1770 int i; 1771 uint16_t statests; 1772 1773 if (num < 0) 1774 num = 0; 1775 if (num >= HDAC_CODEC_MAX) 1776 num = HDAC_CODEC_MAX - 1; 1777 1778 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1779 for (i = num; i < HDAC_CODEC_MAX; i++) { 1780 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1781 /* We have found a codec. */ 1782 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1783 M_HDAC, M_ZERO | M_NOWAIT); 1784 if (codec == NULL) { 1785 device_printf(sc->dev, 1786 "Unable to allocate memory for codec\n"); 1787 continue; 1788 } 1789 codec->commands = NULL; 1790 codec->responses_received = 0; 1791 codec->verbs_sent = 0; 1792 codec->sc = sc; 1793 codec->cad = i; 1794 sc->codecs[i] = codec; 1795 if (hdac_probe_codec(codec) != 0) 1796 break; 1797 } 1798 } 1799 /* All codecs have been probed, now try to attach drivers to them */ 1800 /* bus_generic_attach(sc->dev); */ 1801} 1802 1803/**************************************************************************** 1804 * void hdac_probe_codec(struct hdac_softc *, int) 1805 * 1806 * Probe a the given codec_id for available function groups. 1807 ****************************************************************************/ 1808static int 1809hdac_probe_codec(struct hdac_codec *codec) 1810{ 1811 struct hdac_softc *sc = codec->sc; 1812 struct hdac_devinfo *devinfo; 1813 uint32_t vendorid, revisionid, subnode; 1814 int startnode; 1815 int endnode; 1816 int i; 1817 nid_t cad = codec->cad; 1818 1819 HDA_BOOTVERBOSE( 1820 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1821 ); 1822 vendorid = hdac_command(sc, 1823 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1824 cad); 1825 revisionid = hdac_command(sc, 1826 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1827 cad); 1828 subnode = hdac_command(sc, 1829 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1830 cad); 1831 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1832 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1833 1834 HDA_BOOTVERBOSE( 1835 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1836 startnode, endnode); 1837 ); 1838 for (i = startnode; i < endnode; i++) { 1839 devinfo = hdac_probe_function(codec, i); 1840 if (devinfo != NULL) { 1841 /* XXX Ignore other FG. */ 1842 devinfo->vendor_id = 1843 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1844 devinfo->device_id = 1845 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1846 devinfo->revision_id = 1847 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1848 devinfo->stepping_id = 1849 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1850 HDA_BOOTVERBOSE( 1851 device_printf(sc->dev, 1852 "HDA_DEBUG: \tFound AFG nid=%d " 1853 "[startnode=%d endnode=%d]\n", 1854 devinfo->nid, startnode, endnode); 1855 ); 1856 return (1); 1857 } 1858 } 1859 1860 HDA_BOOTVERBOSE( 1861 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1862 ); 1863 return (0); 1864} 1865 1866static struct hdac_devinfo * 1867hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1868{ 1869 struct hdac_softc *sc = codec->sc; 1870 struct hdac_devinfo *devinfo; 1871 uint32_t fctgrptype; 1872 nid_t cad = codec->cad; 1873 1874 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1875 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1876 1877 /* XXX For now, ignore other FG. */ 1878 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1879 return (NULL); 1880 1881 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1882 M_NOWAIT | M_ZERO); 1883 if (devinfo == NULL) { 1884 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1885 __func__); 1886 return (NULL); 1887 } 1888 1889 devinfo->nid = nid; 1890 devinfo->node_type = fctgrptype; 1891 devinfo->codec = codec; 1892 1893 hdac_add_child(sc, devinfo); 1894 1895 return (devinfo); 1896} 1897 1898static void 1899hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1900{ 1901 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1902 device_set_ivars(devinfo->dev, (void *)devinfo); 1903 /* XXX - Print more information when booting verbose??? */ 1904} 1905 1906static void 1907hdac_widget_connection_parse(struct hdac_widget *w) 1908{ 1909 struct hdac_softc *sc = w->devinfo->codec->sc; 1910 uint32_t res; 1911 int i, j, max, ents, entnum; 1912 nid_t cad = w->devinfo->codec->cad; 1913 nid_t nid = w->nid; 1914 nid_t cnid, addcnid, prevcnid; 1915 1916 w->nconns = 0; 1917 1918 res = hdac_command(sc, 1919 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1920 1921 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1922 1923 if (ents < 1) 1924 return; 1925 1926 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1927 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1928 prevcnid = 0; 1929 1930#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1931#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1932#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1933#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1934#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1935 1936 for (i = 0; i < ents; i += entnum) { 1937 res = hdac_command(sc, 1938 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1939 for (j = 0; j < entnum; j++) { 1940 cnid = CONN_CNID(res, entnum, j); 1941 if (cnid == 0) { 1942 if (w->nconns < ents) 1943 device_printf(sc->dev, 1944 "%s: nid=%d WARNING: zero cnid " 1945 "entnum=%d j=%d index=%d " 1946 "entries=%d found=%d res=0x%08x\n", 1947 __func__, nid, entnum, j, i, 1948 ents, w->nconns, res); 1949 else 1950 goto getconns_out; 1951 } 1952 if (cnid < w->devinfo->startnode || 1953 cnid >= w->devinfo->endnode) { 1954 HDA_BOOTVERBOSE( 1955 device_printf(sc->dev, 1956 "%s: GHOST: nid=%d j=%d " 1957 "entnum=%d index=%d res=0x%08x\n", 1958 __func__, nid, j, entnum, i, res); 1959 ); 1960 } 1961 if (CONN_RANGE(res, entnum, j) == 0) 1962 addcnid = cnid; 1963 else if (prevcnid == 0 || prevcnid >= cnid) { 1964 device_printf(sc->dev, 1965 "%s: WARNING: Invalid child range " 1966 "nid=%d index=%d j=%d entnum=%d " 1967 "prevcnid=%d cnid=%d res=0x%08x\n", 1968 __func__, nid, i, j, entnum, prevcnid, 1969 cnid, res); 1970 addcnid = cnid; 1971 } else 1972 addcnid = prevcnid + 1; 1973 while (addcnid <= cnid) { 1974 if (w->nconns > max) { 1975 device_printf(sc->dev, 1976 "%s: nid=%d: Adding %d: " 1977 "Max connection reached! max=%d\n", 1978 __func__, nid, addcnid, max + 1); 1979 goto getconns_out; 1980 } 1981 w->conns[w->nconns++] = addcnid++; 1982 } 1983 prevcnid = cnid; 1984 } 1985 } 1986 1987getconns_out: 1988 HDA_BOOTVERBOSE( 1989 device_printf(sc->dev, 1990 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1991 __func__, nid, ents, w->nconns); 1992 ); 1993 return; 1994} 1995 1996static uint32_t 1997hdac_widget_pin_getconfig(struct hdac_widget *w) 1998{ 1999 struct hdac_softc *sc; 2000 uint32_t config, orig, id; 2001 nid_t cad, nid; 2002 2003 sc = w->devinfo->codec->sc; 2004 cad = w->devinfo->codec->cad; 2005 nid = w->nid; 2006 id = hdac_codec_id(w->devinfo); 2007 2008 config = hdac_command(sc, 2009 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2010 cad); 2011 orig = config; 2012 2013 /* 2014 * XXX REWRITE!!!! Don't argue! 2015 */ 2016 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2017 switch (nid) { 2018 case 26: 2019 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2020 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2021 break; 2022 case 27: 2023 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2024 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2025 break; 2026 default: 2027 break; 2028 } 2029 } else if (id == HDA_CODEC_ALC880 && 2030 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2031 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2032 /* 2033 * Super broken BIOS 2034 */ 2035 switch (nid) { 2036 case 20: 2037 break; 2038 case 21: 2039 break; 2040 case 22: 2041 break; 2042 case 23: 2043 break; 2044 case 24: /* MIC1 */ 2045 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2046 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2047 break; 2048 case 25: /* XXX MIC2 */ 2049 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2050 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2051 break; 2052 case 26: /* LINE1 */ 2053 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2054 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2055 break; 2056 case 27: /* XXX LINE2 */ 2057 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2058 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2059 break; 2060 case 28: /* CD */ 2061 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2062 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2063 break; 2064 case 30: 2065 break; 2066 case 31: 2067 break; 2068 default: 2069 break; 2070 } 2071 } else if (id == HDA_CODEC_ALC883 && 2072 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2073 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2074 switch (nid) { 2075 case 25: 2076 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2077 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2078 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2079 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2080 break; 2081 case 28: 2082 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2083 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2084 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2085 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2086 break; 2087 default: 2088 break; 2089 } 2090 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2091 HP_V3000_SUBVENDOR) { 2092 switch (nid) { 2093 case 18: 2094 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2095 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2096 break; 2097 case 20: 2098 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2099 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2100 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2101 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2102 break; 2103 case 21: 2104 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2105 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2106 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2107 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2108 break; 2109 default: 2110 break; 2111 } 2112 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2113 HP_DV5000_SUBVENDOR) { 2114 switch (nid) { 2115 case 20: 2116 case 21: 2117 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2118 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2119 break; 2120 default: 2121 break; 2122 } 2123 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2124 ASUS_W6F_SUBVENDOR) { 2125 switch (nid) { 2126 case 11: 2127 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2128 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2129 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2130 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2131 break; 2132 case 15: 2133 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2134 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2135 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2136 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2137 break; 2138 default: 2139 break; 2140 } 2141 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2142 UNIWILL_9075_SUBVENDOR) { 2143 switch (nid) { 2144 case 15: 2145 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2146 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2147 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2148 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2149 break; 2150 default: 2151 break; 2152 } 2153 } else if (id == HDA_CODEC_AD1986A && 2154 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2155 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2156 switch (nid) { 2157 case 28: /* LINE */ 2158 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2159 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2160 break; 2161 case 29: /* MIC */ 2162 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2163 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2164 break; 2165 default: 2166 break; 2167 } 2168 } 2169 2170 HDA_BOOTVERBOSE( 2171 if (config != orig) 2172 device_printf(sc->dev, 2173 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2174 nid, orig, config); 2175 ); 2176 2177 return (config); 2178} 2179 2180static uint32_t 2181hdac_widget_pin_getcaps(struct hdac_widget *w) 2182{ 2183 struct hdac_softc *sc; 2184 uint32_t caps, orig, id; 2185 nid_t cad, nid; 2186 2187 sc = w->devinfo->codec->sc; 2188 cad = w->devinfo->codec->cad; 2189 nid = w->nid; 2190 id = hdac_codec_id(w->devinfo); 2191 2192 caps = hdac_command(sc, 2193 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2194 orig = caps; 2195 2196 HDA_BOOTVERBOSE( 2197 if (caps != orig) 2198 device_printf(sc->dev, 2199 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2200 nid, orig, caps); 2201 ); 2202 2203 return (caps); 2204} 2205 2206static void 2207hdac_widget_pin_parse(struct hdac_widget *w) 2208{ 2209 struct hdac_softc *sc = w->devinfo->codec->sc; 2210 uint32_t config, pincap; 2211 char *devstr, *connstr; 2212 nid_t cad = w->devinfo->codec->cad; 2213 nid_t nid = w->nid; 2214 2215 config = hdac_widget_pin_getconfig(w); 2216 w->wclass.pin.config = config; 2217 2218 pincap = hdac_widget_pin_getcaps(w); 2219 w->wclass.pin.cap = pincap; 2220 2221 w->wclass.pin.ctrl = hdac_command(sc, 2222 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2223 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2224 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2225 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2226 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2227 2228 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2229 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2230 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2231 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2232 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2233 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2234 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2235 w->param.eapdbtl = hdac_command(sc, 2236 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2237 w->param.eapdbtl &= 0x7; 2238 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2239 } else 2240 w->param.eapdbtl = HDAC_INVALID; 2241 2242 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2243 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2244 devstr = "line out"; 2245 break; 2246 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2247 devstr = "speaker"; 2248 break; 2249 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2250 devstr = "headphones out"; 2251 break; 2252 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2253 devstr = "CD"; 2254 break; 2255 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2256 devstr = "SPDIF out"; 2257 break; 2258 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2259 devstr = "digital (other) out"; 2260 break; 2261 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2262 devstr = "modem, line side"; 2263 break; 2264 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2265 devstr = "modem, handset side"; 2266 break; 2267 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2268 devstr = "line in"; 2269 break; 2270 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2271 devstr = "AUX"; 2272 break; 2273 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2274 devstr = "Mic in"; 2275 break; 2276 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2277 devstr = "telephony"; 2278 break; 2279 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2280 devstr = "SPDIF in"; 2281 break; 2282 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2283 devstr = "digital (other) in"; 2284 break; 2285 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2286 devstr = "other"; 2287 break; 2288 default: 2289 devstr = "unknown"; 2290 break; 2291 } 2292 2293 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2294 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2295 connstr = "jack"; 2296 break; 2297 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2298 connstr = "none"; 2299 break; 2300 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2301 connstr = "fixed"; 2302 break; 2303 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2304 connstr = "jack / fixed"; 2305 break; 2306 default: 2307 connstr = "unknown"; 2308 break; 2309 } 2310 2311 strlcat(w->name, ": ", sizeof(w->name)); 2312 strlcat(w->name, devstr, sizeof(w->name)); 2313 strlcat(w->name, " (", sizeof(w->name)); 2314 strlcat(w->name, connstr, sizeof(w->name)); 2315 strlcat(w->name, ")", sizeof(w->name)); 2316} 2317 2318static void 2319hdac_widget_parse(struct hdac_widget *w) 2320{ 2321 struct hdac_softc *sc = w->devinfo->codec->sc; 2322 uint32_t wcap, cap; 2323 char *typestr; 2324 nid_t cad = w->devinfo->codec->cad; 2325 nid_t nid = w->nid; 2326 2327 wcap = hdac_command(sc, 2328 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2329 cad); 2330 w->param.widget_cap = wcap; 2331 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2332 2333 switch (w->type) { 2334 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2335 typestr = "audio output"; 2336 break; 2337 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2338 typestr = "audio input"; 2339 break; 2340 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2341 typestr = "audio mixer"; 2342 break; 2343 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2344 typestr = "audio selector"; 2345 break; 2346 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2347 typestr = "pin"; 2348 break; 2349 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2350 typestr = "power widget"; 2351 break; 2352 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2353 typestr = "volume widget"; 2354 break; 2355 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2356 typestr = "beep widget"; 2357 break; 2358 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2359 typestr = "vendor widget"; 2360 break; 2361 default: 2362 typestr = "unknown type"; 2363 break; 2364 } 2365 2366 strlcpy(w->name, typestr, sizeof(w->name)); 2367 2368 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2369 hdac_command(sc, 2370 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2371 cad); 2372 DELAY(1000); 2373 } 2374 2375 hdac_widget_connection_parse(w); 2376 2377 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2378 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2379 w->param.outamp_cap = 2380 hdac_command(sc, 2381 HDA_CMD_GET_PARAMETER(cad, nid, 2382 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2383 else 2384 w->param.outamp_cap = 2385 w->devinfo->function.audio.outamp_cap; 2386 } else 2387 w->param.outamp_cap = 0; 2388 2389 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2390 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2391 w->param.inamp_cap = 2392 hdac_command(sc, 2393 HDA_CMD_GET_PARAMETER(cad, nid, 2394 HDA_PARAM_INPUT_AMP_CAP), cad); 2395 else 2396 w->param.inamp_cap = 2397 w->devinfo->function.audio.inamp_cap; 2398 } else 2399 w->param.inamp_cap = 0; 2400 2401 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2402 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2403 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2404 cap = hdac_command(sc, 2405 HDA_CMD_GET_PARAMETER(cad, nid, 2406 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2407 w->param.supp_stream_formats = (cap != 0) ? cap : 2408 w->devinfo->function.audio.supp_stream_formats; 2409 cap = hdac_command(sc, 2410 HDA_CMD_GET_PARAMETER(cad, nid, 2411 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2412 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2413 w->devinfo->function.audio.supp_pcm_size_rate; 2414 } else { 2415 w->param.supp_stream_formats = 2416 w->devinfo->function.audio.supp_stream_formats; 2417 w->param.supp_pcm_size_rate = 2418 w->devinfo->function.audio.supp_pcm_size_rate; 2419 } 2420 } else { 2421 w->param.supp_stream_formats = 0; 2422 w->param.supp_pcm_size_rate = 0; 2423 } 2424 2425 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2426 hdac_widget_pin_parse(w); 2427} 2428 2429static struct hdac_widget * 2430hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2431{ 2432 if (devinfo == NULL || devinfo->widget == NULL || 2433 nid < devinfo->startnode || nid >= devinfo->endnode) 2434 return (NULL); 2435 return (&devinfo->widget[nid - devinfo->startnode]); 2436} 2437 2438static __inline int 2439hda_poll_channel(struct hdac_chan *ch) 2440{ 2441 uint32_t sz, delta; 2442 volatile uint32_t ptr; 2443 2444 if (!(ch->flags & HDAC_CHN_RUNNING)) 2445 return (0); 2446 2447 sz = ch->blksz * ch->blkcnt; 2448 if (ch->dmapos != NULL) 2449 ptr = *(ch->dmapos); 2450 else 2451 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2452 ch->off + HDAC_SDLPIB); 2453 ch->ptr = ptr; 2454 ptr %= sz; 2455 ptr &= ~(ch->blksz - 1); 2456 delta = (sz + ptr - ch->prevptr) % sz; 2457 2458 if (delta < ch->blksz) 2459 return (0); 2460 2461 ch->prevptr = ptr; 2462 2463 return (1); 2464} 2465 2466#define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2467 HDAC_CHN_RUNNING) 2468 2469static void 2470hda_poll_callback(void *arg) 2471{ 2472 struct hdac_softc *sc = arg; 2473 uint32_t trigger; 2474 2475 if (sc == NULL) 2476 return; 2477 2478 hdac_lock(sc); 2479 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2480 hdac_unlock(sc); 2481 return; 2482 } 2483 2484 trigger = 0; 2485 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2486 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2487 2488 /* XXX */ 2489 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2490 hda_poll_callback, sc); 2491 2492 hdac_unlock(sc); 2493 2494 if (trigger & HDAC_TRIGGER_PLAY) 2495 chn_intr(sc->play.c); 2496 if (trigger & HDAC_TRIGGER_REC) 2497 chn_intr(sc->rec.c); 2498} 2499 2500static int 2501hdac_rirb_flush(struct hdac_softc *sc) 2502{ 2503 struct hdac_rirb *rirb_base, *rirb; 2504 struct hdac_codec *codec; 2505 struct hdac_command_list *commands; 2506 nid_t cad; 2507 uint32_t resp; 2508 uint8_t rirbwp; 2509 int ret; 2510 2511 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2512 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2513#if 0 2514 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2515 BUS_DMASYNC_POSTREAD); 2516#endif 2517 2518 ret = 0; 2519 2520 while (sc->rirb_rp != rirbwp) { 2521 sc->rirb_rp++; 2522 sc->rirb_rp %= sc->rirb_size; 2523 rirb = &rirb_base[sc->rirb_rp]; 2524 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2525 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2526 sc->codecs[cad] == NULL) 2527 continue; 2528 resp = rirb->response; 2529 codec = sc->codecs[cad]; 2530 commands = codec->commands; 2531 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2532 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2533 ((resp >> 26) & 0xffff); 2534 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2535 } else if (commands != NULL && commands->num_commands > 0 && 2536 codec->responses_received < commands->num_commands) 2537 commands->responses[codec->responses_received++] = 2538 resp; 2539 ret++; 2540 } 2541 2542 return (ret); 2543} 2544 2545static int 2546hdac_unsolq_flush(struct hdac_softc *sc) 2547{ 2548 nid_t cad; 2549 uint32_t tag; 2550 int ret = 0; 2551 2552 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2553 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2554 while (sc->unsolq_rp != sc->unsolq_wp) { 2555 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2556 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2557 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2558 hdac_unsolicited_handler(sc->codecs[cad], tag); 2559 ret++; 2560 } 2561 sc->unsolq_st = HDAC_UNSOLQ_READY; 2562 } 2563 2564 return (ret); 2565} 2566 2567static void 2568hdac_poll_callback(void *arg) 2569{ 2570 struct hdac_softc *sc = arg; 2571 if (sc == NULL) 2572 return; 2573 2574 hdac_lock(sc); 2575 if (sc->polling == 0 || sc->poll_ival == 0) { 2576 hdac_unlock(sc); 2577 return; 2578 } 2579 if (hdac_rirb_flush(sc) != 0) 2580 hdac_unsolq_flush(sc); 2581 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2582 hdac_unlock(sc); 2583} 2584 2585static void 2586hdac_stream_stop(struct hdac_chan *ch) 2587{ 2588 struct hdac_softc *sc = ch->devinfo->codec->sc; 2589 uint32_t ctl; 2590 2591 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2592 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2593 HDAC_SDCTL_RUN); 2594 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2595 2596 ch->flags &= ~HDAC_CHN_RUNNING; 2597 2598 if (sc->polling != 0) { 2599 int pollticks; 2600 2601 if (hda_chan_active(sc) == 0) { 2602 callout_stop(&sc->poll_hda); 2603 sc->poll_ticks = 1; 2604 } else { 2605 if (sc->play.flags & HDAC_CHN_RUNNING) 2606 ch = &sc->play; 2607 else 2608 ch = &sc->rec; 2609 pollticks = ((uint64_t)hz * ch->blksz) / 2610 ((uint64_t)sndbuf_getbps(ch->b) * 2611 sndbuf_getspd(ch->b)); 2612 pollticks >>= 2; 2613 if (pollticks > hz) 2614 pollticks = hz; 2615 if (pollticks < 1) { 2616 HDA_BOOTVERBOSE( 2617 device_printf(sc->dev, 2618 "%s: pollticks=%d < 1 !\n", 2619 __func__, pollticks); 2620 ); 2621 pollticks = 1; 2622 } 2623 if (pollticks > sc->poll_ticks) { 2624 HDA_BOOTVERBOSE( 2625 device_printf(sc->dev, 2626 "%s: pollticks %d -> %d\n", 2627 __func__, sc->poll_ticks, 2628 pollticks); 2629 ); 2630 sc->poll_ticks = pollticks; 2631 callout_reset(&sc->poll_hda, 1, 2632 hda_poll_callback, sc); 2633 } 2634 } 2635 } else { 2636 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2637 ctl &= ~(1 << (ch->off >> 5)); 2638 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2639 } 2640} 2641 2642static void 2643hdac_stream_start(struct hdac_chan *ch) 2644{ 2645 struct hdac_softc *sc = ch->devinfo->codec->sc; 2646 uint32_t ctl; 2647 2648 if (sc->polling != 0) { 2649 int pollticks; 2650 2651 pollticks = ((uint64_t)hz * ch->blksz) / 2652 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2653 pollticks >>= 2; 2654 if (pollticks > hz) 2655 pollticks = hz; 2656 if (pollticks < 1) { 2657 HDA_BOOTVERBOSE( 2658 device_printf(sc->dev, 2659 "%s: pollticks=%d < 1 !\n", 2660 __func__, pollticks); 2661 ); 2662 pollticks = 1; 2663 } 2664 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2665 HDA_BOOTVERBOSE( 2666 if (hda_chan_active(sc) == 0) { 2667 device_printf(sc->dev, 2668 "%s: pollticks=%d\n", 2669 __func__, pollticks); 2670 } else { 2671 device_printf(sc->dev, 2672 "%s: pollticks %d -> %d\n", 2673 __func__, sc->poll_ticks, 2674 pollticks); 2675 } 2676 ); 2677 sc->poll_ticks = pollticks; 2678 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2679 sc); 2680 } 2681 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2682 ctl |= HDAC_SDCTL_RUN; 2683 } else { 2684 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2685 ctl |= 1 << (ch->off >> 5); 2686 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2687 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2688 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2689 HDAC_SDCTL_RUN; 2690 } 2691 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2692 2693 ch->flags |= HDAC_CHN_RUNNING; 2694} 2695 2696static void 2697hdac_stream_reset(struct hdac_chan *ch) 2698{ 2699 struct hdac_softc *sc = ch->devinfo->codec->sc; 2700 int timeout = 1000; 2701 int to = timeout; 2702 uint32_t ctl; 2703 2704 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2705 ctl |= HDAC_SDCTL_SRST; 2706 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2707 do { 2708 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2709 if (ctl & HDAC_SDCTL_SRST) 2710 break; 2711 DELAY(10); 2712 } while (--to); 2713 if (!(ctl & HDAC_SDCTL_SRST)) { 2714 device_printf(sc->dev, "timeout in reset\n"); 2715 } 2716 ctl &= ~HDAC_SDCTL_SRST; 2717 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2718 to = timeout; 2719 do { 2720 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2721 if (!(ctl & HDAC_SDCTL_SRST)) 2722 break; 2723 DELAY(10); 2724 } while (--to); 2725 if (ctl & HDAC_SDCTL_SRST) 2726 device_printf(sc->dev, "can't reset!\n"); 2727} 2728 2729static void 2730hdac_stream_setid(struct hdac_chan *ch) 2731{ 2732 struct hdac_softc *sc = ch->devinfo->codec->sc; 2733 uint32_t ctl; 2734 2735 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2736 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2737 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2738 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2739} 2740 2741static void 2742hdac_bdl_setup(struct hdac_chan *ch) 2743{ 2744 struct hdac_softc *sc = ch->devinfo->codec->sc; 2745 struct hdac_bdle *bdle; 2746 uint64_t addr; 2747 uint32_t blksz, blkcnt; 2748 int i; 2749 2750 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2751 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2752 2753 if (sc->polling != 0) { 2754 blksz = ch->blksz * ch->blkcnt; 2755 blkcnt = 1; 2756 } else { 2757 blksz = ch->blksz; 2758 blkcnt = ch->blkcnt; 2759 } 2760 2761 for (i = 0; i < blkcnt; i++, bdle++) { 2762 bdle->addrl = (uint32_t)addr; 2763 bdle->addrh = (uint32_t)(addr >> 32); 2764 bdle->len = blksz; 2765 bdle->ioc = 1 ^ sc->polling; 2766 addr += blksz; 2767 } 2768 2769 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2770 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2771 addr = ch->bdl_dma.dma_paddr; 2772 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2773 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2774 if (ch->dmapos != NULL && 2775 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2776 addr = sc->pos_dma.dma_paddr; 2777 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2778 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2779 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2780 } 2781} 2782 2783static int 2784hdac_bdl_alloc(struct hdac_chan *ch) 2785{ 2786 struct hdac_softc *sc = ch->devinfo->codec->sc; 2787 int rc; 2788 2789 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2790 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2791 if (rc) { 2792 device_printf(sc->dev, "can't alloc bdl\n"); 2793 return (rc); 2794 } 2795 2796 return (0); 2797} 2798 2799static void 2800hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2801 int index, int lmute, int rmute, 2802 int left, int right, int dir) 2803{ 2804 uint16_t v = 0; 2805 2806 if (sc == NULL) 2807 return; 2808 2809 if (left != right || lmute != rmute) { 2810 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2811 (lmute << 7) | left; 2812 hdac_command(sc, 2813 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2814 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2815 (rmute << 7) | right; 2816 } else 2817 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2818 (lmute << 7) | left; 2819 2820 hdac_command(sc, 2821 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2822} 2823 2824static void 2825hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2826 int left, int right) 2827{ 2828 struct hdac_softc *sc; 2829 nid_t nid, cad; 2830 int lmute, rmute; 2831 2832 if (ctl == NULL || ctl->widget == NULL || 2833 ctl->widget->devinfo == NULL || 2834 ctl->widget->devinfo->codec == NULL || 2835 ctl->widget->devinfo->codec->sc == NULL) 2836 return; 2837 2838 sc = ctl->widget->devinfo->codec->sc; 2839 cad = ctl->widget->devinfo->codec->cad; 2840 nid = ctl->widget->nid; 2841 2842 if (mute == HDA_AMP_MUTE_DEFAULT) { 2843 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2844 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2845 } else { 2846 lmute = HDA_AMP_LEFT_MUTED(mute); 2847 rmute = HDA_AMP_RIGHT_MUTED(mute); 2848 } 2849 2850 if (ctl->dir & HDA_CTL_OUT) 2851 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2852 lmute, rmute, left, right, 0); 2853 if (ctl->dir & HDA_CTL_IN) 2854 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2855 lmute, rmute, left, right, 1); 2856 ctl->left = left; 2857 ctl->right = right; 2858} 2859 2860static void 2861hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2862{ 2863 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2864 return; 2865 hdac_command(w->devinfo->codec->sc, 2866 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2867 w->nid, index), w->devinfo->codec->cad); 2868 w->selconn = index; 2869} 2870 2871 2872/**************************************************************************** 2873 * uint32_t hdac_command_sendone_internal 2874 * 2875 * Wrapper function that sends only one command to a given codec 2876 ****************************************************************************/ 2877static uint32_t 2878hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2879{ 2880 struct hdac_command_list cl; 2881 uint32_t response = HDAC_INVALID; 2882 2883 if (!hdac_lockowned(sc)) 2884 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2885 cl.num_commands = 1; 2886 cl.verbs = &verb; 2887 cl.responses = &response; 2888 2889 hdac_command_send_internal(sc, &cl, cad); 2890 2891 return (response); 2892} 2893 2894/**************************************************************************** 2895 * hdac_command_send_internal 2896 * 2897 * Send a command list to the codec via the corb. We queue as much verbs as 2898 * we can and msleep on the codec. When the interrupt get the responses 2899 * back from the rirb, it will wake us up so we can queue the remaining verbs 2900 * if any. 2901 ****************************************************************************/ 2902static void 2903hdac_command_send_internal(struct hdac_softc *sc, 2904 struct hdac_command_list *commands, nid_t cad) 2905{ 2906 struct hdac_codec *codec; 2907 int corbrp; 2908 uint32_t *corb; 2909 int timeout; 2910 int retry = 10; 2911 struct hdac_rirb *rirb_base; 2912 2913 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2914 commands->num_commands < 1) 2915 return; 2916 2917 codec = sc->codecs[cad]; 2918 codec->commands = commands; 2919 codec->responses_received = 0; 2920 codec->verbs_sent = 0; 2921 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2922 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2923 2924 do { 2925 if (codec->verbs_sent != commands->num_commands) { 2926 /* Queue as many verbs as possible */ 2927 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2928#if 0 2929 bus_dmamap_sync(sc->corb_dma.dma_tag, 2930 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2931#endif 2932 while (codec->verbs_sent != commands->num_commands && 2933 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2934 sc->corb_wp++; 2935 sc->corb_wp %= sc->corb_size; 2936 corb[sc->corb_wp] = 2937 commands->verbs[codec->verbs_sent++]; 2938 } 2939 2940 /* Send the verbs to the codecs */ 2941#if 0 2942 bus_dmamap_sync(sc->corb_dma.dma_tag, 2943 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2944#endif 2945 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2946 } 2947 2948 timeout = 1000; 2949 while (hdac_rirb_flush(sc) == 0 && --timeout) 2950 DELAY(10); 2951 } while ((codec->verbs_sent != commands->num_commands || 2952 codec->responses_received != commands->num_commands) && --retry); 2953 2954 if (retry == 0) 2955 device_printf(sc->dev, 2956 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2957 __func__, commands->num_commands, codec->verbs_sent, 2958 codec->responses_received); 2959 2960 codec->commands = NULL; 2961 codec->responses_received = 0; 2962 codec->verbs_sent = 0; 2963 2964 hdac_unsolq_flush(sc); 2965} 2966 2967 2968/**************************************************************************** 2969 * Device Methods 2970 ****************************************************************************/ 2971 2972/**************************************************************************** 2973 * int hdac_probe(device_t) 2974 * 2975 * Probe for the presence of an hdac. If none is found, check for a generic 2976 * match using the subclass of the device. 2977 ****************************************************************************/ 2978static int 2979hdac_probe(device_t dev) 2980{ 2981 int i, result; 2982 uint32_t model; 2983 uint16_t class, subclass; 2984 char desc[64]; 2985 2986 model = (uint32_t)pci_get_device(dev) << 16; 2987 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2988 class = pci_get_class(dev); 2989 subclass = pci_get_subclass(dev); 2990 2991 bzero(desc, sizeof(desc)); 2992 result = ENXIO; 2993 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2994 if (hdac_devices[i].model == model) { 2995 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2996 result = BUS_PROBE_DEFAULT; 2997 break; 2998 } 2999 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3000 class == PCIC_MULTIMEDIA && 3001 subclass == PCIS_MULTIMEDIA_HDA) { 3002 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3003 result = BUS_PROBE_GENERIC; 3004 break; 3005 } 3006 } 3007 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3008 subclass == PCIS_MULTIMEDIA_HDA) { 3009 strlcpy(desc, "Generic", sizeof(desc)); 3010 result = BUS_PROBE_GENERIC; 3011 } 3012 if (result != ENXIO) { 3013 strlcat(desc, " High Definition Audio Controller", 3014 sizeof(desc)); 3015 device_set_desc_copy(dev, desc); 3016 } 3017 3018 return (result); 3019} 3020 3021static void * 3022hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3023 struct pcm_channel *c, int dir) 3024{ 3025 struct hdac_devinfo *devinfo = data; 3026 struct hdac_softc *sc = devinfo->codec->sc; 3027 struct hdac_chan *ch; 3028 3029 hdac_lock(sc); 3030 if (dir == PCMDIR_PLAY) { 3031 ch = &sc->play; 3032 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3033 devinfo->function.audio.playcnt++; 3034 } else { 3035 ch = &sc->rec; 3036 ch->off = devinfo->function.audio.reccnt << 5; 3037 devinfo->function.audio.reccnt++; 3038 } 3039 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3040 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3041 ch->pcmrates[0] = 48000; 3042 ch->pcmrates[1] = 0; 3043 } 3044 if (sc->pos_dma.dma_vaddr != NULL) 3045 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3046 (sc->streamcnt * 8)); 3047 else 3048 ch->dmapos = NULL; 3049 ch->sid = ++sc->streamcnt; 3050 ch->dir = dir; 3051 ch->b = b; 3052 ch->c = c; 3053 ch->devinfo = devinfo; 3054 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3055 ch->blkcnt = sc->chan_blkcnt; 3056 hdac_unlock(sc); 3057 3058 if (hdac_bdl_alloc(ch) != 0) { 3059 ch->blkcnt = 0; 3060 return (NULL); 3061 } 3062 3063 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3064 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3065 sc->chan_size) != 0) 3066 return (NULL); 3067 3068 return (ch); 3069} 3070 3071static int 3072hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3073{ 3074 struct hdac_chan *ch = data; 3075 int i; 3076 3077 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3078 if (format == ch->caps.fmtlist[i]) { 3079 ch->fmt = format; 3080 return (0); 3081 } 3082 } 3083 3084 return (EINVAL); 3085} 3086 3087static int 3088hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3089{ 3090 struct hdac_chan *ch = data; 3091 uint32_t spd = 0, threshold; 3092 int i; 3093 3094 for (i = 0; ch->pcmrates[i] != 0; i++) { 3095 spd = ch->pcmrates[i]; 3096 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3097 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3098 if (speed < threshold) 3099 break; 3100 } 3101 3102 if (spd == 0) /* impossible */ 3103 ch->spd = 48000; 3104 else 3105 ch->spd = spd; 3106 3107 return (ch->spd); 3108} 3109 3110static void 3111hdac_stream_setup(struct hdac_chan *ch) 3112{ 3113 struct hdac_softc *sc = ch->devinfo->codec->sc; 3114 struct hdac_widget *w; 3115 int i, chn, totalchn; 3116 nid_t cad = ch->devinfo->codec->cad; 3117 uint16_t fmt; 3118 3119 fmt = 0; 3120 if (ch->fmt & AFMT_S16_LE) 3121 fmt |= ch->bit16 << 4; 3122 else if (ch->fmt & AFMT_S32_LE) 3123 fmt |= ch->bit32 << 4; 3124 else 3125 fmt |= 1 << 4; 3126 3127 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3128 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3129 fmt |= hda_rate_tab[i].base; 3130 fmt |= hda_rate_tab[i].mul; 3131 fmt |= hda_rate_tab[i].div; 3132 break; 3133 } 3134 } 3135 3136 if (ch->fmt & AFMT_STEREO) { 3137 fmt |= 1; 3138 totalchn = 2; 3139 } else 3140 totalchn = 1; 3141 3142 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3143 3144 chn = 0; 3145 for (i = 0; ch->io[i] != -1; i++) { 3146 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3147 if (w == NULL) 3148 continue; 3149 HDA_BOOTVERBOSE( 3150 device_printf(sc->dev, 3151 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3152 "fmt=0x%08x\n", 3153 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3154 ch->io[i], fmt); 3155 ); 3156 hdac_command(sc, 3157 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3158 if (ch->dir == PCMDIR_REC) 3159 hdac_command(sc, 3160 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3161 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), 3162 cad); 3163 else 3164 hdac_command(sc, 3165 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3166 ch->sid << 4), cad); 3167 chn += 3168 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3169 2 : 1; 3170 } 3171} 3172 3173static int 3174hdac_channel_setfragments(kobj_t obj, void *data, 3175 uint32_t blksz, uint32_t blkcnt) 3176{ 3177 struct hdac_chan *ch = data; 3178 struct hdac_softc *sc = ch->devinfo->codec->sc; 3179 3180 blksz &= HDA_BLK_ALIGN; 3181 3182 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3183 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3184 if (blksz < HDA_BLK_MIN) 3185 blksz = HDA_BLK_MIN; 3186 if (blkcnt > HDA_BDL_MAX) 3187 blkcnt = HDA_BDL_MAX; 3188 if (blkcnt < HDA_BDL_MIN) 3189 blkcnt = HDA_BDL_MIN; 3190 3191 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3192 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3193 blkcnt >>= 1; 3194 else if ((blksz >> 1) >= HDA_BLK_MIN) 3195 blksz >>= 1; 3196 else 3197 break; 3198 } 3199 3200 if ((sndbuf_getblksz(ch->b) != blksz || 3201 sndbuf_getblkcnt(ch->b) != blkcnt) && 3202 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3203 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3204 __func__, blksz, blkcnt); 3205 3206 ch->blksz = sndbuf_getblksz(ch->b); 3207 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3208 3209 return (1); 3210} 3211 3212static int 3213hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3214{ 3215 struct hdac_chan *ch = data; 3216 struct hdac_softc *sc = ch->devinfo->codec->sc; 3217 3218 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3219 3220 return (ch->blksz); 3221} 3222 3223static void 3224hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3225{ 3226 struct hdac_devinfo *devinfo = ch->devinfo; 3227 nid_t cad = devinfo->codec->cad; 3228 int i; 3229 3230 hdac_stream_stop(ch); 3231 3232 for (i = 0; ch->io[i] != -1; i++) { 3233 hdac_command(sc, 3234 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3235 0), cad); 3236 } 3237} 3238 3239static void 3240hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3241{ 3242 ch->ptr = 0; 3243 ch->prevptr = 0; 3244 hdac_stream_stop(ch); 3245 hdac_stream_reset(ch); 3246 hdac_bdl_setup(ch); 3247 hdac_stream_setid(ch); 3248 hdac_stream_setup(ch); 3249 hdac_stream_start(ch); 3250} 3251 3252static int 3253hdac_channel_trigger(kobj_t obj, void *data, int go) 3254{ 3255 struct hdac_chan *ch = data; 3256 struct hdac_softc *sc = ch->devinfo->codec->sc; 3257 3258 if (!PCMTRIG_COMMON(go)) 3259 return (0); 3260 3261 hdac_lock(sc); 3262 switch (go) { 3263 case PCMTRIG_START: 3264 hdac_channel_start(sc, ch); 3265 break; 3266 case PCMTRIG_STOP: 3267 case PCMTRIG_ABORT: 3268 hdac_channel_stop(sc, ch); 3269 break; 3270 default: 3271 break; 3272 } 3273 hdac_unlock(sc); 3274 3275 return (0); 3276} 3277 3278static int 3279hdac_channel_getptr(kobj_t obj, void *data) 3280{ 3281 struct hdac_chan *ch = data; 3282 struct hdac_softc *sc = ch->devinfo->codec->sc; 3283 uint32_t ptr; 3284 3285 hdac_lock(sc); 3286 if (sc->polling != 0) 3287 ptr = ch->ptr; 3288 else if (ch->dmapos != NULL) 3289 ptr = *(ch->dmapos); 3290 else 3291 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3292 hdac_unlock(sc); 3293 3294 /* 3295 * Round to available space and force 128 bytes aligment. 3296 */ 3297 ptr %= ch->blksz * ch->blkcnt; 3298 ptr &= HDA_BLK_ALIGN; 3299 3300 return (ptr); 3301} 3302 3303static struct pcmchan_caps * 3304hdac_channel_getcaps(kobj_t obj, void *data) 3305{ 3306 return (&((struct hdac_chan *)data)->caps); 3307} 3308 3309static kobj_method_t hdac_channel_methods[] = { 3310 KOBJMETHOD(channel_init, hdac_channel_init), 3311 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3312 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3313 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3314 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3315 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3316 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3317 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3318 { 0, 0 } 3319}; 3320CHANNEL_DECLARE(hdac_channel); 3321 3322static void 3323hdac_jack_poll_callback(void *arg) 3324{ 3325 struct hdac_devinfo *devinfo = arg; 3326 struct hdac_softc *sc; 3327 3328 if (devinfo == NULL || devinfo->codec == NULL || 3329 devinfo->codec->sc == NULL) 3330 return; 3331 sc = devinfo->codec->sc; 3332 hdac_lock(sc); 3333 if (sc->poll_ival == 0) { 3334 hdac_unlock(sc); 3335 return; 3336 } 3337 hdac_hp_switch_handler(devinfo); 3338 callout_reset(&sc->poll_jack, sc->poll_ival, 3339 hdac_jack_poll_callback, devinfo); 3340 hdac_unlock(sc); 3341} 3342 3343static int 3344hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3345{ 3346 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3347 struct hdac_softc *sc = devinfo->codec->sc; 3348 struct hdac_widget *w, *cw; 3349 struct hdac_audio_ctl *ctl; 3350 uint32_t mask, recmask, id; 3351 int i, j, softpcmvol; 3352 nid_t cad; 3353 3354 hdac_lock(sc); 3355 3356 mask = 0; 3357 recmask = 0; 3358 3359 id = hdac_codec_id(devinfo); 3360 cad = devinfo->codec->cad; 3361 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3362 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3363 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3364 continue; 3365 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3366 if (w == NULL || w->enable == 0 || w->type != 3367 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3368 continue; 3369 if (hdac_hp_switch[i].polling != 0) 3370 callout_reset(&sc->poll_jack, 1, 3371 hdac_jack_poll_callback, devinfo); 3372 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3373 hdac_command(sc, 3374 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3375 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3376 HDAC_UNSOLTAG_EVENT_HP), cad); 3377 else 3378 continue; 3379 hdac_hp_switch_handler(devinfo); 3380 HDA_BOOTVERBOSE( 3381 device_printf(sc->dev, 3382 "HDA_DEBUG: Enabling headphone/speaker " 3383 "audio routing switching:\n"); 3384 device_printf(sc->dev, 3385 "HDA_DEBUG: \tindex=%d nid=%d " 3386 "pci_subvendor=0x%08x " 3387 "codec=0x%08x [%s]\n", 3388 i, w->nid, sc->pci_subvendor, id, 3389 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3390 "UNSOL"); 3391 ); 3392 break; 3393 } 3394 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3395 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3396 sc->pci_subvendor) && 3397 hdac_eapd_switch[i].id == id)) 3398 continue; 3399 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3400 if (w == NULL || w->enable == 0) 3401 break; 3402 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3403 w->param.eapdbtl == HDAC_INVALID) 3404 break; 3405 mask |= SOUND_MASK_OGAIN; 3406 break; 3407 } 3408 3409 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3410 w = hdac_widget_get(devinfo, i); 3411 if (w == NULL || w->enable == 0) 3412 continue; 3413 mask |= w->ctlflags; 3414 if (!(w->pflags & HDA_ADC_RECSEL)) 3415 continue; 3416 for (j = 0; j < w->nconns; j++) { 3417 cw = hdac_widget_get(devinfo, w->conns[j]); 3418 if (cw == NULL || cw->enable == 0) 3419 continue; 3420 recmask |= cw->ctlflags; 3421 } 3422 } 3423 3424 if (!(mask & SOUND_MASK_PCM)) { 3425 softpcmvol = 1; 3426 mask |= SOUND_MASK_PCM; 3427 } else 3428 softpcmvol = (devinfo->function.audio.quirks & 3429 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3430 3431 i = 0; 3432 ctl = NULL; 3433 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3434 if (ctl->widget == NULL || ctl->enable == 0) 3435 continue; 3436 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3437 continue; 3438 if (ctl->step > 0) 3439 break; 3440 } 3441 3442 if (softpcmvol == 1 || ctl == NULL) { 3443 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3444 HDA_BOOTVERBOSE( 3445 device_printf(sc->dev, 3446 "HDA_DEBUG: %s Soft PCM volume\n", 3447 (softpcmvol == 1) ? 3448 "Forcing" : "Enabling"); 3449 ); 3450 i = 0; 3451 /* 3452 * XXX Temporary quirk for STAC9220, until the parser 3453 * become smarter. 3454 */ 3455 if (id == HDA_CODEC_STAC9220) { 3456 mask |= SOUND_MASK_VOLUME; 3457 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3458 NULL) { 3459 if (ctl->widget == NULL || ctl->enable == 0) 3460 continue; 3461 if (ctl->widget->nid == 11 && ctl->index == 0) { 3462 ctl->ossmask = SOUND_MASK_VOLUME; 3463 ctl->ossval = 100 | (100 << 8); 3464 } else 3465 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3466 } 3467 } else if (id == HDA_CODEC_STAC9221) { 3468 mask |= SOUND_MASK_VOLUME; 3469 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3470 NULL) { 3471 if (ctl->widget == NULL) 3472 continue; 3473 if (ctl->widget->type == 3474 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3475 ctl->index == 0 && (ctl->widget->nid == 2 || 3476 ctl->widget->enable != 0)) { 3477 ctl->enable = 1; 3478 ctl->ossmask = SOUND_MASK_VOLUME; 3479 ctl->ossval = 100 | (100 << 8); 3480 } else if (ctl->enable == 0) 3481 continue; 3482 else 3483 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3484 } 3485 } else { 3486 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3487 SOUND_MASK_PCM); 3488 if (!(mask & SOUND_MASK_VOLUME)) 3489 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3490 SOUND_MIXER_NONE); 3491 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3492 NULL) { 3493 if (ctl->widget == NULL || ctl->enable == 0) 3494 continue; 3495 if (!HDA_FLAG_MATCH(ctl->ossmask, 3496 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3497 continue; 3498 if (!(ctl->mute == 1 && ctl->step == 0)) 3499 ctl->enable = 0; 3500 } 3501 } 3502 } 3503 3504 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3505 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3506 SOUND_MASK_OGAIN); 3507 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3508 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3509 3510 mix_setrecdevs(m, recmask); 3511 mix_setdevs(m, mask); 3512 3513 hdac_unlock(sc); 3514 3515 return (0); 3516} 3517 3518static int 3519hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3520 unsigned left, unsigned right) 3521{ 3522 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3523 struct hdac_softc *sc = devinfo->codec->sc; 3524 struct hdac_widget *w; 3525 struct hdac_audio_ctl *ctl; 3526 uint32_t id, mute; 3527 int lvol, rvol, mlvol, mrvol; 3528 int i = 0; 3529 3530 hdac_lock(sc); 3531 if (dev == SOUND_MIXER_OGAIN) { 3532 uint32_t orig; 3533 /*if (left != right || !(left == 0 || left == 1)) { 3534 hdac_unlock(sc); 3535 return (-1); 3536 }*/ 3537 id = hdac_codec_id(devinfo); 3538 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3539 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3540 sc->pci_subvendor) && 3541 hdac_eapd_switch[i].id == id) 3542 break; 3543 } 3544 if (i >= HDAC_EAPD_SWITCH_LEN) { 3545 hdac_unlock(sc); 3546 return (-1); 3547 } 3548 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3549 if (w == NULL || 3550 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3551 w->param.eapdbtl == HDAC_INVALID) { 3552 hdac_unlock(sc); 3553 return (-1); 3554 } 3555 orig = w->param.eapdbtl; 3556 if (left == 0) 3557 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3558 else 3559 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3560 if (orig != w->param.eapdbtl) { 3561 uint32_t val; 3562 3563 if (hdac_eapd_switch[i].hp_switch != 0) 3564 hdac_hp_switch_handler(devinfo); 3565 val = w->param.eapdbtl; 3566 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3567 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3568 hdac_command(sc, 3569 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3570 w->nid, val), devinfo->codec->cad); 3571 } 3572 hdac_unlock(sc); 3573 return (left | (left << 8)); 3574 } 3575 if (dev == SOUND_MIXER_VOLUME) 3576 devinfo->function.audio.mvol = left | (right << 8); 3577 3578 mlvol = devinfo->function.audio.mvol & 0x7f; 3579 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3580 lvol = 0; 3581 rvol = 0; 3582 3583 i = 0; 3584 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3585 if (ctl->widget == NULL || ctl->enable == 0 || 3586 !(ctl->ossmask & (1 << dev))) 3587 continue; 3588 switch (dev) { 3589 case SOUND_MIXER_VOLUME: 3590 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3591 lvol = (lvol * ctl->step) / 100; 3592 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3593 rvol = (rvol * ctl->step) / 100; 3594 break; 3595 default: 3596 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3597 lvol = (left * mlvol) / 100; 3598 lvol = (lvol * ctl->step) / 100; 3599 rvol = (right * mrvol) / 100; 3600 rvol = (rvol * ctl->step) / 100; 3601 } else { 3602 lvol = (left * ctl->step) / 100; 3603 rvol = (right * ctl->step) / 100; 3604 } 3605 ctl->ossval = left | (right << 8); 3606 break; 3607 } 3608 mute = 0; 3609 if (ctl->step < 1) { 3610 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3611 (ctl->muted & HDA_AMP_MUTE_LEFT); 3612 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3613 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3614 } else { 3615 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3616 (ctl->muted & HDA_AMP_MUTE_LEFT); 3617 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3618 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3619 } 3620 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3621 } 3622 hdac_unlock(sc); 3623 3624 return (left | (right << 8)); 3625} 3626 3627static int 3628hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3629{ 3630 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3631 struct hdac_widget *w, *cw; 3632 struct hdac_softc *sc = devinfo->codec->sc; 3633 uint32_t ret = src, target; 3634 int i, j; 3635 3636 target = 0; 3637 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3638 if (src & (1 << i)) { 3639 target = 1 << i; 3640 break; 3641 } 3642 } 3643 3644 hdac_lock(sc); 3645 3646 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3647 w = hdac_widget_get(devinfo, i); 3648 if (w == NULL || w->enable == 0) 3649 continue; 3650 if (!(w->pflags & HDA_ADC_RECSEL)) 3651 continue; 3652 for (j = 0; j < w->nconns; j++) { 3653 cw = hdac_widget_get(devinfo, w->conns[j]); 3654 if (cw == NULL || cw->enable == 0) 3655 continue; 3656 if ((target == SOUND_MASK_VOLUME && 3657 cw->type != 3658 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3659 (target != SOUND_MASK_VOLUME && 3660 cw->type == 3661 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3662 continue; 3663 if (cw->ctlflags & target) { 3664 if (!(w->pflags & HDA_ADC_LOCKED)) 3665 hdac_widget_connection_select(w, j); 3666 ret = target; 3667 j += w->nconns; 3668 } 3669 } 3670 } 3671 3672 hdac_unlock(sc); 3673 3674 return (ret); 3675} 3676 3677static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3678 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3679 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3680 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3681 { 0, 0 } 3682}; 3683MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3684 3685static void 3686hdac_unsolq_task(void *context, int pending) 3687{ 3688 struct hdac_softc *sc; 3689 3690 sc = (struct hdac_softc *)context; 3691 3692 hdac_lock(sc); 3693 hdac_unsolq_flush(sc); 3694 hdac_unlock(sc); 3695} 3696 3697/**************************************************************************** 3698 * int hdac_attach(device_t) 3699 * 3700 * Attach the device into the kernel. Interrupts usually won't be enabled 3701 * when this function is called. Setup everything that doesn't require 3702 * interrupts and defer probing of codecs until interrupts are enabled. 3703 ****************************************************************************/ 3704static int 3705hdac_attach(device_t dev) 3706{ 3707 struct hdac_softc *sc; 3708 int result; 3709 int i; 3710 uint16_t vendor; 3711 uint8_t v; 3712 3713 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3714 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3715 sc->dev = dev; 3716 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3717 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3718 vendor = pci_get_vendor(dev); 3719 3720 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3721 /* Screw nx6325 - subdevice/subvendor swapped */ 3722 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3723 } 3724 3725 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3726 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3727 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3728 3729 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3730 3731 sc->poll_ticks = 1; 3732 sc->poll_ival = HDAC_POLL_INTERVAL; 3733 if (resource_int_value(device_get_name(dev), 3734 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3735 sc->polling = 1; 3736 else 3737 sc->polling = 0; 3738 3739 sc->chan_size = pcm_getbuffersize(dev, 3740 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3741 3742 if (resource_int_value(device_get_name(dev), 3743 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3744 i &= HDA_BLK_ALIGN; 3745 if (i < HDA_BLK_MIN) 3746 i = HDA_BLK_MIN; 3747 sc->chan_blkcnt = sc->chan_size / i; 3748 i = 0; 3749 while (sc->chan_blkcnt >> i) 3750 i++; 3751 sc->chan_blkcnt = 1 << (i - 1); 3752 if (sc->chan_blkcnt < HDA_BDL_MIN) 3753 sc->chan_blkcnt = HDA_BDL_MIN; 3754 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3755 sc->chan_blkcnt = HDA_BDL_MAX; 3756 } else 3757 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3758 3759 result = bus_dma_tag_create(NULL, /* parent */ 3760 HDAC_DMA_ALIGNMENT, /* alignment */ 3761 0, /* boundary */ 3762 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3763 BUS_SPACE_MAXADDR, /* highaddr */ 3764 NULL, /* filtfunc */ 3765 NULL, /* fistfuncarg */ 3766 sc->chan_size, /* maxsize */ 3767 1, /* nsegments */ 3768 sc->chan_size, /* maxsegsz */ 3769 0, /* flags */ 3770 NULL, /* lockfunc */ 3771 NULL, /* lockfuncarg */ 3772 &sc->chan_dmat); /* dmat */ 3773 if (result != 0) { 3774 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3775 __func__, result); 3776 snd_mtxfree(sc->lock); 3777 free(sc, M_DEVBUF); 3778 return (ENXIO); 3779 } 3780 3781 3782 sc->hdabus = NULL; 3783 for (i = 0; i < HDAC_CODEC_MAX; i++) 3784 sc->codecs[i] = NULL; 3785 3786 pci_enable_busmaster(dev); 3787 3788 if (vendor == INTEL_VENDORID) { 3789 /* TCSEL -> TC0 */ 3790 v = pci_read_config(dev, 0x44, 1); 3791 pci_write_config(dev, 0x44, v & 0xf8, 1); 3792 HDA_BOOTVERBOSE( 3793 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3794 pci_read_config(dev, 0x44, 1)); 3795 ); 3796 } 3797 3798#if __FreeBSD_version >= 602106 3799 if (resource_int_value(device_get_name(dev), 3800 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3801 pci_msi_count(dev) == 1) 3802 sc->flags |= HDAC_F_MSI; 3803 else 3804#endif 3805 sc->flags &= ~HDAC_F_MSI; 3806 3807#if defined(__i386__) || defined(__amd64__) 3808 sc->flags |= HDAC_F_DMA_NOCACHE; 3809 3810 if (resource_int_value(device_get_name(dev), 3811 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3812#else 3813 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3814#endif 3815 /* 3816 * Try to enable PCIe snoop to avoid messing around with 3817 * uncacheable DMA attribute. Since PCIe snoop register 3818 * config is pretty much vendor specific, there are no 3819 * general solutions on how to enable it, forcing us (even 3820 * Microsoft) to enable uncacheable or write combined DMA 3821 * by default. 3822 * 3823 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3824 */ 3825 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3826 if (hdac_pcie_snoop[i].vendor != vendor) 3827 continue; 3828 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3829 if (hdac_pcie_snoop[i].reg == 0x00) 3830 break; 3831 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3832 if ((v & hdac_pcie_snoop[i].enable) == 3833 hdac_pcie_snoop[i].enable) 3834 break; 3835 v &= hdac_pcie_snoop[i].mask; 3836 v |= hdac_pcie_snoop[i].enable; 3837 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3838 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3839 if ((v & hdac_pcie_snoop[i].enable) != 3840 hdac_pcie_snoop[i].enable) { 3841 HDA_BOOTVERBOSE( 3842 device_printf(dev, 3843 "WARNING: Failed to enable PCIe " 3844 "snoop!\n"); 3845 ); 3846#if defined(__i386__) || defined(__amd64__) 3847 sc->flags |= HDAC_F_DMA_NOCACHE; 3848#endif 3849 } 3850 break; 3851 } 3852#if defined(__i386__) || defined(__amd64__) 3853 } 3854#endif 3855 3856 HDA_BOOTVERBOSE( 3857 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3858 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3859 "Uncacheable" : "PCIe snoop", vendor); 3860 ); 3861 3862 /* Allocate resources */ 3863 result = hdac_mem_alloc(sc); 3864 if (result != 0) 3865 goto hdac_attach_fail; 3866 result = hdac_irq_alloc(sc); 3867 if (result != 0) 3868 goto hdac_attach_fail; 3869 3870 /* Get Capabilities */ 3871 result = hdac_get_capabilities(sc); 3872 if (result != 0) 3873 goto hdac_attach_fail; 3874 3875 /* Allocate CORB and RIRB dma memory */ 3876 result = hdac_dma_alloc(sc, &sc->corb_dma, 3877 sc->corb_size * sizeof(uint32_t)); 3878 if (result != 0) 3879 goto hdac_attach_fail; 3880 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3881 sc->rirb_size * sizeof(struct hdac_rirb)); 3882 if (result != 0) 3883 goto hdac_attach_fail; 3884 3885 /* Quiesce everything */ 3886 hdac_reset(sc); 3887 3888 /* Initialize the CORB and RIRB */ 3889 hdac_corb_init(sc); 3890 hdac_rirb_init(sc); 3891 3892 /* Defer remaining of initialization until interrupts are enabled */ 3893 sc->intrhook.ich_func = hdac_attach2; 3894 sc->intrhook.ich_arg = (void *)sc; 3895 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3896 sc->intrhook.ich_func = NULL; 3897 hdac_attach2((void *)sc); 3898 } 3899 3900 return (0); 3901 3902hdac_attach_fail: 3903 hdac_irq_free(sc); 3904 hdac_dma_free(sc, &sc->rirb_dma); 3905 hdac_dma_free(sc, &sc->corb_dma); 3906 hdac_mem_free(sc); 3907 snd_mtxfree(sc->lock); 3908 free(sc, M_DEVBUF); 3909 3910 return (ENXIO); 3911} 3912 3913static void 3914hdac_audio_parse(struct hdac_devinfo *devinfo) 3915{ 3916 struct hdac_softc *sc = devinfo->codec->sc; 3917 struct hdac_widget *w; 3918 uint32_t res; 3919 int i; 3920 nid_t cad, nid; 3921 3922 cad = devinfo->codec->cad; 3923 nid = devinfo->nid; 3924 3925 hdac_command(sc, 3926 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3927 3928 DELAY(100); 3929 3930 res = hdac_command(sc, 3931 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3932 3933 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3934 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3935 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3936 3937 res = hdac_command(sc, 3938 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3939 devinfo->function.audio.gpio = res; 3940 3941 HDA_BOOTVERBOSE( 3942 device_printf(sc->dev, " Vendor: 0x%08x\n", 3943 devinfo->vendor_id); 3944 device_printf(sc->dev, " Device: 0x%08x\n", 3945 devinfo->device_id); 3946 device_printf(sc->dev, " Revision: 0x%08x\n", 3947 devinfo->revision_id); 3948 device_printf(sc->dev, " Stepping: 0x%08x\n", 3949 devinfo->stepping_id); 3950 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3951 sc->pci_subvendor); 3952 device_printf(sc->dev, " Nodes: start=%d " 3953 "endnode=%d total=%d\n", 3954 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3955 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3956 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3957 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3958 sc->num_iss, sc->num_oss, sc->num_bss); 3959 device_printf(sc->dev, " GPIO: 0x%08x\n", 3960 devinfo->function.audio.gpio); 3961 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3962 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3963 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3964 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3965 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3966 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3967 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3968 ); 3969 3970 res = hdac_command(sc, 3971 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3972 cad); 3973 devinfo->function.audio.supp_stream_formats = res; 3974 3975 res = hdac_command(sc, 3976 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3977 cad); 3978 devinfo->function.audio.supp_pcm_size_rate = res; 3979 3980 res = hdac_command(sc, 3981 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3982 cad); 3983 devinfo->function.audio.outamp_cap = res; 3984 3985 res = hdac_command(sc, 3986 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3987 cad); 3988 devinfo->function.audio.inamp_cap = res; 3989 3990 if (devinfo->nodecnt > 0) 3991 devinfo->widget = (struct hdac_widget *)malloc( 3992 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3993 M_NOWAIT | M_ZERO); 3994 else 3995 devinfo->widget = NULL; 3996 3997 if (devinfo->widget == NULL) { 3998 device_printf(sc->dev, "unable to allocate widgets!\n"); 3999 devinfo->endnode = devinfo->startnode; 4000 devinfo->nodecnt = 0; 4001 return; 4002 } 4003 4004 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4005 w = hdac_widget_get(devinfo, i); 4006 if (w == NULL) 4007 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4008 else { 4009 w->devinfo = devinfo; 4010 w->nid = i; 4011 w->enable = 1; 4012 w->selconn = -1; 4013 w->pflags = 0; 4014 w->ctlflags = 0; 4015 w->param.eapdbtl = HDAC_INVALID; 4016 hdac_widget_parse(w); 4017 } 4018 } 4019} 4020 4021static void 4022hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4023{ 4024 struct hdac_softc *sc = devinfo->codec->sc; 4025 struct hdac_audio_ctl *ctls; 4026 struct hdac_widget *w, *cw; 4027 int i, j, cnt, max, ocap, icap; 4028 int mute, offset, step, size; 4029 4030 /* XXX This is redundant */ 4031 max = 0; 4032 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4033 w = hdac_widget_get(devinfo, i); 4034 if (w == NULL || w->enable == 0) 4035 continue; 4036 if (w->param.outamp_cap != 0) 4037 max++; 4038 if (w->param.inamp_cap != 0) { 4039 switch (w->type) { 4040 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4041 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4042 for (j = 0; j < w->nconns; j++) { 4043 cw = hdac_widget_get(devinfo, 4044 w->conns[j]); 4045 if (cw == NULL || cw->enable == 0) 4046 continue; 4047 max++; 4048 } 4049 break; 4050 default: 4051 max++; 4052 break; 4053 } 4054 } 4055 } 4056 4057 devinfo->function.audio.ctlcnt = max; 4058 4059 if (max < 1) 4060 return; 4061 4062 ctls = (struct hdac_audio_ctl *)malloc( 4063 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4064 4065 if (ctls == NULL) { 4066 /* Blekh! */ 4067 device_printf(sc->dev, "unable to allocate ctls!\n"); 4068 devinfo->function.audio.ctlcnt = 0; 4069 return; 4070 } 4071 4072 cnt = 0; 4073 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4074 if (cnt >= max) { 4075 device_printf(sc->dev, "%s: Ctl overflow!\n", 4076 __func__); 4077 break; 4078 } 4079 w = hdac_widget_get(devinfo, i); 4080 if (w == NULL || w->enable == 0) 4081 continue; 4082 ocap = w->param.outamp_cap; 4083 icap = w->param.inamp_cap; 4084 if (ocap != 0) { 4085 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4086 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4087 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4088 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4089 /*if (offset > step) { 4090 HDA_BOOTVERBOSE( 4091 device_printf(sc->dev, 4092 "HDA_DEBUG: BUGGY outamp: nid=%d " 4093 "[offset=%d > step=%d]\n", 4094 w->nid, offset, step); 4095 ); 4096 offset = step; 4097 }*/ 4098 ctls[cnt].enable = 1; 4099 ctls[cnt].widget = w; 4100 ctls[cnt].mute = mute; 4101 ctls[cnt].step = step; 4102 ctls[cnt].size = size; 4103 ctls[cnt].offset = offset; 4104 ctls[cnt].left = offset; 4105 ctls[cnt].right = offset; 4106 ctls[cnt++].dir = HDA_CTL_OUT; 4107 } 4108 4109 if (icap != 0) { 4110 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4111 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4112 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4113 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4114 /*if (offset > step) { 4115 HDA_BOOTVERBOSE( 4116 device_printf(sc->dev, 4117 "HDA_DEBUG: BUGGY inamp: nid=%d " 4118 "[offset=%d > step=%d]\n", 4119 w->nid, offset, step); 4120 ); 4121 offset = step; 4122 }*/ 4123 switch (w->type) { 4124 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4125 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4126 for (j = 0; j < w->nconns; j++) { 4127 if (cnt >= max) { 4128 device_printf(sc->dev, 4129 "%s: Ctl overflow!\n", 4130 __func__); 4131 break; 4132 } 4133 cw = hdac_widget_get(devinfo, 4134 w->conns[j]); 4135 if (cw == NULL || cw->enable == 0) 4136 continue; 4137 ctls[cnt].enable = 1; 4138 ctls[cnt].widget = w; 4139 ctls[cnt].childwidget = cw; 4140 ctls[cnt].index = j; 4141 ctls[cnt].mute = mute; 4142 ctls[cnt].step = step; 4143 ctls[cnt].size = size; 4144 ctls[cnt].offset = offset; 4145 ctls[cnt].left = offset; 4146 ctls[cnt].right = offset; 4147 ctls[cnt++].dir = HDA_CTL_IN; 4148 } 4149 break; 4150 default: 4151 if (cnt >= max) { 4152 device_printf(sc->dev, 4153 "%s: Ctl overflow!\n", 4154 __func__); 4155 break; 4156 } 4157 ctls[cnt].enable = 1; 4158 ctls[cnt].widget = w; 4159 ctls[cnt].mute = mute; 4160 ctls[cnt].step = step; 4161 ctls[cnt].size = size; 4162 ctls[cnt].offset = offset; 4163 ctls[cnt].left = offset; 4164 ctls[cnt].right = offset; 4165 ctls[cnt++].dir = HDA_CTL_IN; 4166 break; 4167 } 4168 } 4169 } 4170 4171 devinfo->function.audio.ctl = ctls; 4172} 4173 4174static const struct { 4175 uint32_t model; 4176 uint32_t id; 4177 uint32_t set, unset; 4178} hdac_quirks[] = { 4179 /* 4180 * XXX Force stereo quirk. Monoural recording / playback 4181 * on few codecs (especially ALC880) seems broken or 4182 * perhaps unsupported. 4183 */ 4184 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4185 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4186 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4187 HDA_QUIRK_GPIO0, 0 }, 4188 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4189 HDA_QUIRK_GPIO0, 0 }, 4190 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4191 HDA_QUIRK_GPIO0, 0 }, 4192 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4193 HDA_QUIRK_GPIO0, 0 }, 4194 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4195 HDA_QUIRK_GPIO0, 0 }, 4196 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4197 HDA_QUIRK_EAPDINV, 0 }, 4198 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4199 HDA_QUIRK_EAPDINV, 0 }, 4200 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4201 HDA_QUIRK_OVREF, 0 }, 4202 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4203 HDA_QUIRK_OVREF, 0 }, 4204 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4205 HDA_QUIRK_OVREF, 0 }, 4206 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4207 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4208 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4209 HDA_QUIRK_GPIO1, 0 }, 4210 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4211 HDA_QUIRK_EAPDINV, 0 }, 4212 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4213 HDA_QUIRK_EAPDINV, 0 }, 4214 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4215 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4216 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4217 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4218 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4219 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4220 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4221 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4222 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4223 0, HDA_QUIRK_FORCESTEREO }, 4224 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4225 HDA_QUIRK_SOFTPCMVOL, 0 } 4226}; 4227#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4228 4229static void 4230hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4231{ 4232 struct hdac_widget *w; 4233 struct hdac_audio_ctl *ctl; 4234 uint32_t id, subvendor; 4235 int i; 4236 4237 id = hdac_codec_id(devinfo); 4238 subvendor = devinfo->codec->sc->pci_subvendor; 4239 4240 /* 4241 * Quirks 4242 */ 4243 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4244 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4245 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4246 continue; 4247 if (hdac_quirks[i].set != 0) 4248 devinfo->function.audio.quirks |= 4249 hdac_quirks[i].set; 4250 if (hdac_quirks[i].unset != 0) 4251 devinfo->function.audio.quirks &= 4252 ~(hdac_quirks[i].unset); 4253 } 4254 4255 switch (id) { 4256 case HDA_CODEC_ALC260: 4257 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4258 w = hdac_widget_get(devinfo, i); 4259 if (w == NULL || w->enable == 0) 4260 continue; 4261 if (w->type != 4262 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4263 continue; 4264 if (w->nid != 5) 4265 w->enable = 0; 4266 } 4267 if (subvendor == HP_XW4300_SUBVENDOR) { 4268 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4269 if (ctl != NULL && ctl->widget != NULL) { 4270 ctl->ossmask = SOUND_MASK_SPEAKER; 4271 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4272 } 4273 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4274 if (ctl != NULL && ctl->widget != NULL) { 4275 ctl->ossmask = SOUND_MASK_SPEAKER; 4276 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4277 } 4278 } else if (subvendor == HP_3010_SUBVENDOR) { 4279 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4280 if (ctl != NULL && ctl->widget != NULL) { 4281 ctl->ossmask = SOUND_MASK_SPEAKER; 4282 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4283 } 4284 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4285 if (ctl != NULL && ctl->widget != NULL) { 4286 ctl->ossmask = SOUND_MASK_SPEAKER; 4287 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4288 } 4289 } 4290 break; 4291 case HDA_CODEC_ALC262: 4292 if (subvendor == HP_DC7700_SUBVENDOR) { 4293 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4294 if (ctl != NULL && ctl->widget != NULL) { 4295 ctl->ossmask = SOUND_MASK_SPEAKER; 4296 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4297 } 4298 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4299 if (ctl != NULL && ctl->widget != NULL) { 4300 ctl->ossmask = SOUND_MASK_SPEAKER; 4301 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4302 } 4303 } 4304 break; 4305 case HDA_CODEC_ALC268: 4306 if (HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, subvendor)) { 4307 w = hdac_widget_get(devinfo, 29); 4308 if (w != NULL) { 4309 w->enable = 1; 4310 w->type = 4311 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4312 w->param.widget_cap &= 4313 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4314 w->param.widget_cap |= 4315 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4316 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4317 strlcpy(w->name, "beep widget", sizeof(w->name)); 4318 } 4319 } 4320 break; 4321 case HDA_CODEC_ALC861: 4322 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4323 if (ctl != NULL) 4324 ctl->muted = HDA_AMP_MUTE_ALL; 4325 break; 4326 case HDA_CODEC_ALC880: 4327 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4328 w = hdac_widget_get(devinfo, i); 4329 if (w == NULL || w->enable == 0) 4330 continue; 4331 if (w->type == 4332 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4333 w->nid != 9 && w->nid != 29) { 4334 w->enable = 0; 4335 } else if (w->type != 4336 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4337 w->nid == 29) { 4338 w->type = 4339 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4340 w->param.widget_cap &= 4341 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4342 w->param.widget_cap |= 4343 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4344 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4345 strlcpy(w->name, "beep widget", sizeof(w->name)); 4346 } 4347 } 4348 break; 4349 case HDA_CODEC_ALC883: 4350 /* 4351 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4352 * Clear vref cap for jack connectivity. 4353 */ 4354 w = hdac_widget_get(devinfo, 24); 4355 if (w != NULL && w->enable != 0 && w->type == 4356 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4357 (w->wclass.pin.config & 4358 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4359 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4360 w->wclass.pin.cap &= ~( 4361 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4362 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4363 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4364 w = hdac_widget_get(devinfo, 25); 4365 if (w != NULL && w->enable != 0 && w->type == 4366 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4367 (w->wclass.pin.config & 4368 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4369 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4370 w->wclass.pin.cap &= ~( 4371 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4372 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4373 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4374 /* 4375 * nid: 26 = Line-in, leave it alone. 4376 */ 4377 break; 4378 case HDA_CODEC_AD1981HD: 4379 w = hdac_widget_get(devinfo, 11); 4380 if (w != NULL && w->enable != 0 && w->nconns > 3) 4381 w->selconn = 3; 4382 if (subvendor == IBM_M52_SUBVENDOR) { 4383 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4384 if (ctl != NULL) 4385 ctl->ossmask = SOUND_MASK_SPEAKER; 4386 } 4387 break; 4388 case HDA_CODEC_AD1986A: 4389 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4390 w = hdac_widget_get(devinfo, i); 4391 if (w == NULL || w->enable == 0) 4392 continue; 4393 if (w->type != 4394 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4395 continue; 4396 if (w->nid != 3) 4397 w->enable = 0; 4398 } 4399 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4400 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4401 /* nid 28 is mic, nid 29 is line-in */ 4402 w = hdac_widget_get(devinfo, 15); 4403 if (w != NULL) 4404 w->selconn = 2; 4405 w = hdac_widget_get(devinfo, 16); 4406 if (w != NULL) 4407 w->selconn = 1; 4408 } 4409 break; 4410 case HDA_CODEC_AD1988: 4411 case HDA_CODEC_AD1988B: 4412 /*w = hdac_widget_get(devinfo, 12); 4413 if (w != NULL) { 4414 w->selconn = 1; 4415 w->pflags |= HDA_ADC_LOCKED; 4416 } 4417 w = hdac_widget_get(devinfo, 13); 4418 if (w != NULL) { 4419 w->selconn = 4; 4420 w->pflags |= HDA_ADC_LOCKED; 4421 } 4422 w = hdac_widget_get(devinfo, 14); 4423 if (w != NULL) { 4424 w->selconn = 2; 4425 w->pflags |= HDA_ADC_LOCKED; 4426 }*/ 4427 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4428 if (ctl != NULL) { 4429 ctl->ossmask = SOUND_MASK_IGAIN; 4430 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4431 } 4432 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4433 if (ctl != NULL) { 4434 ctl->ossmask = SOUND_MASK_IGAIN; 4435 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4436 } 4437 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4438 if (ctl != NULL) { 4439 ctl->ossmask = SOUND_MASK_IGAIN; 4440 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4441 } 4442 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4443 if (ctl != NULL) { 4444 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4445 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4446 } 4447 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4448 if (ctl != NULL) { 4449 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4450 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4451 } 4452 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4453 if (ctl != NULL) { 4454 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4455 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4456 } 4457 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4458 if (ctl != NULL) { 4459 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4460 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4461 } 4462 break; 4463 case HDA_CODEC_STAC9221: 4464 /* 4465 * Dell XPS M1210 need all DACs for each output jacks 4466 */ 4467 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4468 break; 4469 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4470 w = hdac_widget_get(devinfo, i); 4471 if (w == NULL || w->enable == 0) 4472 continue; 4473 if (w->type != 4474 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4475 continue; 4476 if (w->nid != 2) 4477 w->enable = 0; 4478 } 4479 break; 4480 case HDA_CODEC_STAC9221D: 4481 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4482 w = hdac_widget_get(devinfo, i); 4483 if (w == NULL || w->enable == 0) 4484 continue; 4485 if (w->type == 4486 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4487 w->nid != 6) 4488 w->enable = 0; 4489 4490 } 4491 break; 4492 case HDA_CODEC_STAC9227: 4493 w = hdac_widget_get(devinfo, 8); 4494 if (w != NULL) 4495 w->enable = 0; 4496 w = hdac_widget_get(devinfo, 9); 4497 if (w != NULL) 4498 w->enable = 0; 4499 break; 4500 case HDA_CODEC_CXWAIKIKI: 4501 if (subvendor == HP_DV5000_SUBVENDOR) { 4502 w = hdac_widget_get(devinfo, 27); 4503 if (w != NULL) 4504 w->enable = 0; 4505 } 4506 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4507 if (ctl != NULL) 4508 ctl->ossmask = SOUND_MASK_SKIP; 4509 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4510 if (ctl != NULL && ctl->childwidget != NULL && 4511 ctl->childwidget->enable != 0) { 4512 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4513 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4514 } 4515 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4516 if (ctl != NULL && ctl->childwidget != NULL && 4517 ctl->childwidget->enable != 0) { 4518 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4519 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4520 } 4521 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4522 if (ctl != NULL && ctl->childwidget != NULL && 4523 ctl->childwidget->enable != 0) { 4524 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4525 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4526 } 4527 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4528 if (ctl != NULL) { 4529 ctl->ossmask = SOUND_MASK_SKIP; 4530 /* XXX mixer \=rec mic broken.. why?!? */ 4531 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4532 } 4533 break; 4534 default: 4535 break; 4536 } 4537} 4538 4539static int 4540hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4541{ 4542 int *dev = &devinfo->function.audio.ossidx; 4543 4544 while (*dev < SOUND_MIXER_NRDEVICES) { 4545 switch (*dev) { 4546 case SOUND_MIXER_VOLUME: 4547 case SOUND_MIXER_BASS: 4548 case SOUND_MIXER_TREBLE: 4549 case SOUND_MIXER_PCM: 4550 case SOUND_MIXER_SPEAKER: 4551 case SOUND_MIXER_LINE: 4552 case SOUND_MIXER_MIC: 4553 case SOUND_MIXER_CD: 4554 case SOUND_MIXER_RECLEV: 4555 case SOUND_MIXER_IGAIN: 4556 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4557 (*dev)++; 4558 break; 4559 default: 4560 return (*dev)++; 4561 break; 4562 } 4563 } 4564 4565 return (-1); 4566} 4567 4568static int 4569hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4570{ 4571 struct hdac_widget *w; 4572 int i, ret = 0; 4573 4574 if (depth > HDA_PARSE_MAXDEPTH) 4575 return (0); 4576 w = hdac_widget_get(devinfo, nid); 4577 if (w == NULL || w->enable == 0) 4578 return (0); 4579 switch (w->type) { 4580 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4581 w->pflags |= HDA_DAC_PATH; 4582 ret = 1; 4583 break; 4584 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4585 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4586 for (i = 0; i < w->nconns; i++) { 4587 if (hdac_widget_find_dac_path(devinfo, 4588 w->conns[i], depth + 1) != 0) { 4589 if (w->selconn == -1) 4590 w->selconn = i; 4591 ret = 1; 4592 w->pflags |= HDA_DAC_PATH; 4593 } 4594 } 4595 break; 4596 default: 4597 break; 4598 } 4599 return (ret); 4600} 4601 4602static int 4603hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4604{ 4605 struct hdac_widget *w; 4606 int i, conndev, ret = 0; 4607 4608 if (depth > HDA_PARSE_MAXDEPTH) 4609 return (0); 4610 w = hdac_widget_get(devinfo, nid); 4611 if (w == NULL || w->enable == 0) 4612 return (0); 4613 switch (w->type) { 4614 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4615 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4616 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4617 for (i = 0; i < w->nconns; i++) { 4618 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4619 depth + 1) != 0) { 4620 if (w->selconn == -1) 4621 w->selconn = i; 4622 w->pflags |= HDA_ADC_PATH; 4623 ret = 1; 4624 } 4625 } 4626 break; 4627 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4628 conndev = w->wclass.pin.config & 4629 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4630 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4631 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4632 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4633 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4634 w->pflags |= HDA_ADC_PATH; 4635 ret = 1; 4636 } 4637 break; 4638 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4639 if (w->pflags & HDA_DAC_PATH) { 4640 w->pflags |= HDA_ADC_PATH; 4641 ret = 1; 4642 } 4643 break;*/ 4644 default: 4645 break; 4646 } 4647 return (ret); 4648} 4649 4650static uint32_t 4651hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4652 nid_t nid, nid_t pnid, int index, int depth) 4653{ 4654 struct hdac_widget *w, *pw; 4655 struct hdac_audio_ctl *ctl; 4656 uint32_t fl = 0; 4657 int i, ossdev, conndev, strategy; 4658 4659 if (depth > HDA_PARSE_MAXDEPTH) 4660 return (0); 4661 4662 w = hdac_widget_get(devinfo, nid); 4663 if (w == NULL || w->enable == 0) 4664 return (0); 4665 4666 pw = hdac_widget_get(devinfo, pnid); 4667 strategy = devinfo->function.audio.parsing_strategy; 4668 4669 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4670 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4671 for (i = 0; i < w->nconns; i++) { 4672 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4673 w->nid, i, depth + 1); 4674 } 4675 w->ctlflags |= fl; 4676 return (fl); 4677 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4678 (w->pflags & HDA_DAC_PATH)) { 4679 i = 0; 4680 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4681 if (ctl->enable == 0 || ctl->widget == NULL) 4682 continue; 4683 /* XXX This should be compressed! */ 4684 if (((ctl->widget->nid == w->nid) || 4685 (ctl->widget->nid == pnid && ctl->index == index && 4686 (ctl->dir & HDA_CTL_IN)) || 4687 (ctl->widget->nid == pnid && pw != NULL && 4688 pw->type == 4689 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4690 (pw->nconns < 2 || pw->selconn == index || 4691 pw->selconn == -1) && 4692 (ctl->dir & HDA_CTL_OUT)) || 4693 (strategy == HDA_PARSE_DIRECT && 4694 ctl->widget->nid == w->nid)) && 4695 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4696 /*if (pw != NULL && pw->selconn == -1) 4697 pw->selconn = index; 4698 fl |= SOUND_MASK_VOLUME; 4699 fl |= SOUND_MASK_PCM; 4700 ctl->ossmask |= SOUND_MASK_VOLUME; 4701 ctl->ossmask |= SOUND_MASK_PCM; 4702 ctl->ossdev = SOUND_MIXER_PCM;*/ 4703 if (!(w->ctlflags & SOUND_MASK_PCM) || 4704 (pw != NULL && 4705 !(pw->ctlflags & SOUND_MASK_PCM))) { 4706 fl |= SOUND_MASK_VOLUME; 4707 fl |= SOUND_MASK_PCM; 4708 ctl->ossmask |= SOUND_MASK_VOLUME; 4709 ctl->ossmask |= SOUND_MASK_PCM; 4710 ctl->ossdev = SOUND_MIXER_PCM; 4711 w->ctlflags |= SOUND_MASK_VOLUME; 4712 w->ctlflags |= SOUND_MASK_PCM; 4713 if (pw != NULL) { 4714 if (pw->selconn == -1) 4715 pw->selconn = index; 4716 pw->ctlflags |= 4717 SOUND_MASK_VOLUME; 4718 pw->ctlflags |= 4719 SOUND_MASK_PCM; 4720 } 4721 } 4722 } 4723 } 4724 w->ctlflags |= fl; 4725 return (fl); 4726 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4727 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4728 (w->pflags & HDA_ADC_PATH)) { 4729 conndev = w->wclass.pin.config & 4730 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4731 i = 0; 4732 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4733 if (ctl->enable == 0 || ctl->widget == NULL) 4734 continue; 4735 /* XXX This should be compressed! */ 4736 if (((ctl->widget->nid == pnid && ctl->index == index && 4737 (ctl->dir & HDA_CTL_IN)) || 4738 (ctl->widget->nid == pnid && pw != NULL && 4739 pw->type == 4740 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4741 (pw->nconns < 2 || pw->selconn == index || 4742 pw->selconn == -1) && 4743 (ctl->dir & HDA_CTL_OUT)) || 4744 (strategy == HDA_PARSE_DIRECT && 4745 ctl->widget->nid == w->nid)) && 4746 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4747 if (pw != NULL && pw->selconn == -1) 4748 pw->selconn = index; 4749 ossdev = 0; 4750 switch (conndev) { 4751 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4752 ossdev = SOUND_MIXER_MIC; 4753 break; 4754 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4755 ossdev = SOUND_MIXER_LINE; 4756 break; 4757 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4758 ossdev = SOUND_MIXER_CD; 4759 break; 4760 default: 4761 ossdev = 4762 hdac_audio_ctl_ossmixer_getnextdev( 4763 devinfo); 4764 if (ossdev < 0) 4765 ossdev = 0; 4766 break; 4767 } 4768 if (strategy == HDA_PARSE_MIXER) { 4769 fl |= SOUND_MASK_VOLUME; 4770 ctl->ossmask |= SOUND_MASK_VOLUME; 4771 } 4772 fl |= 1 << ossdev; 4773 ctl->ossmask |= 1 << ossdev; 4774 ctl->ossdev = ossdev; 4775 } 4776 } 4777 w->ctlflags |= fl; 4778 return (fl); 4779 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4780 i = 0; 4781 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4782 if (ctl->enable == 0 || ctl->widget == NULL) 4783 continue; 4784 /* XXX This should be compressed! */ 4785 if (((ctl->widget->nid == pnid && ctl->index == index && 4786 (ctl->dir & HDA_CTL_IN)) || 4787 (ctl->widget->nid == pnid && pw != NULL && 4788 pw->type == 4789 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4790 (pw->nconns < 2 || pw->selconn == index || 4791 pw->selconn == -1) && 4792 (ctl->dir & HDA_CTL_OUT)) || 4793 (strategy == HDA_PARSE_DIRECT && 4794 ctl->widget->nid == w->nid)) && 4795 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4796 if (pw != NULL && pw->selconn == -1) 4797 pw->selconn = index; 4798 fl |= SOUND_MASK_VOLUME; 4799 fl |= SOUND_MASK_SPEAKER; 4800 ctl->ossmask |= SOUND_MASK_VOLUME; 4801 ctl->ossmask |= SOUND_MASK_SPEAKER; 4802 ctl->ossdev = SOUND_MIXER_SPEAKER; 4803 } 4804 } 4805 w->ctlflags |= fl; 4806 return (fl); 4807 } 4808 return (0); 4809} 4810 4811static uint32_t 4812hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4813{ 4814 struct hdac_widget *w, *cw; 4815 struct hdac_audio_ctl *ctl; 4816 uint32_t fl; 4817 int i; 4818 4819 if (depth > HDA_PARSE_MAXDEPTH) 4820 return (0); 4821 4822 w = hdac_widget_get(devinfo, nid); 4823 if (w == NULL || w->enable == 0) 4824 return (0); 4825 /*if (!(w->pflags & HDA_ADC_PATH)) 4826 return (0); 4827 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4828 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4829 return (0);*/ 4830 i = 0; 4831 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4832 if (ctl->enable == 0 || ctl->widget == NULL) 4833 continue; 4834 if (ctl->widget->nid == nid) { 4835 ctl->ossmask |= SOUND_MASK_RECLEV; 4836 w->ctlflags |= SOUND_MASK_RECLEV; 4837 return (SOUND_MASK_RECLEV); 4838 } 4839 } 4840 for (i = 0; i < w->nconns; i++) { 4841 cw = hdac_widget_get(devinfo, w->conns[i]); 4842 if (cw == NULL || cw->enable == 0) 4843 continue; 4844 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4845 continue; 4846 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4847 if (fl != 0) { 4848 cw->ctlflags |= fl; 4849 w->ctlflags |= fl; 4850 return (fl); 4851 } 4852 } 4853 return (0); 4854} 4855 4856static int 4857hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4858{ 4859 struct hdac_widget *w, *cw; 4860 int i, child = 0; 4861 4862 if (depth > HDA_PARSE_MAXDEPTH) 4863 return (0); 4864 4865 w = hdac_widget_get(devinfo, nid); 4866 if (w == NULL || w->enable == 0) 4867 return (0); 4868 /*if (!(w->pflags & HDA_ADC_PATH)) 4869 return (0); 4870 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4871 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4872 return (0);*/ 4873 /* XXX weak! */ 4874 for (i = 0; i < w->nconns; i++) { 4875 cw = hdac_widget_get(devinfo, w->conns[i]); 4876 if (cw == NULL) 4877 continue; 4878 if (++child > 1) { 4879 w->pflags |= HDA_ADC_RECSEL; 4880 return (1); 4881 } 4882 } 4883 for (i = 0; i < w->nconns; i++) { 4884 if (hdac_audio_ctl_recsel_build(devinfo, 4885 w->conns[i], depth + 1) != 0) 4886 return (1); 4887 } 4888 return (0); 4889} 4890 4891static int 4892hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4893{ 4894 struct hdac_widget *w, *cw; 4895 int i, j, conndev, found_dac = 0; 4896 int strategy; 4897 4898 strategy = devinfo->function.audio.parsing_strategy; 4899 4900 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4901 w = hdac_widget_get(devinfo, i); 4902 if (w == NULL || w->enable == 0) 4903 continue; 4904 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4905 continue; 4906 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4907 continue; 4908 conndev = w->wclass.pin.config & 4909 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4910 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4911 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4912 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4913 continue; 4914 for (j = 0; j < w->nconns; j++) { 4915 cw = hdac_widget_get(devinfo, w->conns[j]); 4916 if (cw == NULL || cw->enable == 0) 4917 continue; 4918 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4919 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4920 cw->type == 4921 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4922 continue; 4923 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4924 != 0) { 4925 if (w->selconn == -1) 4926 w->selconn = j; 4927 w->pflags |= HDA_DAC_PATH; 4928 found_dac++; 4929 } 4930 } 4931 } 4932 4933 return (found_dac); 4934} 4935 4936static void 4937hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4938{ 4939 struct hdac_widget *w; 4940 struct hdac_audio_ctl *ctl; 4941 int i, j, dacs, strategy; 4942 4943 /* Construct DAC path */ 4944 strategy = HDA_PARSE_MIXER; 4945 devinfo->function.audio.parsing_strategy = strategy; 4946 HDA_BOOTVERBOSE( 4947 device_printf(devinfo->codec->sc->dev, 4948 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4949 HDA_WIDGET_PARSER_REV); 4950 ); 4951 dacs = hdac_audio_build_tree_strategy(devinfo); 4952 if (dacs == 0) { 4953 HDA_BOOTVERBOSE( 4954 device_printf(devinfo->codec->sc->dev, 4955 "HDA_DEBUG: HWiP: 0 DAC path found! " 4956 "Retrying parser " 4957 "using HDA_PARSE_DIRECT strategy.\n"); 4958 ); 4959 strategy = HDA_PARSE_DIRECT; 4960 devinfo->function.audio.parsing_strategy = strategy; 4961 dacs = hdac_audio_build_tree_strategy(devinfo); 4962 } 4963 4964 HDA_BOOTVERBOSE( 4965 device_printf(devinfo->codec->sc->dev, 4966 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4967 "strategy.\n", 4968 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4969 ); 4970 4971 /* Construct ADC path */ 4972 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4973 w = hdac_widget_get(devinfo, i); 4974 if (w == NULL || w->enable == 0) 4975 continue; 4976 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4977 continue; 4978 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4979 } 4980 4981 /* Output mixers */ 4982 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4983 w = hdac_widget_get(devinfo, i); 4984 if (w == NULL || w->enable == 0) 4985 continue; 4986 if ((strategy == HDA_PARSE_MIXER && 4987 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4988 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4989 && (w->pflags & HDA_DAC_PATH)) || 4990 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4991 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4992 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4993 w->nid, devinfo->startnode - 1, 0, 0); 4994 } else if (w->type == 4995 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4996 j = 0; 4997 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4998 NULL) { 4999 if (ctl->enable == 0 || ctl->widget == NULL) 5000 continue; 5001 if (ctl->widget->nid != w->nid) 5002 continue; 5003 ctl->ossmask |= SOUND_MASK_VOLUME; 5004 ctl->ossmask |= SOUND_MASK_SPEAKER; 5005 ctl->ossdev = SOUND_MIXER_SPEAKER; 5006 w->ctlflags |= SOUND_MASK_VOLUME; 5007 w->ctlflags |= SOUND_MASK_SPEAKER; 5008 } 5009 } 5010 } 5011 5012 /* Input mixers (rec) */ 5013 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5014 w = hdac_widget_get(devinfo, i); 5015 if (w == NULL || w->enable == 0) 5016 continue; 5017 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 5018 w->pflags & HDA_ADC_PATH)) 5019 continue; 5020 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 5021 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 5022 } 5023} 5024 5025#define HDA_COMMIT_CONN (1 << 0) 5026#define HDA_COMMIT_CTRL (1 << 1) 5027#define HDA_COMMIT_EAPD (1 << 2) 5028#define HDA_COMMIT_GPIO (1 << 3) 5029#define HDA_COMMIT_MISC (1 << 4) 5030#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5031 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5032 5033static void 5034hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5035{ 5036 struct hdac_softc *sc = devinfo->codec->sc; 5037 struct hdac_widget *w; 5038 nid_t cad; 5039 int i; 5040 5041 if (!(cfl & HDA_COMMIT_ALL)) 5042 return; 5043 5044 cad = devinfo->codec->cad; 5045 5046 if ((cfl & HDA_COMMIT_MISC)) { 5047 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5048 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5049 0x7e7, 0), cad); 5050 } 5051 5052 if (cfl & HDA_COMMIT_GPIO) { 5053 uint32_t gdata, gmask, gdir; 5054 int commitgpio, numgpio; 5055 5056 gdata = 0; 5057 gmask = 0; 5058 gdir = 0; 5059 commitgpio = 0; 5060 5061 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5062 devinfo->function.audio.gpio); 5063 5064 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5065 commitgpio = (numgpio > 0) ? 1 : 0; 5066 else { 5067 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5068 if (!(devinfo->function.audio.quirks & 5069 (1 << i))) 5070 continue; 5071 if (commitgpio == 0) { 5072 commitgpio = 1; 5073 HDA_BOOTVERBOSE( 5074 gdata = hdac_command(sc, 5075 HDA_CMD_GET_GPIO_DATA(cad, 5076 devinfo->nid), cad); 5077 gmask = hdac_command(sc, 5078 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5079 devinfo->nid), cad); 5080 gdir = hdac_command(sc, 5081 HDA_CMD_GET_GPIO_DIRECTION(cad, 5082 devinfo->nid), cad); 5083 device_printf(sc->dev, 5084 "GPIO init: data=0x%08x " 5085 "mask=0x%08x dir=0x%08x\n", 5086 gdata, gmask, gdir); 5087 gdata = 0; 5088 gmask = 0; 5089 gdir = 0; 5090 ); 5091 } 5092 gdata |= 1 << i; 5093 gmask |= 1 << i; 5094 gdir |= 1 << i; 5095 } 5096 } 5097 5098 if (commitgpio != 0) { 5099 HDA_BOOTVERBOSE( 5100 device_printf(sc->dev, 5101 "GPIO commit: data=0x%08x mask=0x%08x " 5102 "dir=0x%08x\n", 5103 gdata, gmask, gdir); 5104 ); 5105 hdac_command(sc, 5106 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5107 gmask), cad); 5108 hdac_command(sc, 5109 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5110 gdir), cad); 5111 hdac_command(sc, 5112 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5113 gdata), cad); 5114 } 5115 } 5116 5117 for (i = 0; i < devinfo->nodecnt; i++) { 5118 w = &devinfo->widget[i]; 5119 if (w == NULL || w->enable == 0) 5120 continue; 5121 if (cfl & HDA_COMMIT_CONN) { 5122 if (w->selconn == -1) 5123 w->selconn = 0; 5124 if (w->nconns > 0) 5125 hdac_widget_connection_select(w, w->selconn); 5126 } 5127 if ((cfl & HDA_COMMIT_CTRL) && 5128 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5129 uint32_t pincap; 5130 5131 pincap = w->wclass.pin.cap; 5132 5133 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5134 (HDA_DAC_PATH | HDA_ADC_PATH)) 5135 device_printf(sc->dev, "WARNING: node %d " 5136 "participate both for DAC/ADC!\n", w->nid); 5137 if (w->pflags & HDA_DAC_PATH) { 5138 w->wclass.pin.ctrl &= 5139 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5140 if ((w->wclass.pin.config & 5141 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5142 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5143 w->wclass.pin.ctrl &= 5144 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5145 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5146 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5147 w->wclass.pin.ctrl |= 5148 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5149 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5150 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5151 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5152 w->wclass.pin.ctrl |= 5153 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5154 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5155 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5156 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5157 w->wclass.pin.ctrl |= 5158 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5159 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5160 } else if (w->pflags & HDA_ADC_PATH) { 5161 w->wclass.pin.ctrl &= 5162 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5163 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5164 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5165 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5166 w->wclass.pin.ctrl |= 5167 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5168 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5169 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5170 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5171 w->wclass.pin.ctrl |= 5172 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5173 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5174 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5175 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5176 w->wclass.pin.ctrl |= 5177 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5178 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5179 } else 5180 w->wclass.pin.ctrl &= ~( 5181 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5182 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5183 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5184 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5185 hdac_command(sc, 5186 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5187 w->wclass.pin.ctrl), cad); 5188 } 5189 if ((cfl & HDA_COMMIT_EAPD) && 5190 w->param.eapdbtl != HDAC_INVALID) { 5191 uint32_t val; 5192 5193 val = w->param.eapdbtl; 5194 if (devinfo->function.audio.quirks & 5195 HDA_QUIRK_EAPDINV) 5196 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5197 hdac_command(sc, 5198 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5199 val), cad); 5200 5201 } 5202 DELAY(1000); 5203 } 5204} 5205 5206static void 5207hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5208{ 5209 struct hdac_softc *sc = devinfo->codec->sc; 5210 struct hdac_audio_ctl *ctl; 5211 int i; 5212 5213 devinfo->function.audio.mvol = 100 | (100 << 8); 5214 i = 0; 5215 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5216 if (ctl->enable == 0 || ctl->widget == NULL) { 5217 HDA_BOOTVERBOSE( 5218 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5219 i, (ctl->widget != NULL) ? 5220 ctl->widget->nid : -1); 5221 if (ctl->childwidget != NULL) 5222 printf(" childnid=%d", 5223 ctl->childwidget->nid); 5224 if (ctl->widget == NULL) 5225 printf(" NULL WIDGET!"); 5226 printf(" DISABLED\n"); 5227 ); 5228 continue; 5229 } 5230 HDA_BOOTVERBOSE( 5231 if (ctl->ossmask == 0) { 5232 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5233 i, ctl->widget->nid); 5234 if (ctl->childwidget != NULL) 5235 printf(" childnid=%d", 5236 ctl->childwidget->nid); 5237 printf(" Bind to NONE\n"); 5238 } 5239 ); 5240 if (ctl->step > 0) { 5241 ctl->ossval = (ctl->left * 100) / ctl->step; 5242 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5243 } else 5244 ctl->ossval = 0; 5245 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5246 ctl->left, ctl->right); 5247 } 5248} 5249 5250static int 5251hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5252{ 5253 struct hdac_chan *ch; 5254 struct hdac_widget *w; 5255 uint32_t cap, fmtcap, pcmcap, path; 5256 int i, type, ret, max; 5257 5258 if (dir == PCMDIR_PLAY) { 5259 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5260 ch = &devinfo->codec->sc->play; 5261 path = HDA_DAC_PATH; 5262 } else { 5263 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5264 ch = &devinfo->codec->sc->rec; 5265 path = HDA_ADC_PATH; 5266 } 5267 5268 ch->caps = hdac_caps; 5269 ch->caps.fmtlist = ch->fmtlist; 5270 ch->bit16 = 1; 5271 ch->bit32 = 0; 5272 ch->pcmrates[0] = 48000; 5273 ch->pcmrates[1] = 0; 5274 5275 ret = 0; 5276 fmtcap = devinfo->function.audio.supp_stream_formats; 5277 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5278 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5279 5280 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5281 w = hdac_widget_get(devinfo, i); 5282 if (w == NULL || w->enable == 0 || w->type != type || 5283 !(w->pflags & path)) 5284 continue; 5285 cap = w->param.widget_cap; 5286 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5287 continue;*/ 5288 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5289 continue; 5290 cap = w->param.supp_stream_formats; 5291 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5292 } 5293 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5294 }*/ 5295 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5296 continue; 5297 if (ret == 0) { 5298 fmtcap = w->param.supp_stream_formats; 5299 pcmcap = w->param.supp_pcm_size_rate; 5300 } else { 5301 fmtcap &= w->param.supp_stream_formats; 5302 pcmcap &= w->param.supp_pcm_size_rate; 5303 } 5304 ch->io[ret++] = i; 5305 } 5306 ch->io[ret] = -1; 5307 5308 ch->supp_stream_formats = fmtcap; 5309 ch->supp_pcm_size_rate = pcmcap; 5310 5311 /* 5312 * 8bit = 0 5313 * 16bit = 1 5314 * 20bit = 2 5315 * 24bit = 3 5316 * 32bit = 4 5317 */ 5318 if (ret > 0) { 5319 cap = pcmcap; 5320 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5321 ch->bit16 = 1; 5322 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5323 ch->bit16 = 0; 5324 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5325 ch->bit32 = 4; 5326 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5327 ch->bit32 = 3; 5328 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5329 ch->bit32 = 2; 5330 i = 0; 5331 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5332 ch->fmtlist[i++] = AFMT_S16_LE; 5333 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5334 if (ch->bit32 > 0) { 5335 if (!(devinfo->function.audio.quirks & 5336 HDA_QUIRK_FORCESTEREO)) 5337 ch->fmtlist[i++] = AFMT_S32_LE; 5338 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5339 } 5340 ch->fmtlist[i] = 0; 5341 i = 0; 5342 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5343 ch->pcmrates[i++] = 8000; 5344 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5345 ch->pcmrates[i++] = 11025; 5346 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5347 ch->pcmrates[i++] = 16000; 5348 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5349 ch->pcmrates[i++] = 22050; 5350 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5351 ch->pcmrates[i++] = 32000; 5352 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5353 ch->pcmrates[i++] = 44100; 5354 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5355 ch->pcmrates[i++] = 48000; 5356 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5357 ch->pcmrates[i++] = 88200; 5358 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5359 ch->pcmrates[i++] = 96000; 5360 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5361 ch->pcmrates[i++] = 176400; 5362 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5363 ch->pcmrates[i++] = 192000; 5364 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5365 ch->pcmrates[i] = 0; 5366 if (i > 0) { 5367 ch->caps.minspeed = ch->pcmrates[0]; 5368 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5369 } 5370 } 5371 5372 return (ret); 5373} 5374 5375static void 5376hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5377{ 5378 struct hdac_audio_ctl *ctl; 5379 struct hdac_softc *sc = devinfo->codec->sc; 5380 int i; 5381 uint32_t fl = 0; 5382 5383 5384 if (flag == 0) { 5385 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5386 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5387 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5388 } 5389 5390 i = 0; 5391 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5392 if (ctl->enable == 0 || ctl->widget == NULL || 5393 ctl->widget->enable == 0 || (ctl->ossmask & 5394 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5395 continue; 5396 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5397 (flag != 0 && (ctl->ossmask & flag))) { 5398 if (banner != NULL) { 5399 device_printf(sc->dev, "\n"); 5400 device_printf(sc->dev, "%s\n", banner); 5401 } 5402 goto hdac_ctl_dump_it_all; 5403 } 5404 } 5405 5406 return; 5407 5408hdac_ctl_dump_it_all: 5409 i = 0; 5410 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5411 if (ctl->enable == 0 || ctl->widget == NULL || 5412 ctl->widget->enable == 0) 5413 continue; 5414 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5415 (flag != 0 && (ctl->ossmask & flag)))) 5416 continue; 5417 if (flag == 0) { 5418 device_printf(sc->dev, "\n"); 5419 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5420 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5421 } 5422 device_printf(sc->dev, " |\n"); 5423 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5424 ctl->widget->nid, ctl->index); 5425 if (ctl->childwidget != NULL) 5426 printf("(nid: %2d) ", ctl->childwidget->nid); 5427 else 5428 printf(" "); 5429 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5430 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5431 ctl->ossmask); 5432 } 5433} 5434 5435static void 5436hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5437{ 5438 uint32_t cap; 5439 5440 cap = fcap; 5441 if (cap != 0) { 5442 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5443 device_printf(sc->dev, " Format:"); 5444 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5445 printf(" AC3"); 5446 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5447 printf(" FLOAT32"); 5448 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5449 printf(" PCM"); 5450 printf("\n"); 5451 } 5452 cap = pcmcap; 5453 if (cap != 0) { 5454 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5455 device_printf(sc->dev, " PCM size:"); 5456 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5457 printf(" 8"); 5458 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5459 printf(" 16"); 5460 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5461 printf(" 20"); 5462 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5463 printf(" 24"); 5464 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5465 printf(" 32"); 5466 printf("\n"); 5467 device_printf(sc->dev, " PCM rate:"); 5468 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5469 printf(" 8"); 5470 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5471 printf(" 11"); 5472 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5473 printf(" 16"); 5474 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5475 printf(" 22"); 5476 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5477 printf(" 32"); 5478 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5479 printf(" 44"); 5480 printf(" 48"); 5481 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5482 printf(" 88"); 5483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5484 printf(" 96"); 5485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5486 printf(" 176"); 5487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5488 printf(" 192"); 5489 printf("\n"); 5490 } 5491} 5492 5493static void 5494hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5495{ 5496 uint32_t pincap, wcap; 5497 5498 pincap = w->wclass.pin.cap; 5499 wcap = w->param.widget_cap; 5500 5501 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5502 device_printf(sc->dev, " "); 5503 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5504 printf(" ISC"); 5505 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5506 printf(" TRQD"); 5507 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5508 printf(" PDC"); 5509 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5510 printf(" HP"); 5511 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5512 printf(" OUT"); 5513 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5514 printf(" IN"); 5515 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5516 printf(" BAL"); 5517 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5518 printf(" VREF["); 5519 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5520 printf(" 50"); 5521 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5522 printf(" 80"); 5523 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5524 printf(" 100"); 5525 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5526 printf(" GROUND"); 5527 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5528 printf(" HIZ"); 5529 printf(" ]"); 5530 } 5531 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5532 printf(" EAPD"); 5533 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5534 printf(" : UNSOL"); 5535 printf("\n"); 5536 device_printf(sc->dev, " Pin config: 0x%08x\n", 5537 w->wclass.pin.config); 5538 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5539 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5540 printf(" HP"); 5541 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5542 printf(" IN"); 5543 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5544 printf(" OUT"); 5545 printf("\n"); 5546} 5547 5548static void 5549hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5550{ 5551 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5552 device_printf(sc->dev, " " 5553 "mute=%d step=%d size=%d offset=%d\n", 5554 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5555 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5556 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5557 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5558} 5559 5560static void 5561hdac_dump_nodes(struct hdac_devinfo *devinfo) 5562{ 5563 struct hdac_softc *sc = devinfo->codec->sc; 5564 struct hdac_widget *w, *cw; 5565 int i, j; 5566 5567 device_printf(sc->dev, "\n"); 5568 device_printf(sc->dev, "Default Parameter\n"); 5569 device_printf(sc->dev, "-----------------\n"); 5570 hdac_dump_audio_formats(sc, 5571 devinfo->function.audio.supp_stream_formats, 5572 devinfo->function.audio.supp_pcm_size_rate); 5573 device_printf(sc->dev, " IN amp: 0x%08x\n", 5574 devinfo->function.audio.inamp_cap); 5575 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5576 devinfo->function.audio.outamp_cap); 5577 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5578 w = hdac_widget_get(devinfo, i); 5579 if (w == NULL) { 5580 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5581 continue; 5582 } 5583 device_printf(sc->dev, "\n"); 5584 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5585 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5586 "DIGITAL" : "ANALOG", 5587 (w->enable == 0) ? " [DISABLED]" : ""); 5588 device_printf(sc->dev, " name: %s\n", w->name); 5589 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5590 w->param.widget_cap); 5591 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5592 w->pflags); 5593 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5594 w->ctlflags); 5595 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5596 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5597 hdac_dump_audio_formats(sc, 5598 w->param.supp_stream_formats, 5599 w->param.supp_pcm_size_rate); 5600 } else if (w->type == 5601 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5602 hdac_dump_pin(sc, w); 5603 if (w->param.eapdbtl != HDAC_INVALID) 5604 device_printf(sc->dev, " EAPD: 0x%08x\n", 5605 w->param.eapdbtl); 5606 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5607 w->param.outamp_cap != 0) 5608 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5609 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5610 w->param.inamp_cap != 0) 5611 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5612 device_printf(sc->dev, " connections: %d\n", w->nconns); 5613 for (j = 0; j < w->nconns; j++) { 5614 cw = hdac_widget_get(devinfo, w->conns[j]); 5615 device_printf(sc->dev, " |\n"); 5616 device_printf(sc->dev, " + <- nid=%d [%s]", 5617 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5618 if (cw == NULL) 5619 printf(" [UNKNOWN]"); 5620 else if (cw->enable == 0) 5621 printf(" [DISABLED]"); 5622 if (w->nconns > 1 && w->selconn == j && w->type != 5623 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5624 printf(" (selected)"); 5625 printf("\n"); 5626 } 5627 } 5628 5629} 5630 5631static int 5632hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5633{ 5634 struct hdac_widget *w, *cw; 5635 struct hdac_softc *sc = devinfo->codec->sc; 5636 int i; 5637 5638 if (depth > HDA_PARSE_MAXDEPTH) 5639 return (0); 5640 5641 w = hdac_widget_get(devinfo, nid); 5642 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5643 return (0); 5644 5645 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5646 device_printf(sc->dev, "\n"); 5647 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5648 device_printf(sc->dev, " ^\n"); 5649 device_printf(sc->dev, " |\n"); 5650 device_printf(sc->dev, " +-----<------+\n"); 5651 } else { 5652 device_printf(sc->dev, " ^\n"); 5653 device_printf(sc->dev, " |\n"); 5654 device_printf(sc->dev, " "); 5655 printf(" nid=%d [%s]\n", w->nid, w->name); 5656 } 5657 5658 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5659 return (1); 5660 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5661 for (i = 0; i < w->nconns; i++) { 5662 cw = hdac_widget_get(devinfo, w->conns[i]); 5663 if (cw == NULL || cw->enable == 0 || cw->type == 5664 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5665 continue; 5666 if (hdac_dump_dac_internal(devinfo, cw->nid, 5667 depth + 1) != 0) 5668 return (1); 5669 } 5670 } else if ((w->type == 5671 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5672 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5673 w->selconn > -1 && w->selconn < w->nconns) { 5674 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5675 depth + 1) != 0) 5676 return (1); 5677 } 5678 5679 return (0); 5680} 5681 5682static void 5683hdac_dump_dac(struct hdac_devinfo *devinfo) 5684{ 5685 struct hdac_widget *w; 5686 struct hdac_softc *sc = devinfo->codec->sc; 5687 int i, printed = 0; 5688 5689 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5690 w = hdac_widget_get(devinfo, i); 5691 if (w == NULL || w->enable == 0) 5692 continue; 5693 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5694 !(w->pflags & HDA_DAC_PATH)) 5695 continue; 5696 if (printed == 0) { 5697 printed = 1; 5698 device_printf(sc->dev, "\n"); 5699 device_printf(sc->dev, "Playback path:\n"); 5700 } 5701 hdac_dump_dac_internal(devinfo, w->nid, 0); 5702 } 5703} 5704 5705static void 5706hdac_dump_adc(struct hdac_devinfo *devinfo) 5707{ 5708 struct hdac_widget *w, *cw; 5709 struct hdac_softc *sc = devinfo->codec->sc; 5710 int i, j; 5711 int printed = 0; 5712 char ossdevs[256]; 5713 5714 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5715 w = hdac_widget_get(devinfo, i); 5716 if (w == NULL || w->enable == 0) 5717 continue; 5718 if (!(w->pflags & HDA_ADC_RECSEL)) 5719 continue; 5720 if (printed == 0) { 5721 printed = 1; 5722 device_printf(sc->dev, "\n"); 5723 device_printf(sc->dev, "Recording sources:\n"); 5724 } 5725 device_printf(sc->dev, "\n"); 5726 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5727 for (j = 0; j < w->nconns; j++) { 5728 cw = hdac_widget_get(devinfo, w->conns[j]); 5729 if (cw == NULL || cw->enable == 0) 5730 continue; 5731 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5732 ossdevs, sizeof(ossdevs)); 5733 device_printf(sc->dev, " |\n"); 5734 device_printf(sc->dev, " + <- nid=%d [%s]", 5735 cw->nid, cw->name); 5736 if (strlen(ossdevs) > 0) { 5737 printf(" [recsrc: %s]", ossdevs); 5738 } 5739 printf("\n"); 5740 } 5741 } 5742} 5743 5744static void 5745hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5746{ 5747 nid_t *nids; 5748 5749 if (pcnt > 0) { 5750 device_printf(sc->dev, "\n"); 5751 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5752 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5753 sc->play.supp_pcm_size_rate); 5754 device_printf(sc->dev, " DAC:"); 5755 for (nids = sc->play.io; *nids != -1; nids++) 5756 printf(" %d", *nids); 5757 printf("\n"); 5758 } 5759 5760 if (rcnt > 0) { 5761 device_printf(sc->dev, "\n"); 5762 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5763 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5764 sc->rec.supp_pcm_size_rate); 5765 device_printf(sc->dev, " ADC:"); 5766 for (nids = sc->rec.io; *nids != -1; nids++) 5767 printf(" %d", *nids); 5768 printf("\n"); 5769 } 5770} 5771 5772static void 5773hdac_release_resources(struct hdac_softc *sc) 5774{ 5775 struct hdac_devinfo *devinfo = NULL; 5776 device_t *devlist = NULL; 5777 int i, devcount; 5778 5779 if (sc == NULL) 5780 return; 5781 5782 hdac_lock(sc); 5783 sc->polling = 0; 5784 sc->poll_ival = 0; 5785 callout_stop(&sc->poll_hda); 5786 callout_stop(&sc->poll_hdac); 5787 callout_stop(&sc->poll_jack); 5788 hdac_reset(sc); 5789 hdac_unlock(sc); 5790 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5791 callout_drain(&sc->poll_hda); 5792 callout_drain(&sc->poll_hdac); 5793 callout_drain(&sc->poll_jack); 5794 5795 hdac_irq_free(sc); 5796 5797 device_get_children(sc->dev, &devlist, &devcount); 5798 for (i = 0; devlist != NULL && i < devcount; i++) { 5799 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5800 if (devinfo == NULL) 5801 continue; 5802 if (devinfo->widget != NULL) 5803 free(devinfo->widget, M_HDAC); 5804 if (devinfo->node_type == 5805 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5806 devinfo->function.audio.ctl != NULL) 5807 free(devinfo->function.audio.ctl, M_HDAC); 5808 free(devinfo, M_HDAC); 5809 device_delete_child(sc->dev, devlist[i]); 5810 } 5811 if (devlist != NULL) 5812 free(devlist, M_TEMP); 5813 5814 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5815 if (sc->codecs[i] != NULL) 5816 free(sc->codecs[i], M_HDAC); 5817 sc->codecs[i] = NULL; 5818 } 5819 5820 hdac_dma_free(sc, &sc->pos_dma); 5821 hdac_dma_free(sc, &sc->rirb_dma); 5822 hdac_dma_free(sc, &sc->corb_dma); 5823 if (sc->play.blkcnt > 0) 5824 hdac_dma_free(sc, &sc->play.bdl_dma); 5825 if (sc->rec.blkcnt > 0) 5826 hdac_dma_free(sc, &sc->rec.bdl_dma); 5827 if (sc->chan_dmat != NULL) { 5828 bus_dma_tag_destroy(sc->chan_dmat); 5829 sc->chan_dmat = NULL; 5830 } 5831 hdac_mem_free(sc); 5832 snd_mtxfree(sc->lock); 5833 free(sc, M_DEVBUF); 5834} 5835 5836/* This function surely going to make its way into upper level someday. */ 5837static void 5838hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5839{ 5840 const char *res = NULL; 5841 int i = 0, j, k, len, inv; 5842 5843 if (on != NULL) 5844 *on = 0; 5845 if (off != NULL) 5846 *off = 0; 5847 if (sc == NULL) 5848 return; 5849 if (resource_string_value(device_get_name(sc->dev), 5850 device_get_unit(sc->dev), "config", &res) != 0) 5851 return; 5852 if (!(res != NULL && strlen(res) > 0)) 5853 return; 5854 HDA_BOOTVERBOSE( 5855 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5856 ); 5857 for (;;) { 5858 while (res[i] != '\0' && 5859 (res[i] == ',' || isspace(res[i]) != 0)) 5860 i++; 5861 if (res[i] == '\0') { 5862 HDA_BOOTVERBOSE( 5863 printf("\n"); 5864 ); 5865 return; 5866 } 5867 j = i; 5868 while (res[j] != '\0' && 5869 !(res[j] == ',' || isspace(res[j]) != 0)) 5870 j++; 5871 len = j - i; 5872 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5873 inv = 2; 5874 else 5875 inv = 0; 5876 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5877 if (strncmp(res + i + inv, 5878 hdac_quirks_tab[k].key, len - inv) != 0) 5879 continue; 5880 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5881 break; 5882 HDA_BOOTVERBOSE( 5883 printf(" %s%s", (inv != 0) ? "no" : "", 5884 hdac_quirks_tab[k].key); 5885 ); 5886 if (inv == 0 && on != NULL) 5887 *on |= hdac_quirks_tab[k].value; 5888 else if (inv != 0 && off != NULL) 5889 *off |= hdac_quirks_tab[k].value; 5890 break; 5891 } 5892 i = j; 5893 } 5894} 5895 5896#ifdef SND_DYNSYSCTL 5897static int 5898sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5899{ 5900 struct hdac_softc *sc; 5901 struct hdac_devinfo *devinfo; 5902 device_t dev; 5903 uint32_t ctl; 5904 int err, val; 5905 5906 dev = oidp->oid_arg1; 5907 devinfo = pcm_getdevinfo(dev); 5908 if (devinfo == NULL || devinfo->codec == NULL || 5909 devinfo->codec->sc == NULL) 5910 return (EINVAL); 5911 sc = devinfo->codec->sc; 5912 hdac_lock(sc); 5913 val = sc->polling; 5914 hdac_unlock(sc); 5915 err = sysctl_handle_int(oidp, &val, 0, req); 5916 5917 if (err != 0 || req->newptr == NULL) 5918 return (err); 5919 if (val < 0 || val > 1) 5920 return (EINVAL); 5921 5922 hdac_lock(sc); 5923 if (val != sc->polling) { 5924 if (hda_chan_active(sc) != 0) 5925 err = EBUSY; 5926 else if (val == 0) { 5927 callout_stop(&sc->poll_hdac); 5928 hdac_unlock(sc); 5929 callout_drain(&sc->poll_hdac); 5930 hdac_lock(sc); 5931 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5932 sc->rirb_size / 2); 5933 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5934 ctl |= HDAC_RIRBCTL_RINTCTL; 5935 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5936 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5937 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5938 sc->polling = 0; 5939 DELAY(1000); 5940 } else { 5941 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5942 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5943 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5944 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5945 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5946 hdac_unlock(sc); 5947 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5948 hdac_lock(sc); 5949 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5950 sc); 5951 sc->polling = 1; 5952 DELAY(1000); 5953 } 5954 } 5955 hdac_unlock(sc); 5956 5957 return (err); 5958} 5959 5960static int 5961sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5962{ 5963 struct hdac_softc *sc; 5964 struct hdac_devinfo *devinfo; 5965 device_t dev; 5966 int err, val; 5967 5968 dev = oidp->oid_arg1; 5969 devinfo = pcm_getdevinfo(dev); 5970 if (devinfo == NULL || devinfo->codec == NULL || 5971 devinfo->codec->sc == NULL) 5972 return (EINVAL); 5973 sc = devinfo->codec->sc; 5974 hdac_lock(sc); 5975 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5976 hdac_unlock(sc); 5977 err = sysctl_handle_int(oidp, &val, 0, req); 5978 5979 if (err != 0 || req->newptr == NULL) 5980 return (err); 5981 5982 if (val < 1) 5983 val = 1; 5984 if (val > 5000) 5985 val = 5000; 5986 val = ((uint64_t)val * hz) / 1000; 5987 if (val < 1) 5988 val = 1; 5989 if (val > (hz * 5)) 5990 val = hz * 5; 5991 5992 hdac_lock(sc); 5993 sc->poll_ival = val; 5994 hdac_unlock(sc); 5995 5996 return (err); 5997} 5998 5999#ifdef SND_DEBUG 6000static int 6001sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 6002{ 6003 struct hdac_softc *sc; 6004 struct hdac_devinfo *devinfo; 6005 struct hdac_widget *w; 6006 device_t dev; 6007 uint32_t res, pincap, timeout; 6008 int i, err, val; 6009 nid_t cad; 6010 6011 dev = oidp->oid_arg1; 6012 devinfo = pcm_getdevinfo(dev); 6013 if (devinfo == NULL || devinfo->codec == NULL || 6014 devinfo->codec->sc == NULL) 6015 return (EINVAL); 6016 val = 0; 6017 err = sysctl_handle_int(oidp, &val, 0, req); 6018 if (err != 0 || req->newptr == NULL || val == 0) 6019 return (err); 6020 sc = devinfo->codec->sc; 6021 cad = devinfo->codec->cad; 6022 hdac_lock(sc); 6023 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6024 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6025 w = hdac_widget_get(devinfo, i); 6026 if (w == NULL || w->type != 6027 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6028 continue; 6029 pincap = w->wclass.pin.cap; 6030 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6031 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6032 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6033 timeout = 10000; 6034 hdac_command(sc, 6035 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6036 do { 6037 res = hdac_command(sc, 6038 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6039 if (res != 0x7fffffff) 6040 break; 6041 DELAY(10); 6042 } while (--timeout != 0); 6043 } else { 6044 timeout = -1; 6045 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6046 w->nid), cad); 6047 } 6048 device_printf(dev, 6049 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6050 w->nid, timeout, res, 6051 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6052 } 6053 device_printf(dev, 6054 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6055 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6056 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6057 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6058 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6059 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6060 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6061 device_printf(dev, " GPI:"); 6062 res = hdac_command(sc, 6063 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6064 printf(" data=0x%08x", res); 6065 res = hdac_command(sc, 6066 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6067 cad); 6068 printf(" wake=0x%08x", res); 6069 res = hdac_command(sc, 6070 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6071 cad); 6072 printf(" unsol=0x%08x", res); 6073 res = hdac_command(sc, 6074 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6075 printf(" sticky=0x%08x\n", res); 6076 } 6077 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6078 device_printf(dev, " GPO:"); 6079 res = hdac_command(sc, 6080 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6081 printf(" data=0x%08x\n", res); 6082 } 6083 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6084 device_printf(dev, "GPI0:"); 6085 res = hdac_command(sc, 6086 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6087 printf(" data=0x%08x", res); 6088 res = hdac_command(sc, 6089 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6090 printf(" enable=0x%08x", res); 6091 res = hdac_command(sc, 6092 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6093 printf(" direction=0x%08x\n", res); 6094 res = hdac_command(sc, 6095 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6096 device_printf(dev, " wake=0x%08x", res); 6097 res = hdac_command(sc, 6098 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6099 cad); 6100 printf(" unsol=0x%08x", res); 6101 res = hdac_command(sc, 6102 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6103 printf(" sticky=0x%08x\n", res); 6104 } 6105 hdac_unlock(sc); 6106 return (0); 6107} 6108#endif 6109#endif 6110 6111static void 6112hdac_attach2(void *arg) 6113{ 6114 struct hdac_softc *sc; 6115 struct hdac_widget *w; 6116 struct hdac_audio_ctl *ctl; 6117 uint32_t quirks_on, quirks_off; 6118 int pcnt, rcnt, codec_index; 6119 int i; 6120 char status[SND_STATUSLEN]; 6121 device_t *devlist = NULL; 6122 int devcount; 6123 struct hdac_devinfo *devinfo = NULL; 6124 6125 sc = (struct hdac_softc *)arg; 6126 6127 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6128 6129 HDA_BOOTVERBOSE( 6130 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6131 quirks_on, quirks_off); 6132 ); 6133 6134 if (resource_int_value(device_get_name(sc->dev), 6135 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6136 switch (sc->pci_subvendor) { 6137 case GB_G33S2H_SUBVENDOR: 6138 codec_index = 2; 6139 break; 6140 default: 6141 codec_index = 0; 6142 break; 6143 } 6144 } 6145 6146 hdac_lock(sc); 6147 6148 /* Remove ourselves from the config hooks */ 6149 if (sc->intrhook.ich_func != NULL) { 6150 config_intrhook_disestablish(&sc->intrhook); 6151 sc->intrhook.ich_func = NULL; 6152 } 6153 6154 /* Start the corb and rirb engines */ 6155 HDA_BOOTVERBOSE( 6156 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6157 ); 6158 hdac_corb_start(sc); 6159 HDA_BOOTVERBOSE( 6160 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6161 ); 6162 hdac_rirb_start(sc); 6163 6164 HDA_BOOTVERBOSE( 6165 device_printf(sc->dev, 6166 "HDA_DEBUG: Enabling controller interrupt...\n"); 6167 ); 6168 if (sc->polling == 0) 6169 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6170 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6171 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6172 HDAC_GCTL_UNSOL); 6173 6174 DELAY(1000); 6175 6176 HDA_BOOTVERBOSE( 6177 device_printf(sc->dev, 6178 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6179 codec_index); 6180 ); 6181 hdac_scan_codecs(sc, codec_index); 6182 6183 device_get_children(sc->dev, &devlist, &devcount); 6184 for (i = 0; devlist != NULL && i < devcount; i++) { 6185 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6186 if (devinfo != NULL && devinfo->node_type == 6187 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6188 break; 6189 } else 6190 devinfo = NULL; 6191 } 6192 if (devlist != NULL) 6193 free(devlist, M_TEMP); 6194 6195 if (devinfo == NULL) { 6196 hdac_unlock(sc); 6197 device_printf(sc->dev, "Audio Function Group not found!\n"); 6198 hdac_release_resources(sc); 6199 return; 6200 } 6201 6202 HDA_BOOTVERBOSE( 6203 device_printf(sc->dev, 6204 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6205 devinfo->nid, devinfo->codec->cad); 6206 ); 6207 hdac_audio_parse(devinfo); 6208 HDA_BOOTVERBOSE( 6209 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6210 ); 6211 hdac_audio_ctl_parse(devinfo); 6212 HDA_BOOTVERBOSE( 6213 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6214 ); 6215 hdac_vendor_patch_parse(devinfo); 6216 if (quirks_on != 0) 6217 devinfo->function.audio.quirks |= quirks_on; 6218 if (quirks_off != 0) 6219 devinfo->function.audio.quirks &= ~quirks_off; 6220 6221 /* XXX Disable all DIGITAL path. */ 6222 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6223 w = hdac_widget_get(devinfo, i); 6224 if (w == NULL) 6225 continue; 6226 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6227 w->enable = 0; 6228 continue; 6229 } 6230 /* XXX Disable useless pin ? */ 6231 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6232 (w->wclass.pin.config & 6233 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6234 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6235 w->enable = 0; 6236 } 6237 i = 0; 6238 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6239 if (ctl->widget == NULL) 6240 continue; 6241 if (ctl->ossmask & SOUND_MASK_DISABLE) 6242 ctl->enable = 0; 6243 w = ctl->widget; 6244 if (w->enable == 0 || 6245 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6246 ctl->enable = 0; 6247 w = ctl->childwidget; 6248 if (w == NULL) 6249 continue; 6250 if (w->enable == 0 || 6251 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6252 ctl->enable = 0; 6253 } 6254 6255 HDA_BOOTVERBOSE( 6256 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6257 ); 6258 hdac_audio_build_tree(devinfo); 6259 6260 i = 0; 6261 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6262 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6263 ctl->ossmask = 0; 6264 } 6265 HDA_BOOTVERBOSE( 6266 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6267 ); 6268 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6269 HDA_BOOTVERBOSE( 6270 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6271 ); 6272 hdac_audio_ctl_commit(devinfo); 6273 6274 HDA_BOOTVERBOSE( 6275 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6276 ); 6277 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6278 HDA_BOOTVERBOSE( 6279 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6280 ); 6281 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6282 6283 hdac_unlock(sc); 6284 HDA_BOOTVERBOSE( 6285 device_printf(sc->dev, 6286 "HDA_DEBUG: OSS mixer initialization...\n"); 6287 ); 6288 6289 /* 6290 * There is no point of return after this. If the driver failed, 6291 * so be it. Let the detach procedure do all the cleanup. 6292 */ 6293 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6294 device_printf(sc->dev, "Can't register mixer\n"); 6295 6296 if (pcnt > 0) 6297 pcnt = 1; 6298 if (rcnt > 0) 6299 rcnt = 1; 6300 6301 HDA_BOOTVERBOSE( 6302 device_printf(sc->dev, 6303 "HDA_DEBUG: Registering PCM channels...\n"); 6304 ); 6305 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6306 device_printf(sc->dev, "Can't register PCM\n"); 6307 6308 sc->registered++; 6309 6310 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6311 hdac_dma_alloc(sc, &sc->pos_dma, 6312 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6313 HDA_BOOTVERBOSE( 6314 device_printf(sc->dev, 6315 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6316 ); 6317 } 6318 6319 for (i = 0; i < pcnt; i++) 6320 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6321 for (i = 0; i < rcnt; i++) 6322 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6323 6324#ifdef SND_DYNSYSCTL 6325 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6326 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6327 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6328 sysctl_hdac_polling, "I", "Enable polling mode"); 6329 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6330 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6331 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6332 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6333 "Controller/Jack Sense polling interval (1-1000 ms)"); 6334#ifdef SND_DEBUG 6335 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6336 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6337 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6338 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6339#endif 6340#endif 6341 6342 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6343 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6344 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6345 pcm_setstatus(sc->dev, status); 6346 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6347 HDA_BOOTVERBOSE( 6348 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6349 hdac_codec_id(devinfo)); 6350 ); 6351 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6352 HDA_DRV_TEST_REV); 6353 6354 HDA_BOOTVERBOSE( 6355 if (devinfo->function.audio.quirks != 0) { 6356 device_printf(sc->dev, "\n"); 6357 device_printf(sc->dev, "HDA config/quirks:"); 6358 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6359 if ((devinfo->function.audio.quirks & 6360 hdac_quirks_tab[i].value) == 6361 hdac_quirks_tab[i].value) 6362 printf(" %s", hdac_quirks_tab[i].key); 6363 } 6364 printf("\n"); 6365 } 6366 device_printf(sc->dev, "\n"); 6367 device_printf(sc->dev, "+-------------------+\n"); 6368 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6369 device_printf(sc->dev, "+-------------------+\n"); 6370 hdac_dump_nodes(devinfo); 6371 device_printf(sc->dev, "\n"); 6372 device_printf(sc->dev, "+------------------------+\n"); 6373 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6374 device_printf(sc->dev, "+------------------------+\n"); 6375 device_printf(sc->dev, "\n"); 6376 i = 0; 6377 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6378 device_printf(sc->dev, "%3d: nid=%d", i, 6379 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6380 if (ctl->childwidget != NULL) 6381 printf(" cnid=%d", ctl->childwidget->nid); 6382 printf(" dir=0x%x index=%d " 6383 "ossmask=0x%08x ossdev=%d%s\n", 6384 ctl->dir, ctl->index, 6385 ctl->ossmask, ctl->ossdev, 6386 (ctl->enable == 0) ? " [DISABLED]" : ""); 6387 } 6388 device_printf(sc->dev, "\n"); 6389 device_printf(sc->dev, "+-----------------------------------+\n"); 6390 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6391 device_printf(sc->dev, "+-----------------------------------+\n"); 6392 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6393 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6394 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6395 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6396 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6397 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6398 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6399 hdac_dump_ctls(devinfo, NULL, 0); 6400 hdac_dump_dac(devinfo); 6401 hdac_dump_adc(devinfo); 6402 device_printf(sc->dev, "\n"); 6403 device_printf(sc->dev, "+--------------------------------------+\n"); 6404 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6405 device_printf(sc->dev, "+--------------------------------------+\n"); 6406 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6407 ); 6408 6409 if (sc->polling != 0) { 6410 hdac_lock(sc); 6411 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6412 hdac_unlock(sc); 6413 } 6414} 6415 6416/**************************************************************************** 6417 * int hdac_detach(device_t) 6418 * 6419 * Detach and free up resources utilized by the hdac device. 6420 ****************************************************************************/ 6421static int 6422hdac_detach(device_t dev) 6423{ 6424 struct hdac_softc *sc = NULL; 6425 struct hdac_devinfo *devinfo = NULL; 6426 int err; 6427 6428 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6429 if (devinfo != NULL && devinfo->codec != NULL) 6430 sc = devinfo->codec->sc; 6431 if (sc == NULL) 6432 return (0); 6433 6434 if (sc->registered > 0) { 6435 err = pcm_unregister(dev); 6436 if (err != 0) 6437 return (err); 6438 } 6439 6440 hdac_release_resources(sc); 6441 6442 return (0); 6443} 6444 6445static device_method_t hdac_methods[] = { 6446 /* device interface */ 6447 DEVMETHOD(device_probe, hdac_probe), 6448 DEVMETHOD(device_attach, hdac_attach), 6449 DEVMETHOD(device_detach, hdac_detach), 6450 { 0, 0 } 6451}; 6452 6453static driver_t hdac_driver = { 6454 "pcm", 6455 hdac_methods, 6456 PCM_SOFTC_SIZE, 6457}; 6458 6459DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6460MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6461MODULE_VERSION(snd_hda, 1); 6462