hdac.c revision 174004
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sys/ctype.h> 75#include <sys/taskqueue.h> 76 77#include <dev/sound/pci/hda/hdac_private.h> 78#include <dev/sound/pci/hda/hdac_reg.h> 79#include <dev/sound/pci/hda/hda_reg.h> 80#include <dev/sound/pci/hda/hdac.h> 81 82#include "mixer_if.h" 83 84#define HDA_DRV_TEST_REV "20071122_0049" 85#define HDA_WIDGET_PARSER_REV 1 86 87SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 174004 2007-11-28 02:13:20Z ariff $"); 88 89#define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93} while(0) 94 95#if 1 96#undef HDAC_INTR_EXTRA 97#define HDAC_INTR_EXTRA 1 98#endif 99 100#define hdac_lock(sc) snd_mtxlock((sc)->lock) 101#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103#define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 106#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 107 (fl) == 0xffffffff || \ 108 (((fl) & 0xffff0000) == 0xffff0000 && \ 109 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 110 (((fl) & 0x0000ffff) == 0x0000ffff && \ 111 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 112#define HDA_MATCH_ALL 0xffffffff 113#define HDAC_INVALID 0xffffffff 114 115/* Default controller / jack sense poll: 250ms */ 116#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 117 118/* 119 * Make room for possible 4096 playback/record channels, in 100 years to come. 120 */ 121#define HDAC_TRIGGER_NONE 0x00000000 122#define HDAC_TRIGGER_PLAY 0x00000fff 123#define HDAC_TRIGGER_REC 0x00fff000 124#define HDAC_TRIGGER_UNSOL 0x80000000 125 126#define HDA_MODEL_CONSTRUCT(vendor, model) \ 127 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 128 129/* Controller models */ 130 131/* Intel */ 132#define INTEL_VENDORID 0x8086 133#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 134#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 135#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 136#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 137#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 138#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 139 140/* Nvidia */ 141#define NVIDIA_VENDORID 0x10de 142#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 143#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 144#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 145#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 146#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 147#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 148#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 149#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 150#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 151 152/* ATI */ 153#define ATI_VENDORID 0x1002 154#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 155#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 156#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 157 158/* VIA */ 159#define VIA_VENDORID 0x1106 160#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 161#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 162 163/* SiS */ 164#define SIS_VENDORID 0x1039 165#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 166#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 167 168/* OEM/subvendors */ 169 170/* Intel */ 171#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 172 173/* HP/Compaq */ 174#define HP_VENDORID 0x103c 175#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 176#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 177#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 178#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 179#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 180#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 181#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 182#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 183#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 184/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 185#define HP_NX6325_SUBVENDORX 0x103c30b0 186 187/* Dell */ 188#define DELL_VENDORID 0x1028 189#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 190#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 191#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 192#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 193#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 194 195/* Clevo */ 196#define CLEVO_VENDORID 0x1558 197#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 198#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 199 200/* Acer */ 201#define ACER_VENDORID 0x1025 202#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 203#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 204#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 205#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 206 207/* Asus */ 208#define ASUS_VENDORID 0x1043 209#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 210#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 211#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 212#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 213#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 214#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 215#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 216#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 217#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 218#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 219#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 220#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 221#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 222#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 223#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 224 225/* IBM / Lenovo */ 226#define IBM_VENDORID 0x1014 227#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 228#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 229 230/* Lenovo */ 231#define LENOVO_VENDORID 0x17aa 232#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 233#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 234#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 235 236/* Samsung */ 237#define SAMSUNG_VENDORID 0x144d 238#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 239#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 240 241/* Medion ? */ 242#define MEDION_VENDORID 0x161f 243#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 244#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 245 246/* Apple Computer Inc. */ 247#define APPLE_VENDORID 0x106b 248#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 249 250/* 251 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 252 * instead of their own, which is beyond my comprehension 253 * (see HDA_CODEC_STAC9221 below). 254 */ 255#define APPLE_INTEL_MAC 0x76808384 256 257/* LG Electronics */ 258#define LG_VENDORID 0x1854 259#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 260#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 261 262/* Fujitsu Siemens */ 263#define FS_VENDORID 0x1734 264#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 265#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 266#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 267 268/* Fujitsu Limited */ 269#define FL_VENDORID 0x10cf 270#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 271#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 272 273/* Toshiba */ 274#define TOSHIBA_VENDORID 0x1179 275#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 276#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 277#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 278 279/* Micro-Star International (MSI) */ 280#define MSI_VENDORID 0x1462 281#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 282#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 283#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 284 285/* Giga-Byte Technology */ 286#define GB_VENDORID 0x1458 287#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 288#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 289 290/* Uniwill ? */ 291#define UNIWILL_VENDORID 0x1584 292#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 293#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 294 295 296/* Misc constants.. */ 297#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 298#define HDA_AMP_MUTE_NONE (0) 299#define HDA_AMP_MUTE_LEFT (1 << 0) 300#define HDA_AMP_MUTE_RIGHT (1 << 1) 301#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 302 303#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 304#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 305 306#define HDA_DAC_PATH (1 << 0) 307#define HDA_ADC_PATH (1 << 1) 308#define HDA_ADC_RECSEL (1 << 2) 309 310#define HDA_DAC_LOCKED (1 << 3) 311#define HDA_ADC_LOCKED (1 << 4) 312 313#define HDA_CTL_OUT (1 << 0) 314#define HDA_CTL_IN (1 << 1) 315#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 316 317#define HDA_GPIO_MAX 8 318/* 0 - 7 = GPIO , 8 = Flush */ 319#define HDA_QUIRK_GPIO0 (1 << 0) 320#define HDA_QUIRK_GPIO1 (1 << 1) 321#define HDA_QUIRK_GPIO2 (1 << 2) 322#define HDA_QUIRK_GPIO3 (1 << 3) 323#define HDA_QUIRK_GPIO4 (1 << 4) 324#define HDA_QUIRK_GPIO5 (1 << 5) 325#define HDA_QUIRK_GPIO6 (1 << 6) 326#define HDA_QUIRK_GPIO7 (1 << 7) 327#define HDA_QUIRK_GPIOFLUSH (1 << 8) 328 329/* 9 - 25 = anything else */ 330#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 331#define HDA_QUIRK_FIXEDRATE (1 << 10) 332#define HDA_QUIRK_FORCESTEREO (1 << 11) 333#define HDA_QUIRK_EAPDINV (1 << 12) 334#define HDA_QUIRK_DMAPOS (1 << 13) 335 336/* 26 - 31 = vrefs */ 337#define HDA_QUIRK_IVREF50 (1 << 26) 338#define HDA_QUIRK_IVREF80 (1 << 27) 339#define HDA_QUIRK_IVREF100 (1 << 28) 340#define HDA_QUIRK_OVREF50 (1 << 29) 341#define HDA_QUIRK_OVREF80 (1 << 30) 342#define HDA_QUIRK_OVREF100 (1 << 31) 343 344#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 345 HDA_QUIRK_IVREF100) 346#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 347 HDA_QUIRK_OVREF100) 348#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 349 350#define SOUND_MASK_SKIP (1 << 30) 351#define SOUND_MASK_DISABLE (1 << 31) 352 353#if __FreeBSD_version < 600000 354#define taskqueue_drain(...) 355#endif 356 357static const struct { 358 char *key; 359 uint32_t value; 360} hdac_quirks_tab[] = { 361 { "gpio0", HDA_QUIRK_GPIO0 }, 362 { "gpio1", HDA_QUIRK_GPIO1 }, 363 { "gpio2", HDA_QUIRK_GPIO2 }, 364 { "gpio3", HDA_QUIRK_GPIO3 }, 365 { "gpio4", HDA_QUIRK_GPIO4 }, 366 { "gpio5", HDA_QUIRK_GPIO5 }, 367 { "gpio6", HDA_QUIRK_GPIO6 }, 368 { "gpio7", HDA_QUIRK_GPIO7 }, 369 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 370 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 371 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 372 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 373 { "eapdinv", HDA_QUIRK_EAPDINV }, 374 { "dmapos", HDA_QUIRK_DMAPOS }, 375 { "ivref50", HDA_QUIRK_IVREF50 }, 376 { "ivref80", HDA_QUIRK_IVREF80 }, 377 { "ivref100", HDA_QUIRK_IVREF100 }, 378 { "ovref50", HDA_QUIRK_OVREF50 }, 379 { "ovref80", HDA_QUIRK_OVREF80 }, 380 { "ovref100", HDA_QUIRK_OVREF100 }, 381 { "ivref", HDA_QUIRK_IVREF }, 382 { "ovref", HDA_QUIRK_OVREF }, 383 { "vref", HDA_QUIRK_VREF }, 384}; 385#define HDAC_QUIRKS_TAB_LEN \ 386 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 387 388#define HDA_BDL_MIN 2 389#define HDA_BDL_MAX 256 390#define HDA_BDL_DEFAULT HDA_BDL_MIN 391 392#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 393#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 394 395#define HDA_BUFSZ_MIN 4096 396#define HDA_BUFSZ_MAX 65536 397#define HDA_BUFSZ_DEFAULT 16384 398 399#define HDA_PARSE_MAXDEPTH 10 400 401#define HDAC_UNSOLTAG_EVENT_HP 0x00 402#define HDAC_UNSOLTAG_EVENT_TEST 0x01 403 404MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 405 406enum { 407 HDA_PARSE_MIXER, 408 HDA_PARSE_DIRECT 409}; 410 411/* Default */ 412static uint32_t hdac_fmt[] = { 413 AFMT_STEREO | AFMT_S16_LE, 414 0 415}; 416 417static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 418 419static const struct { 420 uint32_t model; 421 char *desc; 422} hdac_devices[] = { 423 { HDA_INTEL_82801F, "Intel 82801F" }, 424 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 425 { HDA_INTEL_82801G, "Intel 82801G" }, 426 { HDA_INTEL_82801H, "Intel 82801H" }, 427 { HDA_INTEL_82801I, "Intel 82801I" }, 428 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 429 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 430 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 431 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 432 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 433 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 434 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 435 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 436 { HDA_ATI_SB450, "ATI SB450" }, 437 { HDA_ATI_SB600, "ATI SB600" }, 438 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 439 { HDA_SIS_966, "SiS 966" }, 440 /* Unknown */ 441 { HDA_INTEL_ALL, "Intel (Unknown)" }, 442 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 443 { HDA_ATI_ALL, "ATI (Unknown)" }, 444 { HDA_VIA_ALL, "VIA (Unknown)" }, 445 { HDA_SIS_ALL, "SiS (Unknown)" }, 446}; 447#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 448 449static const struct { 450 uint16_t vendor; 451 uint8_t reg; 452 uint8_t mask; 453 uint8_t enable; 454} hdac_pcie_snoop[] = { 455 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 456 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 457 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 458}; 459#define HDAC_PCIESNOOP_LEN \ 460 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 461 462static const struct { 463 uint32_t rate; 464 int valid; 465 uint16_t base; 466 uint16_t mul; 467 uint16_t div; 468} hda_rate_tab[] = { 469 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 470 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 471 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 472 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 473 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 474 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 475 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 476 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 477 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 478 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 479 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 480 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 481 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 482 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 483 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 484 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 485 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 486 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 487 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 488 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 489 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 490 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 491 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 492 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 493 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 494 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 495 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 496 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 497 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 498 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 499 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 500 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 501 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 502 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 503 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 504}; 505#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 506 507/* All codecs you can eat... */ 508#define HDA_CODEC_CONSTRUCT(vendor, id) \ 509 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 510 511/* Realtek */ 512#define REALTEK_VENDORID 0x10ec 513#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 514#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 515#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 516#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 517#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 518#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 519#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 520#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 521#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 522#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 523#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 524#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 525 526/* Analog Devices */ 527#define ANALOGDEVICES_VENDORID 0x11d4 528#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 529#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 530#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 531#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 532#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 533#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 534 535/* CMedia */ 536#define CMEDIA_VENDORID 0x434d 537#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 538#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 539 540/* Sigmatel */ 541#define SIGMATEL_VENDORID 0x8384 542#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 543#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 544#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 545#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 546#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 547#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 548#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 549 550/* 551 * Conexant 552 * 553 * Ok, the truth is, I don't have any idea at all whether 554 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 555 * place that tell me it is "Venice" is from its Windows driver INF. 556 * 557 * Venice - CX????? 558 * Waikiki - CX20551-22 559 */ 560#define CONEXANT_VENDORID 0x14f1 561#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 562#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 563#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 564 565/* VIA */ 566#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 567#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 568#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 569#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 570#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 571#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 572#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 573#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 574#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 575#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 576#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 577#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 578#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 579 580 581/* Codecs */ 582static const struct { 583 uint32_t id; 584 char *name; 585} hdac_codecs[] = { 586 { HDA_CODEC_ALC260, "Realtek ALC260" }, 587 { HDA_CODEC_ALC262, "Realtek ALC262" }, 588 { HDA_CODEC_ALC268, "Realtek ALC268" }, 589 { HDA_CODEC_ALC660, "Realtek ALC660" }, 590 { HDA_CODEC_ALC861, "Realtek ALC861" }, 591 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 592 { HDA_CODEC_ALC880, "Realtek ALC880" }, 593 { HDA_CODEC_ALC882, "Realtek ALC882" }, 594 { HDA_CODEC_ALC883, "Realtek ALC883" }, 595 { HDA_CODEC_ALC885, "Realtek ALC885" }, 596 { HDA_CODEC_ALC888, "Realtek ALC888" }, 597 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 598 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 599 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 600 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 601 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 602 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 603 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 604 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 605 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 606 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 607 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 608 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 609 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 610 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 611 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 612 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 613 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 614 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 615 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 616 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 617 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 618 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 619 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 620 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 621 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 622 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 623 /* Unknown codec */ 624 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 625 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 626 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 627 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 628 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 629 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 630}; 631#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 632 633enum { 634 HDAC_HP_SWITCH_CTL, 635 HDAC_HP_SWITCH_CTRL, 636 HDAC_HP_SWITCH_DEBUG 637}; 638 639static const struct { 640 uint32_t model; 641 uint32_t id; 642 int type; 643 int inverted; 644 int polling; 645 int execsense; 646 nid_t hpnid; 647 nid_t spkrnid[8]; 648 nid_t eapdnid; 649} hdac_hp_switch[] = { 650 /* Specific OEM models */ 651 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 652 0, 0, -1, 17, { 16, -1 }, 16 }, 653 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 654 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 655 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 656 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 657 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 658 0, 0, -1, 6, { 5, -1 }, 5 }, 659 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 660 0, 0, -1, 6, { 5, -1 }, 5 }, 661 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 662 0, 0, -1, 6, { 5, -1 }, 5 }, 663 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 664 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 665 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 666 0, 0, -1, 6, { 5, -1 }, -1 }, 667 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 668 0, 0, -1, 27, { 20, -1 }, -1 }, 669 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 670 0, 0, -1, 13, { 14, -1 }, -1 }, 671 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 672 0, 0, -1, 13, { 14, -1 }, -1 }, 673 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 674 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 675 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 676 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 677 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 678 0, 0, -1, 10, { 13, -1 }, -1 }, 679 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 680 1, 0, -1, 26, { 27, -1 }, -1 }, 681 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 682 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 683 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 684 0, 0, -1, 27, { 20, -1 }, -1 }, 685 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 686 0, 0, -1, 20, { 21, -1 }, -1 }, 687 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 688 0, 0, -1, 20, { 21, -1 }, -1 }, 689 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 690 0, 0, -1, 20, { 21, -1 }, -1 }, 691 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 692 0, 0, -1, 20, { 21, -1 }, -1 }, 693 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 694 0, 0, -1, 20, { 27, -1 }, -1 }, 695 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 696 0, 0, -1, 20, { 27, -1 }, -1 }, 697 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 698 0, 0, -1, 20, { 21, -1 }, -1 }, 699 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 700 0, 0, -1, 20, { 16, -1 }, -1 }, 701 /* 702 * All models that at least come from the same vendor with 703 * simmilar codec. 704 */ 705 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 706 0, 0, -1, 17, { 16, -1 }, 16 }, 707 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 708 0, 0, -1, 6, { 5, -1 }, 5 }, 709 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 710 0, 0, -1, 6, { 5, -1 }, -1 }, 711 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 712 0, 0, -1, 13, { 14, -1 }, -1 }, 713#if 0 714 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 715 1, 0, -1, 26, { 27, -1 }, -1 }, 716 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 717 0, 0, -1, 20, { 21, -1 }, -1 }, 718#endif 719}; 720#define HDAC_HP_SWITCH_LEN \ 721 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 722 723static const struct { 724 uint32_t model; 725 uint32_t id; 726 nid_t eapdnid; 727 int hp_switch; 728} hdac_eapd_switch[] = { 729 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 730 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 731 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 732}; 733#define HDAC_EAPD_SWITCH_LEN \ 734 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 735 736/**************************************************************************** 737 * Function prototypes 738 ****************************************************************************/ 739static void hdac_intr_handler(void *); 740static int hdac_reset(struct hdac_softc *); 741static int hdac_get_capabilities(struct hdac_softc *); 742static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 743static int hdac_dma_alloc(struct hdac_softc *, 744 struct hdac_dma *, bus_size_t); 745static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 746static int hdac_mem_alloc(struct hdac_softc *); 747static void hdac_mem_free(struct hdac_softc *); 748static int hdac_irq_alloc(struct hdac_softc *); 749static void hdac_irq_free(struct hdac_softc *); 750static void hdac_corb_init(struct hdac_softc *); 751static void hdac_rirb_init(struct hdac_softc *); 752static void hdac_corb_start(struct hdac_softc *); 753static void hdac_rirb_start(struct hdac_softc *); 754static void hdac_scan_codecs(struct hdac_softc *, int); 755static int hdac_probe_codec(struct hdac_codec *); 756static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 757static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 758 759static void hdac_attach2(void *); 760 761static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 762 uint32_t, int); 763static void hdac_command_send_internal(struct hdac_softc *, 764 struct hdac_command_list *, int); 765 766static int hdac_probe(device_t); 767static int hdac_attach(device_t); 768static int hdac_detach(device_t); 769static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 770static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 771 uint32_t, int, int); 772static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 773 nid_t, int, int); 774static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 775 nid_t, nid_t, int, int, int, int, int, int); 776static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 777static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 778 779static int hdac_rirb_flush(struct hdac_softc *sc); 780static int hdac_unsolq_flush(struct hdac_softc *sc); 781 782#define hdac_command(a1, a2, a3) \ 783 hdac_command_sendone_internal(a1, a2, a3) 784 785#define hdac_codec_id(d) \ 786 ((uint32_t)((d == NULL) ? 0x00000000 : \ 787 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 788 ((uint32_t)(d)->device_id & 0x0000ffff)))) 789 790static char * 791hdac_codec_name(struct hdac_devinfo *devinfo) 792{ 793 uint32_t id; 794 int i; 795 796 id = hdac_codec_id(devinfo); 797 798 for (i = 0; i < HDAC_CODECS_LEN; i++) { 799 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 800 return (hdac_codecs[i].name); 801 } 802 803 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 804} 805 806static char * 807hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 808{ 809 static char *ossname[] = SOUND_DEVICE_NAMES; 810 static char *unknown = "???"; 811 int i; 812 813 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 814 if (devmask & (1 << i)) 815 return (ossname[i]); 816 } 817 return (unknown); 818} 819 820static void 821hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 822{ 823 static char *ossname[] = SOUND_DEVICE_NAMES; 824 int i, first = 1; 825 826 bzero(buf, len); 827 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 828 if (mask & (1 << i)) { 829 if (first == 0) 830 strlcat(buf, ", ", len); 831 strlcat(buf, ossname[i], len); 832 first = 0; 833 } 834 } 835} 836 837static struct hdac_audio_ctl * 838hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 839{ 840 if (devinfo == NULL || 841 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 842 index == NULL || devinfo->function.audio.ctl == NULL || 843 devinfo->function.audio.ctlcnt < 1 || 844 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 845 return (NULL); 846 return (&devinfo->function.audio.ctl[(*index)++]); 847} 848 849static struct hdac_audio_ctl * 850hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 851 int index, int cnt) 852{ 853 struct hdac_audio_ctl *ctl, *retctl = NULL; 854 int i, at, atindex, found = 0; 855 856 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 857 return (NULL); 858 859 at = cnt; 860 if (at == 0) 861 at = 1; 862 else if (at < 0) 863 at = -1; 864 atindex = index; 865 if (atindex < 0) 866 atindex = -1; 867 868 i = 0; 869 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 870 if (ctl->enable == 0 || ctl->widget == NULL) 871 continue; 872 if (!(ctl->widget->nid == nid && (atindex == -1 || 873 ctl->index == atindex))) 874 continue; 875 found++; 876 if (found == cnt) 877 return (ctl); 878 retctl = ctl; 879 } 880 881 return ((at == -1) ? retctl : NULL); 882} 883 884static void 885hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 886{ 887 struct hdac_softc *sc; 888 struct hdac_widget *w; 889 struct hdac_audio_ctl *ctl; 890 uint32_t val, id, res; 891 int i = 0, j, timeout, forcemute; 892 nid_t cad; 893 894 if (devinfo == NULL || devinfo->codec == NULL || 895 devinfo->codec->sc == NULL) 896 return; 897 898 sc = devinfo->codec->sc; 899 cad = devinfo->codec->cad; 900 id = hdac_codec_id(devinfo); 901 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 902 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 903 sc->pci_subvendor) && 904 hdac_hp_switch[i].id == id) 905 break; 906 } 907 908 if (i >= HDAC_HP_SWITCH_LEN) 909 return; 910 911 forcemute = 0; 912 if (hdac_hp_switch[i].eapdnid != -1) { 913 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 914 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 915 forcemute = (w->param.eapdbtl & 916 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 917 } 918 919 if (hdac_hp_switch[i].execsense != -1) 920 hdac_command(sc, 921 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 922 hdac_hp_switch[i].execsense), cad); 923 924 timeout = 10000; 925 do { 926 res = hdac_command(sc, 927 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 928 cad); 929 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 930 break; 931 DELAY(10); 932 } while (--timeout != 0); 933 934 HDA_BOOTVERBOSE( 935 device_printf(sc->dev, 936 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 937 hdac_hp_switch[i].hpnid, timeout, res); 938 ); 939 940 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 941 res ^= hdac_hp_switch[i].inverted; 942 943 switch (hdac_hp_switch[i].type) { 944 case HDAC_HP_SWITCH_CTL: 945 ctl = hdac_audio_ctl_amp_get(devinfo, 946 hdac_hp_switch[i].hpnid, 0, 1); 947 if (ctl != NULL) { 948 val = (res != 0 && forcemute == 0) ? 949 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 950 if (val != ctl->muted) { 951 ctl->muted = val; 952 hdac_audio_ctl_amp_set(ctl, 953 HDA_AMP_MUTE_DEFAULT, ctl->left, 954 ctl->right); 955 } 956 } 957 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 958 ctl = hdac_audio_ctl_amp_get(devinfo, 959 hdac_hp_switch[i].spkrnid[j], 0, 1); 960 if (ctl == NULL) 961 continue; 962 val = (res != 0 || forcemute == 1) ? 963 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 964 if (val == ctl->muted) 965 continue; 966 ctl->muted = val; 967 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 968 ctl->left, ctl->right); 969 } 970 break; 971 case HDAC_HP_SWITCH_CTRL: 972 if (res != 0) { 973 /* HP in */ 974 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 975 if (w != NULL && w->type == 976 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 977 if (forcemute == 0) 978 val = w->wclass.pin.ctrl | 979 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 980 else 981 val = w->wclass.pin.ctrl & 982 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 983 if (val != w->wclass.pin.ctrl) { 984 w->wclass.pin.ctrl = val; 985 hdac_command(sc, 986 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 987 w->nid, w->wclass.pin.ctrl), cad); 988 } 989 } 990 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 991 w = hdac_widget_get(devinfo, 992 hdac_hp_switch[i].spkrnid[j]); 993 if (w == NULL || w->type != 994 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 995 continue; 996 val = w->wclass.pin.ctrl & 997 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 998 if (val == w->wclass.pin.ctrl) 999 continue; 1000 w->wclass.pin.ctrl = val; 1001 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1002 cad, w->nid, w->wclass.pin.ctrl), cad); 1003 } 1004 } else { 1005 /* HP out */ 1006 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1007 if (w != NULL && w->type == 1008 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1009 val = w->wclass.pin.ctrl & 1010 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1011 if (val != w->wclass.pin.ctrl) { 1012 w->wclass.pin.ctrl = val; 1013 hdac_command(sc, 1014 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1015 w->nid, w->wclass.pin.ctrl), cad); 1016 } 1017 } 1018 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1019 w = hdac_widget_get(devinfo, 1020 hdac_hp_switch[i].spkrnid[j]); 1021 if (w == NULL || w->type != 1022 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1023 continue; 1024 if (forcemute == 0) 1025 val = w->wclass.pin.ctrl | 1026 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1027 else 1028 val = w->wclass.pin.ctrl & 1029 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1030 if (val == w->wclass.pin.ctrl) 1031 continue; 1032 w->wclass.pin.ctrl = val; 1033 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1034 cad, w->nid, w->wclass.pin.ctrl), cad); 1035 } 1036 } 1037 break; 1038 case HDAC_HP_SWITCH_DEBUG: 1039 if (hdac_hp_switch[i].execsense != -1) 1040 hdac_command(sc, 1041 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1042 hdac_hp_switch[i].execsense), cad); 1043 res = hdac_command(sc, 1044 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1045 device_printf(sc->dev, 1046 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1047 hdac_hp_switch[i].hpnid, res); 1048 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1049 w = hdac_widget_get(devinfo, 1050 hdac_hp_switch[i].spkrnid[j]); 1051 if (w == NULL || w->type != 1052 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1053 continue; 1054 if (hdac_hp_switch[i].execsense != -1) 1055 hdac_command(sc, 1056 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1057 hdac_hp_switch[i].execsense), cad); 1058 res = hdac_command(sc, 1059 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1060 device_printf(sc->dev, 1061 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1062 j + 1, w->nid, res); 1063 } 1064 break; 1065 default: 1066 break; 1067 } 1068} 1069 1070static void 1071hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1072{ 1073 struct hdac_softc *sc; 1074 struct hdac_devinfo *devinfo = NULL; 1075 device_t *devlist = NULL; 1076 int devcount, i; 1077 1078 if (codec == NULL || codec->sc == NULL) 1079 return; 1080 1081 sc = codec->sc; 1082 1083 HDA_BOOTVERBOSE( 1084 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1085 ); 1086 1087 device_get_children(sc->dev, &devlist, &devcount); 1088 for (i = 0; devlist != NULL && i < devcount; i++) { 1089 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1090 if (devinfo != NULL && devinfo->node_type == 1091 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1092 devinfo->codec != NULL && 1093 devinfo->codec->cad == codec->cad) { 1094 break; 1095 } else 1096 devinfo = NULL; 1097 } 1098 if (devlist != NULL) 1099 free(devlist, M_TEMP); 1100 1101 if (devinfo == NULL) 1102 return; 1103 1104 switch (tag) { 1105 case HDAC_UNSOLTAG_EVENT_HP: 1106 hdac_hp_switch_handler(devinfo); 1107 break; 1108 case HDAC_UNSOLTAG_EVENT_TEST: 1109 device_printf(sc->dev, "Unsol Test!\n"); 1110 break; 1111 default: 1112 break; 1113 } 1114} 1115 1116static int 1117hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1118{ 1119 /* XXX to be removed */ 1120#ifdef HDAC_INTR_EXTRA 1121 uint32_t res; 1122#endif 1123 1124 if (!(ch->flags & HDAC_CHN_RUNNING)) 1125 return (0); 1126 1127 /* XXX to be removed */ 1128#ifdef HDAC_INTR_EXTRA 1129 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1130#endif 1131 1132 /* XXX to be removed */ 1133#ifdef HDAC_INTR_EXTRA 1134 HDA_BOOTVERBOSE( 1135 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1136 device_printf(sc->dev, 1137 "PCMDIR_%s intr triggered beyond stream boundary:" 1138 "%08x\n", 1139 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1140 ); 1141#endif 1142 1143 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1144 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1145 1146 /* XXX to be removed */ 1147#ifdef HDAC_INTR_EXTRA 1148 if (res & HDAC_SDSTS_BCIS) { 1149#endif 1150 return (1); 1151 /* XXX to be removed */ 1152#ifdef HDAC_INTR_EXTRA 1153 } 1154#endif 1155 1156 return (0); 1157} 1158 1159/**************************************************************************** 1160 * void hdac_intr_handler(void *) 1161 * 1162 * Interrupt handler. Processes interrupts received from the hdac. 1163 ****************************************************************************/ 1164static void 1165hdac_intr_handler(void *context) 1166{ 1167 struct hdac_softc *sc; 1168 uint32_t intsts; 1169 uint8_t rirbsts; 1170 struct hdac_rirb *rirb_base; 1171 uint32_t trigger; 1172 1173 sc = (struct hdac_softc *)context; 1174 1175 hdac_lock(sc); 1176 if (sc->polling != 0) { 1177 hdac_unlock(sc); 1178 return; 1179 } 1180 1181 /* Do we have anything to do? */ 1182 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1183 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1184 hdac_unlock(sc); 1185 return; 1186 } 1187 1188 trigger = 0; 1189 1190 /* Was this a controller interrupt? */ 1191 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1192 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1193 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1194 /* Get as many responses that we can */ 1195 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1196 HDAC_WRITE_1(&sc->mem, 1197 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1198 if (hdac_rirb_flush(sc) != 0) 1199 trigger |= HDAC_TRIGGER_UNSOL; 1200 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1201 } 1202 /* XXX to be removed */ 1203 /* Clear interrupt and exit */ 1204#ifdef HDAC_INTR_EXTRA 1205 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1206#endif 1207 } 1208 1209 if (intsts & HDAC_INTSTS_SIS_MASK) { 1210 if ((intsts & (1 << sc->num_iss)) && 1211 hdac_stream_intr(sc, &sc->play) != 0) 1212 trigger |= HDAC_TRIGGER_PLAY; 1213 if ((intsts & (1 << 0)) && 1214 hdac_stream_intr(sc, &sc->rec) != 0) 1215 trigger |= HDAC_TRIGGER_REC; 1216 /* XXX to be removed */ 1217#ifdef HDAC_INTR_EXTRA 1218 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1219 HDAC_INTSTS_SIS_MASK); 1220#endif 1221 } 1222 1223 hdac_unlock(sc); 1224 1225 if (trigger & HDAC_TRIGGER_PLAY) 1226 chn_intr(sc->play.c); 1227 if (trigger & HDAC_TRIGGER_REC) 1228 chn_intr(sc->rec.c); 1229 if (trigger & HDAC_TRIGGER_UNSOL) 1230 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1231} 1232 1233/**************************************************************************** 1234 * int hdac_reset(hdac_softc *) 1235 * 1236 * Reset the hdac to a quiescent and known state. 1237 ****************************************************************************/ 1238static int 1239hdac_reset(struct hdac_softc *sc) 1240{ 1241 uint32_t gctl; 1242 int count, i; 1243 1244 /* 1245 * Stop all Streams DMA engine 1246 */ 1247 for (i = 0; i < sc->num_iss; i++) 1248 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1249 for (i = 0; i < sc->num_oss; i++) 1250 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1251 for (i = 0; i < sc->num_bss; i++) 1252 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1253 1254 /* 1255 * Stop Control DMA engines. 1256 */ 1257 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1258 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1259 1260 /* 1261 * Reset DMA position buffer. 1262 */ 1263 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1264 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1265 1266 /* 1267 * Reset the controller. The reset must remain asserted for 1268 * a minimum of 100us. 1269 */ 1270 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1271 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1272 count = 10000; 1273 do { 1274 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1275 if (!(gctl & HDAC_GCTL_CRST)) 1276 break; 1277 DELAY(10); 1278 } while (--count); 1279 if (gctl & HDAC_GCTL_CRST) { 1280 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1281 return (ENXIO); 1282 } 1283 DELAY(100); 1284 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1285 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1286 count = 10000; 1287 do { 1288 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1289 if (gctl & HDAC_GCTL_CRST) 1290 break; 1291 DELAY(10); 1292 } while (--count); 1293 if (!(gctl & HDAC_GCTL_CRST)) { 1294 device_printf(sc->dev, "Device stuck in reset\n"); 1295 return (ENXIO); 1296 } 1297 1298 /* 1299 * Wait for codecs to finish their own reset sequence. The delay here 1300 * should be of 250us but for some reasons, on it's not enough on my 1301 * computer. Let's use twice as much as necessary to make sure that 1302 * it's reset properly. 1303 */ 1304 DELAY(1000); 1305 1306 return (0); 1307} 1308 1309 1310/**************************************************************************** 1311 * int hdac_get_capabilities(struct hdac_softc *); 1312 * 1313 * Retreive the general capabilities of the hdac; 1314 * Number of Input Streams 1315 * Number of Output Streams 1316 * Number of bidirectional Streams 1317 * 64bit ready 1318 * CORB and RIRB sizes 1319 ****************************************************************************/ 1320static int 1321hdac_get_capabilities(struct hdac_softc *sc) 1322{ 1323 uint16_t gcap; 1324 uint8_t corbsize, rirbsize; 1325 1326 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1327 sc->num_iss = HDAC_GCAP_ISS(gcap); 1328 sc->num_oss = HDAC_GCAP_OSS(gcap); 1329 sc->num_bss = HDAC_GCAP_BSS(gcap); 1330 1331 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1332 1333 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1334 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1335 HDAC_CORBSIZE_CORBSZCAP_256) 1336 sc->corb_size = 256; 1337 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1338 HDAC_CORBSIZE_CORBSZCAP_16) 1339 sc->corb_size = 16; 1340 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1341 HDAC_CORBSIZE_CORBSZCAP_2) 1342 sc->corb_size = 2; 1343 else { 1344 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1345 __func__, corbsize); 1346 return (ENXIO); 1347 } 1348 1349 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1350 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1351 HDAC_RIRBSIZE_RIRBSZCAP_256) 1352 sc->rirb_size = 256; 1353 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1354 HDAC_RIRBSIZE_RIRBSZCAP_16) 1355 sc->rirb_size = 16; 1356 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1357 HDAC_RIRBSIZE_RIRBSZCAP_2) 1358 sc->rirb_size = 2; 1359 else { 1360 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1361 __func__, rirbsize); 1362 return (ENXIO); 1363 } 1364 1365 return (0); 1366} 1367 1368 1369/**************************************************************************** 1370 * void hdac_dma_cb 1371 * 1372 * This function is called by bus_dmamap_load when the mapping has been 1373 * established. We just record the physical address of the mapping into 1374 * the struct hdac_dma passed in. 1375 ****************************************************************************/ 1376static void 1377hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1378{ 1379 struct hdac_dma *dma; 1380 1381 if (error == 0) { 1382 dma = (struct hdac_dma *)callback_arg; 1383 dma->dma_paddr = segs[0].ds_addr; 1384 } 1385} 1386 1387 1388/**************************************************************************** 1389 * int hdac_dma_alloc 1390 * 1391 * This function allocate and setup a dma region (struct hdac_dma). 1392 * It must be freed by a corresponding hdac_dma_free. 1393 ****************************************************************************/ 1394static int 1395hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1396{ 1397 bus_size_t roundsz; 1398 int result; 1399 int lowaddr; 1400 1401 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1402 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1403 BUS_SPACE_MAXADDR_32BIT; 1404 bzero(dma, sizeof(*dma)); 1405 1406 /* 1407 * Create a DMA tag 1408 */ 1409 result = bus_dma_tag_create(NULL, /* parent */ 1410 HDAC_DMA_ALIGNMENT, /* alignment */ 1411 0, /* boundary */ 1412 lowaddr, /* lowaddr */ 1413 BUS_SPACE_MAXADDR, /* highaddr */ 1414 NULL, /* filtfunc */ 1415 NULL, /* fistfuncarg */ 1416 roundsz, /* maxsize */ 1417 1, /* nsegments */ 1418 roundsz, /* maxsegsz */ 1419 0, /* flags */ 1420 NULL, /* lockfunc */ 1421 NULL, /* lockfuncarg */ 1422 &dma->dma_tag); /* dmat */ 1423 if (result != 0) { 1424 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1425 __func__, result); 1426 goto hdac_dma_alloc_fail; 1427 } 1428 1429 /* 1430 * Allocate DMA memory 1431 */ 1432 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1433 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1434 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1435 &dma->dma_map); 1436 if (result != 0) { 1437 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1438 __func__, result); 1439 goto hdac_dma_alloc_fail; 1440 } 1441 1442 dma->dma_size = roundsz; 1443 1444 /* 1445 * Map the memory 1446 */ 1447 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1448 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1449 if (result != 0 || dma->dma_paddr == 0) { 1450 if (result == 0) 1451 result = ENOMEM; 1452 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1453 __func__, result); 1454 goto hdac_dma_alloc_fail; 1455 } 1456 1457 HDA_BOOTVERBOSE( 1458 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1459 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1460 ); 1461 1462 return (0); 1463 1464hdac_dma_alloc_fail: 1465 hdac_dma_free(sc, dma); 1466 1467 return (result); 1468} 1469 1470 1471/**************************************************************************** 1472 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1473 * 1474 * Free a struct dhac_dma that has been previously allocated via the 1475 * hdac_dma_alloc function. 1476 ****************************************************************************/ 1477static void 1478hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1479{ 1480 if (dma->dma_map != NULL) { 1481#if 0 1482 /* Flush caches */ 1483 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1484 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1485#endif 1486 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1487 } 1488 if (dma->dma_vaddr != NULL) { 1489 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1490 dma->dma_vaddr = NULL; 1491 } 1492 dma->dma_map = NULL; 1493 if (dma->dma_tag != NULL) { 1494 bus_dma_tag_destroy(dma->dma_tag); 1495 dma->dma_tag = NULL; 1496 } 1497 dma->dma_size = 0; 1498} 1499 1500/**************************************************************************** 1501 * int hdac_mem_alloc(struct hdac_softc *) 1502 * 1503 * Allocate all the bus resources necessary to speak with the physical 1504 * controller. 1505 ****************************************************************************/ 1506static int 1507hdac_mem_alloc(struct hdac_softc *sc) 1508{ 1509 struct hdac_mem *mem; 1510 1511 mem = &sc->mem; 1512 mem->mem_rid = PCIR_BAR(0); 1513 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1514 &mem->mem_rid, RF_ACTIVE); 1515 if (mem->mem_res == NULL) { 1516 device_printf(sc->dev, 1517 "%s: Unable to allocate memory resource\n", __func__); 1518 return (ENOMEM); 1519 } 1520 mem->mem_tag = rman_get_bustag(mem->mem_res); 1521 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1522 1523 return (0); 1524} 1525 1526/**************************************************************************** 1527 * void hdac_mem_free(struct hdac_softc *) 1528 * 1529 * Free up resources previously allocated by hdac_mem_alloc. 1530 ****************************************************************************/ 1531static void 1532hdac_mem_free(struct hdac_softc *sc) 1533{ 1534 struct hdac_mem *mem; 1535 1536 mem = &sc->mem; 1537 if (mem->mem_res != NULL) 1538 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1539 mem->mem_res); 1540 mem->mem_res = NULL; 1541} 1542 1543/**************************************************************************** 1544 * int hdac_irq_alloc(struct hdac_softc *) 1545 * 1546 * Allocate and setup the resources necessary for interrupt handling. 1547 ****************************************************************************/ 1548static int 1549hdac_irq_alloc(struct hdac_softc *sc) 1550{ 1551 struct hdac_irq *irq; 1552 int result; 1553 1554 irq = &sc->irq; 1555 irq->irq_rid = 0x0; 1556 1557#if __FreeBSD_version >= 602106 1558 if ((sc->flags & HDAC_F_MSI) && 1559 (result = pci_msi_count(sc->dev)) == 1 && 1560 pci_alloc_msi(sc->dev, &result) == 0) 1561 irq->irq_rid = 0x1; 1562 else 1563#endif 1564 sc->flags &= ~HDAC_F_MSI; 1565 1566 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1567 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1568 if (irq->irq_res == NULL) { 1569 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1570 __func__); 1571 goto hdac_irq_alloc_fail; 1572 } 1573 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1574 hdac_intr_handler, sc, &irq->irq_handle); 1575 if (result != 0) { 1576 device_printf(sc->dev, 1577 "%s: Unable to setup interrupt handler (%x)\n", 1578 __func__, result); 1579 goto hdac_irq_alloc_fail; 1580 } 1581 1582 return (0); 1583 1584hdac_irq_alloc_fail: 1585 hdac_irq_free(sc); 1586 1587 return (ENXIO); 1588} 1589 1590/**************************************************************************** 1591 * void hdac_irq_free(struct hdac_softc *) 1592 * 1593 * Free up resources previously allocated by hdac_irq_alloc. 1594 ****************************************************************************/ 1595static void 1596hdac_irq_free(struct hdac_softc *sc) 1597{ 1598 struct hdac_irq *irq; 1599 1600 irq = &sc->irq; 1601 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1602 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1603 if (irq->irq_res != NULL) 1604 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1605 irq->irq_res); 1606#if __FreeBSD_version >= 602106 1607 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1608 pci_release_msi(sc->dev); 1609#endif 1610 irq->irq_handle = NULL; 1611 irq->irq_res = NULL; 1612 irq->irq_rid = 0x0; 1613} 1614 1615/**************************************************************************** 1616 * void hdac_corb_init(struct hdac_softc *) 1617 * 1618 * Initialize the corb registers for operations but do not start it up yet. 1619 * The CORB engine must not be running when this function is called. 1620 ****************************************************************************/ 1621static void 1622hdac_corb_init(struct hdac_softc *sc) 1623{ 1624 uint8_t corbsize; 1625 uint64_t corbpaddr; 1626 1627 /* Setup the CORB size. */ 1628 switch (sc->corb_size) { 1629 case 256: 1630 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1631 break; 1632 case 16: 1633 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1634 break; 1635 case 2: 1636 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1637 break; 1638 default: 1639 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1640 } 1641 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1642 1643 /* Setup the CORB Address in the hdac */ 1644 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1645 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1646 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1647 1648 /* Set the WP and RP */ 1649 sc->corb_wp = 0; 1650 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1651 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1652 /* 1653 * The HDA specification indicates that the CORBRPRST bit will always 1654 * read as zero. Unfortunately, it seems that at least the 82801G 1655 * doesn't reset the bit to zero, which stalls the corb engine. 1656 * manually reset the bit to zero before continuing. 1657 */ 1658 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1659 1660 /* Enable CORB error reporting */ 1661#if 0 1662 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1663#endif 1664} 1665 1666/**************************************************************************** 1667 * void hdac_rirb_init(struct hdac_softc *) 1668 * 1669 * Initialize the rirb registers for operations but do not start it up yet. 1670 * The RIRB engine must not be running when this function is called. 1671 ****************************************************************************/ 1672static void 1673hdac_rirb_init(struct hdac_softc *sc) 1674{ 1675 uint8_t rirbsize; 1676 uint64_t rirbpaddr; 1677 1678 /* Setup the RIRB size. */ 1679 switch (sc->rirb_size) { 1680 case 256: 1681 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1682 break; 1683 case 16: 1684 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1685 break; 1686 case 2: 1687 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1688 break; 1689 default: 1690 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1691 } 1692 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1693 1694 /* Setup the RIRB Address in the hdac */ 1695 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1696 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1697 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1698 1699 /* Setup the WP and RP */ 1700 sc->rirb_rp = 0; 1701 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1702 1703 if (sc->polling == 0) { 1704 /* Setup the interrupt threshold */ 1705 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1706 1707 /* Enable Overrun and response received reporting */ 1708#if 0 1709 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1710 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1711#else 1712 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1713#endif 1714 } 1715 1716#if 0 1717 /* 1718 * Make sure that the Host CPU cache doesn't contain any dirty 1719 * cache lines that falls in the rirb. If I understood correctly, it 1720 * should be sufficient to do this only once as the rirb is purely 1721 * read-only from now on. 1722 */ 1723 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1724 BUS_DMASYNC_PREREAD); 1725#endif 1726} 1727 1728/**************************************************************************** 1729 * void hdac_corb_start(hdac_softc *) 1730 * 1731 * Startup the corb DMA engine 1732 ****************************************************************************/ 1733static void 1734hdac_corb_start(struct hdac_softc *sc) 1735{ 1736 uint32_t corbctl; 1737 1738 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1739 corbctl |= HDAC_CORBCTL_CORBRUN; 1740 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1741} 1742 1743/**************************************************************************** 1744 * void hdac_rirb_start(hdac_softc *) 1745 * 1746 * Startup the rirb DMA engine 1747 ****************************************************************************/ 1748static void 1749hdac_rirb_start(struct hdac_softc *sc) 1750{ 1751 uint32_t rirbctl; 1752 1753 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1754 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1755 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1756} 1757 1758 1759/**************************************************************************** 1760 * void hdac_scan_codecs(struct hdac_softc *, int) 1761 * 1762 * Scan the bus for available codecs, starting with num. 1763 ****************************************************************************/ 1764static void 1765hdac_scan_codecs(struct hdac_softc *sc, int num) 1766{ 1767 struct hdac_codec *codec; 1768 int i; 1769 uint16_t statests; 1770 1771 if (num < 0) 1772 num = 0; 1773 if (num >= HDAC_CODEC_MAX) 1774 num = HDAC_CODEC_MAX - 1; 1775 1776 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1777 for (i = num; i < HDAC_CODEC_MAX; i++) { 1778 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1779 /* We have found a codec. */ 1780 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1781 M_HDAC, M_ZERO | M_NOWAIT); 1782 if (codec == NULL) { 1783 device_printf(sc->dev, 1784 "Unable to allocate memory for codec\n"); 1785 continue; 1786 } 1787 codec->commands = NULL; 1788 codec->responses_received = 0; 1789 codec->verbs_sent = 0; 1790 codec->sc = sc; 1791 codec->cad = i; 1792 sc->codecs[i] = codec; 1793 if (hdac_probe_codec(codec) != 0) 1794 break; 1795 } 1796 } 1797 /* All codecs have been probed, now try to attach drivers to them */ 1798 /* bus_generic_attach(sc->dev); */ 1799} 1800 1801/**************************************************************************** 1802 * void hdac_probe_codec(struct hdac_softc *, int) 1803 * 1804 * Probe a the given codec_id for available function groups. 1805 ****************************************************************************/ 1806static int 1807hdac_probe_codec(struct hdac_codec *codec) 1808{ 1809 struct hdac_softc *sc = codec->sc; 1810 struct hdac_devinfo *devinfo; 1811 uint32_t vendorid, revisionid, subnode; 1812 int startnode; 1813 int endnode; 1814 int i; 1815 nid_t cad = codec->cad; 1816 1817 HDA_BOOTVERBOSE( 1818 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1819 ); 1820 vendorid = hdac_command(sc, 1821 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1822 cad); 1823 revisionid = hdac_command(sc, 1824 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1825 cad); 1826 subnode = hdac_command(sc, 1827 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1828 cad); 1829 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1830 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1831 1832 HDA_BOOTVERBOSE( 1833 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1834 startnode, endnode); 1835 ); 1836 for (i = startnode; i < endnode; i++) { 1837 devinfo = hdac_probe_function(codec, i); 1838 if (devinfo != NULL) { 1839 /* XXX Ignore other FG. */ 1840 devinfo->vendor_id = 1841 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1842 devinfo->device_id = 1843 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1844 devinfo->revision_id = 1845 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1846 devinfo->stepping_id = 1847 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1848 HDA_BOOTVERBOSE( 1849 device_printf(sc->dev, 1850 "HDA_DEBUG: \tFound AFG nid=%d " 1851 "[startnode=%d endnode=%d]\n", 1852 devinfo->nid, startnode, endnode); 1853 ); 1854 return (1); 1855 } 1856 } 1857 1858 HDA_BOOTVERBOSE( 1859 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1860 ); 1861 return (0); 1862} 1863 1864static struct hdac_devinfo * 1865hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1866{ 1867 struct hdac_softc *sc = codec->sc; 1868 struct hdac_devinfo *devinfo; 1869 uint32_t fctgrptype; 1870 nid_t cad = codec->cad; 1871 1872 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1873 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1874 1875 /* XXX For now, ignore other FG. */ 1876 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1877 return (NULL); 1878 1879 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1880 M_NOWAIT | M_ZERO); 1881 if (devinfo == NULL) { 1882 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1883 __func__); 1884 return (NULL); 1885 } 1886 1887 devinfo->nid = nid; 1888 devinfo->node_type = fctgrptype; 1889 devinfo->codec = codec; 1890 1891 hdac_add_child(sc, devinfo); 1892 1893 return (devinfo); 1894} 1895 1896static void 1897hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1898{ 1899 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1900 device_set_ivars(devinfo->dev, (void *)devinfo); 1901 /* XXX - Print more information when booting verbose??? */ 1902} 1903 1904static void 1905hdac_widget_connection_parse(struct hdac_widget *w) 1906{ 1907 struct hdac_softc *sc = w->devinfo->codec->sc; 1908 uint32_t res; 1909 int i, j, max, ents, entnum; 1910 nid_t cad = w->devinfo->codec->cad; 1911 nid_t nid = w->nid; 1912 nid_t cnid, addcnid, prevcnid; 1913 1914 w->nconns = 0; 1915 1916 res = hdac_command(sc, 1917 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1918 1919 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1920 1921 if (ents < 1) 1922 return; 1923 1924 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1925 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1926 prevcnid = 0; 1927 1928#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1929#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1930#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1931#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1932#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1933 1934 for (i = 0; i < ents; i += entnum) { 1935 res = hdac_command(sc, 1936 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1937 for (j = 0; j < entnum; j++) { 1938 cnid = CONN_CNID(res, entnum, j); 1939 if (cnid == 0) { 1940 if (w->nconns < ents) 1941 device_printf(sc->dev, 1942 "%s: nid=%d WARNING: zero cnid " 1943 "entnum=%d j=%d index=%d " 1944 "entries=%d found=%d res=0x%08x\n", 1945 __func__, nid, entnum, j, i, 1946 ents, w->nconns, res); 1947 else 1948 goto getconns_out; 1949 } 1950 if (cnid < w->devinfo->startnode || 1951 cnid >= w->devinfo->endnode) { 1952 HDA_BOOTVERBOSE( 1953 device_printf(sc->dev, 1954 "%s: GHOST: nid=%d j=%d " 1955 "entnum=%d index=%d res=0x%08x\n", 1956 __func__, nid, j, entnum, i, res); 1957 ); 1958 } 1959 if (CONN_RANGE(res, entnum, j) == 0) 1960 addcnid = cnid; 1961 else if (prevcnid == 0 || prevcnid >= cnid) { 1962 device_printf(sc->dev, 1963 "%s: WARNING: Invalid child range " 1964 "nid=%d index=%d j=%d entnum=%d " 1965 "prevcnid=%d cnid=%d res=0x%08x\n", 1966 __func__, nid, i, j, entnum, prevcnid, 1967 cnid, res); 1968 addcnid = cnid; 1969 } else 1970 addcnid = prevcnid + 1; 1971 while (addcnid <= cnid) { 1972 if (w->nconns > max) { 1973 device_printf(sc->dev, 1974 "%s: nid=%d: Adding %d: " 1975 "Max connection reached! max=%d\n", 1976 __func__, nid, addcnid, max + 1); 1977 goto getconns_out; 1978 } 1979 w->conns[w->nconns++] = addcnid++; 1980 } 1981 prevcnid = cnid; 1982 } 1983 } 1984 1985getconns_out: 1986 HDA_BOOTVERBOSE( 1987 device_printf(sc->dev, 1988 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1989 __func__, nid, ents, w->nconns); 1990 ); 1991 return; 1992} 1993 1994static uint32_t 1995hdac_widget_pin_getconfig(struct hdac_widget *w) 1996{ 1997 struct hdac_softc *sc; 1998 uint32_t config, orig, id; 1999 nid_t cad, nid; 2000 2001 sc = w->devinfo->codec->sc; 2002 cad = w->devinfo->codec->cad; 2003 nid = w->nid; 2004 id = hdac_codec_id(w->devinfo); 2005 2006 config = hdac_command(sc, 2007 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2008 cad); 2009 orig = config; 2010 2011 /* 2012 * XXX REWRITE!!!! Don't argue! 2013 */ 2014 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2015 switch (nid) { 2016 case 26: 2017 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2018 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2019 break; 2020 case 27: 2021 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2022 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2023 break; 2024 default: 2025 break; 2026 } 2027 } else if (id == HDA_CODEC_ALC880 && 2028 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2029 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2030 /* 2031 * Super broken BIOS 2032 */ 2033 switch (nid) { 2034 case 20: 2035 break; 2036 case 21: 2037 break; 2038 case 22: 2039 break; 2040 case 23: 2041 break; 2042 case 24: /* MIC1 */ 2043 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2044 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2045 break; 2046 case 25: /* XXX MIC2 */ 2047 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2048 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2049 break; 2050 case 26: /* LINE1 */ 2051 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2052 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2053 break; 2054 case 27: /* XXX LINE2 */ 2055 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2056 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2057 break; 2058 case 28: /* CD */ 2059 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2060 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2061 break; 2062 case 30: 2063 break; 2064 case 31: 2065 break; 2066 default: 2067 break; 2068 } 2069 } else if (id == HDA_CODEC_ALC883 && 2070 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2071 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2072 switch (nid) { 2073 case 25: 2074 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2075 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2076 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2077 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2078 break; 2079 case 28: 2080 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2081 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2082 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2083 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2084 break; 2085 default: 2086 break; 2087 } 2088 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2089 HP_V3000_SUBVENDOR) { 2090 switch (nid) { 2091 case 18: 2092 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2093 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2094 break; 2095 case 20: 2096 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2097 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2098 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2099 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2100 break; 2101 case 21: 2102 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2103 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2104 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2105 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2106 break; 2107 default: 2108 break; 2109 } 2110 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2111 HP_DV5000_SUBVENDOR) { 2112 switch (nid) { 2113 case 20: 2114 case 21: 2115 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2116 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2117 break; 2118 default: 2119 break; 2120 } 2121 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2122 ASUS_W6F_SUBVENDOR) { 2123 switch (nid) { 2124 case 11: 2125 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2126 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2127 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2128 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2129 break; 2130 case 15: 2131 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2132 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2133 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2134 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2135 break; 2136 default: 2137 break; 2138 } 2139 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2140 UNIWILL_9075_SUBVENDOR) { 2141 switch (nid) { 2142 case 15: 2143 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2144 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2145 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2146 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2147 break; 2148 default: 2149 break; 2150 } 2151 } else if (id == HDA_CODEC_AD1986A && 2152 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2153 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2154 switch (nid) { 2155 case 28: /* LINE */ 2156 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2157 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2158 break; 2159 case 29: /* MIC */ 2160 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2161 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2162 break; 2163 default: 2164 break; 2165 } 2166 } 2167 2168 HDA_BOOTVERBOSE( 2169 if (config != orig) 2170 device_printf(sc->dev, 2171 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2172 nid, orig, config); 2173 ); 2174 2175 return (config); 2176} 2177 2178static uint32_t 2179hdac_widget_pin_getcaps(struct hdac_widget *w) 2180{ 2181 struct hdac_softc *sc; 2182 uint32_t caps, orig, id; 2183 nid_t cad, nid; 2184 2185 sc = w->devinfo->codec->sc; 2186 cad = w->devinfo->codec->cad; 2187 nid = w->nid; 2188 id = hdac_codec_id(w->devinfo); 2189 2190 caps = hdac_command(sc, 2191 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2192 orig = caps; 2193 2194 HDA_BOOTVERBOSE( 2195 if (caps != orig) 2196 device_printf(sc->dev, 2197 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2198 nid, orig, caps); 2199 ); 2200 2201 return (caps); 2202} 2203 2204static void 2205hdac_widget_pin_parse(struct hdac_widget *w) 2206{ 2207 struct hdac_softc *sc = w->devinfo->codec->sc; 2208 uint32_t config, pincap; 2209 char *devstr, *connstr; 2210 nid_t cad = w->devinfo->codec->cad; 2211 nid_t nid = w->nid; 2212 2213 config = hdac_widget_pin_getconfig(w); 2214 w->wclass.pin.config = config; 2215 2216 pincap = hdac_widget_pin_getcaps(w); 2217 w->wclass.pin.cap = pincap; 2218 2219 w->wclass.pin.ctrl = hdac_command(sc, 2220 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2221 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2222 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2223 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2224 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2225 2226 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2227 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2228 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2229 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2230 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2231 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2232 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2233 w->param.eapdbtl = hdac_command(sc, 2234 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2235 w->param.eapdbtl &= 0x7; 2236 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2237 } else 2238 w->param.eapdbtl = HDAC_INVALID; 2239 2240 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2241 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2242 devstr = "line out"; 2243 break; 2244 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2245 devstr = "speaker"; 2246 break; 2247 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2248 devstr = "headphones out"; 2249 break; 2250 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2251 devstr = "CD"; 2252 break; 2253 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2254 devstr = "SPDIF out"; 2255 break; 2256 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2257 devstr = "digital (other) out"; 2258 break; 2259 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2260 devstr = "modem, line side"; 2261 break; 2262 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2263 devstr = "modem, handset side"; 2264 break; 2265 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2266 devstr = "line in"; 2267 break; 2268 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2269 devstr = "AUX"; 2270 break; 2271 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2272 devstr = "Mic in"; 2273 break; 2274 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2275 devstr = "telephony"; 2276 break; 2277 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2278 devstr = "SPDIF in"; 2279 break; 2280 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2281 devstr = "digital (other) in"; 2282 break; 2283 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2284 devstr = "other"; 2285 break; 2286 default: 2287 devstr = "unknown"; 2288 break; 2289 } 2290 2291 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2292 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2293 connstr = "jack"; 2294 break; 2295 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2296 connstr = "none"; 2297 break; 2298 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2299 connstr = "fixed"; 2300 break; 2301 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2302 connstr = "jack / fixed"; 2303 break; 2304 default: 2305 connstr = "unknown"; 2306 break; 2307 } 2308 2309 strlcat(w->name, ": ", sizeof(w->name)); 2310 strlcat(w->name, devstr, sizeof(w->name)); 2311 strlcat(w->name, " (", sizeof(w->name)); 2312 strlcat(w->name, connstr, sizeof(w->name)); 2313 strlcat(w->name, ")", sizeof(w->name)); 2314} 2315 2316static void 2317hdac_widget_parse(struct hdac_widget *w) 2318{ 2319 struct hdac_softc *sc = w->devinfo->codec->sc; 2320 uint32_t wcap, cap; 2321 char *typestr; 2322 nid_t cad = w->devinfo->codec->cad; 2323 nid_t nid = w->nid; 2324 2325 wcap = hdac_command(sc, 2326 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2327 cad); 2328 w->param.widget_cap = wcap; 2329 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2330 2331 switch (w->type) { 2332 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2333 typestr = "audio output"; 2334 break; 2335 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2336 typestr = "audio input"; 2337 break; 2338 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2339 typestr = "audio mixer"; 2340 break; 2341 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2342 typestr = "audio selector"; 2343 break; 2344 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2345 typestr = "pin"; 2346 break; 2347 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2348 typestr = "power widget"; 2349 break; 2350 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2351 typestr = "volume widget"; 2352 break; 2353 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2354 typestr = "beep widget"; 2355 break; 2356 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2357 typestr = "vendor widget"; 2358 break; 2359 default: 2360 typestr = "unknown type"; 2361 break; 2362 } 2363 2364 strlcpy(w->name, typestr, sizeof(w->name)); 2365 2366 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2367 hdac_command(sc, 2368 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2369 cad); 2370 DELAY(1000); 2371 } 2372 2373 hdac_widget_connection_parse(w); 2374 2375 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2376 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2377 w->param.outamp_cap = 2378 hdac_command(sc, 2379 HDA_CMD_GET_PARAMETER(cad, nid, 2380 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2381 else 2382 w->param.outamp_cap = 2383 w->devinfo->function.audio.outamp_cap; 2384 } else 2385 w->param.outamp_cap = 0; 2386 2387 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2388 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2389 w->param.inamp_cap = 2390 hdac_command(sc, 2391 HDA_CMD_GET_PARAMETER(cad, nid, 2392 HDA_PARAM_INPUT_AMP_CAP), cad); 2393 else 2394 w->param.inamp_cap = 2395 w->devinfo->function.audio.inamp_cap; 2396 } else 2397 w->param.inamp_cap = 0; 2398 2399 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2400 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2401 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2402 cap = hdac_command(sc, 2403 HDA_CMD_GET_PARAMETER(cad, nid, 2404 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2405 w->param.supp_stream_formats = (cap != 0) ? cap : 2406 w->devinfo->function.audio.supp_stream_formats; 2407 cap = hdac_command(sc, 2408 HDA_CMD_GET_PARAMETER(cad, nid, 2409 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2410 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2411 w->devinfo->function.audio.supp_pcm_size_rate; 2412 } else { 2413 w->param.supp_stream_formats = 2414 w->devinfo->function.audio.supp_stream_formats; 2415 w->param.supp_pcm_size_rate = 2416 w->devinfo->function.audio.supp_pcm_size_rate; 2417 } 2418 } else { 2419 w->param.supp_stream_formats = 0; 2420 w->param.supp_pcm_size_rate = 0; 2421 } 2422 2423 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2424 hdac_widget_pin_parse(w); 2425} 2426 2427static struct hdac_widget * 2428hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2429{ 2430 if (devinfo == NULL || devinfo->widget == NULL || 2431 nid < devinfo->startnode || nid >= devinfo->endnode) 2432 return (NULL); 2433 return (&devinfo->widget[nid - devinfo->startnode]); 2434} 2435 2436static __inline int 2437hda_poll_channel(struct hdac_chan *ch) 2438{ 2439 uint32_t sz, delta; 2440 volatile uint32_t ptr; 2441 2442 if (!(ch->flags & HDAC_CHN_RUNNING)) 2443 return (0); 2444 2445 sz = ch->blksz * ch->blkcnt; 2446 if (ch->dmapos != NULL) 2447 ptr = *(ch->dmapos); 2448 else 2449 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2450 ch->off + HDAC_SDLPIB); 2451 ch->ptr = ptr; 2452 ptr %= sz; 2453 ptr &= ~(ch->blksz - 1); 2454 delta = (sz + ptr - ch->prevptr) % sz; 2455 2456 if (delta < ch->blksz) 2457 return (0); 2458 2459 ch->prevptr = ptr; 2460 2461 return (1); 2462} 2463 2464#define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2465 HDAC_CHN_RUNNING) 2466 2467static void 2468hda_poll_callback(void *arg) 2469{ 2470 struct hdac_softc *sc = arg; 2471 uint32_t trigger; 2472 2473 if (sc == NULL) 2474 return; 2475 2476 hdac_lock(sc); 2477 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2478 hdac_unlock(sc); 2479 return; 2480 } 2481 2482 trigger = 0; 2483 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2484 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2485 2486 /* XXX */ 2487 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2488 hda_poll_callback, sc); 2489 2490 hdac_unlock(sc); 2491 2492 if (trigger & HDAC_TRIGGER_PLAY) 2493 chn_intr(sc->play.c); 2494 if (trigger & HDAC_TRIGGER_REC) 2495 chn_intr(sc->rec.c); 2496} 2497 2498static int 2499hdac_rirb_flush(struct hdac_softc *sc) 2500{ 2501 struct hdac_rirb *rirb_base, *rirb; 2502 struct hdac_codec *codec; 2503 struct hdac_command_list *commands; 2504 nid_t cad; 2505 uint32_t resp; 2506 uint8_t rirbwp; 2507 int ret; 2508 2509 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2510 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2511#if 0 2512 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2513 BUS_DMASYNC_POSTREAD); 2514#endif 2515 2516 ret = 0; 2517 2518 while (sc->rirb_rp != rirbwp) { 2519 sc->rirb_rp++; 2520 sc->rirb_rp %= sc->rirb_size; 2521 rirb = &rirb_base[sc->rirb_rp]; 2522 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2523 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2524 sc->codecs[cad] == NULL) 2525 continue; 2526 resp = rirb->response; 2527 codec = sc->codecs[cad]; 2528 commands = codec->commands; 2529 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2530 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2531 ((resp >> 26) & 0xffff); 2532 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2533 } else if (commands != NULL && commands->num_commands > 0 && 2534 codec->responses_received < commands->num_commands) 2535 commands->responses[codec->responses_received++] = 2536 resp; 2537 ret++; 2538 } 2539 2540 return (ret); 2541} 2542 2543static int 2544hdac_unsolq_flush(struct hdac_softc *sc) 2545{ 2546 nid_t cad; 2547 uint32_t tag; 2548 int ret = 0; 2549 2550 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2551 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2552 while (sc->unsolq_rp != sc->unsolq_wp) { 2553 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2554 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2555 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2556 hdac_unsolicited_handler(sc->codecs[cad], tag); 2557 ret++; 2558 } 2559 sc->unsolq_st = HDAC_UNSOLQ_READY; 2560 } 2561 2562 return (ret); 2563} 2564 2565static void 2566hdac_poll_callback(void *arg) 2567{ 2568 struct hdac_softc *sc = arg; 2569 if (sc == NULL) 2570 return; 2571 2572 hdac_lock(sc); 2573 if (sc->polling == 0 || sc->poll_ival == 0) { 2574 hdac_unlock(sc); 2575 return; 2576 } 2577 if (hdac_rirb_flush(sc) != 0) 2578 hdac_unsolq_flush(sc); 2579 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2580 hdac_unlock(sc); 2581} 2582 2583static void 2584hdac_stream_stop(struct hdac_chan *ch) 2585{ 2586 struct hdac_softc *sc = ch->devinfo->codec->sc; 2587 uint32_t ctl; 2588 2589 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2590 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2591 HDAC_SDCTL_RUN); 2592 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2593 2594 ch->flags &= ~HDAC_CHN_RUNNING; 2595 2596 if (sc->polling != 0) { 2597 int pollticks; 2598 2599 if (hda_chan_active(sc) == 0) { 2600 callout_stop(&sc->poll_hda); 2601 sc->poll_ticks = 1; 2602 } else { 2603 if (sc->play.flags & HDAC_CHN_RUNNING) 2604 ch = &sc->play; 2605 else 2606 ch = &sc->rec; 2607 pollticks = ((uint64_t)hz * ch->blksz) / 2608 ((uint64_t)sndbuf_getbps(ch->b) * 2609 sndbuf_getspd(ch->b)); 2610 pollticks >>= 2; 2611 if (pollticks > hz) 2612 pollticks = hz; 2613 if (pollticks < 1) { 2614 HDA_BOOTVERBOSE( 2615 device_printf(sc->dev, 2616 "%s: pollticks=%d < 1 !\n", 2617 __func__, pollticks); 2618 ); 2619 pollticks = 1; 2620 } 2621 if (pollticks > sc->poll_ticks) { 2622 HDA_BOOTVERBOSE( 2623 device_printf(sc->dev, 2624 "%s: pollticks %d -> %d\n", 2625 __func__, sc->poll_ticks, 2626 pollticks); 2627 ); 2628 sc->poll_ticks = pollticks; 2629 callout_reset(&sc->poll_hda, 1, 2630 hda_poll_callback, sc); 2631 } 2632 } 2633 } else { 2634 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2635 ctl &= ~(1 << (ch->off >> 5)); 2636 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2637 } 2638} 2639 2640static void 2641hdac_stream_start(struct hdac_chan *ch) 2642{ 2643 struct hdac_softc *sc = ch->devinfo->codec->sc; 2644 uint32_t ctl; 2645 2646 if (sc->polling != 0) { 2647 int pollticks; 2648 2649 pollticks = ((uint64_t)hz * ch->blksz) / 2650 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2651 pollticks >>= 2; 2652 if (pollticks > hz) 2653 pollticks = hz; 2654 if (pollticks < 1) { 2655 HDA_BOOTVERBOSE( 2656 device_printf(sc->dev, 2657 "%s: pollticks=%d < 1 !\n", 2658 __func__, pollticks); 2659 ); 2660 pollticks = 1; 2661 } 2662 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2663 HDA_BOOTVERBOSE( 2664 if (hda_chan_active(sc) == 0) { 2665 device_printf(sc->dev, 2666 "%s: pollticks=%d\n", 2667 __func__, pollticks); 2668 } else { 2669 device_printf(sc->dev, 2670 "%s: pollticks %d -> %d\n", 2671 __func__, sc->poll_ticks, 2672 pollticks); 2673 } 2674 ); 2675 sc->poll_ticks = pollticks; 2676 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2677 sc); 2678 } 2679 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2680 ctl |= HDAC_SDCTL_RUN; 2681 } else { 2682 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2683 ctl |= 1 << (ch->off >> 5); 2684 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2685 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2686 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2687 HDAC_SDCTL_RUN; 2688 } 2689 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2690 2691 ch->flags |= HDAC_CHN_RUNNING; 2692} 2693 2694static void 2695hdac_stream_reset(struct hdac_chan *ch) 2696{ 2697 struct hdac_softc *sc = ch->devinfo->codec->sc; 2698 int timeout = 1000; 2699 int to = timeout; 2700 uint32_t ctl; 2701 2702 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2703 ctl |= HDAC_SDCTL_SRST; 2704 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2705 do { 2706 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2707 if (ctl & HDAC_SDCTL_SRST) 2708 break; 2709 DELAY(10); 2710 } while (--to); 2711 if (!(ctl & HDAC_SDCTL_SRST)) { 2712 device_printf(sc->dev, "timeout in reset\n"); 2713 } 2714 ctl &= ~HDAC_SDCTL_SRST; 2715 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2716 to = timeout; 2717 do { 2718 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2719 if (!(ctl & HDAC_SDCTL_SRST)) 2720 break; 2721 DELAY(10); 2722 } while (--to); 2723 if (ctl & HDAC_SDCTL_SRST) 2724 device_printf(sc->dev, "can't reset!\n"); 2725} 2726 2727static void 2728hdac_stream_setid(struct hdac_chan *ch) 2729{ 2730 struct hdac_softc *sc = ch->devinfo->codec->sc; 2731 uint32_t ctl; 2732 2733 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2734 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2735 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2736 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2737} 2738 2739static void 2740hdac_bdl_setup(struct hdac_chan *ch) 2741{ 2742 struct hdac_softc *sc = ch->devinfo->codec->sc; 2743 struct hdac_bdle *bdle; 2744 uint64_t addr; 2745 uint32_t blksz, blkcnt; 2746 int i; 2747 2748 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2749 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2750 2751 if (sc->polling != 0) { 2752 blksz = ch->blksz * ch->blkcnt; 2753 blkcnt = 1; 2754 } else { 2755 blksz = ch->blksz; 2756 blkcnt = ch->blkcnt; 2757 } 2758 2759 for (i = 0; i < blkcnt; i++, bdle++) { 2760 bdle->addrl = (uint32_t)addr; 2761 bdle->addrh = (uint32_t)(addr >> 32); 2762 bdle->len = blksz; 2763 bdle->ioc = 1 ^ sc->polling; 2764 addr += blksz; 2765 } 2766 2767 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2768 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2769 addr = ch->bdl_dma.dma_paddr; 2770 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2771 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2772 if (ch->dmapos != NULL && 2773 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2774 addr = sc->pos_dma.dma_paddr; 2775 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2776 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2777 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2778 } 2779} 2780 2781static int 2782hdac_bdl_alloc(struct hdac_chan *ch) 2783{ 2784 struct hdac_softc *sc = ch->devinfo->codec->sc; 2785 int rc; 2786 2787 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2788 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2789 if (rc) { 2790 device_printf(sc->dev, "can't alloc bdl\n"); 2791 return (rc); 2792 } 2793 2794 return (0); 2795} 2796 2797static void 2798hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2799 int index, int lmute, int rmute, 2800 int left, int right, int dir) 2801{ 2802 uint16_t v = 0; 2803 2804 if (sc == NULL) 2805 return; 2806 2807 if (left != right || lmute != rmute) { 2808 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2809 (lmute << 7) | left; 2810 hdac_command(sc, 2811 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2812 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2813 (rmute << 7) | right; 2814 } else 2815 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2816 (lmute << 7) | left; 2817 2818 hdac_command(sc, 2819 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2820} 2821 2822static void 2823hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2824 int left, int right) 2825{ 2826 struct hdac_softc *sc; 2827 nid_t nid, cad; 2828 int lmute, rmute; 2829 2830 if (ctl == NULL || ctl->widget == NULL || 2831 ctl->widget->devinfo == NULL || 2832 ctl->widget->devinfo->codec == NULL || 2833 ctl->widget->devinfo->codec->sc == NULL) 2834 return; 2835 2836 sc = ctl->widget->devinfo->codec->sc; 2837 cad = ctl->widget->devinfo->codec->cad; 2838 nid = ctl->widget->nid; 2839 2840 if (mute == HDA_AMP_MUTE_DEFAULT) { 2841 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2842 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2843 } else { 2844 lmute = HDA_AMP_LEFT_MUTED(mute); 2845 rmute = HDA_AMP_RIGHT_MUTED(mute); 2846 } 2847 2848 if (ctl->dir & HDA_CTL_OUT) 2849 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2850 lmute, rmute, left, right, 0); 2851 if (ctl->dir & HDA_CTL_IN) 2852 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2853 lmute, rmute, left, right, 1); 2854 ctl->left = left; 2855 ctl->right = right; 2856} 2857 2858static void 2859hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2860{ 2861 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2862 return; 2863 hdac_command(w->devinfo->codec->sc, 2864 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2865 w->nid, index), w->devinfo->codec->cad); 2866 w->selconn = index; 2867} 2868 2869 2870/**************************************************************************** 2871 * uint32_t hdac_command_sendone_internal 2872 * 2873 * Wrapper function that sends only one command to a given codec 2874 ****************************************************************************/ 2875static uint32_t 2876hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2877{ 2878 struct hdac_command_list cl; 2879 uint32_t response = HDAC_INVALID; 2880 2881 if (!hdac_lockowned(sc)) 2882 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2883 cl.num_commands = 1; 2884 cl.verbs = &verb; 2885 cl.responses = &response; 2886 2887 hdac_command_send_internal(sc, &cl, cad); 2888 2889 return (response); 2890} 2891 2892/**************************************************************************** 2893 * hdac_command_send_internal 2894 * 2895 * Send a command list to the codec via the corb. We queue as much verbs as 2896 * we can and msleep on the codec. When the interrupt get the responses 2897 * back from the rirb, it will wake us up so we can queue the remaining verbs 2898 * if any. 2899 ****************************************************************************/ 2900static void 2901hdac_command_send_internal(struct hdac_softc *sc, 2902 struct hdac_command_list *commands, nid_t cad) 2903{ 2904 struct hdac_codec *codec; 2905 int corbrp; 2906 uint32_t *corb; 2907 int timeout; 2908 int retry = 10; 2909 struct hdac_rirb *rirb_base; 2910 2911 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2912 commands->num_commands < 1) 2913 return; 2914 2915 codec = sc->codecs[cad]; 2916 codec->commands = commands; 2917 codec->responses_received = 0; 2918 codec->verbs_sent = 0; 2919 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2920 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2921 2922 do { 2923 if (codec->verbs_sent != commands->num_commands) { 2924 /* Queue as many verbs as possible */ 2925 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2926#if 0 2927 bus_dmamap_sync(sc->corb_dma.dma_tag, 2928 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2929#endif 2930 while (codec->verbs_sent != commands->num_commands && 2931 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2932 sc->corb_wp++; 2933 sc->corb_wp %= sc->corb_size; 2934 corb[sc->corb_wp] = 2935 commands->verbs[codec->verbs_sent++]; 2936 } 2937 2938 /* Send the verbs to the codecs */ 2939#if 0 2940 bus_dmamap_sync(sc->corb_dma.dma_tag, 2941 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2942#endif 2943 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2944 } 2945 2946 timeout = 1000; 2947 while (hdac_rirb_flush(sc) == 0 && --timeout) 2948 DELAY(10); 2949 } while ((codec->verbs_sent != commands->num_commands || 2950 codec->responses_received != commands->num_commands) && --retry); 2951 2952 if (retry == 0) 2953 device_printf(sc->dev, 2954 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2955 __func__, commands->num_commands, codec->verbs_sent, 2956 codec->responses_received); 2957 2958 codec->commands = NULL; 2959 codec->responses_received = 0; 2960 codec->verbs_sent = 0; 2961 2962 hdac_unsolq_flush(sc); 2963} 2964 2965 2966/**************************************************************************** 2967 * Device Methods 2968 ****************************************************************************/ 2969 2970/**************************************************************************** 2971 * int hdac_probe(device_t) 2972 * 2973 * Probe for the presence of an hdac. If none is found, check for a generic 2974 * match using the subclass of the device. 2975 ****************************************************************************/ 2976static int 2977hdac_probe(device_t dev) 2978{ 2979 int i, result; 2980 uint32_t model; 2981 uint16_t class, subclass; 2982 char desc[64]; 2983 2984 model = (uint32_t)pci_get_device(dev) << 16; 2985 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2986 class = pci_get_class(dev); 2987 subclass = pci_get_subclass(dev); 2988 2989 bzero(desc, sizeof(desc)); 2990 result = ENXIO; 2991 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2992 if (hdac_devices[i].model == model) { 2993 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2994 result = BUS_PROBE_DEFAULT; 2995 break; 2996 } 2997 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2998 class == PCIC_MULTIMEDIA && 2999 subclass == PCIS_MULTIMEDIA_HDA) { 3000 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3001 result = BUS_PROBE_GENERIC; 3002 break; 3003 } 3004 } 3005 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3006 subclass == PCIS_MULTIMEDIA_HDA) { 3007 strlcpy(desc, "Generic", sizeof(desc)); 3008 result = BUS_PROBE_GENERIC; 3009 } 3010 if (result != ENXIO) { 3011 strlcat(desc, " High Definition Audio Controller", 3012 sizeof(desc)); 3013 device_set_desc_copy(dev, desc); 3014 } 3015 3016 return (result); 3017} 3018 3019static void * 3020hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3021 struct pcm_channel *c, int dir) 3022{ 3023 struct hdac_devinfo *devinfo = data; 3024 struct hdac_softc *sc = devinfo->codec->sc; 3025 struct hdac_chan *ch; 3026 3027 hdac_lock(sc); 3028 if (dir == PCMDIR_PLAY) { 3029 ch = &sc->play; 3030 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3031 devinfo->function.audio.playcnt++; 3032 } else { 3033 ch = &sc->rec; 3034 ch->off = devinfo->function.audio.reccnt << 5; 3035 devinfo->function.audio.reccnt++; 3036 } 3037 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3038 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3039 ch->pcmrates[0] = 48000; 3040 ch->pcmrates[1] = 0; 3041 } 3042 if (sc->pos_dma.dma_vaddr != NULL) 3043 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3044 (sc->streamcnt * 8)); 3045 else 3046 ch->dmapos = NULL; 3047 ch->sid = ++sc->streamcnt; 3048 ch->dir = dir; 3049 ch->b = b; 3050 ch->c = c; 3051 ch->devinfo = devinfo; 3052 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3053 ch->blkcnt = sc->chan_blkcnt; 3054 hdac_unlock(sc); 3055 3056 if (hdac_bdl_alloc(ch) != 0) { 3057 ch->blkcnt = 0; 3058 return (NULL); 3059 } 3060 3061 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3062 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3063 sc->chan_size) != 0) 3064 return (NULL); 3065 3066 return (ch); 3067} 3068 3069static int 3070hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3071{ 3072 struct hdac_chan *ch = data; 3073 int i; 3074 3075 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3076 if (format == ch->caps.fmtlist[i]) { 3077 ch->fmt = format; 3078 return (0); 3079 } 3080 } 3081 3082 return (EINVAL); 3083} 3084 3085static int 3086hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3087{ 3088 struct hdac_chan *ch = data; 3089 uint32_t spd = 0, threshold; 3090 int i; 3091 3092 for (i = 0; ch->pcmrates[i] != 0; i++) { 3093 spd = ch->pcmrates[i]; 3094 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3095 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3096 if (speed < threshold) 3097 break; 3098 } 3099 3100 if (spd == 0) /* impossible */ 3101 ch->spd = 48000; 3102 else 3103 ch->spd = spd; 3104 3105 return (ch->spd); 3106} 3107 3108static void 3109hdac_stream_setup(struct hdac_chan *ch) 3110{ 3111 struct hdac_softc *sc = ch->devinfo->codec->sc; 3112 struct hdac_widget *w; 3113 int i, chn, totalchn; 3114 nid_t cad = ch->devinfo->codec->cad; 3115 uint16_t fmt; 3116 3117 fmt = 0; 3118 if (ch->fmt & AFMT_S16_LE) 3119 fmt |= ch->bit16 << 4; 3120 else if (ch->fmt & AFMT_S32_LE) 3121 fmt |= ch->bit32 << 4; 3122 else 3123 fmt |= 1 << 4; 3124 3125 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3126 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3127 fmt |= hda_rate_tab[i].base; 3128 fmt |= hda_rate_tab[i].mul; 3129 fmt |= hda_rate_tab[i].div; 3130 break; 3131 } 3132 } 3133 3134 if (ch->fmt & AFMT_STEREO) { 3135 fmt |= 1; 3136 totalchn = 2; 3137 } else 3138 totalchn = 1; 3139 3140 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3141 3142 chn = 0; 3143 for (i = 0; ch->io[i] != -1; i++) { 3144 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3145 if (w == NULL) 3146 continue; 3147 HDA_BOOTVERBOSE( 3148 device_printf(sc->dev, 3149 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3150 "fmt=0x%08x\n", 3151 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3152 ch->io[i], fmt); 3153 ); 3154 hdac_command(sc, 3155 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3156 hdac_command(sc, 3157 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3158 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), cad); 3159 chn += 3160 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3161 2 : 1; 3162 } 3163} 3164 3165static int 3166hdac_channel_setfragments(kobj_t obj, void *data, 3167 uint32_t blksz, uint32_t blkcnt) 3168{ 3169 struct hdac_chan *ch = data; 3170 struct hdac_softc *sc = ch->devinfo->codec->sc; 3171 3172 blksz &= HDA_BLK_ALIGN; 3173 3174 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3175 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3176 if (blksz < HDA_BLK_MIN) 3177 blksz = HDA_BLK_MIN; 3178 if (blkcnt > HDA_BDL_MAX) 3179 blkcnt = HDA_BDL_MAX; 3180 if (blkcnt < HDA_BDL_MIN) 3181 blkcnt = HDA_BDL_MIN; 3182 3183 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3184 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3185 blkcnt >>= 1; 3186 else if ((blksz >> 1) >= HDA_BLK_MIN) 3187 blksz >>= 1; 3188 else 3189 break; 3190 } 3191 3192 if ((sndbuf_getblksz(ch->b) != blksz || 3193 sndbuf_getblkcnt(ch->b) != blkcnt) && 3194 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3195 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3196 __func__, blksz, blkcnt); 3197 3198 ch->blksz = sndbuf_getblksz(ch->b); 3199 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3200 3201 return (1); 3202} 3203 3204static int 3205hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3206{ 3207 struct hdac_chan *ch = data; 3208 struct hdac_softc *sc = ch->devinfo->codec->sc; 3209 3210 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3211 3212 return (ch->blksz); 3213} 3214 3215static void 3216hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3217{ 3218 struct hdac_devinfo *devinfo = ch->devinfo; 3219 nid_t cad = devinfo->codec->cad; 3220 int i; 3221 3222 hdac_stream_stop(ch); 3223 3224 for (i = 0; ch->io[i] != -1; i++) { 3225 hdac_command(sc, 3226 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3227 0), cad); 3228 } 3229} 3230 3231static void 3232hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3233{ 3234 ch->ptr = 0; 3235 ch->prevptr = 0; 3236 hdac_stream_stop(ch); 3237 hdac_stream_reset(ch); 3238 hdac_bdl_setup(ch); 3239 hdac_stream_setid(ch); 3240 hdac_stream_setup(ch); 3241 hdac_stream_start(ch); 3242} 3243 3244static int 3245hdac_channel_trigger(kobj_t obj, void *data, int go) 3246{ 3247 struct hdac_chan *ch = data; 3248 struct hdac_softc *sc = ch->devinfo->codec->sc; 3249 3250 if (!PCMTRIG_COMMON(go)) 3251 return (0); 3252 3253 hdac_lock(sc); 3254 switch (go) { 3255 case PCMTRIG_START: 3256 hdac_channel_start(sc, ch); 3257 break; 3258 case PCMTRIG_STOP: 3259 case PCMTRIG_ABORT: 3260 hdac_channel_stop(sc, ch); 3261 break; 3262 default: 3263 break; 3264 } 3265 hdac_unlock(sc); 3266 3267 return (0); 3268} 3269 3270static int 3271hdac_channel_getptr(kobj_t obj, void *data) 3272{ 3273 struct hdac_chan *ch = data; 3274 struct hdac_softc *sc = ch->devinfo->codec->sc; 3275 uint32_t ptr; 3276 3277 hdac_lock(sc); 3278 if (sc->polling != 0) 3279 ptr = ch->ptr; 3280 else if (ch->dmapos != NULL) 3281 ptr = *(ch->dmapos); 3282 else 3283 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3284 hdac_unlock(sc); 3285 3286 /* 3287 * Round to available space and force 128 bytes aligment. 3288 */ 3289 ptr %= ch->blksz * ch->blkcnt; 3290 ptr &= HDA_BLK_ALIGN; 3291 3292 return (ptr); 3293} 3294 3295static struct pcmchan_caps * 3296hdac_channel_getcaps(kobj_t obj, void *data) 3297{ 3298 return (&((struct hdac_chan *)data)->caps); 3299} 3300 3301static kobj_method_t hdac_channel_methods[] = { 3302 KOBJMETHOD(channel_init, hdac_channel_init), 3303 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3304 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3305 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3306 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3307 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3308 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3309 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3310 { 0, 0 } 3311}; 3312CHANNEL_DECLARE(hdac_channel); 3313 3314static void 3315hdac_jack_poll_callback(void *arg) 3316{ 3317 struct hdac_devinfo *devinfo = arg; 3318 struct hdac_softc *sc; 3319 3320 if (devinfo == NULL || devinfo->codec == NULL || 3321 devinfo->codec->sc == NULL) 3322 return; 3323 sc = devinfo->codec->sc; 3324 hdac_lock(sc); 3325 if (sc->poll_ival == 0) { 3326 hdac_unlock(sc); 3327 return; 3328 } 3329 hdac_hp_switch_handler(devinfo); 3330 callout_reset(&sc->poll_jack, sc->poll_ival, 3331 hdac_jack_poll_callback, devinfo); 3332 hdac_unlock(sc); 3333} 3334 3335static int 3336hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3337{ 3338 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3339 struct hdac_softc *sc = devinfo->codec->sc; 3340 struct hdac_widget *w, *cw; 3341 struct hdac_audio_ctl *ctl; 3342 uint32_t mask, recmask, id; 3343 int i, j, softpcmvol; 3344 nid_t cad; 3345 3346 hdac_lock(sc); 3347 3348 mask = 0; 3349 recmask = 0; 3350 3351 id = hdac_codec_id(devinfo); 3352 cad = devinfo->codec->cad; 3353 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3354 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3355 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3356 continue; 3357 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3358 if (w == NULL || w->enable == 0 || w->type != 3359 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3360 continue; 3361 if (hdac_hp_switch[i].polling != 0) 3362 callout_reset(&sc->poll_jack, 1, 3363 hdac_jack_poll_callback, devinfo); 3364 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3365 hdac_command(sc, 3366 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3367 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3368 HDAC_UNSOLTAG_EVENT_HP), cad); 3369 else 3370 continue; 3371 hdac_hp_switch_handler(devinfo); 3372 HDA_BOOTVERBOSE( 3373 device_printf(sc->dev, 3374 "HDA_DEBUG: Enabling headphone/speaker " 3375 "audio routing switching:\n"); 3376 device_printf(sc->dev, 3377 "HDA_DEBUG: \tindex=%d nid=%d " 3378 "pci_subvendor=0x%08x " 3379 "codec=0x%08x [%s]\n", 3380 i, w->nid, sc->pci_subvendor, id, 3381 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3382 "UNSOL"); 3383 ); 3384 break; 3385 } 3386 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3387 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3388 sc->pci_subvendor) && 3389 hdac_eapd_switch[i].id == id)) 3390 continue; 3391 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3392 if (w == NULL || w->enable == 0) 3393 break; 3394 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3395 w->param.eapdbtl == HDAC_INVALID) 3396 break; 3397 mask |= SOUND_MASK_OGAIN; 3398 break; 3399 } 3400 3401 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3402 w = hdac_widget_get(devinfo, i); 3403 if (w == NULL || w->enable == 0) 3404 continue; 3405 mask |= w->ctlflags; 3406 if (!(w->pflags & HDA_ADC_RECSEL)) 3407 continue; 3408 for (j = 0; j < w->nconns; j++) { 3409 cw = hdac_widget_get(devinfo, w->conns[j]); 3410 if (cw == NULL || cw->enable == 0) 3411 continue; 3412 recmask |= cw->ctlflags; 3413 } 3414 } 3415 3416 if (!(mask & SOUND_MASK_PCM)) { 3417 softpcmvol = 1; 3418 mask |= SOUND_MASK_PCM; 3419 } else 3420 softpcmvol = (devinfo->function.audio.quirks & 3421 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3422 3423 i = 0; 3424 ctl = NULL; 3425 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3426 if (ctl->widget == NULL || ctl->enable == 0) 3427 continue; 3428 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3429 continue; 3430 if (ctl->step > 0) 3431 break; 3432 } 3433 3434 if (softpcmvol == 1 || ctl == NULL) { 3435 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3436 HDA_BOOTVERBOSE( 3437 device_printf(sc->dev, 3438 "HDA_DEBUG: %s Soft PCM volume\n", 3439 (softpcmvol == 1) ? 3440 "Forcing" : "Enabling"); 3441 ); 3442 i = 0; 3443 /* 3444 * XXX Temporary quirk for STAC9220, until the parser 3445 * become smarter. 3446 */ 3447 if (id == HDA_CODEC_STAC9220) { 3448 mask |= SOUND_MASK_VOLUME; 3449 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3450 NULL) { 3451 if (ctl->widget == NULL || ctl->enable == 0) 3452 continue; 3453 if (ctl->widget->nid == 11 && ctl->index == 0) { 3454 ctl->ossmask = SOUND_MASK_VOLUME; 3455 ctl->ossval = 100 | (100 << 8); 3456 } else 3457 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3458 } 3459 } else if (id == HDA_CODEC_STAC9221) { 3460 mask |= SOUND_MASK_VOLUME; 3461 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3462 NULL) { 3463 if (ctl->widget == NULL) 3464 continue; 3465 if (ctl->widget->type == 3466 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3467 ctl->index == 0 && (ctl->widget->nid == 2 || 3468 ctl->widget->enable != 0)) { 3469 ctl->enable = 1; 3470 ctl->ossmask = SOUND_MASK_VOLUME; 3471 ctl->ossval = 100 | (100 << 8); 3472 } else if (ctl->enable == 0) 3473 continue; 3474 else 3475 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3476 } 3477 } else { 3478 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3479 SOUND_MASK_PCM); 3480 if (!(mask & SOUND_MASK_VOLUME)) 3481 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3482 SOUND_MIXER_NONE); 3483 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3484 NULL) { 3485 if (ctl->widget == NULL || ctl->enable == 0) 3486 continue; 3487 if (!HDA_FLAG_MATCH(ctl->ossmask, 3488 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3489 continue; 3490 if (!(ctl->mute == 1 && ctl->step == 0)) 3491 ctl->enable = 0; 3492 } 3493 } 3494 } 3495 3496 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3497 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3498 SOUND_MASK_OGAIN); 3499 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3500 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3501 3502 mix_setrecdevs(m, recmask); 3503 mix_setdevs(m, mask); 3504 3505 hdac_unlock(sc); 3506 3507 return (0); 3508} 3509 3510static int 3511hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3512 unsigned left, unsigned right) 3513{ 3514 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3515 struct hdac_softc *sc = devinfo->codec->sc; 3516 struct hdac_widget *w; 3517 struct hdac_audio_ctl *ctl; 3518 uint32_t id, mute; 3519 int lvol, rvol, mlvol, mrvol; 3520 int i = 0; 3521 3522 hdac_lock(sc); 3523 if (dev == SOUND_MIXER_OGAIN) { 3524 uint32_t orig; 3525 /*if (left != right || !(left == 0 || left == 1)) { 3526 hdac_unlock(sc); 3527 return (-1); 3528 }*/ 3529 id = hdac_codec_id(devinfo); 3530 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3531 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3532 sc->pci_subvendor) && 3533 hdac_eapd_switch[i].id == id) 3534 break; 3535 } 3536 if (i >= HDAC_EAPD_SWITCH_LEN) { 3537 hdac_unlock(sc); 3538 return (-1); 3539 } 3540 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3541 if (w == NULL || 3542 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3543 w->param.eapdbtl == HDAC_INVALID) { 3544 hdac_unlock(sc); 3545 return (-1); 3546 } 3547 orig = w->param.eapdbtl; 3548 if (left == 0) 3549 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3550 else 3551 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3552 if (orig != w->param.eapdbtl) { 3553 uint32_t val; 3554 3555 if (hdac_eapd_switch[i].hp_switch != 0) 3556 hdac_hp_switch_handler(devinfo); 3557 val = w->param.eapdbtl; 3558 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3559 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3560 hdac_command(sc, 3561 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3562 w->nid, val), devinfo->codec->cad); 3563 } 3564 hdac_unlock(sc); 3565 return (left | (left << 8)); 3566 } 3567 if (dev == SOUND_MIXER_VOLUME) 3568 devinfo->function.audio.mvol = left | (right << 8); 3569 3570 mlvol = devinfo->function.audio.mvol & 0x7f; 3571 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3572 lvol = 0; 3573 rvol = 0; 3574 3575 i = 0; 3576 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3577 if (ctl->widget == NULL || ctl->enable == 0 || 3578 !(ctl->ossmask & (1 << dev))) 3579 continue; 3580 switch (dev) { 3581 case SOUND_MIXER_VOLUME: 3582 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3583 lvol = (lvol * ctl->step) / 100; 3584 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3585 rvol = (rvol * ctl->step) / 100; 3586 break; 3587 default: 3588 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3589 lvol = (left * mlvol) / 100; 3590 lvol = (lvol * ctl->step) / 100; 3591 rvol = (right * mrvol) / 100; 3592 rvol = (rvol * ctl->step) / 100; 3593 } else { 3594 lvol = (left * ctl->step) / 100; 3595 rvol = (right * ctl->step) / 100; 3596 } 3597 ctl->ossval = left | (right << 8); 3598 break; 3599 } 3600 mute = 0; 3601 if (ctl->step < 1) { 3602 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3603 (ctl->muted & HDA_AMP_MUTE_LEFT); 3604 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3605 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3606 } else { 3607 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3608 (ctl->muted & HDA_AMP_MUTE_LEFT); 3609 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3610 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3611 } 3612 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3613 } 3614 hdac_unlock(sc); 3615 3616 return (left | (right << 8)); 3617} 3618 3619static int 3620hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3621{ 3622 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3623 struct hdac_widget *w, *cw; 3624 struct hdac_softc *sc = devinfo->codec->sc; 3625 uint32_t ret = src, target; 3626 int i, j; 3627 3628 target = 0; 3629 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3630 if (src & (1 << i)) { 3631 target = 1 << i; 3632 break; 3633 } 3634 } 3635 3636 hdac_lock(sc); 3637 3638 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3639 w = hdac_widget_get(devinfo, i); 3640 if (w == NULL || w->enable == 0) 3641 continue; 3642 if (!(w->pflags & HDA_ADC_RECSEL)) 3643 continue; 3644 for (j = 0; j < w->nconns; j++) { 3645 cw = hdac_widget_get(devinfo, w->conns[j]); 3646 if (cw == NULL || cw->enable == 0) 3647 continue; 3648 if ((target == SOUND_MASK_VOLUME && 3649 cw->type != 3650 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3651 (target != SOUND_MASK_VOLUME && 3652 cw->type == 3653 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3654 continue; 3655 if (cw->ctlflags & target) { 3656 if (!(w->pflags & HDA_ADC_LOCKED)) 3657 hdac_widget_connection_select(w, j); 3658 ret = target; 3659 j += w->nconns; 3660 } 3661 } 3662 } 3663 3664 hdac_unlock(sc); 3665 3666 return (ret); 3667} 3668 3669static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3670 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3671 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3672 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3673 { 0, 0 } 3674}; 3675MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3676 3677static void 3678hdac_unsolq_task(void *context, int pending) 3679{ 3680 struct hdac_softc *sc; 3681 3682 sc = (struct hdac_softc *)context; 3683 3684 hdac_lock(sc); 3685 hdac_unsolq_flush(sc); 3686 hdac_unlock(sc); 3687} 3688 3689/**************************************************************************** 3690 * int hdac_attach(device_t) 3691 * 3692 * Attach the device into the kernel. Interrupts usually won't be enabled 3693 * when this function is called. Setup everything that doesn't require 3694 * interrupts and defer probing of codecs until interrupts are enabled. 3695 ****************************************************************************/ 3696static int 3697hdac_attach(device_t dev) 3698{ 3699 struct hdac_softc *sc; 3700 int result; 3701 int i; 3702 uint16_t vendor; 3703 uint8_t v; 3704 3705 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3706 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3707 sc->dev = dev; 3708 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3709 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3710 vendor = pci_get_vendor(dev); 3711 3712 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3713 /* Screw nx6325 - subdevice/subvendor swapped */ 3714 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3715 } 3716 3717 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3718 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3719 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3720 3721 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3722 3723 sc->poll_ticks = 1; 3724 sc->poll_ival = HDAC_POLL_INTERVAL; 3725 if (resource_int_value(device_get_name(dev), 3726 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3727 sc->polling = 1; 3728 else 3729 sc->polling = 0; 3730 3731 sc->chan_size = pcm_getbuffersize(dev, 3732 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3733 3734 if (resource_int_value(device_get_name(dev), 3735 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3736 i &= HDA_BLK_ALIGN; 3737 if (i < HDA_BLK_MIN) 3738 i = HDA_BLK_MIN; 3739 sc->chan_blkcnt = sc->chan_size / i; 3740 i = 0; 3741 while (sc->chan_blkcnt >> i) 3742 i++; 3743 sc->chan_blkcnt = 1 << (i - 1); 3744 if (sc->chan_blkcnt < HDA_BDL_MIN) 3745 sc->chan_blkcnt = HDA_BDL_MIN; 3746 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3747 sc->chan_blkcnt = HDA_BDL_MAX; 3748 } else 3749 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3750 3751 result = bus_dma_tag_create(NULL, /* parent */ 3752 HDAC_DMA_ALIGNMENT, /* alignment */ 3753 0, /* boundary */ 3754 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3755 BUS_SPACE_MAXADDR, /* highaddr */ 3756 NULL, /* filtfunc */ 3757 NULL, /* fistfuncarg */ 3758 sc->chan_size, /* maxsize */ 3759 1, /* nsegments */ 3760 sc->chan_size, /* maxsegsz */ 3761 0, /* flags */ 3762 NULL, /* lockfunc */ 3763 NULL, /* lockfuncarg */ 3764 &sc->chan_dmat); /* dmat */ 3765 if (result != 0) { 3766 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3767 __func__, result); 3768 snd_mtxfree(sc->lock); 3769 free(sc, M_DEVBUF); 3770 return (ENXIO); 3771 } 3772 3773 3774 sc->hdabus = NULL; 3775 for (i = 0; i < HDAC_CODEC_MAX; i++) 3776 sc->codecs[i] = NULL; 3777 3778 pci_enable_busmaster(dev); 3779 3780 if (vendor == INTEL_VENDORID) { 3781 /* TCSEL -> TC0 */ 3782 v = pci_read_config(dev, 0x44, 1); 3783 pci_write_config(dev, 0x44, v & 0xf8, 1); 3784 HDA_BOOTVERBOSE( 3785 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3786 pci_read_config(dev, 0x44, 1)); 3787 ); 3788 } 3789 3790#if __FreeBSD_version >= 602106 3791 if (resource_int_value(device_get_name(dev), 3792 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3793 pci_msi_count(dev) == 1) 3794 sc->flags |= HDAC_F_MSI; 3795 else 3796#endif 3797 sc->flags &= ~HDAC_F_MSI; 3798 3799#if defined(__i386__) || defined(__amd64__) 3800 sc->flags |= HDAC_F_DMA_NOCACHE; 3801 3802 if (resource_int_value(device_get_name(dev), 3803 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3804#else 3805 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3806#endif 3807 /* 3808 * Try to enable PCIe snoop to avoid messing around with 3809 * uncacheable DMA attribute. Since PCIe snoop register 3810 * config is pretty much vendor specific, there are no 3811 * general solutions on how to enable it, forcing us (even 3812 * Microsoft) to enable uncacheable or write combined DMA 3813 * by default. 3814 * 3815 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3816 */ 3817 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3818 if (hdac_pcie_snoop[i].vendor != vendor) 3819 continue; 3820 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3821 if (hdac_pcie_snoop[i].reg == 0x00) 3822 break; 3823 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3824 if ((v & hdac_pcie_snoop[i].enable) == 3825 hdac_pcie_snoop[i].enable) 3826 break; 3827 v &= hdac_pcie_snoop[i].mask; 3828 v |= hdac_pcie_snoop[i].enable; 3829 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3830 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3831 if ((v & hdac_pcie_snoop[i].enable) != 3832 hdac_pcie_snoop[i].enable) { 3833 HDA_BOOTVERBOSE( 3834 device_printf(dev, 3835 "WARNING: Failed to enable PCIe " 3836 "snoop!\n"); 3837 ); 3838#if defined(__i386__) || defined(__amd64__) 3839 sc->flags |= HDAC_F_DMA_NOCACHE; 3840#endif 3841 } 3842 break; 3843 } 3844#if defined(__i386__) || defined(__amd64__) 3845 } 3846#endif 3847 3848 HDA_BOOTVERBOSE( 3849 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3850 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3851 "Uncacheable" : "PCIe snoop", vendor); 3852 ); 3853 3854 /* Allocate resources */ 3855 result = hdac_mem_alloc(sc); 3856 if (result != 0) 3857 goto hdac_attach_fail; 3858 result = hdac_irq_alloc(sc); 3859 if (result != 0) 3860 goto hdac_attach_fail; 3861 3862 /* Get Capabilities */ 3863 result = hdac_get_capabilities(sc); 3864 if (result != 0) 3865 goto hdac_attach_fail; 3866 3867 /* Allocate CORB and RIRB dma memory */ 3868 result = hdac_dma_alloc(sc, &sc->corb_dma, 3869 sc->corb_size * sizeof(uint32_t)); 3870 if (result != 0) 3871 goto hdac_attach_fail; 3872 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3873 sc->rirb_size * sizeof(struct hdac_rirb)); 3874 if (result != 0) 3875 goto hdac_attach_fail; 3876 3877 /* Quiesce everything */ 3878 hdac_reset(sc); 3879 3880 /* Initialize the CORB and RIRB */ 3881 hdac_corb_init(sc); 3882 hdac_rirb_init(sc); 3883 3884 /* Defer remaining of initialization until interrupts are enabled */ 3885 sc->intrhook.ich_func = hdac_attach2; 3886 sc->intrhook.ich_arg = (void *)sc; 3887 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3888 sc->intrhook.ich_func = NULL; 3889 hdac_attach2((void *)sc); 3890 } 3891 3892 return (0); 3893 3894hdac_attach_fail: 3895 hdac_irq_free(sc); 3896 hdac_dma_free(sc, &sc->rirb_dma); 3897 hdac_dma_free(sc, &sc->corb_dma); 3898 hdac_mem_free(sc); 3899 snd_mtxfree(sc->lock); 3900 free(sc, M_DEVBUF); 3901 3902 return (ENXIO); 3903} 3904 3905static void 3906hdac_audio_parse(struct hdac_devinfo *devinfo) 3907{ 3908 struct hdac_softc *sc = devinfo->codec->sc; 3909 struct hdac_widget *w; 3910 uint32_t res; 3911 int i; 3912 nid_t cad, nid; 3913 3914 cad = devinfo->codec->cad; 3915 nid = devinfo->nid; 3916 3917 hdac_command(sc, 3918 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3919 3920 DELAY(100); 3921 3922 res = hdac_command(sc, 3923 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3924 3925 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3926 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3927 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3928 3929 res = hdac_command(sc, 3930 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3931 devinfo->function.audio.gpio = res; 3932 3933 HDA_BOOTVERBOSE( 3934 device_printf(sc->dev, " Vendor: 0x%08x\n", 3935 devinfo->vendor_id); 3936 device_printf(sc->dev, " Device: 0x%08x\n", 3937 devinfo->device_id); 3938 device_printf(sc->dev, " Revision: 0x%08x\n", 3939 devinfo->revision_id); 3940 device_printf(sc->dev, " Stepping: 0x%08x\n", 3941 devinfo->stepping_id); 3942 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3943 sc->pci_subvendor); 3944 device_printf(sc->dev, " Nodes: start=%d " 3945 "endnode=%d total=%d\n", 3946 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3947 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3948 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3949 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3950 sc->num_iss, sc->num_oss, sc->num_bss); 3951 device_printf(sc->dev, " GPIO: 0x%08x\n", 3952 devinfo->function.audio.gpio); 3953 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3954 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3955 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3956 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3957 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3958 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3959 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3960 ); 3961 3962 res = hdac_command(sc, 3963 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3964 cad); 3965 devinfo->function.audio.supp_stream_formats = res; 3966 3967 res = hdac_command(sc, 3968 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3969 cad); 3970 devinfo->function.audio.supp_pcm_size_rate = res; 3971 3972 res = hdac_command(sc, 3973 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3974 cad); 3975 devinfo->function.audio.outamp_cap = res; 3976 3977 res = hdac_command(sc, 3978 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3979 cad); 3980 devinfo->function.audio.inamp_cap = res; 3981 3982 if (devinfo->nodecnt > 0) 3983 devinfo->widget = (struct hdac_widget *)malloc( 3984 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3985 M_NOWAIT | M_ZERO); 3986 else 3987 devinfo->widget = NULL; 3988 3989 if (devinfo->widget == NULL) { 3990 device_printf(sc->dev, "unable to allocate widgets!\n"); 3991 devinfo->endnode = devinfo->startnode; 3992 devinfo->nodecnt = 0; 3993 return; 3994 } 3995 3996 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3997 w = hdac_widget_get(devinfo, i); 3998 if (w == NULL) 3999 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4000 else { 4001 w->devinfo = devinfo; 4002 w->nid = i; 4003 w->enable = 1; 4004 w->selconn = -1; 4005 w->pflags = 0; 4006 w->ctlflags = 0; 4007 w->param.eapdbtl = HDAC_INVALID; 4008 hdac_widget_parse(w); 4009 } 4010 } 4011} 4012 4013static void 4014hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4015{ 4016 struct hdac_softc *sc = devinfo->codec->sc; 4017 struct hdac_audio_ctl *ctls; 4018 struct hdac_widget *w, *cw; 4019 int i, j, cnt, max, ocap, icap; 4020 int mute, offset, step, size; 4021 4022 /* XXX This is redundant */ 4023 max = 0; 4024 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4025 w = hdac_widget_get(devinfo, i); 4026 if (w == NULL || w->enable == 0) 4027 continue; 4028 if (w->param.outamp_cap != 0) 4029 max++; 4030 if (w->param.inamp_cap != 0) { 4031 switch (w->type) { 4032 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4033 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4034 for (j = 0; j < w->nconns; j++) { 4035 cw = hdac_widget_get(devinfo, 4036 w->conns[j]); 4037 if (cw == NULL || cw->enable == 0) 4038 continue; 4039 max++; 4040 } 4041 break; 4042 default: 4043 max++; 4044 break; 4045 } 4046 } 4047 } 4048 4049 devinfo->function.audio.ctlcnt = max; 4050 4051 if (max < 1) 4052 return; 4053 4054 ctls = (struct hdac_audio_ctl *)malloc( 4055 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4056 4057 if (ctls == NULL) { 4058 /* Blekh! */ 4059 device_printf(sc->dev, "unable to allocate ctls!\n"); 4060 devinfo->function.audio.ctlcnt = 0; 4061 return; 4062 } 4063 4064 cnt = 0; 4065 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4066 if (cnt >= max) { 4067 device_printf(sc->dev, "%s: Ctl overflow!\n", 4068 __func__); 4069 break; 4070 } 4071 w = hdac_widget_get(devinfo, i); 4072 if (w == NULL || w->enable == 0) 4073 continue; 4074 ocap = w->param.outamp_cap; 4075 icap = w->param.inamp_cap; 4076 if (ocap != 0) { 4077 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4078 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4079 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4080 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4081 /*if (offset > step) { 4082 HDA_BOOTVERBOSE( 4083 device_printf(sc->dev, 4084 "HDA_DEBUG: BUGGY outamp: nid=%d " 4085 "[offset=%d > step=%d]\n", 4086 w->nid, offset, step); 4087 ); 4088 offset = step; 4089 }*/ 4090 ctls[cnt].enable = 1; 4091 ctls[cnt].widget = w; 4092 ctls[cnt].mute = mute; 4093 ctls[cnt].step = step; 4094 ctls[cnt].size = size; 4095 ctls[cnt].offset = offset; 4096 ctls[cnt].left = offset; 4097 ctls[cnt].right = offset; 4098 ctls[cnt++].dir = HDA_CTL_OUT; 4099 } 4100 4101 if (icap != 0) { 4102 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4103 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4104 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4105 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4106 /*if (offset > step) { 4107 HDA_BOOTVERBOSE( 4108 device_printf(sc->dev, 4109 "HDA_DEBUG: BUGGY inamp: nid=%d " 4110 "[offset=%d > step=%d]\n", 4111 w->nid, offset, step); 4112 ); 4113 offset = step; 4114 }*/ 4115 switch (w->type) { 4116 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4117 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4118 for (j = 0; j < w->nconns; j++) { 4119 if (cnt >= max) { 4120 device_printf(sc->dev, 4121 "%s: Ctl overflow!\n", 4122 __func__); 4123 break; 4124 } 4125 cw = hdac_widget_get(devinfo, 4126 w->conns[j]); 4127 if (cw == NULL || cw->enable == 0) 4128 continue; 4129 ctls[cnt].enable = 1; 4130 ctls[cnt].widget = w; 4131 ctls[cnt].childwidget = cw; 4132 ctls[cnt].index = j; 4133 ctls[cnt].mute = mute; 4134 ctls[cnt].step = step; 4135 ctls[cnt].size = size; 4136 ctls[cnt].offset = offset; 4137 ctls[cnt].left = offset; 4138 ctls[cnt].right = offset; 4139 ctls[cnt++].dir = HDA_CTL_IN; 4140 } 4141 break; 4142 default: 4143 if (cnt >= max) { 4144 device_printf(sc->dev, 4145 "%s: Ctl overflow!\n", 4146 __func__); 4147 break; 4148 } 4149 ctls[cnt].enable = 1; 4150 ctls[cnt].widget = w; 4151 ctls[cnt].mute = mute; 4152 ctls[cnt].step = step; 4153 ctls[cnt].size = size; 4154 ctls[cnt].offset = offset; 4155 ctls[cnt].left = offset; 4156 ctls[cnt].right = offset; 4157 ctls[cnt++].dir = HDA_CTL_IN; 4158 break; 4159 } 4160 } 4161 } 4162 4163 devinfo->function.audio.ctl = ctls; 4164} 4165 4166static const struct { 4167 uint32_t model; 4168 uint32_t id; 4169 uint32_t set, unset; 4170} hdac_quirks[] = { 4171 /* 4172 * XXX Force stereo quirk. Monoural recording / playback 4173 * on few codecs (especially ALC880) seems broken or 4174 * perhaps unsupported. 4175 */ 4176 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4177 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4178 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4179 HDA_QUIRK_GPIO0, 0 }, 4180 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4181 HDA_QUIRK_GPIO0, 0 }, 4182 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4183 HDA_QUIRK_GPIO0, 0 }, 4184 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4185 HDA_QUIRK_GPIO0, 0 }, 4186 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4187 HDA_QUIRK_GPIO0, 0 }, 4188 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4189 HDA_QUIRK_EAPDINV, 0 }, 4190 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4191 HDA_QUIRK_EAPDINV, 0 }, 4192 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4193 HDA_QUIRK_OVREF, 0 }, 4194 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4195 HDA_QUIRK_OVREF, 0 }, 4196 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4197 HDA_QUIRK_OVREF, 0 }, 4198 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4199 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4200 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4201 HDA_QUIRK_GPIO1, 0 }, 4202 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4203 HDA_QUIRK_EAPDINV, 0 }, 4204 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4205 HDA_QUIRK_EAPDINV, 0 }, 4206 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4207 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4208 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4209 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4210 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4211 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4212 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4213 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4214 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4215 0, HDA_QUIRK_FORCESTEREO }, 4216 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4217 HDA_QUIRK_SOFTPCMVOL, 0 } 4218}; 4219#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4220 4221static void 4222hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4223{ 4224 struct hdac_widget *w; 4225 struct hdac_audio_ctl *ctl; 4226 uint32_t id, subvendor; 4227 int i; 4228 4229 id = hdac_codec_id(devinfo); 4230 subvendor = devinfo->codec->sc->pci_subvendor; 4231 4232 /* 4233 * Quirks 4234 */ 4235 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4236 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4237 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4238 continue; 4239 if (hdac_quirks[i].set != 0) 4240 devinfo->function.audio.quirks |= 4241 hdac_quirks[i].set; 4242 if (hdac_quirks[i].unset != 0) 4243 devinfo->function.audio.quirks &= 4244 ~(hdac_quirks[i].unset); 4245 } 4246 4247 switch (id) { 4248 case HDA_CODEC_ALC260: 4249 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4250 w = hdac_widget_get(devinfo, i); 4251 if (w == NULL || w->enable == 0) 4252 continue; 4253 if (w->type != 4254 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4255 continue; 4256 if (w->nid != 5) 4257 w->enable = 0; 4258 } 4259 if (subvendor == HP_XW4300_SUBVENDOR) { 4260 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4261 if (ctl != NULL && ctl->widget != NULL) { 4262 ctl->ossmask = SOUND_MASK_SPEAKER; 4263 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4264 } 4265 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4266 if (ctl != NULL && ctl->widget != NULL) { 4267 ctl->ossmask = SOUND_MASK_SPEAKER; 4268 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4269 } 4270 } else if (subvendor == HP_3010_SUBVENDOR) { 4271 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4272 if (ctl != NULL && ctl->widget != NULL) { 4273 ctl->ossmask = SOUND_MASK_SPEAKER; 4274 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4275 } 4276 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4277 if (ctl != NULL && ctl->widget != NULL) { 4278 ctl->ossmask = SOUND_MASK_SPEAKER; 4279 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4280 } 4281 } 4282 break; 4283 case HDA_CODEC_ALC262: 4284 if (subvendor == HP_DC7700_SUBVENDOR) { 4285 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4286 if (ctl != NULL && ctl->widget != NULL) { 4287 ctl->ossmask = SOUND_MASK_SPEAKER; 4288 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4289 } 4290 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4291 if (ctl != NULL && ctl->widget != NULL) { 4292 ctl->ossmask = SOUND_MASK_SPEAKER; 4293 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4294 } 4295 } 4296 break; 4297 case HDA_CODEC_ALC861: 4298 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4299 if (ctl != NULL) 4300 ctl->muted = HDA_AMP_MUTE_ALL; 4301 break; 4302 case HDA_CODEC_ALC880: 4303 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4304 w = hdac_widget_get(devinfo, i); 4305 if (w == NULL || w->enable == 0) 4306 continue; 4307 if (w->type == 4308 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4309 w->nid != 9 && w->nid != 29) { 4310 w->enable = 0; 4311 } else if (w->type != 4312 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4313 w->nid == 29) { 4314 w->type = 4315 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4316 w->param.widget_cap &= 4317 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4318 w->param.widget_cap |= 4319 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4320 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4321 strlcpy(w->name, "beep widget", sizeof(w->name)); 4322 } 4323 } 4324 break; 4325 case HDA_CODEC_ALC883: 4326 /* 4327 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4328 * Clear vref cap for jack connectivity. 4329 */ 4330 w = hdac_widget_get(devinfo, 24); 4331 if (w != NULL && w->enable != 0 && w->type == 4332 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4333 (w->wclass.pin.config & 4334 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4335 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4336 w->wclass.pin.cap &= ~( 4337 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4338 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4339 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4340 w = hdac_widget_get(devinfo, 25); 4341 if (w != NULL && w->enable != 0 && w->type == 4342 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4343 (w->wclass.pin.config & 4344 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4345 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4346 w->wclass.pin.cap &= ~( 4347 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4348 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4349 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4350 /* 4351 * nid: 26 = Line-in, leave it alone. 4352 */ 4353 break; 4354 case HDA_CODEC_AD1981HD: 4355 w = hdac_widget_get(devinfo, 11); 4356 if (w != NULL && w->enable != 0 && w->nconns > 3) 4357 w->selconn = 3; 4358 if (subvendor == IBM_M52_SUBVENDOR) { 4359 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4360 if (ctl != NULL) 4361 ctl->ossmask = SOUND_MASK_SPEAKER; 4362 } 4363 break; 4364 case HDA_CODEC_AD1986A: 4365 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4366 w = hdac_widget_get(devinfo, i); 4367 if (w == NULL || w->enable == 0) 4368 continue; 4369 if (w->type != 4370 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4371 continue; 4372 if (w->nid != 3) 4373 w->enable = 0; 4374 } 4375 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4376 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4377 /* nid 28 is mic, nid 29 is line-in */ 4378 w = hdac_widget_get(devinfo, 15); 4379 if (w != NULL) 4380 w->selconn = 2; 4381 w = hdac_widget_get(devinfo, 16); 4382 if (w != NULL) 4383 w->selconn = 1; 4384 } 4385 break; 4386 case HDA_CODEC_AD1988: 4387 case HDA_CODEC_AD1988B: 4388 /*w = hdac_widget_get(devinfo, 12); 4389 if (w != NULL) { 4390 w->selconn = 1; 4391 w->pflags |= HDA_ADC_LOCKED; 4392 } 4393 w = hdac_widget_get(devinfo, 13); 4394 if (w != NULL) { 4395 w->selconn = 4; 4396 w->pflags |= HDA_ADC_LOCKED; 4397 } 4398 w = hdac_widget_get(devinfo, 14); 4399 if (w != NULL) { 4400 w->selconn = 2; 4401 w->pflags |= HDA_ADC_LOCKED; 4402 }*/ 4403 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4404 if (ctl != NULL) { 4405 ctl->ossmask = SOUND_MASK_IGAIN; 4406 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4407 } 4408 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4409 if (ctl != NULL) { 4410 ctl->ossmask = SOUND_MASK_IGAIN; 4411 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4412 } 4413 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4414 if (ctl != NULL) { 4415 ctl->ossmask = SOUND_MASK_IGAIN; 4416 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4417 } 4418 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4419 if (ctl != NULL) { 4420 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4421 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4422 } 4423 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4424 if (ctl != NULL) { 4425 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4426 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4427 } 4428 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4429 if (ctl != NULL) { 4430 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4431 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4432 } 4433 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4434 if (ctl != NULL) { 4435 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4436 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4437 } 4438 break; 4439 case HDA_CODEC_STAC9221: 4440 /* 4441 * Dell XPS M1210 need all DACs for each output jacks 4442 */ 4443 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4444 break; 4445 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4446 w = hdac_widget_get(devinfo, i); 4447 if (w == NULL || w->enable == 0) 4448 continue; 4449 if (w->type != 4450 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4451 continue; 4452 if (w->nid != 2) 4453 w->enable = 0; 4454 } 4455 break; 4456 case HDA_CODEC_STAC9221D: 4457 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4458 w = hdac_widget_get(devinfo, i); 4459 if (w == NULL || w->enable == 0) 4460 continue; 4461 if (w->type == 4462 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4463 w->nid != 6) 4464 w->enable = 0; 4465 4466 } 4467 break; 4468 case HDA_CODEC_STAC9227: 4469 w = hdac_widget_get(devinfo, 8); 4470 if (w != NULL) 4471 w->enable = 0; 4472 w = hdac_widget_get(devinfo, 9); 4473 if (w != NULL) 4474 w->enable = 0; 4475 break; 4476 case HDA_CODEC_CXWAIKIKI: 4477 if (subvendor == HP_DV5000_SUBVENDOR) { 4478 w = hdac_widget_get(devinfo, 27); 4479 if (w != NULL) 4480 w->enable = 0; 4481 } 4482 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4483 if (ctl != NULL) 4484 ctl->ossmask = SOUND_MASK_SKIP; 4485 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4486 if (ctl != NULL && ctl->childwidget != NULL && 4487 ctl->childwidget->enable != 0) { 4488 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4489 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4490 } 4491 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4492 if (ctl != NULL && ctl->childwidget != NULL && 4493 ctl->childwidget->enable != 0) { 4494 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4495 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4496 } 4497 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4498 if (ctl != NULL && ctl->childwidget != NULL && 4499 ctl->childwidget->enable != 0) { 4500 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4501 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4502 } 4503 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4504 if (ctl != NULL) { 4505 ctl->ossmask = SOUND_MASK_SKIP; 4506 /* XXX mixer \=rec mic broken.. why?!? */ 4507 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4508 } 4509 break; 4510 default: 4511 break; 4512 } 4513} 4514 4515static int 4516hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4517{ 4518 int *dev = &devinfo->function.audio.ossidx; 4519 4520 while (*dev < SOUND_MIXER_NRDEVICES) { 4521 switch (*dev) { 4522 case SOUND_MIXER_VOLUME: 4523 case SOUND_MIXER_BASS: 4524 case SOUND_MIXER_TREBLE: 4525 case SOUND_MIXER_PCM: 4526 case SOUND_MIXER_SPEAKER: 4527 case SOUND_MIXER_LINE: 4528 case SOUND_MIXER_MIC: 4529 case SOUND_MIXER_CD: 4530 case SOUND_MIXER_RECLEV: 4531 case SOUND_MIXER_IGAIN: 4532 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4533 (*dev)++; 4534 break; 4535 default: 4536 return (*dev)++; 4537 break; 4538 } 4539 } 4540 4541 return (-1); 4542} 4543 4544static int 4545hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4546{ 4547 struct hdac_widget *w; 4548 int i, ret = 0; 4549 4550 if (depth > HDA_PARSE_MAXDEPTH) 4551 return (0); 4552 w = hdac_widget_get(devinfo, nid); 4553 if (w == NULL || w->enable == 0) 4554 return (0); 4555 switch (w->type) { 4556 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4557 w->pflags |= HDA_DAC_PATH; 4558 ret = 1; 4559 break; 4560 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4561 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4562 for (i = 0; i < w->nconns; i++) { 4563 if (hdac_widget_find_dac_path(devinfo, 4564 w->conns[i], depth + 1) != 0) { 4565 if (w->selconn == -1) 4566 w->selconn = i; 4567 ret = 1; 4568 w->pflags |= HDA_DAC_PATH; 4569 } 4570 } 4571 break; 4572 default: 4573 break; 4574 } 4575 return (ret); 4576} 4577 4578static int 4579hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4580{ 4581 struct hdac_widget *w; 4582 int i, conndev, ret = 0; 4583 4584 if (depth > HDA_PARSE_MAXDEPTH) 4585 return (0); 4586 w = hdac_widget_get(devinfo, nid); 4587 if (w == NULL || w->enable == 0) 4588 return (0); 4589 switch (w->type) { 4590 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4591 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4592 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4593 for (i = 0; i < w->nconns; i++) { 4594 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4595 depth + 1) != 0) { 4596 if (w->selconn == -1) 4597 w->selconn = i; 4598 w->pflags |= HDA_ADC_PATH; 4599 ret = 1; 4600 } 4601 } 4602 break; 4603 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4604 conndev = w->wclass.pin.config & 4605 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4606 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4607 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4608 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4609 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4610 w->pflags |= HDA_ADC_PATH; 4611 ret = 1; 4612 } 4613 break; 4614 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4615 if (w->pflags & HDA_DAC_PATH) { 4616 w->pflags |= HDA_ADC_PATH; 4617 ret = 1; 4618 } 4619 break;*/ 4620 default: 4621 break; 4622 } 4623 return (ret); 4624} 4625 4626static uint32_t 4627hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4628 nid_t nid, nid_t pnid, int index, int depth) 4629{ 4630 struct hdac_widget *w, *pw; 4631 struct hdac_audio_ctl *ctl; 4632 uint32_t fl = 0; 4633 int i, ossdev, conndev, strategy; 4634 4635 if (depth > HDA_PARSE_MAXDEPTH) 4636 return (0); 4637 4638 w = hdac_widget_get(devinfo, nid); 4639 if (w == NULL || w->enable == 0) 4640 return (0); 4641 4642 pw = hdac_widget_get(devinfo, pnid); 4643 strategy = devinfo->function.audio.parsing_strategy; 4644 4645 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4646 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4647 for (i = 0; i < w->nconns; i++) { 4648 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4649 w->nid, i, depth + 1); 4650 } 4651 w->ctlflags |= fl; 4652 return (fl); 4653 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4654 (w->pflags & HDA_DAC_PATH)) { 4655 i = 0; 4656 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4657 if (ctl->enable == 0 || ctl->widget == NULL) 4658 continue; 4659 /* XXX This should be compressed! */ 4660 if (((ctl->widget->nid == w->nid) || 4661 (ctl->widget->nid == pnid && ctl->index == index && 4662 (ctl->dir & HDA_CTL_IN)) || 4663 (ctl->widget->nid == pnid && pw != NULL && 4664 pw->type == 4665 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4666 (pw->nconns < 2 || pw->selconn == index || 4667 pw->selconn == -1) && 4668 (ctl->dir & HDA_CTL_OUT)) || 4669 (strategy == HDA_PARSE_DIRECT && 4670 ctl->widget->nid == w->nid)) && 4671 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4672 /*if (pw != NULL && pw->selconn == -1) 4673 pw->selconn = index; 4674 fl |= SOUND_MASK_VOLUME; 4675 fl |= SOUND_MASK_PCM; 4676 ctl->ossmask |= SOUND_MASK_VOLUME; 4677 ctl->ossmask |= SOUND_MASK_PCM; 4678 ctl->ossdev = SOUND_MIXER_PCM;*/ 4679 if (!(w->ctlflags & SOUND_MASK_PCM) || 4680 (pw != NULL && 4681 !(pw->ctlflags & SOUND_MASK_PCM))) { 4682 fl |= SOUND_MASK_VOLUME; 4683 fl |= SOUND_MASK_PCM; 4684 ctl->ossmask |= SOUND_MASK_VOLUME; 4685 ctl->ossmask |= SOUND_MASK_PCM; 4686 ctl->ossdev = SOUND_MIXER_PCM; 4687 w->ctlflags |= SOUND_MASK_VOLUME; 4688 w->ctlflags |= SOUND_MASK_PCM; 4689 if (pw != NULL) { 4690 if (pw->selconn == -1) 4691 pw->selconn = index; 4692 pw->ctlflags |= 4693 SOUND_MASK_VOLUME; 4694 pw->ctlflags |= 4695 SOUND_MASK_PCM; 4696 } 4697 } 4698 } 4699 } 4700 w->ctlflags |= fl; 4701 return (fl); 4702 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4703 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4704 (w->pflags & HDA_ADC_PATH)) { 4705 conndev = w->wclass.pin.config & 4706 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4707 i = 0; 4708 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4709 if (ctl->enable == 0 || ctl->widget == NULL) 4710 continue; 4711 /* XXX This should be compressed! */ 4712 if (((ctl->widget->nid == pnid && ctl->index == index && 4713 (ctl->dir & HDA_CTL_IN)) || 4714 (ctl->widget->nid == pnid && pw != NULL && 4715 pw->type == 4716 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4717 (pw->nconns < 2 || pw->selconn == index || 4718 pw->selconn == -1) && 4719 (ctl->dir & HDA_CTL_OUT)) || 4720 (strategy == HDA_PARSE_DIRECT && 4721 ctl->widget->nid == w->nid)) && 4722 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4723 if (pw != NULL && pw->selconn == -1) 4724 pw->selconn = index; 4725 ossdev = 0; 4726 switch (conndev) { 4727 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4728 ossdev = SOUND_MIXER_MIC; 4729 break; 4730 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4731 ossdev = SOUND_MIXER_LINE; 4732 break; 4733 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4734 ossdev = SOUND_MIXER_CD; 4735 break; 4736 default: 4737 ossdev = 4738 hdac_audio_ctl_ossmixer_getnextdev( 4739 devinfo); 4740 if (ossdev < 0) 4741 ossdev = 0; 4742 break; 4743 } 4744 if (strategy == HDA_PARSE_MIXER) { 4745 fl |= SOUND_MASK_VOLUME; 4746 ctl->ossmask |= SOUND_MASK_VOLUME; 4747 } 4748 fl |= 1 << ossdev; 4749 ctl->ossmask |= 1 << ossdev; 4750 ctl->ossdev = ossdev; 4751 } 4752 } 4753 w->ctlflags |= fl; 4754 return (fl); 4755 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4756 i = 0; 4757 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4758 if (ctl->enable == 0 || ctl->widget == NULL) 4759 continue; 4760 /* XXX This should be compressed! */ 4761 if (((ctl->widget->nid == pnid && ctl->index == index && 4762 (ctl->dir & HDA_CTL_IN)) || 4763 (ctl->widget->nid == pnid && pw != NULL && 4764 pw->type == 4765 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4766 (pw->nconns < 2 || pw->selconn == index || 4767 pw->selconn == -1) && 4768 (ctl->dir & HDA_CTL_OUT)) || 4769 (strategy == HDA_PARSE_DIRECT && 4770 ctl->widget->nid == w->nid)) && 4771 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4772 if (pw != NULL && pw->selconn == -1) 4773 pw->selconn = index; 4774 fl |= SOUND_MASK_VOLUME; 4775 fl |= SOUND_MASK_SPEAKER; 4776 ctl->ossmask |= SOUND_MASK_VOLUME; 4777 ctl->ossmask |= SOUND_MASK_SPEAKER; 4778 ctl->ossdev = SOUND_MIXER_SPEAKER; 4779 } 4780 } 4781 w->ctlflags |= fl; 4782 return (fl); 4783 } 4784 return (0); 4785} 4786 4787static uint32_t 4788hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4789{ 4790 struct hdac_widget *w, *cw; 4791 struct hdac_audio_ctl *ctl; 4792 uint32_t fl; 4793 int i; 4794 4795 if (depth > HDA_PARSE_MAXDEPTH) 4796 return (0); 4797 4798 w = hdac_widget_get(devinfo, nid); 4799 if (w == NULL || w->enable == 0) 4800 return (0); 4801 /*if (!(w->pflags & HDA_ADC_PATH)) 4802 return (0); 4803 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4804 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4805 return (0);*/ 4806 i = 0; 4807 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4808 if (ctl->enable == 0 || ctl->widget == NULL) 4809 continue; 4810 if (ctl->widget->nid == nid) { 4811 ctl->ossmask |= SOUND_MASK_RECLEV; 4812 w->ctlflags |= SOUND_MASK_RECLEV; 4813 return (SOUND_MASK_RECLEV); 4814 } 4815 } 4816 for (i = 0; i < w->nconns; i++) { 4817 cw = hdac_widget_get(devinfo, w->conns[i]); 4818 if (cw == NULL || cw->enable == 0) 4819 continue; 4820 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4821 continue; 4822 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4823 if (fl != 0) { 4824 cw->ctlflags |= fl; 4825 w->ctlflags |= fl; 4826 return (fl); 4827 } 4828 } 4829 return (0); 4830} 4831 4832static int 4833hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4834{ 4835 struct hdac_widget *w, *cw; 4836 int i, child = 0; 4837 4838 if (depth > HDA_PARSE_MAXDEPTH) 4839 return (0); 4840 4841 w = hdac_widget_get(devinfo, nid); 4842 if (w == NULL || w->enable == 0) 4843 return (0); 4844 /*if (!(w->pflags & HDA_ADC_PATH)) 4845 return (0); 4846 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4847 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4848 return (0);*/ 4849 /* XXX weak! */ 4850 for (i = 0; i < w->nconns; i++) { 4851 cw = hdac_widget_get(devinfo, w->conns[i]); 4852 if (cw == NULL) 4853 continue; 4854 if (++child > 1) { 4855 w->pflags |= HDA_ADC_RECSEL; 4856 return (1); 4857 } 4858 } 4859 for (i = 0; i < w->nconns; i++) { 4860 if (hdac_audio_ctl_recsel_build(devinfo, 4861 w->conns[i], depth + 1) != 0) 4862 return (1); 4863 } 4864 return (0); 4865} 4866 4867static int 4868hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4869{ 4870 struct hdac_widget *w, *cw; 4871 int i, j, conndev, found_dac = 0; 4872 int strategy; 4873 4874 strategy = devinfo->function.audio.parsing_strategy; 4875 4876 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4877 w = hdac_widget_get(devinfo, i); 4878 if (w == NULL || w->enable == 0) 4879 continue; 4880 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4881 continue; 4882 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4883 continue; 4884 conndev = w->wclass.pin.config & 4885 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4886 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4887 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4888 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4889 continue; 4890 for (j = 0; j < w->nconns; j++) { 4891 cw = hdac_widget_get(devinfo, w->conns[j]); 4892 if (cw == NULL || cw->enable == 0) 4893 continue; 4894 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4895 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4896 cw->type == 4897 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4898 continue; 4899 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4900 != 0) { 4901 if (w->selconn == -1) 4902 w->selconn = j; 4903 w->pflags |= HDA_DAC_PATH; 4904 found_dac++; 4905 } 4906 } 4907 } 4908 4909 return (found_dac); 4910} 4911 4912static void 4913hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4914{ 4915 struct hdac_widget *w; 4916 struct hdac_audio_ctl *ctl; 4917 int i, j, dacs, strategy; 4918 4919 /* Construct DAC path */ 4920 strategy = HDA_PARSE_MIXER; 4921 devinfo->function.audio.parsing_strategy = strategy; 4922 HDA_BOOTVERBOSE( 4923 device_printf(devinfo->codec->sc->dev, 4924 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4925 HDA_WIDGET_PARSER_REV); 4926 ); 4927 dacs = hdac_audio_build_tree_strategy(devinfo); 4928 if (dacs == 0) { 4929 HDA_BOOTVERBOSE( 4930 device_printf(devinfo->codec->sc->dev, 4931 "HDA_DEBUG: HWiP: 0 DAC path found! " 4932 "Retrying parser " 4933 "using HDA_PARSE_DIRECT strategy.\n"); 4934 ); 4935 strategy = HDA_PARSE_DIRECT; 4936 devinfo->function.audio.parsing_strategy = strategy; 4937 dacs = hdac_audio_build_tree_strategy(devinfo); 4938 } 4939 4940 HDA_BOOTVERBOSE( 4941 device_printf(devinfo->codec->sc->dev, 4942 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4943 "strategy.\n", 4944 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4945 ); 4946 4947 /* Construct ADC path */ 4948 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4949 w = hdac_widget_get(devinfo, i); 4950 if (w == NULL || w->enable == 0) 4951 continue; 4952 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4953 continue; 4954 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4955 } 4956 4957 /* Output mixers */ 4958 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4959 w = hdac_widget_get(devinfo, i); 4960 if (w == NULL || w->enable == 0) 4961 continue; 4962 if ((strategy == HDA_PARSE_MIXER && 4963 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4964 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4965 && (w->pflags & HDA_DAC_PATH)) || 4966 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4967 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4968 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4969 w->nid, devinfo->startnode - 1, 0, 0); 4970 } else if (w->type == 4971 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4972 j = 0; 4973 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4974 NULL) { 4975 if (ctl->enable == 0 || ctl->widget == NULL) 4976 continue; 4977 if (ctl->widget->nid != w->nid) 4978 continue; 4979 ctl->ossmask |= SOUND_MASK_VOLUME; 4980 ctl->ossmask |= SOUND_MASK_SPEAKER; 4981 ctl->ossdev = SOUND_MIXER_SPEAKER; 4982 w->ctlflags |= SOUND_MASK_VOLUME; 4983 w->ctlflags |= SOUND_MASK_SPEAKER; 4984 } 4985 } 4986 } 4987 4988 /* Input mixers (rec) */ 4989 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4990 w = hdac_widget_get(devinfo, i); 4991 if (w == NULL || w->enable == 0) 4992 continue; 4993 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4994 w->pflags & HDA_ADC_PATH)) 4995 continue; 4996 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4997 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4998 } 4999} 5000 5001#define HDA_COMMIT_CONN (1 << 0) 5002#define HDA_COMMIT_CTRL (1 << 1) 5003#define HDA_COMMIT_EAPD (1 << 2) 5004#define HDA_COMMIT_GPIO (1 << 3) 5005#define HDA_COMMIT_MISC (1 << 4) 5006#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5007 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5008 5009static void 5010hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5011{ 5012 struct hdac_softc *sc = devinfo->codec->sc; 5013 struct hdac_widget *w; 5014 nid_t cad; 5015 int i; 5016 5017 if (!(cfl & HDA_COMMIT_ALL)) 5018 return; 5019 5020 cad = devinfo->codec->cad; 5021 5022 if ((cfl & HDA_COMMIT_MISC)) { 5023 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5024 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5025 0x7e7, 0), cad); 5026 } 5027 5028 if (cfl & HDA_COMMIT_GPIO) { 5029 uint32_t gdata, gmask, gdir; 5030 int commitgpio, numgpio; 5031 5032 gdata = 0; 5033 gmask = 0; 5034 gdir = 0; 5035 commitgpio = 0; 5036 5037 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5038 devinfo->function.audio.gpio); 5039 5040 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5041 commitgpio = (numgpio > 0) ? 1 : 0; 5042 else { 5043 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5044 if (!(devinfo->function.audio.quirks & 5045 (1 << i))) 5046 continue; 5047 if (commitgpio == 0) { 5048 commitgpio = 1; 5049 HDA_BOOTVERBOSE( 5050 gdata = hdac_command(sc, 5051 HDA_CMD_GET_GPIO_DATA(cad, 5052 devinfo->nid), cad); 5053 gmask = hdac_command(sc, 5054 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5055 devinfo->nid), cad); 5056 gdir = hdac_command(sc, 5057 HDA_CMD_GET_GPIO_DIRECTION(cad, 5058 devinfo->nid), cad); 5059 device_printf(sc->dev, 5060 "GPIO init: data=0x%08x " 5061 "mask=0x%08x dir=0x%08x\n", 5062 gdata, gmask, gdir); 5063 gdata = 0; 5064 gmask = 0; 5065 gdir = 0; 5066 ); 5067 } 5068 gdata |= 1 << i; 5069 gmask |= 1 << i; 5070 gdir |= 1 << i; 5071 } 5072 } 5073 5074 if (commitgpio != 0) { 5075 HDA_BOOTVERBOSE( 5076 device_printf(sc->dev, 5077 "GPIO commit: data=0x%08x mask=0x%08x " 5078 "dir=0x%08x\n", 5079 gdata, gmask, gdir); 5080 ); 5081 hdac_command(sc, 5082 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5083 gmask), cad); 5084 hdac_command(sc, 5085 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5086 gdir), cad); 5087 hdac_command(sc, 5088 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5089 gdata), cad); 5090 } 5091 } 5092 5093 for (i = 0; i < devinfo->nodecnt; i++) { 5094 w = &devinfo->widget[i]; 5095 if (w == NULL || w->enable == 0) 5096 continue; 5097 if (cfl & HDA_COMMIT_CONN) { 5098 if (w->selconn == -1) 5099 w->selconn = 0; 5100 if (w->nconns > 0) 5101 hdac_widget_connection_select(w, w->selconn); 5102 } 5103 if ((cfl & HDA_COMMIT_CTRL) && 5104 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5105 uint32_t pincap; 5106 5107 pincap = w->wclass.pin.cap; 5108 5109 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5110 (HDA_DAC_PATH | HDA_ADC_PATH)) 5111 device_printf(sc->dev, "WARNING: node %d " 5112 "participate both for DAC/ADC!\n", w->nid); 5113 if (w->pflags & HDA_DAC_PATH) { 5114 w->wclass.pin.ctrl &= 5115 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5116 if ((w->wclass.pin.config & 5117 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5118 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5119 w->wclass.pin.ctrl &= 5120 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5121 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5122 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5123 w->wclass.pin.ctrl |= 5124 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5125 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5126 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5127 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5128 w->wclass.pin.ctrl |= 5129 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5130 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5131 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5132 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5133 w->wclass.pin.ctrl |= 5134 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5135 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5136 } else if (w->pflags & HDA_ADC_PATH) { 5137 w->wclass.pin.ctrl &= 5138 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5139 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5140 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5141 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5142 w->wclass.pin.ctrl |= 5143 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5144 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5145 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5146 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5147 w->wclass.pin.ctrl |= 5148 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5149 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5150 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5151 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5152 w->wclass.pin.ctrl |= 5153 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5154 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5155 } else 5156 w->wclass.pin.ctrl &= ~( 5157 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5158 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5159 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5160 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5161 hdac_command(sc, 5162 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5163 w->wclass.pin.ctrl), cad); 5164 } 5165 if ((cfl & HDA_COMMIT_EAPD) && 5166 w->param.eapdbtl != HDAC_INVALID) { 5167 uint32_t val; 5168 5169 val = w->param.eapdbtl; 5170 if (devinfo->function.audio.quirks & 5171 HDA_QUIRK_EAPDINV) 5172 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5173 hdac_command(sc, 5174 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5175 val), cad); 5176 5177 } 5178 DELAY(1000); 5179 } 5180} 5181 5182static void 5183hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5184{ 5185 struct hdac_softc *sc = devinfo->codec->sc; 5186 struct hdac_audio_ctl *ctl; 5187 int i; 5188 5189 devinfo->function.audio.mvol = 100 | (100 << 8); 5190 i = 0; 5191 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5192 if (ctl->enable == 0 || ctl->widget == NULL) { 5193 HDA_BOOTVERBOSE( 5194 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5195 i, (ctl->widget != NULL) ? 5196 ctl->widget->nid : -1); 5197 if (ctl->childwidget != NULL) 5198 printf(" childnid=%d", 5199 ctl->childwidget->nid); 5200 if (ctl->widget == NULL) 5201 printf(" NULL WIDGET!"); 5202 printf(" DISABLED\n"); 5203 ); 5204 continue; 5205 } 5206 HDA_BOOTVERBOSE( 5207 if (ctl->ossmask == 0) { 5208 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5209 i, ctl->widget->nid); 5210 if (ctl->childwidget != NULL) 5211 printf(" childnid=%d", 5212 ctl->childwidget->nid); 5213 printf(" Bind to NONE\n"); 5214 } 5215 ); 5216 if (ctl->step > 0) { 5217 ctl->ossval = (ctl->left * 100) / ctl->step; 5218 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5219 } else 5220 ctl->ossval = 0; 5221 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5222 ctl->left, ctl->right); 5223 } 5224} 5225 5226static int 5227hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5228{ 5229 struct hdac_chan *ch; 5230 struct hdac_widget *w; 5231 uint32_t cap, fmtcap, pcmcap, path; 5232 int i, type, ret, max; 5233 5234 if (dir == PCMDIR_PLAY) { 5235 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5236 ch = &devinfo->codec->sc->play; 5237 path = HDA_DAC_PATH; 5238 } else { 5239 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5240 ch = &devinfo->codec->sc->rec; 5241 path = HDA_ADC_PATH; 5242 } 5243 5244 ch->caps = hdac_caps; 5245 ch->caps.fmtlist = ch->fmtlist; 5246 ch->bit16 = 1; 5247 ch->bit32 = 0; 5248 ch->pcmrates[0] = 48000; 5249 ch->pcmrates[1] = 0; 5250 5251 ret = 0; 5252 fmtcap = devinfo->function.audio.supp_stream_formats; 5253 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5254 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5255 5256 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5257 w = hdac_widget_get(devinfo, i); 5258 if (w == NULL || w->enable == 0 || w->type != type || 5259 !(w->pflags & path)) 5260 continue; 5261 cap = w->param.widget_cap; 5262 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5263 continue;*/ 5264 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5265 continue; 5266 cap = w->param.supp_stream_formats; 5267 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5268 } 5269 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5270 }*/ 5271 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5272 continue; 5273 if (ret == 0) { 5274 fmtcap = w->param.supp_stream_formats; 5275 pcmcap = w->param.supp_pcm_size_rate; 5276 } else { 5277 fmtcap &= w->param.supp_stream_formats; 5278 pcmcap &= w->param.supp_pcm_size_rate; 5279 } 5280 ch->io[ret++] = i; 5281 } 5282 ch->io[ret] = -1; 5283 5284 ch->supp_stream_formats = fmtcap; 5285 ch->supp_pcm_size_rate = pcmcap; 5286 5287 /* 5288 * 8bit = 0 5289 * 16bit = 1 5290 * 20bit = 2 5291 * 24bit = 3 5292 * 32bit = 4 5293 */ 5294 if (ret > 0) { 5295 cap = pcmcap; 5296 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5297 ch->bit16 = 1; 5298 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5299 ch->bit16 = 0; 5300 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5301 ch->bit32 = 4; 5302 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5303 ch->bit32 = 3; 5304 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5305 ch->bit32 = 2; 5306 i = 0; 5307 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5308 ch->fmtlist[i++] = AFMT_S16_LE; 5309 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5310 if (ch->bit32 > 0) { 5311 if (!(devinfo->function.audio.quirks & 5312 HDA_QUIRK_FORCESTEREO)) 5313 ch->fmtlist[i++] = AFMT_S32_LE; 5314 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5315 } 5316 ch->fmtlist[i] = 0; 5317 i = 0; 5318 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5319 ch->pcmrates[i++] = 8000; 5320 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5321 ch->pcmrates[i++] = 11025; 5322 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5323 ch->pcmrates[i++] = 16000; 5324 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5325 ch->pcmrates[i++] = 22050; 5326 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5327 ch->pcmrates[i++] = 32000; 5328 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5329 ch->pcmrates[i++] = 44100; 5330 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5331 ch->pcmrates[i++] = 48000; 5332 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5333 ch->pcmrates[i++] = 88200; 5334 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5335 ch->pcmrates[i++] = 96000; 5336 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5337 ch->pcmrates[i++] = 176400; 5338 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5339 ch->pcmrates[i++] = 192000; 5340 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5341 ch->pcmrates[i] = 0; 5342 if (i > 0) { 5343 ch->caps.minspeed = ch->pcmrates[0]; 5344 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5345 } 5346 } 5347 5348 return (ret); 5349} 5350 5351static void 5352hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5353{ 5354 struct hdac_audio_ctl *ctl; 5355 struct hdac_softc *sc = devinfo->codec->sc; 5356 int i; 5357 uint32_t fl = 0; 5358 5359 5360 if (flag == 0) { 5361 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5362 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5363 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5364 } 5365 5366 i = 0; 5367 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5368 if (ctl->enable == 0 || ctl->widget == NULL || 5369 ctl->widget->enable == 0 || (ctl->ossmask & 5370 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5371 continue; 5372 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5373 (flag != 0 && (ctl->ossmask & flag))) { 5374 if (banner != NULL) { 5375 device_printf(sc->dev, "\n"); 5376 device_printf(sc->dev, "%s\n", banner); 5377 } 5378 goto hdac_ctl_dump_it_all; 5379 } 5380 } 5381 5382 return; 5383 5384hdac_ctl_dump_it_all: 5385 i = 0; 5386 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5387 if (ctl->enable == 0 || ctl->widget == NULL || 5388 ctl->widget->enable == 0) 5389 continue; 5390 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5391 (flag != 0 && (ctl->ossmask & flag)))) 5392 continue; 5393 if (flag == 0) { 5394 device_printf(sc->dev, "\n"); 5395 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5396 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5397 } 5398 device_printf(sc->dev, " |\n"); 5399 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5400 ctl->widget->nid, ctl->index); 5401 if (ctl->childwidget != NULL) 5402 printf("(nid: %2d) ", ctl->childwidget->nid); 5403 else 5404 printf(" "); 5405 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5406 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5407 ctl->ossmask); 5408 } 5409} 5410 5411static void 5412hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5413{ 5414 uint32_t cap; 5415 5416 cap = fcap; 5417 if (cap != 0) { 5418 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5419 device_printf(sc->dev, " Format:"); 5420 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5421 printf(" AC3"); 5422 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5423 printf(" FLOAT32"); 5424 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5425 printf(" PCM"); 5426 printf("\n"); 5427 } 5428 cap = pcmcap; 5429 if (cap != 0) { 5430 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5431 device_printf(sc->dev, " PCM size:"); 5432 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5433 printf(" 8"); 5434 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5435 printf(" 16"); 5436 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5437 printf(" 20"); 5438 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5439 printf(" 24"); 5440 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5441 printf(" 32"); 5442 printf("\n"); 5443 device_printf(sc->dev, " PCM rate:"); 5444 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5445 printf(" 8"); 5446 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5447 printf(" 11"); 5448 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5449 printf(" 16"); 5450 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5451 printf(" 22"); 5452 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5453 printf(" 32"); 5454 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5455 printf(" 44"); 5456 printf(" 48"); 5457 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5458 printf(" 88"); 5459 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5460 printf(" 96"); 5461 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5462 printf(" 176"); 5463 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5464 printf(" 192"); 5465 printf("\n"); 5466 } 5467} 5468 5469static void 5470hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5471{ 5472 uint32_t pincap, wcap; 5473 5474 pincap = w->wclass.pin.cap; 5475 wcap = w->param.widget_cap; 5476 5477 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5478 device_printf(sc->dev, " "); 5479 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5480 printf(" ISC"); 5481 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5482 printf(" TRQD"); 5483 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5484 printf(" PDC"); 5485 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5486 printf(" HP"); 5487 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5488 printf(" OUT"); 5489 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5490 printf(" IN"); 5491 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5492 printf(" BAL"); 5493 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5494 printf(" VREF["); 5495 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5496 printf(" 50"); 5497 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5498 printf(" 80"); 5499 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5500 printf(" 100"); 5501 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5502 printf(" GROUND"); 5503 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5504 printf(" HIZ"); 5505 printf(" ]"); 5506 } 5507 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5508 printf(" EAPD"); 5509 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5510 printf(" : UNSOL"); 5511 printf("\n"); 5512 device_printf(sc->dev, " Pin config: 0x%08x\n", 5513 w->wclass.pin.config); 5514 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5515 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5516 printf(" HP"); 5517 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5518 printf(" IN"); 5519 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5520 printf(" OUT"); 5521 printf("\n"); 5522} 5523 5524static void 5525hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5526{ 5527 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5528 device_printf(sc->dev, " " 5529 "mute=%d step=%d size=%d offset=%d\n", 5530 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5531 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5532 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5533 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5534} 5535 5536static void 5537hdac_dump_nodes(struct hdac_devinfo *devinfo) 5538{ 5539 struct hdac_softc *sc = devinfo->codec->sc; 5540 struct hdac_widget *w, *cw; 5541 int i, j; 5542 5543 device_printf(sc->dev, "\n"); 5544 device_printf(sc->dev, "Default Parameter\n"); 5545 device_printf(sc->dev, "-----------------\n"); 5546 hdac_dump_audio_formats(sc, 5547 devinfo->function.audio.supp_stream_formats, 5548 devinfo->function.audio.supp_pcm_size_rate); 5549 device_printf(sc->dev, " IN amp: 0x%08x\n", 5550 devinfo->function.audio.inamp_cap); 5551 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5552 devinfo->function.audio.outamp_cap); 5553 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5554 w = hdac_widget_get(devinfo, i); 5555 if (w == NULL) { 5556 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5557 continue; 5558 } 5559 device_printf(sc->dev, "\n"); 5560 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5561 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5562 "DIGITAL" : "ANALOG", 5563 (w->enable == 0) ? " [DISABLED]" : ""); 5564 device_printf(sc->dev, " name: %s\n", w->name); 5565 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5566 w->param.widget_cap); 5567 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5568 w->pflags); 5569 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5570 w->ctlflags); 5571 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5572 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5573 hdac_dump_audio_formats(sc, 5574 w->param.supp_stream_formats, 5575 w->param.supp_pcm_size_rate); 5576 } else if (w->type == 5577 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5578 hdac_dump_pin(sc, w); 5579 if (w->param.eapdbtl != HDAC_INVALID) 5580 device_printf(sc->dev, " EAPD: 0x%08x\n", 5581 w->param.eapdbtl); 5582 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5583 w->param.outamp_cap != 0) 5584 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5585 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5586 w->param.inamp_cap != 0) 5587 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5588 device_printf(sc->dev, " connections: %d\n", w->nconns); 5589 for (j = 0; j < w->nconns; j++) { 5590 cw = hdac_widget_get(devinfo, w->conns[j]); 5591 device_printf(sc->dev, " |\n"); 5592 device_printf(sc->dev, " + <- nid=%d [%s]", 5593 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5594 if (cw == NULL) 5595 printf(" [UNKNOWN]"); 5596 else if (cw->enable == 0) 5597 printf(" [DISABLED]"); 5598 if (w->nconns > 1 && w->selconn == j && w->type != 5599 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5600 printf(" (selected)"); 5601 printf("\n"); 5602 } 5603 } 5604 5605} 5606 5607static int 5608hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5609{ 5610 struct hdac_widget *w, *cw; 5611 struct hdac_softc *sc = devinfo->codec->sc; 5612 int i; 5613 5614 if (depth > HDA_PARSE_MAXDEPTH) 5615 return (0); 5616 5617 w = hdac_widget_get(devinfo, nid); 5618 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5619 return (0); 5620 5621 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5622 device_printf(sc->dev, "\n"); 5623 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5624 device_printf(sc->dev, " ^\n"); 5625 device_printf(sc->dev, " |\n"); 5626 device_printf(sc->dev, " +-----<------+\n"); 5627 } else { 5628 device_printf(sc->dev, " ^\n"); 5629 device_printf(sc->dev, " |\n"); 5630 device_printf(sc->dev, " "); 5631 printf(" nid=%d [%s]\n", w->nid, w->name); 5632 } 5633 5634 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5635 return (1); 5636 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5637 for (i = 0; i < w->nconns; i++) { 5638 cw = hdac_widget_get(devinfo, w->conns[i]); 5639 if (cw == NULL || cw->enable == 0 || cw->type == 5640 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5641 continue; 5642 if (hdac_dump_dac_internal(devinfo, cw->nid, 5643 depth + 1) != 0) 5644 return (1); 5645 } 5646 } else if ((w->type == 5647 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5648 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5649 w->selconn > -1 && w->selconn < w->nconns) { 5650 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5651 depth + 1) != 0) 5652 return (1); 5653 } 5654 5655 return (0); 5656} 5657 5658static void 5659hdac_dump_dac(struct hdac_devinfo *devinfo) 5660{ 5661 struct hdac_widget *w; 5662 struct hdac_softc *sc = devinfo->codec->sc; 5663 int i, printed = 0; 5664 5665 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5666 w = hdac_widget_get(devinfo, i); 5667 if (w == NULL || w->enable == 0) 5668 continue; 5669 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5670 !(w->pflags & HDA_DAC_PATH)) 5671 continue; 5672 if (printed == 0) { 5673 printed = 1; 5674 device_printf(sc->dev, "\n"); 5675 device_printf(sc->dev, "Playback path:\n"); 5676 } 5677 hdac_dump_dac_internal(devinfo, w->nid, 0); 5678 } 5679} 5680 5681static void 5682hdac_dump_adc(struct hdac_devinfo *devinfo) 5683{ 5684 struct hdac_widget *w, *cw; 5685 struct hdac_softc *sc = devinfo->codec->sc; 5686 int i, j; 5687 int printed = 0; 5688 char ossdevs[256]; 5689 5690 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5691 w = hdac_widget_get(devinfo, i); 5692 if (w == NULL || w->enable == 0) 5693 continue; 5694 if (!(w->pflags & HDA_ADC_RECSEL)) 5695 continue; 5696 if (printed == 0) { 5697 printed = 1; 5698 device_printf(sc->dev, "\n"); 5699 device_printf(sc->dev, "Recording sources:\n"); 5700 } 5701 device_printf(sc->dev, "\n"); 5702 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5703 for (j = 0; j < w->nconns; j++) { 5704 cw = hdac_widget_get(devinfo, w->conns[j]); 5705 if (cw == NULL || cw->enable == 0) 5706 continue; 5707 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5708 ossdevs, sizeof(ossdevs)); 5709 device_printf(sc->dev, " |\n"); 5710 device_printf(sc->dev, " + <- nid=%d [%s]", 5711 cw->nid, cw->name); 5712 if (strlen(ossdevs) > 0) { 5713 printf(" [recsrc: %s]", ossdevs); 5714 } 5715 printf("\n"); 5716 } 5717 } 5718} 5719 5720static void 5721hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5722{ 5723 nid_t *nids; 5724 5725 if (pcnt > 0) { 5726 device_printf(sc->dev, "\n"); 5727 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5728 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5729 sc->play.supp_pcm_size_rate); 5730 device_printf(sc->dev, " DAC:"); 5731 for (nids = sc->play.io; *nids != -1; nids++) 5732 printf(" %d", *nids); 5733 printf("\n"); 5734 } 5735 5736 if (rcnt > 0) { 5737 device_printf(sc->dev, "\n"); 5738 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5739 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5740 sc->rec.supp_pcm_size_rate); 5741 device_printf(sc->dev, " ADC:"); 5742 for (nids = sc->rec.io; *nids != -1; nids++) 5743 printf(" %d", *nids); 5744 printf("\n"); 5745 } 5746} 5747 5748static void 5749hdac_release_resources(struct hdac_softc *sc) 5750{ 5751 struct hdac_devinfo *devinfo = NULL; 5752 device_t *devlist = NULL; 5753 int i, devcount; 5754 5755 if (sc == NULL) 5756 return; 5757 5758 hdac_lock(sc); 5759 sc->polling = 0; 5760 sc->poll_ival = 0; 5761 callout_stop(&sc->poll_hda); 5762 callout_stop(&sc->poll_hdac); 5763 callout_stop(&sc->poll_jack); 5764 hdac_reset(sc); 5765 hdac_unlock(sc); 5766 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5767 callout_drain(&sc->poll_hda); 5768 callout_drain(&sc->poll_hdac); 5769 callout_drain(&sc->poll_jack); 5770 5771 hdac_irq_free(sc); 5772 5773 device_get_children(sc->dev, &devlist, &devcount); 5774 for (i = 0; devlist != NULL && i < devcount; i++) { 5775 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5776 if (devinfo == NULL) 5777 continue; 5778 if (devinfo->widget != NULL) 5779 free(devinfo->widget, M_HDAC); 5780 if (devinfo->node_type == 5781 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5782 devinfo->function.audio.ctl != NULL) 5783 free(devinfo->function.audio.ctl, M_HDAC); 5784 free(devinfo, M_HDAC); 5785 device_delete_child(sc->dev, devlist[i]); 5786 } 5787 if (devlist != NULL) 5788 free(devlist, M_TEMP); 5789 5790 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5791 if (sc->codecs[i] != NULL) 5792 free(sc->codecs[i], M_HDAC); 5793 sc->codecs[i] = NULL; 5794 } 5795 5796 hdac_dma_free(sc, &sc->pos_dma); 5797 hdac_dma_free(sc, &sc->rirb_dma); 5798 hdac_dma_free(sc, &sc->corb_dma); 5799 if (sc->play.blkcnt > 0) 5800 hdac_dma_free(sc, &sc->play.bdl_dma); 5801 if (sc->rec.blkcnt > 0) 5802 hdac_dma_free(sc, &sc->rec.bdl_dma); 5803 if (sc->chan_dmat != NULL) { 5804 bus_dma_tag_destroy(sc->chan_dmat); 5805 sc->chan_dmat = NULL; 5806 } 5807 hdac_mem_free(sc); 5808 snd_mtxfree(sc->lock); 5809 free(sc, M_DEVBUF); 5810} 5811 5812/* This function surely going to make its way into upper level someday. */ 5813static void 5814hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5815{ 5816 const char *res = NULL; 5817 int i = 0, j, k, len, inv; 5818 5819 if (on != NULL) 5820 *on = 0; 5821 if (off != NULL) 5822 *off = 0; 5823 if (sc == NULL) 5824 return; 5825 if (resource_string_value(device_get_name(sc->dev), 5826 device_get_unit(sc->dev), "config", &res) != 0) 5827 return; 5828 if (!(res != NULL && strlen(res) > 0)) 5829 return; 5830 HDA_BOOTVERBOSE( 5831 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5832 ); 5833 for (;;) { 5834 while (res[i] != '\0' && 5835 (res[i] == ',' || isspace(res[i]) != 0)) 5836 i++; 5837 if (res[i] == '\0') { 5838 HDA_BOOTVERBOSE( 5839 printf("\n"); 5840 ); 5841 return; 5842 } 5843 j = i; 5844 while (res[j] != '\0' && 5845 !(res[j] == ',' || isspace(res[j]) != 0)) 5846 j++; 5847 len = j - i; 5848 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5849 inv = 2; 5850 else 5851 inv = 0; 5852 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5853 if (strncmp(res + i + inv, 5854 hdac_quirks_tab[k].key, len - inv) != 0) 5855 continue; 5856 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5857 break; 5858 HDA_BOOTVERBOSE( 5859 printf(" %s%s", (inv != 0) ? "no" : "", 5860 hdac_quirks_tab[k].key); 5861 ); 5862 if (inv == 0 && on != NULL) 5863 *on |= hdac_quirks_tab[k].value; 5864 else if (inv != 0 && off != NULL) 5865 *off |= hdac_quirks_tab[k].value; 5866 break; 5867 } 5868 i = j; 5869 } 5870} 5871 5872#ifdef SND_DYNSYSCTL 5873static int 5874sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5875{ 5876 struct hdac_softc *sc; 5877 struct hdac_devinfo *devinfo; 5878 device_t dev; 5879 uint32_t ctl; 5880 int err, val; 5881 5882 dev = oidp->oid_arg1; 5883 devinfo = pcm_getdevinfo(dev); 5884 if (devinfo == NULL || devinfo->codec == NULL || 5885 devinfo->codec->sc == NULL) 5886 return (EINVAL); 5887 sc = devinfo->codec->sc; 5888 hdac_lock(sc); 5889 val = sc->polling; 5890 hdac_unlock(sc); 5891 err = sysctl_handle_int(oidp, &val, 0, req); 5892 5893 if (err != 0 || req->newptr == NULL) 5894 return (err); 5895 if (val < 0 || val > 1) 5896 return (EINVAL); 5897 5898 hdac_lock(sc); 5899 if (val != sc->polling) { 5900 if (hda_chan_active(sc) != 0) 5901 err = EBUSY; 5902 else if (val == 0) { 5903 callout_stop(&sc->poll_hdac); 5904 hdac_unlock(sc); 5905 callout_drain(&sc->poll_hdac); 5906 hdac_lock(sc); 5907 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5908 sc->rirb_size / 2); 5909 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5910 ctl |= HDAC_RIRBCTL_RINTCTL; 5911 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5912 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5913 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5914 sc->polling = 0; 5915 DELAY(1000); 5916 } else { 5917 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5918 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5919 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5920 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5921 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5922 hdac_unlock(sc); 5923 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5924 hdac_lock(sc); 5925 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5926 sc); 5927 sc->polling = 1; 5928 DELAY(1000); 5929 } 5930 } 5931 hdac_unlock(sc); 5932 5933 return (err); 5934} 5935 5936static int 5937sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5938{ 5939 struct hdac_softc *sc; 5940 struct hdac_devinfo *devinfo; 5941 device_t dev; 5942 int err, val; 5943 5944 dev = oidp->oid_arg1; 5945 devinfo = pcm_getdevinfo(dev); 5946 if (devinfo == NULL || devinfo->codec == NULL || 5947 devinfo->codec->sc == NULL) 5948 return (EINVAL); 5949 sc = devinfo->codec->sc; 5950 hdac_lock(sc); 5951 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5952 hdac_unlock(sc); 5953 err = sysctl_handle_int(oidp, &val, 0, req); 5954 5955 if (err != 0 || req->newptr == NULL) 5956 return (err); 5957 5958 if (val < 1) 5959 val = 1; 5960 if (val > 5000) 5961 val = 5000; 5962 val = ((uint64_t)val * hz) / 1000; 5963 if (val < 1) 5964 val = 1; 5965 if (val > (hz * 5)) 5966 val = hz * 5; 5967 5968 hdac_lock(sc); 5969 sc->poll_ival = val; 5970 hdac_unlock(sc); 5971 5972 return (err); 5973} 5974 5975#ifdef SND_DEBUG 5976static int 5977sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 5978{ 5979 struct hdac_softc *sc; 5980 struct hdac_devinfo *devinfo; 5981 struct hdac_widget *w; 5982 device_t dev; 5983 uint32_t res, pincap, timeout; 5984 int i, err, val; 5985 nid_t cad; 5986 5987 dev = oidp->oid_arg1; 5988 devinfo = pcm_getdevinfo(dev); 5989 if (devinfo == NULL || devinfo->codec == NULL || 5990 devinfo->codec->sc == NULL) 5991 return (EINVAL); 5992 val = 0; 5993 err = sysctl_handle_int(oidp, &val, 0, req); 5994 if (err != 0 || req->newptr == NULL || val == 0) 5995 return (err); 5996 sc = devinfo->codec->sc; 5997 cad = devinfo->codec->cad; 5998 hdac_lock(sc); 5999 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 6000 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6001 w = hdac_widget_get(devinfo, i); 6002 if (w == NULL || w->type != 6003 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6004 continue; 6005 pincap = w->wclass.pin.cap; 6006 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6007 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6008 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6009 timeout = 10000; 6010 hdac_command(sc, 6011 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6012 do { 6013 res = hdac_command(sc, 6014 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6015 if (res != 0x7fffffff) 6016 break; 6017 DELAY(10); 6018 } while (--timeout != 0); 6019 } else { 6020 timeout = -1; 6021 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6022 w->nid), cad); 6023 } 6024 device_printf(dev, 6025 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6026 w->nid, timeout, res, 6027 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6028 } 6029 device_printf(dev, 6030 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6031 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6032 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6033 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6034 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6035 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6036 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6037 device_printf(dev, " GPI:"); 6038 res = hdac_command(sc, 6039 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6040 printf(" data=0x%08x", res); 6041 res = hdac_command(sc, 6042 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6043 cad); 6044 printf(" wake=0x%08x", res); 6045 res = hdac_command(sc, 6046 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6047 cad); 6048 printf(" unsol=0x%08x", res); 6049 res = hdac_command(sc, 6050 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6051 printf(" sticky=0x%08x\n", res); 6052 } 6053 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6054 device_printf(dev, " GPO:"); 6055 res = hdac_command(sc, 6056 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6057 printf(" data=0x%08x\n", res); 6058 } 6059 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6060 device_printf(dev, "GPI0:"); 6061 res = hdac_command(sc, 6062 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6063 printf(" data=0x%08x", res); 6064 res = hdac_command(sc, 6065 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6066 printf(" enable=0x%08x", res); 6067 res = hdac_command(sc, 6068 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6069 printf(" direction=0x%08x\n", res); 6070 res = hdac_command(sc, 6071 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6072 device_printf(dev, " wake=0x%08x", res); 6073 res = hdac_command(sc, 6074 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6075 cad); 6076 printf(" unsol=0x%08x", res); 6077 res = hdac_command(sc, 6078 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6079 printf(" sticky=0x%08x\n", res); 6080 } 6081 hdac_unlock(sc); 6082 return (0); 6083} 6084#endif 6085#endif 6086 6087static void 6088hdac_attach2(void *arg) 6089{ 6090 struct hdac_softc *sc; 6091 struct hdac_widget *w; 6092 struct hdac_audio_ctl *ctl; 6093 uint32_t quirks_on, quirks_off; 6094 int pcnt, rcnt, codec_index; 6095 int i; 6096 char status[SND_STATUSLEN]; 6097 device_t *devlist = NULL; 6098 int devcount; 6099 struct hdac_devinfo *devinfo = NULL; 6100 6101 sc = (struct hdac_softc *)arg; 6102 6103 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6104 6105 HDA_BOOTVERBOSE( 6106 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6107 quirks_on, quirks_off); 6108 ); 6109 6110 if (resource_int_value(device_get_name(sc->dev), 6111 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6112 switch (sc->pci_subvendor) { 6113 case GB_G33S2H_SUBVENDOR: 6114 codec_index = 2; 6115 break; 6116 default: 6117 codec_index = 0; 6118 break; 6119 } 6120 } 6121 6122 hdac_lock(sc); 6123 6124 /* Remove ourselves from the config hooks */ 6125 if (sc->intrhook.ich_func != NULL) { 6126 config_intrhook_disestablish(&sc->intrhook); 6127 sc->intrhook.ich_func = NULL; 6128 } 6129 6130 /* Start the corb and rirb engines */ 6131 HDA_BOOTVERBOSE( 6132 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6133 ); 6134 hdac_corb_start(sc); 6135 HDA_BOOTVERBOSE( 6136 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6137 ); 6138 hdac_rirb_start(sc); 6139 6140 HDA_BOOTVERBOSE( 6141 device_printf(sc->dev, 6142 "HDA_DEBUG: Enabling controller interrupt...\n"); 6143 ); 6144 if (sc->polling == 0) 6145 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6146 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6147 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6148 HDAC_GCTL_UNSOL); 6149 6150 DELAY(1000); 6151 6152 HDA_BOOTVERBOSE( 6153 device_printf(sc->dev, 6154 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6155 codec_index); 6156 ); 6157 hdac_scan_codecs(sc, codec_index); 6158 6159 device_get_children(sc->dev, &devlist, &devcount); 6160 for (i = 0; devlist != NULL && i < devcount; i++) { 6161 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6162 if (devinfo != NULL && devinfo->node_type == 6163 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6164 break; 6165 } else 6166 devinfo = NULL; 6167 } 6168 if (devlist != NULL) 6169 free(devlist, M_TEMP); 6170 6171 if (devinfo == NULL) { 6172 hdac_unlock(sc); 6173 device_printf(sc->dev, "Audio Function Group not found!\n"); 6174 hdac_release_resources(sc); 6175 return; 6176 } 6177 6178 HDA_BOOTVERBOSE( 6179 device_printf(sc->dev, 6180 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6181 devinfo->nid, devinfo->codec->cad); 6182 ); 6183 hdac_audio_parse(devinfo); 6184 HDA_BOOTVERBOSE( 6185 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6186 ); 6187 hdac_audio_ctl_parse(devinfo); 6188 HDA_BOOTVERBOSE( 6189 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6190 ); 6191 hdac_vendor_patch_parse(devinfo); 6192 if (quirks_on != 0) 6193 devinfo->function.audio.quirks |= quirks_on; 6194 if (quirks_off != 0) 6195 devinfo->function.audio.quirks &= ~quirks_off; 6196 6197 /* XXX Disable all DIGITAL path. */ 6198 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6199 w = hdac_widget_get(devinfo, i); 6200 if (w == NULL) 6201 continue; 6202 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6203 w->enable = 0; 6204 continue; 6205 } 6206 /* XXX Disable useless pin ? */ 6207 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6208 (w->wclass.pin.config & 6209 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6210 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6211 w->enable = 0; 6212 } 6213 i = 0; 6214 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6215 if (ctl->widget == NULL) 6216 continue; 6217 if (ctl->ossmask & SOUND_MASK_DISABLE) 6218 ctl->enable = 0; 6219 w = ctl->widget; 6220 if (w->enable == 0 || 6221 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6222 ctl->enable = 0; 6223 w = ctl->childwidget; 6224 if (w == NULL) 6225 continue; 6226 if (w->enable == 0 || 6227 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6228 ctl->enable = 0; 6229 } 6230 6231 HDA_BOOTVERBOSE( 6232 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6233 ); 6234 hdac_audio_build_tree(devinfo); 6235 6236 i = 0; 6237 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6238 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6239 ctl->ossmask = 0; 6240 } 6241 HDA_BOOTVERBOSE( 6242 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6243 ); 6244 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6245 HDA_BOOTVERBOSE( 6246 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6247 ); 6248 hdac_audio_ctl_commit(devinfo); 6249 6250 HDA_BOOTVERBOSE( 6251 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6252 ); 6253 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6254 HDA_BOOTVERBOSE( 6255 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6256 ); 6257 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6258 6259 hdac_unlock(sc); 6260 HDA_BOOTVERBOSE( 6261 device_printf(sc->dev, 6262 "HDA_DEBUG: OSS mixer initialization...\n"); 6263 ); 6264 6265 /* 6266 * There is no point of return after this. If the driver failed, 6267 * so be it. Let the detach procedure do all the cleanup. 6268 */ 6269 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6270 device_printf(sc->dev, "Can't register mixer\n"); 6271 6272 if (pcnt > 0) 6273 pcnt = 1; 6274 if (rcnt > 0) 6275 rcnt = 1; 6276 6277 HDA_BOOTVERBOSE( 6278 device_printf(sc->dev, 6279 "HDA_DEBUG: Registering PCM channels...\n"); 6280 ); 6281 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6282 device_printf(sc->dev, "Can't register PCM\n"); 6283 6284 sc->registered++; 6285 6286 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6287 hdac_dma_alloc(sc, &sc->pos_dma, 6288 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6289 HDA_BOOTVERBOSE( 6290 device_printf(sc->dev, 6291 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6292 ); 6293 } 6294 6295 for (i = 0; i < pcnt; i++) 6296 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6297 for (i = 0; i < rcnt; i++) 6298 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6299 6300#ifdef SND_DYNSYSCTL 6301 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6302 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6303 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6304 sysctl_hdac_polling, "I", "Enable polling mode"); 6305 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6306 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6307 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6308 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6309 "Controller/Jack Sense polling interval (1-1000 ms)"); 6310#ifdef SND_DEBUG 6311 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6312 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6313 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6314 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6315#endif 6316#endif 6317 6318 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6319 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6320 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6321 pcm_setstatus(sc->dev, status); 6322 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6323 HDA_BOOTVERBOSE( 6324 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6325 hdac_codec_id(devinfo)); 6326 ); 6327 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6328 HDA_DRV_TEST_REV); 6329 6330 HDA_BOOTVERBOSE( 6331 if (devinfo->function.audio.quirks != 0) { 6332 device_printf(sc->dev, "\n"); 6333 device_printf(sc->dev, "HDA config/quirks:"); 6334 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6335 if ((devinfo->function.audio.quirks & 6336 hdac_quirks_tab[i].value) == 6337 hdac_quirks_tab[i].value) 6338 printf(" %s", hdac_quirks_tab[i].key); 6339 } 6340 printf("\n"); 6341 } 6342 device_printf(sc->dev, "\n"); 6343 device_printf(sc->dev, "+-------------------+\n"); 6344 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6345 device_printf(sc->dev, "+-------------------+\n"); 6346 hdac_dump_nodes(devinfo); 6347 device_printf(sc->dev, "\n"); 6348 device_printf(sc->dev, "+------------------------+\n"); 6349 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6350 device_printf(sc->dev, "+------------------------+\n"); 6351 device_printf(sc->dev, "\n"); 6352 i = 0; 6353 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6354 device_printf(sc->dev, "%3d: nid=%d", i, 6355 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6356 if (ctl->childwidget != NULL) 6357 printf(" cnid=%d", ctl->childwidget->nid); 6358 printf(" dir=0x%x index=%d " 6359 "ossmask=0x%08x ossdev=%d%s\n", 6360 ctl->dir, ctl->index, 6361 ctl->ossmask, ctl->ossdev, 6362 (ctl->enable == 0) ? " [DISABLED]" : ""); 6363 } 6364 device_printf(sc->dev, "\n"); 6365 device_printf(sc->dev, "+-----------------------------------+\n"); 6366 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6367 device_printf(sc->dev, "+-----------------------------------+\n"); 6368 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6369 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6370 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6371 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6372 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6373 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6374 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6375 hdac_dump_ctls(devinfo, NULL, 0); 6376 hdac_dump_dac(devinfo); 6377 hdac_dump_adc(devinfo); 6378 device_printf(sc->dev, "\n"); 6379 device_printf(sc->dev, "+--------------------------------------+\n"); 6380 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6381 device_printf(sc->dev, "+--------------------------------------+\n"); 6382 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6383 ); 6384 6385 if (sc->polling != 0) { 6386 hdac_lock(sc); 6387 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6388 hdac_unlock(sc); 6389 } 6390} 6391 6392/**************************************************************************** 6393 * int hdac_detach(device_t) 6394 * 6395 * Detach and free up resources utilized by the hdac device. 6396 ****************************************************************************/ 6397static int 6398hdac_detach(device_t dev) 6399{ 6400 struct hdac_softc *sc = NULL; 6401 struct hdac_devinfo *devinfo = NULL; 6402 int err; 6403 6404 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6405 if (devinfo != NULL && devinfo->codec != NULL) 6406 sc = devinfo->codec->sc; 6407 if (sc == NULL) 6408 return (0); 6409 6410 if (sc->registered > 0) { 6411 err = pcm_unregister(dev); 6412 if (err != 0) 6413 return (err); 6414 } 6415 6416 hdac_release_resources(sc); 6417 6418 return (0); 6419} 6420 6421static device_method_t hdac_methods[] = { 6422 /* device interface */ 6423 DEVMETHOD(device_probe, hdac_probe), 6424 DEVMETHOD(device_attach, hdac_attach), 6425 DEVMETHOD(device_detach, hdac_detach), 6426 { 0, 0 } 6427}; 6428 6429static driver_t hdac_driver = { 6430 "pcm", 6431 hdac_methods, 6432 PCM_SOFTC_SIZE, 6433}; 6434 6435DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6436MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6437MODULE_VERSION(snd_hda, 1); 6438