hdac.c revision 173817
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sys/ctype.h> 75#include <sys/taskqueue.h> 76 77#include <dev/sound/pci/hda/hdac_private.h> 78#include <dev/sound/pci/hda/hdac_reg.h> 79#include <dev/sound/pci/hda/hda_reg.h> 80#include <dev/sound/pci/hda/hdac.h> 81 82#include "mixer_if.h" 83 84#define HDA_DRV_TEST_REV "20071122_0049" 85#define HDA_WIDGET_PARSER_REV 1 86 87SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 173817 2007-11-21 11:39:27Z ariff $"); 88 89#define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93} while(0) 94 95#if 1 96#undef HDAC_INTR_EXTRA 97#define HDAC_INTR_EXTRA 1 98#endif 99 100#define hdac_lock(sc) snd_mtxlock((sc)->lock) 101#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103#define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 106#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 107 (fl) == 0xffffffff || \ 108 (((fl) & 0xffff0000) == 0xffff0000 && \ 109 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 110 (((fl) & 0x0000ffff) == 0x0000ffff && \ 111 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 112#define HDA_MATCH_ALL 0xffffffff 113#define HDAC_INVALID 0xffffffff 114 115/* Default controller / jack sense poll: 250ms */ 116#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 117 118/* 119 * Make room for possible 4096 playback/record channels, in 100 years to come. 120 */ 121#define HDAC_TRIGGER_NONE 0x00000000 122#define HDAC_TRIGGER_PLAY 0x00000fff 123#define HDAC_TRIGGER_REC 0x00fff000 124#define HDAC_TRIGGER_UNSOL 0x80000000 125 126#define HDA_MODEL_CONSTRUCT(vendor, model) \ 127 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 128 129/* Controller models */ 130 131/* Intel */ 132#define INTEL_VENDORID 0x8086 133#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 134#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 135#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 136#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 137#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 138#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 139 140/* Nvidia */ 141#define NVIDIA_VENDORID 0x10de 142#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 143#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 144#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 145#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 146#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 147#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 148#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 149#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 150#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 151 152/* ATI */ 153#define ATI_VENDORID 0x1002 154#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 155#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 156#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 157 158/* VIA */ 159#define VIA_VENDORID 0x1106 160#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 161#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 162 163/* SiS */ 164#define SIS_VENDORID 0x1039 165#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 166#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 167 168/* OEM/subvendors */ 169 170/* Intel */ 171#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 172 173/* HP/Compaq */ 174#define HP_VENDORID 0x103c 175#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 176#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 177#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 178#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 179#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 180#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 181#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 182#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 183#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 184/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 185#define HP_NX6325_SUBVENDORX 0x103c30b0 186 187/* Dell */ 188#define DELL_VENDORID 0x1028 189#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 190#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 191#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 192#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 193#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 194 195/* Clevo */ 196#define CLEVO_VENDORID 0x1558 197#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 198#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 199 200/* Acer */ 201#define ACER_VENDORID 0x1025 202#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 203#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 204#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 205#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 206 207/* Asus */ 208#define ASUS_VENDORID 0x1043 209#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 210#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 211#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 212#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 213#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 214#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 215#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 216#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 217#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 218#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 219#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 220#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 221#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 222#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 223#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 224 225/* IBM / Lenovo */ 226#define IBM_VENDORID 0x1014 227#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 228#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 229 230/* Lenovo */ 231#define LENOVO_VENDORID 0x17aa 232#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 233#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 234#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 235 236/* Samsung */ 237#define SAMSUNG_VENDORID 0x144d 238#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 239#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 240 241/* Medion ? */ 242#define MEDION_VENDORID 0x161f 243#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 244#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 245 246/* Apple Computer Inc. */ 247#define APPLE_VENDORID 0x106b 248#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 249 250/* 251 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 252 * instead of their own, which is beyond my comprehension 253 * (see HDA_CODEC_STAC9221 below). 254 */ 255#define APPLE_INTEL_MAC 0x76808384 256 257/* LG Electronics */ 258#define LG_VENDORID 0x1854 259#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 260#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 261 262/* Fujitsu Siemens */ 263#define FS_VENDORID 0x1734 264#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 265#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 266#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 267 268/* Fujitsu Limited */ 269#define FL_VENDORID 0x10cf 270#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 271#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 272 273/* Toshiba */ 274#define TOSHIBA_VENDORID 0x1179 275#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 276#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 277#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 278 279/* Micro-Star International (MSI) */ 280#define MSI_VENDORID 0x1462 281#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 282#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 283#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 284 285/* Giga-Byte Technology */ 286#define GB_VENDORID 0x1458 287#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 288#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 289 290/* Uniwill ? */ 291#define UNIWILL_VENDORID 0x1584 292#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 293#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 294 295 296/* Misc constants.. */ 297#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 298#define HDA_AMP_MUTE_NONE (0) 299#define HDA_AMP_MUTE_LEFT (1 << 0) 300#define HDA_AMP_MUTE_RIGHT (1 << 1) 301#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 302 303#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 304#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 305 306#define HDA_DAC_PATH (1 << 0) 307#define HDA_ADC_PATH (1 << 1) 308#define HDA_ADC_RECSEL (1 << 2) 309 310#define HDA_DAC_LOCKED (1 << 3) 311#define HDA_ADC_LOCKED (1 << 4) 312 313#define HDA_CTL_OUT (1 << 0) 314#define HDA_CTL_IN (1 << 1) 315#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 316 317#define HDA_GPIO_MAX 8 318/* 0 - 7 = GPIO , 8 = Flush */ 319#define HDA_QUIRK_GPIO0 (1 << 0) 320#define HDA_QUIRK_GPIO1 (1 << 1) 321#define HDA_QUIRK_GPIO2 (1 << 2) 322#define HDA_QUIRK_GPIO3 (1 << 3) 323#define HDA_QUIRK_GPIO4 (1 << 4) 324#define HDA_QUIRK_GPIO5 (1 << 5) 325#define HDA_QUIRK_GPIO6 (1 << 6) 326#define HDA_QUIRK_GPIO7 (1 << 7) 327#define HDA_QUIRK_GPIOFLUSH (1 << 8) 328 329/* 9 - 25 = anything else */ 330#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 331#define HDA_QUIRK_FIXEDRATE (1 << 10) 332#define HDA_QUIRK_FORCESTEREO (1 << 11) 333#define HDA_QUIRK_EAPDINV (1 << 12) 334#define HDA_QUIRK_DMAPOS (1 << 13) 335 336/* 26 - 31 = vrefs */ 337#define HDA_QUIRK_IVREF50 (1 << 26) 338#define HDA_QUIRK_IVREF80 (1 << 27) 339#define HDA_QUIRK_IVREF100 (1 << 28) 340#define HDA_QUIRK_OVREF50 (1 << 29) 341#define HDA_QUIRK_OVREF80 (1 << 30) 342#define HDA_QUIRK_OVREF100 (1 << 31) 343 344#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 345 HDA_QUIRK_IVREF100) 346#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 347 HDA_QUIRK_OVREF100) 348#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 349 350#define SOUND_MASK_SKIP (1 << 30) 351#define SOUND_MASK_DISABLE (1 << 31) 352 353#if __FreeBSD_version < 600000 354#define taskqueue_drain(...) 355#endif 356 357static const struct { 358 char *key; 359 uint32_t value; 360} hdac_quirks_tab[] = { 361 { "gpio0", HDA_QUIRK_GPIO0 }, 362 { "gpio1", HDA_QUIRK_GPIO1 }, 363 { "gpio2", HDA_QUIRK_GPIO2 }, 364 { "gpio3", HDA_QUIRK_GPIO3 }, 365 { "gpio4", HDA_QUIRK_GPIO4 }, 366 { "gpio5", HDA_QUIRK_GPIO5 }, 367 { "gpio6", HDA_QUIRK_GPIO6 }, 368 { "gpio7", HDA_QUIRK_GPIO7 }, 369 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 370 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 371 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 372 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 373 { "eapdinv", HDA_QUIRK_EAPDINV }, 374 { "dmapos", HDA_QUIRK_DMAPOS }, 375 { "ivref50", HDA_QUIRK_IVREF50 }, 376 { "ivref80", HDA_QUIRK_IVREF80 }, 377 { "ivref100", HDA_QUIRK_IVREF100 }, 378 { "ovref50", HDA_QUIRK_OVREF50 }, 379 { "ovref80", HDA_QUIRK_OVREF80 }, 380 { "ovref100", HDA_QUIRK_OVREF100 }, 381 { "ivref", HDA_QUIRK_IVREF }, 382 { "ovref", HDA_QUIRK_OVREF }, 383 { "vref", HDA_QUIRK_VREF }, 384}; 385#define HDAC_QUIRKS_TAB_LEN \ 386 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 387 388#define HDA_BDL_MIN 2 389#define HDA_BDL_MAX 256 390#define HDA_BDL_DEFAULT HDA_BDL_MIN 391 392#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 393#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 394 395#define HDA_BUFSZ_MIN 4096 396#define HDA_BUFSZ_MAX 65536 397#define HDA_BUFSZ_DEFAULT 16384 398 399#define HDA_PARSE_MAXDEPTH 10 400 401#define HDAC_UNSOLTAG_EVENT_HP 0x00 402#define HDAC_UNSOLTAG_EVENT_TEST 0x01 403 404MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 405 406enum { 407 HDA_PARSE_MIXER, 408 HDA_PARSE_DIRECT 409}; 410 411/* Default */ 412static uint32_t hdac_fmt[] = { 413 AFMT_STEREO | AFMT_S16_LE, 414 0 415}; 416 417static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 418 419static const struct { 420 uint32_t model; 421 char *desc; 422} hdac_devices[] = { 423 { HDA_INTEL_82801F, "Intel 82801F" }, 424 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 425 { HDA_INTEL_82801G, "Intel 82801G" }, 426 { HDA_INTEL_82801H, "Intel 82801H" }, 427 { HDA_INTEL_82801I, "Intel 82801I" }, 428 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 429 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 430 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 431 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 432 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 433 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 434 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 435 { HDA_ATI_SB450, "ATI SB450" }, 436 { HDA_ATI_SB600, "ATI SB600" }, 437 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 438 { HDA_SIS_966, "SiS 966" }, 439 /* Unknown */ 440 { HDA_INTEL_ALL, "Intel (Unknown)" }, 441 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 442 { HDA_ATI_ALL, "ATI (Unknown)" }, 443 { HDA_VIA_ALL, "VIA (Unknown)" }, 444 { HDA_SIS_ALL, "SiS (Unknown)" }, 445}; 446#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 447 448static const struct { 449 uint16_t vendor; 450 uint8_t reg; 451 uint8_t mask; 452 uint8_t enable; 453} hdac_pcie_snoop[] = { 454 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 455 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 456 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 457}; 458#define HDAC_PCIESNOOP_LEN \ 459 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 460 461static const struct { 462 uint32_t rate; 463 int valid; 464 uint16_t base; 465 uint16_t mul; 466 uint16_t div; 467} hda_rate_tab[] = { 468 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 469 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 470 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 471 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 472 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 473 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 474 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 475 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 476 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 477 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 478 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 479 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 480 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 481 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 482 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 483 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 484 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 485 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 486 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 487 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 488 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 489 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 490 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 491 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 492 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 493 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 494 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 495 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 496 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 497 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 498 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 499 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 500 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 501 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 502 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 503}; 504#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 505 506/* All codecs you can eat... */ 507#define HDA_CODEC_CONSTRUCT(vendor, id) \ 508 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 509 510/* Realtek */ 511#define REALTEK_VENDORID 0x10ec 512#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 513#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 514#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 515#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 516#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 517#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 518#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 519#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 520#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 521#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 522#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 523#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 524 525/* Analog Devices */ 526#define ANALOGDEVICES_VENDORID 0x11d4 527#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 528#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 529#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 530#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 531#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 532#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 533 534/* CMedia */ 535#define CMEDIA_VENDORID 0x434d 536#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 537#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 538 539/* Sigmatel */ 540#define SIGMATEL_VENDORID 0x8384 541#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 542#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 543#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 544#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 545#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 546#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 547#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 548 549/* 550 * Conexant 551 * 552 * Ok, the truth is, I don't have any idea at all whether 553 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 554 * place that tell me it is "Venice" is from its Windows driver INF. 555 * 556 * Venice - CX????? 557 * Waikiki - CX20551-22 558 */ 559#define CONEXANT_VENDORID 0x14f1 560#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 561#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 562#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 563 564/* VIA */ 565#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 566#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 567#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 568#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 569#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 570#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 571#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 572#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 573#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 574#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 575#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 576#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 577#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 578 579 580/* Codecs */ 581static const struct { 582 uint32_t id; 583 char *name; 584} hdac_codecs[] = { 585 { HDA_CODEC_ALC260, "Realtek ALC260" }, 586 { HDA_CODEC_ALC262, "Realtek ALC262" }, 587 { HDA_CODEC_ALC268, "Realtek ALC268" }, 588 { HDA_CODEC_ALC660, "Realtek ALC660" }, 589 { HDA_CODEC_ALC861, "Realtek ALC861" }, 590 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 591 { HDA_CODEC_ALC880, "Realtek ALC880" }, 592 { HDA_CODEC_ALC882, "Realtek ALC882" }, 593 { HDA_CODEC_ALC883, "Realtek ALC883" }, 594 { HDA_CODEC_ALC885, "Realtek ALC885" }, 595 { HDA_CODEC_ALC888, "Realtek ALC888" }, 596 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 597 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 598 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 599 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 600 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 601 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 602 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 603 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 604 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 605 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 606 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 607 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 608 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 609 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 610 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 611 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 612 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 613 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 614 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 615 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 616 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 617 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 618 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 619 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 620 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 621 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 622 /* Unknown codec */ 623 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 624 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 625 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 626 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 627 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 628 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 629}; 630#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 631 632enum { 633 HDAC_HP_SWITCH_CTL, 634 HDAC_HP_SWITCH_CTRL, 635 HDAC_HP_SWITCH_DEBUG 636}; 637 638static const struct { 639 uint32_t model; 640 uint32_t id; 641 int type; 642 int inverted; 643 int polling; 644 int execsense; 645 nid_t hpnid; 646 nid_t spkrnid[8]; 647 nid_t eapdnid; 648} hdac_hp_switch[] = { 649 /* Specific OEM models */ 650 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 651 0, 0, -1, 17, { 16, -1 }, 16 }, 652 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 653 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 654 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 655 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 656 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 657 0, 0, -1, 6, { 5, -1 }, 5 }, 658 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 659 0, 0, -1, 6, { 5, -1 }, 5 }, 660 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 661 0, 0, -1, 6, { 5, -1 }, 5 }, 662 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 663 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 664 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 665 0, 0, -1, 6, { 5, -1 }, -1 }, 666 { TOSHIBA_A135_SUBVENDOR, HDA_CODEC_ALC861VD, HDAC_HP_SWITCH_CTL, 667 0, 0, -1, 27, { 20, -1 }, -1 }, 668 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 669 0, 0, -1, 13, { 14, -1 }, -1 }, 670 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 671 0, 0, -1, 13, { 14, -1 }, -1 }, 672 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 673 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 674 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, HDAC_HP_SWITCH_CTL, 675 0, 0, -1, 21, { 20, 22, -1 }, -1 }, 676 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 677 0, 0, -1, 10, { 13, -1 }, -1 }, 678 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 679 1, 0, -1, 26, { 27, -1 }, -1 }, 680 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 681 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 682 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 683 0, 0, -1, 27, { 20, -1 }, -1 }, 684 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 685 0, 0, -1, 20, { 21, -1 }, -1 }, 686 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 687 0, 0, -1, 20, { 21, -1 }, -1 }, 688 { ACER_A4520_SUBVENDOR, HDA_CODEC_ALC268, HDAC_HP_SWITCH_CTL, 689 0, 0, -1, 20, { 21, -1 }, -1 }, 690 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 691 0, 0, -1, 20, { 21, -1 }, -1 }, 692 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 693 0, 0, -1, 20, { 27, -1 }, -1 }, 694 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 695 0, 0, -1, 20, { 27, -1 }, -1 }, 696 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 697 0, 0, -1, 20, { 21, -1 }, -1 }, 698 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 699 0, 0, -1, 20, { 16, -1 }, -1 }, 700 /* 701 * All models that at least come from the same vendor with 702 * simmilar codec. 703 */ 704 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 705 0, 0, -1, 17, { 16, -1 }, 16 }, 706 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 707 0, 0, -1, 6, { 5, -1 }, 5 }, 708 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 709 0, 0, -1, 6, { 5, -1 }, -1 }, 710 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 711 0, 0, -1, 13, { 14, -1 }, -1 }, 712#if 0 713 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 714 1, 0, -1, 26, { 27, -1 }, -1 }, 715 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 716 0, 0, -1, 20, { 21, -1 }, -1 }, 717#endif 718}; 719#define HDAC_HP_SWITCH_LEN \ 720 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 721 722static const struct { 723 uint32_t model; 724 uint32_t id; 725 nid_t eapdnid; 726 int hp_switch; 727} hdac_eapd_switch[] = { 728 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 729 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 730 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 731}; 732#define HDAC_EAPD_SWITCH_LEN \ 733 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 734 735/**************************************************************************** 736 * Function prototypes 737 ****************************************************************************/ 738static void hdac_intr_handler(void *); 739static int hdac_reset(struct hdac_softc *); 740static int hdac_get_capabilities(struct hdac_softc *); 741static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 742static int hdac_dma_alloc(struct hdac_softc *, 743 struct hdac_dma *, bus_size_t); 744static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 745static int hdac_mem_alloc(struct hdac_softc *); 746static void hdac_mem_free(struct hdac_softc *); 747static int hdac_irq_alloc(struct hdac_softc *); 748static void hdac_irq_free(struct hdac_softc *); 749static void hdac_corb_init(struct hdac_softc *); 750static void hdac_rirb_init(struct hdac_softc *); 751static void hdac_corb_start(struct hdac_softc *); 752static void hdac_rirb_start(struct hdac_softc *); 753static void hdac_scan_codecs(struct hdac_softc *, int); 754static int hdac_probe_codec(struct hdac_codec *); 755static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 756static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 757 758static void hdac_attach2(void *); 759 760static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 761 uint32_t, int); 762static void hdac_command_send_internal(struct hdac_softc *, 763 struct hdac_command_list *, int); 764 765static int hdac_probe(device_t); 766static int hdac_attach(device_t); 767static int hdac_detach(device_t); 768static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 769static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 770 uint32_t, int, int); 771static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 772 nid_t, int, int); 773static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 774 nid_t, nid_t, int, int, int, int, int, int); 775static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 776static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 777 778static int hdac_rirb_flush(struct hdac_softc *sc); 779static int hdac_unsolq_flush(struct hdac_softc *sc); 780 781#define hdac_command(a1, a2, a3) \ 782 hdac_command_sendone_internal(a1, a2, a3) 783 784#define hdac_codec_id(d) \ 785 ((uint32_t)((d == NULL) ? 0x00000000 : \ 786 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 787 ((uint32_t)(d)->device_id & 0x0000ffff)))) 788 789static char * 790hdac_codec_name(struct hdac_devinfo *devinfo) 791{ 792 uint32_t id; 793 int i; 794 795 id = hdac_codec_id(devinfo); 796 797 for (i = 0; i < HDAC_CODECS_LEN; i++) { 798 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 799 return (hdac_codecs[i].name); 800 } 801 802 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 803} 804 805static char * 806hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 807{ 808 static char *ossname[] = SOUND_DEVICE_NAMES; 809 static char *unknown = "???"; 810 int i; 811 812 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 813 if (devmask & (1 << i)) 814 return (ossname[i]); 815 } 816 return (unknown); 817} 818 819static void 820hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 821{ 822 static char *ossname[] = SOUND_DEVICE_NAMES; 823 int i, first = 1; 824 825 bzero(buf, len); 826 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 827 if (mask & (1 << i)) { 828 if (first == 0) 829 strlcat(buf, ", ", len); 830 strlcat(buf, ossname[i], len); 831 first = 0; 832 } 833 } 834} 835 836static struct hdac_audio_ctl * 837hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 838{ 839 if (devinfo == NULL || 840 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 841 index == NULL || devinfo->function.audio.ctl == NULL || 842 devinfo->function.audio.ctlcnt < 1 || 843 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 844 return (NULL); 845 return (&devinfo->function.audio.ctl[(*index)++]); 846} 847 848static struct hdac_audio_ctl * 849hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 850 int index, int cnt) 851{ 852 struct hdac_audio_ctl *ctl, *retctl = NULL; 853 int i, at, atindex, found = 0; 854 855 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 856 return (NULL); 857 858 at = cnt; 859 if (at == 0) 860 at = 1; 861 else if (at < 0) 862 at = -1; 863 atindex = index; 864 if (atindex < 0) 865 atindex = -1; 866 867 i = 0; 868 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 869 if (ctl->enable == 0 || ctl->widget == NULL) 870 continue; 871 if (!(ctl->widget->nid == nid && (atindex == -1 || 872 ctl->index == atindex))) 873 continue; 874 found++; 875 if (found == cnt) 876 return (ctl); 877 retctl = ctl; 878 } 879 880 return ((at == -1) ? retctl : NULL); 881} 882 883static void 884hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 885{ 886 struct hdac_softc *sc; 887 struct hdac_widget *w; 888 struct hdac_audio_ctl *ctl; 889 uint32_t val, id, res; 890 int i = 0, j, timeout, forcemute; 891 nid_t cad; 892 893 if (devinfo == NULL || devinfo->codec == NULL || 894 devinfo->codec->sc == NULL) 895 return; 896 897 sc = devinfo->codec->sc; 898 cad = devinfo->codec->cad; 899 id = hdac_codec_id(devinfo); 900 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 901 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 902 sc->pci_subvendor) && 903 hdac_hp_switch[i].id == id) 904 break; 905 } 906 907 if (i >= HDAC_HP_SWITCH_LEN) 908 return; 909 910 forcemute = 0; 911 if (hdac_hp_switch[i].eapdnid != -1) { 912 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 913 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 914 forcemute = (w->param.eapdbtl & 915 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 916 } 917 918 if (hdac_hp_switch[i].execsense != -1) 919 hdac_command(sc, 920 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 921 hdac_hp_switch[i].execsense), cad); 922 923 timeout = 10000; 924 do { 925 res = hdac_command(sc, 926 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 927 cad); 928 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 929 break; 930 DELAY(10); 931 } while (--timeout != 0); 932 933 HDA_BOOTVERBOSE( 934 device_printf(sc->dev, 935 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 936 hdac_hp_switch[i].hpnid, timeout, res); 937 ); 938 939 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 940 res ^= hdac_hp_switch[i].inverted; 941 942 switch (hdac_hp_switch[i].type) { 943 case HDAC_HP_SWITCH_CTL: 944 ctl = hdac_audio_ctl_amp_get(devinfo, 945 hdac_hp_switch[i].hpnid, 0, 1); 946 if (ctl != NULL) { 947 val = (res != 0 && forcemute == 0) ? 948 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 949 if (val != ctl->muted) { 950 ctl->muted = val; 951 hdac_audio_ctl_amp_set(ctl, 952 HDA_AMP_MUTE_DEFAULT, ctl->left, 953 ctl->right); 954 } 955 } 956 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 957 ctl = hdac_audio_ctl_amp_get(devinfo, 958 hdac_hp_switch[i].spkrnid[j], 0, 1); 959 if (ctl == NULL) 960 continue; 961 val = (res != 0 || forcemute == 1) ? 962 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 963 if (val == ctl->muted) 964 continue; 965 ctl->muted = val; 966 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 967 ctl->left, ctl->right); 968 } 969 break; 970 case HDAC_HP_SWITCH_CTRL: 971 if (res != 0) { 972 /* HP in */ 973 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 974 if (w != NULL && w->type == 975 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 976 if (forcemute == 0) 977 val = w->wclass.pin.ctrl | 978 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 979 else 980 val = w->wclass.pin.ctrl & 981 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 982 if (val != w->wclass.pin.ctrl) { 983 w->wclass.pin.ctrl = val; 984 hdac_command(sc, 985 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 986 w->nid, w->wclass.pin.ctrl), cad); 987 } 988 } 989 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 990 w = hdac_widget_get(devinfo, 991 hdac_hp_switch[i].spkrnid[j]); 992 if (w == NULL || w->type != 993 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 994 continue; 995 val = w->wclass.pin.ctrl & 996 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 997 if (val == w->wclass.pin.ctrl) 998 continue; 999 w->wclass.pin.ctrl = val; 1000 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1001 cad, w->nid, w->wclass.pin.ctrl), cad); 1002 } 1003 } else { 1004 /* HP out */ 1005 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 1006 if (w != NULL && w->type == 1007 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1008 val = w->wclass.pin.ctrl & 1009 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1010 if (val != w->wclass.pin.ctrl) { 1011 w->wclass.pin.ctrl = val; 1012 hdac_command(sc, 1013 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1014 w->nid, w->wclass.pin.ctrl), cad); 1015 } 1016 } 1017 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1018 w = hdac_widget_get(devinfo, 1019 hdac_hp_switch[i].spkrnid[j]); 1020 if (w == NULL || w->type != 1021 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1022 continue; 1023 if (forcemute == 0) 1024 val = w->wclass.pin.ctrl | 1025 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1026 else 1027 val = w->wclass.pin.ctrl & 1028 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1029 if (val == w->wclass.pin.ctrl) 1030 continue; 1031 w->wclass.pin.ctrl = val; 1032 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1033 cad, w->nid, w->wclass.pin.ctrl), cad); 1034 } 1035 } 1036 break; 1037 case HDAC_HP_SWITCH_DEBUG: 1038 if (hdac_hp_switch[i].execsense != -1) 1039 hdac_command(sc, 1040 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1041 hdac_hp_switch[i].execsense), cad); 1042 res = hdac_command(sc, 1043 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1044 device_printf(sc->dev, 1045 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1046 hdac_hp_switch[i].hpnid, res); 1047 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1048 w = hdac_widget_get(devinfo, 1049 hdac_hp_switch[i].spkrnid[j]); 1050 if (w == NULL || w->type != 1051 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1052 continue; 1053 if (hdac_hp_switch[i].execsense != -1) 1054 hdac_command(sc, 1055 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1056 hdac_hp_switch[i].execsense), cad); 1057 res = hdac_command(sc, 1058 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1059 device_printf(sc->dev, 1060 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1061 j + 1, w->nid, res); 1062 } 1063 break; 1064 default: 1065 break; 1066 } 1067} 1068 1069static void 1070hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1071{ 1072 struct hdac_softc *sc; 1073 struct hdac_devinfo *devinfo = NULL; 1074 device_t *devlist = NULL; 1075 int devcount, i; 1076 1077 if (codec == NULL || codec->sc == NULL) 1078 return; 1079 1080 sc = codec->sc; 1081 1082 HDA_BOOTVERBOSE( 1083 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1084 ); 1085 1086 device_get_children(sc->dev, &devlist, &devcount); 1087 for (i = 0; devlist != NULL && i < devcount; i++) { 1088 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1089 if (devinfo != NULL && devinfo->node_type == 1090 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1091 devinfo->codec != NULL && 1092 devinfo->codec->cad == codec->cad) { 1093 break; 1094 } else 1095 devinfo = NULL; 1096 } 1097 if (devlist != NULL) 1098 free(devlist, M_TEMP); 1099 1100 if (devinfo == NULL) 1101 return; 1102 1103 switch (tag) { 1104 case HDAC_UNSOLTAG_EVENT_HP: 1105 hdac_hp_switch_handler(devinfo); 1106 break; 1107 case HDAC_UNSOLTAG_EVENT_TEST: 1108 device_printf(sc->dev, "Unsol Test!\n"); 1109 break; 1110 default: 1111 break; 1112 } 1113} 1114 1115static int 1116hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1117{ 1118 /* XXX to be removed */ 1119#ifdef HDAC_INTR_EXTRA 1120 uint32_t res; 1121#endif 1122 1123 if (!(ch->flags & HDAC_CHN_RUNNING)) 1124 return (0); 1125 1126 /* XXX to be removed */ 1127#ifdef HDAC_INTR_EXTRA 1128 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1129#endif 1130 1131 /* XXX to be removed */ 1132#ifdef HDAC_INTR_EXTRA 1133 HDA_BOOTVERBOSE( 1134 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1135 device_printf(sc->dev, 1136 "PCMDIR_%s intr triggered beyond stream boundary:" 1137 "%08x\n", 1138 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1139 ); 1140#endif 1141 1142 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1143 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1144 1145 /* XXX to be removed */ 1146#ifdef HDAC_INTR_EXTRA 1147 if (res & HDAC_SDSTS_BCIS) { 1148#endif 1149 return (1); 1150 /* XXX to be removed */ 1151#ifdef HDAC_INTR_EXTRA 1152 } 1153#endif 1154 1155 return (0); 1156} 1157 1158/**************************************************************************** 1159 * void hdac_intr_handler(void *) 1160 * 1161 * Interrupt handler. Processes interrupts received from the hdac. 1162 ****************************************************************************/ 1163static void 1164hdac_intr_handler(void *context) 1165{ 1166 struct hdac_softc *sc; 1167 uint32_t intsts; 1168 uint8_t rirbsts; 1169 struct hdac_rirb *rirb_base; 1170 uint32_t trigger; 1171 1172 sc = (struct hdac_softc *)context; 1173 1174 hdac_lock(sc); 1175 if (sc->polling != 0) { 1176 hdac_unlock(sc); 1177 return; 1178 } 1179 1180 /* Do we have anything to do? */ 1181 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1182 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1183 hdac_unlock(sc); 1184 return; 1185 } 1186 1187 trigger = 0; 1188 1189 /* Was this a controller interrupt? */ 1190 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1191 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1192 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1193 /* Get as many responses that we can */ 1194 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1195 HDAC_WRITE_1(&sc->mem, 1196 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1197 if (hdac_rirb_flush(sc) != 0) 1198 trigger |= HDAC_TRIGGER_UNSOL; 1199 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1200 } 1201 /* XXX to be removed */ 1202 /* Clear interrupt and exit */ 1203#ifdef HDAC_INTR_EXTRA 1204 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1205#endif 1206 } 1207 1208 if (intsts & HDAC_INTSTS_SIS_MASK) { 1209 if ((intsts & (1 << sc->num_iss)) && 1210 hdac_stream_intr(sc, &sc->play) != 0) 1211 trigger |= HDAC_TRIGGER_PLAY; 1212 if ((intsts & (1 << 0)) && 1213 hdac_stream_intr(sc, &sc->rec) != 0) 1214 trigger |= HDAC_TRIGGER_REC; 1215 /* XXX to be removed */ 1216#ifdef HDAC_INTR_EXTRA 1217 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1218 HDAC_INTSTS_SIS_MASK); 1219#endif 1220 } 1221 1222 hdac_unlock(sc); 1223 1224 if (trigger & HDAC_TRIGGER_PLAY) 1225 chn_intr(sc->play.c); 1226 if (trigger & HDAC_TRIGGER_REC) 1227 chn_intr(sc->rec.c); 1228 if (trigger & HDAC_TRIGGER_UNSOL) 1229 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1230} 1231 1232/**************************************************************************** 1233 * int hdac_reset(hdac_softc *) 1234 * 1235 * Reset the hdac to a quiescent and known state. 1236 ****************************************************************************/ 1237static int 1238hdac_reset(struct hdac_softc *sc) 1239{ 1240 uint32_t gctl; 1241 int count, i; 1242 1243 /* 1244 * Stop all Streams DMA engine 1245 */ 1246 for (i = 0; i < sc->num_iss; i++) 1247 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1248 for (i = 0; i < sc->num_oss; i++) 1249 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1250 for (i = 0; i < sc->num_bss; i++) 1251 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1252 1253 /* 1254 * Stop Control DMA engines. 1255 */ 1256 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1257 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1258 1259 /* 1260 * Reset DMA position buffer. 1261 */ 1262 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1263 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1264 1265 /* 1266 * Reset the controller. The reset must remain asserted for 1267 * a minimum of 100us. 1268 */ 1269 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1270 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1271 count = 10000; 1272 do { 1273 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1274 if (!(gctl & HDAC_GCTL_CRST)) 1275 break; 1276 DELAY(10); 1277 } while (--count); 1278 if (gctl & HDAC_GCTL_CRST) { 1279 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1280 return (ENXIO); 1281 } 1282 DELAY(100); 1283 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1284 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1285 count = 10000; 1286 do { 1287 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1288 if (gctl & HDAC_GCTL_CRST) 1289 break; 1290 DELAY(10); 1291 } while (--count); 1292 if (!(gctl & HDAC_GCTL_CRST)) { 1293 device_printf(sc->dev, "Device stuck in reset\n"); 1294 return (ENXIO); 1295 } 1296 1297 /* 1298 * Wait for codecs to finish their own reset sequence. The delay here 1299 * should be of 250us but for some reasons, on it's not enough on my 1300 * computer. Let's use twice as much as necessary to make sure that 1301 * it's reset properly. 1302 */ 1303 DELAY(1000); 1304 1305 return (0); 1306} 1307 1308 1309/**************************************************************************** 1310 * int hdac_get_capabilities(struct hdac_softc *); 1311 * 1312 * Retreive the general capabilities of the hdac; 1313 * Number of Input Streams 1314 * Number of Output Streams 1315 * Number of bidirectional Streams 1316 * 64bit ready 1317 * CORB and RIRB sizes 1318 ****************************************************************************/ 1319static int 1320hdac_get_capabilities(struct hdac_softc *sc) 1321{ 1322 uint16_t gcap; 1323 uint8_t corbsize, rirbsize; 1324 1325 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1326 sc->num_iss = HDAC_GCAP_ISS(gcap); 1327 sc->num_oss = HDAC_GCAP_OSS(gcap); 1328 sc->num_bss = HDAC_GCAP_BSS(gcap); 1329 1330 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1331 1332 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1333 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1334 HDAC_CORBSIZE_CORBSZCAP_256) 1335 sc->corb_size = 256; 1336 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1337 HDAC_CORBSIZE_CORBSZCAP_16) 1338 sc->corb_size = 16; 1339 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1340 HDAC_CORBSIZE_CORBSZCAP_2) 1341 sc->corb_size = 2; 1342 else { 1343 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1344 __func__, corbsize); 1345 return (ENXIO); 1346 } 1347 1348 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1349 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1350 HDAC_RIRBSIZE_RIRBSZCAP_256) 1351 sc->rirb_size = 256; 1352 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1353 HDAC_RIRBSIZE_RIRBSZCAP_16) 1354 sc->rirb_size = 16; 1355 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1356 HDAC_RIRBSIZE_RIRBSZCAP_2) 1357 sc->rirb_size = 2; 1358 else { 1359 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1360 __func__, rirbsize); 1361 return (ENXIO); 1362 } 1363 1364 return (0); 1365} 1366 1367 1368/**************************************************************************** 1369 * void hdac_dma_cb 1370 * 1371 * This function is called by bus_dmamap_load when the mapping has been 1372 * established. We just record the physical address of the mapping into 1373 * the struct hdac_dma passed in. 1374 ****************************************************************************/ 1375static void 1376hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1377{ 1378 struct hdac_dma *dma; 1379 1380 if (error == 0) { 1381 dma = (struct hdac_dma *)callback_arg; 1382 dma->dma_paddr = segs[0].ds_addr; 1383 } 1384} 1385 1386 1387/**************************************************************************** 1388 * int hdac_dma_alloc 1389 * 1390 * This function allocate and setup a dma region (struct hdac_dma). 1391 * It must be freed by a corresponding hdac_dma_free. 1392 ****************************************************************************/ 1393static int 1394hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1395{ 1396 bus_size_t roundsz; 1397 int result; 1398 int lowaddr; 1399 1400 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1401 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1402 BUS_SPACE_MAXADDR_32BIT; 1403 bzero(dma, sizeof(*dma)); 1404 1405 /* 1406 * Create a DMA tag 1407 */ 1408 result = bus_dma_tag_create(NULL, /* parent */ 1409 HDAC_DMA_ALIGNMENT, /* alignment */ 1410 0, /* boundary */ 1411 lowaddr, /* lowaddr */ 1412 BUS_SPACE_MAXADDR, /* highaddr */ 1413 NULL, /* filtfunc */ 1414 NULL, /* fistfuncarg */ 1415 roundsz, /* maxsize */ 1416 1, /* nsegments */ 1417 roundsz, /* maxsegsz */ 1418 0, /* flags */ 1419 NULL, /* lockfunc */ 1420 NULL, /* lockfuncarg */ 1421 &dma->dma_tag); /* dmat */ 1422 if (result != 0) { 1423 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1424 __func__, result); 1425 goto hdac_dma_alloc_fail; 1426 } 1427 1428 /* 1429 * Allocate DMA memory 1430 */ 1431 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1432 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1433 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1434 &dma->dma_map); 1435 if (result != 0) { 1436 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1437 __func__, result); 1438 goto hdac_dma_alloc_fail; 1439 } 1440 1441 dma->dma_size = roundsz; 1442 1443 /* 1444 * Map the memory 1445 */ 1446 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1447 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1448 if (result != 0 || dma->dma_paddr == 0) { 1449 if (result == 0) 1450 result = ENOMEM; 1451 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1452 __func__, result); 1453 goto hdac_dma_alloc_fail; 1454 } 1455 1456 HDA_BOOTVERBOSE( 1457 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1458 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1459 ); 1460 1461 return (0); 1462 1463hdac_dma_alloc_fail: 1464 hdac_dma_free(sc, dma); 1465 1466 return (result); 1467} 1468 1469 1470/**************************************************************************** 1471 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1472 * 1473 * Free a struct dhac_dma that has been previously allocated via the 1474 * hdac_dma_alloc function. 1475 ****************************************************************************/ 1476static void 1477hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1478{ 1479 if (dma->dma_map != NULL) { 1480#if 0 1481 /* Flush caches */ 1482 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1483 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1484#endif 1485 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1486 } 1487 if (dma->dma_vaddr != NULL) { 1488 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1489 dma->dma_vaddr = NULL; 1490 } 1491 dma->dma_map = NULL; 1492 if (dma->dma_tag != NULL) { 1493 bus_dma_tag_destroy(dma->dma_tag); 1494 dma->dma_tag = NULL; 1495 } 1496 dma->dma_size = 0; 1497} 1498 1499/**************************************************************************** 1500 * int hdac_mem_alloc(struct hdac_softc *) 1501 * 1502 * Allocate all the bus resources necessary to speak with the physical 1503 * controller. 1504 ****************************************************************************/ 1505static int 1506hdac_mem_alloc(struct hdac_softc *sc) 1507{ 1508 struct hdac_mem *mem; 1509 1510 mem = &sc->mem; 1511 mem->mem_rid = PCIR_BAR(0); 1512 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1513 &mem->mem_rid, RF_ACTIVE); 1514 if (mem->mem_res == NULL) { 1515 device_printf(sc->dev, 1516 "%s: Unable to allocate memory resource\n", __func__); 1517 return (ENOMEM); 1518 } 1519 mem->mem_tag = rman_get_bustag(mem->mem_res); 1520 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1521 1522 return (0); 1523} 1524 1525/**************************************************************************** 1526 * void hdac_mem_free(struct hdac_softc *) 1527 * 1528 * Free up resources previously allocated by hdac_mem_alloc. 1529 ****************************************************************************/ 1530static void 1531hdac_mem_free(struct hdac_softc *sc) 1532{ 1533 struct hdac_mem *mem; 1534 1535 mem = &sc->mem; 1536 if (mem->mem_res != NULL) 1537 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1538 mem->mem_res); 1539 mem->mem_res = NULL; 1540} 1541 1542/**************************************************************************** 1543 * int hdac_irq_alloc(struct hdac_softc *) 1544 * 1545 * Allocate and setup the resources necessary for interrupt handling. 1546 ****************************************************************************/ 1547static int 1548hdac_irq_alloc(struct hdac_softc *sc) 1549{ 1550 struct hdac_irq *irq; 1551 int result; 1552 1553 irq = &sc->irq; 1554 irq->irq_rid = 0x0; 1555 1556#if __FreeBSD_version >= 602106 1557 if ((sc->flags & HDAC_F_MSI) && 1558 (result = pci_msi_count(sc->dev)) == 1 && 1559 pci_alloc_msi(sc->dev, &result) == 0) 1560 irq->irq_rid = 0x1; 1561 else 1562#endif 1563 sc->flags &= ~HDAC_F_MSI; 1564 1565 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1566 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1567 if (irq->irq_res == NULL) { 1568 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1569 __func__); 1570 goto hdac_irq_alloc_fail; 1571 } 1572 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1573 hdac_intr_handler, sc, &irq->irq_handle); 1574 if (result != 0) { 1575 device_printf(sc->dev, 1576 "%s: Unable to setup interrupt handler (%x)\n", 1577 __func__, result); 1578 goto hdac_irq_alloc_fail; 1579 } 1580 1581 return (0); 1582 1583hdac_irq_alloc_fail: 1584 hdac_irq_free(sc); 1585 1586 return (ENXIO); 1587} 1588 1589/**************************************************************************** 1590 * void hdac_irq_free(struct hdac_softc *) 1591 * 1592 * Free up resources previously allocated by hdac_irq_alloc. 1593 ****************************************************************************/ 1594static void 1595hdac_irq_free(struct hdac_softc *sc) 1596{ 1597 struct hdac_irq *irq; 1598 1599 irq = &sc->irq; 1600 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1601 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1602 if (irq->irq_res != NULL) 1603 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1604 irq->irq_res); 1605#if __FreeBSD_version >= 602106 1606 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1607 pci_release_msi(sc->dev); 1608#endif 1609 irq->irq_handle = NULL; 1610 irq->irq_res = NULL; 1611 irq->irq_rid = 0x0; 1612} 1613 1614/**************************************************************************** 1615 * void hdac_corb_init(struct hdac_softc *) 1616 * 1617 * Initialize the corb registers for operations but do not start it up yet. 1618 * The CORB engine must not be running when this function is called. 1619 ****************************************************************************/ 1620static void 1621hdac_corb_init(struct hdac_softc *sc) 1622{ 1623 uint8_t corbsize; 1624 uint64_t corbpaddr; 1625 1626 /* Setup the CORB size. */ 1627 switch (sc->corb_size) { 1628 case 256: 1629 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1630 break; 1631 case 16: 1632 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1633 break; 1634 case 2: 1635 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1636 break; 1637 default: 1638 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1639 } 1640 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1641 1642 /* Setup the CORB Address in the hdac */ 1643 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1644 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1645 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1646 1647 /* Set the WP and RP */ 1648 sc->corb_wp = 0; 1649 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1650 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1651 /* 1652 * The HDA specification indicates that the CORBRPRST bit will always 1653 * read as zero. Unfortunately, it seems that at least the 82801G 1654 * doesn't reset the bit to zero, which stalls the corb engine. 1655 * manually reset the bit to zero before continuing. 1656 */ 1657 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1658 1659 /* Enable CORB error reporting */ 1660#if 0 1661 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1662#endif 1663} 1664 1665/**************************************************************************** 1666 * void hdac_rirb_init(struct hdac_softc *) 1667 * 1668 * Initialize the rirb registers for operations but do not start it up yet. 1669 * The RIRB engine must not be running when this function is called. 1670 ****************************************************************************/ 1671static void 1672hdac_rirb_init(struct hdac_softc *sc) 1673{ 1674 uint8_t rirbsize; 1675 uint64_t rirbpaddr; 1676 1677 /* Setup the RIRB size. */ 1678 switch (sc->rirb_size) { 1679 case 256: 1680 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1681 break; 1682 case 16: 1683 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1684 break; 1685 case 2: 1686 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1687 break; 1688 default: 1689 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1690 } 1691 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1692 1693 /* Setup the RIRB Address in the hdac */ 1694 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1695 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1696 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1697 1698 /* Setup the WP and RP */ 1699 sc->rirb_rp = 0; 1700 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1701 1702 if (sc->polling == 0) { 1703 /* Setup the interrupt threshold */ 1704 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1705 1706 /* Enable Overrun and response received reporting */ 1707#if 0 1708 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1709 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1710#else 1711 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1712#endif 1713 } 1714 1715#if 0 1716 /* 1717 * Make sure that the Host CPU cache doesn't contain any dirty 1718 * cache lines that falls in the rirb. If I understood correctly, it 1719 * should be sufficient to do this only once as the rirb is purely 1720 * read-only from now on. 1721 */ 1722 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1723 BUS_DMASYNC_PREREAD); 1724#endif 1725} 1726 1727/**************************************************************************** 1728 * void hdac_corb_start(hdac_softc *) 1729 * 1730 * Startup the corb DMA engine 1731 ****************************************************************************/ 1732static void 1733hdac_corb_start(struct hdac_softc *sc) 1734{ 1735 uint32_t corbctl; 1736 1737 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1738 corbctl |= HDAC_CORBCTL_CORBRUN; 1739 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1740} 1741 1742/**************************************************************************** 1743 * void hdac_rirb_start(hdac_softc *) 1744 * 1745 * Startup the rirb DMA engine 1746 ****************************************************************************/ 1747static void 1748hdac_rirb_start(struct hdac_softc *sc) 1749{ 1750 uint32_t rirbctl; 1751 1752 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1753 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1754 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1755} 1756 1757 1758/**************************************************************************** 1759 * void hdac_scan_codecs(struct hdac_softc *, int) 1760 * 1761 * Scan the bus for available codecs, starting with num. 1762 ****************************************************************************/ 1763static void 1764hdac_scan_codecs(struct hdac_softc *sc, int num) 1765{ 1766 struct hdac_codec *codec; 1767 int i; 1768 uint16_t statests; 1769 1770 if (num < 0) 1771 num = 0; 1772 if (num >= HDAC_CODEC_MAX) 1773 num = HDAC_CODEC_MAX - 1; 1774 1775 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1776 for (i = num; i < HDAC_CODEC_MAX; i++) { 1777 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1778 /* We have found a codec. */ 1779 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1780 M_HDAC, M_ZERO | M_NOWAIT); 1781 if (codec == NULL) { 1782 device_printf(sc->dev, 1783 "Unable to allocate memory for codec\n"); 1784 continue; 1785 } 1786 codec->commands = NULL; 1787 codec->responses_received = 0; 1788 codec->verbs_sent = 0; 1789 codec->sc = sc; 1790 codec->cad = i; 1791 sc->codecs[i] = codec; 1792 if (hdac_probe_codec(codec) != 0) 1793 break; 1794 } 1795 } 1796 /* All codecs have been probed, now try to attach drivers to them */ 1797 /* bus_generic_attach(sc->dev); */ 1798} 1799 1800/**************************************************************************** 1801 * void hdac_probe_codec(struct hdac_softc *, int) 1802 * 1803 * Probe a the given codec_id for available function groups. 1804 ****************************************************************************/ 1805static int 1806hdac_probe_codec(struct hdac_codec *codec) 1807{ 1808 struct hdac_softc *sc = codec->sc; 1809 struct hdac_devinfo *devinfo; 1810 uint32_t vendorid, revisionid, subnode; 1811 int startnode; 1812 int endnode; 1813 int i; 1814 nid_t cad = codec->cad; 1815 1816 HDA_BOOTVERBOSE( 1817 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1818 ); 1819 vendorid = hdac_command(sc, 1820 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1821 cad); 1822 revisionid = hdac_command(sc, 1823 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1824 cad); 1825 subnode = hdac_command(sc, 1826 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1827 cad); 1828 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1829 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1830 1831 HDA_BOOTVERBOSE( 1832 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1833 startnode, endnode); 1834 ); 1835 for (i = startnode; i < endnode; i++) { 1836 devinfo = hdac_probe_function(codec, i); 1837 if (devinfo != NULL) { 1838 /* XXX Ignore other FG. */ 1839 devinfo->vendor_id = 1840 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1841 devinfo->device_id = 1842 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1843 devinfo->revision_id = 1844 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1845 devinfo->stepping_id = 1846 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1847 HDA_BOOTVERBOSE( 1848 device_printf(sc->dev, 1849 "HDA_DEBUG: \tFound AFG nid=%d " 1850 "[startnode=%d endnode=%d]\n", 1851 devinfo->nid, startnode, endnode); 1852 ); 1853 return (1); 1854 } 1855 } 1856 1857 HDA_BOOTVERBOSE( 1858 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1859 ); 1860 return (0); 1861} 1862 1863static struct hdac_devinfo * 1864hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1865{ 1866 struct hdac_softc *sc = codec->sc; 1867 struct hdac_devinfo *devinfo; 1868 uint32_t fctgrptype; 1869 nid_t cad = codec->cad; 1870 1871 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1872 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1873 1874 /* XXX For now, ignore other FG. */ 1875 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1876 return (NULL); 1877 1878 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1879 M_NOWAIT | M_ZERO); 1880 if (devinfo == NULL) { 1881 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1882 __func__); 1883 return (NULL); 1884 } 1885 1886 devinfo->nid = nid; 1887 devinfo->node_type = fctgrptype; 1888 devinfo->codec = codec; 1889 1890 hdac_add_child(sc, devinfo); 1891 1892 return (devinfo); 1893} 1894 1895static void 1896hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1897{ 1898 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1899 device_set_ivars(devinfo->dev, (void *)devinfo); 1900 /* XXX - Print more information when booting verbose??? */ 1901} 1902 1903static void 1904hdac_widget_connection_parse(struct hdac_widget *w) 1905{ 1906 struct hdac_softc *sc = w->devinfo->codec->sc; 1907 uint32_t res; 1908 int i, j, max, ents, entnum; 1909 nid_t cad = w->devinfo->codec->cad; 1910 nid_t nid = w->nid; 1911 nid_t cnid, addcnid, prevcnid; 1912 1913 w->nconns = 0; 1914 1915 res = hdac_command(sc, 1916 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1917 1918 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1919 1920 if (ents < 1) 1921 return; 1922 1923 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1924 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1925 prevcnid = 0; 1926 1927#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1928#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1929#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1930#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1931#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1932 1933 for (i = 0; i < ents; i += entnum) { 1934 res = hdac_command(sc, 1935 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1936 for (j = 0; j < entnum; j++) { 1937 cnid = CONN_CNID(res, entnum, j); 1938 if (cnid == 0) { 1939 if (w->nconns < ents) 1940 device_printf(sc->dev, 1941 "%s: nid=%d WARNING: zero cnid " 1942 "entnum=%d j=%d index=%d " 1943 "entries=%d found=%d res=0x%08x\n", 1944 __func__, nid, entnum, j, i, 1945 ents, w->nconns, res); 1946 else 1947 goto getconns_out; 1948 } 1949 if (cnid < w->devinfo->startnode || 1950 cnid >= w->devinfo->endnode) { 1951 HDA_BOOTVERBOSE( 1952 device_printf(sc->dev, 1953 "%s: GHOST: nid=%d j=%d " 1954 "entnum=%d index=%d res=0x%08x\n", 1955 __func__, nid, j, entnum, i, res); 1956 ); 1957 } 1958 if (CONN_RANGE(res, entnum, j) == 0) 1959 addcnid = cnid; 1960 else if (prevcnid == 0 || prevcnid >= cnid) { 1961 device_printf(sc->dev, 1962 "%s: WARNING: Invalid child range " 1963 "nid=%d index=%d j=%d entnum=%d " 1964 "prevcnid=%d cnid=%d res=0x%08x\n", 1965 __func__, nid, i, j, entnum, prevcnid, 1966 cnid, res); 1967 addcnid = cnid; 1968 } else 1969 addcnid = prevcnid + 1; 1970 while (addcnid <= cnid) { 1971 if (w->nconns > max) { 1972 device_printf(sc->dev, 1973 "%s: nid=%d: Adding %d: " 1974 "Max connection reached! max=%d\n", 1975 __func__, nid, addcnid, max + 1); 1976 goto getconns_out; 1977 } 1978 w->conns[w->nconns++] = addcnid++; 1979 } 1980 prevcnid = cnid; 1981 } 1982 } 1983 1984getconns_out: 1985 HDA_BOOTVERBOSE( 1986 device_printf(sc->dev, 1987 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1988 __func__, nid, ents, w->nconns); 1989 ); 1990 return; 1991} 1992 1993static uint32_t 1994hdac_widget_pin_getconfig(struct hdac_widget *w) 1995{ 1996 struct hdac_softc *sc; 1997 uint32_t config, orig, id; 1998 nid_t cad, nid; 1999 2000 sc = w->devinfo->codec->sc; 2001 cad = w->devinfo->codec->cad; 2002 nid = w->nid; 2003 id = hdac_codec_id(w->devinfo); 2004 2005 config = hdac_command(sc, 2006 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2007 cad); 2008 orig = config; 2009 2010 /* 2011 * XXX REWRITE!!!! Don't argue! 2012 */ 2013 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2014 switch (nid) { 2015 case 26: 2016 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2017 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2018 break; 2019 case 27: 2020 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2021 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2022 break; 2023 default: 2024 break; 2025 } 2026 } else if (id == HDA_CODEC_ALC880 && 2027 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2028 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2029 /* 2030 * Super broken BIOS 2031 */ 2032 switch (nid) { 2033 case 20: 2034 break; 2035 case 21: 2036 break; 2037 case 22: 2038 break; 2039 case 23: 2040 break; 2041 case 24: /* MIC1 */ 2042 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2043 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2044 break; 2045 case 25: /* XXX MIC2 */ 2046 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2047 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2048 break; 2049 case 26: /* LINE1 */ 2050 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2051 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2052 break; 2053 case 27: /* XXX LINE2 */ 2054 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2055 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2056 break; 2057 case 28: /* CD */ 2058 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2059 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2060 break; 2061 case 30: 2062 break; 2063 case 31: 2064 break; 2065 default: 2066 break; 2067 } 2068 } else if (id == HDA_CODEC_ALC883 && 2069 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2070 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2071 switch (nid) { 2072 case 25: 2073 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2074 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2075 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2076 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2077 break; 2078 case 28: 2079 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2080 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2081 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2082 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2083 break; 2084 default: 2085 break; 2086 } 2087 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2088 HP_V3000_SUBVENDOR) { 2089 switch (nid) { 2090 case 18: 2091 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2092 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2093 break; 2094 case 20: 2095 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2096 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2097 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2098 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2099 break; 2100 case 21: 2101 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2102 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2103 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2104 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2105 break; 2106 default: 2107 break; 2108 } 2109 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2110 HP_DV5000_SUBVENDOR) { 2111 switch (nid) { 2112 case 20: 2113 case 21: 2114 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2115 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2116 break; 2117 default: 2118 break; 2119 } 2120 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2121 ASUS_W6F_SUBVENDOR) { 2122 switch (nid) { 2123 case 11: 2124 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2125 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2126 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2127 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2128 break; 2129 case 15: 2130 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2131 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2132 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2133 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2134 break; 2135 default: 2136 break; 2137 } 2138 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2139 UNIWILL_9075_SUBVENDOR) { 2140 switch (nid) { 2141 case 15: 2142 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2143 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2144 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2145 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2146 break; 2147 default: 2148 break; 2149 } 2150 } else if (id == HDA_CODEC_AD1986A && 2151 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2152 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2153 switch (nid) { 2154 case 28: /* LINE */ 2155 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2156 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2157 break; 2158 case 29: /* MIC */ 2159 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2160 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2161 break; 2162 default: 2163 break; 2164 } 2165 } 2166 2167 HDA_BOOTVERBOSE( 2168 if (config != orig) 2169 device_printf(sc->dev, 2170 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2171 nid, orig, config); 2172 ); 2173 2174 return (config); 2175} 2176 2177static uint32_t 2178hdac_widget_pin_getcaps(struct hdac_widget *w) 2179{ 2180 struct hdac_softc *sc; 2181 uint32_t caps, orig, id; 2182 nid_t cad, nid; 2183 2184 sc = w->devinfo->codec->sc; 2185 cad = w->devinfo->codec->cad; 2186 nid = w->nid; 2187 id = hdac_codec_id(w->devinfo); 2188 2189 caps = hdac_command(sc, 2190 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2191 orig = caps; 2192 2193 HDA_BOOTVERBOSE( 2194 if (caps != orig) 2195 device_printf(sc->dev, 2196 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2197 nid, orig, caps); 2198 ); 2199 2200 return (caps); 2201} 2202 2203static void 2204hdac_widget_pin_parse(struct hdac_widget *w) 2205{ 2206 struct hdac_softc *sc = w->devinfo->codec->sc; 2207 uint32_t config, pincap; 2208 char *devstr, *connstr; 2209 nid_t cad = w->devinfo->codec->cad; 2210 nid_t nid = w->nid; 2211 2212 config = hdac_widget_pin_getconfig(w); 2213 w->wclass.pin.config = config; 2214 2215 pincap = hdac_widget_pin_getcaps(w); 2216 w->wclass.pin.cap = pincap; 2217 2218 w->wclass.pin.ctrl = hdac_command(sc, 2219 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2220 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2221 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2222 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2223 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2224 2225 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2226 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2227 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2228 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2229 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2230 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2231 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2232 w->param.eapdbtl = hdac_command(sc, 2233 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2234 w->param.eapdbtl &= 0x7; 2235 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2236 } else 2237 w->param.eapdbtl = HDAC_INVALID; 2238 2239 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2240 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2241 devstr = "line out"; 2242 break; 2243 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2244 devstr = "speaker"; 2245 break; 2246 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2247 devstr = "headphones out"; 2248 break; 2249 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2250 devstr = "CD"; 2251 break; 2252 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2253 devstr = "SPDIF out"; 2254 break; 2255 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2256 devstr = "digital (other) out"; 2257 break; 2258 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2259 devstr = "modem, line side"; 2260 break; 2261 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2262 devstr = "modem, handset side"; 2263 break; 2264 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2265 devstr = "line in"; 2266 break; 2267 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2268 devstr = "AUX"; 2269 break; 2270 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2271 devstr = "Mic in"; 2272 break; 2273 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2274 devstr = "telephony"; 2275 break; 2276 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2277 devstr = "SPDIF in"; 2278 break; 2279 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2280 devstr = "digital (other) in"; 2281 break; 2282 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2283 devstr = "other"; 2284 break; 2285 default: 2286 devstr = "unknown"; 2287 break; 2288 } 2289 2290 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2291 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2292 connstr = "jack"; 2293 break; 2294 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2295 connstr = "none"; 2296 break; 2297 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2298 connstr = "fixed"; 2299 break; 2300 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2301 connstr = "jack / fixed"; 2302 break; 2303 default: 2304 connstr = "unknown"; 2305 break; 2306 } 2307 2308 strlcat(w->name, ": ", sizeof(w->name)); 2309 strlcat(w->name, devstr, sizeof(w->name)); 2310 strlcat(w->name, " (", sizeof(w->name)); 2311 strlcat(w->name, connstr, sizeof(w->name)); 2312 strlcat(w->name, ")", sizeof(w->name)); 2313} 2314 2315static void 2316hdac_widget_parse(struct hdac_widget *w) 2317{ 2318 struct hdac_softc *sc = w->devinfo->codec->sc; 2319 uint32_t wcap, cap; 2320 char *typestr; 2321 nid_t cad = w->devinfo->codec->cad; 2322 nid_t nid = w->nid; 2323 2324 wcap = hdac_command(sc, 2325 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2326 cad); 2327 w->param.widget_cap = wcap; 2328 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2329 2330 switch (w->type) { 2331 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2332 typestr = "audio output"; 2333 break; 2334 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2335 typestr = "audio input"; 2336 break; 2337 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2338 typestr = "audio mixer"; 2339 break; 2340 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2341 typestr = "audio selector"; 2342 break; 2343 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2344 typestr = "pin"; 2345 break; 2346 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2347 typestr = "power widget"; 2348 break; 2349 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2350 typestr = "volume widget"; 2351 break; 2352 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2353 typestr = "beep widget"; 2354 break; 2355 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2356 typestr = "vendor widget"; 2357 break; 2358 default: 2359 typestr = "unknown type"; 2360 break; 2361 } 2362 2363 strlcpy(w->name, typestr, sizeof(w->name)); 2364 2365 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2366 hdac_command(sc, 2367 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2368 cad); 2369 DELAY(1000); 2370 } 2371 2372 hdac_widget_connection_parse(w); 2373 2374 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2375 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2376 w->param.outamp_cap = 2377 hdac_command(sc, 2378 HDA_CMD_GET_PARAMETER(cad, nid, 2379 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2380 else 2381 w->param.outamp_cap = 2382 w->devinfo->function.audio.outamp_cap; 2383 } else 2384 w->param.outamp_cap = 0; 2385 2386 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2387 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2388 w->param.inamp_cap = 2389 hdac_command(sc, 2390 HDA_CMD_GET_PARAMETER(cad, nid, 2391 HDA_PARAM_INPUT_AMP_CAP), cad); 2392 else 2393 w->param.inamp_cap = 2394 w->devinfo->function.audio.inamp_cap; 2395 } else 2396 w->param.inamp_cap = 0; 2397 2398 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2399 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2400 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2401 cap = hdac_command(sc, 2402 HDA_CMD_GET_PARAMETER(cad, nid, 2403 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2404 w->param.supp_stream_formats = (cap != 0) ? cap : 2405 w->devinfo->function.audio.supp_stream_formats; 2406 cap = hdac_command(sc, 2407 HDA_CMD_GET_PARAMETER(cad, nid, 2408 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2409 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2410 w->devinfo->function.audio.supp_pcm_size_rate; 2411 } else { 2412 w->param.supp_stream_formats = 2413 w->devinfo->function.audio.supp_stream_formats; 2414 w->param.supp_pcm_size_rate = 2415 w->devinfo->function.audio.supp_pcm_size_rate; 2416 } 2417 } else { 2418 w->param.supp_stream_formats = 0; 2419 w->param.supp_pcm_size_rate = 0; 2420 } 2421 2422 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2423 hdac_widget_pin_parse(w); 2424} 2425 2426static struct hdac_widget * 2427hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2428{ 2429 if (devinfo == NULL || devinfo->widget == NULL || 2430 nid < devinfo->startnode || nid >= devinfo->endnode) 2431 return (NULL); 2432 return (&devinfo->widget[nid - devinfo->startnode]); 2433} 2434 2435static __inline int 2436hda_poll_channel(struct hdac_chan *ch) 2437{ 2438 uint32_t sz, delta; 2439 volatile uint32_t ptr; 2440 2441 if (!(ch->flags & HDAC_CHN_RUNNING)) 2442 return (0); 2443 2444 sz = ch->blksz * ch->blkcnt; 2445 if (ch->dmapos != NULL) 2446 ptr = *(ch->dmapos); 2447 else 2448 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2449 ch->off + HDAC_SDLPIB); 2450 ch->ptr = ptr; 2451 ptr %= sz; 2452 ptr &= ~(ch->blksz - 1); 2453 delta = (sz + ptr - ch->prevptr) % sz; 2454 2455 if (delta < ch->blksz) 2456 return (0); 2457 2458 ch->prevptr = ptr; 2459 2460 return (1); 2461} 2462 2463#define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2464 HDAC_CHN_RUNNING) 2465 2466static void 2467hda_poll_callback(void *arg) 2468{ 2469 struct hdac_softc *sc = arg; 2470 uint32_t trigger; 2471 2472 if (sc == NULL) 2473 return; 2474 2475 hdac_lock(sc); 2476 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2477 hdac_unlock(sc); 2478 return; 2479 } 2480 2481 trigger = 0; 2482 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2483 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2484 2485 /* XXX */ 2486 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2487 hda_poll_callback, sc); 2488 2489 hdac_unlock(sc); 2490 2491 if (trigger & HDAC_TRIGGER_PLAY) 2492 chn_intr(sc->play.c); 2493 if (trigger & HDAC_TRIGGER_REC) 2494 chn_intr(sc->rec.c); 2495} 2496 2497static int 2498hdac_rirb_flush(struct hdac_softc *sc) 2499{ 2500 struct hdac_rirb *rirb_base, *rirb; 2501 struct hdac_codec *codec; 2502 struct hdac_command_list *commands; 2503 nid_t cad; 2504 uint32_t resp; 2505 uint8_t rirbwp; 2506 int ret; 2507 2508 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2509 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2510#if 0 2511 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2512 BUS_DMASYNC_POSTREAD); 2513#endif 2514 2515 ret = 0; 2516 2517 while (sc->rirb_rp != rirbwp) { 2518 sc->rirb_rp++; 2519 sc->rirb_rp %= sc->rirb_size; 2520 rirb = &rirb_base[sc->rirb_rp]; 2521 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2522 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2523 sc->codecs[cad] == NULL) 2524 continue; 2525 resp = rirb->response; 2526 codec = sc->codecs[cad]; 2527 commands = codec->commands; 2528 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2529 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2530 ((resp >> 26) & 0xffff); 2531 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2532 } else if (commands != NULL && commands->num_commands > 0 && 2533 codec->responses_received < commands->num_commands) 2534 commands->responses[codec->responses_received++] = 2535 resp; 2536 ret++; 2537 } 2538 2539 return (ret); 2540} 2541 2542static int 2543hdac_unsolq_flush(struct hdac_softc *sc) 2544{ 2545 nid_t cad; 2546 uint32_t tag; 2547 int ret = 0; 2548 2549 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2550 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2551 while (sc->unsolq_rp != sc->unsolq_wp) { 2552 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2553 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2554 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2555 hdac_unsolicited_handler(sc->codecs[cad], tag); 2556 ret++; 2557 } 2558 sc->unsolq_st = HDAC_UNSOLQ_READY; 2559 } 2560 2561 return (ret); 2562} 2563 2564static void 2565hdac_poll_callback(void *arg) 2566{ 2567 struct hdac_softc *sc = arg; 2568 if (sc == NULL) 2569 return; 2570 2571 hdac_lock(sc); 2572 if (sc->polling == 0 || sc->poll_ival == 0) { 2573 hdac_unlock(sc); 2574 return; 2575 } 2576 if (hdac_rirb_flush(sc) != 0) 2577 hdac_unsolq_flush(sc); 2578 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2579 hdac_unlock(sc); 2580} 2581 2582static void 2583hdac_stream_stop(struct hdac_chan *ch) 2584{ 2585 struct hdac_softc *sc = ch->devinfo->codec->sc; 2586 uint32_t ctl; 2587 2588 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2589 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2590 HDAC_SDCTL_RUN); 2591 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2592 2593 ch->flags &= ~HDAC_CHN_RUNNING; 2594 2595 if (sc->polling != 0) { 2596 int pollticks; 2597 2598 if (hda_chan_active(sc) == 0) { 2599 callout_stop(&sc->poll_hda); 2600 sc->poll_ticks = 1; 2601 } else { 2602 if (sc->play.flags & HDAC_CHN_RUNNING) 2603 ch = &sc->play; 2604 else 2605 ch = &sc->rec; 2606 pollticks = ((uint64_t)hz * ch->blksz) / 2607 ((uint64_t)sndbuf_getbps(ch->b) * 2608 sndbuf_getspd(ch->b)); 2609 pollticks >>= 2; 2610 if (pollticks > hz) 2611 pollticks = hz; 2612 if (pollticks < 1) { 2613 HDA_BOOTVERBOSE( 2614 device_printf(sc->dev, 2615 "%s: pollticks=%d < 1 !\n", 2616 __func__, pollticks); 2617 ); 2618 pollticks = 1; 2619 } 2620 if (pollticks > sc->poll_ticks) { 2621 HDA_BOOTVERBOSE( 2622 device_printf(sc->dev, 2623 "%s: pollticks %d -> %d\n", 2624 __func__, sc->poll_ticks, 2625 pollticks); 2626 ); 2627 sc->poll_ticks = pollticks; 2628 callout_reset(&sc->poll_hda, 1, 2629 hda_poll_callback, sc); 2630 } 2631 } 2632 } else { 2633 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2634 ctl &= ~(1 << (ch->off >> 5)); 2635 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2636 } 2637} 2638 2639static void 2640hdac_stream_start(struct hdac_chan *ch) 2641{ 2642 struct hdac_softc *sc = ch->devinfo->codec->sc; 2643 uint32_t ctl; 2644 2645 if (sc->polling != 0) { 2646 int pollticks; 2647 2648 pollticks = ((uint64_t)hz * ch->blksz) / 2649 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2650 pollticks >>= 2; 2651 if (pollticks > hz) 2652 pollticks = hz; 2653 if (pollticks < 1) { 2654 HDA_BOOTVERBOSE( 2655 device_printf(sc->dev, 2656 "%s: pollticks=%d < 1 !\n", 2657 __func__, pollticks); 2658 ); 2659 pollticks = 1; 2660 } 2661 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2662 HDA_BOOTVERBOSE( 2663 if (hda_chan_active(sc) == 0) { 2664 device_printf(sc->dev, 2665 "%s: pollticks=%d\n", 2666 __func__, pollticks); 2667 } else { 2668 device_printf(sc->dev, 2669 "%s: pollticks %d -> %d\n", 2670 __func__, sc->poll_ticks, 2671 pollticks); 2672 } 2673 ); 2674 sc->poll_ticks = pollticks; 2675 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2676 sc); 2677 } 2678 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2679 ctl |= HDAC_SDCTL_RUN; 2680 } else { 2681 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2682 ctl |= 1 << (ch->off >> 5); 2683 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2684 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2685 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2686 HDAC_SDCTL_RUN; 2687 } 2688 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2689 2690 ch->flags |= HDAC_CHN_RUNNING; 2691} 2692 2693static void 2694hdac_stream_reset(struct hdac_chan *ch) 2695{ 2696 struct hdac_softc *sc = ch->devinfo->codec->sc; 2697 int timeout = 1000; 2698 int to = timeout; 2699 uint32_t ctl; 2700 2701 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2702 ctl |= HDAC_SDCTL_SRST; 2703 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2704 do { 2705 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2706 if (ctl & HDAC_SDCTL_SRST) 2707 break; 2708 DELAY(10); 2709 } while (--to); 2710 if (!(ctl & HDAC_SDCTL_SRST)) { 2711 device_printf(sc->dev, "timeout in reset\n"); 2712 } 2713 ctl &= ~HDAC_SDCTL_SRST; 2714 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2715 to = timeout; 2716 do { 2717 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2718 if (!(ctl & HDAC_SDCTL_SRST)) 2719 break; 2720 DELAY(10); 2721 } while (--to); 2722 if (ctl & HDAC_SDCTL_SRST) 2723 device_printf(sc->dev, "can't reset!\n"); 2724} 2725 2726static void 2727hdac_stream_setid(struct hdac_chan *ch) 2728{ 2729 struct hdac_softc *sc = ch->devinfo->codec->sc; 2730 uint32_t ctl; 2731 2732 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2733 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2734 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2735 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2736} 2737 2738static void 2739hdac_bdl_setup(struct hdac_chan *ch) 2740{ 2741 struct hdac_softc *sc = ch->devinfo->codec->sc; 2742 struct hdac_bdle *bdle; 2743 uint64_t addr; 2744 uint32_t blksz, blkcnt; 2745 int i; 2746 2747 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2748 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2749 2750 if (sc->polling != 0) { 2751 blksz = ch->blksz * ch->blkcnt; 2752 blkcnt = 1; 2753 } else { 2754 blksz = ch->blksz; 2755 blkcnt = ch->blkcnt; 2756 } 2757 2758 for (i = 0; i < blkcnt; i++, bdle++) { 2759 bdle->addrl = (uint32_t)addr; 2760 bdle->addrh = (uint32_t)(addr >> 32); 2761 bdle->len = blksz; 2762 bdle->ioc = 1 ^ sc->polling; 2763 addr += blksz; 2764 } 2765 2766 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2767 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2768 addr = ch->bdl_dma.dma_paddr; 2769 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2770 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2771 if (ch->dmapos != NULL && 2772 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2773 addr = sc->pos_dma.dma_paddr; 2774 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2775 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2776 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2777 } 2778} 2779 2780static int 2781hdac_bdl_alloc(struct hdac_chan *ch) 2782{ 2783 struct hdac_softc *sc = ch->devinfo->codec->sc; 2784 int rc; 2785 2786 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2787 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2788 if (rc) { 2789 device_printf(sc->dev, "can't alloc bdl\n"); 2790 return (rc); 2791 } 2792 2793 return (0); 2794} 2795 2796static void 2797hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2798 int index, int lmute, int rmute, 2799 int left, int right, int dir) 2800{ 2801 uint16_t v = 0; 2802 2803 if (sc == NULL) 2804 return; 2805 2806 if (left != right || lmute != rmute) { 2807 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2808 (lmute << 7) | left; 2809 hdac_command(sc, 2810 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2811 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2812 (rmute << 7) | right; 2813 } else 2814 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2815 (lmute << 7) | left; 2816 2817 hdac_command(sc, 2818 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2819} 2820 2821static void 2822hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2823 int left, int right) 2824{ 2825 struct hdac_softc *sc; 2826 nid_t nid, cad; 2827 int lmute, rmute; 2828 2829 if (ctl == NULL || ctl->widget == NULL || 2830 ctl->widget->devinfo == NULL || 2831 ctl->widget->devinfo->codec == NULL || 2832 ctl->widget->devinfo->codec->sc == NULL) 2833 return; 2834 2835 sc = ctl->widget->devinfo->codec->sc; 2836 cad = ctl->widget->devinfo->codec->cad; 2837 nid = ctl->widget->nid; 2838 2839 if (mute == HDA_AMP_MUTE_DEFAULT) { 2840 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2841 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2842 } else { 2843 lmute = HDA_AMP_LEFT_MUTED(mute); 2844 rmute = HDA_AMP_RIGHT_MUTED(mute); 2845 } 2846 2847 if (ctl->dir & HDA_CTL_OUT) 2848 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2849 lmute, rmute, left, right, 0); 2850 if (ctl->dir & HDA_CTL_IN) 2851 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2852 lmute, rmute, left, right, 1); 2853 ctl->left = left; 2854 ctl->right = right; 2855} 2856 2857static void 2858hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2859{ 2860 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2861 return; 2862 hdac_command(w->devinfo->codec->sc, 2863 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2864 w->nid, index), w->devinfo->codec->cad); 2865 w->selconn = index; 2866} 2867 2868 2869/**************************************************************************** 2870 * uint32_t hdac_command_sendone_internal 2871 * 2872 * Wrapper function that sends only one command to a given codec 2873 ****************************************************************************/ 2874static uint32_t 2875hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2876{ 2877 struct hdac_command_list cl; 2878 uint32_t response = HDAC_INVALID; 2879 2880 if (!hdac_lockowned(sc)) 2881 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2882 cl.num_commands = 1; 2883 cl.verbs = &verb; 2884 cl.responses = &response; 2885 2886 hdac_command_send_internal(sc, &cl, cad); 2887 2888 return (response); 2889} 2890 2891/**************************************************************************** 2892 * hdac_command_send_internal 2893 * 2894 * Send a command list to the codec via the corb. We queue as much verbs as 2895 * we can and msleep on the codec. When the interrupt get the responses 2896 * back from the rirb, it will wake us up so we can queue the remaining verbs 2897 * if any. 2898 ****************************************************************************/ 2899static void 2900hdac_command_send_internal(struct hdac_softc *sc, 2901 struct hdac_command_list *commands, nid_t cad) 2902{ 2903 struct hdac_codec *codec; 2904 int corbrp; 2905 uint32_t *corb; 2906 int timeout; 2907 int retry = 10; 2908 struct hdac_rirb *rirb_base; 2909 2910 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2911 commands->num_commands < 1) 2912 return; 2913 2914 codec = sc->codecs[cad]; 2915 codec->commands = commands; 2916 codec->responses_received = 0; 2917 codec->verbs_sent = 0; 2918 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2919 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2920 2921 do { 2922 if (codec->verbs_sent != commands->num_commands) { 2923 /* Queue as many verbs as possible */ 2924 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2925#if 0 2926 bus_dmamap_sync(sc->corb_dma.dma_tag, 2927 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2928#endif 2929 while (codec->verbs_sent != commands->num_commands && 2930 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2931 sc->corb_wp++; 2932 sc->corb_wp %= sc->corb_size; 2933 corb[sc->corb_wp] = 2934 commands->verbs[codec->verbs_sent++]; 2935 } 2936 2937 /* Send the verbs to the codecs */ 2938#if 0 2939 bus_dmamap_sync(sc->corb_dma.dma_tag, 2940 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2941#endif 2942 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2943 } 2944 2945 timeout = 1000; 2946 while (hdac_rirb_flush(sc) == 0 && --timeout) 2947 DELAY(10); 2948 } while ((codec->verbs_sent != commands->num_commands || 2949 codec->responses_received != commands->num_commands) && --retry); 2950 2951 if (retry == 0) 2952 device_printf(sc->dev, 2953 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2954 __func__, commands->num_commands, codec->verbs_sent, 2955 codec->responses_received); 2956 2957 codec->commands = NULL; 2958 codec->responses_received = 0; 2959 codec->verbs_sent = 0; 2960 2961 hdac_unsolq_flush(sc); 2962} 2963 2964 2965/**************************************************************************** 2966 * Device Methods 2967 ****************************************************************************/ 2968 2969/**************************************************************************** 2970 * int hdac_probe(device_t) 2971 * 2972 * Probe for the presence of an hdac. If none is found, check for a generic 2973 * match using the subclass of the device. 2974 ****************************************************************************/ 2975static int 2976hdac_probe(device_t dev) 2977{ 2978 int i, result; 2979 uint32_t model; 2980 uint16_t class, subclass; 2981 char desc[64]; 2982 2983 model = (uint32_t)pci_get_device(dev) << 16; 2984 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2985 class = pci_get_class(dev); 2986 subclass = pci_get_subclass(dev); 2987 2988 bzero(desc, sizeof(desc)); 2989 result = ENXIO; 2990 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2991 if (hdac_devices[i].model == model) { 2992 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2993 result = BUS_PROBE_DEFAULT; 2994 break; 2995 } 2996 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2997 class == PCIC_MULTIMEDIA && 2998 subclass == PCIS_MULTIMEDIA_HDA) { 2999 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3000 result = BUS_PROBE_GENERIC; 3001 break; 3002 } 3003 } 3004 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3005 subclass == PCIS_MULTIMEDIA_HDA) { 3006 strlcpy(desc, "Generic", sizeof(desc)); 3007 result = BUS_PROBE_GENERIC; 3008 } 3009 if (result != ENXIO) { 3010 strlcat(desc, " High Definition Audio Controller", 3011 sizeof(desc)); 3012 device_set_desc_copy(dev, desc); 3013 } 3014 3015 return (result); 3016} 3017 3018static void * 3019hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3020 struct pcm_channel *c, int dir) 3021{ 3022 struct hdac_devinfo *devinfo = data; 3023 struct hdac_softc *sc = devinfo->codec->sc; 3024 struct hdac_chan *ch; 3025 3026 hdac_lock(sc); 3027 if (dir == PCMDIR_PLAY) { 3028 ch = &sc->play; 3029 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3030 devinfo->function.audio.playcnt++; 3031 } else { 3032 ch = &sc->rec; 3033 ch->off = devinfo->function.audio.reccnt << 5; 3034 devinfo->function.audio.reccnt++; 3035 } 3036 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3037 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3038 ch->pcmrates[0] = 48000; 3039 ch->pcmrates[1] = 0; 3040 } 3041 if (sc->pos_dma.dma_vaddr != NULL) 3042 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3043 (sc->streamcnt * 8)); 3044 else 3045 ch->dmapos = NULL; 3046 ch->sid = ++sc->streamcnt; 3047 ch->dir = dir; 3048 ch->b = b; 3049 ch->c = c; 3050 ch->devinfo = devinfo; 3051 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3052 ch->blkcnt = sc->chan_blkcnt; 3053 hdac_unlock(sc); 3054 3055 if (hdac_bdl_alloc(ch) != 0) { 3056 ch->blkcnt = 0; 3057 return (NULL); 3058 } 3059 3060 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3061 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3062 sc->chan_size) != 0) 3063 return (NULL); 3064 3065 return (ch); 3066} 3067 3068static int 3069hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3070{ 3071 struct hdac_chan *ch = data; 3072 int i; 3073 3074 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3075 if (format == ch->caps.fmtlist[i]) { 3076 ch->fmt = format; 3077 return (0); 3078 } 3079 } 3080 3081 return (EINVAL); 3082} 3083 3084static int 3085hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3086{ 3087 struct hdac_chan *ch = data; 3088 uint32_t spd = 0, threshold; 3089 int i; 3090 3091 for (i = 0; ch->pcmrates[i] != 0; i++) { 3092 spd = ch->pcmrates[i]; 3093 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3094 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3095 if (speed < threshold) 3096 break; 3097 } 3098 3099 if (spd == 0) /* impossible */ 3100 ch->spd = 48000; 3101 else 3102 ch->spd = spd; 3103 3104 return (ch->spd); 3105} 3106 3107static void 3108hdac_stream_setup(struct hdac_chan *ch) 3109{ 3110 struct hdac_softc *sc = ch->devinfo->codec->sc; 3111 struct hdac_widget *w; 3112 int i, chn, totalchn; 3113 nid_t cad = ch->devinfo->codec->cad; 3114 uint16_t fmt; 3115 3116 fmt = 0; 3117 if (ch->fmt & AFMT_S16_LE) 3118 fmt |= ch->bit16 << 4; 3119 else if (ch->fmt & AFMT_S32_LE) 3120 fmt |= ch->bit32 << 4; 3121 else 3122 fmt |= 1 << 4; 3123 3124 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3125 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3126 fmt |= hda_rate_tab[i].base; 3127 fmt |= hda_rate_tab[i].mul; 3128 fmt |= hda_rate_tab[i].div; 3129 break; 3130 } 3131 } 3132 3133 if (ch->fmt & AFMT_STEREO) { 3134 fmt |= 1; 3135 totalchn = 2; 3136 } else 3137 totalchn = 1; 3138 3139 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3140 3141 chn = 0; 3142 for (i = 0; ch->io[i] != -1; i++) { 3143 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3144 if (w == NULL) 3145 continue; 3146 HDA_BOOTVERBOSE( 3147 device_printf(sc->dev, 3148 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3149 "fmt=0x%08x\n", 3150 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3151 ch->io[i], fmt); 3152 ); 3153 hdac_command(sc, 3154 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3155 hdac_command(sc, 3156 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3157 (chn < totalchn) ? ((ch->sid << 4) | chn) : 0), cad); 3158 chn += 3159 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3160 2 : 1; 3161 } 3162} 3163 3164static int 3165hdac_channel_setfragments(kobj_t obj, void *data, 3166 uint32_t blksz, uint32_t blkcnt) 3167{ 3168 struct hdac_chan *ch = data; 3169 struct hdac_softc *sc = ch->devinfo->codec->sc; 3170 3171 blksz &= HDA_BLK_ALIGN; 3172 3173 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3174 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3175 if (blksz < HDA_BLK_MIN) 3176 blksz = HDA_BLK_MIN; 3177 if (blkcnt > HDA_BDL_MAX) 3178 blkcnt = HDA_BDL_MAX; 3179 if (blkcnt < HDA_BDL_MIN) 3180 blkcnt = HDA_BDL_MIN; 3181 3182 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3183 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3184 blkcnt >>= 1; 3185 else if ((blksz >> 1) >= HDA_BLK_MIN) 3186 blksz >>= 1; 3187 else 3188 break; 3189 } 3190 3191 if ((sndbuf_getblksz(ch->b) != blksz || 3192 sndbuf_getblkcnt(ch->b) != blkcnt) && 3193 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3194 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3195 __func__, blksz, blkcnt); 3196 3197 ch->blksz = sndbuf_getblksz(ch->b); 3198 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3199 3200 return (1); 3201} 3202 3203static int 3204hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3205{ 3206 struct hdac_chan *ch = data; 3207 struct hdac_softc *sc = ch->devinfo->codec->sc; 3208 3209 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3210 3211 return (ch->blksz); 3212} 3213 3214static void 3215hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3216{ 3217 struct hdac_devinfo *devinfo = ch->devinfo; 3218 nid_t cad = devinfo->codec->cad; 3219 int i; 3220 3221 hdac_stream_stop(ch); 3222 3223 for (i = 0; ch->io[i] != -1; i++) { 3224 hdac_command(sc, 3225 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3226 0), cad); 3227 } 3228} 3229 3230static void 3231hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3232{ 3233 ch->ptr = 0; 3234 ch->prevptr = 0; 3235 hdac_stream_stop(ch); 3236 hdac_stream_reset(ch); 3237 hdac_bdl_setup(ch); 3238 hdac_stream_setid(ch); 3239 hdac_stream_setup(ch); 3240 hdac_stream_start(ch); 3241} 3242 3243static int 3244hdac_channel_trigger(kobj_t obj, void *data, int go) 3245{ 3246 struct hdac_chan *ch = data; 3247 struct hdac_softc *sc = ch->devinfo->codec->sc; 3248 3249 if (!PCMTRIG_COMMON(go)) 3250 return (0); 3251 3252 hdac_lock(sc); 3253 switch (go) { 3254 case PCMTRIG_START: 3255 hdac_channel_start(sc, ch); 3256 break; 3257 case PCMTRIG_STOP: 3258 case PCMTRIG_ABORT: 3259 hdac_channel_stop(sc, ch); 3260 break; 3261 default: 3262 break; 3263 } 3264 hdac_unlock(sc); 3265 3266 return (0); 3267} 3268 3269static int 3270hdac_channel_getptr(kobj_t obj, void *data) 3271{ 3272 struct hdac_chan *ch = data; 3273 struct hdac_softc *sc = ch->devinfo->codec->sc; 3274 uint32_t ptr; 3275 3276 hdac_lock(sc); 3277 if (sc->polling != 0) 3278 ptr = ch->ptr; 3279 else if (ch->dmapos != NULL) 3280 ptr = *(ch->dmapos); 3281 else 3282 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3283 hdac_unlock(sc); 3284 3285 /* 3286 * Round to available space and force 128 bytes aligment. 3287 */ 3288 ptr %= ch->blksz * ch->blkcnt; 3289 ptr &= HDA_BLK_ALIGN; 3290 3291 return (ptr); 3292} 3293 3294static struct pcmchan_caps * 3295hdac_channel_getcaps(kobj_t obj, void *data) 3296{ 3297 return (&((struct hdac_chan *)data)->caps); 3298} 3299 3300static kobj_method_t hdac_channel_methods[] = { 3301 KOBJMETHOD(channel_init, hdac_channel_init), 3302 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3303 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3304 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3305 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3306 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3307 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3308 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3309 { 0, 0 } 3310}; 3311CHANNEL_DECLARE(hdac_channel); 3312 3313static void 3314hdac_jack_poll_callback(void *arg) 3315{ 3316 struct hdac_devinfo *devinfo = arg; 3317 struct hdac_softc *sc; 3318 3319 if (devinfo == NULL || devinfo->codec == NULL || 3320 devinfo->codec->sc == NULL) 3321 return; 3322 sc = devinfo->codec->sc; 3323 hdac_lock(sc); 3324 if (sc->poll_ival == 0) { 3325 hdac_unlock(sc); 3326 return; 3327 } 3328 hdac_hp_switch_handler(devinfo); 3329 callout_reset(&sc->poll_jack, sc->poll_ival, 3330 hdac_jack_poll_callback, devinfo); 3331 hdac_unlock(sc); 3332} 3333 3334static int 3335hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3336{ 3337 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3338 struct hdac_softc *sc = devinfo->codec->sc; 3339 struct hdac_widget *w, *cw; 3340 struct hdac_audio_ctl *ctl; 3341 uint32_t mask, recmask, id; 3342 int i, j, softpcmvol; 3343 nid_t cad; 3344 3345 hdac_lock(sc); 3346 3347 mask = 0; 3348 recmask = 0; 3349 3350 id = hdac_codec_id(devinfo); 3351 cad = devinfo->codec->cad; 3352 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3353 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3354 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3355 continue; 3356 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3357 if (w == NULL || w->enable == 0 || w->type != 3358 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3359 continue; 3360 if (hdac_hp_switch[i].polling != 0) 3361 callout_reset(&sc->poll_jack, 1, 3362 hdac_jack_poll_callback, devinfo); 3363 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3364 hdac_command(sc, 3365 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3366 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3367 HDAC_UNSOLTAG_EVENT_HP), cad); 3368 else 3369 continue; 3370 hdac_hp_switch_handler(devinfo); 3371 HDA_BOOTVERBOSE( 3372 device_printf(sc->dev, 3373 "HDA_DEBUG: Enabling headphone/speaker " 3374 "audio routing switching:\n"); 3375 device_printf(sc->dev, 3376 "HDA_DEBUG: \tindex=%d nid=%d " 3377 "pci_subvendor=0x%08x " 3378 "codec=0x%08x [%s]\n", 3379 i, w->nid, sc->pci_subvendor, id, 3380 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3381 "UNSOL"); 3382 ); 3383 break; 3384 } 3385 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3386 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3387 sc->pci_subvendor) && 3388 hdac_eapd_switch[i].id == id)) 3389 continue; 3390 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3391 if (w == NULL || w->enable == 0) 3392 break; 3393 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3394 w->param.eapdbtl == HDAC_INVALID) 3395 break; 3396 mask |= SOUND_MASK_OGAIN; 3397 break; 3398 } 3399 3400 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3401 w = hdac_widget_get(devinfo, i); 3402 if (w == NULL || w->enable == 0) 3403 continue; 3404 mask |= w->ctlflags; 3405 if (!(w->pflags & HDA_ADC_RECSEL)) 3406 continue; 3407 for (j = 0; j < w->nconns; j++) { 3408 cw = hdac_widget_get(devinfo, w->conns[j]); 3409 if (cw == NULL || cw->enable == 0) 3410 continue; 3411 recmask |= cw->ctlflags; 3412 } 3413 } 3414 3415 if (!(mask & SOUND_MASK_PCM)) { 3416 softpcmvol = 1; 3417 mask |= SOUND_MASK_PCM; 3418 } else 3419 softpcmvol = (devinfo->function.audio.quirks & 3420 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3421 3422 i = 0; 3423 ctl = NULL; 3424 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3425 if (ctl->widget == NULL || ctl->enable == 0) 3426 continue; 3427 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3428 continue; 3429 if (ctl->step > 0) 3430 break; 3431 } 3432 3433 if (softpcmvol == 1 || ctl == NULL) { 3434 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3435 HDA_BOOTVERBOSE( 3436 device_printf(sc->dev, 3437 "HDA_DEBUG: %s Soft PCM volume\n", 3438 (softpcmvol == 1) ? 3439 "Forcing" : "Enabling"); 3440 ); 3441 i = 0; 3442 /* 3443 * XXX Temporary quirk for STAC9220, until the parser 3444 * become smarter. 3445 */ 3446 if (id == HDA_CODEC_STAC9220) { 3447 mask |= SOUND_MASK_VOLUME; 3448 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3449 NULL) { 3450 if (ctl->widget == NULL || ctl->enable == 0) 3451 continue; 3452 if (ctl->widget->nid == 11 && ctl->index == 0) { 3453 ctl->ossmask = SOUND_MASK_VOLUME; 3454 ctl->ossval = 100 | (100 << 8); 3455 } else 3456 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3457 } 3458 } else if (id == HDA_CODEC_STAC9221) { 3459 mask |= SOUND_MASK_VOLUME; 3460 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3461 NULL) { 3462 if (ctl->widget == NULL) 3463 continue; 3464 if (ctl->widget->type == 3465 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3466 ctl->index == 0 && (ctl->widget->nid == 2 || 3467 ctl->widget->enable != 0)) { 3468 ctl->enable = 1; 3469 ctl->ossmask = SOUND_MASK_VOLUME; 3470 ctl->ossval = 100 | (100 << 8); 3471 } else if (ctl->enable == 0) 3472 continue; 3473 else 3474 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3475 } 3476 } else { 3477 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3478 SOUND_MASK_PCM); 3479 if (!(mask & SOUND_MASK_VOLUME)) 3480 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3481 SOUND_MIXER_NONE); 3482 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3483 NULL) { 3484 if (ctl->widget == NULL || ctl->enable == 0) 3485 continue; 3486 if (!HDA_FLAG_MATCH(ctl->ossmask, 3487 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3488 continue; 3489 if (!(ctl->mute == 1 && ctl->step == 0)) 3490 ctl->enable = 0; 3491 } 3492 } 3493 } 3494 3495 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3496 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3497 SOUND_MASK_OGAIN); 3498 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3499 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3500 3501 mix_setrecdevs(m, recmask); 3502 mix_setdevs(m, mask); 3503 3504 hdac_unlock(sc); 3505 3506 return (0); 3507} 3508 3509static int 3510hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3511 unsigned left, unsigned right) 3512{ 3513 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3514 struct hdac_softc *sc = devinfo->codec->sc; 3515 struct hdac_widget *w; 3516 struct hdac_audio_ctl *ctl; 3517 uint32_t id, mute; 3518 int lvol, rvol, mlvol, mrvol; 3519 int i = 0; 3520 3521 hdac_lock(sc); 3522 if (dev == SOUND_MIXER_OGAIN) { 3523 uint32_t orig; 3524 /*if (left != right || !(left == 0 || left == 1)) { 3525 hdac_unlock(sc); 3526 return (-1); 3527 }*/ 3528 id = hdac_codec_id(devinfo); 3529 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3530 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3531 sc->pci_subvendor) && 3532 hdac_eapd_switch[i].id == id) 3533 break; 3534 } 3535 if (i >= HDAC_EAPD_SWITCH_LEN) { 3536 hdac_unlock(sc); 3537 return (-1); 3538 } 3539 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3540 if (w == NULL || 3541 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3542 w->param.eapdbtl == HDAC_INVALID) { 3543 hdac_unlock(sc); 3544 return (-1); 3545 } 3546 orig = w->param.eapdbtl; 3547 if (left == 0) 3548 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3549 else 3550 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3551 if (orig != w->param.eapdbtl) { 3552 uint32_t val; 3553 3554 if (hdac_eapd_switch[i].hp_switch != 0) 3555 hdac_hp_switch_handler(devinfo); 3556 val = w->param.eapdbtl; 3557 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3558 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3559 hdac_command(sc, 3560 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3561 w->nid, val), devinfo->codec->cad); 3562 } 3563 hdac_unlock(sc); 3564 return (left | (left << 8)); 3565 } 3566 if (dev == SOUND_MIXER_VOLUME) 3567 devinfo->function.audio.mvol = left | (right << 8); 3568 3569 mlvol = devinfo->function.audio.mvol & 0x7f; 3570 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3571 lvol = 0; 3572 rvol = 0; 3573 3574 i = 0; 3575 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3576 if (ctl->widget == NULL || ctl->enable == 0 || 3577 !(ctl->ossmask & (1 << dev))) 3578 continue; 3579 switch (dev) { 3580 case SOUND_MIXER_VOLUME: 3581 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3582 lvol = (lvol * ctl->step) / 100; 3583 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3584 rvol = (rvol * ctl->step) / 100; 3585 break; 3586 default: 3587 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3588 lvol = (left * mlvol) / 100; 3589 lvol = (lvol * ctl->step) / 100; 3590 rvol = (right * mrvol) / 100; 3591 rvol = (rvol * ctl->step) / 100; 3592 } else { 3593 lvol = (left * ctl->step) / 100; 3594 rvol = (right * ctl->step) / 100; 3595 } 3596 ctl->ossval = left | (right << 8); 3597 break; 3598 } 3599 mute = 0; 3600 if (ctl->step < 1) { 3601 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3602 (ctl->muted & HDA_AMP_MUTE_LEFT); 3603 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3604 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3605 } else { 3606 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3607 (ctl->muted & HDA_AMP_MUTE_LEFT); 3608 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3609 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3610 } 3611 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3612 } 3613 hdac_unlock(sc); 3614 3615 return (left | (right << 8)); 3616} 3617 3618static int 3619hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3620{ 3621 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3622 struct hdac_widget *w, *cw; 3623 struct hdac_softc *sc = devinfo->codec->sc; 3624 uint32_t ret = src, target; 3625 int i, j; 3626 3627 target = 0; 3628 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3629 if (src & (1 << i)) { 3630 target = 1 << i; 3631 break; 3632 } 3633 } 3634 3635 hdac_lock(sc); 3636 3637 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3638 w = hdac_widget_get(devinfo, i); 3639 if (w == NULL || w->enable == 0) 3640 continue; 3641 if (!(w->pflags & HDA_ADC_RECSEL)) 3642 continue; 3643 for (j = 0; j < w->nconns; j++) { 3644 cw = hdac_widget_get(devinfo, w->conns[j]); 3645 if (cw == NULL || cw->enable == 0) 3646 continue; 3647 if ((target == SOUND_MASK_VOLUME && 3648 cw->type != 3649 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3650 (target != SOUND_MASK_VOLUME && 3651 cw->type == 3652 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3653 continue; 3654 if (cw->ctlflags & target) { 3655 if (!(w->pflags & HDA_ADC_LOCKED)) 3656 hdac_widget_connection_select(w, j); 3657 ret = target; 3658 j += w->nconns; 3659 } 3660 } 3661 } 3662 3663 hdac_unlock(sc); 3664 3665 return (ret); 3666} 3667 3668static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3669 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3670 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3671 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3672 { 0, 0 } 3673}; 3674MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3675 3676static void 3677hdac_unsolq_task(void *context, int pending) 3678{ 3679 struct hdac_softc *sc; 3680 3681 sc = (struct hdac_softc *)context; 3682 3683 hdac_lock(sc); 3684 hdac_unsolq_flush(sc); 3685 hdac_unlock(sc); 3686} 3687 3688/**************************************************************************** 3689 * int hdac_attach(device_t) 3690 * 3691 * Attach the device into the kernel. Interrupts usually won't be enabled 3692 * when this function is called. Setup everything that doesn't require 3693 * interrupts and defer probing of codecs until interrupts are enabled. 3694 ****************************************************************************/ 3695static int 3696hdac_attach(device_t dev) 3697{ 3698 struct hdac_softc *sc; 3699 int result; 3700 int i; 3701 uint16_t vendor; 3702 uint8_t v; 3703 3704 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3705 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3706 sc->dev = dev; 3707 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3708 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3709 vendor = pci_get_vendor(dev); 3710 3711 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3712 /* Screw nx6325 - subdevice/subvendor swapped */ 3713 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3714 } 3715 3716 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3717 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3718 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3719 3720 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3721 3722 sc->poll_ticks = 1; 3723 sc->poll_ival = HDAC_POLL_INTERVAL; 3724 if (resource_int_value(device_get_name(dev), 3725 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3726 sc->polling = 1; 3727 else 3728 sc->polling = 0; 3729 3730 sc->chan_size = pcm_getbuffersize(dev, 3731 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3732 3733 if (resource_int_value(device_get_name(dev), 3734 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3735 i &= HDA_BLK_ALIGN; 3736 if (i < HDA_BLK_MIN) 3737 i = HDA_BLK_MIN; 3738 sc->chan_blkcnt = sc->chan_size / i; 3739 i = 0; 3740 while (sc->chan_blkcnt >> i) 3741 i++; 3742 sc->chan_blkcnt = 1 << (i - 1); 3743 if (sc->chan_blkcnt < HDA_BDL_MIN) 3744 sc->chan_blkcnt = HDA_BDL_MIN; 3745 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3746 sc->chan_blkcnt = HDA_BDL_MAX; 3747 } else 3748 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3749 3750 result = bus_dma_tag_create(NULL, /* parent */ 3751 HDAC_DMA_ALIGNMENT, /* alignment */ 3752 0, /* boundary */ 3753 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3754 BUS_SPACE_MAXADDR, /* highaddr */ 3755 NULL, /* filtfunc */ 3756 NULL, /* fistfuncarg */ 3757 sc->chan_size, /* maxsize */ 3758 1, /* nsegments */ 3759 sc->chan_size, /* maxsegsz */ 3760 0, /* flags */ 3761 NULL, /* lockfunc */ 3762 NULL, /* lockfuncarg */ 3763 &sc->chan_dmat); /* dmat */ 3764 if (result != 0) { 3765 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3766 __func__, result); 3767 snd_mtxfree(sc->lock); 3768 free(sc, M_DEVBUF); 3769 return (ENXIO); 3770 } 3771 3772 3773 sc->hdabus = NULL; 3774 for (i = 0; i < HDAC_CODEC_MAX; i++) 3775 sc->codecs[i] = NULL; 3776 3777 pci_enable_busmaster(dev); 3778 3779 if (vendor == INTEL_VENDORID) { 3780 /* TCSEL -> TC0 */ 3781 v = pci_read_config(dev, 0x44, 1); 3782 pci_write_config(dev, 0x44, v & 0xf8, 1); 3783 HDA_BOOTVERBOSE( 3784 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3785 pci_read_config(dev, 0x44, 1)); 3786 ); 3787 } 3788 3789#if __FreeBSD_version >= 602106 3790 if (resource_int_value(device_get_name(dev), 3791 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3792 pci_msi_count(dev) == 1) 3793 sc->flags |= HDAC_F_MSI; 3794 else 3795#endif 3796 sc->flags &= ~HDAC_F_MSI; 3797 3798#if defined(__i386__) || defined(__amd64__) 3799 sc->flags |= HDAC_F_DMA_NOCACHE; 3800 3801 if (resource_int_value(device_get_name(dev), 3802 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3803#else 3804 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3805#endif 3806 /* 3807 * Try to enable PCIe snoop to avoid messing around with 3808 * uncacheable DMA attribute. Since PCIe snoop register 3809 * config is pretty much vendor specific, there are no 3810 * general solutions on how to enable it, forcing us (even 3811 * Microsoft) to enable uncacheable or write combined DMA 3812 * by default. 3813 * 3814 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3815 */ 3816 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3817 if (hdac_pcie_snoop[i].vendor != vendor) 3818 continue; 3819 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3820 if (hdac_pcie_snoop[i].reg == 0x00) 3821 break; 3822 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3823 if ((v & hdac_pcie_snoop[i].enable) == 3824 hdac_pcie_snoop[i].enable) 3825 break; 3826 v &= hdac_pcie_snoop[i].mask; 3827 v |= hdac_pcie_snoop[i].enable; 3828 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3829 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3830 if ((v & hdac_pcie_snoop[i].enable) != 3831 hdac_pcie_snoop[i].enable) { 3832 HDA_BOOTVERBOSE( 3833 device_printf(dev, 3834 "WARNING: Failed to enable PCIe " 3835 "snoop!\n"); 3836 ); 3837#if defined(__i386__) || defined(__amd64__) 3838 sc->flags |= HDAC_F_DMA_NOCACHE; 3839#endif 3840 } 3841 break; 3842 } 3843#if defined(__i386__) || defined(__amd64__) 3844 } 3845#endif 3846 3847 HDA_BOOTVERBOSE( 3848 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3849 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3850 "Uncacheable" : "PCIe snoop", vendor); 3851 ); 3852 3853 /* Allocate resources */ 3854 result = hdac_mem_alloc(sc); 3855 if (result != 0) 3856 goto hdac_attach_fail; 3857 result = hdac_irq_alloc(sc); 3858 if (result != 0) 3859 goto hdac_attach_fail; 3860 3861 /* Get Capabilities */ 3862 result = hdac_get_capabilities(sc); 3863 if (result != 0) 3864 goto hdac_attach_fail; 3865 3866 /* Allocate CORB and RIRB dma memory */ 3867 result = hdac_dma_alloc(sc, &sc->corb_dma, 3868 sc->corb_size * sizeof(uint32_t)); 3869 if (result != 0) 3870 goto hdac_attach_fail; 3871 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3872 sc->rirb_size * sizeof(struct hdac_rirb)); 3873 if (result != 0) 3874 goto hdac_attach_fail; 3875 3876 /* Quiesce everything */ 3877 hdac_reset(sc); 3878 3879 /* Initialize the CORB and RIRB */ 3880 hdac_corb_init(sc); 3881 hdac_rirb_init(sc); 3882 3883 /* Defer remaining of initialization until interrupts are enabled */ 3884 sc->intrhook.ich_func = hdac_attach2; 3885 sc->intrhook.ich_arg = (void *)sc; 3886 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3887 sc->intrhook.ich_func = NULL; 3888 hdac_attach2((void *)sc); 3889 } 3890 3891 return (0); 3892 3893hdac_attach_fail: 3894 hdac_irq_free(sc); 3895 hdac_dma_free(sc, &sc->rirb_dma); 3896 hdac_dma_free(sc, &sc->corb_dma); 3897 hdac_mem_free(sc); 3898 snd_mtxfree(sc->lock); 3899 free(sc, M_DEVBUF); 3900 3901 return (ENXIO); 3902} 3903 3904static void 3905hdac_audio_parse(struct hdac_devinfo *devinfo) 3906{ 3907 struct hdac_softc *sc = devinfo->codec->sc; 3908 struct hdac_widget *w; 3909 uint32_t res; 3910 int i; 3911 nid_t cad, nid; 3912 3913 cad = devinfo->codec->cad; 3914 nid = devinfo->nid; 3915 3916 hdac_command(sc, 3917 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3918 3919 DELAY(100); 3920 3921 res = hdac_command(sc, 3922 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3923 3924 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3925 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3926 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3927 3928 res = hdac_command(sc, 3929 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3930 devinfo->function.audio.gpio = res; 3931 3932 HDA_BOOTVERBOSE( 3933 device_printf(sc->dev, " Vendor: 0x%08x\n", 3934 devinfo->vendor_id); 3935 device_printf(sc->dev, " Device: 0x%08x\n", 3936 devinfo->device_id); 3937 device_printf(sc->dev, " Revision: 0x%08x\n", 3938 devinfo->revision_id); 3939 device_printf(sc->dev, " Stepping: 0x%08x\n", 3940 devinfo->stepping_id); 3941 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3942 sc->pci_subvendor); 3943 device_printf(sc->dev, " Nodes: start=%d " 3944 "endnode=%d total=%d\n", 3945 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3946 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3947 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3948 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3949 sc->num_iss, sc->num_oss, sc->num_bss); 3950 device_printf(sc->dev, " GPIO: 0x%08x\n", 3951 devinfo->function.audio.gpio); 3952 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3953 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3954 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3955 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3956 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3957 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3958 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3959 ); 3960 3961 res = hdac_command(sc, 3962 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3963 cad); 3964 devinfo->function.audio.supp_stream_formats = res; 3965 3966 res = hdac_command(sc, 3967 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3968 cad); 3969 devinfo->function.audio.supp_pcm_size_rate = res; 3970 3971 res = hdac_command(sc, 3972 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3973 cad); 3974 devinfo->function.audio.outamp_cap = res; 3975 3976 res = hdac_command(sc, 3977 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3978 cad); 3979 devinfo->function.audio.inamp_cap = res; 3980 3981 if (devinfo->nodecnt > 0) 3982 devinfo->widget = (struct hdac_widget *)malloc( 3983 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3984 M_NOWAIT | M_ZERO); 3985 else 3986 devinfo->widget = NULL; 3987 3988 if (devinfo->widget == NULL) { 3989 device_printf(sc->dev, "unable to allocate widgets!\n"); 3990 devinfo->endnode = devinfo->startnode; 3991 devinfo->nodecnt = 0; 3992 return; 3993 } 3994 3995 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3996 w = hdac_widget_get(devinfo, i); 3997 if (w == NULL) 3998 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3999 else { 4000 w->devinfo = devinfo; 4001 w->nid = i; 4002 w->enable = 1; 4003 w->selconn = -1; 4004 w->pflags = 0; 4005 w->ctlflags = 0; 4006 w->param.eapdbtl = HDAC_INVALID; 4007 hdac_widget_parse(w); 4008 } 4009 } 4010} 4011 4012static void 4013hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4014{ 4015 struct hdac_softc *sc = devinfo->codec->sc; 4016 struct hdac_audio_ctl *ctls; 4017 struct hdac_widget *w, *cw; 4018 int i, j, cnt, max, ocap, icap; 4019 int mute, offset, step, size; 4020 4021 /* XXX This is redundant */ 4022 max = 0; 4023 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4024 w = hdac_widget_get(devinfo, i); 4025 if (w == NULL || w->enable == 0) 4026 continue; 4027 if (w->param.outamp_cap != 0) 4028 max++; 4029 if (w->param.inamp_cap != 0) { 4030 switch (w->type) { 4031 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4032 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4033 for (j = 0; j < w->nconns; j++) { 4034 cw = hdac_widget_get(devinfo, 4035 w->conns[j]); 4036 if (cw == NULL || cw->enable == 0) 4037 continue; 4038 max++; 4039 } 4040 break; 4041 default: 4042 max++; 4043 break; 4044 } 4045 } 4046 } 4047 4048 devinfo->function.audio.ctlcnt = max; 4049 4050 if (max < 1) 4051 return; 4052 4053 ctls = (struct hdac_audio_ctl *)malloc( 4054 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4055 4056 if (ctls == NULL) { 4057 /* Blekh! */ 4058 device_printf(sc->dev, "unable to allocate ctls!\n"); 4059 devinfo->function.audio.ctlcnt = 0; 4060 return; 4061 } 4062 4063 cnt = 0; 4064 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4065 if (cnt >= max) { 4066 device_printf(sc->dev, "%s: Ctl overflow!\n", 4067 __func__); 4068 break; 4069 } 4070 w = hdac_widget_get(devinfo, i); 4071 if (w == NULL || w->enable == 0) 4072 continue; 4073 ocap = w->param.outamp_cap; 4074 icap = w->param.inamp_cap; 4075 if (ocap != 0) { 4076 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4077 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4078 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4079 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4080 /*if (offset > step) { 4081 HDA_BOOTVERBOSE( 4082 device_printf(sc->dev, 4083 "HDA_DEBUG: BUGGY outamp: nid=%d " 4084 "[offset=%d > step=%d]\n", 4085 w->nid, offset, step); 4086 ); 4087 offset = step; 4088 }*/ 4089 ctls[cnt].enable = 1; 4090 ctls[cnt].widget = w; 4091 ctls[cnt].mute = mute; 4092 ctls[cnt].step = step; 4093 ctls[cnt].size = size; 4094 ctls[cnt].offset = offset; 4095 ctls[cnt].left = offset; 4096 ctls[cnt].right = offset; 4097 ctls[cnt++].dir = HDA_CTL_OUT; 4098 } 4099 4100 if (icap != 0) { 4101 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4102 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4103 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4104 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4105 /*if (offset > step) { 4106 HDA_BOOTVERBOSE( 4107 device_printf(sc->dev, 4108 "HDA_DEBUG: BUGGY inamp: nid=%d " 4109 "[offset=%d > step=%d]\n", 4110 w->nid, offset, step); 4111 ); 4112 offset = step; 4113 }*/ 4114 switch (w->type) { 4115 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4116 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4117 for (j = 0; j < w->nconns; j++) { 4118 if (cnt >= max) { 4119 device_printf(sc->dev, 4120 "%s: Ctl overflow!\n", 4121 __func__); 4122 break; 4123 } 4124 cw = hdac_widget_get(devinfo, 4125 w->conns[j]); 4126 if (cw == NULL || cw->enable == 0) 4127 continue; 4128 ctls[cnt].enable = 1; 4129 ctls[cnt].widget = w; 4130 ctls[cnt].childwidget = cw; 4131 ctls[cnt].index = j; 4132 ctls[cnt].mute = mute; 4133 ctls[cnt].step = step; 4134 ctls[cnt].size = size; 4135 ctls[cnt].offset = offset; 4136 ctls[cnt].left = offset; 4137 ctls[cnt].right = offset; 4138 ctls[cnt++].dir = HDA_CTL_IN; 4139 } 4140 break; 4141 default: 4142 if (cnt >= max) { 4143 device_printf(sc->dev, 4144 "%s: Ctl overflow!\n", 4145 __func__); 4146 break; 4147 } 4148 ctls[cnt].enable = 1; 4149 ctls[cnt].widget = w; 4150 ctls[cnt].mute = mute; 4151 ctls[cnt].step = step; 4152 ctls[cnt].size = size; 4153 ctls[cnt].offset = offset; 4154 ctls[cnt].left = offset; 4155 ctls[cnt].right = offset; 4156 ctls[cnt++].dir = HDA_CTL_IN; 4157 break; 4158 } 4159 } 4160 } 4161 4162 devinfo->function.audio.ctl = ctls; 4163} 4164 4165static const struct { 4166 uint32_t model; 4167 uint32_t id; 4168 uint32_t set, unset; 4169} hdac_quirks[] = { 4170 /* 4171 * XXX Force stereo quirk. Monoural recording / playback 4172 * on few codecs (especially ALC880) seems broken or 4173 * perhaps unsupported. 4174 */ 4175 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4176 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4177 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4178 HDA_QUIRK_GPIO0, 0 }, 4179 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4180 HDA_QUIRK_GPIO0, 0 }, 4181 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4182 HDA_QUIRK_GPIO0, 0 }, 4183 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4184 HDA_QUIRK_GPIO0, 0 }, 4185 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4186 HDA_QUIRK_GPIO0, 0 }, 4187 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4188 HDA_QUIRK_EAPDINV, 0 }, 4189 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4190 HDA_QUIRK_EAPDINV, 0 }, 4191 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4192 HDA_QUIRK_OVREF, 0 }, 4193 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4194 HDA_QUIRK_OVREF, 0 }, 4195 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4196 HDA_QUIRK_OVREF, 0 }, 4197 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4198 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4199 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4200 HDA_QUIRK_GPIO1, 0 }, 4201 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4202 HDA_QUIRK_EAPDINV, 0 }, 4203 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4204 HDA_QUIRK_EAPDINV, 0 }, 4205 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4206 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4207 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4208 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4209 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4210 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4211 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4212 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4213 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4214 0, HDA_QUIRK_FORCESTEREO }, 4215 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4216 HDA_QUIRK_SOFTPCMVOL, 0 } 4217}; 4218#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4219 4220static void 4221hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4222{ 4223 struct hdac_widget *w; 4224 struct hdac_audio_ctl *ctl; 4225 uint32_t id, subvendor; 4226 int i; 4227 4228 id = hdac_codec_id(devinfo); 4229 subvendor = devinfo->codec->sc->pci_subvendor; 4230 4231 /* 4232 * Quirks 4233 */ 4234 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4235 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4236 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4237 continue; 4238 if (hdac_quirks[i].set != 0) 4239 devinfo->function.audio.quirks |= 4240 hdac_quirks[i].set; 4241 if (hdac_quirks[i].unset != 0) 4242 devinfo->function.audio.quirks &= 4243 ~(hdac_quirks[i].unset); 4244 } 4245 4246 switch (id) { 4247 case HDA_CODEC_ALC260: 4248 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4249 w = hdac_widget_get(devinfo, i); 4250 if (w == NULL || w->enable == 0) 4251 continue; 4252 if (w->type != 4253 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4254 continue; 4255 if (w->nid != 5) 4256 w->enable = 0; 4257 } 4258 if (subvendor == HP_XW4300_SUBVENDOR) { 4259 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4260 if (ctl != NULL && ctl->widget != NULL) { 4261 ctl->ossmask = SOUND_MASK_SPEAKER; 4262 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4263 } 4264 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4265 if (ctl != NULL && ctl->widget != NULL) { 4266 ctl->ossmask = SOUND_MASK_SPEAKER; 4267 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4268 } 4269 } else if (subvendor == HP_3010_SUBVENDOR) { 4270 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4271 if (ctl != NULL && ctl->widget != NULL) { 4272 ctl->ossmask = SOUND_MASK_SPEAKER; 4273 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4274 } 4275 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4276 if (ctl != NULL && ctl->widget != NULL) { 4277 ctl->ossmask = SOUND_MASK_SPEAKER; 4278 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4279 } 4280 } 4281 break; 4282 case HDA_CODEC_ALC262: 4283 if (subvendor == HP_DC7700_SUBVENDOR) { 4284 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4285 if (ctl != NULL && ctl->widget != NULL) { 4286 ctl->ossmask = SOUND_MASK_SPEAKER; 4287 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4288 } 4289 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4290 if (ctl != NULL && ctl->widget != NULL) { 4291 ctl->ossmask = SOUND_MASK_SPEAKER; 4292 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4293 } 4294 } 4295 break; 4296 case HDA_CODEC_ALC861: 4297 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4298 if (ctl != NULL) 4299 ctl->muted = HDA_AMP_MUTE_ALL; 4300 break; 4301 case HDA_CODEC_ALC880: 4302 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4303 w = hdac_widget_get(devinfo, i); 4304 if (w == NULL || w->enable == 0) 4305 continue; 4306 if (w->type == 4307 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4308 w->nid != 9 && w->nid != 29) { 4309 w->enable = 0; 4310 } else if (w->type != 4311 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4312 w->nid == 29) { 4313 w->type = 4314 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4315 w->param.widget_cap &= 4316 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4317 w->param.widget_cap |= 4318 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4319 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4320 strlcpy(w->name, "beep widget", sizeof(w->name)); 4321 } 4322 } 4323 break; 4324 case HDA_CODEC_ALC883: 4325 /* 4326 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4327 * Clear vref cap for jack connectivity. 4328 */ 4329 w = hdac_widget_get(devinfo, 24); 4330 if (w != NULL && w->enable != 0 && w->type == 4331 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4332 (w->wclass.pin.config & 4333 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4334 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4335 w->wclass.pin.cap &= ~( 4336 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4337 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4338 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4339 w = hdac_widget_get(devinfo, 25); 4340 if (w != NULL && w->enable != 0 && w->type == 4341 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4342 (w->wclass.pin.config & 4343 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4344 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4345 w->wclass.pin.cap &= ~( 4346 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4347 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4348 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4349 /* 4350 * nid: 26 = Line-in, leave it alone. 4351 */ 4352 break; 4353 case HDA_CODEC_AD1981HD: 4354 w = hdac_widget_get(devinfo, 11); 4355 if (w != NULL && w->enable != 0 && w->nconns > 3) 4356 w->selconn = 3; 4357 if (subvendor == IBM_M52_SUBVENDOR) { 4358 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4359 if (ctl != NULL) 4360 ctl->ossmask = SOUND_MASK_SPEAKER; 4361 } 4362 break; 4363 case HDA_CODEC_AD1986A: 4364 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4365 w = hdac_widget_get(devinfo, i); 4366 if (w == NULL || w->enable == 0) 4367 continue; 4368 if (w->type != 4369 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4370 continue; 4371 if (w->nid != 3) 4372 w->enable = 0; 4373 } 4374 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4375 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4376 /* nid 28 is mic, nid 29 is line-in */ 4377 w = hdac_widget_get(devinfo, 15); 4378 if (w != NULL) 4379 w->selconn = 2; 4380 w = hdac_widget_get(devinfo, 16); 4381 if (w != NULL) 4382 w->selconn = 1; 4383 } 4384 break; 4385 case HDA_CODEC_AD1988: 4386 case HDA_CODEC_AD1988B: 4387 /*w = hdac_widget_get(devinfo, 12); 4388 if (w != NULL) { 4389 w->selconn = 1; 4390 w->pflags |= HDA_ADC_LOCKED; 4391 } 4392 w = hdac_widget_get(devinfo, 13); 4393 if (w != NULL) { 4394 w->selconn = 4; 4395 w->pflags |= HDA_ADC_LOCKED; 4396 } 4397 w = hdac_widget_get(devinfo, 14); 4398 if (w != NULL) { 4399 w->selconn = 2; 4400 w->pflags |= HDA_ADC_LOCKED; 4401 }*/ 4402 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4403 if (ctl != NULL) { 4404 ctl->ossmask = SOUND_MASK_IGAIN; 4405 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4406 } 4407 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4408 if (ctl != NULL) { 4409 ctl->ossmask = SOUND_MASK_IGAIN; 4410 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4411 } 4412 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4413 if (ctl != NULL) { 4414 ctl->ossmask = SOUND_MASK_IGAIN; 4415 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4416 } 4417 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4418 if (ctl != NULL) { 4419 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4420 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4421 } 4422 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4423 if (ctl != NULL) { 4424 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4425 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4426 } 4427 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4428 if (ctl != NULL) { 4429 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4430 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4431 } 4432 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4433 if (ctl != NULL) { 4434 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4435 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4436 } 4437 break; 4438 case HDA_CODEC_STAC9221: 4439 /* 4440 * Dell XPS M1210 need all DACs for each output jacks 4441 */ 4442 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4443 break; 4444 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4445 w = hdac_widget_get(devinfo, i); 4446 if (w == NULL || w->enable == 0) 4447 continue; 4448 if (w->type != 4449 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4450 continue; 4451 if (w->nid != 2) 4452 w->enable = 0; 4453 } 4454 break; 4455 case HDA_CODEC_STAC9221D: 4456 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4457 w = hdac_widget_get(devinfo, i); 4458 if (w == NULL || w->enable == 0) 4459 continue; 4460 if (w->type == 4461 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4462 w->nid != 6) 4463 w->enable = 0; 4464 4465 } 4466 break; 4467 case HDA_CODEC_STAC9227: 4468 w = hdac_widget_get(devinfo, 8); 4469 if (w != NULL) 4470 w->enable = 0; 4471 w = hdac_widget_get(devinfo, 9); 4472 if (w != NULL) 4473 w->enable = 0; 4474 break; 4475 case HDA_CODEC_CXWAIKIKI: 4476 if (subvendor == HP_DV5000_SUBVENDOR) { 4477 w = hdac_widget_get(devinfo, 27); 4478 if (w != NULL) 4479 w->enable = 0; 4480 } 4481 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4482 if (ctl != NULL) 4483 ctl->ossmask = SOUND_MASK_SKIP; 4484 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4485 if (ctl != NULL && ctl->childwidget != NULL && 4486 ctl->childwidget->enable != 0) { 4487 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4488 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4489 } 4490 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4491 if (ctl != NULL && ctl->childwidget != NULL && 4492 ctl->childwidget->enable != 0) { 4493 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4494 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4495 } 4496 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4497 if (ctl != NULL && ctl->childwidget != NULL && 4498 ctl->childwidget->enable != 0) { 4499 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4500 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4501 } 4502 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4503 if (ctl != NULL) { 4504 ctl->ossmask = SOUND_MASK_SKIP; 4505 /* XXX mixer \=rec mic broken.. why?!? */ 4506 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4507 } 4508 break; 4509 default: 4510 break; 4511 } 4512} 4513 4514static int 4515hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4516{ 4517 int *dev = &devinfo->function.audio.ossidx; 4518 4519 while (*dev < SOUND_MIXER_NRDEVICES) { 4520 switch (*dev) { 4521 case SOUND_MIXER_VOLUME: 4522 case SOUND_MIXER_BASS: 4523 case SOUND_MIXER_TREBLE: 4524 case SOUND_MIXER_PCM: 4525 case SOUND_MIXER_SPEAKER: 4526 case SOUND_MIXER_LINE: 4527 case SOUND_MIXER_MIC: 4528 case SOUND_MIXER_CD: 4529 case SOUND_MIXER_RECLEV: 4530 case SOUND_MIXER_IGAIN: 4531 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4532 (*dev)++; 4533 break; 4534 default: 4535 return (*dev)++; 4536 break; 4537 } 4538 } 4539 4540 return (-1); 4541} 4542 4543static int 4544hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4545{ 4546 struct hdac_widget *w; 4547 int i, ret = 0; 4548 4549 if (depth > HDA_PARSE_MAXDEPTH) 4550 return (0); 4551 w = hdac_widget_get(devinfo, nid); 4552 if (w == NULL || w->enable == 0) 4553 return (0); 4554 switch (w->type) { 4555 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4556 w->pflags |= HDA_DAC_PATH; 4557 ret = 1; 4558 break; 4559 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4560 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4561 for (i = 0; i < w->nconns; i++) { 4562 if (hdac_widget_find_dac_path(devinfo, 4563 w->conns[i], depth + 1) != 0) { 4564 if (w->selconn == -1) 4565 w->selconn = i; 4566 ret = 1; 4567 w->pflags |= HDA_DAC_PATH; 4568 } 4569 } 4570 break; 4571 default: 4572 break; 4573 } 4574 return (ret); 4575} 4576 4577static int 4578hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4579{ 4580 struct hdac_widget *w; 4581 int i, conndev, ret = 0; 4582 4583 if (depth > HDA_PARSE_MAXDEPTH) 4584 return (0); 4585 w = hdac_widget_get(devinfo, nid); 4586 if (w == NULL || w->enable == 0) 4587 return (0); 4588 switch (w->type) { 4589 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4590 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4591 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4592 for (i = 0; i < w->nconns; i++) { 4593 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4594 depth + 1) != 0) { 4595 if (w->selconn == -1) 4596 w->selconn = i; 4597 w->pflags |= HDA_ADC_PATH; 4598 ret = 1; 4599 } 4600 } 4601 break; 4602 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4603 conndev = w->wclass.pin.config & 4604 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4605 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4606 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4607 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4608 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4609 w->pflags |= HDA_ADC_PATH; 4610 ret = 1; 4611 } 4612 break; 4613 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4614 if (w->pflags & HDA_DAC_PATH) { 4615 w->pflags |= HDA_ADC_PATH; 4616 ret = 1; 4617 } 4618 break;*/ 4619 default: 4620 break; 4621 } 4622 return (ret); 4623} 4624 4625static uint32_t 4626hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4627 nid_t nid, nid_t pnid, int index, int depth) 4628{ 4629 struct hdac_widget *w, *pw; 4630 struct hdac_audio_ctl *ctl; 4631 uint32_t fl = 0; 4632 int i, ossdev, conndev, strategy; 4633 4634 if (depth > HDA_PARSE_MAXDEPTH) 4635 return (0); 4636 4637 w = hdac_widget_get(devinfo, nid); 4638 if (w == NULL || w->enable == 0) 4639 return (0); 4640 4641 pw = hdac_widget_get(devinfo, pnid); 4642 strategy = devinfo->function.audio.parsing_strategy; 4643 4644 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4645 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4646 for (i = 0; i < w->nconns; i++) { 4647 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4648 w->nid, i, depth + 1); 4649 } 4650 w->ctlflags |= fl; 4651 return (fl); 4652 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4653 (w->pflags & HDA_DAC_PATH)) { 4654 i = 0; 4655 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4656 if (ctl->enable == 0 || ctl->widget == NULL) 4657 continue; 4658 /* XXX This should be compressed! */ 4659 if (((ctl->widget->nid == w->nid) || 4660 (ctl->widget->nid == pnid && ctl->index == index && 4661 (ctl->dir & HDA_CTL_IN)) || 4662 (ctl->widget->nid == pnid && pw != NULL && 4663 pw->type == 4664 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4665 (pw->nconns < 2 || pw->selconn == index || 4666 pw->selconn == -1) && 4667 (ctl->dir & HDA_CTL_OUT)) || 4668 (strategy == HDA_PARSE_DIRECT && 4669 ctl->widget->nid == w->nid)) && 4670 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4671 /*if (pw != NULL && pw->selconn == -1) 4672 pw->selconn = index; 4673 fl |= SOUND_MASK_VOLUME; 4674 fl |= SOUND_MASK_PCM; 4675 ctl->ossmask |= SOUND_MASK_VOLUME; 4676 ctl->ossmask |= SOUND_MASK_PCM; 4677 ctl->ossdev = SOUND_MIXER_PCM;*/ 4678 if (!(w->ctlflags & SOUND_MASK_PCM) || 4679 (pw != NULL && 4680 !(pw->ctlflags & SOUND_MASK_PCM))) { 4681 fl |= SOUND_MASK_VOLUME; 4682 fl |= SOUND_MASK_PCM; 4683 ctl->ossmask |= SOUND_MASK_VOLUME; 4684 ctl->ossmask |= SOUND_MASK_PCM; 4685 ctl->ossdev = SOUND_MIXER_PCM; 4686 w->ctlflags |= SOUND_MASK_VOLUME; 4687 w->ctlflags |= SOUND_MASK_PCM; 4688 if (pw != NULL) { 4689 if (pw->selconn == -1) 4690 pw->selconn = index; 4691 pw->ctlflags |= 4692 SOUND_MASK_VOLUME; 4693 pw->ctlflags |= 4694 SOUND_MASK_PCM; 4695 } 4696 } 4697 } 4698 } 4699 w->ctlflags |= fl; 4700 return (fl); 4701 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4702 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4703 (w->pflags & HDA_ADC_PATH)) { 4704 conndev = w->wclass.pin.config & 4705 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4706 i = 0; 4707 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4708 if (ctl->enable == 0 || ctl->widget == NULL) 4709 continue; 4710 /* XXX This should be compressed! */ 4711 if (((ctl->widget->nid == pnid && ctl->index == index && 4712 (ctl->dir & HDA_CTL_IN)) || 4713 (ctl->widget->nid == pnid && pw != NULL && 4714 pw->type == 4715 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4716 (pw->nconns < 2 || pw->selconn == index || 4717 pw->selconn == -1) && 4718 (ctl->dir & HDA_CTL_OUT)) || 4719 (strategy == HDA_PARSE_DIRECT && 4720 ctl->widget->nid == w->nid)) && 4721 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4722 if (pw != NULL && pw->selconn == -1) 4723 pw->selconn = index; 4724 ossdev = 0; 4725 switch (conndev) { 4726 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4727 ossdev = SOUND_MIXER_MIC; 4728 break; 4729 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4730 ossdev = SOUND_MIXER_LINE; 4731 break; 4732 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4733 ossdev = SOUND_MIXER_CD; 4734 break; 4735 default: 4736 ossdev = 4737 hdac_audio_ctl_ossmixer_getnextdev( 4738 devinfo); 4739 if (ossdev < 0) 4740 ossdev = 0; 4741 break; 4742 } 4743 if (strategy == HDA_PARSE_MIXER) { 4744 fl |= SOUND_MASK_VOLUME; 4745 ctl->ossmask |= SOUND_MASK_VOLUME; 4746 } 4747 fl |= 1 << ossdev; 4748 ctl->ossmask |= 1 << ossdev; 4749 ctl->ossdev = ossdev; 4750 } 4751 } 4752 w->ctlflags |= fl; 4753 return (fl); 4754 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4755 i = 0; 4756 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4757 if (ctl->enable == 0 || ctl->widget == NULL) 4758 continue; 4759 /* XXX This should be compressed! */ 4760 if (((ctl->widget->nid == pnid && ctl->index == index && 4761 (ctl->dir & HDA_CTL_IN)) || 4762 (ctl->widget->nid == pnid && pw != NULL && 4763 pw->type == 4764 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4765 (pw->nconns < 2 || pw->selconn == index || 4766 pw->selconn == -1) && 4767 (ctl->dir & HDA_CTL_OUT)) || 4768 (strategy == HDA_PARSE_DIRECT && 4769 ctl->widget->nid == w->nid)) && 4770 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4771 if (pw != NULL && pw->selconn == -1) 4772 pw->selconn = index; 4773 fl |= SOUND_MASK_VOLUME; 4774 fl |= SOUND_MASK_SPEAKER; 4775 ctl->ossmask |= SOUND_MASK_VOLUME; 4776 ctl->ossmask |= SOUND_MASK_SPEAKER; 4777 ctl->ossdev = SOUND_MIXER_SPEAKER; 4778 } 4779 } 4780 w->ctlflags |= fl; 4781 return (fl); 4782 } 4783 return (0); 4784} 4785 4786static uint32_t 4787hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4788{ 4789 struct hdac_widget *w, *cw; 4790 struct hdac_audio_ctl *ctl; 4791 uint32_t fl; 4792 int i; 4793 4794 if (depth > HDA_PARSE_MAXDEPTH) 4795 return (0); 4796 4797 w = hdac_widget_get(devinfo, nid); 4798 if (w == NULL || w->enable == 0) 4799 return (0); 4800 /*if (!(w->pflags & HDA_ADC_PATH)) 4801 return (0); 4802 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4803 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4804 return (0);*/ 4805 i = 0; 4806 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4807 if (ctl->enable == 0 || ctl->widget == NULL) 4808 continue; 4809 if (ctl->widget->nid == nid) { 4810 ctl->ossmask |= SOUND_MASK_RECLEV; 4811 w->ctlflags |= SOUND_MASK_RECLEV; 4812 return (SOUND_MASK_RECLEV); 4813 } 4814 } 4815 for (i = 0; i < w->nconns; i++) { 4816 cw = hdac_widget_get(devinfo, w->conns[i]); 4817 if (cw == NULL || cw->enable == 0) 4818 continue; 4819 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4820 continue; 4821 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4822 if (fl != 0) { 4823 cw->ctlflags |= fl; 4824 w->ctlflags |= fl; 4825 return (fl); 4826 } 4827 } 4828 return (0); 4829} 4830 4831static int 4832hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4833{ 4834 struct hdac_widget *w, *cw; 4835 int i, child = 0; 4836 4837 if (depth > HDA_PARSE_MAXDEPTH) 4838 return (0); 4839 4840 w = hdac_widget_get(devinfo, nid); 4841 if (w == NULL || w->enable == 0) 4842 return (0); 4843 /*if (!(w->pflags & HDA_ADC_PATH)) 4844 return (0); 4845 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4846 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4847 return (0);*/ 4848 /* XXX weak! */ 4849 for (i = 0; i < w->nconns; i++) { 4850 cw = hdac_widget_get(devinfo, w->conns[i]); 4851 if (cw == NULL) 4852 continue; 4853 if (++child > 1) { 4854 w->pflags |= HDA_ADC_RECSEL; 4855 return (1); 4856 } 4857 } 4858 for (i = 0; i < w->nconns; i++) { 4859 if (hdac_audio_ctl_recsel_build(devinfo, 4860 w->conns[i], depth + 1) != 0) 4861 return (1); 4862 } 4863 return (0); 4864} 4865 4866static int 4867hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4868{ 4869 struct hdac_widget *w, *cw; 4870 int i, j, conndev, found_dac = 0; 4871 int strategy; 4872 4873 strategy = devinfo->function.audio.parsing_strategy; 4874 4875 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4876 w = hdac_widget_get(devinfo, i); 4877 if (w == NULL || w->enable == 0) 4878 continue; 4879 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4880 continue; 4881 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4882 continue; 4883 conndev = w->wclass.pin.config & 4884 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4885 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4886 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4887 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4888 continue; 4889 for (j = 0; j < w->nconns; j++) { 4890 cw = hdac_widget_get(devinfo, w->conns[j]); 4891 if (cw == NULL || cw->enable == 0) 4892 continue; 4893 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4894 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4895 cw->type == 4896 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4897 continue; 4898 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4899 != 0) { 4900 if (w->selconn == -1) 4901 w->selconn = j; 4902 w->pflags |= HDA_DAC_PATH; 4903 found_dac++; 4904 } 4905 } 4906 } 4907 4908 return (found_dac); 4909} 4910 4911static void 4912hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4913{ 4914 struct hdac_widget *w; 4915 struct hdac_audio_ctl *ctl; 4916 int i, j, dacs, strategy; 4917 4918 /* Construct DAC path */ 4919 strategy = HDA_PARSE_MIXER; 4920 devinfo->function.audio.parsing_strategy = strategy; 4921 HDA_BOOTVERBOSE( 4922 device_printf(devinfo->codec->sc->dev, 4923 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4924 HDA_WIDGET_PARSER_REV); 4925 ); 4926 dacs = hdac_audio_build_tree_strategy(devinfo); 4927 if (dacs == 0) { 4928 HDA_BOOTVERBOSE( 4929 device_printf(devinfo->codec->sc->dev, 4930 "HDA_DEBUG: HWiP: 0 DAC path found! " 4931 "Retrying parser " 4932 "using HDA_PARSE_DIRECT strategy.\n"); 4933 ); 4934 strategy = HDA_PARSE_DIRECT; 4935 devinfo->function.audio.parsing_strategy = strategy; 4936 dacs = hdac_audio_build_tree_strategy(devinfo); 4937 } 4938 4939 HDA_BOOTVERBOSE( 4940 device_printf(devinfo->codec->sc->dev, 4941 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4942 "strategy.\n", 4943 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4944 ); 4945 4946 /* Construct ADC path */ 4947 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4948 w = hdac_widget_get(devinfo, i); 4949 if (w == NULL || w->enable == 0) 4950 continue; 4951 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4952 continue; 4953 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4954 } 4955 4956 /* Output mixers */ 4957 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4958 w = hdac_widget_get(devinfo, i); 4959 if (w == NULL || w->enable == 0) 4960 continue; 4961 if ((strategy == HDA_PARSE_MIXER && 4962 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4963 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4964 && (w->pflags & HDA_DAC_PATH)) || 4965 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4966 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4967 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4968 w->nid, devinfo->startnode - 1, 0, 0); 4969 } else if (w->type == 4970 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4971 j = 0; 4972 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4973 NULL) { 4974 if (ctl->enable == 0 || ctl->widget == NULL) 4975 continue; 4976 if (ctl->widget->nid != w->nid) 4977 continue; 4978 ctl->ossmask |= SOUND_MASK_VOLUME; 4979 ctl->ossmask |= SOUND_MASK_SPEAKER; 4980 ctl->ossdev = SOUND_MIXER_SPEAKER; 4981 w->ctlflags |= SOUND_MASK_VOLUME; 4982 w->ctlflags |= SOUND_MASK_SPEAKER; 4983 } 4984 } 4985 } 4986 4987 /* Input mixers (rec) */ 4988 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4989 w = hdac_widget_get(devinfo, i); 4990 if (w == NULL || w->enable == 0) 4991 continue; 4992 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4993 w->pflags & HDA_ADC_PATH)) 4994 continue; 4995 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4996 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4997 } 4998} 4999 5000#define HDA_COMMIT_CONN (1 << 0) 5001#define HDA_COMMIT_CTRL (1 << 1) 5002#define HDA_COMMIT_EAPD (1 << 2) 5003#define HDA_COMMIT_GPIO (1 << 3) 5004#define HDA_COMMIT_MISC (1 << 4) 5005#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 5006 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 5007 5008static void 5009hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 5010{ 5011 struct hdac_softc *sc = devinfo->codec->sc; 5012 struct hdac_widget *w; 5013 nid_t cad; 5014 int i; 5015 5016 if (!(cfl & HDA_COMMIT_ALL)) 5017 return; 5018 5019 cad = devinfo->codec->cad; 5020 5021 if ((cfl & HDA_COMMIT_MISC)) { 5022 if (sc->pci_subvendor == APPLE_INTEL_MAC) 5023 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 5024 0x7e7, 0), cad); 5025 } 5026 5027 if (cfl & HDA_COMMIT_GPIO) { 5028 uint32_t gdata, gmask, gdir; 5029 int commitgpio, numgpio; 5030 5031 gdata = 0; 5032 gmask = 0; 5033 gdir = 0; 5034 commitgpio = 0; 5035 5036 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5037 devinfo->function.audio.gpio); 5038 5039 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5040 commitgpio = (numgpio > 0) ? 1 : 0; 5041 else { 5042 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5043 if (!(devinfo->function.audio.quirks & 5044 (1 << i))) 5045 continue; 5046 if (commitgpio == 0) { 5047 commitgpio = 1; 5048 HDA_BOOTVERBOSE( 5049 gdata = hdac_command(sc, 5050 HDA_CMD_GET_GPIO_DATA(cad, 5051 devinfo->nid), cad); 5052 gmask = hdac_command(sc, 5053 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5054 devinfo->nid), cad); 5055 gdir = hdac_command(sc, 5056 HDA_CMD_GET_GPIO_DIRECTION(cad, 5057 devinfo->nid), cad); 5058 device_printf(sc->dev, 5059 "GPIO init: data=0x%08x " 5060 "mask=0x%08x dir=0x%08x\n", 5061 gdata, gmask, gdir); 5062 gdata = 0; 5063 gmask = 0; 5064 gdir = 0; 5065 ); 5066 } 5067 gdata |= 1 << i; 5068 gmask |= 1 << i; 5069 gdir |= 1 << i; 5070 } 5071 } 5072 5073 if (commitgpio != 0) { 5074 HDA_BOOTVERBOSE( 5075 device_printf(sc->dev, 5076 "GPIO commit: data=0x%08x mask=0x%08x " 5077 "dir=0x%08x\n", 5078 gdata, gmask, gdir); 5079 ); 5080 hdac_command(sc, 5081 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5082 gmask), cad); 5083 hdac_command(sc, 5084 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5085 gdir), cad); 5086 hdac_command(sc, 5087 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5088 gdata), cad); 5089 } 5090 } 5091 5092 for (i = 0; i < devinfo->nodecnt; i++) { 5093 w = &devinfo->widget[i]; 5094 if (w == NULL || w->enable == 0) 5095 continue; 5096 if (cfl & HDA_COMMIT_CONN) { 5097 if (w->selconn == -1) 5098 w->selconn = 0; 5099 if (w->nconns > 0) 5100 hdac_widget_connection_select(w, w->selconn); 5101 } 5102 if ((cfl & HDA_COMMIT_CTRL) && 5103 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5104 uint32_t pincap; 5105 5106 pincap = w->wclass.pin.cap; 5107 5108 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5109 (HDA_DAC_PATH | HDA_ADC_PATH)) 5110 device_printf(sc->dev, "WARNING: node %d " 5111 "participate both for DAC/ADC!\n", w->nid); 5112 if (w->pflags & HDA_DAC_PATH) { 5113 w->wclass.pin.ctrl &= 5114 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5115 if ((w->wclass.pin.config & 5116 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5117 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5118 w->wclass.pin.ctrl &= 5119 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5120 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5121 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5122 w->wclass.pin.ctrl |= 5123 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5124 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5125 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5126 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5127 w->wclass.pin.ctrl |= 5128 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5129 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5130 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5131 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5132 w->wclass.pin.ctrl |= 5133 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5134 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5135 } else if (w->pflags & HDA_ADC_PATH) { 5136 w->wclass.pin.ctrl &= 5137 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5138 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5139 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5140 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5141 w->wclass.pin.ctrl |= 5142 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5143 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5144 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5145 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5146 w->wclass.pin.ctrl |= 5147 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5148 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5149 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5150 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5151 w->wclass.pin.ctrl |= 5152 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5153 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5154 } else 5155 w->wclass.pin.ctrl &= ~( 5156 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5157 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5158 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5159 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5160 hdac_command(sc, 5161 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5162 w->wclass.pin.ctrl), cad); 5163 } 5164 if ((cfl & HDA_COMMIT_EAPD) && 5165 w->param.eapdbtl != HDAC_INVALID) { 5166 uint32_t val; 5167 5168 val = w->param.eapdbtl; 5169 if (devinfo->function.audio.quirks & 5170 HDA_QUIRK_EAPDINV) 5171 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5172 hdac_command(sc, 5173 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5174 val), cad); 5175 5176 } 5177 DELAY(1000); 5178 } 5179} 5180 5181static void 5182hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5183{ 5184 struct hdac_softc *sc = devinfo->codec->sc; 5185 struct hdac_audio_ctl *ctl; 5186 int i; 5187 5188 devinfo->function.audio.mvol = 100 | (100 << 8); 5189 i = 0; 5190 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5191 if (ctl->enable == 0 || ctl->widget == NULL) { 5192 HDA_BOOTVERBOSE( 5193 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5194 i, (ctl->widget != NULL) ? 5195 ctl->widget->nid : -1); 5196 if (ctl->childwidget != NULL) 5197 printf(" childnid=%d", 5198 ctl->childwidget->nid); 5199 if (ctl->widget == NULL) 5200 printf(" NULL WIDGET!"); 5201 printf(" DISABLED\n"); 5202 ); 5203 continue; 5204 } 5205 HDA_BOOTVERBOSE( 5206 if (ctl->ossmask == 0) { 5207 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5208 i, ctl->widget->nid); 5209 if (ctl->childwidget != NULL) 5210 printf(" childnid=%d", 5211 ctl->childwidget->nid); 5212 printf(" Bind to NONE\n"); 5213 } 5214 ); 5215 if (ctl->step > 0) { 5216 ctl->ossval = (ctl->left * 100) / ctl->step; 5217 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5218 } else 5219 ctl->ossval = 0; 5220 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5221 ctl->left, ctl->right); 5222 } 5223} 5224 5225static int 5226hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5227{ 5228 struct hdac_chan *ch; 5229 struct hdac_widget *w; 5230 uint32_t cap, fmtcap, pcmcap, path; 5231 int i, type, ret, max; 5232 5233 if (dir == PCMDIR_PLAY) { 5234 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5235 ch = &devinfo->codec->sc->play; 5236 path = HDA_DAC_PATH; 5237 } else { 5238 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5239 ch = &devinfo->codec->sc->rec; 5240 path = HDA_ADC_PATH; 5241 } 5242 5243 ch->caps = hdac_caps; 5244 ch->caps.fmtlist = ch->fmtlist; 5245 ch->bit16 = 1; 5246 ch->bit32 = 0; 5247 ch->pcmrates[0] = 48000; 5248 ch->pcmrates[1] = 0; 5249 5250 ret = 0; 5251 fmtcap = devinfo->function.audio.supp_stream_formats; 5252 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5253 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5254 5255 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5256 w = hdac_widget_get(devinfo, i); 5257 if (w == NULL || w->enable == 0 || w->type != type || 5258 !(w->pflags & path)) 5259 continue; 5260 cap = w->param.widget_cap; 5261 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5262 continue;*/ 5263 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5264 continue; 5265 cap = w->param.supp_stream_formats; 5266 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5267 } 5268 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5269 }*/ 5270 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5271 continue; 5272 if (ret == 0) { 5273 fmtcap = w->param.supp_stream_formats; 5274 pcmcap = w->param.supp_pcm_size_rate; 5275 } else { 5276 fmtcap &= w->param.supp_stream_formats; 5277 pcmcap &= w->param.supp_pcm_size_rate; 5278 } 5279 ch->io[ret++] = i; 5280 } 5281 ch->io[ret] = -1; 5282 5283 ch->supp_stream_formats = fmtcap; 5284 ch->supp_pcm_size_rate = pcmcap; 5285 5286 /* 5287 * 8bit = 0 5288 * 16bit = 1 5289 * 20bit = 2 5290 * 24bit = 3 5291 * 32bit = 4 5292 */ 5293 if (ret > 0) { 5294 cap = pcmcap; 5295 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5296 ch->bit16 = 1; 5297 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5298 ch->bit16 = 0; 5299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5300 ch->bit32 = 4; 5301 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5302 ch->bit32 = 3; 5303 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5304 ch->bit32 = 2; 5305 i = 0; 5306 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5307 ch->fmtlist[i++] = AFMT_S16_LE; 5308 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5309 if (ch->bit32 > 0) { 5310 if (!(devinfo->function.audio.quirks & 5311 HDA_QUIRK_FORCESTEREO)) 5312 ch->fmtlist[i++] = AFMT_S32_LE; 5313 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5314 } 5315 ch->fmtlist[i] = 0; 5316 i = 0; 5317 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5318 ch->pcmrates[i++] = 8000; 5319 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5320 ch->pcmrates[i++] = 11025; 5321 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5322 ch->pcmrates[i++] = 16000; 5323 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5324 ch->pcmrates[i++] = 22050; 5325 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5326 ch->pcmrates[i++] = 32000; 5327 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5328 ch->pcmrates[i++] = 44100; 5329 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5330 ch->pcmrates[i++] = 48000; 5331 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5332 ch->pcmrates[i++] = 88200; 5333 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5334 ch->pcmrates[i++] = 96000; 5335 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5336 ch->pcmrates[i++] = 176400; 5337 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5338 ch->pcmrates[i++] = 192000; 5339 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5340 ch->pcmrates[i] = 0; 5341 if (i > 0) { 5342 ch->caps.minspeed = ch->pcmrates[0]; 5343 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5344 } 5345 } 5346 5347 return (ret); 5348} 5349 5350static void 5351hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5352{ 5353 struct hdac_audio_ctl *ctl; 5354 struct hdac_softc *sc = devinfo->codec->sc; 5355 int i; 5356 uint32_t fl = 0; 5357 5358 5359 if (flag == 0) { 5360 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5361 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5362 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5363 } 5364 5365 i = 0; 5366 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5367 if (ctl->enable == 0 || ctl->widget == NULL || 5368 ctl->widget->enable == 0 || (ctl->ossmask & 5369 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5370 continue; 5371 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5372 (flag != 0 && (ctl->ossmask & flag))) { 5373 if (banner != NULL) { 5374 device_printf(sc->dev, "\n"); 5375 device_printf(sc->dev, "%s\n", banner); 5376 } 5377 goto hdac_ctl_dump_it_all; 5378 } 5379 } 5380 5381 return; 5382 5383hdac_ctl_dump_it_all: 5384 i = 0; 5385 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5386 if (ctl->enable == 0 || ctl->widget == NULL || 5387 ctl->widget->enable == 0) 5388 continue; 5389 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5390 (flag != 0 && (ctl->ossmask & flag)))) 5391 continue; 5392 if (flag == 0) { 5393 device_printf(sc->dev, "\n"); 5394 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5395 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5396 } 5397 device_printf(sc->dev, " |\n"); 5398 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5399 ctl->widget->nid, ctl->index); 5400 if (ctl->childwidget != NULL) 5401 printf("(nid: %2d) ", ctl->childwidget->nid); 5402 else 5403 printf(" "); 5404 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5405 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5406 ctl->ossmask); 5407 } 5408} 5409 5410static void 5411hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5412{ 5413 uint32_t cap; 5414 5415 cap = fcap; 5416 if (cap != 0) { 5417 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5418 device_printf(sc->dev, " Format:"); 5419 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5420 printf(" AC3"); 5421 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5422 printf(" FLOAT32"); 5423 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5424 printf(" PCM"); 5425 printf("\n"); 5426 } 5427 cap = pcmcap; 5428 if (cap != 0) { 5429 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5430 device_printf(sc->dev, " PCM size:"); 5431 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5432 printf(" 8"); 5433 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5434 printf(" 16"); 5435 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5436 printf(" 20"); 5437 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5438 printf(" 24"); 5439 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5440 printf(" 32"); 5441 printf("\n"); 5442 device_printf(sc->dev, " PCM rate:"); 5443 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5444 printf(" 8"); 5445 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5446 printf(" 11"); 5447 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5448 printf(" 16"); 5449 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5450 printf(" 22"); 5451 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5452 printf(" 32"); 5453 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5454 printf(" 44"); 5455 printf(" 48"); 5456 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5457 printf(" 88"); 5458 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5459 printf(" 96"); 5460 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5461 printf(" 176"); 5462 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5463 printf(" 192"); 5464 printf("\n"); 5465 } 5466} 5467 5468static void 5469hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5470{ 5471 uint32_t pincap, wcap; 5472 5473 pincap = w->wclass.pin.cap; 5474 wcap = w->param.widget_cap; 5475 5476 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5477 device_printf(sc->dev, " "); 5478 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5479 printf(" ISC"); 5480 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5481 printf(" TRQD"); 5482 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5483 printf(" PDC"); 5484 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5485 printf(" HP"); 5486 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5487 printf(" OUT"); 5488 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5489 printf(" IN"); 5490 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5491 printf(" BAL"); 5492 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5493 printf(" VREF["); 5494 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5495 printf(" 50"); 5496 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5497 printf(" 80"); 5498 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5499 printf(" 100"); 5500 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5501 printf(" GROUND"); 5502 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5503 printf(" HIZ"); 5504 printf(" ]"); 5505 } 5506 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5507 printf(" EAPD"); 5508 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5509 printf(" : UNSOL"); 5510 printf("\n"); 5511 device_printf(sc->dev, " Pin config: 0x%08x\n", 5512 w->wclass.pin.config); 5513 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5514 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5515 printf(" HP"); 5516 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5517 printf(" IN"); 5518 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5519 printf(" OUT"); 5520 printf("\n"); 5521} 5522 5523static void 5524hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5525{ 5526 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5527 device_printf(sc->dev, " " 5528 "mute=%d step=%d size=%d offset=%d\n", 5529 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5530 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5531 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5532 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5533} 5534 5535static void 5536hdac_dump_nodes(struct hdac_devinfo *devinfo) 5537{ 5538 struct hdac_softc *sc = devinfo->codec->sc; 5539 struct hdac_widget *w, *cw; 5540 int i, j; 5541 5542 device_printf(sc->dev, "\n"); 5543 device_printf(sc->dev, "Default Parameter\n"); 5544 device_printf(sc->dev, "-----------------\n"); 5545 hdac_dump_audio_formats(sc, 5546 devinfo->function.audio.supp_stream_formats, 5547 devinfo->function.audio.supp_pcm_size_rate); 5548 device_printf(sc->dev, " IN amp: 0x%08x\n", 5549 devinfo->function.audio.inamp_cap); 5550 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5551 devinfo->function.audio.outamp_cap); 5552 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5553 w = hdac_widget_get(devinfo, i); 5554 if (w == NULL) { 5555 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5556 continue; 5557 } 5558 device_printf(sc->dev, "\n"); 5559 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5560 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5561 "DIGITAL" : "ANALOG", 5562 (w->enable == 0) ? " [DISABLED]" : ""); 5563 device_printf(sc->dev, " name: %s\n", w->name); 5564 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5565 w->param.widget_cap); 5566 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5567 w->pflags); 5568 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5569 w->ctlflags); 5570 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5571 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5572 hdac_dump_audio_formats(sc, 5573 w->param.supp_stream_formats, 5574 w->param.supp_pcm_size_rate); 5575 } else if (w->type == 5576 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5577 hdac_dump_pin(sc, w); 5578 if (w->param.eapdbtl != HDAC_INVALID) 5579 device_printf(sc->dev, " EAPD: 0x%08x\n", 5580 w->param.eapdbtl); 5581 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5582 w->param.outamp_cap != 0) 5583 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5584 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5585 w->param.inamp_cap != 0) 5586 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5587 device_printf(sc->dev, " connections: %d\n", w->nconns); 5588 for (j = 0; j < w->nconns; j++) { 5589 cw = hdac_widget_get(devinfo, w->conns[j]); 5590 device_printf(sc->dev, " |\n"); 5591 device_printf(sc->dev, " + <- nid=%d [%s]", 5592 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5593 if (cw == NULL) 5594 printf(" [UNKNOWN]"); 5595 else if (cw->enable == 0) 5596 printf(" [DISABLED]"); 5597 if (w->nconns > 1 && w->selconn == j && w->type != 5598 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5599 printf(" (selected)"); 5600 printf("\n"); 5601 } 5602 } 5603 5604} 5605 5606static int 5607hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5608{ 5609 struct hdac_widget *w, *cw; 5610 struct hdac_softc *sc = devinfo->codec->sc; 5611 int i; 5612 5613 if (depth > HDA_PARSE_MAXDEPTH) 5614 return (0); 5615 5616 w = hdac_widget_get(devinfo, nid); 5617 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5618 return (0); 5619 5620 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5621 device_printf(sc->dev, "\n"); 5622 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5623 device_printf(sc->dev, " ^\n"); 5624 device_printf(sc->dev, " |\n"); 5625 device_printf(sc->dev, " +-----<------+\n"); 5626 } else { 5627 device_printf(sc->dev, " ^\n"); 5628 device_printf(sc->dev, " |\n"); 5629 device_printf(sc->dev, " "); 5630 printf(" nid=%d [%s]\n", w->nid, w->name); 5631 } 5632 5633 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5634 return (1); 5635 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5636 for (i = 0; i < w->nconns; i++) { 5637 cw = hdac_widget_get(devinfo, w->conns[i]); 5638 if (cw == NULL || cw->enable == 0 || cw->type == 5639 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5640 continue; 5641 if (hdac_dump_dac_internal(devinfo, cw->nid, 5642 depth + 1) != 0) 5643 return (1); 5644 } 5645 } else if ((w->type == 5646 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5647 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5648 w->selconn > -1 && w->selconn < w->nconns) { 5649 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5650 depth + 1) != 0) 5651 return (1); 5652 } 5653 5654 return (0); 5655} 5656 5657static void 5658hdac_dump_dac(struct hdac_devinfo *devinfo) 5659{ 5660 struct hdac_widget *w; 5661 struct hdac_softc *sc = devinfo->codec->sc; 5662 int i, printed = 0; 5663 5664 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5665 w = hdac_widget_get(devinfo, i); 5666 if (w == NULL || w->enable == 0) 5667 continue; 5668 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5669 !(w->pflags & HDA_DAC_PATH)) 5670 continue; 5671 if (printed == 0) { 5672 printed = 1; 5673 device_printf(sc->dev, "\n"); 5674 device_printf(sc->dev, "Playback path:\n"); 5675 } 5676 hdac_dump_dac_internal(devinfo, w->nid, 0); 5677 } 5678} 5679 5680static void 5681hdac_dump_adc(struct hdac_devinfo *devinfo) 5682{ 5683 struct hdac_widget *w, *cw; 5684 struct hdac_softc *sc = devinfo->codec->sc; 5685 int i, j; 5686 int printed = 0; 5687 char ossdevs[256]; 5688 5689 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5690 w = hdac_widget_get(devinfo, i); 5691 if (w == NULL || w->enable == 0) 5692 continue; 5693 if (!(w->pflags & HDA_ADC_RECSEL)) 5694 continue; 5695 if (printed == 0) { 5696 printed = 1; 5697 device_printf(sc->dev, "\n"); 5698 device_printf(sc->dev, "Recording sources:\n"); 5699 } 5700 device_printf(sc->dev, "\n"); 5701 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5702 for (j = 0; j < w->nconns; j++) { 5703 cw = hdac_widget_get(devinfo, w->conns[j]); 5704 if (cw == NULL || cw->enable == 0) 5705 continue; 5706 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5707 ossdevs, sizeof(ossdevs)); 5708 device_printf(sc->dev, " |\n"); 5709 device_printf(sc->dev, " + <- nid=%d [%s]", 5710 cw->nid, cw->name); 5711 if (strlen(ossdevs) > 0) { 5712 printf(" [recsrc: %s]", ossdevs); 5713 } 5714 printf("\n"); 5715 } 5716 } 5717} 5718 5719static void 5720hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5721{ 5722 nid_t *nids; 5723 5724 if (pcnt > 0) { 5725 device_printf(sc->dev, "\n"); 5726 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5727 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5728 sc->play.supp_pcm_size_rate); 5729 device_printf(sc->dev, " DAC:"); 5730 for (nids = sc->play.io; *nids != -1; nids++) 5731 printf(" %d", *nids); 5732 printf("\n"); 5733 } 5734 5735 if (rcnt > 0) { 5736 device_printf(sc->dev, "\n"); 5737 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5738 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5739 sc->rec.supp_pcm_size_rate); 5740 device_printf(sc->dev, " ADC:"); 5741 for (nids = sc->rec.io; *nids != -1; nids++) 5742 printf(" %d", *nids); 5743 printf("\n"); 5744 } 5745} 5746 5747static void 5748hdac_release_resources(struct hdac_softc *sc) 5749{ 5750 struct hdac_devinfo *devinfo = NULL; 5751 device_t *devlist = NULL; 5752 int i, devcount; 5753 5754 if (sc == NULL) 5755 return; 5756 5757 hdac_lock(sc); 5758 sc->polling = 0; 5759 sc->poll_ival = 0; 5760 callout_stop(&sc->poll_hda); 5761 callout_stop(&sc->poll_hdac); 5762 callout_stop(&sc->poll_jack); 5763 hdac_reset(sc); 5764 hdac_unlock(sc); 5765 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5766 callout_drain(&sc->poll_hda); 5767 callout_drain(&sc->poll_hdac); 5768 callout_drain(&sc->poll_jack); 5769 5770 hdac_irq_free(sc); 5771 5772 device_get_children(sc->dev, &devlist, &devcount); 5773 for (i = 0; devlist != NULL && i < devcount; i++) { 5774 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5775 if (devinfo == NULL) 5776 continue; 5777 if (devinfo->widget != NULL) 5778 free(devinfo->widget, M_HDAC); 5779 if (devinfo->node_type == 5780 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5781 devinfo->function.audio.ctl != NULL) 5782 free(devinfo->function.audio.ctl, M_HDAC); 5783 free(devinfo, M_HDAC); 5784 device_delete_child(sc->dev, devlist[i]); 5785 } 5786 if (devlist != NULL) 5787 free(devlist, M_TEMP); 5788 5789 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5790 if (sc->codecs[i] != NULL) 5791 free(sc->codecs[i], M_HDAC); 5792 sc->codecs[i] = NULL; 5793 } 5794 5795 hdac_dma_free(sc, &sc->pos_dma); 5796 hdac_dma_free(sc, &sc->rirb_dma); 5797 hdac_dma_free(sc, &sc->corb_dma); 5798 if (sc->play.blkcnt > 0) 5799 hdac_dma_free(sc, &sc->play.bdl_dma); 5800 if (sc->rec.blkcnt > 0) 5801 hdac_dma_free(sc, &sc->rec.bdl_dma); 5802 if (sc->chan_dmat != NULL) { 5803 bus_dma_tag_destroy(sc->chan_dmat); 5804 sc->chan_dmat = NULL; 5805 } 5806 hdac_mem_free(sc); 5807 snd_mtxfree(sc->lock); 5808 free(sc, M_DEVBUF); 5809} 5810 5811/* This function surely going to make its way into upper level someday. */ 5812static void 5813hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5814{ 5815 const char *res = NULL; 5816 int i = 0, j, k, len, inv; 5817 5818 if (on != NULL) 5819 *on = 0; 5820 if (off != NULL) 5821 *off = 0; 5822 if (sc == NULL) 5823 return; 5824 if (resource_string_value(device_get_name(sc->dev), 5825 device_get_unit(sc->dev), "config", &res) != 0) 5826 return; 5827 if (!(res != NULL && strlen(res) > 0)) 5828 return; 5829 HDA_BOOTVERBOSE( 5830 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5831 ); 5832 for (;;) { 5833 while (res[i] != '\0' && 5834 (res[i] == ',' || isspace(res[i]) != 0)) 5835 i++; 5836 if (res[i] == '\0') { 5837 HDA_BOOTVERBOSE( 5838 printf("\n"); 5839 ); 5840 return; 5841 } 5842 j = i; 5843 while (res[j] != '\0' && 5844 !(res[j] == ',' || isspace(res[j]) != 0)) 5845 j++; 5846 len = j - i; 5847 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5848 inv = 2; 5849 else 5850 inv = 0; 5851 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5852 if (strncmp(res + i + inv, 5853 hdac_quirks_tab[k].key, len - inv) != 0) 5854 continue; 5855 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5856 break; 5857 HDA_BOOTVERBOSE( 5858 printf(" %s%s", (inv != 0) ? "no" : "", 5859 hdac_quirks_tab[k].key); 5860 ); 5861 if (inv == 0 && on != NULL) 5862 *on |= hdac_quirks_tab[k].value; 5863 else if (inv != 0 && off != NULL) 5864 *off |= hdac_quirks_tab[k].value; 5865 break; 5866 } 5867 i = j; 5868 } 5869} 5870 5871#ifdef SND_DYNSYSCTL 5872static int 5873sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5874{ 5875 struct hdac_softc *sc; 5876 struct hdac_devinfo *devinfo; 5877 device_t dev; 5878 uint32_t ctl; 5879 int err, val; 5880 5881 dev = oidp->oid_arg1; 5882 devinfo = pcm_getdevinfo(dev); 5883 if (devinfo == NULL || devinfo->codec == NULL || 5884 devinfo->codec->sc == NULL) 5885 return (EINVAL); 5886 sc = devinfo->codec->sc; 5887 hdac_lock(sc); 5888 val = sc->polling; 5889 hdac_unlock(sc); 5890 err = sysctl_handle_int(oidp, &val, 0, req); 5891 5892 if (err != 0 || req->newptr == NULL) 5893 return (err); 5894 if (val < 0 || val > 1) 5895 return (EINVAL); 5896 5897 hdac_lock(sc); 5898 if (val != sc->polling) { 5899 if (hda_chan_active(sc) != 0) 5900 err = EBUSY; 5901 else if (val == 0) { 5902 callout_stop(&sc->poll_hdac); 5903 hdac_unlock(sc); 5904 callout_drain(&sc->poll_hdac); 5905 hdac_lock(sc); 5906 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5907 sc->rirb_size / 2); 5908 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5909 ctl |= HDAC_RIRBCTL_RINTCTL; 5910 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5911 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5912 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5913 sc->polling = 0; 5914 DELAY(1000); 5915 } else { 5916 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5917 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5918 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5919 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5920 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5921 hdac_unlock(sc); 5922 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5923 hdac_lock(sc); 5924 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5925 sc); 5926 sc->polling = 1; 5927 DELAY(1000); 5928 } 5929 } 5930 hdac_unlock(sc); 5931 5932 return (err); 5933} 5934 5935static int 5936sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5937{ 5938 struct hdac_softc *sc; 5939 struct hdac_devinfo *devinfo; 5940 device_t dev; 5941 int err, val; 5942 5943 dev = oidp->oid_arg1; 5944 devinfo = pcm_getdevinfo(dev); 5945 if (devinfo == NULL || devinfo->codec == NULL || 5946 devinfo->codec->sc == NULL) 5947 return (EINVAL); 5948 sc = devinfo->codec->sc; 5949 hdac_lock(sc); 5950 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5951 hdac_unlock(sc); 5952 err = sysctl_handle_int(oidp, &val, 0, req); 5953 5954 if (err != 0 || req->newptr == NULL) 5955 return (err); 5956 5957 if (val < 1) 5958 val = 1; 5959 if (val > 5000) 5960 val = 5000; 5961 val = ((uint64_t)val * hz) / 1000; 5962 if (val < 1) 5963 val = 1; 5964 if (val > (hz * 5)) 5965 val = hz * 5; 5966 5967 hdac_lock(sc); 5968 sc->poll_ival = val; 5969 hdac_unlock(sc); 5970 5971 return (err); 5972} 5973 5974#ifdef SND_DEBUG 5975static int 5976sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 5977{ 5978 struct hdac_softc *sc; 5979 struct hdac_devinfo *devinfo; 5980 struct hdac_widget *w; 5981 device_t dev; 5982 uint32_t res, pincap, timeout; 5983 int i, err, val; 5984 nid_t cad; 5985 5986 dev = oidp->oid_arg1; 5987 devinfo = pcm_getdevinfo(dev); 5988 if (devinfo == NULL || devinfo->codec == NULL || 5989 devinfo->codec->sc == NULL) 5990 return (EINVAL); 5991 val = 0; 5992 err = sysctl_handle_int(oidp, &val, 0, req); 5993 if (err != 0 || req->newptr == NULL || val == 0) 5994 return (err); 5995 sc = devinfo->codec->sc; 5996 cad = devinfo->codec->cad; 5997 hdac_lock(sc); 5998 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 5999 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6000 w = hdac_widget_get(devinfo, i); 6001 if (w == NULL || w->type != 6002 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6003 continue; 6004 pincap = w->wclass.pin.cap; 6005 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 6006 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 6007 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 6008 timeout = 10000; 6009 hdac_command(sc, 6010 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 6011 do { 6012 res = hdac_command(sc, 6013 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 6014 if (res != 0x7fffffff) 6015 break; 6016 DELAY(10); 6017 } while (--timeout != 0); 6018 } else { 6019 timeout = -1; 6020 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 6021 w->nid), cad); 6022 } 6023 device_printf(dev, 6024 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 6025 w->nid, timeout, res, 6026 (w->enable == 0) ? "DISABLED" : "ENABLED"); 6027 } 6028 device_printf(dev, 6029 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6030 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6031 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6032 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6033 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6034 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6035 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6036 device_printf(dev, " GPI:"); 6037 res = hdac_command(sc, 6038 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6039 printf(" data=0x%08x", res); 6040 res = hdac_command(sc, 6041 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6042 cad); 6043 printf(" wake=0x%08x", res); 6044 res = hdac_command(sc, 6045 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6046 cad); 6047 printf(" unsol=0x%08x", res); 6048 res = hdac_command(sc, 6049 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6050 printf(" sticky=0x%08x\n", res); 6051 } 6052 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6053 device_printf(dev, " GPO:"); 6054 res = hdac_command(sc, 6055 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6056 printf(" data=0x%08x\n", res); 6057 } 6058 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6059 device_printf(dev, "GPI0:"); 6060 res = hdac_command(sc, 6061 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6062 printf(" data=0x%08x", res); 6063 res = hdac_command(sc, 6064 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6065 printf(" enable=0x%08x", res); 6066 res = hdac_command(sc, 6067 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6068 printf(" direction=0x%08x\n", res); 6069 res = hdac_command(sc, 6070 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6071 device_printf(dev, " wake=0x%08x", res); 6072 res = hdac_command(sc, 6073 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6074 cad); 6075 printf(" unsol=0x%08x", res); 6076 res = hdac_command(sc, 6077 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6078 printf(" sticky=0x%08x\n", res); 6079 } 6080 hdac_unlock(sc); 6081 return (0); 6082} 6083#endif 6084#endif 6085 6086static void 6087hdac_attach2(void *arg) 6088{ 6089 struct hdac_softc *sc; 6090 struct hdac_widget *w; 6091 struct hdac_audio_ctl *ctl; 6092 uint32_t quirks_on, quirks_off; 6093 int pcnt, rcnt, codec_index; 6094 int i; 6095 char status[SND_STATUSLEN]; 6096 device_t *devlist = NULL; 6097 int devcount; 6098 struct hdac_devinfo *devinfo = NULL; 6099 6100 sc = (struct hdac_softc *)arg; 6101 6102 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6103 6104 HDA_BOOTVERBOSE( 6105 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6106 quirks_on, quirks_off); 6107 ); 6108 6109 if (resource_int_value(device_get_name(sc->dev), 6110 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6111 switch (sc->pci_subvendor) { 6112 case GB_G33S2H_SUBVENDOR: 6113 codec_index = 2; 6114 break; 6115 default: 6116 codec_index = 0; 6117 break; 6118 } 6119 } 6120 6121 hdac_lock(sc); 6122 6123 /* Remove ourselves from the config hooks */ 6124 if (sc->intrhook.ich_func != NULL) { 6125 config_intrhook_disestablish(&sc->intrhook); 6126 sc->intrhook.ich_func = NULL; 6127 } 6128 6129 /* Start the corb and rirb engines */ 6130 HDA_BOOTVERBOSE( 6131 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6132 ); 6133 hdac_corb_start(sc); 6134 HDA_BOOTVERBOSE( 6135 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6136 ); 6137 hdac_rirb_start(sc); 6138 6139 HDA_BOOTVERBOSE( 6140 device_printf(sc->dev, 6141 "HDA_DEBUG: Enabling controller interrupt...\n"); 6142 ); 6143 if (sc->polling == 0) 6144 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6145 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6146 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6147 HDAC_GCTL_UNSOL); 6148 6149 DELAY(1000); 6150 6151 HDA_BOOTVERBOSE( 6152 device_printf(sc->dev, 6153 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6154 codec_index); 6155 ); 6156 hdac_scan_codecs(sc, codec_index); 6157 6158 device_get_children(sc->dev, &devlist, &devcount); 6159 for (i = 0; devlist != NULL && i < devcount; i++) { 6160 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6161 if (devinfo != NULL && devinfo->node_type == 6162 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6163 break; 6164 } else 6165 devinfo = NULL; 6166 } 6167 if (devlist != NULL) 6168 free(devlist, M_TEMP); 6169 6170 if (devinfo == NULL) { 6171 hdac_unlock(sc); 6172 device_printf(sc->dev, "Audio Function Group not found!\n"); 6173 hdac_release_resources(sc); 6174 return; 6175 } 6176 6177 HDA_BOOTVERBOSE( 6178 device_printf(sc->dev, 6179 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6180 devinfo->nid, devinfo->codec->cad); 6181 ); 6182 hdac_audio_parse(devinfo); 6183 HDA_BOOTVERBOSE( 6184 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6185 ); 6186 hdac_audio_ctl_parse(devinfo); 6187 HDA_BOOTVERBOSE( 6188 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6189 ); 6190 hdac_vendor_patch_parse(devinfo); 6191 if (quirks_on != 0) 6192 devinfo->function.audio.quirks |= quirks_on; 6193 if (quirks_off != 0) 6194 devinfo->function.audio.quirks &= ~quirks_off; 6195 6196 /* XXX Disable all DIGITAL path. */ 6197 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6198 w = hdac_widget_get(devinfo, i); 6199 if (w == NULL) 6200 continue; 6201 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6202 w->enable = 0; 6203 continue; 6204 } 6205 /* XXX Disable useless pin ? */ 6206 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6207 (w->wclass.pin.config & 6208 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6209 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6210 w->enable = 0; 6211 } 6212 i = 0; 6213 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6214 if (ctl->widget == NULL) 6215 continue; 6216 if (ctl->ossmask & SOUND_MASK_DISABLE) 6217 ctl->enable = 0; 6218 w = ctl->widget; 6219 if (w->enable == 0 || 6220 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6221 ctl->enable = 0; 6222 w = ctl->childwidget; 6223 if (w == NULL) 6224 continue; 6225 if (w->enable == 0 || 6226 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6227 ctl->enable = 0; 6228 } 6229 6230 HDA_BOOTVERBOSE( 6231 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6232 ); 6233 hdac_audio_build_tree(devinfo); 6234 6235 i = 0; 6236 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6237 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6238 ctl->ossmask = 0; 6239 } 6240 HDA_BOOTVERBOSE( 6241 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6242 ); 6243 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6244 HDA_BOOTVERBOSE( 6245 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6246 ); 6247 hdac_audio_ctl_commit(devinfo); 6248 6249 HDA_BOOTVERBOSE( 6250 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6251 ); 6252 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6253 HDA_BOOTVERBOSE( 6254 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6255 ); 6256 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6257 6258 hdac_unlock(sc); 6259 HDA_BOOTVERBOSE( 6260 device_printf(sc->dev, 6261 "HDA_DEBUG: OSS mixer initialization...\n"); 6262 ); 6263 6264 /* 6265 * There is no point of return after this. If the driver failed, 6266 * so be it. Let the detach procedure do all the cleanup. 6267 */ 6268 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6269 device_printf(sc->dev, "Can't register mixer\n"); 6270 6271 if (pcnt > 0) 6272 pcnt = 1; 6273 if (rcnt > 0) 6274 rcnt = 1; 6275 6276 HDA_BOOTVERBOSE( 6277 device_printf(sc->dev, 6278 "HDA_DEBUG: Registering PCM channels...\n"); 6279 ); 6280 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6281 device_printf(sc->dev, "Can't register PCM\n"); 6282 6283 sc->registered++; 6284 6285 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6286 hdac_dma_alloc(sc, &sc->pos_dma, 6287 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6288 HDA_BOOTVERBOSE( 6289 device_printf(sc->dev, 6290 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6291 ); 6292 } 6293 6294 for (i = 0; i < pcnt; i++) 6295 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6296 for (i = 0; i < rcnt; i++) 6297 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6298 6299#ifdef SND_DYNSYSCTL 6300 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6301 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6302 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6303 sysctl_hdac_polling, "I", "Enable polling mode"); 6304 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6305 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6306 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6307 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6308 "Controller/Jack Sense polling interval (1-1000 ms)"); 6309#ifdef SND_DEBUG 6310 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6311 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6312 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6313 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6314#endif 6315#endif 6316 6317 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6318 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6319 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6320 pcm_setstatus(sc->dev, status); 6321 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6322 HDA_BOOTVERBOSE( 6323 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6324 hdac_codec_id(devinfo)); 6325 ); 6326 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6327 HDA_DRV_TEST_REV); 6328 6329 HDA_BOOTVERBOSE( 6330 if (devinfo->function.audio.quirks != 0) { 6331 device_printf(sc->dev, "\n"); 6332 device_printf(sc->dev, "HDA config/quirks:"); 6333 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6334 if ((devinfo->function.audio.quirks & 6335 hdac_quirks_tab[i].value) == 6336 hdac_quirks_tab[i].value) 6337 printf(" %s", hdac_quirks_tab[i].key); 6338 } 6339 printf("\n"); 6340 } 6341 device_printf(sc->dev, "\n"); 6342 device_printf(sc->dev, "+-------------------+\n"); 6343 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6344 device_printf(sc->dev, "+-------------------+\n"); 6345 hdac_dump_nodes(devinfo); 6346 device_printf(sc->dev, "\n"); 6347 device_printf(sc->dev, "+------------------------+\n"); 6348 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6349 device_printf(sc->dev, "+------------------------+\n"); 6350 device_printf(sc->dev, "\n"); 6351 i = 0; 6352 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6353 device_printf(sc->dev, "%3d: nid=%d", i, 6354 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6355 if (ctl->childwidget != NULL) 6356 printf(" cnid=%d", ctl->childwidget->nid); 6357 printf(" dir=0x%x index=%d " 6358 "ossmask=0x%08x ossdev=%d%s\n", 6359 ctl->dir, ctl->index, 6360 ctl->ossmask, ctl->ossdev, 6361 (ctl->enable == 0) ? " [DISABLED]" : ""); 6362 } 6363 device_printf(sc->dev, "\n"); 6364 device_printf(sc->dev, "+-----------------------------------+\n"); 6365 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6366 device_printf(sc->dev, "+-----------------------------------+\n"); 6367 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6368 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6369 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6370 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6371 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6372 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6373 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6374 hdac_dump_ctls(devinfo, NULL, 0); 6375 hdac_dump_dac(devinfo); 6376 hdac_dump_adc(devinfo); 6377 device_printf(sc->dev, "\n"); 6378 device_printf(sc->dev, "+--------------------------------------+\n"); 6379 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6380 device_printf(sc->dev, "+--------------------------------------+\n"); 6381 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6382 ); 6383 6384 if (sc->polling != 0) { 6385 hdac_lock(sc); 6386 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6387 hdac_unlock(sc); 6388 } 6389} 6390 6391/**************************************************************************** 6392 * int hdac_detach(device_t) 6393 * 6394 * Detach and free up resources utilized by the hdac device. 6395 ****************************************************************************/ 6396static int 6397hdac_detach(device_t dev) 6398{ 6399 struct hdac_softc *sc = NULL; 6400 struct hdac_devinfo *devinfo = NULL; 6401 int err; 6402 6403 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6404 if (devinfo != NULL && devinfo->codec != NULL) 6405 sc = devinfo->codec->sc; 6406 if (sc == NULL) 6407 return (0); 6408 6409 if (sc->registered > 0) { 6410 err = pcm_unregister(dev); 6411 if (err != 0) 6412 return (err); 6413 } 6414 6415 hdac_release_resources(sc); 6416 6417 return (0); 6418} 6419 6420static device_method_t hdac_methods[] = { 6421 /* device interface */ 6422 DEVMETHOD(device_probe, hdac_probe), 6423 DEVMETHOD(device_attach, hdac_attach), 6424 DEVMETHOD(device_detach, hdac_detach), 6425 { 0, 0 } 6426}; 6427 6428static driver_t hdac_driver = { 6429 "pcm", 6430 hdac_methods, 6431 PCM_SOFTC_SIZE, 6432}; 6433 6434DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6435MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6436MODULE_VERSION(snd_hda, 1); 6437