hdac.c revision 172811
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sys/ctype.h> 75#include <sys/taskqueue.h> 76 77#include <dev/sound/pci/hda/hdac_private.h> 78#include <dev/sound/pci/hda/hdac_reg.h> 79#include <dev/sound/pci/hda/hda_reg.h> 80#include <dev/sound/pci/hda/hdac.h> 81 82#include "mixer_if.h" 83 84#define HDA_DRV_TEST_REV "20071020_0048" 85#define HDA_WIDGET_PARSER_REV 1 86 87SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 172811 2007-10-19 15:49:39Z ariff $"); 88 89#define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93} while(0) 94 95#if 1 96#undef HDAC_INTR_EXTRA 97#define HDAC_INTR_EXTRA 1 98#endif 99 100#define hdac_lock(sc) snd_mtxlock((sc)->lock) 101#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103#define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 106#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 107 (fl) == 0xffffffff || \ 108 (((fl) & 0xffff0000) == 0xffff0000 && \ 109 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 110 (((fl) & 0x0000ffff) == 0x0000ffff && \ 111 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 112#define HDA_MATCH_ALL 0xffffffff 113#define HDAC_INVALID 0xffffffff 114 115/* Default controller / jack sense poll: 250ms */ 116#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 117 118/* 119 * Make room for possible 4096 playback/record channels, in 100 years to come. 120 */ 121#define HDAC_TRIGGER_NONE 0x00000000 122#define HDAC_TRIGGER_PLAY 0x00000fff 123#define HDAC_TRIGGER_REC 0x00fff000 124#define HDAC_TRIGGER_UNSOL 0x80000000 125 126#define HDA_MODEL_CONSTRUCT(vendor, model) \ 127 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 128 129/* Controller models */ 130 131/* Intel */ 132#define INTEL_VENDORID 0x8086 133#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 134#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 135#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 136#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 137#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 138#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 139 140/* Nvidia */ 141#define NVIDIA_VENDORID 0x10de 142#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 143#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 144#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 145#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 146#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 147#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 148#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 149 150/* ATI */ 151#define ATI_VENDORID 0x1002 152#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 153#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 154#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 155 156/* VIA */ 157#define VIA_VENDORID 0x1106 158#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 159#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 160 161/* SiS */ 162#define SIS_VENDORID 0x1039 163#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 164#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 165 166/* OEM/subvendors */ 167 168/* Intel */ 169#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 170 171/* HP/Compaq */ 172#define HP_VENDORID 0x103c 173#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 174#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 175#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 176#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 177#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 178#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 179#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 180#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 181#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 182/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 183#define HP_NX6325_SUBVENDORX 0x103c30b0 184 185/* Dell */ 186#define DELL_VENDORID 0x1028 187#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 188#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 189#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 190#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 191#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 192 193/* Clevo */ 194#define CLEVO_VENDORID 0x1558 195#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 196#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 197 198/* Acer */ 199#define ACER_VENDORID 0x1025 200#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 201#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 202#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 203 204/* Asus */ 205#define ASUS_VENDORID 0x1043 206#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 207#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 208#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 209#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 210#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 211#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 212#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 213#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 214#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 215#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 216#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 217#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 218#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 219#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 220#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 221 222/* IBM / Lenovo */ 223#define IBM_VENDORID 0x1014 224#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 225#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 226 227/* Lenovo */ 228#define LENOVO_VENDORID 0x17aa 229#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 230#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 231#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 232 233/* Samsung */ 234#define SAMSUNG_VENDORID 0x144d 235#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 236#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 237 238/* Medion ? */ 239#define MEDION_VENDORID 0x161f 240#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 241#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 242 243/* 244 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 245 * instead of their own, which is beyond my comprehension 246 * (see HDA_CODEC_STAC9221 below). 247 */ 248#define APPLE_INTEL_MAC 0x76808384 249 250/* LG Electronics */ 251#define LG_VENDORID 0x1854 252#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 253#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 254 255/* Fujitsu Siemens */ 256#define FS_VENDORID 0x1734 257#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 258#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 259#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 260 261/* Fujitsu Limited */ 262#define FL_VENDORID 0x10cf 263#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 264#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 265 266/* Toshiba */ 267#define TOSHIBA_VENDORID 0x1179 268#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 269#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 270 271/* Micro-Star International (MSI) */ 272#define MSI_VENDORID 0x1462 273#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 274#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 275#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 276 277/* Giga-Byte Technology */ 278#define GB_VENDORID 0x1458 279#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 280#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 281 282/* Uniwill ? */ 283#define UNIWILL_VENDORID 0x1584 284#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 285#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 286 287 288/* Misc constants.. */ 289#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 290#define HDA_AMP_MUTE_NONE (0) 291#define HDA_AMP_MUTE_LEFT (1 << 0) 292#define HDA_AMP_MUTE_RIGHT (1 << 1) 293#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 294 295#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 296#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 297 298#define HDA_DAC_PATH (1 << 0) 299#define HDA_ADC_PATH (1 << 1) 300#define HDA_ADC_RECSEL (1 << 2) 301 302#define HDA_DAC_LOCKED (1 << 3) 303#define HDA_ADC_LOCKED (1 << 4) 304 305#define HDA_CTL_OUT (1 << 0) 306#define HDA_CTL_IN (1 << 1) 307#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 308 309#define HDA_GPIO_MAX 8 310/* 0 - 7 = GPIO , 8 = Flush */ 311#define HDA_QUIRK_GPIO0 (1 << 0) 312#define HDA_QUIRK_GPIO1 (1 << 1) 313#define HDA_QUIRK_GPIO2 (1 << 2) 314#define HDA_QUIRK_GPIO3 (1 << 3) 315#define HDA_QUIRK_GPIO4 (1 << 4) 316#define HDA_QUIRK_GPIO5 (1 << 5) 317#define HDA_QUIRK_GPIO6 (1 << 6) 318#define HDA_QUIRK_GPIO7 (1 << 7) 319#define HDA_QUIRK_GPIOFLUSH (1 << 8) 320 321/* 9 - 25 = anything else */ 322#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 323#define HDA_QUIRK_FIXEDRATE (1 << 10) 324#define HDA_QUIRK_FORCESTEREO (1 << 11) 325#define HDA_QUIRK_EAPDINV (1 << 12) 326#define HDA_QUIRK_DMAPOS (1 << 13) 327 328/* 26 - 31 = vrefs */ 329#define HDA_QUIRK_IVREF50 (1 << 26) 330#define HDA_QUIRK_IVREF80 (1 << 27) 331#define HDA_QUIRK_IVREF100 (1 << 28) 332#define HDA_QUIRK_OVREF50 (1 << 29) 333#define HDA_QUIRK_OVREF80 (1 << 30) 334#define HDA_QUIRK_OVREF100 (1 << 31) 335 336#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 337 HDA_QUIRK_IVREF100) 338#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 339 HDA_QUIRK_OVREF100) 340#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 341 342#define SOUND_MASK_SKIP (1 << 30) 343#define SOUND_MASK_DISABLE (1 << 31) 344 345#if __FreeBSD_version < 600000 346#define taskqueue_drain(...) 347#endif 348 349static const struct { 350 char *key; 351 uint32_t value; 352} hdac_quirks_tab[] = { 353 { "gpio0", HDA_QUIRK_GPIO0 }, 354 { "gpio1", HDA_QUIRK_GPIO1 }, 355 { "gpio2", HDA_QUIRK_GPIO2 }, 356 { "gpio3", HDA_QUIRK_GPIO3 }, 357 { "gpio4", HDA_QUIRK_GPIO4 }, 358 { "gpio5", HDA_QUIRK_GPIO5 }, 359 { "gpio6", HDA_QUIRK_GPIO6 }, 360 { "gpio7", HDA_QUIRK_GPIO7 }, 361 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 362 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 363 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 364 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 365 { "eapdinv", HDA_QUIRK_EAPDINV }, 366 { "dmapos", HDA_QUIRK_DMAPOS }, 367 { "ivref50", HDA_QUIRK_IVREF50 }, 368 { "ivref80", HDA_QUIRK_IVREF80 }, 369 { "ivref100", HDA_QUIRK_IVREF100 }, 370 { "ovref50", HDA_QUIRK_OVREF50 }, 371 { "ovref80", HDA_QUIRK_OVREF80 }, 372 { "ovref100", HDA_QUIRK_OVREF100 }, 373 { "ivref", HDA_QUIRK_IVREF }, 374 { "ovref", HDA_QUIRK_OVREF }, 375 { "vref", HDA_QUIRK_VREF }, 376}; 377#define HDAC_QUIRKS_TAB_LEN \ 378 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 379 380#define HDA_BDL_MIN 2 381#define HDA_BDL_MAX 256 382#define HDA_BDL_DEFAULT HDA_BDL_MIN 383 384#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 385#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 386 387#define HDA_BUFSZ_MIN 4096 388#define HDA_BUFSZ_MAX 65536 389#define HDA_BUFSZ_DEFAULT 16384 390 391#define HDA_PARSE_MAXDEPTH 10 392 393#define HDAC_UNSOLTAG_EVENT_HP 0x00 394#define HDAC_UNSOLTAG_EVENT_TEST 0x01 395 396MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 397 398enum { 399 HDA_PARSE_MIXER, 400 HDA_PARSE_DIRECT 401}; 402 403/* Default */ 404static uint32_t hdac_fmt[] = { 405 AFMT_STEREO | AFMT_S16_LE, 406 0 407}; 408 409static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 410 411static const struct { 412 uint32_t model; 413 char *desc; 414} hdac_devices[] = { 415 { HDA_INTEL_82801F, "Intel 82801F" }, 416 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 417 { HDA_INTEL_82801G, "Intel 82801G" }, 418 { HDA_INTEL_82801H, "Intel 82801H" }, 419 { HDA_INTEL_82801I, "Intel 82801I" }, 420 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 421 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 422 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 423 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 424 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 425 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 426 { HDA_ATI_SB450, "ATI SB450" }, 427 { HDA_ATI_SB600, "ATI SB600" }, 428 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 429 { HDA_SIS_966, "SiS 966" }, 430 /* Unknown */ 431 { HDA_INTEL_ALL, "Intel (Unknown)" }, 432 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 433 { HDA_ATI_ALL, "ATI (Unknown)" }, 434 { HDA_VIA_ALL, "VIA (Unknown)" }, 435 { HDA_SIS_ALL, "SiS (Unknown)" }, 436}; 437#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 438 439static const struct { 440 uint16_t vendor; 441 uint8_t reg; 442 uint8_t mask; 443 uint8_t enable; 444} hdac_pcie_snoop[] = { 445 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 446 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 447 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 448}; 449#define HDAC_PCIESNOOP_LEN \ 450 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 451 452static const struct { 453 uint32_t rate; 454 int valid; 455 uint16_t base; 456 uint16_t mul; 457 uint16_t div; 458} hda_rate_tab[] = { 459 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 460 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 461 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 462 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 463 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 464 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 465 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 466 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 467 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 468 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 469 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 470 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 471 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 472 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 473 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 474 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 475 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 476 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 477 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 478 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 479 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 480 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 481 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 482 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 483 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 484 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 485 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 486 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 487 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 488 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 489 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 490 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 491 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 492 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 493 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 494}; 495#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 496 497/* All codecs you can eat... */ 498#define HDA_CODEC_CONSTRUCT(vendor, id) \ 499 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 500 501/* Realtek */ 502#define REALTEK_VENDORID 0x10ec 503#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 504#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 505#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 506#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 507#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 508#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 509#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 510#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 511#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 512#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 513#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 514#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 515 516/* Analog Devices */ 517#define ANALOGDEVICES_VENDORID 0x11d4 518#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 519#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 520#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 521#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 522#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 523#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 524 525/* CMedia */ 526#define CMEDIA_VENDORID 0x434d 527#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 528#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 529 530/* Sigmatel */ 531#define SIGMATEL_VENDORID 0x8384 532#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 533#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 534#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 535#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 536#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 537#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 538#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 539 540/* 541 * Conexant 542 * 543 * Ok, the truth is, I don't have any idea at all whether 544 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 545 * place that tell me it is "Venice" is from its Windows driver INF. 546 * 547 * Venice - CX????? 548 * Waikiki - CX20551-22 549 */ 550#define CONEXANT_VENDORID 0x14f1 551#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 552#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 553#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 554 555/* VIA */ 556#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 557#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 558#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 559#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 560#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 561#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 562#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 563#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 564#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 565#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 566#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 567#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 568#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 569 570 571/* Codecs */ 572static const struct { 573 uint32_t id; 574 char *name; 575} hdac_codecs[] = { 576 { HDA_CODEC_ALC260, "Realtek ALC260" }, 577 { HDA_CODEC_ALC262, "Realtek ALC262" }, 578 { HDA_CODEC_ALC268, "Realtek ALC268" }, 579 { HDA_CODEC_ALC660, "Realtek ALC660" }, 580 { HDA_CODEC_ALC861, "Realtek ALC861" }, 581 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 582 { HDA_CODEC_ALC880, "Realtek ALC880" }, 583 { HDA_CODEC_ALC882, "Realtek ALC882" }, 584 { HDA_CODEC_ALC883, "Realtek ALC883" }, 585 { HDA_CODEC_ALC885, "Realtek ALC885" }, 586 { HDA_CODEC_ALC888, "Realtek ALC888" }, 587 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 588 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 589 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 590 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 591 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 592 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 593 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 594 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 595 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 596 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 597 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 598 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 599 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 600 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 601 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 602 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 603 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 604 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 605 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 606 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 607 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 608 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 609 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 610 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 611 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 612 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 613 /* Unknown codec */ 614 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 615 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 616 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 617 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 618 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 619 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 620}; 621#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 622 623enum { 624 HDAC_HP_SWITCH_CTL, 625 HDAC_HP_SWITCH_CTRL, 626 HDAC_HP_SWITCH_DEBUG 627}; 628 629static const struct { 630 uint32_t model; 631 uint32_t id; 632 int type; 633 int inverted; 634 int polling; 635 int execsense; 636 nid_t hpnid; 637 nid_t spkrnid[8]; 638 nid_t eapdnid; 639} hdac_hp_switch[] = { 640 /* Specific OEM models */ 641 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 642 0, 0, -1, 17, { 16, -1 }, 16 }, 643 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 644 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 645 /* { HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 646 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 }, */ 647 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 648 0, 0, -1, 6, { 5, -1 }, 5 }, 649 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 650 0, 0, -1, 6, { 5, -1 }, 5 }, 651 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 652 0, 0, -1, 6, { 5, -1 }, 5 }, 653 /* { HP_DC7700_SUBVENDOR, HDA_CODEC_ALC262, HDAC_HP_SWITCH_CTL, 654 0, 0, -1, 21, { 22, 27, -1 }, -1 }, */ 655 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 656 0, 0, -1, 6, { 5, -1 }, -1 }, 657 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 658 0, 0, -1, 13, { 14, -1 }, -1 }, 659 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 660 0, 0, -1, 13, { 14, -1 }, -1 }, 661 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 662 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 663 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 664 0, 0, -1, 10, { 13, -1 }, -1 }, 665 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 666 1, 0, -1, 26, { 27, -1 }, -1 }, 667 /* { LENOVO_TCA55_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 668 0, 0, -1, 26, { 27, 28, 29, 30, -1 }, -1 }, */ 669 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 670 0, 0, -1, 27, { 20, -1 }, -1 }, 671 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 672 0, 0, -1, 20, { 21, -1 }, -1 }, 673 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 674 0, 0, -1, 20, { 21, -1 }, -1 }, 675 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 676 0, 0, -1, 20, { 21, -1 }, -1 }, 677 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 678 0, 0, -1, 20, { 27, -1 }, -1 }, 679 { MSI_MS034A_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 680 0, 0, -1, 20, { 27, -1 }, -1 }, 681 { FS_SI1848_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 682 0, 0, -1, 20, { 21, -1 }, -1 }, 683 { FL_S7020D_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 684 0, 0, -1, 20, { 16, -1 }, -1 }, 685 /* 686 * All models that at least come from the same vendor with 687 * simmilar codec. 688 */ 689 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 690 0, 0, -1, 17, { 16, -1 }, 16 }, 691 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 692 0, 0, -1, 6, { 5, -1 }, 5 }, 693 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 694 0, 0, -1, 6, { 5, -1 }, -1 }, 695 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 696 0, 0, -1, 13, { 14, -1 }, -1 }, 697#if 0 698 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 699 1, 0, -1, 26, { 27, -1 }, -1 }, 700 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 701 0, 0, -1, 20, { 21, -1 }, -1 }, 702#endif 703}; 704#define HDAC_HP_SWITCH_LEN \ 705 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 706 707static const struct { 708 uint32_t model; 709 uint32_t id; 710 nid_t eapdnid; 711 int hp_switch; 712} hdac_eapd_switch[] = { 713 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 714 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 715 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 716}; 717#define HDAC_EAPD_SWITCH_LEN \ 718 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 719 720/**************************************************************************** 721 * Function prototypes 722 ****************************************************************************/ 723static void hdac_intr_handler(void *); 724static int hdac_reset(struct hdac_softc *); 725static int hdac_get_capabilities(struct hdac_softc *); 726static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 727static int hdac_dma_alloc(struct hdac_softc *, 728 struct hdac_dma *, bus_size_t); 729static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 730static int hdac_mem_alloc(struct hdac_softc *); 731static void hdac_mem_free(struct hdac_softc *); 732static int hdac_irq_alloc(struct hdac_softc *); 733static void hdac_irq_free(struct hdac_softc *); 734static void hdac_corb_init(struct hdac_softc *); 735static void hdac_rirb_init(struct hdac_softc *); 736static void hdac_corb_start(struct hdac_softc *); 737static void hdac_rirb_start(struct hdac_softc *); 738static void hdac_scan_codecs(struct hdac_softc *, int); 739static int hdac_probe_codec(struct hdac_codec *); 740static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 741static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 742 743static void hdac_attach2(void *); 744 745static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 746 uint32_t, int); 747static void hdac_command_send_internal(struct hdac_softc *, 748 struct hdac_command_list *, int); 749 750static int hdac_probe(device_t); 751static int hdac_attach(device_t); 752static int hdac_detach(device_t); 753static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 754static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 755 uint32_t, int, int); 756static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 757 nid_t, int, int); 758static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 759 nid_t, nid_t, int, int, int, int, int, int); 760static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 761static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 762 763static int hdac_rirb_flush(struct hdac_softc *sc); 764static int hdac_unsolq_flush(struct hdac_softc *sc); 765 766#define hdac_command(a1, a2, a3) \ 767 hdac_command_sendone_internal(a1, a2, a3) 768 769#define hdac_codec_id(d) \ 770 ((uint32_t)((d == NULL) ? 0x00000000 : \ 771 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 772 ((uint32_t)(d)->device_id & 0x0000ffff)))) 773 774static char * 775hdac_codec_name(struct hdac_devinfo *devinfo) 776{ 777 uint32_t id; 778 int i; 779 780 id = hdac_codec_id(devinfo); 781 782 for (i = 0; i < HDAC_CODECS_LEN; i++) { 783 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 784 return (hdac_codecs[i].name); 785 } 786 787 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 788} 789 790static char * 791hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 792{ 793 static char *ossname[] = SOUND_DEVICE_NAMES; 794 static char *unknown = "???"; 795 int i; 796 797 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 798 if (devmask & (1 << i)) 799 return (ossname[i]); 800 } 801 return (unknown); 802} 803 804static void 805hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 806{ 807 static char *ossname[] = SOUND_DEVICE_NAMES; 808 int i, first = 1; 809 810 bzero(buf, len); 811 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 812 if (mask & (1 << i)) { 813 if (first == 0) 814 strlcat(buf, ", ", len); 815 strlcat(buf, ossname[i], len); 816 first = 0; 817 } 818 } 819} 820 821static struct hdac_audio_ctl * 822hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 823{ 824 if (devinfo == NULL || 825 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 826 index == NULL || devinfo->function.audio.ctl == NULL || 827 devinfo->function.audio.ctlcnt < 1 || 828 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 829 return (NULL); 830 return (&devinfo->function.audio.ctl[(*index)++]); 831} 832 833static struct hdac_audio_ctl * 834hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 835 int index, int cnt) 836{ 837 struct hdac_audio_ctl *ctl, *retctl = NULL; 838 int i, at, atindex, found = 0; 839 840 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 841 return (NULL); 842 843 at = cnt; 844 if (at == 0) 845 at = 1; 846 else if (at < 0) 847 at = -1; 848 atindex = index; 849 if (atindex < 0) 850 atindex = -1; 851 852 i = 0; 853 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 854 if (ctl->enable == 0 || ctl->widget == NULL) 855 continue; 856 if (!(ctl->widget->nid == nid && (atindex == -1 || 857 ctl->index == atindex))) 858 continue; 859 found++; 860 if (found == cnt) 861 return (ctl); 862 retctl = ctl; 863 } 864 865 return ((at == -1) ? retctl : NULL); 866} 867 868static void 869hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 870{ 871 struct hdac_softc *sc; 872 struct hdac_widget *w; 873 struct hdac_audio_ctl *ctl; 874 uint32_t val, id, res; 875 int i = 0, j, timeout, forcemute; 876 nid_t cad; 877 878 if (devinfo == NULL || devinfo->codec == NULL || 879 devinfo->codec->sc == NULL) 880 return; 881 882 sc = devinfo->codec->sc; 883 cad = devinfo->codec->cad; 884 id = hdac_codec_id(devinfo); 885 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 886 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 887 sc->pci_subvendor) && 888 hdac_hp_switch[i].id == id) 889 break; 890 } 891 892 if (i >= HDAC_HP_SWITCH_LEN) 893 return; 894 895 forcemute = 0; 896 if (hdac_hp_switch[i].eapdnid != -1) { 897 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 898 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 899 forcemute = (w->param.eapdbtl & 900 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 901 } 902 903 if (hdac_hp_switch[i].execsense != -1) 904 hdac_command(sc, 905 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 906 hdac_hp_switch[i].execsense), cad); 907 908 timeout = 10000; 909 do { 910 res = hdac_command(sc, 911 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 912 cad); 913 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 914 break; 915 DELAY(10); 916 } while (--timeout != 0); 917 918 HDA_BOOTVERBOSE( 919 device_printf(sc->dev, 920 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 921 hdac_hp_switch[i].hpnid, timeout, res); 922 ); 923 924 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 925 res ^= hdac_hp_switch[i].inverted; 926 927 switch (hdac_hp_switch[i].type) { 928 case HDAC_HP_SWITCH_CTL: 929 ctl = hdac_audio_ctl_amp_get(devinfo, 930 hdac_hp_switch[i].hpnid, 0, 1); 931 if (ctl != NULL) { 932 val = (res != 0 && forcemute == 0) ? 933 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 934 if (val != ctl->muted) { 935 ctl->muted = val; 936 hdac_audio_ctl_amp_set(ctl, 937 HDA_AMP_MUTE_DEFAULT, ctl->left, 938 ctl->right); 939 } 940 } 941 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 942 ctl = hdac_audio_ctl_amp_get(devinfo, 943 hdac_hp_switch[i].spkrnid[j], 0, 1); 944 if (ctl == NULL) 945 continue; 946 val = (res != 0 || forcemute == 1) ? 947 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 948 if (val == ctl->muted) 949 continue; 950 ctl->muted = val; 951 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 952 ctl->left, ctl->right); 953 } 954 break; 955 case HDAC_HP_SWITCH_CTRL: 956 if (res != 0) { 957 /* HP in */ 958 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 959 if (w != NULL && w->type == 960 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 961 if (forcemute == 0) 962 val = w->wclass.pin.ctrl | 963 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 964 else 965 val = w->wclass.pin.ctrl & 966 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 967 if (val != w->wclass.pin.ctrl) { 968 w->wclass.pin.ctrl = val; 969 hdac_command(sc, 970 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 971 w->nid, w->wclass.pin.ctrl), cad); 972 } 973 } 974 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 975 w = hdac_widget_get(devinfo, 976 hdac_hp_switch[i].spkrnid[j]); 977 if (w == NULL || w->type != 978 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 979 continue; 980 val = w->wclass.pin.ctrl & 981 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 982 if (val == w->wclass.pin.ctrl) 983 continue; 984 w->wclass.pin.ctrl = val; 985 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 986 cad, w->nid, w->wclass.pin.ctrl), cad); 987 } 988 } else { 989 /* HP out */ 990 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 991 if (w != NULL && w->type == 992 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 993 val = w->wclass.pin.ctrl & 994 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 995 if (val != w->wclass.pin.ctrl) { 996 w->wclass.pin.ctrl = val; 997 hdac_command(sc, 998 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 999 w->nid, w->wclass.pin.ctrl), cad); 1000 } 1001 } 1002 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1003 w = hdac_widget_get(devinfo, 1004 hdac_hp_switch[i].spkrnid[j]); 1005 if (w == NULL || w->type != 1006 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1007 continue; 1008 if (forcemute == 0) 1009 val = w->wclass.pin.ctrl | 1010 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1011 else 1012 val = w->wclass.pin.ctrl & 1013 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1014 if (val == w->wclass.pin.ctrl) 1015 continue; 1016 w->wclass.pin.ctrl = val; 1017 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 1018 cad, w->nid, w->wclass.pin.ctrl), cad); 1019 } 1020 } 1021 break; 1022 case HDAC_HP_SWITCH_DEBUG: 1023 if (hdac_hp_switch[i].execsense != -1) 1024 hdac_command(sc, 1025 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 1026 hdac_hp_switch[i].execsense), cad); 1027 res = hdac_command(sc, 1028 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1029 device_printf(sc->dev, 1030 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1031 hdac_hp_switch[i].hpnid, res); 1032 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1033 w = hdac_widget_get(devinfo, 1034 hdac_hp_switch[i].spkrnid[j]); 1035 if (w == NULL || w->type != 1036 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1037 continue; 1038 if (hdac_hp_switch[i].execsense != -1) 1039 hdac_command(sc, 1040 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1041 hdac_hp_switch[i].execsense), cad); 1042 res = hdac_command(sc, 1043 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1044 device_printf(sc->dev, 1045 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1046 j + 1, w->nid, res); 1047 } 1048 break; 1049 default: 1050 break; 1051 } 1052} 1053 1054static void 1055hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1056{ 1057 struct hdac_softc *sc; 1058 struct hdac_devinfo *devinfo = NULL; 1059 device_t *devlist = NULL; 1060 int devcount, i; 1061 1062 if (codec == NULL || codec->sc == NULL) 1063 return; 1064 1065 sc = codec->sc; 1066 1067 HDA_BOOTVERBOSE( 1068 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1069 ); 1070 1071 device_get_children(sc->dev, &devlist, &devcount); 1072 for (i = 0; devlist != NULL && i < devcount; i++) { 1073 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1074 if (devinfo != NULL && devinfo->node_type == 1075 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1076 devinfo->codec != NULL && 1077 devinfo->codec->cad == codec->cad) { 1078 break; 1079 } else 1080 devinfo = NULL; 1081 } 1082 if (devlist != NULL) 1083 free(devlist, M_TEMP); 1084 1085 if (devinfo == NULL) 1086 return; 1087 1088 switch (tag) { 1089 case HDAC_UNSOLTAG_EVENT_HP: 1090 hdac_hp_switch_handler(devinfo); 1091 break; 1092 case HDAC_UNSOLTAG_EVENT_TEST: 1093 device_printf(sc->dev, "Unsol Test!\n"); 1094 break; 1095 default: 1096 break; 1097 } 1098} 1099 1100static int 1101hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1102{ 1103 /* XXX to be removed */ 1104#ifdef HDAC_INTR_EXTRA 1105 uint32_t res; 1106#endif 1107 1108 if (!(ch->flags & HDAC_CHN_RUNNING)) 1109 return (0); 1110 1111 /* XXX to be removed */ 1112#ifdef HDAC_INTR_EXTRA 1113 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1114#endif 1115 1116 /* XXX to be removed */ 1117#ifdef HDAC_INTR_EXTRA 1118 HDA_BOOTVERBOSE( 1119 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1120 device_printf(sc->dev, 1121 "PCMDIR_%s intr triggered beyond stream boundary:" 1122 "%08x\n", 1123 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1124 ); 1125#endif 1126 1127 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1128 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1129 1130 /* XXX to be removed */ 1131#ifdef HDAC_INTR_EXTRA 1132 if (res & HDAC_SDSTS_BCIS) { 1133#endif 1134 return (1); 1135 /* XXX to be removed */ 1136#ifdef HDAC_INTR_EXTRA 1137 } 1138#endif 1139 1140 return (0); 1141} 1142 1143/**************************************************************************** 1144 * void hdac_intr_handler(void *) 1145 * 1146 * Interrupt handler. Processes interrupts received from the hdac. 1147 ****************************************************************************/ 1148static void 1149hdac_intr_handler(void *context) 1150{ 1151 struct hdac_softc *sc; 1152 uint32_t intsts; 1153 uint8_t rirbsts; 1154 struct hdac_rirb *rirb_base; 1155 uint32_t trigger; 1156 1157 sc = (struct hdac_softc *)context; 1158 1159 hdac_lock(sc); 1160 if (sc->polling != 0) { 1161 hdac_unlock(sc); 1162 return; 1163 } 1164 1165 /* Do we have anything to do? */ 1166 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1167 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1168 hdac_unlock(sc); 1169 return; 1170 } 1171 1172 trigger = 0; 1173 1174 /* Was this a controller interrupt? */ 1175 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1176 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1177 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1178 /* Get as many responses that we can */ 1179 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1180 HDAC_WRITE_1(&sc->mem, 1181 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1182 if (hdac_rirb_flush(sc) != 0) 1183 trigger |= HDAC_TRIGGER_UNSOL; 1184 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1185 } 1186 /* XXX to be removed */ 1187 /* Clear interrupt and exit */ 1188#ifdef HDAC_INTR_EXTRA 1189 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1190#endif 1191 } 1192 1193 if (intsts & HDAC_INTSTS_SIS_MASK) { 1194 if ((intsts & (1 << sc->num_iss)) && 1195 hdac_stream_intr(sc, &sc->play) != 0) 1196 trigger |= HDAC_TRIGGER_PLAY; 1197 if ((intsts & (1 << 0)) && 1198 hdac_stream_intr(sc, &sc->rec) != 0) 1199 trigger |= HDAC_TRIGGER_REC; 1200 /* XXX to be removed */ 1201#ifdef HDAC_INTR_EXTRA 1202 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1203 HDAC_INTSTS_SIS_MASK); 1204#endif 1205 } 1206 1207 hdac_unlock(sc); 1208 1209 if (trigger & HDAC_TRIGGER_PLAY) 1210 chn_intr(sc->play.c); 1211 if (trigger & HDAC_TRIGGER_REC) 1212 chn_intr(sc->rec.c); 1213 if (trigger & HDAC_TRIGGER_UNSOL) 1214 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1215} 1216 1217/**************************************************************************** 1218 * int hdac_reset(hdac_softc *) 1219 * 1220 * Reset the hdac to a quiescent and known state. 1221 ****************************************************************************/ 1222static int 1223hdac_reset(struct hdac_softc *sc) 1224{ 1225 uint32_t gctl; 1226 int count, i; 1227 1228 /* 1229 * Stop all Streams DMA engine 1230 */ 1231 for (i = 0; i < sc->num_iss; i++) 1232 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1233 for (i = 0; i < sc->num_oss; i++) 1234 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1235 for (i = 0; i < sc->num_bss; i++) 1236 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1237 1238 /* 1239 * Stop Control DMA engines. 1240 */ 1241 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1242 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1243 1244 /* 1245 * Reset DMA position buffer. 1246 */ 1247 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1248 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1249 1250 /* 1251 * Reset the controller. The reset must remain asserted for 1252 * a minimum of 100us. 1253 */ 1254 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1255 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1256 count = 10000; 1257 do { 1258 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1259 if (!(gctl & HDAC_GCTL_CRST)) 1260 break; 1261 DELAY(10); 1262 } while (--count); 1263 if (gctl & HDAC_GCTL_CRST) { 1264 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1265 return (ENXIO); 1266 } 1267 DELAY(100); 1268 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1269 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1270 count = 10000; 1271 do { 1272 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1273 if (gctl & HDAC_GCTL_CRST) 1274 break; 1275 DELAY(10); 1276 } while (--count); 1277 if (!(gctl & HDAC_GCTL_CRST)) { 1278 device_printf(sc->dev, "Device stuck in reset\n"); 1279 return (ENXIO); 1280 } 1281 1282 /* 1283 * Wait for codecs to finish their own reset sequence. The delay here 1284 * should be of 250us but for some reasons, on it's not enough on my 1285 * computer. Let's use twice as much as necessary to make sure that 1286 * it's reset properly. 1287 */ 1288 DELAY(1000); 1289 1290 return (0); 1291} 1292 1293 1294/**************************************************************************** 1295 * int hdac_get_capabilities(struct hdac_softc *); 1296 * 1297 * Retreive the general capabilities of the hdac; 1298 * Number of Input Streams 1299 * Number of Output Streams 1300 * Number of bidirectional Streams 1301 * 64bit ready 1302 * CORB and RIRB sizes 1303 ****************************************************************************/ 1304static int 1305hdac_get_capabilities(struct hdac_softc *sc) 1306{ 1307 uint16_t gcap; 1308 uint8_t corbsize, rirbsize; 1309 1310 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1311 sc->num_iss = HDAC_GCAP_ISS(gcap); 1312 sc->num_oss = HDAC_GCAP_OSS(gcap); 1313 sc->num_bss = HDAC_GCAP_BSS(gcap); 1314 1315 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1316 1317 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1318 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1319 HDAC_CORBSIZE_CORBSZCAP_256) 1320 sc->corb_size = 256; 1321 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1322 HDAC_CORBSIZE_CORBSZCAP_16) 1323 sc->corb_size = 16; 1324 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1325 HDAC_CORBSIZE_CORBSZCAP_2) 1326 sc->corb_size = 2; 1327 else { 1328 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1329 __func__, corbsize); 1330 return (ENXIO); 1331 } 1332 1333 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1334 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1335 HDAC_RIRBSIZE_RIRBSZCAP_256) 1336 sc->rirb_size = 256; 1337 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1338 HDAC_RIRBSIZE_RIRBSZCAP_16) 1339 sc->rirb_size = 16; 1340 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1341 HDAC_RIRBSIZE_RIRBSZCAP_2) 1342 sc->rirb_size = 2; 1343 else { 1344 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1345 __func__, rirbsize); 1346 return (ENXIO); 1347 } 1348 1349 return (0); 1350} 1351 1352 1353/**************************************************************************** 1354 * void hdac_dma_cb 1355 * 1356 * This function is called by bus_dmamap_load when the mapping has been 1357 * established. We just record the physical address of the mapping into 1358 * the struct hdac_dma passed in. 1359 ****************************************************************************/ 1360static void 1361hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1362{ 1363 struct hdac_dma *dma; 1364 1365 if (error == 0) { 1366 dma = (struct hdac_dma *)callback_arg; 1367 dma->dma_paddr = segs[0].ds_addr; 1368 } 1369} 1370 1371 1372/**************************************************************************** 1373 * int hdac_dma_alloc 1374 * 1375 * This function allocate and setup a dma region (struct hdac_dma). 1376 * It must be freed by a corresponding hdac_dma_free. 1377 ****************************************************************************/ 1378static int 1379hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1380{ 1381 bus_size_t roundsz; 1382 int result; 1383 int lowaddr; 1384 1385 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1386 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1387 BUS_SPACE_MAXADDR_32BIT; 1388 bzero(dma, sizeof(*dma)); 1389 1390 /* 1391 * Create a DMA tag 1392 */ 1393 result = bus_dma_tag_create(NULL, /* parent */ 1394 HDAC_DMA_ALIGNMENT, /* alignment */ 1395 0, /* boundary */ 1396 lowaddr, /* lowaddr */ 1397 BUS_SPACE_MAXADDR, /* highaddr */ 1398 NULL, /* filtfunc */ 1399 NULL, /* fistfuncarg */ 1400 roundsz, /* maxsize */ 1401 1, /* nsegments */ 1402 roundsz, /* maxsegsz */ 1403 0, /* flags */ 1404 NULL, /* lockfunc */ 1405 NULL, /* lockfuncarg */ 1406 &dma->dma_tag); /* dmat */ 1407 if (result != 0) { 1408 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1409 __func__, result); 1410 goto hdac_dma_alloc_fail; 1411 } 1412 1413 /* 1414 * Allocate DMA memory 1415 */ 1416 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1417 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1418 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1419 &dma->dma_map); 1420 if (result != 0) { 1421 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1422 __func__, result); 1423 goto hdac_dma_alloc_fail; 1424 } 1425 1426 dma->dma_size = roundsz; 1427 1428 /* 1429 * Map the memory 1430 */ 1431 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1432 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1433 if (result != 0 || dma->dma_paddr == 0) { 1434 if (result == 0) 1435 result = ENOMEM; 1436 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1437 __func__, result); 1438 goto hdac_dma_alloc_fail; 1439 } 1440 1441 HDA_BOOTVERBOSE( 1442 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1443 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1444 ); 1445 1446 return (0); 1447 1448hdac_dma_alloc_fail: 1449 hdac_dma_free(sc, dma); 1450 1451 return (result); 1452} 1453 1454 1455/**************************************************************************** 1456 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1457 * 1458 * Free a struct dhac_dma that has been previously allocated via the 1459 * hdac_dma_alloc function. 1460 ****************************************************************************/ 1461static void 1462hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1463{ 1464 if (dma->dma_map != NULL) { 1465#if 0 1466 /* Flush caches */ 1467 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1468 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1469#endif 1470 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1471 } 1472 if (dma->dma_vaddr != NULL) { 1473 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1474 dma->dma_vaddr = NULL; 1475 } 1476 dma->dma_map = NULL; 1477 if (dma->dma_tag != NULL) { 1478 bus_dma_tag_destroy(dma->dma_tag); 1479 dma->dma_tag = NULL; 1480 } 1481 dma->dma_size = 0; 1482} 1483 1484/**************************************************************************** 1485 * int hdac_mem_alloc(struct hdac_softc *) 1486 * 1487 * Allocate all the bus resources necessary to speak with the physical 1488 * controller. 1489 ****************************************************************************/ 1490static int 1491hdac_mem_alloc(struct hdac_softc *sc) 1492{ 1493 struct hdac_mem *mem; 1494 1495 mem = &sc->mem; 1496 mem->mem_rid = PCIR_BAR(0); 1497 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1498 &mem->mem_rid, RF_ACTIVE); 1499 if (mem->mem_res == NULL) { 1500 device_printf(sc->dev, 1501 "%s: Unable to allocate memory resource\n", __func__); 1502 return (ENOMEM); 1503 } 1504 mem->mem_tag = rman_get_bustag(mem->mem_res); 1505 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1506 1507 return (0); 1508} 1509 1510/**************************************************************************** 1511 * void hdac_mem_free(struct hdac_softc *) 1512 * 1513 * Free up resources previously allocated by hdac_mem_alloc. 1514 ****************************************************************************/ 1515static void 1516hdac_mem_free(struct hdac_softc *sc) 1517{ 1518 struct hdac_mem *mem; 1519 1520 mem = &sc->mem; 1521 if (mem->mem_res != NULL) 1522 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1523 mem->mem_res); 1524 mem->mem_res = NULL; 1525} 1526 1527/**************************************************************************** 1528 * int hdac_irq_alloc(struct hdac_softc *) 1529 * 1530 * Allocate and setup the resources necessary for interrupt handling. 1531 ****************************************************************************/ 1532static int 1533hdac_irq_alloc(struct hdac_softc *sc) 1534{ 1535 struct hdac_irq *irq; 1536 int result; 1537 1538 irq = &sc->irq; 1539 irq->irq_rid = 0x0; 1540 1541#if __FreeBSD_version >= 602106 1542 if ((sc->flags & HDAC_F_MSI) && 1543 (result = pci_msi_count(sc->dev)) == 1 && 1544 pci_alloc_msi(sc->dev, &result) == 0) 1545 irq->irq_rid = 0x1; 1546 else 1547#endif 1548 sc->flags &= ~HDAC_F_MSI; 1549 1550 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1551 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1552 if (irq->irq_res == NULL) { 1553 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1554 __func__); 1555 goto hdac_irq_alloc_fail; 1556 } 1557 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1558 hdac_intr_handler, sc, &irq->irq_handle); 1559 if (result != 0) { 1560 device_printf(sc->dev, 1561 "%s: Unable to setup interrupt handler (%x)\n", 1562 __func__, result); 1563 goto hdac_irq_alloc_fail; 1564 } 1565 1566 return (0); 1567 1568hdac_irq_alloc_fail: 1569 hdac_irq_free(sc); 1570 1571 return (ENXIO); 1572} 1573 1574/**************************************************************************** 1575 * void hdac_irq_free(struct hdac_softc *) 1576 * 1577 * Free up resources previously allocated by hdac_irq_alloc. 1578 ****************************************************************************/ 1579static void 1580hdac_irq_free(struct hdac_softc *sc) 1581{ 1582 struct hdac_irq *irq; 1583 1584 irq = &sc->irq; 1585 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1586 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1587 if (irq->irq_res != NULL) 1588 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1589 irq->irq_res); 1590#if __FreeBSD_version >= 602106 1591 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1592 pci_release_msi(sc->dev); 1593#endif 1594 irq->irq_handle = NULL; 1595 irq->irq_res = NULL; 1596 irq->irq_rid = 0x0; 1597} 1598 1599/**************************************************************************** 1600 * void hdac_corb_init(struct hdac_softc *) 1601 * 1602 * Initialize the corb registers for operations but do not start it up yet. 1603 * The CORB engine must not be running when this function is called. 1604 ****************************************************************************/ 1605static void 1606hdac_corb_init(struct hdac_softc *sc) 1607{ 1608 uint8_t corbsize; 1609 uint64_t corbpaddr; 1610 1611 /* Setup the CORB size. */ 1612 switch (sc->corb_size) { 1613 case 256: 1614 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1615 break; 1616 case 16: 1617 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1618 break; 1619 case 2: 1620 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1621 break; 1622 default: 1623 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1624 } 1625 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1626 1627 /* Setup the CORB Address in the hdac */ 1628 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1629 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1630 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1631 1632 /* Set the WP and RP */ 1633 sc->corb_wp = 0; 1634 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1635 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1636 /* 1637 * The HDA specification indicates that the CORBRPRST bit will always 1638 * read as zero. Unfortunately, it seems that at least the 82801G 1639 * doesn't reset the bit to zero, which stalls the corb engine. 1640 * manually reset the bit to zero before continuing. 1641 */ 1642 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1643 1644 /* Enable CORB error reporting */ 1645#if 0 1646 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1647#endif 1648} 1649 1650/**************************************************************************** 1651 * void hdac_rirb_init(struct hdac_softc *) 1652 * 1653 * Initialize the rirb registers for operations but do not start it up yet. 1654 * The RIRB engine must not be running when this function is called. 1655 ****************************************************************************/ 1656static void 1657hdac_rirb_init(struct hdac_softc *sc) 1658{ 1659 uint8_t rirbsize; 1660 uint64_t rirbpaddr; 1661 1662 /* Setup the RIRB size. */ 1663 switch (sc->rirb_size) { 1664 case 256: 1665 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1666 break; 1667 case 16: 1668 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1669 break; 1670 case 2: 1671 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1672 break; 1673 default: 1674 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1675 } 1676 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1677 1678 /* Setup the RIRB Address in the hdac */ 1679 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1680 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1681 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1682 1683 /* Setup the WP and RP */ 1684 sc->rirb_rp = 0; 1685 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1686 1687 if (sc->polling == 0) { 1688 /* Setup the interrupt threshold */ 1689 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1690 1691 /* Enable Overrun and response received reporting */ 1692#if 0 1693 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1694 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1695#else 1696 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1697#endif 1698 } 1699 1700#if 0 1701 /* 1702 * Make sure that the Host CPU cache doesn't contain any dirty 1703 * cache lines that falls in the rirb. If I understood correctly, it 1704 * should be sufficient to do this only once as the rirb is purely 1705 * read-only from now on. 1706 */ 1707 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1708 BUS_DMASYNC_PREREAD); 1709#endif 1710} 1711 1712/**************************************************************************** 1713 * void hdac_corb_start(hdac_softc *) 1714 * 1715 * Startup the corb DMA engine 1716 ****************************************************************************/ 1717static void 1718hdac_corb_start(struct hdac_softc *sc) 1719{ 1720 uint32_t corbctl; 1721 1722 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1723 corbctl |= HDAC_CORBCTL_CORBRUN; 1724 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1725} 1726 1727/**************************************************************************** 1728 * void hdac_rirb_start(hdac_softc *) 1729 * 1730 * Startup the rirb DMA engine 1731 ****************************************************************************/ 1732static void 1733hdac_rirb_start(struct hdac_softc *sc) 1734{ 1735 uint32_t rirbctl; 1736 1737 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1738 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1739 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1740} 1741 1742 1743/**************************************************************************** 1744 * void hdac_scan_codecs(struct hdac_softc *, int) 1745 * 1746 * Scan the bus for available codecs, starting with num. 1747 ****************************************************************************/ 1748static void 1749hdac_scan_codecs(struct hdac_softc *sc, int num) 1750{ 1751 struct hdac_codec *codec; 1752 int i; 1753 uint16_t statests; 1754 1755 if (num < 0) 1756 num = 0; 1757 if (num >= HDAC_CODEC_MAX) 1758 num = HDAC_CODEC_MAX - 1; 1759 1760 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1761 for (i = num; i < HDAC_CODEC_MAX; i++) { 1762 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1763 /* We have found a codec. */ 1764 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1765 M_HDAC, M_ZERO | M_NOWAIT); 1766 if (codec == NULL) { 1767 device_printf(sc->dev, 1768 "Unable to allocate memory for codec\n"); 1769 continue; 1770 } 1771 codec->commands = NULL; 1772 codec->responses_received = 0; 1773 codec->verbs_sent = 0; 1774 codec->sc = sc; 1775 codec->cad = i; 1776 sc->codecs[i] = codec; 1777 if (hdac_probe_codec(codec) != 0) 1778 break; 1779 } 1780 } 1781 /* All codecs have been probed, now try to attach drivers to them */ 1782 /* bus_generic_attach(sc->dev); */ 1783} 1784 1785/**************************************************************************** 1786 * void hdac_probe_codec(struct hdac_softc *, int) 1787 * 1788 * Probe a the given codec_id for available function groups. 1789 ****************************************************************************/ 1790static int 1791hdac_probe_codec(struct hdac_codec *codec) 1792{ 1793 struct hdac_softc *sc = codec->sc; 1794 struct hdac_devinfo *devinfo; 1795 uint32_t vendorid, revisionid, subnode; 1796 int startnode; 1797 int endnode; 1798 int i; 1799 nid_t cad = codec->cad; 1800 1801 HDA_BOOTVERBOSE( 1802 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1803 ); 1804 vendorid = hdac_command(sc, 1805 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1806 cad); 1807 revisionid = hdac_command(sc, 1808 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1809 cad); 1810 subnode = hdac_command(sc, 1811 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1812 cad); 1813 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1814 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1815 1816 HDA_BOOTVERBOSE( 1817 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1818 startnode, endnode); 1819 ); 1820 for (i = startnode; i < endnode; i++) { 1821 devinfo = hdac_probe_function(codec, i); 1822 if (devinfo != NULL) { 1823 /* XXX Ignore other FG. */ 1824 devinfo->vendor_id = 1825 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1826 devinfo->device_id = 1827 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1828 devinfo->revision_id = 1829 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1830 devinfo->stepping_id = 1831 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1832 HDA_BOOTVERBOSE( 1833 device_printf(sc->dev, 1834 "HDA_DEBUG: \tFound AFG nid=%d " 1835 "[startnode=%d endnode=%d]\n", 1836 devinfo->nid, startnode, endnode); 1837 ); 1838 return (1); 1839 } 1840 } 1841 1842 HDA_BOOTVERBOSE( 1843 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1844 ); 1845 return (0); 1846} 1847 1848static struct hdac_devinfo * 1849hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1850{ 1851 struct hdac_softc *sc = codec->sc; 1852 struct hdac_devinfo *devinfo; 1853 uint32_t fctgrptype; 1854 nid_t cad = codec->cad; 1855 1856 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1857 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1858 1859 /* XXX For now, ignore other FG. */ 1860 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1861 return (NULL); 1862 1863 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1864 M_NOWAIT | M_ZERO); 1865 if (devinfo == NULL) { 1866 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1867 __func__); 1868 return (NULL); 1869 } 1870 1871 devinfo->nid = nid; 1872 devinfo->node_type = fctgrptype; 1873 devinfo->codec = codec; 1874 1875 hdac_add_child(sc, devinfo); 1876 1877 return (devinfo); 1878} 1879 1880static void 1881hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1882{ 1883 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1884 device_set_ivars(devinfo->dev, (void *)devinfo); 1885 /* XXX - Print more information when booting verbose??? */ 1886} 1887 1888static void 1889hdac_widget_connection_parse(struct hdac_widget *w) 1890{ 1891 struct hdac_softc *sc = w->devinfo->codec->sc; 1892 uint32_t res; 1893 int i, j, max, ents, entnum; 1894 nid_t cad = w->devinfo->codec->cad; 1895 nid_t nid = w->nid; 1896 nid_t cnid, addcnid, prevcnid; 1897 1898 w->nconns = 0; 1899 1900 res = hdac_command(sc, 1901 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1902 1903 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1904 1905 if (ents < 1) 1906 return; 1907 1908 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1909 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1910 prevcnid = 0; 1911 1912#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1913#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1914#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1915#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1916#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1917 1918 for (i = 0; i < ents; i += entnum) { 1919 res = hdac_command(sc, 1920 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1921 for (j = 0; j < entnum; j++) { 1922 cnid = CONN_CNID(res, entnum, j); 1923 if (cnid == 0) { 1924 if (w->nconns < ents) 1925 device_printf(sc->dev, 1926 "%s: nid=%d WARNING: zero cnid " 1927 "entnum=%d j=%d index=%d " 1928 "entries=%d found=%d res=0x%08x\n", 1929 __func__, nid, entnum, j, i, 1930 ents, w->nconns, res); 1931 else 1932 goto getconns_out; 1933 } 1934 if (cnid < w->devinfo->startnode || 1935 cnid >= w->devinfo->endnode) { 1936 HDA_BOOTVERBOSE( 1937 device_printf(sc->dev, 1938 "%s: GHOST: nid=%d j=%d " 1939 "entnum=%d index=%d res=0x%08x\n", 1940 __func__, nid, j, entnum, i, res); 1941 ); 1942 } 1943 if (CONN_RANGE(res, entnum, j) == 0) 1944 addcnid = cnid; 1945 else if (prevcnid == 0 || prevcnid >= cnid) { 1946 device_printf(sc->dev, 1947 "%s: WARNING: Invalid child range " 1948 "nid=%d index=%d j=%d entnum=%d " 1949 "prevcnid=%d cnid=%d res=0x%08x\n", 1950 __func__, nid, i, j, entnum, prevcnid, 1951 cnid, res); 1952 addcnid = cnid; 1953 } else 1954 addcnid = prevcnid + 1; 1955 while (addcnid <= cnid) { 1956 if (w->nconns > max) { 1957 device_printf(sc->dev, 1958 "%s: nid=%d: Adding %d: " 1959 "Max connection reached! max=%d\n", 1960 __func__, nid, addcnid, max + 1); 1961 goto getconns_out; 1962 } 1963 w->conns[w->nconns++] = addcnid++; 1964 } 1965 prevcnid = cnid; 1966 } 1967 } 1968 1969getconns_out: 1970 HDA_BOOTVERBOSE( 1971 device_printf(sc->dev, 1972 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1973 __func__, nid, ents, w->nconns); 1974 ); 1975 return; 1976} 1977 1978static uint32_t 1979hdac_widget_pin_getconfig(struct hdac_widget *w) 1980{ 1981 struct hdac_softc *sc; 1982 uint32_t config, orig, id; 1983 nid_t cad, nid; 1984 1985 sc = w->devinfo->codec->sc; 1986 cad = w->devinfo->codec->cad; 1987 nid = w->nid; 1988 id = hdac_codec_id(w->devinfo); 1989 1990 config = hdac_command(sc, 1991 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1992 cad); 1993 orig = config; 1994 1995 /* 1996 * XXX REWRITE!!!! Don't argue! 1997 */ 1998 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1999 switch (nid) { 2000 case 26: 2001 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2002 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2003 break; 2004 case 27: 2005 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2006 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2007 break; 2008 default: 2009 break; 2010 } 2011 } else if (id == HDA_CODEC_ALC880 && 2012 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2013 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2014 /* 2015 * Super broken BIOS 2016 */ 2017 switch (nid) { 2018 case 20: 2019 break; 2020 case 21: 2021 break; 2022 case 22: 2023 break; 2024 case 23: 2025 break; 2026 case 24: /* MIC1 */ 2027 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2028 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2029 break; 2030 case 25: /* XXX MIC2 */ 2031 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2032 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2033 break; 2034 case 26: /* LINE1 */ 2035 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2036 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2037 break; 2038 case 27: /* XXX LINE2 */ 2039 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2040 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2041 break; 2042 case 28: /* CD */ 2043 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2044 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2045 break; 2046 case 30: 2047 break; 2048 case 31: 2049 break; 2050 default: 2051 break; 2052 } 2053 } else if (id == HDA_CODEC_ALC883 && 2054 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2055 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2056 switch (nid) { 2057 case 25: 2058 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2059 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2060 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2061 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2062 break; 2063 case 28: 2064 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2065 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2066 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2067 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2068 break; 2069 default: 2070 break; 2071 } 2072 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2073 HP_V3000_SUBVENDOR) { 2074 switch (nid) { 2075 case 18: 2076 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2077 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2078 break; 2079 case 20: 2080 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2081 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2082 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2083 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2084 break; 2085 case 21: 2086 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2087 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2088 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2089 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2090 break; 2091 default: 2092 break; 2093 } 2094 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2095 HP_DV5000_SUBVENDOR) { 2096 switch (nid) { 2097 case 20: 2098 case 21: 2099 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2100 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2101 break; 2102 default: 2103 break; 2104 } 2105 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2106 ASUS_W6F_SUBVENDOR) { 2107 switch (nid) { 2108 case 11: 2109 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2110 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2111 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2112 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2113 break; 2114 case 15: 2115 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2116 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2117 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2118 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2119 break; 2120 default: 2121 break; 2122 } 2123 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2124 UNIWILL_9075_SUBVENDOR) { 2125 switch (nid) { 2126 case 15: 2127 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2128 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2129 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2130 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2131 break; 2132 default: 2133 break; 2134 } 2135 } else if (id == HDA_CODEC_AD1986A && 2136 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2137 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2138 switch (nid) { 2139 case 28: /* LINE */ 2140 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2141 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2142 break; 2143 case 29: /* MIC */ 2144 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2145 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2146 break; 2147 default: 2148 break; 2149 } 2150 } 2151 2152 HDA_BOOTVERBOSE( 2153 if (config != orig) 2154 device_printf(sc->dev, 2155 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2156 nid, orig, config); 2157 ); 2158 2159 return (config); 2160} 2161 2162static uint32_t 2163hdac_widget_pin_getcaps(struct hdac_widget *w) 2164{ 2165 struct hdac_softc *sc; 2166 uint32_t caps, orig, id; 2167 nid_t cad, nid; 2168 2169 sc = w->devinfo->codec->sc; 2170 cad = w->devinfo->codec->cad; 2171 nid = w->nid; 2172 id = hdac_codec_id(w->devinfo); 2173 2174 caps = hdac_command(sc, 2175 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2176 orig = caps; 2177 2178 HDA_BOOTVERBOSE( 2179 if (caps != orig) 2180 device_printf(sc->dev, 2181 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2182 nid, orig, caps); 2183 ); 2184 2185 return (caps); 2186} 2187 2188static void 2189hdac_widget_pin_parse(struct hdac_widget *w) 2190{ 2191 struct hdac_softc *sc = w->devinfo->codec->sc; 2192 uint32_t config, pincap; 2193 char *devstr, *connstr; 2194 nid_t cad = w->devinfo->codec->cad; 2195 nid_t nid = w->nid; 2196 2197 config = hdac_widget_pin_getconfig(w); 2198 w->wclass.pin.config = config; 2199 2200 pincap = hdac_widget_pin_getcaps(w); 2201 w->wclass.pin.cap = pincap; 2202 2203 w->wclass.pin.ctrl = hdac_command(sc, 2204 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2205 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2206 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2207 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2208 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2209 2210 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2211 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2212 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2213 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2214 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2215 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2216 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2217 w->param.eapdbtl = hdac_command(sc, 2218 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2219 w->param.eapdbtl &= 0x7; 2220 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2221 } else 2222 w->param.eapdbtl = HDAC_INVALID; 2223 2224 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2225 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2226 devstr = "line out"; 2227 break; 2228 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2229 devstr = "speaker"; 2230 break; 2231 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2232 devstr = "headphones out"; 2233 break; 2234 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2235 devstr = "CD"; 2236 break; 2237 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2238 devstr = "SPDIF out"; 2239 break; 2240 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2241 devstr = "digital (other) out"; 2242 break; 2243 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2244 devstr = "modem, line side"; 2245 break; 2246 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2247 devstr = "modem, handset side"; 2248 break; 2249 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2250 devstr = "line in"; 2251 break; 2252 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2253 devstr = "AUX"; 2254 break; 2255 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2256 devstr = "Mic in"; 2257 break; 2258 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2259 devstr = "telephony"; 2260 break; 2261 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2262 devstr = "SPDIF in"; 2263 break; 2264 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2265 devstr = "digital (other) in"; 2266 break; 2267 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2268 devstr = "other"; 2269 break; 2270 default: 2271 devstr = "unknown"; 2272 break; 2273 } 2274 2275 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2276 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2277 connstr = "jack"; 2278 break; 2279 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2280 connstr = "none"; 2281 break; 2282 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2283 connstr = "fixed"; 2284 break; 2285 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2286 connstr = "jack / fixed"; 2287 break; 2288 default: 2289 connstr = "unknown"; 2290 break; 2291 } 2292 2293 strlcat(w->name, ": ", sizeof(w->name)); 2294 strlcat(w->name, devstr, sizeof(w->name)); 2295 strlcat(w->name, " (", sizeof(w->name)); 2296 strlcat(w->name, connstr, sizeof(w->name)); 2297 strlcat(w->name, ")", sizeof(w->name)); 2298} 2299 2300static void 2301hdac_widget_parse(struct hdac_widget *w) 2302{ 2303 struct hdac_softc *sc = w->devinfo->codec->sc; 2304 uint32_t wcap, cap; 2305 char *typestr; 2306 nid_t cad = w->devinfo->codec->cad; 2307 nid_t nid = w->nid; 2308 2309 wcap = hdac_command(sc, 2310 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2311 cad); 2312 w->param.widget_cap = wcap; 2313 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2314 2315 switch (w->type) { 2316 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2317 typestr = "audio output"; 2318 break; 2319 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2320 typestr = "audio input"; 2321 break; 2322 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2323 typestr = "audio mixer"; 2324 break; 2325 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2326 typestr = "audio selector"; 2327 break; 2328 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2329 typestr = "pin"; 2330 break; 2331 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2332 typestr = "power widget"; 2333 break; 2334 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2335 typestr = "volume widget"; 2336 break; 2337 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2338 typestr = "beep widget"; 2339 break; 2340 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2341 typestr = "vendor widget"; 2342 break; 2343 default: 2344 typestr = "unknown type"; 2345 break; 2346 } 2347 2348 strlcpy(w->name, typestr, sizeof(w->name)); 2349 2350 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2351 hdac_command(sc, 2352 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2353 cad); 2354 DELAY(1000); 2355 } 2356 2357 hdac_widget_connection_parse(w); 2358 2359 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2360 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2361 w->param.outamp_cap = 2362 hdac_command(sc, 2363 HDA_CMD_GET_PARAMETER(cad, nid, 2364 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2365 else 2366 w->param.outamp_cap = 2367 w->devinfo->function.audio.outamp_cap; 2368 } else 2369 w->param.outamp_cap = 0; 2370 2371 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2372 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2373 w->param.inamp_cap = 2374 hdac_command(sc, 2375 HDA_CMD_GET_PARAMETER(cad, nid, 2376 HDA_PARAM_INPUT_AMP_CAP), cad); 2377 else 2378 w->param.inamp_cap = 2379 w->devinfo->function.audio.inamp_cap; 2380 } else 2381 w->param.inamp_cap = 0; 2382 2383 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2384 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2385 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2386 cap = hdac_command(sc, 2387 HDA_CMD_GET_PARAMETER(cad, nid, 2388 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2389 w->param.supp_stream_formats = (cap != 0) ? cap : 2390 w->devinfo->function.audio.supp_stream_formats; 2391 cap = hdac_command(sc, 2392 HDA_CMD_GET_PARAMETER(cad, nid, 2393 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2394 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2395 w->devinfo->function.audio.supp_pcm_size_rate; 2396 } else { 2397 w->param.supp_stream_formats = 2398 w->devinfo->function.audio.supp_stream_formats; 2399 w->param.supp_pcm_size_rate = 2400 w->devinfo->function.audio.supp_pcm_size_rate; 2401 } 2402 } else { 2403 w->param.supp_stream_formats = 0; 2404 w->param.supp_pcm_size_rate = 0; 2405 } 2406 2407 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2408 hdac_widget_pin_parse(w); 2409} 2410 2411static struct hdac_widget * 2412hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2413{ 2414 if (devinfo == NULL || devinfo->widget == NULL || 2415 nid < devinfo->startnode || nid >= devinfo->endnode) 2416 return (NULL); 2417 return (&devinfo->widget[nid - devinfo->startnode]); 2418} 2419 2420static __inline int 2421hda_poll_channel(struct hdac_chan *ch) 2422{ 2423 uint32_t sz, delta; 2424 volatile uint32_t ptr; 2425 2426 if (!(ch->flags & HDAC_CHN_RUNNING)) 2427 return (0); 2428 2429 sz = ch->blksz * ch->blkcnt; 2430 if (ch->dmapos != NULL) 2431 ptr = *(ch->dmapos); 2432 else 2433 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2434 ch->off + HDAC_SDLPIB); 2435 ch->ptr = ptr; 2436 ptr %= sz; 2437 ptr &= ~(ch->blksz - 1); 2438 delta = (sz + ptr - ch->prevptr) % sz; 2439 2440 if (delta < ch->blksz) 2441 return (0); 2442 2443 ch->prevptr = ptr; 2444 2445 return (1); 2446} 2447 2448#define hda_chan_active(sc) (((sc)->play.flags | (sc)->rec.flags) & \ 2449 HDAC_CHN_RUNNING) 2450 2451static void 2452hda_poll_callback(void *arg) 2453{ 2454 struct hdac_softc *sc = arg; 2455 uint32_t trigger; 2456 2457 if (sc == NULL) 2458 return; 2459 2460 hdac_lock(sc); 2461 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2462 hdac_unlock(sc); 2463 return; 2464 } 2465 2466 trigger = 0; 2467 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2468 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2469 2470 /* XXX */ 2471 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2472 hda_poll_callback, sc); 2473 2474 hdac_unlock(sc); 2475 2476 if (trigger & HDAC_TRIGGER_PLAY) 2477 chn_intr(sc->play.c); 2478 if (trigger & HDAC_TRIGGER_REC) 2479 chn_intr(sc->rec.c); 2480} 2481 2482static int 2483hdac_rirb_flush(struct hdac_softc *sc) 2484{ 2485 struct hdac_rirb *rirb_base, *rirb; 2486 struct hdac_codec *codec; 2487 struct hdac_command_list *commands; 2488 nid_t cad; 2489 uint32_t resp; 2490 uint8_t rirbwp; 2491 int ret; 2492 2493 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2494 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2495#if 0 2496 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2497 BUS_DMASYNC_POSTREAD); 2498#endif 2499 2500 ret = 0; 2501 2502 while (sc->rirb_rp != rirbwp) { 2503 sc->rirb_rp++; 2504 sc->rirb_rp %= sc->rirb_size; 2505 rirb = &rirb_base[sc->rirb_rp]; 2506 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2507 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2508 sc->codecs[cad] == NULL) 2509 continue; 2510 resp = rirb->response; 2511 codec = sc->codecs[cad]; 2512 commands = codec->commands; 2513 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2514 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2515 ((resp >> 26) & 0xffff); 2516 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2517 } else if (commands != NULL && commands->num_commands > 0 && 2518 codec->responses_received < commands->num_commands) 2519 commands->responses[codec->responses_received++] = 2520 resp; 2521 ret++; 2522 } 2523 2524 return (ret); 2525} 2526 2527static int 2528hdac_unsolq_flush(struct hdac_softc *sc) 2529{ 2530 nid_t cad; 2531 uint32_t tag; 2532 int ret = 0; 2533 2534 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2535 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2536 while (sc->unsolq_rp != sc->unsolq_wp) { 2537 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2538 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2539 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2540 hdac_unsolicited_handler(sc->codecs[cad], tag); 2541 ret++; 2542 } 2543 sc->unsolq_st = HDAC_UNSOLQ_READY; 2544 } 2545 2546 return (ret); 2547} 2548 2549static void 2550hdac_poll_callback(void *arg) 2551{ 2552 struct hdac_softc *sc = arg; 2553 if (sc == NULL) 2554 return; 2555 2556 hdac_lock(sc); 2557 if (sc->polling == 0 || sc->poll_ival == 0) { 2558 hdac_unlock(sc); 2559 return; 2560 } 2561 if (hdac_rirb_flush(sc) != 0) 2562 hdac_unsolq_flush(sc); 2563 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2564 hdac_unlock(sc); 2565} 2566 2567static void 2568hdac_stream_stop(struct hdac_chan *ch) 2569{ 2570 struct hdac_softc *sc = ch->devinfo->codec->sc; 2571 uint32_t ctl; 2572 2573 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2574 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2575 HDAC_SDCTL_RUN); 2576 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2577 2578 ch->flags &= ~HDAC_CHN_RUNNING; 2579 2580 if (sc->polling != 0) { 2581 int pollticks; 2582 2583 if (hda_chan_active(sc) == 0) { 2584 callout_stop(&sc->poll_hda); 2585 sc->poll_ticks = 1; 2586 } else { 2587 if (sc->play.flags & HDAC_CHN_RUNNING) 2588 ch = &sc->play; 2589 else 2590 ch = &sc->rec; 2591 pollticks = ((uint64_t)hz * ch->blksz) / 2592 ((uint64_t)sndbuf_getbps(ch->b) * 2593 sndbuf_getspd(ch->b)); 2594 pollticks >>= 2; 2595 if (pollticks > hz) 2596 pollticks = hz; 2597 if (pollticks < 1) { 2598 HDA_BOOTVERBOSE( 2599 device_printf(sc->dev, 2600 "%s: pollticks=%d < 1 !\n", 2601 __func__, pollticks); 2602 ); 2603 pollticks = 1; 2604 } 2605 if (pollticks > sc->poll_ticks) { 2606 HDA_BOOTVERBOSE( 2607 device_printf(sc->dev, 2608 "%s: pollticks %d -> %d\n", 2609 __func__, sc->poll_ticks, 2610 pollticks); 2611 ); 2612 sc->poll_ticks = pollticks; 2613 callout_reset(&sc->poll_hda, 1, 2614 hda_poll_callback, sc); 2615 } 2616 } 2617 } else { 2618 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2619 ctl &= ~(1 << (ch->off >> 5)); 2620 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2621 } 2622} 2623 2624static void 2625hdac_stream_start(struct hdac_chan *ch) 2626{ 2627 struct hdac_softc *sc = ch->devinfo->codec->sc; 2628 uint32_t ctl; 2629 2630 if (sc->polling != 0) { 2631 int pollticks; 2632 2633 pollticks = ((uint64_t)hz * ch->blksz) / 2634 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2635 pollticks >>= 2; 2636 if (pollticks > hz) 2637 pollticks = hz; 2638 if (pollticks < 1) { 2639 HDA_BOOTVERBOSE( 2640 device_printf(sc->dev, 2641 "%s: pollticks=%d < 1 !\n", 2642 __func__, pollticks); 2643 ); 2644 pollticks = 1; 2645 } 2646 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2647 HDA_BOOTVERBOSE( 2648 if (hda_chan_active(sc) == 0) { 2649 device_printf(sc->dev, 2650 "%s: pollticks=%d\n", 2651 __func__, pollticks); 2652 } else { 2653 device_printf(sc->dev, 2654 "%s: pollticks %d -> %d\n", 2655 __func__, sc->poll_ticks, 2656 pollticks); 2657 } 2658 ); 2659 sc->poll_ticks = pollticks; 2660 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2661 sc); 2662 } 2663 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2664 ctl |= HDAC_SDCTL_RUN; 2665 } else { 2666 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2667 ctl |= 1 << (ch->off >> 5); 2668 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2669 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2670 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2671 HDAC_SDCTL_RUN; 2672 } 2673 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2674 2675 ch->flags |= HDAC_CHN_RUNNING; 2676} 2677 2678static void 2679hdac_stream_reset(struct hdac_chan *ch) 2680{ 2681 struct hdac_softc *sc = ch->devinfo->codec->sc; 2682 int timeout = 1000; 2683 int to = timeout; 2684 uint32_t ctl; 2685 2686 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2687 ctl |= HDAC_SDCTL_SRST; 2688 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2689 do { 2690 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2691 if (ctl & HDAC_SDCTL_SRST) 2692 break; 2693 DELAY(10); 2694 } while (--to); 2695 if (!(ctl & HDAC_SDCTL_SRST)) { 2696 device_printf(sc->dev, "timeout in reset\n"); 2697 } 2698 ctl &= ~HDAC_SDCTL_SRST; 2699 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2700 to = timeout; 2701 do { 2702 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2703 if (!(ctl & HDAC_SDCTL_SRST)) 2704 break; 2705 DELAY(10); 2706 } while (--to); 2707 if (ctl & HDAC_SDCTL_SRST) 2708 device_printf(sc->dev, "can't reset!\n"); 2709} 2710 2711static void 2712hdac_stream_setid(struct hdac_chan *ch) 2713{ 2714 struct hdac_softc *sc = ch->devinfo->codec->sc; 2715 uint32_t ctl; 2716 2717 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2718 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2719 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2720 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2721} 2722 2723static void 2724hdac_bdl_setup(struct hdac_chan *ch) 2725{ 2726 struct hdac_softc *sc = ch->devinfo->codec->sc; 2727 struct hdac_bdle *bdle; 2728 uint64_t addr; 2729 uint32_t blksz, blkcnt; 2730 int i; 2731 2732 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2733 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2734 2735 if (sc->polling != 0) { 2736 blksz = ch->blksz * ch->blkcnt; 2737 blkcnt = 1; 2738 } else { 2739 blksz = ch->blksz; 2740 blkcnt = ch->blkcnt; 2741 } 2742 2743 for (i = 0; i < blkcnt; i++, bdle++) { 2744 bdle->addrl = (uint32_t)addr; 2745 bdle->addrh = (uint32_t)(addr >> 32); 2746 bdle->len = blksz; 2747 bdle->ioc = 1 ^ sc->polling; 2748 addr += blksz; 2749 } 2750 2751 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2752 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2753 addr = ch->bdl_dma.dma_paddr; 2754 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2755 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2756 if (ch->dmapos != NULL && 2757 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2758 addr = sc->pos_dma.dma_paddr; 2759 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2760 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2761 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2762 } 2763} 2764 2765static int 2766hdac_bdl_alloc(struct hdac_chan *ch) 2767{ 2768 struct hdac_softc *sc = ch->devinfo->codec->sc; 2769 int rc; 2770 2771 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2772 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2773 if (rc) { 2774 device_printf(sc->dev, "can't alloc bdl\n"); 2775 return (rc); 2776 } 2777 2778 return (0); 2779} 2780 2781static void 2782hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2783 int index, int lmute, int rmute, 2784 int left, int right, int dir) 2785{ 2786 uint16_t v = 0; 2787 2788 if (sc == NULL) 2789 return; 2790 2791 if (left != right || lmute != rmute) { 2792 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2793 (lmute << 7) | left; 2794 hdac_command(sc, 2795 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2796 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2797 (rmute << 7) | right; 2798 } else 2799 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2800 (lmute << 7) | left; 2801 2802 hdac_command(sc, 2803 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2804} 2805 2806static void 2807hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2808 int left, int right) 2809{ 2810 struct hdac_softc *sc; 2811 nid_t nid, cad; 2812 int lmute, rmute; 2813 2814 if (ctl == NULL || ctl->widget == NULL || 2815 ctl->widget->devinfo == NULL || 2816 ctl->widget->devinfo->codec == NULL || 2817 ctl->widget->devinfo->codec->sc == NULL) 2818 return; 2819 2820 sc = ctl->widget->devinfo->codec->sc; 2821 cad = ctl->widget->devinfo->codec->cad; 2822 nid = ctl->widget->nid; 2823 2824 if (mute == HDA_AMP_MUTE_DEFAULT) { 2825 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2826 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2827 } else { 2828 lmute = HDA_AMP_LEFT_MUTED(mute); 2829 rmute = HDA_AMP_RIGHT_MUTED(mute); 2830 } 2831 2832 if (ctl->dir & HDA_CTL_OUT) 2833 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2834 lmute, rmute, left, right, 0); 2835 if (ctl->dir & HDA_CTL_IN) 2836 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2837 lmute, rmute, left, right, 1); 2838 ctl->left = left; 2839 ctl->right = right; 2840} 2841 2842static void 2843hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2844{ 2845 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2846 return; 2847 hdac_command(w->devinfo->codec->sc, 2848 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2849 w->nid, index), w->devinfo->codec->cad); 2850 w->selconn = index; 2851} 2852 2853 2854/**************************************************************************** 2855 * uint32_t hdac_command_sendone_internal 2856 * 2857 * Wrapper function that sends only one command to a given codec 2858 ****************************************************************************/ 2859static uint32_t 2860hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2861{ 2862 struct hdac_command_list cl; 2863 uint32_t response = HDAC_INVALID; 2864 2865 if (!hdac_lockowned(sc)) 2866 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2867 cl.num_commands = 1; 2868 cl.verbs = &verb; 2869 cl.responses = &response; 2870 2871 hdac_command_send_internal(sc, &cl, cad); 2872 2873 return (response); 2874} 2875 2876/**************************************************************************** 2877 * hdac_command_send_internal 2878 * 2879 * Send a command list to the codec via the corb. We queue as much verbs as 2880 * we can and msleep on the codec. When the interrupt get the responses 2881 * back from the rirb, it will wake us up so we can queue the remaining verbs 2882 * if any. 2883 ****************************************************************************/ 2884static void 2885hdac_command_send_internal(struct hdac_softc *sc, 2886 struct hdac_command_list *commands, nid_t cad) 2887{ 2888 struct hdac_codec *codec; 2889 int corbrp; 2890 uint32_t *corb; 2891 int timeout; 2892 int retry = 10; 2893 struct hdac_rirb *rirb_base; 2894 2895 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2896 commands->num_commands < 1) 2897 return; 2898 2899 codec = sc->codecs[cad]; 2900 codec->commands = commands; 2901 codec->responses_received = 0; 2902 codec->verbs_sent = 0; 2903 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2904 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2905 2906 do { 2907 if (codec->verbs_sent != commands->num_commands) { 2908 /* Queue as many verbs as possible */ 2909 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2910#if 0 2911 bus_dmamap_sync(sc->corb_dma.dma_tag, 2912 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2913#endif 2914 while (codec->verbs_sent != commands->num_commands && 2915 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2916 sc->corb_wp++; 2917 sc->corb_wp %= sc->corb_size; 2918 corb[sc->corb_wp] = 2919 commands->verbs[codec->verbs_sent++]; 2920 } 2921 2922 /* Send the verbs to the codecs */ 2923#if 0 2924 bus_dmamap_sync(sc->corb_dma.dma_tag, 2925 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2926#endif 2927 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2928 } 2929 2930 timeout = 1000; 2931 while (hdac_rirb_flush(sc) == 0 && --timeout) 2932 DELAY(10); 2933 } while ((codec->verbs_sent != commands->num_commands || 2934 codec->responses_received != commands->num_commands) && --retry); 2935 2936 if (retry == 0) 2937 device_printf(sc->dev, 2938 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2939 __func__, commands->num_commands, codec->verbs_sent, 2940 codec->responses_received); 2941 2942 codec->commands = NULL; 2943 codec->responses_received = 0; 2944 codec->verbs_sent = 0; 2945 2946 hdac_unsolq_flush(sc); 2947} 2948 2949 2950/**************************************************************************** 2951 * Device Methods 2952 ****************************************************************************/ 2953 2954/**************************************************************************** 2955 * int hdac_probe(device_t) 2956 * 2957 * Probe for the presence of an hdac. If none is found, check for a generic 2958 * match using the subclass of the device. 2959 ****************************************************************************/ 2960static int 2961hdac_probe(device_t dev) 2962{ 2963 int i, result; 2964 uint32_t model; 2965 uint16_t class, subclass; 2966 char desc[64]; 2967 2968 model = (uint32_t)pci_get_device(dev) << 16; 2969 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2970 class = pci_get_class(dev); 2971 subclass = pci_get_subclass(dev); 2972 2973 bzero(desc, sizeof(desc)); 2974 result = ENXIO; 2975 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2976 if (hdac_devices[i].model == model) { 2977 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2978 result = BUS_PROBE_DEFAULT; 2979 break; 2980 } 2981 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2982 class == PCIC_MULTIMEDIA && 2983 subclass == PCIS_MULTIMEDIA_HDA) { 2984 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2985 result = BUS_PROBE_GENERIC; 2986 break; 2987 } 2988 } 2989 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2990 subclass == PCIS_MULTIMEDIA_HDA) { 2991 strlcpy(desc, "Generic", sizeof(desc)); 2992 result = BUS_PROBE_GENERIC; 2993 } 2994 if (result != ENXIO) { 2995 strlcat(desc, " High Definition Audio Controller", 2996 sizeof(desc)); 2997 device_set_desc_copy(dev, desc); 2998 } 2999 3000 return (result); 3001} 3002 3003static void * 3004hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3005 struct pcm_channel *c, int dir) 3006{ 3007 struct hdac_devinfo *devinfo = data; 3008 struct hdac_softc *sc = devinfo->codec->sc; 3009 struct hdac_chan *ch; 3010 3011 hdac_lock(sc); 3012 if (dir == PCMDIR_PLAY) { 3013 ch = &sc->play; 3014 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 3015 devinfo->function.audio.playcnt++; 3016 } else { 3017 ch = &sc->rec; 3018 ch->off = devinfo->function.audio.reccnt << 5; 3019 devinfo->function.audio.reccnt++; 3020 } 3021 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3022 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3023 ch->pcmrates[0] = 48000; 3024 ch->pcmrates[1] = 0; 3025 } 3026 if (sc->pos_dma.dma_vaddr != NULL) 3027 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3028 (sc->streamcnt * 8)); 3029 else 3030 ch->dmapos = NULL; 3031 ch->sid = ++sc->streamcnt; 3032 ch->dir = dir; 3033 ch->b = b; 3034 ch->c = c; 3035 ch->devinfo = devinfo; 3036 ch->blksz = sc->chan_size / sc->chan_blkcnt; 3037 ch->blkcnt = sc->chan_blkcnt; 3038 hdac_unlock(sc); 3039 3040 if (hdac_bdl_alloc(ch) != 0) { 3041 ch->blkcnt = 0; 3042 return (NULL); 3043 } 3044 3045 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3046 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3047 sc->chan_size) != 0) 3048 return (NULL); 3049 3050 return (ch); 3051} 3052 3053static int 3054hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3055{ 3056 struct hdac_chan *ch = data; 3057 int i; 3058 3059 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3060 if (format == ch->caps.fmtlist[i]) { 3061 ch->fmt = format; 3062 return (0); 3063 } 3064 } 3065 3066 return (EINVAL); 3067} 3068 3069static int 3070hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3071{ 3072 struct hdac_chan *ch = data; 3073 uint32_t spd = 0, threshold; 3074 int i; 3075 3076 for (i = 0; ch->pcmrates[i] != 0; i++) { 3077 spd = ch->pcmrates[i]; 3078 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3079 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3080 if (speed < threshold) 3081 break; 3082 } 3083 3084 if (spd == 0) /* impossible */ 3085 ch->spd = 48000; 3086 else 3087 ch->spd = spd; 3088 3089 return (ch->spd); 3090} 3091 3092static void 3093hdac_stream_setup(struct hdac_chan *ch) 3094{ 3095 struct hdac_softc *sc = ch->devinfo->codec->sc; 3096 int i; 3097 nid_t cad = ch->devinfo->codec->cad; 3098 uint16_t fmt; 3099 3100 fmt = 0; 3101 if (ch->fmt & AFMT_S16_LE) 3102 fmt |= ch->bit16 << 4; 3103 else if (ch->fmt & AFMT_S32_LE) 3104 fmt |= ch->bit32 << 4; 3105 else 3106 fmt |= 1 << 4; 3107 3108 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3109 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3110 fmt |= hda_rate_tab[i].base; 3111 fmt |= hda_rate_tab[i].mul; 3112 fmt |= hda_rate_tab[i].div; 3113 break; 3114 } 3115 } 3116 3117 if (ch->fmt & AFMT_STEREO) 3118 fmt |= 1; 3119 3120 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3121 3122 for (i = 0; ch->io[i] != -1; i++) { 3123 HDA_BOOTVERBOSE( 3124 device_printf(sc->dev, 3125 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3126 "fmt=0x%08x\n", 3127 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3128 ch->io[i], fmt); 3129 ); 3130 hdac_command(sc, 3131 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3132 hdac_command(sc, 3133 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3134 ch->sid << 4), cad); 3135 } 3136} 3137 3138static int 3139hdac_channel_setfragments(kobj_t obj, void *data, 3140 uint32_t blksz, uint32_t blkcnt) 3141{ 3142 struct hdac_chan *ch = data; 3143 struct hdac_softc *sc = ch->devinfo->codec->sc; 3144 3145 blksz &= HDA_BLK_ALIGN; 3146 3147 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3148 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3149 if (blksz < HDA_BLK_MIN) 3150 blksz = HDA_BLK_MIN; 3151 if (blkcnt > HDA_BDL_MAX) 3152 blkcnt = HDA_BDL_MAX; 3153 if (blkcnt < HDA_BDL_MIN) 3154 blkcnt = HDA_BDL_MIN; 3155 3156 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3157 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3158 blkcnt >>= 1; 3159 else if ((blksz >> 1) >= HDA_BLK_MIN) 3160 blksz >>= 1; 3161 else 3162 break; 3163 } 3164 3165 if ((sndbuf_getblksz(ch->b) != blksz || 3166 sndbuf_getblkcnt(ch->b) != blkcnt) && 3167 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3168 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3169 __func__, blksz, blkcnt); 3170 3171 ch->blksz = sndbuf_getblksz(ch->b); 3172 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3173 3174 return (1); 3175} 3176 3177static int 3178hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3179{ 3180 struct hdac_chan *ch = data; 3181 struct hdac_softc *sc = ch->devinfo->codec->sc; 3182 3183 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3184 3185 return (ch->blksz); 3186} 3187 3188static void 3189hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3190{ 3191 struct hdac_devinfo *devinfo = ch->devinfo; 3192 nid_t cad = devinfo->codec->cad; 3193 int i; 3194 3195 hdac_stream_stop(ch); 3196 3197 for (i = 0; ch->io[i] != -1; i++) { 3198 hdac_command(sc, 3199 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3200 0), cad); 3201 } 3202} 3203 3204static void 3205hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3206{ 3207 ch->ptr = 0; 3208 ch->prevptr = 0; 3209 hdac_stream_stop(ch); 3210 hdac_stream_reset(ch); 3211 hdac_bdl_setup(ch); 3212 hdac_stream_setid(ch); 3213 hdac_stream_setup(ch); 3214 hdac_stream_start(ch); 3215} 3216 3217static int 3218hdac_channel_trigger(kobj_t obj, void *data, int go) 3219{ 3220 struct hdac_chan *ch = data; 3221 struct hdac_softc *sc = ch->devinfo->codec->sc; 3222 3223 if (!PCMTRIG_COMMON(go)) 3224 return (0); 3225 3226 hdac_lock(sc); 3227 switch (go) { 3228 case PCMTRIG_START: 3229 hdac_channel_start(sc, ch); 3230 break; 3231 case PCMTRIG_STOP: 3232 case PCMTRIG_ABORT: 3233 hdac_channel_stop(sc, ch); 3234 break; 3235 default: 3236 break; 3237 } 3238 hdac_unlock(sc); 3239 3240 return (0); 3241} 3242 3243static int 3244hdac_channel_getptr(kobj_t obj, void *data) 3245{ 3246 struct hdac_chan *ch = data; 3247 struct hdac_softc *sc = ch->devinfo->codec->sc; 3248 uint32_t ptr; 3249 3250 hdac_lock(sc); 3251 if (sc->polling != 0) 3252 ptr = ch->ptr; 3253 else if (ch->dmapos != NULL) 3254 ptr = *(ch->dmapos); 3255 else 3256 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3257 hdac_unlock(sc); 3258 3259 /* 3260 * Round to available space and force 128 bytes aligment. 3261 */ 3262 ptr %= ch->blksz * ch->blkcnt; 3263 ptr &= HDA_BLK_ALIGN; 3264 3265 return (ptr); 3266} 3267 3268static struct pcmchan_caps * 3269hdac_channel_getcaps(kobj_t obj, void *data) 3270{ 3271 return (&((struct hdac_chan *)data)->caps); 3272} 3273 3274static kobj_method_t hdac_channel_methods[] = { 3275 KOBJMETHOD(channel_init, hdac_channel_init), 3276 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3277 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3278 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3279 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3280 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3281 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3282 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3283 { 0, 0 } 3284}; 3285CHANNEL_DECLARE(hdac_channel); 3286 3287static void 3288hdac_jack_poll_callback(void *arg) 3289{ 3290 struct hdac_devinfo *devinfo = arg; 3291 struct hdac_softc *sc; 3292 3293 if (devinfo == NULL || devinfo->codec == NULL || 3294 devinfo->codec->sc == NULL) 3295 return; 3296 sc = devinfo->codec->sc; 3297 hdac_lock(sc); 3298 if (sc->poll_ival == 0) { 3299 hdac_unlock(sc); 3300 return; 3301 } 3302 hdac_hp_switch_handler(devinfo); 3303 callout_reset(&sc->poll_jack, sc->poll_ival, 3304 hdac_jack_poll_callback, devinfo); 3305 hdac_unlock(sc); 3306} 3307 3308static int 3309hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3310{ 3311 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3312 struct hdac_softc *sc = devinfo->codec->sc; 3313 struct hdac_widget *w, *cw; 3314 struct hdac_audio_ctl *ctl; 3315 uint32_t mask, recmask, id; 3316 int i, j, softpcmvol; 3317 nid_t cad; 3318 3319 hdac_lock(sc); 3320 3321 mask = 0; 3322 recmask = 0; 3323 3324 id = hdac_codec_id(devinfo); 3325 cad = devinfo->codec->cad; 3326 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3327 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3328 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3329 continue; 3330 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3331 if (w == NULL || w->enable == 0 || w->type != 3332 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3333 continue; 3334 if (hdac_hp_switch[i].polling != 0) 3335 callout_reset(&sc->poll_jack, 1, 3336 hdac_jack_poll_callback, devinfo); 3337 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3338 hdac_command(sc, 3339 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3340 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3341 HDAC_UNSOLTAG_EVENT_HP), cad); 3342 else 3343 continue; 3344 hdac_hp_switch_handler(devinfo); 3345 HDA_BOOTVERBOSE( 3346 device_printf(sc->dev, 3347 "HDA_DEBUG: Enabling headphone/speaker " 3348 "audio routing switching:\n"); 3349 device_printf(sc->dev, 3350 "HDA_DEBUG: \tindex=%d nid=%d " 3351 "pci_subvendor=0x%08x " 3352 "codec=0x%08x [%s]\n", 3353 i, w->nid, sc->pci_subvendor, id, 3354 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3355 "UNSOL"); 3356 ); 3357 break; 3358 } 3359 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3360 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3361 sc->pci_subvendor) && 3362 hdac_eapd_switch[i].id == id)) 3363 continue; 3364 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3365 if (w == NULL || w->enable == 0) 3366 break; 3367 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3368 w->param.eapdbtl == HDAC_INVALID) 3369 break; 3370 mask |= SOUND_MASK_OGAIN; 3371 break; 3372 } 3373 3374 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3375 w = hdac_widget_get(devinfo, i); 3376 if (w == NULL || w->enable == 0) 3377 continue; 3378 mask |= w->ctlflags; 3379 if (!(w->pflags & HDA_ADC_RECSEL)) 3380 continue; 3381 for (j = 0; j < w->nconns; j++) { 3382 cw = hdac_widget_get(devinfo, w->conns[j]); 3383 if (cw == NULL || cw->enable == 0) 3384 continue; 3385 recmask |= cw->ctlflags; 3386 } 3387 } 3388 3389 if (!(mask & SOUND_MASK_PCM)) { 3390 softpcmvol = 1; 3391 mask |= SOUND_MASK_PCM; 3392 } else 3393 softpcmvol = (devinfo->function.audio.quirks & 3394 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3395 3396 i = 0; 3397 ctl = NULL; 3398 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3399 if (ctl->widget == NULL || ctl->enable == 0) 3400 continue; 3401 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3402 continue; 3403 if (ctl->step > 0) 3404 break; 3405 } 3406 3407 if (softpcmvol == 1 || ctl == NULL) { 3408 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3409 HDA_BOOTVERBOSE( 3410 device_printf(sc->dev, 3411 "HDA_DEBUG: %s Soft PCM volume\n", 3412 (softpcmvol == 1) ? 3413 "Forcing" : "Enabling"); 3414 ); 3415 i = 0; 3416 /* 3417 * XXX Temporary quirk for STAC9220, until the parser 3418 * become smarter. 3419 */ 3420 if (id == HDA_CODEC_STAC9220) { 3421 mask |= SOUND_MASK_VOLUME; 3422 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3423 NULL) { 3424 if (ctl->widget == NULL || ctl->enable == 0) 3425 continue; 3426 if (ctl->widget->nid == 11 && ctl->index == 0) { 3427 ctl->ossmask = SOUND_MASK_VOLUME; 3428 ctl->ossval = 100 | (100 << 8); 3429 } else 3430 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3431 } 3432 } else if (id == HDA_CODEC_STAC9221) { 3433 mask |= SOUND_MASK_VOLUME; 3434 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3435 NULL) { 3436 if (ctl->widget == NULL) 3437 continue; 3438 if (ctl->widget->type == 3439 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3440 ctl->index == 0 && (ctl->widget->nid == 2 || 3441 ctl->widget->enable != 0)) { 3442 ctl->enable = 1; 3443 ctl->ossmask = SOUND_MASK_VOLUME; 3444 ctl->ossval = 100 | (100 << 8); 3445 } else if (ctl->enable == 0) 3446 continue; 3447 else 3448 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3449 } 3450 } else { 3451 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3452 SOUND_MASK_PCM); 3453 if (!(mask & SOUND_MASK_VOLUME)) 3454 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3455 SOUND_MIXER_NONE); 3456 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3457 NULL) { 3458 if (ctl->widget == NULL || ctl->enable == 0) 3459 continue; 3460 if (!HDA_FLAG_MATCH(ctl->ossmask, 3461 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3462 continue; 3463 if (!(ctl->mute == 1 && ctl->step == 0)) 3464 ctl->enable = 0; 3465 } 3466 } 3467 } 3468 3469 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3470 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3471 SOUND_MASK_OGAIN); 3472 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3473 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3474 3475 mix_setrecdevs(m, recmask); 3476 mix_setdevs(m, mask); 3477 3478 hdac_unlock(sc); 3479 3480 return (0); 3481} 3482 3483static int 3484hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3485 unsigned left, unsigned right) 3486{ 3487 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3488 struct hdac_softc *sc = devinfo->codec->sc; 3489 struct hdac_widget *w; 3490 struct hdac_audio_ctl *ctl; 3491 uint32_t id, mute; 3492 int lvol, rvol, mlvol, mrvol; 3493 int i = 0; 3494 3495 hdac_lock(sc); 3496 if (dev == SOUND_MIXER_OGAIN) { 3497 uint32_t orig; 3498 /*if (left != right || !(left == 0 || left == 1)) { 3499 hdac_unlock(sc); 3500 return (-1); 3501 }*/ 3502 id = hdac_codec_id(devinfo); 3503 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3504 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3505 sc->pci_subvendor) && 3506 hdac_eapd_switch[i].id == id) 3507 break; 3508 } 3509 if (i >= HDAC_EAPD_SWITCH_LEN) { 3510 hdac_unlock(sc); 3511 return (-1); 3512 } 3513 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3514 if (w == NULL || 3515 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3516 w->param.eapdbtl == HDAC_INVALID) { 3517 hdac_unlock(sc); 3518 return (-1); 3519 } 3520 orig = w->param.eapdbtl; 3521 if (left == 0) 3522 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3523 else 3524 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3525 if (orig != w->param.eapdbtl) { 3526 uint32_t val; 3527 3528 if (hdac_eapd_switch[i].hp_switch != 0) 3529 hdac_hp_switch_handler(devinfo); 3530 val = w->param.eapdbtl; 3531 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3532 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3533 hdac_command(sc, 3534 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3535 w->nid, val), devinfo->codec->cad); 3536 } 3537 hdac_unlock(sc); 3538 return (left | (left << 8)); 3539 } 3540 if (dev == SOUND_MIXER_VOLUME) 3541 devinfo->function.audio.mvol = left | (right << 8); 3542 3543 mlvol = devinfo->function.audio.mvol & 0x7f; 3544 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3545 lvol = 0; 3546 rvol = 0; 3547 3548 i = 0; 3549 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3550 if (ctl->widget == NULL || ctl->enable == 0 || 3551 !(ctl->ossmask & (1 << dev))) 3552 continue; 3553 switch (dev) { 3554 case SOUND_MIXER_VOLUME: 3555 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3556 lvol = (lvol * ctl->step) / 100; 3557 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3558 rvol = (rvol * ctl->step) / 100; 3559 break; 3560 default: 3561 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3562 lvol = (left * mlvol) / 100; 3563 lvol = (lvol * ctl->step) / 100; 3564 rvol = (right * mrvol) / 100; 3565 rvol = (rvol * ctl->step) / 100; 3566 } else { 3567 lvol = (left * ctl->step) / 100; 3568 rvol = (right * ctl->step) / 100; 3569 } 3570 ctl->ossval = left | (right << 8); 3571 break; 3572 } 3573 mute = 0; 3574 if (ctl->step < 1) { 3575 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3576 (ctl->muted & HDA_AMP_MUTE_LEFT); 3577 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3578 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3579 } else { 3580 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3581 (ctl->muted & HDA_AMP_MUTE_LEFT); 3582 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3583 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3584 } 3585 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3586 } 3587 hdac_unlock(sc); 3588 3589 return (left | (right << 8)); 3590} 3591 3592static int 3593hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3594{ 3595 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3596 struct hdac_widget *w, *cw; 3597 struct hdac_softc *sc = devinfo->codec->sc; 3598 uint32_t ret = src, target; 3599 int i, j; 3600 3601 target = 0; 3602 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3603 if (src & (1 << i)) { 3604 target = 1 << i; 3605 break; 3606 } 3607 } 3608 3609 hdac_lock(sc); 3610 3611 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3612 w = hdac_widget_get(devinfo, i); 3613 if (w == NULL || w->enable == 0) 3614 continue; 3615 if (!(w->pflags & HDA_ADC_RECSEL)) 3616 continue; 3617 for (j = 0; j < w->nconns; j++) { 3618 cw = hdac_widget_get(devinfo, w->conns[j]); 3619 if (cw == NULL || cw->enable == 0) 3620 continue; 3621 if ((target == SOUND_MASK_VOLUME && 3622 cw->type != 3623 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3624 (target != SOUND_MASK_VOLUME && 3625 cw->type == 3626 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3627 continue; 3628 if (cw->ctlflags & target) { 3629 if (!(w->pflags & HDA_ADC_LOCKED)) 3630 hdac_widget_connection_select(w, j); 3631 ret = target; 3632 j += w->nconns; 3633 } 3634 } 3635 } 3636 3637 hdac_unlock(sc); 3638 3639 return (ret); 3640} 3641 3642static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3643 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3644 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3645 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3646 { 0, 0 } 3647}; 3648MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3649 3650static void 3651hdac_unsolq_task(void *context, int pending) 3652{ 3653 struct hdac_softc *sc; 3654 3655 sc = (struct hdac_softc *)context; 3656 3657 hdac_lock(sc); 3658 hdac_unsolq_flush(sc); 3659 hdac_unlock(sc); 3660} 3661 3662/**************************************************************************** 3663 * int hdac_attach(device_t) 3664 * 3665 * Attach the device into the kernel. Interrupts usually won't be enabled 3666 * when this function is called. Setup everything that doesn't require 3667 * interrupts and defer probing of codecs until interrupts are enabled. 3668 ****************************************************************************/ 3669static int 3670hdac_attach(device_t dev) 3671{ 3672 struct hdac_softc *sc; 3673 int result; 3674 int i; 3675 uint16_t vendor; 3676 uint8_t v; 3677 3678 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3679 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3680 sc->dev = dev; 3681 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3682 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3683 vendor = pci_get_vendor(dev); 3684 3685 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3686 /* Screw nx6325 - subdevice/subvendor swapped */ 3687 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3688 } 3689 3690 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3691 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3692 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3693 3694 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3695 3696 sc->poll_ticks = 1; 3697 sc->poll_ival = HDAC_POLL_INTERVAL; 3698 if (resource_int_value(device_get_name(dev), 3699 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3700 sc->polling = 1; 3701 else 3702 sc->polling = 0; 3703 3704 sc->chan_size = pcm_getbuffersize(dev, 3705 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3706 3707 if (resource_int_value(device_get_name(dev), 3708 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3709 i &= HDA_BLK_ALIGN; 3710 if (i < HDA_BLK_MIN) 3711 i = HDA_BLK_MIN; 3712 sc->chan_blkcnt = sc->chan_size / i; 3713 i = 0; 3714 while (sc->chan_blkcnt >> i) 3715 i++; 3716 sc->chan_blkcnt = 1 << (i - 1); 3717 if (sc->chan_blkcnt < HDA_BDL_MIN) 3718 sc->chan_blkcnt = HDA_BDL_MIN; 3719 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3720 sc->chan_blkcnt = HDA_BDL_MAX; 3721 } else 3722 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3723 3724 result = bus_dma_tag_create(NULL, /* parent */ 3725 HDAC_DMA_ALIGNMENT, /* alignment */ 3726 0, /* boundary */ 3727 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3728 BUS_SPACE_MAXADDR, /* highaddr */ 3729 NULL, /* filtfunc */ 3730 NULL, /* fistfuncarg */ 3731 sc->chan_size, /* maxsize */ 3732 1, /* nsegments */ 3733 sc->chan_size, /* maxsegsz */ 3734 0, /* flags */ 3735 NULL, /* lockfunc */ 3736 NULL, /* lockfuncarg */ 3737 &sc->chan_dmat); /* dmat */ 3738 if (result != 0) { 3739 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3740 __func__, result); 3741 snd_mtxfree(sc->lock); 3742 free(sc, M_DEVBUF); 3743 return (ENXIO); 3744 } 3745 3746 3747 sc->hdabus = NULL; 3748 for (i = 0; i < HDAC_CODEC_MAX; i++) 3749 sc->codecs[i] = NULL; 3750 3751 pci_enable_busmaster(dev); 3752 3753 if (vendor == INTEL_VENDORID) { 3754 /* TCSEL -> TC0 */ 3755 v = pci_read_config(dev, 0x44, 1); 3756 pci_write_config(dev, 0x44, v & 0xf8, 1); 3757 HDA_BOOTVERBOSE( 3758 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3759 pci_read_config(dev, 0x44, 1)); 3760 ); 3761 } 3762 3763#if __FreeBSD_version >= 602106 3764 if (resource_int_value(device_get_name(dev), 3765 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 3766 pci_msi_count(dev) == 1) 3767 sc->flags |= HDAC_F_MSI; 3768 else 3769#endif 3770 sc->flags &= ~HDAC_F_MSI; 3771 3772#if defined(__i386__) || defined(__amd64__) 3773 sc->flags |= HDAC_F_DMA_NOCACHE; 3774 3775 if (resource_int_value(device_get_name(dev), 3776 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3777#else 3778 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3779#endif 3780 /* 3781 * Try to enable PCIe snoop to avoid messing around with 3782 * uncacheable DMA attribute. Since PCIe snoop register 3783 * config is pretty much vendor specific, there are no 3784 * general solutions on how to enable it, forcing us (even 3785 * Microsoft) to enable uncacheable or write combined DMA 3786 * by default. 3787 * 3788 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3789 */ 3790 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3791 if (hdac_pcie_snoop[i].vendor != vendor) 3792 continue; 3793 sc->flags &= ~HDAC_F_DMA_NOCACHE; 3794 if (hdac_pcie_snoop[i].reg == 0x00) 3795 break; 3796 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3797 if ((v & hdac_pcie_snoop[i].enable) == 3798 hdac_pcie_snoop[i].enable) 3799 break; 3800 v &= hdac_pcie_snoop[i].mask; 3801 v |= hdac_pcie_snoop[i].enable; 3802 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3803 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3804 if ((v & hdac_pcie_snoop[i].enable) != 3805 hdac_pcie_snoop[i].enable) { 3806 HDA_BOOTVERBOSE( 3807 device_printf(dev, 3808 "WARNING: Failed to enable PCIe " 3809 "snoop!\n"); 3810 ); 3811#if defined(__i386__) || defined(__amd64__) 3812 sc->flags |= HDAC_F_DMA_NOCACHE; 3813#endif 3814 } 3815 break; 3816 } 3817#if defined(__i386__) || defined(__amd64__) 3818 } 3819#endif 3820 3821 HDA_BOOTVERBOSE( 3822 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3823 (sc->flags & HDAC_F_DMA_NOCACHE) ? 3824 "Uncacheable" : "PCIe snoop", vendor); 3825 ); 3826 3827 /* Allocate resources */ 3828 result = hdac_mem_alloc(sc); 3829 if (result != 0) 3830 goto hdac_attach_fail; 3831 result = hdac_irq_alloc(sc); 3832 if (result != 0) 3833 goto hdac_attach_fail; 3834 3835 /* Get Capabilities */ 3836 result = hdac_get_capabilities(sc); 3837 if (result != 0) 3838 goto hdac_attach_fail; 3839 3840 /* Allocate CORB and RIRB dma memory */ 3841 result = hdac_dma_alloc(sc, &sc->corb_dma, 3842 sc->corb_size * sizeof(uint32_t)); 3843 if (result != 0) 3844 goto hdac_attach_fail; 3845 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3846 sc->rirb_size * sizeof(struct hdac_rirb)); 3847 if (result != 0) 3848 goto hdac_attach_fail; 3849 3850 /* Quiesce everything */ 3851 hdac_reset(sc); 3852 3853 /* Initialize the CORB and RIRB */ 3854 hdac_corb_init(sc); 3855 hdac_rirb_init(sc); 3856 3857 /* Defer remaining of initialization until interrupts are enabled */ 3858 sc->intrhook.ich_func = hdac_attach2; 3859 sc->intrhook.ich_arg = (void *)sc; 3860 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3861 sc->intrhook.ich_func = NULL; 3862 hdac_attach2((void *)sc); 3863 } 3864 3865 return (0); 3866 3867hdac_attach_fail: 3868 hdac_irq_free(sc); 3869 hdac_dma_free(sc, &sc->rirb_dma); 3870 hdac_dma_free(sc, &sc->corb_dma); 3871 hdac_mem_free(sc); 3872 snd_mtxfree(sc->lock); 3873 free(sc, M_DEVBUF); 3874 3875 return (ENXIO); 3876} 3877 3878static void 3879hdac_audio_parse(struct hdac_devinfo *devinfo) 3880{ 3881 struct hdac_softc *sc = devinfo->codec->sc; 3882 struct hdac_widget *w; 3883 uint32_t res; 3884 int i; 3885 nid_t cad, nid; 3886 3887 cad = devinfo->codec->cad; 3888 nid = devinfo->nid; 3889 3890 hdac_command(sc, 3891 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3892 3893 DELAY(100); 3894 3895 res = hdac_command(sc, 3896 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3897 3898 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3899 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3900 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3901 3902 res = hdac_command(sc, 3903 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3904 devinfo->function.audio.gpio = res; 3905 3906 HDA_BOOTVERBOSE( 3907 device_printf(sc->dev, " Vendor: 0x%08x\n", 3908 devinfo->vendor_id); 3909 device_printf(sc->dev, " Device: 0x%08x\n", 3910 devinfo->device_id); 3911 device_printf(sc->dev, " Revision: 0x%08x\n", 3912 devinfo->revision_id); 3913 device_printf(sc->dev, " Stepping: 0x%08x\n", 3914 devinfo->stepping_id); 3915 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3916 sc->pci_subvendor); 3917 device_printf(sc->dev, " Nodes: start=%d " 3918 "endnode=%d total=%d\n", 3919 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3920 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3921 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3922 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3923 sc->num_iss, sc->num_oss, sc->num_bss); 3924 device_printf(sc->dev, " GPIO: 0x%08x\n", 3925 devinfo->function.audio.gpio); 3926 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3927 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3928 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3929 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3930 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3931 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3932 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3933 ); 3934 3935 res = hdac_command(sc, 3936 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3937 cad); 3938 devinfo->function.audio.supp_stream_formats = res; 3939 3940 res = hdac_command(sc, 3941 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3942 cad); 3943 devinfo->function.audio.supp_pcm_size_rate = res; 3944 3945 res = hdac_command(sc, 3946 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3947 cad); 3948 devinfo->function.audio.outamp_cap = res; 3949 3950 res = hdac_command(sc, 3951 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3952 cad); 3953 devinfo->function.audio.inamp_cap = res; 3954 3955 if (devinfo->nodecnt > 0) 3956 devinfo->widget = (struct hdac_widget *)malloc( 3957 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3958 M_NOWAIT | M_ZERO); 3959 else 3960 devinfo->widget = NULL; 3961 3962 if (devinfo->widget == NULL) { 3963 device_printf(sc->dev, "unable to allocate widgets!\n"); 3964 devinfo->endnode = devinfo->startnode; 3965 devinfo->nodecnt = 0; 3966 return; 3967 } 3968 3969 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3970 w = hdac_widget_get(devinfo, i); 3971 if (w == NULL) 3972 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3973 else { 3974 w->devinfo = devinfo; 3975 w->nid = i; 3976 w->enable = 1; 3977 w->selconn = -1; 3978 w->pflags = 0; 3979 w->ctlflags = 0; 3980 w->param.eapdbtl = HDAC_INVALID; 3981 hdac_widget_parse(w); 3982 } 3983 } 3984} 3985 3986static void 3987hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3988{ 3989 struct hdac_softc *sc = devinfo->codec->sc; 3990 struct hdac_audio_ctl *ctls; 3991 struct hdac_widget *w, *cw; 3992 int i, j, cnt, max, ocap, icap; 3993 int mute, offset, step, size; 3994 3995 /* XXX This is redundant */ 3996 max = 0; 3997 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3998 w = hdac_widget_get(devinfo, i); 3999 if (w == NULL || w->enable == 0) 4000 continue; 4001 if (w->param.outamp_cap != 0) 4002 max++; 4003 if (w->param.inamp_cap != 0) { 4004 switch (w->type) { 4005 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4006 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4007 for (j = 0; j < w->nconns; j++) { 4008 cw = hdac_widget_get(devinfo, 4009 w->conns[j]); 4010 if (cw == NULL || cw->enable == 0) 4011 continue; 4012 max++; 4013 } 4014 break; 4015 default: 4016 max++; 4017 break; 4018 } 4019 } 4020 } 4021 4022 devinfo->function.audio.ctlcnt = max; 4023 4024 if (max < 1) 4025 return; 4026 4027 ctls = (struct hdac_audio_ctl *)malloc( 4028 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4029 4030 if (ctls == NULL) { 4031 /* Blekh! */ 4032 device_printf(sc->dev, "unable to allocate ctls!\n"); 4033 devinfo->function.audio.ctlcnt = 0; 4034 return; 4035 } 4036 4037 cnt = 0; 4038 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4039 if (cnt >= max) { 4040 device_printf(sc->dev, "%s: Ctl overflow!\n", 4041 __func__); 4042 break; 4043 } 4044 w = hdac_widget_get(devinfo, i); 4045 if (w == NULL || w->enable == 0) 4046 continue; 4047 ocap = w->param.outamp_cap; 4048 icap = w->param.inamp_cap; 4049 if (ocap != 0) { 4050 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4051 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4052 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4053 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4054 /*if (offset > step) { 4055 HDA_BOOTVERBOSE( 4056 device_printf(sc->dev, 4057 "HDA_DEBUG: BUGGY outamp: nid=%d " 4058 "[offset=%d > step=%d]\n", 4059 w->nid, offset, step); 4060 ); 4061 offset = step; 4062 }*/ 4063 ctls[cnt].enable = 1; 4064 ctls[cnt].widget = w; 4065 ctls[cnt].mute = mute; 4066 ctls[cnt].step = step; 4067 ctls[cnt].size = size; 4068 ctls[cnt].offset = offset; 4069 ctls[cnt].left = offset; 4070 ctls[cnt].right = offset; 4071 ctls[cnt++].dir = HDA_CTL_OUT; 4072 } 4073 4074 if (icap != 0) { 4075 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4076 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4077 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4078 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4079 /*if (offset > step) { 4080 HDA_BOOTVERBOSE( 4081 device_printf(sc->dev, 4082 "HDA_DEBUG: BUGGY inamp: nid=%d " 4083 "[offset=%d > step=%d]\n", 4084 w->nid, offset, step); 4085 ); 4086 offset = step; 4087 }*/ 4088 switch (w->type) { 4089 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4090 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4091 for (j = 0; j < w->nconns; j++) { 4092 if (cnt >= max) { 4093 device_printf(sc->dev, 4094 "%s: Ctl overflow!\n", 4095 __func__); 4096 break; 4097 } 4098 cw = hdac_widget_get(devinfo, 4099 w->conns[j]); 4100 if (cw == NULL || cw->enable == 0) 4101 continue; 4102 ctls[cnt].enable = 1; 4103 ctls[cnt].widget = w; 4104 ctls[cnt].childwidget = cw; 4105 ctls[cnt].index = j; 4106 ctls[cnt].mute = mute; 4107 ctls[cnt].step = step; 4108 ctls[cnt].size = size; 4109 ctls[cnt].offset = offset; 4110 ctls[cnt].left = offset; 4111 ctls[cnt].right = offset; 4112 ctls[cnt++].dir = HDA_CTL_IN; 4113 } 4114 break; 4115 default: 4116 if (cnt >= max) { 4117 device_printf(sc->dev, 4118 "%s: Ctl overflow!\n", 4119 __func__); 4120 break; 4121 } 4122 ctls[cnt].enable = 1; 4123 ctls[cnt].widget = w; 4124 ctls[cnt].mute = mute; 4125 ctls[cnt].step = step; 4126 ctls[cnt].size = size; 4127 ctls[cnt].offset = offset; 4128 ctls[cnt].left = offset; 4129 ctls[cnt].right = offset; 4130 ctls[cnt++].dir = HDA_CTL_IN; 4131 break; 4132 } 4133 } 4134 } 4135 4136 devinfo->function.audio.ctl = ctls; 4137} 4138 4139static const struct { 4140 uint32_t model; 4141 uint32_t id; 4142 uint32_t set, unset; 4143} hdac_quirks[] = { 4144 /* 4145 * XXX Force stereo quirk. Monoural recording / playback 4146 * on few codecs (especially ALC880) seems broken or 4147 * perhaps unsupported. 4148 */ 4149 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4150 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4151 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4152 HDA_QUIRK_GPIO0, 0 }, 4153 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4154 HDA_QUIRK_GPIO0, 0 }, 4155 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4156 HDA_QUIRK_GPIO0, 0 }, 4157 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4158 HDA_QUIRK_GPIO0, 0 }, 4159 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4160 HDA_QUIRK_GPIO0, 0 }, 4161 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4162 HDA_QUIRK_EAPDINV, 0 }, 4163 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4164 HDA_QUIRK_EAPDINV, 0 }, 4165 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4166 HDA_QUIRK_OVREF, 0 }, 4167 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4168 HDA_QUIRK_OVREF, 0 }, 4169 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4170 HDA_QUIRK_OVREF, 0 }, 4171 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4172 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4173 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4174 HDA_QUIRK_GPIO1, 0 }, 4175 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4176 HDA_QUIRK_EAPDINV, 0 }, 4177 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4178 HDA_QUIRK_EAPDINV, 0 }, 4179 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4180 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4181 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4182 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4183 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4184 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4185 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4186 0, HDA_QUIRK_FORCESTEREO }, 4187 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4188 HDA_QUIRK_SOFTPCMVOL, 0 } 4189}; 4190#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4191 4192static void 4193hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4194{ 4195 struct hdac_widget *w; 4196 struct hdac_audio_ctl *ctl; 4197 uint32_t id, subvendor; 4198 int i; 4199 4200 id = hdac_codec_id(devinfo); 4201 subvendor = devinfo->codec->sc->pci_subvendor; 4202 4203 /* 4204 * Quirks 4205 */ 4206 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4207 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4208 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4209 continue; 4210 if (hdac_quirks[i].set != 0) 4211 devinfo->function.audio.quirks |= 4212 hdac_quirks[i].set; 4213 if (hdac_quirks[i].unset != 0) 4214 devinfo->function.audio.quirks &= 4215 ~(hdac_quirks[i].unset); 4216 } 4217 4218 switch (id) { 4219 case HDA_CODEC_ALC260: 4220 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4221 w = hdac_widget_get(devinfo, i); 4222 if (w == NULL || w->enable == 0) 4223 continue; 4224 if (w->type != 4225 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4226 continue; 4227 if (w->nid != 5) 4228 w->enable = 0; 4229 } 4230 if (subvendor == HP_XW4300_SUBVENDOR) { 4231 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4232 if (ctl != NULL && ctl->widget != NULL) { 4233 ctl->ossmask = SOUND_MASK_SPEAKER; 4234 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4235 } 4236 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4237 if (ctl != NULL && ctl->widget != NULL) { 4238 ctl->ossmask = SOUND_MASK_SPEAKER; 4239 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4240 } 4241 } else if (subvendor == HP_3010_SUBVENDOR) { 4242 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4243 if (ctl != NULL && ctl->widget != NULL) { 4244 ctl->ossmask = SOUND_MASK_SPEAKER; 4245 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4246 } 4247 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4248 if (ctl != NULL && ctl->widget != NULL) { 4249 ctl->ossmask = SOUND_MASK_SPEAKER; 4250 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4251 } 4252 } 4253 break; 4254 case HDA_CODEC_ALC262: 4255 if (subvendor == HP_DC7700_SUBVENDOR) { 4256 ctl = hdac_audio_ctl_amp_get(devinfo, 22, 0, 1); 4257 if (ctl != NULL && ctl->widget != NULL) { 4258 ctl->ossmask = SOUND_MASK_SPEAKER; 4259 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4260 } 4261 ctl = hdac_audio_ctl_amp_get(devinfo, 27, 0, 1); 4262 if (ctl != NULL && ctl->widget != NULL) { 4263 ctl->ossmask = SOUND_MASK_SPEAKER; 4264 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4265 } 4266 } 4267 break; 4268 case HDA_CODEC_ALC861: 4269 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4270 if (ctl != NULL) 4271 ctl->muted = HDA_AMP_MUTE_ALL; 4272 break; 4273 case HDA_CODEC_ALC880: 4274 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4275 w = hdac_widget_get(devinfo, i); 4276 if (w == NULL || w->enable == 0) 4277 continue; 4278 if (w->type == 4279 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4280 w->nid != 9 && w->nid != 29) { 4281 w->enable = 0; 4282 } else if (w->type != 4283 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4284 w->nid == 29) { 4285 w->type = 4286 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4287 w->param.widget_cap &= 4288 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4289 w->param.widget_cap |= 4290 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4291 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4292 strlcpy(w->name, "beep widget", sizeof(w->name)); 4293 } 4294 } 4295 break; 4296 case HDA_CODEC_ALC883: 4297 /* 4298 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4299 * Clear vref cap for jack connectivity. 4300 */ 4301 w = hdac_widget_get(devinfo, 24); 4302 if (w != NULL && w->enable != 0 && w->type == 4303 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4304 (w->wclass.pin.config & 4305 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4306 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4307 w->wclass.pin.cap &= ~( 4308 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4309 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4310 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4311 w = hdac_widget_get(devinfo, 25); 4312 if (w != NULL && w->enable != 0 && w->type == 4313 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4314 (w->wclass.pin.config & 4315 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4316 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4317 w->wclass.pin.cap &= ~( 4318 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4319 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4320 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4321 /* 4322 * nid: 26 = Line-in, leave it alone. 4323 */ 4324 break; 4325 case HDA_CODEC_AD1981HD: 4326 w = hdac_widget_get(devinfo, 11); 4327 if (w != NULL && w->enable != 0 && w->nconns > 3) 4328 w->selconn = 3; 4329 if (subvendor == IBM_M52_SUBVENDOR) { 4330 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4331 if (ctl != NULL) 4332 ctl->ossmask = SOUND_MASK_SPEAKER; 4333 } 4334 break; 4335 case HDA_CODEC_AD1986A: 4336 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4337 w = hdac_widget_get(devinfo, i); 4338 if (w == NULL || w->enable == 0) 4339 continue; 4340 if (w->type != 4341 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4342 continue; 4343 if (w->nid != 3) 4344 w->enable = 0; 4345 } 4346 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4347 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4348 /* nid 28 is mic, nid 29 is line-in */ 4349 w = hdac_widget_get(devinfo, 15); 4350 if (w != NULL) 4351 w->selconn = 2; 4352 w = hdac_widget_get(devinfo, 16); 4353 if (w != NULL) 4354 w->selconn = 1; 4355 } 4356 break; 4357 case HDA_CODEC_AD1988: 4358 case HDA_CODEC_AD1988B: 4359 /*w = hdac_widget_get(devinfo, 12); 4360 if (w != NULL) { 4361 w->selconn = 1; 4362 w->pflags |= HDA_ADC_LOCKED; 4363 } 4364 w = hdac_widget_get(devinfo, 13); 4365 if (w != NULL) { 4366 w->selconn = 4; 4367 w->pflags |= HDA_ADC_LOCKED; 4368 } 4369 w = hdac_widget_get(devinfo, 14); 4370 if (w != NULL) { 4371 w->selconn = 2; 4372 w->pflags |= HDA_ADC_LOCKED; 4373 }*/ 4374 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4375 if (ctl != NULL) { 4376 ctl->ossmask = SOUND_MASK_IGAIN; 4377 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4378 } 4379 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4380 if (ctl != NULL) { 4381 ctl->ossmask = SOUND_MASK_IGAIN; 4382 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4383 } 4384 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4385 if (ctl != NULL) { 4386 ctl->ossmask = SOUND_MASK_IGAIN; 4387 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4388 } 4389 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4390 if (ctl != NULL) { 4391 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4392 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4393 } 4394 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4395 if (ctl != NULL) { 4396 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4397 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4398 } 4399 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4400 if (ctl != NULL) { 4401 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4402 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4403 } 4404 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4405 if (ctl != NULL) { 4406 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4407 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4408 } 4409 break; 4410 case HDA_CODEC_STAC9221: 4411 /* 4412 * Dell XPS M1210 need all DACs for each output jacks 4413 */ 4414 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4415 break; 4416 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4417 w = hdac_widget_get(devinfo, i); 4418 if (w == NULL || w->enable == 0) 4419 continue; 4420 if (w->type != 4421 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4422 continue; 4423 if (w->nid != 2) 4424 w->enable = 0; 4425 } 4426 break; 4427 case HDA_CODEC_STAC9221D: 4428 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4429 w = hdac_widget_get(devinfo, i); 4430 if (w == NULL || w->enable == 0) 4431 continue; 4432 if (w->type == 4433 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4434 w->nid != 6) 4435 w->enable = 0; 4436 4437 } 4438 break; 4439 case HDA_CODEC_STAC9227: 4440 w = hdac_widget_get(devinfo, 8); 4441 if (w != NULL) 4442 w->enable = 0; 4443 w = hdac_widget_get(devinfo, 9); 4444 if (w != NULL) 4445 w->enable = 0; 4446 break; 4447 case HDA_CODEC_CXWAIKIKI: 4448 if (subvendor == HP_DV5000_SUBVENDOR) { 4449 w = hdac_widget_get(devinfo, 27); 4450 if (w != NULL) 4451 w->enable = 0; 4452 } 4453 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4454 if (ctl != NULL) 4455 ctl->ossmask = SOUND_MASK_SKIP; 4456 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4457 if (ctl != NULL && ctl->childwidget != NULL && 4458 ctl->childwidget->enable != 0) { 4459 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4460 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4461 } 4462 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4463 if (ctl != NULL && ctl->childwidget != NULL && 4464 ctl->childwidget->enable != 0) { 4465 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4466 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4467 } 4468 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4469 if (ctl != NULL && ctl->childwidget != NULL && 4470 ctl->childwidget->enable != 0) { 4471 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4472 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4473 } 4474 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4475 if (ctl != NULL) { 4476 ctl->ossmask = SOUND_MASK_SKIP; 4477 /* XXX mixer \=rec mic broken.. why?!? */ 4478 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4479 } 4480 break; 4481 default: 4482 break; 4483 } 4484} 4485 4486static int 4487hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4488{ 4489 int *dev = &devinfo->function.audio.ossidx; 4490 4491 while (*dev < SOUND_MIXER_NRDEVICES) { 4492 switch (*dev) { 4493 case SOUND_MIXER_VOLUME: 4494 case SOUND_MIXER_BASS: 4495 case SOUND_MIXER_TREBLE: 4496 case SOUND_MIXER_PCM: 4497 case SOUND_MIXER_SPEAKER: 4498 case SOUND_MIXER_LINE: 4499 case SOUND_MIXER_MIC: 4500 case SOUND_MIXER_CD: 4501 case SOUND_MIXER_RECLEV: 4502 case SOUND_MIXER_IGAIN: 4503 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4504 (*dev)++; 4505 break; 4506 default: 4507 return (*dev)++; 4508 break; 4509 } 4510 } 4511 4512 return (-1); 4513} 4514 4515static int 4516hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4517{ 4518 struct hdac_widget *w; 4519 int i, ret = 0; 4520 4521 if (depth > HDA_PARSE_MAXDEPTH) 4522 return (0); 4523 w = hdac_widget_get(devinfo, nid); 4524 if (w == NULL || w->enable == 0) 4525 return (0); 4526 switch (w->type) { 4527 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4528 w->pflags |= HDA_DAC_PATH; 4529 ret = 1; 4530 break; 4531 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4532 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4533 for (i = 0; i < w->nconns; i++) { 4534 if (hdac_widget_find_dac_path(devinfo, 4535 w->conns[i], depth + 1) != 0) { 4536 if (w->selconn == -1) 4537 w->selconn = i; 4538 ret = 1; 4539 w->pflags |= HDA_DAC_PATH; 4540 } 4541 } 4542 break; 4543 default: 4544 break; 4545 } 4546 return (ret); 4547} 4548 4549static int 4550hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4551{ 4552 struct hdac_widget *w; 4553 int i, conndev, ret = 0; 4554 4555 if (depth > HDA_PARSE_MAXDEPTH) 4556 return (0); 4557 w = hdac_widget_get(devinfo, nid); 4558 if (w == NULL || w->enable == 0) 4559 return (0); 4560 switch (w->type) { 4561 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4562 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4563 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4564 for (i = 0; i < w->nconns; i++) { 4565 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4566 depth + 1) != 0) { 4567 if (w->selconn == -1) 4568 w->selconn = i; 4569 w->pflags |= HDA_ADC_PATH; 4570 ret = 1; 4571 } 4572 } 4573 break; 4574 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4575 conndev = w->wclass.pin.config & 4576 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4577 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4578 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4579 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4580 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4581 w->pflags |= HDA_ADC_PATH; 4582 ret = 1; 4583 } 4584 break; 4585 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4586 if (w->pflags & HDA_DAC_PATH) { 4587 w->pflags |= HDA_ADC_PATH; 4588 ret = 1; 4589 } 4590 break;*/ 4591 default: 4592 break; 4593 } 4594 return (ret); 4595} 4596 4597static uint32_t 4598hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4599 nid_t nid, nid_t pnid, int index, int depth) 4600{ 4601 struct hdac_widget *w, *pw; 4602 struct hdac_audio_ctl *ctl; 4603 uint32_t fl = 0; 4604 int i, ossdev, conndev, strategy; 4605 4606 if (depth > HDA_PARSE_MAXDEPTH) 4607 return (0); 4608 4609 w = hdac_widget_get(devinfo, nid); 4610 if (w == NULL || w->enable == 0) 4611 return (0); 4612 4613 pw = hdac_widget_get(devinfo, pnid); 4614 strategy = devinfo->function.audio.parsing_strategy; 4615 4616 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4617 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4618 for (i = 0; i < w->nconns; i++) { 4619 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4620 w->nid, i, depth + 1); 4621 } 4622 w->ctlflags |= fl; 4623 return (fl); 4624 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4625 (w->pflags & HDA_DAC_PATH)) { 4626 i = 0; 4627 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4628 if (ctl->enable == 0 || ctl->widget == NULL) 4629 continue; 4630 /* XXX This should be compressed! */ 4631 if (((ctl->widget->nid == w->nid) || 4632 (ctl->widget->nid == pnid && ctl->index == index && 4633 (ctl->dir & HDA_CTL_IN)) || 4634 (ctl->widget->nid == pnid && pw != NULL && 4635 pw->type == 4636 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4637 (pw->nconns < 2 || pw->selconn == index || 4638 pw->selconn == -1) && 4639 (ctl->dir & HDA_CTL_OUT)) || 4640 (strategy == HDA_PARSE_DIRECT && 4641 ctl->widget->nid == w->nid)) && 4642 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4643 /*if (pw != NULL && pw->selconn == -1) 4644 pw->selconn = index; 4645 fl |= SOUND_MASK_VOLUME; 4646 fl |= SOUND_MASK_PCM; 4647 ctl->ossmask |= SOUND_MASK_VOLUME; 4648 ctl->ossmask |= SOUND_MASK_PCM; 4649 ctl->ossdev = SOUND_MIXER_PCM;*/ 4650 if (!(w->ctlflags & SOUND_MASK_PCM) || 4651 (pw != NULL && 4652 !(pw->ctlflags & SOUND_MASK_PCM))) { 4653 fl |= SOUND_MASK_VOLUME; 4654 fl |= SOUND_MASK_PCM; 4655 ctl->ossmask |= SOUND_MASK_VOLUME; 4656 ctl->ossmask |= SOUND_MASK_PCM; 4657 ctl->ossdev = SOUND_MIXER_PCM; 4658 w->ctlflags |= SOUND_MASK_VOLUME; 4659 w->ctlflags |= SOUND_MASK_PCM; 4660 if (pw != NULL) { 4661 if (pw->selconn == -1) 4662 pw->selconn = index; 4663 pw->ctlflags |= 4664 SOUND_MASK_VOLUME; 4665 pw->ctlflags |= 4666 SOUND_MASK_PCM; 4667 } 4668 } 4669 } 4670 } 4671 w->ctlflags |= fl; 4672 return (fl); 4673 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4674 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4675 (w->pflags & HDA_ADC_PATH)) { 4676 conndev = w->wclass.pin.config & 4677 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4678 i = 0; 4679 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4680 if (ctl->enable == 0 || ctl->widget == NULL) 4681 continue; 4682 /* XXX This should be compressed! */ 4683 if (((ctl->widget->nid == pnid && ctl->index == index && 4684 (ctl->dir & HDA_CTL_IN)) || 4685 (ctl->widget->nid == pnid && pw != NULL && 4686 pw->type == 4687 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4688 (pw->nconns < 2 || pw->selconn == index || 4689 pw->selconn == -1) && 4690 (ctl->dir & HDA_CTL_OUT)) || 4691 (strategy == HDA_PARSE_DIRECT && 4692 ctl->widget->nid == w->nid)) && 4693 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4694 if (pw != NULL && pw->selconn == -1) 4695 pw->selconn = index; 4696 ossdev = 0; 4697 switch (conndev) { 4698 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4699 ossdev = SOUND_MIXER_MIC; 4700 break; 4701 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4702 ossdev = SOUND_MIXER_LINE; 4703 break; 4704 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4705 ossdev = SOUND_MIXER_CD; 4706 break; 4707 default: 4708 ossdev = 4709 hdac_audio_ctl_ossmixer_getnextdev( 4710 devinfo); 4711 if (ossdev < 0) 4712 ossdev = 0; 4713 break; 4714 } 4715 if (strategy == HDA_PARSE_MIXER) { 4716 fl |= SOUND_MASK_VOLUME; 4717 ctl->ossmask |= SOUND_MASK_VOLUME; 4718 } 4719 fl |= 1 << ossdev; 4720 ctl->ossmask |= 1 << ossdev; 4721 ctl->ossdev = ossdev; 4722 } 4723 } 4724 w->ctlflags |= fl; 4725 return (fl); 4726 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4727 i = 0; 4728 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4729 if (ctl->enable == 0 || ctl->widget == NULL) 4730 continue; 4731 /* XXX This should be compressed! */ 4732 if (((ctl->widget->nid == pnid && ctl->index == index && 4733 (ctl->dir & HDA_CTL_IN)) || 4734 (ctl->widget->nid == pnid && pw != NULL && 4735 pw->type == 4736 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4737 (pw->nconns < 2 || pw->selconn == index || 4738 pw->selconn == -1) && 4739 (ctl->dir & HDA_CTL_OUT)) || 4740 (strategy == HDA_PARSE_DIRECT && 4741 ctl->widget->nid == w->nid)) && 4742 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4743 if (pw != NULL && pw->selconn == -1) 4744 pw->selconn = index; 4745 fl |= SOUND_MASK_VOLUME; 4746 fl |= SOUND_MASK_SPEAKER; 4747 ctl->ossmask |= SOUND_MASK_VOLUME; 4748 ctl->ossmask |= SOUND_MASK_SPEAKER; 4749 ctl->ossdev = SOUND_MIXER_SPEAKER; 4750 } 4751 } 4752 w->ctlflags |= fl; 4753 return (fl); 4754 } 4755 return (0); 4756} 4757 4758static uint32_t 4759hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4760{ 4761 struct hdac_widget *w, *cw; 4762 struct hdac_audio_ctl *ctl; 4763 uint32_t fl; 4764 int i; 4765 4766 if (depth > HDA_PARSE_MAXDEPTH) 4767 return (0); 4768 4769 w = hdac_widget_get(devinfo, nid); 4770 if (w == NULL || w->enable == 0) 4771 return (0); 4772 /*if (!(w->pflags & HDA_ADC_PATH)) 4773 return (0); 4774 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4775 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4776 return (0);*/ 4777 i = 0; 4778 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4779 if (ctl->enable == 0 || ctl->widget == NULL) 4780 continue; 4781 if (ctl->widget->nid == nid) { 4782 ctl->ossmask |= SOUND_MASK_RECLEV; 4783 w->ctlflags |= SOUND_MASK_RECLEV; 4784 return (SOUND_MASK_RECLEV); 4785 } 4786 } 4787 for (i = 0; i < w->nconns; i++) { 4788 cw = hdac_widget_get(devinfo, w->conns[i]); 4789 if (cw == NULL || cw->enable == 0) 4790 continue; 4791 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4792 continue; 4793 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4794 if (fl != 0) { 4795 cw->ctlflags |= fl; 4796 w->ctlflags |= fl; 4797 return (fl); 4798 } 4799 } 4800 return (0); 4801} 4802 4803static int 4804hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4805{ 4806 struct hdac_widget *w, *cw; 4807 int i, child = 0; 4808 4809 if (depth > HDA_PARSE_MAXDEPTH) 4810 return (0); 4811 4812 w = hdac_widget_get(devinfo, nid); 4813 if (w == NULL || w->enable == 0) 4814 return (0); 4815 /*if (!(w->pflags & HDA_ADC_PATH)) 4816 return (0); 4817 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4818 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4819 return (0);*/ 4820 /* XXX weak! */ 4821 for (i = 0; i < w->nconns; i++) { 4822 cw = hdac_widget_get(devinfo, w->conns[i]); 4823 if (cw == NULL) 4824 continue; 4825 if (++child > 1) { 4826 w->pflags |= HDA_ADC_RECSEL; 4827 return (1); 4828 } 4829 } 4830 for (i = 0; i < w->nconns; i++) { 4831 if (hdac_audio_ctl_recsel_build(devinfo, 4832 w->conns[i], depth + 1) != 0) 4833 return (1); 4834 } 4835 return (0); 4836} 4837 4838static int 4839hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4840{ 4841 struct hdac_widget *w, *cw; 4842 int i, j, conndev, found_dac = 0; 4843 int strategy; 4844 4845 strategy = devinfo->function.audio.parsing_strategy; 4846 4847 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4848 w = hdac_widget_get(devinfo, i); 4849 if (w == NULL || w->enable == 0) 4850 continue; 4851 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4852 continue; 4853 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4854 continue; 4855 conndev = w->wclass.pin.config & 4856 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4857 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4858 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4859 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4860 continue; 4861 for (j = 0; j < w->nconns; j++) { 4862 cw = hdac_widget_get(devinfo, w->conns[j]); 4863 if (cw == NULL || cw->enable == 0) 4864 continue; 4865 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4866 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4867 cw->type == 4868 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4869 continue; 4870 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4871 != 0) { 4872 if (w->selconn == -1) 4873 w->selconn = j; 4874 w->pflags |= HDA_DAC_PATH; 4875 found_dac++; 4876 } 4877 } 4878 } 4879 4880 return (found_dac); 4881} 4882 4883static void 4884hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4885{ 4886 struct hdac_widget *w; 4887 struct hdac_audio_ctl *ctl; 4888 int i, j, dacs, strategy; 4889 4890 /* Construct DAC path */ 4891 strategy = HDA_PARSE_MIXER; 4892 devinfo->function.audio.parsing_strategy = strategy; 4893 HDA_BOOTVERBOSE( 4894 device_printf(devinfo->codec->sc->dev, 4895 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4896 HDA_WIDGET_PARSER_REV); 4897 ); 4898 dacs = hdac_audio_build_tree_strategy(devinfo); 4899 if (dacs == 0) { 4900 HDA_BOOTVERBOSE( 4901 device_printf(devinfo->codec->sc->dev, 4902 "HDA_DEBUG: HWiP: 0 DAC path found! " 4903 "Retrying parser " 4904 "using HDA_PARSE_DIRECT strategy.\n"); 4905 ); 4906 strategy = HDA_PARSE_DIRECT; 4907 devinfo->function.audio.parsing_strategy = strategy; 4908 dacs = hdac_audio_build_tree_strategy(devinfo); 4909 } 4910 4911 HDA_BOOTVERBOSE( 4912 device_printf(devinfo->codec->sc->dev, 4913 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4914 "strategy.\n", 4915 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4916 ); 4917 4918 /* Construct ADC path */ 4919 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4920 w = hdac_widget_get(devinfo, i); 4921 if (w == NULL || w->enable == 0) 4922 continue; 4923 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4924 continue; 4925 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4926 } 4927 4928 /* Output mixers */ 4929 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4930 w = hdac_widget_get(devinfo, i); 4931 if (w == NULL || w->enable == 0) 4932 continue; 4933 if ((strategy == HDA_PARSE_MIXER && 4934 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4935 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4936 && (w->pflags & HDA_DAC_PATH)) || 4937 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4938 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4939 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4940 w->nid, devinfo->startnode - 1, 0, 0); 4941 } else if (w->type == 4942 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4943 j = 0; 4944 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4945 NULL) { 4946 if (ctl->enable == 0 || ctl->widget == NULL) 4947 continue; 4948 if (ctl->widget->nid != w->nid) 4949 continue; 4950 ctl->ossmask |= SOUND_MASK_VOLUME; 4951 ctl->ossmask |= SOUND_MASK_SPEAKER; 4952 ctl->ossdev = SOUND_MIXER_SPEAKER; 4953 w->ctlflags |= SOUND_MASK_VOLUME; 4954 w->ctlflags |= SOUND_MASK_SPEAKER; 4955 } 4956 } 4957 } 4958 4959 /* Input mixers (rec) */ 4960 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4961 w = hdac_widget_get(devinfo, i); 4962 if (w == NULL || w->enable == 0) 4963 continue; 4964 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4965 w->pflags & HDA_ADC_PATH)) 4966 continue; 4967 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4968 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4969 } 4970} 4971 4972#define HDA_COMMIT_CONN (1 << 0) 4973#define HDA_COMMIT_CTRL (1 << 1) 4974#define HDA_COMMIT_EAPD (1 << 2) 4975#define HDA_COMMIT_GPIO (1 << 3) 4976#define HDA_COMMIT_MISC (1 << 4) 4977#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4978 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 4979 4980static void 4981hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4982{ 4983 struct hdac_softc *sc = devinfo->codec->sc; 4984 struct hdac_widget *w; 4985 nid_t cad; 4986 int i; 4987 4988 if (!(cfl & HDA_COMMIT_ALL)) 4989 return; 4990 4991 cad = devinfo->codec->cad; 4992 4993 if ((cfl & HDA_COMMIT_MISC)) { 4994 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4995 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4996 0x7e7, 0), cad); 4997 } 4998 4999 if (cfl & HDA_COMMIT_GPIO) { 5000 uint32_t gdata, gmask, gdir; 5001 int commitgpio, numgpio; 5002 5003 gdata = 0; 5004 gmask = 0; 5005 gdir = 0; 5006 commitgpio = 0; 5007 5008 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 5009 devinfo->function.audio.gpio); 5010 5011 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 5012 commitgpio = (numgpio > 0) ? 1 : 0; 5013 else { 5014 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 5015 if (!(devinfo->function.audio.quirks & 5016 (1 << i))) 5017 continue; 5018 if (commitgpio == 0) { 5019 commitgpio = 1; 5020 HDA_BOOTVERBOSE( 5021 gdata = hdac_command(sc, 5022 HDA_CMD_GET_GPIO_DATA(cad, 5023 devinfo->nid), cad); 5024 gmask = hdac_command(sc, 5025 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 5026 devinfo->nid), cad); 5027 gdir = hdac_command(sc, 5028 HDA_CMD_GET_GPIO_DIRECTION(cad, 5029 devinfo->nid), cad); 5030 device_printf(sc->dev, 5031 "GPIO init: data=0x%08x " 5032 "mask=0x%08x dir=0x%08x\n", 5033 gdata, gmask, gdir); 5034 gdata = 0; 5035 gmask = 0; 5036 gdir = 0; 5037 ); 5038 } 5039 gdata |= 1 << i; 5040 gmask |= 1 << i; 5041 gdir |= 1 << i; 5042 } 5043 } 5044 5045 if (commitgpio != 0) { 5046 HDA_BOOTVERBOSE( 5047 device_printf(sc->dev, 5048 "GPIO commit: data=0x%08x mask=0x%08x " 5049 "dir=0x%08x\n", 5050 gdata, gmask, gdir); 5051 ); 5052 hdac_command(sc, 5053 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 5054 gmask), cad); 5055 hdac_command(sc, 5056 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 5057 gdir), cad); 5058 hdac_command(sc, 5059 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 5060 gdata), cad); 5061 } 5062 } 5063 5064 for (i = 0; i < devinfo->nodecnt; i++) { 5065 w = &devinfo->widget[i]; 5066 if (w == NULL || w->enable == 0) 5067 continue; 5068 if (cfl & HDA_COMMIT_CONN) { 5069 if (w->selconn == -1) 5070 w->selconn = 0; 5071 if (w->nconns > 0) 5072 hdac_widget_connection_select(w, w->selconn); 5073 } 5074 if ((cfl & HDA_COMMIT_CTRL) && 5075 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5076 uint32_t pincap; 5077 5078 pincap = w->wclass.pin.cap; 5079 5080 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5081 (HDA_DAC_PATH | HDA_ADC_PATH)) 5082 device_printf(sc->dev, "WARNING: node %d " 5083 "participate both for DAC/ADC!\n", w->nid); 5084 if (w->pflags & HDA_DAC_PATH) { 5085 w->wclass.pin.ctrl &= 5086 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5087 if ((w->wclass.pin.config & 5088 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5089 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5090 w->wclass.pin.ctrl &= 5091 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5092 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5093 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5094 w->wclass.pin.ctrl |= 5095 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5096 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5097 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5098 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5099 w->wclass.pin.ctrl |= 5100 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5101 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5102 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5103 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5104 w->wclass.pin.ctrl |= 5105 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5106 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5107 } else if (w->pflags & HDA_ADC_PATH) { 5108 w->wclass.pin.ctrl &= 5109 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5110 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5111 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5112 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5113 w->wclass.pin.ctrl |= 5114 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5115 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5116 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5117 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5118 w->wclass.pin.ctrl |= 5119 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5120 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5121 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5122 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5123 w->wclass.pin.ctrl |= 5124 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5125 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5126 } else 5127 w->wclass.pin.ctrl &= ~( 5128 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5129 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5130 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5131 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5132 hdac_command(sc, 5133 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5134 w->wclass.pin.ctrl), cad); 5135 } 5136 if ((cfl & HDA_COMMIT_EAPD) && 5137 w->param.eapdbtl != HDAC_INVALID) { 5138 uint32_t val; 5139 5140 val = w->param.eapdbtl; 5141 if (devinfo->function.audio.quirks & 5142 HDA_QUIRK_EAPDINV) 5143 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5144 hdac_command(sc, 5145 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5146 val), cad); 5147 5148 } 5149 DELAY(1000); 5150 } 5151} 5152 5153static void 5154hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5155{ 5156 struct hdac_softc *sc = devinfo->codec->sc; 5157 struct hdac_audio_ctl *ctl; 5158 int i; 5159 5160 devinfo->function.audio.mvol = 100 | (100 << 8); 5161 i = 0; 5162 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5163 if (ctl->enable == 0 || ctl->widget == NULL) { 5164 HDA_BOOTVERBOSE( 5165 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5166 i, (ctl->widget != NULL) ? 5167 ctl->widget->nid : -1); 5168 if (ctl->childwidget != NULL) 5169 printf(" childnid=%d", 5170 ctl->childwidget->nid); 5171 if (ctl->widget == NULL) 5172 printf(" NULL WIDGET!"); 5173 printf(" DISABLED\n"); 5174 ); 5175 continue; 5176 } 5177 HDA_BOOTVERBOSE( 5178 if (ctl->ossmask == 0) { 5179 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5180 i, ctl->widget->nid); 5181 if (ctl->childwidget != NULL) 5182 printf(" childnid=%d", 5183 ctl->childwidget->nid); 5184 printf(" Bind to NONE\n"); 5185 } 5186 ); 5187 if (ctl->step > 0) { 5188 ctl->ossval = (ctl->left * 100) / ctl->step; 5189 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5190 } else 5191 ctl->ossval = 0; 5192 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5193 ctl->left, ctl->right); 5194 } 5195} 5196 5197static int 5198hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5199{ 5200 struct hdac_chan *ch; 5201 struct hdac_widget *w; 5202 uint32_t cap, fmtcap, pcmcap, path; 5203 int i, type, ret, max; 5204 5205 if (dir == PCMDIR_PLAY) { 5206 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5207 ch = &devinfo->codec->sc->play; 5208 path = HDA_DAC_PATH; 5209 } else { 5210 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5211 ch = &devinfo->codec->sc->rec; 5212 path = HDA_ADC_PATH; 5213 } 5214 5215 ch->caps = hdac_caps; 5216 ch->caps.fmtlist = ch->fmtlist; 5217 ch->bit16 = 1; 5218 ch->bit32 = 0; 5219 ch->pcmrates[0] = 48000; 5220 ch->pcmrates[1] = 0; 5221 5222 ret = 0; 5223 fmtcap = devinfo->function.audio.supp_stream_formats; 5224 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5225 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5226 5227 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5228 w = hdac_widget_get(devinfo, i); 5229 if (w == NULL || w->enable == 0 || w->type != type || 5230 !(w->pflags & path)) 5231 continue; 5232 cap = w->param.widget_cap; 5233 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5234 continue;*/ 5235 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5236 continue; 5237 cap = w->param.supp_stream_formats; 5238 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5239 } 5240 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5241 }*/ 5242 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5243 continue; 5244 if (ret == 0) { 5245 fmtcap = w->param.supp_stream_formats; 5246 pcmcap = w->param.supp_pcm_size_rate; 5247 } else { 5248 fmtcap &= w->param.supp_stream_formats; 5249 pcmcap &= w->param.supp_pcm_size_rate; 5250 } 5251 ch->io[ret++] = i; 5252 } 5253 ch->io[ret] = -1; 5254 5255 ch->supp_stream_formats = fmtcap; 5256 ch->supp_pcm_size_rate = pcmcap; 5257 5258 /* 5259 * 8bit = 0 5260 * 16bit = 1 5261 * 20bit = 2 5262 * 24bit = 3 5263 * 32bit = 4 5264 */ 5265 if (ret > 0) { 5266 cap = pcmcap; 5267 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5268 ch->bit16 = 1; 5269 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5270 ch->bit16 = 0; 5271 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5272 ch->bit32 = 4; 5273 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5274 ch->bit32 = 3; 5275 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5276 ch->bit32 = 2; 5277 i = 0; 5278 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5279 ch->fmtlist[i++] = AFMT_S16_LE; 5280 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5281 if (ch->bit32 > 0) { 5282 if (!(devinfo->function.audio.quirks & 5283 HDA_QUIRK_FORCESTEREO)) 5284 ch->fmtlist[i++] = AFMT_S32_LE; 5285 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5286 } 5287 ch->fmtlist[i] = 0; 5288 i = 0; 5289 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5290 ch->pcmrates[i++] = 8000; 5291 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5292 ch->pcmrates[i++] = 11025; 5293 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5294 ch->pcmrates[i++] = 16000; 5295 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5296 ch->pcmrates[i++] = 22050; 5297 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5298 ch->pcmrates[i++] = 32000; 5299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5300 ch->pcmrates[i++] = 44100; 5301 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5302 ch->pcmrates[i++] = 48000; 5303 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5304 ch->pcmrates[i++] = 88200; 5305 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5306 ch->pcmrates[i++] = 96000; 5307 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5308 ch->pcmrates[i++] = 176400; 5309 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5310 ch->pcmrates[i++] = 192000; 5311 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5312 ch->pcmrates[i] = 0; 5313 if (i > 0) { 5314 ch->caps.minspeed = ch->pcmrates[0]; 5315 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5316 } 5317 } 5318 5319 return (ret); 5320} 5321 5322static void 5323hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5324{ 5325 struct hdac_audio_ctl *ctl; 5326 struct hdac_softc *sc = devinfo->codec->sc; 5327 int i; 5328 uint32_t fl = 0; 5329 5330 5331 if (flag == 0) { 5332 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5333 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5334 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5335 } 5336 5337 i = 0; 5338 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5339 if (ctl->enable == 0 || ctl->widget == NULL || 5340 ctl->widget->enable == 0 || (ctl->ossmask & 5341 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5342 continue; 5343 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5344 (flag != 0 && (ctl->ossmask & flag))) { 5345 if (banner != NULL) { 5346 device_printf(sc->dev, "\n"); 5347 device_printf(sc->dev, "%s\n", banner); 5348 } 5349 goto hdac_ctl_dump_it_all; 5350 } 5351 } 5352 5353 return; 5354 5355hdac_ctl_dump_it_all: 5356 i = 0; 5357 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5358 if (ctl->enable == 0 || ctl->widget == NULL || 5359 ctl->widget->enable == 0) 5360 continue; 5361 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5362 (flag != 0 && (ctl->ossmask & flag)))) 5363 continue; 5364 if (flag == 0) { 5365 device_printf(sc->dev, "\n"); 5366 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5367 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5368 } 5369 device_printf(sc->dev, " |\n"); 5370 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5371 ctl->widget->nid, ctl->index); 5372 if (ctl->childwidget != NULL) 5373 printf("(nid: %2d) ", ctl->childwidget->nid); 5374 else 5375 printf(" "); 5376 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5377 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5378 ctl->ossmask); 5379 } 5380} 5381 5382static void 5383hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5384{ 5385 uint32_t cap; 5386 5387 cap = fcap; 5388 if (cap != 0) { 5389 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5390 device_printf(sc->dev, " Format:"); 5391 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5392 printf(" AC3"); 5393 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5394 printf(" FLOAT32"); 5395 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5396 printf(" PCM"); 5397 printf("\n"); 5398 } 5399 cap = pcmcap; 5400 if (cap != 0) { 5401 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5402 device_printf(sc->dev, " PCM size:"); 5403 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5404 printf(" 8"); 5405 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5406 printf(" 16"); 5407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5408 printf(" 20"); 5409 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5410 printf(" 24"); 5411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5412 printf(" 32"); 5413 printf("\n"); 5414 device_printf(sc->dev, " PCM rate:"); 5415 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5416 printf(" 8"); 5417 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5418 printf(" 11"); 5419 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5420 printf(" 16"); 5421 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5422 printf(" 22"); 5423 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5424 printf(" 32"); 5425 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5426 printf(" 44"); 5427 printf(" 48"); 5428 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5429 printf(" 88"); 5430 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5431 printf(" 96"); 5432 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5433 printf(" 176"); 5434 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5435 printf(" 192"); 5436 printf("\n"); 5437 } 5438} 5439 5440static void 5441hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5442{ 5443 uint32_t pincap, wcap; 5444 5445 pincap = w->wclass.pin.cap; 5446 wcap = w->param.widget_cap; 5447 5448 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5449 device_printf(sc->dev, " "); 5450 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5451 printf(" ISC"); 5452 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5453 printf(" TRQD"); 5454 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5455 printf(" PDC"); 5456 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5457 printf(" HP"); 5458 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5459 printf(" OUT"); 5460 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5461 printf(" IN"); 5462 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5463 printf(" BAL"); 5464 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5465 printf(" VREF["); 5466 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5467 printf(" 50"); 5468 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5469 printf(" 80"); 5470 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5471 printf(" 100"); 5472 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5473 printf(" GROUND"); 5474 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5475 printf(" HIZ"); 5476 printf(" ]"); 5477 } 5478 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5479 printf(" EAPD"); 5480 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5481 printf(" : UNSOL"); 5482 printf("\n"); 5483 device_printf(sc->dev, " Pin config: 0x%08x\n", 5484 w->wclass.pin.config); 5485 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5486 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5487 printf(" HP"); 5488 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5489 printf(" IN"); 5490 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5491 printf(" OUT"); 5492 printf("\n"); 5493} 5494 5495static void 5496hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5497{ 5498 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5499 device_printf(sc->dev, " " 5500 "mute=%d step=%d size=%d offset=%d\n", 5501 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5502 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5503 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5504 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5505} 5506 5507static void 5508hdac_dump_nodes(struct hdac_devinfo *devinfo) 5509{ 5510 struct hdac_softc *sc = devinfo->codec->sc; 5511 struct hdac_widget *w, *cw; 5512 int i, j; 5513 5514 device_printf(sc->dev, "\n"); 5515 device_printf(sc->dev, "Default Parameter\n"); 5516 device_printf(sc->dev, "-----------------\n"); 5517 hdac_dump_audio_formats(sc, 5518 devinfo->function.audio.supp_stream_formats, 5519 devinfo->function.audio.supp_pcm_size_rate); 5520 device_printf(sc->dev, " IN amp: 0x%08x\n", 5521 devinfo->function.audio.inamp_cap); 5522 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5523 devinfo->function.audio.outamp_cap); 5524 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5525 w = hdac_widget_get(devinfo, i); 5526 if (w == NULL) { 5527 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5528 continue; 5529 } 5530 device_printf(sc->dev, "\n"); 5531 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5532 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5533 "DIGITAL" : "ANALOG", 5534 (w->enable == 0) ? " [DISABLED]" : ""); 5535 device_printf(sc->dev, " name: %s\n", w->name); 5536 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5537 w->param.widget_cap); 5538 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5539 w->pflags); 5540 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5541 w->ctlflags); 5542 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5543 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5544 hdac_dump_audio_formats(sc, 5545 w->param.supp_stream_formats, 5546 w->param.supp_pcm_size_rate); 5547 } else if (w->type == 5548 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5549 hdac_dump_pin(sc, w); 5550 if (w->param.eapdbtl != HDAC_INVALID) 5551 device_printf(sc->dev, " EAPD: 0x%08x\n", 5552 w->param.eapdbtl); 5553 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5554 w->param.outamp_cap != 0) 5555 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5556 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5557 w->param.inamp_cap != 0) 5558 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5559 device_printf(sc->dev, " connections: %d\n", w->nconns); 5560 for (j = 0; j < w->nconns; j++) { 5561 cw = hdac_widget_get(devinfo, w->conns[j]); 5562 device_printf(sc->dev, " |\n"); 5563 device_printf(sc->dev, " + <- nid=%d [%s]", 5564 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5565 if (cw == NULL) 5566 printf(" [UNKNOWN]"); 5567 else if (cw->enable == 0) 5568 printf(" [DISABLED]"); 5569 if (w->nconns > 1 && w->selconn == j && w->type != 5570 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5571 printf(" (selected)"); 5572 printf("\n"); 5573 } 5574 } 5575 5576} 5577 5578static int 5579hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5580{ 5581 struct hdac_widget *w, *cw; 5582 struct hdac_softc *sc = devinfo->codec->sc; 5583 int i; 5584 5585 if (depth > HDA_PARSE_MAXDEPTH) 5586 return (0); 5587 5588 w = hdac_widget_get(devinfo, nid); 5589 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5590 return (0); 5591 5592 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5593 device_printf(sc->dev, "\n"); 5594 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5595 device_printf(sc->dev, " ^\n"); 5596 device_printf(sc->dev, " |\n"); 5597 device_printf(sc->dev, " +-----<------+\n"); 5598 } else { 5599 device_printf(sc->dev, " ^\n"); 5600 device_printf(sc->dev, " |\n"); 5601 device_printf(sc->dev, " "); 5602 printf(" nid=%d [%s]\n", w->nid, w->name); 5603 } 5604 5605 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5606 return (1); 5607 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5608 for (i = 0; i < w->nconns; i++) { 5609 cw = hdac_widget_get(devinfo, w->conns[i]); 5610 if (cw == NULL || cw->enable == 0 || cw->type == 5611 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5612 continue; 5613 if (hdac_dump_dac_internal(devinfo, cw->nid, 5614 depth + 1) != 0) 5615 return (1); 5616 } 5617 } else if ((w->type == 5618 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5619 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5620 w->selconn > -1 && w->selconn < w->nconns) { 5621 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5622 depth + 1) != 0) 5623 return (1); 5624 } 5625 5626 return (0); 5627} 5628 5629static void 5630hdac_dump_dac(struct hdac_devinfo *devinfo) 5631{ 5632 struct hdac_widget *w; 5633 struct hdac_softc *sc = devinfo->codec->sc; 5634 int i, printed = 0; 5635 5636 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5637 w = hdac_widget_get(devinfo, i); 5638 if (w == NULL || w->enable == 0) 5639 continue; 5640 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5641 !(w->pflags & HDA_DAC_PATH)) 5642 continue; 5643 if (printed == 0) { 5644 printed = 1; 5645 device_printf(sc->dev, "\n"); 5646 device_printf(sc->dev, "Playback path:\n"); 5647 } 5648 hdac_dump_dac_internal(devinfo, w->nid, 0); 5649 } 5650} 5651 5652static void 5653hdac_dump_adc(struct hdac_devinfo *devinfo) 5654{ 5655 struct hdac_widget *w, *cw; 5656 struct hdac_softc *sc = devinfo->codec->sc; 5657 int i, j; 5658 int printed = 0; 5659 char ossdevs[256]; 5660 5661 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5662 w = hdac_widget_get(devinfo, i); 5663 if (w == NULL || w->enable == 0) 5664 continue; 5665 if (!(w->pflags & HDA_ADC_RECSEL)) 5666 continue; 5667 if (printed == 0) { 5668 printed = 1; 5669 device_printf(sc->dev, "\n"); 5670 device_printf(sc->dev, "Recording sources:\n"); 5671 } 5672 device_printf(sc->dev, "\n"); 5673 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5674 for (j = 0; j < w->nconns; j++) { 5675 cw = hdac_widget_get(devinfo, w->conns[j]); 5676 if (cw == NULL || cw->enable == 0) 5677 continue; 5678 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5679 ossdevs, sizeof(ossdevs)); 5680 device_printf(sc->dev, " |\n"); 5681 device_printf(sc->dev, " + <- nid=%d [%s]", 5682 cw->nid, cw->name); 5683 if (strlen(ossdevs) > 0) { 5684 printf(" [recsrc: %s]", ossdevs); 5685 } 5686 printf("\n"); 5687 } 5688 } 5689} 5690 5691static void 5692hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5693{ 5694 nid_t *nids; 5695 5696 if (pcnt > 0) { 5697 device_printf(sc->dev, "\n"); 5698 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5699 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5700 sc->play.supp_pcm_size_rate); 5701 device_printf(sc->dev, " DAC:"); 5702 for (nids = sc->play.io; *nids != -1; nids++) 5703 printf(" %d", *nids); 5704 printf("\n"); 5705 } 5706 5707 if (rcnt > 0) { 5708 device_printf(sc->dev, "\n"); 5709 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5710 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5711 sc->rec.supp_pcm_size_rate); 5712 device_printf(sc->dev, " ADC:"); 5713 for (nids = sc->rec.io; *nids != -1; nids++) 5714 printf(" %d", *nids); 5715 printf("\n"); 5716 } 5717} 5718 5719static void 5720hdac_release_resources(struct hdac_softc *sc) 5721{ 5722 struct hdac_devinfo *devinfo = NULL; 5723 device_t *devlist = NULL; 5724 int i, devcount; 5725 5726 if (sc == NULL) 5727 return; 5728 5729 hdac_lock(sc); 5730 sc->polling = 0; 5731 sc->poll_ival = 0; 5732 callout_stop(&sc->poll_hda); 5733 callout_stop(&sc->poll_hdac); 5734 callout_stop(&sc->poll_jack); 5735 hdac_reset(sc); 5736 hdac_unlock(sc); 5737 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5738 callout_drain(&sc->poll_hda); 5739 callout_drain(&sc->poll_hdac); 5740 callout_drain(&sc->poll_jack); 5741 5742 hdac_irq_free(sc); 5743 5744 device_get_children(sc->dev, &devlist, &devcount); 5745 for (i = 0; devlist != NULL && i < devcount; i++) { 5746 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5747 if (devinfo == NULL) 5748 continue; 5749 if (devinfo->widget != NULL) 5750 free(devinfo->widget, M_HDAC); 5751 if (devinfo->node_type == 5752 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5753 devinfo->function.audio.ctl != NULL) 5754 free(devinfo->function.audio.ctl, M_HDAC); 5755 free(devinfo, M_HDAC); 5756 device_delete_child(sc->dev, devlist[i]); 5757 } 5758 if (devlist != NULL) 5759 free(devlist, M_TEMP); 5760 5761 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5762 if (sc->codecs[i] != NULL) 5763 free(sc->codecs[i], M_HDAC); 5764 sc->codecs[i] = NULL; 5765 } 5766 5767 hdac_dma_free(sc, &sc->pos_dma); 5768 hdac_dma_free(sc, &sc->rirb_dma); 5769 hdac_dma_free(sc, &sc->corb_dma); 5770 if (sc->play.blkcnt > 0) 5771 hdac_dma_free(sc, &sc->play.bdl_dma); 5772 if (sc->rec.blkcnt > 0) 5773 hdac_dma_free(sc, &sc->rec.bdl_dma); 5774 if (sc->chan_dmat != NULL) { 5775 bus_dma_tag_destroy(sc->chan_dmat); 5776 sc->chan_dmat = NULL; 5777 } 5778 hdac_mem_free(sc); 5779 snd_mtxfree(sc->lock); 5780 free(sc, M_DEVBUF); 5781} 5782 5783/* This function surely going to make its way into upper level someday. */ 5784static void 5785hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5786{ 5787 const char *res = NULL; 5788 int i = 0, j, k, len, inv; 5789 5790 if (on != NULL) 5791 *on = 0; 5792 if (off != NULL) 5793 *off = 0; 5794 if (sc == NULL) 5795 return; 5796 if (resource_string_value(device_get_name(sc->dev), 5797 device_get_unit(sc->dev), "config", &res) != 0) 5798 return; 5799 if (!(res != NULL && strlen(res) > 0)) 5800 return; 5801 HDA_BOOTVERBOSE( 5802 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5803 ); 5804 for (;;) { 5805 while (res[i] != '\0' && 5806 (res[i] == ',' || isspace(res[i]) != 0)) 5807 i++; 5808 if (res[i] == '\0') { 5809 HDA_BOOTVERBOSE( 5810 printf("\n"); 5811 ); 5812 return; 5813 } 5814 j = i; 5815 while (res[j] != '\0' && 5816 !(res[j] == ',' || isspace(res[j]) != 0)) 5817 j++; 5818 len = j - i; 5819 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5820 inv = 2; 5821 else 5822 inv = 0; 5823 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5824 if (strncmp(res + i + inv, 5825 hdac_quirks_tab[k].key, len - inv) != 0) 5826 continue; 5827 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5828 break; 5829 HDA_BOOTVERBOSE( 5830 printf(" %s%s", (inv != 0) ? "no" : "", 5831 hdac_quirks_tab[k].key); 5832 ); 5833 if (inv == 0 && on != NULL) 5834 *on |= hdac_quirks_tab[k].value; 5835 else if (inv != 0 && off != NULL) 5836 *off |= hdac_quirks_tab[k].value; 5837 break; 5838 } 5839 i = j; 5840 } 5841} 5842 5843#ifdef SND_DYNSYSCTL 5844static int 5845sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5846{ 5847 struct hdac_softc *sc; 5848 struct hdac_devinfo *devinfo; 5849 device_t dev; 5850 uint32_t ctl; 5851 int err, val; 5852 5853 dev = oidp->oid_arg1; 5854 devinfo = pcm_getdevinfo(dev); 5855 if (devinfo == NULL || devinfo->codec == NULL || 5856 devinfo->codec->sc == NULL) 5857 return (EINVAL); 5858 sc = devinfo->codec->sc; 5859 hdac_lock(sc); 5860 val = sc->polling; 5861 hdac_unlock(sc); 5862 err = sysctl_handle_int(oidp, &val, 0, req); 5863 5864 if (err != 0 || req->newptr == NULL) 5865 return (err); 5866 if (val < 0 || val > 1) 5867 return (EINVAL); 5868 5869 hdac_lock(sc); 5870 if (val != sc->polling) { 5871 if (hda_chan_active(sc) != 0) 5872 err = EBUSY; 5873 else if (val == 0) { 5874 callout_stop(&sc->poll_hdac); 5875 hdac_unlock(sc); 5876 callout_drain(&sc->poll_hdac); 5877 hdac_lock(sc); 5878 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5879 sc->rirb_size / 2); 5880 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5881 ctl |= HDAC_RIRBCTL_RINTCTL; 5882 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5883 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5884 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5885 sc->polling = 0; 5886 DELAY(1000); 5887 } else { 5888 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5889 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5890 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5891 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5892 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5893 hdac_unlock(sc); 5894 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5895 hdac_lock(sc); 5896 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5897 sc); 5898 sc->polling = 1; 5899 DELAY(1000); 5900 } 5901 } 5902 hdac_unlock(sc); 5903 5904 return (err); 5905} 5906 5907static int 5908sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5909{ 5910 struct hdac_softc *sc; 5911 struct hdac_devinfo *devinfo; 5912 device_t dev; 5913 int err, val; 5914 5915 dev = oidp->oid_arg1; 5916 devinfo = pcm_getdevinfo(dev); 5917 if (devinfo == NULL || devinfo->codec == NULL || 5918 devinfo->codec->sc == NULL) 5919 return (EINVAL); 5920 sc = devinfo->codec->sc; 5921 hdac_lock(sc); 5922 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5923 hdac_unlock(sc); 5924 err = sysctl_handle_int(oidp, &val, 0, req); 5925 5926 if (err != 0 || req->newptr == NULL) 5927 return (err); 5928 5929 if (val < 1) 5930 val = 1; 5931 if (val > 5000) 5932 val = 5000; 5933 val = ((uint64_t)val * hz) / 1000; 5934 if (val < 1) 5935 val = 1; 5936 if (val > (hz * 5)) 5937 val = hz * 5; 5938 5939 hdac_lock(sc); 5940 sc->poll_ival = val; 5941 hdac_unlock(sc); 5942 5943 return (err); 5944} 5945 5946#ifdef SND_DEBUG 5947static int 5948sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 5949{ 5950 struct hdac_softc *sc; 5951 struct hdac_devinfo *devinfo; 5952 struct hdac_widget *w; 5953 device_t dev; 5954 uint32_t res, pincap, timeout; 5955 int i, err, val; 5956 nid_t cad; 5957 5958 dev = oidp->oid_arg1; 5959 devinfo = pcm_getdevinfo(dev); 5960 if (devinfo == NULL || devinfo->codec == NULL || 5961 devinfo->codec->sc == NULL) 5962 return (EINVAL); 5963 val = 0; 5964 err = sysctl_handle_int(oidp, &val, 0, req); 5965 if (err != 0 || req->newptr == NULL || val == 0) 5966 return (err); 5967 sc = devinfo->codec->sc; 5968 cad = devinfo->codec->cad; 5969 hdac_lock(sc); 5970 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 5971 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5972 w = hdac_widget_get(devinfo, i); 5973 if (w == NULL || w->type != 5974 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5975 continue; 5976 pincap = w->wclass.pin.cap; 5977 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 5978 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 5979 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 5980 timeout = 10000; 5981 hdac_command(sc, 5982 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 5983 do { 5984 res = hdac_command(sc, 5985 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 5986 if (res != 0x7fffffff) 5987 break; 5988 DELAY(10); 5989 } while (--timeout != 0); 5990 } else { 5991 timeout = -1; 5992 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 5993 w->nid), cad); 5994 } 5995 device_printf(dev, 5996 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 5997 w->nid, timeout, res, 5998 (w->enable == 0) ? "DISABLED" : "ENABLED"); 5999 } 6000 device_printf(dev, 6001 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 6002 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 6003 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 6004 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 6005 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 6006 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 6007 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 6008 device_printf(dev, " GPI:"); 6009 res = hdac_command(sc, 6010 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 6011 printf(" data=0x%08x", res); 6012 res = hdac_command(sc, 6013 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 6014 cad); 6015 printf(" wake=0x%08x", res); 6016 res = hdac_command(sc, 6017 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6018 cad); 6019 printf(" unsol=0x%08x", res); 6020 res = hdac_command(sc, 6021 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 6022 printf(" sticky=0x%08x\n", res); 6023 } 6024 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 6025 device_printf(dev, " GPO:"); 6026 res = hdac_command(sc, 6027 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 6028 printf(" data=0x%08x\n", res); 6029 } 6030 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 6031 device_printf(dev, "GPI0:"); 6032 res = hdac_command(sc, 6033 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 6034 printf(" data=0x%08x", res); 6035 res = hdac_command(sc, 6036 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 6037 printf(" enable=0x%08x", res); 6038 res = hdac_command(sc, 6039 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 6040 printf(" direction=0x%08x\n", res); 6041 res = hdac_command(sc, 6042 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 6043 device_printf(dev, " wake=0x%08x", res); 6044 res = hdac_command(sc, 6045 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 6046 cad); 6047 printf(" unsol=0x%08x", res); 6048 res = hdac_command(sc, 6049 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 6050 printf(" sticky=0x%08x\n", res); 6051 } 6052 hdac_unlock(sc); 6053 return (0); 6054} 6055#endif 6056#endif 6057 6058static void 6059hdac_attach2(void *arg) 6060{ 6061 struct hdac_softc *sc; 6062 struct hdac_widget *w; 6063 struct hdac_audio_ctl *ctl; 6064 uint32_t quirks_on, quirks_off; 6065 int pcnt, rcnt, codec_index; 6066 int i; 6067 char status[SND_STATUSLEN]; 6068 device_t *devlist = NULL; 6069 int devcount; 6070 struct hdac_devinfo *devinfo = NULL; 6071 6072 sc = (struct hdac_softc *)arg; 6073 6074 hdac_config_fetch(sc, &quirks_on, &quirks_off); 6075 6076 HDA_BOOTVERBOSE( 6077 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6078 quirks_on, quirks_off); 6079 ); 6080 6081 if (resource_int_value(device_get_name(sc->dev), 6082 device_get_unit(sc->dev), "codec_index", &codec_index) != 0) { 6083 switch (sc->pci_subvendor) { 6084 case GB_G33S2H_SUBVENDOR: 6085 codec_index = 2; 6086 break; 6087 default: 6088 codec_index = 0; 6089 break; 6090 } 6091 } 6092 6093 hdac_lock(sc); 6094 6095 /* Remove ourselves from the config hooks */ 6096 if (sc->intrhook.ich_func != NULL) { 6097 config_intrhook_disestablish(&sc->intrhook); 6098 sc->intrhook.ich_func = NULL; 6099 } 6100 6101 /* Start the corb and rirb engines */ 6102 HDA_BOOTVERBOSE( 6103 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6104 ); 6105 hdac_corb_start(sc); 6106 HDA_BOOTVERBOSE( 6107 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6108 ); 6109 hdac_rirb_start(sc); 6110 6111 HDA_BOOTVERBOSE( 6112 device_printf(sc->dev, 6113 "HDA_DEBUG: Enabling controller interrupt...\n"); 6114 ); 6115 if (sc->polling == 0) 6116 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6117 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6118 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6119 HDAC_GCTL_UNSOL); 6120 6121 DELAY(1000); 6122 6123 HDA_BOOTVERBOSE( 6124 device_printf(sc->dev, 6125 "HDA_DEBUG: Scanning HDA codecs [start index=%d] ...\n", 6126 codec_index); 6127 ); 6128 hdac_scan_codecs(sc, codec_index); 6129 6130 device_get_children(sc->dev, &devlist, &devcount); 6131 for (i = 0; devlist != NULL && i < devcount; i++) { 6132 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6133 if (devinfo != NULL && devinfo->node_type == 6134 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6135 break; 6136 } else 6137 devinfo = NULL; 6138 } 6139 if (devlist != NULL) 6140 free(devlist, M_TEMP); 6141 6142 if (devinfo == NULL) { 6143 hdac_unlock(sc); 6144 device_printf(sc->dev, "Audio Function Group not found!\n"); 6145 hdac_release_resources(sc); 6146 return; 6147 } 6148 6149 HDA_BOOTVERBOSE( 6150 device_printf(sc->dev, 6151 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6152 devinfo->nid, devinfo->codec->cad); 6153 ); 6154 hdac_audio_parse(devinfo); 6155 HDA_BOOTVERBOSE( 6156 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6157 ); 6158 hdac_audio_ctl_parse(devinfo); 6159 HDA_BOOTVERBOSE( 6160 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6161 ); 6162 hdac_vendor_patch_parse(devinfo); 6163 if (quirks_on != 0) 6164 devinfo->function.audio.quirks |= quirks_on; 6165 if (quirks_off != 0) 6166 devinfo->function.audio.quirks &= ~quirks_off; 6167 6168 /* XXX Disable all DIGITAL path. */ 6169 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6170 w = hdac_widget_get(devinfo, i); 6171 if (w == NULL) 6172 continue; 6173 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6174 w->enable = 0; 6175 continue; 6176 } 6177 /* XXX Disable useless pin ? */ 6178 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6179 (w->wclass.pin.config & 6180 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6181 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6182 w->enable = 0; 6183 } 6184 i = 0; 6185 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6186 if (ctl->widget == NULL) 6187 continue; 6188 if (ctl->ossmask & SOUND_MASK_DISABLE) 6189 ctl->enable = 0; 6190 w = ctl->widget; 6191 if (w->enable == 0 || 6192 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6193 ctl->enable = 0; 6194 w = ctl->childwidget; 6195 if (w == NULL) 6196 continue; 6197 if (w->enable == 0 || 6198 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6199 ctl->enable = 0; 6200 } 6201 6202 HDA_BOOTVERBOSE( 6203 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6204 ); 6205 hdac_audio_build_tree(devinfo); 6206 6207 i = 0; 6208 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6209 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6210 ctl->ossmask = 0; 6211 } 6212 HDA_BOOTVERBOSE( 6213 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6214 ); 6215 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6216 HDA_BOOTVERBOSE( 6217 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6218 ); 6219 hdac_audio_ctl_commit(devinfo); 6220 6221 HDA_BOOTVERBOSE( 6222 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6223 ); 6224 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6225 HDA_BOOTVERBOSE( 6226 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6227 ); 6228 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6229 6230 hdac_unlock(sc); 6231 HDA_BOOTVERBOSE( 6232 device_printf(sc->dev, 6233 "HDA_DEBUG: OSS mixer initialization...\n"); 6234 ); 6235 6236 /* 6237 * There is no point of return after this. If the driver failed, 6238 * so be it. Let the detach procedure do all the cleanup. 6239 */ 6240 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6241 device_printf(sc->dev, "Can't register mixer\n"); 6242 6243 if (pcnt > 0) 6244 pcnt = 1; 6245 if (rcnt > 0) 6246 rcnt = 1; 6247 6248 HDA_BOOTVERBOSE( 6249 device_printf(sc->dev, 6250 "HDA_DEBUG: Registering PCM channels...\n"); 6251 ); 6252 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6253 device_printf(sc->dev, "Can't register PCM\n"); 6254 6255 sc->registered++; 6256 6257 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6258 hdac_dma_alloc(sc, &sc->pos_dma, 6259 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6260 HDA_BOOTVERBOSE( 6261 device_printf(sc->dev, 6262 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6263 ); 6264 } 6265 6266 for (i = 0; i < pcnt; i++) 6267 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6268 for (i = 0; i < rcnt; i++) 6269 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6270 6271#ifdef SND_DYNSYSCTL 6272 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6273 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6274 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6275 sysctl_hdac_polling, "I", "Enable polling mode"); 6276 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6277 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6278 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6279 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6280 "Controller/Jack Sense polling interval (1-1000 ms)"); 6281#ifdef SND_DEBUG 6282 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6283 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6284 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6285 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6286#endif 6287#endif 6288 6289 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6290 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6291 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6292 pcm_setstatus(sc->dev, status); 6293 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6294 HDA_BOOTVERBOSE( 6295 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6296 hdac_codec_id(devinfo)); 6297 ); 6298 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6299 HDA_DRV_TEST_REV); 6300 6301 HDA_BOOTVERBOSE( 6302 if (devinfo->function.audio.quirks != 0) { 6303 device_printf(sc->dev, "\n"); 6304 device_printf(sc->dev, "HDA config/quirks:"); 6305 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6306 if ((devinfo->function.audio.quirks & 6307 hdac_quirks_tab[i].value) == 6308 hdac_quirks_tab[i].value) 6309 printf(" %s", hdac_quirks_tab[i].key); 6310 } 6311 printf("\n"); 6312 } 6313 device_printf(sc->dev, "\n"); 6314 device_printf(sc->dev, "+-------------------+\n"); 6315 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6316 device_printf(sc->dev, "+-------------------+\n"); 6317 hdac_dump_nodes(devinfo); 6318 device_printf(sc->dev, "\n"); 6319 device_printf(sc->dev, "+------------------------+\n"); 6320 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6321 device_printf(sc->dev, "+------------------------+\n"); 6322 device_printf(sc->dev, "\n"); 6323 i = 0; 6324 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6325 device_printf(sc->dev, "%3d: nid=%d", i, 6326 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6327 if (ctl->childwidget != NULL) 6328 printf(" cnid=%d", ctl->childwidget->nid); 6329 printf(" dir=0x%x index=%d " 6330 "ossmask=0x%08x ossdev=%d%s\n", 6331 ctl->dir, ctl->index, 6332 ctl->ossmask, ctl->ossdev, 6333 (ctl->enable == 0) ? " [DISABLED]" : ""); 6334 } 6335 device_printf(sc->dev, "\n"); 6336 device_printf(sc->dev, "+-----------------------------------+\n"); 6337 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6338 device_printf(sc->dev, "+-----------------------------------+\n"); 6339 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6340 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6341 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6342 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6343 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6344 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6345 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6346 hdac_dump_ctls(devinfo, NULL, 0); 6347 hdac_dump_dac(devinfo); 6348 hdac_dump_adc(devinfo); 6349 device_printf(sc->dev, "\n"); 6350 device_printf(sc->dev, "+--------------------------------------+\n"); 6351 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6352 device_printf(sc->dev, "+--------------------------------------+\n"); 6353 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6354 ); 6355 6356 if (sc->polling != 0) { 6357 hdac_lock(sc); 6358 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6359 hdac_unlock(sc); 6360 } 6361} 6362 6363/**************************************************************************** 6364 * int hdac_detach(device_t) 6365 * 6366 * Detach and free up resources utilized by the hdac device. 6367 ****************************************************************************/ 6368static int 6369hdac_detach(device_t dev) 6370{ 6371 struct hdac_softc *sc = NULL; 6372 struct hdac_devinfo *devinfo = NULL; 6373 int err; 6374 6375 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6376 if (devinfo != NULL && devinfo->codec != NULL) 6377 sc = devinfo->codec->sc; 6378 if (sc == NULL) 6379 return (0); 6380 6381 if (sc->registered > 0) { 6382 err = pcm_unregister(dev); 6383 if (err != 0) 6384 return (err); 6385 } 6386 6387 hdac_release_resources(sc); 6388 6389 return (0); 6390} 6391 6392static device_method_t hdac_methods[] = { 6393 /* device interface */ 6394 DEVMETHOD(device_probe, hdac_probe), 6395 DEVMETHOD(device_attach, hdac_attach), 6396 DEVMETHOD(device_detach, hdac_detach), 6397 { 0, 0 } 6398}; 6399 6400static driver_t hdac_driver = { 6401 "pcm", 6402 hdac_methods, 6403 PCM_SOFTC_SIZE, 6404}; 6405 6406DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6407MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6408MODULE_VERSION(snd_hda, 1); 6409