hdac.c revision 171141
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sys/ctype.h> 75#include <sys/taskqueue.h> 76 77#include <dev/sound/pci/hda/hdac_private.h> 78#include <dev/sound/pci/hda/hdac_reg.h> 79#include <dev/sound/pci/hda/hda_reg.h> 80#include <dev/sound/pci/hda/hdac.h> 81 82#include "mixer_if.h" 83 84#define HDA_DRV_TEST_REV "20070702_0046" 85#define HDA_WIDGET_PARSER_REV 1 86 87SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 171141 2007-07-01 17:31:20Z ariff $"); 88 89#define HDA_BOOTVERBOSE(stmt) do { \ 90 if (bootverbose != 0 || snd_verbose > 3) { \ 91 stmt \ 92 } \ 93} while(0) 94 95#if 1 96#undef HDAC_INTR_EXTRA 97#define HDAC_INTR_EXTRA 1 98#endif 99 100#define hdac_lock(sc) snd_mtxlock((sc)->lock) 101#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 102#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 103#define hdac_lockowned(sc) mtx_owned((sc)->lock) 104 105#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 106#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 107 (fl) == 0xffffffff || \ 108 (((fl) & 0xffff0000) == 0xffff0000 && \ 109 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 110 (((fl) & 0x0000ffff) == 0x0000ffff && \ 111 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 112#define HDA_MATCH_ALL 0xffffffff 113#define HDAC_INVALID 0xffffffff 114 115/* Default controller / jack sense poll: 250ms */ 116#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 117 118/* 119 * Make room for possible 4096 playback/record channels, in 100 years to come. 120 */ 121#define HDAC_TRIGGER_NONE 0x00000000 122#define HDAC_TRIGGER_PLAY 0x00000fff 123#define HDAC_TRIGGER_REC 0x00fff000 124#define HDAC_TRIGGER_UNSOL 0x80000000 125 126#define HDA_MODEL_CONSTRUCT(vendor, model) \ 127 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 128 129/* Controller models */ 130 131/* Intel */ 132#define INTEL_VENDORID 0x8086 133#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 134#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 135#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 136#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 137#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 138 139/* Nvidia */ 140#define NVIDIA_VENDORID 0x10de 141#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 142#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 143#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 144#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 145#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 146#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 147#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 148 149/* ATI */ 150#define ATI_VENDORID 0x1002 151#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 152#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 153#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 154 155/* VIA */ 156#define VIA_VENDORID 0x1106 157#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 158#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 159 160/* SiS */ 161#define SIS_VENDORID 0x1039 162#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 163#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 164 165/* OEM/subvendors */ 166 167/* Intel */ 168#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 169 170/* HP/Compaq */ 171#define HP_VENDORID 0x103c 172#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 173#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 174#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 175#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 176#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 177#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 178#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 179#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 180/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 181#define HP_NX6325_SUBVENDORX 0x103c30b0 182 183/* Dell */ 184#define DELL_VENDORID 0x1028 185#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 186#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 187#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 188#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 189#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 190 191/* Clevo */ 192#define CLEVO_VENDORID 0x1558 193#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 194#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 195 196/* Acer */ 197#define ACER_VENDORID 0x1025 198#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 199#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 200#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 201 202/* Asus */ 203#define ASUS_VENDORID 0x1043 204#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 205#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 206#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 207#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 208#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 209#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 210#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 211#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 212#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 213#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 214#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 215#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 216#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 217#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 218#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 219 220/* IBM / Lenovo */ 221#define IBM_VENDORID 0x1014 222#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 223#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 224 225/* Lenovo */ 226#define LENOVO_VENDORID 0x17aa 227#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 228#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 229 230/* Samsung */ 231#define SAMSUNG_VENDORID 0x144d 232#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 233#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 234 235/* Medion ? */ 236#define MEDION_VENDORID 0x161f 237#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 238#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 239 240/* 241 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 242 * instead of their own, which is beyond my comprehension 243 * (see HDA_CODEC_STAC9221 below). 244 */ 245#define APPLE_INTEL_MAC 0x76808384 246 247/* LG Electronics */ 248#define LG_VENDORID 0x1854 249#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 250#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 251 252/* Fujitsu Siemens */ 253#define FS_VENDORID 0x1734 254#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 255#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 256 257/* Toshiba */ 258#define TOSHIBA_VENDORID 0x1179 259#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 260#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 261 262/* Micro-Star International (MSI) */ 263#define MSI_VENDORID 0x1462 264#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 265#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 266 267/* Uniwill ? */ 268#define UNIWILL_VENDORID 0x1584 269#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 270#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 271 272 273/* Misc constants.. */ 274#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 275#define HDA_AMP_MUTE_NONE (0) 276#define HDA_AMP_MUTE_LEFT (1 << 0) 277#define HDA_AMP_MUTE_RIGHT (1 << 1) 278#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 279 280#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 281#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 282 283#define HDA_DAC_PATH (1 << 0) 284#define HDA_ADC_PATH (1 << 1) 285#define HDA_ADC_RECSEL (1 << 2) 286 287#define HDA_DAC_LOCKED (1 << 3) 288#define HDA_ADC_LOCKED (1 << 4) 289 290#define HDA_CTL_OUT (1 << 0) 291#define HDA_CTL_IN (1 << 1) 292#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 293 294#define HDA_GPIO_MAX 8 295/* 0 - 7 = GPIO , 8 = Flush */ 296#define HDA_QUIRK_GPIO0 (1 << 0) 297#define HDA_QUIRK_GPIO1 (1 << 1) 298#define HDA_QUIRK_GPIO2 (1 << 2) 299#define HDA_QUIRK_GPIO3 (1 << 3) 300#define HDA_QUIRK_GPIO4 (1 << 4) 301#define HDA_QUIRK_GPIO5 (1 << 5) 302#define HDA_QUIRK_GPIO6 (1 << 6) 303#define HDA_QUIRK_GPIO7 (1 << 7) 304#define HDA_QUIRK_GPIOFLUSH (1 << 8) 305 306/* 9 - 25 = anything else */ 307#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 308#define HDA_QUIRK_FIXEDRATE (1 << 10) 309#define HDA_QUIRK_FORCESTEREO (1 << 11) 310#define HDA_QUIRK_EAPDINV (1 << 12) 311#define HDA_QUIRK_DMAPOS (1 << 13) 312 313/* 26 - 31 = vrefs */ 314#define HDA_QUIRK_IVREF50 (1 << 26) 315#define HDA_QUIRK_IVREF80 (1 << 27) 316#define HDA_QUIRK_IVREF100 (1 << 28) 317#define HDA_QUIRK_OVREF50 (1 << 29) 318#define HDA_QUIRK_OVREF80 (1 << 30) 319#define HDA_QUIRK_OVREF100 (1 << 31) 320 321#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 322 HDA_QUIRK_IVREF100) 323#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 324 HDA_QUIRK_OVREF100) 325#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 326 327#define SOUND_MASK_SKIP (1 << 30) 328#define SOUND_MASK_DISABLE (1 << 31) 329 330#if __FreeBSD_version < 600000 331#define taskqueue_drain(...) 332#endif 333 334static const struct { 335 char *key; 336 uint32_t value; 337} hdac_quirks_tab[] = { 338 { "gpio0", HDA_QUIRK_GPIO0 }, 339 { "gpio1", HDA_QUIRK_GPIO1 }, 340 { "gpio2", HDA_QUIRK_GPIO2 }, 341 { "gpio3", HDA_QUIRK_GPIO3 }, 342 { "gpio4", HDA_QUIRK_GPIO4 }, 343 { "gpio5", HDA_QUIRK_GPIO5 }, 344 { "gpio6", HDA_QUIRK_GPIO6 }, 345 { "gpio7", HDA_QUIRK_GPIO7 }, 346 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 347 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 348 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 349 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 350 { "eapdinv", HDA_QUIRK_EAPDINV }, 351 { "dmapos", HDA_QUIRK_DMAPOS }, 352 { "ivref50", HDA_QUIRK_IVREF50 }, 353 { "ivref80", HDA_QUIRK_IVREF80 }, 354 { "ivref100", HDA_QUIRK_IVREF100 }, 355 { "ovref50", HDA_QUIRK_OVREF50 }, 356 { "ovref80", HDA_QUIRK_OVREF80 }, 357 { "ovref100", HDA_QUIRK_OVREF100 }, 358 { "ivref", HDA_QUIRK_IVREF }, 359 { "ovref", HDA_QUIRK_OVREF }, 360 { "vref", HDA_QUIRK_VREF }, 361}; 362#define HDAC_QUIRKS_TAB_LEN \ 363 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 364 365#define HDA_BDL_MIN 2 366#define HDA_BDL_MAX 256 367#define HDA_BDL_DEFAULT HDA_BDL_MIN 368 369#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 370#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 371 372#define HDA_BUFSZ_MIN 4096 373#define HDA_BUFSZ_MAX 65536 374#define HDA_BUFSZ_DEFAULT 16384 375 376#define HDA_PARSE_MAXDEPTH 10 377 378#define HDAC_UNSOLTAG_EVENT_HP 0x00 379#define HDAC_UNSOLTAG_EVENT_TEST 0x01 380 381MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 382 383enum { 384 HDA_PARSE_MIXER, 385 HDA_PARSE_DIRECT 386}; 387 388/* Default */ 389static uint32_t hdac_fmt[] = { 390 AFMT_STEREO | AFMT_S16_LE, 391 0 392}; 393 394static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 395 396static const struct { 397 uint32_t model; 398 char *desc; 399} hdac_devices[] = { 400 { HDA_INTEL_82801F, "Intel 82801F" }, 401 { HDA_INTEL_82801G, "Intel 82801G" }, 402 { HDA_INTEL_82801H, "Intel 82801H" }, 403 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 404 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 405 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 406 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 407 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 408 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 409 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 410 { HDA_ATI_SB450, "ATI SB450" }, 411 { HDA_ATI_SB600, "ATI SB600" }, 412 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 413 { HDA_SIS_966, "SiS 966" }, 414 /* Unknown */ 415 { HDA_INTEL_ALL, "Intel (Unknown)" }, 416 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 417 { HDA_ATI_ALL, "ATI (Unknown)" }, 418 { HDA_VIA_ALL, "VIA (Unknown)" }, 419 { HDA_SIS_ALL, "SiS (Unknown)" }, 420}; 421#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 422 423static const struct { 424 uint16_t vendor; 425 uint8_t reg; 426 uint8_t mask; 427 uint8_t enable; 428} hdac_pcie_snoop[] = { 429 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 430 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 431 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 432}; 433#define HDAC_PCIESNOOP_LEN \ 434 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 435 436static const struct { 437 uint32_t rate; 438 int valid; 439 uint16_t base; 440 uint16_t mul; 441 uint16_t div; 442} hda_rate_tab[] = { 443 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 444 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 445 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 446 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 447 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 448 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 449 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 450 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 451 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 452 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 453 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 454 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 455 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 456 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 457 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 458 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 459 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 460 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 461 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 462 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 463 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 464 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 465 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 466 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 467 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 468 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 469 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 470 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 471 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 472 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 473 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 474 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 475 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 476 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 477 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 478}; 479#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 480 481/* All codecs you can eat... */ 482#define HDA_CODEC_CONSTRUCT(vendor, id) \ 483 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 484 485/* Realtek */ 486#define REALTEK_VENDORID 0x10ec 487#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 488#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 489#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 490#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 491#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 492#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 493#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 494#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 495#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 496#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 497#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 498 499/* Analog Devices */ 500#define ANALOGDEVICES_VENDORID 0x11d4 501#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 502#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 503#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 504#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 505#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 506#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 507 508/* CMedia */ 509#define CMEDIA_VENDORID 0x434d 510#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 511#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 512 513/* Sigmatel */ 514#define SIGMATEL_VENDORID 0x8384 515#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 516#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 517#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 518#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 519#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 520#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 521#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 522 523/* 524 * Conexant 525 * 526 * Ok, the truth is, I don't have any idea at all whether 527 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 528 * place that tell me it is "Venice" is from its Windows driver INF. 529 * 530 * Venice - CX????? 531 * Waikiki - CX20551-22 532 */ 533#define CONEXANT_VENDORID 0x14f1 534#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 535#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 536#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 537 538/* VIA */ 539#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 540#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 541#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 542#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 543#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 544#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 545#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 546#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 547#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 548#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 549#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 550#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 551#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 552 553 554/* Codecs */ 555static const struct { 556 uint32_t id; 557 char *name; 558} hdac_codecs[] = { 559 { HDA_CODEC_ALC260, "Realtek ALC260" }, 560 { HDA_CODEC_ALC262, "Realtek ALC262" }, 561 { HDA_CODEC_ALC660, "Realtek ALC660" }, 562 { HDA_CODEC_ALC861, "Realtek ALC861" }, 563 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 564 { HDA_CODEC_ALC880, "Realtek ALC880" }, 565 { HDA_CODEC_ALC882, "Realtek ALC882" }, 566 { HDA_CODEC_ALC883, "Realtek ALC883" }, 567 { HDA_CODEC_ALC885, "Realtek ALC885" }, 568 { HDA_CODEC_ALC888, "Realtek ALC888" }, 569 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 570 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 571 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 572 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 573 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 574 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 575 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 576 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 577 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 578 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 579 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 580 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 581 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 582 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 583 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 584 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 585 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 586 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 587 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 588 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 589 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 590 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 591 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 592 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 593 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 594 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 595 /* Unknown codec */ 596 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 597 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 598 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 599 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 600 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 601 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 602}; 603#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 604 605enum { 606 HDAC_HP_SWITCH_CTL, 607 HDAC_HP_SWITCH_CTRL, 608 HDAC_HP_SWITCH_DEBUG 609}; 610 611static const struct { 612 uint32_t model; 613 uint32_t id; 614 int type; 615 int inverted; 616 int polling; 617 int execsense; 618 nid_t hpnid; 619 nid_t spkrnid[8]; 620 nid_t eapdnid; 621} hdac_hp_switch[] = { 622 /* Specific OEM models */ 623 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 624 0, 0, -1, 17, { 16, -1 }, 16 }, 625 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 626 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 627 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 628 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/ 629 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 630 0, 0, -1, 6, { 5, -1 }, 5 }, 631 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 632 0, 0, -1, 6, { 5, -1 }, 5 }, 633 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 634 0, 0, -1, 6, { 5, -1 }, 5 }, 635 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 636 0, 0, -1, 6, { 5, -1 }, -1 }, 637 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 638 0, 0, -1, 13, { 14, -1 }, -1 }, 639 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 640 0, 0, -1, 13, { 14, -1 }, -1 }, 641 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 642 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 643 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 644 0, 0, -1, 10, { 13, -1 }, -1 }, 645 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 646 1, 0, -1, 26, { 27, -1 }, -1 }, 647 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 648 0, 0, -1, 27, { 20, -1 }, -1 }, 649 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 650 0, 0, -1, 20, { 21, -1 }, -1 }, 651 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 652 0, 0, -1, 20, { 21, -1 }, -1 }, 653 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 654 0, 0, -1, 20, { 21, -1 }, -1 }, 655 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 656 0, 0, -1, 20, { 27, -1 }, -1 }, 657 /* 658 * All models that at least come from the same vendor with 659 * simmilar codec. 660 */ 661 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 662 0, 0, -1, 17, { 16, -1 }, 16 }, 663 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 664 0, 0, -1, 6, { 5, -1 }, 5 }, 665 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 666 0, 0, -1, 6, { 5, -1 }, -1 }, 667 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 668 0, 0, -1, 13, { 14, -1 }, -1 }, 669 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 670 1, 0, -1, 26, { 27, -1 }, -1 }, 671#if 0 672 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 673 0, 0, -1, 20, { 21, -1 }, -1 }, 674#endif 675}; 676#define HDAC_HP_SWITCH_LEN \ 677 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 678 679static const struct { 680 uint32_t model; 681 uint32_t id; 682 nid_t eapdnid; 683 int hp_switch; 684} hdac_eapd_switch[] = { 685 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 686 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 687 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 688}; 689#define HDAC_EAPD_SWITCH_LEN \ 690 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 691 692/**************************************************************************** 693 * Function prototypes 694 ****************************************************************************/ 695static void hdac_intr_handler(void *); 696static int hdac_reset(struct hdac_softc *); 697static int hdac_get_capabilities(struct hdac_softc *); 698static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 699static int hdac_dma_alloc(struct hdac_softc *, 700 struct hdac_dma *, bus_size_t); 701static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 702static int hdac_mem_alloc(struct hdac_softc *); 703static void hdac_mem_free(struct hdac_softc *); 704static int hdac_irq_alloc(struct hdac_softc *); 705static void hdac_irq_free(struct hdac_softc *); 706static void hdac_corb_init(struct hdac_softc *); 707static void hdac_rirb_init(struct hdac_softc *); 708static void hdac_corb_start(struct hdac_softc *); 709static void hdac_rirb_start(struct hdac_softc *); 710static void hdac_scan_codecs(struct hdac_softc *); 711static int hdac_probe_codec(struct hdac_codec *); 712static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 713static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 714 715static void hdac_attach2(void *); 716 717static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 718 uint32_t, int); 719static void hdac_command_send_internal(struct hdac_softc *, 720 struct hdac_command_list *, int); 721 722static int hdac_probe(device_t); 723static int hdac_attach(device_t); 724static int hdac_detach(device_t); 725static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 726static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 727 uint32_t, int, int); 728static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 729 nid_t, int, int); 730static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 731 nid_t, nid_t, int, int, int, int, int, int); 732static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 733static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 734 735static int hdac_rirb_flush(struct hdac_softc *sc); 736static int hdac_unsolq_flush(struct hdac_softc *sc); 737 738#define hdac_command(a1, a2, a3) \ 739 hdac_command_sendone_internal(a1, a2, a3) 740 741#define hdac_codec_id(d) \ 742 ((uint32_t)((d == NULL) ? 0x00000000 : \ 743 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 744 ((uint32_t)(d)->device_id & 0x0000ffff)))) 745 746static char * 747hdac_codec_name(struct hdac_devinfo *devinfo) 748{ 749 uint32_t id; 750 int i; 751 752 id = hdac_codec_id(devinfo); 753 754 for (i = 0; i < HDAC_CODECS_LEN; i++) { 755 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 756 return (hdac_codecs[i].name); 757 } 758 759 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 760} 761 762static char * 763hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 764{ 765 static char *ossname[] = SOUND_DEVICE_NAMES; 766 static char *unknown = "???"; 767 int i; 768 769 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 770 if (devmask & (1 << i)) 771 return (ossname[i]); 772 } 773 return (unknown); 774} 775 776static void 777hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 778{ 779 static char *ossname[] = SOUND_DEVICE_NAMES; 780 int i, first = 1; 781 782 bzero(buf, len); 783 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 784 if (mask & (1 << i)) { 785 if (first == 0) 786 strlcat(buf, ", ", len); 787 strlcat(buf, ossname[i], len); 788 first = 0; 789 } 790 } 791} 792 793static struct hdac_audio_ctl * 794hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 795{ 796 if (devinfo == NULL || 797 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 798 index == NULL || devinfo->function.audio.ctl == NULL || 799 devinfo->function.audio.ctlcnt < 1 || 800 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 801 return (NULL); 802 return (&devinfo->function.audio.ctl[(*index)++]); 803} 804 805static struct hdac_audio_ctl * 806hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 807 int index, int cnt) 808{ 809 struct hdac_audio_ctl *ctl, *retctl = NULL; 810 int i, at, atindex, found = 0; 811 812 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 813 return (NULL); 814 815 at = cnt; 816 if (at == 0) 817 at = 1; 818 else if (at < 0) 819 at = -1; 820 atindex = index; 821 if (atindex < 0) 822 atindex = -1; 823 824 i = 0; 825 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 826 if (ctl->enable == 0 || ctl->widget == NULL) 827 continue; 828 if (!(ctl->widget->nid == nid && (atindex == -1 || 829 ctl->index == atindex))) 830 continue; 831 found++; 832 if (found == cnt) 833 return (ctl); 834 retctl = ctl; 835 } 836 837 return ((at == -1) ? retctl : NULL); 838} 839 840static void 841hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 842{ 843 struct hdac_softc *sc; 844 struct hdac_widget *w; 845 struct hdac_audio_ctl *ctl; 846 uint32_t val, id, res; 847 int i = 0, j, timeout, forcemute; 848 nid_t cad; 849 850 if (devinfo == NULL || devinfo->codec == NULL || 851 devinfo->codec->sc == NULL) 852 return; 853 854 sc = devinfo->codec->sc; 855 cad = devinfo->codec->cad; 856 id = hdac_codec_id(devinfo); 857 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 858 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 859 sc->pci_subvendor) && 860 hdac_hp_switch[i].id == id) 861 break; 862 } 863 864 if (i >= HDAC_HP_SWITCH_LEN) 865 return; 866 867 forcemute = 0; 868 if (hdac_hp_switch[i].eapdnid != -1) { 869 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 870 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 871 forcemute = (w->param.eapdbtl & 872 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 873 } 874 875 if (hdac_hp_switch[i].execsense != -1) 876 hdac_command(sc, 877 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 878 hdac_hp_switch[i].execsense), cad); 879 880 timeout = 10000; 881 do { 882 res = hdac_command(sc, 883 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), 884 cad); 885 if (hdac_hp_switch[i].execsense == -1 || res != 0x7fffffff) 886 break; 887 DELAY(10); 888 } while (--timeout != 0); 889 890 HDA_BOOTVERBOSE( 891 device_printf(sc->dev, 892 "HDA_DEBUG: Pin sense: nid=%d timeout=%d res=0x%08x\n", 893 hdac_hp_switch[i].hpnid, timeout, res); 894 ); 895 896 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 897 res ^= hdac_hp_switch[i].inverted; 898 899 switch (hdac_hp_switch[i].type) { 900 case HDAC_HP_SWITCH_CTL: 901 ctl = hdac_audio_ctl_amp_get(devinfo, 902 hdac_hp_switch[i].hpnid, 0, 1); 903 if (ctl != NULL) { 904 val = (res != 0 && forcemute == 0) ? 905 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 906 if (val != ctl->muted) { 907 ctl->muted = val; 908 hdac_audio_ctl_amp_set(ctl, 909 HDA_AMP_MUTE_DEFAULT, ctl->left, 910 ctl->right); 911 } 912 } 913 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 914 ctl = hdac_audio_ctl_amp_get(devinfo, 915 hdac_hp_switch[i].spkrnid[j], 0, 1); 916 if (ctl == NULL) 917 continue; 918 val = (res != 0 || forcemute == 1) ? 919 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 920 if (val == ctl->muted) 921 continue; 922 ctl->muted = val; 923 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 924 ctl->left, ctl->right); 925 } 926 break; 927 case HDAC_HP_SWITCH_CTRL: 928 if (res != 0) { 929 /* HP in */ 930 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 931 if (w != NULL && w->type == 932 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 933 if (forcemute == 0) 934 val = w->wclass.pin.ctrl | 935 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 936 else 937 val = w->wclass.pin.ctrl & 938 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 939 if (val != w->wclass.pin.ctrl) { 940 w->wclass.pin.ctrl = val; 941 hdac_command(sc, 942 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 943 w->nid, w->wclass.pin.ctrl), cad); 944 } 945 } 946 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 947 w = hdac_widget_get(devinfo, 948 hdac_hp_switch[i].spkrnid[j]); 949 if (w == NULL || w->type != 950 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 951 continue; 952 val = w->wclass.pin.ctrl & 953 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 954 if (val == w->wclass.pin.ctrl) 955 continue; 956 w->wclass.pin.ctrl = val; 957 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 958 cad, w->nid, w->wclass.pin.ctrl), cad); 959 } 960 } else { 961 /* HP out */ 962 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 963 if (w != NULL && w->type == 964 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 965 val = w->wclass.pin.ctrl & 966 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 967 if (val != w->wclass.pin.ctrl) { 968 w->wclass.pin.ctrl = val; 969 hdac_command(sc, 970 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 971 w->nid, w->wclass.pin.ctrl), cad); 972 } 973 } 974 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 975 w = hdac_widget_get(devinfo, 976 hdac_hp_switch[i].spkrnid[j]); 977 if (w == NULL || w->type != 978 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 979 continue; 980 if (forcemute == 0) 981 val = w->wclass.pin.ctrl | 982 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 983 else 984 val = w->wclass.pin.ctrl & 985 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 986 if (val == w->wclass.pin.ctrl) 987 continue; 988 w->wclass.pin.ctrl = val; 989 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 990 cad, w->nid, w->wclass.pin.ctrl), cad); 991 } 992 } 993 break; 994 case HDAC_HP_SWITCH_DEBUG: 995 if (hdac_hp_switch[i].execsense != -1) 996 hdac_command(sc, 997 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 998 hdac_hp_switch[i].execsense), cad); 999 res = hdac_command(sc, 1000 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 1001 device_printf(sc->dev, 1002 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1003 hdac_hp_switch[i].hpnid, res); 1004 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 1005 w = hdac_widget_get(devinfo, 1006 hdac_hp_switch[i].spkrnid[j]); 1007 if (w == NULL || w->type != 1008 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1009 continue; 1010 if (hdac_hp_switch[i].execsense != -1) 1011 hdac_command(sc, 1012 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 1013 hdac_hp_switch[i].execsense), cad); 1014 res = hdac_command(sc, 1015 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 1016 device_printf(sc->dev, 1017 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 1018 j + 1, w->nid, res); 1019 } 1020 break; 1021 default: 1022 break; 1023 } 1024} 1025 1026static void 1027hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1028{ 1029 struct hdac_softc *sc; 1030 struct hdac_devinfo *devinfo = NULL; 1031 device_t *devlist = NULL; 1032 int devcount, i; 1033 1034 if (codec == NULL || codec->sc == NULL) 1035 return; 1036 1037 sc = codec->sc; 1038 1039 HDA_BOOTVERBOSE( 1040 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1041 ); 1042 1043 device_get_children(sc->dev, &devlist, &devcount); 1044 for (i = 0; devlist != NULL && i < devcount; i++) { 1045 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1046 if (devinfo != NULL && devinfo->node_type == 1047 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1048 devinfo->codec != NULL && 1049 devinfo->codec->cad == codec->cad) { 1050 break; 1051 } else 1052 devinfo = NULL; 1053 } 1054 if (devlist != NULL) 1055 free(devlist, M_TEMP); 1056 1057 if (devinfo == NULL) 1058 return; 1059 1060 switch (tag) { 1061 case HDAC_UNSOLTAG_EVENT_HP: 1062 hdac_hp_switch_handler(devinfo); 1063 break; 1064 case HDAC_UNSOLTAG_EVENT_TEST: 1065 device_printf(sc->dev, "Unsol Test!\n"); 1066 break; 1067 default: 1068 break; 1069 } 1070} 1071 1072static int 1073hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1074{ 1075 /* XXX to be removed */ 1076#ifdef HDAC_INTR_EXTRA 1077 uint32_t res; 1078#endif 1079 1080 if (ch->blkcnt == 0) 1081 return (0); 1082 1083 /* XXX to be removed */ 1084#ifdef HDAC_INTR_EXTRA 1085 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1086#endif 1087 1088 /* XXX to be removed */ 1089#ifdef HDAC_INTR_EXTRA 1090 HDA_BOOTVERBOSE( 1091 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1092 device_printf(sc->dev, 1093 "PCMDIR_%s intr triggered beyond stream boundary:" 1094 "%08x\n", 1095 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1096 ); 1097#endif 1098 1099 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1100 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1101 1102 /* XXX to be removed */ 1103#ifdef HDAC_INTR_EXTRA 1104 if (res & HDAC_SDSTS_BCIS) { 1105#endif 1106 return (1); 1107 /* XXX to be removed */ 1108#ifdef HDAC_INTR_EXTRA 1109 } 1110#endif 1111 1112 return (0); 1113} 1114 1115/**************************************************************************** 1116 * void hdac_intr_handler(void *) 1117 * 1118 * Interrupt handler. Processes interrupts received from the hdac. 1119 ****************************************************************************/ 1120static void 1121hdac_intr_handler(void *context) 1122{ 1123 struct hdac_softc *sc; 1124 uint32_t intsts; 1125 uint8_t rirbsts; 1126 struct hdac_rirb *rirb_base; 1127 uint32_t trigger; 1128 1129 sc = (struct hdac_softc *)context; 1130 1131 hdac_lock(sc); 1132 if (sc->polling != 0) { 1133 hdac_unlock(sc); 1134 return; 1135 } 1136 1137 /* Do we have anything to do? */ 1138 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1139 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1140 hdac_unlock(sc); 1141 return; 1142 } 1143 1144 trigger = 0; 1145 1146 /* Was this a controller interrupt? */ 1147 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1148 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1149 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1150 /* Get as many responses that we can */ 1151 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1152 HDAC_WRITE_1(&sc->mem, 1153 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1154 if (hdac_rirb_flush(sc) != 0) 1155 trigger |= HDAC_TRIGGER_UNSOL; 1156 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1157 } 1158 /* XXX to be removed */ 1159 /* Clear interrupt and exit */ 1160#ifdef HDAC_INTR_EXTRA 1161 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1162#endif 1163 } 1164 1165 if (intsts & HDAC_INTSTS_SIS_MASK) { 1166 if ((intsts & (1 << sc->num_iss)) && 1167 hdac_stream_intr(sc, &sc->play) != 0) 1168 trigger |= HDAC_TRIGGER_PLAY; 1169 if ((intsts & (1 << 0)) && 1170 hdac_stream_intr(sc, &sc->rec) != 0) 1171 trigger |= HDAC_TRIGGER_REC; 1172 /* XXX to be removed */ 1173#ifdef HDAC_INTR_EXTRA 1174 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1175 HDAC_INTSTS_SIS_MASK); 1176#endif 1177 } 1178 1179 hdac_unlock(sc); 1180 1181 if (trigger & HDAC_TRIGGER_PLAY) 1182 chn_intr(sc->play.c); 1183 if (trigger & HDAC_TRIGGER_REC) 1184 chn_intr(sc->rec.c); 1185 if (trigger & HDAC_TRIGGER_UNSOL) 1186 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1187} 1188 1189/**************************************************************************** 1190 * int hdac_reset(hdac_softc *) 1191 * 1192 * Reset the hdac to a quiescent and known state. 1193 ****************************************************************************/ 1194static int 1195hdac_reset(struct hdac_softc *sc) 1196{ 1197 uint32_t gctl; 1198 int count, i; 1199 1200 /* 1201 * Stop all Streams DMA engine 1202 */ 1203 for (i = 0; i < sc->num_iss; i++) 1204 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1205 for (i = 0; i < sc->num_oss; i++) 1206 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1207 for (i = 0; i < sc->num_bss; i++) 1208 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1209 1210 /* 1211 * Stop Control DMA engines. 1212 */ 1213 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1214 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1215 1216 /* 1217 * Reset DMA position buffer. 1218 */ 1219 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1220 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1221 1222 /* 1223 * Reset the controller. The reset must remain asserted for 1224 * a minimum of 100us. 1225 */ 1226 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1227 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1228 count = 10000; 1229 do { 1230 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1231 if (!(gctl & HDAC_GCTL_CRST)) 1232 break; 1233 DELAY(10); 1234 } while (--count); 1235 if (gctl & HDAC_GCTL_CRST) { 1236 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1237 return (ENXIO); 1238 } 1239 DELAY(100); 1240 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1241 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1242 count = 10000; 1243 do { 1244 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1245 if (gctl & HDAC_GCTL_CRST) 1246 break; 1247 DELAY(10); 1248 } while (--count); 1249 if (!(gctl & HDAC_GCTL_CRST)) { 1250 device_printf(sc->dev, "Device stuck in reset\n"); 1251 return (ENXIO); 1252 } 1253 1254 /* 1255 * Wait for codecs to finish their own reset sequence. The delay here 1256 * should be of 250us but for some reasons, on it's not enough on my 1257 * computer. Let's use twice as much as necessary to make sure that 1258 * it's reset properly. 1259 */ 1260 DELAY(1000); 1261 1262 return (0); 1263} 1264 1265 1266/**************************************************************************** 1267 * int hdac_get_capabilities(struct hdac_softc *); 1268 * 1269 * Retreive the general capabilities of the hdac; 1270 * Number of Input Streams 1271 * Number of Output Streams 1272 * Number of bidirectional Streams 1273 * 64bit ready 1274 * CORB and RIRB sizes 1275 ****************************************************************************/ 1276static int 1277hdac_get_capabilities(struct hdac_softc *sc) 1278{ 1279 uint16_t gcap; 1280 uint8_t corbsize, rirbsize; 1281 1282 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1283 sc->num_iss = HDAC_GCAP_ISS(gcap); 1284 sc->num_oss = HDAC_GCAP_OSS(gcap); 1285 sc->num_bss = HDAC_GCAP_BSS(gcap); 1286 1287 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1288 1289 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1290 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1291 HDAC_CORBSIZE_CORBSZCAP_256) 1292 sc->corb_size = 256; 1293 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1294 HDAC_CORBSIZE_CORBSZCAP_16) 1295 sc->corb_size = 16; 1296 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1297 HDAC_CORBSIZE_CORBSZCAP_2) 1298 sc->corb_size = 2; 1299 else { 1300 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1301 __func__, corbsize); 1302 return (ENXIO); 1303 } 1304 1305 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1306 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1307 HDAC_RIRBSIZE_RIRBSZCAP_256) 1308 sc->rirb_size = 256; 1309 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1310 HDAC_RIRBSIZE_RIRBSZCAP_16) 1311 sc->rirb_size = 16; 1312 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1313 HDAC_RIRBSIZE_RIRBSZCAP_2) 1314 sc->rirb_size = 2; 1315 else { 1316 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1317 __func__, rirbsize); 1318 return (ENXIO); 1319 } 1320 1321 return (0); 1322} 1323 1324 1325/**************************************************************************** 1326 * void hdac_dma_cb 1327 * 1328 * This function is called by bus_dmamap_load when the mapping has been 1329 * established. We just record the physical address of the mapping into 1330 * the struct hdac_dma passed in. 1331 ****************************************************************************/ 1332static void 1333hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1334{ 1335 struct hdac_dma *dma; 1336 1337 if (error == 0) { 1338 dma = (struct hdac_dma *)callback_arg; 1339 dma->dma_paddr = segs[0].ds_addr; 1340 } 1341} 1342 1343 1344/**************************************************************************** 1345 * int hdac_dma_alloc 1346 * 1347 * This function allocate and setup a dma region (struct hdac_dma). 1348 * It must be freed by a corresponding hdac_dma_free. 1349 ****************************************************************************/ 1350static int 1351hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1352{ 1353 bus_size_t roundsz; 1354 int result; 1355 int lowaddr; 1356 1357 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1358 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1359 BUS_SPACE_MAXADDR_32BIT; 1360 bzero(dma, sizeof(*dma)); 1361 1362 /* 1363 * Create a DMA tag 1364 */ 1365 result = bus_dma_tag_create(NULL, /* parent */ 1366 HDAC_DMA_ALIGNMENT, /* alignment */ 1367 0, /* boundary */ 1368 lowaddr, /* lowaddr */ 1369 BUS_SPACE_MAXADDR, /* highaddr */ 1370 NULL, /* filtfunc */ 1371 NULL, /* fistfuncarg */ 1372 roundsz, /* maxsize */ 1373 1, /* nsegments */ 1374 roundsz, /* maxsegsz */ 1375 0, /* flags */ 1376 NULL, /* lockfunc */ 1377 NULL, /* lockfuncarg */ 1378 &dma->dma_tag); /* dmat */ 1379 if (result != 0) { 1380 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1381 __func__, result); 1382 goto hdac_dma_alloc_fail; 1383 } 1384 1385 /* 1386 * Allocate DMA memory 1387 */ 1388 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1389 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1390 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map); 1391 if (result != 0) { 1392 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1393 __func__, result); 1394 goto hdac_dma_alloc_fail; 1395 } 1396 1397 dma->dma_size = roundsz; 1398 1399 /* 1400 * Map the memory 1401 */ 1402 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1403 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1404 if (result != 0 || dma->dma_paddr == 0) { 1405 if (result == 0) 1406 result = ENOMEM; 1407 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1408 __func__, result); 1409 goto hdac_dma_alloc_fail; 1410 } 1411 1412 HDA_BOOTVERBOSE( 1413 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1414 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1415 ); 1416 1417 return (0); 1418 1419hdac_dma_alloc_fail: 1420 hdac_dma_free(sc, dma); 1421 1422 return (result); 1423} 1424 1425 1426/**************************************************************************** 1427 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1428 * 1429 * Free a struct dhac_dma that has been previously allocated via the 1430 * hdac_dma_alloc function. 1431 ****************************************************************************/ 1432static void 1433hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1434{ 1435 if (dma->dma_map != NULL) { 1436#if 0 1437 /* Flush caches */ 1438 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1439 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1440#endif 1441 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1442 } 1443 if (dma->dma_vaddr != NULL) { 1444 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1445 dma->dma_vaddr = NULL; 1446 } 1447 dma->dma_map = NULL; 1448 if (dma->dma_tag != NULL) { 1449 bus_dma_tag_destroy(dma->dma_tag); 1450 dma->dma_tag = NULL; 1451 } 1452 dma->dma_size = 0; 1453} 1454 1455/**************************************************************************** 1456 * int hdac_mem_alloc(struct hdac_softc *) 1457 * 1458 * Allocate all the bus resources necessary to speak with the physical 1459 * controller. 1460 ****************************************************************************/ 1461static int 1462hdac_mem_alloc(struct hdac_softc *sc) 1463{ 1464 struct hdac_mem *mem; 1465 1466 mem = &sc->mem; 1467 mem->mem_rid = PCIR_BAR(0); 1468 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1469 &mem->mem_rid, RF_ACTIVE); 1470 if (mem->mem_res == NULL) { 1471 device_printf(sc->dev, 1472 "%s: Unable to allocate memory resource\n", __func__); 1473 return (ENOMEM); 1474 } 1475 mem->mem_tag = rman_get_bustag(mem->mem_res); 1476 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1477 1478 return (0); 1479} 1480 1481/**************************************************************************** 1482 * void hdac_mem_free(struct hdac_softc *) 1483 * 1484 * Free up resources previously allocated by hdac_mem_alloc. 1485 ****************************************************************************/ 1486static void 1487hdac_mem_free(struct hdac_softc *sc) 1488{ 1489 struct hdac_mem *mem; 1490 1491 mem = &sc->mem; 1492 if (mem->mem_res != NULL) 1493 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1494 mem->mem_res); 1495 mem->mem_res = NULL; 1496} 1497 1498/**************************************************************************** 1499 * int hdac_irq_alloc(struct hdac_softc *) 1500 * 1501 * Allocate and setup the resources necessary for interrupt handling. 1502 ****************************************************************************/ 1503static int 1504hdac_irq_alloc(struct hdac_softc *sc) 1505{ 1506 struct hdac_irq *irq; 1507 int result; 1508 1509 irq = &sc->irq; 1510 irq->irq_rid = 0x0; 1511 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1512 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1513 if (irq->irq_res == NULL) { 1514 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1515 __func__); 1516 goto hdac_irq_alloc_fail; 1517 } 1518 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1519 hdac_intr_handler, sc, &irq->irq_handle); 1520 if (result != 0) { 1521 device_printf(sc->dev, 1522 "%s: Unable to setup interrupt handler (%x)\n", 1523 __func__, result); 1524 goto hdac_irq_alloc_fail; 1525 } 1526 1527 return (0); 1528 1529hdac_irq_alloc_fail: 1530 hdac_irq_free(sc); 1531 1532 return (ENXIO); 1533} 1534 1535/**************************************************************************** 1536 * void hdac_irq_free(struct hdac_softc *) 1537 * 1538 * Free up resources previously allocated by hdac_irq_alloc. 1539 ****************************************************************************/ 1540static void 1541hdac_irq_free(struct hdac_softc *sc) 1542{ 1543 struct hdac_irq *irq; 1544 1545 irq = &sc->irq; 1546 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1547 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1548 if (irq->irq_res != NULL) 1549 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1550 irq->irq_res); 1551 irq->irq_handle = NULL; 1552 irq->irq_res = NULL; 1553} 1554 1555/**************************************************************************** 1556 * void hdac_corb_init(struct hdac_softc *) 1557 * 1558 * Initialize the corb registers for operations but do not start it up yet. 1559 * The CORB engine must not be running when this function is called. 1560 ****************************************************************************/ 1561static void 1562hdac_corb_init(struct hdac_softc *sc) 1563{ 1564 uint8_t corbsize; 1565 uint64_t corbpaddr; 1566 1567 /* Setup the CORB size. */ 1568 switch (sc->corb_size) { 1569 case 256: 1570 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1571 break; 1572 case 16: 1573 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1574 break; 1575 case 2: 1576 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1577 break; 1578 default: 1579 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1580 } 1581 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1582 1583 /* Setup the CORB Address in the hdac */ 1584 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1585 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1586 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1587 1588 /* Set the WP and RP */ 1589 sc->corb_wp = 0; 1590 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1591 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1592 /* 1593 * The HDA specification indicates that the CORBRPRST bit will always 1594 * read as zero. Unfortunately, it seems that at least the 82801G 1595 * doesn't reset the bit to zero, which stalls the corb engine. 1596 * manually reset the bit to zero before continuing. 1597 */ 1598 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1599 1600 /* Enable CORB error reporting */ 1601#if 0 1602 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1603#endif 1604} 1605 1606/**************************************************************************** 1607 * void hdac_rirb_init(struct hdac_softc *) 1608 * 1609 * Initialize the rirb registers for operations but do not start it up yet. 1610 * The RIRB engine must not be running when this function is called. 1611 ****************************************************************************/ 1612static void 1613hdac_rirb_init(struct hdac_softc *sc) 1614{ 1615 uint8_t rirbsize; 1616 uint64_t rirbpaddr; 1617 1618 /* Setup the RIRB size. */ 1619 switch (sc->rirb_size) { 1620 case 256: 1621 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1622 break; 1623 case 16: 1624 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1625 break; 1626 case 2: 1627 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1628 break; 1629 default: 1630 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1631 } 1632 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1633 1634 /* Setup the RIRB Address in the hdac */ 1635 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1636 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1637 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1638 1639 /* Setup the WP and RP */ 1640 sc->rirb_rp = 0; 1641 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1642 1643 if (sc->polling == 0) { 1644 /* Setup the interrupt threshold */ 1645 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1646 1647 /* Enable Overrun and response received reporting */ 1648#if 0 1649 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1650 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1651#else 1652 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1653#endif 1654 } 1655 1656#if 0 1657 /* 1658 * Make sure that the Host CPU cache doesn't contain any dirty 1659 * cache lines that falls in the rirb. If I understood correctly, it 1660 * should be sufficient to do this only once as the rirb is purely 1661 * read-only from now on. 1662 */ 1663 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1664 BUS_DMASYNC_PREREAD); 1665#endif 1666} 1667 1668/**************************************************************************** 1669 * void hdac_corb_start(hdac_softc *) 1670 * 1671 * Startup the corb DMA engine 1672 ****************************************************************************/ 1673static void 1674hdac_corb_start(struct hdac_softc *sc) 1675{ 1676 uint32_t corbctl; 1677 1678 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1679 corbctl |= HDAC_CORBCTL_CORBRUN; 1680 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1681} 1682 1683/**************************************************************************** 1684 * void hdac_rirb_start(hdac_softc *) 1685 * 1686 * Startup the rirb DMA engine 1687 ****************************************************************************/ 1688static void 1689hdac_rirb_start(struct hdac_softc *sc) 1690{ 1691 uint32_t rirbctl; 1692 1693 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1694 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1695 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1696} 1697 1698 1699/**************************************************************************** 1700 * void hdac_scan_codecs(struct hdac_softc *) 1701 * 1702 * Scan the bus for available codecs. 1703 ****************************************************************************/ 1704static void 1705hdac_scan_codecs(struct hdac_softc *sc) 1706{ 1707 struct hdac_codec *codec; 1708 int i; 1709 uint16_t statests; 1710 1711 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1712 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1713 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1714 /* We have found a codec. */ 1715 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1716 M_HDAC, M_ZERO | M_NOWAIT); 1717 if (codec == NULL) { 1718 device_printf(sc->dev, 1719 "Unable to allocate memory for codec\n"); 1720 continue; 1721 } 1722 codec->commands = NULL; 1723 codec->responses_received = 0; 1724 codec->verbs_sent = 0; 1725 codec->sc = sc; 1726 codec->cad = i; 1727 sc->codecs[i] = codec; 1728 if (hdac_probe_codec(codec) != 0) 1729 break; 1730 } 1731 } 1732 /* All codecs have been probed, now try to attach drivers to them */ 1733 /* bus_generic_attach(sc->dev); */ 1734} 1735 1736/**************************************************************************** 1737 * void hdac_probe_codec(struct hdac_softc *, int) 1738 * 1739 * Probe a the given codec_id for available function groups. 1740 ****************************************************************************/ 1741static int 1742hdac_probe_codec(struct hdac_codec *codec) 1743{ 1744 struct hdac_softc *sc = codec->sc; 1745 struct hdac_devinfo *devinfo; 1746 uint32_t vendorid, revisionid, subnode; 1747 int startnode; 1748 int endnode; 1749 int i; 1750 nid_t cad = codec->cad; 1751 1752 HDA_BOOTVERBOSE( 1753 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1754 ); 1755 vendorid = hdac_command(sc, 1756 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1757 cad); 1758 revisionid = hdac_command(sc, 1759 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1760 cad); 1761 subnode = hdac_command(sc, 1762 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1763 cad); 1764 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1765 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1766 1767 HDA_BOOTVERBOSE( 1768 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1769 startnode, endnode); 1770 ); 1771 for (i = startnode; i < endnode; i++) { 1772 devinfo = hdac_probe_function(codec, i); 1773 if (devinfo != NULL) { 1774 /* XXX Ignore other FG. */ 1775 devinfo->vendor_id = 1776 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1777 devinfo->device_id = 1778 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1779 devinfo->revision_id = 1780 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1781 devinfo->stepping_id = 1782 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1783 HDA_BOOTVERBOSE( 1784 device_printf(sc->dev, 1785 "HDA_DEBUG: \tFound AFG nid=%d " 1786 "[startnode=%d endnode=%d]\n", 1787 devinfo->nid, startnode, endnode); 1788 ); 1789 return (1); 1790 } 1791 } 1792 1793 HDA_BOOTVERBOSE( 1794 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1795 ); 1796 return (0); 1797} 1798 1799static struct hdac_devinfo * 1800hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1801{ 1802 struct hdac_softc *sc = codec->sc; 1803 struct hdac_devinfo *devinfo; 1804 uint32_t fctgrptype; 1805 nid_t cad = codec->cad; 1806 1807 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1808 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1809 1810 /* XXX For now, ignore other FG. */ 1811 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1812 return (NULL); 1813 1814 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1815 M_NOWAIT | M_ZERO); 1816 if (devinfo == NULL) { 1817 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1818 __func__); 1819 return (NULL); 1820 } 1821 1822 devinfo->nid = nid; 1823 devinfo->node_type = fctgrptype; 1824 devinfo->codec = codec; 1825 1826 hdac_add_child(sc, devinfo); 1827 1828 return (devinfo); 1829} 1830 1831static void 1832hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1833{ 1834 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1835 device_set_ivars(devinfo->dev, (void *)devinfo); 1836 /* XXX - Print more information when booting verbose??? */ 1837} 1838 1839static void 1840hdac_widget_connection_parse(struct hdac_widget *w) 1841{ 1842 struct hdac_softc *sc = w->devinfo->codec->sc; 1843 uint32_t res; 1844 int i, j, max, ents, entnum; 1845 nid_t cad = w->devinfo->codec->cad; 1846 nid_t nid = w->nid; 1847 nid_t cnid, addcnid, prevcnid; 1848 1849 w->nconns = 0; 1850 1851 res = hdac_command(sc, 1852 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1853 1854 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1855 1856 if (ents < 1) 1857 return; 1858 1859 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1860 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1861 prevcnid = 0; 1862 1863#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1864#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1865#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1866#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1867#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1868 1869 for (i = 0; i < ents; i += entnum) { 1870 res = hdac_command(sc, 1871 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1872 for (j = 0; j < entnum; j++) { 1873 cnid = CONN_CNID(res, entnum, j); 1874 if (cnid == 0) { 1875 if (w->nconns < ents) 1876 device_printf(sc->dev, 1877 "%s: nid=%d WARNING: zero cnid " 1878 "entnum=%d j=%d index=%d " 1879 "entries=%d found=%d res=0x%08x\n", 1880 __func__, nid, entnum, j, i, 1881 ents, w->nconns, res); 1882 else 1883 goto getconns_out; 1884 } 1885 if (cnid < w->devinfo->startnode || 1886 cnid >= w->devinfo->endnode) { 1887 HDA_BOOTVERBOSE( 1888 device_printf(sc->dev, 1889 "%s: GHOST: nid=%d j=%d " 1890 "entnum=%d index=%d res=0x%08x\n", 1891 __func__, nid, j, entnum, i, res); 1892 ); 1893 } 1894 if (CONN_RANGE(res, entnum, j) == 0) 1895 addcnid = cnid; 1896 else if (prevcnid == 0 || prevcnid >= cnid) { 1897 device_printf(sc->dev, 1898 "%s: WARNING: Invalid child range " 1899 "nid=%d index=%d j=%d entnum=%d " 1900 "prevcnid=%d cnid=%d res=0x%08x\n", 1901 __func__, nid, i, j, entnum, prevcnid, 1902 cnid, res); 1903 addcnid = cnid; 1904 } else 1905 addcnid = prevcnid + 1; 1906 while (addcnid <= cnid) { 1907 if (w->nconns > max) { 1908 device_printf(sc->dev, 1909 "%s: nid=%d: Adding %d: " 1910 "Max connection reached! max=%d\n", 1911 __func__, nid, addcnid, max + 1); 1912 goto getconns_out; 1913 } 1914 w->conns[w->nconns++] = addcnid++; 1915 } 1916 prevcnid = cnid; 1917 } 1918 } 1919 1920getconns_out: 1921 HDA_BOOTVERBOSE( 1922 device_printf(sc->dev, 1923 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1924 __func__, nid, ents, w->nconns); 1925 ); 1926 return; 1927} 1928 1929static uint32_t 1930hdac_widget_pin_getconfig(struct hdac_widget *w) 1931{ 1932 struct hdac_softc *sc; 1933 uint32_t config, orig, id; 1934 nid_t cad, nid; 1935 1936 sc = w->devinfo->codec->sc; 1937 cad = w->devinfo->codec->cad; 1938 nid = w->nid; 1939 id = hdac_codec_id(w->devinfo); 1940 1941 config = hdac_command(sc, 1942 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1943 cad); 1944 orig = config; 1945 1946 /* 1947 * XXX REWRITE!!!! Don't argue! 1948 */ 1949 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1950 switch (nid) { 1951 case 26: 1952 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1953 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1954 break; 1955 case 27: 1956 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1957 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1958 break; 1959 default: 1960 break; 1961 } 1962 } else if (id == HDA_CODEC_ALC880 && 1963 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1964 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1965 /* 1966 * Super broken BIOS 1967 */ 1968 switch (nid) { 1969 case 20: 1970 break; 1971 case 21: 1972 break; 1973 case 22: 1974 break; 1975 case 23: 1976 break; 1977 case 24: /* MIC1 */ 1978 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1979 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1980 break; 1981 case 25: /* XXX MIC2 */ 1982 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1983 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1984 break; 1985 case 26: /* LINE1 */ 1986 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1987 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1988 break; 1989 case 27: /* XXX LINE2 */ 1990 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1991 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1992 break; 1993 case 28: /* CD */ 1994 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1995 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1996 break; 1997 case 30: 1998 break; 1999 case 31: 2000 break; 2001 default: 2002 break; 2003 } 2004 } else if (id == HDA_CODEC_ALC883 && 2005 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2006 switch (nid) { 2007 case 25: 2008 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2009 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2010 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2011 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2012 break; 2013 case 28: 2014 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2015 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2016 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2017 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2018 break; 2019 default: 2020 break; 2021 } 2022 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 2023 HP_V3000_SUBVENDOR) { 2024 switch (nid) { 2025 case 18: 2026 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2027 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2028 break; 2029 case 20: 2030 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2031 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2032 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2033 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2034 break; 2035 case 21: 2036 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2037 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2038 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2039 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2040 break; 2041 default: 2042 break; 2043 } 2044 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2045 HP_DV5000_SUBVENDOR) { 2046 switch (nid) { 2047 case 20: 2048 case 21: 2049 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2050 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2051 break; 2052 default: 2053 break; 2054 } 2055 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2056 ASUS_W6F_SUBVENDOR) { 2057 switch (nid) { 2058 case 11: 2059 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2060 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2061 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2062 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2063 break; 2064 case 15: 2065 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2066 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2067 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2068 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2069 break; 2070 default: 2071 break; 2072 } 2073 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2074 UNIWILL_9075_SUBVENDOR) { 2075 switch (nid) { 2076 case 15: 2077 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2078 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2079 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2080 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2081 break; 2082 default: 2083 break; 2084 } 2085 } else if (id == HDA_CODEC_AD1986A && 2086 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2087 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2088 switch (nid) { 2089 case 28: /* LINE */ 2090 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2091 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2092 break; 2093 case 29: /* MIC */ 2094 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2095 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2096 break; 2097 default: 2098 break; 2099 } 2100 } 2101 2102 HDA_BOOTVERBOSE( 2103 if (config != orig) 2104 device_printf(sc->dev, 2105 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2106 nid, orig, config); 2107 ); 2108 2109 return (config); 2110} 2111 2112static uint32_t 2113hdac_widget_pin_getcaps(struct hdac_widget *w) 2114{ 2115 struct hdac_softc *sc; 2116 uint32_t caps, orig, id; 2117 nid_t cad, nid; 2118 2119 sc = w->devinfo->codec->sc; 2120 cad = w->devinfo->codec->cad; 2121 nid = w->nid; 2122 id = hdac_codec_id(w->devinfo); 2123 2124 caps = hdac_command(sc, 2125 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2126 orig = caps; 2127 2128 HDA_BOOTVERBOSE( 2129 if (caps != orig) 2130 device_printf(sc->dev, 2131 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2132 nid, orig, caps); 2133 ); 2134 2135 return (caps); 2136} 2137 2138static void 2139hdac_widget_pin_parse(struct hdac_widget *w) 2140{ 2141 struct hdac_softc *sc = w->devinfo->codec->sc; 2142 uint32_t config, pincap; 2143 char *devstr, *connstr; 2144 nid_t cad = w->devinfo->codec->cad; 2145 nid_t nid = w->nid; 2146 2147 config = hdac_widget_pin_getconfig(w); 2148 w->wclass.pin.config = config; 2149 2150 pincap = hdac_widget_pin_getcaps(w); 2151 w->wclass.pin.cap = pincap; 2152 2153 w->wclass.pin.ctrl = hdac_command(sc, 2154 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2155 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2156 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2157 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2158 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2159 2160 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2161 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2162 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2163 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2164 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2165 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2166 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2167 w->param.eapdbtl = hdac_command(sc, 2168 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2169 w->param.eapdbtl &= 0x7; 2170 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2171 } else 2172 w->param.eapdbtl = HDAC_INVALID; 2173 2174 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2175 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2176 devstr = "line out"; 2177 break; 2178 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2179 devstr = "speaker"; 2180 break; 2181 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2182 devstr = "headphones out"; 2183 break; 2184 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2185 devstr = "CD"; 2186 break; 2187 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2188 devstr = "SPDIF out"; 2189 break; 2190 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2191 devstr = "digital (other) out"; 2192 break; 2193 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2194 devstr = "modem, line side"; 2195 break; 2196 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2197 devstr = "modem, handset side"; 2198 break; 2199 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2200 devstr = "line in"; 2201 break; 2202 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2203 devstr = "AUX"; 2204 break; 2205 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2206 devstr = "Mic in"; 2207 break; 2208 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2209 devstr = "telephony"; 2210 break; 2211 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2212 devstr = "SPDIF in"; 2213 break; 2214 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2215 devstr = "digital (other) in"; 2216 break; 2217 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2218 devstr = "other"; 2219 break; 2220 default: 2221 devstr = "unknown"; 2222 break; 2223 } 2224 2225 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2226 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2227 connstr = "jack"; 2228 break; 2229 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2230 connstr = "none"; 2231 break; 2232 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2233 connstr = "fixed"; 2234 break; 2235 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2236 connstr = "jack / fixed"; 2237 break; 2238 default: 2239 connstr = "unknown"; 2240 break; 2241 } 2242 2243 strlcat(w->name, ": ", sizeof(w->name)); 2244 strlcat(w->name, devstr, sizeof(w->name)); 2245 strlcat(w->name, " (", sizeof(w->name)); 2246 strlcat(w->name, connstr, sizeof(w->name)); 2247 strlcat(w->name, ")", sizeof(w->name)); 2248} 2249 2250static void 2251hdac_widget_parse(struct hdac_widget *w) 2252{ 2253 struct hdac_softc *sc = w->devinfo->codec->sc; 2254 uint32_t wcap, cap; 2255 char *typestr; 2256 nid_t cad = w->devinfo->codec->cad; 2257 nid_t nid = w->nid; 2258 2259 wcap = hdac_command(sc, 2260 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2261 cad); 2262 w->param.widget_cap = wcap; 2263 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2264 2265 switch (w->type) { 2266 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2267 typestr = "audio output"; 2268 break; 2269 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2270 typestr = "audio input"; 2271 break; 2272 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2273 typestr = "audio mixer"; 2274 break; 2275 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2276 typestr = "audio selector"; 2277 break; 2278 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2279 typestr = "pin"; 2280 break; 2281 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2282 typestr = "power widget"; 2283 break; 2284 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2285 typestr = "volume widget"; 2286 break; 2287 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2288 typestr = "beep widget"; 2289 break; 2290 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2291 typestr = "vendor widget"; 2292 break; 2293 default: 2294 typestr = "unknown type"; 2295 break; 2296 } 2297 2298 strlcpy(w->name, typestr, sizeof(w->name)); 2299 2300 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2301 hdac_command(sc, 2302 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2303 cad); 2304 DELAY(1000); 2305 } 2306 2307 hdac_widget_connection_parse(w); 2308 2309 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2310 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2311 w->param.outamp_cap = 2312 hdac_command(sc, 2313 HDA_CMD_GET_PARAMETER(cad, nid, 2314 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2315 else 2316 w->param.outamp_cap = 2317 w->devinfo->function.audio.outamp_cap; 2318 } else 2319 w->param.outamp_cap = 0; 2320 2321 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2322 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2323 w->param.inamp_cap = 2324 hdac_command(sc, 2325 HDA_CMD_GET_PARAMETER(cad, nid, 2326 HDA_PARAM_INPUT_AMP_CAP), cad); 2327 else 2328 w->param.inamp_cap = 2329 w->devinfo->function.audio.inamp_cap; 2330 } else 2331 w->param.inamp_cap = 0; 2332 2333 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2334 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2335 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2336 cap = hdac_command(sc, 2337 HDA_CMD_GET_PARAMETER(cad, nid, 2338 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2339 w->param.supp_stream_formats = (cap != 0) ? cap : 2340 w->devinfo->function.audio.supp_stream_formats; 2341 cap = hdac_command(sc, 2342 HDA_CMD_GET_PARAMETER(cad, nid, 2343 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2344 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2345 w->devinfo->function.audio.supp_pcm_size_rate; 2346 } else { 2347 w->param.supp_stream_formats = 2348 w->devinfo->function.audio.supp_stream_formats; 2349 w->param.supp_pcm_size_rate = 2350 w->devinfo->function.audio.supp_pcm_size_rate; 2351 } 2352 } else { 2353 w->param.supp_stream_formats = 0; 2354 w->param.supp_pcm_size_rate = 0; 2355 } 2356 2357 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2358 hdac_widget_pin_parse(w); 2359} 2360 2361static struct hdac_widget * 2362hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2363{ 2364 if (devinfo == NULL || devinfo->widget == NULL || 2365 nid < devinfo->startnode || nid >= devinfo->endnode) 2366 return (NULL); 2367 return (&devinfo->widget[nid - devinfo->startnode]); 2368} 2369 2370static __inline int 2371hda_poll_channel(struct hdac_chan *ch) 2372{ 2373 uint32_t sz, delta; 2374 volatile uint32_t ptr; 2375 2376 if (ch->active == 0) 2377 return (0); 2378 2379 sz = ch->blksz * ch->blkcnt; 2380 if (ch->dmapos != NULL) 2381 ptr = *(ch->dmapos); 2382 else 2383 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2384 ch->off + HDAC_SDLPIB); 2385 ch->ptr = ptr; 2386 ptr %= sz; 2387 ptr &= ~(ch->blksz - 1); 2388 delta = (sz + ptr - ch->prevptr) % sz; 2389 2390 if (delta < ch->blksz) 2391 return (0); 2392 2393 ch->prevptr = ptr; 2394 2395 return (1); 2396} 2397 2398#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2399 2400static void 2401hda_poll_callback(void *arg) 2402{ 2403 struct hdac_softc *sc = arg; 2404 uint32_t trigger; 2405 2406 if (sc == NULL) 2407 return; 2408 2409 hdac_lock(sc); 2410 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2411 hdac_unlock(sc); 2412 return; 2413 } 2414 2415 trigger = 0; 2416 trigger |= (hda_poll_channel(&sc->play) != 0) ? HDAC_TRIGGER_PLAY : 0; 2417 trigger |= (hda_poll_channel(&sc->rec)) != 0 ? HDAC_TRIGGER_REC : 0; 2418 2419 /* XXX */ 2420 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2421 hda_poll_callback, sc); 2422 2423 hdac_unlock(sc); 2424 2425 if (trigger & HDAC_TRIGGER_PLAY) 2426 chn_intr(sc->play.c); 2427 if (trigger & HDAC_TRIGGER_REC) 2428 chn_intr(sc->rec.c); 2429} 2430 2431static int 2432hdac_rirb_flush(struct hdac_softc *sc) 2433{ 2434 struct hdac_rirb *rirb_base, *rirb; 2435 struct hdac_codec *codec; 2436 struct hdac_command_list *commands; 2437 nid_t cad; 2438 uint32_t resp; 2439 uint8_t rirbwp; 2440 int ret; 2441 2442 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2443 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2444#if 0 2445 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2446 BUS_DMASYNC_POSTREAD); 2447#endif 2448 2449 ret = 0; 2450 2451 while (sc->rirb_rp != rirbwp) { 2452 sc->rirb_rp++; 2453 sc->rirb_rp %= sc->rirb_size; 2454 rirb = &rirb_base[sc->rirb_rp]; 2455 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2456 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2457 sc->codecs[cad] == NULL) 2458 continue; 2459 resp = rirb->response; 2460 codec = sc->codecs[cad]; 2461 commands = codec->commands; 2462 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2463 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2464 ((resp >> 26) & 0xffff); 2465 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2466 } else if (commands != NULL && commands->num_commands > 0 && 2467 codec->responses_received < commands->num_commands) 2468 commands->responses[codec->responses_received++] = 2469 resp; 2470 ret++; 2471 } 2472 2473 return (ret); 2474} 2475 2476static int 2477hdac_unsolq_flush(struct hdac_softc *sc) 2478{ 2479 nid_t cad; 2480 uint32_t tag; 2481 int ret = 0; 2482 2483 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2484 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2485 while (sc->unsolq_rp != sc->unsolq_wp) { 2486 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2487 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2488 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2489 hdac_unsolicited_handler(sc->codecs[cad], tag); 2490 ret++; 2491 } 2492 sc->unsolq_st = HDAC_UNSOLQ_READY; 2493 } 2494 2495 return (ret); 2496} 2497 2498static void 2499hdac_poll_callback(void *arg) 2500{ 2501 struct hdac_softc *sc = arg; 2502 if (sc == NULL) 2503 return; 2504 2505 hdac_lock(sc); 2506 if (sc->polling == 0 || sc->poll_ival == 0) { 2507 hdac_unlock(sc); 2508 return; 2509 } 2510 if (hdac_rirb_flush(sc) != 0) 2511 hdac_unsolq_flush(sc); 2512 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2513 hdac_unlock(sc); 2514} 2515 2516static void 2517hdac_stream_stop(struct hdac_chan *ch) 2518{ 2519 struct hdac_softc *sc = ch->devinfo->codec->sc; 2520 uint32_t ctl; 2521 2522 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2523 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2524 HDAC_SDCTL_RUN); 2525 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2526 2527 ch->active = 0; 2528 2529 if (sc->polling != 0) { 2530 int pollticks; 2531 2532 if (hda_chan_active(sc) == 0) { 2533 callout_stop(&sc->poll_hda); 2534 sc->poll_ticks = 1; 2535 } else { 2536 if (sc->play.active != 0) 2537 ch = &sc->play; 2538 else 2539 ch = &sc->rec; 2540 pollticks = ((uint64_t)hz * ch->blksz) / 2541 ((uint64_t)sndbuf_getbps(ch->b) * 2542 sndbuf_getspd(ch->b)); 2543 pollticks >>= 2; 2544 if (pollticks > hz) 2545 pollticks = hz; 2546 if (pollticks < 1) { 2547 HDA_BOOTVERBOSE( 2548 device_printf(sc->dev, 2549 "%s: pollticks=%d < 1 !\n", 2550 __func__, pollticks); 2551 ); 2552 pollticks = 1; 2553 } 2554 if (pollticks > sc->poll_ticks) { 2555 HDA_BOOTVERBOSE( 2556 device_printf(sc->dev, 2557 "%s: pollticks %d -> %d\n", 2558 __func__, sc->poll_ticks, 2559 pollticks); 2560 ); 2561 sc->poll_ticks = pollticks; 2562 callout_reset(&sc->poll_hda, 1, 2563 hda_poll_callback, sc); 2564 } 2565 } 2566 } else { 2567 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2568 ctl &= ~(1 << (ch->off >> 5)); 2569 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2570 } 2571} 2572 2573static void 2574hdac_stream_start(struct hdac_chan *ch) 2575{ 2576 struct hdac_softc *sc = ch->devinfo->codec->sc; 2577 uint32_t ctl; 2578 2579 if (sc->polling != 0) { 2580 int pollticks; 2581 2582 pollticks = ((uint64_t)hz * ch->blksz) / 2583 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2584 pollticks >>= 2; 2585 if (pollticks > hz) 2586 pollticks = hz; 2587 if (pollticks < 1) { 2588 HDA_BOOTVERBOSE( 2589 device_printf(sc->dev, 2590 "%s: pollticks=%d < 1 !\n", 2591 __func__, pollticks); 2592 ); 2593 pollticks = 1; 2594 } 2595 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2596 HDA_BOOTVERBOSE( 2597 if (hda_chan_active(sc) == 0) { 2598 device_printf(sc->dev, 2599 "%s: pollticks=%d\n", 2600 __func__, pollticks); 2601 } else { 2602 device_printf(sc->dev, 2603 "%s: pollticks %d -> %d\n", 2604 __func__, sc->poll_ticks, 2605 pollticks); 2606 } 2607 ); 2608 sc->poll_ticks = pollticks; 2609 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2610 sc); 2611 } 2612 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2613 ctl |= HDAC_SDCTL_RUN; 2614 } else { 2615 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2616 ctl |= 1 << (ch->off >> 5); 2617 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2618 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2619 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2620 HDAC_SDCTL_RUN; 2621 } 2622 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2623 2624 ch->active = 1; 2625} 2626 2627static void 2628hdac_stream_reset(struct hdac_chan *ch) 2629{ 2630 struct hdac_softc *sc = ch->devinfo->codec->sc; 2631 int timeout = 1000; 2632 int to = timeout; 2633 uint32_t ctl; 2634 2635 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2636 ctl |= HDAC_SDCTL_SRST; 2637 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2638 do { 2639 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2640 if (ctl & HDAC_SDCTL_SRST) 2641 break; 2642 DELAY(10); 2643 } while (--to); 2644 if (!(ctl & HDAC_SDCTL_SRST)) { 2645 device_printf(sc->dev, "timeout in reset\n"); 2646 } 2647 ctl &= ~HDAC_SDCTL_SRST; 2648 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2649 to = timeout; 2650 do { 2651 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2652 if (!(ctl & HDAC_SDCTL_SRST)) 2653 break; 2654 DELAY(10); 2655 } while (--to); 2656 if (ctl & HDAC_SDCTL_SRST) 2657 device_printf(sc->dev, "can't reset!\n"); 2658} 2659 2660static void 2661hdac_stream_setid(struct hdac_chan *ch) 2662{ 2663 struct hdac_softc *sc = ch->devinfo->codec->sc; 2664 uint32_t ctl; 2665 2666 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2667 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2668 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2669 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2670} 2671 2672static void 2673hdac_bdl_setup(struct hdac_chan *ch) 2674{ 2675 struct hdac_softc *sc = ch->devinfo->codec->sc; 2676 struct hdac_bdle *bdle; 2677 uint64_t addr; 2678 uint32_t blksz, blkcnt; 2679 int i; 2680 2681 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2682 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2683 2684 if (sc->polling != 0) { 2685 blksz = ch->blksz * ch->blkcnt; 2686 blkcnt = 1; 2687 } else { 2688 blksz = ch->blksz; 2689 blkcnt = ch->blkcnt; 2690 } 2691 2692 for (i = 0; i < blkcnt; i++, bdle++) { 2693 bdle->addrl = (uint32_t)addr; 2694 bdle->addrh = (uint32_t)(addr >> 32); 2695 bdle->len = blksz; 2696 bdle->ioc = 1 ^ sc->polling; 2697 addr += blksz; 2698 } 2699 2700 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2701 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2702 addr = ch->bdl_dma.dma_paddr; 2703 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2704 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2705 if (ch->dmapos != NULL && 2706 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2707 addr = sc->pos_dma.dma_paddr; 2708 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2709 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2710 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2711 } 2712} 2713 2714static int 2715hdac_bdl_alloc(struct hdac_chan *ch) 2716{ 2717 struct hdac_softc *sc = ch->devinfo->codec->sc; 2718 int rc; 2719 2720 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2721 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2722 if (rc) { 2723 device_printf(sc->dev, "can't alloc bdl\n"); 2724 return (rc); 2725 } 2726 2727 return (0); 2728} 2729 2730static void 2731hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2732 int index, int lmute, int rmute, 2733 int left, int right, int dir) 2734{ 2735 uint16_t v = 0; 2736 2737 if (sc == NULL) 2738 return; 2739 2740 if (left != right || lmute != rmute) { 2741 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2742 (lmute << 7) | left; 2743 hdac_command(sc, 2744 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2745 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2746 (rmute << 7) | right; 2747 } else 2748 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2749 (lmute << 7) | left; 2750 2751 hdac_command(sc, 2752 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2753} 2754 2755static void 2756hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2757 int left, int right) 2758{ 2759 struct hdac_softc *sc; 2760 nid_t nid, cad; 2761 int lmute, rmute; 2762 2763 if (ctl == NULL || ctl->widget == NULL || 2764 ctl->widget->devinfo == NULL || 2765 ctl->widget->devinfo->codec == NULL || 2766 ctl->widget->devinfo->codec->sc == NULL) 2767 return; 2768 2769 sc = ctl->widget->devinfo->codec->sc; 2770 cad = ctl->widget->devinfo->codec->cad; 2771 nid = ctl->widget->nid; 2772 2773 if (mute == HDA_AMP_MUTE_DEFAULT) { 2774 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2775 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2776 } else { 2777 lmute = HDA_AMP_LEFT_MUTED(mute); 2778 rmute = HDA_AMP_RIGHT_MUTED(mute); 2779 } 2780 2781 if (ctl->dir & HDA_CTL_OUT) 2782 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2783 lmute, rmute, left, right, 0); 2784 if (ctl->dir & HDA_CTL_IN) 2785 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2786 lmute, rmute, left, right, 1); 2787 ctl->left = left; 2788 ctl->right = right; 2789} 2790 2791static void 2792hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2793{ 2794 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2795 return; 2796 hdac_command(w->devinfo->codec->sc, 2797 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2798 w->nid, index), w->devinfo->codec->cad); 2799 w->selconn = index; 2800} 2801 2802 2803/**************************************************************************** 2804 * uint32_t hdac_command_sendone_internal 2805 * 2806 * Wrapper function that sends only one command to a given codec 2807 ****************************************************************************/ 2808static uint32_t 2809hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2810{ 2811 struct hdac_command_list cl; 2812 uint32_t response = HDAC_INVALID; 2813 2814 if (!hdac_lockowned(sc)) 2815 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2816 cl.num_commands = 1; 2817 cl.verbs = &verb; 2818 cl.responses = &response; 2819 2820 hdac_command_send_internal(sc, &cl, cad); 2821 2822 return (response); 2823} 2824 2825/**************************************************************************** 2826 * hdac_command_send_internal 2827 * 2828 * Send a command list to the codec via the corb. We queue as much verbs as 2829 * we can and msleep on the codec. When the interrupt get the responses 2830 * back from the rirb, it will wake us up so we can queue the remaining verbs 2831 * if any. 2832 ****************************************************************************/ 2833static void 2834hdac_command_send_internal(struct hdac_softc *sc, 2835 struct hdac_command_list *commands, nid_t cad) 2836{ 2837 struct hdac_codec *codec; 2838 int corbrp; 2839 uint32_t *corb; 2840 int timeout; 2841 int retry = 10; 2842 struct hdac_rirb *rirb_base; 2843 2844 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2845 commands->num_commands < 1) 2846 return; 2847 2848 codec = sc->codecs[cad]; 2849 codec->commands = commands; 2850 codec->responses_received = 0; 2851 codec->verbs_sent = 0; 2852 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2853 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2854 2855 do { 2856 if (codec->verbs_sent != commands->num_commands) { 2857 /* Queue as many verbs as possible */ 2858 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2859#if 0 2860 bus_dmamap_sync(sc->corb_dma.dma_tag, 2861 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2862#endif 2863 while (codec->verbs_sent != commands->num_commands && 2864 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2865 sc->corb_wp++; 2866 sc->corb_wp %= sc->corb_size; 2867 corb[sc->corb_wp] = 2868 commands->verbs[codec->verbs_sent++]; 2869 } 2870 2871 /* Send the verbs to the codecs */ 2872#if 0 2873 bus_dmamap_sync(sc->corb_dma.dma_tag, 2874 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2875#endif 2876 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2877 } 2878 2879 timeout = 1000; 2880 while (hdac_rirb_flush(sc) == 0 && --timeout) 2881 DELAY(10); 2882 } while ((codec->verbs_sent != commands->num_commands || 2883 codec->responses_received != commands->num_commands) && --retry); 2884 2885 if (retry == 0) 2886 device_printf(sc->dev, 2887 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2888 __func__, commands->num_commands, codec->verbs_sent, 2889 codec->responses_received); 2890 2891 codec->commands = NULL; 2892 codec->responses_received = 0; 2893 codec->verbs_sent = 0; 2894 2895 hdac_unsolq_flush(sc); 2896} 2897 2898 2899/**************************************************************************** 2900 * Device Methods 2901 ****************************************************************************/ 2902 2903/**************************************************************************** 2904 * int hdac_probe(device_t) 2905 * 2906 * Probe for the presence of an hdac. If none is found, check for a generic 2907 * match using the subclass of the device. 2908 ****************************************************************************/ 2909static int 2910hdac_probe(device_t dev) 2911{ 2912 int i, result; 2913 uint32_t model; 2914 uint16_t class, subclass; 2915 char desc[64]; 2916 2917 model = (uint32_t)pci_get_device(dev) << 16; 2918 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2919 class = pci_get_class(dev); 2920 subclass = pci_get_subclass(dev); 2921 2922 bzero(desc, sizeof(desc)); 2923 result = ENXIO; 2924 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2925 if (hdac_devices[i].model == model) { 2926 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2927 result = BUS_PROBE_DEFAULT; 2928 break; 2929 } 2930 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2931 class == PCIC_MULTIMEDIA && 2932 subclass == PCIS_MULTIMEDIA_HDA) { 2933 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2934 result = BUS_PROBE_GENERIC; 2935 break; 2936 } 2937 } 2938 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2939 subclass == PCIS_MULTIMEDIA_HDA) { 2940 strlcpy(desc, "Generic", sizeof(desc)); 2941 result = BUS_PROBE_GENERIC; 2942 } 2943 if (result != ENXIO) { 2944 strlcat(desc, " High Definition Audio Controller", 2945 sizeof(desc)); 2946 device_set_desc_copy(dev, desc); 2947 } 2948 2949 return (result); 2950} 2951 2952static void * 2953hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2954 struct pcm_channel *c, int dir) 2955{ 2956 struct hdac_devinfo *devinfo = data; 2957 struct hdac_softc *sc = devinfo->codec->sc; 2958 struct hdac_chan *ch; 2959 2960 hdac_lock(sc); 2961 if (dir == PCMDIR_PLAY) { 2962 ch = &sc->play; 2963 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2964 devinfo->function.audio.playcnt++; 2965 } else { 2966 ch = &sc->rec; 2967 ch->off = devinfo->function.audio.reccnt << 5; 2968 devinfo->function.audio.reccnt++; 2969 } 2970 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2971 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2972 ch->pcmrates[0] = 48000; 2973 ch->pcmrates[1] = 0; 2974 } 2975 if (sc->pos_dma.dma_vaddr != NULL) 2976 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 2977 (sc->streamcnt * 8)); 2978 else 2979 ch->dmapos = NULL; 2980 ch->sid = ++sc->streamcnt; 2981 ch->dir = dir; 2982 ch->b = b; 2983 ch->c = c; 2984 ch->devinfo = devinfo; 2985 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2986 ch->blkcnt = sc->chan_blkcnt; 2987 hdac_unlock(sc); 2988 2989 if (hdac_bdl_alloc(ch) != 0) { 2990 ch->blkcnt = 0; 2991 return (NULL); 2992 } 2993 2994 if (sndbuf_alloc(ch->b, sc->chan_dmat, 2995 (sc->nocache != 0) ? BUS_DMA_NOCACHE : 0, sc->chan_size) != 0) 2996 return (NULL); 2997 2998 return (ch); 2999} 3000 3001static int 3002hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3003{ 3004 struct hdac_chan *ch = data; 3005 int i; 3006 3007 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3008 if (format == ch->caps.fmtlist[i]) { 3009 ch->fmt = format; 3010 return (0); 3011 } 3012 } 3013 3014 return (EINVAL); 3015} 3016 3017static int 3018hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3019{ 3020 struct hdac_chan *ch = data; 3021 uint32_t spd = 0, threshold; 3022 int i; 3023 3024 for (i = 0; ch->pcmrates[i] != 0; i++) { 3025 spd = ch->pcmrates[i]; 3026 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3027 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3028 if (speed < threshold) 3029 break; 3030 } 3031 3032 if (spd == 0) /* impossible */ 3033 ch->spd = 48000; 3034 else 3035 ch->spd = spd; 3036 3037 return (ch->spd); 3038} 3039 3040static void 3041hdac_stream_setup(struct hdac_chan *ch) 3042{ 3043 struct hdac_softc *sc = ch->devinfo->codec->sc; 3044 int i; 3045 nid_t cad = ch->devinfo->codec->cad; 3046 uint16_t fmt; 3047 3048 fmt = 0; 3049 if (ch->fmt & AFMT_S16_LE) 3050 fmt |= ch->bit16 << 4; 3051 else if (ch->fmt & AFMT_S32_LE) 3052 fmt |= ch->bit32 << 4; 3053 else 3054 fmt |= 1 << 4; 3055 3056 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3057 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3058 fmt |= hda_rate_tab[i].base; 3059 fmt |= hda_rate_tab[i].mul; 3060 fmt |= hda_rate_tab[i].div; 3061 break; 3062 } 3063 } 3064 3065 if (ch->fmt & AFMT_STEREO) 3066 fmt |= 1; 3067 3068 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3069 3070 for (i = 0; ch->io[i] != -1; i++) { 3071 HDA_BOOTVERBOSE( 3072 device_printf(sc->dev, 3073 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3074 "fmt=0x%08x\n", 3075 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3076 ch->io[i], fmt); 3077 ); 3078 hdac_command(sc, 3079 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3080 hdac_command(sc, 3081 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3082 ch->sid << 4), cad); 3083 } 3084} 3085 3086static int 3087hdac_channel_setfragments(kobj_t obj, void *data, 3088 uint32_t blksz, uint32_t blkcnt) 3089{ 3090 struct hdac_chan *ch = data; 3091 struct hdac_softc *sc = ch->devinfo->codec->sc; 3092 3093 blksz &= HDA_BLK_ALIGN; 3094 3095 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3096 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3097 if (blksz < HDA_BLK_MIN) 3098 blksz = HDA_BLK_MIN; 3099 if (blkcnt > HDA_BDL_MAX) 3100 blkcnt = HDA_BDL_MAX; 3101 if (blkcnt < HDA_BDL_MIN) 3102 blkcnt = HDA_BDL_MIN; 3103 3104 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3105 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3106 blkcnt >>= 1; 3107 else if ((blksz >> 1) >= HDA_BLK_MIN) 3108 blksz >>= 1; 3109 else 3110 break; 3111 } 3112 3113 if ((sndbuf_getblksz(ch->b) != blksz || 3114 sndbuf_getblkcnt(ch->b) != blkcnt) && 3115 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3116 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3117 __func__, blksz, blkcnt); 3118 3119 ch->blksz = sndbuf_getblksz(ch->b); 3120 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3121 3122 return (1); 3123} 3124 3125static int 3126hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3127{ 3128 struct hdac_chan *ch = data; 3129 struct hdac_softc *sc = ch->devinfo->codec->sc; 3130 3131 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3132 3133 return (ch->blksz); 3134} 3135 3136static void 3137hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3138{ 3139 struct hdac_devinfo *devinfo = ch->devinfo; 3140 nid_t cad = devinfo->codec->cad; 3141 int i; 3142 3143 hdac_stream_stop(ch); 3144 3145 for (i = 0; ch->io[i] != -1; i++) { 3146 hdac_command(sc, 3147 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3148 0), cad); 3149 } 3150} 3151 3152static void 3153hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3154{ 3155 ch->ptr = 0; 3156 ch->prevptr = 0; 3157 hdac_stream_stop(ch); 3158 hdac_stream_reset(ch); 3159 hdac_bdl_setup(ch); 3160 hdac_stream_setid(ch); 3161 hdac_stream_setup(ch); 3162 hdac_stream_start(ch); 3163} 3164 3165static int 3166hdac_channel_trigger(kobj_t obj, void *data, int go) 3167{ 3168 struct hdac_chan *ch = data; 3169 struct hdac_softc *sc = ch->devinfo->codec->sc; 3170 3171 if (!PCMTRIG_COMMON(go)) 3172 return (0); 3173 3174 hdac_lock(sc); 3175 switch (go) { 3176 case PCMTRIG_START: 3177 hdac_channel_start(sc, ch); 3178 break; 3179 case PCMTRIG_STOP: 3180 case PCMTRIG_ABORT: 3181 hdac_channel_stop(sc, ch); 3182 break; 3183 default: 3184 break; 3185 } 3186 hdac_unlock(sc); 3187 3188 return (0); 3189} 3190 3191static int 3192hdac_channel_getptr(kobj_t obj, void *data) 3193{ 3194 struct hdac_chan *ch = data; 3195 struct hdac_softc *sc = ch->devinfo->codec->sc; 3196 uint32_t ptr; 3197 3198 hdac_lock(sc); 3199 if (sc->polling != 0) 3200 ptr = ch->ptr; 3201 else if (ch->dmapos != NULL) 3202 ptr = *(ch->dmapos); 3203 else 3204 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3205 hdac_unlock(sc); 3206 3207 /* 3208 * Round to available space and force 128 bytes aligment. 3209 */ 3210 ptr %= ch->blksz * ch->blkcnt; 3211 ptr &= HDA_BLK_ALIGN; 3212 3213 return (ptr); 3214} 3215 3216static struct pcmchan_caps * 3217hdac_channel_getcaps(kobj_t obj, void *data) 3218{ 3219 return (&((struct hdac_chan *)data)->caps); 3220} 3221 3222static kobj_method_t hdac_channel_methods[] = { 3223 KOBJMETHOD(channel_init, hdac_channel_init), 3224 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3225 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3226 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3227 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3228 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3229 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3230 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3231 { 0, 0 } 3232}; 3233CHANNEL_DECLARE(hdac_channel); 3234 3235static void 3236hdac_jack_poll_callback(void *arg) 3237{ 3238 struct hdac_devinfo *devinfo = arg; 3239 struct hdac_softc *sc; 3240 3241 if (devinfo == NULL || devinfo->codec == NULL || 3242 devinfo->codec->sc == NULL) 3243 return; 3244 sc = devinfo->codec->sc; 3245 hdac_lock(sc); 3246 if (sc->poll_ival == 0) { 3247 hdac_unlock(sc); 3248 return; 3249 } 3250 hdac_hp_switch_handler(devinfo); 3251 callout_reset(&sc->poll_jack, sc->poll_ival, 3252 hdac_jack_poll_callback, devinfo); 3253 hdac_unlock(sc); 3254} 3255 3256static int 3257hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3258{ 3259 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3260 struct hdac_softc *sc = devinfo->codec->sc; 3261 struct hdac_widget *w, *cw; 3262 struct hdac_audio_ctl *ctl; 3263 uint32_t mask, recmask, id; 3264 int i, j, softpcmvol; 3265 nid_t cad; 3266 3267 hdac_lock(sc); 3268 3269 mask = 0; 3270 recmask = 0; 3271 3272 id = hdac_codec_id(devinfo); 3273 cad = devinfo->codec->cad; 3274 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3275 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3276 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3277 continue; 3278 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3279 if (w == NULL || w->enable == 0 || w->type != 3280 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3281 continue; 3282 if (hdac_hp_switch[i].polling != 0) 3283 callout_reset(&sc->poll_jack, 1, 3284 hdac_jack_poll_callback, devinfo); 3285 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3286 hdac_command(sc, 3287 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3288 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3289 HDAC_UNSOLTAG_EVENT_HP), cad); 3290 else 3291 continue; 3292 hdac_hp_switch_handler(devinfo); 3293 HDA_BOOTVERBOSE( 3294 device_printf(sc->dev, 3295 "HDA_DEBUG: Enabling headphone/speaker " 3296 "audio routing switching:\n"); 3297 device_printf(sc->dev, 3298 "HDA_DEBUG: \tindex=%d nid=%d " 3299 "pci_subvendor=0x%08x " 3300 "codec=0x%08x [%s]\n", 3301 i, w->nid, sc->pci_subvendor, id, 3302 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3303 "UNSOL"); 3304 ); 3305 break; 3306 } 3307 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3308 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3309 sc->pci_subvendor) && 3310 hdac_eapd_switch[i].id == id)) 3311 continue; 3312 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3313 if (w == NULL || w->enable == 0) 3314 break; 3315 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3316 w->param.eapdbtl == HDAC_INVALID) 3317 break; 3318 mask |= SOUND_MASK_OGAIN; 3319 break; 3320 } 3321 3322 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3323 w = hdac_widget_get(devinfo, i); 3324 if (w == NULL || w->enable == 0) 3325 continue; 3326 mask |= w->ctlflags; 3327 if (!(w->pflags & HDA_ADC_RECSEL)) 3328 continue; 3329 for (j = 0; j < w->nconns; j++) { 3330 cw = hdac_widget_get(devinfo, w->conns[j]); 3331 if (cw == NULL || cw->enable == 0) 3332 continue; 3333 recmask |= cw->ctlflags; 3334 } 3335 } 3336 3337 if (!(mask & SOUND_MASK_PCM)) { 3338 softpcmvol = 1; 3339 mask |= SOUND_MASK_PCM; 3340 } else 3341 softpcmvol = (devinfo->function.audio.quirks & 3342 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3343 3344 i = 0; 3345 ctl = NULL; 3346 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3347 if (ctl->widget == NULL || ctl->enable == 0) 3348 continue; 3349 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3350 continue; 3351 if (ctl->step > 0) 3352 break; 3353 } 3354 3355 if (softpcmvol == 1 || ctl == NULL) { 3356 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3357 HDA_BOOTVERBOSE( 3358 device_printf(sc->dev, 3359 "HDA_DEBUG: %s Soft PCM volume\n", 3360 (softpcmvol == 1) ? 3361 "Forcing" : "Enabling"); 3362 ); 3363 i = 0; 3364 /* 3365 * XXX Temporary quirk for STAC9220, until the parser 3366 * become smarter. 3367 */ 3368 if (id == HDA_CODEC_STAC9220) { 3369 mask |= SOUND_MASK_VOLUME; 3370 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3371 NULL) { 3372 if (ctl->widget == NULL || ctl->enable == 0) 3373 continue; 3374 if (ctl->widget->nid == 11 && ctl->index == 0) { 3375 ctl->ossmask = SOUND_MASK_VOLUME; 3376 ctl->ossval = 100 | (100 << 8); 3377 } else 3378 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3379 } 3380 } else if (id == HDA_CODEC_STAC9221) { 3381 mask |= SOUND_MASK_VOLUME; 3382 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3383 NULL) { 3384 if (ctl->widget == NULL) 3385 continue; 3386 if (ctl->widget->type == 3387 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3388 ctl->index == 0 && (ctl->widget->nid == 2 || 3389 ctl->widget->enable != 0)) { 3390 ctl->enable = 1; 3391 ctl->ossmask = SOUND_MASK_VOLUME; 3392 ctl->ossval = 100 | (100 << 8); 3393 } else if (ctl->enable == 0) 3394 continue; 3395 else 3396 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3397 } 3398 } else { 3399 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3400 SOUND_MASK_PCM); 3401 if (!(mask & SOUND_MASK_VOLUME)) 3402 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3403 SOUND_MIXER_NONE); 3404 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3405 NULL) { 3406 if (ctl->widget == NULL || ctl->enable == 0) 3407 continue; 3408 if (!HDA_FLAG_MATCH(ctl->ossmask, 3409 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3410 continue; 3411 if (!(ctl->mute == 1 && ctl->step == 0)) 3412 ctl->enable = 0; 3413 } 3414 } 3415 } 3416 3417 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3418 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3419 SOUND_MASK_OGAIN); 3420 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3421 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3422 3423 mix_setrecdevs(m, recmask); 3424 mix_setdevs(m, mask); 3425 3426 hdac_unlock(sc); 3427 3428 return (0); 3429} 3430 3431static int 3432hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3433 unsigned left, unsigned right) 3434{ 3435 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3436 struct hdac_softc *sc = devinfo->codec->sc; 3437 struct hdac_widget *w; 3438 struct hdac_audio_ctl *ctl; 3439 uint32_t id, mute; 3440 int lvol, rvol, mlvol, mrvol; 3441 int i = 0; 3442 3443 hdac_lock(sc); 3444 if (dev == SOUND_MIXER_OGAIN) { 3445 uint32_t orig; 3446 /*if (left != right || !(left == 0 || left == 1)) { 3447 hdac_unlock(sc); 3448 return (-1); 3449 }*/ 3450 id = hdac_codec_id(devinfo); 3451 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3452 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3453 sc->pci_subvendor) && 3454 hdac_eapd_switch[i].id == id) 3455 break; 3456 } 3457 if (i >= HDAC_EAPD_SWITCH_LEN) { 3458 hdac_unlock(sc); 3459 return (-1); 3460 } 3461 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3462 if (w == NULL || 3463 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3464 w->param.eapdbtl == HDAC_INVALID) { 3465 hdac_unlock(sc); 3466 return (-1); 3467 } 3468 orig = w->param.eapdbtl; 3469 if (left == 0) 3470 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3471 else 3472 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3473 if (orig != w->param.eapdbtl) { 3474 uint32_t val; 3475 3476 if (hdac_eapd_switch[i].hp_switch != 0) 3477 hdac_hp_switch_handler(devinfo); 3478 val = w->param.eapdbtl; 3479 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3480 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3481 hdac_command(sc, 3482 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3483 w->nid, val), devinfo->codec->cad); 3484 } 3485 hdac_unlock(sc); 3486 return (left | (left << 8)); 3487 } 3488 if (dev == SOUND_MIXER_VOLUME) 3489 devinfo->function.audio.mvol = left | (right << 8); 3490 3491 mlvol = devinfo->function.audio.mvol & 0x7f; 3492 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3493 lvol = 0; 3494 rvol = 0; 3495 3496 i = 0; 3497 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3498 if (ctl->widget == NULL || ctl->enable == 0 || 3499 !(ctl->ossmask & (1 << dev))) 3500 continue; 3501 switch (dev) { 3502 case SOUND_MIXER_VOLUME: 3503 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3504 lvol = (lvol * ctl->step) / 100; 3505 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3506 rvol = (rvol * ctl->step) / 100; 3507 break; 3508 default: 3509 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3510 lvol = (left * mlvol) / 100; 3511 lvol = (lvol * ctl->step) / 100; 3512 rvol = (right * mrvol) / 100; 3513 rvol = (rvol * ctl->step) / 100; 3514 } else { 3515 lvol = (left * ctl->step) / 100; 3516 rvol = (right * ctl->step) / 100; 3517 } 3518 ctl->ossval = left | (right << 8); 3519 break; 3520 } 3521 mute = 0; 3522 if (ctl->step < 1) { 3523 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3524 (ctl->muted & HDA_AMP_MUTE_LEFT); 3525 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3526 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3527 } else { 3528 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3529 (ctl->muted & HDA_AMP_MUTE_LEFT); 3530 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3531 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3532 } 3533 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3534 } 3535 hdac_unlock(sc); 3536 3537 return (left | (right << 8)); 3538} 3539 3540static int 3541hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3542{ 3543 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3544 struct hdac_widget *w, *cw; 3545 struct hdac_softc *sc = devinfo->codec->sc; 3546 uint32_t ret = src, target; 3547 int i, j; 3548 3549 target = 0; 3550 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3551 if (src & (1 << i)) { 3552 target = 1 << i; 3553 break; 3554 } 3555 } 3556 3557 hdac_lock(sc); 3558 3559 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3560 w = hdac_widget_get(devinfo, i); 3561 if (w == NULL || w->enable == 0) 3562 continue; 3563 if (!(w->pflags & HDA_ADC_RECSEL)) 3564 continue; 3565 for (j = 0; j < w->nconns; j++) { 3566 cw = hdac_widget_get(devinfo, w->conns[j]); 3567 if (cw == NULL || cw->enable == 0) 3568 continue; 3569 if ((target == SOUND_MASK_VOLUME && 3570 cw->type != 3571 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3572 (target != SOUND_MASK_VOLUME && 3573 cw->type == 3574 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3575 continue; 3576 if (cw->ctlflags & target) { 3577 if (!(w->pflags & HDA_ADC_LOCKED)) 3578 hdac_widget_connection_select(w, j); 3579 ret = target; 3580 j += w->nconns; 3581 } 3582 } 3583 } 3584 3585 hdac_unlock(sc); 3586 3587 return (ret); 3588} 3589 3590static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3591 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3592 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3593 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3594 { 0, 0 } 3595}; 3596MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3597 3598static void 3599hdac_unsolq_task(void *context, int pending) 3600{ 3601 struct hdac_softc *sc; 3602 3603 sc = (struct hdac_softc *)context; 3604 3605 hdac_lock(sc); 3606 hdac_unsolq_flush(sc); 3607 hdac_unlock(sc); 3608} 3609 3610/**************************************************************************** 3611 * int hdac_attach(device_t) 3612 * 3613 * Attach the device into the kernel. Interrupts usually won't be enabled 3614 * when this function is called. Setup everything that doesn't require 3615 * interrupts and defer probing of codecs until interrupts are enabled. 3616 ****************************************************************************/ 3617static int 3618hdac_attach(device_t dev) 3619{ 3620 struct hdac_softc *sc; 3621 int result; 3622 int i; 3623 uint16_t vendor; 3624 uint8_t v; 3625 3626 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 3627 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3628 sc->dev = dev; 3629 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3630 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3631 vendor = pci_get_vendor(dev); 3632 3633 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3634 /* Screw nx6325 - subdevice/subvendor swapped */ 3635 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3636 } 3637 3638 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3639 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3640 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3641 3642 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 3643 3644 sc->poll_ticks = 1; 3645 sc->poll_ival = HDAC_POLL_INTERVAL; 3646 if (resource_int_value(device_get_name(dev), 3647 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3648 sc->polling = 1; 3649 else 3650 sc->polling = 0; 3651 3652 sc->chan_size = pcm_getbuffersize(dev, 3653 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3654 3655 if (resource_int_value(device_get_name(dev), 3656 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3657 i &= HDA_BLK_ALIGN; 3658 if (i < HDA_BLK_MIN) 3659 i = HDA_BLK_MIN; 3660 sc->chan_blkcnt = sc->chan_size / i; 3661 i = 0; 3662 while (sc->chan_blkcnt >> i) 3663 i++; 3664 sc->chan_blkcnt = 1 << (i - 1); 3665 if (sc->chan_blkcnt < HDA_BDL_MIN) 3666 sc->chan_blkcnt = HDA_BDL_MIN; 3667 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3668 sc->chan_blkcnt = HDA_BDL_MAX; 3669 } else 3670 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3671 3672 result = bus_dma_tag_create(NULL, /* parent */ 3673 HDAC_DMA_ALIGNMENT, /* alignment */ 3674 0, /* boundary */ 3675 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3676 BUS_SPACE_MAXADDR, /* highaddr */ 3677 NULL, /* filtfunc */ 3678 NULL, /* fistfuncarg */ 3679 sc->chan_size, /* maxsize */ 3680 1, /* nsegments */ 3681 sc->chan_size, /* maxsegsz */ 3682 0, /* flags */ 3683 NULL, /* lockfunc */ 3684 NULL, /* lockfuncarg */ 3685 &sc->chan_dmat); /* dmat */ 3686 if (result != 0) { 3687 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3688 __func__, result); 3689 snd_mtxfree(sc->lock); 3690 free(sc, M_DEVBUF); 3691 return (ENXIO); 3692 } 3693 3694 3695 sc->hdabus = NULL; 3696 for (i = 0; i < HDAC_CODEC_MAX; i++) 3697 sc->codecs[i] = NULL; 3698 3699 pci_enable_busmaster(dev); 3700 3701 if (vendor == INTEL_VENDORID) { 3702 /* TCSEL -> TC0 */ 3703 v = pci_read_config(dev, 0x44, 1); 3704 pci_write_config(dev, 0x44, v & 0xf8, 1); 3705 HDA_BOOTVERBOSE( 3706 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3707 pci_read_config(dev, 0x44, 1)); 3708 ); 3709 } 3710 3711#if defined(__i386__) || defined(__amd64__) 3712 sc->nocache = 1; 3713 3714 if (resource_int_value(device_get_name(dev), 3715 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3716#else 3717 sc->nocache = 0; 3718#endif 3719 /* 3720 * Try to enable PCIe snoop to avoid messing around with 3721 * uncacheable DMA attribute. Since PCIe snoop register 3722 * config is pretty much vendor specific, there are no 3723 * general solutions on how to enable it, forcing us (even 3724 * Microsoft) to enable uncacheable or write combined DMA 3725 * by default. 3726 * 3727 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3728 */ 3729 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3730 if (hdac_pcie_snoop[i].vendor != vendor) 3731 continue; 3732 sc->nocache = 0; 3733 if (hdac_pcie_snoop[i].reg == 0x00) 3734 break; 3735 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3736 if ((v & hdac_pcie_snoop[i].enable) == 3737 hdac_pcie_snoop[i].enable) 3738 break; 3739 v &= hdac_pcie_snoop[i].mask; 3740 v |= hdac_pcie_snoop[i].enable; 3741 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3742 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3743 if ((v & hdac_pcie_snoop[i].enable) != 3744 hdac_pcie_snoop[i].enable) { 3745 HDA_BOOTVERBOSE( 3746 device_printf(dev, 3747 "WARNING: Failed to enable PCIe " 3748 "snoop!\n"); 3749 ); 3750#if defined(__i386__) || defined(__amd64__) 3751 sc->nocache = 1; 3752#endif 3753 } 3754 break; 3755 } 3756#if defined(__i386__) || defined(__amd64__) 3757 } 3758#endif 3759 3760 HDA_BOOTVERBOSE( 3761 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3762 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor); 3763 ); 3764 3765 /* Allocate resources */ 3766 result = hdac_mem_alloc(sc); 3767 if (result != 0) 3768 goto hdac_attach_fail; 3769 result = hdac_irq_alloc(sc); 3770 if (result != 0) 3771 goto hdac_attach_fail; 3772 3773 /* Get Capabilities */ 3774 result = hdac_get_capabilities(sc); 3775 if (result != 0) 3776 goto hdac_attach_fail; 3777 3778 /* Allocate CORB and RIRB dma memory */ 3779 result = hdac_dma_alloc(sc, &sc->corb_dma, 3780 sc->corb_size * sizeof(uint32_t)); 3781 if (result != 0) 3782 goto hdac_attach_fail; 3783 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3784 sc->rirb_size * sizeof(struct hdac_rirb)); 3785 if (result != 0) 3786 goto hdac_attach_fail; 3787 3788 /* Quiesce everything */ 3789 hdac_reset(sc); 3790 3791 /* Initialize the CORB and RIRB */ 3792 hdac_corb_init(sc); 3793 hdac_rirb_init(sc); 3794 3795 /* Defer remaining of initialization until interrupts are enabled */ 3796 sc->intrhook.ich_func = hdac_attach2; 3797 sc->intrhook.ich_arg = (void *)sc; 3798 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3799 sc->intrhook.ich_func = NULL; 3800 hdac_attach2((void *)sc); 3801 } 3802 3803 return (0); 3804 3805hdac_attach_fail: 3806 hdac_irq_free(sc); 3807 hdac_dma_free(sc, &sc->rirb_dma); 3808 hdac_dma_free(sc, &sc->corb_dma); 3809 hdac_mem_free(sc); 3810 snd_mtxfree(sc->lock); 3811 free(sc, M_DEVBUF); 3812 3813 return (ENXIO); 3814} 3815 3816static void 3817hdac_audio_parse(struct hdac_devinfo *devinfo) 3818{ 3819 struct hdac_softc *sc = devinfo->codec->sc; 3820 struct hdac_widget *w; 3821 uint32_t res; 3822 int i; 3823 nid_t cad, nid; 3824 3825 cad = devinfo->codec->cad; 3826 nid = devinfo->nid; 3827 3828 hdac_command(sc, 3829 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3830 3831 DELAY(100); 3832 3833 res = hdac_command(sc, 3834 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3835 3836 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3837 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3838 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3839 3840 res = hdac_command(sc, 3841 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3842 devinfo->function.audio.gpio = res; 3843 3844 HDA_BOOTVERBOSE( 3845 device_printf(sc->dev, " Vendor: 0x%08x\n", 3846 devinfo->vendor_id); 3847 device_printf(sc->dev, " Device: 0x%08x\n", 3848 devinfo->device_id); 3849 device_printf(sc->dev, " Revision: 0x%08x\n", 3850 devinfo->revision_id); 3851 device_printf(sc->dev, " Stepping: 0x%08x\n", 3852 devinfo->stepping_id); 3853 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3854 sc->pci_subvendor); 3855 device_printf(sc->dev, " Nodes: start=%d " 3856 "endnode=%d total=%d\n", 3857 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3858 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3859 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3860 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3861 sc->num_iss, sc->num_oss, sc->num_bss); 3862 device_printf(sc->dev, " GPIO: 0x%08x\n", 3863 devinfo->function.audio.gpio); 3864 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3865 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3866 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3867 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3868 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3869 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3870 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3871 ); 3872 3873 res = hdac_command(sc, 3874 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3875 cad); 3876 devinfo->function.audio.supp_stream_formats = res; 3877 3878 res = hdac_command(sc, 3879 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3880 cad); 3881 devinfo->function.audio.supp_pcm_size_rate = res; 3882 3883 res = hdac_command(sc, 3884 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3885 cad); 3886 devinfo->function.audio.outamp_cap = res; 3887 3888 res = hdac_command(sc, 3889 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3890 cad); 3891 devinfo->function.audio.inamp_cap = res; 3892 3893 if (devinfo->nodecnt > 0) 3894 devinfo->widget = (struct hdac_widget *)malloc( 3895 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3896 M_NOWAIT | M_ZERO); 3897 else 3898 devinfo->widget = NULL; 3899 3900 if (devinfo->widget == NULL) { 3901 device_printf(sc->dev, "unable to allocate widgets!\n"); 3902 devinfo->endnode = devinfo->startnode; 3903 devinfo->nodecnt = 0; 3904 return; 3905 } 3906 3907 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3908 w = hdac_widget_get(devinfo, i); 3909 if (w == NULL) 3910 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3911 else { 3912 w->devinfo = devinfo; 3913 w->nid = i; 3914 w->enable = 1; 3915 w->selconn = -1; 3916 w->pflags = 0; 3917 w->ctlflags = 0; 3918 w->param.eapdbtl = HDAC_INVALID; 3919 hdac_widget_parse(w); 3920 } 3921 } 3922} 3923 3924static void 3925hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3926{ 3927 struct hdac_softc *sc = devinfo->codec->sc; 3928 struct hdac_audio_ctl *ctls; 3929 struct hdac_widget *w, *cw; 3930 int i, j, cnt, max, ocap, icap; 3931 int mute, offset, step, size; 3932 3933 /* XXX This is redundant */ 3934 max = 0; 3935 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3936 w = hdac_widget_get(devinfo, i); 3937 if (w == NULL || w->enable == 0) 3938 continue; 3939 if (w->param.outamp_cap != 0) 3940 max++; 3941 if (w->param.inamp_cap != 0) { 3942 switch (w->type) { 3943 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3944 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3945 for (j = 0; j < w->nconns; j++) { 3946 cw = hdac_widget_get(devinfo, 3947 w->conns[j]); 3948 if (cw == NULL || cw->enable == 0) 3949 continue; 3950 max++; 3951 } 3952 break; 3953 default: 3954 max++; 3955 break; 3956 } 3957 } 3958 } 3959 3960 devinfo->function.audio.ctlcnt = max; 3961 3962 if (max < 1) 3963 return; 3964 3965 ctls = (struct hdac_audio_ctl *)malloc( 3966 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3967 3968 if (ctls == NULL) { 3969 /* Blekh! */ 3970 device_printf(sc->dev, "unable to allocate ctls!\n"); 3971 devinfo->function.audio.ctlcnt = 0; 3972 return; 3973 } 3974 3975 cnt = 0; 3976 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3977 if (cnt >= max) { 3978 device_printf(sc->dev, "%s: Ctl overflow!\n", 3979 __func__); 3980 break; 3981 } 3982 w = hdac_widget_get(devinfo, i); 3983 if (w == NULL || w->enable == 0) 3984 continue; 3985 ocap = w->param.outamp_cap; 3986 icap = w->param.inamp_cap; 3987 if (ocap != 0) { 3988 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3989 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3990 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3991 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3992 /*if (offset > step) { 3993 HDA_BOOTVERBOSE( 3994 device_printf(sc->dev, 3995 "HDA_DEBUG: BUGGY outamp: nid=%d " 3996 "[offset=%d > step=%d]\n", 3997 w->nid, offset, step); 3998 ); 3999 offset = step; 4000 }*/ 4001 ctls[cnt].enable = 1; 4002 ctls[cnt].widget = w; 4003 ctls[cnt].mute = mute; 4004 ctls[cnt].step = step; 4005 ctls[cnt].size = size; 4006 ctls[cnt].offset = offset; 4007 ctls[cnt].left = offset; 4008 ctls[cnt].right = offset; 4009 ctls[cnt++].dir = HDA_CTL_OUT; 4010 } 4011 4012 if (icap != 0) { 4013 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4014 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4015 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4016 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4017 /*if (offset > step) { 4018 HDA_BOOTVERBOSE( 4019 device_printf(sc->dev, 4020 "HDA_DEBUG: BUGGY inamp: nid=%d " 4021 "[offset=%d > step=%d]\n", 4022 w->nid, offset, step); 4023 ); 4024 offset = step; 4025 }*/ 4026 switch (w->type) { 4027 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4028 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4029 for (j = 0; j < w->nconns; j++) { 4030 if (cnt >= max) { 4031 device_printf(sc->dev, 4032 "%s: Ctl overflow!\n", 4033 __func__); 4034 break; 4035 } 4036 cw = hdac_widget_get(devinfo, 4037 w->conns[j]); 4038 if (cw == NULL || cw->enable == 0) 4039 continue; 4040 ctls[cnt].enable = 1; 4041 ctls[cnt].widget = w; 4042 ctls[cnt].childwidget = cw; 4043 ctls[cnt].index = j; 4044 ctls[cnt].mute = mute; 4045 ctls[cnt].step = step; 4046 ctls[cnt].size = size; 4047 ctls[cnt].offset = offset; 4048 ctls[cnt].left = offset; 4049 ctls[cnt].right = offset; 4050 ctls[cnt++].dir = HDA_CTL_IN; 4051 } 4052 break; 4053 default: 4054 if (cnt >= max) { 4055 device_printf(sc->dev, 4056 "%s: Ctl overflow!\n", 4057 __func__); 4058 break; 4059 } 4060 ctls[cnt].enable = 1; 4061 ctls[cnt].widget = w; 4062 ctls[cnt].mute = mute; 4063 ctls[cnt].step = step; 4064 ctls[cnt].size = size; 4065 ctls[cnt].offset = offset; 4066 ctls[cnt].left = offset; 4067 ctls[cnt].right = offset; 4068 ctls[cnt++].dir = HDA_CTL_IN; 4069 break; 4070 } 4071 } 4072 } 4073 4074 devinfo->function.audio.ctl = ctls; 4075} 4076 4077static const struct { 4078 uint32_t model; 4079 uint32_t id; 4080 uint32_t set, unset; 4081} hdac_quirks[] = { 4082 /* 4083 * XXX Force stereo quirk. Monoural recording / playback 4084 * on few codecs (especially ALC880) seems broken or 4085 * perhaps unsupported. 4086 */ 4087 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4088 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4089 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4090 HDA_QUIRK_GPIO0, 0 }, 4091 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4092 HDA_QUIRK_GPIO0, 0 }, 4093 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4094 HDA_QUIRK_GPIO0, 0 }, 4095 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4096 HDA_QUIRK_GPIO0, 0 }, 4097 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4098 HDA_QUIRK_GPIO0, 0 }, 4099 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4100 HDA_QUIRK_EAPDINV, 0 }, 4101 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4102 HDA_QUIRK_EAPDINV, 0 }, 4103 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4104 HDA_QUIRK_OVREF, 0 }, 4105 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4106 HDA_QUIRK_OVREF, 0 }, 4107 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4108 HDA_QUIRK_OVREF, 0 }, 4109 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4110 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4111 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4112 HDA_QUIRK_GPIO1, 0 }, 4113 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4114 HDA_QUIRK_EAPDINV, 0 }, 4115 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4116 HDA_QUIRK_EAPDINV, 0 }, 4117 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4118 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4119 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4120 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4121 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4122 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4123 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4124 0, HDA_QUIRK_FORCESTEREO }, 4125 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4126 HDA_QUIRK_SOFTPCMVOL, 0 } 4127}; 4128#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4129 4130static void 4131hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4132{ 4133 struct hdac_widget *w; 4134 struct hdac_audio_ctl *ctl; 4135 uint32_t id, subvendor; 4136 int i; 4137 4138 id = hdac_codec_id(devinfo); 4139 subvendor = devinfo->codec->sc->pci_subvendor; 4140 4141 /* 4142 * Quirks 4143 */ 4144 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4145 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4146 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4147 continue; 4148 if (hdac_quirks[i].set != 0) 4149 devinfo->function.audio.quirks |= 4150 hdac_quirks[i].set; 4151 if (hdac_quirks[i].unset != 0) 4152 devinfo->function.audio.quirks &= 4153 ~(hdac_quirks[i].unset); 4154 } 4155 4156 switch (id) { 4157 case HDA_CODEC_ALC260: 4158 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4159 w = hdac_widget_get(devinfo, i); 4160 if (w == NULL || w->enable == 0) 4161 continue; 4162 if (w->type != 4163 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4164 continue; 4165 if (w->nid != 5) 4166 w->enable = 0; 4167 } 4168 if (subvendor == HP_XW4300_SUBVENDOR) { 4169 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4170 if (ctl != NULL && ctl->widget != NULL) { 4171 ctl->ossmask = SOUND_MASK_SPEAKER; 4172 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4173 } 4174 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4175 if (ctl != NULL && ctl->widget != NULL) { 4176 ctl->ossmask = SOUND_MASK_SPEAKER; 4177 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4178 } 4179 } else if (subvendor == HP_3010_SUBVENDOR) { 4180 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4181 if (ctl != NULL && ctl->widget != NULL) { 4182 ctl->ossmask = SOUND_MASK_SPEAKER; 4183 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4184 } 4185 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4186 if (ctl != NULL && ctl->widget != NULL) { 4187 ctl->ossmask = SOUND_MASK_SPEAKER; 4188 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4189 } 4190 } 4191 break; 4192 case HDA_CODEC_ALC861: 4193 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4194 if (ctl != NULL) 4195 ctl->muted = HDA_AMP_MUTE_ALL; 4196 break; 4197 case HDA_CODEC_ALC880: 4198 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4199 w = hdac_widget_get(devinfo, i); 4200 if (w == NULL || w->enable == 0) 4201 continue; 4202 if (w->type == 4203 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4204 w->nid != 9 && w->nid != 29) { 4205 w->enable = 0; 4206 } else if (w->type != 4207 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4208 w->nid == 29) { 4209 w->type = 4210 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4211 w->param.widget_cap &= 4212 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4213 w->param.widget_cap |= 4214 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4215 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4216 strlcpy(w->name, "beep widget", sizeof(w->name)); 4217 } 4218 } 4219 break; 4220 case HDA_CODEC_ALC883: 4221 /* 4222 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4223 * Clear vref cap for jack connectivity. 4224 */ 4225 w = hdac_widget_get(devinfo, 24); 4226 if (w != NULL && w->enable != 0 && w->type == 4227 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4228 (w->wclass.pin.config & 4229 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4230 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4231 w->wclass.pin.cap &= ~( 4232 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4233 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4234 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4235 w = hdac_widget_get(devinfo, 25); 4236 if (w != NULL && w->enable != 0 && w->type == 4237 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4238 (w->wclass.pin.config & 4239 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4240 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4241 w->wclass.pin.cap &= ~( 4242 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4243 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4244 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4245 /* 4246 * nid: 26 = Line-in, leave it alone. 4247 */ 4248 break; 4249 case HDA_CODEC_AD1981HD: 4250 w = hdac_widget_get(devinfo, 11); 4251 if (w != NULL && w->enable != 0 && w->nconns > 3) 4252 w->selconn = 3; 4253 if (subvendor == IBM_M52_SUBVENDOR) { 4254 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4255 if (ctl != NULL) 4256 ctl->ossmask = SOUND_MASK_SPEAKER; 4257 } 4258 break; 4259 case HDA_CODEC_AD1986A: 4260 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4261 w = hdac_widget_get(devinfo, i); 4262 if (w == NULL || w->enable == 0) 4263 continue; 4264 if (w->type != 4265 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4266 continue; 4267 if (w->nid != 3) 4268 w->enable = 0; 4269 } 4270 if (subvendor == ASUS_M2NPVMX_SUBVENDOR || 4271 subvendor == ASUS_A8NVMCSM_SUBVENDOR) { 4272 /* nid 28 is mic, nid 29 is line-in */ 4273 w = hdac_widget_get(devinfo, 15); 4274 if (w != NULL) 4275 w->selconn = 2; 4276 w = hdac_widget_get(devinfo, 16); 4277 if (w != NULL) 4278 w->selconn = 1; 4279 } 4280 break; 4281 case HDA_CODEC_AD1988: 4282 case HDA_CODEC_AD1988B: 4283 /*w = hdac_widget_get(devinfo, 12); 4284 if (w != NULL) { 4285 w->selconn = 1; 4286 w->pflags |= HDA_ADC_LOCKED; 4287 } 4288 w = hdac_widget_get(devinfo, 13); 4289 if (w != NULL) { 4290 w->selconn = 4; 4291 w->pflags |= HDA_ADC_LOCKED; 4292 } 4293 w = hdac_widget_get(devinfo, 14); 4294 if (w != NULL) { 4295 w->selconn = 2; 4296 w->pflags |= HDA_ADC_LOCKED; 4297 }*/ 4298 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4299 if (ctl != NULL) { 4300 ctl->ossmask = SOUND_MASK_IGAIN; 4301 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4302 } 4303 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4304 if (ctl != NULL) { 4305 ctl->ossmask = SOUND_MASK_IGAIN; 4306 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4307 } 4308 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4309 if (ctl != NULL) { 4310 ctl->ossmask = SOUND_MASK_IGAIN; 4311 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4312 } 4313 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4314 if (ctl != NULL) { 4315 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4316 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4317 } 4318 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4319 if (ctl != NULL) { 4320 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4321 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4322 } 4323 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4324 if (ctl != NULL) { 4325 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4326 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4327 } 4328 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4329 if (ctl != NULL) { 4330 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4331 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4332 } 4333 break; 4334 case HDA_CODEC_STAC9221: 4335 /* 4336 * Dell XPS M1210 need all DACs for each output jacks 4337 */ 4338 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4339 break; 4340 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4341 w = hdac_widget_get(devinfo, i); 4342 if (w == NULL || w->enable == 0) 4343 continue; 4344 if (w->type != 4345 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4346 continue; 4347 if (w->nid != 2) 4348 w->enable = 0; 4349 } 4350 break; 4351 case HDA_CODEC_STAC9221D: 4352 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4353 w = hdac_widget_get(devinfo, i); 4354 if (w == NULL || w->enable == 0) 4355 continue; 4356 if (w->type == 4357 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4358 w->nid != 6) 4359 w->enable = 0; 4360 4361 } 4362 break; 4363 case HDA_CODEC_STAC9227: 4364 w = hdac_widget_get(devinfo, 8); 4365 if (w != NULL) 4366 w->enable = 0; 4367 w = hdac_widget_get(devinfo, 9); 4368 if (w != NULL) 4369 w->enable = 0; 4370 break; 4371 case HDA_CODEC_CXWAIKIKI: 4372 if (subvendor == HP_DV5000_SUBVENDOR) { 4373 w = hdac_widget_get(devinfo, 27); 4374 if (w != NULL) 4375 w->enable = 0; 4376 } 4377 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4378 if (ctl != NULL) 4379 ctl->ossmask = SOUND_MASK_SKIP; 4380 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4381 if (ctl != NULL && ctl->childwidget != NULL && 4382 ctl->childwidget->enable != 0) { 4383 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4384 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4385 } 4386 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4387 if (ctl != NULL && ctl->childwidget != NULL && 4388 ctl->childwidget->enable != 0) { 4389 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4390 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4391 } 4392 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4393 if (ctl != NULL && ctl->childwidget != NULL && 4394 ctl->childwidget->enable != 0) { 4395 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4396 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4397 } 4398 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4399 if (ctl != NULL) { 4400 ctl->ossmask = SOUND_MASK_SKIP; 4401 /* XXX mixer \=rec mic broken.. why?!? */ 4402 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4403 } 4404 break; 4405 default: 4406 break; 4407 } 4408} 4409 4410static int 4411hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4412{ 4413 int *dev = &devinfo->function.audio.ossidx; 4414 4415 while (*dev < SOUND_MIXER_NRDEVICES) { 4416 switch (*dev) { 4417 case SOUND_MIXER_VOLUME: 4418 case SOUND_MIXER_BASS: 4419 case SOUND_MIXER_TREBLE: 4420 case SOUND_MIXER_PCM: 4421 case SOUND_MIXER_SPEAKER: 4422 case SOUND_MIXER_LINE: 4423 case SOUND_MIXER_MIC: 4424 case SOUND_MIXER_CD: 4425 case SOUND_MIXER_RECLEV: 4426 case SOUND_MIXER_IGAIN: 4427 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4428 (*dev)++; 4429 break; 4430 default: 4431 return (*dev)++; 4432 break; 4433 } 4434 } 4435 4436 return (-1); 4437} 4438 4439static int 4440hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4441{ 4442 struct hdac_widget *w; 4443 int i, ret = 0; 4444 4445 if (depth > HDA_PARSE_MAXDEPTH) 4446 return (0); 4447 w = hdac_widget_get(devinfo, nid); 4448 if (w == NULL || w->enable == 0) 4449 return (0); 4450 switch (w->type) { 4451 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4452 w->pflags |= HDA_DAC_PATH; 4453 ret = 1; 4454 break; 4455 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4456 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4457 for (i = 0; i < w->nconns; i++) { 4458 if (hdac_widget_find_dac_path(devinfo, 4459 w->conns[i], depth + 1) != 0) { 4460 if (w->selconn == -1) 4461 w->selconn = i; 4462 ret = 1; 4463 w->pflags |= HDA_DAC_PATH; 4464 } 4465 } 4466 break; 4467 default: 4468 break; 4469 } 4470 return (ret); 4471} 4472 4473static int 4474hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4475{ 4476 struct hdac_widget *w; 4477 int i, conndev, ret = 0; 4478 4479 if (depth > HDA_PARSE_MAXDEPTH) 4480 return (0); 4481 w = hdac_widget_get(devinfo, nid); 4482 if (w == NULL || w->enable == 0) 4483 return (0); 4484 switch (w->type) { 4485 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4486 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4487 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4488 for (i = 0; i < w->nconns; i++) { 4489 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4490 depth + 1) != 0) { 4491 if (w->selconn == -1) 4492 w->selconn = i; 4493 w->pflags |= HDA_ADC_PATH; 4494 ret = 1; 4495 } 4496 } 4497 break; 4498 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4499 conndev = w->wclass.pin.config & 4500 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4501 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4502 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4503 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4504 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4505 w->pflags |= HDA_ADC_PATH; 4506 ret = 1; 4507 } 4508 break; 4509 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4510 if (w->pflags & HDA_DAC_PATH) { 4511 w->pflags |= HDA_ADC_PATH; 4512 ret = 1; 4513 } 4514 break;*/ 4515 default: 4516 break; 4517 } 4518 return (ret); 4519} 4520 4521static uint32_t 4522hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4523 nid_t nid, nid_t pnid, int index, int depth) 4524{ 4525 struct hdac_widget *w, *pw; 4526 struct hdac_audio_ctl *ctl; 4527 uint32_t fl = 0; 4528 int i, ossdev, conndev, strategy; 4529 4530 if (depth > HDA_PARSE_MAXDEPTH) 4531 return (0); 4532 4533 w = hdac_widget_get(devinfo, nid); 4534 if (w == NULL || w->enable == 0) 4535 return (0); 4536 4537 pw = hdac_widget_get(devinfo, pnid); 4538 strategy = devinfo->function.audio.parsing_strategy; 4539 4540 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4541 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4542 for (i = 0; i < w->nconns; i++) { 4543 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4544 w->nid, i, depth + 1); 4545 } 4546 w->ctlflags |= fl; 4547 return (fl); 4548 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4549 (w->pflags & HDA_DAC_PATH)) { 4550 i = 0; 4551 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4552 if (ctl->enable == 0 || ctl->widget == NULL) 4553 continue; 4554 /* XXX This should be compressed! */ 4555 if (((ctl->widget->nid == w->nid) || 4556 (ctl->widget->nid == pnid && ctl->index == index && 4557 (ctl->dir & HDA_CTL_IN)) || 4558 (ctl->widget->nid == pnid && pw != NULL && 4559 pw->type == 4560 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4561 (pw->nconns < 2 || pw->selconn == index || 4562 pw->selconn == -1) && 4563 (ctl->dir & HDA_CTL_OUT)) || 4564 (strategy == HDA_PARSE_DIRECT && 4565 ctl->widget->nid == w->nid)) && 4566 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4567 /*if (pw != NULL && pw->selconn == -1) 4568 pw->selconn = index; 4569 fl |= SOUND_MASK_VOLUME; 4570 fl |= SOUND_MASK_PCM; 4571 ctl->ossmask |= SOUND_MASK_VOLUME; 4572 ctl->ossmask |= SOUND_MASK_PCM; 4573 ctl->ossdev = SOUND_MIXER_PCM;*/ 4574 if (!(w->ctlflags & SOUND_MASK_PCM) || 4575 (pw != NULL && 4576 !(pw->ctlflags & SOUND_MASK_PCM))) { 4577 fl |= SOUND_MASK_VOLUME; 4578 fl |= SOUND_MASK_PCM; 4579 ctl->ossmask |= SOUND_MASK_VOLUME; 4580 ctl->ossmask |= SOUND_MASK_PCM; 4581 ctl->ossdev = SOUND_MIXER_PCM; 4582 w->ctlflags |= SOUND_MASK_VOLUME; 4583 w->ctlflags |= SOUND_MASK_PCM; 4584 if (pw != NULL) { 4585 if (pw->selconn == -1) 4586 pw->selconn = index; 4587 pw->ctlflags |= 4588 SOUND_MASK_VOLUME; 4589 pw->ctlflags |= 4590 SOUND_MASK_PCM; 4591 } 4592 } 4593 } 4594 } 4595 w->ctlflags |= fl; 4596 return (fl); 4597 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4598 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4599 (w->pflags & HDA_ADC_PATH)) { 4600 conndev = w->wclass.pin.config & 4601 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4602 i = 0; 4603 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4604 if (ctl->enable == 0 || ctl->widget == NULL) 4605 continue; 4606 /* XXX This should be compressed! */ 4607 if (((ctl->widget->nid == pnid && ctl->index == index && 4608 (ctl->dir & HDA_CTL_IN)) || 4609 (ctl->widget->nid == pnid && pw != NULL && 4610 pw->type == 4611 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4612 (pw->nconns < 2 || pw->selconn == index || 4613 pw->selconn == -1) && 4614 (ctl->dir & HDA_CTL_OUT)) || 4615 (strategy == HDA_PARSE_DIRECT && 4616 ctl->widget->nid == w->nid)) && 4617 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4618 if (pw != NULL && pw->selconn == -1) 4619 pw->selconn = index; 4620 ossdev = 0; 4621 switch (conndev) { 4622 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4623 ossdev = SOUND_MIXER_MIC; 4624 break; 4625 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4626 ossdev = SOUND_MIXER_LINE; 4627 break; 4628 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4629 ossdev = SOUND_MIXER_CD; 4630 break; 4631 default: 4632 ossdev = 4633 hdac_audio_ctl_ossmixer_getnextdev( 4634 devinfo); 4635 if (ossdev < 0) 4636 ossdev = 0; 4637 break; 4638 } 4639 if (strategy == HDA_PARSE_MIXER) { 4640 fl |= SOUND_MASK_VOLUME; 4641 ctl->ossmask |= SOUND_MASK_VOLUME; 4642 } 4643 fl |= 1 << ossdev; 4644 ctl->ossmask |= 1 << ossdev; 4645 ctl->ossdev = ossdev; 4646 } 4647 } 4648 w->ctlflags |= fl; 4649 return (fl); 4650 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4651 i = 0; 4652 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4653 if (ctl->enable == 0 || ctl->widget == NULL) 4654 continue; 4655 /* XXX This should be compressed! */ 4656 if (((ctl->widget->nid == pnid && ctl->index == index && 4657 (ctl->dir & HDA_CTL_IN)) || 4658 (ctl->widget->nid == pnid && pw != NULL && 4659 pw->type == 4660 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4661 (pw->nconns < 2 || pw->selconn == index || 4662 pw->selconn == -1) && 4663 (ctl->dir & HDA_CTL_OUT)) || 4664 (strategy == HDA_PARSE_DIRECT && 4665 ctl->widget->nid == w->nid)) && 4666 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4667 if (pw != NULL && pw->selconn == -1) 4668 pw->selconn = index; 4669 fl |= SOUND_MASK_VOLUME; 4670 fl |= SOUND_MASK_SPEAKER; 4671 ctl->ossmask |= SOUND_MASK_VOLUME; 4672 ctl->ossmask |= SOUND_MASK_SPEAKER; 4673 ctl->ossdev = SOUND_MIXER_SPEAKER; 4674 } 4675 } 4676 w->ctlflags |= fl; 4677 return (fl); 4678 } 4679 return (0); 4680} 4681 4682static uint32_t 4683hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4684{ 4685 struct hdac_widget *w, *cw; 4686 struct hdac_audio_ctl *ctl; 4687 uint32_t fl; 4688 int i; 4689 4690 if (depth > HDA_PARSE_MAXDEPTH) 4691 return (0); 4692 4693 w = hdac_widget_get(devinfo, nid); 4694 if (w == NULL || w->enable == 0) 4695 return (0); 4696 /*if (!(w->pflags & HDA_ADC_PATH)) 4697 return (0); 4698 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4699 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4700 return (0);*/ 4701 i = 0; 4702 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4703 if (ctl->enable == 0 || ctl->widget == NULL) 4704 continue; 4705 if (ctl->widget->nid == nid) { 4706 ctl->ossmask |= SOUND_MASK_RECLEV; 4707 w->ctlflags |= SOUND_MASK_RECLEV; 4708 return (SOUND_MASK_RECLEV); 4709 } 4710 } 4711 for (i = 0; i < w->nconns; i++) { 4712 cw = hdac_widget_get(devinfo, w->conns[i]); 4713 if (cw == NULL || cw->enable == 0) 4714 continue; 4715 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4716 continue; 4717 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4718 if (fl != 0) { 4719 cw->ctlflags |= fl; 4720 w->ctlflags |= fl; 4721 return (fl); 4722 } 4723 } 4724 return (0); 4725} 4726 4727static int 4728hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4729{ 4730 struct hdac_widget *w, *cw; 4731 int i, child = 0; 4732 4733 if (depth > HDA_PARSE_MAXDEPTH) 4734 return (0); 4735 4736 w = hdac_widget_get(devinfo, nid); 4737 if (w == NULL || w->enable == 0) 4738 return (0); 4739 /*if (!(w->pflags & HDA_ADC_PATH)) 4740 return (0); 4741 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4742 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4743 return (0);*/ 4744 /* XXX weak! */ 4745 for (i = 0; i < w->nconns; i++) { 4746 cw = hdac_widget_get(devinfo, w->conns[i]); 4747 if (cw == NULL) 4748 continue; 4749 if (++child > 1) { 4750 w->pflags |= HDA_ADC_RECSEL; 4751 return (1); 4752 } 4753 } 4754 for (i = 0; i < w->nconns; i++) { 4755 if (hdac_audio_ctl_recsel_build(devinfo, 4756 w->conns[i], depth + 1) != 0) 4757 return (1); 4758 } 4759 return (0); 4760} 4761 4762static int 4763hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4764{ 4765 struct hdac_widget *w, *cw; 4766 int i, j, conndev, found_dac = 0; 4767 int strategy; 4768 4769 strategy = devinfo->function.audio.parsing_strategy; 4770 4771 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4772 w = hdac_widget_get(devinfo, i); 4773 if (w == NULL || w->enable == 0) 4774 continue; 4775 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4776 continue; 4777 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4778 continue; 4779 conndev = w->wclass.pin.config & 4780 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4781 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4782 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4783 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4784 continue; 4785 for (j = 0; j < w->nconns; j++) { 4786 cw = hdac_widget_get(devinfo, w->conns[j]); 4787 if (cw == NULL || cw->enable == 0) 4788 continue; 4789 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4790 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4791 cw->type == 4792 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4793 continue; 4794 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4795 != 0) { 4796 if (w->selconn == -1) 4797 w->selconn = j; 4798 w->pflags |= HDA_DAC_PATH; 4799 found_dac++; 4800 } 4801 } 4802 } 4803 4804 return (found_dac); 4805} 4806 4807static void 4808hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4809{ 4810 struct hdac_widget *w; 4811 struct hdac_audio_ctl *ctl; 4812 int i, j, dacs, strategy; 4813 4814 /* Construct DAC path */ 4815 strategy = HDA_PARSE_MIXER; 4816 devinfo->function.audio.parsing_strategy = strategy; 4817 HDA_BOOTVERBOSE( 4818 device_printf(devinfo->codec->sc->dev, 4819 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4820 HDA_WIDGET_PARSER_REV); 4821 ); 4822 dacs = hdac_audio_build_tree_strategy(devinfo); 4823 if (dacs == 0) { 4824 HDA_BOOTVERBOSE( 4825 device_printf(devinfo->codec->sc->dev, 4826 "HDA_DEBUG: HWiP: 0 DAC path found! " 4827 "Retrying parser " 4828 "using HDA_PARSE_DIRECT strategy.\n"); 4829 ); 4830 strategy = HDA_PARSE_DIRECT; 4831 devinfo->function.audio.parsing_strategy = strategy; 4832 dacs = hdac_audio_build_tree_strategy(devinfo); 4833 } 4834 4835 HDA_BOOTVERBOSE( 4836 device_printf(devinfo->codec->sc->dev, 4837 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4838 "strategy.\n", 4839 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4840 ); 4841 4842 /* Construct ADC path */ 4843 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4844 w = hdac_widget_get(devinfo, i); 4845 if (w == NULL || w->enable == 0) 4846 continue; 4847 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4848 continue; 4849 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4850 } 4851 4852 /* Output mixers */ 4853 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4854 w = hdac_widget_get(devinfo, i); 4855 if (w == NULL || w->enable == 0) 4856 continue; 4857 if ((strategy == HDA_PARSE_MIXER && 4858 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4859 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4860 && (w->pflags & HDA_DAC_PATH)) || 4861 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4862 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4863 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4864 w->nid, devinfo->startnode - 1, 0, 0); 4865 } else if (w->type == 4866 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4867 j = 0; 4868 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4869 NULL) { 4870 if (ctl->enable == 0 || ctl->widget == NULL) 4871 continue; 4872 if (ctl->widget->nid != w->nid) 4873 continue; 4874 ctl->ossmask |= SOUND_MASK_VOLUME; 4875 ctl->ossmask |= SOUND_MASK_SPEAKER; 4876 ctl->ossdev = SOUND_MIXER_SPEAKER; 4877 w->ctlflags |= SOUND_MASK_VOLUME; 4878 w->ctlflags |= SOUND_MASK_SPEAKER; 4879 } 4880 } 4881 } 4882 4883 /* Input mixers (rec) */ 4884 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4885 w = hdac_widget_get(devinfo, i); 4886 if (w == NULL || w->enable == 0) 4887 continue; 4888 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4889 w->pflags & HDA_ADC_PATH)) 4890 continue; 4891 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4892 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4893 } 4894} 4895 4896#define HDA_COMMIT_CONN (1 << 0) 4897#define HDA_COMMIT_CTRL (1 << 1) 4898#define HDA_COMMIT_EAPD (1 << 2) 4899#define HDA_COMMIT_GPIO (1 << 3) 4900#define HDA_COMMIT_MISC (1 << 4) 4901#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4902 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 4903 4904static void 4905hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4906{ 4907 struct hdac_softc *sc = devinfo->codec->sc; 4908 struct hdac_widget *w; 4909 nid_t cad; 4910 int i; 4911 4912 if (!(cfl & HDA_COMMIT_ALL)) 4913 return; 4914 4915 cad = devinfo->codec->cad; 4916 4917 if ((cfl & HDA_COMMIT_MISC)) { 4918 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4919 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4920 0x7e7, 0), cad); 4921 } 4922 4923 if (cfl & HDA_COMMIT_GPIO) { 4924 uint32_t gdata, gmask, gdir; 4925 int commitgpio, numgpio; 4926 4927 gdata = 0; 4928 gmask = 0; 4929 gdir = 0; 4930 commitgpio = 0; 4931 4932 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 4933 devinfo->function.audio.gpio); 4934 4935 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4936 commitgpio = (numgpio > 0) ? 1 : 0; 4937 else { 4938 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 4939 if (!(devinfo->function.audio.quirks & 4940 (1 << i))) 4941 continue; 4942 if (commitgpio == 0) { 4943 commitgpio = 1; 4944 HDA_BOOTVERBOSE( 4945 gdata = hdac_command(sc, 4946 HDA_CMD_GET_GPIO_DATA(cad, 4947 devinfo->nid), cad); 4948 gmask = hdac_command(sc, 4949 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4950 devinfo->nid), cad); 4951 gdir = hdac_command(sc, 4952 HDA_CMD_GET_GPIO_DIRECTION(cad, 4953 devinfo->nid), cad); 4954 device_printf(sc->dev, 4955 "GPIO init: data=0x%08x " 4956 "mask=0x%08x dir=0x%08x\n", 4957 gdata, gmask, gdir); 4958 gdata = 0; 4959 gmask = 0; 4960 gdir = 0; 4961 ); 4962 } 4963 gdata |= 1 << i; 4964 gmask |= 1 << i; 4965 gdir |= 1 << i; 4966 } 4967 } 4968 4969 if (commitgpio != 0) { 4970 HDA_BOOTVERBOSE( 4971 device_printf(sc->dev, 4972 "GPIO commit: data=0x%08x mask=0x%08x " 4973 "dir=0x%08x\n", 4974 gdata, gmask, gdir); 4975 ); 4976 hdac_command(sc, 4977 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4978 gmask), cad); 4979 hdac_command(sc, 4980 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4981 gdir), cad); 4982 hdac_command(sc, 4983 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4984 gdata), cad); 4985 } 4986 } 4987 4988 for (i = 0; i < devinfo->nodecnt; i++) { 4989 w = &devinfo->widget[i]; 4990 if (w == NULL || w->enable == 0) 4991 continue; 4992 if (cfl & HDA_COMMIT_CONN) { 4993 if (w->selconn == -1) 4994 w->selconn = 0; 4995 if (w->nconns > 0) 4996 hdac_widget_connection_select(w, w->selconn); 4997 } 4998 if ((cfl & HDA_COMMIT_CTRL) && 4999 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5000 uint32_t pincap; 5001 5002 pincap = w->wclass.pin.cap; 5003 5004 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 5005 (HDA_DAC_PATH | HDA_ADC_PATH)) 5006 device_printf(sc->dev, "WARNING: node %d " 5007 "participate both for DAC/ADC!\n", w->nid); 5008 if (w->pflags & HDA_DAC_PATH) { 5009 w->wclass.pin.ctrl &= 5010 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 5011 if ((w->wclass.pin.config & 5012 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 5013 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 5014 w->wclass.pin.ctrl &= 5015 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 5016 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 5017 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5018 w->wclass.pin.ctrl |= 5019 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5020 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5021 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 5022 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5023 w->wclass.pin.ctrl |= 5024 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5025 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5026 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 5027 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5028 w->wclass.pin.ctrl |= 5029 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5030 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5031 } else if (w->pflags & HDA_ADC_PATH) { 5032 w->wclass.pin.ctrl &= 5033 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5034 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 5035 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 5036 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5037 w->wclass.pin.ctrl |= 5038 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5039 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 5040 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 5041 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5042 w->wclass.pin.ctrl |= 5043 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5044 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 5045 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 5046 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5047 w->wclass.pin.ctrl |= 5048 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5049 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5050 } else 5051 w->wclass.pin.ctrl &= ~( 5052 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5053 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5054 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5055 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5056 hdac_command(sc, 5057 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5058 w->wclass.pin.ctrl), cad); 5059 } 5060 if ((cfl & HDA_COMMIT_EAPD) && 5061 w->param.eapdbtl != HDAC_INVALID) { 5062 uint32_t val; 5063 5064 val = w->param.eapdbtl; 5065 if (devinfo->function.audio.quirks & 5066 HDA_QUIRK_EAPDINV) 5067 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5068 hdac_command(sc, 5069 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5070 val), cad); 5071 5072 } 5073 DELAY(1000); 5074 } 5075} 5076 5077static void 5078hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5079{ 5080 struct hdac_softc *sc = devinfo->codec->sc; 5081 struct hdac_audio_ctl *ctl; 5082 int i; 5083 5084 devinfo->function.audio.mvol = 100 | (100 << 8); 5085 i = 0; 5086 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5087 if (ctl->enable == 0 || ctl->widget == NULL) { 5088 HDA_BOOTVERBOSE( 5089 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5090 i, (ctl->widget != NULL) ? 5091 ctl->widget->nid : -1); 5092 if (ctl->childwidget != NULL) 5093 printf(" childnid=%d", 5094 ctl->childwidget->nid); 5095 if (ctl->widget == NULL) 5096 printf(" NULL WIDGET!"); 5097 printf(" DISABLED\n"); 5098 ); 5099 continue; 5100 } 5101 HDA_BOOTVERBOSE( 5102 if (ctl->ossmask == 0) { 5103 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5104 i, ctl->widget->nid); 5105 if (ctl->childwidget != NULL) 5106 printf(" childnid=%d", 5107 ctl->childwidget->nid); 5108 printf(" Bind to NONE\n"); 5109 } 5110 ); 5111 if (ctl->step > 0) { 5112 ctl->ossval = (ctl->left * 100) / ctl->step; 5113 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5114 } else 5115 ctl->ossval = 0; 5116 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5117 ctl->left, ctl->right); 5118 } 5119} 5120 5121static int 5122hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5123{ 5124 struct hdac_chan *ch; 5125 struct hdac_widget *w; 5126 uint32_t cap, fmtcap, pcmcap, path; 5127 int i, type, ret, max; 5128 5129 if (dir == PCMDIR_PLAY) { 5130 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5131 ch = &devinfo->codec->sc->play; 5132 path = HDA_DAC_PATH; 5133 } else { 5134 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5135 ch = &devinfo->codec->sc->rec; 5136 path = HDA_ADC_PATH; 5137 } 5138 5139 ch->caps = hdac_caps; 5140 ch->caps.fmtlist = ch->fmtlist; 5141 ch->bit16 = 1; 5142 ch->bit32 = 0; 5143 ch->pcmrates[0] = 48000; 5144 ch->pcmrates[1] = 0; 5145 5146 ret = 0; 5147 fmtcap = devinfo->function.audio.supp_stream_formats; 5148 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5149 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5150 5151 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5152 w = hdac_widget_get(devinfo, i); 5153 if (w == NULL || w->enable == 0 || w->type != type || 5154 !(w->pflags & path)) 5155 continue; 5156 cap = w->param.widget_cap; 5157 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5158 continue;*/ 5159 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5160 continue; 5161 cap = w->param.supp_stream_formats; 5162 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5163 } 5164 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5165 }*/ 5166 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5167 continue; 5168 if (ret == 0) { 5169 fmtcap = w->param.supp_stream_formats; 5170 pcmcap = w->param.supp_pcm_size_rate; 5171 } else { 5172 fmtcap &= w->param.supp_stream_formats; 5173 pcmcap &= w->param.supp_pcm_size_rate; 5174 } 5175 ch->io[ret++] = i; 5176 } 5177 ch->io[ret] = -1; 5178 5179 ch->supp_stream_formats = fmtcap; 5180 ch->supp_pcm_size_rate = pcmcap; 5181 5182 /* 5183 * 8bit = 0 5184 * 16bit = 1 5185 * 20bit = 2 5186 * 24bit = 3 5187 * 32bit = 4 5188 */ 5189 if (ret > 0) { 5190 cap = pcmcap; 5191 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5192 ch->bit16 = 1; 5193 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5194 ch->bit16 = 0; 5195 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5196 ch->bit32 = 4; 5197 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5198 ch->bit32 = 3; 5199 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5200 ch->bit32 = 2; 5201 i = 0; 5202 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5203 ch->fmtlist[i++] = AFMT_S16_LE; 5204 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5205 if (ch->bit32 > 0) { 5206 if (!(devinfo->function.audio.quirks & 5207 HDA_QUIRK_FORCESTEREO)) 5208 ch->fmtlist[i++] = AFMT_S32_LE; 5209 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5210 } 5211 ch->fmtlist[i] = 0; 5212 i = 0; 5213 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5214 ch->pcmrates[i++] = 8000; 5215 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5216 ch->pcmrates[i++] = 11025; 5217 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5218 ch->pcmrates[i++] = 16000; 5219 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5220 ch->pcmrates[i++] = 22050; 5221 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5222 ch->pcmrates[i++] = 32000; 5223 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5224 ch->pcmrates[i++] = 44100; 5225 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5226 ch->pcmrates[i++] = 48000; 5227 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5228 ch->pcmrates[i++] = 88200; 5229 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5230 ch->pcmrates[i++] = 96000; 5231 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5232 ch->pcmrates[i++] = 176400; 5233 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5234 ch->pcmrates[i++] = 192000; 5235 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5236 ch->pcmrates[i] = 0; 5237 if (i > 0) { 5238 ch->caps.minspeed = ch->pcmrates[0]; 5239 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5240 } 5241 } 5242 5243 return (ret); 5244} 5245 5246static void 5247hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5248{ 5249 struct hdac_audio_ctl *ctl; 5250 struct hdac_softc *sc = devinfo->codec->sc; 5251 int i; 5252 uint32_t fl = 0; 5253 5254 5255 if (flag == 0) { 5256 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5257 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5258 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5259 } 5260 5261 i = 0; 5262 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5263 if (ctl->enable == 0 || ctl->widget == NULL || 5264 ctl->widget->enable == 0 || (ctl->ossmask & 5265 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5266 continue; 5267 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5268 (flag != 0 && (ctl->ossmask & flag))) { 5269 if (banner != NULL) { 5270 device_printf(sc->dev, "\n"); 5271 device_printf(sc->dev, "%s\n", banner); 5272 } 5273 goto hdac_ctl_dump_it_all; 5274 } 5275 } 5276 5277 return; 5278 5279hdac_ctl_dump_it_all: 5280 i = 0; 5281 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5282 if (ctl->enable == 0 || ctl->widget == NULL || 5283 ctl->widget->enable == 0) 5284 continue; 5285 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5286 (flag != 0 && (ctl->ossmask & flag)))) 5287 continue; 5288 if (flag == 0) { 5289 device_printf(sc->dev, "\n"); 5290 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5291 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5292 } 5293 device_printf(sc->dev, " |\n"); 5294 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5295 ctl->widget->nid, ctl->index); 5296 if (ctl->childwidget != NULL) 5297 printf("(nid: %2d) ", ctl->childwidget->nid); 5298 else 5299 printf(" "); 5300 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5301 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5302 ctl->ossmask); 5303 } 5304} 5305 5306static void 5307hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5308{ 5309 uint32_t cap; 5310 5311 cap = fcap; 5312 if (cap != 0) { 5313 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5314 device_printf(sc->dev, " Format:"); 5315 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5316 printf(" AC3"); 5317 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5318 printf(" FLOAT32"); 5319 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5320 printf(" PCM"); 5321 printf("\n"); 5322 } 5323 cap = pcmcap; 5324 if (cap != 0) { 5325 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5326 device_printf(sc->dev, " PCM size:"); 5327 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5328 printf(" 8"); 5329 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5330 printf(" 16"); 5331 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5332 printf(" 20"); 5333 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5334 printf(" 24"); 5335 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5336 printf(" 32"); 5337 printf("\n"); 5338 device_printf(sc->dev, " PCM rate:"); 5339 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5340 printf(" 8"); 5341 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5342 printf(" 11"); 5343 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5344 printf(" 16"); 5345 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5346 printf(" 22"); 5347 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5348 printf(" 32"); 5349 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5350 printf(" 44"); 5351 printf(" 48"); 5352 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5353 printf(" 88"); 5354 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5355 printf(" 96"); 5356 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5357 printf(" 176"); 5358 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5359 printf(" 192"); 5360 printf("\n"); 5361 } 5362} 5363 5364static void 5365hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5366{ 5367 uint32_t pincap, wcap; 5368 5369 pincap = w->wclass.pin.cap; 5370 wcap = w->param.widget_cap; 5371 5372 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5373 device_printf(sc->dev, " "); 5374 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5375 printf(" ISC"); 5376 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5377 printf(" TRQD"); 5378 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5379 printf(" PDC"); 5380 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5381 printf(" HP"); 5382 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5383 printf(" OUT"); 5384 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5385 printf(" IN"); 5386 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5387 printf(" BAL"); 5388 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5389 printf(" VREF["); 5390 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5391 printf(" 50"); 5392 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5393 printf(" 80"); 5394 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5395 printf(" 100"); 5396 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5397 printf(" GROUND"); 5398 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5399 printf(" HIZ"); 5400 printf(" ]"); 5401 } 5402 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5403 printf(" EAPD"); 5404 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5405 printf(" : UNSOL"); 5406 printf("\n"); 5407 device_printf(sc->dev, " Pin config: 0x%08x\n", 5408 w->wclass.pin.config); 5409 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5410 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5411 printf(" HP"); 5412 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5413 printf(" IN"); 5414 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5415 printf(" OUT"); 5416 printf("\n"); 5417} 5418 5419static void 5420hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5421{ 5422 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5423 device_printf(sc->dev, " " 5424 "mute=%d step=%d size=%d offset=%d\n", 5425 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5426 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5427 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5428 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5429} 5430 5431static void 5432hdac_dump_nodes(struct hdac_devinfo *devinfo) 5433{ 5434 struct hdac_softc *sc = devinfo->codec->sc; 5435 struct hdac_widget *w, *cw; 5436 int i, j; 5437 5438 device_printf(sc->dev, "\n"); 5439 device_printf(sc->dev, "Default Parameter\n"); 5440 device_printf(sc->dev, "-----------------\n"); 5441 hdac_dump_audio_formats(sc, 5442 devinfo->function.audio.supp_stream_formats, 5443 devinfo->function.audio.supp_pcm_size_rate); 5444 device_printf(sc->dev, " IN amp: 0x%08x\n", 5445 devinfo->function.audio.inamp_cap); 5446 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5447 devinfo->function.audio.outamp_cap); 5448 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5449 w = hdac_widget_get(devinfo, i); 5450 if (w == NULL) { 5451 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5452 continue; 5453 } 5454 device_printf(sc->dev, "\n"); 5455 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5456 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5457 "DIGITAL" : "ANALOG", 5458 (w->enable == 0) ? " [DISABLED]" : ""); 5459 device_printf(sc->dev, " name: %s\n", w->name); 5460 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5461 w->param.widget_cap); 5462 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5463 w->pflags); 5464 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5465 w->ctlflags); 5466 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5467 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5468 hdac_dump_audio_formats(sc, 5469 w->param.supp_stream_formats, 5470 w->param.supp_pcm_size_rate); 5471 } else if (w->type == 5472 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5473 hdac_dump_pin(sc, w); 5474 if (w->param.eapdbtl != HDAC_INVALID) 5475 device_printf(sc->dev, " EAPD: 0x%08x\n", 5476 w->param.eapdbtl); 5477 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5478 w->param.outamp_cap != 0) 5479 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5480 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5481 w->param.inamp_cap != 0) 5482 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5483 device_printf(sc->dev, " connections: %d\n", w->nconns); 5484 for (j = 0; j < w->nconns; j++) { 5485 cw = hdac_widget_get(devinfo, w->conns[j]); 5486 device_printf(sc->dev, " |\n"); 5487 device_printf(sc->dev, " + <- nid=%d [%s]", 5488 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5489 if (cw == NULL) 5490 printf(" [UNKNOWN]"); 5491 else if (cw->enable == 0) 5492 printf(" [DISABLED]"); 5493 if (w->nconns > 1 && w->selconn == j && w->type != 5494 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5495 printf(" (selected)"); 5496 printf("\n"); 5497 } 5498 } 5499 5500} 5501 5502static int 5503hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5504{ 5505 struct hdac_widget *w, *cw; 5506 struct hdac_softc *sc = devinfo->codec->sc; 5507 int i; 5508 5509 if (depth > HDA_PARSE_MAXDEPTH) 5510 return (0); 5511 5512 w = hdac_widget_get(devinfo, nid); 5513 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5514 return (0); 5515 5516 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5517 device_printf(sc->dev, "\n"); 5518 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5519 device_printf(sc->dev, " ^\n"); 5520 device_printf(sc->dev, " |\n"); 5521 device_printf(sc->dev, " +-----<------+\n"); 5522 } else { 5523 device_printf(sc->dev, " ^\n"); 5524 device_printf(sc->dev, " |\n"); 5525 device_printf(sc->dev, " "); 5526 printf(" nid=%d [%s]\n", w->nid, w->name); 5527 } 5528 5529 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5530 return (1); 5531 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5532 for (i = 0; i < w->nconns; i++) { 5533 cw = hdac_widget_get(devinfo, w->conns[i]); 5534 if (cw == NULL || cw->enable == 0 || cw->type == 5535 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5536 continue; 5537 if (hdac_dump_dac_internal(devinfo, cw->nid, 5538 depth + 1) != 0) 5539 return (1); 5540 } 5541 } else if ((w->type == 5542 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5543 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5544 w->selconn > -1 && w->selconn < w->nconns) { 5545 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5546 depth + 1) != 0) 5547 return (1); 5548 } 5549 5550 return (0); 5551} 5552 5553static void 5554hdac_dump_dac(struct hdac_devinfo *devinfo) 5555{ 5556 struct hdac_widget *w; 5557 struct hdac_softc *sc = devinfo->codec->sc; 5558 int i, printed = 0; 5559 5560 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5561 w = hdac_widget_get(devinfo, i); 5562 if (w == NULL || w->enable == 0) 5563 continue; 5564 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5565 !(w->pflags & HDA_DAC_PATH)) 5566 continue; 5567 if (printed == 0) { 5568 printed = 1; 5569 device_printf(sc->dev, "\n"); 5570 device_printf(sc->dev, "Playback path:\n"); 5571 } 5572 hdac_dump_dac_internal(devinfo, w->nid, 0); 5573 } 5574} 5575 5576static void 5577hdac_dump_adc(struct hdac_devinfo *devinfo) 5578{ 5579 struct hdac_widget *w, *cw; 5580 struct hdac_softc *sc = devinfo->codec->sc; 5581 int i, j; 5582 int printed = 0; 5583 char ossdevs[256]; 5584 5585 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5586 w = hdac_widget_get(devinfo, i); 5587 if (w == NULL || w->enable == 0) 5588 continue; 5589 if (!(w->pflags & HDA_ADC_RECSEL)) 5590 continue; 5591 if (printed == 0) { 5592 printed = 1; 5593 device_printf(sc->dev, "\n"); 5594 device_printf(sc->dev, "Recording sources:\n"); 5595 } 5596 device_printf(sc->dev, "\n"); 5597 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5598 for (j = 0; j < w->nconns; j++) { 5599 cw = hdac_widget_get(devinfo, w->conns[j]); 5600 if (cw == NULL || cw->enable == 0) 5601 continue; 5602 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5603 ossdevs, sizeof(ossdevs)); 5604 device_printf(sc->dev, " |\n"); 5605 device_printf(sc->dev, " + <- nid=%d [%s]", 5606 cw->nid, cw->name); 5607 if (strlen(ossdevs) > 0) { 5608 printf(" [recsrc: %s]", ossdevs); 5609 } 5610 printf("\n"); 5611 } 5612 } 5613} 5614 5615static void 5616hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5617{ 5618 nid_t *nids; 5619 5620 if (pcnt > 0) { 5621 device_printf(sc->dev, "\n"); 5622 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5623 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5624 sc->play.supp_pcm_size_rate); 5625 device_printf(sc->dev, " DAC:"); 5626 for (nids = sc->play.io; *nids != -1; nids++) 5627 printf(" %d", *nids); 5628 printf("\n"); 5629 } 5630 5631 if (rcnt > 0) { 5632 device_printf(sc->dev, "\n"); 5633 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5634 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5635 sc->rec.supp_pcm_size_rate); 5636 device_printf(sc->dev, " ADC:"); 5637 for (nids = sc->rec.io; *nids != -1; nids++) 5638 printf(" %d", *nids); 5639 printf("\n"); 5640 } 5641} 5642 5643static void 5644hdac_release_resources(struct hdac_softc *sc) 5645{ 5646 struct hdac_devinfo *devinfo = NULL; 5647 device_t *devlist = NULL; 5648 int i, devcount; 5649 5650 if (sc == NULL) 5651 return; 5652 5653 hdac_lock(sc); 5654 sc->polling = 0; 5655 sc->poll_ival = 0; 5656 callout_stop(&sc->poll_hda); 5657 callout_stop(&sc->poll_hdac); 5658 callout_stop(&sc->poll_jack); 5659 hdac_reset(sc); 5660 hdac_unlock(sc); 5661 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5662 callout_drain(&sc->poll_hda); 5663 callout_drain(&sc->poll_hdac); 5664 callout_drain(&sc->poll_jack); 5665 5666 hdac_irq_free(sc); 5667 5668 device_get_children(sc->dev, &devlist, &devcount); 5669 for (i = 0; devlist != NULL && i < devcount; i++) { 5670 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5671 if (devinfo == NULL) 5672 continue; 5673 if (devinfo->widget != NULL) 5674 free(devinfo->widget, M_HDAC); 5675 if (devinfo->node_type == 5676 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5677 devinfo->function.audio.ctl != NULL) 5678 free(devinfo->function.audio.ctl, M_HDAC); 5679 free(devinfo, M_HDAC); 5680 device_delete_child(sc->dev, devlist[i]); 5681 } 5682 if (devlist != NULL) 5683 free(devlist, M_TEMP); 5684 5685 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5686 if (sc->codecs[i] != NULL) 5687 free(sc->codecs[i], M_HDAC); 5688 sc->codecs[i] = NULL; 5689 } 5690 5691 hdac_dma_free(sc, &sc->pos_dma); 5692 hdac_dma_free(sc, &sc->rirb_dma); 5693 hdac_dma_free(sc, &sc->corb_dma); 5694 if (sc->play.blkcnt > 0) 5695 hdac_dma_free(sc, &sc->play.bdl_dma); 5696 if (sc->rec.blkcnt > 0) 5697 hdac_dma_free(sc, &sc->rec.bdl_dma); 5698 if (sc->chan_dmat != NULL) { 5699 bus_dma_tag_destroy(sc->chan_dmat); 5700 sc->chan_dmat = NULL; 5701 } 5702 hdac_mem_free(sc); 5703 snd_mtxfree(sc->lock); 5704 free(sc, M_DEVBUF); 5705} 5706 5707/* This function surely going to make its way into upper level someday. */ 5708static void 5709hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5710{ 5711 const char *res = NULL; 5712 int i = 0, j, k, len, inv; 5713 5714 if (on != NULL) 5715 *on = 0; 5716 if (off != NULL) 5717 *off = 0; 5718 if (sc == NULL) 5719 return; 5720 if (resource_string_value(device_get_name(sc->dev), 5721 device_get_unit(sc->dev), "config", &res) != 0) 5722 return; 5723 if (!(res != NULL && strlen(res) > 0)) 5724 return; 5725 HDA_BOOTVERBOSE( 5726 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5727 ); 5728 for (;;) { 5729 while (res[i] != '\0' && 5730 (res[i] == ',' || isspace(res[i]) != 0)) 5731 i++; 5732 if (res[i] == '\0') { 5733 HDA_BOOTVERBOSE( 5734 printf("\n"); 5735 ); 5736 return; 5737 } 5738 j = i; 5739 while (res[j] != '\0' && 5740 !(res[j] == ',' || isspace(res[j]) != 0)) 5741 j++; 5742 len = j - i; 5743 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5744 inv = 2; 5745 else 5746 inv = 0; 5747 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5748 if (strncmp(res + i + inv, 5749 hdac_quirks_tab[k].key, len - inv) != 0) 5750 continue; 5751 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5752 break; 5753 HDA_BOOTVERBOSE( 5754 printf(" %s%s", (inv != 0) ? "no" : "", 5755 hdac_quirks_tab[k].key); 5756 ); 5757 if (inv == 0 && on != NULL) 5758 *on |= hdac_quirks_tab[k].value; 5759 else if (inv != 0 && off != NULL) 5760 *off |= hdac_quirks_tab[k].value; 5761 break; 5762 } 5763 i = j; 5764 } 5765} 5766 5767#ifdef SND_DYNSYSCTL 5768static int 5769sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5770{ 5771 struct hdac_softc *sc; 5772 struct hdac_devinfo *devinfo; 5773 device_t dev; 5774 uint32_t ctl; 5775 int err, val; 5776 5777 dev = oidp->oid_arg1; 5778 devinfo = pcm_getdevinfo(dev); 5779 if (devinfo == NULL || devinfo->codec == NULL || 5780 devinfo->codec->sc == NULL) 5781 return (EINVAL); 5782 sc = devinfo->codec->sc; 5783 hdac_lock(sc); 5784 val = sc->polling; 5785 hdac_unlock(sc); 5786 err = sysctl_handle_int(oidp, &val, 0, req); 5787 5788 if (err != 0 || req->newptr == NULL) 5789 return (err); 5790 if (val < 0 || val > 1) 5791 return (EINVAL); 5792 5793 hdac_lock(sc); 5794 if (val != sc->polling) { 5795 if (hda_chan_active(sc) != 0) 5796 err = EBUSY; 5797 else if (val == 0) { 5798 callout_stop(&sc->poll_hdac); 5799 hdac_unlock(sc); 5800 callout_drain(&sc->poll_hdac); 5801 hdac_lock(sc); 5802 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5803 sc->rirb_size / 2); 5804 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5805 ctl |= HDAC_RIRBCTL_RINTCTL; 5806 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5807 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5808 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5809 sc->polling = 0; 5810 DELAY(1000); 5811 } else { 5812 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5813 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5814 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5815 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5816 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5817 hdac_unlock(sc); 5818 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 5819 hdac_lock(sc); 5820 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5821 sc); 5822 sc->polling = 1; 5823 DELAY(1000); 5824 } 5825 } 5826 hdac_unlock(sc); 5827 5828 return (err); 5829} 5830 5831static int 5832sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5833{ 5834 struct hdac_softc *sc; 5835 struct hdac_devinfo *devinfo; 5836 device_t dev; 5837 int err, val; 5838 5839 dev = oidp->oid_arg1; 5840 devinfo = pcm_getdevinfo(dev); 5841 if (devinfo == NULL || devinfo->codec == NULL || 5842 devinfo->codec->sc == NULL) 5843 return (EINVAL); 5844 sc = devinfo->codec->sc; 5845 hdac_lock(sc); 5846 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5847 hdac_unlock(sc); 5848 err = sysctl_handle_int(oidp, &val, 0, req); 5849 5850 if (err != 0 || req->newptr == NULL) 5851 return (err); 5852 5853 if (val < 1) 5854 val = 1; 5855 if (val > 5000) 5856 val = 5000; 5857 val = ((uint64_t)val * hz) / 1000; 5858 if (val < 1) 5859 val = 1; 5860 if (val > (hz * 5)) 5861 val = hz * 5; 5862 5863 hdac_lock(sc); 5864 sc->poll_ival = val; 5865 hdac_unlock(sc); 5866 5867 return (err); 5868} 5869 5870#ifdef SND_DEBUG 5871static int 5872sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 5873{ 5874 struct hdac_softc *sc; 5875 struct hdac_devinfo *devinfo; 5876 struct hdac_widget *w; 5877 device_t dev; 5878 uint32_t res, pincap, timeout; 5879 int i, err, val; 5880 nid_t cad; 5881 5882 dev = oidp->oid_arg1; 5883 devinfo = pcm_getdevinfo(dev); 5884 if (devinfo == NULL || devinfo->codec == NULL || 5885 devinfo->codec->sc == NULL) 5886 return (EINVAL); 5887 val = 0; 5888 err = sysctl_handle_int(oidp, &val, 0, req); 5889 if (err != 0 || req->newptr == NULL || val == 0) 5890 return (err); 5891 sc = devinfo->codec->sc; 5892 cad = devinfo->codec->cad; 5893 hdac_lock(sc); 5894 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 5895 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5896 w = hdac_widget_get(devinfo, i); 5897 if (w == NULL || w->type != 5898 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5899 continue; 5900 pincap = w->wclass.pin.cap; 5901 if ((HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 5902 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) && 5903 HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 5904 timeout = 10000; 5905 hdac_command(sc, 5906 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 5907 do { 5908 res = hdac_command(sc, 5909 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 5910 if (res != 0x7fffffff) 5911 break; 5912 DELAY(10); 5913 } while (--timeout != 0); 5914 } else { 5915 timeout = -1; 5916 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 5917 w->nid), cad); 5918 } 5919 device_printf(dev, 5920 "PIN_SENSE: nid=%-3d timeout=%d res=0x%08x [%s]\n", 5921 w->nid, timeout, res, 5922 (w->enable == 0) ? "DISABLED" : "ENABLED"); 5923 } 5924 device_printf(dev, 5925 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 5926 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 5927 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 5928 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 5929 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 5930 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 5931 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 5932 device_printf(dev, " GPI:"); 5933 res = hdac_command(sc, 5934 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 5935 printf(" data=0x%08x", res); 5936 res = hdac_command(sc, 5937 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 5938 cad); 5939 printf(" wake=0x%08x", res); 5940 res = hdac_command(sc, 5941 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5942 cad); 5943 printf(" unsol=0x%08x", res); 5944 res = hdac_command(sc, 5945 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 5946 printf(" sticky=0x%08x\n", res); 5947 } 5948 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 5949 device_printf(dev, " GPO:"); 5950 res = hdac_command(sc, 5951 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 5952 printf(" data=0x%08x\n", res); 5953 } 5954 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 5955 device_printf(dev, "GPI0:"); 5956 res = hdac_command(sc, 5957 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 5958 printf(" data=0x%08x", res); 5959 res = hdac_command(sc, 5960 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 5961 printf(" enable=0x%08x", res); 5962 res = hdac_command(sc, 5963 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 5964 printf(" direction=0x%08x\n", res); 5965 res = hdac_command(sc, 5966 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 5967 device_printf(dev, " wake=0x%08x", res); 5968 res = hdac_command(sc, 5969 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5970 cad); 5971 printf(" unsol=0x%08x", res); 5972 res = hdac_command(sc, 5973 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 5974 printf(" sticky=0x%08x\n", res); 5975 } 5976 hdac_unlock(sc); 5977 return (0); 5978} 5979#endif 5980#endif 5981 5982static void 5983hdac_attach2(void *arg) 5984{ 5985 struct hdac_softc *sc; 5986 struct hdac_widget *w; 5987 struct hdac_audio_ctl *ctl; 5988 uint32_t quirks_on, quirks_off; 5989 int pcnt, rcnt; 5990 int i; 5991 char status[SND_STATUSLEN]; 5992 device_t *devlist = NULL; 5993 int devcount; 5994 struct hdac_devinfo *devinfo = NULL; 5995 5996 sc = (struct hdac_softc *)arg; 5997 5998 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5999 6000 HDA_BOOTVERBOSE( 6001 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 6002 quirks_on, quirks_off); 6003 ); 6004 6005 hdac_lock(sc); 6006 6007 /* Remove ourselves from the config hooks */ 6008 if (sc->intrhook.ich_func != NULL) { 6009 config_intrhook_disestablish(&sc->intrhook); 6010 sc->intrhook.ich_func = NULL; 6011 } 6012 6013 /* Start the corb and rirb engines */ 6014 HDA_BOOTVERBOSE( 6015 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 6016 ); 6017 hdac_corb_start(sc); 6018 HDA_BOOTVERBOSE( 6019 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 6020 ); 6021 hdac_rirb_start(sc); 6022 6023 HDA_BOOTVERBOSE( 6024 device_printf(sc->dev, 6025 "HDA_DEBUG: Enabling controller interrupt...\n"); 6026 ); 6027 if (sc->polling == 0) 6028 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 6029 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 6030 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 6031 HDAC_GCTL_UNSOL); 6032 6033 DELAY(1000); 6034 6035 HDA_BOOTVERBOSE( 6036 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 6037 ); 6038 hdac_scan_codecs(sc); 6039 6040 device_get_children(sc->dev, &devlist, &devcount); 6041 for (i = 0; devlist != NULL && i < devcount; i++) { 6042 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 6043 if (devinfo != NULL && devinfo->node_type == 6044 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6045 break; 6046 } else 6047 devinfo = NULL; 6048 } 6049 if (devlist != NULL) 6050 free(devlist, M_TEMP); 6051 6052 if (devinfo == NULL) { 6053 hdac_unlock(sc); 6054 device_printf(sc->dev, "Audio Function Group not found!\n"); 6055 hdac_release_resources(sc); 6056 return; 6057 } 6058 6059 HDA_BOOTVERBOSE( 6060 device_printf(sc->dev, 6061 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 6062 devinfo->nid, devinfo->codec->cad); 6063 ); 6064 hdac_audio_parse(devinfo); 6065 HDA_BOOTVERBOSE( 6066 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 6067 ); 6068 hdac_audio_ctl_parse(devinfo); 6069 HDA_BOOTVERBOSE( 6070 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6071 ); 6072 hdac_vendor_patch_parse(devinfo); 6073 if (quirks_on != 0) 6074 devinfo->function.audio.quirks |= quirks_on; 6075 if (quirks_off != 0) 6076 devinfo->function.audio.quirks &= ~quirks_off; 6077 6078 /* XXX Disable all DIGITAL path. */ 6079 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6080 w = hdac_widget_get(devinfo, i); 6081 if (w == NULL) 6082 continue; 6083 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6084 w->enable = 0; 6085 continue; 6086 } 6087 /* XXX Disable useless pin ? */ 6088 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6089 (w->wclass.pin.config & 6090 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6091 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6092 w->enable = 0; 6093 } 6094 i = 0; 6095 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6096 if (ctl->widget == NULL) 6097 continue; 6098 if (ctl->ossmask & SOUND_MASK_DISABLE) 6099 ctl->enable = 0; 6100 w = ctl->widget; 6101 if (w->enable == 0 || 6102 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6103 ctl->enable = 0; 6104 w = ctl->childwidget; 6105 if (w == NULL) 6106 continue; 6107 if (w->enable == 0 || 6108 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6109 ctl->enable = 0; 6110 } 6111 6112 HDA_BOOTVERBOSE( 6113 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6114 ); 6115 hdac_audio_build_tree(devinfo); 6116 6117 i = 0; 6118 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6119 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6120 ctl->ossmask = 0; 6121 } 6122 HDA_BOOTVERBOSE( 6123 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6124 ); 6125 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6126 HDA_BOOTVERBOSE( 6127 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6128 ); 6129 hdac_audio_ctl_commit(devinfo); 6130 6131 HDA_BOOTVERBOSE( 6132 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6133 ); 6134 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6135 HDA_BOOTVERBOSE( 6136 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6137 ); 6138 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6139 6140 hdac_unlock(sc); 6141 HDA_BOOTVERBOSE( 6142 device_printf(sc->dev, 6143 "HDA_DEBUG: OSS mixer initialization...\n"); 6144 ); 6145 6146 /* 6147 * There is no point of return after this. If the driver failed, 6148 * so be it. Let the detach procedure do all the cleanup. 6149 */ 6150 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6151 device_printf(sc->dev, "Can't register mixer\n"); 6152 6153 if (pcnt > 0) 6154 pcnt = 1; 6155 if (rcnt > 0) 6156 rcnt = 1; 6157 6158 HDA_BOOTVERBOSE( 6159 device_printf(sc->dev, 6160 "HDA_DEBUG: Registering PCM channels...\n"); 6161 ); 6162 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6163 device_printf(sc->dev, "Can't register PCM\n"); 6164 6165 sc->registered++; 6166 6167 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6168 hdac_dma_alloc(sc, &sc->pos_dma, 6169 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6170 HDA_BOOTVERBOSE( 6171 device_printf(sc->dev, 6172 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6173 ); 6174 } 6175 6176 for (i = 0; i < pcnt; i++) 6177 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6178 for (i = 0; i < rcnt; i++) 6179 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6180 6181#ifdef SND_DYNSYSCTL 6182 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6183 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6184 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6185 sysctl_hdac_polling, "I", "Enable polling mode"); 6186 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6187 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6188 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6189 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6190 "Controller/Jack Sense polling interval (1-1000 ms)"); 6191#ifdef SND_DEBUG 6192 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6193 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6194 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6195 sysctl_hdac_pindump, "I", "Dump pin states/data"); 6196#endif 6197#endif 6198 6199 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6200 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6201 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6202 pcm_setstatus(sc->dev, status); 6203 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6204 HDA_BOOTVERBOSE( 6205 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6206 hdac_codec_id(devinfo)); 6207 ); 6208 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6209 HDA_DRV_TEST_REV); 6210 6211 HDA_BOOTVERBOSE( 6212 if (devinfo->function.audio.quirks != 0) { 6213 device_printf(sc->dev, "\n"); 6214 device_printf(sc->dev, "HDA config/quirks:"); 6215 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6216 if ((devinfo->function.audio.quirks & 6217 hdac_quirks_tab[i].value) == 6218 hdac_quirks_tab[i].value) 6219 printf(" %s", hdac_quirks_tab[i].key); 6220 } 6221 printf("\n"); 6222 } 6223 device_printf(sc->dev, "\n"); 6224 device_printf(sc->dev, "+-------------------+\n"); 6225 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6226 device_printf(sc->dev, "+-------------------+\n"); 6227 hdac_dump_nodes(devinfo); 6228 device_printf(sc->dev, "\n"); 6229 device_printf(sc->dev, "+------------------------+\n"); 6230 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6231 device_printf(sc->dev, "+------------------------+\n"); 6232 device_printf(sc->dev, "\n"); 6233 i = 0; 6234 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6235 device_printf(sc->dev, "%3d: nid=%d", i, 6236 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6237 if (ctl->childwidget != NULL) 6238 printf(" cnid=%d", ctl->childwidget->nid); 6239 printf(" dir=0x%x index=%d " 6240 "ossmask=0x%08x ossdev=%d%s\n", 6241 ctl->dir, ctl->index, 6242 ctl->ossmask, ctl->ossdev, 6243 (ctl->enable == 0) ? " [DISABLED]" : ""); 6244 } 6245 device_printf(sc->dev, "\n"); 6246 device_printf(sc->dev, "+-----------------------------------+\n"); 6247 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6248 device_printf(sc->dev, "+-----------------------------------+\n"); 6249 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6250 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6251 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6252 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6253 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6254 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6255 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6256 hdac_dump_ctls(devinfo, NULL, 0); 6257 hdac_dump_dac(devinfo); 6258 hdac_dump_adc(devinfo); 6259 device_printf(sc->dev, "\n"); 6260 device_printf(sc->dev, "+--------------------------------------+\n"); 6261 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6262 device_printf(sc->dev, "+--------------------------------------+\n"); 6263 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6264 ); 6265 6266 if (sc->polling != 0) { 6267 hdac_lock(sc); 6268 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6269 hdac_unlock(sc); 6270 } 6271} 6272 6273/**************************************************************************** 6274 * int hdac_detach(device_t) 6275 * 6276 * Detach and free up resources utilized by the hdac device. 6277 ****************************************************************************/ 6278static int 6279hdac_detach(device_t dev) 6280{ 6281 struct hdac_softc *sc = NULL; 6282 struct hdac_devinfo *devinfo = NULL; 6283 int err; 6284 6285 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6286 if (devinfo != NULL && devinfo->codec != NULL) 6287 sc = devinfo->codec->sc; 6288 if (sc == NULL) 6289 return (0); 6290 6291 if (sc->registered > 0) { 6292 err = pcm_unregister(dev); 6293 if (err != 0) 6294 return (err); 6295 } 6296 6297 hdac_release_resources(sc); 6298 6299 return (0); 6300} 6301 6302static device_method_t hdac_methods[] = { 6303 /* device interface */ 6304 DEVMETHOD(device_probe, hdac_probe), 6305 DEVMETHOD(device_attach, hdac_attach), 6306 DEVMETHOD(device_detach, hdac_detach), 6307 { 0, 0 } 6308}; 6309 6310static driver_t hdac_driver = { 6311 "pcm", 6312 hdac_methods, 6313 PCM_SOFTC_SIZE, 6314}; 6315 6316DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6317MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6318MODULE_VERSION(snd_hda, 1); 6319