hdac.c revision 170518
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20070611_0045" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 170518 2007-06-10 23:01:40Z ariff $"); 87 88#define HDA_BOOTVERBOSE(stmt) do { \ 89 if (bootverbose != 0 || snd_verbose > 3) { \ 90 stmt \ 91 } \ 92} while(0) 93 94#if 1 95#undef HDAC_INTR_EXTRA 96#define HDAC_INTR_EXTRA 1 97#endif 98 99#define hdac_lock(sc) snd_mtxlock((sc)->lock) 100#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 101#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 102#define hdac_lockowned(sc) mtx_owned((sc)->lock) 103 104#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 105#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 106 (fl) == 0xffffffff || \ 107 (((fl) & 0xffff0000) == 0xffff0000 && \ 108 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 109 (((fl) & 0x0000ffff) == 0x0000ffff && \ 110 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 111#define HDA_MATCH_ALL 0xffffffff 112#define HDAC_INVALID 0xffffffff 113 114/* Default controller / jack sense poll: 250ms */ 115#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 116 117#define HDA_MODEL_CONSTRUCT(vendor, model) \ 118 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 119 120/* Controller models */ 121 122/* Intel */ 123#define INTEL_VENDORID 0x8086 124#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 125#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 126#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 127#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 128#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 129 130/* Nvidia */ 131#define NVIDIA_VENDORID 0x10de 132#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 133#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 134#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 135#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 136#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 137#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 138#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 139 140/* ATI */ 141#define ATI_VENDORID 0x1002 142#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 143#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 144#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 145 146/* VIA */ 147#define VIA_VENDORID 0x1106 148#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 149#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 150 151/* SiS */ 152#define SIS_VENDORID 0x1039 153#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 154#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 155 156/* OEM/subvendors */ 157 158/* Intel */ 159#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 160 161/* HP/Compaq */ 162#define HP_VENDORID 0x103c 163#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 164#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 165#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 166#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 167#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 168#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 169#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 170#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 171/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 172#define HP_NX6325_SUBVENDORX 0x103c30b0 173 174/* Dell */ 175#define DELL_VENDORID 0x1028 176#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 177#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 178#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 179#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 180#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 181 182/* Clevo */ 183#define CLEVO_VENDORID 0x1558 184#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 185#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 186 187/* Acer */ 188#define ACER_VENDORID 0x1025 189#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 190#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 191#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 192 193/* Asus */ 194#define ASUS_VENDORID 0x1043 195#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 196#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 197#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 198#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 199#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 200#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 201#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 202#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 203#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 204#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 205#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 206#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 207#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 208#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 209 210/* IBM / Lenovo */ 211#define IBM_VENDORID 0x1014 212#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 213#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 214 215/* Lenovo */ 216#define LENOVO_VENDORID 0x17aa 217#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 218#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 219 220/* Samsung */ 221#define SAMSUNG_VENDORID 0x144d 222#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 223#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 224 225/* Medion ? */ 226#define MEDION_VENDORID 0x161f 227#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 228#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 229 230/* 231 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 232 * instead of their own, which is beyond my comprehension 233 * (see HDA_CODEC_STAC9221 below). 234 */ 235#define APPLE_INTEL_MAC 0x76808384 236 237/* LG Electronics */ 238#define LG_VENDORID 0x1854 239#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 240#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 241 242/* Fujitsu Siemens */ 243#define FS_VENDORID 0x1734 244#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 245#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 246 247/* Toshiba */ 248#define TOSHIBA_VENDORID 0x1179 249#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 250#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 251 252/* Micro-Star International (MSI) */ 253#define MSI_VENDORID 0x1462 254#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 255#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 256 257/* Uniwill ? */ 258#define UNIWILL_VENDORID 0x1584 259#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 260 261 262/* Misc constants.. */ 263#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 264#define HDA_AMP_MUTE_NONE (0) 265#define HDA_AMP_MUTE_LEFT (1 << 0) 266#define HDA_AMP_MUTE_RIGHT (1 << 1) 267#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 268 269#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 270#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 271 272#define HDA_DAC_PATH (1 << 0) 273#define HDA_ADC_PATH (1 << 1) 274#define HDA_ADC_RECSEL (1 << 2) 275 276#define HDA_DAC_LOCKED (1 << 3) 277#define HDA_ADC_LOCKED (1 << 4) 278 279#define HDA_CTL_OUT (1 << 0) 280#define HDA_CTL_IN (1 << 1) 281#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 282 283#define HDA_GPIO_MAX 8 284/* 0 - 7 = GPIO , 8 = Flush */ 285#define HDA_QUIRK_GPIO0 (1 << 0) 286#define HDA_QUIRK_GPIO1 (1 << 1) 287#define HDA_QUIRK_GPIO2 (1 << 2) 288#define HDA_QUIRK_GPIO3 (1 << 3) 289#define HDA_QUIRK_GPIO4 (1 << 4) 290#define HDA_QUIRK_GPIO5 (1 << 5) 291#define HDA_QUIRK_GPIO6 (1 << 6) 292#define HDA_QUIRK_GPIO7 (1 << 7) 293#define HDA_QUIRK_GPIOFLUSH (1 << 8) 294 295/* 9 - 25 = anything else */ 296#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 297#define HDA_QUIRK_FIXEDRATE (1 << 10) 298#define HDA_QUIRK_FORCESTEREO (1 << 11) 299#define HDA_QUIRK_EAPDINV (1 << 12) 300#define HDA_QUIRK_DMAPOS (1 << 13) 301 302/* 26 - 31 = vrefs */ 303#define HDA_QUIRK_IVREF50 (1 << 26) 304#define HDA_QUIRK_IVREF80 (1 << 27) 305#define HDA_QUIRK_IVREF100 (1 << 28) 306#define HDA_QUIRK_OVREF50 (1 << 29) 307#define HDA_QUIRK_OVREF80 (1 << 30) 308#define HDA_QUIRK_OVREF100 (1 << 31) 309 310#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 311 HDA_QUIRK_IVREF100) 312#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 313 HDA_QUIRK_OVREF100) 314#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 315 316#define SOUND_MASK_SKIP (1 << 30) 317#define SOUND_MASK_DISABLE (1 << 31) 318 319static const struct { 320 char *key; 321 uint32_t value; 322} hdac_quirks_tab[] = { 323 { "gpio0", HDA_QUIRK_GPIO0 }, 324 { "gpio1", HDA_QUIRK_GPIO1 }, 325 { "gpio2", HDA_QUIRK_GPIO2 }, 326 { "gpio3", HDA_QUIRK_GPIO3 }, 327 { "gpio4", HDA_QUIRK_GPIO4 }, 328 { "gpio5", HDA_QUIRK_GPIO5 }, 329 { "gpio6", HDA_QUIRK_GPIO6 }, 330 { "gpio7", HDA_QUIRK_GPIO7 }, 331 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 332 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 333 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 334 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 335 { "eapdinv", HDA_QUIRK_EAPDINV }, 336 { "dmapos", HDA_QUIRK_DMAPOS }, 337 { "ivref50", HDA_QUIRK_IVREF50 }, 338 { "ivref80", HDA_QUIRK_IVREF80 }, 339 { "ivref100", HDA_QUIRK_IVREF100 }, 340 { "ovref50", HDA_QUIRK_OVREF50 }, 341 { "ovref80", HDA_QUIRK_OVREF80 }, 342 { "ovref100", HDA_QUIRK_OVREF100 }, 343 { "ivref", HDA_QUIRK_IVREF }, 344 { "ovref", HDA_QUIRK_OVREF }, 345 { "vref", HDA_QUIRK_VREF }, 346}; 347#define HDAC_QUIRKS_TAB_LEN \ 348 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 349 350#define HDA_BDL_MIN 2 351#define HDA_BDL_MAX 256 352#define HDA_BDL_DEFAULT HDA_BDL_MIN 353 354#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 355#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 356 357#define HDA_BUFSZ_MIN 4096 358#define HDA_BUFSZ_MAX 65536 359#define HDA_BUFSZ_DEFAULT 16384 360 361#define HDA_PARSE_MAXDEPTH 10 362 363#define HDAC_UNSOLTAG_EVENT_HP 0x00 364#define HDAC_UNSOLTAG_EVENT_TEST 0x01 365 366MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 367 368enum { 369 HDA_PARSE_MIXER, 370 HDA_PARSE_DIRECT 371}; 372 373/* Default */ 374static uint32_t hdac_fmt[] = { 375 AFMT_STEREO | AFMT_S16_LE, 376 0 377}; 378 379static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 380 381static const struct { 382 uint32_t model; 383 char *desc; 384} hdac_devices[] = { 385 { HDA_INTEL_82801F, "Intel 82801F" }, 386 { HDA_INTEL_82801G, "Intel 82801G" }, 387 { HDA_INTEL_82801H, "Intel 82801H" }, 388 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 389 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 390 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 391 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 392 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 393 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 394 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 395 { HDA_ATI_SB450, "ATI SB450" }, 396 { HDA_ATI_SB600, "ATI SB600" }, 397 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 398 { HDA_SIS_966, "SiS 966" }, 399 /* Unknown */ 400 { HDA_INTEL_ALL, "Intel (Unknown)" }, 401 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 402 { HDA_ATI_ALL, "ATI (Unknown)" }, 403 { HDA_VIA_ALL, "VIA (Unknown)" }, 404 { HDA_SIS_ALL, "SiS (Unknown)" }, 405}; 406#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 407 408static const struct { 409 uint16_t vendor; 410 uint8_t reg; 411 uint8_t mask; 412 uint8_t enable; 413} hdac_pcie_snoop[] = { 414 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 415 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 416 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 417}; 418#define HDAC_PCIESNOOP_LEN \ 419 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 420 421static const struct { 422 uint32_t rate; 423 int valid; 424 uint16_t base; 425 uint16_t mul; 426 uint16_t div; 427} hda_rate_tab[] = { 428 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 429 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 430 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 431 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 432 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 433 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 434 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 435 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 436 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 437 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 438 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 439 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 440 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 441 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 442 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 443 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 444 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 445 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 446 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 447 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 448 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 449 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 450 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 451 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 452 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 453 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 454 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 455 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 456 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 457 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 458 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 459 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 460 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 461 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 462 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 463}; 464#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 465 466/* All codecs you can eat... */ 467#define HDA_CODEC_CONSTRUCT(vendor, id) \ 468 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 469 470/* Realtek */ 471#define REALTEK_VENDORID 0x10ec 472#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 473#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 474#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 475#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 476#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 477#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 478#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 479#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 480#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 481#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 482#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 483 484/* Analog Devices */ 485#define ANALOGDEVICES_VENDORID 0x11d4 486#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 487#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 488#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 489#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 490#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 491#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 492 493/* CMedia */ 494#define CMEDIA_VENDORID 0x434d 495#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 496#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 497 498/* Sigmatel */ 499#define SIGMATEL_VENDORID 0x8384 500#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 501#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 502#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 503#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 504#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 505#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 506#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 507 508/* 509 * Conexant 510 * 511 * Ok, the truth is, I don't have any idea at all whether 512 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 513 * place that tell me it is "Venice" is from its Windows driver INF. 514 * 515 * Venice - CX????? 516 * Waikiki - CX20551-22 517 */ 518#define CONEXANT_VENDORID 0x14f1 519#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 520#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 521#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 522 523/* VIA */ 524#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 525#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 526#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 527#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 528#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 529#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 530#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 531#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 532#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 533#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 534#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 535#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 536#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 537 538 539/* Codecs */ 540static const struct { 541 uint32_t id; 542 char *name; 543} hdac_codecs[] = { 544 { HDA_CODEC_ALC260, "Realtek ALC260" }, 545 { HDA_CODEC_ALC262, "Realtek ALC262" }, 546 { HDA_CODEC_ALC660, "Realtek ALC660" }, 547 { HDA_CODEC_ALC861, "Realtek ALC861" }, 548 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 549 { HDA_CODEC_ALC880, "Realtek ALC880" }, 550 { HDA_CODEC_ALC882, "Realtek ALC882" }, 551 { HDA_CODEC_ALC883, "Realtek ALC883" }, 552 { HDA_CODEC_ALC885, "Realtek ALC885" }, 553 { HDA_CODEC_ALC888, "Realtek ALC888" }, 554 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 555 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 556 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 557 { HDA_CODEC_AD1988, "Analog Devices AD1988" }, 558 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 559 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 560 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 561 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 562 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 563 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 564 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 565 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 566 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 567 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 568 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 569 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 570 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 571 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 572 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 573 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 574 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 575 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 576 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 577 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 578 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 579 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 580 /* Unknown codec */ 581 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 582 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 583 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 584 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 585 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 586 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 587}; 588#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 589 590enum { 591 HDAC_HP_SWITCH_CTL, 592 HDAC_HP_SWITCH_CTRL, 593 HDAC_HP_SWITCH_DEBUG 594}; 595 596static const struct { 597 uint32_t model; 598 uint32_t id; 599 int type; 600 int inverted; 601 int polling; 602 int execsense; 603 nid_t hpnid; 604 nid_t spkrnid[8]; 605 nid_t eapdnid; 606} hdac_hp_switch[] = { 607 /* Specific OEM models */ 608 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 609 0, 0, -1, 17, { 16, -1 }, 16 }, 610 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL, 611 0, 0, -1, 21, { 16, 17, -1 }, -1 } */ 612 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG, 613 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/ 614 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 615 0, 0, -1, 6, { 5, -1 }, 5 }, 616 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 617 0, 0, -1, 6, { 5, -1 }, 5 }, 618 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 619 0, 0, -1, 6, { 5, -1 }, 5 }, 620 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 621 0, 0, -1, 6, { 5, -1 }, -1 }, 622 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 623 0, 0, -1, 13, { 14, -1 }, -1 }, 624 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 625 0, 0, -1, 13, { 14, -1 }, -1 }, 626 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL, 627 0, 0, -1, 6, { 5, 7, -1 }, -1 }, 628 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 629 0, 0, -1, 10, { 13, -1 }, -1 }, 630 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 631 1, 0, -1, 26, { 27, -1 }, -1 }, 632 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 633 0, 0, -1, 27, { 20, -1 }, -1 }, 634 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 635 0, 0, -1, 20, { 21, -1 }, -1 }, 636 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 637 0, 0, -1, 20, { 21, -1 }, -1 }, 638 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 639 0, 0, -1, 20, { 27, -1 }, -1 }, 640 /* 641 * All models that at least come from the same vendor with 642 * simmilar codec. 643 */ 644 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 645 0, 0, -1, 17, { 16, -1 }, 16 }, 646 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 647 0, 0, -1, 6, { 5, -1 }, 5 }, 648 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 649 0, 0, -1, 6, { 5, -1 }, -1 }, 650 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 651 0, 0, -1, 13, { 14, -1 }, -1 }, 652 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 653 1, 0, -1, 26, { 27, -1 }, -1 }, 654#if 0 655 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 656 0, 0, -1, 20, { 21, -1 }, -1 }, 657#endif 658}; 659#define HDAC_HP_SWITCH_LEN \ 660 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 661 662static const struct { 663 uint32_t model; 664 uint32_t id; 665 nid_t eapdnid; 666 int hp_switch; 667} hdac_eapd_switch[] = { 668 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 669 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 670 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 671}; 672#define HDAC_EAPD_SWITCH_LEN \ 673 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 674 675/**************************************************************************** 676 * Function prototypes 677 ****************************************************************************/ 678static void hdac_intr_handler(void *); 679static int hdac_reset(struct hdac_softc *); 680static int hdac_get_capabilities(struct hdac_softc *); 681static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 682static int hdac_dma_alloc(struct hdac_softc *, 683 struct hdac_dma *, bus_size_t); 684static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 685static int hdac_mem_alloc(struct hdac_softc *); 686static void hdac_mem_free(struct hdac_softc *); 687static int hdac_irq_alloc(struct hdac_softc *); 688static void hdac_irq_free(struct hdac_softc *); 689static void hdac_corb_init(struct hdac_softc *); 690static void hdac_rirb_init(struct hdac_softc *); 691static void hdac_corb_start(struct hdac_softc *); 692static void hdac_rirb_start(struct hdac_softc *); 693static void hdac_scan_codecs(struct hdac_softc *); 694static int hdac_probe_codec(struct hdac_codec *); 695static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 696static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 697 698static void hdac_attach2(void *); 699 700static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 701 uint32_t, int); 702static void hdac_command_send_internal(struct hdac_softc *, 703 struct hdac_command_list *, int); 704 705static int hdac_probe(device_t); 706static int hdac_attach(device_t); 707static int hdac_detach(device_t); 708static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 709static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 710 uint32_t, int, int); 711static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 712 nid_t, int, int); 713static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 714 nid_t, nid_t, int, int, int, int, int, int); 715static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 716static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 717 718static int hdac_rirb_flush(struct hdac_softc *sc); 719static int hdac_unsolq_flush(struct hdac_softc *sc); 720 721#define hdac_command(a1, a2, a3) \ 722 hdac_command_sendone_internal(a1, a2, a3) 723 724#define hdac_codec_id(d) \ 725 ((uint32_t)((d == NULL) ? 0x00000000 : \ 726 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 727 ((uint32_t)(d)->device_id & 0x0000ffff)))) 728 729static char * 730hdac_codec_name(struct hdac_devinfo *devinfo) 731{ 732 uint32_t id; 733 int i; 734 735 id = hdac_codec_id(devinfo); 736 737 for (i = 0; i < HDAC_CODECS_LEN; i++) { 738 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 739 return (hdac_codecs[i].name); 740 } 741 742 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 743} 744 745static char * 746hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 747{ 748 static char *ossname[] = SOUND_DEVICE_NAMES; 749 static char *unknown = "???"; 750 int i; 751 752 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 753 if (devmask & (1 << i)) 754 return (ossname[i]); 755 } 756 return (unknown); 757} 758 759static void 760hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 761{ 762 static char *ossname[] = SOUND_DEVICE_NAMES; 763 int i, first = 1; 764 765 bzero(buf, len); 766 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 767 if (mask & (1 << i)) { 768 if (first == 0) 769 strlcat(buf, ", ", len); 770 strlcat(buf, ossname[i], len); 771 first = 0; 772 } 773 } 774} 775 776static struct hdac_audio_ctl * 777hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 778{ 779 if (devinfo == NULL || 780 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 781 index == NULL || devinfo->function.audio.ctl == NULL || 782 devinfo->function.audio.ctlcnt < 1 || 783 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 784 return (NULL); 785 return (&devinfo->function.audio.ctl[(*index)++]); 786} 787 788static struct hdac_audio_ctl * 789hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 790 int index, int cnt) 791{ 792 struct hdac_audio_ctl *ctl, *retctl = NULL; 793 int i, at, atindex, found = 0; 794 795 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 796 return (NULL); 797 798 at = cnt; 799 if (at == 0) 800 at = 1; 801 else if (at < 0) 802 at = -1; 803 atindex = index; 804 if (atindex < 0) 805 atindex = -1; 806 807 i = 0; 808 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 809 if (ctl->enable == 0 || ctl->widget == NULL) 810 continue; 811 if (!(ctl->widget->nid == nid && (atindex == -1 || 812 ctl->index == atindex))) 813 continue; 814 found++; 815 if (found == cnt) 816 return (ctl); 817 retctl = ctl; 818 } 819 820 return ((at == -1) ? retctl : NULL); 821} 822 823static void 824hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 825{ 826 struct hdac_softc *sc; 827 struct hdac_widget *w; 828 struct hdac_audio_ctl *ctl; 829 uint32_t val, id, res; 830 int i = 0, j, forcemute; 831 nid_t cad; 832 833 if (devinfo == NULL || devinfo->codec == NULL || 834 devinfo->codec->sc == NULL) 835 return; 836 837 sc = devinfo->codec->sc; 838 cad = devinfo->codec->cad; 839 id = hdac_codec_id(devinfo); 840 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 841 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 842 sc->pci_subvendor) && 843 hdac_hp_switch[i].id == id) 844 break; 845 } 846 847 if (i >= HDAC_HP_SWITCH_LEN) 848 return; 849 850 forcemute = 0; 851 if (hdac_hp_switch[i].eapdnid != -1) { 852 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 853 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 854 forcemute = (w->param.eapdbtl & 855 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 856 } 857 858 if (hdac_hp_switch[i].execsense != -1) 859 hdac_command(sc, 860 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 861 hdac_hp_switch[i].execsense), cad); 862 res = hdac_command(sc, 863 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 864 HDA_BOOTVERBOSE( 865 device_printf(sc->dev, 866 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 867 hdac_hp_switch[i].hpnid, res); 868 ); 869 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 870 res ^= hdac_hp_switch[i].inverted; 871 872 switch (hdac_hp_switch[i].type) { 873 case HDAC_HP_SWITCH_CTL: 874 ctl = hdac_audio_ctl_amp_get(devinfo, 875 hdac_hp_switch[i].hpnid, 0, 1); 876 if (ctl != NULL) { 877 val = (res != 0 && forcemute == 0) ? 878 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 879 if (val != ctl->muted) { 880 ctl->muted = val; 881 hdac_audio_ctl_amp_set(ctl, 882 HDA_AMP_MUTE_DEFAULT, ctl->left, 883 ctl->right); 884 } 885 } 886 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 887 ctl = hdac_audio_ctl_amp_get(devinfo, 888 hdac_hp_switch[i].spkrnid[j], 0, 1); 889 if (ctl == NULL) 890 continue; 891 val = (res != 0 || forcemute == 1) ? 892 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 893 if (val == ctl->muted) 894 continue; 895 ctl->muted = val; 896 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 897 ctl->left, ctl->right); 898 } 899 break; 900 case HDAC_HP_SWITCH_CTRL: 901 if (res != 0) { 902 /* HP in */ 903 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 904 if (w != NULL && w->type == 905 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 906 if (forcemute == 0) 907 val = w->wclass.pin.ctrl | 908 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 909 else 910 val = w->wclass.pin.ctrl & 911 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 912 if (val != w->wclass.pin.ctrl) { 913 w->wclass.pin.ctrl = val; 914 hdac_command(sc, 915 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 916 w->nid, w->wclass.pin.ctrl), cad); 917 } 918 } 919 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 920 w = hdac_widget_get(devinfo, 921 hdac_hp_switch[i].spkrnid[j]); 922 if (w == NULL || w->type != 923 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 924 continue; 925 val = w->wclass.pin.ctrl & 926 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 927 if (val == w->wclass.pin.ctrl) 928 continue; 929 w->wclass.pin.ctrl = val; 930 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 931 cad, w->nid, w->wclass.pin.ctrl), cad); 932 } 933 } else { 934 /* HP out */ 935 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 936 if (w != NULL && w->type == 937 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 938 val = w->wclass.pin.ctrl & 939 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 940 if (val != w->wclass.pin.ctrl) { 941 w->wclass.pin.ctrl = val; 942 hdac_command(sc, 943 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 944 w->nid, w->wclass.pin.ctrl), cad); 945 } 946 } 947 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 948 w = hdac_widget_get(devinfo, 949 hdac_hp_switch[i].spkrnid[j]); 950 if (w == NULL || w->type != 951 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 952 continue; 953 if (forcemute == 0) 954 val = w->wclass.pin.ctrl | 955 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 956 else 957 val = w->wclass.pin.ctrl & 958 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 959 if (val == w->wclass.pin.ctrl) 960 continue; 961 w->wclass.pin.ctrl = val; 962 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL( 963 cad, w->nid, w->wclass.pin.ctrl), cad); 964 } 965 } 966 break; 967 case HDAC_HP_SWITCH_DEBUG: 968 if (hdac_hp_switch[i].execsense != -1) 969 hdac_command(sc, 970 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid, 971 hdac_hp_switch[i].execsense), cad); 972 res = hdac_command(sc, 973 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 974 device_printf(sc->dev, 975 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 976 hdac_hp_switch[i].hpnid, res); 977 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 978 w = hdac_widget_get(devinfo, 979 hdac_hp_switch[i].spkrnid[j]); 980 if (w == NULL || w->type != 981 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 982 continue; 983 if (hdac_hp_switch[i].execsense != -1) 984 hdac_command(sc, 985 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 986 hdac_hp_switch[i].execsense), cad); 987 res = hdac_command(sc, 988 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 989 device_printf(sc->dev, 990 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 991 j + 1, w->nid, res); 992 } 993 break; 994 default: 995 break; 996 } 997} 998 999static void 1000hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1001{ 1002 struct hdac_softc *sc; 1003 struct hdac_devinfo *devinfo = NULL; 1004 device_t *devlist = NULL; 1005 int devcount, i; 1006 1007 if (codec == NULL || codec->sc == NULL) 1008 return; 1009 1010 sc = codec->sc; 1011 1012 HDA_BOOTVERBOSE( 1013 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 1014 ); 1015 1016 device_get_children(sc->dev, &devlist, &devcount); 1017 for (i = 0; devlist != NULL && i < devcount; i++) { 1018 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 1019 if (devinfo != NULL && devinfo->node_type == 1020 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 1021 devinfo->codec != NULL && 1022 devinfo->codec->cad == codec->cad) { 1023 break; 1024 } else 1025 devinfo = NULL; 1026 } 1027 if (devlist != NULL) 1028 free(devlist, M_TEMP); 1029 1030 if (devinfo == NULL) 1031 return; 1032 1033 switch (tag) { 1034 case HDAC_UNSOLTAG_EVENT_HP: 1035 hdac_hp_switch_handler(devinfo); 1036 break; 1037 case HDAC_UNSOLTAG_EVENT_TEST: 1038 device_printf(sc->dev, "Unsol Test!\n"); 1039 break; 1040 default: 1041 break; 1042 } 1043} 1044 1045static int 1046hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1047{ 1048 /* XXX to be removed */ 1049#ifdef HDAC_INTR_EXTRA 1050 uint32_t res; 1051#endif 1052 1053 if (ch->blkcnt == 0) 1054 return (0); 1055 1056 /* XXX to be removed */ 1057#ifdef HDAC_INTR_EXTRA 1058 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1059#endif 1060 1061 /* XXX to be removed */ 1062#ifdef HDAC_INTR_EXTRA 1063 HDA_BOOTVERBOSE( 1064 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1065 device_printf(sc->dev, 1066 "PCMDIR_%s intr triggered beyond stream boundary:" 1067 "%08x\n", 1068 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1069 ); 1070#endif 1071 1072 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1073 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1074 1075 /* XXX to be removed */ 1076#ifdef HDAC_INTR_EXTRA 1077 if (res & HDAC_SDSTS_BCIS) { 1078#endif 1079 return (1); 1080 /* XXX to be removed */ 1081#ifdef HDAC_INTR_EXTRA 1082 } 1083#endif 1084 1085 return (0); 1086} 1087 1088/**************************************************************************** 1089 * void hdac_intr_handler(void *) 1090 * 1091 * Interrupt handler. Processes interrupts received from the hdac. 1092 ****************************************************************************/ 1093static void 1094hdac_intr_handler(void *context) 1095{ 1096 struct hdac_softc *sc; 1097 uint32_t intsts; 1098 uint8_t rirbsts; 1099 struct hdac_rirb *rirb_base; 1100 uint32_t trigger = 0; 1101 1102 sc = (struct hdac_softc *)context; 1103 1104 hdac_lock(sc); 1105 if (sc->polling != 0) { 1106 hdac_unlock(sc); 1107 return; 1108 } 1109 /* Do we have anything to do? */ 1110 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1111 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1112 hdac_unlock(sc); 1113 return; 1114 } 1115 1116 /* Was this a controller interrupt? */ 1117 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1118 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1119 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1120 /* Get as many responses that we can */ 1121 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1122 HDAC_WRITE_1(&sc->mem, 1123 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1124 hdac_rirb_flush(sc); 1125 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1126 } 1127 /* XXX to be removed */ 1128 /* Clear interrupt and exit */ 1129#ifdef HDAC_INTR_EXTRA 1130 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1131#endif 1132 } 1133 1134 hdac_unsolq_flush(sc); 1135 1136 if (intsts & HDAC_INTSTS_SIS_MASK) { 1137 if ((intsts & (1 << sc->num_iss)) && 1138 hdac_stream_intr(sc, &sc->play) != 0) 1139 trigger |= 1; 1140 if ((intsts & (1 << 0)) && 1141 hdac_stream_intr(sc, &sc->rec) != 0) 1142 trigger |= 2; 1143 /* XXX to be removed */ 1144#ifdef HDAC_INTR_EXTRA 1145 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1146 HDAC_INTSTS_SIS_MASK); 1147#endif 1148 } 1149 1150 hdac_unlock(sc); 1151 1152 if (trigger & 1) 1153 chn_intr(sc->play.c); 1154 if (trigger & 2) 1155 chn_intr(sc->rec.c); 1156} 1157 1158/**************************************************************************** 1159 * int hdac_reset(hdac_softc *) 1160 * 1161 * Reset the hdac to a quiescent and known state. 1162 ****************************************************************************/ 1163static int 1164hdac_reset(struct hdac_softc *sc) 1165{ 1166 uint32_t gctl; 1167 int count, i; 1168 1169 /* 1170 * Stop all Streams DMA engine 1171 */ 1172 for (i = 0; i < sc->num_iss; i++) 1173 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1174 for (i = 0; i < sc->num_oss; i++) 1175 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1176 for (i = 0; i < sc->num_bss; i++) 1177 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1178 1179 /* 1180 * Stop Control DMA engines. 1181 */ 1182 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1183 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1184 1185 /* 1186 * Reset DMA position buffer. 1187 */ 1188 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1189 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1190 1191 /* 1192 * Reset the controller. The reset must remain asserted for 1193 * a minimum of 100us. 1194 */ 1195 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1196 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1197 count = 10000; 1198 do { 1199 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1200 if (!(gctl & HDAC_GCTL_CRST)) 1201 break; 1202 DELAY(10); 1203 } while (--count); 1204 if (gctl & HDAC_GCTL_CRST) { 1205 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1206 return (ENXIO); 1207 } 1208 DELAY(100); 1209 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1210 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1211 count = 10000; 1212 do { 1213 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1214 if (gctl & HDAC_GCTL_CRST) 1215 break; 1216 DELAY(10); 1217 } while (--count); 1218 if (!(gctl & HDAC_GCTL_CRST)) { 1219 device_printf(sc->dev, "Device stuck in reset\n"); 1220 return (ENXIO); 1221 } 1222 1223 /* 1224 * Wait for codecs to finish their own reset sequence. The delay here 1225 * should be of 250us but for some reasons, on it's not enough on my 1226 * computer. Let's use twice as much as necessary to make sure that 1227 * it's reset properly. 1228 */ 1229 DELAY(1000); 1230 1231 return (0); 1232} 1233 1234 1235/**************************************************************************** 1236 * int hdac_get_capabilities(struct hdac_softc *); 1237 * 1238 * Retreive the general capabilities of the hdac; 1239 * Number of Input Streams 1240 * Number of Output Streams 1241 * Number of bidirectional Streams 1242 * 64bit ready 1243 * CORB and RIRB sizes 1244 ****************************************************************************/ 1245static int 1246hdac_get_capabilities(struct hdac_softc *sc) 1247{ 1248 uint16_t gcap; 1249 uint8_t corbsize, rirbsize; 1250 1251 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1252 sc->num_iss = HDAC_GCAP_ISS(gcap); 1253 sc->num_oss = HDAC_GCAP_OSS(gcap); 1254 sc->num_bss = HDAC_GCAP_BSS(gcap); 1255 1256 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1257 1258 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1259 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1260 HDAC_CORBSIZE_CORBSZCAP_256) 1261 sc->corb_size = 256; 1262 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1263 HDAC_CORBSIZE_CORBSZCAP_16) 1264 sc->corb_size = 16; 1265 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1266 HDAC_CORBSIZE_CORBSZCAP_2) 1267 sc->corb_size = 2; 1268 else { 1269 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1270 __func__, corbsize); 1271 return (ENXIO); 1272 } 1273 1274 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1275 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1276 HDAC_RIRBSIZE_RIRBSZCAP_256) 1277 sc->rirb_size = 256; 1278 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1279 HDAC_RIRBSIZE_RIRBSZCAP_16) 1280 sc->rirb_size = 16; 1281 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1282 HDAC_RIRBSIZE_RIRBSZCAP_2) 1283 sc->rirb_size = 2; 1284 else { 1285 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1286 __func__, rirbsize); 1287 return (ENXIO); 1288 } 1289 1290 return (0); 1291} 1292 1293 1294/**************************************************************************** 1295 * void hdac_dma_cb 1296 * 1297 * This function is called by bus_dmamap_load when the mapping has been 1298 * established. We just record the physical address of the mapping into 1299 * the struct hdac_dma passed in. 1300 ****************************************************************************/ 1301static void 1302hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1303{ 1304 struct hdac_dma *dma; 1305 1306 if (error == 0) { 1307 dma = (struct hdac_dma *)callback_arg; 1308 dma->dma_paddr = segs[0].ds_addr; 1309 } 1310} 1311 1312 1313/**************************************************************************** 1314 * int hdac_dma_alloc 1315 * 1316 * This function allocate and setup a dma region (struct hdac_dma). 1317 * It must be freed by a corresponding hdac_dma_free. 1318 ****************************************************************************/ 1319static int 1320hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1321{ 1322 bus_size_t roundsz; 1323 int result; 1324 int lowaddr; 1325 1326 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1327 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1328 BUS_SPACE_MAXADDR_32BIT; 1329 bzero(dma, sizeof(*dma)); 1330 1331 /* 1332 * Create a DMA tag 1333 */ 1334 result = bus_dma_tag_create(NULL, /* parent */ 1335 HDAC_DMA_ALIGNMENT, /* alignment */ 1336 0, /* boundary */ 1337 lowaddr, /* lowaddr */ 1338 BUS_SPACE_MAXADDR, /* highaddr */ 1339 NULL, /* filtfunc */ 1340 NULL, /* fistfuncarg */ 1341 roundsz, /* maxsize */ 1342 1, /* nsegments */ 1343 roundsz, /* maxsegsz */ 1344 0, /* flags */ 1345 NULL, /* lockfunc */ 1346 NULL, /* lockfuncarg */ 1347 &dma->dma_tag); /* dmat */ 1348 if (result != 0) { 1349 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1350 __func__, result); 1351 goto hdac_dma_alloc_fail; 1352 } 1353 1354 /* 1355 * Allocate DMA memory 1356 */ 1357 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1358 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1359 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map); 1360 if (result != 0) { 1361 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1362 __func__, result); 1363 goto hdac_dma_alloc_fail; 1364 } 1365 1366 dma->dma_size = roundsz; 1367 1368 /* 1369 * Map the memory 1370 */ 1371 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1372 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1373 if (result != 0 || dma->dma_paddr == 0) { 1374 if (result == 0) 1375 result = ENOMEM; 1376 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1377 __func__, result); 1378 goto hdac_dma_alloc_fail; 1379 } 1380 1381 HDA_BOOTVERBOSE( 1382 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1383 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1384 ); 1385 1386 return (0); 1387 1388hdac_dma_alloc_fail: 1389 hdac_dma_free(sc, dma); 1390 1391 return (result); 1392} 1393 1394 1395/**************************************************************************** 1396 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1397 * 1398 * Free a struct dhac_dma that has been previously allocated via the 1399 * hdac_dma_alloc function. 1400 ****************************************************************************/ 1401static void 1402hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1403{ 1404 if (dma->dma_map != NULL) { 1405#if 0 1406 /* Flush caches */ 1407 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1408 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1409#endif 1410 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1411 } 1412 if (dma->dma_vaddr != NULL) { 1413 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1414 dma->dma_vaddr = NULL; 1415 } 1416 dma->dma_map = NULL; 1417 if (dma->dma_tag != NULL) { 1418 bus_dma_tag_destroy(dma->dma_tag); 1419 dma->dma_tag = NULL; 1420 } 1421 dma->dma_size = 0; 1422} 1423 1424/**************************************************************************** 1425 * int hdac_mem_alloc(struct hdac_softc *) 1426 * 1427 * Allocate all the bus resources necessary to speak with the physical 1428 * controller. 1429 ****************************************************************************/ 1430static int 1431hdac_mem_alloc(struct hdac_softc *sc) 1432{ 1433 struct hdac_mem *mem; 1434 1435 mem = &sc->mem; 1436 mem->mem_rid = PCIR_BAR(0); 1437 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1438 &mem->mem_rid, RF_ACTIVE); 1439 if (mem->mem_res == NULL) { 1440 device_printf(sc->dev, 1441 "%s: Unable to allocate memory resource\n", __func__); 1442 return (ENOMEM); 1443 } 1444 mem->mem_tag = rman_get_bustag(mem->mem_res); 1445 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1446 1447 return (0); 1448} 1449 1450/**************************************************************************** 1451 * void hdac_mem_free(struct hdac_softc *) 1452 * 1453 * Free up resources previously allocated by hdac_mem_alloc. 1454 ****************************************************************************/ 1455static void 1456hdac_mem_free(struct hdac_softc *sc) 1457{ 1458 struct hdac_mem *mem; 1459 1460 mem = &sc->mem; 1461 if (mem->mem_res != NULL) 1462 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1463 mem->mem_res); 1464 mem->mem_res = NULL; 1465} 1466 1467/**************************************************************************** 1468 * int hdac_irq_alloc(struct hdac_softc *) 1469 * 1470 * Allocate and setup the resources necessary for interrupt handling. 1471 ****************************************************************************/ 1472static int 1473hdac_irq_alloc(struct hdac_softc *sc) 1474{ 1475 struct hdac_irq *irq; 1476 int result; 1477 1478 irq = &sc->irq; 1479 irq->irq_rid = 0x0; 1480 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1481 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1482 if (irq->irq_res == NULL) { 1483 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1484 __func__); 1485 goto hdac_irq_alloc_fail; 1486 } 1487 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1488 hdac_intr_handler, sc, &irq->irq_handle); 1489 if (result != 0) { 1490 device_printf(sc->dev, 1491 "%s: Unable to setup interrupt handler (%x)\n", 1492 __func__, result); 1493 goto hdac_irq_alloc_fail; 1494 } 1495 1496 return (0); 1497 1498hdac_irq_alloc_fail: 1499 hdac_irq_free(sc); 1500 1501 return (ENXIO); 1502} 1503 1504/**************************************************************************** 1505 * void hdac_irq_free(struct hdac_softc *) 1506 * 1507 * Free up resources previously allocated by hdac_irq_alloc. 1508 ****************************************************************************/ 1509static void 1510hdac_irq_free(struct hdac_softc *sc) 1511{ 1512 struct hdac_irq *irq; 1513 1514 irq = &sc->irq; 1515 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1516 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1517 if (irq->irq_res != NULL) 1518 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1519 irq->irq_res); 1520 irq->irq_handle = NULL; 1521 irq->irq_res = NULL; 1522} 1523 1524/**************************************************************************** 1525 * void hdac_corb_init(struct hdac_softc *) 1526 * 1527 * Initialize the corb registers for operations but do not start it up yet. 1528 * The CORB engine must not be running when this function is called. 1529 ****************************************************************************/ 1530static void 1531hdac_corb_init(struct hdac_softc *sc) 1532{ 1533 uint8_t corbsize; 1534 uint64_t corbpaddr; 1535 1536 /* Setup the CORB size. */ 1537 switch (sc->corb_size) { 1538 case 256: 1539 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1540 break; 1541 case 16: 1542 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1543 break; 1544 case 2: 1545 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1546 break; 1547 default: 1548 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1549 } 1550 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1551 1552 /* Setup the CORB Address in the hdac */ 1553 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1554 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1555 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1556 1557 /* Set the WP and RP */ 1558 sc->corb_wp = 0; 1559 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1560 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1561 /* 1562 * The HDA specification indicates that the CORBRPRST bit will always 1563 * read as zero. Unfortunately, it seems that at least the 82801G 1564 * doesn't reset the bit to zero, which stalls the corb engine. 1565 * manually reset the bit to zero before continuing. 1566 */ 1567 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1568 1569 /* Enable CORB error reporting */ 1570#if 0 1571 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1572#endif 1573} 1574 1575/**************************************************************************** 1576 * void hdac_rirb_init(struct hdac_softc *) 1577 * 1578 * Initialize the rirb registers for operations but do not start it up yet. 1579 * The RIRB engine must not be running when this function is called. 1580 ****************************************************************************/ 1581static void 1582hdac_rirb_init(struct hdac_softc *sc) 1583{ 1584 uint8_t rirbsize; 1585 uint64_t rirbpaddr; 1586 1587 /* Setup the RIRB size. */ 1588 switch (sc->rirb_size) { 1589 case 256: 1590 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1591 break; 1592 case 16: 1593 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1594 break; 1595 case 2: 1596 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1597 break; 1598 default: 1599 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1600 } 1601 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1602 1603 /* Setup the RIRB Address in the hdac */ 1604 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1605 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1606 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1607 1608 /* Setup the WP and RP */ 1609 sc->rirb_rp = 0; 1610 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1611 1612 if (sc->polling == 0) { 1613 /* Setup the interrupt threshold */ 1614 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1615 1616 /* Enable Overrun and response received reporting */ 1617#if 0 1618 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1619 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1620#else 1621 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1622#endif 1623 } 1624 1625#if 0 1626 /* 1627 * Make sure that the Host CPU cache doesn't contain any dirty 1628 * cache lines that falls in the rirb. If I understood correctly, it 1629 * should be sufficient to do this only once as the rirb is purely 1630 * read-only from now on. 1631 */ 1632 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1633 BUS_DMASYNC_PREREAD); 1634#endif 1635} 1636 1637/**************************************************************************** 1638 * void hdac_corb_start(hdac_softc *) 1639 * 1640 * Startup the corb DMA engine 1641 ****************************************************************************/ 1642static void 1643hdac_corb_start(struct hdac_softc *sc) 1644{ 1645 uint32_t corbctl; 1646 1647 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1648 corbctl |= HDAC_CORBCTL_CORBRUN; 1649 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1650} 1651 1652/**************************************************************************** 1653 * void hdac_rirb_start(hdac_softc *) 1654 * 1655 * Startup the rirb DMA engine 1656 ****************************************************************************/ 1657static void 1658hdac_rirb_start(struct hdac_softc *sc) 1659{ 1660 uint32_t rirbctl; 1661 1662 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1663 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1664 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1665} 1666 1667 1668/**************************************************************************** 1669 * void hdac_scan_codecs(struct hdac_softc *) 1670 * 1671 * Scan the bus for available codecs. 1672 ****************************************************************************/ 1673static void 1674hdac_scan_codecs(struct hdac_softc *sc) 1675{ 1676 struct hdac_codec *codec; 1677 int i; 1678 uint16_t statests; 1679 1680 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1681 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1682 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1683 /* We have found a codec. */ 1684 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1685 M_HDAC, M_ZERO | M_NOWAIT); 1686 if (codec == NULL) { 1687 device_printf(sc->dev, 1688 "Unable to allocate memory for codec\n"); 1689 continue; 1690 } 1691 codec->commands = NULL; 1692 codec->responses_received = 0; 1693 codec->verbs_sent = 0; 1694 codec->sc = sc; 1695 codec->cad = i; 1696 sc->codecs[i] = codec; 1697 if (hdac_probe_codec(codec) != 0) 1698 break; 1699 } 1700 } 1701 /* All codecs have been probed, now try to attach drivers to them */ 1702 /* bus_generic_attach(sc->dev); */ 1703} 1704 1705/**************************************************************************** 1706 * void hdac_probe_codec(struct hdac_softc *, int) 1707 * 1708 * Probe a the given codec_id for available function groups. 1709 ****************************************************************************/ 1710static int 1711hdac_probe_codec(struct hdac_codec *codec) 1712{ 1713 struct hdac_softc *sc = codec->sc; 1714 struct hdac_devinfo *devinfo; 1715 uint32_t vendorid, revisionid, subnode; 1716 int startnode; 1717 int endnode; 1718 int i; 1719 nid_t cad = codec->cad; 1720 1721 HDA_BOOTVERBOSE( 1722 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1723 ); 1724 vendorid = hdac_command(sc, 1725 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1726 cad); 1727 revisionid = hdac_command(sc, 1728 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1729 cad); 1730 subnode = hdac_command(sc, 1731 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1732 cad); 1733 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1734 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1735 1736 HDA_BOOTVERBOSE( 1737 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1738 startnode, endnode); 1739 ); 1740 for (i = startnode; i < endnode; i++) { 1741 devinfo = hdac_probe_function(codec, i); 1742 if (devinfo != NULL) { 1743 /* XXX Ignore other FG. */ 1744 devinfo->vendor_id = 1745 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1746 devinfo->device_id = 1747 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1748 devinfo->revision_id = 1749 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1750 devinfo->stepping_id = 1751 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1752 HDA_BOOTVERBOSE( 1753 device_printf(sc->dev, 1754 "HDA_DEBUG: \tFound AFG nid=%d " 1755 "[startnode=%d endnode=%d]\n", 1756 devinfo->nid, startnode, endnode); 1757 ); 1758 return (1); 1759 } 1760 } 1761 1762 HDA_BOOTVERBOSE( 1763 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1764 ); 1765 return (0); 1766} 1767 1768static struct hdac_devinfo * 1769hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1770{ 1771 struct hdac_softc *sc = codec->sc; 1772 struct hdac_devinfo *devinfo; 1773 uint32_t fctgrptype; 1774 nid_t cad = codec->cad; 1775 1776 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1777 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1778 1779 /* XXX For now, ignore other FG. */ 1780 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1781 return (NULL); 1782 1783 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1784 M_NOWAIT | M_ZERO); 1785 if (devinfo == NULL) { 1786 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1787 __func__); 1788 return (NULL); 1789 } 1790 1791 devinfo->nid = nid; 1792 devinfo->node_type = fctgrptype; 1793 devinfo->codec = codec; 1794 1795 hdac_add_child(sc, devinfo); 1796 1797 return (devinfo); 1798} 1799 1800static void 1801hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1802{ 1803 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1804 device_set_ivars(devinfo->dev, (void *)devinfo); 1805 /* XXX - Print more information when booting verbose??? */ 1806} 1807 1808static void 1809hdac_widget_connection_parse(struct hdac_widget *w) 1810{ 1811 struct hdac_softc *sc = w->devinfo->codec->sc; 1812 uint32_t res; 1813 int i, j, max, ents, entnum; 1814 nid_t cad = w->devinfo->codec->cad; 1815 nid_t nid = w->nid; 1816 nid_t cnid, addcnid, prevcnid; 1817 1818 w->nconns = 0; 1819 1820 res = hdac_command(sc, 1821 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1822 1823 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1824 1825 if (ents < 1) 1826 return; 1827 1828 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1829 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1830 prevcnid = 0; 1831 1832#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 1833#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 1834#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 1835#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 1836#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 1837 1838 for (i = 0; i < ents; i += entnum) { 1839 res = hdac_command(sc, 1840 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1841 for (j = 0; j < entnum; j++) { 1842 cnid = CONN_CNID(res, entnum, j); 1843 if (cnid == 0) { 1844 if (w->nconns < ents) 1845 device_printf(sc->dev, 1846 "%s: nid=%d WARNING: zero cnid " 1847 "entnum=%d j=%d index=%d " 1848 "entries=%d found=%d res=0x%08x\n", 1849 __func__, nid, entnum, j, i, 1850 ents, w->nconns, res); 1851 else 1852 goto getconns_out; 1853 } 1854 if (cnid < w->devinfo->startnode || 1855 cnid >= w->devinfo->endnode) { 1856 HDA_BOOTVERBOSE( 1857 device_printf(sc->dev, 1858 "%s: GHOST: nid=%d j=%d " 1859 "entnum=%d index=%d res=0x%08x\n", 1860 __func__, nid, j, entnum, i, res); 1861 ); 1862 } 1863 if (CONN_RANGE(res, entnum, j) == 0) 1864 addcnid = cnid; 1865 else if (prevcnid == 0 || prevcnid >= cnid) { 1866 device_printf(sc->dev, 1867 "%s: WARNING: Invalid child range " 1868 "nid=%d index=%d j=%d entnum=%d " 1869 "prevcnid=%d cnid=%d res=0x%08x\n", 1870 __func__, nid, i, j, entnum, prevcnid, 1871 cnid, res); 1872 addcnid = cnid; 1873 } else 1874 addcnid = prevcnid + 1; 1875 while (addcnid <= cnid) { 1876 if (w->nconns > max) { 1877 device_printf(sc->dev, 1878 "%s: nid=%d: Adding %d: " 1879 "Max connection reached! max=%d\n", 1880 __func__, nid, addcnid, max + 1); 1881 goto getconns_out; 1882 } 1883 w->conns[w->nconns++] = addcnid++; 1884 } 1885 prevcnid = cnid; 1886 } 1887 } 1888 1889getconns_out: 1890 HDA_BOOTVERBOSE( 1891 device_printf(sc->dev, 1892 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n", 1893 __func__, nid, ents, w->nconns); 1894 ); 1895 return; 1896} 1897 1898static uint32_t 1899hdac_widget_pin_getconfig(struct hdac_widget *w) 1900{ 1901 struct hdac_softc *sc; 1902 uint32_t config, orig, id; 1903 nid_t cad, nid; 1904 1905 sc = w->devinfo->codec->sc; 1906 cad = w->devinfo->codec->cad; 1907 nid = w->nid; 1908 id = hdac_codec_id(w->devinfo); 1909 1910 config = hdac_command(sc, 1911 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1912 cad); 1913 orig = config; 1914 1915 /* 1916 * XXX REWRITE!!!! Don't argue! 1917 */ 1918 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1919 switch (nid) { 1920 case 26: 1921 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1922 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1923 break; 1924 case 27: 1925 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1926 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1927 break; 1928 default: 1929 break; 1930 } 1931 } else if (id == HDA_CODEC_ALC880 && 1932 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1933 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1934 /* 1935 * Super broken BIOS 1936 */ 1937 switch (nid) { 1938 case 20: 1939 break; 1940 case 21: 1941 break; 1942 case 22: 1943 break; 1944 case 23: 1945 break; 1946 case 24: /* MIC1 */ 1947 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1948 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1949 break; 1950 case 25: /* XXX MIC2 */ 1951 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1952 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1953 break; 1954 case 26: /* LINE1 */ 1955 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1956 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1957 break; 1958 case 27: /* XXX LINE2 */ 1959 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1960 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1961 break; 1962 case 28: /* CD */ 1963 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1964 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1965 break; 1966 case 30: 1967 break; 1968 case 31: 1969 break; 1970 default: 1971 break; 1972 } 1973 } else if (id == HDA_CODEC_ALC883 && 1974 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1975 switch (nid) { 1976 case 25: 1977 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1978 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1979 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1980 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1981 break; 1982 case 28: 1983 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1984 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1985 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1986 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1987 break; 1988 default: 1989 break; 1990 } 1991 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1992 HP_V3000_SUBVENDOR) { 1993 switch (nid) { 1994 case 18: 1995 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1996 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1997 break; 1998 case 20: 1999 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2000 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2001 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2002 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2003 break; 2004 case 21: 2005 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2006 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2007 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2008 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2009 break; 2010 default: 2011 break; 2012 } 2013 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor == 2014 HP_DV5000_SUBVENDOR) { 2015 switch (nid) { 2016 case 20: 2017 case 21: 2018 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2019 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2020 break; 2021 default: 2022 break; 2023 } 2024 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2025 ASUS_W6F_SUBVENDOR) { 2026 switch (nid) { 2027 case 11: 2028 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2029 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2030 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2031 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2032 break; 2033 case 15: 2034 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2035 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2036 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2037 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2038 break; 2039 default: 2040 break; 2041 } 2042 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2043 UNIWILL_9075_SUBVENDOR) { 2044 switch (nid) { 2045 case 15: 2046 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2047 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2048 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2049 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2050 break; 2051 default: 2052 break; 2053 } 2054 } else if (id == HDA_CODEC_AD1986A && sc->pci_subvendor == 2055 ASUS_M2NPVMX_SUBVENDOR) { 2056 switch (nid) { 2057 case 28: /* LINE */ 2058 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2059 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2060 break; 2061 case 29: /* MIC */ 2062 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2063 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2064 break; 2065 default: 2066 break; 2067 } 2068 } 2069 2070 HDA_BOOTVERBOSE( 2071 if (config != orig) 2072 device_printf(sc->dev, 2073 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 2074 nid, orig, config); 2075 ); 2076 2077 return (config); 2078} 2079 2080static uint32_t 2081hdac_widget_pin_getcaps(struct hdac_widget *w) 2082{ 2083 struct hdac_softc *sc; 2084 uint32_t caps, orig, id; 2085 nid_t cad, nid; 2086 2087 sc = w->devinfo->codec->sc; 2088 cad = w->devinfo->codec->cad; 2089 nid = w->nid; 2090 id = hdac_codec_id(w->devinfo); 2091 2092 caps = hdac_command(sc, 2093 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2094 orig = caps; 2095 2096 HDA_BOOTVERBOSE( 2097 if (caps != orig) 2098 device_printf(sc->dev, 2099 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 2100 nid, orig, caps); 2101 ); 2102 2103 return (caps); 2104} 2105 2106static void 2107hdac_widget_pin_parse(struct hdac_widget *w) 2108{ 2109 struct hdac_softc *sc = w->devinfo->codec->sc; 2110 uint32_t config, pincap; 2111 char *devstr, *connstr; 2112 nid_t cad = w->devinfo->codec->cad; 2113 nid_t nid = w->nid; 2114 2115 config = hdac_widget_pin_getconfig(w); 2116 w->wclass.pin.config = config; 2117 2118 pincap = hdac_widget_pin_getcaps(w); 2119 w->wclass.pin.cap = pincap; 2120 2121 w->wclass.pin.ctrl = hdac_command(sc, 2122 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 2123 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 2124 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 2125 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 2126 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 2127 2128 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 2129 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 2130 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 2131 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 2132 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 2133 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 2134 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2135 w->param.eapdbtl = hdac_command(sc, 2136 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2137 w->param.eapdbtl &= 0x7; 2138 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2139 } else 2140 w->param.eapdbtl = HDAC_INVALID; 2141 2142 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 2143 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 2144 devstr = "line out"; 2145 break; 2146 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 2147 devstr = "speaker"; 2148 break; 2149 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 2150 devstr = "headphones out"; 2151 break; 2152 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 2153 devstr = "CD"; 2154 break; 2155 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 2156 devstr = "SPDIF out"; 2157 break; 2158 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 2159 devstr = "digital (other) out"; 2160 break; 2161 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 2162 devstr = "modem, line side"; 2163 break; 2164 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 2165 devstr = "modem, handset side"; 2166 break; 2167 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 2168 devstr = "line in"; 2169 break; 2170 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 2171 devstr = "AUX"; 2172 break; 2173 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 2174 devstr = "Mic in"; 2175 break; 2176 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 2177 devstr = "telephony"; 2178 break; 2179 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 2180 devstr = "SPDIF in"; 2181 break; 2182 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 2183 devstr = "digital (other) in"; 2184 break; 2185 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 2186 devstr = "other"; 2187 break; 2188 default: 2189 devstr = "unknown"; 2190 break; 2191 } 2192 2193 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 2194 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 2195 connstr = "jack"; 2196 break; 2197 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 2198 connstr = "none"; 2199 break; 2200 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 2201 connstr = "fixed"; 2202 break; 2203 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 2204 connstr = "jack / fixed"; 2205 break; 2206 default: 2207 connstr = "unknown"; 2208 break; 2209 } 2210 2211 strlcat(w->name, ": ", sizeof(w->name)); 2212 strlcat(w->name, devstr, sizeof(w->name)); 2213 strlcat(w->name, " (", sizeof(w->name)); 2214 strlcat(w->name, connstr, sizeof(w->name)); 2215 strlcat(w->name, ")", sizeof(w->name)); 2216} 2217 2218static void 2219hdac_widget_parse(struct hdac_widget *w) 2220{ 2221 struct hdac_softc *sc = w->devinfo->codec->sc; 2222 uint32_t wcap, cap; 2223 char *typestr; 2224 nid_t cad = w->devinfo->codec->cad; 2225 nid_t nid = w->nid; 2226 2227 wcap = hdac_command(sc, 2228 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2229 cad); 2230 w->param.widget_cap = wcap; 2231 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2232 2233 switch (w->type) { 2234 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2235 typestr = "audio output"; 2236 break; 2237 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2238 typestr = "audio input"; 2239 break; 2240 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2241 typestr = "audio mixer"; 2242 break; 2243 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2244 typestr = "audio selector"; 2245 break; 2246 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2247 typestr = "pin"; 2248 break; 2249 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2250 typestr = "power widget"; 2251 break; 2252 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2253 typestr = "volume widget"; 2254 break; 2255 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2256 typestr = "beep widget"; 2257 break; 2258 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2259 typestr = "vendor widget"; 2260 break; 2261 default: 2262 typestr = "unknown type"; 2263 break; 2264 } 2265 2266 strlcpy(w->name, typestr, sizeof(w->name)); 2267 2268 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2269 hdac_command(sc, 2270 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2271 cad); 2272 DELAY(1000); 2273 } 2274 2275 hdac_widget_connection_parse(w); 2276 2277 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2278 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2279 w->param.outamp_cap = 2280 hdac_command(sc, 2281 HDA_CMD_GET_PARAMETER(cad, nid, 2282 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2283 else 2284 w->param.outamp_cap = 2285 w->devinfo->function.audio.outamp_cap; 2286 } else 2287 w->param.outamp_cap = 0; 2288 2289 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2290 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2291 w->param.inamp_cap = 2292 hdac_command(sc, 2293 HDA_CMD_GET_PARAMETER(cad, nid, 2294 HDA_PARAM_INPUT_AMP_CAP), cad); 2295 else 2296 w->param.inamp_cap = 2297 w->devinfo->function.audio.inamp_cap; 2298 } else 2299 w->param.inamp_cap = 0; 2300 2301 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2302 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2303 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2304 cap = hdac_command(sc, 2305 HDA_CMD_GET_PARAMETER(cad, nid, 2306 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2307 w->param.supp_stream_formats = (cap != 0) ? cap : 2308 w->devinfo->function.audio.supp_stream_formats; 2309 cap = hdac_command(sc, 2310 HDA_CMD_GET_PARAMETER(cad, nid, 2311 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2312 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2313 w->devinfo->function.audio.supp_pcm_size_rate; 2314 } else { 2315 w->param.supp_stream_formats = 2316 w->devinfo->function.audio.supp_stream_formats; 2317 w->param.supp_pcm_size_rate = 2318 w->devinfo->function.audio.supp_pcm_size_rate; 2319 } 2320 } else { 2321 w->param.supp_stream_formats = 0; 2322 w->param.supp_pcm_size_rate = 0; 2323 } 2324 2325 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2326 hdac_widget_pin_parse(w); 2327} 2328 2329static struct hdac_widget * 2330hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2331{ 2332 if (devinfo == NULL || devinfo->widget == NULL || 2333 nid < devinfo->startnode || nid >= devinfo->endnode) 2334 return (NULL); 2335 return (&devinfo->widget[nid - devinfo->startnode]); 2336} 2337 2338static __inline int 2339hda_poll_channel(struct hdac_chan *ch) 2340{ 2341 uint32_t sz, delta; 2342 volatile uint32_t ptr; 2343 2344 if (ch->active == 0) 2345 return (0); 2346 2347 sz = ch->blksz * ch->blkcnt; 2348 if (ch->dmapos != NULL) 2349 ptr = *(ch->dmapos); 2350 else 2351 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2352 ch->off + HDAC_SDLPIB); 2353 ch->ptr = ptr; 2354 ptr %= sz; 2355 ptr &= ~(ch->blksz - 1); 2356 delta = (sz + ptr - ch->prevptr) % sz; 2357 2358 if (delta < ch->blksz) 2359 return (0); 2360 2361 ch->prevptr = ptr; 2362 2363 return (1); 2364} 2365 2366#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2367 2368static void 2369hda_poll_callback(void *arg) 2370{ 2371 struct hdac_softc *sc = arg; 2372 uint32_t trigger = 0; 2373 2374 if (sc == NULL) 2375 return; 2376 2377 hdac_lock(sc); 2378 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2379 hdac_unlock(sc); 2380 return; 2381 } 2382 2383 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2384 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2385 2386 /* XXX */ 2387 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2388 hda_poll_callback, sc); 2389 2390 hdac_unlock(sc); 2391 2392 if (trigger & 1) 2393 chn_intr(sc->play.c); 2394 if (trigger & 2) 2395 chn_intr(sc->rec.c); 2396} 2397 2398static int 2399hdac_rirb_flush(struct hdac_softc *sc) 2400{ 2401 struct hdac_rirb *rirb_base, *rirb; 2402 struct hdac_codec *codec; 2403 struct hdac_command_list *commands; 2404 nid_t cad; 2405 uint32_t resp; 2406 uint8_t rirbwp; 2407 int ret = 0; 2408 2409 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2410 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2411#if 0 2412 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2413 BUS_DMASYNC_POSTREAD); 2414#endif 2415 2416 while (sc->rirb_rp != rirbwp) { 2417 sc->rirb_rp++; 2418 sc->rirb_rp %= sc->rirb_size; 2419 rirb = &rirb_base[sc->rirb_rp]; 2420 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2421 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2422 sc->codecs[cad] == NULL) 2423 continue; 2424 resp = rirb->response; 2425 codec = sc->codecs[cad]; 2426 commands = codec->commands; 2427 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2428 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2429 ((resp >> 26) & 0xffff); 2430 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2431 } else if (commands != NULL && commands->num_commands > 0 && 2432 codec->responses_received < commands->num_commands) 2433 commands->responses[codec->responses_received++] = 2434 resp; 2435 ret++; 2436 } 2437 2438 return (ret); 2439} 2440 2441static int 2442hdac_unsolq_flush(struct hdac_softc *sc) 2443{ 2444 nid_t cad; 2445 uint32_t tag; 2446 int ret = 0; 2447 2448 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2449 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2450 while (sc->unsolq_rp != sc->unsolq_wp) { 2451 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2452 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2453 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2454 hdac_unsolicited_handler(sc->codecs[cad], tag); 2455 ret++; 2456 } 2457 sc->unsolq_st = HDAC_UNSOLQ_READY; 2458 } 2459 2460 return (ret); 2461} 2462 2463static void 2464hdac_poll_callback(void *arg) 2465{ 2466 struct hdac_softc *sc = arg; 2467 if (sc == NULL) 2468 return; 2469 2470 hdac_lock(sc); 2471 if (sc->polling == 0 || sc->poll_ival == 0) { 2472 hdac_unlock(sc); 2473 return; 2474 } 2475 hdac_rirb_flush(sc); 2476 hdac_unsolq_flush(sc); 2477 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2478 hdac_unlock(sc); 2479} 2480 2481static void 2482hdac_stream_stop(struct hdac_chan *ch) 2483{ 2484 struct hdac_softc *sc = ch->devinfo->codec->sc; 2485 uint32_t ctl; 2486 2487 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2488 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2489 HDAC_SDCTL_RUN); 2490 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2491 2492 ch->active = 0; 2493 2494 if (sc->polling != 0) { 2495 int pollticks; 2496 2497 if (hda_chan_active(sc) == 0) { 2498 callout_stop(&sc->poll_hda); 2499 sc->poll_ticks = 1; 2500 } else { 2501 if (sc->play.active != 0) 2502 ch = &sc->play; 2503 else 2504 ch = &sc->rec; 2505 pollticks = ((uint64_t)hz * ch->blksz) / 2506 ((uint64_t)sndbuf_getbps(ch->b) * 2507 sndbuf_getspd(ch->b)); 2508 pollticks >>= 2; 2509 if (pollticks > hz) 2510 pollticks = hz; 2511 if (pollticks < 1) { 2512 HDA_BOOTVERBOSE( 2513 device_printf(sc->dev, 2514 "%s: pollticks=%d < 1 !\n", 2515 __func__, pollticks); 2516 ); 2517 pollticks = 1; 2518 } 2519 if (pollticks > sc->poll_ticks) { 2520 HDA_BOOTVERBOSE( 2521 device_printf(sc->dev, 2522 "%s: pollticks %d -> %d\n", 2523 __func__, sc->poll_ticks, 2524 pollticks); 2525 ); 2526 sc->poll_ticks = pollticks; 2527 callout_reset(&sc->poll_hda, 1, 2528 hda_poll_callback, sc); 2529 } 2530 } 2531 } else { 2532 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2533 ctl &= ~(1 << (ch->off >> 5)); 2534 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2535 } 2536} 2537 2538static void 2539hdac_stream_start(struct hdac_chan *ch) 2540{ 2541 struct hdac_softc *sc = ch->devinfo->codec->sc; 2542 uint32_t ctl; 2543 2544 if (sc->polling != 0) { 2545 int pollticks; 2546 2547 pollticks = ((uint64_t)hz * ch->blksz) / 2548 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2549 pollticks >>= 2; 2550 if (pollticks > hz) 2551 pollticks = hz; 2552 if (pollticks < 1) { 2553 HDA_BOOTVERBOSE( 2554 device_printf(sc->dev, 2555 "%s: pollticks=%d < 1 !\n", 2556 __func__, pollticks); 2557 ); 2558 pollticks = 1; 2559 } 2560 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2561 HDA_BOOTVERBOSE( 2562 if (hda_chan_active(sc) == 0) { 2563 device_printf(sc->dev, 2564 "%s: pollticks=%d\n", 2565 __func__, pollticks); 2566 } else { 2567 device_printf(sc->dev, 2568 "%s: pollticks %d -> %d\n", 2569 __func__, sc->poll_ticks, 2570 pollticks); 2571 } 2572 ); 2573 sc->poll_ticks = pollticks; 2574 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2575 sc); 2576 } 2577 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2578 ctl |= HDAC_SDCTL_RUN; 2579 } else { 2580 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2581 ctl |= 1 << (ch->off >> 5); 2582 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2583 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2584 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2585 HDAC_SDCTL_RUN; 2586 } 2587 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2588 2589 ch->active = 1; 2590} 2591 2592static void 2593hdac_stream_reset(struct hdac_chan *ch) 2594{ 2595 struct hdac_softc *sc = ch->devinfo->codec->sc; 2596 int timeout = 1000; 2597 int to = timeout; 2598 uint32_t ctl; 2599 2600 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2601 ctl |= HDAC_SDCTL_SRST; 2602 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2603 do { 2604 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2605 if (ctl & HDAC_SDCTL_SRST) 2606 break; 2607 DELAY(10); 2608 } while (--to); 2609 if (!(ctl & HDAC_SDCTL_SRST)) { 2610 device_printf(sc->dev, "timeout in reset\n"); 2611 } 2612 ctl &= ~HDAC_SDCTL_SRST; 2613 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2614 to = timeout; 2615 do { 2616 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2617 if (!(ctl & HDAC_SDCTL_SRST)) 2618 break; 2619 DELAY(10); 2620 } while (--to); 2621 if (ctl & HDAC_SDCTL_SRST) 2622 device_printf(sc->dev, "can't reset!\n"); 2623} 2624 2625static void 2626hdac_stream_setid(struct hdac_chan *ch) 2627{ 2628 struct hdac_softc *sc = ch->devinfo->codec->sc; 2629 uint32_t ctl; 2630 2631 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2632 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2633 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2634 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2635} 2636 2637static void 2638hdac_bdl_setup(struct hdac_chan *ch) 2639{ 2640 struct hdac_softc *sc = ch->devinfo->codec->sc; 2641 struct hdac_bdle *bdle; 2642 uint64_t addr; 2643 uint32_t blksz, blkcnt; 2644 int i; 2645 2646 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2647 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2648 2649 if (sc->polling != 0) { 2650 blksz = ch->blksz * ch->blkcnt; 2651 blkcnt = 1; 2652 } else { 2653 blksz = ch->blksz; 2654 blkcnt = ch->blkcnt; 2655 } 2656 2657 for (i = 0; i < blkcnt; i++, bdle++) { 2658 bdle->addrl = (uint32_t)addr; 2659 bdle->addrh = (uint32_t)(addr >> 32); 2660 bdle->len = blksz; 2661 bdle->ioc = 1 ^ sc->polling; 2662 addr += blksz; 2663 } 2664 2665 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2666 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2667 addr = ch->bdl_dma.dma_paddr; 2668 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2669 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2670 if (ch->dmapos != NULL && 2671 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 2672 addr = sc->pos_dma.dma_paddr; 2673 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 2674 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 2675 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 2676 } 2677} 2678 2679static int 2680hdac_bdl_alloc(struct hdac_chan *ch) 2681{ 2682 struct hdac_softc *sc = ch->devinfo->codec->sc; 2683 int rc; 2684 2685 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2686 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2687 if (rc) { 2688 device_printf(sc->dev, "can't alloc bdl\n"); 2689 return (rc); 2690 } 2691 2692 return (0); 2693} 2694 2695static void 2696hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2697 int index, int lmute, int rmute, 2698 int left, int right, int dir) 2699{ 2700 uint16_t v = 0; 2701 2702 if (sc == NULL) 2703 return; 2704 2705 if (left != right || lmute != rmute) { 2706 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2707 (lmute << 7) | left; 2708 hdac_command(sc, 2709 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2710 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2711 (rmute << 7) | right; 2712 } else 2713 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2714 (lmute << 7) | left; 2715 2716 hdac_command(sc, 2717 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2718} 2719 2720static void 2721hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2722 int left, int right) 2723{ 2724 struct hdac_softc *sc; 2725 nid_t nid, cad; 2726 int lmute, rmute; 2727 2728 if (ctl == NULL || ctl->widget == NULL || 2729 ctl->widget->devinfo == NULL || 2730 ctl->widget->devinfo->codec == NULL || 2731 ctl->widget->devinfo->codec->sc == NULL) 2732 return; 2733 2734 sc = ctl->widget->devinfo->codec->sc; 2735 cad = ctl->widget->devinfo->codec->cad; 2736 nid = ctl->widget->nid; 2737 2738 if (mute == HDA_AMP_MUTE_DEFAULT) { 2739 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2740 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2741 } else { 2742 lmute = HDA_AMP_LEFT_MUTED(mute); 2743 rmute = HDA_AMP_RIGHT_MUTED(mute); 2744 } 2745 2746 if (ctl->dir & HDA_CTL_OUT) 2747 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2748 lmute, rmute, left, right, 0); 2749 if (ctl->dir & HDA_CTL_IN) 2750 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2751 lmute, rmute, left, right, 1); 2752 ctl->left = left; 2753 ctl->right = right; 2754} 2755 2756static void 2757hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2758{ 2759 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2760 return; 2761 hdac_command(w->devinfo->codec->sc, 2762 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2763 w->nid, index), w->devinfo->codec->cad); 2764 w->selconn = index; 2765} 2766 2767 2768/**************************************************************************** 2769 * uint32_t hdac_command_sendone_internal 2770 * 2771 * Wrapper function that sends only one command to a given codec 2772 ****************************************************************************/ 2773static uint32_t 2774hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2775{ 2776 struct hdac_command_list cl; 2777 uint32_t response = HDAC_INVALID; 2778 2779 if (!hdac_lockowned(sc)) 2780 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2781 cl.num_commands = 1; 2782 cl.verbs = &verb; 2783 cl.responses = &response; 2784 2785 hdac_command_send_internal(sc, &cl, cad); 2786 2787 return (response); 2788} 2789 2790/**************************************************************************** 2791 * hdac_command_send_internal 2792 * 2793 * Send a command list to the codec via the corb. We queue as much verbs as 2794 * we can and msleep on the codec. When the interrupt get the responses 2795 * back from the rirb, it will wake us up so we can queue the remaining verbs 2796 * if any. 2797 ****************************************************************************/ 2798static void 2799hdac_command_send_internal(struct hdac_softc *sc, 2800 struct hdac_command_list *commands, nid_t cad) 2801{ 2802 struct hdac_codec *codec; 2803 int corbrp; 2804 uint32_t *corb; 2805 int timeout; 2806 int retry = 10; 2807 struct hdac_rirb *rirb_base; 2808 2809 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2810 commands->num_commands < 1) 2811 return; 2812 2813 codec = sc->codecs[cad]; 2814 codec->commands = commands; 2815 codec->responses_received = 0; 2816 codec->verbs_sent = 0; 2817 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2818 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2819 2820 do { 2821 if (codec->verbs_sent != commands->num_commands) { 2822 /* Queue as many verbs as possible */ 2823 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2824#if 0 2825 bus_dmamap_sync(sc->corb_dma.dma_tag, 2826 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2827#endif 2828 while (codec->verbs_sent != commands->num_commands && 2829 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2830 sc->corb_wp++; 2831 sc->corb_wp %= sc->corb_size; 2832 corb[sc->corb_wp] = 2833 commands->verbs[codec->verbs_sent++]; 2834 } 2835 2836 /* Send the verbs to the codecs */ 2837#if 0 2838 bus_dmamap_sync(sc->corb_dma.dma_tag, 2839 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2840#endif 2841 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2842 } 2843 2844 timeout = 1000; 2845 while (hdac_rirb_flush(sc) == 0 && --timeout) 2846 DELAY(10); 2847 } while ((codec->verbs_sent != commands->num_commands || 2848 codec->responses_received != commands->num_commands) && --retry); 2849 2850 if (retry == 0) 2851 device_printf(sc->dev, 2852 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2853 __func__, commands->num_commands, codec->verbs_sent, 2854 codec->responses_received); 2855 2856 codec->commands = NULL; 2857 codec->responses_received = 0; 2858 codec->verbs_sent = 0; 2859 2860 hdac_unsolq_flush(sc); 2861} 2862 2863 2864/**************************************************************************** 2865 * Device Methods 2866 ****************************************************************************/ 2867 2868/**************************************************************************** 2869 * int hdac_probe(device_t) 2870 * 2871 * Probe for the presence of an hdac. If none is found, check for a generic 2872 * match using the subclass of the device. 2873 ****************************************************************************/ 2874static int 2875hdac_probe(device_t dev) 2876{ 2877 int i, result; 2878 uint32_t model; 2879 uint16_t class, subclass; 2880 char desc[64]; 2881 2882 model = (uint32_t)pci_get_device(dev) << 16; 2883 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2884 class = pci_get_class(dev); 2885 subclass = pci_get_subclass(dev); 2886 2887 bzero(desc, sizeof(desc)); 2888 result = ENXIO; 2889 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2890 if (hdac_devices[i].model == model) { 2891 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2892 result = BUS_PROBE_DEFAULT; 2893 break; 2894 } 2895 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2896 class == PCIC_MULTIMEDIA && 2897 subclass == PCIS_MULTIMEDIA_HDA) { 2898 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2899 result = BUS_PROBE_GENERIC; 2900 break; 2901 } 2902 } 2903 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2904 subclass == PCIS_MULTIMEDIA_HDA) { 2905 strlcpy(desc, "Generic", sizeof(desc)); 2906 result = BUS_PROBE_GENERIC; 2907 } 2908 if (result != ENXIO) { 2909 strlcat(desc, " High Definition Audio Controller", 2910 sizeof(desc)); 2911 device_set_desc_copy(dev, desc); 2912 } 2913 2914 return (result); 2915} 2916 2917static void * 2918hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2919 struct pcm_channel *c, int dir) 2920{ 2921 struct hdac_devinfo *devinfo = data; 2922 struct hdac_softc *sc = devinfo->codec->sc; 2923 struct hdac_chan *ch; 2924 2925 hdac_lock(sc); 2926 if (dir == PCMDIR_PLAY) { 2927 ch = &sc->play; 2928 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2929 devinfo->function.audio.playcnt++; 2930 } else { 2931 ch = &sc->rec; 2932 ch->off = devinfo->function.audio.reccnt << 5; 2933 devinfo->function.audio.reccnt++; 2934 } 2935 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2936 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2937 ch->pcmrates[0] = 48000; 2938 ch->pcmrates[1] = 0; 2939 } 2940 if (sc->pos_dma.dma_vaddr != NULL) 2941 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 2942 (sc->streamcnt * 8)); 2943 else 2944 ch->dmapos = NULL; 2945 ch->sid = ++sc->streamcnt; 2946 ch->dir = dir; 2947 ch->b = b; 2948 ch->c = c; 2949 ch->devinfo = devinfo; 2950 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2951 ch->blkcnt = sc->chan_blkcnt; 2952 hdac_unlock(sc); 2953 2954 if (hdac_bdl_alloc(ch) != 0) { 2955 ch->blkcnt = 0; 2956 return (NULL); 2957 } 2958 2959 if (sndbuf_alloc(ch->b, sc->chan_dmat, 2960 (sc->nocache != 0) ? BUS_DMA_NOCACHE : 0, sc->chan_size) != 0) 2961 return (NULL); 2962 2963 return (ch); 2964} 2965 2966static int 2967hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2968{ 2969 struct hdac_chan *ch = data; 2970 int i; 2971 2972 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2973 if (format == ch->caps.fmtlist[i]) { 2974 ch->fmt = format; 2975 return (0); 2976 } 2977 } 2978 2979 return (EINVAL); 2980} 2981 2982static int 2983hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2984{ 2985 struct hdac_chan *ch = data; 2986 uint32_t spd = 0, threshold; 2987 int i; 2988 2989 for (i = 0; ch->pcmrates[i] != 0; i++) { 2990 spd = ch->pcmrates[i]; 2991 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2992 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2993 if (speed < threshold) 2994 break; 2995 } 2996 2997 if (spd == 0) /* impossible */ 2998 ch->spd = 48000; 2999 else 3000 ch->spd = spd; 3001 3002 return (ch->spd); 3003} 3004 3005static void 3006hdac_stream_setup(struct hdac_chan *ch) 3007{ 3008 struct hdac_softc *sc = ch->devinfo->codec->sc; 3009 int i; 3010 nid_t cad = ch->devinfo->codec->cad; 3011 uint16_t fmt; 3012 3013 fmt = 0; 3014 if (ch->fmt & AFMT_S16_LE) 3015 fmt |= ch->bit16 << 4; 3016 else if (ch->fmt & AFMT_S32_LE) 3017 fmt |= ch->bit32 << 4; 3018 else 3019 fmt |= 1 << 4; 3020 3021 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3022 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3023 fmt |= hda_rate_tab[i].base; 3024 fmt |= hda_rate_tab[i].mul; 3025 fmt |= hda_rate_tab[i].div; 3026 break; 3027 } 3028 } 3029 3030 if (ch->fmt & AFMT_STEREO) 3031 fmt |= 1; 3032 3033 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3034 3035 for (i = 0; ch->io[i] != -1; i++) { 3036 HDA_BOOTVERBOSE( 3037 device_printf(sc->dev, 3038 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 3039 "fmt=0x%08x\n", 3040 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3041 ch->io[i], fmt); 3042 ); 3043 hdac_command(sc, 3044 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3045 hdac_command(sc, 3046 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3047 ch->sid << 4), cad); 3048 } 3049} 3050 3051static int 3052hdac_channel_setfragments(kobj_t obj, void *data, 3053 uint32_t blksz, uint32_t blkcnt) 3054{ 3055 struct hdac_chan *ch = data; 3056 struct hdac_softc *sc = ch->devinfo->codec->sc; 3057 3058 blksz &= HDA_BLK_ALIGN; 3059 3060 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3061 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3062 if (blksz < HDA_BLK_MIN) 3063 blksz = HDA_BLK_MIN; 3064 if (blkcnt > HDA_BDL_MAX) 3065 blkcnt = HDA_BDL_MAX; 3066 if (blkcnt < HDA_BDL_MIN) 3067 blkcnt = HDA_BDL_MIN; 3068 3069 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3070 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3071 blkcnt >>= 1; 3072 else if ((blksz >> 1) >= HDA_BLK_MIN) 3073 blksz >>= 1; 3074 else 3075 break; 3076 } 3077 3078 if ((sndbuf_getblksz(ch->b) != blksz || 3079 sndbuf_getblkcnt(ch->b) != blkcnt) && 3080 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3081 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3082 __func__, blksz, blkcnt); 3083 3084 ch->blksz = sndbuf_getblksz(ch->b); 3085 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3086 3087 return (1); 3088} 3089 3090static int 3091hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3092{ 3093 struct hdac_chan *ch = data; 3094 struct hdac_softc *sc = ch->devinfo->codec->sc; 3095 3096 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 3097 3098 return (ch->blksz); 3099} 3100 3101static void 3102hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3103{ 3104 struct hdac_devinfo *devinfo = ch->devinfo; 3105 nid_t cad = devinfo->codec->cad; 3106 int i; 3107 3108 hdac_stream_stop(ch); 3109 3110 for (i = 0; ch->io[i] != -1; i++) { 3111 hdac_command(sc, 3112 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3113 0), cad); 3114 } 3115} 3116 3117static void 3118hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3119{ 3120 ch->ptr = 0; 3121 ch->prevptr = 0; 3122 hdac_stream_stop(ch); 3123 hdac_stream_reset(ch); 3124 hdac_bdl_setup(ch); 3125 hdac_stream_setid(ch); 3126 hdac_stream_setup(ch); 3127 hdac_stream_start(ch); 3128} 3129 3130static int 3131hdac_channel_trigger(kobj_t obj, void *data, int go) 3132{ 3133 struct hdac_chan *ch = data; 3134 struct hdac_softc *sc = ch->devinfo->codec->sc; 3135 3136 hdac_lock(sc); 3137 switch (go) { 3138 case PCMTRIG_START: 3139 hdac_channel_start(sc, ch); 3140 break; 3141 case PCMTRIG_STOP: 3142 case PCMTRIG_ABORT: 3143 hdac_channel_stop(sc, ch); 3144 break; 3145 default: 3146 break; 3147 } 3148 hdac_unlock(sc); 3149 3150 return (0); 3151} 3152 3153static int 3154hdac_channel_getptr(kobj_t obj, void *data) 3155{ 3156 struct hdac_chan *ch = data; 3157 struct hdac_softc *sc = ch->devinfo->codec->sc; 3158 uint32_t ptr; 3159 3160 hdac_lock(sc); 3161 if (sc->polling != 0) 3162 ptr = ch->ptr; 3163 else if (ch->dmapos != NULL) 3164 ptr = *(ch->dmapos); 3165 else 3166 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3167 hdac_unlock(sc); 3168 3169 /* 3170 * Round to available space and force 128 bytes aligment. 3171 */ 3172 ptr %= ch->blksz * ch->blkcnt; 3173 ptr &= HDA_BLK_ALIGN; 3174 3175 return (ptr); 3176} 3177 3178static struct pcmchan_caps * 3179hdac_channel_getcaps(kobj_t obj, void *data) 3180{ 3181 return (&((struct hdac_chan *)data)->caps); 3182} 3183 3184static kobj_method_t hdac_channel_methods[] = { 3185 KOBJMETHOD(channel_init, hdac_channel_init), 3186 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3187 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3188 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3189 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3190 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3191 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3192 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3193 { 0, 0 } 3194}; 3195CHANNEL_DECLARE(hdac_channel); 3196 3197static void 3198hdac_jack_poll_callback(void *arg) 3199{ 3200 struct hdac_devinfo *devinfo = arg; 3201 struct hdac_softc *sc; 3202 3203 if (devinfo == NULL || devinfo->codec == NULL || 3204 devinfo->codec->sc == NULL) 3205 return; 3206 sc = devinfo->codec->sc; 3207 hdac_lock(sc); 3208 if (sc->poll_ival == 0) { 3209 hdac_unlock(sc); 3210 return; 3211 } 3212 hdac_hp_switch_handler(devinfo); 3213 callout_reset(&sc->poll_jack, sc->poll_ival, 3214 hdac_jack_poll_callback, devinfo); 3215 hdac_unlock(sc); 3216} 3217 3218static int 3219hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3220{ 3221 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3222 struct hdac_softc *sc = devinfo->codec->sc; 3223 struct hdac_widget *w, *cw; 3224 struct hdac_audio_ctl *ctl; 3225 uint32_t mask, recmask, id; 3226 int i, j, softpcmvol; 3227 nid_t cad; 3228 3229 hdac_lock(sc); 3230 3231 mask = 0; 3232 recmask = 0; 3233 3234 id = hdac_codec_id(devinfo); 3235 cad = devinfo->codec->cad; 3236 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 3237 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 3238 sc->pci_subvendor) && hdac_hp_switch[i].id == id)) 3239 continue; 3240 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 3241 if (w == NULL || w->enable == 0 || w->type != 3242 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3243 continue; 3244 if (hdac_hp_switch[i].polling != 0) 3245 callout_reset(&sc->poll_jack, 1, 3246 hdac_jack_poll_callback, devinfo); 3247 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 3248 hdac_command(sc, 3249 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 3250 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 3251 HDAC_UNSOLTAG_EVENT_HP), cad); 3252 else 3253 continue; 3254 hdac_hp_switch_handler(devinfo); 3255 HDA_BOOTVERBOSE( 3256 device_printf(sc->dev, 3257 "HDA_DEBUG: Enabling headphone/speaker " 3258 "audio routing switching:\n"); 3259 device_printf(sc->dev, 3260 "HDA_DEBUG: \tindex=%d nid=%d " 3261 "pci_subvendor=0x%08x " 3262 "codec=0x%08x [%s]\n", 3263 i, w->nid, sc->pci_subvendor, id, 3264 (hdac_hp_switch[i].polling != 0) ? "POLL" : 3265 "UNSOL"); 3266 ); 3267 break; 3268 } 3269 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3270 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3271 sc->pci_subvendor) && 3272 hdac_eapd_switch[i].id == id)) 3273 continue; 3274 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3275 if (w == NULL || w->enable == 0) 3276 break; 3277 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3278 w->param.eapdbtl == HDAC_INVALID) 3279 break; 3280 mask |= SOUND_MASK_OGAIN; 3281 break; 3282 } 3283 3284 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3285 w = hdac_widget_get(devinfo, i); 3286 if (w == NULL || w->enable == 0) 3287 continue; 3288 mask |= w->ctlflags; 3289 if (!(w->pflags & HDA_ADC_RECSEL)) 3290 continue; 3291 for (j = 0; j < w->nconns; j++) { 3292 cw = hdac_widget_get(devinfo, w->conns[j]); 3293 if (cw == NULL || cw->enable == 0) 3294 continue; 3295 recmask |= cw->ctlflags; 3296 } 3297 } 3298 3299 if (!(mask & SOUND_MASK_PCM)) { 3300 softpcmvol = 1; 3301 mask |= SOUND_MASK_PCM; 3302 } else 3303 softpcmvol = (devinfo->function.audio.quirks & 3304 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3305 3306 i = 0; 3307 ctl = NULL; 3308 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3309 if (ctl->widget == NULL || ctl->enable == 0) 3310 continue; 3311 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3312 continue; 3313 if (ctl->step > 0) 3314 break; 3315 } 3316 3317 if (softpcmvol == 1 || ctl == NULL) { 3318 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL); 3319 HDA_BOOTVERBOSE( 3320 device_printf(sc->dev, 3321 "HDA_DEBUG: %s Soft PCM volume\n", 3322 (softpcmvol == 1) ? 3323 "Forcing" : "Enabling"); 3324 ); 3325 i = 0; 3326 /* 3327 * XXX Temporary quirk for STAC9220, until the parser 3328 * become smarter. 3329 */ 3330 if (id == HDA_CODEC_STAC9220) { 3331 mask |= SOUND_MASK_VOLUME; 3332 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3333 NULL) { 3334 if (ctl->widget == NULL || ctl->enable == 0) 3335 continue; 3336 if (ctl->widget->nid == 11 && ctl->index == 0) { 3337 ctl->ossmask = SOUND_MASK_VOLUME; 3338 ctl->ossval = 100 | (100 << 8); 3339 } else 3340 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3341 } 3342 } else if (id == HDA_CODEC_STAC9221) { 3343 mask |= SOUND_MASK_VOLUME; 3344 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3345 NULL) { 3346 if (ctl->widget == NULL) 3347 continue; 3348 if (ctl->widget->type == 3349 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3350 ctl->index == 0 && (ctl->widget->nid == 2 || 3351 ctl->widget->enable != 0)) { 3352 ctl->enable = 1; 3353 ctl->ossmask = SOUND_MASK_VOLUME; 3354 ctl->ossval = 100 | (100 << 8); 3355 } else if (ctl->enable == 0) 3356 continue; 3357 else 3358 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3359 } 3360 } else { 3361 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3362 SOUND_MASK_PCM); 3363 if (!(mask & SOUND_MASK_VOLUME)) 3364 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3365 SOUND_MIXER_NONE); 3366 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3367 NULL) { 3368 if (ctl->widget == NULL || ctl->enable == 0) 3369 continue; 3370 if (!HDA_FLAG_MATCH(ctl->ossmask, 3371 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3372 continue; 3373 if (!(ctl->mute == 1 && ctl->step == 0)) 3374 ctl->enable = 0; 3375 } 3376 } 3377 } 3378 3379 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER | 3380 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN | 3381 SOUND_MASK_OGAIN); 3382 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3383 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3384 3385 mix_setrecdevs(m, recmask); 3386 mix_setdevs(m, mask); 3387 3388 hdac_unlock(sc); 3389 3390 return (0); 3391} 3392 3393static int 3394hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3395 unsigned left, unsigned right) 3396{ 3397 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3398 struct hdac_softc *sc = devinfo->codec->sc; 3399 struct hdac_widget *w; 3400 struct hdac_audio_ctl *ctl; 3401 uint32_t id, mute; 3402 int lvol, rvol, mlvol, mrvol; 3403 int i = 0; 3404 3405 hdac_lock(sc); 3406 if (dev == SOUND_MIXER_OGAIN) { 3407 uint32_t orig; 3408 /*if (left != right || !(left == 0 || left == 1)) { 3409 hdac_unlock(sc); 3410 return (-1); 3411 }*/ 3412 id = hdac_codec_id(devinfo); 3413 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3414 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3415 sc->pci_subvendor) && 3416 hdac_eapd_switch[i].id == id) 3417 break; 3418 } 3419 if (i >= HDAC_EAPD_SWITCH_LEN) { 3420 hdac_unlock(sc); 3421 return (-1); 3422 } 3423 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3424 if (w == NULL || 3425 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3426 w->param.eapdbtl == HDAC_INVALID) { 3427 hdac_unlock(sc); 3428 return (-1); 3429 } 3430 orig = w->param.eapdbtl; 3431 if (left == 0) 3432 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3433 else 3434 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3435 if (orig != w->param.eapdbtl) { 3436 uint32_t val; 3437 3438 if (hdac_eapd_switch[i].hp_switch != 0) 3439 hdac_hp_switch_handler(devinfo); 3440 val = w->param.eapdbtl; 3441 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3442 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3443 hdac_command(sc, 3444 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3445 w->nid, val), devinfo->codec->cad); 3446 } 3447 hdac_unlock(sc); 3448 return (left | (left << 8)); 3449 } 3450 if (dev == SOUND_MIXER_VOLUME) 3451 devinfo->function.audio.mvol = left | (right << 8); 3452 3453 mlvol = devinfo->function.audio.mvol & 0x7f; 3454 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3455 lvol = 0; 3456 rvol = 0; 3457 3458 i = 0; 3459 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3460 if (ctl->widget == NULL || ctl->enable == 0 || 3461 !(ctl->ossmask & (1 << dev))) 3462 continue; 3463 switch (dev) { 3464 case SOUND_MIXER_VOLUME: 3465 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3466 lvol = (lvol * ctl->step) / 100; 3467 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3468 rvol = (rvol * ctl->step) / 100; 3469 break; 3470 default: 3471 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3472 lvol = (left * mlvol) / 100; 3473 lvol = (lvol * ctl->step) / 100; 3474 rvol = (right * mrvol) / 100; 3475 rvol = (rvol * ctl->step) / 100; 3476 } else { 3477 lvol = (left * ctl->step) / 100; 3478 rvol = (right * ctl->step) / 100; 3479 } 3480 ctl->ossval = left | (right << 8); 3481 break; 3482 } 3483 mute = 0; 3484 if (ctl->step < 1) { 3485 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3486 (ctl->muted & HDA_AMP_MUTE_LEFT); 3487 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3488 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3489 } else { 3490 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3491 (ctl->muted & HDA_AMP_MUTE_LEFT); 3492 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3493 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3494 } 3495 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3496 } 3497 hdac_unlock(sc); 3498 3499 return (left | (right << 8)); 3500} 3501 3502static int 3503hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3504{ 3505 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3506 struct hdac_widget *w, *cw; 3507 struct hdac_softc *sc = devinfo->codec->sc; 3508 uint32_t ret = src, target; 3509 int i, j; 3510 3511 target = 0; 3512 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3513 if (src & (1 << i)) { 3514 target = 1 << i; 3515 break; 3516 } 3517 } 3518 3519 hdac_lock(sc); 3520 3521 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3522 w = hdac_widget_get(devinfo, i); 3523 if (w == NULL || w->enable == 0) 3524 continue; 3525 if (!(w->pflags & HDA_ADC_RECSEL)) 3526 continue; 3527 for (j = 0; j < w->nconns; j++) { 3528 cw = hdac_widget_get(devinfo, w->conns[j]); 3529 if (cw == NULL || cw->enable == 0) 3530 continue; 3531 if ((target == SOUND_MASK_VOLUME && 3532 cw->type != 3533 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3534 (target != SOUND_MASK_VOLUME && 3535 cw->type == 3536 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3537 continue; 3538 if (cw->ctlflags & target) { 3539 if (!(w->pflags & HDA_ADC_LOCKED)) 3540 hdac_widget_connection_select(w, j); 3541 ret = target; 3542 j += w->nconns; 3543 } 3544 } 3545 } 3546 3547 hdac_unlock(sc); 3548 3549 return (ret); 3550} 3551 3552static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3553 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3554 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3555 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3556 { 0, 0 } 3557}; 3558MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3559 3560/**************************************************************************** 3561 * int hdac_attach(device_t) 3562 * 3563 * Attach the device into the kernel. Interrupts usually won't be enabled 3564 * when this function is called. Setup everything that doesn't require 3565 * interrupts and defer probing of codecs until interrupts are enabled. 3566 ****************************************************************************/ 3567static int 3568hdac_attach(device_t dev) 3569{ 3570 struct hdac_softc *sc; 3571 int result; 3572 int i; 3573 uint16_t vendor; 3574 uint8_t v; 3575 3576 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3577 if (sc == NULL) { 3578 device_printf(dev, "cannot allocate softc\n"); 3579 return (ENOMEM); 3580 } 3581 3582 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3583 sc->dev = dev; 3584 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3585 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3586 vendor = pci_get_vendor(dev); 3587 3588 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3589 /* Screw nx6325 - subdevice/subvendor swapped */ 3590 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3591 } 3592 3593 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3594 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3595 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 3596 3597 sc->poll_ticks = 1; 3598 sc->poll_ival = HDAC_POLL_INTERVAL; 3599 if (resource_int_value(device_get_name(dev), 3600 device_get_unit(dev), "polling", &i) == 0 && i != 0) 3601 sc->polling = 1; 3602 else 3603 sc->polling = 0; 3604 3605 sc->chan_size = pcm_getbuffersize(dev, 3606 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3607 3608 if (resource_int_value(device_get_name(dev), 3609 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 3610 i &= HDA_BLK_ALIGN; 3611 if (i < HDA_BLK_MIN) 3612 i = HDA_BLK_MIN; 3613 sc->chan_blkcnt = sc->chan_size / i; 3614 i = 0; 3615 while (sc->chan_blkcnt >> i) 3616 i++; 3617 sc->chan_blkcnt = 1 << (i - 1); 3618 if (sc->chan_blkcnt < HDA_BDL_MIN) 3619 sc->chan_blkcnt = HDA_BDL_MIN; 3620 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3621 sc->chan_blkcnt = HDA_BDL_MAX; 3622 } else 3623 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3624 3625 result = bus_dma_tag_create(NULL, /* parent */ 3626 HDAC_DMA_ALIGNMENT, /* alignment */ 3627 0, /* boundary */ 3628 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3629 BUS_SPACE_MAXADDR, /* highaddr */ 3630 NULL, /* filtfunc */ 3631 NULL, /* fistfuncarg */ 3632 sc->chan_size, /* maxsize */ 3633 1, /* nsegments */ 3634 sc->chan_size, /* maxsegsz */ 3635 0, /* flags */ 3636 NULL, /* lockfunc */ 3637 NULL, /* lockfuncarg */ 3638 &sc->chan_dmat); /* dmat */ 3639 if (result != 0) { 3640 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 3641 __func__, result); 3642 snd_mtxfree(sc->lock); 3643 free(sc, M_DEVBUF); 3644 return (ENXIO); 3645 } 3646 3647 3648 sc->hdabus = NULL; 3649 for (i = 0; i < HDAC_CODEC_MAX; i++) 3650 sc->codecs[i] = NULL; 3651 3652 pci_enable_busmaster(dev); 3653 3654 if (vendor == INTEL_VENDORID) { 3655 /* TCSEL -> TC0 */ 3656 v = pci_read_config(dev, 0x44, 1); 3657 pci_write_config(dev, 0x44, v & 0xf8, 1); 3658 HDA_BOOTVERBOSE( 3659 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 3660 pci_read_config(dev, 0x44, 1)); 3661 ); 3662 } 3663 3664#if defined(__i386__) || defined(__amd64__) 3665 sc->nocache = 1; 3666 3667 if (resource_int_value(device_get_name(dev), 3668 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 3669#else 3670 sc->nocache = 0; 3671#endif 3672 /* 3673 * Try to enable PCIe snoop to avoid messing around with 3674 * uncacheable DMA attribute. Since PCIe snoop register 3675 * config is pretty much vendor specific, there are no 3676 * general solutions on how to enable it, forcing us (even 3677 * Microsoft) to enable uncacheable or write combined DMA 3678 * by default. 3679 * 3680 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 3681 */ 3682 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 3683 if (hdac_pcie_snoop[i].vendor != vendor) 3684 continue; 3685 sc->nocache = 0; 3686 if (hdac_pcie_snoop[i].reg == 0x00) 3687 break; 3688 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3689 if ((v & hdac_pcie_snoop[i].enable) == 3690 hdac_pcie_snoop[i].enable) 3691 break; 3692 v &= hdac_pcie_snoop[i].mask; 3693 v |= hdac_pcie_snoop[i].enable; 3694 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 3695 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 3696 if ((v & hdac_pcie_snoop[i].enable) != 3697 hdac_pcie_snoop[i].enable) { 3698 HDA_BOOTVERBOSE( 3699 device_printf(dev, 3700 "WARNING: Failed to enable PCIe " 3701 "snoop!\n"); 3702 ); 3703#if defined(__i386__) || defined(__amd64__) 3704 sc->nocache = 1; 3705#endif 3706 } 3707 break; 3708 } 3709#if defined(__i386__) || defined(__amd64__) 3710 } 3711#endif 3712 3713 HDA_BOOTVERBOSE( 3714 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 3715 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor); 3716 ); 3717 3718 /* Allocate resources */ 3719 result = hdac_mem_alloc(sc); 3720 if (result != 0) 3721 goto hdac_attach_fail; 3722 result = hdac_irq_alloc(sc); 3723 if (result != 0) 3724 goto hdac_attach_fail; 3725 3726 /* Get Capabilities */ 3727 result = hdac_get_capabilities(sc); 3728 if (result != 0) 3729 goto hdac_attach_fail; 3730 3731 /* Allocate CORB and RIRB dma memory */ 3732 result = hdac_dma_alloc(sc, &sc->corb_dma, 3733 sc->corb_size * sizeof(uint32_t)); 3734 if (result != 0) 3735 goto hdac_attach_fail; 3736 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3737 sc->rirb_size * sizeof(struct hdac_rirb)); 3738 if (result != 0) 3739 goto hdac_attach_fail; 3740 3741 /* Quiesce everything */ 3742 hdac_reset(sc); 3743 3744 /* Initialize the CORB and RIRB */ 3745 hdac_corb_init(sc); 3746 hdac_rirb_init(sc); 3747 3748 /* Defer remaining of initialization until interrupts are enabled */ 3749 sc->intrhook.ich_func = hdac_attach2; 3750 sc->intrhook.ich_arg = (void *)sc; 3751 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3752 sc->intrhook.ich_func = NULL; 3753 hdac_attach2((void *)sc); 3754 } 3755 3756 return (0); 3757 3758hdac_attach_fail: 3759 hdac_irq_free(sc); 3760 hdac_dma_free(sc, &sc->rirb_dma); 3761 hdac_dma_free(sc, &sc->corb_dma); 3762 hdac_mem_free(sc); 3763 snd_mtxfree(sc->lock); 3764 free(sc, M_DEVBUF); 3765 3766 return (ENXIO); 3767} 3768 3769static void 3770hdac_audio_parse(struct hdac_devinfo *devinfo) 3771{ 3772 struct hdac_softc *sc = devinfo->codec->sc; 3773 struct hdac_widget *w; 3774 uint32_t res; 3775 int i; 3776 nid_t cad, nid; 3777 3778 cad = devinfo->codec->cad; 3779 nid = devinfo->nid; 3780 3781 hdac_command(sc, 3782 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3783 3784 DELAY(100); 3785 3786 res = hdac_command(sc, 3787 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3788 3789 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3790 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3791 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3792 3793 res = hdac_command(sc, 3794 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 3795 devinfo->function.audio.gpio = res; 3796 3797 HDA_BOOTVERBOSE( 3798 device_printf(sc->dev, " Vendor: 0x%08x\n", 3799 devinfo->vendor_id); 3800 device_printf(sc->dev, " Device: 0x%08x\n", 3801 devinfo->device_id); 3802 device_printf(sc->dev, " Revision: 0x%08x\n", 3803 devinfo->revision_id); 3804 device_printf(sc->dev, " Stepping: 0x%08x\n", 3805 devinfo->stepping_id); 3806 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3807 sc->pci_subvendor); 3808 device_printf(sc->dev, " Nodes: start=%d " 3809 "endnode=%d total=%d\n", 3810 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3811 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 3812 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 3813 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 3814 sc->num_iss, sc->num_oss, sc->num_bss); 3815 device_printf(sc->dev, " GPIO: 0x%08x\n", 3816 devinfo->function.audio.gpio); 3817 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d " 3818 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 3819 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 3820 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 3821 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 3822 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 3823 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 3824 ); 3825 3826 res = hdac_command(sc, 3827 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3828 cad); 3829 devinfo->function.audio.supp_stream_formats = res; 3830 3831 res = hdac_command(sc, 3832 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3833 cad); 3834 devinfo->function.audio.supp_pcm_size_rate = res; 3835 3836 res = hdac_command(sc, 3837 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3838 cad); 3839 devinfo->function.audio.outamp_cap = res; 3840 3841 res = hdac_command(sc, 3842 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3843 cad); 3844 devinfo->function.audio.inamp_cap = res; 3845 3846 if (devinfo->nodecnt > 0) 3847 devinfo->widget = (struct hdac_widget *)malloc( 3848 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3849 M_NOWAIT | M_ZERO); 3850 else 3851 devinfo->widget = NULL; 3852 3853 if (devinfo->widget == NULL) { 3854 device_printf(sc->dev, "unable to allocate widgets!\n"); 3855 devinfo->endnode = devinfo->startnode; 3856 devinfo->nodecnt = 0; 3857 return; 3858 } 3859 3860 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3861 w = hdac_widget_get(devinfo, i); 3862 if (w == NULL) 3863 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3864 else { 3865 w->devinfo = devinfo; 3866 w->nid = i; 3867 w->enable = 1; 3868 w->selconn = -1; 3869 w->pflags = 0; 3870 w->ctlflags = 0; 3871 w->param.eapdbtl = HDAC_INVALID; 3872 hdac_widget_parse(w); 3873 } 3874 } 3875} 3876 3877static void 3878hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3879{ 3880 struct hdac_softc *sc = devinfo->codec->sc; 3881 struct hdac_audio_ctl *ctls; 3882 struct hdac_widget *w, *cw; 3883 int i, j, cnt, max, ocap, icap; 3884 int mute, offset, step, size; 3885 3886 /* XXX This is redundant */ 3887 max = 0; 3888 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3889 w = hdac_widget_get(devinfo, i); 3890 if (w == NULL || w->enable == 0) 3891 continue; 3892 if (w->param.outamp_cap != 0) 3893 max++; 3894 if (w->param.inamp_cap != 0) { 3895 switch (w->type) { 3896 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3897 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3898 for (j = 0; j < w->nconns; j++) { 3899 cw = hdac_widget_get(devinfo, 3900 w->conns[j]); 3901 if (cw == NULL || cw->enable == 0) 3902 continue; 3903 max++; 3904 } 3905 break; 3906 default: 3907 max++; 3908 break; 3909 } 3910 } 3911 } 3912 3913 devinfo->function.audio.ctlcnt = max; 3914 3915 if (max < 1) 3916 return; 3917 3918 ctls = (struct hdac_audio_ctl *)malloc( 3919 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3920 3921 if (ctls == NULL) { 3922 /* Blekh! */ 3923 device_printf(sc->dev, "unable to allocate ctls!\n"); 3924 devinfo->function.audio.ctlcnt = 0; 3925 return; 3926 } 3927 3928 cnt = 0; 3929 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3930 if (cnt >= max) { 3931 device_printf(sc->dev, "%s: Ctl overflow!\n", 3932 __func__); 3933 break; 3934 } 3935 w = hdac_widget_get(devinfo, i); 3936 if (w == NULL || w->enable == 0) 3937 continue; 3938 ocap = w->param.outamp_cap; 3939 icap = w->param.inamp_cap; 3940 if (ocap != 0) { 3941 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3942 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3943 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3944 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3945 /*if (offset > step) { 3946 HDA_BOOTVERBOSE( 3947 device_printf(sc->dev, 3948 "HDA_DEBUG: BUGGY outamp: nid=%d " 3949 "[offset=%d > step=%d]\n", 3950 w->nid, offset, step); 3951 ); 3952 offset = step; 3953 }*/ 3954 ctls[cnt].enable = 1; 3955 ctls[cnt].widget = w; 3956 ctls[cnt].mute = mute; 3957 ctls[cnt].step = step; 3958 ctls[cnt].size = size; 3959 ctls[cnt].offset = offset; 3960 ctls[cnt].left = offset; 3961 ctls[cnt].right = offset; 3962 ctls[cnt++].dir = HDA_CTL_OUT; 3963 } 3964 3965 if (icap != 0) { 3966 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3967 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3968 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3969 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3970 /*if (offset > step) { 3971 HDA_BOOTVERBOSE( 3972 device_printf(sc->dev, 3973 "HDA_DEBUG: BUGGY inamp: nid=%d " 3974 "[offset=%d > step=%d]\n", 3975 w->nid, offset, step); 3976 ); 3977 offset = step; 3978 }*/ 3979 switch (w->type) { 3980 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3981 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3982 for (j = 0; j < w->nconns; j++) { 3983 if (cnt >= max) { 3984 device_printf(sc->dev, 3985 "%s: Ctl overflow!\n", 3986 __func__); 3987 break; 3988 } 3989 cw = hdac_widget_get(devinfo, 3990 w->conns[j]); 3991 if (cw == NULL || cw->enable == 0) 3992 continue; 3993 ctls[cnt].enable = 1; 3994 ctls[cnt].widget = w; 3995 ctls[cnt].childwidget = cw; 3996 ctls[cnt].index = j; 3997 ctls[cnt].mute = mute; 3998 ctls[cnt].step = step; 3999 ctls[cnt].size = size; 4000 ctls[cnt].offset = offset; 4001 ctls[cnt].left = offset; 4002 ctls[cnt].right = offset; 4003 ctls[cnt++].dir = HDA_CTL_IN; 4004 } 4005 break; 4006 default: 4007 if (cnt >= max) { 4008 device_printf(sc->dev, 4009 "%s: Ctl overflow!\n", 4010 __func__); 4011 break; 4012 } 4013 ctls[cnt].enable = 1; 4014 ctls[cnt].widget = w; 4015 ctls[cnt].mute = mute; 4016 ctls[cnt].step = step; 4017 ctls[cnt].size = size; 4018 ctls[cnt].offset = offset; 4019 ctls[cnt].left = offset; 4020 ctls[cnt].right = offset; 4021 ctls[cnt++].dir = HDA_CTL_IN; 4022 break; 4023 } 4024 } 4025 } 4026 4027 devinfo->function.audio.ctl = ctls; 4028} 4029 4030static const struct { 4031 uint32_t model; 4032 uint32_t id; 4033 uint32_t set, unset; 4034} hdac_quirks[] = { 4035 /* 4036 * XXX Force stereo quirk. Monoural recording / playback 4037 * on few codecs (especially ALC880) seems broken or 4038 * perhaps unsupported. 4039 */ 4040 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4041 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4042 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4043 HDA_QUIRK_GPIO0, 0 }, 4044 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4045 HDA_QUIRK_GPIO0, 0 }, 4046 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4047 HDA_QUIRK_GPIO0, 0 }, 4048 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4049 HDA_QUIRK_GPIO0, 0 }, 4050 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4051 HDA_QUIRK_GPIO0, 0 }, 4052 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4053 HDA_QUIRK_EAPDINV, 0 }, 4054 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 4055 HDA_QUIRK_EAPDINV, 0 }, 4056 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4057 HDA_QUIRK_OVREF, 0 }, 4058 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861, 4059 HDA_QUIRK_OVREF, 0 }, 4060 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4061 HDA_QUIRK_OVREF, 0 }, 4062 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4063 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4064 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4065 HDA_QUIRK_GPIO1, 0 }, 4066 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4067 HDA_QUIRK_EAPDINV, 0 }, 4068 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4069 HDA_QUIRK_EAPDINV, 0 }, 4070 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4071 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4072 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4073 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4074 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4075 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4076 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 4077 0, HDA_QUIRK_FORCESTEREO }, 4078 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 4079 HDA_QUIRK_SOFTPCMVOL, 0 } 4080}; 4081#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4082 4083static void 4084hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4085{ 4086 struct hdac_widget *w; 4087 struct hdac_audio_ctl *ctl; 4088 uint32_t id, subvendor; 4089 int i; 4090 4091 id = hdac_codec_id(devinfo); 4092 subvendor = devinfo->codec->sc->pci_subvendor; 4093 4094 /* 4095 * Quirks 4096 */ 4097 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4098 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4099 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4100 continue; 4101 if (hdac_quirks[i].set != 0) 4102 devinfo->function.audio.quirks |= 4103 hdac_quirks[i].set; 4104 if (hdac_quirks[i].unset != 0) 4105 devinfo->function.audio.quirks &= 4106 ~(hdac_quirks[i].unset); 4107 } 4108 4109 switch (id) { 4110 case HDA_CODEC_ALC260: 4111 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4112 w = hdac_widget_get(devinfo, i); 4113 if (w == NULL || w->enable == 0) 4114 continue; 4115 if (w->type != 4116 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4117 continue; 4118 if (w->nid != 5) 4119 w->enable = 0; 4120 } 4121 if (subvendor == HP_XW4300_SUBVENDOR) { 4122 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4123 if (ctl != NULL && ctl->widget != NULL) { 4124 ctl->ossmask = SOUND_MASK_SPEAKER; 4125 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4126 } 4127 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4128 if (ctl != NULL && ctl->widget != NULL) { 4129 ctl->ossmask = SOUND_MASK_SPEAKER; 4130 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4131 } 4132 } else if (subvendor == HP_3010_SUBVENDOR) { 4133 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 4134 if (ctl != NULL && ctl->widget != NULL) { 4135 ctl->ossmask = SOUND_MASK_SPEAKER; 4136 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4137 } 4138 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1); 4139 if (ctl != NULL && ctl->widget != NULL) { 4140 ctl->ossmask = SOUND_MASK_SPEAKER; 4141 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4142 } 4143 } 4144 break; 4145 case HDA_CODEC_ALC861: 4146 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1); 4147 if (ctl != NULL) 4148 ctl->muted = HDA_AMP_MUTE_ALL; 4149 break; 4150 case HDA_CODEC_ALC880: 4151 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4152 w = hdac_widget_get(devinfo, i); 4153 if (w == NULL || w->enable == 0) 4154 continue; 4155 if (w->type == 4156 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4157 w->nid != 9 && w->nid != 29) { 4158 w->enable = 0; 4159 } else if (w->type != 4160 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 4161 w->nid == 29) { 4162 w->type = 4163 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 4164 w->param.widget_cap &= 4165 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 4166 w->param.widget_cap |= 4167 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 4168 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 4169 strlcpy(w->name, "beep widget", sizeof(w->name)); 4170 } 4171 } 4172 break; 4173 case HDA_CODEC_ALC883: 4174 /* 4175 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4176 * Clear vref cap for jack connectivity. 4177 */ 4178 w = hdac_widget_get(devinfo, 24); 4179 if (w != NULL && w->enable != 0 && w->type == 4180 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4181 (w->wclass.pin.config & 4182 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4183 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4184 w->wclass.pin.cap &= ~( 4185 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4186 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4187 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4188 w = hdac_widget_get(devinfo, 25); 4189 if (w != NULL && w->enable != 0 && w->type == 4190 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4191 (w->wclass.pin.config & 4192 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4193 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4194 w->wclass.pin.cap &= ~( 4195 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4196 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4197 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4198 /* 4199 * nid: 26 = Line-in, leave it alone. 4200 */ 4201 break; 4202 case HDA_CODEC_AD1981HD: 4203 w = hdac_widget_get(devinfo, 11); 4204 if (w != NULL && w->enable != 0 && w->nconns > 3) 4205 w->selconn = 3; 4206 if (subvendor == IBM_M52_SUBVENDOR) { 4207 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 4208 if (ctl != NULL) 4209 ctl->ossmask = SOUND_MASK_SPEAKER; 4210 } 4211 break; 4212 case HDA_CODEC_AD1986A: 4213 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4214 w = hdac_widget_get(devinfo, i); 4215 if (w == NULL || w->enable == 0) 4216 continue; 4217 if (w->type != 4218 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4219 continue; 4220 if (w->nid != 3) 4221 w->enable = 0; 4222 } 4223 if (subvendor == ASUS_M2NPVMX_SUBVENDOR) { 4224 /* nid 28 is mic, nid 29 is line-in */ 4225 w = hdac_widget_get(devinfo, 15); 4226 if (w != NULL) 4227 w->selconn = 2; 4228 w = hdac_widget_get(devinfo, 16); 4229 if (w != NULL) 4230 w->selconn = 1; 4231 } 4232 break; 4233 case HDA_CODEC_AD1988: 4234 case HDA_CODEC_AD1988B: 4235 /*w = hdac_widget_get(devinfo, 12); 4236 if (w != NULL) { 4237 w->selconn = 1; 4238 w->pflags |= HDA_ADC_LOCKED; 4239 } 4240 w = hdac_widget_get(devinfo, 13); 4241 if (w != NULL) { 4242 w->selconn = 4; 4243 w->pflags |= HDA_ADC_LOCKED; 4244 } 4245 w = hdac_widget_get(devinfo, 14); 4246 if (w != NULL) { 4247 w->selconn = 2; 4248 w->pflags |= HDA_ADC_LOCKED; 4249 }*/ 4250 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1); 4251 if (ctl != NULL) { 4252 ctl->ossmask = SOUND_MASK_IGAIN; 4253 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4254 } 4255 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1); 4256 if (ctl != NULL) { 4257 ctl->ossmask = SOUND_MASK_IGAIN; 4258 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4259 } 4260 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1); 4261 if (ctl != NULL) { 4262 ctl->ossmask = SOUND_MASK_IGAIN; 4263 ctl->widget->ctlflags |= SOUND_MASK_IGAIN; 4264 } 4265 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1); 4266 if (ctl != NULL) { 4267 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4268 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4269 } 4270 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1); 4271 if (ctl != NULL) { 4272 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4273 ctl->widget->ctlflags |= SOUND_MASK_MIC; 4274 } 4275 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1); 4276 if (ctl != NULL) { 4277 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4278 ctl->widget->ctlflags |= SOUND_MASK_LINE; 4279 } 4280 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1); 4281 if (ctl != NULL) { 4282 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME; 4283 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 4284 } 4285 break; 4286 case HDA_CODEC_STAC9221: 4287 /* 4288 * Dell XPS M1210 need all DACs for each output jacks 4289 */ 4290 if (subvendor == DELL_XPSM1210_SUBVENDOR) 4291 break; 4292 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4293 w = hdac_widget_get(devinfo, i); 4294 if (w == NULL || w->enable == 0) 4295 continue; 4296 if (w->type != 4297 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 4298 continue; 4299 if (w->nid != 2) 4300 w->enable = 0; 4301 } 4302 break; 4303 case HDA_CODEC_STAC9221D: 4304 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4305 w = hdac_widget_get(devinfo, i); 4306 if (w == NULL || w->enable == 0) 4307 continue; 4308 if (w->type == 4309 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4310 w->nid != 6) 4311 w->enable = 0; 4312 4313 } 4314 break; 4315 case HDA_CODEC_STAC9227: 4316 w = hdac_widget_get(devinfo, 8); 4317 if (w != NULL) 4318 w->enable = 0; 4319 w = hdac_widget_get(devinfo, 9); 4320 if (w != NULL) 4321 w->enable = 0; 4322 break; 4323 case HDA_CODEC_CXWAIKIKI: 4324 if (subvendor == HP_DV5000_SUBVENDOR) { 4325 w = hdac_widget_get(devinfo, 27); 4326 if (w != NULL) 4327 w->enable = 0; 4328 } 4329 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 4330 if (ctl != NULL) 4331 ctl->ossmask = SOUND_MASK_SKIP; 4332 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1); 4333 if (ctl != NULL && ctl->childwidget != NULL && 4334 ctl->childwidget->enable != 0) { 4335 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME; 4336 ctl->childwidget->ctlflags |= SOUND_MASK_PCM; 4337 } 4338 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1); 4339 if (ctl != NULL && ctl->childwidget != NULL && 4340 ctl->childwidget->enable != 0) { 4341 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME; 4342 ctl->childwidget->ctlflags |= SOUND_MASK_LINE; 4343 } 4344 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1); 4345 if (ctl != NULL && ctl->childwidget != NULL && 4346 ctl->childwidget->enable != 0) { 4347 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME; 4348 ctl->childwidget->ctlflags |= SOUND_MASK_MIC; 4349 } 4350 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1); 4351 if (ctl != NULL) { 4352 ctl->ossmask = SOUND_MASK_SKIP; 4353 /* XXX mixer \=rec mic broken.. why?!? */ 4354 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */ 4355 } 4356 break; 4357 default: 4358 break; 4359 } 4360} 4361 4362static int 4363hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 4364{ 4365 int *dev = &devinfo->function.audio.ossidx; 4366 4367 while (*dev < SOUND_MIXER_NRDEVICES) { 4368 switch (*dev) { 4369 case SOUND_MIXER_VOLUME: 4370 case SOUND_MIXER_BASS: 4371 case SOUND_MIXER_TREBLE: 4372 case SOUND_MIXER_PCM: 4373 case SOUND_MIXER_SPEAKER: 4374 case SOUND_MIXER_LINE: 4375 case SOUND_MIXER_MIC: 4376 case SOUND_MIXER_CD: 4377 case SOUND_MIXER_RECLEV: 4378 case SOUND_MIXER_IGAIN: 4379 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 4380 (*dev)++; 4381 break; 4382 default: 4383 return (*dev)++; 4384 break; 4385 } 4386 } 4387 4388 return (-1); 4389} 4390 4391static int 4392hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4393{ 4394 struct hdac_widget *w; 4395 int i, ret = 0; 4396 4397 if (depth > HDA_PARSE_MAXDEPTH) 4398 return (0); 4399 w = hdac_widget_get(devinfo, nid); 4400 if (w == NULL || w->enable == 0) 4401 return (0); 4402 switch (w->type) { 4403 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4404 w->pflags |= HDA_DAC_PATH; 4405 ret = 1; 4406 break; 4407 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4408 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4409 for (i = 0; i < w->nconns; i++) { 4410 if (hdac_widget_find_dac_path(devinfo, 4411 w->conns[i], depth + 1) != 0) { 4412 if (w->selconn == -1) 4413 w->selconn = i; 4414 ret = 1; 4415 w->pflags |= HDA_DAC_PATH; 4416 } 4417 } 4418 break; 4419 default: 4420 break; 4421 } 4422 return (ret); 4423} 4424 4425static int 4426hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4427{ 4428 struct hdac_widget *w; 4429 int i, conndev, ret = 0; 4430 4431 if (depth > HDA_PARSE_MAXDEPTH) 4432 return (0); 4433 w = hdac_widget_get(devinfo, nid); 4434 if (w == NULL || w->enable == 0) 4435 return (0); 4436 switch (w->type) { 4437 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4438 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4439 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4440 for (i = 0; i < w->nconns; i++) { 4441 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 4442 depth + 1) != 0) { 4443 if (w->selconn == -1) 4444 w->selconn = i; 4445 w->pflags |= HDA_ADC_PATH; 4446 ret = 1; 4447 } 4448 } 4449 break; 4450 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4451 conndev = w->wclass.pin.config & 4452 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4453 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4454 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 4455 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 4456 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 4457 w->pflags |= HDA_ADC_PATH; 4458 ret = 1; 4459 } 4460 break; 4461 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4462 if (w->pflags & HDA_DAC_PATH) { 4463 w->pflags |= HDA_ADC_PATH; 4464 ret = 1; 4465 } 4466 break;*/ 4467 default: 4468 break; 4469 } 4470 return (ret); 4471} 4472 4473static uint32_t 4474hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 4475 nid_t nid, nid_t pnid, int index, int depth) 4476{ 4477 struct hdac_widget *w, *pw; 4478 struct hdac_audio_ctl *ctl; 4479 uint32_t fl = 0; 4480 int i, ossdev, conndev, strategy; 4481 4482 if (depth > HDA_PARSE_MAXDEPTH) 4483 return (0); 4484 4485 w = hdac_widget_get(devinfo, nid); 4486 if (w == NULL || w->enable == 0) 4487 return (0); 4488 4489 pw = hdac_widget_get(devinfo, pnid); 4490 strategy = devinfo->function.audio.parsing_strategy; 4491 4492 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 4493 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 4494 for (i = 0; i < w->nconns; i++) { 4495 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 4496 w->nid, i, depth + 1); 4497 } 4498 w->ctlflags |= fl; 4499 return (fl); 4500 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4501 (w->pflags & HDA_DAC_PATH)) { 4502 i = 0; 4503 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4504 if (ctl->enable == 0 || ctl->widget == NULL) 4505 continue; 4506 /* XXX This should be compressed! */ 4507 if (((ctl->widget->nid == w->nid) || 4508 (ctl->widget->nid == pnid && ctl->index == index && 4509 (ctl->dir & HDA_CTL_IN)) || 4510 (ctl->widget->nid == pnid && pw != NULL && 4511 pw->type == 4512 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4513 (pw->nconns < 2 || pw->selconn == index || 4514 pw->selconn == -1) && 4515 (ctl->dir & HDA_CTL_OUT)) || 4516 (strategy == HDA_PARSE_DIRECT && 4517 ctl->widget->nid == w->nid)) && 4518 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4519 /*if (pw != NULL && pw->selconn == -1) 4520 pw->selconn = index; 4521 fl |= SOUND_MASK_VOLUME; 4522 fl |= SOUND_MASK_PCM; 4523 ctl->ossmask |= SOUND_MASK_VOLUME; 4524 ctl->ossmask |= SOUND_MASK_PCM; 4525 ctl->ossdev = SOUND_MIXER_PCM;*/ 4526 if (!(w->ctlflags & SOUND_MASK_PCM) || 4527 (pw != NULL && 4528 !(pw->ctlflags & SOUND_MASK_PCM))) { 4529 fl |= SOUND_MASK_VOLUME; 4530 fl |= SOUND_MASK_PCM; 4531 ctl->ossmask |= SOUND_MASK_VOLUME; 4532 ctl->ossmask |= SOUND_MASK_PCM; 4533 ctl->ossdev = SOUND_MIXER_PCM; 4534 w->ctlflags |= SOUND_MASK_VOLUME; 4535 w->ctlflags |= SOUND_MASK_PCM; 4536 if (pw != NULL) { 4537 if (pw->selconn == -1) 4538 pw->selconn = index; 4539 pw->ctlflags |= 4540 SOUND_MASK_VOLUME; 4541 pw->ctlflags |= 4542 SOUND_MASK_PCM; 4543 } 4544 } 4545 } 4546 } 4547 w->ctlflags |= fl; 4548 return (fl); 4549 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4550 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4551 (w->pflags & HDA_ADC_PATH)) { 4552 conndev = w->wclass.pin.config & 4553 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4554 i = 0; 4555 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4556 if (ctl->enable == 0 || ctl->widget == NULL) 4557 continue; 4558 /* XXX This should be compressed! */ 4559 if (((ctl->widget->nid == pnid && ctl->index == index && 4560 (ctl->dir & HDA_CTL_IN)) || 4561 (ctl->widget->nid == pnid && pw != NULL && 4562 pw->type == 4563 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4564 (pw->nconns < 2 || pw->selconn == index || 4565 pw->selconn == -1) && 4566 (ctl->dir & HDA_CTL_OUT)) || 4567 (strategy == HDA_PARSE_DIRECT && 4568 ctl->widget->nid == w->nid)) && 4569 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4570 if (pw != NULL && pw->selconn == -1) 4571 pw->selconn = index; 4572 ossdev = 0; 4573 switch (conndev) { 4574 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4575 ossdev = SOUND_MIXER_MIC; 4576 break; 4577 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4578 ossdev = SOUND_MIXER_LINE; 4579 break; 4580 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4581 ossdev = SOUND_MIXER_CD; 4582 break; 4583 default: 4584 ossdev = 4585 hdac_audio_ctl_ossmixer_getnextdev( 4586 devinfo); 4587 if (ossdev < 0) 4588 ossdev = 0; 4589 break; 4590 } 4591 if (strategy == HDA_PARSE_MIXER) { 4592 fl |= SOUND_MASK_VOLUME; 4593 ctl->ossmask |= SOUND_MASK_VOLUME; 4594 } 4595 fl |= 1 << ossdev; 4596 ctl->ossmask |= 1 << ossdev; 4597 ctl->ossdev = ossdev; 4598 } 4599 } 4600 w->ctlflags |= fl; 4601 return (fl); 4602 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4603 i = 0; 4604 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4605 if (ctl->enable == 0 || ctl->widget == NULL) 4606 continue; 4607 /* XXX This should be compressed! */ 4608 if (((ctl->widget->nid == pnid && ctl->index == index && 4609 (ctl->dir & HDA_CTL_IN)) || 4610 (ctl->widget->nid == pnid && pw != NULL && 4611 pw->type == 4612 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4613 (pw->nconns < 2 || pw->selconn == index || 4614 pw->selconn == -1) && 4615 (ctl->dir & HDA_CTL_OUT)) || 4616 (strategy == HDA_PARSE_DIRECT && 4617 ctl->widget->nid == w->nid)) && 4618 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4619 if (pw != NULL && pw->selconn == -1) 4620 pw->selconn = index; 4621 fl |= SOUND_MASK_VOLUME; 4622 fl |= SOUND_MASK_SPEAKER; 4623 ctl->ossmask |= SOUND_MASK_VOLUME; 4624 ctl->ossmask |= SOUND_MASK_SPEAKER; 4625 ctl->ossdev = SOUND_MIXER_SPEAKER; 4626 } 4627 } 4628 w->ctlflags |= fl; 4629 return (fl); 4630 } 4631 return (0); 4632} 4633 4634static uint32_t 4635hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4636{ 4637 struct hdac_widget *w, *cw; 4638 struct hdac_audio_ctl *ctl; 4639 uint32_t fl; 4640 int i; 4641 4642 if (depth > HDA_PARSE_MAXDEPTH) 4643 return (0); 4644 4645 w = hdac_widget_get(devinfo, nid); 4646 if (w == NULL || w->enable == 0) 4647 return (0); 4648 /*if (!(w->pflags & HDA_ADC_PATH)) 4649 return (0); 4650 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4651 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4652 return (0);*/ 4653 i = 0; 4654 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4655 if (ctl->enable == 0 || ctl->widget == NULL) 4656 continue; 4657 if (ctl->widget->nid == nid) { 4658 ctl->ossmask |= SOUND_MASK_RECLEV; 4659 w->ctlflags |= SOUND_MASK_RECLEV; 4660 return (SOUND_MASK_RECLEV); 4661 } 4662 } 4663 for (i = 0; i < w->nconns; i++) { 4664 cw = hdac_widget_get(devinfo, w->conns[i]); 4665 if (cw == NULL || cw->enable == 0) 4666 continue; 4667 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4668 continue; 4669 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4670 if (fl != 0) { 4671 cw->ctlflags |= fl; 4672 w->ctlflags |= fl; 4673 return (fl); 4674 } 4675 } 4676 return (0); 4677} 4678 4679static int 4680hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4681{ 4682 struct hdac_widget *w, *cw; 4683 int i, child = 0; 4684 4685 if (depth > HDA_PARSE_MAXDEPTH) 4686 return (0); 4687 4688 w = hdac_widget_get(devinfo, nid); 4689 if (w == NULL || w->enable == 0) 4690 return (0); 4691 /*if (!(w->pflags & HDA_ADC_PATH)) 4692 return (0); 4693 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4694 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4695 return (0);*/ 4696 /* XXX weak! */ 4697 for (i = 0; i < w->nconns; i++) { 4698 cw = hdac_widget_get(devinfo, w->conns[i]); 4699 if (cw == NULL) 4700 continue; 4701 if (++child > 1) { 4702 w->pflags |= HDA_ADC_RECSEL; 4703 return (1); 4704 } 4705 } 4706 for (i = 0; i < w->nconns; i++) { 4707 if (hdac_audio_ctl_recsel_build(devinfo, 4708 w->conns[i], depth + 1) != 0) 4709 return (1); 4710 } 4711 return (0); 4712} 4713 4714static int 4715hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4716{ 4717 struct hdac_widget *w, *cw; 4718 int i, j, conndev, found_dac = 0; 4719 int strategy; 4720 4721 strategy = devinfo->function.audio.parsing_strategy; 4722 4723 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4724 w = hdac_widget_get(devinfo, i); 4725 if (w == NULL || w->enable == 0) 4726 continue; 4727 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4728 continue; 4729 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4730 continue; 4731 conndev = w->wclass.pin.config & 4732 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4733 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4734 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4735 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4736 continue; 4737 for (j = 0; j < w->nconns; j++) { 4738 cw = hdac_widget_get(devinfo, w->conns[j]); 4739 if (cw == NULL || cw->enable == 0) 4740 continue; 4741 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4742 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4743 cw->type == 4744 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4745 continue; 4746 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4747 != 0) { 4748 if (w->selconn == -1) 4749 w->selconn = j; 4750 w->pflags |= HDA_DAC_PATH; 4751 found_dac++; 4752 } 4753 } 4754 } 4755 4756 return (found_dac); 4757} 4758 4759static void 4760hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4761{ 4762 struct hdac_widget *w; 4763 struct hdac_audio_ctl *ctl; 4764 int i, j, dacs, strategy; 4765 4766 /* Construct DAC path */ 4767 strategy = HDA_PARSE_MIXER; 4768 devinfo->function.audio.parsing_strategy = strategy; 4769 HDA_BOOTVERBOSE( 4770 device_printf(devinfo->codec->sc->dev, 4771 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4772 HDA_WIDGET_PARSER_REV); 4773 ); 4774 dacs = hdac_audio_build_tree_strategy(devinfo); 4775 if (dacs == 0) { 4776 HDA_BOOTVERBOSE( 4777 device_printf(devinfo->codec->sc->dev, 4778 "HDA_DEBUG: HWiP: 0 DAC path found! " 4779 "Retrying parser " 4780 "using HDA_PARSE_DIRECT strategy.\n"); 4781 ); 4782 strategy = HDA_PARSE_DIRECT; 4783 devinfo->function.audio.parsing_strategy = strategy; 4784 dacs = hdac_audio_build_tree_strategy(devinfo); 4785 } 4786 4787 HDA_BOOTVERBOSE( 4788 device_printf(devinfo->codec->sc->dev, 4789 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4790 "strategy.\n", 4791 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4792 ); 4793 4794 /* Construct ADC path */ 4795 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4796 w = hdac_widget_get(devinfo, i); 4797 if (w == NULL || w->enable == 0) 4798 continue; 4799 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4800 continue; 4801 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4802 } 4803 4804 /* Output mixers */ 4805 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4806 w = hdac_widget_get(devinfo, i); 4807 if (w == NULL || w->enable == 0) 4808 continue; 4809 if ((strategy == HDA_PARSE_MIXER && 4810 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4811 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4812 && (w->pflags & HDA_DAC_PATH)) || 4813 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4814 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4815 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4816 w->nid, devinfo->startnode - 1, 0, 0); 4817 } else if (w->type == 4818 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4819 j = 0; 4820 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4821 NULL) { 4822 if (ctl->enable == 0 || ctl->widget == NULL) 4823 continue; 4824 if (ctl->widget->nid != w->nid) 4825 continue; 4826 ctl->ossmask |= SOUND_MASK_VOLUME; 4827 ctl->ossmask |= SOUND_MASK_SPEAKER; 4828 ctl->ossdev = SOUND_MIXER_SPEAKER; 4829 w->ctlflags |= SOUND_MASK_VOLUME; 4830 w->ctlflags |= SOUND_MASK_SPEAKER; 4831 } 4832 } 4833 } 4834 4835 /* Input mixers (rec) */ 4836 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4837 w = hdac_widget_get(devinfo, i); 4838 if (w == NULL || w->enable == 0) 4839 continue; 4840 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4841 w->pflags & HDA_ADC_PATH)) 4842 continue; 4843 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4844 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4845 } 4846} 4847 4848#define HDA_COMMIT_CONN (1 << 0) 4849#define HDA_COMMIT_CTRL (1 << 1) 4850#define HDA_COMMIT_EAPD (1 << 2) 4851#define HDA_COMMIT_GPIO (1 << 3) 4852#define HDA_COMMIT_MISC (1 << 4) 4853#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4854 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC) 4855 4856static void 4857hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4858{ 4859 struct hdac_softc *sc = devinfo->codec->sc; 4860 struct hdac_widget *w; 4861 nid_t cad; 4862 int i; 4863 4864 if (!(cfl & HDA_COMMIT_ALL)) 4865 return; 4866 4867 cad = devinfo->codec->cad; 4868 4869 if ((cfl & HDA_COMMIT_MISC)) { 4870 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4871 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4872 0x7e7, 0), cad); 4873 } 4874 4875 if (cfl & HDA_COMMIT_GPIO) { 4876 uint32_t gdata, gmask, gdir; 4877 int commitgpio, numgpio; 4878 4879 gdata = 0; 4880 gmask = 0; 4881 gdir = 0; 4882 commitgpio = 0; 4883 4884 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 4885 devinfo->function.audio.gpio); 4886 4887 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4888 commitgpio = (numgpio > 0) ? 1 : 0; 4889 else { 4890 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 4891 if (!(devinfo->function.audio.quirks & 4892 (1 << i))) 4893 continue; 4894 if (commitgpio == 0) { 4895 commitgpio = 1; 4896 HDA_BOOTVERBOSE( 4897 gdata = hdac_command(sc, 4898 HDA_CMD_GET_GPIO_DATA(cad, 4899 devinfo->nid), cad); 4900 gmask = hdac_command(sc, 4901 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4902 devinfo->nid), cad); 4903 gdir = hdac_command(sc, 4904 HDA_CMD_GET_GPIO_DIRECTION(cad, 4905 devinfo->nid), cad); 4906 device_printf(sc->dev, 4907 "GPIO init: data=0x%08x " 4908 "mask=0x%08x dir=0x%08x\n", 4909 gdata, gmask, gdir); 4910 gdata = 0; 4911 gmask = 0; 4912 gdir = 0; 4913 ); 4914 } 4915 gdata |= 1 << i; 4916 gmask |= 1 << i; 4917 gdir |= 1 << i; 4918 } 4919 } 4920 4921 if (commitgpio != 0) { 4922 HDA_BOOTVERBOSE( 4923 device_printf(sc->dev, 4924 "GPIO commit: data=0x%08x mask=0x%08x " 4925 "dir=0x%08x\n", 4926 gdata, gmask, gdir); 4927 ); 4928 hdac_command(sc, 4929 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4930 gmask), cad); 4931 hdac_command(sc, 4932 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4933 gdir), cad); 4934 hdac_command(sc, 4935 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4936 gdata), cad); 4937 } 4938 } 4939 4940 for (i = 0; i < devinfo->nodecnt; i++) { 4941 w = &devinfo->widget[i]; 4942 if (w == NULL || w->enable == 0) 4943 continue; 4944 if (cfl & HDA_COMMIT_CONN) { 4945 if (w->selconn == -1) 4946 w->selconn = 0; 4947 if (w->nconns > 0) 4948 hdac_widget_connection_select(w, w->selconn); 4949 } 4950 if ((cfl & HDA_COMMIT_CTRL) && 4951 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4952 uint32_t pincap; 4953 4954 pincap = w->wclass.pin.cap; 4955 4956 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4957 (HDA_DAC_PATH | HDA_ADC_PATH)) 4958 device_printf(sc->dev, "WARNING: node %d " 4959 "participate both for DAC/ADC!\n", w->nid); 4960 if (w->pflags & HDA_DAC_PATH) { 4961 w->wclass.pin.ctrl &= 4962 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4963 if ((w->wclass.pin.config & 4964 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4965 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4966 w->wclass.pin.ctrl &= 4967 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4968 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 4969 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4970 w->wclass.pin.ctrl |= 4971 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4972 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 4973 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 4974 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4975 w->wclass.pin.ctrl |= 4976 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4977 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 4978 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 4979 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4980 w->wclass.pin.ctrl |= 4981 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4982 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 4983 } else if (w->pflags & HDA_ADC_PATH) { 4984 w->wclass.pin.ctrl &= 4985 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4986 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4987 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 4988 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4989 w->wclass.pin.ctrl |= 4990 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4991 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 4992 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 4993 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4994 w->wclass.pin.ctrl |= 4995 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4996 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 4997 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 4998 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4999 w->wclass.pin.ctrl |= 5000 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 5001 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 5002 } else 5003 w->wclass.pin.ctrl &= ~( 5004 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 5005 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 5006 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 5007 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 5008 hdac_command(sc, 5009 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 5010 w->wclass.pin.ctrl), cad); 5011 } 5012 if ((cfl & HDA_COMMIT_EAPD) && 5013 w->param.eapdbtl != HDAC_INVALID) { 5014 uint32_t val; 5015 5016 val = w->param.eapdbtl; 5017 if (devinfo->function.audio.quirks & 5018 HDA_QUIRK_EAPDINV) 5019 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 5020 hdac_command(sc, 5021 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 5022 val), cad); 5023 5024 } 5025 DELAY(1000); 5026 } 5027} 5028 5029static void 5030hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 5031{ 5032 struct hdac_softc *sc = devinfo->codec->sc; 5033 struct hdac_audio_ctl *ctl; 5034 int i; 5035 5036 devinfo->function.audio.mvol = 100 | (100 << 8); 5037 i = 0; 5038 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5039 if (ctl->enable == 0 || ctl->widget == NULL) { 5040 HDA_BOOTVERBOSE( 5041 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5042 i, (ctl->widget != NULL) ? 5043 ctl->widget->nid : -1); 5044 if (ctl->childwidget != NULL) 5045 printf(" childnid=%d", 5046 ctl->childwidget->nid); 5047 if (ctl->widget == NULL) 5048 printf(" NULL WIDGET!"); 5049 printf(" DISABLED\n"); 5050 ); 5051 continue; 5052 } 5053 HDA_BOOTVERBOSE( 5054 if (ctl->ossmask == 0) { 5055 device_printf(sc->dev, "[%2d] Ctl nid=%d", 5056 i, ctl->widget->nid); 5057 if (ctl->childwidget != NULL) 5058 printf(" childnid=%d", 5059 ctl->childwidget->nid); 5060 printf(" Bind to NONE\n"); 5061 } 5062 ); 5063 if (ctl->step > 0) { 5064 ctl->ossval = (ctl->left * 100) / ctl->step; 5065 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 5066 } else 5067 ctl->ossval = 0; 5068 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 5069 ctl->left, ctl->right); 5070 } 5071} 5072 5073static int 5074hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 5075{ 5076 struct hdac_chan *ch; 5077 struct hdac_widget *w; 5078 uint32_t cap, fmtcap, pcmcap, path; 5079 int i, type, ret, max; 5080 5081 if (dir == PCMDIR_PLAY) { 5082 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 5083 ch = &devinfo->codec->sc->play; 5084 path = HDA_DAC_PATH; 5085 } else { 5086 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 5087 ch = &devinfo->codec->sc->rec; 5088 path = HDA_ADC_PATH; 5089 } 5090 5091 ch->caps = hdac_caps; 5092 ch->caps.fmtlist = ch->fmtlist; 5093 ch->bit16 = 1; 5094 ch->bit32 = 0; 5095 ch->pcmrates[0] = 48000; 5096 ch->pcmrates[1] = 0; 5097 5098 ret = 0; 5099 fmtcap = devinfo->function.audio.supp_stream_formats; 5100 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 5101 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 5102 5103 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 5104 w = hdac_widget_get(devinfo, i); 5105 if (w == NULL || w->enable == 0 || w->type != type || 5106 !(w->pflags & path)) 5107 continue; 5108 cap = w->param.widget_cap; 5109 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 5110 continue;*/ 5111 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 5112 continue; 5113 cap = w->param.supp_stream_formats; 5114 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 5115 } 5116 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 5117 }*/ 5118 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5119 continue; 5120 if (ret == 0) { 5121 fmtcap = w->param.supp_stream_formats; 5122 pcmcap = w->param.supp_pcm_size_rate; 5123 } else { 5124 fmtcap &= w->param.supp_stream_formats; 5125 pcmcap &= w->param.supp_pcm_size_rate; 5126 } 5127 ch->io[ret++] = i; 5128 } 5129 ch->io[ret] = -1; 5130 5131 ch->supp_stream_formats = fmtcap; 5132 ch->supp_pcm_size_rate = pcmcap; 5133 5134 /* 5135 * 8bit = 0 5136 * 16bit = 1 5137 * 20bit = 2 5138 * 24bit = 3 5139 * 32bit = 4 5140 */ 5141 if (ret > 0) { 5142 cap = pcmcap; 5143 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5144 ch->bit16 = 1; 5145 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5146 ch->bit16 = 0; 5147 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5148 ch->bit32 = 4; 5149 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5150 ch->bit32 = 3; 5151 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5152 ch->bit32 = 2; 5153 i = 0; 5154 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 5155 ch->fmtlist[i++] = AFMT_S16_LE; 5156 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 5157 if (ch->bit32 > 0) { 5158 if (!(devinfo->function.audio.quirks & 5159 HDA_QUIRK_FORCESTEREO)) 5160 ch->fmtlist[i++] = AFMT_S32_LE; 5161 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 5162 } 5163 ch->fmtlist[i] = 0; 5164 i = 0; 5165 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5166 ch->pcmrates[i++] = 8000; 5167 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5168 ch->pcmrates[i++] = 11025; 5169 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5170 ch->pcmrates[i++] = 16000; 5171 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5172 ch->pcmrates[i++] = 22050; 5173 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5174 ch->pcmrates[i++] = 32000; 5175 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5176 ch->pcmrates[i++] = 44100; 5177 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 5178 ch->pcmrates[i++] = 48000; 5179 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5180 ch->pcmrates[i++] = 88200; 5181 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5182 ch->pcmrates[i++] = 96000; 5183 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5184 ch->pcmrates[i++] = 176400; 5185 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5186 ch->pcmrates[i++] = 192000; 5187 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 5188 ch->pcmrates[i] = 0; 5189 if (i > 0) { 5190 ch->caps.minspeed = ch->pcmrates[0]; 5191 ch->caps.maxspeed = ch->pcmrates[i - 1]; 5192 } 5193 } 5194 5195 return (ret); 5196} 5197 5198static void 5199hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 5200{ 5201 struct hdac_audio_ctl *ctl; 5202 struct hdac_softc *sc = devinfo->codec->sc; 5203 int i; 5204 uint32_t fl = 0; 5205 5206 5207 if (flag == 0) { 5208 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 5209 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 5210 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 5211 } 5212 5213 i = 0; 5214 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5215 if (ctl->enable == 0 || ctl->widget == NULL || 5216 ctl->widget->enable == 0 || (ctl->ossmask & 5217 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))) 5218 continue; 5219 if ((flag == 0 && (ctl->ossmask & ~fl)) || 5220 (flag != 0 && (ctl->ossmask & flag))) { 5221 if (banner != NULL) { 5222 device_printf(sc->dev, "\n"); 5223 device_printf(sc->dev, "%s\n", banner); 5224 } 5225 goto hdac_ctl_dump_it_all; 5226 } 5227 } 5228 5229 return; 5230 5231hdac_ctl_dump_it_all: 5232 i = 0; 5233 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5234 if (ctl->enable == 0 || ctl->widget == NULL || 5235 ctl->widget->enable == 0) 5236 continue; 5237 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 5238 (flag != 0 && (ctl->ossmask & flag)))) 5239 continue; 5240 if (flag == 0) { 5241 device_printf(sc->dev, "\n"); 5242 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 5243 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 5244 } 5245 device_printf(sc->dev, " |\n"); 5246 device_printf(sc->dev, " +- nid: %2d index: %2d ", 5247 ctl->widget->nid, ctl->index); 5248 if (ctl->childwidget != NULL) 5249 printf("(nid: %2d) ", ctl->childwidget->nid); 5250 else 5251 printf(" "); 5252 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 5253 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 5254 ctl->ossmask); 5255 } 5256} 5257 5258static void 5259hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 5260{ 5261 uint32_t cap; 5262 5263 cap = fcap; 5264 if (cap != 0) { 5265 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 5266 device_printf(sc->dev, " Format:"); 5267 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 5268 printf(" AC3"); 5269 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 5270 printf(" FLOAT32"); 5271 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 5272 printf(" PCM"); 5273 printf("\n"); 5274 } 5275 cap = pcmcap; 5276 if (cap != 0) { 5277 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 5278 device_printf(sc->dev, " PCM size:"); 5279 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 5280 printf(" 8"); 5281 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 5282 printf(" 16"); 5283 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 5284 printf(" 20"); 5285 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 5286 printf(" 24"); 5287 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 5288 printf(" 32"); 5289 printf("\n"); 5290 device_printf(sc->dev, " PCM rate:"); 5291 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 5292 printf(" 8"); 5293 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 5294 printf(" 11"); 5295 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 5296 printf(" 16"); 5297 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 5298 printf(" 22"); 5299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 5300 printf(" 32"); 5301 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 5302 printf(" 44"); 5303 printf(" 48"); 5304 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 5305 printf(" 88"); 5306 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 5307 printf(" 96"); 5308 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 5309 printf(" 176"); 5310 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 5311 printf(" 192"); 5312 printf("\n"); 5313 } 5314} 5315 5316static void 5317hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 5318{ 5319 uint32_t pincap, wcap; 5320 5321 pincap = w->wclass.pin.cap; 5322 wcap = w->param.widget_cap; 5323 5324 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 5325 device_printf(sc->dev, " "); 5326 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 5327 printf(" ISC"); 5328 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 5329 printf(" TRQD"); 5330 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 5331 printf(" PDC"); 5332 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 5333 printf(" HP"); 5334 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 5335 printf(" OUT"); 5336 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 5337 printf(" IN"); 5338 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 5339 printf(" BAL"); 5340 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 5341 printf(" VREF["); 5342 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 5343 printf(" 50"); 5344 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 5345 printf(" 80"); 5346 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 5347 printf(" 100"); 5348 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 5349 printf(" GROUND"); 5350 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 5351 printf(" HIZ"); 5352 printf(" ]"); 5353 } 5354 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 5355 printf(" EAPD"); 5356 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 5357 printf(" : UNSOL"); 5358 printf("\n"); 5359 device_printf(sc->dev, " Pin config: 0x%08x\n", 5360 w->wclass.pin.config); 5361 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 5362 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 5363 printf(" HP"); 5364 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 5365 printf(" IN"); 5366 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 5367 printf(" OUT"); 5368 printf("\n"); 5369} 5370 5371static void 5372hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 5373{ 5374 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 5375 device_printf(sc->dev, " " 5376 "mute=%d step=%d size=%d offset=%d\n", 5377 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 5378 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 5379 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 5380 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 5381} 5382 5383static void 5384hdac_dump_nodes(struct hdac_devinfo *devinfo) 5385{ 5386 struct hdac_softc *sc = devinfo->codec->sc; 5387 struct hdac_widget *w, *cw; 5388 int i, j; 5389 5390 device_printf(sc->dev, "\n"); 5391 device_printf(sc->dev, "Default Parameter\n"); 5392 device_printf(sc->dev, "-----------------\n"); 5393 hdac_dump_audio_formats(sc, 5394 devinfo->function.audio.supp_stream_formats, 5395 devinfo->function.audio.supp_pcm_size_rate); 5396 device_printf(sc->dev, " IN amp: 0x%08x\n", 5397 devinfo->function.audio.inamp_cap); 5398 device_printf(sc->dev, " OUT amp: 0x%08x\n", 5399 devinfo->function.audio.outamp_cap); 5400 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5401 w = hdac_widget_get(devinfo, i); 5402 if (w == NULL) { 5403 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 5404 continue; 5405 } 5406 device_printf(sc->dev, "\n"); 5407 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 5408 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 5409 "DIGITAL" : "ANALOG", 5410 (w->enable == 0) ? " [DISABLED]" : ""); 5411 device_printf(sc->dev, " name: %s\n", w->name); 5412 device_printf(sc->dev, " widget_cap: 0x%08x\n", 5413 w->param.widget_cap); 5414 device_printf(sc->dev, " Parse flags: 0x%08x\n", 5415 w->pflags); 5416 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 5417 w->ctlflags); 5418 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5419 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 5420 hdac_dump_audio_formats(sc, 5421 w->param.supp_stream_formats, 5422 w->param.supp_pcm_size_rate); 5423 } else if (w->type == 5424 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5425 hdac_dump_pin(sc, w); 5426 if (w->param.eapdbtl != HDAC_INVALID) 5427 device_printf(sc->dev, " EAPD: 0x%08x\n", 5428 w->param.eapdbtl); 5429 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 5430 w->param.outamp_cap != 0) 5431 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 5432 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 5433 w->param.inamp_cap != 0) 5434 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 5435 device_printf(sc->dev, " connections: %d\n", w->nconns); 5436 for (j = 0; j < w->nconns; j++) { 5437 cw = hdac_widget_get(devinfo, w->conns[j]); 5438 device_printf(sc->dev, " |\n"); 5439 device_printf(sc->dev, " + <- nid=%d [%s]", 5440 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 5441 if (cw == NULL) 5442 printf(" [UNKNOWN]"); 5443 else if (cw->enable == 0) 5444 printf(" [DISABLED]"); 5445 if (w->nconns > 1 && w->selconn == j && w->type != 5446 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5447 printf(" (selected)"); 5448 printf("\n"); 5449 } 5450 } 5451 5452} 5453 5454static int 5455hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5456{ 5457 struct hdac_widget *w, *cw; 5458 struct hdac_softc *sc = devinfo->codec->sc; 5459 int i; 5460 5461 if (depth > HDA_PARSE_MAXDEPTH) 5462 return (0); 5463 5464 w = hdac_widget_get(devinfo, nid); 5465 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 5466 return (0); 5467 5468 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5469 device_printf(sc->dev, "\n"); 5470 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5471 device_printf(sc->dev, " ^\n"); 5472 device_printf(sc->dev, " |\n"); 5473 device_printf(sc->dev, " +-----<------+\n"); 5474 } else { 5475 device_printf(sc->dev, " ^\n"); 5476 device_printf(sc->dev, " |\n"); 5477 device_printf(sc->dev, " "); 5478 printf(" nid=%d [%s]\n", w->nid, w->name); 5479 } 5480 5481 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 5482 return (1); 5483 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 5484 for (i = 0; i < w->nconns; i++) { 5485 cw = hdac_widget_get(devinfo, w->conns[i]); 5486 if (cw == NULL || cw->enable == 0 || cw->type == 5487 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5488 continue; 5489 if (hdac_dump_dac_internal(devinfo, cw->nid, 5490 depth + 1) != 0) 5491 return (1); 5492 } 5493 } else if ((w->type == 5494 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 5495 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5496 w->selconn > -1 && w->selconn < w->nconns) { 5497 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 5498 depth + 1) != 0) 5499 return (1); 5500 } 5501 5502 return (0); 5503} 5504 5505static void 5506hdac_dump_dac(struct hdac_devinfo *devinfo) 5507{ 5508 struct hdac_widget *w; 5509 struct hdac_softc *sc = devinfo->codec->sc; 5510 int i, printed = 0; 5511 5512 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5513 w = hdac_widget_get(devinfo, i); 5514 if (w == NULL || w->enable == 0) 5515 continue; 5516 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 5517 !(w->pflags & HDA_DAC_PATH)) 5518 continue; 5519 if (printed == 0) { 5520 printed = 1; 5521 device_printf(sc->dev, "\n"); 5522 device_printf(sc->dev, "Playback path:\n"); 5523 } 5524 hdac_dump_dac_internal(devinfo, w->nid, 0); 5525 } 5526} 5527 5528static void 5529hdac_dump_adc(struct hdac_devinfo *devinfo) 5530{ 5531 struct hdac_widget *w, *cw; 5532 struct hdac_softc *sc = devinfo->codec->sc; 5533 int i, j; 5534 int printed = 0; 5535 char ossdevs[256]; 5536 5537 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5538 w = hdac_widget_get(devinfo, i); 5539 if (w == NULL || w->enable == 0) 5540 continue; 5541 if (!(w->pflags & HDA_ADC_RECSEL)) 5542 continue; 5543 if (printed == 0) { 5544 printed = 1; 5545 device_printf(sc->dev, "\n"); 5546 device_printf(sc->dev, "Recording sources:\n"); 5547 } 5548 device_printf(sc->dev, "\n"); 5549 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5550 for (j = 0; j < w->nconns; j++) { 5551 cw = hdac_widget_get(devinfo, w->conns[j]); 5552 if (cw == NULL || cw->enable == 0) 5553 continue; 5554 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5555 ossdevs, sizeof(ossdevs)); 5556 device_printf(sc->dev, " |\n"); 5557 device_printf(sc->dev, " + <- nid=%d [%s]", 5558 cw->nid, cw->name); 5559 if (strlen(ossdevs) > 0) { 5560 printf(" [recsrc: %s]", ossdevs); 5561 } 5562 printf("\n"); 5563 } 5564 } 5565} 5566 5567static void 5568hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5569{ 5570 nid_t *nids; 5571 5572 if (pcnt > 0) { 5573 device_printf(sc->dev, "\n"); 5574 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5575 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5576 sc->play.supp_pcm_size_rate); 5577 device_printf(sc->dev, " DAC:"); 5578 for (nids = sc->play.io; *nids != -1; nids++) 5579 printf(" %d", *nids); 5580 printf("\n"); 5581 } 5582 5583 if (rcnt > 0) { 5584 device_printf(sc->dev, "\n"); 5585 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5586 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5587 sc->rec.supp_pcm_size_rate); 5588 device_printf(sc->dev, " ADC:"); 5589 for (nids = sc->rec.io; *nids != -1; nids++) 5590 printf(" %d", *nids); 5591 printf("\n"); 5592 } 5593} 5594 5595static void 5596hdac_release_resources(struct hdac_softc *sc) 5597{ 5598 struct hdac_devinfo *devinfo = NULL; 5599 device_t *devlist = NULL; 5600 int i, devcount; 5601 5602 if (sc == NULL) 5603 return; 5604 5605 hdac_lock(sc); 5606 sc->polling = 0; 5607 sc->poll_ival = 0; 5608 callout_stop(&sc->poll_hdac); 5609 callout_stop(&sc->poll_jack); 5610 hdac_reset(sc); 5611 hdac_unlock(sc); 5612 callout_drain(&sc->poll_hdac); 5613 callout_drain(&sc->poll_jack); 5614 5615 hdac_irq_free(sc); 5616 5617 device_get_children(sc->dev, &devlist, &devcount); 5618 for (i = 0; devlist != NULL && i < devcount; i++) { 5619 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5620 if (devinfo == NULL) 5621 continue; 5622 if (devinfo->widget != NULL) 5623 free(devinfo->widget, M_HDAC); 5624 if (devinfo->node_type == 5625 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5626 devinfo->function.audio.ctl != NULL) 5627 free(devinfo->function.audio.ctl, M_HDAC); 5628 free(devinfo, M_HDAC); 5629 device_delete_child(sc->dev, devlist[i]); 5630 } 5631 if (devlist != NULL) 5632 free(devlist, M_TEMP); 5633 5634 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5635 if (sc->codecs[i] != NULL) 5636 free(sc->codecs[i], M_HDAC); 5637 sc->codecs[i] = NULL; 5638 } 5639 5640 hdac_dma_free(sc, &sc->pos_dma); 5641 hdac_dma_free(sc, &sc->rirb_dma); 5642 hdac_dma_free(sc, &sc->corb_dma); 5643 if (sc->play.blkcnt > 0) 5644 hdac_dma_free(sc, &sc->play.bdl_dma); 5645 if (sc->rec.blkcnt > 0) 5646 hdac_dma_free(sc, &sc->rec.bdl_dma); 5647 if (sc->chan_dmat != NULL) { 5648 bus_dma_tag_destroy(sc->chan_dmat); 5649 sc->chan_dmat = NULL; 5650 } 5651 hdac_mem_free(sc); 5652 snd_mtxfree(sc->lock); 5653 free(sc, M_DEVBUF); 5654} 5655 5656/* This function surely going to make its way into upper level someday. */ 5657static void 5658hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5659{ 5660 const char *res = NULL; 5661 int i = 0, j, k, len, inv; 5662 5663 if (on != NULL) 5664 *on = 0; 5665 if (off != NULL) 5666 *off = 0; 5667 if (sc == NULL) 5668 return; 5669 if (resource_string_value(device_get_name(sc->dev), 5670 device_get_unit(sc->dev), "config", &res) != 0) 5671 return; 5672 if (!(res != NULL && strlen(res) > 0)) 5673 return; 5674 HDA_BOOTVERBOSE( 5675 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5676 ); 5677 for (;;) { 5678 while (res[i] != '\0' && 5679 (res[i] == ',' || isspace(res[i]) != 0)) 5680 i++; 5681 if (res[i] == '\0') { 5682 HDA_BOOTVERBOSE( 5683 printf("\n"); 5684 ); 5685 return; 5686 } 5687 j = i; 5688 while (res[j] != '\0' && 5689 !(res[j] == ',' || isspace(res[j]) != 0)) 5690 j++; 5691 len = j - i; 5692 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5693 inv = 2; 5694 else 5695 inv = 0; 5696 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5697 if (strncmp(res + i + inv, 5698 hdac_quirks_tab[k].key, len - inv) != 0) 5699 continue; 5700 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5701 break; 5702 HDA_BOOTVERBOSE( 5703 printf(" %s%s", (inv != 0) ? "no" : "", 5704 hdac_quirks_tab[k].key); 5705 ); 5706 if (inv == 0 && on != NULL) 5707 *on |= hdac_quirks_tab[k].value; 5708 else if (inv != 0 && off != NULL) 5709 *off |= hdac_quirks_tab[k].value; 5710 break; 5711 } 5712 i = j; 5713 } 5714} 5715 5716#ifdef SND_DYNSYSCTL 5717static int 5718sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5719{ 5720 struct hdac_softc *sc; 5721 struct hdac_devinfo *devinfo; 5722 device_t dev; 5723 uint32_t ctl; 5724 int err, val; 5725 5726 dev = oidp->oid_arg1; 5727 devinfo = pcm_getdevinfo(dev); 5728 if (devinfo == NULL || devinfo->codec == NULL || 5729 devinfo->codec->sc == NULL) 5730 return (EINVAL); 5731 sc = devinfo->codec->sc; 5732 hdac_lock(sc); 5733 val = sc->polling; 5734 hdac_unlock(sc); 5735 err = sysctl_handle_int(oidp, &val, 0, req); 5736 5737 if (err != 0 || req->newptr == NULL) 5738 return (err); 5739 if (val < 0 || val > 1) 5740 return (EINVAL); 5741 5742 hdac_lock(sc); 5743 if (val != sc->polling) { 5744 if (hda_chan_active(sc) != 0) 5745 err = EBUSY; 5746 else if (val == 0) { 5747 callout_stop(&sc->poll_hdac); 5748 hdac_unlock(sc); 5749 callout_drain(&sc->poll_hdac); 5750 hdac_lock(sc); 5751 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5752 sc->rirb_size / 2); 5753 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5754 ctl |= HDAC_RIRBCTL_RINTCTL; 5755 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5756 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5757 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5758 sc->polling = 0; 5759 DELAY(1000); 5760 } else { 5761 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5762 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5763 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5764 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5765 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5766 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5767 sc); 5768 sc->polling = 1; 5769 DELAY(1000); 5770 } 5771 } 5772 hdac_unlock(sc); 5773 5774 return (err); 5775} 5776 5777static int 5778sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 5779{ 5780 struct hdac_softc *sc; 5781 struct hdac_devinfo *devinfo; 5782 device_t dev; 5783 int err, val; 5784 5785 dev = oidp->oid_arg1; 5786 devinfo = pcm_getdevinfo(dev); 5787 if (devinfo == NULL || devinfo->codec == NULL || 5788 devinfo->codec->sc == NULL) 5789 return (EINVAL); 5790 sc = devinfo->codec->sc; 5791 hdac_lock(sc); 5792 val = ((uint64_t)sc->poll_ival * 1000) / hz; 5793 hdac_unlock(sc); 5794 err = sysctl_handle_int(oidp, &val, 0, req); 5795 5796 if (err != 0 || req->newptr == NULL) 5797 return (err); 5798 5799 if (val < 1) 5800 val = 1; 5801 if (val > 5000) 5802 val = 5000; 5803 val = ((uint64_t)val * hz) / 1000; 5804 if (val < 1) 5805 val = 1; 5806 if (val > (hz * 5)) 5807 val = hz * 5; 5808 5809 hdac_lock(sc); 5810 sc->poll_ival = val; 5811 hdac_unlock(sc); 5812 5813 return (err); 5814} 5815 5816#ifdef SND_DEBUG 5817static int 5818sysctl_hdac_dump(SYSCTL_HANDLER_ARGS) 5819{ 5820 struct hdac_softc *sc; 5821 struct hdac_devinfo *devinfo; 5822 struct hdac_widget *w; 5823 device_t dev; 5824 uint32_t res, execres; 5825 int i, err, val; 5826 nid_t cad; 5827 5828 dev = oidp->oid_arg1; 5829 devinfo = pcm_getdevinfo(dev); 5830 if (devinfo == NULL || devinfo->codec == NULL || 5831 devinfo->codec->sc == NULL) 5832 return (EINVAL); 5833 val = 0; 5834 err = sysctl_handle_int(oidp, &val, 0, req); 5835 if (err != 0 || req->newptr == NULL || val == 0) 5836 return (err); 5837 sc = devinfo->codec->sc; 5838 cad = devinfo->codec->cad; 5839 hdac_lock(sc); 5840 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid); 5841 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5842 w = hdac_widget_get(devinfo, i); 5843 if (w == NULL || w->type != 5844 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5845 continue; 5846 execres = hdac_command(sc, HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), 5847 cad); 5848 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 5849 device_printf(dev, "nid=%-3d exec=0x%08x sense=0x%08x [%s]\n", 5850 w->nid, execres, res, 5851 (w->enable == 0) ? "DISABLED" : "ENABLED"); 5852 } 5853 device_printf(dev, 5854 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 5855 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 5856 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 5857 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 5858 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 5859 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 5860 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 5861 device_printf(dev, " GPI:"); 5862 res = hdac_command(sc, 5863 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 5864 printf(" data=0x%08x", res); 5865 res = hdac_command(sc, 5866 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 5867 cad); 5868 printf(" wake=0x%08x", res); 5869 res = hdac_command(sc, 5870 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5871 cad); 5872 printf(" unsol=0x%08x", res); 5873 res = hdac_command(sc, 5874 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 5875 printf(" sticky=0x%08x\n", res); 5876 } 5877 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 5878 device_printf(dev, " GPO:"); 5879 res = hdac_command(sc, 5880 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 5881 printf(" data=0x%08x\n", res); 5882 } 5883 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 5884 device_printf(dev, "GPI0:"); 5885 res = hdac_command(sc, 5886 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 5887 printf(" data=0x%08x", res); 5888 res = hdac_command(sc, 5889 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 5890 printf(" enable=0x%08x", res); 5891 res = hdac_command(sc, 5892 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 5893 printf(" direction=0x%08x\n", res); 5894 res = hdac_command(sc, 5895 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 5896 device_printf(dev, " wake=0x%08x", res); 5897 res = hdac_command(sc, 5898 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 5899 cad); 5900 printf(" unsol=0x%08x", res); 5901 res = hdac_command(sc, 5902 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 5903 printf(" sticky=0x%08x\n", res); 5904 } 5905 hdac_unlock(sc); 5906 return (0); 5907} 5908#endif 5909#endif 5910 5911static void 5912hdac_attach2(void *arg) 5913{ 5914 struct hdac_softc *sc; 5915 struct hdac_widget *w; 5916 struct hdac_audio_ctl *ctl; 5917 uint32_t quirks_on, quirks_off; 5918 int pcnt, rcnt; 5919 int i; 5920 char status[SND_STATUSLEN]; 5921 device_t *devlist = NULL; 5922 int devcount; 5923 struct hdac_devinfo *devinfo = NULL; 5924 5925 sc = (struct hdac_softc *)arg; 5926 5927 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5928 5929 HDA_BOOTVERBOSE( 5930 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5931 quirks_on, quirks_off); 5932 ); 5933 5934 hdac_lock(sc); 5935 5936 /* Remove ourselves from the config hooks */ 5937 if (sc->intrhook.ich_func != NULL) { 5938 config_intrhook_disestablish(&sc->intrhook); 5939 sc->intrhook.ich_func = NULL; 5940 } 5941 5942 /* Start the corb and rirb engines */ 5943 HDA_BOOTVERBOSE( 5944 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5945 ); 5946 hdac_corb_start(sc); 5947 HDA_BOOTVERBOSE( 5948 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5949 ); 5950 hdac_rirb_start(sc); 5951 5952 HDA_BOOTVERBOSE( 5953 device_printf(sc->dev, 5954 "HDA_DEBUG: Enabling controller interrupt...\n"); 5955 ); 5956 if (sc->polling == 0) 5957 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5958 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5959 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5960 HDAC_GCTL_UNSOL); 5961 5962 DELAY(1000); 5963 5964 HDA_BOOTVERBOSE( 5965 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5966 ); 5967 hdac_scan_codecs(sc); 5968 5969 device_get_children(sc->dev, &devlist, &devcount); 5970 for (i = 0; devlist != NULL && i < devcount; i++) { 5971 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5972 if (devinfo != NULL && devinfo->node_type == 5973 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5974 break; 5975 } else 5976 devinfo = NULL; 5977 } 5978 if (devlist != NULL) 5979 free(devlist, M_TEMP); 5980 5981 if (devinfo == NULL) { 5982 hdac_unlock(sc); 5983 device_printf(sc->dev, "Audio Function Group not found!\n"); 5984 hdac_release_resources(sc); 5985 return; 5986 } 5987 5988 HDA_BOOTVERBOSE( 5989 device_printf(sc->dev, 5990 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5991 devinfo->nid, devinfo->codec->cad); 5992 ); 5993 hdac_audio_parse(devinfo); 5994 HDA_BOOTVERBOSE( 5995 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5996 ); 5997 hdac_audio_ctl_parse(devinfo); 5998 HDA_BOOTVERBOSE( 5999 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 6000 ); 6001 hdac_vendor_patch_parse(devinfo); 6002 if (quirks_on != 0) 6003 devinfo->function.audio.quirks |= quirks_on; 6004 if (quirks_off != 0) 6005 devinfo->function.audio.quirks &= ~quirks_off; 6006 6007 /* XXX Disable all DIGITAL path. */ 6008 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6009 w = hdac_widget_get(devinfo, i); 6010 if (w == NULL) 6011 continue; 6012 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 6013 w->enable = 0; 6014 continue; 6015 } 6016 /* XXX Disable useless pin ? */ 6017 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6018 (w->wclass.pin.config & 6019 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 6020 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 6021 w->enable = 0; 6022 } 6023 i = 0; 6024 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6025 if (ctl->widget == NULL) 6026 continue; 6027 if (ctl->ossmask & SOUND_MASK_DISABLE) 6028 ctl->enable = 0; 6029 w = ctl->widget; 6030 if (w->enable == 0 || 6031 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6032 ctl->enable = 0; 6033 w = ctl->childwidget; 6034 if (w == NULL) 6035 continue; 6036 if (w->enable == 0 || 6037 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6038 ctl->enable = 0; 6039 } 6040 6041 HDA_BOOTVERBOSE( 6042 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 6043 ); 6044 hdac_audio_build_tree(devinfo); 6045 6046 i = 0; 6047 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6048 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)) 6049 ctl->ossmask = 0; 6050 } 6051 HDA_BOOTVERBOSE( 6052 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 6053 ); 6054 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 6055 HDA_BOOTVERBOSE( 6056 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 6057 ); 6058 hdac_audio_ctl_commit(devinfo); 6059 6060 HDA_BOOTVERBOSE( 6061 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 6062 ); 6063 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 6064 HDA_BOOTVERBOSE( 6065 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 6066 ); 6067 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 6068 6069 hdac_unlock(sc); 6070 HDA_BOOTVERBOSE( 6071 device_printf(sc->dev, 6072 "HDA_DEBUG: OSS mixer initialization...\n"); 6073 ); 6074 6075 /* 6076 * There is no point of return after this. If the driver failed, 6077 * so be it. Let the detach procedure do all the cleanup. 6078 */ 6079 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 6080 device_printf(sc->dev, "Can't register mixer\n"); 6081 6082 if (pcnt > 0) 6083 pcnt = 1; 6084 if (rcnt > 0) 6085 rcnt = 1; 6086 6087 HDA_BOOTVERBOSE( 6088 device_printf(sc->dev, 6089 "HDA_DEBUG: Registering PCM channels...\n"); 6090 ); 6091 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 6092 device_printf(sc->dev, "Can't register PCM\n"); 6093 6094 sc->registered++; 6095 6096 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 6097 hdac_dma_alloc(sc, &sc->pos_dma, 6098 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 6099 HDA_BOOTVERBOSE( 6100 device_printf(sc->dev, 6101 "Failed to allocate DMA pos buffer (non-fatal)\n"); 6102 ); 6103 } 6104 6105 for (i = 0; i < pcnt; i++) 6106 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 6107 for (i = 0; i < rcnt; i++) 6108 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 6109 6110#ifdef SND_DYNSYSCTL 6111 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6112 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6113 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6114 sysctl_hdac_polling, "I", "Enable polling mode"); 6115 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6116 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6117 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 6118 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 6119 "Controller/Jack Sense polling interval (1-1000 ms)"); 6120#ifdef SND_DEBUG 6121 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 6122 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 6123 "dump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 6124 sysctl_hdac_dump, "I", "Dump states"); 6125#endif 6126#endif 6127 6128 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 6129 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 6130 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 6131 pcm_setstatus(sc->dev, status); 6132 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 6133 HDA_BOOTVERBOSE( 6134 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 6135 hdac_codec_id(devinfo)); 6136 ); 6137 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 6138 HDA_DRV_TEST_REV); 6139 6140 HDA_BOOTVERBOSE( 6141 if (devinfo->function.audio.quirks != 0) { 6142 device_printf(sc->dev, "\n"); 6143 device_printf(sc->dev, "HDA config/quirks:"); 6144 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 6145 if ((devinfo->function.audio.quirks & 6146 hdac_quirks_tab[i].value) == 6147 hdac_quirks_tab[i].value) 6148 printf(" %s", hdac_quirks_tab[i].key); 6149 } 6150 printf("\n"); 6151 } 6152 device_printf(sc->dev, "\n"); 6153 device_printf(sc->dev, "+-------------------+\n"); 6154 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 6155 device_printf(sc->dev, "+-------------------+\n"); 6156 hdac_dump_nodes(devinfo); 6157 device_printf(sc->dev, "\n"); 6158 device_printf(sc->dev, "+------------------------+\n"); 6159 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 6160 device_printf(sc->dev, "+------------------------+\n"); 6161 device_printf(sc->dev, "\n"); 6162 i = 0; 6163 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6164 device_printf(sc->dev, "%3d: nid=%d", i, 6165 (ctl->widget != NULL) ? ctl->widget->nid : -1); 6166 if (ctl->childwidget != NULL) 6167 printf(" cnid=%d", ctl->childwidget->nid); 6168 printf(" dir=0x%x index=%d " 6169 "ossmask=0x%08x ossdev=%d%s\n", 6170 ctl->dir, ctl->index, 6171 ctl->ossmask, ctl->ossdev, 6172 (ctl->enable == 0) ? " [DISABLED]" : ""); 6173 } 6174 device_printf(sc->dev, "\n"); 6175 device_printf(sc->dev, "+-----------------------------------+\n"); 6176 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 6177 device_printf(sc->dev, "+-----------------------------------+\n"); 6178 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 6179 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 6180 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 6181 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 6182 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 6183 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 6184 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 6185 hdac_dump_ctls(devinfo, NULL, 0); 6186 hdac_dump_dac(devinfo); 6187 hdac_dump_adc(devinfo); 6188 device_printf(sc->dev, "\n"); 6189 device_printf(sc->dev, "+--------------------------------------+\n"); 6190 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 6191 device_printf(sc->dev, "+--------------------------------------+\n"); 6192 hdac_dump_pcmchannels(sc, pcnt, rcnt); 6193 ); 6194 6195 if (sc->polling != 0) { 6196 hdac_lock(sc); 6197 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 6198 hdac_unlock(sc); 6199 } 6200} 6201 6202/**************************************************************************** 6203 * int hdac_detach(device_t) 6204 * 6205 * Detach and free up resources utilized by the hdac device. 6206 ****************************************************************************/ 6207static int 6208hdac_detach(device_t dev) 6209{ 6210 struct hdac_softc *sc = NULL; 6211 struct hdac_devinfo *devinfo = NULL; 6212 int err; 6213 6214 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 6215 if (devinfo != NULL && devinfo->codec != NULL) 6216 sc = devinfo->codec->sc; 6217 if (sc == NULL) 6218 return (0); 6219 6220 if (sc->registered > 0) { 6221 err = pcm_unregister(dev); 6222 if (err != 0) 6223 return (err); 6224 } 6225 6226 hdac_release_resources(sc); 6227 6228 return (0); 6229} 6230 6231static device_method_t hdac_methods[] = { 6232 /* device interface */ 6233 DEVMETHOD(device_probe, hdac_probe), 6234 DEVMETHOD(device_attach, hdac_attach), 6235 DEVMETHOD(device_detach, hdac_detach), 6236 { 0, 0 } 6237}; 6238 6239static driver_t hdac_driver = { 6240 "pcm", 6241 hdac_methods, 6242 PCM_SOFTC_SIZE, 6243}; 6244 6245DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 6246MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 6247MODULE_VERSION(snd_hda, 1); 6248