hdac.c revision 167738
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83/* 84 * XXX PAT superhero, until we have true support for BUS_DMA_NOCACHE. 85 * Blindly assume that pmap_change_attr() exist if PAT_UNCACHEABLE 86 * is defined. If not, fetch it from our cute little-pmap. 87 */ 88#if defined(__i386__) || defined(__amd64__) 89#include <machine/specialreg.h> 90#ifndef PAT_UNCACHEABLE 91#include <dev/sound/pci/hda/lpmap.c> 92#endif 93#endif 94 95#define HDAC_DMA_UNCACHEABLE 0 96#define HDAC_DMA_WRITEBACK 1 97 98#define HDA_DRV_TEST_REV "20070320_0043" 99#define HDA_WIDGET_PARSER_REV 1 100 101SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 167738 2007-03-20 11:24:29Z ariff $"); 102 103#undef HDA_DEBUG_ENABLED 104#define HDA_DEBUG_ENABLED 1 105 106#ifdef HDA_DEBUG_ENABLED 107#define HDA_DEBUG(stmt) do { \ 108 stmt \ 109} while(0) 110#else 111#define HDA_DEBUG(stmt) 112#endif 113 114#define HDA_BOOTVERBOSE(stmt) do { \ 115 if (bootverbose) { \ 116 stmt \ 117 } \ 118} while(0) 119 120#if 1 121#undef HDAC_INTR_EXTRA 122#define HDAC_INTR_EXTRA 1 123#endif 124 125#define hdac_lock(sc) snd_mtxlock((sc)->lock) 126#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 127#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 128#define hdac_lockowned(sc) mtx_owned((sc)->lock) 129 130#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 131#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 132 (fl) == 0xffffffff || \ 133 (((fl) & 0xffff0000) == 0xffff0000 && \ 134 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 135 (((fl) & 0x0000ffff) == 0x0000ffff && \ 136 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 137#define HDA_MATCH_ALL 0xffffffff 138#define HDAC_INVALID 0xffffffff 139 140#define HDA_MODEL_CONSTRUCT(vendor, model) \ 141 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 142 143/* Controller models */ 144 145/* Intel */ 146#define INTEL_VENDORID 0x8086 147#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 151#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 152 153/* Nvidia */ 154#define NVIDIA_VENDORID 0x10de 155#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 156#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 157#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 158#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 159#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 160#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 161#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 162 163/* ATI */ 164#define ATI_VENDORID 0x1002 165#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 166#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 167#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 168 169/* VIA */ 170#define VIA_VENDORID 0x1106 171#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 172#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 173 174/* SiS */ 175#define SIS_VENDORID 0x1039 176#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 177#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 178 179/* OEM/subvendors */ 180 181/* Intel */ 182#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 183 184/* HP/Compaq */ 185#define HP_VENDORID 0x103c 186#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 187#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 188#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 189#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 190#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 191#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 192/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 193#define HP_NX6325_SUBVENDORX 0x103c30b0 194 195/* Dell */ 196#define DELL_VENDORID 0x1028 197#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 198#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 199#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 200 201/* Clevo */ 202#define CLEVO_VENDORID 0x1558 203#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 204#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 205 206/* Acer */ 207#define ACER_VENDORID 0x1025 208#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 209#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 210 211/* Asus */ 212#define ASUS_VENDORID 0x1043 213#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 214#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 215#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 216#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 217#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 218#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 219#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 220#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 221 222/* IBM / Lenovo */ 223#define IBM_VENDORID 0x1014 224#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 225#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 226 227/* Lenovo */ 228#define LENOVO_VENDORID 0x17aa 229#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 230#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 231 232/* Samsung */ 233#define SAMSUNG_VENDORID 0x144d 234#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 235#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 236 237/* Medion ? */ 238#define MEDION_VENDORID 0x161f 239#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 240#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 241 242/* 243 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 244 * instead of their own, which is beyond my comprehension 245 * (see HDA_CODEC_STAC9221 below). 246 */ 247#define APPLE_INTEL_MAC 0x76808384 248 249/* LG Electronics */ 250#define LG_VENDORID 0x1854 251#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 252#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 253 254/* Fujitsu Siemens */ 255#define FS_VENDORID 0x1734 256#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 257#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 258 259/* Toshiba */ 260#define TOSHIBA_VENDORID 0x1179 261#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 262#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 263 264/* Micro-Star International (MSI) */ 265#define MSI_VENDORID 0x1462 266#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 267#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 268 269/* Misc constants.. */ 270#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 271#define HDA_AMP_MUTE_NONE (0) 272#define HDA_AMP_MUTE_LEFT (1 << 0) 273#define HDA_AMP_MUTE_RIGHT (1 << 1) 274#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 275 276#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 277#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 278 279#define HDA_DAC_PATH (1 << 0) 280#define HDA_ADC_PATH (1 << 1) 281#define HDA_ADC_RECSEL (1 << 2) 282 283#define HDA_CTL_OUT (1 << 0) 284#define HDA_CTL_IN (1 << 1) 285#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 286 287#define HDA_GPIO_MAX 15 288/* 0 - 14 = GPIO */ 289#define HDA_QUIRK_GPIO0 (1 << 0) 290#define HDA_QUIRK_GPIO1 (1 << 1) 291#define HDA_QUIRK_GPIO2 (1 << 2) 292#define HDA_QUIRK_GPIOFLUSH (1 << 15) 293#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 294#define HDA_QUIRK_FIXEDRATE (1 << 17) 295#define HDA_QUIRK_FORCESTEREO (1 << 18) 296#define HDA_QUIRK_EAPDINV (1 << 19) 297#define HDA_QUIRK_VREF (1 << 20) 298 299static const struct { 300 char *key; 301 uint32_t value; 302} hdac_quirks_tab[] = { 303 { "gpio0", HDA_QUIRK_GPIO0 }, 304 { "gpio1", HDA_QUIRK_GPIO1 }, 305 { "gpio2", HDA_QUIRK_GPIO2 }, 306 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 307 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 308 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 309 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 310 { "eapdinv", HDA_QUIRK_EAPDINV }, 311 { "vref", HDA_QUIRK_VREF }, 312}; 313#define HDAC_QUIRKS_TAB_LEN \ 314 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 315 316#define HDA_BDL_MIN 2 317#define HDA_BDL_MAX 256 318#define HDA_BDL_DEFAULT HDA_BDL_MIN 319 320#define HDA_BLK_MIN 128 321#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 322 323#define HDA_BUFSZ_MIN 4096 324#define HDA_BUFSZ_MAX 65536 325#define HDA_BUFSZ_DEFAULT 16384 326 327#define HDA_PARSE_MAXDEPTH 10 328 329#define HDAC_UNSOLTAG_EVENT_HP 0x00 330 331MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 332 333enum { 334 HDA_PARSE_MIXER, 335 HDA_PARSE_DIRECT 336}; 337 338/* Default */ 339static uint32_t hdac_fmt[] = { 340 AFMT_STEREO | AFMT_S16_LE, 341 0 342}; 343 344static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 345 346static const struct { 347 uint32_t model; 348 char *desc; 349} hdac_devices[] = { 350 { HDA_INTEL_82801F, "Intel 82801F" }, 351 { HDA_INTEL_82801G, "Intel 82801G" }, 352 { HDA_INTEL_82801H, "Intel 82801H" }, 353 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 354 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 355 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 356 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 357 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 358 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 359 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 360 { HDA_ATI_SB450, "ATI SB450" }, 361 { HDA_ATI_SB600, "ATI SB600" }, 362 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 363 { HDA_SIS_966, "SiS 966" }, 364 /* Unknown */ 365 { HDA_INTEL_ALL, "Intel (Unknown)" }, 366 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 367 { HDA_ATI_ALL, "ATI (Unknown)" }, 368 { HDA_VIA_ALL, "VIA (Unknown)" }, 369 { HDA_SIS_ALL, "SiS (Unknown)" }, 370}; 371#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 372 373static const struct { 374 uint32_t rate; 375 int valid; 376 uint16_t base; 377 uint16_t mul; 378 uint16_t div; 379} hda_rate_tab[] = { 380 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 381 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 382 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 383 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 384 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 385 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 386 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 387 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 388 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 389 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 390 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 391 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 392 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 393 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 394 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 395 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 396 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 397 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 398 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 399 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 400 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 401 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 402 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 403 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 404 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 405 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 406 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 407 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 408 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 409 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 410 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 411 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 412 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 413 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 414 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 415}; 416#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 417 418/* All codecs you can eat... */ 419#define HDA_CODEC_CONSTRUCT(vendor, id) \ 420 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 421 422/* Realtek */ 423#define REALTEK_VENDORID 0x10ec 424#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 425#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 426#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 427#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 428#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 429#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 430#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 431 432/* Analog Device */ 433#define ANALOGDEVICE_VENDORID 0x11d4 434#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 435#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 436#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 437#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 438 439/* CMedia */ 440#define CMEDIA_VENDORID 0x434d 441#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 442#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 443 444/* Sigmatel */ 445#define SIGMATEL_VENDORID 0x8384 446#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 447#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 448#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 449#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 450#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 451#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 452#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 453 454/* 455 * Conexant 456 * 457 * Ok, the truth is, I don't have any idea at all whether 458 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 459 * place that tell me it is "Venice" is from its Windows driver INF. 460 * 461 * Venice - CX????? 462 * Waikiki - CX20551-22 463 */ 464#define CONEXANT_VENDORID 0x14f1 465#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 466#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 467#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 468 469 470/* Codecs */ 471static const struct { 472 uint32_t id; 473 char *name; 474} hdac_codecs[] = { 475 { HDA_CODEC_ALC260, "Realtek ALC260" }, 476 { HDA_CODEC_ALC861, "Realtek ALC861" }, 477 { HDA_CODEC_ALC880, "Realtek ALC880" }, 478 { HDA_CODEC_ALC882, "Realtek ALC882" }, 479 { HDA_CODEC_ALC883, "Realtek ALC883" }, 480 { HDA_CODEC_ALC888, "Realtek ALC888" }, 481 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 482 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 483 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 484 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 485 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 486 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 487 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 488 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 489 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 490 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 491 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 492 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 493 /* Unknown codec */ 494 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 495 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 496 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 497 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 498 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 499}; 500#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 501 502enum { 503 HDAC_HP_SWITCH_CTL, 504 HDAC_HP_SWITCH_CTRL 505}; 506 507static const struct { 508 uint32_t model; 509 uint32_t id; 510 int type; 511 int inverted; 512 nid_t hpnid; 513 nid_t spkrnid[8]; 514 nid_t eapdnid; 515} hdac_hp_switch[] = { 516 /* Specific OEM models */ 517 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 518 17, { 16, -1 }, 16 }, 519 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 520 6, { 5, -1 }, 5 }, 521 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 522 6, { 5, -1 }, 5 }, 523 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 524 6, { 5, -1 }, 5 }, 525 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 526 6, { 5, -1 }, -1 }, 527 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 528 13, { 14, -1 }, -1 }, 529 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 530 13, { 14, -1 }, -1 }, 531 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 532 10, { 13, -1 }, -1 }, 533 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 534 26, { 27, -1 }, -1 }, 535 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 536 27, { 20, -1 }, -1 }, 537 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 538 20, { 21, -1 }, -1 }, 539 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 540 20, { 27, -1 }, -1 }, 541 /* 542 * All models that at least come from the same vendor with 543 * simmilar codec. 544 */ 545 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 546 17, { 16, -1 }, 16 }, 547 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 548 6, { 5, -1 }, 5 }, 549 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 550 6, { 5, -1 }, -1 }, 551 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 552 13, { 14, -1 }, -1 }, 553 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 554 26, { 27, -1 }, -1 }, 555#if 0 556 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 557 20, { 21, -1 }, -1 }, 558#endif 559}; 560#define HDAC_HP_SWITCH_LEN \ 561 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 562 563static const struct { 564 uint32_t model; 565 uint32_t id; 566 nid_t eapdnid; 567 int hp_switch; 568} hdac_eapd_switch[] = { 569 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 570 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 571 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 572}; 573#define HDAC_EAPD_SWITCH_LEN \ 574 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 575 576/**************************************************************************** 577 * Function prototypes 578 ****************************************************************************/ 579static void hdac_intr_handler(void *); 580static int hdac_reset(struct hdac_softc *); 581static int hdac_get_capabilities(struct hdac_softc *); 582static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 583static int hdac_dma_alloc(struct hdac_softc *, 584 struct hdac_dma *, bus_size_t); 585static void hdac_dma_free(struct hdac_dma *); 586static int hdac_mem_alloc(struct hdac_softc *); 587static void hdac_mem_free(struct hdac_softc *); 588static int hdac_irq_alloc(struct hdac_softc *); 589static void hdac_irq_free(struct hdac_softc *); 590static void hdac_corb_init(struct hdac_softc *); 591static void hdac_rirb_init(struct hdac_softc *); 592static void hdac_corb_start(struct hdac_softc *); 593static void hdac_rirb_start(struct hdac_softc *); 594static void hdac_scan_codecs(struct hdac_softc *); 595static int hdac_probe_codec(struct hdac_codec *); 596static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 597static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 598 599static void hdac_attach2(void *); 600 601static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 602 uint32_t, int); 603static void hdac_command_send_internal(struct hdac_softc *, 604 struct hdac_command_list *, int); 605 606static int hdac_probe(device_t); 607static int hdac_attach(device_t); 608static int hdac_detach(device_t); 609static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 610static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 611 uint32_t, int, int); 612static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 613 nid_t, int, int); 614static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 615 nid_t, nid_t, int, int, int, int, int, int); 616static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 617static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 618 619static int hdac_rirb_flush(struct hdac_softc *sc); 620static int hdac_unsolq_flush(struct hdac_softc *sc); 621 622#define hdac_command(a1, a2, a3) \ 623 hdac_command_sendone_internal(a1, a2, a3) 624 625#define hdac_codec_id(d) \ 626 ((uint32_t)((d == NULL) ? 0x00000000 : \ 627 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 628 ((uint32_t)(d)->device_id & 0x0000ffff)))) 629 630static char * 631hdac_codec_name(struct hdac_devinfo *devinfo) 632{ 633 uint32_t id; 634 int i; 635 636 id = hdac_codec_id(devinfo); 637 638 for (i = 0; i < HDAC_CODECS_LEN; i++) { 639 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 640 return (hdac_codecs[i].name); 641 } 642 643 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 644} 645 646static char * 647hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 648{ 649 static char *ossname[] = SOUND_DEVICE_NAMES; 650 static char *unknown = "???"; 651 int i; 652 653 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 654 if (devmask & (1 << i)) 655 return (ossname[i]); 656 } 657 return (unknown); 658} 659 660static void 661hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 662{ 663 static char *ossname[] = SOUND_DEVICE_NAMES; 664 int i, first = 1; 665 666 bzero(buf, len); 667 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 668 if (mask & (1 << i)) { 669 if (first == 0) 670 strlcat(buf, ", ", len); 671 strlcat(buf, ossname[i], len); 672 first = 0; 673 } 674 } 675} 676 677static struct hdac_audio_ctl * 678hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 679{ 680 if (devinfo == NULL || 681 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 682 index == NULL || devinfo->function.audio.ctl == NULL || 683 devinfo->function.audio.ctlcnt < 1 || 684 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 685 return (NULL); 686 return (&devinfo->function.audio.ctl[(*index)++]); 687} 688 689static struct hdac_audio_ctl * 690hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 691 int index, int cnt) 692{ 693 struct hdac_audio_ctl *ctl, *retctl = NULL; 694 int i, at, atindex, found = 0; 695 696 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 697 return (NULL); 698 699 at = cnt; 700 if (at == 0) 701 at = 1; 702 else if (at < 0) 703 at = -1; 704 atindex = index; 705 if (atindex < 0) 706 atindex = -1; 707 708 i = 0; 709 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 710 if (ctl->enable == 0 || ctl->widget == NULL) 711 continue; 712 if (!(ctl->widget->nid == nid && (atindex == -1 || 713 ctl->index == atindex))) 714 continue; 715 found++; 716 if (found == cnt) 717 return (ctl); 718 retctl = ctl; 719 } 720 721 return ((at == -1) ? retctl : NULL); 722} 723 724static void 725hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 726{ 727 struct hdac_softc *sc; 728 struct hdac_widget *w; 729 struct hdac_audio_ctl *ctl; 730 uint32_t id, res; 731 int i = 0, j, forcemute; 732 nid_t cad; 733 734 if (devinfo == NULL || devinfo->codec == NULL || 735 devinfo->codec->sc == NULL) 736 return; 737 738 sc = devinfo->codec->sc; 739 cad = devinfo->codec->cad; 740 id = hdac_codec_id(devinfo); 741 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 742 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 743 sc->pci_subvendor) && 744 hdac_hp_switch[i].id == id) 745 break; 746 } 747 748 if (i >= HDAC_HP_SWITCH_LEN) 749 return; 750 751 forcemute = 0; 752 if (hdac_hp_switch[i].eapdnid != -1) { 753 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 754 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 755 forcemute = (w->param.eapdbtl & 756 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 757 } 758 759 res = hdac_command(sc, 760 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 761 HDA_BOOTVERBOSE( 762 device_printf(sc->dev, 763 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 764 hdac_hp_switch[i].hpnid, res); 765 ); 766 res >>= 31; 767 res ^= hdac_hp_switch[i].inverted; 768 769 switch (hdac_hp_switch[i].type) { 770 case HDAC_HP_SWITCH_CTL: 771 ctl = hdac_audio_ctl_amp_get(devinfo, 772 hdac_hp_switch[i].hpnid, 0, 1); 773 if (ctl != NULL) { 774 ctl->muted = (res != 0 && forcemute == 0) ? 775 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 776 hdac_audio_ctl_amp_set(ctl, 777 HDA_AMP_MUTE_DEFAULT, ctl->left, 778 ctl->right); 779 } 780 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 781 ctl = hdac_audio_ctl_amp_get(devinfo, 782 hdac_hp_switch[i].spkrnid[j], 0, 1); 783 if (ctl != NULL) { 784 ctl->muted = (res != 0 || forcemute == 1) ? 785 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 786 hdac_audio_ctl_amp_set(ctl, 787 HDA_AMP_MUTE_DEFAULT, ctl->left, 788 ctl->right); 789 } 790 } 791 break; 792 case HDAC_HP_SWITCH_CTRL: 793 if (res != 0) { 794 /* HP in */ 795 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 796 if (w != NULL && w->type == 797 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 798 if (forcemute == 0) 799 w->wclass.pin.ctrl |= 800 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 801 else 802 w->wclass.pin.ctrl &= 803 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 804 hdac_command(sc, 805 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 806 w->wclass.pin.ctrl), cad); 807 } 808 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 809 w = hdac_widget_get(devinfo, 810 hdac_hp_switch[i].spkrnid[j]); 811 if (w != NULL && w->type == 812 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 813 w->wclass.pin.ctrl &= 814 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 815 hdac_command(sc, 816 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 817 w->nid, 818 w->wclass.pin.ctrl), cad); 819 } 820 } 821 } else { 822 /* HP out */ 823 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 824 if (w != NULL && w->type == 825 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 826 w->wclass.pin.ctrl &= 827 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 828 hdac_command(sc, 829 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 830 w->wclass.pin.ctrl), cad); 831 } 832 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 833 w = hdac_widget_get(devinfo, 834 hdac_hp_switch[i].spkrnid[j]); 835 if (w != NULL && w->type == 836 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 837 if (forcemute == 0) 838 w->wclass.pin.ctrl |= 839 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 840 else 841 w->wclass.pin.ctrl &= 842 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 843 hdac_command(sc, 844 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 845 w->nid, 846 w->wclass.pin.ctrl), cad); 847 } 848 } 849 } 850 break; 851 default: 852 break; 853 } 854} 855 856static void 857hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 858{ 859 struct hdac_softc *sc; 860 struct hdac_devinfo *devinfo = NULL; 861 device_t *devlist = NULL; 862 int devcount, i; 863 864 if (codec == NULL || codec->sc == NULL) 865 return; 866 867 sc = codec->sc; 868 869 HDA_BOOTVERBOSE( 870 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 871 ); 872 873 device_get_children(sc->dev, &devlist, &devcount); 874 for (i = 0; devlist != NULL && i < devcount; i++) { 875 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 876 if (devinfo != NULL && devinfo->node_type == 877 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 878 devinfo->codec != NULL && 879 devinfo->codec->cad == codec->cad) { 880 break; 881 } else 882 devinfo = NULL; 883 } 884 if (devlist != NULL) 885 free(devlist, M_TEMP); 886 887 if (devinfo == NULL) 888 return; 889 890 switch (tag) { 891 case HDAC_UNSOLTAG_EVENT_HP: 892 hdac_hp_switch_handler(devinfo); 893 break; 894 default: 895 break; 896 } 897} 898 899static int 900hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 901{ 902 /* XXX to be removed */ 903#ifdef HDAC_INTR_EXTRA 904 uint32_t res; 905#endif 906 907 if (ch->blkcnt == 0) 908 return (0); 909 910 /* XXX to be removed */ 911#ifdef HDAC_INTR_EXTRA 912 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 913#endif 914 915 /* XXX to be removed */ 916#ifdef HDAC_INTR_EXTRA 917 HDA_BOOTVERBOSE( 918 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 919 device_printf(sc->dev, 920 "PCMDIR_%s intr triggered beyond stream boundary:" 921 "%08x\n", 922 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 923 ); 924#endif 925 926 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 927 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 928 929 /* XXX to be removed */ 930#ifdef HDAC_INTR_EXTRA 931 if (res & HDAC_SDSTS_BCIS) { 932#endif 933 return (1); 934 /* XXX to be removed */ 935#ifdef HDAC_INTR_EXTRA 936 } 937#endif 938 939 return (0); 940} 941 942/**************************************************************************** 943 * void hdac_intr_handler(void *) 944 * 945 * Interrupt handler. Processes interrupts received from the hdac. 946 ****************************************************************************/ 947static void 948hdac_intr_handler(void *context) 949{ 950 struct hdac_softc *sc; 951 uint32_t intsts; 952 uint8_t rirbsts; 953 struct hdac_rirb *rirb_base; 954 uint32_t trigger = 0; 955 956 sc = (struct hdac_softc *)context; 957 958 hdac_lock(sc); 959 if (sc->polling != 0) { 960 hdac_unlock(sc); 961 return; 962 } 963 /* Do we have anything to do? */ 964 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 965 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 966 hdac_unlock(sc); 967 return; 968 } 969 970 /* Was this a controller interrupt? */ 971 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 972 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 973 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 974 /* Get as many responses that we can */ 975 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 976 HDAC_WRITE_1(&sc->mem, 977 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 978 hdac_rirb_flush(sc); 979 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 980 } 981 /* XXX to be removed */ 982 /* Clear interrupt and exit */ 983#ifdef HDAC_INTR_EXTRA 984 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 985#endif 986 } 987 988 hdac_unsolq_flush(sc); 989 990 if (intsts & HDAC_INTSTS_SIS_MASK) { 991 if ((intsts & (1 << sc->num_iss)) && 992 hdac_stream_intr(sc, &sc->play) != 0) 993 trigger |= 1; 994 if ((intsts & (1 << 0)) && 995 hdac_stream_intr(sc, &sc->rec) != 0) 996 trigger |= 2; 997 /* XXX to be removed */ 998#ifdef HDAC_INTR_EXTRA 999 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1000 HDAC_INTSTS_SIS_MASK); 1001#endif 1002 } 1003 1004 hdac_unlock(sc); 1005 1006 if (trigger & 1) 1007 chn_intr(sc->play.c); 1008 if (trigger & 2) 1009 chn_intr(sc->rec.c); 1010} 1011 1012/**************************************************************************** 1013 * int hdac_reset(hdac_softc *) 1014 * 1015 * Reset the hdac to a quiescent and known state. 1016 ****************************************************************************/ 1017static int 1018hdac_reset(struct hdac_softc *sc) 1019{ 1020 uint32_t gctl; 1021 int count, i; 1022 1023 /* 1024 * Stop all Streams DMA engine 1025 */ 1026 for (i = 0; i < sc->num_iss; i++) 1027 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1028 for (i = 0; i < sc->num_oss; i++) 1029 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1030 for (i = 0; i < sc->num_bss; i++) 1031 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1032 1033 /* 1034 * Stop Control DMA engines 1035 */ 1036 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1037 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1038 1039 /* 1040 * Reset the controller. The reset must remain asserted for 1041 * a minimum of 100us. 1042 */ 1043 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1044 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1045 count = 10000; 1046 do { 1047 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1048 if (!(gctl & HDAC_GCTL_CRST)) 1049 break; 1050 DELAY(10); 1051 } while (--count); 1052 if (gctl & HDAC_GCTL_CRST) { 1053 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1054 return (ENXIO); 1055 } 1056 DELAY(100); 1057 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1058 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1059 count = 10000; 1060 do { 1061 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1062 if (gctl & HDAC_GCTL_CRST) 1063 break; 1064 DELAY(10); 1065 } while (--count); 1066 if (!(gctl & HDAC_GCTL_CRST)) { 1067 device_printf(sc->dev, "Device stuck in reset\n"); 1068 return (ENXIO); 1069 } 1070 1071 /* 1072 * Wait for codecs to finish their own reset sequence. The delay here 1073 * should be of 250us but for some reasons, on it's not enough on my 1074 * computer. Let's use twice as much as necessary to make sure that 1075 * it's reset properly. 1076 */ 1077 DELAY(1000); 1078 1079 return (0); 1080} 1081 1082 1083/**************************************************************************** 1084 * int hdac_get_capabilities(struct hdac_softc *); 1085 * 1086 * Retreive the general capabilities of the hdac; 1087 * Number of Input Streams 1088 * Number of Output Streams 1089 * Number of bidirectional Streams 1090 * 64bit ready 1091 * CORB and RIRB sizes 1092 ****************************************************************************/ 1093static int 1094hdac_get_capabilities(struct hdac_softc *sc) 1095{ 1096 uint16_t gcap; 1097 uint8_t corbsize, rirbsize; 1098 1099 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1100 sc->num_iss = HDAC_GCAP_ISS(gcap); 1101 sc->num_oss = HDAC_GCAP_OSS(gcap); 1102 sc->num_bss = HDAC_GCAP_BSS(gcap); 1103 1104 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1105 1106 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1107 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1108 HDAC_CORBSIZE_CORBSZCAP_256) 1109 sc->corb_size = 256; 1110 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1111 HDAC_CORBSIZE_CORBSZCAP_16) 1112 sc->corb_size = 16; 1113 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1114 HDAC_CORBSIZE_CORBSZCAP_2) 1115 sc->corb_size = 2; 1116 else { 1117 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1118 __func__, corbsize); 1119 return (ENXIO); 1120 } 1121 1122 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1123 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1124 HDAC_RIRBSIZE_RIRBSZCAP_256) 1125 sc->rirb_size = 256; 1126 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1127 HDAC_RIRBSIZE_RIRBSZCAP_16) 1128 sc->rirb_size = 16; 1129 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1130 HDAC_RIRBSIZE_RIRBSZCAP_2) 1131 sc->rirb_size = 2; 1132 else { 1133 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1134 __func__, rirbsize); 1135 return (ENXIO); 1136 } 1137 1138 return (0); 1139} 1140 1141 1142/**************************************************************************** 1143 * void hdac_dma_cb 1144 * 1145 * This function is called by bus_dmamap_load when the mapping has been 1146 * established. We just record the physical address of the mapping into 1147 * the struct hdac_dma passed in. 1148 ****************************************************************************/ 1149static void 1150hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1151{ 1152 struct hdac_dma *dma; 1153 1154 if (error == 0) { 1155 dma = (struct hdac_dma *)callback_arg; 1156 dma->dma_paddr = segs[0].ds_addr; 1157 } 1158} 1159 1160static void 1161hdac_dma_attr(vm_offset_t va, vm_size_t size, int mode) 1162{ 1163#if defined(__i386__) || defined(__amd64__) 1164 switch (mode) { 1165 case HDAC_DMA_UNCACHEABLE: 1166 pmap_change_attr(va, size, PAT_UNCACHEABLE); 1167 break; 1168 case HDAC_DMA_WRITEBACK: 1169 pmap_change_attr(va, size, PAT_WRITE_BACK); 1170 break; 1171 default: 1172 break; 1173 } 1174#endif 1175} 1176 1177/**************************************************************************** 1178 * int hdac_dma_alloc 1179 * 1180 * This function allocate and setup a dma region (struct hdac_dma). 1181 * It must be freed by a corresponding hdac_dma_free. 1182 ****************************************************************************/ 1183static int 1184hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1185{ 1186 int result; 1187 int lowaddr; 1188 1189 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1190 BUS_SPACE_MAXADDR_32BIT; 1191 bzero(dma, sizeof(*dma)); 1192 1193 /* 1194 * Create a DMA tag 1195 */ 1196 result = bus_dma_tag_create(NULL, /* parent */ 1197 HDAC_DMA_ALIGNMENT, /* alignment */ 1198 0, /* boundary */ 1199 lowaddr, /* lowaddr */ 1200 BUS_SPACE_MAXADDR, /* highaddr */ 1201 NULL, /* filtfunc */ 1202 NULL, /* fistfuncarg */ 1203 size, /* maxsize */ 1204 1, /* nsegments */ 1205 size, /* maxsegsz */ 1206 0, /* flags */ 1207 NULL, /* lockfunc */ 1208 NULL, /* lockfuncarg */ 1209 &dma->dma_tag); /* dmat */ 1210 if (result != 0) { 1211 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1212 __func__, result); 1213 goto fail; 1214 } 1215 1216 /* 1217 * Allocate DMA memory 1218 */ 1219 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1220 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map); 1221 if (result != 0) { 1222 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1223 __func__, result); 1224 goto fail; 1225 } 1226 1227 /* 1228 * Map the memory 1229 */ 1230 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1231 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1232 BUS_DMA_NOWAIT); 1233 if (result != 0 || dma->dma_paddr == 0) { 1234 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1235 __func__, result); 1236 goto fail; 1237 } 1238 hdac_dma_attr((vm_offset_t)dma->dma_vaddr, size, HDAC_DMA_UNCACHEABLE); 1239 dma->dma_size = size; 1240 1241 return (0); 1242fail: 1243 if (dma->dma_map != NULL) 1244 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1245 if (dma->dma_tag != NULL) 1246 bus_dma_tag_destroy(dma->dma_tag); 1247 return (result); 1248} 1249 1250 1251/**************************************************************************** 1252 * void hdac_dma_free(struct hdac_dma *) 1253 * 1254 * Free a struct dhac_dma that has been previously allocated via the 1255 * hdac_dma_alloc function. 1256 ****************************************************************************/ 1257static void 1258hdac_dma_free(struct hdac_dma *dma) 1259{ 1260 if (dma->dma_tag != NULL) { 1261 /* Flush caches */ 1262 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1263 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1264 hdac_dma_attr((vm_offset_t)dma->dma_vaddr, dma->dma_size, 1265 HDAC_DMA_WRITEBACK); 1266 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1267 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1268 bus_dma_tag_destroy(dma->dma_tag); 1269 } 1270} 1271 1272/**************************************************************************** 1273 * int hdac_mem_alloc(struct hdac_softc *) 1274 * 1275 * Allocate all the bus resources necessary to speak with the physical 1276 * controller. 1277 ****************************************************************************/ 1278static int 1279hdac_mem_alloc(struct hdac_softc *sc) 1280{ 1281 struct hdac_mem *mem; 1282 1283 mem = &sc->mem; 1284 mem->mem_rid = PCIR_BAR(0); 1285 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1286 &mem->mem_rid, RF_ACTIVE); 1287 if (mem->mem_res == NULL) { 1288 device_printf(sc->dev, 1289 "%s: Unable to allocate memory resource\n", __func__); 1290 return (ENOMEM); 1291 } 1292 mem->mem_tag = rman_get_bustag(mem->mem_res); 1293 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1294 1295 return (0); 1296} 1297 1298/**************************************************************************** 1299 * void hdac_mem_free(struct hdac_softc *) 1300 * 1301 * Free up resources previously allocated by hdac_mem_alloc. 1302 ****************************************************************************/ 1303static void 1304hdac_mem_free(struct hdac_softc *sc) 1305{ 1306 struct hdac_mem *mem; 1307 1308 mem = &sc->mem; 1309 if (mem->mem_res != NULL) 1310 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1311 mem->mem_res); 1312 mem->mem_res = NULL; 1313} 1314 1315/**************************************************************************** 1316 * int hdac_irq_alloc(struct hdac_softc *) 1317 * 1318 * Allocate and setup the resources necessary for interrupt handling. 1319 ****************************************************************************/ 1320static int 1321hdac_irq_alloc(struct hdac_softc *sc) 1322{ 1323 struct hdac_irq *irq; 1324 int result; 1325 1326 irq = &sc->irq; 1327 irq->irq_rid = 0x0; 1328 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1329 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1330 if (irq->irq_res == NULL) { 1331 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1332 __func__); 1333 goto fail; 1334 } 1335 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1336 hdac_intr_handler, sc, &irq->irq_handle); 1337 if (result != 0) { 1338 device_printf(sc->dev, 1339 "%s: Unable to setup interrupt handler (%x)\n", 1340 __func__, result); 1341 goto fail; 1342 } 1343 1344 return (0); 1345 1346fail: 1347 hdac_irq_free(sc); 1348 1349 return (ENXIO); 1350} 1351 1352/**************************************************************************** 1353 * void hdac_irq_free(struct hdac_softc *) 1354 * 1355 * Free up resources previously allocated by hdac_irq_alloc. 1356 ****************************************************************************/ 1357static void 1358hdac_irq_free(struct hdac_softc *sc) 1359{ 1360 struct hdac_irq *irq; 1361 1362 irq = &sc->irq; 1363 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1364 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1365 if (irq->irq_res != NULL) 1366 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1367 irq->irq_res); 1368 irq->irq_handle = NULL; 1369 irq->irq_res = NULL; 1370} 1371 1372/**************************************************************************** 1373 * void hdac_corb_init(struct hdac_softc *) 1374 * 1375 * Initialize the corb registers for operations but do not start it up yet. 1376 * The CORB engine must not be running when this function is called. 1377 ****************************************************************************/ 1378static void 1379hdac_corb_init(struct hdac_softc *sc) 1380{ 1381 uint8_t corbsize; 1382 uint64_t corbpaddr; 1383 1384 /* Setup the CORB size. */ 1385 switch (sc->corb_size) { 1386 case 256: 1387 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1388 break; 1389 case 16: 1390 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1391 break; 1392 case 2: 1393 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1394 break; 1395 default: 1396 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1397 } 1398 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1399 1400 /* Setup the CORB Address in the hdac */ 1401 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1402 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1403 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1404 1405 /* Set the WP and RP */ 1406 sc->corb_wp = 0; 1407 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1408 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1409 /* 1410 * The HDA specification indicates that the CORBRPRST bit will always 1411 * read as zero. Unfortunately, it seems that at least the 82801G 1412 * doesn't reset the bit to zero, which stalls the corb engine. 1413 * manually reset the bit to zero before continuing. 1414 */ 1415 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1416 1417 /* Enable CORB error reporting */ 1418#if 0 1419 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1420#endif 1421} 1422 1423/**************************************************************************** 1424 * void hdac_rirb_init(struct hdac_softc *) 1425 * 1426 * Initialize the rirb registers for operations but do not start it up yet. 1427 * The RIRB engine must not be running when this function is called. 1428 ****************************************************************************/ 1429static void 1430hdac_rirb_init(struct hdac_softc *sc) 1431{ 1432 uint8_t rirbsize; 1433 uint64_t rirbpaddr; 1434 1435 /* Setup the RIRB size. */ 1436 switch (sc->rirb_size) { 1437 case 256: 1438 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1439 break; 1440 case 16: 1441 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1442 break; 1443 case 2: 1444 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1445 break; 1446 default: 1447 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1448 } 1449 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1450 1451 /* Setup the RIRB Address in the hdac */ 1452 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1453 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1454 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1455 1456 /* Setup the WP and RP */ 1457 sc->rirb_rp = 0; 1458 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1459 1460 if (sc->polling == 0) { 1461 /* Setup the interrupt threshold */ 1462 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1463 1464 /* Enable Overrun and response received reporting */ 1465#if 0 1466 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1467 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1468#else 1469 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1470#endif 1471 } 1472 1473 /* 1474 * Make sure that the Host CPU cache doesn't contain any dirty 1475 * cache lines that falls in the rirb. If I understood correctly, it 1476 * should be sufficient to do this only once as the rirb is purely 1477 * read-only from now on. 1478 */ 1479 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1480 BUS_DMASYNC_PREREAD); 1481} 1482 1483/**************************************************************************** 1484 * void hdac_corb_start(hdac_softc *) 1485 * 1486 * Startup the corb DMA engine 1487 ****************************************************************************/ 1488static void 1489hdac_corb_start(struct hdac_softc *sc) 1490{ 1491 uint32_t corbctl; 1492 1493 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1494 corbctl |= HDAC_CORBCTL_CORBRUN; 1495 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1496} 1497 1498/**************************************************************************** 1499 * void hdac_rirb_start(hdac_softc *) 1500 * 1501 * Startup the rirb DMA engine 1502 ****************************************************************************/ 1503static void 1504hdac_rirb_start(struct hdac_softc *sc) 1505{ 1506 uint32_t rirbctl; 1507 1508 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1509 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1510 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1511} 1512 1513 1514/**************************************************************************** 1515 * void hdac_scan_codecs(struct hdac_softc *) 1516 * 1517 * Scan the bus for available codecs. 1518 ****************************************************************************/ 1519static void 1520hdac_scan_codecs(struct hdac_softc *sc) 1521{ 1522 struct hdac_codec *codec; 1523 int i; 1524 uint16_t statests; 1525 1526 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1527 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1528 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1529 /* We have found a codec. */ 1530 hdac_unlock(sc); 1531 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1532 M_HDAC, M_ZERO | M_NOWAIT); 1533 hdac_lock(sc); 1534 if (codec == NULL) { 1535 device_printf(sc->dev, 1536 "Unable to allocate memory for codec\n"); 1537 continue; 1538 } 1539 codec->commands = NULL; 1540 codec->responses_received = 0; 1541 codec->verbs_sent = 0; 1542 codec->sc = sc; 1543 codec->cad = i; 1544 sc->codecs[i] = codec; 1545 if (hdac_probe_codec(codec) != 0) 1546 break; 1547 } 1548 } 1549 /* All codecs have been probed, now try to attach drivers to them */ 1550 /* bus_generic_attach(sc->dev); */ 1551} 1552 1553/**************************************************************************** 1554 * void hdac_probe_codec(struct hdac_softc *, int) 1555 * 1556 * Probe a the given codec_id for available function groups. 1557 ****************************************************************************/ 1558static int 1559hdac_probe_codec(struct hdac_codec *codec) 1560{ 1561 struct hdac_softc *sc = codec->sc; 1562 struct hdac_devinfo *devinfo; 1563 uint32_t vendorid, revisionid, subnode; 1564 int startnode; 1565 int endnode; 1566 int i; 1567 nid_t cad = codec->cad; 1568 1569 HDA_BOOTVERBOSE( 1570 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1571 ); 1572 vendorid = hdac_command(sc, 1573 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1574 cad); 1575 revisionid = hdac_command(sc, 1576 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1577 cad); 1578 subnode = hdac_command(sc, 1579 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1580 cad); 1581 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1582 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1583 1584 HDA_BOOTVERBOSE( 1585 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1586 startnode, endnode); 1587 ); 1588 for (i = startnode; i < endnode; i++) { 1589 devinfo = hdac_probe_function(codec, i); 1590 if (devinfo != NULL) { 1591 /* XXX Ignore other FG. */ 1592 devinfo->vendor_id = 1593 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1594 devinfo->device_id = 1595 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1596 devinfo->revision_id = 1597 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1598 devinfo->stepping_id = 1599 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1600 HDA_BOOTVERBOSE( 1601 device_printf(sc->dev, 1602 "HDA_DEBUG: \tFound AFG nid=%d " 1603 "[startnode=%d endnode=%d]\n", 1604 devinfo->nid, startnode, endnode); 1605 ); 1606 return (1); 1607 } 1608 } 1609 1610 HDA_BOOTVERBOSE( 1611 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1612 ); 1613 return (0); 1614} 1615 1616static struct hdac_devinfo * 1617hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1618{ 1619 struct hdac_softc *sc = codec->sc; 1620 struct hdac_devinfo *devinfo; 1621 uint32_t fctgrptype; 1622 nid_t cad = codec->cad; 1623 1624 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1625 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1626 1627 /* XXX For now, ignore other FG. */ 1628 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1629 return (NULL); 1630 1631 hdac_unlock(sc); 1632 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1633 M_NOWAIT | M_ZERO); 1634 hdac_lock(sc); 1635 if (devinfo == NULL) { 1636 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1637 __func__); 1638 return (NULL); 1639 } 1640 1641 devinfo->nid = nid; 1642 devinfo->node_type = fctgrptype; 1643 devinfo->codec = codec; 1644 1645 hdac_add_child(sc, devinfo); 1646 1647 return (devinfo); 1648} 1649 1650static void 1651hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1652{ 1653 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1654 device_set_ivars(devinfo->dev, (void *)devinfo); 1655 /* XXX - Print more information when booting verbose??? */ 1656} 1657 1658static void 1659hdac_widget_connection_parse(struct hdac_widget *w) 1660{ 1661 struct hdac_softc *sc = w->devinfo->codec->sc; 1662 uint32_t res; 1663 int i, j, max, found, entnum, cnid; 1664 nid_t cad = w->devinfo->codec->cad; 1665 nid_t nid = w->nid; 1666 1667 res = hdac_command(sc, 1668 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1669 1670 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1671 1672 if (w->nconns < 1) 1673 return; 1674 1675 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1676 res = 0; 1677 i = 0; 1678 found = 0; 1679 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1680 1681 while (i < w->nconns) { 1682 res = hdac_command(sc, 1683 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1684 for (j = 0; j < entnum; j++) { 1685 cnid = res; 1686 cnid >>= (32 / entnum) * j; 1687 cnid &= (1 << (32 / entnum)) - 1; 1688 if (cnid == 0) 1689 continue; 1690 if (found > max) { 1691 device_printf(sc->dev, 1692 "node %d: Adding %d: " 1693 "Max connection reached!\n", 1694 nid, cnid); 1695 continue; 1696 } 1697 w->conns[found++] = cnid; 1698 } 1699 i += entnum; 1700 } 1701 1702 HDA_BOOTVERBOSE( 1703 if (w->nconns != found) { 1704 device_printf(sc->dev, 1705 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1706 "length=%d != found=%d\n", 1707 nid, w->nconns, found); 1708 } 1709 ); 1710} 1711 1712static uint32_t 1713hdac_widget_pin_getconfig(struct hdac_widget *w) 1714{ 1715 struct hdac_softc *sc; 1716 uint32_t config, orig, id; 1717 nid_t cad, nid; 1718 1719 sc = w->devinfo->codec->sc; 1720 cad = w->devinfo->codec->cad; 1721 nid = w->nid; 1722 id = hdac_codec_id(w->devinfo); 1723 1724 config = hdac_command(sc, 1725 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1726 cad); 1727 orig = config; 1728 1729 /* 1730 * XXX REWRITE!!!! Don't argue! 1731 */ 1732 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1733 switch (nid) { 1734 case 26: 1735 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1736 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1737 break; 1738 case 27: 1739 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1740 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1741 break; 1742 default: 1743 break; 1744 } 1745 } else if (id == HDA_CODEC_ALC880 && 1746 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1747 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1748 /* 1749 * Super broken BIOS 1750 */ 1751 switch (nid) { 1752 case 20: 1753 break; 1754 case 21: 1755 break; 1756 case 22: 1757 break; 1758 case 23: 1759 break; 1760 case 24: /* MIC1 */ 1761 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1762 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1763 break; 1764 case 25: /* XXX MIC2 */ 1765 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1766 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1767 break; 1768 case 26: /* LINE1 */ 1769 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1770 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1771 break; 1772 case 27: /* XXX LINE2 */ 1773 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1774 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1775 break; 1776 case 28: /* CD */ 1777 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1778 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1779 break; 1780 case 30: 1781 break; 1782 case 31: 1783 break; 1784 default: 1785 break; 1786 } 1787 } else if (id == HDA_CODEC_ALC883 && 1788 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1789 switch (nid) { 1790 case 25: 1791 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1792 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1793 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1794 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1795 break; 1796 default: 1797 break; 1798 } 1799 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1800 HP_V3000_SUBVENDOR) { 1801 switch (nid) { 1802 case 18: 1803 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1804 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1805 break; 1806 case 20: 1807 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1808 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1809 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1810 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1811 break; 1812 case 21: 1813 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1814 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1815 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1816 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1817 break; 1818 default: 1819 break; 1820 } 1821 } 1822 1823 HDA_BOOTVERBOSE( 1824 if (config != orig) 1825 device_printf(sc->dev, 1826 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 1827 nid, orig, config); 1828 ); 1829 1830 return (config); 1831} 1832 1833static uint32_t 1834hdac_widget_pin_getcaps(struct hdac_widget *w) 1835{ 1836 struct hdac_softc *sc; 1837 uint32_t caps, orig, id; 1838 nid_t cad, nid; 1839 1840 sc = w->devinfo->codec->sc; 1841 cad = w->devinfo->codec->cad; 1842 nid = w->nid; 1843 id = hdac_codec_id(w->devinfo); 1844 1845 caps = hdac_command(sc, 1846 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1847 orig = caps; 1848 1849 HDA_BOOTVERBOSE( 1850 if (caps != orig) 1851 device_printf(sc->dev, 1852 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 1853 nid, orig, caps); 1854 ); 1855 1856 return (caps); 1857} 1858 1859static void 1860hdac_widget_pin_parse(struct hdac_widget *w) 1861{ 1862 struct hdac_softc *sc = w->devinfo->codec->sc; 1863 uint32_t config, pincap; 1864 char *devstr, *connstr; 1865 nid_t cad = w->devinfo->codec->cad; 1866 nid_t nid = w->nid; 1867 1868 config = hdac_widget_pin_getconfig(w); 1869 w->wclass.pin.config = config; 1870 1871 pincap = hdac_widget_pin_getcaps(w); 1872 w->wclass.pin.cap = pincap; 1873 1874 w->wclass.pin.ctrl = hdac_command(sc, 1875 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1876 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1877 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1878 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1879 1880 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1881 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1882 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1883 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1884 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1885 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1886 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1887 w->param.eapdbtl = hdac_command(sc, 1888 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1889 w->param.eapdbtl &= 0x7; 1890 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1891 } else 1892 w->param.eapdbtl = HDAC_INVALID; 1893 1894 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1895 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1896 devstr = "line out"; 1897 break; 1898 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1899 devstr = "speaker"; 1900 break; 1901 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1902 devstr = "headphones out"; 1903 break; 1904 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1905 devstr = "CD"; 1906 break; 1907 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1908 devstr = "SPDIF out"; 1909 break; 1910 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1911 devstr = "digital (other) out"; 1912 break; 1913 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1914 devstr = "modem, line side"; 1915 break; 1916 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1917 devstr = "modem, handset side"; 1918 break; 1919 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1920 devstr = "line in"; 1921 break; 1922 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1923 devstr = "AUX"; 1924 break; 1925 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1926 devstr = "Mic in"; 1927 break; 1928 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1929 devstr = "telephony"; 1930 break; 1931 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1932 devstr = "SPDIF in"; 1933 break; 1934 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1935 devstr = "digital (other) in"; 1936 break; 1937 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1938 devstr = "other"; 1939 break; 1940 default: 1941 devstr = "unknown"; 1942 break; 1943 } 1944 1945 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1946 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1947 connstr = "jack"; 1948 break; 1949 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1950 connstr = "none"; 1951 break; 1952 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1953 connstr = "fixed"; 1954 break; 1955 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1956 connstr = "jack / fixed"; 1957 break; 1958 default: 1959 connstr = "unknown"; 1960 break; 1961 } 1962 1963 strlcat(w->name, ": ", sizeof(w->name)); 1964 strlcat(w->name, devstr, sizeof(w->name)); 1965 strlcat(w->name, " (", sizeof(w->name)); 1966 strlcat(w->name, connstr, sizeof(w->name)); 1967 strlcat(w->name, ")", sizeof(w->name)); 1968} 1969 1970static void 1971hdac_widget_parse(struct hdac_widget *w) 1972{ 1973 struct hdac_softc *sc = w->devinfo->codec->sc; 1974 uint32_t wcap, cap; 1975 char *typestr; 1976 nid_t cad = w->devinfo->codec->cad; 1977 nid_t nid = w->nid; 1978 1979 wcap = hdac_command(sc, 1980 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1981 cad); 1982 w->param.widget_cap = wcap; 1983 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1984 1985 switch (w->type) { 1986 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1987 typestr = "audio output"; 1988 break; 1989 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1990 typestr = "audio input"; 1991 break; 1992 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1993 typestr = "audio mixer"; 1994 break; 1995 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1996 typestr = "audio selector"; 1997 break; 1998 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1999 typestr = "pin"; 2000 break; 2001 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2002 typestr = "power widget"; 2003 break; 2004 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2005 typestr = "volume widget"; 2006 break; 2007 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2008 typestr = "beep widget"; 2009 break; 2010 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2011 typestr = "vendor widget"; 2012 break; 2013 default: 2014 typestr = "unknown type"; 2015 break; 2016 } 2017 2018 strlcpy(w->name, typestr, sizeof(w->name)); 2019 2020 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2021 hdac_command(sc, 2022 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2023 cad); 2024 DELAY(1000); 2025 } 2026 2027 hdac_widget_connection_parse(w); 2028 2029 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2030 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2031 w->param.outamp_cap = 2032 hdac_command(sc, 2033 HDA_CMD_GET_PARAMETER(cad, nid, 2034 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2035 else 2036 w->param.outamp_cap = 2037 w->devinfo->function.audio.outamp_cap; 2038 } else 2039 w->param.outamp_cap = 0; 2040 2041 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2042 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2043 w->param.inamp_cap = 2044 hdac_command(sc, 2045 HDA_CMD_GET_PARAMETER(cad, nid, 2046 HDA_PARAM_INPUT_AMP_CAP), cad); 2047 else 2048 w->param.inamp_cap = 2049 w->devinfo->function.audio.inamp_cap; 2050 } else 2051 w->param.inamp_cap = 0; 2052 2053 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2054 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2055 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2056 cap = hdac_command(sc, 2057 HDA_CMD_GET_PARAMETER(cad, nid, 2058 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2059 w->param.supp_stream_formats = (cap != 0) ? cap : 2060 w->devinfo->function.audio.supp_stream_formats; 2061 cap = hdac_command(sc, 2062 HDA_CMD_GET_PARAMETER(cad, nid, 2063 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2064 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2065 w->devinfo->function.audio.supp_pcm_size_rate; 2066 } else { 2067 w->param.supp_stream_formats = 2068 w->devinfo->function.audio.supp_stream_formats; 2069 w->param.supp_pcm_size_rate = 2070 w->devinfo->function.audio.supp_pcm_size_rate; 2071 } 2072 } else { 2073 w->param.supp_stream_formats = 0; 2074 w->param.supp_pcm_size_rate = 0; 2075 } 2076 2077 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2078 hdac_widget_pin_parse(w); 2079} 2080 2081static struct hdac_widget * 2082hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2083{ 2084 if (devinfo == NULL || devinfo->widget == NULL || 2085 nid < devinfo->startnode || nid >= devinfo->endnode) 2086 return (NULL); 2087 return (&devinfo->widget[nid - devinfo->startnode]); 2088} 2089 2090static __inline int 2091hda_poll_channel(struct hdac_chan *ch) 2092{ 2093 uint32_t sz, delta; 2094 volatile uint32_t ptr; 2095 2096 if (ch->active == 0) 2097 return (0); 2098 2099 sz = ch->blksz * ch->blkcnt; 2100 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2101 ch->ptr = ptr; 2102 ptr %= sz; 2103 ptr &= ~(ch->blksz - 1); 2104 delta = (sz + ptr - ch->prevptr) % sz; 2105 2106 if (delta < ch->blksz) 2107 return (0); 2108 2109 ch->prevptr = ptr; 2110 2111 return (1); 2112} 2113 2114#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2115 2116static void 2117hda_poll_callback(void *arg) 2118{ 2119 struct hdac_softc *sc = arg; 2120 uint32_t trigger = 0; 2121 2122 if (sc == NULL) 2123 return; 2124 2125 hdac_lock(sc); 2126 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2127 hdac_unlock(sc); 2128 return; 2129 } 2130 2131 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2132 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2133 2134 /* XXX */ 2135 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2136 hda_poll_callback, sc); 2137 2138 hdac_unlock(sc); 2139 2140 if (trigger & 1) 2141 chn_intr(sc->play.c); 2142 if (trigger & 2) 2143 chn_intr(sc->rec.c); 2144} 2145 2146static int 2147hdac_rirb_flush(struct hdac_softc *sc) 2148{ 2149 struct hdac_rirb *rirb_base, *rirb; 2150 struct hdac_codec *codec; 2151 struct hdac_command_list *commands; 2152 nid_t cad; 2153 uint32_t resp; 2154 uint8_t rirbwp; 2155 int ret = 0; 2156 2157 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2158 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2159 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2160 BUS_DMASYNC_POSTREAD); 2161 2162 while (sc->rirb_rp != rirbwp) { 2163 sc->rirb_rp++; 2164 sc->rirb_rp %= sc->rirb_size; 2165 rirb = &rirb_base[sc->rirb_rp]; 2166 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2167 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2168 sc->codecs[cad] == NULL) 2169 continue; 2170 resp = rirb->response; 2171 codec = sc->codecs[cad]; 2172 commands = codec->commands; 2173 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2174 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2175 ((resp >> 26) & 0xffff); 2176 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2177 } else if (commands != NULL && commands->num_commands > 0 && 2178 codec->responses_received < commands->num_commands) 2179 commands->responses[codec->responses_received++] = 2180 resp; 2181 ret++; 2182 } 2183 2184 return (ret); 2185} 2186 2187static int 2188hdac_unsolq_flush(struct hdac_softc *sc) 2189{ 2190 nid_t cad; 2191 uint32_t tag; 2192 int ret = 0; 2193 2194 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2195 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2196 while (sc->unsolq_rp != sc->unsolq_wp) { 2197 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2198 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2199 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2200 hdac_unsolicited_handler(sc->codecs[cad], tag); 2201 ret++; 2202 } 2203 sc->unsolq_st = HDAC_UNSOLQ_READY; 2204 } 2205 2206 return (ret); 2207} 2208 2209static void 2210hdac_poll_callback(void *arg) 2211{ 2212 struct hdac_softc *sc = arg; 2213 if (sc == NULL) 2214 return; 2215 2216 hdac_lock(sc); 2217 if (sc->polling == 0) { 2218 hdac_unlock(sc); 2219 return; 2220 } 2221 hdac_rirb_flush(sc); 2222 hdac_unsolq_flush(sc); 2223 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2224 hdac_poll_callback, sc); 2225 hdac_unlock(sc); 2226} 2227 2228static void 2229hdac_stream_stop(struct hdac_chan *ch) 2230{ 2231 struct hdac_softc *sc = ch->devinfo->codec->sc; 2232 uint32_t ctl; 2233 2234 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2235 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2236 HDAC_SDCTL_RUN); 2237 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2238 2239 ch->active = 0; 2240 2241 if (sc->polling != 0) { 2242 int pollticks; 2243 2244 if (hda_chan_active(sc) == 0) { 2245 callout_stop(&sc->poll_hda); 2246 sc->poll_ticks = 1; 2247 } else { 2248 if (sc->play.active != 0) 2249 ch = &sc->play; 2250 else 2251 ch = &sc->rec; 2252 pollticks = ((uint64_t)hz * ch->blksz) / 2253 ((uint64_t)sndbuf_getbps(ch->b) * 2254 sndbuf_getspd(ch->b)); 2255 pollticks >>= 2; 2256 if (pollticks > hz) 2257 pollticks = hz; 2258 if (pollticks < 1) { 2259 HDA_BOOTVERBOSE( 2260 device_printf(sc->dev, 2261 "%s: pollticks=%d < 1 !\n", 2262 __func__, pollticks); 2263 ); 2264 pollticks = 1; 2265 } 2266 if (pollticks > sc->poll_ticks) { 2267 HDA_BOOTVERBOSE( 2268 device_printf(sc->dev, 2269 "%s: pollticks %d -> %d\n", 2270 __func__, sc->poll_ticks, 2271 pollticks); 2272 ); 2273 sc->poll_ticks = pollticks; 2274 callout_reset(&sc->poll_hda, 1, 2275 hda_poll_callback, sc); 2276 } 2277 } 2278 } else { 2279 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2280 ctl &= ~(1 << (ch->off >> 5)); 2281 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2282 } 2283} 2284 2285static void 2286hdac_stream_start(struct hdac_chan *ch) 2287{ 2288 struct hdac_softc *sc = ch->devinfo->codec->sc; 2289 uint32_t ctl; 2290 2291 if (sc->polling != 0) { 2292 int pollticks; 2293 2294 pollticks = ((uint64_t)hz * ch->blksz) / 2295 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2296 pollticks >>= 2; 2297 if (pollticks > hz) 2298 pollticks = hz; 2299 if (pollticks < 1) { 2300 HDA_BOOTVERBOSE( 2301 device_printf(sc->dev, 2302 "%s: pollticks=%d < 1 !\n", 2303 __func__, pollticks); 2304 ); 2305 pollticks = 1; 2306 } 2307 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2308 HDA_BOOTVERBOSE( 2309 if (hda_chan_active(sc) == 0) { 2310 device_printf(sc->dev, 2311 "%s: pollticks=%d\n", 2312 __func__, pollticks); 2313 } else { 2314 device_printf(sc->dev, 2315 "%s: pollticks %d -> %d\n", 2316 __func__, sc->poll_ticks, 2317 pollticks); 2318 } 2319 ); 2320 sc->poll_ticks = pollticks; 2321 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2322 sc); 2323 } 2324 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2325 ctl |= HDAC_SDCTL_RUN; 2326 } else { 2327 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2328 ctl |= 1 << (ch->off >> 5); 2329 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2330 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2331 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2332 HDAC_SDCTL_RUN; 2333 } 2334 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2335 2336 ch->active = 1; 2337} 2338 2339static void 2340hdac_stream_reset(struct hdac_chan *ch) 2341{ 2342 struct hdac_softc *sc = ch->devinfo->codec->sc; 2343 int timeout = 1000; 2344 int to = timeout; 2345 uint32_t ctl; 2346 2347 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2348 ctl |= HDAC_SDCTL_SRST; 2349 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2350 do { 2351 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2352 if (ctl & HDAC_SDCTL_SRST) 2353 break; 2354 DELAY(10); 2355 } while (--to); 2356 if (!(ctl & HDAC_SDCTL_SRST)) { 2357 device_printf(sc->dev, "timeout in reset\n"); 2358 } 2359 ctl &= ~HDAC_SDCTL_SRST; 2360 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2361 to = timeout; 2362 do { 2363 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2364 if (!(ctl & HDAC_SDCTL_SRST)) 2365 break; 2366 DELAY(10); 2367 } while (--to); 2368 if (ctl & HDAC_SDCTL_SRST) 2369 device_printf(sc->dev, "can't reset!\n"); 2370} 2371 2372static void 2373hdac_stream_setid(struct hdac_chan *ch) 2374{ 2375 struct hdac_softc *sc = ch->devinfo->codec->sc; 2376 uint32_t ctl; 2377 2378 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2379 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2380 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2381 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2382} 2383 2384static void 2385hdac_bdl_setup(struct hdac_chan *ch) 2386{ 2387 struct hdac_softc *sc = ch->devinfo->codec->sc; 2388 struct hdac_bdle *bdle; 2389 uint64_t addr; 2390 uint32_t blksz, blkcnt; 2391 int i; 2392 2393 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2394 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2395 2396 if (sc->polling != 0) { 2397 blksz = ch->blksz * ch->blkcnt; 2398 blkcnt = 1; 2399 } else { 2400 blksz = ch->blksz; 2401 blkcnt = ch->blkcnt; 2402 } 2403 2404 for (i = 0; i < blkcnt; i++, bdle++) { 2405 bdle->addrl = (uint32_t)addr; 2406 bdle->addrh = (uint32_t)(addr >> 32); 2407 bdle->len = blksz; 2408 bdle->ioc = 1 ^ sc->polling; 2409 addr += blksz; 2410 } 2411 2412 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2413 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2414 addr = ch->bdl_dma.dma_paddr; 2415 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2416 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2417} 2418 2419static int 2420hdac_bdl_alloc(struct hdac_chan *ch) 2421{ 2422 struct hdac_softc *sc = ch->devinfo->codec->sc; 2423 int rc; 2424 2425 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2426 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2427 if (rc) { 2428 device_printf(sc->dev, "can't alloc bdl\n"); 2429 return (rc); 2430 } 2431 2432 return (0); 2433} 2434 2435static void 2436hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2437 int index, int lmute, int rmute, 2438 int left, int right, int dir) 2439{ 2440 uint16_t v = 0; 2441 2442 if (sc == NULL) 2443 return; 2444 2445 if (left != right || lmute != rmute) { 2446 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2447 (lmute << 7) | left; 2448 hdac_command(sc, 2449 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2450 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2451 (rmute << 7) | right; 2452 } else 2453 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2454 (lmute << 7) | left; 2455 2456 hdac_command(sc, 2457 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2458} 2459 2460static void 2461hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2462 int left, int right) 2463{ 2464 struct hdac_softc *sc; 2465 nid_t nid, cad; 2466 int lmute, rmute; 2467 2468 if (ctl == NULL || ctl->widget == NULL || 2469 ctl->widget->devinfo == NULL || 2470 ctl->widget->devinfo->codec == NULL || 2471 ctl->widget->devinfo->codec->sc == NULL) 2472 return; 2473 2474 sc = ctl->widget->devinfo->codec->sc; 2475 cad = ctl->widget->devinfo->codec->cad; 2476 nid = ctl->widget->nid; 2477 2478 if (mute == HDA_AMP_MUTE_DEFAULT) { 2479 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2480 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2481 } else { 2482 lmute = HDA_AMP_LEFT_MUTED(mute); 2483 rmute = HDA_AMP_RIGHT_MUTED(mute); 2484 } 2485 2486 if (ctl->dir & HDA_CTL_OUT) 2487 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2488 lmute, rmute, left, right, 0); 2489 if (ctl->dir & HDA_CTL_IN) 2490 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2491 lmute, rmute, left, right, 1); 2492 ctl->left = left; 2493 ctl->right = right; 2494} 2495 2496static void 2497hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2498{ 2499 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2500 return; 2501 hdac_command(w->devinfo->codec->sc, 2502 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2503 w->nid, index), w->devinfo->codec->cad); 2504 w->selconn = index; 2505} 2506 2507 2508/**************************************************************************** 2509 * uint32_t hdac_command_sendone_internal 2510 * 2511 * Wrapper function that sends only one command to a given codec 2512 ****************************************************************************/ 2513static uint32_t 2514hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2515{ 2516 struct hdac_command_list cl; 2517 uint32_t response = HDAC_INVALID; 2518 2519 if (!hdac_lockowned(sc)) 2520 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2521 cl.num_commands = 1; 2522 cl.verbs = &verb; 2523 cl.responses = &response; 2524 2525 hdac_command_send_internal(sc, &cl, cad); 2526 2527 return (response); 2528} 2529 2530/**************************************************************************** 2531 * hdac_command_send_internal 2532 * 2533 * Send a command list to the codec via the corb. We queue as much verbs as 2534 * we can and msleep on the codec. When the interrupt get the responses 2535 * back from the rirb, it will wake us up so we can queue the remaining verbs 2536 * if any. 2537 ****************************************************************************/ 2538static void 2539hdac_command_send_internal(struct hdac_softc *sc, 2540 struct hdac_command_list *commands, nid_t cad) 2541{ 2542 struct hdac_codec *codec; 2543 int corbrp; 2544 uint32_t *corb; 2545 int timeout; 2546 int retry = 10; 2547 struct hdac_rirb *rirb_base; 2548 2549 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2550 commands->num_commands < 1) 2551 return; 2552 2553 codec = sc->codecs[cad]; 2554 codec->commands = commands; 2555 codec->responses_received = 0; 2556 codec->verbs_sent = 0; 2557 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2558 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2559 2560 do { 2561 if (codec->verbs_sent != commands->num_commands) { 2562 /* Queue as many verbs as possible */ 2563 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2564 bus_dmamap_sync(sc->corb_dma.dma_tag, 2565 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2566 while (codec->verbs_sent != commands->num_commands && 2567 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2568 sc->corb_wp++; 2569 sc->corb_wp %= sc->corb_size; 2570 corb[sc->corb_wp] = 2571 commands->verbs[codec->verbs_sent++]; 2572 } 2573 2574 /* Send the verbs to the codecs */ 2575 bus_dmamap_sync(sc->corb_dma.dma_tag, 2576 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2577 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2578 } 2579 2580 timeout = 1000; 2581 while (hdac_rirb_flush(sc) == 0 && --timeout) 2582 DELAY(10); 2583 } while ((codec->verbs_sent != commands->num_commands || 2584 codec->responses_received != commands->num_commands) && --retry); 2585 2586 if (retry == 0) 2587 device_printf(sc->dev, 2588 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2589 __func__, commands->num_commands, codec->verbs_sent, 2590 codec->responses_received); 2591 2592 codec->commands = NULL; 2593 codec->responses_received = 0; 2594 codec->verbs_sent = 0; 2595 2596 hdac_unsolq_flush(sc); 2597} 2598 2599 2600/**************************************************************************** 2601 * Device Methods 2602 ****************************************************************************/ 2603 2604/**************************************************************************** 2605 * int hdac_probe(device_t) 2606 * 2607 * Probe for the presence of an hdac. If none is found, check for a generic 2608 * match using the subclass of the device. 2609 ****************************************************************************/ 2610static int 2611hdac_probe(device_t dev) 2612{ 2613 int i, result; 2614 uint32_t model; 2615 uint16_t class, subclass; 2616 char desc[64]; 2617 2618 model = (uint32_t)pci_get_device(dev) << 16; 2619 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2620 class = pci_get_class(dev); 2621 subclass = pci_get_subclass(dev); 2622 2623 bzero(desc, sizeof(desc)); 2624 result = ENXIO; 2625 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2626 if (hdac_devices[i].model == model) { 2627 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2628 result = BUS_PROBE_DEFAULT; 2629 break; 2630 } 2631 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2632 class == PCIC_MULTIMEDIA && 2633 subclass == PCIS_MULTIMEDIA_HDA) { 2634 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2635 result = BUS_PROBE_GENERIC; 2636 break; 2637 } 2638 } 2639 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2640 subclass == PCIS_MULTIMEDIA_HDA) { 2641 strlcpy(desc, "Generic", sizeof(desc)); 2642 result = BUS_PROBE_GENERIC; 2643 } 2644 if (result != ENXIO) { 2645 strlcat(desc, " High Definition Audio Controller", 2646 sizeof(desc)); 2647 device_set_desc_copy(dev, desc); 2648 } 2649 2650 return (result); 2651} 2652 2653static int 2654hdac_channel_free(kobj_t obj, void *data) 2655{ 2656 struct hdac_chan *ch = data; 2657 2658 hdac_dma_attr((vm_offset_t)ch->b->buf, sndbuf_getmaxsize(ch->b), 2659 HDAC_DMA_WRITEBACK); 2660 2661 return (1); 2662} 2663 2664static void * 2665hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2666 struct pcm_channel *c, int dir) 2667{ 2668 struct hdac_devinfo *devinfo = data; 2669 struct hdac_softc *sc = devinfo->codec->sc; 2670 struct hdac_chan *ch; 2671 2672 hdac_lock(sc); 2673 if (dir == PCMDIR_PLAY) { 2674 ch = &sc->play; 2675 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2676 ch->dir = PCMDIR_PLAY; 2677 ch->sid = ++sc->streamcnt; 2678 devinfo->function.audio.playcnt++; 2679 } else { 2680 ch = &sc->rec; 2681 ch->off = devinfo->function.audio.reccnt << 5; 2682 ch->dir = PCMDIR_REC; 2683 ch->sid = ++sc->streamcnt; 2684 devinfo->function.audio.reccnt++; 2685 } 2686 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2687 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2688 ch->pcmrates[0] = 48000; 2689 ch->pcmrates[1] = 0; 2690 } 2691 ch->b = b; 2692 ch->c = c; 2693 ch->devinfo = devinfo; 2694 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2695 ch->blkcnt = sc->chan_blkcnt; 2696 hdac_unlock(sc); 2697 2698 if (hdac_bdl_alloc(ch) != 0) { 2699 ch->blkcnt = 0; 2700 return (NULL); 2701 } 2702 2703 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2704 return (NULL); 2705 2706 hdac_dma_attr((vm_offset_t)ch->b->buf, sndbuf_getmaxsize(ch->b), 2707 HDAC_DMA_UNCACHEABLE); 2708 2709 return (ch); 2710} 2711 2712static int 2713hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2714{ 2715 struct hdac_chan *ch = data; 2716 int i; 2717 2718 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2719 if (format == ch->caps.fmtlist[i]) { 2720 ch->fmt = format; 2721 return (0); 2722 } 2723 } 2724 2725 return (EINVAL); 2726} 2727 2728static int 2729hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2730{ 2731 struct hdac_chan *ch = data; 2732 uint32_t spd = 0, threshold; 2733 int i; 2734 2735 for (i = 0; ch->pcmrates[i] != 0; i++) { 2736 spd = ch->pcmrates[i]; 2737 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2738 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2739 if (speed < threshold) 2740 break; 2741 } 2742 2743 if (spd == 0) /* impossible */ 2744 ch->spd = 48000; 2745 else 2746 ch->spd = spd; 2747 2748 return (ch->spd); 2749} 2750 2751static void 2752hdac_stream_setup(struct hdac_chan *ch) 2753{ 2754 struct hdac_softc *sc = ch->devinfo->codec->sc; 2755 int i; 2756 nid_t cad = ch->devinfo->codec->cad; 2757 uint16_t fmt; 2758 2759 fmt = 0; 2760 if (ch->fmt & AFMT_S16_LE) 2761 fmt |= ch->bit16 << 4; 2762 else if (ch->fmt & AFMT_S32_LE) 2763 fmt |= ch->bit32 << 4; 2764 else 2765 fmt |= 1 << 4; 2766 2767 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2768 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2769 fmt |= hda_rate_tab[i].base; 2770 fmt |= hda_rate_tab[i].mul; 2771 fmt |= hda_rate_tab[i].div; 2772 break; 2773 } 2774 } 2775 2776 if (ch->fmt & AFMT_STEREO) 2777 fmt |= 1; 2778 2779 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2780 2781 for (i = 0; ch->io[i] != -1; i++) { 2782 HDA_BOOTVERBOSE( 2783 device_printf(sc->dev, 2784 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2785 "fmt=0x%08x\n", 2786 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2787 ch->io[i], fmt); 2788 ); 2789 hdac_command(sc, 2790 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2791 hdac_command(sc, 2792 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2793 ch->sid << 4), cad); 2794 } 2795} 2796 2797static int 2798hdac_channel_setfragments(kobj_t obj, void *data, 2799 uint32_t blksz, uint32_t blkcnt) 2800{ 2801 struct hdac_chan *ch = data; 2802 struct hdac_softc *sc = ch->devinfo->codec->sc; 2803 2804 blksz &= HDA_BLK_ALIGN; 2805 2806 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 2807 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 2808 if (blksz < HDA_BLK_MIN) 2809 blksz = HDA_BLK_MIN; 2810 if (blkcnt > HDA_BDL_MAX) 2811 blkcnt = HDA_BDL_MAX; 2812 if (blkcnt < HDA_BDL_MIN) 2813 blkcnt = HDA_BDL_MIN; 2814 2815 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 2816 if ((blkcnt >> 1) >= HDA_BDL_MIN) 2817 blkcnt >>= 1; 2818 else if ((blksz >> 1) >= HDA_BLK_MIN) 2819 blksz >>= 1; 2820 else 2821 break; 2822 } 2823 2824 if ((sndbuf_getblksz(ch->b) != blksz || 2825 sndbuf_getblkcnt(ch->b) != blkcnt) && 2826 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 2827 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2828 __func__, blksz, blkcnt); 2829 2830 ch->blksz = sndbuf_getblksz(ch->b); 2831 ch->blkcnt = sndbuf_getblkcnt(ch->b); 2832 2833 return (1); 2834} 2835 2836static int 2837hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2838{ 2839 struct hdac_chan *ch = data; 2840 struct hdac_softc *sc = ch->devinfo->codec->sc; 2841 2842 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 2843 2844 return (ch->blksz); 2845} 2846 2847static void 2848hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2849{ 2850 struct hdac_devinfo *devinfo = ch->devinfo; 2851 nid_t cad = devinfo->codec->cad; 2852 int i; 2853 2854 hdac_stream_stop(ch); 2855 2856 for (i = 0; ch->io[i] != -1; i++) { 2857 hdac_command(sc, 2858 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2859 0), cad); 2860 } 2861} 2862 2863static void 2864hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2865{ 2866 ch->ptr = 0; 2867 ch->prevptr = 0; 2868 hdac_stream_stop(ch); 2869 hdac_stream_reset(ch); 2870 hdac_bdl_setup(ch); 2871 hdac_stream_setid(ch); 2872 hdac_stream_setup(ch); 2873 hdac_stream_start(ch); 2874} 2875 2876static int 2877hdac_channel_trigger(kobj_t obj, void *data, int go) 2878{ 2879 struct hdac_chan *ch = data; 2880 struct hdac_softc *sc = ch->devinfo->codec->sc; 2881 2882 hdac_lock(sc); 2883 switch (go) { 2884 case PCMTRIG_START: 2885 hdac_channel_start(sc, ch); 2886 break; 2887 case PCMTRIG_STOP: 2888 case PCMTRIG_ABORT: 2889 hdac_channel_stop(sc, ch); 2890 break; 2891 default: 2892 break; 2893 } 2894 hdac_unlock(sc); 2895 2896 return (0); 2897} 2898 2899static int 2900hdac_channel_getptr(kobj_t obj, void *data) 2901{ 2902 struct hdac_chan *ch = data; 2903 struct hdac_softc *sc = ch->devinfo->codec->sc; 2904 uint32_t ptr; 2905 2906 hdac_lock(sc); 2907 if (sc->polling != 0) 2908 ptr = ch->ptr; 2909 else 2910 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2911 hdac_unlock(sc); 2912 2913 /* 2914 * Round to available space and force 128 bytes aligment. 2915 */ 2916 ptr %= ch->blksz * ch->blkcnt; 2917 ptr &= HDA_BLK_ALIGN; 2918 2919 return (ptr); 2920} 2921 2922static struct pcmchan_caps * 2923hdac_channel_getcaps(kobj_t obj, void *data) 2924{ 2925 return (&((struct hdac_chan *)data)->caps); 2926} 2927 2928static kobj_method_t hdac_channel_methods[] = { 2929 KOBJMETHOD(channel_init, hdac_channel_init), 2930 KOBJMETHOD(channel_free, hdac_channel_free), 2931 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2932 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2933 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2934 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 2935 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2936 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2937 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2938 { 0, 0 } 2939}; 2940CHANNEL_DECLARE(hdac_channel); 2941 2942static int 2943hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2944{ 2945 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2946 struct hdac_softc *sc = devinfo->codec->sc; 2947 struct hdac_widget *w, *cw; 2948 struct hdac_audio_ctl *ctl; 2949 uint32_t mask, recmask, id; 2950 int i, j, softpcmvol; 2951 nid_t cad; 2952 2953 hdac_lock(sc); 2954 2955 mask = 0; 2956 recmask = 0; 2957 2958 id = hdac_codec_id(devinfo); 2959 cad = devinfo->codec->cad; 2960 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2961 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2962 sc->pci_subvendor) && 2963 hdac_hp_switch[i].id == id)) 2964 continue; 2965 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2966 if (w != NULL && w->enable != 0 2967 && w->type == 2968 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2969 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2970 hdac_command(sc, 2971 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2972 w->nid, 2973 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2974 HDAC_UNSOLTAG_EVENT_HP), cad); 2975 hdac_hp_switch_handler(devinfo); 2976 HDA_BOOTVERBOSE( 2977 device_printf(sc->dev, 2978 "HDA_DEBUG: Enabling headphone/speaker " 2979 "audio routing switching:\n"); 2980 device_printf(sc->dev, 2981 "HDA_DEBUG: \tindex=%d nid=%d " 2982 "pci_subvendor=0x%08x " 2983 "codec=0x%08x\n", 2984 i, w->nid, sc->pci_subvendor, id); 2985 ); 2986 } 2987 break; 2988 } 2989 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2990 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2991 sc->pci_subvendor) && 2992 hdac_eapd_switch[i].id == id)) 2993 continue; 2994 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2995 if (w == NULL || w->enable == 0) 2996 break; 2997 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2998 w->param.eapdbtl == HDAC_INVALID) 2999 break; 3000 mask |= SOUND_MASK_OGAIN; 3001 break; 3002 } 3003 3004 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3005 w = hdac_widget_get(devinfo, i); 3006 if (w == NULL || w->enable == 0) 3007 continue; 3008 mask |= w->ctlflags; 3009 if (!(w->pflags & HDA_ADC_RECSEL)) 3010 continue; 3011 for (j = 0; j < w->nconns; j++) { 3012 cw = hdac_widget_get(devinfo, w->conns[j]); 3013 if (cw == NULL || cw->enable == 0) 3014 continue; 3015 recmask |= cw->ctlflags; 3016 } 3017 } 3018 3019 if (!(mask & SOUND_MASK_PCM)) { 3020 softpcmvol = 1; 3021 mask |= SOUND_MASK_PCM; 3022 } else 3023 softpcmvol = (devinfo->function.audio.quirks & 3024 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 3025 3026 i = 0; 3027 ctl = NULL; 3028 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3029 if (ctl->widget == NULL || ctl->enable == 0) 3030 continue; 3031 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3032 continue; 3033 if (ctl->step > 0) 3034 break; 3035 } 3036 3037 if (softpcmvol == 1 || ctl == NULL) { 3038 struct snddev_info *d = NULL; 3039 d = device_get_softc(sc->dev); 3040 if (d != NULL) { 3041 d->flags |= SD_F_SOFTPCMVOL; 3042 HDA_BOOTVERBOSE( 3043 device_printf(sc->dev, 3044 "HDA_DEBUG: %s Soft PCM volume\n", 3045 (softpcmvol == 1) ? 3046 "Forcing" : "Enabling"); 3047 ); 3048 } 3049 i = 0; 3050 /* 3051 * XXX Temporary quirk for STAC9220, until the parser 3052 * become smarter. 3053 */ 3054 if (id == HDA_CODEC_STAC9220) { 3055 mask |= SOUND_MASK_VOLUME; 3056 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3057 NULL) { 3058 if (ctl->widget == NULL || ctl->enable == 0) 3059 continue; 3060 if (ctl->widget->nid == 11 && ctl->index == 0) { 3061 ctl->ossmask = SOUND_MASK_VOLUME; 3062 ctl->ossval = 100 | (100 << 8); 3063 } else 3064 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3065 } 3066 } else if (id == HDA_CODEC_STAC9221) { 3067 mask |= SOUND_MASK_VOLUME; 3068 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3069 NULL) { 3070 if (ctl->widget == NULL) 3071 continue; 3072 if (ctl->widget->nid == 2 && ctl->index == 0) { 3073 ctl->enable = 1; 3074 ctl->ossmask = SOUND_MASK_VOLUME; 3075 ctl->ossval = 100 | (100 << 8); 3076 } else if (ctl->enable == 0) 3077 continue; 3078 else 3079 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3080 } 3081 } else { 3082 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3083 SOUND_MASK_PCM); 3084 if (!(mask & SOUND_MASK_VOLUME)) 3085 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3086 SOUND_MIXER_NONE); 3087 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3088 NULL) { 3089 if (ctl->widget == NULL || ctl->enable == 0) 3090 continue; 3091 if (!HDA_FLAG_MATCH(ctl->ossmask, 3092 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3093 continue; 3094 if (!(ctl->mute == 1 && ctl->step == 0)) 3095 ctl->enable = 0; 3096 } 3097 } 3098 } 3099 3100 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 3101 3102 mix_setrecdevs(m, recmask); 3103 mix_setdevs(m, mask); 3104 3105 hdac_unlock(sc); 3106 3107 return (0); 3108} 3109 3110static int 3111hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3112 unsigned left, unsigned right) 3113{ 3114 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3115 struct hdac_softc *sc = devinfo->codec->sc; 3116 struct hdac_widget *w; 3117 struct hdac_audio_ctl *ctl; 3118 uint32_t id, mute; 3119 int lvol, rvol, mlvol, mrvol; 3120 int i = 0; 3121 3122 hdac_lock(sc); 3123 if (dev == SOUND_MIXER_OGAIN) { 3124 uint32_t orig; 3125 /*if (left != right || !(left == 0 || left == 1)) { 3126 hdac_unlock(sc); 3127 return (-1); 3128 }*/ 3129 id = hdac_codec_id(devinfo); 3130 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3131 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3132 sc->pci_subvendor) && 3133 hdac_eapd_switch[i].id == id) 3134 break; 3135 } 3136 if (i >= HDAC_EAPD_SWITCH_LEN) { 3137 hdac_unlock(sc); 3138 return (-1); 3139 } 3140 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3141 if (w == NULL || 3142 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3143 w->param.eapdbtl == HDAC_INVALID) { 3144 hdac_unlock(sc); 3145 return (-1); 3146 } 3147 orig = w->param.eapdbtl; 3148 if (left == 0) 3149 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3150 else 3151 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3152 if (orig != w->param.eapdbtl) { 3153 uint32_t val; 3154 3155 if (hdac_eapd_switch[i].hp_switch != 0) 3156 hdac_hp_switch_handler(devinfo); 3157 val = w->param.eapdbtl; 3158 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3159 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3160 hdac_command(sc, 3161 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3162 w->nid, val), devinfo->codec->cad); 3163 } 3164 hdac_unlock(sc); 3165 return (left | (left << 8)); 3166 } 3167 if (dev == SOUND_MIXER_VOLUME) 3168 devinfo->function.audio.mvol = left | (right << 8); 3169 3170 mlvol = devinfo->function.audio.mvol & 0x7f; 3171 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3172 lvol = 0; 3173 rvol = 0; 3174 3175 i = 0; 3176 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3177 if (ctl->widget == NULL || ctl->enable == 0 || 3178 !(ctl->ossmask & (1 << dev))) 3179 continue; 3180 switch (dev) { 3181 case SOUND_MIXER_VOLUME: 3182 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3183 lvol = (lvol * ctl->step) / 100; 3184 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3185 rvol = (rvol * ctl->step) / 100; 3186 break; 3187 default: 3188 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3189 lvol = (left * mlvol) / 100; 3190 lvol = (lvol * ctl->step) / 100; 3191 rvol = (right * mrvol) / 100; 3192 rvol = (rvol * ctl->step) / 100; 3193 } else { 3194 lvol = (left * ctl->step) / 100; 3195 rvol = (right * ctl->step) / 100; 3196 } 3197 ctl->ossval = left | (right << 8); 3198 break; 3199 } 3200 mute = 0; 3201 if (ctl->step < 1) { 3202 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3203 (ctl->muted & HDA_AMP_MUTE_LEFT); 3204 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3205 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3206 } else { 3207 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3208 (ctl->muted & HDA_AMP_MUTE_LEFT); 3209 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3210 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3211 } 3212 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3213 } 3214 hdac_unlock(sc); 3215 3216 return (left | (right << 8)); 3217} 3218 3219static int 3220hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3221{ 3222 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3223 struct hdac_widget *w, *cw; 3224 struct hdac_softc *sc = devinfo->codec->sc; 3225 uint32_t ret = src, target; 3226 int i, j; 3227 3228 target = 0; 3229 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3230 if (src & (1 << i)) { 3231 target = 1 << i; 3232 break; 3233 } 3234 } 3235 3236 hdac_lock(sc); 3237 3238 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3239 w = hdac_widget_get(devinfo, i); 3240 if (w == NULL || w->enable == 0) 3241 continue; 3242 if (!(w->pflags & HDA_ADC_RECSEL)) 3243 continue; 3244 for (j = 0; j < w->nconns; j++) { 3245 cw = hdac_widget_get(devinfo, w->conns[j]); 3246 if (cw == NULL || cw->enable == 0) 3247 continue; 3248 if ((target == SOUND_MASK_VOLUME && 3249 cw->type != 3250 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3251 (target != SOUND_MASK_VOLUME && 3252 cw->type == 3253 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3254 continue; 3255 if (cw->ctlflags & target) { 3256 hdac_widget_connection_select(w, j); 3257 ret = target; 3258 j += w->nconns; 3259 } 3260 } 3261 } 3262 3263 hdac_unlock(sc); 3264 3265 return (ret); 3266} 3267 3268static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3269 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3270 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3271 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3272 { 0, 0 } 3273}; 3274MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3275 3276/**************************************************************************** 3277 * int hdac_attach(device_t) 3278 * 3279 * Attach the device into the kernel. Interrupts usually won't be enabled 3280 * when this function is called. Setup everything that doesn't require 3281 * interrupts and defer probing of codecs until interrupts are enabled. 3282 ****************************************************************************/ 3283static int 3284hdac_attach(device_t dev) 3285{ 3286 struct hdac_softc *sc; 3287 int result; 3288 int i = 0; 3289 3290 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3291 if (sc == NULL) { 3292 device_printf(dev, "cannot allocate softc\n"); 3293 return (ENOMEM); 3294 } 3295 3296 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3297 sc->dev = dev; 3298 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3299 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3300 3301 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3302 /* Screw nx6325 - subdevice/subvendor swapped */ 3303 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3304 } 3305 3306 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3307 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3308 3309 sc->poll_ticks = 1; 3310 if (resource_int_value(device_get_name(sc->dev), 3311 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3312 sc->polling = 1; 3313 else 3314 sc->polling = 0; 3315 3316 sc->chan_size = pcm_getbuffersize(dev, 3317 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3318 3319 if (resource_int_value(device_get_name(sc->dev), 3320 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3321 i &= HDA_BLK_ALIGN; 3322 if (i < HDA_BLK_MIN) 3323 i = HDA_BLK_MIN; 3324 sc->chan_blkcnt = sc->chan_size / i; 3325 i = 0; 3326 while (sc->chan_blkcnt >> i) 3327 i++; 3328 sc->chan_blkcnt = 1 << (i - 1); 3329 if (sc->chan_blkcnt < HDA_BDL_MIN) 3330 sc->chan_blkcnt = HDA_BDL_MIN; 3331 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3332 sc->chan_blkcnt = HDA_BDL_MAX; 3333 } else 3334 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3335 3336 result = bus_dma_tag_create(NULL, /* parent */ 3337 HDAC_DMA_ALIGNMENT, /* alignment */ 3338 0, /* boundary */ 3339 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3340 BUS_SPACE_MAXADDR, /* highaddr */ 3341 NULL, /* filtfunc */ 3342 NULL, /* fistfuncarg */ 3343 sc->chan_size, /* maxsize */ 3344 1, /* nsegments */ 3345 sc->chan_size, /* maxsegsz */ 3346 0, /* flags */ 3347 NULL, /* lockfunc */ 3348 NULL, /* lockfuncarg */ 3349 &sc->chan_dmat); /* dmat */ 3350 if (result != 0) { 3351 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3352 __func__, result); 3353 snd_mtxfree(sc->lock); 3354 free(sc, M_DEVBUF); 3355 return (ENXIO); 3356 } 3357 3358 3359 sc->hdabus = NULL; 3360 for (i = 0; i < HDAC_CODEC_MAX; i++) 3361 sc->codecs[i] = NULL; 3362 3363 pci_enable_busmaster(dev); 3364 3365 /* Allocate resources */ 3366 result = hdac_mem_alloc(sc); 3367 if (result != 0) 3368 goto hdac_attach_fail; 3369 result = hdac_irq_alloc(sc); 3370 if (result != 0) 3371 goto hdac_attach_fail; 3372 3373 /* Get Capabilities */ 3374 result = hdac_get_capabilities(sc); 3375 if (result != 0) 3376 goto hdac_attach_fail; 3377 3378 /* Allocate CORB and RIRB dma memory */ 3379 result = hdac_dma_alloc(sc, &sc->corb_dma, 3380 sc->corb_size * sizeof(uint32_t)); 3381 if (result != 0) 3382 goto hdac_attach_fail; 3383 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3384 sc->rirb_size * sizeof(struct hdac_rirb)); 3385 if (result != 0) 3386 goto hdac_attach_fail; 3387 3388 /* Quiesce everything */ 3389 hdac_reset(sc); 3390 3391 /* Disable PCI-Express QOS */ 3392 pci_write_config(sc->dev, 0x44, 3393 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3394 3395 /* Initialize the CORB and RIRB */ 3396 hdac_corb_init(sc); 3397 hdac_rirb_init(sc); 3398 3399 /* Defer remaining of initialization until interrupts are enabled */ 3400 sc->intrhook.ich_func = hdac_attach2; 3401 sc->intrhook.ich_arg = (void *)sc; 3402 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3403 sc->intrhook.ich_func = NULL; 3404 hdac_attach2((void *)sc); 3405 } 3406 3407 return (0); 3408 3409hdac_attach_fail: 3410 hdac_dma_free(&sc->rirb_dma); 3411 hdac_dma_free(&sc->corb_dma); 3412 hdac_irq_free(sc); 3413 hdac_mem_free(sc); 3414 snd_mtxfree(sc->lock); 3415 free(sc, M_DEVBUF); 3416 3417 return (ENXIO); 3418} 3419 3420static void 3421hdac_audio_parse(struct hdac_devinfo *devinfo) 3422{ 3423 struct hdac_softc *sc = devinfo->codec->sc; 3424 struct hdac_widget *w; 3425 uint32_t res; 3426 int i; 3427 nid_t cad, nid; 3428 3429 cad = devinfo->codec->cad; 3430 nid = devinfo->nid; 3431 3432 hdac_command(sc, 3433 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3434 3435 DELAY(100); 3436 3437 res = hdac_command(sc, 3438 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3439 3440 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3441 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3442 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3443 3444 HDA_BOOTVERBOSE( 3445 device_printf(sc->dev, " Vendor: 0x%08x\n", 3446 devinfo->vendor_id); 3447 device_printf(sc->dev, " Device: 0x%08x\n", 3448 devinfo->device_id); 3449 device_printf(sc->dev, " Revision: 0x%08x\n", 3450 devinfo->revision_id); 3451 device_printf(sc->dev, " Stepping: 0x%08x\n", 3452 devinfo->stepping_id); 3453 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3454 sc->pci_subvendor); 3455 device_printf(sc->dev, " Nodes: start=%d " 3456 "endnode=%d total=%d\n", 3457 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3458 ); 3459 3460 res = hdac_command(sc, 3461 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3462 cad); 3463 devinfo->function.audio.supp_stream_formats = res; 3464 3465 res = hdac_command(sc, 3466 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3467 cad); 3468 devinfo->function.audio.supp_pcm_size_rate = res; 3469 3470 res = hdac_command(sc, 3471 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3472 cad); 3473 devinfo->function.audio.outamp_cap = res; 3474 3475 res = hdac_command(sc, 3476 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3477 cad); 3478 devinfo->function.audio.inamp_cap = res; 3479 3480 if (devinfo->nodecnt > 0) { 3481 hdac_unlock(sc); 3482 devinfo->widget = (struct hdac_widget *)malloc( 3483 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3484 M_NOWAIT | M_ZERO); 3485 hdac_lock(sc); 3486 } else 3487 devinfo->widget = NULL; 3488 3489 if (devinfo->widget == NULL) { 3490 device_printf(sc->dev, "unable to allocate widgets!\n"); 3491 devinfo->endnode = devinfo->startnode; 3492 devinfo->nodecnt = 0; 3493 return; 3494 } 3495 3496 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3497 w = hdac_widget_get(devinfo, i); 3498 if (w == NULL) 3499 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3500 else { 3501 w->devinfo = devinfo; 3502 w->nid = i; 3503 w->enable = 1; 3504 w->selconn = -1; 3505 w->pflags = 0; 3506 w->ctlflags = 0; 3507 w->param.eapdbtl = HDAC_INVALID; 3508 hdac_widget_parse(w); 3509 } 3510 } 3511} 3512 3513static void 3514hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3515{ 3516 struct hdac_softc *sc = devinfo->codec->sc; 3517 struct hdac_audio_ctl *ctls; 3518 struct hdac_widget *w, *cw; 3519 int i, j, cnt, max, ocap, icap; 3520 int mute, offset, step, size; 3521 3522 /* XXX This is redundant */ 3523 max = 0; 3524 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3525 w = hdac_widget_get(devinfo, i); 3526 if (w == NULL || w->enable == 0) 3527 continue; 3528 if (w->param.outamp_cap != 0) 3529 max++; 3530 if (w->param.inamp_cap != 0) { 3531 switch (w->type) { 3532 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3533 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3534 for (j = 0; j < w->nconns; j++) { 3535 cw = hdac_widget_get(devinfo, 3536 w->conns[j]); 3537 if (cw == NULL || cw->enable == 0) 3538 continue; 3539 max++; 3540 } 3541 break; 3542 default: 3543 max++; 3544 break; 3545 } 3546 } 3547 } 3548 3549 devinfo->function.audio.ctlcnt = max; 3550 3551 if (max < 1) 3552 return; 3553 3554 hdac_unlock(sc); 3555 ctls = (struct hdac_audio_ctl *)malloc( 3556 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3557 hdac_lock(sc); 3558 3559 if (ctls == NULL) { 3560 /* Blekh! */ 3561 device_printf(sc->dev, "unable to allocate ctls!\n"); 3562 devinfo->function.audio.ctlcnt = 0; 3563 return; 3564 } 3565 3566 cnt = 0; 3567 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3568 if (cnt >= max) { 3569 device_printf(sc->dev, "%s: Ctl overflow!\n", 3570 __func__); 3571 break; 3572 } 3573 w = hdac_widget_get(devinfo, i); 3574 if (w == NULL || w->enable == 0) 3575 continue; 3576 ocap = w->param.outamp_cap; 3577 icap = w->param.inamp_cap; 3578 if (ocap != 0) { 3579 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3580 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3581 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3582 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3583 /*if (offset > step) { 3584 HDA_BOOTVERBOSE( 3585 device_printf(sc->dev, 3586 "HDA_DEBUG: BUGGY outamp: nid=%d " 3587 "[offset=%d > step=%d]\n", 3588 w->nid, offset, step); 3589 ); 3590 offset = step; 3591 }*/ 3592 ctls[cnt].enable = 1; 3593 ctls[cnt].widget = w; 3594 ctls[cnt].mute = mute; 3595 ctls[cnt].step = step; 3596 ctls[cnt].size = size; 3597 ctls[cnt].offset = offset; 3598 ctls[cnt].left = offset; 3599 ctls[cnt].right = offset; 3600 ctls[cnt++].dir = HDA_CTL_OUT; 3601 } 3602 3603 if (icap != 0) { 3604 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3605 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3606 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3607 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3608 /*if (offset > step) { 3609 HDA_BOOTVERBOSE( 3610 device_printf(sc->dev, 3611 "HDA_DEBUG: BUGGY inamp: nid=%d " 3612 "[offset=%d > step=%d]\n", 3613 w->nid, offset, step); 3614 ); 3615 offset = step; 3616 }*/ 3617 switch (w->type) { 3618 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3619 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3620 for (j = 0; j < w->nconns; j++) { 3621 if (cnt >= max) { 3622 device_printf(sc->dev, 3623 "%s: Ctl overflow!\n", 3624 __func__); 3625 break; 3626 } 3627 cw = hdac_widget_get(devinfo, 3628 w->conns[j]); 3629 if (cw == NULL || cw->enable == 0) 3630 continue; 3631 ctls[cnt].enable = 1; 3632 ctls[cnt].widget = w; 3633 ctls[cnt].childwidget = cw; 3634 ctls[cnt].index = j; 3635 ctls[cnt].mute = mute; 3636 ctls[cnt].step = step; 3637 ctls[cnt].size = size; 3638 ctls[cnt].offset = offset; 3639 ctls[cnt].left = offset; 3640 ctls[cnt].right = offset; 3641 ctls[cnt++].dir = HDA_CTL_IN; 3642 } 3643 break; 3644 default: 3645 if (cnt >= max) { 3646 device_printf(sc->dev, 3647 "%s: Ctl overflow!\n", 3648 __func__); 3649 break; 3650 } 3651 ctls[cnt].enable = 1; 3652 ctls[cnt].widget = w; 3653 ctls[cnt].mute = mute; 3654 ctls[cnt].step = step; 3655 ctls[cnt].size = size; 3656 ctls[cnt].offset = offset; 3657 ctls[cnt].left = offset; 3658 ctls[cnt].right = offset; 3659 ctls[cnt++].dir = HDA_CTL_IN; 3660 break; 3661 } 3662 } 3663 } 3664 3665 devinfo->function.audio.ctl = ctls; 3666} 3667 3668static const struct { 3669 uint32_t model; 3670 uint32_t id; 3671 uint32_t set, unset; 3672} hdac_quirks[] = { 3673 /* 3674 * XXX Force stereo quirk. Monoural recording / playback 3675 * on few codecs (especially ALC880) seems broken or 3676 * perhaps unsupported. 3677 */ 3678 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3679 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3680 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3681 HDA_QUIRK_GPIO0, 0 }, 3682 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3683 HDA_QUIRK_GPIO0, 0 }, 3684 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3685 HDA_QUIRK_GPIO0, 0 }, 3686 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 3687 HDA_QUIRK_GPIO0, 0 }, 3688 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3689 HDA_QUIRK_EAPDINV, 0 }, 3690 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3691 HDA_QUIRK_EAPDINV, 0 }, 3692 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3693 HDA_QUIRK_GPIO1, 0 }, 3694 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3695 HDA_QUIRK_EAPDINV, 0 }, 3696 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3697 HDA_QUIRK_EAPDINV, 0 }, 3698 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3699 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3700 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3701 0, HDA_QUIRK_FORCESTEREO }, 3702 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3703 HDA_QUIRK_SOFTPCMVOL, 0 } 3704}; 3705#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3706 3707static void 3708hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3709{ 3710 struct hdac_widget *w; 3711 struct hdac_audio_ctl *ctl; 3712 uint32_t id, subvendor; 3713 int i; 3714 3715 id = hdac_codec_id(devinfo); 3716 subvendor = devinfo->codec->sc->pci_subvendor; 3717 3718 /* 3719 * Quirks 3720 */ 3721 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3722 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3723 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3724 continue; 3725 if (hdac_quirks[i].set != 0) 3726 devinfo->function.audio.quirks |= 3727 hdac_quirks[i].set; 3728 if (hdac_quirks[i].unset != 0) 3729 devinfo->function.audio.quirks &= 3730 ~(hdac_quirks[i].unset); 3731 } 3732 3733 switch (id) { 3734 case HDA_CODEC_ALC260: 3735 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3736 w = hdac_widget_get(devinfo, i); 3737 if (w == NULL || w->enable == 0) 3738 continue; 3739 if (w->type != 3740 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3741 continue; 3742 if (w->nid != 5) 3743 w->enable = 0; 3744 } 3745 if (subvendor == HP_XW4300_SUBVENDOR) { 3746 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3747 if (ctl != NULL && ctl->widget != NULL) { 3748 ctl->ossmask = SOUND_MASK_SPEAKER; 3749 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3750 } 3751 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3752 if (ctl != NULL && ctl->widget != NULL) { 3753 ctl->ossmask = SOUND_MASK_SPEAKER; 3754 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3755 } 3756 } 3757 break; 3758 case HDA_CODEC_ALC861: 3759 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3760 if (ctl != NULL) 3761 ctl->muted = HDA_AMP_MUTE_ALL; 3762 break; 3763 case HDA_CODEC_ALC880: 3764 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3765 w = hdac_widget_get(devinfo, i); 3766 if (w == NULL || w->enable == 0) 3767 continue; 3768 if (w->type == 3769 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3770 w->nid != 9 && w->nid != 29) { 3771 w->enable = 0; 3772 } else if (w->type != 3773 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3774 w->nid == 29) { 3775 w->type = 3776 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3777 w->param.widget_cap &= 3778 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3779 w->param.widget_cap |= 3780 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3781 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3782 strlcpy(w->name, "beep widget", sizeof(w->name)); 3783 } 3784 } 3785 break; 3786 case HDA_CODEC_ALC883: 3787 /* 3788 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 3789 * Clear vref cap for jack connectivity. 3790 */ 3791 w = hdac_widget_get(devinfo, 24); 3792 if (w != NULL && w->enable != 0 && w->type == 3793 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3794 (w->wclass.pin.config & 3795 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3796 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3797 w->wclass.pin.cap &= ~( 3798 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3799 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3800 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3801 w = hdac_widget_get(devinfo, 25); 3802 if (w != NULL && w->enable != 0 && w->type == 3803 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3804 (w->wclass.pin.config & 3805 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3806 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3807 w->wclass.pin.cap &= ~( 3808 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3809 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3810 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3811 /* 3812 * nid: 26 = Line-in, leave it alone. 3813 */ 3814 break; 3815 case HDA_CODEC_AD1981HD: 3816 w = hdac_widget_get(devinfo, 11); 3817 if (w != NULL && w->enable != 0 && w->nconns > 3) 3818 w->selconn = 3; 3819 if (subvendor == IBM_M52_SUBVENDOR) { 3820 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3821 if (ctl != NULL) 3822 ctl->ossmask = SOUND_MASK_SPEAKER; 3823 } 3824 break; 3825 case HDA_CODEC_AD1986A: 3826 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3827 w = hdac_widget_get(devinfo, i); 3828 if (w == NULL || w->enable == 0) 3829 continue; 3830 if (w->type != 3831 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3832 continue; 3833 if (w->nid != 3) 3834 w->enable = 0; 3835 } 3836 break; 3837 case HDA_CODEC_STAC9221: 3838 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3839 w = hdac_widget_get(devinfo, i); 3840 if (w == NULL || w->enable == 0) 3841 continue; 3842 if (w->type != 3843 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3844 continue; 3845 if (w->nid != 2) 3846 w->enable = 0; 3847 } 3848 break; 3849 case HDA_CODEC_STAC9221D: 3850 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3851 w = hdac_widget_get(devinfo, i); 3852 if (w == NULL || w->enable == 0) 3853 continue; 3854 if (w->type == 3855 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3856 w->nid != 6) 3857 w->enable = 0; 3858 3859 } 3860 break; 3861 default: 3862 break; 3863 } 3864} 3865 3866static int 3867hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3868{ 3869 int *dev = &devinfo->function.audio.ossidx; 3870 3871 while (*dev < SOUND_MIXER_NRDEVICES) { 3872 switch (*dev) { 3873 case SOUND_MIXER_VOLUME: 3874 case SOUND_MIXER_BASS: 3875 case SOUND_MIXER_TREBLE: 3876 case SOUND_MIXER_PCM: 3877 case SOUND_MIXER_SPEAKER: 3878 case SOUND_MIXER_LINE: 3879 case SOUND_MIXER_MIC: 3880 case SOUND_MIXER_CD: 3881 case SOUND_MIXER_RECLEV: 3882 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3883 (*dev)++; 3884 break; 3885 default: 3886 return (*dev)++; 3887 break; 3888 } 3889 } 3890 3891 return (-1); 3892} 3893 3894static int 3895hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3896{ 3897 struct hdac_widget *w; 3898 int i, ret = 0; 3899 3900 if (depth > HDA_PARSE_MAXDEPTH) 3901 return (0); 3902 w = hdac_widget_get(devinfo, nid); 3903 if (w == NULL || w->enable == 0) 3904 return (0); 3905 switch (w->type) { 3906 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3907 w->pflags |= HDA_DAC_PATH; 3908 ret = 1; 3909 break; 3910 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3911 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3912 for (i = 0; i < w->nconns; i++) { 3913 if (hdac_widget_find_dac_path(devinfo, 3914 w->conns[i], depth + 1) != 0) { 3915 if (w->selconn == -1) 3916 w->selconn = i; 3917 ret = 1; 3918 w->pflags |= HDA_DAC_PATH; 3919 } 3920 } 3921 break; 3922 default: 3923 break; 3924 } 3925 return (ret); 3926} 3927 3928static int 3929hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3930{ 3931 struct hdac_widget *w; 3932 int i, conndev, ret = 0; 3933 3934 if (depth > HDA_PARSE_MAXDEPTH) 3935 return (0); 3936 w = hdac_widget_get(devinfo, nid); 3937 if (w == NULL || w->enable == 0) 3938 return (0); 3939 switch (w->type) { 3940 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3941 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3942 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3943 for (i = 0; i < w->nconns; i++) { 3944 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3945 depth + 1) != 0) { 3946 if (w->selconn == -1) 3947 w->selconn = i; 3948 w->pflags |= HDA_ADC_PATH; 3949 ret = 1; 3950 } 3951 } 3952 break; 3953 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3954 conndev = w->wclass.pin.config & 3955 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3956 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3957 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3958 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3959 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3960 w->pflags |= HDA_ADC_PATH; 3961 ret = 1; 3962 } 3963 break; 3964 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3965 if (w->pflags & HDA_DAC_PATH) { 3966 w->pflags |= HDA_ADC_PATH; 3967 ret = 1; 3968 } 3969 break;*/ 3970 default: 3971 break; 3972 } 3973 return (ret); 3974} 3975 3976static uint32_t 3977hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3978 nid_t nid, nid_t pnid, int index, int depth) 3979{ 3980 struct hdac_widget *w, *pw; 3981 struct hdac_audio_ctl *ctl; 3982 uint32_t fl = 0; 3983 int i, ossdev, conndev, strategy; 3984 3985 if (depth > HDA_PARSE_MAXDEPTH) 3986 return (0); 3987 3988 w = hdac_widget_get(devinfo, nid); 3989 if (w == NULL || w->enable == 0) 3990 return (0); 3991 3992 pw = hdac_widget_get(devinfo, pnid); 3993 strategy = devinfo->function.audio.parsing_strategy; 3994 3995 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3996 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3997 for (i = 0; i < w->nconns; i++) { 3998 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3999 w->nid, i, depth + 1); 4000 } 4001 w->ctlflags |= fl; 4002 return (fl); 4003 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 4004 (w->pflags & HDA_DAC_PATH)) { 4005 i = 0; 4006 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4007 if (ctl->enable == 0 || ctl->widget == NULL) 4008 continue; 4009 /* XXX This should be compressed! */ 4010 if ((ctl->widget->nid == w->nid) || 4011 (ctl->widget->nid == pnid && ctl->index == index && 4012 (ctl->dir & HDA_CTL_IN)) || 4013 (ctl->widget->nid == pnid && pw != NULL && 4014 pw->type == 4015 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4016 (pw->nconns < 2 || pw->selconn == index || 4017 pw->selconn == -1) && 4018 (ctl->dir & HDA_CTL_OUT)) || 4019 (strategy == HDA_PARSE_DIRECT && 4020 ctl->widget->nid == w->nid)) { 4021 /*if (pw != NULL && pw->selconn == -1) 4022 pw->selconn = index; 4023 fl |= SOUND_MASK_VOLUME; 4024 fl |= SOUND_MASK_PCM; 4025 ctl->ossmask |= SOUND_MASK_VOLUME; 4026 ctl->ossmask |= SOUND_MASK_PCM; 4027 ctl->ossdev = SOUND_MIXER_PCM;*/ 4028 if (!(w->ctlflags & SOUND_MASK_PCM) || 4029 (pw != NULL && 4030 !(pw->ctlflags & SOUND_MASK_PCM))) { 4031 fl |= SOUND_MASK_VOLUME; 4032 fl |= SOUND_MASK_PCM; 4033 ctl->ossmask |= SOUND_MASK_VOLUME; 4034 ctl->ossmask |= SOUND_MASK_PCM; 4035 ctl->ossdev = SOUND_MIXER_PCM; 4036 w->ctlflags |= SOUND_MASK_VOLUME; 4037 w->ctlflags |= SOUND_MASK_PCM; 4038 if (pw != NULL) { 4039 if (pw->selconn == -1) 4040 pw->selconn = index; 4041 pw->ctlflags |= 4042 SOUND_MASK_VOLUME; 4043 pw->ctlflags |= 4044 SOUND_MASK_PCM; 4045 } 4046 } 4047 } 4048 } 4049 w->ctlflags |= fl; 4050 return (fl); 4051 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4052 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4053 (w->pflags & HDA_ADC_PATH)) { 4054 conndev = w->wclass.pin.config & 4055 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4056 i = 0; 4057 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4058 if (ctl->enable == 0 || ctl->widget == NULL) 4059 continue; 4060 /* XXX This should be compressed! */ 4061 if (((ctl->widget->nid == pnid && ctl->index == index && 4062 (ctl->dir & HDA_CTL_IN)) || 4063 (ctl->widget->nid == pnid && pw != NULL && 4064 pw->type == 4065 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4066 (pw->nconns < 2 || pw->selconn == index || 4067 pw->selconn == -1) && 4068 (ctl->dir & HDA_CTL_OUT)) || 4069 (strategy == HDA_PARSE_DIRECT && 4070 ctl->widget->nid == w->nid)) && 4071 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4072 if (pw != NULL && pw->selconn == -1) 4073 pw->selconn = index; 4074 ossdev = 0; 4075 switch (conndev) { 4076 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4077 ossdev = SOUND_MIXER_MIC; 4078 break; 4079 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4080 ossdev = SOUND_MIXER_LINE; 4081 break; 4082 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4083 ossdev = SOUND_MIXER_CD; 4084 break; 4085 default: 4086 ossdev = 4087 hdac_audio_ctl_ossmixer_getnextdev( 4088 devinfo); 4089 if (ossdev < 0) 4090 ossdev = 0; 4091 break; 4092 } 4093 if (strategy == HDA_PARSE_MIXER) { 4094 fl |= SOUND_MASK_VOLUME; 4095 ctl->ossmask |= SOUND_MASK_VOLUME; 4096 } 4097 fl |= 1 << ossdev; 4098 ctl->ossmask |= 1 << ossdev; 4099 ctl->ossdev = ossdev; 4100 } 4101 } 4102 w->ctlflags |= fl; 4103 return (fl); 4104 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4105 i = 0; 4106 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4107 if (ctl->enable == 0 || ctl->widget == NULL) 4108 continue; 4109 /* XXX This should be compressed! */ 4110 if (((ctl->widget->nid == pnid && ctl->index == index && 4111 (ctl->dir & HDA_CTL_IN)) || 4112 (ctl->widget->nid == pnid && pw != NULL && 4113 pw->type == 4114 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4115 (pw->nconns < 2 || pw->selconn == index || 4116 pw->selconn == -1) && 4117 (ctl->dir & HDA_CTL_OUT)) || 4118 (strategy == HDA_PARSE_DIRECT && 4119 ctl->widget->nid == w->nid)) && 4120 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4121 if (pw != NULL && pw->selconn == -1) 4122 pw->selconn = index; 4123 fl |= SOUND_MASK_VOLUME; 4124 fl |= SOUND_MASK_SPEAKER; 4125 ctl->ossmask |= SOUND_MASK_VOLUME; 4126 ctl->ossmask |= SOUND_MASK_SPEAKER; 4127 ctl->ossdev = SOUND_MIXER_SPEAKER; 4128 } 4129 } 4130 w->ctlflags |= fl; 4131 return (fl); 4132 } 4133 return (0); 4134} 4135 4136static uint32_t 4137hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4138{ 4139 struct hdac_widget *w, *cw; 4140 struct hdac_audio_ctl *ctl; 4141 uint32_t fl; 4142 int i; 4143 4144 if (depth > HDA_PARSE_MAXDEPTH) 4145 return (0); 4146 4147 w = hdac_widget_get(devinfo, nid); 4148 if (w == NULL || w->enable == 0) 4149 return (0); 4150 /*if (!(w->pflags & HDA_ADC_PATH)) 4151 return (0); 4152 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4153 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4154 return (0);*/ 4155 i = 0; 4156 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4157 if (ctl->enable == 0 || ctl->widget == NULL) 4158 continue; 4159 if (ctl->widget->nid == nid) { 4160 ctl->ossmask |= SOUND_MASK_RECLEV; 4161 w->ctlflags |= SOUND_MASK_RECLEV; 4162 return (SOUND_MASK_RECLEV); 4163 } 4164 } 4165 for (i = 0; i < w->nconns; i++) { 4166 cw = hdac_widget_get(devinfo, w->conns[i]); 4167 if (cw == NULL || cw->enable == 0) 4168 continue; 4169 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4170 continue; 4171 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4172 if (fl != 0) { 4173 cw->ctlflags |= fl; 4174 w->ctlflags |= fl; 4175 return (fl); 4176 } 4177 } 4178 return (0); 4179} 4180 4181static int 4182hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4183{ 4184 struct hdac_widget *w, *cw; 4185 int i, child = 0; 4186 4187 if (depth > HDA_PARSE_MAXDEPTH) 4188 return (0); 4189 4190 w = hdac_widget_get(devinfo, nid); 4191 if (w == NULL || w->enable == 0) 4192 return (0); 4193 /*if (!(w->pflags & HDA_ADC_PATH)) 4194 return (0); 4195 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4196 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4197 return (0);*/ 4198 /* XXX weak! */ 4199 for (i = 0; i < w->nconns; i++) { 4200 cw = hdac_widget_get(devinfo, w->conns[i]); 4201 if (cw == NULL) 4202 continue; 4203 if (++child > 1) { 4204 w->pflags |= HDA_ADC_RECSEL; 4205 return (1); 4206 } 4207 } 4208 for (i = 0; i < w->nconns; i++) { 4209 if (hdac_audio_ctl_recsel_build(devinfo, 4210 w->conns[i], depth + 1) != 0) 4211 return (1); 4212 } 4213 return (0); 4214} 4215 4216static int 4217hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4218{ 4219 struct hdac_widget *w, *cw; 4220 int i, j, conndev, found_dac = 0; 4221 int strategy; 4222 4223 strategy = devinfo->function.audio.parsing_strategy; 4224 4225 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4226 w = hdac_widget_get(devinfo, i); 4227 if (w == NULL || w->enable == 0) 4228 continue; 4229 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4230 continue; 4231 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4232 continue; 4233 conndev = w->wclass.pin.config & 4234 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4235 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4236 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4237 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4238 continue; 4239 for (j = 0; j < w->nconns; j++) { 4240 cw = hdac_widget_get(devinfo, w->conns[j]); 4241 if (cw == NULL || cw->enable == 0) 4242 continue; 4243 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4244 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4245 cw->type == 4246 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4247 continue; 4248 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4249 != 0) { 4250 if (w->selconn == -1) 4251 w->selconn = j; 4252 w->pflags |= HDA_DAC_PATH; 4253 found_dac++; 4254 } 4255 } 4256 } 4257 4258 return (found_dac); 4259} 4260 4261static void 4262hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4263{ 4264 struct hdac_widget *w; 4265 struct hdac_audio_ctl *ctl; 4266 int i, j, dacs, strategy; 4267 4268 /* Construct DAC path */ 4269 strategy = HDA_PARSE_MIXER; 4270 devinfo->function.audio.parsing_strategy = strategy; 4271 HDA_BOOTVERBOSE( 4272 device_printf(devinfo->codec->sc->dev, 4273 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4274 HDA_WIDGET_PARSER_REV); 4275 ); 4276 dacs = hdac_audio_build_tree_strategy(devinfo); 4277 if (dacs == 0) { 4278 HDA_BOOTVERBOSE( 4279 device_printf(devinfo->codec->sc->dev, 4280 "HDA_DEBUG: HWiP: 0 DAC path found! " 4281 "Retrying parser " 4282 "using HDA_PARSE_DIRECT strategy.\n"); 4283 ); 4284 strategy = HDA_PARSE_DIRECT; 4285 devinfo->function.audio.parsing_strategy = strategy; 4286 dacs = hdac_audio_build_tree_strategy(devinfo); 4287 } 4288 4289 HDA_BOOTVERBOSE( 4290 device_printf(devinfo->codec->sc->dev, 4291 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4292 "strategy.\n", 4293 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4294 ); 4295 4296 /* Construct ADC path */ 4297 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4298 w = hdac_widget_get(devinfo, i); 4299 if (w == NULL || w->enable == 0) 4300 continue; 4301 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4302 continue; 4303 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4304 } 4305 4306 /* Output mixers */ 4307 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4308 w = hdac_widget_get(devinfo, i); 4309 if (w == NULL || w->enable == 0) 4310 continue; 4311 if ((strategy == HDA_PARSE_MIXER && 4312 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4313 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4314 && (w->pflags & HDA_DAC_PATH)) || 4315 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4316 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4317 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4318 w->nid, devinfo->startnode - 1, 0, 0); 4319 } else if (w->type == 4320 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4321 j = 0; 4322 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4323 NULL) { 4324 if (ctl->enable == 0 || ctl->widget == NULL) 4325 continue; 4326 if (ctl->widget->nid != w->nid) 4327 continue; 4328 ctl->ossmask |= SOUND_MASK_VOLUME; 4329 ctl->ossmask |= SOUND_MASK_SPEAKER; 4330 ctl->ossdev = SOUND_MIXER_SPEAKER; 4331 w->ctlflags |= SOUND_MASK_VOLUME; 4332 w->ctlflags |= SOUND_MASK_SPEAKER; 4333 } 4334 } 4335 } 4336 4337 /* Input mixers (rec) */ 4338 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4339 w = hdac_widget_get(devinfo, i); 4340 if (w == NULL || w->enable == 0) 4341 continue; 4342 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4343 w->pflags & HDA_ADC_PATH)) 4344 continue; 4345 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4346 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4347 } 4348} 4349 4350#define HDA_COMMIT_CONN (1 << 0) 4351#define HDA_COMMIT_CTRL (1 << 1) 4352#define HDA_COMMIT_EAPD (1 << 2) 4353#define HDA_COMMIT_GPIO (1 << 3) 4354#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4355 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4356 4357static void 4358hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4359{ 4360 struct hdac_softc *sc = devinfo->codec->sc; 4361 struct hdac_widget *w; 4362 nid_t cad; 4363 int i; 4364 4365 if (!(cfl & HDA_COMMIT_ALL)) 4366 return; 4367 4368 cad = devinfo->codec->cad; 4369 4370 if (cfl & HDA_COMMIT_GPIO) { 4371 uint32_t gdata, gmask, gdir; 4372 int commitgpio = 0; 4373 4374 gdata = 0; 4375 gmask = 0; 4376 gdir = 0; 4377 4378 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4379 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4380 0x7e7, 0), cad); 4381 4382 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4383 commitgpio = 1; 4384 else { 4385 for (i = 0; i < HDA_GPIO_MAX; i++) { 4386 if (!(devinfo->function.audio.quirks & 4387 (1 << i))) 4388 continue; 4389 if (commitgpio == 0) { 4390 commitgpio = 1; 4391 gdata = hdac_command(sc, 4392 HDA_CMD_GET_GPIO_DATA(cad, 4393 devinfo->nid), cad); 4394 gmask = hdac_command(sc, 4395 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4396 devinfo->nid), cad); 4397 gdir = hdac_command(sc, 4398 HDA_CMD_GET_GPIO_DIRECTION(cad, 4399 devinfo->nid), cad); 4400 HDA_BOOTVERBOSE( 4401 device_printf(sc->dev, 4402 "GPIO init: data=0x%08x " 4403 "mask=0x%08x dir=0x%08x\n", 4404 gdata, gmask, gdir); 4405 ); 4406 } 4407 gdata |= 1 << i; 4408 gmask |= 1 << i; 4409 gdir |= 1 << i; 4410 } 4411 } 4412 4413 if (commitgpio != 0) { 4414 HDA_BOOTVERBOSE( 4415 device_printf(sc->dev, 4416 "GPIO commit: data=0x%08x mask=0x%08x " 4417 "dir=0x%08x\n", 4418 gdata, gmask, gdir); 4419 ); 4420 hdac_command(sc, 4421 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4422 gmask), cad); 4423 hdac_command(sc, 4424 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4425 gdir), cad); 4426 hdac_command(sc, 4427 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4428 gdata), cad); 4429 } 4430 } 4431 4432 for (i = 0; i < devinfo->nodecnt; i++) { 4433 w = &devinfo->widget[i]; 4434 if (w == NULL || w->enable == 0) 4435 continue; 4436 if (cfl & HDA_COMMIT_CONN) { 4437 if (w->selconn == -1) 4438 w->selconn = 0; 4439 if (w->nconns > 0) 4440 hdac_widget_connection_select(w, w->selconn); 4441 } 4442 if ((cfl & HDA_COMMIT_CTRL) && 4443 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4444 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4445 (HDA_DAC_PATH | HDA_ADC_PATH)) 4446 device_printf(sc->dev, "WARNING: node %d " 4447 "participate both for DAC/ADC!\n", w->nid); 4448 if (w->pflags & HDA_DAC_PATH) { 4449 w->wclass.pin.ctrl &= 4450 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4451 if ((w->wclass.pin.config & 4452 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4453 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4454 w->wclass.pin.ctrl &= 4455 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4456 } else if (w->pflags & HDA_ADC_PATH) { 4457 w->wclass.pin.ctrl &= 4458 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4459 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4460 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4461 uint32_t pincap = w->wclass.pin.cap; 4462 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4463 w->wclass.pin.ctrl |= 4464 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4465 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4466 ); 4467 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4468 w->wclass.pin.ctrl |= 4469 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4470 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4471 ); 4472 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4473 w->wclass.pin.ctrl |= 4474 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4475 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4476 ); 4477 } 4478 } else 4479 w->wclass.pin.ctrl &= ~( 4480 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4481 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4482 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4483 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4484 hdac_command(sc, 4485 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4486 w->wclass.pin.ctrl), cad); 4487 } 4488 if ((cfl & HDA_COMMIT_EAPD) && 4489 w->param.eapdbtl != HDAC_INVALID) { 4490 uint32_t val; 4491 4492 val = w->param.eapdbtl; 4493 if (devinfo->function.audio.quirks & 4494 HDA_QUIRK_EAPDINV) 4495 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4496 hdac_command(sc, 4497 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4498 val), cad); 4499 4500 } 4501 DELAY(1000); 4502 } 4503} 4504 4505static void 4506hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4507{ 4508 struct hdac_softc *sc = devinfo->codec->sc; 4509 struct hdac_audio_ctl *ctl; 4510 int i; 4511 4512 devinfo->function.audio.mvol = 100 | (100 << 8); 4513 i = 0; 4514 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4515 if (ctl->enable == 0 || ctl->widget == NULL) { 4516 HDA_BOOTVERBOSE( 4517 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4518 i, (ctl->widget != NULL) ? 4519 ctl->widget->nid : -1); 4520 if (ctl->childwidget != NULL) 4521 printf(" childnid=%d", 4522 ctl->childwidget->nid); 4523 if (ctl->widget == NULL) 4524 printf(" NULL WIDGET!"); 4525 printf(" DISABLED\n"); 4526 ); 4527 continue; 4528 } 4529 HDA_BOOTVERBOSE( 4530 if (ctl->ossmask == 0) { 4531 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4532 i, ctl->widget->nid); 4533 if (ctl->childwidget != NULL) 4534 printf(" childnid=%d", 4535 ctl->childwidget->nid); 4536 printf(" Bind to NONE\n"); 4537 } 4538 ); 4539 if (ctl->step > 0) { 4540 ctl->ossval = (ctl->left * 100) / ctl->step; 4541 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4542 } else 4543 ctl->ossval = 0; 4544 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4545 ctl->left, ctl->right); 4546 } 4547} 4548 4549static int 4550hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4551{ 4552 struct hdac_chan *ch; 4553 struct hdac_widget *w; 4554 uint32_t cap, fmtcap, pcmcap, path; 4555 int i, type, ret, max; 4556 4557 if (dir == PCMDIR_PLAY) { 4558 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4559 ch = &devinfo->codec->sc->play; 4560 path = HDA_DAC_PATH; 4561 } else { 4562 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4563 ch = &devinfo->codec->sc->rec; 4564 path = HDA_ADC_PATH; 4565 } 4566 4567 ch->caps = hdac_caps; 4568 ch->caps.fmtlist = ch->fmtlist; 4569 ch->bit16 = 1; 4570 ch->bit32 = 0; 4571 ch->pcmrates[0] = 48000; 4572 ch->pcmrates[1] = 0; 4573 4574 ret = 0; 4575 fmtcap = devinfo->function.audio.supp_stream_formats; 4576 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4577 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4578 4579 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4580 w = hdac_widget_get(devinfo, i); 4581 if (w == NULL || w->enable == 0 || w->type != type || 4582 !(w->pflags & path)) 4583 continue; 4584 cap = w->param.widget_cap; 4585 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4586 continue;*/ 4587 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4588 continue; 4589 cap = w->param.supp_stream_formats; 4590 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4591 } 4592 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4593 }*/ 4594 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4595 continue; 4596 if (ret == 0) { 4597 fmtcap = w->param.supp_stream_formats; 4598 pcmcap = w->param.supp_pcm_size_rate; 4599 } else { 4600 fmtcap &= w->param.supp_stream_formats; 4601 pcmcap &= w->param.supp_pcm_size_rate; 4602 } 4603 ch->io[ret++] = i; 4604 } 4605 ch->io[ret] = -1; 4606 4607 ch->supp_stream_formats = fmtcap; 4608 ch->supp_pcm_size_rate = pcmcap; 4609 4610 /* 4611 * 8bit = 0 4612 * 16bit = 1 4613 * 20bit = 2 4614 * 24bit = 3 4615 * 32bit = 4 4616 */ 4617 if (ret > 0) { 4618 cap = pcmcap; 4619 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4620 ch->bit16 = 1; 4621 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4622 ch->bit16 = 0; 4623 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4624 ch->bit32 = 4; 4625 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4626 ch->bit32 = 3; 4627 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4628 ch->bit32 = 2; 4629 i = 0; 4630 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4631 ch->fmtlist[i++] = AFMT_S16_LE; 4632 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4633 if (ch->bit32 > 0) { 4634 if (!(devinfo->function.audio.quirks & 4635 HDA_QUIRK_FORCESTEREO)) 4636 ch->fmtlist[i++] = AFMT_S32_LE; 4637 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4638 } 4639 ch->fmtlist[i] = 0; 4640 i = 0; 4641 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4642 ch->pcmrates[i++] = 8000; 4643 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4644 ch->pcmrates[i++] = 11025; 4645 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4646 ch->pcmrates[i++] = 16000; 4647 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4648 ch->pcmrates[i++] = 22050; 4649 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4650 ch->pcmrates[i++] = 32000; 4651 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4652 ch->pcmrates[i++] = 44100; 4653 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4654 ch->pcmrates[i++] = 48000; 4655 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4656 ch->pcmrates[i++] = 88200; 4657 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4658 ch->pcmrates[i++] = 96000; 4659 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4660 ch->pcmrates[i++] = 176400; 4661 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4662 ch->pcmrates[i++] = 192000; 4663 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4664 ch->pcmrates[i] = 0; 4665 if (i > 0) { 4666 ch->caps.minspeed = ch->pcmrates[0]; 4667 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4668 } 4669 } 4670 4671 return (ret); 4672} 4673 4674static void 4675hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4676{ 4677 struct hdac_audio_ctl *ctl; 4678 struct hdac_softc *sc = devinfo->codec->sc; 4679 int i; 4680 uint32_t fl = 0; 4681 4682 4683 if (flag == 0) { 4684 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4685 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4686 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4687 } 4688 4689 i = 0; 4690 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4691 if (ctl->enable == 0 || ctl->widget == NULL || 4692 ctl->widget->enable == 0) 4693 continue; 4694 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4695 (flag != 0 && (ctl->ossmask & flag))) { 4696 if (banner != NULL) { 4697 device_printf(sc->dev, "\n"); 4698 device_printf(sc->dev, "%s\n", banner); 4699 } 4700 goto hdac_ctl_dump_it_all; 4701 } 4702 } 4703 4704 return; 4705 4706hdac_ctl_dump_it_all: 4707 i = 0; 4708 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4709 if (ctl->enable == 0 || ctl->widget == NULL || 4710 ctl->widget->enable == 0) 4711 continue; 4712 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4713 (flag != 0 && (ctl->ossmask & flag)))) 4714 continue; 4715 if (flag == 0) { 4716 device_printf(sc->dev, "\n"); 4717 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4718 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4719 } 4720 device_printf(sc->dev, " |\n"); 4721 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4722 ctl->widget->nid, ctl->index); 4723 if (ctl->childwidget != NULL) 4724 printf("(nid: %2d) ", ctl->childwidget->nid); 4725 else 4726 printf(" "); 4727 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4728 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4729 ctl->ossmask); 4730 } 4731} 4732 4733static void 4734hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4735{ 4736 uint32_t cap; 4737 4738 cap = fcap; 4739 if (cap != 0) { 4740 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4741 device_printf(sc->dev, " Format:"); 4742 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4743 printf(" AC3"); 4744 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4745 printf(" FLOAT32"); 4746 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4747 printf(" PCM"); 4748 printf("\n"); 4749 } 4750 cap = pcmcap; 4751 if (cap != 0) { 4752 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4753 device_printf(sc->dev, " PCM size:"); 4754 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4755 printf(" 8"); 4756 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4757 printf(" 16"); 4758 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4759 printf(" 20"); 4760 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4761 printf(" 24"); 4762 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4763 printf(" 32"); 4764 printf("\n"); 4765 device_printf(sc->dev, " PCM rate:"); 4766 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4767 printf(" 8"); 4768 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4769 printf(" 11"); 4770 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4771 printf(" 16"); 4772 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4773 printf(" 22"); 4774 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4775 printf(" 32"); 4776 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4777 printf(" 44"); 4778 printf(" 48"); 4779 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4780 printf(" 88"); 4781 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4782 printf(" 96"); 4783 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4784 printf(" 176"); 4785 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4786 printf(" 192"); 4787 printf("\n"); 4788 } 4789} 4790 4791static void 4792hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4793{ 4794 uint32_t pincap, wcap; 4795 4796 pincap = w->wclass.pin.cap; 4797 wcap = w->param.widget_cap; 4798 4799 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4800 device_printf(sc->dev, " "); 4801 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4802 printf(" ISC"); 4803 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4804 printf(" TRQD"); 4805 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4806 printf(" PDC"); 4807 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4808 printf(" HP"); 4809 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4810 printf(" OUT"); 4811 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4812 printf(" IN"); 4813 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4814 printf(" BAL"); 4815 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4816 printf(" VREF["); 4817 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4818 printf(" 50"); 4819 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4820 printf(" 80"); 4821 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4822 printf(" 100"); 4823 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4824 printf(" GROUND"); 4825 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4826 printf(" HIZ"); 4827 printf(" ]"); 4828 } 4829 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4830 printf(" EAPD"); 4831 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4832 printf(" : UNSOL"); 4833 printf("\n"); 4834 device_printf(sc->dev, " Pin config: 0x%08x\n", 4835 w->wclass.pin.config); 4836 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4837 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4838 printf(" HP"); 4839 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4840 printf(" IN"); 4841 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4842 printf(" OUT"); 4843 printf("\n"); 4844} 4845 4846static void 4847hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4848{ 4849 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4850 device_printf(sc->dev, " " 4851 "mute=%d step=%d size=%d offset=%d\n", 4852 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4853 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4854 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4855 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4856} 4857 4858static void 4859hdac_dump_nodes(struct hdac_devinfo *devinfo) 4860{ 4861 struct hdac_softc *sc = devinfo->codec->sc; 4862 struct hdac_widget *w, *cw; 4863 int i, j; 4864 4865 device_printf(sc->dev, "\n"); 4866 device_printf(sc->dev, "Default Parameter\n"); 4867 device_printf(sc->dev, "-----------------\n"); 4868 hdac_dump_audio_formats(sc, 4869 devinfo->function.audio.supp_stream_formats, 4870 devinfo->function.audio.supp_pcm_size_rate); 4871 device_printf(sc->dev, " IN amp: 0x%08x\n", 4872 devinfo->function.audio.inamp_cap); 4873 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4874 devinfo->function.audio.outamp_cap); 4875 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4876 w = hdac_widget_get(devinfo, i); 4877 if (w == NULL) { 4878 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4879 continue; 4880 } 4881 device_printf(sc->dev, "\n"); 4882 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4883 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4884 "DIGITAL" : "ANALOG", 4885 (w->enable == 0) ? " [DISABLED]" : ""); 4886 device_printf(sc->dev, " name: %s\n", w->name); 4887 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4888 w->param.widget_cap); 4889 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4890 w->pflags); 4891 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4892 w->ctlflags); 4893 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4894 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4895 hdac_dump_audio_formats(sc, 4896 w->param.supp_stream_formats, 4897 w->param.supp_pcm_size_rate); 4898 } else if (w->type == 4899 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4900 hdac_dump_pin(sc, w); 4901 if (w->param.eapdbtl != HDAC_INVALID) 4902 device_printf(sc->dev, " EAPD: 0x%08x\n", 4903 w->param.eapdbtl); 4904 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4905 w->param.outamp_cap != 0) 4906 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4907 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4908 w->param.inamp_cap != 0) 4909 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4910 device_printf(sc->dev, " connections: %d\n", w->nconns); 4911 for (j = 0; j < w->nconns; j++) { 4912 cw = hdac_widget_get(devinfo, w->conns[j]); 4913 device_printf(sc->dev, " |\n"); 4914 device_printf(sc->dev, " + <- nid=%d [%s]", 4915 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4916 if (cw == NULL) 4917 printf(" [UNKNOWN]"); 4918 else if (cw->enable == 0) 4919 printf(" [DISABLED]"); 4920 if (w->nconns > 1 && w->selconn == j && w->type != 4921 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4922 printf(" (selected)"); 4923 printf("\n"); 4924 } 4925 } 4926 4927} 4928 4929static int 4930hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4931{ 4932 struct hdac_widget *w, *cw; 4933 struct hdac_softc *sc = devinfo->codec->sc; 4934 int i; 4935 4936 if (depth > HDA_PARSE_MAXDEPTH) 4937 return (0); 4938 4939 w = hdac_widget_get(devinfo, nid); 4940 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4941 return (0); 4942 4943 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4944 device_printf(sc->dev, "\n"); 4945 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4946 device_printf(sc->dev, " ^\n"); 4947 device_printf(sc->dev, " |\n"); 4948 device_printf(sc->dev, " +-----<------+\n"); 4949 } else { 4950 device_printf(sc->dev, " ^\n"); 4951 device_printf(sc->dev, " |\n"); 4952 device_printf(sc->dev, " "); 4953 printf(" nid=%d [%s]\n", w->nid, w->name); 4954 } 4955 4956 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4957 return (1); 4958 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4959 for (i = 0; i < w->nconns; i++) { 4960 cw = hdac_widget_get(devinfo, w->conns[i]); 4961 if (cw == NULL || cw->enable == 0 || cw->type == 4962 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4963 continue; 4964 if (hdac_dump_dac_internal(devinfo, cw->nid, 4965 depth + 1) != 0) 4966 return (1); 4967 } 4968 } else if ((w->type == 4969 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4970 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4971 w->selconn > -1 && w->selconn < w->nconns) { 4972 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4973 depth + 1) != 0) 4974 return (1); 4975 } 4976 4977 return (0); 4978} 4979 4980static void 4981hdac_dump_dac(struct hdac_devinfo *devinfo) 4982{ 4983 struct hdac_widget *w; 4984 struct hdac_softc *sc = devinfo->codec->sc; 4985 int i, printed = 0; 4986 4987 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4988 w = hdac_widget_get(devinfo, i); 4989 if (w == NULL || w->enable == 0) 4990 continue; 4991 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4992 !(w->pflags & HDA_DAC_PATH)) 4993 continue; 4994 if (printed == 0) { 4995 printed = 1; 4996 device_printf(sc->dev, "\n"); 4997 device_printf(sc->dev, "Playback path:\n"); 4998 } 4999 hdac_dump_dac_internal(devinfo, w->nid, 0); 5000 } 5001} 5002 5003static void 5004hdac_dump_adc(struct hdac_devinfo *devinfo) 5005{ 5006 struct hdac_widget *w, *cw; 5007 struct hdac_softc *sc = devinfo->codec->sc; 5008 int i, j; 5009 int printed = 0; 5010 char ossdevs[256]; 5011 5012 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5013 w = hdac_widget_get(devinfo, i); 5014 if (w == NULL || w->enable == 0) 5015 continue; 5016 if (!(w->pflags & HDA_ADC_RECSEL)) 5017 continue; 5018 if (printed == 0) { 5019 printed = 1; 5020 device_printf(sc->dev, "\n"); 5021 device_printf(sc->dev, "Recording sources:\n"); 5022 } 5023 device_printf(sc->dev, "\n"); 5024 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 5025 for (j = 0; j < w->nconns; j++) { 5026 cw = hdac_widget_get(devinfo, w->conns[j]); 5027 if (cw == NULL || cw->enable == 0) 5028 continue; 5029 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5030 ossdevs, sizeof(ossdevs)); 5031 device_printf(sc->dev, " |\n"); 5032 device_printf(sc->dev, " + <- nid=%d [%s]", 5033 cw->nid, cw->name); 5034 if (strlen(ossdevs) > 0) { 5035 printf(" [recsrc: %s]", ossdevs); 5036 } 5037 printf("\n"); 5038 } 5039 } 5040} 5041 5042static void 5043hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5044{ 5045 nid_t *nids; 5046 5047 if (pcnt > 0) { 5048 device_printf(sc->dev, "\n"); 5049 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5050 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5051 sc->play.supp_pcm_size_rate); 5052 device_printf(sc->dev, " DAC:"); 5053 for (nids = sc->play.io; *nids != -1; nids++) 5054 printf(" %d", *nids); 5055 printf("\n"); 5056 } 5057 5058 if (rcnt > 0) { 5059 device_printf(sc->dev, "\n"); 5060 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5061 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5062 sc->rec.supp_pcm_size_rate); 5063 device_printf(sc->dev, " ADC:"); 5064 for (nids = sc->rec.io; *nids != -1; nids++) 5065 printf(" %d", *nids); 5066 printf("\n"); 5067 } 5068} 5069 5070static void 5071hdac_release_resources(struct hdac_softc *sc) 5072{ 5073 struct hdac_devinfo *devinfo = NULL; 5074 device_t *devlist = NULL; 5075 int i, devcount; 5076 5077 if (sc == NULL) 5078 return; 5079 5080 hdac_lock(sc); 5081 if (sc->polling != 0) 5082 callout_stop(&sc->poll_hdac); 5083 hdac_reset(sc); 5084 hdac_unlock(sc); 5085 snd_mtxfree(sc->lock); 5086 5087 device_get_children(sc->dev, &devlist, &devcount); 5088 for (i = 0; devlist != NULL && i < devcount; i++) { 5089 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5090 if (devinfo == NULL) 5091 continue; 5092 if (devinfo->widget != NULL) 5093 free(devinfo->widget, M_HDAC); 5094 if (devinfo->node_type == 5095 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5096 devinfo->function.audio.ctl != NULL) 5097 free(devinfo->function.audio.ctl, M_HDAC); 5098 free(devinfo, M_HDAC); 5099 device_delete_child(sc->dev, devlist[i]); 5100 } 5101 if (devlist != NULL) 5102 free(devlist, M_TEMP); 5103 5104 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5105 if (sc->codecs[i] != NULL) 5106 free(sc->codecs[i], M_HDAC); 5107 sc->codecs[i] = NULL; 5108 } 5109 5110 hdac_dma_free(&sc->rirb_dma); 5111 hdac_dma_free(&sc->corb_dma); 5112 if (sc->play.blkcnt > 0) 5113 hdac_dma_free(&sc->play.bdl_dma); 5114 if (sc->rec.blkcnt > 0) 5115 hdac_dma_free(&sc->rec.bdl_dma); 5116 if (sc->chan_dmat != NULL) { 5117 bus_dma_tag_destroy(sc->chan_dmat); 5118 sc->chan_dmat = NULL; 5119 } 5120 hdac_irq_free(sc); 5121 hdac_mem_free(sc); 5122 free(sc, M_DEVBUF); 5123} 5124 5125/* This function surely going to make its way into upper level someday. */ 5126static void 5127hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5128{ 5129 const char *res = NULL; 5130 int i = 0, j, k, len, inv; 5131 5132 if (on != NULL) 5133 *on = 0; 5134 if (off != NULL) 5135 *off = 0; 5136 if (sc == NULL) 5137 return; 5138 if (resource_string_value(device_get_name(sc->dev), 5139 device_get_unit(sc->dev), "config", &res) != 0) 5140 return; 5141 if (!(res != NULL && strlen(res) > 0)) 5142 return; 5143 HDA_BOOTVERBOSE( 5144 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5145 ); 5146 for (;;) { 5147 while (res[i] != '\0' && 5148 (res[i] == ',' || isspace(res[i]) != 0)) 5149 i++; 5150 if (res[i] == '\0') { 5151 HDA_BOOTVERBOSE( 5152 printf("\n"); 5153 ); 5154 return; 5155 } 5156 j = i; 5157 while (res[j] != '\0' && 5158 !(res[j] == ',' || isspace(res[j]) != 0)) 5159 j++; 5160 len = j - i; 5161 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5162 inv = 2; 5163 else 5164 inv = 0; 5165 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5166 if (strncmp(res + i + inv, 5167 hdac_quirks_tab[k].key, len - inv) != 0) 5168 continue; 5169 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5170 break; 5171 HDA_BOOTVERBOSE( 5172 printf(" %s%s", (inv != 0) ? "no" : "", 5173 hdac_quirks_tab[k].key); 5174 ); 5175 if (inv == 0 && on != NULL) 5176 *on |= hdac_quirks_tab[k].value; 5177 else if (inv != 0 && off != NULL) 5178 *off |= hdac_quirks_tab[k].value; 5179 break; 5180 } 5181 i = j; 5182 } 5183} 5184 5185#ifdef SND_DYNSYSCTL 5186static int 5187sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5188{ 5189 struct hdac_softc *sc; 5190 struct hdac_devinfo *devinfo; 5191 device_t dev; 5192 uint32_t ctl; 5193 int err, val; 5194 5195 dev = oidp->oid_arg1; 5196 devinfo = pcm_getdevinfo(dev); 5197 if (devinfo == NULL || devinfo->codec == NULL || 5198 devinfo->codec->sc == NULL) 5199 return (EINVAL); 5200 sc = devinfo->codec->sc; 5201 hdac_lock(sc); 5202 val = sc->polling; 5203 hdac_unlock(sc); 5204 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5205 5206 if (err || req->newptr == NULL) 5207 return (err); 5208 if (val < 0 || val > 1) 5209 return (EINVAL); 5210 5211 hdac_lock(sc); 5212 if (val != sc->polling) { 5213 if (hda_chan_active(sc) != 0) 5214 err = EBUSY; 5215 else if (val == 0) { 5216 callout_stop(&sc->poll_hdac); 5217 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5218 sc->rirb_size / 2); 5219 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5220 ctl |= HDAC_RIRBCTL_RINTCTL; 5221 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5222 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5223 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5224 sc->polling = 0; 5225 DELAY(1000); 5226 } else { 5227 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5228 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5229 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5230 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5231 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5232 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5233 sc); 5234 sc->polling = 1; 5235 DELAY(1000); 5236 } 5237 } 5238 hdac_unlock(sc); 5239 5240 return (err); 5241} 5242#endif 5243 5244static void 5245hdac_attach2(void *arg) 5246{ 5247 struct hdac_softc *sc; 5248 struct hdac_widget *w; 5249 struct hdac_audio_ctl *ctl; 5250 uint32_t quirks_on, quirks_off; 5251 int pcnt, rcnt; 5252 int i; 5253 char status[SND_STATUSLEN]; 5254 device_t *devlist = NULL; 5255 int devcount; 5256 struct hdac_devinfo *devinfo = NULL; 5257 5258 sc = (struct hdac_softc *)arg; 5259 5260 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5261 5262 HDA_BOOTVERBOSE( 5263 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5264 quirks_on, quirks_off); 5265 ); 5266 5267 hdac_lock(sc); 5268 5269 /* Remove ourselves from the config hooks */ 5270 if (sc->intrhook.ich_func != NULL) { 5271 config_intrhook_disestablish(&sc->intrhook); 5272 sc->intrhook.ich_func = NULL; 5273 } 5274 5275 /* Start the corb and rirb engines */ 5276 HDA_BOOTVERBOSE( 5277 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5278 ); 5279 hdac_corb_start(sc); 5280 HDA_BOOTVERBOSE( 5281 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5282 ); 5283 hdac_rirb_start(sc); 5284 5285 HDA_BOOTVERBOSE( 5286 device_printf(sc->dev, 5287 "HDA_DEBUG: Enabling controller interrupt...\n"); 5288 ); 5289 if (sc->polling == 0) 5290 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5291 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5292 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5293 HDAC_GCTL_UNSOL); 5294 5295 DELAY(1000); 5296 5297 HDA_BOOTVERBOSE( 5298 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5299 ); 5300 hdac_scan_codecs(sc); 5301 5302 device_get_children(sc->dev, &devlist, &devcount); 5303 for (i = 0; devlist != NULL && i < devcount; i++) { 5304 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5305 if (devinfo != NULL && devinfo->node_type == 5306 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5307 break; 5308 } else 5309 devinfo = NULL; 5310 } 5311 if (devlist != NULL) 5312 free(devlist, M_TEMP); 5313 5314 if (devinfo == NULL) { 5315 hdac_unlock(sc); 5316 device_printf(sc->dev, "Audio Function Group not found!\n"); 5317 hdac_release_resources(sc); 5318 return; 5319 } 5320 5321 HDA_BOOTVERBOSE( 5322 device_printf(sc->dev, 5323 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5324 devinfo->nid, devinfo->codec->cad); 5325 ); 5326 hdac_audio_parse(devinfo); 5327 HDA_BOOTVERBOSE( 5328 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5329 ); 5330 hdac_audio_ctl_parse(devinfo); 5331 HDA_BOOTVERBOSE( 5332 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5333 ); 5334 hdac_vendor_patch_parse(devinfo); 5335 if (quirks_on != 0) 5336 devinfo->function.audio.quirks |= quirks_on; 5337 if (quirks_off != 0) 5338 devinfo->function.audio.quirks &= ~quirks_off; 5339 5340 /* XXX Disable all DIGITAL path. */ 5341 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5342 w = hdac_widget_get(devinfo, i); 5343 if (w == NULL) 5344 continue; 5345 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5346 w->enable = 0; 5347 continue; 5348 } 5349 /* XXX Disable useless pin ? */ 5350 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5351 (w->wclass.pin.config & 5352 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5353 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5354 w->enable = 0; 5355 } 5356 i = 0; 5357 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5358 if (ctl->widget == NULL) 5359 continue; 5360 w = ctl->widget; 5361 if (w->enable == 0) 5362 ctl->enable = 0; 5363 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5364 ctl->enable = 0; 5365 w = ctl->childwidget; 5366 if (w == NULL) 5367 continue; 5368 if (w->enable == 0 || 5369 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5370 ctl->enable = 0; 5371 } 5372 5373 HDA_BOOTVERBOSE( 5374 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5375 ); 5376 hdac_audio_build_tree(devinfo); 5377 5378 HDA_BOOTVERBOSE( 5379 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5380 ); 5381 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5382 HDA_BOOTVERBOSE( 5383 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5384 ); 5385 hdac_audio_ctl_commit(devinfo); 5386 5387 HDA_BOOTVERBOSE( 5388 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5389 ); 5390 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5391 HDA_BOOTVERBOSE( 5392 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5393 ); 5394 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5395 5396 hdac_unlock(sc); 5397 HDA_BOOTVERBOSE( 5398 device_printf(sc->dev, 5399 "HDA_DEBUG: OSS mixer initialization...\n"); 5400 ); 5401 5402 /* 5403 * There is no point of return after this. If the driver failed, 5404 * so be it. Let the detach procedure do all the cleanup. 5405 */ 5406 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5407 device_printf(sc->dev, "Can't register mixer\n"); 5408 5409 if (pcnt > 0) 5410 pcnt = 1; 5411 if (rcnt > 0) 5412 rcnt = 1; 5413 5414 HDA_BOOTVERBOSE( 5415 device_printf(sc->dev, 5416 "HDA_DEBUG: Registering PCM channels...\n"); 5417 ); 5418 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5419 device_printf(sc->dev, "Can't register PCM\n"); 5420 5421 sc->registered++; 5422 5423 for (i = 0; i < pcnt; i++) 5424 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5425 for (i = 0; i < rcnt; i++) 5426 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5427 5428#ifdef SND_DYNSYSCTL 5429 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5430 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5431 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5432 sysctl_hdac_polling, "I", "Enable polling mode"); 5433#endif 5434 5435 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5436 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5437 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5438 pcm_setstatus(sc->dev, status); 5439 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5440 HDA_BOOTVERBOSE( 5441 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5442 hdac_codec_id(devinfo)); 5443 ); 5444 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5445 HDA_DRV_TEST_REV); 5446 5447 HDA_BOOTVERBOSE( 5448 if (devinfo->function.audio.quirks != 0) { 5449 device_printf(sc->dev, "\n"); 5450 device_printf(sc->dev, "HDA config/quirks:"); 5451 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5452 if (devinfo->function.audio.quirks & 5453 hdac_quirks_tab[i].value) 5454 printf(" %s", hdac_quirks_tab[i].key); 5455 } 5456 printf("\n"); 5457 } 5458 device_printf(sc->dev, "\n"); 5459 device_printf(sc->dev, "+-------------------+\n"); 5460 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5461 device_printf(sc->dev, "+-------------------+\n"); 5462 hdac_dump_nodes(devinfo); 5463 device_printf(sc->dev, "\n"); 5464 device_printf(sc->dev, "+------------------------+\n"); 5465 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5466 device_printf(sc->dev, "+------------------------+\n"); 5467 device_printf(sc->dev, "\n"); 5468 i = 0; 5469 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5470 device_printf(sc->dev, "%3d: nid=%d", i, 5471 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5472 if (ctl->childwidget != NULL) 5473 printf(" cnid=%d", ctl->childwidget->nid); 5474 printf(" dir=0x%x index=%d " 5475 "ossmask=0x%08x ossdev=%d%s\n", 5476 ctl->dir, ctl->index, 5477 ctl->ossmask, ctl->ossdev, 5478 (ctl->enable == 0) ? " [DISABLED]" : ""); 5479 } 5480 device_printf(sc->dev, "\n"); 5481 device_printf(sc->dev, "+-----------------------------------+\n"); 5482 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5483 device_printf(sc->dev, "+-----------------------------------+\n"); 5484 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5485 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5486 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5487 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5488 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5489 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5490 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5491 hdac_dump_ctls(devinfo, NULL, 0); 5492 hdac_dump_dac(devinfo); 5493 hdac_dump_adc(devinfo); 5494 device_printf(sc->dev, "\n"); 5495 device_printf(sc->dev, "+--------------------------------------+\n"); 5496 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5497 device_printf(sc->dev, "+--------------------------------------+\n"); 5498 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5499 ); 5500 5501 if (sc->polling != 0) { 5502 hdac_lock(sc); 5503 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5504 hdac_unlock(sc); 5505 } 5506} 5507 5508/**************************************************************************** 5509 * int hdac_detach(device_t) 5510 * 5511 * Detach and free up resources utilized by the hdac device. 5512 ****************************************************************************/ 5513static int 5514hdac_detach(device_t dev) 5515{ 5516 struct hdac_softc *sc = NULL; 5517 struct hdac_devinfo *devinfo = NULL; 5518 int err; 5519 5520 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5521 if (devinfo != NULL && devinfo->codec != NULL) 5522 sc = devinfo->codec->sc; 5523 if (sc == NULL) 5524 return (0); 5525 5526 if (sc->registered > 0) { 5527 err = pcm_unregister(dev); 5528 if (err != 0) 5529 return (err); 5530 } 5531 5532 hdac_release_resources(sc); 5533 5534 return (0); 5535} 5536 5537static device_method_t hdac_methods[] = { 5538 /* device interface */ 5539 DEVMETHOD(device_probe, hdac_probe), 5540 DEVMETHOD(device_attach, hdac_attach), 5541 DEVMETHOD(device_detach, hdac_detach), 5542 { 0, 0 } 5543}; 5544 5545static driver_t hdac_driver = { 5546 "pcm", 5547 hdac_methods, 5548 PCM_SOFTC_SIZE, 5549}; 5550 5551DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5552MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5553MODULE_VERSION(snd_hda, 1); 5554