hdac.c revision 167648
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20070317_0042" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 167648 2007-03-16 17:18:17Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* Intel */ 167#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168 169/* HP/Compaq */ 170#define HP_VENDORID 0x103c 171#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 176#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 177/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 178#define HP_NX6325_SUBVENDORX 0x103c30b0 179 180/* Dell */ 181#define DELL_VENDORID 0x1028 182#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 183#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 184#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 185 186/* Clevo */ 187#define CLEVO_VENDORID 0x1558 188#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 189#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 190 191/* Acer */ 192#define ACER_VENDORID 0x1025 193#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 194#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 195 196/* Asus */ 197#define ASUS_VENDORID 0x1043 198#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 199#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 200#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 201#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 202#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 203#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 204#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 205#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 206 207/* IBM / Lenovo */ 208#define IBM_VENDORID 0x1014 209#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 210#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 211 212/* Lenovo */ 213#define LENOVO_VENDORID 0x17aa 214#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 215#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 216 217/* Samsung */ 218#define SAMSUNG_VENDORID 0x144d 219#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 220#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 221 222/* Medion ? */ 223#define MEDION_VENDORID 0x161f 224#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 225#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 226 227/* 228 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 229 * instead of their own, which is beyond my comprehension 230 * (see HDA_CODEC_STAC9221 below). 231 */ 232#define APPLE_INTEL_MAC 0x76808384 233 234/* LG Electronics */ 235#define LG_VENDORID 0x1854 236#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 237#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 238 239/* Fujitsu Siemens */ 240#define FS_VENDORID 0x1734 241#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 242#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 243 244/* Toshiba */ 245#define TOSHIBA_VENDORID 0x1179 246#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 247#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 248 249/* Micro-Star International (MSI) */ 250#define MSI_VENDORID 0x1462 251#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 252#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 253 254/* Misc constants.. */ 255#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 256#define HDA_AMP_MUTE_NONE (0) 257#define HDA_AMP_MUTE_LEFT (1 << 0) 258#define HDA_AMP_MUTE_RIGHT (1 << 1) 259#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 260 261#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 262#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 263 264#define HDA_DAC_PATH (1 << 0) 265#define HDA_ADC_PATH (1 << 1) 266#define HDA_ADC_RECSEL (1 << 2) 267 268#define HDA_CTL_OUT (1 << 0) 269#define HDA_CTL_IN (1 << 1) 270#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 271 272#define HDA_GPIO_MAX 15 273/* 0 - 14 = GPIO */ 274#define HDA_QUIRK_GPIO0 (1 << 0) 275#define HDA_QUIRK_GPIO1 (1 << 1) 276#define HDA_QUIRK_GPIO2 (1 << 2) 277#define HDA_QUIRK_GPIOFLUSH (1 << 15) 278#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 279#define HDA_QUIRK_FIXEDRATE (1 << 17) 280#define HDA_QUIRK_FORCESTEREO (1 << 18) 281#define HDA_QUIRK_EAPDINV (1 << 19) 282#define HDA_QUIRK_VREF (1 << 20) 283 284static const struct { 285 char *key; 286 uint32_t value; 287} hdac_quirks_tab[] = { 288 { "gpio0", HDA_QUIRK_GPIO0 }, 289 { "gpio1", HDA_QUIRK_GPIO1 }, 290 { "gpio2", HDA_QUIRK_GPIO2 }, 291 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 292 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 293 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 294 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 295 { "eapdinv", HDA_QUIRK_EAPDINV }, 296 { "vref", HDA_QUIRK_VREF }, 297}; 298#define HDAC_QUIRKS_TAB_LEN \ 299 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 300 301#define HDA_BDL_MIN 2 302#define HDA_BDL_MAX 256 303#define HDA_BDL_DEFAULT HDA_BDL_MIN 304 305#define HDA_BLK_MIN 128 306#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 307 308#define HDA_BUFSZ_MIN 4096 309#define HDA_BUFSZ_MAX 65536 310#define HDA_BUFSZ_DEFAULT 16384 311 312#define HDA_PARSE_MAXDEPTH 10 313 314#define HDAC_UNSOLTAG_EVENT_HP 0x00 315 316MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 317 318enum { 319 HDA_PARSE_MIXER, 320 HDA_PARSE_DIRECT 321}; 322 323/* Default */ 324static uint32_t hdac_fmt[] = { 325 AFMT_STEREO | AFMT_S16_LE, 326 0 327}; 328 329static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 330 331static const struct { 332 uint32_t model; 333 char *desc; 334} hdac_devices[] = { 335 { HDA_INTEL_82801F, "Intel 82801F" }, 336 { HDA_INTEL_82801G, "Intel 82801G" }, 337 { HDA_INTEL_82801H, "Intel 82801H" }, 338 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 339 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 340 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 341 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 342 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 343 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 344 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 345 { HDA_ATI_SB450, "ATI SB450" }, 346 { HDA_ATI_SB600, "ATI SB600" }, 347 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 348 { HDA_SIS_966, "SiS 966" }, 349 /* Unknown */ 350 { HDA_INTEL_ALL, "Intel (Unknown)" }, 351 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 352 { HDA_ATI_ALL, "ATI (Unknown)" }, 353 { HDA_VIA_ALL, "VIA (Unknown)" }, 354 { HDA_SIS_ALL, "SiS (Unknown)" }, 355}; 356#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 357 358static const struct { 359 uint32_t rate; 360 int valid; 361 uint16_t base; 362 uint16_t mul; 363 uint16_t div; 364} hda_rate_tab[] = { 365 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 366 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 367 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 368 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 369 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 370 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 371 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 372 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 373 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 374 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 375 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 376 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 377 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 378 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 379 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 380 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 381 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 382 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 383 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 384 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 385 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 386 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 387 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 388 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 389 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 390 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 391 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 392 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 393 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 394 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 395 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 396 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 397 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 398 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 399 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 400}; 401#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 402 403/* All codecs you can eat... */ 404#define HDA_CODEC_CONSTRUCT(vendor, id) \ 405 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 406 407/* Realtek */ 408#define REALTEK_VENDORID 0x10ec 409#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 410#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 411#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 412#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 413#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 414#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 415#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 416 417/* Analog Device */ 418#define ANALOGDEVICE_VENDORID 0x11d4 419#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 420#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 421#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 422#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 423 424/* CMedia */ 425#define CMEDIA_VENDORID 0x434d 426#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 427#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 428 429/* Sigmatel */ 430#define SIGMATEL_VENDORID 0x8384 431#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 432#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 433#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 434#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 435#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 436#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 437#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 438 439/* 440 * Conexant 441 * 442 * Ok, the truth is, I don't have any idea at all whether 443 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 444 * place that tell me it is "Venice" is from its Windows driver INF. 445 * 446 * Venice - CX????? 447 * Waikiki - CX20551-22 448 */ 449#define CONEXANT_VENDORID 0x14f1 450#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 451#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 452#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 453 454 455/* Codecs */ 456static const struct { 457 uint32_t id; 458 char *name; 459} hdac_codecs[] = { 460 { HDA_CODEC_ALC260, "Realtek ALC260" }, 461 { HDA_CODEC_ALC861, "Realtek ALC861" }, 462 { HDA_CODEC_ALC880, "Realtek ALC880" }, 463 { HDA_CODEC_ALC882, "Realtek ALC882" }, 464 { HDA_CODEC_ALC883, "Realtek ALC883" }, 465 { HDA_CODEC_ALC888, "Realtek ALC888" }, 466 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 467 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 468 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 469 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 470 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 471 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 472 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 473 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 474 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 475 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 476 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 477 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 478 /* Unknown codec */ 479 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 480 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 481 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 482 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 483 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 484}; 485#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 486 487enum { 488 HDAC_HP_SWITCH_CTL, 489 HDAC_HP_SWITCH_CTRL 490}; 491 492static const struct { 493 uint32_t model; 494 uint32_t id; 495 int type; 496 int inverted; 497 nid_t hpnid; 498 nid_t spkrnid[8]; 499 nid_t eapdnid; 500} hdac_hp_switch[] = { 501 /* Specific OEM models */ 502 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 503 17, { 16, -1 }, 16 }, 504 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 505 6, { 5, -1 }, 5 }, 506 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 507 6, { 5, -1 }, 5 }, 508 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 509 6, { 5, -1 }, 5 }, 510 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 511 6, { 5, -1 }, -1 }, 512 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 513 13, { 14, -1 }, -1 }, 514 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 515 13, { 14, -1 }, -1 }, 516 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 517 10, { 13, -1 }, -1 }, 518 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 519 26, { 27, -1 }, -1 }, 520 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 521 27, { 20, -1 }, -1 }, 522 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 523 20, { 21, -1 }, -1 }, 524 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 525 20, { 27, -1 }, -1 }, 526 /* 527 * All models that at least come from the same vendor with 528 * simmilar codec. 529 */ 530 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 531 17, { 16, -1 }, 16 }, 532 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 533 6, { 5, -1 }, 5 }, 534 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 535 6, { 5, -1 }, -1 }, 536 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 537 13, { 14, -1 }, -1 }, 538 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 539 26, { 27, -1 }, -1 }, 540#if 0 541 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 542 20, { 21, -1 }, -1 }, 543#endif 544}; 545#define HDAC_HP_SWITCH_LEN \ 546 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 547 548static const struct { 549 uint32_t model; 550 uint32_t id; 551 nid_t eapdnid; 552 int hp_switch; 553} hdac_eapd_switch[] = { 554 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 555 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 556 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 557}; 558#define HDAC_EAPD_SWITCH_LEN \ 559 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 560 561/**************************************************************************** 562 * Function prototypes 563 ****************************************************************************/ 564static void hdac_intr_handler(void *); 565static int hdac_reset(struct hdac_softc *); 566static int hdac_get_capabilities(struct hdac_softc *); 567static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 568static int hdac_dma_alloc(struct hdac_softc *, 569 struct hdac_dma *, bus_size_t); 570static void hdac_dma_free(struct hdac_dma *); 571static int hdac_mem_alloc(struct hdac_softc *); 572static void hdac_mem_free(struct hdac_softc *); 573static int hdac_irq_alloc(struct hdac_softc *); 574static void hdac_irq_free(struct hdac_softc *); 575static void hdac_corb_init(struct hdac_softc *); 576static void hdac_rirb_init(struct hdac_softc *); 577static void hdac_corb_start(struct hdac_softc *); 578static void hdac_rirb_start(struct hdac_softc *); 579static void hdac_scan_codecs(struct hdac_softc *); 580static int hdac_probe_codec(struct hdac_codec *); 581static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 582static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 583 584static void hdac_attach2(void *); 585 586static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 587 uint32_t, int); 588static void hdac_command_send_internal(struct hdac_softc *, 589 struct hdac_command_list *, int); 590 591static int hdac_probe(device_t); 592static int hdac_attach(device_t); 593static int hdac_detach(device_t); 594static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 595static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 596 uint32_t, int, int); 597static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 598 nid_t, int, int); 599static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 600 nid_t, nid_t, int, int, int, int, int, int); 601static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 602static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 603 604static int hdac_rirb_flush(struct hdac_softc *sc); 605static int hdac_unsolq_flush(struct hdac_softc *sc); 606 607#define hdac_command(a1, a2, a3) \ 608 hdac_command_sendone_internal(a1, a2, a3) 609 610#define hdac_codec_id(d) \ 611 ((uint32_t)((d == NULL) ? 0x00000000 : \ 612 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 613 ((uint32_t)(d)->device_id & 0x0000ffff)))) 614 615static char * 616hdac_codec_name(struct hdac_devinfo *devinfo) 617{ 618 uint32_t id; 619 int i; 620 621 id = hdac_codec_id(devinfo); 622 623 for (i = 0; i < HDAC_CODECS_LEN; i++) { 624 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 625 return (hdac_codecs[i].name); 626 } 627 628 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 629} 630 631static char * 632hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 633{ 634 static char *ossname[] = SOUND_DEVICE_NAMES; 635 static char *unknown = "???"; 636 int i; 637 638 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 639 if (devmask & (1 << i)) 640 return (ossname[i]); 641 } 642 return (unknown); 643} 644 645static void 646hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 647{ 648 static char *ossname[] = SOUND_DEVICE_NAMES; 649 int i, first = 1; 650 651 bzero(buf, len); 652 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 653 if (mask & (1 << i)) { 654 if (first == 0) 655 strlcat(buf, ", ", len); 656 strlcat(buf, ossname[i], len); 657 first = 0; 658 } 659 } 660} 661 662static struct hdac_audio_ctl * 663hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 664{ 665 if (devinfo == NULL || 666 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 667 index == NULL || devinfo->function.audio.ctl == NULL || 668 devinfo->function.audio.ctlcnt < 1 || 669 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 670 return (NULL); 671 return (&devinfo->function.audio.ctl[(*index)++]); 672} 673 674static struct hdac_audio_ctl * 675hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 676 int index, int cnt) 677{ 678 struct hdac_audio_ctl *ctl, *retctl = NULL; 679 int i, at, atindex, found = 0; 680 681 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 682 return (NULL); 683 684 at = cnt; 685 if (at == 0) 686 at = 1; 687 else if (at < 0) 688 at = -1; 689 atindex = index; 690 if (atindex < 0) 691 atindex = -1; 692 693 i = 0; 694 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 695 if (ctl->enable == 0 || ctl->widget == NULL) 696 continue; 697 if (!(ctl->widget->nid == nid && (atindex == -1 || 698 ctl->index == atindex))) 699 continue; 700 found++; 701 if (found == cnt) 702 return (ctl); 703 retctl = ctl; 704 } 705 706 return ((at == -1) ? retctl : NULL); 707} 708 709static void 710hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 711{ 712 struct hdac_softc *sc; 713 struct hdac_widget *w; 714 struct hdac_audio_ctl *ctl; 715 uint32_t id, res; 716 int i = 0, j, forcemute; 717 nid_t cad; 718 719 if (devinfo == NULL || devinfo->codec == NULL || 720 devinfo->codec->sc == NULL) 721 return; 722 723 sc = devinfo->codec->sc; 724 cad = devinfo->codec->cad; 725 id = hdac_codec_id(devinfo); 726 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 727 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 728 sc->pci_subvendor) && 729 hdac_hp_switch[i].id == id) 730 break; 731 } 732 733 if (i >= HDAC_HP_SWITCH_LEN) 734 return; 735 736 forcemute = 0; 737 if (hdac_hp_switch[i].eapdnid != -1) { 738 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 739 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 740 forcemute = (w->param.eapdbtl & 741 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 742 } 743 744 res = hdac_command(sc, 745 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 746 HDA_BOOTVERBOSE( 747 device_printf(sc->dev, 748 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 749 hdac_hp_switch[i].hpnid, res); 750 ); 751 res >>= 31; 752 res ^= hdac_hp_switch[i].inverted; 753 754 switch (hdac_hp_switch[i].type) { 755 case HDAC_HP_SWITCH_CTL: 756 ctl = hdac_audio_ctl_amp_get(devinfo, 757 hdac_hp_switch[i].hpnid, 0, 1); 758 if (ctl != NULL) { 759 ctl->muted = (res != 0 && forcemute == 0) ? 760 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 761 hdac_audio_ctl_amp_set(ctl, 762 HDA_AMP_MUTE_DEFAULT, ctl->left, 763 ctl->right); 764 } 765 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 766 ctl = hdac_audio_ctl_amp_get(devinfo, 767 hdac_hp_switch[i].spkrnid[j], 0, 1); 768 if (ctl != NULL) { 769 ctl->muted = (res != 0 || forcemute == 1) ? 770 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 771 hdac_audio_ctl_amp_set(ctl, 772 HDA_AMP_MUTE_DEFAULT, ctl->left, 773 ctl->right); 774 } 775 } 776 break; 777 case HDAC_HP_SWITCH_CTRL: 778 if (res != 0) { 779 /* HP in */ 780 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 781 if (w != NULL && w->type == 782 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 783 if (forcemute == 0) 784 w->wclass.pin.ctrl |= 785 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 786 else 787 w->wclass.pin.ctrl &= 788 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 789 hdac_command(sc, 790 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 791 w->wclass.pin.ctrl), cad); 792 } 793 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 794 w = hdac_widget_get(devinfo, 795 hdac_hp_switch[i].spkrnid[j]); 796 if (w != NULL && w->type == 797 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 798 w->wclass.pin.ctrl &= 799 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 800 hdac_command(sc, 801 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 802 w->nid, 803 w->wclass.pin.ctrl), cad); 804 } 805 } 806 } else { 807 /* HP out */ 808 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 809 if (w != NULL && w->type == 810 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 811 w->wclass.pin.ctrl &= 812 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 813 hdac_command(sc, 814 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 815 w->wclass.pin.ctrl), cad); 816 } 817 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 818 w = hdac_widget_get(devinfo, 819 hdac_hp_switch[i].spkrnid[j]); 820 if (w != NULL && w->type == 821 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 822 if (forcemute == 0) 823 w->wclass.pin.ctrl |= 824 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 825 else 826 w->wclass.pin.ctrl &= 827 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 828 hdac_command(sc, 829 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 830 w->nid, 831 w->wclass.pin.ctrl), cad); 832 } 833 } 834 } 835 break; 836 default: 837 break; 838 } 839} 840 841static void 842hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 843{ 844 struct hdac_softc *sc; 845 struct hdac_devinfo *devinfo = NULL; 846 device_t *devlist = NULL; 847 int devcount, i; 848 849 if (codec == NULL || codec->sc == NULL) 850 return; 851 852 sc = codec->sc; 853 854 HDA_BOOTVERBOSE( 855 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 856 ); 857 858 device_get_children(sc->dev, &devlist, &devcount); 859 for (i = 0; devlist != NULL && i < devcount; i++) { 860 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 861 if (devinfo != NULL && devinfo->node_type == 862 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 863 devinfo->codec != NULL && 864 devinfo->codec->cad == codec->cad) { 865 break; 866 } else 867 devinfo = NULL; 868 } 869 if (devlist != NULL) 870 free(devlist, M_TEMP); 871 872 if (devinfo == NULL) 873 return; 874 875 switch (tag) { 876 case HDAC_UNSOLTAG_EVENT_HP: 877 hdac_hp_switch_handler(devinfo); 878 break; 879 default: 880 break; 881 } 882} 883 884static int 885hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 886{ 887 /* XXX to be removed */ 888#ifdef HDAC_INTR_EXTRA 889 uint32_t res; 890#endif 891 892 if (ch->blkcnt == 0) 893 return (0); 894 895 /* XXX to be removed */ 896#ifdef HDAC_INTR_EXTRA 897 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 898#endif 899 900 /* XXX to be removed */ 901#ifdef HDAC_INTR_EXTRA 902 HDA_BOOTVERBOSE( 903 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 904 device_printf(sc->dev, 905 "PCMDIR_%s intr triggered beyond stream boundary:" 906 "%08x\n", 907 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 908 ); 909#endif 910 911 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 912 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 913 914 /* XXX to be removed */ 915#ifdef HDAC_INTR_EXTRA 916 if (res & HDAC_SDSTS_BCIS) { 917#endif 918 return (1); 919 /* XXX to be removed */ 920#ifdef HDAC_INTR_EXTRA 921 } 922#endif 923 924 return (0); 925} 926 927/**************************************************************************** 928 * void hdac_intr_handler(void *) 929 * 930 * Interrupt handler. Processes interrupts received from the hdac. 931 ****************************************************************************/ 932static void 933hdac_intr_handler(void *context) 934{ 935 struct hdac_softc *sc; 936 uint32_t intsts; 937 uint8_t rirbsts; 938 struct hdac_rirb *rirb_base; 939 uint32_t trigger = 0; 940 941 sc = (struct hdac_softc *)context; 942 943 hdac_lock(sc); 944 if (sc->polling != 0) { 945 hdac_unlock(sc); 946 return; 947 } 948 /* Do we have anything to do? */ 949 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 950 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 951 hdac_unlock(sc); 952 return; 953 } 954 955 /* Was this a controller interrupt? */ 956 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 957 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 958 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 959 /* Get as many responses that we can */ 960 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 961 HDAC_WRITE_1(&sc->mem, 962 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 963 hdac_rirb_flush(sc); 964 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 965 } 966 /* XXX to be removed */ 967 /* Clear interrupt and exit */ 968#ifdef HDAC_INTR_EXTRA 969 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 970#endif 971 } 972 973 hdac_unsolq_flush(sc); 974 975 if (intsts & HDAC_INTSTS_SIS_MASK) { 976 if ((intsts & (1 << sc->num_iss)) && 977 hdac_stream_intr(sc, &sc->play) != 0) 978 trigger |= 1; 979 if ((intsts & (1 << 0)) && 980 hdac_stream_intr(sc, &sc->rec) != 0) 981 trigger |= 2; 982 /* XXX to be removed */ 983#ifdef HDAC_INTR_EXTRA 984 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 985 HDAC_INTSTS_SIS_MASK); 986#endif 987 } 988 989 hdac_unlock(sc); 990 991 if (trigger & 1) 992 chn_intr(sc->play.c); 993 if (trigger & 2) 994 chn_intr(sc->rec.c); 995} 996 997/**************************************************************************** 998 * int hdac_reset(hdac_softc *) 999 * 1000 * Reset the hdac to a quiescent and known state. 1001 ****************************************************************************/ 1002static int 1003hdac_reset(struct hdac_softc *sc) 1004{ 1005 uint32_t gctl; 1006 int count, i; 1007 1008 /* 1009 * Stop all Streams DMA engine 1010 */ 1011 for (i = 0; i < sc->num_iss; i++) 1012 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1013 for (i = 0; i < sc->num_oss; i++) 1014 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1015 for (i = 0; i < sc->num_bss; i++) 1016 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1017 1018 /* 1019 * Stop Control DMA engines 1020 */ 1021 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1022 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1023 1024 /* 1025 * Reset the controller. The reset must remain asserted for 1026 * a minimum of 100us. 1027 */ 1028 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1029 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1030 count = 10000; 1031 do { 1032 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1033 if (!(gctl & HDAC_GCTL_CRST)) 1034 break; 1035 DELAY(10); 1036 } while (--count); 1037 if (gctl & HDAC_GCTL_CRST) { 1038 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1039 return (ENXIO); 1040 } 1041 DELAY(100); 1042 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1043 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1044 count = 10000; 1045 do { 1046 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1047 if (gctl & HDAC_GCTL_CRST) 1048 break; 1049 DELAY(10); 1050 } while (--count); 1051 if (!(gctl & HDAC_GCTL_CRST)) { 1052 device_printf(sc->dev, "Device stuck in reset\n"); 1053 return (ENXIO); 1054 } 1055 1056 /* 1057 * Wait for codecs to finish their own reset sequence. The delay here 1058 * should be of 250us but for some reasons, on it's not enough on my 1059 * computer. Let's use twice as much as necessary to make sure that 1060 * it's reset properly. 1061 */ 1062 DELAY(1000); 1063 1064 return (0); 1065} 1066 1067 1068/**************************************************************************** 1069 * int hdac_get_capabilities(struct hdac_softc *); 1070 * 1071 * Retreive the general capabilities of the hdac; 1072 * Number of Input Streams 1073 * Number of Output Streams 1074 * Number of bidirectional Streams 1075 * 64bit ready 1076 * CORB and RIRB sizes 1077 ****************************************************************************/ 1078static int 1079hdac_get_capabilities(struct hdac_softc *sc) 1080{ 1081 uint16_t gcap; 1082 uint8_t corbsize, rirbsize; 1083 1084 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1085 sc->num_iss = HDAC_GCAP_ISS(gcap); 1086 sc->num_oss = HDAC_GCAP_OSS(gcap); 1087 sc->num_bss = HDAC_GCAP_BSS(gcap); 1088 1089 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1090 1091 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1092 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1093 HDAC_CORBSIZE_CORBSZCAP_256) 1094 sc->corb_size = 256; 1095 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1096 HDAC_CORBSIZE_CORBSZCAP_16) 1097 sc->corb_size = 16; 1098 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1099 HDAC_CORBSIZE_CORBSZCAP_2) 1100 sc->corb_size = 2; 1101 else { 1102 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1103 __func__, corbsize); 1104 return (ENXIO); 1105 } 1106 1107 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1108 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1109 HDAC_RIRBSIZE_RIRBSZCAP_256) 1110 sc->rirb_size = 256; 1111 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1112 HDAC_RIRBSIZE_RIRBSZCAP_16) 1113 sc->rirb_size = 16; 1114 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1115 HDAC_RIRBSIZE_RIRBSZCAP_2) 1116 sc->rirb_size = 2; 1117 else { 1118 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1119 __func__, rirbsize); 1120 return (ENXIO); 1121 } 1122 1123 return (0); 1124} 1125 1126 1127/**************************************************************************** 1128 * void hdac_dma_cb 1129 * 1130 * This function is called by bus_dmamap_load when the mapping has been 1131 * established. We just record the physical address of the mapping into 1132 * the struct hdac_dma passed in. 1133 ****************************************************************************/ 1134static void 1135hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1136{ 1137 struct hdac_dma *dma; 1138 1139 if (error == 0) { 1140 dma = (struct hdac_dma *)callback_arg; 1141 dma->dma_paddr = segs[0].ds_addr; 1142 } 1143} 1144 1145static void 1146hdac_dma_nocache(void *ptr) 1147{ 1148#if 0 1149#if defined(__i386__) || defined(__amd64__) 1150 pt_entry_t *pte; 1151 vm_offset_t va; 1152 1153 va = (vm_offset_t)ptr; 1154 pte = vtopte(va); 1155 if (pte) { 1156 *pte |= PG_N; 1157 invltlb(); 1158 } 1159#endif 1160#endif 1161} 1162 1163/**************************************************************************** 1164 * int hdac_dma_alloc 1165 * 1166 * This function allocate and setup a dma region (struct hdac_dma). 1167 * It must be freed by a corresponding hdac_dma_free. 1168 ****************************************************************************/ 1169static int 1170hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1171{ 1172 int result; 1173 int lowaddr; 1174 1175 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1176 BUS_SPACE_MAXADDR_32BIT; 1177 bzero(dma, sizeof(*dma)); 1178 1179 /* 1180 * Create a DMA tag 1181 */ 1182 result = bus_dma_tag_create(NULL, /* parent */ 1183 HDAC_DMA_ALIGNMENT, /* alignment */ 1184 0, /* boundary */ 1185 lowaddr, /* lowaddr */ 1186 BUS_SPACE_MAXADDR, /* highaddr */ 1187 NULL, /* filtfunc */ 1188 NULL, /* fistfuncarg */ 1189 size, /* maxsize */ 1190 1, /* nsegments */ 1191 size, /* maxsegsz */ 1192 0, /* flags */ 1193 NULL, /* lockfunc */ 1194 NULL, /* lockfuncarg */ 1195 &dma->dma_tag); /* dmat */ 1196 if (result != 0) { 1197 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1198 __func__, result); 1199 goto fail; 1200 } 1201 1202 /* 1203 * Allocate DMA memory 1204 */ 1205 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1206 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1207 if (result != 0) { 1208 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1209 __func__, result); 1210 goto fail; 1211 } 1212 1213 /* 1214 * Map the memory 1215 */ 1216 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1217 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1218 BUS_DMA_NOWAIT); 1219 if (result != 0 || dma->dma_paddr == 0) { 1220 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1221 __func__, result); 1222 goto fail; 1223 } 1224 bzero((void *)dma->dma_vaddr, size); 1225 hdac_dma_nocache(dma->dma_vaddr); 1226 1227 return (0); 1228fail: 1229 if (dma->dma_map != NULL) 1230 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1231 if (dma->dma_tag != NULL) 1232 bus_dma_tag_destroy(dma->dma_tag); 1233 return (result); 1234} 1235 1236 1237/**************************************************************************** 1238 * void hdac_dma_free(struct hdac_dma *) 1239 * 1240 * Free a struct dhac_dma that has been previously allocated via the 1241 * hdac_dma_alloc function. 1242 ****************************************************************************/ 1243static void 1244hdac_dma_free(struct hdac_dma *dma) 1245{ 1246 if (dma->dma_tag != NULL) { 1247 /* Flush caches */ 1248 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1249 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1250 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1251 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1252 bus_dma_tag_destroy(dma->dma_tag); 1253 } 1254} 1255 1256/**************************************************************************** 1257 * int hdac_mem_alloc(struct hdac_softc *) 1258 * 1259 * Allocate all the bus resources necessary to speak with the physical 1260 * controller. 1261 ****************************************************************************/ 1262static int 1263hdac_mem_alloc(struct hdac_softc *sc) 1264{ 1265 struct hdac_mem *mem; 1266 1267 mem = &sc->mem; 1268 mem->mem_rid = PCIR_BAR(0); 1269 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1270 &mem->mem_rid, RF_ACTIVE); 1271 if (mem->mem_res == NULL) { 1272 device_printf(sc->dev, 1273 "%s: Unable to allocate memory resource\n", __func__); 1274 return (ENOMEM); 1275 } 1276 mem->mem_tag = rman_get_bustag(mem->mem_res); 1277 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1278 1279 return (0); 1280} 1281 1282/**************************************************************************** 1283 * void hdac_mem_free(struct hdac_softc *) 1284 * 1285 * Free up resources previously allocated by hdac_mem_alloc. 1286 ****************************************************************************/ 1287static void 1288hdac_mem_free(struct hdac_softc *sc) 1289{ 1290 struct hdac_mem *mem; 1291 1292 mem = &sc->mem; 1293 if (mem->mem_res != NULL) 1294 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1295 mem->mem_res); 1296 mem->mem_res = NULL; 1297} 1298 1299/**************************************************************************** 1300 * int hdac_irq_alloc(struct hdac_softc *) 1301 * 1302 * Allocate and setup the resources necessary for interrupt handling. 1303 ****************************************************************************/ 1304static int 1305hdac_irq_alloc(struct hdac_softc *sc) 1306{ 1307 struct hdac_irq *irq; 1308 int result; 1309 1310 irq = &sc->irq; 1311 irq->irq_rid = 0x0; 1312 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1313 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1314 if (irq->irq_res == NULL) { 1315 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1316 __func__); 1317 goto fail; 1318 } 1319 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1320 hdac_intr_handler, sc, &irq->irq_handle); 1321 if (result != 0) { 1322 device_printf(sc->dev, 1323 "%s: Unable to setup interrupt handler (%x)\n", 1324 __func__, result); 1325 goto fail; 1326 } 1327 1328 return (0); 1329 1330fail: 1331 hdac_irq_free(sc); 1332 1333 return (ENXIO); 1334} 1335 1336/**************************************************************************** 1337 * void hdac_irq_free(struct hdac_softc *) 1338 * 1339 * Free up resources previously allocated by hdac_irq_alloc. 1340 ****************************************************************************/ 1341static void 1342hdac_irq_free(struct hdac_softc *sc) 1343{ 1344 struct hdac_irq *irq; 1345 1346 irq = &sc->irq; 1347 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1348 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1349 if (irq->irq_res != NULL) 1350 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1351 irq->irq_res); 1352 irq->irq_handle = NULL; 1353 irq->irq_res = NULL; 1354} 1355 1356/**************************************************************************** 1357 * void hdac_corb_init(struct hdac_softc *) 1358 * 1359 * Initialize the corb registers for operations but do not start it up yet. 1360 * The CORB engine must not be running when this function is called. 1361 ****************************************************************************/ 1362static void 1363hdac_corb_init(struct hdac_softc *sc) 1364{ 1365 uint8_t corbsize; 1366 uint64_t corbpaddr; 1367 1368 /* Setup the CORB size. */ 1369 switch (sc->corb_size) { 1370 case 256: 1371 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1372 break; 1373 case 16: 1374 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1375 break; 1376 case 2: 1377 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1378 break; 1379 default: 1380 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1381 } 1382 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1383 1384 /* Setup the CORB Address in the hdac */ 1385 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1386 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1387 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1388 1389 /* Set the WP and RP */ 1390 sc->corb_wp = 0; 1391 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1392 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1393 /* 1394 * The HDA specification indicates that the CORBRPRST bit will always 1395 * read as zero. Unfortunately, it seems that at least the 82801G 1396 * doesn't reset the bit to zero, which stalls the corb engine. 1397 * manually reset the bit to zero before continuing. 1398 */ 1399 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1400 1401 /* Enable CORB error reporting */ 1402#if 0 1403 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1404#endif 1405} 1406 1407/**************************************************************************** 1408 * void hdac_rirb_init(struct hdac_softc *) 1409 * 1410 * Initialize the rirb registers for operations but do not start it up yet. 1411 * The RIRB engine must not be running when this function is called. 1412 ****************************************************************************/ 1413static void 1414hdac_rirb_init(struct hdac_softc *sc) 1415{ 1416 uint8_t rirbsize; 1417 uint64_t rirbpaddr; 1418 1419 /* Setup the RIRB size. */ 1420 switch (sc->rirb_size) { 1421 case 256: 1422 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1423 break; 1424 case 16: 1425 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1426 break; 1427 case 2: 1428 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1429 break; 1430 default: 1431 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1432 } 1433 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1434 1435 /* Setup the RIRB Address in the hdac */ 1436 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1437 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1438 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1439 1440 /* Setup the WP and RP */ 1441 sc->rirb_rp = 0; 1442 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1443 1444 if (sc->polling == 0) { 1445 /* Setup the interrupt threshold */ 1446 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1447 1448 /* Enable Overrun and response received reporting */ 1449#if 0 1450 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1451 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1452#else 1453 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1454#endif 1455 } 1456 1457 /* 1458 * Make sure that the Host CPU cache doesn't contain any dirty 1459 * cache lines that falls in the rirb. If I understood correctly, it 1460 * should be sufficient to do this only once as the rirb is purely 1461 * read-only from now on. 1462 */ 1463 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1464 BUS_DMASYNC_PREREAD); 1465} 1466 1467/**************************************************************************** 1468 * void hdac_corb_start(hdac_softc *) 1469 * 1470 * Startup the corb DMA engine 1471 ****************************************************************************/ 1472static void 1473hdac_corb_start(struct hdac_softc *sc) 1474{ 1475 uint32_t corbctl; 1476 1477 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1478 corbctl |= HDAC_CORBCTL_CORBRUN; 1479 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1480} 1481 1482/**************************************************************************** 1483 * void hdac_rirb_start(hdac_softc *) 1484 * 1485 * Startup the rirb DMA engine 1486 ****************************************************************************/ 1487static void 1488hdac_rirb_start(struct hdac_softc *sc) 1489{ 1490 uint32_t rirbctl; 1491 1492 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1493 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1494 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1495} 1496 1497 1498/**************************************************************************** 1499 * void hdac_scan_codecs(struct hdac_softc *) 1500 * 1501 * Scan the bus for available codecs. 1502 ****************************************************************************/ 1503static void 1504hdac_scan_codecs(struct hdac_softc *sc) 1505{ 1506 struct hdac_codec *codec; 1507 int i; 1508 uint16_t statests; 1509 1510 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1511 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1512 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1513 /* We have found a codec. */ 1514 hdac_unlock(sc); 1515 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1516 M_HDAC, M_ZERO | M_NOWAIT); 1517 hdac_lock(sc); 1518 if (codec == NULL) { 1519 device_printf(sc->dev, 1520 "Unable to allocate memory for codec\n"); 1521 continue; 1522 } 1523 codec->commands = NULL; 1524 codec->responses_received = 0; 1525 codec->verbs_sent = 0; 1526 codec->sc = sc; 1527 codec->cad = i; 1528 sc->codecs[i] = codec; 1529 if (hdac_probe_codec(codec) != 0) 1530 break; 1531 } 1532 } 1533 /* All codecs have been probed, now try to attach drivers to them */ 1534 /* bus_generic_attach(sc->dev); */ 1535} 1536 1537/**************************************************************************** 1538 * void hdac_probe_codec(struct hdac_softc *, int) 1539 * 1540 * Probe a the given codec_id for available function groups. 1541 ****************************************************************************/ 1542static int 1543hdac_probe_codec(struct hdac_codec *codec) 1544{ 1545 struct hdac_softc *sc = codec->sc; 1546 struct hdac_devinfo *devinfo; 1547 uint32_t vendorid, revisionid, subnode; 1548 int startnode; 1549 int endnode; 1550 int i; 1551 nid_t cad = codec->cad; 1552 1553 HDA_BOOTVERBOSE( 1554 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1555 ); 1556 vendorid = hdac_command(sc, 1557 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1558 cad); 1559 revisionid = hdac_command(sc, 1560 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1561 cad); 1562 subnode = hdac_command(sc, 1563 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1564 cad); 1565 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1566 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1567 1568 HDA_BOOTVERBOSE( 1569 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1570 startnode, endnode); 1571 ); 1572 for (i = startnode; i < endnode; i++) { 1573 devinfo = hdac_probe_function(codec, i); 1574 if (devinfo != NULL) { 1575 /* XXX Ignore other FG. */ 1576 devinfo->vendor_id = 1577 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1578 devinfo->device_id = 1579 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1580 devinfo->revision_id = 1581 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1582 devinfo->stepping_id = 1583 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1584 HDA_BOOTVERBOSE( 1585 device_printf(sc->dev, 1586 "HDA_DEBUG: \tFound AFG nid=%d " 1587 "[startnode=%d endnode=%d]\n", 1588 devinfo->nid, startnode, endnode); 1589 ); 1590 return (1); 1591 } 1592 } 1593 1594 HDA_BOOTVERBOSE( 1595 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1596 ); 1597 return (0); 1598} 1599 1600static struct hdac_devinfo * 1601hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1602{ 1603 struct hdac_softc *sc = codec->sc; 1604 struct hdac_devinfo *devinfo; 1605 uint32_t fctgrptype; 1606 nid_t cad = codec->cad; 1607 1608 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1609 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1610 1611 /* XXX For now, ignore other FG. */ 1612 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1613 return (NULL); 1614 1615 hdac_unlock(sc); 1616 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1617 M_NOWAIT | M_ZERO); 1618 hdac_lock(sc); 1619 if (devinfo == NULL) { 1620 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1621 __func__); 1622 return (NULL); 1623 } 1624 1625 devinfo->nid = nid; 1626 devinfo->node_type = fctgrptype; 1627 devinfo->codec = codec; 1628 1629 hdac_add_child(sc, devinfo); 1630 1631 return (devinfo); 1632} 1633 1634static void 1635hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1636{ 1637 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1638 device_set_ivars(devinfo->dev, (void *)devinfo); 1639 /* XXX - Print more information when booting verbose??? */ 1640} 1641 1642static void 1643hdac_widget_connection_parse(struct hdac_widget *w) 1644{ 1645 struct hdac_softc *sc = w->devinfo->codec->sc; 1646 uint32_t res; 1647 int i, j, max, found, entnum, cnid; 1648 nid_t cad = w->devinfo->codec->cad; 1649 nid_t nid = w->nid; 1650 1651 res = hdac_command(sc, 1652 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1653 1654 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1655 1656 if (w->nconns < 1) 1657 return; 1658 1659 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1660 res = 0; 1661 i = 0; 1662 found = 0; 1663 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1664 1665 while (i < w->nconns) { 1666 res = hdac_command(sc, 1667 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1668 for (j = 0; j < entnum; j++) { 1669 cnid = res; 1670 cnid >>= (32 / entnum) * j; 1671 cnid &= (1 << (32 / entnum)) - 1; 1672 if (cnid == 0) 1673 continue; 1674 if (found > max) { 1675 device_printf(sc->dev, 1676 "node %d: Adding %d: " 1677 "Max connection reached!\n", 1678 nid, cnid); 1679 continue; 1680 } 1681 w->conns[found++] = cnid; 1682 } 1683 i += entnum; 1684 } 1685 1686 HDA_BOOTVERBOSE( 1687 if (w->nconns != found) { 1688 device_printf(sc->dev, 1689 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1690 "length=%d != found=%d\n", 1691 nid, w->nconns, found); 1692 } 1693 ); 1694} 1695 1696static uint32_t 1697hdac_widget_pin_getconfig(struct hdac_widget *w) 1698{ 1699 struct hdac_softc *sc; 1700 uint32_t config, orig, id; 1701 nid_t cad, nid; 1702 1703 sc = w->devinfo->codec->sc; 1704 cad = w->devinfo->codec->cad; 1705 nid = w->nid; 1706 id = hdac_codec_id(w->devinfo); 1707 1708 config = hdac_command(sc, 1709 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1710 cad); 1711 orig = config; 1712 1713 /* 1714 * XXX REWRITE!!!! Don't argue! 1715 */ 1716 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1717 switch (nid) { 1718 case 26: 1719 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1720 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1721 break; 1722 case 27: 1723 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1724 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1725 break; 1726 default: 1727 break; 1728 } 1729 } else if (id == HDA_CODEC_ALC880 && 1730 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1731 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1732 /* 1733 * Super broken BIOS 1734 */ 1735 switch (nid) { 1736 case 20: 1737 break; 1738 case 21: 1739 break; 1740 case 22: 1741 break; 1742 case 23: 1743 break; 1744 case 24: /* MIC1 */ 1745 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1746 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1747 break; 1748 case 25: /* XXX MIC2 */ 1749 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1750 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1751 break; 1752 case 26: /* LINE1 */ 1753 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1754 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1755 break; 1756 case 27: /* XXX LINE2 */ 1757 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1758 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1759 break; 1760 case 28: /* CD */ 1761 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1762 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1763 break; 1764 case 30: 1765 break; 1766 case 31: 1767 break; 1768 default: 1769 break; 1770 } 1771 } else if (id == HDA_CODEC_ALC883 && 1772 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1773 switch (nid) { 1774 case 25: 1775 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1776 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1777 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1778 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1779 break; 1780 default: 1781 break; 1782 } 1783 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1784 HP_V3000_SUBVENDOR) { 1785 switch (nid) { 1786 case 18: 1787 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1788 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1789 break; 1790 case 20: 1791 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1792 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1793 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1794 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1795 break; 1796 case 21: 1797 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1798 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1799 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1800 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1801 break; 1802 default: 1803 break; 1804 } 1805 } 1806 1807 HDA_BOOTVERBOSE( 1808 if (config != orig) 1809 device_printf(sc->dev, 1810 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 1811 nid, orig, config); 1812 ); 1813 1814 return (config); 1815} 1816 1817static uint32_t 1818hdac_widget_pin_getcaps(struct hdac_widget *w) 1819{ 1820 struct hdac_softc *sc; 1821 uint32_t caps, orig, id; 1822 nid_t cad, nid; 1823 1824 sc = w->devinfo->codec->sc; 1825 cad = w->devinfo->codec->cad; 1826 nid = w->nid; 1827 id = hdac_codec_id(w->devinfo); 1828 1829 caps = hdac_command(sc, 1830 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1831 orig = caps; 1832 1833 HDA_BOOTVERBOSE( 1834 if (caps != orig) 1835 device_printf(sc->dev, 1836 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 1837 nid, orig, caps); 1838 ); 1839 1840 return (caps); 1841} 1842 1843static void 1844hdac_widget_pin_parse(struct hdac_widget *w) 1845{ 1846 struct hdac_softc *sc = w->devinfo->codec->sc; 1847 uint32_t config, pincap; 1848 char *devstr, *connstr; 1849 nid_t cad = w->devinfo->codec->cad; 1850 nid_t nid = w->nid; 1851 1852 config = hdac_widget_pin_getconfig(w); 1853 w->wclass.pin.config = config; 1854 1855 pincap = hdac_widget_pin_getcaps(w); 1856 w->wclass.pin.cap = pincap; 1857 1858 w->wclass.pin.ctrl = hdac_command(sc, 1859 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1860 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1861 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1862 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1863 1864 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1865 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1866 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1867 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1868 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1869 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1870 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1871 w->param.eapdbtl = hdac_command(sc, 1872 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1873 w->param.eapdbtl &= 0x7; 1874 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1875 } else 1876 w->param.eapdbtl = HDAC_INVALID; 1877 1878 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1879 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1880 devstr = "line out"; 1881 break; 1882 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1883 devstr = "speaker"; 1884 break; 1885 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1886 devstr = "headphones out"; 1887 break; 1888 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1889 devstr = "CD"; 1890 break; 1891 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1892 devstr = "SPDIF out"; 1893 break; 1894 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1895 devstr = "digital (other) out"; 1896 break; 1897 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1898 devstr = "modem, line side"; 1899 break; 1900 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1901 devstr = "modem, handset side"; 1902 break; 1903 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1904 devstr = "line in"; 1905 break; 1906 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1907 devstr = "AUX"; 1908 break; 1909 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1910 devstr = "Mic in"; 1911 break; 1912 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1913 devstr = "telephony"; 1914 break; 1915 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1916 devstr = "SPDIF in"; 1917 break; 1918 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1919 devstr = "digital (other) in"; 1920 break; 1921 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1922 devstr = "other"; 1923 break; 1924 default: 1925 devstr = "unknown"; 1926 break; 1927 } 1928 1929 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1930 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1931 connstr = "jack"; 1932 break; 1933 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1934 connstr = "none"; 1935 break; 1936 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1937 connstr = "fixed"; 1938 break; 1939 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1940 connstr = "jack / fixed"; 1941 break; 1942 default: 1943 connstr = "unknown"; 1944 break; 1945 } 1946 1947 strlcat(w->name, ": ", sizeof(w->name)); 1948 strlcat(w->name, devstr, sizeof(w->name)); 1949 strlcat(w->name, " (", sizeof(w->name)); 1950 strlcat(w->name, connstr, sizeof(w->name)); 1951 strlcat(w->name, ")", sizeof(w->name)); 1952} 1953 1954static void 1955hdac_widget_parse(struct hdac_widget *w) 1956{ 1957 struct hdac_softc *sc = w->devinfo->codec->sc; 1958 uint32_t wcap, cap; 1959 char *typestr; 1960 nid_t cad = w->devinfo->codec->cad; 1961 nid_t nid = w->nid; 1962 1963 wcap = hdac_command(sc, 1964 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1965 cad); 1966 w->param.widget_cap = wcap; 1967 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1968 1969 switch (w->type) { 1970 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1971 typestr = "audio output"; 1972 break; 1973 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1974 typestr = "audio input"; 1975 break; 1976 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1977 typestr = "audio mixer"; 1978 break; 1979 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1980 typestr = "audio selector"; 1981 break; 1982 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1983 typestr = "pin"; 1984 break; 1985 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1986 typestr = "power widget"; 1987 break; 1988 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1989 typestr = "volume widget"; 1990 break; 1991 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1992 typestr = "beep widget"; 1993 break; 1994 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1995 typestr = "vendor widget"; 1996 break; 1997 default: 1998 typestr = "unknown type"; 1999 break; 2000 } 2001 2002 strlcpy(w->name, typestr, sizeof(w->name)); 2003 2004 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2005 hdac_command(sc, 2006 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2007 cad); 2008 DELAY(1000); 2009 } 2010 2011 hdac_widget_connection_parse(w); 2012 2013 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2014 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2015 w->param.outamp_cap = 2016 hdac_command(sc, 2017 HDA_CMD_GET_PARAMETER(cad, nid, 2018 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2019 else 2020 w->param.outamp_cap = 2021 w->devinfo->function.audio.outamp_cap; 2022 } else 2023 w->param.outamp_cap = 0; 2024 2025 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2026 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2027 w->param.inamp_cap = 2028 hdac_command(sc, 2029 HDA_CMD_GET_PARAMETER(cad, nid, 2030 HDA_PARAM_INPUT_AMP_CAP), cad); 2031 else 2032 w->param.inamp_cap = 2033 w->devinfo->function.audio.inamp_cap; 2034 } else 2035 w->param.inamp_cap = 0; 2036 2037 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2038 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2039 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2040 cap = hdac_command(sc, 2041 HDA_CMD_GET_PARAMETER(cad, nid, 2042 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2043 w->param.supp_stream_formats = (cap != 0) ? cap : 2044 w->devinfo->function.audio.supp_stream_formats; 2045 cap = hdac_command(sc, 2046 HDA_CMD_GET_PARAMETER(cad, nid, 2047 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2048 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2049 w->devinfo->function.audio.supp_pcm_size_rate; 2050 } else { 2051 w->param.supp_stream_formats = 2052 w->devinfo->function.audio.supp_stream_formats; 2053 w->param.supp_pcm_size_rate = 2054 w->devinfo->function.audio.supp_pcm_size_rate; 2055 } 2056 } else { 2057 w->param.supp_stream_formats = 0; 2058 w->param.supp_pcm_size_rate = 0; 2059 } 2060 2061 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2062 hdac_widget_pin_parse(w); 2063} 2064 2065static struct hdac_widget * 2066hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2067{ 2068 if (devinfo == NULL || devinfo->widget == NULL || 2069 nid < devinfo->startnode || nid >= devinfo->endnode) 2070 return (NULL); 2071 return (&devinfo->widget[nid - devinfo->startnode]); 2072} 2073 2074static __inline int 2075hda_poll_channel(struct hdac_chan *ch) 2076{ 2077 uint32_t sz, delta; 2078 volatile uint32_t ptr; 2079 2080 if (ch->active == 0) 2081 return (0); 2082 2083 sz = ch->blksz * ch->blkcnt; 2084 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2085 ch->ptr = ptr; 2086 ptr %= sz; 2087 ptr &= ~(ch->blksz - 1); 2088 delta = (sz + ptr - ch->prevptr) % sz; 2089 2090 if (delta < ch->blksz) 2091 return (0); 2092 2093 ch->prevptr = ptr; 2094 2095 return (1); 2096} 2097 2098#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2099 2100static void 2101hda_poll_callback(void *arg) 2102{ 2103 struct hdac_softc *sc = arg; 2104 uint32_t trigger = 0; 2105 2106 if (sc == NULL) 2107 return; 2108 2109 hdac_lock(sc); 2110 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2111 hdac_unlock(sc); 2112 return; 2113 } 2114 2115 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2116 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2117 2118 /* XXX */ 2119 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2120 hda_poll_callback, sc); 2121 2122 hdac_unlock(sc); 2123 2124 if (trigger & 1) 2125 chn_intr(sc->play.c); 2126 if (trigger & 2) 2127 chn_intr(sc->rec.c); 2128} 2129 2130static int 2131hdac_rirb_flush(struct hdac_softc *sc) 2132{ 2133 struct hdac_rirb *rirb_base, *rirb; 2134 struct hdac_codec *codec; 2135 struct hdac_command_list *commands; 2136 nid_t cad; 2137 uint32_t resp; 2138 uint8_t rirbwp; 2139 int ret = 0; 2140 2141 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2142 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2143 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2144 BUS_DMASYNC_POSTREAD); 2145 2146 while (sc->rirb_rp != rirbwp) { 2147 sc->rirb_rp++; 2148 sc->rirb_rp %= sc->rirb_size; 2149 rirb = &rirb_base[sc->rirb_rp]; 2150 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2151 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2152 sc->codecs[cad] == NULL) 2153 continue; 2154 resp = rirb->response; 2155 codec = sc->codecs[cad]; 2156 commands = codec->commands; 2157 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2158 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2159 ((resp >> 26) & 0xffff); 2160 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2161 } else if (commands != NULL && commands->num_commands > 0 && 2162 codec->responses_received < commands->num_commands) 2163 commands->responses[codec->responses_received++] = 2164 resp; 2165 ret++; 2166 } 2167 2168 return (ret); 2169} 2170 2171static int 2172hdac_unsolq_flush(struct hdac_softc *sc) 2173{ 2174 nid_t cad; 2175 uint32_t tag; 2176 int ret = 0; 2177 2178 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2179 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2180 while (sc->unsolq_rp != sc->unsolq_wp) { 2181 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2182 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2183 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2184 hdac_unsolicited_handler(sc->codecs[cad], tag); 2185 ret++; 2186 } 2187 sc->unsolq_st = HDAC_UNSOLQ_READY; 2188 } 2189 2190 return (ret); 2191} 2192 2193static void 2194hdac_poll_callback(void *arg) 2195{ 2196 struct hdac_softc *sc = arg; 2197 if (sc == NULL) 2198 return; 2199 2200 hdac_lock(sc); 2201 if (sc->polling == 0) { 2202 hdac_unlock(sc); 2203 return; 2204 } 2205 hdac_rirb_flush(sc); 2206 hdac_unsolq_flush(sc); 2207 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2208 hdac_poll_callback, sc); 2209 hdac_unlock(sc); 2210} 2211 2212static void 2213hdac_stream_stop(struct hdac_chan *ch) 2214{ 2215 struct hdac_softc *sc = ch->devinfo->codec->sc; 2216 uint32_t ctl; 2217 2218 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2219 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2220 HDAC_SDCTL_RUN); 2221 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2222 2223 ch->active = 0; 2224 2225 if (sc->polling != 0) { 2226 int pollticks; 2227 2228 if (hda_chan_active(sc) == 0) { 2229 callout_stop(&sc->poll_hda); 2230 sc->poll_ticks = 1; 2231 } else { 2232 if (sc->play.active != 0) 2233 ch = &sc->play; 2234 else 2235 ch = &sc->rec; 2236 pollticks = ((uint64_t)hz * ch->blksz) / 2237 ((uint64_t)sndbuf_getbps(ch->b) * 2238 sndbuf_getspd(ch->b)); 2239 pollticks >>= 2; 2240 if (pollticks > hz) 2241 pollticks = hz; 2242 if (pollticks < 1) { 2243 HDA_BOOTVERBOSE( 2244 device_printf(sc->dev, 2245 "%s: pollticks=%d < 1 !\n", 2246 __func__, pollticks); 2247 ); 2248 pollticks = 1; 2249 } 2250 if (pollticks > sc->poll_ticks) { 2251 HDA_BOOTVERBOSE( 2252 device_printf(sc->dev, 2253 "%s: pollticks %d -> %d\n", 2254 __func__, sc->poll_ticks, 2255 pollticks); 2256 ); 2257 sc->poll_ticks = pollticks; 2258 callout_reset(&sc->poll_hda, 1, 2259 hda_poll_callback, sc); 2260 } 2261 } 2262 } else { 2263 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2264 ctl &= ~(1 << (ch->off >> 5)); 2265 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2266 } 2267} 2268 2269static void 2270hdac_stream_start(struct hdac_chan *ch) 2271{ 2272 struct hdac_softc *sc = ch->devinfo->codec->sc; 2273 uint32_t ctl; 2274 2275 if (sc->polling != 0) { 2276 int pollticks; 2277 2278 pollticks = ((uint64_t)hz * ch->blksz) / 2279 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2280 pollticks >>= 2; 2281 if (pollticks > hz) 2282 pollticks = hz; 2283 if (pollticks < 1) { 2284 HDA_BOOTVERBOSE( 2285 device_printf(sc->dev, 2286 "%s: pollticks=%d < 1 !\n", 2287 __func__, pollticks); 2288 ); 2289 pollticks = 1; 2290 } 2291 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2292 HDA_BOOTVERBOSE( 2293 if (hda_chan_active(sc) == 0) { 2294 device_printf(sc->dev, 2295 "%s: pollticks=%d\n", 2296 __func__, pollticks); 2297 } else { 2298 device_printf(sc->dev, 2299 "%s: pollticks %d -> %d\n", 2300 __func__, sc->poll_ticks, 2301 pollticks); 2302 } 2303 ); 2304 sc->poll_ticks = pollticks; 2305 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2306 sc); 2307 } 2308 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2309 ctl |= HDAC_SDCTL_RUN; 2310 } else { 2311 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2312 ctl |= 1 << (ch->off >> 5); 2313 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2314 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2315 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2316 HDAC_SDCTL_RUN; 2317 } 2318 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2319 2320 ch->active = 1; 2321} 2322 2323static void 2324hdac_stream_reset(struct hdac_chan *ch) 2325{ 2326 struct hdac_softc *sc = ch->devinfo->codec->sc; 2327 int timeout = 1000; 2328 int to = timeout; 2329 uint32_t ctl; 2330 2331 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2332 ctl |= HDAC_SDCTL_SRST; 2333 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2334 do { 2335 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2336 if (ctl & HDAC_SDCTL_SRST) 2337 break; 2338 DELAY(10); 2339 } while (--to); 2340 if (!(ctl & HDAC_SDCTL_SRST)) { 2341 device_printf(sc->dev, "timeout in reset\n"); 2342 } 2343 ctl &= ~HDAC_SDCTL_SRST; 2344 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2345 to = timeout; 2346 do { 2347 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2348 if (!(ctl & HDAC_SDCTL_SRST)) 2349 break; 2350 DELAY(10); 2351 } while (--to); 2352 if (ctl & HDAC_SDCTL_SRST) 2353 device_printf(sc->dev, "can't reset!\n"); 2354} 2355 2356static void 2357hdac_stream_setid(struct hdac_chan *ch) 2358{ 2359 struct hdac_softc *sc = ch->devinfo->codec->sc; 2360 uint32_t ctl; 2361 2362 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2363 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2364 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2365 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2366} 2367 2368static void 2369hdac_bdl_setup(struct hdac_chan *ch) 2370{ 2371 struct hdac_softc *sc = ch->devinfo->codec->sc; 2372 struct hdac_bdle *bdle; 2373 uint64_t addr; 2374 uint32_t blksz, blkcnt; 2375 int i; 2376 2377 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2378 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2379 2380 if (sc->polling != 0) { 2381 blksz = ch->blksz * ch->blkcnt; 2382 blkcnt = 1; 2383 } else { 2384 blksz = ch->blksz; 2385 blkcnt = ch->blkcnt; 2386 } 2387 2388 for (i = 0; i < blkcnt; i++, bdle++) { 2389 bdle->addrl = (uint32_t)addr; 2390 bdle->addrh = (uint32_t)(addr >> 32); 2391 bdle->len = blksz; 2392 bdle->ioc = 1 ^ sc->polling; 2393 addr += blksz; 2394 } 2395 2396 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2397 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2398 addr = ch->bdl_dma.dma_paddr; 2399 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2400 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2401} 2402 2403static int 2404hdac_bdl_alloc(struct hdac_chan *ch) 2405{ 2406 struct hdac_softc *sc = ch->devinfo->codec->sc; 2407 int rc; 2408 2409 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2410 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2411 if (rc) { 2412 device_printf(sc->dev, "can't alloc bdl\n"); 2413 return (rc); 2414 } 2415 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2416 2417 return (0); 2418} 2419 2420static void 2421hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2422 int index, int lmute, int rmute, 2423 int left, int right, int dir) 2424{ 2425 uint16_t v = 0; 2426 2427 if (sc == NULL) 2428 return; 2429 2430 if (left != right || lmute != rmute) { 2431 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2432 (lmute << 7) | left; 2433 hdac_command(sc, 2434 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2435 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2436 (rmute << 7) | right; 2437 } else 2438 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2439 (lmute << 7) | left; 2440 2441 hdac_command(sc, 2442 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2443} 2444 2445static void 2446hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2447 int left, int right) 2448{ 2449 struct hdac_softc *sc; 2450 nid_t nid, cad; 2451 int lmute, rmute; 2452 2453 if (ctl == NULL || ctl->widget == NULL || 2454 ctl->widget->devinfo == NULL || 2455 ctl->widget->devinfo->codec == NULL || 2456 ctl->widget->devinfo->codec->sc == NULL) 2457 return; 2458 2459 sc = ctl->widget->devinfo->codec->sc; 2460 cad = ctl->widget->devinfo->codec->cad; 2461 nid = ctl->widget->nid; 2462 2463 if (mute == HDA_AMP_MUTE_DEFAULT) { 2464 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2465 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2466 } else { 2467 lmute = HDA_AMP_LEFT_MUTED(mute); 2468 rmute = HDA_AMP_RIGHT_MUTED(mute); 2469 } 2470 2471 if (ctl->dir & HDA_CTL_OUT) 2472 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2473 lmute, rmute, left, right, 0); 2474 if (ctl->dir & HDA_CTL_IN) 2475 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2476 lmute, rmute, left, right, 1); 2477 ctl->left = left; 2478 ctl->right = right; 2479} 2480 2481static void 2482hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2483{ 2484 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2485 return; 2486 hdac_command(w->devinfo->codec->sc, 2487 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2488 w->nid, index), w->devinfo->codec->cad); 2489 w->selconn = index; 2490} 2491 2492 2493/**************************************************************************** 2494 * uint32_t hdac_command_sendone_internal 2495 * 2496 * Wrapper function that sends only one command to a given codec 2497 ****************************************************************************/ 2498static uint32_t 2499hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2500{ 2501 struct hdac_command_list cl; 2502 uint32_t response = HDAC_INVALID; 2503 2504 if (!hdac_lockowned(sc)) 2505 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2506 cl.num_commands = 1; 2507 cl.verbs = &verb; 2508 cl.responses = &response; 2509 2510 hdac_command_send_internal(sc, &cl, cad); 2511 2512 return (response); 2513} 2514 2515/**************************************************************************** 2516 * hdac_command_send_internal 2517 * 2518 * Send a command list to the codec via the corb. We queue as much verbs as 2519 * we can and msleep on the codec. When the interrupt get the responses 2520 * back from the rirb, it will wake us up so we can queue the remaining verbs 2521 * if any. 2522 ****************************************************************************/ 2523static void 2524hdac_command_send_internal(struct hdac_softc *sc, 2525 struct hdac_command_list *commands, nid_t cad) 2526{ 2527 struct hdac_codec *codec; 2528 int corbrp; 2529 uint32_t *corb; 2530 int timeout; 2531 int retry = 10; 2532 struct hdac_rirb *rirb_base; 2533 2534 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2535 commands->num_commands < 1) 2536 return; 2537 2538 codec = sc->codecs[cad]; 2539 codec->commands = commands; 2540 codec->responses_received = 0; 2541 codec->verbs_sent = 0; 2542 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2543 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2544 2545 do { 2546 if (codec->verbs_sent != commands->num_commands) { 2547 /* Queue as many verbs as possible */ 2548 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2549 bus_dmamap_sync(sc->corb_dma.dma_tag, 2550 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2551 while (codec->verbs_sent != commands->num_commands && 2552 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2553 sc->corb_wp++; 2554 sc->corb_wp %= sc->corb_size; 2555 corb[sc->corb_wp] = 2556 commands->verbs[codec->verbs_sent++]; 2557 } 2558 2559 /* Send the verbs to the codecs */ 2560 bus_dmamap_sync(sc->corb_dma.dma_tag, 2561 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2562 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2563 } 2564 2565 timeout = 1000; 2566 while (hdac_rirb_flush(sc) == 0 && --timeout) 2567 DELAY(10); 2568 } while ((codec->verbs_sent != commands->num_commands || 2569 codec->responses_received != commands->num_commands) && --retry); 2570 2571 if (retry == 0) 2572 device_printf(sc->dev, 2573 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2574 __func__, commands->num_commands, codec->verbs_sent, 2575 codec->responses_received); 2576 2577 codec->commands = NULL; 2578 codec->responses_received = 0; 2579 codec->verbs_sent = 0; 2580 2581 hdac_unsolq_flush(sc); 2582} 2583 2584 2585/**************************************************************************** 2586 * Device Methods 2587 ****************************************************************************/ 2588 2589/**************************************************************************** 2590 * int hdac_probe(device_t) 2591 * 2592 * Probe for the presence of an hdac. If none is found, check for a generic 2593 * match using the subclass of the device. 2594 ****************************************************************************/ 2595static int 2596hdac_probe(device_t dev) 2597{ 2598 int i, result; 2599 uint32_t model; 2600 uint16_t class, subclass; 2601 char desc[64]; 2602 2603 model = (uint32_t)pci_get_device(dev) << 16; 2604 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2605 class = pci_get_class(dev); 2606 subclass = pci_get_subclass(dev); 2607 2608 bzero(desc, sizeof(desc)); 2609 result = ENXIO; 2610 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2611 if (hdac_devices[i].model == model) { 2612 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2613 result = BUS_PROBE_DEFAULT; 2614 break; 2615 } 2616 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2617 class == PCIC_MULTIMEDIA && 2618 subclass == PCIS_MULTIMEDIA_HDA) { 2619 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2620 result = BUS_PROBE_GENERIC; 2621 break; 2622 } 2623 } 2624 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2625 subclass == PCIS_MULTIMEDIA_HDA) { 2626 strlcpy(desc, "Generic", sizeof(desc)); 2627 result = BUS_PROBE_GENERIC; 2628 } 2629 if (result != ENXIO) { 2630 strlcat(desc, " High Definition Audio Controller", 2631 sizeof(desc)); 2632 device_set_desc_copy(dev, desc); 2633 } 2634 2635 return (result); 2636} 2637 2638static void * 2639hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2640 struct pcm_channel *c, int dir) 2641{ 2642 struct hdac_devinfo *devinfo = data; 2643 struct hdac_softc *sc = devinfo->codec->sc; 2644 struct hdac_chan *ch; 2645 2646 hdac_lock(sc); 2647 if (dir == PCMDIR_PLAY) { 2648 ch = &sc->play; 2649 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2650 ch->dir = PCMDIR_PLAY; 2651 ch->sid = ++sc->streamcnt; 2652 devinfo->function.audio.playcnt++; 2653 } else { 2654 ch = &sc->rec; 2655 ch->off = devinfo->function.audio.reccnt << 5; 2656 ch->dir = PCMDIR_REC; 2657 ch->sid = ++sc->streamcnt; 2658 devinfo->function.audio.reccnt++; 2659 } 2660 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2661 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2662 ch->pcmrates[0] = 48000; 2663 ch->pcmrates[1] = 0; 2664 } 2665 ch->b = b; 2666 ch->c = c; 2667 ch->devinfo = devinfo; 2668 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2669 ch->blkcnt = sc->chan_blkcnt; 2670 hdac_unlock(sc); 2671 2672 if (hdac_bdl_alloc(ch) != 0) { 2673 ch->blkcnt = 0; 2674 return (NULL); 2675 } 2676 2677 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2678 return (NULL); 2679 2680 hdac_dma_nocache(ch->b->buf); 2681 2682 return (ch); 2683} 2684 2685static int 2686hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2687{ 2688 struct hdac_chan *ch = data; 2689 int i; 2690 2691 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2692 if (format == ch->caps.fmtlist[i]) { 2693 ch->fmt = format; 2694 return (0); 2695 } 2696 } 2697 2698 return (EINVAL); 2699} 2700 2701static int 2702hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2703{ 2704 struct hdac_chan *ch = data; 2705 uint32_t spd = 0, threshold; 2706 int i; 2707 2708 for (i = 0; ch->pcmrates[i] != 0; i++) { 2709 spd = ch->pcmrates[i]; 2710 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2711 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2712 if (speed < threshold) 2713 break; 2714 } 2715 2716 if (spd == 0) /* impossible */ 2717 ch->spd = 48000; 2718 else 2719 ch->spd = spd; 2720 2721 return (ch->spd); 2722} 2723 2724static void 2725hdac_stream_setup(struct hdac_chan *ch) 2726{ 2727 struct hdac_softc *sc = ch->devinfo->codec->sc; 2728 int i; 2729 nid_t cad = ch->devinfo->codec->cad; 2730 uint16_t fmt; 2731 2732 fmt = 0; 2733 if (ch->fmt & AFMT_S16_LE) 2734 fmt |= ch->bit16 << 4; 2735 else if (ch->fmt & AFMT_S32_LE) 2736 fmt |= ch->bit32 << 4; 2737 else 2738 fmt |= 1 << 4; 2739 2740 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2741 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2742 fmt |= hda_rate_tab[i].base; 2743 fmt |= hda_rate_tab[i].mul; 2744 fmt |= hda_rate_tab[i].div; 2745 break; 2746 } 2747 } 2748 2749 if (ch->fmt & AFMT_STEREO) 2750 fmt |= 1; 2751 2752 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2753 2754 for (i = 0; ch->io[i] != -1; i++) { 2755 HDA_BOOTVERBOSE( 2756 device_printf(sc->dev, 2757 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2758 "fmt=0x%08x\n", 2759 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2760 ch->io[i], fmt); 2761 ); 2762 hdac_command(sc, 2763 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2764 hdac_command(sc, 2765 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2766 ch->sid << 4), cad); 2767 } 2768} 2769 2770static int 2771hdac_channel_setfragments(kobj_t obj, void *data, 2772 uint32_t blksz, uint32_t blkcnt) 2773{ 2774 struct hdac_chan *ch = data; 2775 struct hdac_softc *sc = ch->devinfo->codec->sc; 2776 2777 blksz &= HDA_BLK_ALIGN; 2778 2779 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 2780 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 2781 if (blksz < HDA_BLK_MIN) 2782 blksz = HDA_BLK_MIN; 2783 if (blkcnt > HDA_BDL_MAX) 2784 blkcnt = HDA_BDL_MAX; 2785 if (blkcnt < HDA_BDL_MIN) 2786 blkcnt = HDA_BDL_MIN; 2787 2788 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 2789 if ((blkcnt >> 1) >= HDA_BDL_MIN) 2790 blkcnt >>= 1; 2791 else if ((blksz >> 1) >= HDA_BLK_MIN) 2792 blksz >>= 1; 2793 else 2794 break; 2795 } 2796 2797 if ((sndbuf_getblksz(ch->b) != blksz || 2798 sndbuf_getblkcnt(ch->b) != blkcnt) && 2799 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 2800 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2801 __func__, blksz, blkcnt); 2802 2803 ch->blksz = sndbuf_getblksz(ch->b); 2804 ch->blkcnt = sndbuf_getblkcnt(ch->b); 2805 2806 return (1); 2807} 2808 2809static int 2810hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2811{ 2812 struct hdac_chan *ch = data; 2813 struct hdac_softc *sc = ch->devinfo->codec->sc; 2814 2815 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt); 2816 2817 return (ch->blksz); 2818} 2819 2820static void 2821hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2822{ 2823 struct hdac_devinfo *devinfo = ch->devinfo; 2824 nid_t cad = devinfo->codec->cad; 2825 int i; 2826 2827 hdac_stream_stop(ch); 2828 2829 for (i = 0; ch->io[i] != -1; i++) { 2830 hdac_command(sc, 2831 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2832 0), cad); 2833 } 2834} 2835 2836static void 2837hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2838{ 2839 ch->ptr = 0; 2840 ch->prevptr = 0; 2841 hdac_stream_stop(ch); 2842 hdac_stream_reset(ch); 2843 hdac_bdl_setup(ch); 2844 hdac_stream_setid(ch); 2845 hdac_stream_setup(ch); 2846 hdac_stream_start(ch); 2847} 2848 2849static int 2850hdac_channel_trigger(kobj_t obj, void *data, int go) 2851{ 2852 struct hdac_chan *ch = data; 2853 struct hdac_softc *sc = ch->devinfo->codec->sc; 2854 2855 hdac_lock(sc); 2856 switch (go) { 2857 case PCMTRIG_START: 2858 hdac_channel_start(sc, ch); 2859 break; 2860 case PCMTRIG_STOP: 2861 case PCMTRIG_ABORT: 2862 hdac_channel_stop(sc, ch); 2863 break; 2864 default: 2865 break; 2866 } 2867 hdac_unlock(sc); 2868 2869 return (0); 2870} 2871 2872static int 2873hdac_channel_getptr(kobj_t obj, void *data) 2874{ 2875 struct hdac_chan *ch = data; 2876 struct hdac_softc *sc = ch->devinfo->codec->sc; 2877 uint32_t ptr; 2878 2879 hdac_lock(sc); 2880 if (sc->polling != 0) 2881 ptr = ch->ptr; 2882 else 2883 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2884 hdac_unlock(sc); 2885 2886 /* 2887 * Round to available space and force 128 bytes aligment. 2888 */ 2889 ptr %= ch->blksz * ch->blkcnt; 2890 ptr &= HDA_BLK_ALIGN; 2891 2892 return (ptr); 2893} 2894 2895static struct pcmchan_caps * 2896hdac_channel_getcaps(kobj_t obj, void *data) 2897{ 2898 return (&((struct hdac_chan *)data)->caps); 2899} 2900 2901static kobj_method_t hdac_channel_methods[] = { 2902 KOBJMETHOD(channel_init, hdac_channel_init), 2903 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2904 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2905 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2906 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 2907 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2908 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2909 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2910 { 0, 0 } 2911}; 2912CHANNEL_DECLARE(hdac_channel); 2913 2914static int 2915hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2916{ 2917 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2918 struct hdac_softc *sc = devinfo->codec->sc; 2919 struct hdac_widget *w, *cw; 2920 struct hdac_audio_ctl *ctl; 2921 uint32_t mask, recmask, id; 2922 int i, j, softpcmvol; 2923 nid_t cad; 2924 2925 hdac_lock(sc); 2926 2927 mask = 0; 2928 recmask = 0; 2929 2930 id = hdac_codec_id(devinfo); 2931 cad = devinfo->codec->cad; 2932 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2933 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2934 sc->pci_subvendor) && 2935 hdac_hp_switch[i].id == id)) 2936 continue; 2937 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2938 if (w != NULL && w->enable != 0 2939 && w->type == 2940 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2941 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2942 hdac_command(sc, 2943 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2944 w->nid, 2945 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2946 HDAC_UNSOLTAG_EVENT_HP), cad); 2947 hdac_hp_switch_handler(devinfo); 2948 HDA_BOOTVERBOSE( 2949 device_printf(sc->dev, 2950 "HDA_DEBUG: Enabling headphone/speaker " 2951 "audio routing switching:\n"); 2952 device_printf(sc->dev, 2953 "HDA_DEBUG: \tindex=%d nid=%d " 2954 "pci_subvendor=0x%08x " 2955 "codec=0x%08x\n", 2956 i, w->nid, sc->pci_subvendor, id); 2957 ); 2958 } 2959 break; 2960 } 2961 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2962 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2963 sc->pci_subvendor) && 2964 hdac_eapd_switch[i].id == id)) 2965 continue; 2966 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2967 if (w == NULL || w->enable == 0) 2968 break; 2969 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2970 w->param.eapdbtl == HDAC_INVALID) 2971 break; 2972 mask |= SOUND_MASK_OGAIN; 2973 break; 2974 } 2975 2976 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2977 w = hdac_widget_get(devinfo, i); 2978 if (w == NULL || w->enable == 0) 2979 continue; 2980 mask |= w->ctlflags; 2981 if (!(w->pflags & HDA_ADC_RECSEL)) 2982 continue; 2983 for (j = 0; j < w->nconns; j++) { 2984 cw = hdac_widget_get(devinfo, w->conns[j]); 2985 if (cw == NULL || cw->enable == 0) 2986 continue; 2987 recmask |= cw->ctlflags; 2988 } 2989 } 2990 2991 if (!(mask & SOUND_MASK_PCM)) { 2992 softpcmvol = 1; 2993 mask |= SOUND_MASK_PCM; 2994 } else 2995 softpcmvol = (devinfo->function.audio.quirks & 2996 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2997 2998 i = 0; 2999 ctl = NULL; 3000 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3001 if (ctl->widget == NULL || ctl->enable == 0) 3002 continue; 3003 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3004 continue; 3005 if (ctl->step > 0) 3006 break; 3007 } 3008 3009 if (softpcmvol == 1 || ctl == NULL) { 3010 struct snddev_info *d = NULL; 3011 d = device_get_softc(sc->dev); 3012 if (d != NULL) { 3013 d->flags |= SD_F_SOFTPCMVOL; 3014 HDA_BOOTVERBOSE( 3015 device_printf(sc->dev, 3016 "HDA_DEBUG: %s Soft PCM volume\n", 3017 (softpcmvol == 1) ? 3018 "Forcing" : "Enabling"); 3019 ); 3020 } 3021 i = 0; 3022 /* 3023 * XXX Temporary quirk for STAC9220, until the parser 3024 * become smarter. 3025 */ 3026 if (id == HDA_CODEC_STAC9220) { 3027 mask |= SOUND_MASK_VOLUME; 3028 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3029 NULL) { 3030 if (ctl->widget == NULL || ctl->enable == 0) 3031 continue; 3032 if (ctl->widget->nid == 11 && ctl->index == 0) { 3033 ctl->ossmask = SOUND_MASK_VOLUME; 3034 ctl->ossval = 100 | (100 << 8); 3035 } else 3036 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3037 } 3038 } else if (id == HDA_CODEC_STAC9221) { 3039 mask |= SOUND_MASK_VOLUME; 3040 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3041 NULL) { 3042 if (ctl->widget == NULL) 3043 continue; 3044 if (ctl->widget->nid == 2 && ctl->index == 0) { 3045 ctl->enable = 1; 3046 ctl->ossmask = SOUND_MASK_VOLUME; 3047 ctl->ossval = 100 | (100 << 8); 3048 } else if (ctl->enable == 0) 3049 continue; 3050 else 3051 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3052 } 3053 } else { 3054 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3055 SOUND_MASK_PCM); 3056 if (!(mask & SOUND_MASK_VOLUME)) 3057 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3058 SOUND_MIXER_NONE); 3059 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3060 NULL) { 3061 if (ctl->widget == NULL || ctl->enable == 0) 3062 continue; 3063 if (!HDA_FLAG_MATCH(ctl->ossmask, 3064 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3065 continue; 3066 if (!(ctl->mute == 1 && ctl->step == 0)) 3067 ctl->enable = 0; 3068 } 3069 } 3070 } 3071 3072 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 3073 3074 mix_setrecdevs(m, recmask); 3075 mix_setdevs(m, mask); 3076 3077 hdac_unlock(sc); 3078 3079 return (0); 3080} 3081 3082static int 3083hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3084 unsigned left, unsigned right) 3085{ 3086 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3087 struct hdac_softc *sc = devinfo->codec->sc; 3088 struct hdac_widget *w; 3089 struct hdac_audio_ctl *ctl; 3090 uint32_t id, mute; 3091 int lvol, rvol, mlvol, mrvol; 3092 int i = 0; 3093 3094 hdac_lock(sc); 3095 if (dev == SOUND_MIXER_OGAIN) { 3096 uint32_t orig; 3097 /*if (left != right || !(left == 0 || left == 1)) { 3098 hdac_unlock(sc); 3099 return (-1); 3100 }*/ 3101 id = hdac_codec_id(devinfo); 3102 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3103 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3104 sc->pci_subvendor) && 3105 hdac_eapd_switch[i].id == id) 3106 break; 3107 } 3108 if (i >= HDAC_EAPD_SWITCH_LEN) { 3109 hdac_unlock(sc); 3110 return (-1); 3111 } 3112 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3113 if (w == NULL || 3114 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3115 w->param.eapdbtl == HDAC_INVALID) { 3116 hdac_unlock(sc); 3117 return (-1); 3118 } 3119 orig = w->param.eapdbtl; 3120 if (left == 0) 3121 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3122 else 3123 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3124 if (orig != w->param.eapdbtl) { 3125 uint32_t val; 3126 3127 if (hdac_eapd_switch[i].hp_switch != 0) 3128 hdac_hp_switch_handler(devinfo); 3129 val = w->param.eapdbtl; 3130 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3131 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3132 hdac_command(sc, 3133 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3134 w->nid, val), devinfo->codec->cad); 3135 } 3136 hdac_unlock(sc); 3137 return (left | (left << 8)); 3138 } 3139 if (dev == SOUND_MIXER_VOLUME) 3140 devinfo->function.audio.mvol = left | (right << 8); 3141 3142 mlvol = devinfo->function.audio.mvol & 0x7f; 3143 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3144 lvol = 0; 3145 rvol = 0; 3146 3147 i = 0; 3148 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3149 if (ctl->widget == NULL || ctl->enable == 0 || 3150 !(ctl->ossmask & (1 << dev))) 3151 continue; 3152 switch (dev) { 3153 case SOUND_MIXER_VOLUME: 3154 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3155 lvol = (lvol * ctl->step) / 100; 3156 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3157 rvol = (rvol * ctl->step) / 100; 3158 break; 3159 default: 3160 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3161 lvol = (left * mlvol) / 100; 3162 lvol = (lvol * ctl->step) / 100; 3163 rvol = (right * mrvol) / 100; 3164 rvol = (rvol * ctl->step) / 100; 3165 } else { 3166 lvol = (left * ctl->step) / 100; 3167 rvol = (right * ctl->step) / 100; 3168 } 3169 ctl->ossval = left | (right << 8); 3170 break; 3171 } 3172 mute = 0; 3173 if (ctl->step < 1) { 3174 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3175 (ctl->muted & HDA_AMP_MUTE_LEFT); 3176 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3177 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3178 } else { 3179 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3180 (ctl->muted & HDA_AMP_MUTE_LEFT); 3181 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3182 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3183 } 3184 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3185 } 3186 hdac_unlock(sc); 3187 3188 return (left | (right << 8)); 3189} 3190 3191static int 3192hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3193{ 3194 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3195 struct hdac_widget *w, *cw; 3196 struct hdac_softc *sc = devinfo->codec->sc; 3197 uint32_t ret = src, target; 3198 int i, j; 3199 3200 target = 0; 3201 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3202 if (src & (1 << i)) { 3203 target = 1 << i; 3204 break; 3205 } 3206 } 3207 3208 hdac_lock(sc); 3209 3210 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3211 w = hdac_widget_get(devinfo, i); 3212 if (w == NULL || w->enable == 0) 3213 continue; 3214 if (!(w->pflags & HDA_ADC_RECSEL)) 3215 continue; 3216 for (j = 0; j < w->nconns; j++) { 3217 cw = hdac_widget_get(devinfo, w->conns[j]); 3218 if (cw == NULL || cw->enable == 0) 3219 continue; 3220 if ((target == SOUND_MASK_VOLUME && 3221 cw->type != 3222 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3223 (target != SOUND_MASK_VOLUME && 3224 cw->type == 3225 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3226 continue; 3227 if (cw->ctlflags & target) { 3228 hdac_widget_connection_select(w, j); 3229 ret = target; 3230 j += w->nconns; 3231 } 3232 } 3233 } 3234 3235 hdac_unlock(sc); 3236 3237 return (ret); 3238} 3239 3240static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3241 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3242 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3243 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3244 { 0, 0 } 3245}; 3246MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3247 3248/**************************************************************************** 3249 * int hdac_attach(device_t) 3250 * 3251 * Attach the device into the kernel. Interrupts usually won't be enabled 3252 * when this function is called. Setup everything that doesn't require 3253 * interrupts and defer probing of codecs until interrupts are enabled. 3254 ****************************************************************************/ 3255static int 3256hdac_attach(device_t dev) 3257{ 3258 struct hdac_softc *sc; 3259 int result; 3260 int i = 0; 3261 3262 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3263 if (sc == NULL) { 3264 device_printf(dev, "cannot allocate softc\n"); 3265 return (ENOMEM); 3266 } 3267 3268 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3269 sc->dev = dev; 3270 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3271 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3272 3273 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3274 /* Screw nx6325 - subdevice/subvendor swapped */ 3275 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3276 } 3277 3278 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3279 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3280 3281 sc->poll_ticks = 1; 3282 if (resource_int_value(device_get_name(sc->dev), 3283 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3284 sc->polling = 1; 3285 else 3286 sc->polling = 0; 3287 3288 sc->chan_size = pcm_getbuffersize(dev, 3289 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3290 3291 if (resource_int_value(device_get_name(sc->dev), 3292 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3293 i &= HDA_BLK_ALIGN; 3294 if (i < HDA_BLK_MIN) 3295 i = HDA_BLK_MIN; 3296 sc->chan_blkcnt = sc->chan_size / i; 3297 i = 0; 3298 while (sc->chan_blkcnt >> i) 3299 i++; 3300 sc->chan_blkcnt = 1 << (i - 1); 3301 if (sc->chan_blkcnt < HDA_BDL_MIN) 3302 sc->chan_blkcnt = HDA_BDL_MIN; 3303 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3304 sc->chan_blkcnt = HDA_BDL_MAX; 3305 } else 3306 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3307 3308 result = bus_dma_tag_create(NULL, /* parent */ 3309 HDAC_DMA_ALIGNMENT, /* alignment */ 3310 0, /* boundary */ 3311 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3312 BUS_SPACE_MAXADDR, /* highaddr */ 3313 NULL, /* filtfunc */ 3314 NULL, /* fistfuncarg */ 3315 sc->chan_size, /* maxsize */ 3316 1, /* nsegments */ 3317 sc->chan_size, /* maxsegsz */ 3318 0, /* flags */ 3319 NULL, /* lockfunc */ 3320 NULL, /* lockfuncarg */ 3321 &sc->chan_dmat); /* dmat */ 3322 if (result != 0) { 3323 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3324 __func__, result); 3325 snd_mtxfree(sc->lock); 3326 free(sc, M_DEVBUF); 3327 return (ENXIO); 3328 } 3329 3330 3331 sc->hdabus = NULL; 3332 for (i = 0; i < HDAC_CODEC_MAX; i++) 3333 sc->codecs[i] = NULL; 3334 3335 pci_enable_busmaster(dev); 3336 3337 /* Allocate resources */ 3338 result = hdac_mem_alloc(sc); 3339 if (result != 0) 3340 goto hdac_attach_fail; 3341 result = hdac_irq_alloc(sc); 3342 if (result != 0) 3343 goto hdac_attach_fail; 3344 3345 /* Get Capabilities */ 3346 result = hdac_get_capabilities(sc); 3347 if (result != 0) 3348 goto hdac_attach_fail; 3349 3350 /* Allocate CORB and RIRB dma memory */ 3351 result = hdac_dma_alloc(sc, &sc->corb_dma, 3352 sc->corb_size * sizeof(uint32_t)); 3353 if (result != 0) 3354 goto hdac_attach_fail; 3355 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3356 sc->rirb_size * sizeof(struct hdac_rirb)); 3357 if (result != 0) 3358 goto hdac_attach_fail; 3359 3360 /* Quiesce everything */ 3361 hdac_reset(sc); 3362 3363 /* Disable PCI-Express QOS */ 3364 pci_write_config(sc->dev, 0x44, 3365 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3366 3367 /* Initialize the CORB and RIRB */ 3368 hdac_corb_init(sc); 3369 hdac_rirb_init(sc); 3370 3371 /* Defer remaining of initialization until interrupts are enabled */ 3372 sc->intrhook.ich_func = hdac_attach2; 3373 sc->intrhook.ich_arg = (void *)sc; 3374 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3375 sc->intrhook.ich_func = NULL; 3376 hdac_attach2((void *)sc); 3377 } 3378 3379 return (0); 3380 3381hdac_attach_fail: 3382 hdac_dma_free(&sc->rirb_dma); 3383 hdac_dma_free(&sc->corb_dma); 3384 hdac_irq_free(sc); 3385 hdac_mem_free(sc); 3386 snd_mtxfree(sc->lock); 3387 free(sc, M_DEVBUF); 3388 3389 return (ENXIO); 3390} 3391 3392static void 3393hdac_audio_parse(struct hdac_devinfo *devinfo) 3394{ 3395 struct hdac_softc *sc = devinfo->codec->sc; 3396 struct hdac_widget *w; 3397 uint32_t res; 3398 int i; 3399 nid_t cad, nid; 3400 3401 cad = devinfo->codec->cad; 3402 nid = devinfo->nid; 3403 3404 hdac_command(sc, 3405 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3406 3407 DELAY(100); 3408 3409 res = hdac_command(sc, 3410 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3411 3412 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3413 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3414 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3415 3416 HDA_BOOTVERBOSE( 3417 device_printf(sc->dev, " Vendor: 0x%08x\n", 3418 devinfo->vendor_id); 3419 device_printf(sc->dev, " Device: 0x%08x\n", 3420 devinfo->device_id); 3421 device_printf(sc->dev, " Revision: 0x%08x\n", 3422 devinfo->revision_id); 3423 device_printf(sc->dev, " Stepping: 0x%08x\n", 3424 devinfo->stepping_id); 3425 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3426 sc->pci_subvendor); 3427 device_printf(sc->dev, " Nodes: start=%d " 3428 "endnode=%d total=%d\n", 3429 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3430 ); 3431 3432 res = hdac_command(sc, 3433 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3434 cad); 3435 devinfo->function.audio.supp_stream_formats = res; 3436 3437 res = hdac_command(sc, 3438 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3439 cad); 3440 devinfo->function.audio.supp_pcm_size_rate = res; 3441 3442 res = hdac_command(sc, 3443 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3444 cad); 3445 devinfo->function.audio.outamp_cap = res; 3446 3447 res = hdac_command(sc, 3448 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3449 cad); 3450 devinfo->function.audio.inamp_cap = res; 3451 3452 if (devinfo->nodecnt > 0) { 3453 hdac_unlock(sc); 3454 devinfo->widget = (struct hdac_widget *)malloc( 3455 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3456 M_NOWAIT | M_ZERO); 3457 hdac_lock(sc); 3458 } else 3459 devinfo->widget = NULL; 3460 3461 if (devinfo->widget == NULL) { 3462 device_printf(sc->dev, "unable to allocate widgets!\n"); 3463 devinfo->endnode = devinfo->startnode; 3464 devinfo->nodecnt = 0; 3465 return; 3466 } 3467 3468 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3469 w = hdac_widget_get(devinfo, i); 3470 if (w == NULL) 3471 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3472 else { 3473 w->devinfo = devinfo; 3474 w->nid = i; 3475 w->enable = 1; 3476 w->selconn = -1; 3477 w->pflags = 0; 3478 w->ctlflags = 0; 3479 w->param.eapdbtl = HDAC_INVALID; 3480 hdac_widget_parse(w); 3481 } 3482 } 3483} 3484 3485static void 3486hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3487{ 3488 struct hdac_softc *sc = devinfo->codec->sc; 3489 struct hdac_audio_ctl *ctls; 3490 struct hdac_widget *w, *cw; 3491 int i, j, cnt, max, ocap, icap; 3492 int mute, offset, step, size; 3493 3494 /* XXX This is redundant */ 3495 max = 0; 3496 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3497 w = hdac_widget_get(devinfo, i); 3498 if (w == NULL || w->enable == 0) 3499 continue; 3500 if (w->param.outamp_cap != 0) 3501 max++; 3502 if (w->param.inamp_cap != 0) { 3503 switch (w->type) { 3504 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3505 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3506 for (j = 0; j < w->nconns; j++) { 3507 cw = hdac_widget_get(devinfo, 3508 w->conns[j]); 3509 if (cw == NULL || cw->enable == 0) 3510 continue; 3511 max++; 3512 } 3513 break; 3514 default: 3515 max++; 3516 break; 3517 } 3518 } 3519 } 3520 3521 devinfo->function.audio.ctlcnt = max; 3522 3523 if (max < 1) 3524 return; 3525 3526 hdac_unlock(sc); 3527 ctls = (struct hdac_audio_ctl *)malloc( 3528 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3529 hdac_lock(sc); 3530 3531 if (ctls == NULL) { 3532 /* Blekh! */ 3533 device_printf(sc->dev, "unable to allocate ctls!\n"); 3534 devinfo->function.audio.ctlcnt = 0; 3535 return; 3536 } 3537 3538 cnt = 0; 3539 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3540 if (cnt >= max) { 3541 device_printf(sc->dev, "%s: Ctl overflow!\n", 3542 __func__); 3543 break; 3544 } 3545 w = hdac_widget_get(devinfo, i); 3546 if (w == NULL || w->enable == 0) 3547 continue; 3548 ocap = w->param.outamp_cap; 3549 icap = w->param.inamp_cap; 3550 if (ocap != 0) { 3551 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3552 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3553 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3554 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3555 /*if (offset > step) { 3556 HDA_BOOTVERBOSE( 3557 device_printf(sc->dev, 3558 "HDA_DEBUG: BUGGY outamp: nid=%d " 3559 "[offset=%d > step=%d]\n", 3560 w->nid, offset, step); 3561 ); 3562 offset = step; 3563 }*/ 3564 ctls[cnt].enable = 1; 3565 ctls[cnt].widget = w; 3566 ctls[cnt].mute = mute; 3567 ctls[cnt].step = step; 3568 ctls[cnt].size = size; 3569 ctls[cnt].offset = offset; 3570 ctls[cnt].left = offset; 3571 ctls[cnt].right = offset; 3572 ctls[cnt++].dir = HDA_CTL_OUT; 3573 } 3574 3575 if (icap != 0) { 3576 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3577 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3578 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3579 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3580 /*if (offset > step) { 3581 HDA_BOOTVERBOSE( 3582 device_printf(sc->dev, 3583 "HDA_DEBUG: BUGGY inamp: nid=%d " 3584 "[offset=%d > step=%d]\n", 3585 w->nid, offset, step); 3586 ); 3587 offset = step; 3588 }*/ 3589 switch (w->type) { 3590 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3591 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3592 for (j = 0; j < w->nconns; j++) { 3593 if (cnt >= max) { 3594 device_printf(sc->dev, 3595 "%s: Ctl overflow!\n", 3596 __func__); 3597 break; 3598 } 3599 cw = hdac_widget_get(devinfo, 3600 w->conns[j]); 3601 if (cw == NULL || cw->enable == 0) 3602 continue; 3603 ctls[cnt].enable = 1; 3604 ctls[cnt].widget = w; 3605 ctls[cnt].childwidget = cw; 3606 ctls[cnt].index = j; 3607 ctls[cnt].mute = mute; 3608 ctls[cnt].step = step; 3609 ctls[cnt].size = size; 3610 ctls[cnt].offset = offset; 3611 ctls[cnt].left = offset; 3612 ctls[cnt].right = offset; 3613 ctls[cnt++].dir = HDA_CTL_IN; 3614 } 3615 break; 3616 default: 3617 if (cnt >= max) { 3618 device_printf(sc->dev, 3619 "%s: Ctl overflow!\n", 3620 __func__); 3621 break; 3622 } 3623 ctls[cnt].enable = 1; 3624 ctls[cnt].widget = w; 3625 ctls[cnt].mute = mute; 3626 ctls[cnt].step = step; 3627 ctls[cnt].size = size; 3628 ctls[cnt].offset = offset; 3629 ctls[cnt].left = offset; 3630 ctls[cnt].right = offset; 3631 ctls[cnt++].dir = HDA_CTL_IN; 3632 break; 3633 } 3634 } 3635 } 3636 3637 devinfo->function.audio.ctl = ctls; 3638} 3639 3640static const struct { 3641 uint32_t model; 3642 uint32_t id; 3643 uint32_t set, unset; 3644} hdac_quirks[] = { 3645 /* 3646 * XXX Force stereo quirk. Monoural recording / playback 3647 * on few codecs (especially ALC880) seems broken or 3648 * perhaps unsupported. 3649 */ 3650 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3651 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3652 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3653 HDA_QUIRK_GPIO0, 0 }, 3654 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3655 HDA_QUIRK_GPIO0, 0 }, 3656 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3657 HDA_QUIRK_GPIO0, 0 }, 3658 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 3659 HDA_QUIRK_GPIO0, 0 }, 3660 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3661 HDA_QUIRK_EAPDINV, 0 }, 3662 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3663 HDA_QUIRK_EAPDINV, 0 }, 3664 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3665 HDA_QUIRK_GPIO1, 0 }, 3666 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3667 HDA_QUIRK_EAPDINV, 0 }, 3668 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3669 HDA_QUIRK_EAPDINV, 0 }, 3670 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3671 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3672 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3673 0, HDA_QUIRK_FORCESTEREO }, 3674 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3675 HDA_QUIRK_SOFTPCMVOL, 0 } 3676}; 3677#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3678 3679static void 3680hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3681{ 3682 struct hdac_widget *w; 3683 struct hdac_audio_ctl *ctl; 3684 uint32_t id, subvendor; 3685 int i; 3686 3687 id = hdac_codec_id(devinfo); 3688 subvendor = devinfo->codec->sc->pci_subvendor; 3689 3690 /* 3691 * Quirks 3692 */ 3693 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3694 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3695 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3696 continue; 3697 if (hdac_quirks[i].set != 0) 3698 devinfo->function.audio.quirks |= 3699 hdac_quirks[i].set; 3700 if (hdac_quirks[i].unset != 0) 3701 devinfo->function.audio.quirks &= 3702 ~(hdac_quirks[i].unset); 3703 } 3704 3705 switch (id) { 3706 case HDA_CODEC_ALC260: 3707 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3708 w = hdac_widget_get(devinfo, i); 3709 if (w == NULL || w->enable == 0) 3710 continue; 3711 if (w->type != 3712 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3713 continue; 3714 if (w->nid != 5) 3715 w->enable = 0; 3716 } 3717 if (subvendor == HP_XW4300_SUBVENDOR) { 3718 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3719 if (ctl != NULL && ctl->widget != NULL) { 3720 ctl->ossmask = SOUND_MASK_SPEAKER; 3721 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3722 } 3723 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3724 if (ctl != NULL && ctl->widget != NULL) { 3725 ctl->ossmask = SOUND_MASK_SPEAKER; 3726 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3727 } 3728 } 3729 break; 3730 case HDA_CODEC_ALC861: 3731 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3732 if (ctl != NULL) 3733 ctl->muted = HDA_AMP_MUTE_ALL; 3734 break; 3735 case HDA_CODEC_ALC880: 3736 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3737 w = hdac_widget_get(devinfo, i); 3738 if (w == NULL || w->enable == 0) 3739 continue; 3740 if (w->type == 3741 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3742 w->nid != 9 && w->nid != 29) { 3743 w->enable = 0; 3744 } else if (w->type != 3745 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3746 w->nid == 29) { 3747 w->type = 3748 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3749 w->param.widget_cap &= 3750 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3751 w->param.widget_cap |= 3752 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3753 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3754 strlcpy(w->name, "beep widget", sizeof(w->name)); 3755 } 3756 } 3757 break; 3758 case HDA_CODEC_ALC883: 3759 /* 3760 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 3761 * Clear vref cap for jack connectivity. 3762 */ 3763 w = hdac_widget_get(devinfo, 24); 3764 if (w != NULL && w->enable != 0 && w->type == 3765 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3766 (w->wclass.pin.config & 3767 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3768 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3769 w->wclass.pin.cap &= ~( 3770 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3771 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3772 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3773 w = hdac_widget_get(devinfo, 25); 3774 if (w != NULL && w->enable != 0 && w->type == 3775 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3776 (w->wclass.pin.config & 3777 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3778 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3779 w->wclass.pin.cap &= ~( 3780 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3781 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3782 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3783 /* 3784 * nid: 26 = Line-in, leave it alone. 3785 */ 3786 break; 3787 case HDA_CODEC_AD1981HD: 3788 w = hdac_widget_get(devinfo, 11); 3789 if (w != NULL && w->enable != 0 && w->nconns > 3) 3790 w->selconn = 3; 3791 if (subvendor == IBM_M52_SUBVENDOR) { 3792 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3793 if (ctl != NULL) 3794 ctl->ossmask = SOUND_MASK_SPEAKER; 3795 } 3796 break; 3797 case HDA_CODEC_AD1986A: 3798 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3799 w = hdac_widget_get(devinfo, i); 3800 if (w == NULL || w->enable == 0) 3801 continue; 3802 if (w->type != 3803 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3804 continue; 3805 if (w->nid != 3) 3806 w->enable = 0; 3807 } 3808 break; 3809 case HDA_CODEC_STAC9221: 3810 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3811 w = hdac_widget_get(devinfo, i); 3812 if (w == NULL || w->enable == 0) 3813 continue; 3814 if (w->type != 3815 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3816 continue; 3817 if (w->nid != 2) 3818 w->enable = 0; 3819 } 3820 break; 3821 case HDA_CODEC_STAC9221D: 3822 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3823 w = hdac_widget_get(devinfo, i); 3824 if (w == NULL || w->enable == 0) 3825 continue; 3826 if (w->type == 3827 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3828 w->nid != 6) 3829 w->enable = 0; 3830 3831 } 3832 break; 3833 default: 3834 break; 3835 } 3836} 3837 3838static int 3839hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3840{ 3841 int *dev = &devinfo->function.audio.ossidx; 3842 3843 while (*dev < SOUND_MIXER_NRDEVICES) { 3844 switch (*dev) { 3845 case SOUND_MIXER_VOLUME: 3846 case SOUND_MIXER_BASS: 3847 case SOUND_MIXER_TREBLE: 3848 case SOUND_MIXER_PCM: 3849 case SOUND_MIXER_SPEAKER: 3850 case SOUND_MIXER_LINE: 3851 case SOUND_MIXER_MIC: 3852 case SOUND_MIXER_CD: 3853 case SOUND_MIXER_RECLEV: 3854 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3855 (*dev)++; 3856 break; 3857 default: 3858 return (*dev)++; 3859 break; 3860 } 3861 } 3862 3863 return (-1); 3864} 3865 3866static int 3867hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3868{ 3869 struct hdac_widget *w; 3870 int i, ret = 0; 3871 3872 if (depth > HDA_PARSE_MAXDEPTH) 3873 return (0); 3874 w = hdac_widget_get(devinfo, nid); 3875 if (w == NULL || w->enable == 0) 3876 return (0); 3877 switch (w->type) { 3878 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3879 w->pflags |= HDA_DAC_PATH; 3880 ret = 1; 3881 break; 3882 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3883 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3884 for (i = 0; i < w->nconns; i++) { 3885 if (hdac_widget_find_dac_path(devinfo, 3886 w->conns[i], depth + 1) != 0) { 3887 if (w->selconn == -1) 3888 w->selconn = i; 3889 ret = 1; 3890 w->pflags |= HDA_DAC_PATH; 3891 } 3892 } 3893 break; 3894 default: 3895 break; 3896 } 3897 return (ret); 3898} 3899 3900static int 3901hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3902{ 3903 struct hdac_widget *w; 3904 int i, conndev, ret = 0; 3905 3906 if (depth > HDA_PARSE_MAXDEPTH) 3907 return (0); 3908 w = hdac_widget_get(devinfo, nid); 3909 if (w == NULL || w->enable == 0) 3910 return (0); 3911 switch (w->type) { 3912 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3913 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3914 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3915 for (i = 0; i < w->nconns; i++) { 3916 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3917 depth + 1) != 0) { 3918 if (w->selconn == -1) 3919 w->selconn = i; 3920 w->pflags |= HDA_ADC_PATH; 3921 ret = 1; 3922 } 3923 } 3924 break; 3925 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3926 conndev = w->wclass.pin.config & 3927 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3928 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3929 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3930 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3931 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3932 w->pflags |= HDA_ADC_PATH; 3933 ret = 1; 3934 } 3935 break; 3936 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3937 if (w->pflags & HDA_DAC_PATH) { 3938 w->pflags |= HDA_ADC_PATH; 3939 ret = 1; 3940 } 3941 break;*/ 3942 default: 3943 break; 3944 } 3945 return (ret); 3946} 3947 3948static uint32_t 3949hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3950 nid_t nid, nid_t pnid, int index, int depth) 3951{ 3952 struct hdac_widget *w, *pw; 3953 struct hdac_audio_ctl *ctl; 3954 uint32_t fl = 0; 3955 int i, ossdev, conndev, strategy; 3956 3957 if (depth > HDA_PARSE_MAXDEPTH) 3958 return (0); 3959 3960 w = hdac_widget_get(devinfo, nid); 3961 if (w == NULL || w->enable == 0) 3962 return (0); 3963 3964 pw = hdac_widget_get(devinfo, pnid); 3965 strategy = devinfo->function.audio.parsing_strategy; 3966 3967 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3968 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3969 for (i = 0; i < w->nconns; i++) { 3970 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3971 w->nid, i, depth + 1); 3972 } 3973 w->ctlflags |= fl; 3974 return (fl); 3975 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3976 (w->pflags & HDA_DAC_PATH)) { 3977 i = 0; 3978 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3979 if (ctl->enable == 0 || ctl->widget == NULL) 3980 continue; 3981 /* XXX This should be compressed! */ 3982 if ((ctl->widget->nid == w->nid) || 3983 (ctl->widget->nid == pnid && ctl->index == index && 3984 (ctl->dir & HDA_CTL_IN)) || 3985 (ctl->widget->nid == pnid && pw != NULL && 3986 pw->type == 3987 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3988 (pw->nconns < 2 || pw->selconn == index || 3989 pw->selconn == -1) && 3990 (ctl->dir & HDA_CTL_OUT)) || 3991 (strategy == HDA_PARSE_DIRECT && 3992 ctl->widget->nid == w->nid)) { 3993 /*if (pw != NULL && pw->selconn == -1) 3994 pw->selconn = index; 3995 fl |= SOUND_MASK_VOLUME; 3996 fl |= SOUND_MASK_PCM; 3997 ctl->ossmask |= SOUND_MASK_VOLUME; 3998 ctl->ossmask |= SOUND_MASK_PCM; 3999 ctl->ossdev = SOUND_MIXER_PCM;*/ 4000 if (!(w->ctlflags & SOUND_MASK_PCM) || 4001 (pw != NULL && 4002 !(pw->ctlflags & SOUND_MASK_PCM))) { 4003 fl |= SOUND_MASK_VOLUME; 4004 fl |= SOUND_MASK_PCM; 4005 ctl->ossmask |= SOUND_MASK_VOLUME; 4006 ctl->ossmask |= SOUND_MASK_PCM; 4007 ctl->ossdev = SOUND_MIXER_PCM; 4008 w->ctlflags |= SOUND_MASK_VOLUME; 4009 w->ctlflags |= SOUND_MASK_PCM; 4010 if (pw != NULL) { 4011 if (pw->selconn == -1) 4012 pw->selconn = index; 4013 pw->ctlflags |= 4014 SOUND_MASK_VOLUME; 4015 pw->ctlflags |= 4016 SOUND_MASK_PCM; 4017 } 4018 } 4019 } 4020 } 4021 w->ctlflags |= fl; 4022 return (fl); 4023 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4024 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 4025 (w->pflags & HDA_ADC_PATH)) { 4026 conndev = w->wclass.pin.config & 4027 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4028 i = 0; 4029 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4030 if (ctl->enable == 0 || ctl->widget == NULL) 4031 continue; 4032 /* XXX This should be compressed! */ 4033 if (((ctl->widget->nid == pnid && ctl->index == index && 4034 (ctl->dir & HDA_CTL_IN)) || 4035 (ctl->widget->nid == pnid && pw != NULL && 4036 pw->type == 4037 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4038 (pw->nconns < 2 || pw->selconn == index || 4039 pw->selconn == -1) && 4040 (ctl->dir & HDA_CTL_OUT)) || 4041 (strategy == HDA_PARSE_DIRECT && 4042 ctl->widget->nid == w->nid)) && 4043 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4044 if (pw != NULL && pw->selconn == -1) 4045 pw->selconn = index; 4046 ossdev = 0; 4047 switch (conndev) { 4048 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4049 ossdev = SOUND_MIXER_MIC; 4050 break; 4051 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4052 ossdev = SOUND_MIXER_LINE; 4053 break; 4054 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4055 ossdev = SOUND_MIXER_CD; 4056 break; 4057 default: 4058 ossdev = 4059 hdac_audio_ctl_ossmixer_getnextdev( 4060 devinfo); 4061 if (ossdev < 0) 4062 ossdev = 0; 4063 break; 4064 } 4065 if (strategy == HDA_PARSE_MIXER) { 4066 fl |= SOUND_MASK_VOLUME; 4067 ctl->ossmask |= SOUND_MASK_VOLUME; 4068 } 4069 fl |= 1 << ossdev; 4070 ctl->ossmask |= 1 << ossdev; 4071 ctl->ossdev = ossdev; 4072 } 4073 } 4074 w->ctlflags |= fl; 4075 return (fl); 4076 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4077 i = 0; 4078 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4079 if (ctl->enable == 0 || ctl->widget == NULL) 4080 continue; 4081 /* XXX This should be compressed! */ 4082 if (((ctl->widget->nid == pnid && ctl->index == index && 4083 (ctl->dir & HDA_CTL_IN)) || 4084 (ctl->widget->nid == pnid && pw != NULL && 4085 pw->type == 4086 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4087 (pw->nconns < 2 || pw->selconn == index || 4088 pw->selconn == -1) && 4089 (ctl->dir & HDA_CTL_OUT)) || 4090 (strategy == HDA_PARSE_DIRECT && 4091 ctl->widget->nid == w->nid)) && 4092 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4093 if (pw != NULL && pw->selconn == -1) 4094 pw->selconn = index; 4095 fl |= SOUND_MASK_VOLUME; 4096 fl |= SOUND_MASK_SPEAKER; 4097 ctl->ossmask |= SOUND_MASK_VOLUME; 4098 ctl->ossmask |= SOUND_MASK_SPEAKER; 4099 ctl->ossdev = SOUND_MIXER_SPEAKER; 4100 } 4101 } 4102 w->ctlflags |= fl; 4103 return (fl); 4104 } 4105 return (0); 4106} 4107 4108static uint32_t 4109hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4110{ 4111 struct hdac_widget *w, *cw; 4112 struct hdac_audio_ctl *ctl; 4113 uint32_t fl; 4114 int i; 4115 4116 if (depth > HDA_PARSE_MAXDEPTH) 4117 return (0); 4118 4119 w = hdac_widget_get(devinfo, nid); 4120 if (w == NULL || w->enable == 0) 4121 return (0); 4122 /*if (!(w->pflags & HDA_ADC_PATH)) 4123 return (0); 4124 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4125 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4126 return (0);*/ 4127 i = 0; 4128 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4129 if (ctl->enable == 0 || ctl->widget == NULL) 4130 continue; 4131 if (ctl->widget->nid == nid) { 4132 ctl->ossmask |= SOUND_MASK_RECLEV; 4133 w->ctlflags |= SOUND_MASK_RECLEV; 4134 return (SOUND_MASK_RECLEV); 4135 } 4136 } 4137 for (i = 0; i < w->nconns; i++) { 4138 cw = hdac_widget_get(devinfo, w->conns[i]); 4139 if (cw == NULL || cw->enable == 0) 4140 continue; 4141 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4142 continue; 4143 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4144 if (fl != 0) { 4145 cw->ctlflags |= fl; 4146 w->ctlflags |= fl; 4147 return (fl); 4148 } 4149 } 4150 return (0); 4151} 4152 4153static int 4154hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4155{ 4156 struct hdac_widget *w, *cw; 4157 int i, child = 0; 4158 4159 if (depth > HDA_PARSE_MAXDEPTH) 4160 return (0); 4161 4162 w = hdac_widget_get(devinfo, nid); 4163 if (w == NULL || w->enable == 0) 4164 return (0); 4165 /*if (!(w->pflags & HDA_ADC_PATH)) 4166 return (0); 4167 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4168 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4169 return (0);*/ 4170 /* XXX weak! */ 4171 for (i = 0; i < w->nconns; i++) { 4172 cw = hdac_widget_get(devinfo, w->conns[i]); 4173 if (cw == NULL) 4174 continue; 4175 if (++child > 1) { 4176 w->pflags |= HDA_ADC_RECSEL; 4177 return (1); 4178 } 4179 } 4180 for (i = 0; i < w->nconns; i++) { 4181 if (hdac_audio_ctl_recsel_build(devinfo, 4182 w->conns[i], depth + 1) != 0) 4183 return (1); 4184 } 4185 return (0); 4186} 4187 4188static int 4189hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4190{ 4191 struct hdac_widget *w, *cw; 4192 int i, j, conndev, found_dac = 0; 4193 int strategy; 4194 4195 strategy = devinfo->function.audio.parsing_strategy; 4196 4197 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4198 w = hdac_widget_get(devinfo, i); 4199 if (w == NULL || w->enable == 0) 4200 continue; 4201 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4202 continue; 4203 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4204 continue; 4205 conndev = w->wclass.pin.config & 4206 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4207 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4208 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4209 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4210 continue; 4211 for (j = 0; j < w->nconns; j++) { 4212 cw = hdac_widget_get(devinfo, w->conns[j]); 4213 if (cw == NULL || cw->enable == 0) 4214 continue; 4215 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4216 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4217 cw->type == 4218 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4219 continue; 4220 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4221 != 0) { 4222 if (w->selconn == -1) 4223 w->selconn = j; 4224 w->pflags |= HDA_DAC_PATH; 4225 found_dac++; 4226 } 4227 } 4228 } 4229 4230 return (found_dac); 4231} 4232 4233static void 4234hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4235{ 4236 struct hdac_widget *w; 4237 struct hdac_audio_ctl *ctl; 4238 int i, j, dacs, strategy; 4239 4240 /* Construct DAC path */ 4241 strategy = HDA_PARSE_MIXER; 4242 devinfo->function.audio.parsing_strategy = strategy; 4243 HDA_BOOTVERBOSE( 4244 device_printf(devinfo->codec->sc->dev, 4245 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4246 HDA_WIDGET_PARSER_REV); 4247 ); 4248 dacs = hdac_audio_build_tree_strategy(devinfo); 4249 if (dacs == 0) { 4250 HDA_BOOTVERBOSE( 4251 device_printf(devinfo->codec->sc->dev, 4252 "HDA_DEBUG: HWiP: 0 DAC path found! " 4253 "Retrying parser " 4254 "using HDA_PARSE_DIRECT strategy.\n"); 4255 ); 4256 strategy = HDA_PARSE_DIRECT; 4257 devinfo->function.audio.parsing_strategy = strategy; 4258 dacs = hdac_audio_build_tree_strategy(devinfo); 4259 } 4260 4261 HDA_BOOTVERBOSE( 4262 device_printf(devinfo->codec->sc->dev, 4263 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4264 "strategy.\n", 4265 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4266 ); 4267 4268 /* Construct ADC path */ 4269 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4270 w = hdac_widget_get(devinfo, i); 4271 if (w == NULL || w->enable == 0) 4272 continue; 4273 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4274 continue; 4275 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4276 } 4277 4278 /* Output mixers */ 4279 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4280 w = hdac_widget_get(devinfo, i); 4281 if (w == NULL || w->enable == 0) 4282 continue; 4283 if ((strategy == HDA_PARSE_MIXER && 4284 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4285 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4286 && (w->pflags & HDA_DAC_PATH)) || 4287 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4288 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4289 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4290 w->nid, devinfo->startnode - 1, 0, 0); 4291 } else if (w->type == 4292 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4293 j = 0; 4294 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4295 NULL) { 4296 if (ctl->enable == 0 || ctl->widget == NULL) 4297 continue; 4298 if (ctl->widget->nid != w->nid) 4299 continue; 4300 ctl->ossmask |= SOUND_MASK_VOLUME; 4301 ctl->ossmask |= SOUND_MASK_SPEAKER; 4302 ctl->ossdev = SOUND_MIXER_SPEAKER; 4303 w->ctlflags |= SOUND_MASK_VOLUME; 4304 w->ctlflags |= SOUND_MASK_SPEAKER; 4305 } 4306 } 4307 } 4308 4309 /* Input mixers (rec) */ 4310 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4311 w = hdac_widget_get(devinfo, i); 4312 if (w == NULL || w->enable == 0) 4313 continue; 4314 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4315 w->pflags & HDA_ADC_PATH)) 4316 continue; 4317 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4318 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4319 } 4320} 4321 4322#define HDA_COMMIT_CONN (1 << 0) 4323#define HDA_COMMIT_CTRL (1 << 1) 4324#define HDA_COMMIT_EAPD (1 << 2) 4325#define HDA_COMMIT_GPIO (1 << 3) 4326#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4327 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4328 4329static void 4330hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4331{ 4332 struct hdac_softc *sc = devinfo->codec->sc; 4333 struct hdac_widget *w; 4334 nid_t cad; 4335 int i; 4336 4337 if (!(cfl & HDA_COMMIT_ALL)) 4338 return; 4339 4340 cad = devinfo->codec->cad; 4341 4342 if (cfl & HDA_COMMIT_GPIO) { 4343 uint32_t gdata, gmask, gdir; 4344 int commitgpio = 0; 4345 4346 gdata = 0; 4347 gmask = 0; 4348 gdir = 0; 4349 4350 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4351 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4352 0x7e7, 0), cad); 4353 4354 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4355 commitgpio = 1; 4356 else { 4357 for (i = 0; i < HDA_GPIO_MAX; i++) { 4358 if (!(devinfo->function.audio.quirks & 4359 (1 << i))) 4360 continue; 4361 if (commitgpio == 0) { 4362 commitgpio = 1; 4363 gdata = hdac_command(sc, 4364 HDA_CMD_GET_GPIO_DATA(cad, 4365 devinfo->nid), cad); 4366 gmask = hdac_command(sc, 4367 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4368 devinfo->nid), cad); 4369 gdir = hdac_command(sc, 4370 HDA_CMD_GET_GPIO_DIRECTION(cad, 4371 devinfo->nid), cad); 4372 HDA_BOOTVERBOSE( 4373 device_printf(sc->dev, 4374 "GPIO init: data=0x%08x " 4375 "mask=0x%08x dir=0x%08x\n", 4376 gdata, gmask, gdir); 4377 ); 4378 } 4379 gdata |= 1 << i; 4380 gmask |= 1 << i; 4381 gdir |= 1 << i; 4382 } 4383 } 4384 4385 if (commitgpio != 0) { 4386 HDA_BOOTVERBOSE( 4387 device_printf(sc->dev, 4388 "GPIO commit: data=0x%08x mask=0x%08x " 4389 "dir=0x%08x\n", 4390 gdata, gmask, gdir); 4391 ); 4392 hdac_command(sc, 4393 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4394 gmask), cad); 4395 hdac_command(sc, 4396 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4397 gdir), cad); 4398 hdac_command(sc, 4399 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4400 gdata), cad); 4401 } 4402 } 4403 4404 for (i = 0; i < devinfo->nodecnt; i++) { 4405 w = &devinfo->widget[i]; 4406 if (w == NULL || w->enable == 0) 4407 continue; 4408 if (cfl & HDA_COMMIT_CONN) { 4409 if (w->selconn == -1) 4410 w->selconn = 0; 4411 if (w->nconns > 0) 4412 hdac_widget_connection_select(w, w->selconn); 4413 } 4414 if ((cfl & HDA_COMMIT_CTRL) && 4415 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4416 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4417 (HDA_DAC_PATH | HDA_ADC_PATH)) 4418 device_printf(sc->dev, "WARNING: node %d " 4419 "participate both for DAC/ADC!\n", w->nid); 4420 if (w->pflags & HDA_DAC_PATH) { 4421 w->wclass.pin.ctrl &= 4422 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4423 if ((w->wclass.pin.config & 4424 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4425 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4426 w->wclass.pin.ctrl &= 4427 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4428 } else if (w->pflags & HDA_ADC_PATH) { 4429 w->wclass.pin.ctrl &= 4430 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4431 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4432 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4433 uint32_t pincap = w->wclass.pin.cap; 4434 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4435 w->wclass.pin.ctrl |= 4436 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4437 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4438 ); 4439 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4440 w->wclass.pin.ctrl |= 4441 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4442 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4443 ); 4444 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4445 w->wclass.pin.ctrl |= 4446 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4447 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4448 ); 4449 } 4450 } else 4451 w->wclass.pin.ctrl &= ~( 4452 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4453 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4454 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4455 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4456 hdac_command(sc, 4457 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4458 w->wclass.pin.ctrl), cad); 4459 } 4460 if ((cfl & HDA_COMMIT_EAPD) && 4461 w->param.eapdbtl != HDAC_INVALID) { 4462 uint32_t val; 4463 4464 val = w->param.eapdbtl; 4465 if (devinfo->function.audio.quirks & 4466 HDA_QUIRK_EAPDINV) 4467 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4468 hdac_command(sc, 4469 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4470 val), cad); 4471 4472 } 4473 DELAY(1000); 4474 } 4475} 4476 4477static void 4478hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4479{ 4480 struct hdac_softc *sc = devinfo->codec->sc; 4481 struct hdac_audio_ctl *ctl; 4482 int i; 4483 4484 devinfo->function.audio.mvol = 100 | (100 << 8); 4485 i = 0; 4486 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4487 if (ctl->enable == 0 || ctl->widget == NULL) { 4488 HDA_BOOTVERBOSE( 4489 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4490 i, (ctl->widget != NULL) ? 4491 ctl->widget->nid : -1); 4492 if (ctl->childwidget != NULL) 4493 printf(" childnid=%d", 4494 ctl->childwidget->nid); 4495 if (ctl->widget == NULL) 4496 printf(" NULL WIDGET!"); 4497 printf(" DISABLED\n"); 4498 ); 4499 continue; 4500 } 4501 HDA_BOOTVERBOSE( 4502 if (ctl->ossmask == 0) { 4503 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4504 i, ctl->widget->nid); 4505 if (ctl->childwidget != NULL) 4506 printf(" childnid=%d", 4507 ctl->childwidget->nid); 4508 printf(" Bind to NONE\n"); 4509 } 4510 ); 4511 if (ctl->step > 0) { 4512 ctl->ossval = (ctl->left * 100) / ctl->step; 4513 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4514 } else 4515 ctl->ossval = 0; 4516 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4517 ctl->left, ctl->right); 4518 } 4519} 4520 4521static int 4522hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4523{ 4524 struct hdac_chan *ch; 4525 struct hdac_widget *w; 4526 uint32_t cap, fmtcap, pcmcap, path; 4527 int i, type, ret, max; 4528 4529 if (dir == PCMDIR_PLAY) { 4530 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4531 ch = &devinfo->codec->sc->play; 4532 path = HDA_DAC_PATH; 4533 } else { 4534 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4535 ch = &devinfo->codec->sc->rec; 4536 path = HDA_ADC_PATH; 4537 } 4538 4539 ch->caps = hdac_caps; 4540 ch->caps.fmtlist = ch->fmtlist; 4541 ch->bit16 = 1; 4542 ch->bit32 = 0; 4543 ch->pcmrates[0] = 48000; 4544 ch->pcmrates[1] = 0; 4545 4546 ret = 0; 4547 fmtcap = devinfo->function.audio.supp_stream_formats; 4548 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4549 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4550 4551 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4552 w = hdac_widget_get(devinfo, i); 4553 if (w == NULL || w->enable == 0 || w->type != type || 4554 !(w->pflags & path)) 4555 continue; 4556 cap = w->param.widget_cap; 4557 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4558 continue;*/ 4559 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4560 continue; 4561 cap = w->param.supp_stream_formats; 4562 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4563 } 4564 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4565 }*/ 4566 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4567 continue; 4568 if (ret == 0) { 4569 fmtcap = w->param.supp_stream_formats; 4570 pcmcap = w->param.supp_pcm_size_rate; 4571 } else { 4572 fmtcap &= w->param.supp_stream_formats; 4573 pcmcap &= w->param.supp_pcm_size_rate; 4574 } 4575 ch->io[ret++] = i; 4576 } 4577 ch->io[ret] = -1; 4578 4579 ch->supp_stream_formats = fmtcap; 4580 ch->supp_pcm_size_rate = pcmcap; 4581 4582 /* 4583 * 8bit = 0 4584 * 16bit = 1 4585 * 20bit = 2 4586 * 24bit = 3 4587 * 32bit = 4 4588 */ 4589 if (ret > 0) { 4590 cap = pcmcap; 4591 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4592 ch->bit16 = 1; 4593 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4594 ch->bit16 = 0; 4595 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4596 ch->bit32 = 4; 4597 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4598 ch->bit32 = 3; 4599 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4600 ch->bit32 = 2; 4601 i = 0; 4602 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4603 ch->fmtlist[i++] = AFMT_S16_LE; 4604 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4605 if (ch->bit32 > 0) { 4606 if (!(devinfo->function.audio.quirks & 4607 HDA_QUIRK_FORCESTEREO)) 4608 ch->fmtlist[i++] = AFMT_S32_LE; 4609 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4610 } 4611 ch->fmtlist[i] = 0; 4612 i = 0; 4613 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4614 ch->pcmrates[i++] = 8000; 4615 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4616 ch->pcmrates[i++] = 11025; 4617 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4618 ch->pcmrates[i++] = 16000; 4619 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4620 ch->pcmrates[i++] = 22050; 4621 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4622 ch->pcmrates[i++] = 32000; 4623 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4624 ch->pcmrates[i++] = 44100; 4625 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4626 ch->pcmrates[i++] = 48000; 4627 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4628 ch->pcmrates[i++] = 88200; 4629 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4630 ch->pcmrates[i++] = 96000; 4631 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4632 ch->pcmrates[i++] = 176400; 4633 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4634 ch->pcmrates[i++] = 192000; 4635 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4636 ch->pcmrates[i] = 0; 4637 if (i > 0) { 4638 ch->caps.minspeed = ch->pcmrates[0]; 4639 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4640 } 4641 } 4642 4643 return (ret); 4644} 4645 4646static void 4647hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4648{ 4649 struct hdac_audio_ctl *ctl; 4650 struct hdac_softc *sc = devinfo->codec->sc; 4651 int i; 4652 uint32_t fl = 0; 4653 4654 4655 if (flag == 0) { 4656 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4657 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4658 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4659 } 4660 4661 i = 0; 4662 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4663 if (ctl->enable == 0 || ctl->widget == NULL || 4664 ctl->widget->enable == 0) 4665 continue; 4666 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4667 (flag != 0 && (ctl->ossmask & flag))) { 4668 if (banner != NULL) { 4669 device_printf(sc->dev, "\n"); 4670 device_printf(sc->dev, "%s\n", banner); 4671 } 4672 goto hdac_ctl_dump_it_all; 4673 } 4674 } 4675 4676 return; 4677 4678hdac_ctl_dump_it_all: 4679 i = 0; 4680 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4681 if (ctl->enable == 0 || ctl->widget == NULL || 4682 ctl->widget->enable == 0) 4683 continue; 4684 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4685 (flag != 0 && (ctl->ossmask & flag)))) 4686 continue; 4687 if (flag == 0) { 4688 device_printf(sc->dev, "\n"); 4689 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4690 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4691 } 4692 device_printf(sc->dev, " |\n"); 4693 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4694 ctl->widget->nid, ctl->index); 4695 if (ctl->childwidget != NULL) 4696 printf("(nid: %2d) ", ctl->childwidget->nid); 4697 else 4698 printf(" "); 4699 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4700 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4701 ctl->ossmask); 4702 } 4703} 4704 4705static void 4706hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4707{ 4708 uint32_t cap; 4709 4710 cap = fcap; 4711 if (cap != 0) { 4712 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4713 device_printf(sc->dev, " Format:"); 4714 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4715 printf(" AC3"); 4716 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4717 printf(" FLOAT32"); 4718 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4719 printf(" PCM"); 4720 printf("\n"); 4721 } 4722 cap = pcmcap; 4723 if (cap != 0) { 4724 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4725 device_printf(sc->dev, " PCM size:"); 4726 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4727 printf(" 8"); 4728 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4729 printf(" 16"); 4730 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4731 printf(" 20"); 4732 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4733 printf(" 24"); 4734 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4735 printf(" 32"); 4736 printf("\n"); 4737 device_printf(sc->dev, " PCM rate:"); 4738 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4739 printf(" 8"); 4740 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4741 printf(" 11"); 4742 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4743 printf(" 16"); 4744 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4745 printf(" 22"); 4746 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4747 printf(" 32"); 4748 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4749 printf(" 44"); 4750 printf(" 48"); 4751 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4752 printf(" 88"); 4753 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4754 printf(" 96"); 4755 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4756 printf(" 176"); 4757 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4758 printf(" 192"); 4759 printf("\n"); 4760 } 4761} 4762 4763static void 4764hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4765{ 4766 uint32_t pincap, wcap; 4767 4768 pincap = w->wclass.pin.cap; 4769 wcap = w->param.widget_cap; 4770 4771 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4772 device_printf(sc->dev, " "); 4773 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4774 printf(" ISC"); 4775 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4776 printf(" TRQD"); 4777 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4778 printf(" PDC"); 4779 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4780 printf(" HP"); 4781 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4782 printf(" OUT"); 4783 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4784 printf(" IN"); 4785 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4786 printf(" BAL"); 4787 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4788 printf(" VREF["); 4789 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4790 printf(" 50"); 4791 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4792 printf(" 80"); 4793 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4794 printf(" 100"); 4795 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4796 printf(" GROUND"); 4797 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4798 printf(" HIZ"); 4799 printf(" ]"); 4800 } 4801 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4802 printf(" EAPD"); 4803 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4804 printf(" : UNSOL"); 4805 printf("\n"); 4806 device_printf(sc->dev, " Pin config: 0x%08x\n", 4807 w->wclass.pin.config); 4808 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4809 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4810 printf(" HP"); 4811 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4812 printf(" IN"); 4813 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4814 printf(" OUT"); 4815 printf("\n"); 4816} 4817 4818static void 4819hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4820{ 4821 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4822 device_printf(sc->dev, " " 4823 "mute=%d step=%d size=%d offset=%d\n", 4824 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4825 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4826 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4827 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4828} 4829 4830static void 4831hdac_dump_nodes(struct hdac_devinfo *devinfo) 4832{ 4833 struct hdac_softc *sc = devinfo->codec->sc; 4834 struct hdac_widget *w, *cw; 4835 int i, j; 4836 4837 device_printf(sc->dev, "\n"); 4838 device_printf(sc->dev, "Default Parameter\n"); 4839 device_printf(sc->dev, "-----------------\n"); 4840 hdac_dump_audio_formats(sc, 4841 devinfo->function.audio.supp_stream_formats, 4842 devinfo->function.audio.supp_pcm_size_rate); 4843 device_printf(sc->dev, " IN amp: 0x%08x\n", 4844 devinfo->function.audio.inamp_cap); 4845 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4846 devinfo->function.audio.outamp_cap); 4847 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4848 w = hdac_widget_get(devinfo, i); 4849 if (w == NULL) { 4850 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4851 continue; 4852 } 4853 device_printf(sc->dev, "\n"); 4854 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4855 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4856 "DIGITAL" : "ANALOG", 4857 (w->enable == 0) ? " [DISABLED]" : ""); 4858 device_printf(sc->dev, " name: %s\n", w->name); 4859 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4860 w->param.widget_cap); 4861 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4862 w->pflags); 4863 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4864 w->ctlflags); 4865 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4866 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4867 hdac_dump_audio_formats(sc, 4868 w->param.supp_stream_formats, 4869 w->param.supp_pcm_size_rate); 4870 } else if (w->type == 4871 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4872 hdac_dump_pin(sc, w); 4873 if (w->param.eapdbtl != HDAC_INVALID) 4874 device_printf(sc->dev, " EAPD: 0x%08x\n", 4875 w->param.eapdbtl); 4876 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4877 w->param.outamp_cap != 0) 4878 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4879 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4880 w->param.inamp_cap != 0) 4881 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4882 device_printf(sc->dev, " connections: %d\n", w->nconns); 4883 for (j = 0; j < w->nconns; j++) { 4884 cw = hdac_widget_get(devinfo, w->conns[j]); 4885 device_printf(sc->dev, " |\n"); 4886 device_printf(sc->dev, " + <- nid=%d [%s]", 4887 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4888 if (cw == NULL) 4889 printf(" [UNKNOWN]"); 4890 else if (cw->enable == 0) 4891 printf(" [DISABLED]"); 4892 if (w->nconns > 1 && w->selconn == j && w->type != 4893 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4894 printf(" (selected)"); 4895 printf("\n"); 4896 } 4897 } 4898 4899} 4900 4901static int 4902hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4903{ 4904 struct hdac_widget *w, *cw; 4905 struct hdac_softc *sc = devinfo->codec->sc; 4906 int i; 4907 4908 if (depth > HDA_PARSE_MAXDEPTH) 4909 return (0); 4910 4911 w = hdac_widget_get(devinfo, nid); 4912 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4913 return (0); 4914 4915 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4916 device_printf(sc->dev, "\n"); 4917 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4918 device_printf(sc->dev, " ^\n"); 4919 device_printf(sc->dev, " |\n"); 4920 device_printf(sc->dev, " +-----<------+\n"); 4921 } else { 4922 device_printf(sc->dev, " ^\n"); 4923 device_printf(sc->dev, " |\n"); 4924 device_printf(sc->dev, " "); 4925 printf(" nid=%d [%s]\n", w->nid, w->name); 4926 } 4927 4928 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4929 return (1); 4930 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4931 for (i = 0; i < w->nconns; i++) { 4932 cw = hdac_widget_get(devinfo, w->conns[i]); 4933 if (cw == NULL || cw->enable == 0 || cw->type == 4934 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4935 continue; 4936 if (hdac_dump_dac_internal(devinfo, cw->nid, 4937 depth + 1) != 0) 4938 return (1); 4939 } 4940 } else if ((w->type == 4941 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4942 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4943 w->selconn > -1 && w->selconn < w->nconns) { 4944 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4945 depth + 1) != 0) 4946 return (1); 4947 } 4948 4949 return (0); 4950} 4951 4952static void 4953hdac_dump_dac(struct hdac_devinfo *devinfo) 4954{ 4955 struct hdac_widget *w; 4956 struct hdac_softc *sc = devinfo->codec->sc; 4957 int i, printed = 0; 4958 4959 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4960 w = hdac_widget_get(devinfo, i); 4961 if (w == NULL || w->enable == 0) 4962 continue; 4963 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4964 !(w->pflags & HDA_DAC_PATH)) 4965 continue; 4966 if (printed == 0) { 4967 printed = 1; 4968 device_printf(sc->dev, "\n"); 4969 device_printf(sc->dev, "Playback path:\n"); 4970 } 4971 hdac_dump_dac_internal(devinfo, w->nid, 0); 4972 } 4973} 4974 4975static void 4976hdac_dump_adc(struct hdac_devinfo *devinfo) 4977{ 4978 struct hdac_widget *w, *cw; 4979 struct hdac_softc *sc = devinfo->codec->sc; 4980 int i, j; 4981 int printed = 0; 4982 char ossdevs[256]; 4983 4984 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4985 w = hdac_widget_get(devinfo, i); 4986 if (w == NULL || w->enable == 0) 4987 continue; 4988 if (!(w->pflags & HDA_ADC_RECSEL)) 4989 continue; 4990 if (printed == 0) { 4991 printed = 1; 4992 device_printf(sc->dev, "\n"); 4993 device_printf(sc->dev, "Recording sources:\n"); 4994 } 4995 device_printf(sc->dev, "\n"); 4996 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4997 for (j = 0; j < w->nconns; j++) { 4998 cw = hdac_widget_get(devinfo, w->conns[j]); 4999 if (cw == NULL || cw->enable == 0) 5000 continue; 5001 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 5002 ossdevs, sizeof(ossdevs)); 5003 device_printf(sc->dev, " |\n"); 5004 device_printf(sc->dev, " + <- nid=%d [%s]", 5005 cw->nid, cw->name); 5006 if (strlen(ossdevs) > 0) { 5007 printf(" [recsrc: %s]", ossdevs); 5008 } 5009 printf("\n"); 5010 } 5011 } 5012} 5013 5014static void 5015hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 5016{ 5017 nid_t *nids; 5018 5019 if (pcnt > 0) { 5020 device_printf(sc->dev, "\n"); 5021 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 5022 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5023 sc->play.supp_pcm_size_rate); 5024 device_printf(sc->dev, " DAC:"); 5025 for (nids = sc->play.io; *nids != -1; nids++) 5026 printf(" %d", *nids); 5027 printf("\n"); 5028 } 5029 5030 if (rcnt > 0) { 5031 device_printf(sc->dev, "\n"); 5032 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5033 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5034 sc->rec.supp_pcm_size_rate); 5035 device_printf(sc->dev, " ADC:"); 5036 for (nids = sc->rec.io; *nids != -1; nids++) 5037 printf(" %d", *nids); 5038 printf("\n"); 5039 } 5040} 5041 5042static void 5043hdac_release_resources(struct hdac_softc *sc) 5044{ 5045 struct hdac_devinfo *devinfo = NULL; 5046 device_t *devlist = NULL; 5047 int i, devcount; 5048 5049 if (sc == NULL) 5050 return; 5051 5052 hdac_lock(sc); 5053 if (sc->polling != 0) 5054 callout_stop(&sc->poll_hdac); 5055 hdac_reset(sc); 5056 hdac_unlock(sc); 5057 snd_mtxfree(sc->lock); 5058 5059 device_get_children(sc->dev, &devlist, &devcount); 5060 for (i = 0; devlist != NULL && i < devcount; i++) { 5061 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5062 if (devinfo == NULL) 5063 continue; 5064 if (devinfo->widget != NULL) 5065 free(devinfo->widget, M_HDAC); 5066 if (devinfo->node_type == 5067 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5068 devinfo->function.audio.ctl != NULL) 5069 free(devinfo->function.audio.ctl, M_HDAC); 5070 free(devinfo, M_HDAC); 5071 device_delete_child(sc->dev, devlist[i]); 5072 } 5073 if (devlist != NULL) 5074 free(devlist, M_TEMP); 5075 5076 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5077 if (sc->codecs[i] != NULL) 5078 free(sc->codecs[i], M_HDAC); 5079 sc->codecs[i] = NULL; 5080 } 5081 5082 hdac_dma_free(&sc->rirb_dma); 5083 hdac_dma_free(&sc->corb_dma); 5084 if (sc->play.blkcnt > 0) 5085 hdac_dma_free(&sc->play.bdl_dma); 5086 if (sc->rec.blkcnt > 0) 5087 hdac_dma_free(&sc->rec.bdl_dma); 5088 hdac_irq_free(sc); 5089 hdac_mem_free(sc); 5090 free(sc, M_DEVBUF); 5091 5092} 5093 5094/* This function surely going to make its way into upper level someday. */ 5095static void 5096hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5097{ 5098 const char *res = NULL; 5099 int i = 0, j, k, len, inv; 5100 5101 if (on != NULL) 5102 *on = 0; 5103 if (off != NULL) 5104 *off = 0; 5105 if (sc == NULL) 5106 return; 5107 if (resource_string_value(device_get_name(sc->dev), 5108 device_get_unit(sc->dev), "config", &res) != 0) 5109 return; 5110 if (!(res != NULL && strlen(res) > 0)) 5111 return; 5112 HDA_BOOTVERBOSE( 5113 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5114 ); 5115 for (;;) { 5116 while (res[i] != '\0' && 5117 (res[i] == ',' || isspace(res[i]) != 0)) 5118 i++; 5119 if (res[i] == '\0') { 5120 HDA_BOOTVERBOSE( 5121 printf("\n"); 5122 ); 5123 return; 5124 } 5125 j = i; 5126 while (res[j] != '\0' && 5127 !(res[j] == ',' || isspace(res[j]) != 0)) 5128 j++; 5129 len = j - i; 5130 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5131 inv = 2; 5132 else 5133 inv = 0; 5134 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5135 if (strncmp(res + i + inv, 5136 hdac_quirks_tab[k].key, len - inv) != 0) 5137 continue; 5138 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5139 break; 5140 HDA_BOOTVERBOSE( 5141 printf(" %s%s", (inv != 0) ? "no" : "", 5142 hdac_quirks_tab[k].key); 5143 ); 5144 if (inv == 0 && on != NULL) 5145 *on |= hdac_quirks_tab[k].value; 5146 else if (inv != 0 && off != NULL) 5147 *off |= hdac_quirks_tab[k].value; 5148 break; 5149 } 5150 i = j; 5151 } 5152} 5153 5154#ifdef SND_DYNSYSCTL 5155static int 5156sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5157{ 5158 struct hdac_softc *sc; 5159 struct hdac_devinfo *devinfo; 5160 device_t dev; 5161 uint32_t ctl; 5162 int err, val; 5163 5164 dev = oidp->oid_arg1; 5165 devinfo = pcm_getdevinfo(dev); 5166 if (devinfo == NULL || devinfo->codec == NULL || 5167 devinfo->codec->sc == NULL) 5168 return (EINVAL); 5169 sc = devinfo->codec->sc; 5170 hdac_lock(sc); 5171 val = sc->polling; 5172 hdac_unlock(sc); 5173 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5174 5175 if (err || req->newptr == NULL) 5176 return (err); 5177 if (val < 0 || val > 1) 5178 return (EINVAL); 5179 5180 hdac_lock(sc); 5181 if (val != sc->polling) { 5182 if (hda_chan_active(sc) != 0) 5183 err = EBUSY; 5184 else if (val == 0) { 5185 callout_stop(&sc->poll_hdac); 5186 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5187 sc->rirb_size / 2); 5188 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5189 ctl |= HDAC_RIRBCTL_RINTCTL; 5190 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5191 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5192 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5193 sc->polling = 0; 5194 DELAY(1000); 5195 } else { 5196 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5197 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5198 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5199 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5200 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5201 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5202 sc); 5203 sc->polling = 1; 5204 DELAY(1000); 5205 } 5206 } 5207 hdac_unlock(sc); 5208 5209 return (err); 5210} 5211#endif 5212 5213static void 5214hdac_attach2(void *arg) 5215{ 5216 struct hdac_softc *sc; 5217 struct hdac_widget *w; 5218 struct hdac_audio_ctl *ctl; 5219 uint32_t quirks_on, quirks_off; 5220 int pcnt, rcnt; 5221 int i; 5222 char status[SND_STATUSLEN]; 5223 device_t *devlist = NULL; 5224 int devcount; 5225 struct hdac_devinfo *devinfo = NULL; 5226 5227 sc = (struct hdac_softc *)arg; 5228 5229 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5230 5231 HDA_BOOTVERBOSE( 5232 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5233 quirks_on, quirks_off); 5234 ); 5235 5236 hdac_lock(sc); 5237 5238 /* Remove ourselves from the config hooks */ 5239 if (sc->intrhook.ich_func != NULL) { 5240 config_intrhook_disestablish(&sc->intrhook); 5241 sc->intrhook.ich_func = NULL; 5242 } 5243 5244 /* Start the corb and rirb engines */ 5245 HDA_BOOTVERBOSE( 5246 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5247 ); 5248 hdac_corb_start(sc); 5249 HDA_BOOTVERBOSE( 5250 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5251 ); 5252 hdac_rirb_start(sc); 5253 5254 HDA_BOOTVERBOSE( 5255 device_printf(sc->dev, 5256 "HDA_DEBUG: Enabling controller interrupt...\n"); 5257 ); 5258 if (sc->polling == 0) 5259 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5260 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5261 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5262 HDAC_GCTL_UNSOL); 5263 5264 DELAY(1000); 5265 5266 HDA_BOOTVERBOSE( 5267 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5268 ); 5269 hdac_scan_codecs(sc); 5270 5271 device_get_children(sc->dev, &devlist, &devcount); 5272 for (i = 0; devlist != NULL && i < devcount; i++) { 5273 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5274 if (devinfo != NULL && devinfo->node_type == 5275 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5276 break; 5277 } else 5278 devinfo = NULL; 5279 } 5280 if (devlist != NULL) 5281 free(devlist, M_TEMP); 5282 5283 if (devinfo == NULL) { 5284 hdac_unlock(sc); 5285 device_printf(sc->dev, "Audio Function Group not found!\n"); 5286 hdac_release_resources(sc); 5287 return; 5288 } 5289 5290 HDA_BOOTVERBOSE( 5291 device_printf(sc->dev, 5292 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5293 devinfo->nid, devinfo->codec->cad); 5294 ); 5295 hdac_audio_parse(devinfo); 5296 HDA_BOOTVERBOSE( 5297 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5298 ); 5299 hdac_audio_ctl_parse(devinfo); 5300 HDA_BOOTVERBOSE( 5301 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5302 ); 5303 hdac_vendor_patch_parse(devinfo); 5304 if (quirks_on != 0) 5305 devinfo->function.audio.quirks |= quirks_on; 5306 if (quirks_off != 0) 5307 devinfo->function.audio.quirks &= ~quirks_off; 5308 5309 /* XXX Disable all DIGITAL path. */ 5310 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5311 w = hdac_widget_get(devinfo, i); 5312 if (w == NULL) 5313 continue; 5314 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5315 w->enable = 0; 5316 continue; 5317 } 5318 /* XXX Disable useless pin ? */ 5319 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5320 (w->wclass.pin.config & 5321 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5322 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5323 w->enable = 0; 5324 } 5325 i = 0; 5326 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5327 if (ctl->widget == NULL) 5328 continue; 5329 w = ctl->widget; 5330 if (w->enable == 0) 5331 ctl->enable = 0; 5332 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5333 ctl->enable = 0; 5334 w = ctl->childwidget; 5335 if (w == NULL) 5336 continue; 5337 if (w->enable == 0 || 5338 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5339 ctl->enable = 0; 5340 } 5341 5342 HDA_BOOTVERBOSE( 5343 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5344 ); 5345 hdac_audio_build_tree(devinfo); 5346 5347 HDA_BOOTVERBOSE( 5348 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5349 ); 5350 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5351 HDA_BOOTVERBOSE( 5352 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5353 ); 5354 hdac_audio_ctl_commit(devinfo); 5355 5356 HDA_BOOTVERBOSE( 5357 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5358 ); 5359 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5360 HDA_BOOTVERBOSE( 5361 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5362 ); 5363 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5364 5365 hdac_unlock(sc); 5366 HDA_BOOTVERBOSE( 5367 device_printf(sc->dev, 5368 "HDA_DEBUG: OSS mixer initialization...\n"); 5369 ); 5370 5371 /* 5372 * There is no point of return after this. If the driver failed, 5373 * so be it. Let the detach procedure do all the cleanup. 5374 */ 5375 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5376 device_printf(sc->dev, "Can't register mixer\n"); 5377 5378 if (pcnt > 0) 5379 pcnt = 1; 5380 if (rcnt > 0) 5381 rcnt = 1; 5382 5383 HDA_BOOTVERBOSE( 5384 device_printf(sc->dev, 5385 "HDA_DEBUG: Registering PCM channels...\n"); 5386 ); 5387 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5388 device_printf(sc->dev, "Can't register PCM\n"); 5389 5390 sc->registered++; 5391 5392 for (i = 0; i < pcnt; i++) 5393 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5394 for (i = 0; i < rcnt; i++) 5395 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5396 5397#ifdef SND_DYNSYSCTL 5398 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5399 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5400 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5401 sysctl_hdac_polling, "I", "Enable polling mode"); 5402#endif 5403 5404 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5405 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5406 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5407 pcm_setstatus(sc->dev, status); 5408 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5409 HDA_BOOTVERBOSE( 5410 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5411 hdac_codec_id(devinfo)); 5412 ); 5413 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5414 HDA_DRV_TEST_REV); 5415 5416 HDA_BOOTVERBOSE( 5417 if (devinfo->function.audio.quirks != 0) { 5418 device_printf(sc->dev, "\n"); 5419 device_printf(sc->dev, "HDA config/quirks:"); 5420 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5421 if (devinfo->function.audio.quirks & 5422 hdac_quirks_tab[i].value) 5423 printf(" %s", hdac_quirks_tab[i].key); 5424 } 5425 printf("\n"); 5426 } 5427 device_printf(sc->dev, "\n"); 5428 device_printf(sc->dev, "+-------------------+\n"); 5429 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5430 device_printf(sc->dev, "+-------------------+\n"); 5431 hdac_dump_nodes(devinfo); 5432 device_printf(sc->dev, "\n"); 5433 device_printf(sc->dev, "+------------------------+\n"); 5434 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5435 device_printf(sc->dev, "+------------------------+\n"); 5436 device_printf(sc->dev, "\n"); 5437 i = 0; 5438 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5439 device_printf(sc->dev, "%3d: nid=%d", i, 5440 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5441 if (ctl->childwidget != NULL) 5442 printf(" cnid=%d", ctl->childwidget->nid); 5443 printf(" dir=0x%x index=%d " 5444 "ossmask=0x%08x ossdev=%d%s\n", 5445 ctl->dir, ctl->index, 5446 ctl->ossmask, ctl->ossdev, 5447 (ctl->enable == 0) ? " [DISABLED]" : ""); 5448 } 5449 device_printf(sc->dev, "\n"); 5450 device_printf(sc->dev, "+-----------------------------------+\n"); 5451 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5452 device_printf(sc->dev, "+-----------------------------------+\n"); 5453 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5454 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5455 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5456 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5457 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5458 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5459 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5460 hdac_dump_ctls(devinfo, NULL, 0); 5461 hdac_dump_dac(devinfo); 5462 hdac_dump_adc(devinfo); 5463 device_printf(sc->dev, "\n"); 5464 device_printf(sc->dev, "+--------------------------------------+\n"); 5465 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5466 device_printf(sc->dev, "+--------------------------------------+\n"); 5467 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5468 ); 5469 5470 if (sc->polling != 0) { 5471 hdac_lock(sc); 5472 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5473 hdac_unlock(sc); 5474 } 5475} 5476 5477/**************************************************************************** 5478 * int hdac_detach(device_t) 5479 * 5480 * Detach and free up resources utilized by the hdac device. 5481 ****************************************************************************/ 5482static int 5483hdac_detach(device_t dev) 5484{ 5485 struct hdac_softc *sc = NULL; 5486 struct hdac_devinfo *devinfo = NULL; 5487 int err; 5488 5489 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5490 if (devinfo != NULL && devinfo->codec != NULL) 5491 sc = devinfo->codec->sc; 5492 if (sc == NULL) 5493 return (0); 5494 5495 if (sc->registered > 0) { 5496 err = pcm_unregister(dev); 5497 if (err != 0) 5498 return (err); 5499 } 5500 5501 hdac_release_resources(sc); 5502 5503 return (0); 5504} 5505 5506static device_method_t hdac_methods[] = { 5507 /* device interface */ 5508 DEVMETHOD(device_probe, hdac_probe), 5509 DEVMETHOD(device_attach, hdac_attach), 5510 DEVMETHOD(device_detach, hdac_detach), 5511 { 0, 0 } 5512}; 5513 5514static driver_t hdac_driver = { 5515 "pcm", 5516 hdac_methods, 5517 PCM_SOFTC_SIZE, 5518}; 5519 5520DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5521MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5522MODULE_VERSION(snd_hda, 1); 5523