hdac.c revision 167623
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20070316_0041" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 167623 2007-03-16 01:44:21Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* Intel */ 167#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168 169/* HP/Compaq */ 170#define HP_VENDORID 0x103c 171#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 176#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 177/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 178#define HP_NX6325_SUBVENDORX 0x103c30b0 179 180/* Dell */ 181#define DELL_VENDORID 0x1028 182#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 183#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 184#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 185 186/* Clevo */ 187#define CLEVO_VENDORID 0x1558 188#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 189#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 190 191/* Acer */ 192#define ACER_VENDORID 0x1025 193#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 194#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 195 196/* Asus */ 197#define ASUS_VENDORID 0x1043 198#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 199#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 200#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 201#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 202#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 203#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 204#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 205 206/* IBM / Lenovo */ 207#define IBM_VENDORID 0x1014 208#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 209#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 210 211/* Lenovo */ 212#define LENOVO_VENDORID 0x17aa 213#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 214#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 215 216/* Samsung */ 217#define SAMSUNG_VENDORID 0x144d 218#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 219#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 220 221/* Medion ? */ 222#define MEDION_VENDORID 0x161f 223#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 224#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 225 226/* 227 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 228 * instead of their own, which is beyond my comprehension 229 * (see HDA_CODEC_STAC9221 below). 230 */ 231#define APPLE_INTEL_MAC 0x76808384 232 233/* LG Electronics */ 234#define LG_VENDORID 0x1854 235#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 236#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 237 238/* Fujitsu Siemens */ 239#define FS_VENDORID 0x1734 240#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 241#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 242 243/* Toshiba */ 244#define TOSHIBA_VENDORID 0x1179 245#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 246#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 247 248/* Micro-Star International (MSI) */ 249#define MSI_VENDORID 0x1462 250#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 251#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 252 253/* Misc constants.. */ 254#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 255#define HDA_AMP_MUTE_NONE (0) 256#define HDA_AMP_MUTE_LEFT (1 << 0) 257#define HDA_AMP_MUTE_RIGHT (1 << 1) 258#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 259 260#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 261#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 262 263#define HDA_DAC_PATH (1 << 0) 264#define HDA_ADC_PATH (1 << 1) 265#define HDA_ADC_RECSEL (1 << 2) 266 267#define HDA_CTL_OUT (1 << 0) 268#define HDA_CTL_IN (1 << 1) 269#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 270 271#define HDA_GPIO_MAX 15 272/* 0 - 14 = GPIO */ 273#define HDA_QUIRK_GPIO0 (1 << 0) 274#define HDA_QUIRK_GPIO1 (1 << 1) 275#define HDA_QUIRK_GPIO2 (1 << 2) 276#define HDA_QUIRK_GPIOFLUSH (1 << 15) 277#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 278#define HDA_QUIRK_FIXEDRATE (1 << 17) 279#define HDA_QUIRK_FORCESTEREO (1 << 18) 280#define HDA_QUIRK_EAPDINV (1 << 19) 281#define HDA_QUIRK_VREF (1 << 20) 282 283static const struct { 284 char *key; 285 uint32_t value; 286} hdac_quirks_tab[] = { 287 { "gpio0", HDA_QUIRK_GPIO0 }, 288 { "gpio1", HDA_QUIRK_GPIO1 }, 289 { "gpio2", HDA_QUIRK_GPIO2 }, 290 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 291 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 292 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 293 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 294 { "eapdinv", HDA_QUIRK_EAPDINV }, 295 { "vref", HDA_QUIRK_VREF }, 296}; 297#define HDAC_QUIRKS_TAB_LEN \ 298 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 299 300#define HDA_BDL_MIN 2 301#define HDA_BDL_MAX 256 302#define HDA_BDL_DEFAULT HDA_BDL_MIN 303 304#define HDA_BUFSZ_MIN 4096 305#define HDA_BUFSZ_MAX 65536 306#define HDA_BUFSZ_DEFAULT 16384 307 308#define HDA_PARSE_MAXDEPTH 10 309 310#define HDAC_UNSOLTAG_EVENT_HP 0x00 311 312MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 313 314enum { 315 HDA_PARSE_MIXER, 316 HDA_PARSE_DIRECT 317}; 318 319/* Default */ 320static uint32_t hdac_fmt[] = { 321 AFMT_STEREO | AFMT_S16_LE, 322 0 323}; 324 325static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 326 327static const struct { 328 uint32_t model; 329 char *desc; 330} hdac_devices[] = { 331 { HDA_INTEL_82801F, "Intel 82801F" }, 332 { HDA_INTEL_82801G, "Intel 82801G" }, 333 { HDA_INTEL_82801H, "Intel 82801H" }, 334 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 335 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 336 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 337 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 338 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 339 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 340 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 341 { HDA_ATI_SB450, "ATI SB450" }, 342 { HDA_ATI_SB600, "ATI SB600" }, 343 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 344 { HDA_SIS_966, "SiS 966" }, 345 /* Unknown */ 346 { HDA_INTEL_ALL, "Intel (Unknown)" }, 347 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 348 { HDA_ATI_ALL, "ATI (Unknown)" }, 349 { HDA_VIA_ALL, "VIA (Unknown)" }, 350 { HDA_SIS_ALL, "SiS (Unknown)" }, 351}; 352#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 353 354static const struct { 355 uint32_t rate; 356 int valid; 357 uint16_t base; 358 uint16_t mul; 359 uint16_t div; 360} hda_rate_tab[] = { 361 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 362 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 363 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 364 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 365 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 366 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 367 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 368 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 369 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 370 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 371 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 372 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 373 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 374 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 375 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 376 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 377 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 378 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 379 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 380 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 381 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 382 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 383 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 384 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 385 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 386 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 387 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 388 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 389 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 390 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 391 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 392 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 393 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 394 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 395 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 396}; 397#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 398 399/* All codecs you can eat... */ 400#define HDA_CODEC_CONSTRUCT(vendor, id) \ 401 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 402 403/* Realtek */ 404#define REALTEK_VENDORID 0x10ec 405#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 406#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 407#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 408#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 409#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 410#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 411#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 412 413/* Analog Device */ 414#define ANALOGDEVICE_VENDORID 0x11d4 415#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 416#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 417#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 418#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 419 420/* CMedia */ 421#define CMEDIA_VENDORID 0x434d 422#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 423#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 424 425/* Sigmatel */ 426#define SIGMATEL_VENDORID 0x8384 427#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 428#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 429#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 430#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 431#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 432#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 433#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 434 435/* 436 * Conexant 437 * 438 * Ok, the truth is, I don't have any idea at all whether 439 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 440 * place that tell me it is "Venice" is from its Windows driver INF. 441 * 442 * Venice - CX????? 443 * Waikiki - CX20551-22 444 */ 445#define CONEXANT_VENDORID 0x14f1 446#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 447#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 448#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 449 450 451/* Codecs */ 452static const struct { 453 uint32_t id; 454 char *name; 455} hdac_codecs[] = { 456 { HDA_CODEC_ALC260, "Realtek ALC260" }, 457 { HDA_CODEC_ALC861, "Realtek ALC861" }, 458 { HDA_CODEC_ALC880, "Realtek ALC880" }, 459 { HDA_CODEC_ALC882, "Realtek ALC882" }, 460 { HDA_CODEC_ALC883, "Realtek ALC883" }, 461 { HDA_CODEC_ALC888, "Realtek ALC888" }, 462 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 463 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 464 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 465 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 466 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 467 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 468 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 469 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 470 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 471 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 472 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 473 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 474 /* Unknown codec */ 475 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 476 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 477 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 478 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 479 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 480}; 481#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 482 483enum { 484 HDAC_HP_SWITCH_CTL, 485 HDAC_HP_SWITCH_CTRL 486}; 487 488static const struct { 489 uint32_t model; 490 uint32_t id; 491 int type; 492 int inverted; 493 nid_t hpnid; 494 nid_t spkrnid[8]; 495 nid_t eapdnid; 496} hdac_hp_switch[] = { 497 /* Specific OEM models */ 498 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 499 17, { 16, -1 }, 16 }, 500 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 501 6, { 5, -1 }, 5 }, 502 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 503 6, { 5, -1 }, 5 }, 504 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 505 6, { 5, -1 }, 5 }, 506 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 507 6, { 5, -1 }, -1 }, 508 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 509 13, { 14, -1 }, -1 }, 510 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 511 13, { 14, -1 }, -1 }, 512 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 513 10, { 13, -1 }, -1 }, 514 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 515 26, { 27, -1 }, -1 }, 516 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 517 27, { 20, -1 }, -1 }, 518 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 519 20, { 21, -1 }, -1 }, 520 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 521 20, { 27, -1 }, -1 }, 522 /* 523 * All models that at least come from the same vendor with 524 * simmilar codec. 525 */ 526 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 527 17, { 16, -1 }, 16 }, 528 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 529 6, { 5, -1 }, 5 }, 530 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 531 6, { 5, -1 }, -1 }, 532 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 533 13, { 14, -1 }, -1 }, 534 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 535 26, { 27, -1 }, -1 }, 536#if 0 537 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 538 20, { 21, -1 }, -1 }, 539#endif 540}; 541#define HDAC_HP_SWITCH_LEN \ 542 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 543 544static const struct { 545 uint32_t model; 546 uint32_t id; 547 nid_t eapdnid; 548 int hp_switch; 549} hdac_eapd_switch[] = { 550 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 551 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 552 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 553}; 554#define HDAC_EAPD_SWITCH_LEN \ 555 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 556 557/**************************************************************************** 558 * Function prototypes 559 ****************************************************************************/ 560static void hdac_intr_handler(void *); 561static int hdac_reset(struct hdac_softc *); 562static int hdac_get_capabilities(struct hdac_softc *); 563static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 564static int hdac_dma_alloc(struct hdac_softc *, 565 struct hdac_dma *, bus_size_t); 566static void hdac_dma_free(struct hdac_dma *); 567static int hdac_mem_alloc(struct hdac_softc *); 568static void hdac_mem_free(struct hdac_softc *); 569static int hdac_irq_alloc(struct hdac_softc *); 570static void hdac_irq_free(struct hdac_softc *); 571static void hdac_corb_init(struct hdac_softc *); 572static void hdac_rirb_init(struct hdac_softc *); 573static void hdac_corb_start(struct hdac_softc *); 574static void hdac_rirb_start(struct hdac_softc *); 575static void hdac_scan_codecs(struct hdac_softc *); 576static int hdac_probe_codec(struct hdac_codec *); 577static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 578static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 579 580static void hdac_attach2(void *); 581 582static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 583 uint32_t, int); 584static void hdac_command_send_internal(struct hdac_softc *, 585 struct hdac_command_list *, int); 586 587static int hdac_probe(device_t); 588static int hdac_attach(device_t); 589static int hdac_detach(device_t); 590static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 591static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 592 uint32_t, int, int); 593static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 594 nid_t, int, int); 595static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 596 nid_t, nid_t, int, int, int, int, int, int); 597static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 598static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 599 600static int hdac_rirb_flush(struct hdac_softc *sc); 601static int hdac_unsolq_flush(struct hdac_softc *sc); 602 603#define hdac_command(a1, a2, a3) \ 604 hdac_command_sendone_internal(a1, a2, a3) 605 606#define hdac_codec_id(d) \ 607 ((uint32_t)((d == NULL) ? 0x00000000 : \ 608 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 609 ((uint32_t)(d)->device_id & 0x0000ffff)))) 610 611static char * 612hdac_codec_name(struct hdac_devinfo *devinfo) 613{ 614 uint32_t id; 615 int i; 616 617 id = hdac_codec_id(devinfo); 618 619 for (i = 0; i < HDAC_CODECS_LEN; i++) { 620 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 621 return (hdac_codecs[i].name); 622 } 623 624 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 625} 626 627static char * 628hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 629{ 630 static char *ossname[] = SOUND_DEVICE_NAMES; 631 static char *unknown = "???"; 632 int i; 633 634 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 635 if (devmask & (1 << i)) 636 return (ossname[i]); 637 } 638 return (unknown); 639} 640 641static void 642hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 643{ 644 static char *ossname[] = SOUND_DEVICE_NAMES; 645 int i, first = 1; 646 647 bzero(buf, len); 648 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 649 if (mask & (1 << i)) { 650 if (first == 0) 651 strlcat(buf, ", ", len); 652 strlcat(buf, ossname[i], len); 653 first = 0; 654 } 655 } 656} 657 658static struct hdac_audio_ctl * 659hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 660{ 661 if (devinfo == NULL || 662 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 663 index == NULL || devinfo->function.audio.ctl == NULL || 664 devinfo->function.audio.ctlcnt < 1 || 665 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 666 return (NULL); 667 return (&devinfo->function.audio.ctl[(*index)++]); 668} 669 670static struct hdac_audio_ctl * 671hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 672 int index, int cnt) 673{ 674 struct hdac_audio_ctl *ctl, *retctl = NULL; 675 int i, at, atindex, found = 0; 676 677 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 678 return (NULL); 679 680 at = cnt; 681 if (at == 0) 682 at = 1; 683 else if (at < 0) 684 at = -1; 685 atindex = index; 686 if (atindex < 0) 687 atindex = -1; 688 689 i = 0; 690 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 691 if (ctl->enable == 0 || ctl->widget == NULL) 692 continue; 693 if (!(ctl->widget->nid == nid && (atindex == -1 || 694 ctl->index == atindex))) 695 continue; 696 found++; 697 if (found == cnt) 698 return (ctl); 699 retctl = ctl; 700 } 701 702 return ((at == -1) ? retctl : NULL); 703} 704 705static void 706hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 707{ 708 struct hdac_softc *sc; 709 struct hdac_widget *w; 710 struct hdac_audio_ctl *ctl; 711 uint32_t id, res; 712 int i = 0, j, forcemute; 713 nid_t cad; 714 715 if (devinfo == NULL || devinfo->codec == NULL || 716 devinfo->codec->sc == NULL) 717 return; 718 719 sc = devinfo->codec->sc; 720 cad = devinfo->codec->cad; 721 id = hdac_codec_id(devinfo); 722 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 723 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 724 sc->pci_subvendor) && 725 hdac_hp_switch[i].id == id) 726 break; 727 } 728 729 if (i >= HDAC_HP_SWITCH_LEN) 730 return; 731 732 forcemute = 0; 733 if (hdac_hp_switch[i].eapdnid != -1) { 734 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 735 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 736 forcemute = (w->param.eapdbtl & 737 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 738 } 739 740 res = hdac_command(sc, 741 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 742 HDA_BOOTVERBOSE( 743 device_printf(sc->dev, 744 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 745 hdac_hp_switch[i].hpnid, res); 746 ); 747 res >>= 31; 748 res ^= hdac_hp_switch[i].inverted; 749 750 switch (hdac_hp_switch[i].type) { 751 case HDAC_HP_SWITCH_CTL: 752 ctl = hdac_audio_ctl_amp_get(devinfo, 753 hdac_hp_switch[i].hpnid, 0, 1); 754 if (ctl != NULL) { 755 ctl->muted = (res != 0 && forcemute == 0) ? 756 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 757 hdac_audio_ctl_amp_set(ctl, 758 HDA_AMP_MUTE_DEFAULT, ctl->left, 759 ctl->right); 760 } 761 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 762 ctl = hdac_audio_ctl_amp_get(devinfo, 763 hdac_hp_switch[i].spkrnid[j], 0, 1); 764 if (ctl != NULL) { 765 ctl->muted = (res != 0 || forcemute == 1) ? 766 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 767 hdac_audio_ctl_amp_set(ctl, 768 HDA_AMP_MUTE_DEFAULT, ctl->left, 769 ctl->right); 770 } 771 } 772 break; 773 case HDAC_HP_SWITCH_CTRL: 774 if (res != 0) { 775 /* HP in */ 776 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 777 if (w != NULL && w->type == 778 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 779 if (forcemute == 0) 780 w->wclass.pin.ctrl |= 781 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 782 else 783 w->wclass.pin.ctrl &= 784 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 785 hdac_command(sc, 786 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 787 w->wclass.pin.ctrl), cad); 788 } 789 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 790 w = hdac_widget_get(devinfo, 791 hdac_hp_switch[i].spkrnid[j]); 792 if (w != NULL && w->type == 793 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 794 w->wclass.pin.ctrl &= 795 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 796 hdac_command(sc, 797 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 798 w->nid, 799 w->wclass.pin.ctrl), cad); 800 } 801 } 802 } else { 803 /* HP out */ 804 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 805 if (w != NULL && w->type == 806 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 807 w->wclass.pin.ctrl &= 808 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 809 hdac_command(sc, 810 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 811 w->wclass.pin.ctrl), cad); 812 } 813 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 814 w = hdac_widget_get(devinfo, 815 hdac_hp_switch[i].spkrnid[j]); 816 if (w != NULL && w->type == 817 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 818 if (forcemute == 0) 819 w->wclass.pin.ctrl |= 820 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 821 else 822 w->wclass.pin.ctrl &= 823 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 824 hdac_command(sc, 825 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 826 w->nid, 827 w->wclass.pin.ctrl), cad); 828 } 829 } 830 } 831 break; 832 default: 833 break; 834 } 835} 836 837static void 838hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 839{ 840 struct hdac_softc *sc; 841 struct hdac_devinfo *devinfo = NULL; 842 device_t *devlist = NULL; 843 int devcount, i; 844 845 if (codec == NULL || codec->sc == NULL) 846 return; 847 848 sc = codec->sc; 849 850 HDA_BOOTVERBOSE( 851 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 852 ); 853 854 device_get_children(sc->dev, &devlist, &devcount); 855 for (i = 0; devlist != NULL && i < devcount; i++) { 856 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 857 if (devinfo != NULL && devinfo->node_type == 858 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 859 devinfo->codec != NULL && 860 devinfo->codec->cad == codec->cad) { 861 break; 862 } else 863 devinfo = NULL; 864 } 865 if (devlist != NULL) 866 free(devlist, M_TEMP); 867 868 if (devinfo == NULL) 869 return; 870 871 switch (tag) { 872 case HDAC_UNSOLTAG_EVENT_HP: 873 hdac_hp_switch_handler(devinfo); 874 break; 875 default: 876 break; 877 } 878} 879 880static int 881hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 882{ 883 /* XXX to be removed */ 884#ifdef HDAC_INTR_EXTRA 885 uint32_t res; 886#endif 887 888 if (ch->blkcnt == 0) 889 return (0); 890 891 /* XXX to be removed */ 892#ifdef HDAC_INTR_EXTRA 893 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 894#endif 895 896 /* XXX to be removed */ 897#ifdef HDAC_INTR_EXTRA 898 HDA_BOOTVERBOSE( 899 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 900 device_printf(sc->dev, 901 "PCMDIR_%s intr triggered beyond stream boundary:" 902 "%08x\n", 903 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 904 ); 905#endif 906 907 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 908 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 909 910 /* XXX to be removed */ 911#ifdef HDAC_INTR_EXTRA 912 if (res & HDAC_SDSTS_BCIS) { 913#endif 914 return (1); 915 /* XXX to be removed */ 916#ifdef HDAC_INTR_EXTRA 917 } 918#endif 919 920 return (0); 921} 922 923/**************************************************************************** 924 * void hdac_intr_handler(void *) 925 * 926 * Interrupt handler. Processes interrupts received from the hdac. 927 ****************************************************************************/ 928static void 929hdac_intr_handler(void *context) 930{ 931 struct hdac_softc *sc; 932 uint32_t intsts; 933 uint8_t rirbsts; 934 struct hdac_rirb *rirb_base; 935 uint32_t trigger = 0; 936 937 sc = (struct hdac_softc *)context; 938 939 hdac_lock(sc); 940 if (sc->polling != 0) { 941 hdac_unlock(sc); 942 return; 943 } 944 /* Do we have anything to do? */ 945 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 946 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 947 hdac_unlock(sc); 948 return; 949 } 950 951 /* Was this a controller interrupt? */ 952 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 953 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 954 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 955 /* Get as many responses that we can */ 956 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 957 HDAC_WRITE_1(&sc->mem, 958 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 959 hdac_rirb_flush(sc); 960 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 961 } 962 /* XXX to be removed */ 963 /* Clear interrupt and exit */ 964#ifdef HDAC_INTR_EXTRA 965 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 966#endif 967 } 968 969 hdac_unsolq_flush(sc); 970 971 if (intsts & HDAC_INTSTS_SIS_MASK) { 972 if ((intsts & (1 << sc->num_iss)) && 973 hdac_stream_intr(sc, &sc->play) != 0) 974 trigger |= 1; 975 if ((intsts & (1 << 0)) && 976 hdac_stream_intr(sc, &sc->rec) != 0) 977 trigger |= 2; 978 /* XXX to be removed */ 979#ifdef HDAC_INTR_EXTRA 980 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 981 HDAC_INTSTS_SIS_MASK); 982#endif 983 } 984 985 hdac_unlock(sc); 986 987 if (trigger & 1) 988 chn_intr(sc->play.c); 989 if (trigger & 2) 990 chn_intr(sc->rec.c); 991} 992 993/**************************************************************************** 994 * int hdac_reset(hdac_softc *) 995 * 996 * Reset the hdac to a quiescent and known state. 997 ****************************************************************************/ 998static int 999hdac_reset(struct hdac_softc *sc) 1000{ 1001 uint32_t gctl; 1002 int count, i; 1003 1004 /* 1005 * Stop all Streams DMA engine 1006 */ 1007 for (i = 0; i < sc->num_iss; i++) 1008 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1009 for (i = 0; i < sc->num_oss; i++) 1010 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1011 for (i = 0; i < sc->num_bss; i++) 1012 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1013 1014 /* 1015 * Stop Control DMA engines 1016 */ 1017 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1018 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1019 1020 /* 1021 * Reset the controller. The reset must remain asserted for 1022 * a minimum of 100us. 1023 */ 1024 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1025 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1026 count = 10000; 1027 do { 1028 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1029 if (!(gctl & HDAC_GCTL_CRST)) 1030 break; 1031 DELAY(10); 1032 } while (--count); 1033 if (gctl & HDAC_GCTL_CRST) { 1034 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1035 return (ENXIO); 1036 } 1037 DELAY(100); 1038 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1039 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1040 count = 10000; 1041 do { 1042 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1043 if (gctl & HDAC_GCTL_CRST) 1044 break; 1045 DELAY(10); 1046 } while (--count); 1047 if (!(gctl & HDAC_GCTL_CRST)) { 1048 device_printf(sc->dev, "Device stuck in reset\n"); 1049 return (ENXIO); 1050 } 1051 1052 /* 1053 * Wait for codecs to finish their own reset sequence. The delay here 1054 * should be of 250us but for some reasons, on it's not enough on my 1055 * computer. Let's use twice as much as necessary to make sure that 1056 * it's reset properly. 1057 */ 1058 DELAY(1000); 1059 1060 return (0); 1061} 1062 1063 1064/**************************************************************************** 1065 * int hdac_get_capabilities(struct hdac_softc *); 1066 * 1067 * Retreive the general capabilities of the hdac; 1068 * Number of Input Streams 1069 * Number of Output Streams 1070 * Number of bidirectional Streams 1071 * 64bit ready 1072 * CORB and RIRB sizes 1073 ****************************************************************************/ 1074static int 1075hdac_get_capabilities(struct hdac_softc *sc) 1076{ 1077 uint16_t gcap; 1078 uint8_t corbsize, rirbsize; 1079 1080 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1081 sc->num_iss = HDAC_GCAP_ISS(gcap); 1082 sc->num_oss = HDAC_GCAP_OSS(gcap); 1083 sc->num_bss = HDAC_GCAP_BSS(gcap); 1084 1085 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1086 1087 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1088 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1089 HDAC_CORBSIZE_CORBSZCAP_256) 1090 sc->corb_size = 256; 1091 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1092 HDAC_CORBSIZE_CORBSZCAP_16) 1093 sc->corb_size = 16; 1094 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1095 HDAC_CORBSIZE_CORBSZCAP_2) 1096 sc->corb_size = 2; 1097 else { 1098 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1099 __func__, corbsize); 1100 return (ENXIO); 1101 } 1102 1103 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1104 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1105 HDAC_RIRBSIZE_RIRBSZCAP_256) 1106 sc->rirb_size = 256; 1107 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1108 HDAC_RIRBSIZE_RIRBSZCAP_16) 1109 sc->rirb_size = 16; 1110 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1111 HDAC_RIRBSIZE_RIRBSZCAP_2) 1112 sc->rirb_size = 2; 1113 else { 1114 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1115 __func__, rirbsize); 1116 return (ENXIO); 1117 } 1118 1119 return (0); 1120} 1121 1122 1123/**************************************************************************** 1124 * void hdac_dma_cb 1125 * 1126 * This function is called by bus_dmamap_load when the mapping has been 1127 * established. We just record the physical address of the mapping into 1128 * the struct hdac_dma passed in. 1129 ****************************************************************************/ 1130static void 1131hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1132{ 1133 struct hdac_dma *dma; 1134 1135 if (error == 0) { 1136 dma = (struct hdac_dma *)callback_arg; 1137 dma->dma_paddr = segs[0].ds_addr; 1138 } 1139} 1140 1141static void 1142hdac_dma_nocache(void *ptr) 1143{ 1144#if 0 1145#if defined(__i386__) || defined(__amd64__) 1146 pt_entry_t *pte; 1147 vm_offset_t va; 1148 1149 va = (vm_offset_t)ptr; 1150 pte = vtopte(va); 1151 if (pte) { 1152 *pte |= PG_N; 1153 invltlb(); 1154 } 1155#endif 1156#endif 1157} 1158 1159/**************************************************************************** 1160 * int hdac_dma_alloc 1161 * 1162 * This function allocate and setup a dma region (struct hdac_dma). 1163 * It must be freed by a corresponding hdac_dma_free. 1164 ****************************************************************************/ 1165static int 1166hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1167{ 1168 int result; 1169 int lowaddr; 1170 1171 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1172 BUS_SPACE_MAXADDR_32BIT; 1173 bzero(dma, sizeof(*dma)); 1174 1175 /* 1176 * Create a DMA tag 1177 */ 1178 result = bus_dma_tag_create(NULL, /* parent */ 1179 HDAC_DMA_ALIGNMENT, /* alignment */ 1180 0, /* boundary */ 1181 lowaddr, /* lowaddr */ 1182 BUS_SPACE_MAXADDR, /* highaddr */ 1183 NULL, /* filtfunc */ 1184 NULL, /* fistfuncarg */ 1185 size, /* maxsize */ 1186 1, /* nsegments */ 1187 size, /* maxsegsz */ 1188 0, /* flags */ 1189 NULL, /* lockfunc */ 1190 NULL, /* lockfuncarg */ 1191 &dma->dma_tag); /* dmat */ 1192 if (result != 0) { 1193 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1194 __func__, result); 1195 goto fail; 1196 } 1197 1198 /* 1199 * Allocate DMA memory 1200 */ 1201 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1202 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1203 if (result != 0) { 1204 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1205 __func__, result); 1206 goto fail; 1207 } 1208 1209 /* 1210 * Map the memory 1211 */ 1212 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1213 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1214 BUS_DMA_NOWAIT); 1215 if (result != 0 || dma->dma_paddr == 0) { 1216 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1217 __func__, result); 1218 goto fail; 1219 } 1220 bzero((void *)dma->dma_vaddr, size); 1221 hdac_dma_nocache(dma->dma_vaddr); 1222 1223 return (0); 1224fail: 1225 if (dma->dma_map != NULL) 1226 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1227 if (dma->dma_tag != NULL) 1228 bus_dma_tag_destroy(dma->dma_tag); 1229 return (result); 1230} 1231 1232 1233/**************************************************************************** 1234 * void hdac_dma_free(struct hdac_dma *) 1235 * 1236 * Free a struct dhac_dma that has been previously allocated via the 1237 * hdac_dma_alloc function. 1238 ****************************************************************************/ 1239static void 1240hdac_dma_free(struct hdac_dma *dma) 1241{ 1242 if (dma->dma_tag != NULL) { 1243 /* Flush caches */ 1244 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1245 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1246 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1247 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1248 bus_dma_tag_destroy(dma->dma_tag); 1249 } 1250} 1251 1252/**************************************************************************** 1253 * int hdac_mem_alloc(struct hdac_softc *) 1254 * 1255 * Allocate all the bus resources necessary to speak with the physical 1256 * controller. 1257 ****************************************************************************/ 1258static int 1259hdac_mem_alloc(struct hdac_softc *sc) 1260{ 1261 struct hdac_mem *mem; 1262 1263 mem = &sc->mem; 1264 mem->mem_rid = PCIR_BAR(0); 1265 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1266 &mem->mem_rid, RF_ACTIVE); 1267 if (mem->mem_res == NULL) { 1268 device_printf(sc->dev, 1269 "%s: Unable to allocate memory resource\n", __func__); 1270 return (ENOMEM); 1271 } 1272 mem->mem_tag = rman_get_bustag(mem->mem_res); 1273 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1274 1275 return (0); 1276} 1277 1278/**************************************************************************** 1279 * void hdac_mem_free(struct hdac_softc *) 1280 * 1281 * Free up resources previously allocated by hdac_mem_alloc. 1282 ****************************************************************************/ 1283static void 1284hdac_mem_free(struct hdac_softc *sc) 1285{ 1286 struct hdac_mem *mem; 1287 1288 mem = &sc->mem; 1289 if (mem->mem_res != NULL) 1290 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1291 mem->mem_res); 1292 mem->mem_res = NULL; 1293} 1294 1295/**************************************************************************** 1296 * int hdac_irq_alloc(struct hdac_softc *) 1297 * 1298 * Allocate and setup the resources necessary for interrupt handling. 1299 ****************************************************************************/ 1300static int 1301hdac_irq_alloc(struct hdac_softc *sc) 1302{ 1303 struct hdac_irq *irq; 1304 int result; 1305 1306 irq = &sc->irq; 1307 irq->irq_rid = 0x0; 1308 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1309 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1310 if (irq->irq_res == NULL) { 1311 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1312 __func__); 1313 goto fail; 1314 } 1315 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1316 hdac_intr_handler, sc, &irq->irq_handle); 1317 if (result != 0) { 1318 device_printf(sc->dev, 1319 "%s: Unable to setup interrupt handler (%x)\n", 1320 __func__, result); 1321 goto fail; 1322 } 1323 1324 return (0); 1325 1326fail: 1327 hdac_irq_free(sc); 1328 1329 return (ENXIO); 1330} 1331 1332/**************************************************************************** 1333 * void hdac_irq_free(struct hdac_softc *) 1334 * 1335 * Free up resources previously allocated by hdac_irq_alloc. 1336 ****************************************************************************/ 1337static void 1338hdac_irq_free(struct hdac_softc *sc) 1339{ 1340 struct hdac_irq *irq; 1341 1342 irq = &sc->irq; 1343 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1344 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1345 if (irq->irq_res != NULL) 1346 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1347 irq->irq_res); 1348 irq->irq_handle = NULL; 1349 irq->irq_res = NULL; 1350} 1351 1352/**************************************************************************** 1353 * void hdac_corb_init(struct hdac_softc *) 1354 * 1355 * Initialize the corb registers for operations but do not start it up yet. 1356 * The CORB engine must not be running when this function is called. 1357 ****************************************************************************/ 1358static void 1359hdac_corb_init(struct hdac_softc *sc) 1360{ 1361 uint8_t corbsize; 1362 uint64_t corbpaddr; 1363 1364 /* Setup the CORB size. */ 1365 switch (sc->corb_size) { 1366 case 256: 1367 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1368 break; 1369 case 16: 1370 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1371 break; 1372 case 2: 1373 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1374 break; 1375 default: 1376 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1377 } 1378 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1379 1380 /* Setup the CORB Address in the hdac */ 1381 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1382 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1383 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1384 1385 /* Set the WP and RP */ 1386 sc->corb_wp = 0; 1387 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1388 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1389 /* 1390 * The HDA specification indicates that the CORBRPRST bit will always 1391 * read as zero. Unfortunately, it seems that at least the 82801G 1392 * doesn't reset the bit to zero, which stalls the corb engine. 1393 * manually reset the bit to zero before continuing. 1394 */ 1395 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1396 1397 /* Enable CORB error reporting */ 1398#if 0 1399 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1400#endif 1401} 1402 1403/**************************************************************************** 1404 * void hdac_rirb_init(struct hdac_softc *) 1405 * 1406 * Initialize the rirb registers for operations but do not start it up yet. 1407 * The RIRB engine must not be running when this function is called. 1408 ****************************************************************************/ 1409static void 1410hdac_rirb_init(struct hdac_softc *sc) 1411{ 1412 uint8_t rirbsize; 1413 uint64_t rirbpaddr; 1414 1415 /* Setup the RIRB size. */ 1416 switch (sc->rirb_size) { 1417 case 256: 1418 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1419 break; 1420 case 16: 1421 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1422 break; 1423 case 2: 1424 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1425 break; 1426 default: 1427 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1428 } 1429 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1430 1431 /* Setup the RIRB Address in the hdac */ 1432 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1433 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1434 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1435 1436 /* Setup the WP and RP */ 1437 sc->rirb_rp = 0; 1438 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1439 1440 if (sc->polling == 0) { 1441 /* Setup the interrupt threshold */ 1442 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1443 1444 /* Enable Overrun and response received reporting */ 1445#if 0 1446 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1447 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1448#else 1449 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1450#endif 1451 } 1452 1453 /* 1454 * Make sure that the Host CPU cache doesn't contain any dirty 1455 * cache lines that falls in the rirb. If I understood correctly, it 1456 * should be sufficient to do this only once as the rirb is purely 1457 * read-only from now on. 1458 */ 1459 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1460 BUS_DMASYNC_PREREAD); 1461} 1462 1463/**************************************************************************** 1464 * void hdac_corb_start(hdac_softc *) 1465 * 1466 * Startup the corb DMA engine 1467 ****************************************************************************/ 1468static void 1469hdac_corb_start(struct hdac_softc *sc) 1470{ 1471 uint32_t corbctl; 1472 1473 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1474 corbctl |= HDAC_CORBCTL_CORBRUN; 1475 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1476} 1477 1478/**************************************************************************** 1479 * void hdac_rirb_start(hdac_softc *) 1480 * 1481 * Startup the rirb DMA engine 1482 ****************************************************************************/ 1483static void 1484hdac_rirb_start(struct hdac_softc *sc) 1485{ 1486 uint32_t rirbctl; 1487 1488 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1489 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1490 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1491} 1492 1493 1494/**************************************************************************** 1495 * void hdac_scan_codecs(struct hdac_softc *) 1496 * 1497 * Scan the bus for available codecs. 1498 ****************************************************************************/ 1499static void 1500hdac_scan_codecs(struct hdac_softc *sc) 1501{ 1502 struct hdac_codec *codec; 1503 int i; 1504 uint16_t statests; 1505 1506 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1507 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1508 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1509 /* We have found a codec. */ 1510 hdac_unlock(sc); 1511 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1512 M_HDAC, M_ZERO | M_NOWAIT); 1513 hdac_lock(sc); 1514 if (codec == NULL) { 1515 device_printf(sc->dev, 1516 "Unable to allocate memory for codec\n"); 1517 continue; 1518 } 1519 codec->commands = NULL; 1520 codec->responses_received = 0; 1521 codec->verbs_sent = 0; 1522 codec->sc = sc; 1523 codec->cad = i; 1524 sc->codecs[i] = codec; 1525 if (hdac_probe_codec(codec) != 0) 1526 break; 1527 } 1528 } 1529 /* All codecs have been probed, now try to attach drivers to them */ 1530 /* bus_generic_attach(sc->dev); */ 1531} 1532 1533/**************************************************************************** 1534 * void hdac_probe_codec(struct hdac_softc *, int) 1535 * 1536 * Probe a the given codec_id for available function groups. 1537 ****************************************************************************/ 1538static int 1539hdac_probe_codec(struct hdac_codec *codec) 1540{ 1541 struct hdac_softc *sc = codec->sc; 1542 struct hdac_devinfo *devinfo; 1543 uint32_t vendorid, revisionid, subnode; 1544 int startnode; 1545 int endnode; 1546 int i; 1547 nid_t cad = codec->cad; 1548 1549 HDA_BOOTVERBOSE( 1550 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1551 ); 1552 vendorid = hdac_command(sc, 1553 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1554 cad); 1555 revisionid = hdac_command(sc, 1556 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1557 cad); 1558 subnode = hdac_command(sc, 1559 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1560 cad); 1561 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1562 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1563 1564 HDA_BOOTVERBOSE( 1565 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1566 startnode, endnode); 1567 ); 1568 for (i = startnode; i < endnode; i++) { 1569 devinfo = hdac_probe_function(codec, i); 1570 if (devinfo != NULL) { 1571 /* XXX Ignore other FG. */ 1572 devinfo->vendor_id = 1573 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1574 devinfo->device_id = 1575 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1576 devinfo->revision_id = 1577 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1578 devinfo->stepping_id = 1579 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1580 HDA_BOOTVERBOSE( 1581 device_printf(sc->dev, 1582 "HDA_DEBUG: \tFound AFG nid=%d " 1583 "[startnode=%d endnode=%d]\n", 1584 devinfo->nid, startnode, endnode); 1585 ); 1586 return (1); 1587 } 1588 } 1589 1590 HDA_BOOTVERBOSE( 1591 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1592 ); 1593 return (0); 1594} 1595 1596static struct hdac_devinfo * 1597hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1598{ 1599 struct hdac_softc *sc = codec->sc; 1600 struct hdac_devinfo *devinfo; 1601 uint32_t fctgrptype; 1602 nid_t cad = codec->cad; 1603 1604 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1605 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1606 1607 /* XXX For now, ignore other FG. */ 1608 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1609 return (NULL); 1610 1611 hdac_unlock(sc); 1612 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1613 M_NOWAIT | M_ZERO); 1614 hdac_lock(sc); 1615 if (devinfo == NULL) { 1616 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1617 __func__); 1618 return (NULL); 1619 } 1620 1621 devinfo->nid = nid; 1622 devinfo->node_type = fctgrptype; 1623 devinfo->codec = codec; 1624 1625 hdac_add_child(sc, devinfo); 1626 1627 return (devinfo); 1628} 1629 1630static void 1631hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1632{ 1633 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1634 device_set_ivars(devinfo->dev, (void *)devinfo); 1635 /* XXX - Print more information when booting verbose??? */ 1636} 1637 1638static void 1639hdac_widget_connection_parse(struct hdac_widget *w) 1640{ 1641 struct hdac_softc *sc = w->devinfo->codec->sc; 1642 uint32_t res; 1643 int i, j, max, found, entnum, cnid; 1644 nid_t cad = w->devinfo->codec->cad; 1645 nid_t nid = w->nid; 1646 1647 res = hdac_command(sc, 1648 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1649 1650 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1651 1652 if (w->nconns < 1) 1653 return; 1654 1655 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1656 res = 0; 1657 i = 0; 1658 found = 0; 1659 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1660 1661 while (i < w->nconns) { 1662 res = hdac_command(sc, 1663 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1664 for (j = 0; j < entnum; j++) { 1665 cnid = res; 1666 cnid >>= (32 / entnum) * j; 1667 cnid &= (1 << (32 / entnum)) - 1; 1668 if (cnid == 0) 1669 continue; 1670 if (found > max) { 1671 device_printf(sc->dev, 1672 "node %d: Adding %d: " 1673 "Max connection reached!\n", 1674 nid, cnid); 1675 continue; 1676 } 1677 w->conns[found++] = cnid; 1678 } 1679 i += entnum; 1680 } 1681 1682 HDA_BOOTVERBOSE( 1683 if (w->nconns != found) { 1684 device_printf(sc->dev, 1685 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1686 "length=%d != found=%d\n", 1687 nid, w->nconns, found); 1688 } 1689 ); 1690} 1691 1692static uint32_t 1693hdac_widget_pin_getconfig(struct hdac_widget *w) 1694{ 1695 struct hdac_softc *sc; 1696 uint32_t config, orig, id; 1697 nid_t cad, nid; 1698 1699 sc = w->devinfo->codec->sc; 1700 cad = w->devinfo->codec->cad; 1701 nid = w->nid; 1702 id = hdac_codec_id(w->devinfo); 1703 1704 config = hdac_command(sc, 1705 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1706 cad); 1707 orig = config; 1708 1709 /* 1710 * XXX REWRITE!!!! Don't argue! 1711 */ 1712 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1713 switch (nid) { 1714 case 26: 1715 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1716 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1717 break; 1718 case 27: 1719 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1720 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1721 break; 1722 default: 1723 break; 1724 } 1725 } else if (id == HDA_CODEC_ALC880 && 1726 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1727 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1728 /* 1729 * Super broken BIOS 1730 */ 1731 switch (nid) { 1732 case 20: 1733 break; 1734 case 21: 1735 break; 1736 case 22: 1737 break; 1738 case 23: 1739 break; 1740 case 24: /* MIC1 */ 1741 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1742 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1743 break; 1744 case 25: /* XXX MIC2 */ 1745 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1746 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1747 break; 1748 case 26: /* LINE1 */ 1749 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1750 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1751 break; 1752 case 27: /* XXX LINE2 */ 1753 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1754 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1755 break; 1756 case 28: /* CD */ 1757 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1758 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1759 break; 1760 case 30: 1761 break; 1762 case 31: 1763 break; 1764 default: 1765 break; 1766 } 1767 } else if (id == HDA_CODEC_ALC883 && 1768 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1769 switch (nid) { 1770 case 25: 1771 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1772 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1773 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1774 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1775 break; 1776 default: 1777 break; 1778 } 1779 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1780 HP_V3000_SUBVENDOR) { 1781 switch (nid) { 1782 case 18: 1783 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1784 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1785 break; 1786 case 20: 1787 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1788 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1789 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1790 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1791 break; 1792 case 21: 1793 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1794 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1795 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1796 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1797 break; 1798 default: 1799 break; 1800 } 1801 } 1802 1803 HDA_BOOTVERBOSE( 1804 if (config != orig) 1805 device_printf(sc->dev, 1806 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 1807 nid, orig, config); 1808 ); 1809 1810 return (config); 1811} 1812 1813static uint32_t 1814hdac_widget_pin_getcaps(struct hdac_widget *w) 1815{ 1816 struct hdac_softc *sc; 1817 uint32_t caps, orig, id; 1818 nid_t cad, nid; 1819 1820 sc = w->devinfo->codec->sc; 1821 cad = w->devinfo->codec->cad; 1822 nid = w->nid; 1823 id = hdac_codec_id(w->devinfo); 1824 1825 caps = hdac_command(sc, 1826 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1827 orig = caps; 1828 1829 HDA_BOOTVERBOSE( 1830 if (caps != orig) 1831 device_printf(sc->dev, 1832 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 1833 nid, orig, caps); 1834 ); 1835 1836 return (caps); 1837} 1838 1839static void 1840hdac_widget_pin_parse(struct hdac_widget *w) 1841{ 1842 struct hdac_softc *sc = w->devinfo->codec->sc; 1843 uint32_t config, pincap; 1844 char *devstr, *connstr; 1845 nid_t cad = w->devinfo->codec->cad; 1846 nid_t nid = w->nid; 1847 1848 config = hdac_widget_pin_getconfig(w); 1849 w->wclass.pin.config = config; 1850 1851 pincap = hdac_widget_pin_getcaps(w); 1852 w->wclass.pin.cap = pincap; 1853 1854 w->wclass.pin.ctrl = hdac_command(sc, 1855 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1856 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1857 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1858 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1859 1860 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1861 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1862 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1863 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1864 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1865 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1866 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1867 w->param.eapdbtl = hdac_command(sc, 1868 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1869 w->param.eapdbtl &= 0x7; 1870 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1871 } else 1872 w->param.eapdbtl = HDAC_INVALID; 1873 1874 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1875 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1876 devstr = "line out"; 1877 break; 1878 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1879 devstr = "speaker"; 1880 break; 1881 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1882 devstr = "headphones out"; 1883 break; 1884 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1885 devstr = "CD"; 1886 break; 1887 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1888 devstr = "SPDIF out"; 1889 break; 1890 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1891 devstr = "digital (other) out"; 1892 break; 1893 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1894 devstr = "modem, line side"; 1895 break; 1896 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1897 devstr = "modem, handset side"; 1898 break; 1899 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1900 devstr = "line in"; 1901 break; 1902 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1903 devstr = "AUX"; 1904 break; 1905 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1906 devstr = "Mic in"; 1907 break; 1908 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1909 devstr = "telephony"; 1910 break; 1911 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1912 devstr = "SPDIF in"; 1913 break; 1914 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1915 devstr = "digital (other) in"; 1916 break; 1917 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1918 devstr = "other"; 1919 break; 1920 default: 1921 devstr = "unknown"; 1922 break; 1923 } 1924 1925 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1926 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1927 connstr = "jack"; 1928 break; 1929 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1930 connstr = "none"; 1931 break; 1932 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1933 connstr = "fixed"; 1934 break; 1935 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1936 connstr = "jack / fixed"; 1937 break; 1938 default: 1939 connstr = "unknown"; 1940 break; 1941 } 1942 1943 strlcat(w->name, ": ", sizeof(w->name)); 1944 strlcat(w->name, devstr, sizeof(w->name)); 1945 strlcat(w->name, " (", sizeof(w->name)); 1946 strlcat(w->name, connstr, sizeof(w->name)); 1947 strlcat(w->name, ")", sizeof(w->name)); 1948} 1949 1950static void 1951hdac_widget_parse(struct hdac_widget *w) 1952{ 1953 struct hdac_softc *sc = w->devinfo->codec->sc; 1954 uint32_t wcap, cap; 1955 char *typestr; 1956 nid_t cad = w->devinfo->codec->cad; 1957 nid_t nid = w->nid; 1958 1959 wcap = hdac_command(sc, 1960 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1961 cad); 1962 w->param.widget_cap = wcap; 1963 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1964 1965 switch (w->type) { 1966 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1967 typestr = "audio output"; 1968 break; 1969 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1970 typestr = "audio input"; 1971 break; 1972 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1973 typestr = "audio mixer"; 1974 break; 1975 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1976 typestr = "audio selector"; 1977 break; 1978 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1979 typestr = "pin"; 1980 break; 1981 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1982 typestr = "power widget"; 1983 break; 1984 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1985 typestr = "volume widget"; 1986 break; 1987 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1988 typestr = "beep widget"; 1989 break; 1990 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1991 typestr = "vendor widget"; 1992 break; 1993 default: 1994 typestr = "unknown type"; 1995 break; 1996 } 1997 1998 strlcpy(w->name, typestr, sizeof(w->name)); 1999 2000 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2001 hdac_command(sc, 2002 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2003 cad); 2004 DELAY(1000); 2005 } 2006 2007 hdac_widget_connection_parse(w); 2008 2009 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2010 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2011 w->param.outamp_cap = 2012 hdac_command(sc, 2013 HDA_CMD_GET_PARAMETER(cad, nid, 2014 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2015 else 2016 w->param.outamp_cap = 2017 w->devinfo->function.audio.outamp_cap; 2018 } else 2019 w->param.outamp_cap = 0; 2020 2021 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2022 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2023 w->param.inamp_cap = 2024 hdac_command(sc, 2025 HDA_CMD_GET_PARAMETER(cad, nid, 2026 HDA_PARAM_INPUT_AMP_CAP), cad); 2027 else 2028 w->param.inamp_cap = 2029 w->devinfo->function.audio.inamp_cap; 2030 } else 2031 w->param.inamp_cap = 0; 2032 2033 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2034 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2035 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2036 cap = hdac_command(sc, 2037 HDA_CMD_GET_PARAMETER(cad, nid, 2038 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2039 w->param.supp_stream_formats = (cap != 0) ? cap : 2040 w->devinfo->function.audio.supp_stream_formats; 2041 cap = hdac_command(sc, 2042 HDA_CMD_GET_PARAMETER(cad, nid, 2043 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2044 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2045 w->devinfo->function.audio.supp_pcm_size_rate; 2046 } else { 2047 w->param.supp_stream_formats = 2048 w->devinfo->function.audio.supp_stream_formats; 2049 w->param.supp_pcm_size_rate = 2050 w->devinfo->function.audio.supp_pcm_size_rate; 2051 } 2052 } else { 2053 w->param.supp_stream_formats = 0; 2054 w->param.supp_pcm_size_rate = 0; 2055 } 2056 2057 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2058 hdac_widget_pin_parse(w); 2059} 2060 2061static struct hdac_widget * 2062hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2063{ 2064 if (devinfo == NULL || devinfo->widget == NULL || 2065 nid < devinfo->startnode || nid >= devinfo->endnode) 2066 return (NULL); 2067 return (&devinfo->widget[nid - devinfo->startnode]); 2068} 2069 2070static __inline int 2071hda_poll_channel(struct hdac_chan *ch) 2072{ 2073 uint32_t sz, delta; 2074 volatile uint32_t ptr; 2075 2076 if (ch->active == 0) 2077 return (0); 2078 2079 sz = ch->blksz * ch->blkcnt; 2080 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2081 ch->ptr = ptr; 2082 ptr %= sz; 2083 ptr &= ~(ch->blksz - 1); 2084 delta = (sz + ptr - ch->prevptr) % sz; 2085 2086 if (delta < ch->blksz) 2087 return (0); 2088 2089 ch->prevptr = ptr; 2090 2091 return (1); 2092} 2093 2094#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2095 2096static void 2097hda_poll_callback(void *arg) 2098{ 2099 struct hdac_softc *sc = arg; 2100 uint32_t trigger = 0; 2101 2102 if (sc == NULL) 2103 return; 2104 2105 hdac_lock(sc); 2106 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2107 hdac_unlock(sc); 2108 return; 2109 } 2110 2111 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2112 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2113 2114 /* XXX */ 2115 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2116 hda_poll_callback, sc); 2117 2118 hdac_unlock(sc); 2119 2120 if (trigger & 1) 2121 chn_intr(sc->play.c); 2122 if (trigger & 2) 2123 chn_intr(sc->rec.c); 2124} 2125 2126static int 2127hdac_rirb_flush(struct hdac_softc *sc) 2128{ 2129 struct hdac_rirb *rirb_base, *rirb; 2130 struct hdac_codec *codec; 2131 struct hdac_command_list *commands; 2132 nid_t cad; 2133 uint32_t resp; 2134 uint8_t rirbwp; 2135 int ret = 0; 2136 2137 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2138 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2139 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2140 BUS_DMASYNC_POSTREAD); 2141 2142 while (sc->rirb_rp != rirbwp) { 2143 sc->rirb_rp++; 2144 sc->rirb_rp %= sc->rirb_size; 2145 rirb = &rirb_base[sc->rirb_rp]; 2146 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2147 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2148 sc->codecs[cad] == NULL) 2149 continue; 2150 resp = rirb->response; 2151 codec = sc->codecs[cad]; 2152 commands = codec->commands; 2153 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2154 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2155 ((resp >> 26) & 0xffff); 2156 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2157 } else if (commands != NULL && commands->num_commands > 0 && 2158 codec->responses_received < commands->num_commands) 2159 commands->responses[codec->responses_received++] = 2160 resp; 2161 ret++; 2162 } 2163 2164 return (ret); 2165} 2166 2167static int 2168hdac_unsolq_flush(struct hdac_softc *sc) 2169{ 2170 nid_t cad; 2171 uint32_t tag; 2172 int ret = 0; 2173 2174 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2175 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2176 while (sc->unsolq_rp != sc->unsolq_wp) { 2177 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2178 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2179 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2180 hdac_unsolicited_handler(sc->codecs[cad], tag); 2181 ret++; 2182 } 2183 sc->unsolq_st = HDAC_UNSOLQ_READY; 2184 } 2185 2186 return (ret); 2187} 2188 2189static void 2190hdac_poll_callback(void *arg) 2191{ 2192 struct hdac_softc *sc = arg; 2193 if (sc == NULL) 2194 return; 2195 2196 hdac_lock(sc); 2197 if (sc->polling == 0) { 2198 hdac_unlock(sc); 2199 return; 2200 } 2201 hdac_rirb_flush(sc); 2202 hdac_unsolq_flush(sc); 2203 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2204 hdac_poll_callback, sc); 2205 hdac_unlock(sc); 2206} 2207 2208static void 2209hdac_stream_stop(struct hdac_chan *ch) 2210{ 2211 struct hdac_softc *sc = ch->devinfo->codec->sc; 2212 uint32_t ctl; 2213 2214 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2215 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2216 HDAC_SDCTL_RUN); 2217 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2218 2219 ch->active = 0; 2220 2221 if (sc->polling != 0) { 2222 int pollticks; 2223 2224 if (hda_chan_active(sc) == 0) { 2225 callout_stop(&sc->poll_hda); 2226 sc->poll_ticks = 1; 2227 } else { 2228 if (sc->play.active != 0) 2229 ch = &sc->play; 2230 else 2231 ch = &sc->rec; 2232 pollticks = ((uint64_t)hz * ch->blksz) / 2233 ((uint64_t)sndbuf_getbps(ch->b) * 2234 sndbuf_getspd(ch->b)); 2235 pollticks >>= 2; 2236 if (pollticks > hz) 2237 pollticks = hz; 2238 if (pollticks < 1) { 2239 HDA_BOOTVERBOSE( 2240 device_printf(sc->dev, 2241 "%s: pollticks=%d < 1 !\n", 2242 __func__, pollticks); 2243 ); 2244 pollticks = 1; 2245 } 2246 if (pollticks > sc->poll_ticks) { 2247 HDA_BOOTVERBOSE( 2248 device_printf(sc->dev, 2249 "%s: pollticks %d -> %d\n", 2250 __func__, sc->poll_ticks, 2251 pollticks); 2252 ); 2253 sc->poll_ticks = pollticks; 2254 callout_reset(&sc->poll_hda, 1, 2255 hda_poll_callback, sc); 2256 } 2257 } 2258 } else { 2259 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2260 ctl &= ~(1 << (ch->off >> 5)); 2261 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2262 } 2263} 2264 2265static void 2266hdac_stream_start(struct hdac_chan *ch) 2267{ 2268 struct hdac_softc *sc = ch->devinfo->codec->sc; 2269 uint32_t ctl; 2270 2271 if (sc->polling != 0) { 2272 int pollticks; 2273 2274 pollticks = ((uint64_t)hz * ch->blksz) / 2275 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2276 pollticks >>= 2; 2277 if (pollticks > hz) 2278 pollticks = hz; 2279 if (pollticks < 1) { 2280 HDA_BOOTVERBOSE( 2281 device_printf(sc->dev, 2282 "%s: pollticks=%d < 1 !\n", 2283 __func__, pollticks); 2284 ); 2285 pollticks = 1; 2286 } 2287 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2288 HDA_BOOTVERBOSE( 2289 if (hda_chan_active(sc) == 0) { 2290 device_printf(sc->dev, 2291 "%s: pollticks=%d\n", 2292 __func__, pollticks); 2293 } else { 2294 device_printf(sc->dev, 2295 "%s: pollticks %d -> %d\n", 2296 __func__, sc->poll_ticks, 2297 pollticks); 2298 } 2299 ); 2300 sc->poll_ticks = pollticks; 2301 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2302 sc); 2303 } 2304 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2305 ctl |= HDAC_SDCTL_RUN; 2306 } else { 2307 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2308 ctl |= 1 << (ch->off >> 5); 2309 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2310 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2311 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2312 HDAC_SDCTL_RUN; 2313 } 2314 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2315 2316 ch->active = 1; 2317} 2318 2319static void 2320hdac_stream_reset(struct hdac_chan *ch) 2321{ 2322 struct hdac_softc *sc = ch->devinfo->codec->sc; 2323 int timeout = 1000; 2324 int to = timeout; 2325 uint32_t ctl; 2326 2327 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2328 ctl |= HDAC_SDCTL_SRST; 2329 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2330 do { 2331 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2332 if (ctl & HDAC_SDCTL_SRST) 2333 break; 2334 DELAY(10); 2335 } while (--to); 2336 if (!(ctl & HDAC_SDCTL_SRST)) { 2337 device_printf(sc->dev, "timeout in reset\n"); 2338 } 2339 ctl &= ~HDAC_SDCTL_SRST; 2340 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2341 to = timeout; 2342 do { 2343 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2344 if (!(ctl & HDAC_SDCTL_SRST)) 2345 break; 2346 DELAY(10); 2347 } while (--to); 2348 if (ctl & HDAC_SDCTL_SRST) 2349 device_printf(sc->dev, "can't reset!\n"); 2350} 2351 2352static void 2353hdac_stream_setid(struct hdac_chan *ch) 2354{ 2355 struct hdac_softc *sc = ch->devinfo->codec->sc; 2356 uint32_t ctl; 2357 2358 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2359 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2360 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2361 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2362} 2363 2364static void 2365hdac_bdl_setup(struct hdac_chan *ch) 2366{ 2367 struct hdac_softc *sc = ch->devinfo->codec->sc; 2368 struct hdac_bdle *bdle; 2369 uint64_t addr; 2370 uint32_t blksz, blkcnt; 2371 int i; 2372 2373 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2374 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2375 2376 if (sc->polling != 0) { 2377 blksz = ch->blksz * ch->blkcnt; 2378 blkcnt = 1; 2379 } else { 2380 blksz = ch->blksz; 2381 blkcnt = ch->blkcnt; 2382 } 2383 2384 for (i = 0; i < blkcnt; i++, bdle++) { 2385 bdle->addrl = (uint32_t)addr; 2386 bdle->addrh = (uint32_t)(addr >> 32); 2387 bdle->len = blksz; 2388 bdle->ioc = 1 ^ sc->polling; 2389 addr += blksz; 2390 } 2391 2392 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2393 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2394 addr = ch->bdl_dma.dma_paddr; 2395 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2396 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2397} 2398 2399static int 2400hdac_bdl_alloc(struct hdac_chan *ch) 2401{ 2402 struct hdac_softc *sc = ch->devinfo->codec->sc; 2403 int rc; 2404 2405 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2406 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2407 if (rc) { 2408 device_printf(sc->dev, "can't alloc bdl\n"); 2409 return (rc); 2410 } 2411 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2412 2413 return (0); 2414} 2415 2416static void 2417hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2418 int index, int lmute, int rmute, 2419 int left, int right, int dir) 2420{ 2421 uint16_t v = 0; 2422 2423 if (sc == NULL) 2424 return; 2425 2426 if (left != right || lmute != rmute) { 2427 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2428 (lmute << 7) | left; 2429 hdac_command(sc, 2430 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2431 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2432 (rmute << 7) | right; 2433 } else 2434 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2435 (lmute << 7) | left; 2436 2437 hdac_command(sc, 2438 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2439} 2440 2441static void 2442hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2443 int left, int right) 2444{ 2445 struct hdac_softc *sc; 2446 nid_t nid, cad; 2447 int lmute, rmute; 2448 2449 if (ctl == NULL || ctl->widget == NULL || 2450 ctl->widget->devinfo == NULL || 2451 ctl->widget->devinfo->codec == NULL || 2452 ctl->widget->devinfo->codec->sc == NULL) 2453 return; 2454 2455 sc = ctl->widget->devinfo->codec->sc; 2456 cad = ctl->widget->devinfo->codec->cad; 2457 nid = ctl->widget->nid; 2458 2459 if (mute == HDA_AMP_MUTE_DEFAULT) { 2460 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2461 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2462 } else { 2463 lmute = HDA_AMP_LEFT_MUTED(mute); 2464 rmute = HDA_AMP_RIGHT_MUTED(mute); 2465 } 2466 2467 if (ctl->dir & HDA_CTL_OUT) 2468 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2469 lmute, rmute, left, right, 0); 2470 if (ctl->dir & HDA_CTL_IN) 2471 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2472 lmute, rmute, left, right, 1); 2473 ctl->left = left; 2474 ctl->right = right; 2475} 2476 2477static void 2478hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2479{ 2480 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2481 return; 2482 hdac_command(w->devinfo->codec->sc, 2483 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2484 w->nid, index), w->devinfo->codec->cad); 2485 w->selconn = index; 2486} 2487 2488 2489/**************************************************************************** 2490 * uint32_t hdac_command_sendone_internal 2491 * 2492 * Wrapper function that sends only one command to a given codec 2493 ****************************************************************************/ 2494static uint32_t 2495hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2496{ 2497 struct hdac_command_list cl; 2498 uint32_t response = HDAC_INVALID; 2499 2500 if (!hdac_lockowned(sc)) 2501 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2502 cl.num_commands = 1; 2503 cl.verbs = &verb; 2504 cl.responses = &response; 2505 2506 hdac_command_send_internal(sc, &cl, cad); 2507 2508 return (response); 2509} 2510 2511/**************************************************************************** 2512 * hdac_command_send_internal 2513 * 2514 * Send a command list to the codec via the corb. We queue as much verbs as 2515 * we can and msleep on the codec. When the interrupt get the responses 2516 * back from the rirb, it will wake us up so we can queue the remaining verbs 2517 * if any. 2518 ****************************************************************************/ 2519static void 2520hdac_command_send_internal(struct hdac_softc *sc, 2521 struct hdac_command_list *commands, nid_t cad) 2522{ 2523 struct hdac_codec *codec; 2524 int corbrp; 2525 uint32_t *corb; 2526 int timeout; 2527 int retry = 10; 2528 struct hdac_rirb *rirb_base; 2529 2530 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2531 commands->num_commands < 1) 2532 return; 2533 2534 codec = sc->codecs[cad]; 2535 codec->commands = commands; 2536 codec->responses_received = 0; 2537 codec->verbs_sent = 0; 2538 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2539 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2540 2541 do { 2542 if (codec->verbs_sent != commands->num_commands) { 2543 /* Queue as many verbs as possible */ 2544 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2545 bus_dmamap_sync(sc->corb_dma.dma_tag, 2546 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2547 while (codec->verbs_sent != commands->num_commands && 2548 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2549 sc->corb_wp++; 2550 sc->corb_wp %= sc->corb_size; 2551 corb[sc->corb_wp] = 2552 commands->verbs[codec->verbs_sent++]; 2553 } 2554 2555 /* Send the verbs to the codecs */ 2556 bus_dmamap_sync(sc->corb_dma.dma_tag, 2557 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2558 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2559 } 2560 2561 timeout = 1000; 2562 while (hdac_rirb_flush(sc) == 0 && --timeout) 2563 DELAY(10); 2564 } while ((codec->verbs_sent != commands->num_commands || 2565 codec->responses_received != commands->num_commands) && --retry); 2566 2567 if (retry == 0) 2568 device_printf(sc->dev, 2569 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2570 __func__, commands->num_commands, codec->verbs_sent, 2571 codec->responses_received); 2572 2573 codec->commands = NULL; 2574 codec->responses_received = 0; 2575 codec->verbs_sent = 0; 2576 2577 hdac_unsolq_flush(sc); 2578} 2579 2580 2581/**************************************************************************** 2582 * Device Methods 2583 ****************************************************************************/ 2584 2585/**************************************************************************** 2586 * int hdac_probe(device_t) 2587 * 2588 * Probe for the presence of an hdac. If none is found, check for a generic 2589 * match using the subclass of the device. 2590 ****************************************************************************/ 2591static int 2592hdac_probe(device_t dev) 2593{ 2594 int i, result; 2595 uint32_t model; 2596 uint16_t class, subclass; 2597 char desc[64]; 2598 2599 model = (uint32_t)pci_get_device(dev) << 16; 2600 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2601 class = pci_get_class(dev); 2602 subclass = pci_get_subclass(dev); 2603 2604 bzero(desc, sizeof(desc)); 2605 result = ENXIO; 2606 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2607 if (hdac_devices[i].model == model) { 2608 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2609 result = BUS_PROBE_DEFAULT; 2610 break; 2611 } 2612 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2613 class == PCIC_MULTIMEDIA && 2614 subclass == PCIS_MULTIMEDIA_HDA) { 2615 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2616 result = BUS_PROBE_GENERIC; 2617 break; 2618 } 2619 } 2620 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2621 subclass == PCIS_MULTIMEDIA_HDA) { 2622 strlcpy(desc, "Generic", sizeof(desc)); 2623 result = BUS_PROBE_GENERIC; 2624 } 2625 if (result != ENXIO) { 2626 strlcat(desc, " High Definition Audio Controller", 2627 sizeof(desc)); 2628 device_set_desc_copy(dev, desc); 2629 } 2630 2631 return (result); 2632} 2633 2634static void * 2635hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2636 struct pcm_channel *c, int dir) 2637{ 2638 struct hdac_devinfo *devinfo = data; 2639 struct hdac_softc *sc = devinfo->codec->sc; 2640 struct hdac_chan *ch; 2641 2642 hdac_lock(sc); 2643 if (dir == PCMDIR_PLAY) { 2644 ch = &sc->play; 2645 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2646 ch->dir = PCMDIR_PLAY; 2647 ch->sid = ++sc->streamcnt; 2648 devinfo->function.audio.playcnt++; 2649 } else { 2650 ch = &sc->rec; 2651 ch->off = devinfo->function.audio.reccnt << 5; 2652 ch->dir = PCMDIR_REC; 2653 ch->sid = ++sc->streamcnt; 2654 devinfo->function.audio.reccnt++; 2655 } 2656 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2657 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2658 ch->pcmrates[0] = 48000; 2659 ch->pcmrates[1] = 0; 2660 } 2661 ch->b = b; 2662 ch->c = c; 2663 ch->devinfo = devinfo; 2664 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2665 ch->blkcnt = sc->chan_blkcnt; 2666 hdac_unlock(sc); 2667 2668 if (hdac_bdl_alloc(ch) != 0) { 2669 ch->blkcnt = 0; 2670 return (NULL); 2671 } 2672 2673 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2674 return (NULL); 2675 2676 hdac_dma_nocache(ch->b->buf); 2677 2678 return (ch); 2679} 2680 2681static int 2682hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2683{ 2684 struct hdac_chan *ch = data; 2685 int i; 2686 2687 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2688 if (format == ch->caps.fmtlist[i]) { 2689 ch->fmt = format; 2690 return (0); 2691 } 2692 } 2693 2694 return (EINVAL); 2695} 2696 2697static int 2698hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2699{ 2700 struct hdac_chan *ch = data; 2701 uint32_t spd = 0, threshold; 2702 int i; 2703 2704 for (i = 0; ch->pcmrates[i] != 0; i++) { 2705 spd = ch->pcmrates[i]; 2706 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2707 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2708 if (speed < threshold) 2709 break; 2710 } 2711 2712 if (spd == 0) /* impossible */ 2713 ch->spd = 48000; 2714 else 2715 ch->spd = spd; 2716 2717 return (ch->spd); 2718} 2719 2720static void 2721hdac_stream_setup(struct hdac_chan *ch) 2722{ 2723 struct hdac_softc *sc = ch->devinfo->codec->sc; 2724 int i; 2725 nid_t cad = ch->devinfo->codec->cad; 2726 uint16_t fmt; 2727 2728 fmt = 0; 2729 if (ch->fmt & AFMT_S16_LE) 2730 fmt |= ch->bit16 << 4; 2731 else if (ch->fmt & AFMT_S32_LE) 2732 fmt |= ch->bit32 << 4; 2733 else 2734 fmt |= 1 << 4; 2735 2736 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2737 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2738 fmt |= hda_rate_tab[i].base; 2739 fmt |= hda_rate_tab[i].mul; 2740 fmt |= hda_rate_tab[i].div; 2741 break; 2742 } 2743 } 2744 2745 if (ch->fmt & AFMT_STEREO) 2746 fmt |= 1; 2747 2748 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2749 2750 for (i = 0; ch->io[i] != -1; i++) { 2751 HDA_BOOTVERBOSE( 2752 device_printf(sc->dev, 2753 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2754 "fmt=0x%08x\n", 2755 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2756 ch->io[i], fmt); 2757 ); 2758 hdac_command(sc, 2759 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2760 hdac_command(sc, 2761 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2762 ch->sid << 4), cad); 2763 } 2764} 2765 2766static int 2767hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2768{ 2769 struct hdac_chan *ch = data; 2770 struct hdac_softc *sc = ch->devinfo->codec->sc; 2771 2772 blksz &= ~0x7f; 2773 if (blksz < 0x80) 2774 blksz = 0x80; 2775 2776 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2777 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2778 2779 if ((sndbuf_getblksz(ch->b) != blksz || 2780 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2781 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2782 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2783 __func__, blksz, ch->blkcnt); 2784 2785 ch->blksz = sndbuf_getblksz(ch->b); 2786 2787 return (ch->blksz); 2788} 2789 2790static void 2791hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2792{ 2793 struct hdac_devinfo *devinfo = ch->devinfo; 2794 nid_t cad = devinfo->codec->cad; 2795 int i; 2796 2797 hdac_stream_stop(ch); 2798 2799 for (i = 0; ch->io[i] != -1; i++) { 2800 hdac_command(sc, 2801 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2802 0), cad); 2803 } 2804} 2805 2806static void 2807hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2808{ 2809 ch->ptr = 0; 2810 ch->prevptr = 0; 2811 hdac_stream_stop(ch); 2812 hdac_stream_reset(ch); 2813 hdac_bdl_setup(ch); 2814 hdac_stream_setid(ch); 2815 hdac_stream_setup(ch); 2816 hdac_stream_start(ch); 2817} 2818 2819static int 2820hdac_channel_trigger(kobj_t obj, void *data, int go) 2821{ 2822 struct hdac_chan *ch = data; 2823 struct hdac_softc *sc = ch->devinfo->codec->sc; 2824 2825 hdac_lock(sc); 2826 switch (go) { 2827 case PCMTRIG_START: 2828 hdac_channel_start(sc, ch); 2829 break; 2830 case PCMTRIG_STOP: 2831 case PCMTRIG_ABORT: 2832 hdac_channel_stop(sc, ch); 2833 break; 2834 default: 2835 break; 2836 } 2837 hdac_unlock(sc); 2838 2839 return (0); 2840} 2841 2842static int 2843hdac_channel_getptr(kobj_t obj, void *data) 2844{ 2845 struct hdac_chan *ch = data; 2846 struct hdac_softc *sc = ch->devinfo->codec->sc; 2847 uint32_t ptr; 2848 2849 hdac_lock(sc); 2850 if (sc->polling != 0) 2851 ptr = ch->ptr; 2852 else 2853 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2854 hdac_unlock(sc); 2855 2856 /* 2857 * Round to available space and force 128 bytes aligment. 2858 */ 2859 ptr %= ch->blksz * ch->blkcnt; 2860 ptr &= ~0x7f; 2861 2862 return (ptr); 2863} 2864 2865static struct pcmchan_caps * 2866hdac_channel_getcaps(kobj_t obj, void *data) 2867{ 2868 return (&((struct hdac_chan *)data)->caps); 2869} 2870 2871static kobj_method_t hdac_channel_methods[] = { 2872 KOBJMETHOD(channel_init, hdac_channel_init), 2873 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2874 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2875 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2876 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2877 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2878 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2879 { 0, 0 } 2880}; 2881CHANNEL_DECLARE(hdac_channel); 2882 2883static int 2884hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2885{ 2886 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2887 struct hdac_softc *sc = devinfo->codec->sc; 2888 struct hdac_widget *w, *cw; 2889 struct hdac_audio_ctl *ctl; 2890 uint32_t mask, recmask, id; 2891 int i, j, softpcmvol; 2892 nid_t cad; 2893 2894 hdac_lock(sc); 2895 2896 mask = 0; 2897 recmask = 0; 2898 2899 id = hdac_codec_id(devinfo); 2900 cad = devinfo->codec->cad; 2901 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2902 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2903 sc->pci_subvendor) && 2904 hdac_hp_switch[i].id == id)) 2905 continue; 2906 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2907 if (w != NULL && w->enable != 0 2908 && w->type == 2909 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2910 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2911 hdac_command(sc, 2912 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2913 w->nid, 2914 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2915 HDAC_UNSOLTAG_EVENT_HP), cad); 2916 hdac_hp_switch_handler(devinfo); 2917 HDA_BOOTVERBOSE( 2918 device_printf(sc->dev, 2919 "HDA_DEBUG: Enabling headphone/speaker " 2920 "audio routing switching:\n"); 2921 device_printf(sc->dev, 2922 "HDA_DEBUG: \tindex=%d nid=%d " 2923 "pci_subvendor=0x%08x " 2924 "codec=0x%08x\n", 2925 i, w->nid, sc->pci_subvendor, id); 2926 ); 2927 } 2928 break; 2929 } 2930 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2931 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2932 sc->pci_subvendor) && 2933 hdac_eapd_switch[i].id == id)) 2934 continue; 2935 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2936 if (w == NULL || w->enable == 0) 2937 break; 2938 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2939 w->param.eapdbtl == HDAC_INVALID) 2940 break; 2941 mask |= SOUND_MASK_OGAIN; 2942 break; 2943 } 2944 2945 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2946 w = hdac_widget_get(devinfo, i); 2947 if (w == NULL || w->enable == 0) 2948 continue; 2949 mask |= w->ctlflags; 2950 if (!(w->pflags & HDA_ADC_RECSEL)) 2951 continue; 2952 for (j = 0; j < w->nconns; j++) { 2953 cw = hdac_widget_get(devinfo, w->conns[j]); 2954 if (cw == NULL || cw->enable == 0) 2955 continue; 2956 recmask |= cw->ctlflags; 2957 } 2958 } 2959 2960 if (!(mask & SOUND_MASK_PCM)) { 2961 softpcmvol = 1; 2962 mask |= SOUND_MASK_PCM; 2963 } else 2964 softpcmvol = (devinfo->function.audio.quirks & 2965 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2966 2967 i = 0; 2968 ctl = NULL; 2969 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2970 if (ctl->widget == NULL || ctl->enable == 0) 2971 continue; 2972 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2973 continue; 2974 if (ctl->step > 0) 2975 break; 2976 } 2977 2978 if (softpcmvol == 1 || ctl == NULL) { 2979 struct snddev_info *d = NULL; 2980 d = device_get_softc(sc->dev); 2981 if (d != NULL) { 2982 d->flags |= SD_F_SOFTPCMVOL; 2983 HDA_BOOTVERBOSE( 2984 device_printf(sc->dev, 2985 "HDA_DEBUG: %s Soft PCM volume\n", 2986 (softpcmvol == 1) ? 2987 "Forcing" : "Enabling"); 2988 ); 2989 } 2990 i = 0; 2991 /* 2992 * XXX Temporary quirk for STAC9220, until the parser 2993 * become smarter. 2994 */ 2995 if (id == HDA_CODEC_STAC9220) { 2996 mask |= SOUND_MASK_VOLUME; 2997 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2998 NULL) { 2999 if (ctl->widget == NULL || ctl->enable == 0) 3000 continue; 3001 if (ctl->widget->nid == 11 && ctl->index == 0) { 3002 ctl->ossmask = SOUND_MASK_VOLUME; 3003 ctl->ossval = 100 | (100 << 8); 3004 } else 3005 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3006 } 3007 } else if (id == HDA_CODEC_STAC9221) { 3008 mask |= SOUND_MASK_VOLUME; 3009 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3010 NULL) { 3011 if (ctl->widget == NULL) 3012 continue; 3013 if (ctl->widget->nid == 2 && ctl->index == 0) { 3014 ctl->enable = 1; 3015 ctl->ossmask = SOUND_MASK_VOLUME; 3016 ctl->ossval = 100 | (100 << 8); 3017 } else if (ctl->enable == 0) 3018 continue; 3019 else 3020 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3021 } 3022 } else { 3023 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3024 SOUND_MASK_PCM); 3025 if (!(mask & SOUND_MASK_VOLUME)) 3026 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3027 SOUND_MIXER_NONE); 3028 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3029 NULL) { 3030 if (ctl->widget == NULL || ctl->enable == 0) 3031 continue; 3032 if (!HDA_FLAG_MATCH(ctl->ossmask, 3033 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3034 continue; 3035 if (!(ctl->mute == 1 && ctl->step == 0)) 3036 ctl->enable = 0; 3037 } 3038 } 3039 } 3040 3041 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 3042 3043 mix_setrecdevs(m, recmask); 3044 mix_setdevs(m, mask); 3045 3046 hdac_unlock(sc); 3047 3048 return (0); 3049} 3050 3051static int 3052hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3053 unsigned left, unsigned right) 3054{ 3055 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3056 struct hdac_softc *sc = devinfo->codec->sc; 3057 struct hdac_widget *w; 3058 struct hdac_audio_ctl *ctl; 3059 uint32_t id, mute; 3060 int lvol, rvol, mlvol, mrvol; 3061 int i = 0; 3062 3063 hdac_lock(sc); 3064 if (dev == SOUND_MIXER_OGAIN) { 3065 uint32_t orig; 3066 /*if (left != right || !(left == 0 || left == 1)) { 3067 hdac_unlock(sc); 3068 return (-1); 3069 }*/ 3070 id = hdac_codec_id(devinfo); 3071 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3072 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3073 sc->pci_subvendor) && 3074 hdac_eapd_switch[i].id == id) 3075 break; 3076 } 3077 if (i >= HDAC_EAPD_SWITCH_LEN) { 3078 hdac_unlock(sc); 3079 return (-1); 3080 } 3081 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3082 if (w == NULL || 3083 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3084 w->param.eapdbtl == HDAC_INVALID) { 3085 hdac_unlock(sc); 3086 return (-1); 3087 } 3088 orig = w->param.eapdbtl; 3089 if (left == 0) 3090 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3091 else 3092 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3093 if (orig != w->param.eapdbtl) { 3094 uint32_t val; 3095 3096 if (hdac_eapd_switch[i].hp_switch != 0) 3097 hdac_hp_switch_handler(devinfo); 3098 val = w->param.eapdbtl; 3099 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3100 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3101 hdac_command(sc, 3102 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3103 w->nid, val), devinfo->codec->cad); 3104 } 3105 hdac_unlock(sc); 3106 return (left | (left << 8)); 3107 } 3108 if (dev == SOUND_MIXER_VOLUME) 3109 devinfo->function.audio.mvol = left | (right << 8); 3110 3111 mlvol = devinfo->function.audio.mvol & 0x7f; 3112 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3113 lvol = 0; 3114 rvol = 0; 3115 3116 i = 0; 3117 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3118 if (ctl->widget == NULL || ctl->enable == 0 || 3119 !(ctl->ossmask & (1 << dev))) 3120 continue; 3121 switch (dev) { 3122 case SOUND_MIXER_VOLUME: 3123 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3124 lvol = (lvol * ctl->step) / 100; 3125 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3126 rvol = (rvol * ctl->step) / 100; 3127 break; 3128 default: 3129 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3130 lvol = (left * mlvol) / 100; 3131 lvol = (lvol * ctl->step) / 100; 3132 rvol = (right * mrvol) / 100; 3133 rvol = (rvol * ctl->step) / 100; 3134 } else { 3135 lvol = (left * ctl->step) / 100; 3136 rvol = (right * ctl->step) / 100; 3137 } 3138 ctl->ossval = left | (right << 8); 3139 break; 3140 } 3141 mute = 0; 3142 if (ctl->step < 1) { 3143 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3144 (ctl->muted & HDA_AMP_MUTE_LEFT); 3145 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3146 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3147 } else { 3148 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3149 (ctl->muted & HDA_AMP_MUTE_LEFT); 3150 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3151 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3152 } 3153 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3154 } 3155 hdac_unlock(sc); 3156 3157 return (left | (right << 8)); 3158} 3159 3160static int 3161hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3162{ 3163 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3164 struct hdac_widget *w, *cw; 3165 struct hdac_softc *sc = devinfo->codec->sc; 3166 uint32_t ret = src, target; 3167 int i, j; 3168 3169 target = 0; 3170 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3171 if (src & (1 << i)) { 3172 target = 1 << i; 3173 break; 3174 } 3175 } 3176 3177 hdac_lock(sc); 3178 3179 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3180 w = hdac_widget_get(devinfo, i); 3181 if (w == NULL || w->enable == 0) 3182 continue; 3183 if (!(w->pflags & HDA_ADC_RECSEL)) 3184 continue; 3185 for (j = 0; j < w->nconns; j++) { 3186 cw = hdac_widget_get(devinfo, w->conns[j]); 3187 if (cw == NULL || cw->enable == 0) 3188 continue; 3189 if ((target == SOUND_MASK_VOLUME && 3190 cw->type != 3191 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3192 (target != SOUND_MASK_VOLUME && 3193 cw->type == 3194 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3195 continue; 3196 if (cw->ctlflags & target) { 3197 hdac_widget_connection_select(w, j); 3198 ret = target; 3199 j += w->nconns; 3200 } 3201 } 3202 } 3203 3204 hdac_unlock(sc); 3205 3206 return (ret); 3207} 3208 3209static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3210 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3211 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3212 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3213 { 0, 0 } 3214}; 3215MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3216 3217/**************************************************************************** 3218 * int hdac_attach(device_t) 3219 * 3220 * Attach the device into the kernel. Interrupts usually won't be enabled 3221 * when this function is called. Setup everything that doesn't require 3222 * interrupts and defer probing of codecs until interrupts are enabled. 3223 ****************************************************************************/ 3224static int 3225hdac_attach(device_t dev) 3226{ 3227 struct hdac_softc *sc; 3228 int result; 3229 int i = 0; 3230 3231 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3232 if (sc == NULL) { 3233 device_printf(dev, "cannot allocate softc\n"); 3234 return (ENOMEM); 3235 } 3236 3237 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3238 sc->dev = dev; 3239 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3240 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3241 3242 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3243 /* Screw nx6325 - subdevice/subvendor swapped */ 3244 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3245 } 3246 3247 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3248 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3249 3250 sc->poll_ticks = 1; 3251 if (resource_int_value(device_get_name(sc->dev), 3252 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3253 sc->polling = 1; 3254 else 3255 sc->polling = 0; 3256 3257 sc->chan_size = pcm_getbuffersize(dev, 3258 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3259 3260 if (resource_int_value(device_get_name(sc->dev), 3261 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3262 i &= ~0x7f; 3263 if (i < 0x80) 3264 i = 0x80; 3265 sc->chan_blkcnt = sc->chan_size / i; 3266 i = 0; 3267 while (sc->chan_blkcnt >> i) 3268 i++; 3269 sc->chan_blkcnt = 1 << (i - 1); 3270 if (sc->chan_blkcnt < HDA_BDL_MIN) 3271 sc->chan_blkcnt = HDA_BDL_MIN; 3272 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3273 sc->chan_blkcnt = HDA_BDL_MAX; 3274 } else 3275 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3276 3277 result = bus_dma_tag_create(NULL, /* parent */ 3278 HDAC_DMA_ALIGNMENT, /* alignment */ 3279 0, /* boundary */ 3280 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3281 BUS_SPACE_MAXADDR, /* highaddr */ 3282 NULL, /* filtfunc */ 3283 NULL, /* fistfuncarg */ 3284 sc->chan_size, /* maxsize */ 3285 1, /* nsegments */ 3286 sc->chan_size, /* maxsegsz */ 3287 0, /* flags */ 3288 NULL, /* lockfunc */ 3289 NULL, /* lockfuncarg */ 3290 &sc->chan_dmat); /* dmat */ 3291 if (result != 0) { 3292 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3293 __func__, result); 3294 snd_mtxfree(sc->lock); 3295 free(sc, M_DEVBUF); 3296 return (ENXIO); 3297 } 3298 3299 3300 sc->hdabus = NULL; 3301 for (i = 0; i < HDAC_CODEC_MAX; i++) 3302 sc->codecs[i] = NULL; 3303 3304 pci_enable_busmaster(dev); 3305 3306 /* Allocate resources */ 3307 result = hdac_mem_alloc(sc); 3308 if (result != 0) 3309 goto hdac_attach_fail; 3310 result = hdac_irq_alloc(sc); 3311 if (result != 0) 3312 goto hdac_attach_fail; 3313 3314 /* Get Capabilities */ 3315 result = hdac_get_capabilities(sc); 3316 if (result != 0) 3317 goto hdac_attach_fail; 3318 3319 /* Allocate CORB and RIRB dma memory */ 3320 result = hdac_dma_alloc(sc, &sc->corb_dma, 3321 sc->corb_size * sizeof(uint32_t)); 3322 if (result != 0) 3323 goto hdac_attach_fail; 3324 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3325 sc->rirb_size * sizeof(struct hdac_rirb)); 3326 if (result != 0) 3327 goto hdac_attach_fail; 3328 3329 /* Quiesce everything */ 3330 hdac_reset(sc); 3331 3332 /* Disable PCI-Express QOS */ 3333 pci_write_config(sc->dev, 0x44, 3334 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3335 3336 /* Initialize the CORB and RIRB */ 3337 hdac_corb_init(sc); 3338 hdac_rirb_init(sc); 3339 3340 /* Defer remaining of initialization until interrupts are enabled */ 3341 sc->intrhook.ich_func = hdac_attach2; 3342 sc->intrhook.ich_arg = (void *)sc; 3343 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3344 sc->intrhook.ich_func = NULL; 3345 hdac_attach2((void *)sc); 3346 } 3347 3348 return (0); 3349 3350hdac_attach_fail: 3351 hdac_dma_free(&sc->rirb_dma); 3352 hdac_dma_free(&sc->corb_dma); 3353 hdac_irq_free(sc); 3354 hdac_mem_free(sc); 3355 snd_mtxfree(sc->lock); 3356 free(sc, M_DEVBUF); 3357 3358 return (ENXIO); 3359} 3360 3361static void 3362hdac_audio_parse(struct hdac_devinfo *devinfo) 3363{ 3364 struct hdac_softc *sc = devinfo->codec->sc; 3365 struct hdac_widget *w; 3366 uint32_t res; 3367 int i; 3368 nid_t cad, nid; 3369 3370 cad = devinfo->codec->cad; 3371 nid = devinfo->nid; 3372 3373 hdac_command(sc, 3374 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3375 3376 DELAY(100); 3377 3378 res = hdac_command(sc, 3379 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3380 3381 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3382 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3383 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3384 3385 HDA_BOOTVERBOSE( 3386 device_printf(sc->dev, " Vendor: 0x%08x\n", 3387 devinfo->vendor_id); 3388 device_printf(sc->dev, " Device: 0x%08x\n", 3389 devinfo->device_id); 3390 device_printf(sc->dev, " Revision: 0x%08x\n", 3391 devinfo->revision_id); 3392 device_printf(sc->dev, " Stepping: 0x%08x\n", 3393 devinfo->stepping_id); 3394 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3395 sc->pci_subvendor); 3396 device_printf(sc->dev, " Nodes: start=%d " 3397 "endnode=%d total=%d\n", 3398 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3399 ); 3400 3401 res = hdac_command(sc, 3402 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3403 cad); 3404 devinfo->function.audio.supp_stream_formats = res; 3405 3406 res = hdac_command(sc, 3407 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3408 cad); 3409 devinfo->function.audio.supp_pcm_size_rate = res; 3410 3411 res = hdac_command(sc, 3412 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3413 cad); 3414 devinfo->function.audio.outamp_cap = res; 3415 3416 res = hdac_command(sc, 3417 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3418 cad); 3419 devinfo->function.audio.inamp_cap = res; 3420 3421 if (devinfo->nodecnt > 0) { 3422 hdac_unlock(sc); 3423 devinfo->widget = (struct hdac_widget *)malloc( 3424 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3425 M_NOWAIT | M_ZERO); 3426 hdac_lock(sc); 3427 } else 3428 devinfo->widget = NULL; 3429 3430 if (devinfo->widget == NULL) { 3431 device_printf(sc->dev, "unable to allocate widgets!\n"); 3432 devinfo->endnode = devinfo->startnode; 3433 devinfo->nodecnt = 0; 3434 return; 3435 } 3436 3437 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3438 w = hdac_widget_get(devinfo, i); 3439 if (w == NULL) 3440 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3441 else { 3442 w->devinfo = devinfo; 3443 w->nid = i; 3444 w->enable = 1; 3445 w->selconn = -1; 3446 w->pflags = 0; 3447 w->ctlflags = 0; 3448 w->param.eapdbtl = HDAC_INVALID; 3449 hdac_widget_parse(w); 3450 } 3451 } 3452} 3453 3454static void 3455hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3456{ 3457 struct hdac_softc *sc = devinfo->codec->sc; 3458 struct hdac_audio_ctl *ctls; 3459 struct hdac_widget *w, *cw; 3460 int i, j, cnt, max, ocap, icap; 3461 int mute, offset, step, size; 3462 3463 /* XXX This is redundant */ 3464 max = 0; 3465 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3466 w = hdac_widget_get(devinfo, i); 3467 if (w == NULL || w->enable == 0) 3468 continue; 3469 if (w->param.outamp_cap != 0) 3470 max++; 3471 if (w->param.inamp_cap != 0) { 3472 switch (w->type) { 3473 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3474 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3475 for (j = 0; j < w->nconns; j++) { 3476 cw = hdac_widget_get(devinfo, 3477 w->conns[j]); 3478 if (cw == NULL || cw->enable == 0) 3479 continue; 3480 max++; 3481 } 3482 break; 3483 default: 3484 max++; 3485 break; 3486 } 3487 } 3488 } 3489 3490 devinfo->function.audio.ctlcnt = max; 3491 3492 if (max < 1) 3493 return; 3494 3495 hdac_unlock(sc); 3496 ctls = (struct hdac_audio_ctl *)malloc( 3497 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3498 hdac_lock(sc); 3499 3500 if (ctls == NULL) { 3501 /* Blekh! */ 3502 device_printf(sc->dev, "unable to allocate ctls!\n"); 3503 devinfo->function.audio.ctlcnt = 0; 3504 return; 3505 } 3506 3507 cnt = 0; 3508 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3509 if (cnt >= max) { 3510 device_printf(sc->dev, "%s: Ctl overflow!\n", 3511 __func__); 3512 break; 3513 } 3514 w = hdac_widget_get(devinfo, i); 3515 if (w == NULL || w->enable == 0) 3516 continue; 3517 ocap = w->param.outamp_cap; 3518 icap = w->param.inamp_cap; 3519 if (ocap != 0) { 3520 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3521 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3522 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3523 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3524 /*if (offset > step) { 3525 HDA_BOOTVERBOSE( 3526 device_printf(sc->dev, 3527 "HDA_DEBUG: BUGGY outamp: nid=%d " 3528 "[offset=%d > step=%d]\n", 3529 w->nid, offset, step); 3530 ); 3531 offset = step; 3532 }*/ 3533 ctls[cnt].enable = 1; 3534 ctls[cnt].widget = w; 3535 ctls[cnt].mute = mute; 3536 ctls[cnt].step = step; 3537 ctls[cnt].size = size; 3538 ctls[cnt].offset = offset; 3539 ctls[cnt].left = offset; 3540 ctls[cnt].right = offset; 3541 ctls[cnt++].dir = HDA_CTL_OUT; 3542 } 3543 3544 if (icap != 0) { 3545 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3546 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3547 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3548 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3549 /*if (offset > step) { 3550 HDA_BOOTVERBOSE( 3551 device_printf(sc->dev, 3552 "HDA_DEBUG: BUGGY inamp: nid=%d " 3553 "[offset=%d > step=%d]\n", 3554 w->nid, offset, step); 3555 ); 3556 offset = step; 3557 }*/ 3558 switch (w->type) { 3559 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3560 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3561 for (j = 0; j < w->nconns; j++) { 3562 if (cnt >= max) { 3563 device_printf(sc->dev, 3564 "%s: Ctl overflow!\n", 3565 __func__); 3566 break; 3567 } 3568 cw = hdac_widget_get(devinfo, 3569 w->conns[j]); 3570 if (cw == NULL || cw->enable == 0) 3571 continue; 3572 ctls[cnt].enable = 1; 3573 ctls[cnt].widget = w; 3574 ctls[cnt].childwidget = cw; 3575 ctls[cnt].index = j; 3576 ctls[cnt].mute = mute; 3577 ctls[cnt].step = step; 3578 ctls[cnt].size = size; 3579 ctls[cnt].offset = offset; 3580 ctls[cnt].left = offset; 3581 ctls[cnt].right = offset; 3582 ctls[cnt++].dir = HDA_CTL_IN; 3583 } 3584 break; 3585 default: 3586 if (cnt >= max) { 3587 device_printf(sc->dev, 3588 "%s: Ctl overflow!\n", 3589 __func__); 3590 break; 3591 } 3592 ctls[cnt].enable = 1; 3593 ctls[cnt].widget = w; 3594 ctls[cnt].mute = mute; 3595 ctls[cnt].step = step; 3596 ctls[cnt].size = size; 3597 ctls[cnt].offset = offset; 3598 ctls[cnt].left = offset; 3599 ctls[cnt].right = offset; 3600 ctls[cnt++].dir = HDA_CTL_IN; 3601 break; 3602 } 3603 } 3604 } 3605 3606 devinfo->function.audio.ctl = ctls; 3607} 3608 3609static const struct { 3610 uint32_t model; 3611 uint32_t id; 3612 uint32_t set, unset; 3613} hdac_quirks[] = { 3614 /* 3615 * XXX Force stereo quirk. Monoural recording / playback 3616 * on few codecs (especially ALC880) seems broken or 3617 * perhaps unsupported. 3618 */ 3619 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3620 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3621 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3622 HDA_QUIRK_GPIO0, 0 }, 3623 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3624 HDA_QUIRK_GPIO0, 0 }, 3625 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3626 HDA_QUIRK_GPIO0, 0 }, 3627 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 3628 HDA_QUIRK_GPIO0, 0 }, 3629 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3630 HDA_QUIRK_EAPDINV, 0 }, 3631 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3632 HDA_QUIRK_EAPDINV, 0 }, 3633 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3634 HDA_QUIRK_GPIO1, 0 }, 3635 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3636 HDA_QUIRK_EAPDINV, 0 }, 3637 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3638 HDA_QUIRK_EAPDINV, 0 }, 3639 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3640 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3641 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3642 0, HDA_QUIRK_FORCESTEREO }, 3643 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3644 HDA_QUIRK_SOFTPCMVOL, 0 } 3645}; 3646#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3647 3648static void 3649hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3650{ 3651 struct hdac_widget *w; 3652 struct hdac_audio_ctl *ctl; 3653 uint32_t id, subvendor; 3654 int i; 3655 3656 id = hdac_codec_id(devinfo); 3657 subvendor = devinfo->codec->sc->pci_subvendor; 3658 3659 /* 3660 * Quirks 3661 */ 3662 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3663 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3664 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3665 continue; 3666 if (hdac_quirks[i].set != 0) 3667 devinfo->function.audio.quirks |= 3668 hdac_quirks[i].set; 3669 if (hdac_quirks[i].unset != 0) 3670 devinfo->function.audio.quirks &= 3671 ~(hdac_quirks[i].unset); 3672 } 3673 3674 switch (id) { 3675 case HDA_CODEC_ALC260: 3676 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3677 w = hdac_widget_get(devinfo, i); 3678 if (w == NULL || w->enable == 0) 3679 continue; 3680 if (w->type != 3681 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3682 continue; 3683 if (w->nid != 5) 3684 w->enable = 0; 3685 } 3686 if (subvendor == HP_XW4300_SUBVENDOR) { 3687 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3688 if (ctl != NULL && ctl->widget != NULL) { 3689 ctl->ossmask = SOUND_MASK_SPEAKER; 3690 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3691 } 3692 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3693 if (ctl != NULL && ctl->widget != NULL) { 3694 ctl->ossmask = SOUND_MASK_SPEAKER; 3695 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3696 } 3697 } 3698 break; 3699 case HDA_CODEC_ALC861: 3700 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3701 if (ctl != NULL) 3702 ctl->muted = HDA_AMP_MUTE_ALL; 3703 break; 3704 case HDA_CODEC_ALC880: 3705 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3706 w = hdac_widget_get(devinfo, i); 3707 if (w == NULL || w->enable == 0) 3708 continue; 3709 if (w->type == 3710 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3711 w->nid != 9 && w->nid != 29) { 3712 w->enable = 0; 3713 } else if (w->type != 3714 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3715 w->nid == 29) { 3716 w->type = 3717 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3718 w->param.widget_cap &= 3719 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3720 w->param.widget_cap |= 3721 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3722 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3723 strlcpy(w->name, "beep widget", sizeof(w->name)); 3724 } 3725 } 3726 break; 3727 case HDA_CODEC_ALC883: 3728 /* 3729 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 3730 * Clear vref cap for jack connectivity. 3731 */ 3732 w = hdac_widget_get(devinfo, 24); 3733 if (w != NULL && w->enable != 0 && w->type == 3734 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3735 (w->wclass.pin.config & 3736 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3737 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3738 w->wclass.pin.cap &= ~( 3739 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3740 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3741 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3742 w = hdac_widget_get(devinfo, 25); 3743 if (w != NULL && w->enable != 0 && w->type == 3744 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3745 (w->wclass.pin.config & 3746 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3747 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3748 w->wclass.pin.cap &= ~( 3749 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3750 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3751 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3752 /* 3753 * nid: 26 = Line-in, leave it alone. 3754 */ 3755 break; 3756 case HDA_CODEC_AD1981HD: 3757 w = hdac_widget_get(devinfo, 11); 3758 if (w != NULL && w->enable != 0 && w->nconns > 3) 3759 w->selconn = 3; 3760 if (subvendor == IBM_M52_SUBVENDOR) { 3761 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3762 if (ctl != NULL) 3763 ctl->ossmask = SOUND_MASK_SPEAKER; 3764 } 3765 break; 3766 case HDA_CODEC_AD1986A: 3767 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3768 w = hdac_widget_get(devinfo, i); 3769 if (w == NULL || w->enable == 0) 3770 continue; 3771 if (w->type != 3772 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3773 continue; 3774 if (w->nid != 3) 3775 w->enable = 0; 3776 } 3777 break; 3778 case HDA_CODEC_STAC9221: 3779 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3780 w = hdac_widget_get(devinfo, i); 3781 if (w == NULL || w->enable == 0) 3782 continue; 3783 if (w->type != 3784 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3785 continue; 3786 if (w->nid != 2) 3787 w->enable = 0; 3788 } 3789 break; 3790 case HDA_CODEC_STAC9221D: 3791 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3792 w = hdac_widget_get(devinfo, i); 3793 if (w == NULL || w->enable == 0) 3794 continue; 3795 if (w->type == 3796 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3797 w->nid != 6) 3798 w->enable = 0; 3799 3800 } 3801 break; 3802 default: 3803 break; 3804 } 3805} 3806 3807static int 3808hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3809{ 3810 int *dev = &devinfo->function.audio.ossidx; 3811 3812 while (*dev < SOUND_MIXER_NRDEVICES) { 3813 switch (*dev) { 3814 case SOUND_MIXER_VOLUME: 3815 case SOUND_MIXER_BASS: 3816 case SOUND_MIXER_TREBLE: 3817 case SOUND_MIXER_PCM: 3818 case SOUND_MIXER_SPEAKER: 3819 case SOUND_MIXER_LINE: 3820 case SOUND_MIXER_MIC: 3821 case SOUND_MIXER_CD: 3822 case SOUND_MIXER_RECLEV: 3823 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3824 (*dev)++; 3825 break; 3826 default: 3827 return (*dev)++; 3828 break; 3829 } 3830 } 3831 3832 return (-1); 3833} 3834 3835static int 3836hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3837{ 3838 struct hdac_widget *w; 3839 int i, ret = 0; 3840 3841 if (depth > HDA_PARSE_MAXDEPTH) 3842 return (0); 3843 w = hdac_widget_get(devinfo, nid); 3844 if (w == NULL || w->enable == 0) 3845 return (0); 3846 switch (w->type) { 3847 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3848 w->pflags |= HDA_DAC_PATH; 3849 ret = 1; 3850 break; 3851 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3852 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3853 for (i = 0; i < w->nconns; i++) { 3854 if (hdac_widget_find_dac_path(devinfo, 3855 w->conns[i], depth + 1) != 0) { 3856 if (w->selconn == -1) 3857 w->selconn = i; 3858 ret = 1; 3859 w->pflags |= HDA_DAC_PATH; 3860 } 3861 } 3862 break; 3863 default: 3864 break; 3865 } 3866 return (ret); 3867} 3868 3869static int 3870hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3871{ 3872 struct hdac_widget *w; 3873 int i, conndev, ret = 0; 3874 3875 if (depth > HDA_PARSE_MAXDEPTH) 3876 return (0); 3877 w = hdac_widget_get(devinfo, nid); 3878 if (w == NULL || w->enable == 0) 3879 return (0); 3880 switch (w->type) { 3881 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3882 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3883 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3884 for (i = 0; i < w->nconns; i++) { 3885 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3886 depth + 1) != 0) { 3887 if (w->selconn == -1) 3888 w->selconn = i; 3889 w->pflags |= HDA_ADC_PATH; 3890 ret = 1; 3891 } 3892 } 3893 break; 3894 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3895 conndev = w->wclass.pin.config & 3896 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3897 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3898 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3899 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3900 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3901 w->pflags |= HDA_ADC_PATH; 3902 ret = 1; 3903 } 3904 break; 3905 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3906 if (w->pflags & HDA_DAC_PATH) { 3907 w->pflags |= HDA_ADC_PATH; 3908 ret = 1; 3909 } 3910 break;*/ 3911 default: 3912 break; 3913 } 3914 return (ret); 3915} 3916 3917static uint32_t 3918hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3919 nid_t nid, nid_t pnid, int index, int depth) 3920{ 3921 struct hdac_widget *w, *pw; 3922 struct hdac_audio_ctl *ctl; 3923 uint32_t fl = 0; 3924 int i, ossdev, conndev, strategy; 3925 3926 if (depth > HDA_PARSE_MAXDEPTH) 3927 return (0); 3928 3929 w = hdac_widget_get(devinfo, nid); 3930 if (w == NULL || w->enable == 0) 3931 return (0); 3932 3933 pw = hdac_widget_get(devinfo, pnid); 3934 strategy = devinfo->function.audio.parsing_strategy; 3935 3936 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3937 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3938 for (i = 0; i < w->nconns; i++) { 3939 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3940 w->nid, i, depth + 1); 3941 } 3942 w->ctlflags |= fl; 3943 return (fl); 3944 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3945 (w->pflags & HDA_DAC_PATH)) { 3946 i = 0; 3947 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3948 if (ctl->enable == 0 || ctl->widget == NULL) 3949 continue; 3950 /* XXX This should be compressed! */ 3951 if ((ctl->widget->nid == w->nid) || 3952 (ctl->widget->nid == pnid && ctl->index == index && 3953 (ctl->dir & HDA_CTL_IN)) || 3954 (ctl->widget->nid == pnid && pw != NULL && 3955 pw->type == 3956 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3957 (pw->nconns < 2 || pw->selconn == index || 3958 pw->selconn == -1) && 3959 (ctl->dir & HDA_CTL_OUT)) || 3960 (strategy == HDA_PARSE_DIRECT && 3961 ctl->widget->nid == w->nid)) { 3962 /*if (pw != NULL && pw->selconn == -1) 3963 pw->selconn = index; 3964 fl |= SOUND_MASK_VOLUME; 3965 fl |= SOUND_MASK_PCM; 3966 ctl->ossmask |= SOUND_MASK_VOLUME; 3967 ctl->ossmask |= SOUND_MASK_PCM; 3968 ctl->ossdev = SOUND_MIXER_PCM;*/ 3969 if (!(w->ctlflags & SOUND_MASK_PCM) || 3970 (pw != NULL && 3971 !(pw->ctlflags & SOUND_MASK_PCM))) { 3972 fl |= SOUND_MASK_VOLUME; 3973 fl |= SOUND_MASK_PCM; 3974 ctl->ossmask |= SOUND_MASK_VOLUME; 3975 ctl->ossmask |= SOUND_MASK_PCM; 3976 ctl->ossdev = SOUND_MIXER_PCM; 3977 w->ctlflags |= SOUND_MASK_VOLUME; 3978 w->ctlflags |= SOUND_MASK_PCM; 3979 if (pw != NULL) { 3980 if (pw->selconn == -1) 3981 pw->selconn = index; 3982 pw->ctlflags |= 3983 SOUND_MASK_VOLUME; 3984 pw->ctlflags |= 3985 SOUND_MASK_PCM; 3986 } 3987 } 3988 } 3989 } 3990 w->ctlflags |= fl; 3991 return (fl); 3992 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3993 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3994 (w->pflags & HDA_ADC_PATH)) { 3995 conndev = w->wclass.pin.config & 3996 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3997 i = 0; 3998 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3999 if (ctl->enable == 0 || ctl->widget == NULL) 4000 continue; 4001 /* XXX This should be compressed! */ 4002 if (((ctl->widget->nid == pnid && ctl->index == index && 4003 (ctl->dir & HDA_CTL_IN)) || 4004 (ctl->widget->nid == pnid && pw != NULL && 4005 pw->type == 4006 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4007 (pw->nconns < 2 || pw->selconn == index || 4008 pw->selconn == -1) && 4009 (ctl->dir & HDA_CTL_OUT)) || 4010 (strategy == HDA_PARSE_DIRECT && 4011 ctl->widget->nid == w->nid)) && 4012 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4013 if (pw != NULL && pw->selconn == -1) 4014 pw->selconn = index; 4015 ossdev = 0; 4016 switch (conndev) { 4017 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4018 ossdev = SOUND_MIXER_MIC; 4019 break; 4020 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4021 ossdev = SOUND_MIXER_LINE; 4022 break; 4023 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4024 ossdev = SOUND_MIXER_CD; 4025 break; 4026 default: 4027 ossdev = 4028 hdac_audio_ctl_ossmixer_getnextdev( 4029 devinfo); 4030 if (ossdev < 0) 4031 ossdev = 0; 4032 break; 4033 } 4034 if (strategy == HDA_PARSE_MIXER) { 4035 fl |= SOUND_MASK_VOLUME; 4036 ctl->ossmask |= SOUND_MASK_VOLUME; 4037 } 4038 fl |= 1 << ossdev; 4039 ctl->ossmask |= 1 << ossdev; 4040 ctl->ossdev = ossdev; 4041 } 4042 } 4043 w->ctlflags |= fl; 4044 return (fl); 4045 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4046 i = 0; 4047 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4048 if (ctl->enable == 0 || ctl->widget == NULL) 4049 continue; 4050 /* XXX This should be compressed! */ 4051 if (((ctl->widget->nid == pnid && ctl->index == index && 4052 (ctl->dir & HDA_CTL_IN)) || 4053 (ctl->widget->nid == pnid && pw != NULL && 4054 pw->type == 4055 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4056 (pw->nconns < 2 || pw->selconn == index || 4057 pw->selconn == -1) && 4058 (ctl->dir & HDA_CTL_OUT)) || 4059 (strategy == HDA_PARSE_DIRECT && 4060 ctl->widget->nid == w->nid)) && 4061 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4062 if (pw != NULL && pw->selconn == -1) 4063 pw->selconn = index; 4064 fl |= SOUND_MASK_VOLUME; 4065 fl |= SOUND_MASK_SPEAKER; 4066 ctl->ossmask |= SOUND_MASK_VOLUME; 4067 ctl->ossmask |= SOUND_MASK_SPEAKER; 4068 ctl->ossdev = SOUND_MIXER_SPEAKER; 4069 } 4070 } 4071 w->ctlflags |= fl; 4072 return (fl); 4073 } 4074 return (0); 4075} 4076 4077static uint32_t 4078hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4079{ 4080 struct hdac_widget *w, *cw; 4081 struct hdac_audio_ctl *ctl; 4082 uint32_t fl; 4083 int i; 4084 4085 if (depth > HDA_PARSE_MAXDEPTH) 4086 return (0); 4087 4088 w = hdac_widget_get(devinfo, nid); 4089 if (w == NULL || w->enable == 0) 4090 return (0); 4091 /*if (!(w->pflags & HDA_ADC_PATH)) 4092 return (0); 4093 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4094 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4095 return (0);*/ 4096 i = 0; 4097 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4098 if (ctl->enable == 0 || ctl->widget == NULL) 4099 continue; 4100 if (ctl->widget->nid == nid) { 4101 ctl->ossmask |= SOUND_MASK_RECLEV; 4102 w->ctlflags |= SOUND_MASK_RECLEV; 4103 return (SOUND_MASK_RECLEV); 4104 } 4105 } 4106 for (i = 0; i < w->nconns; i++) { 4107 cw = hdac_widget_get(devinfo, w->conns[i]); 4108 if (cw == NULL || cw->enable == 0) 4109 continue; 4110 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4111 continue; 4112 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4113 if (fl != 0) { 4114 cw->ctlflags |= fl; 4115 w->ctlflags |= fl; 4116 return (fl); 4117 } 4118 } 4119 return (0); 4120} 4121 4122static int 4123hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4124{ 4125 struct hdac_widget *w, *cw; 4126 int i, child = 0; 4127 4128 if (depth > HDA_PARSE_MAXDEPTH) 4129 return (0); 4130 4131 w = hdac_widget_get(devinfo, nid); 4132 if (w == NULL || w->enable == 0) 4133 return (0); 4134 /*if (!(w->pflags & HDA_ADC_PATH)) 4135 return (0); 4136 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4137 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4138 return (0);*/ 4139 /* XXX weak! */ 4140 for (i = 0; i < w->nconns; i++) { 4141 cw = hdac_widget_get(devinfo, w->conns[i]); 4142 if (cw == NULL) 4143 continue; 4144 if (++child > 1) { 4145 w->pflags |= HDA_ADC_RECSEL; 4146 return (1); 4147 } 4148 } 4149 for (i = 0; i < w->nconns; i++) { 4150 if (hdac_audio_ctl_recsel_build(devinfo, 4151 w->conns[i], depth + 1) != 0) 4152 return (1); 4153 } 4154 return (0); 4155} 4156 4157static int 4158hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4159{ 4160 struct hdac_widget *w, *cw; 4161 int i, j, conndev, found_dac = 0; 4162 int strategy; 4163 4164 strategy = devinfo->function.audio.parsing_strategy; 4165 4166 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4167 w = hdac_widget_get(devinfo, i); 4168 if (w == NULL || w->enable == 0) 4169 continue; 4170 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4171 continue; 4172 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4173 continue; 4174 conndev = w->wclass.pin.config & 4175 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4176 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4177 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4178 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4179 continue; 4180 for (j = 0; j < w->nconns; j++) { 4181 cw = hdac_widget_get(devinfo, w->conns[j]); 4182 if (cw == NULL || cw->enable == 0) 4183 continue; 4184 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4185 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4186 cw->type == 4187 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4188 continue; 4189 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4190 != 0) { 4191 if (w->selconn == -1) 4192 w->selconn = j; 4193 w->pflags |= HDA_DAC_PATH; 4194 found_dac++; 4195 } 4196 } 4197 } 4198 4199 return (found_dac); 4200} 4201 4202static void 4203hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4204{ 4205 struct hdac_widget *w; 4206 struct hdac_audio_ctl *ctl; 4207 int i, j, dacs, strategy; 4208 4209 /* Construct DAC path */ 4210 strategy = HDA_PARSE_MIXER; 4211 devinfo->function.audio.parsing_strategy = strategy; 4212 HDA_BOOTVERBOSE( 4213 device_printf(devinfo->codec->sc->dev, 4214 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4215 HDA_WIDGET_PARSER_REV); 4216 ); 4217 dacs = hdac_audio_build_tree_strategy(devinfo); 4218 if (dacs == 0) { 4219 HDA_BOOTVERBOSE( 4220 device_printf(devinfo->codec->sc->dev, 4221 "HDA_DEBUG: HWiP: 0 DAC path found! " 4222 "Retrying parser " 4223 "using HDA_PARSE_DIRECT strategy.\n"); 4224 ); 4225 strategy = HDA_PARSE_DIRECT; 4226 devinfo->function.audio.parsing_strategy = strategy; 4227 dacs = hdac_audio_build_tree_strategy(devinfo); 4228 } 4229 4230 HDA_BOOTVERBOSE( 4231 device_printf(devinfo->codec->sc->dev, 4232 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4233 "strategy.\n", 4234 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4235 ); 4236 4237 /* Construct ADC path */ 4238 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4239 w = hdac_widget_get(devinfo, i); 4240 if (w == NULL || w->enable == 0) 4241 continue; 4242 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4243 continue; 4244 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4245 } 4246 4247 /* Output mixers */ 4248 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4249 w = hdac_widget_get(devinfo, i); 4250 if (w == NULL || w->enable == 0) 4251 continue; 4252 if ((strategy == HDA_PARSE_MIXER && 4253 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4254 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4255 && (w->pflags & HDA_DAC_PATH)) || 4256 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4257 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4258 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4259 w->nid, devinfo->startnode - 1, 0, 0); 4260 } else if (w->type == 4261 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4262 j = 0; 4263 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4264 NULL) { 4265 if (ctl->enable == 0 || ctl->widget == NULL) 4266 continue; 4267 if (ctl->widget->nid != w->nid) 4268 continue; 4269 ctl->ossmask |= SOUND_MASK_VOLUME; 4270 ctl->ossmask |= SOUND_MASK_SPEAKER; 4271 ctl->ossdev = SOUND_MIXER_SPEAKER; 4272 w->ctlflags |= SOUND_MASK_VOLUME; 4273 w->ctlflags |= SOUND_MASK_SPEAKER; 4274 } 4275 } 4276 } 4277 4278 /* Input mixers (rec) */ 4279 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4280 w = hdac_widget_get(devinfo, i); 4281 if (w == NULL || w->enable == 0) 4282 continue; 4283 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4284 w->pflags & HDA_ADC_PATH)) 4285 continue; 4286 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4287 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4288 } 4289} 4290 4291#define HDA_COMMIT_CONN (1 << 0) 4292#define HDA_COMMIT_CTRL (1 << 1) 4293#define HDA_COMMIT_EAPD (1 << 2) 4294#define HDA_COMMIT_GPIO (1 << 3) 4295#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4296 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4297 4298static void 4299hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4300{ 4301 struct hdac_softc *sc = devinfo->codec->sc; 4302 struct hdac_widget *w; 4303 nid_t cad; 4304 int i; 4305 4306 if (!(cfl & HDA_COMMIT_ALL)) 4307 return; 4308 4309 cad = devinfo->codec->cad; 4310 4311 if (cfl & HDA_COMMIT_GPIO) { 4312 uint32_t gdata, gmask, gdir; 4313 int commitgpio = 0; 4314 4315 gdata = 0; 4316 gmask = 0; 4317 gdir = 0; 4318 4319 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4320 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4321 0x7e7, 0), cad); 4322 4323 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4324 commitgpio = 1; 4325 else { 4326 for (i = 0; i < HDA_GPIO_MAX; i++) { 4327 if (!(devinfo->function.audio.quirks & 4328 (1 << i))) 4329 continue; 4330 if (commitgpio == 0) { 4331 commitgpio = 1; 4332 gdata = hdac_command(sc, 4333 HDA_CMD_GET_GPIO_DATA(cad, 4334 devinfo->nid), cad); 4335 gmask = hdac_command(sc, 4336 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4337 devinfo->nid), cad); 4338 gdir = hdac_command(sc, 4339 HDA_CMD_GET_GPIO_DIRECTION(cad, 4340 devinfo->nid), cad); 4341 HDA_BOOTVERBOSE( 4342 device_printf(sc->dev, 4343 "GPIO init: data=0x%08x " 4344 "mask=0x%08x dir=0x%08x\n", 4345 gdata, gmask, gdir); 4346 ); 4347 } 4348 gdata |= 1 << i; 4349 gmask |= 1 << i; 4350 gdir |= 1 << i; 4351 } 4352 } 4353 4354 if (commitgpio != 0) { 4355 HDA_BOOTVERBOSE( 4356 device_printf(sc->dev, 4357 "GPIO commit: data=0x%08x mask=0x%08x " 4358 "dir=0x%08x\n", 4359 gdata, gmask, gdir); 4360 ); 4361 hdac_command(sc, 4362 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4363 gmask), cad); 4364 hdac_command(sc, 4365 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4366 gdir), cad); 4367 hdac_command(sc, 4368 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4369 gdata), cad); 4370 } 4371 } 4372 4373 for (i = 0; i < devinfo->nodecnt; i++) { 4374 w = &devinfo->widget[i]; 4375 if (w == NULL || w->enable == 0) 4376 continue; 4377 if (cfl & HDA_COMMIT_CONN) { 4378 if (w->selconn == -1) 4379 w->selconn = 0; 4380 if (w->nconns > 0) 4381 hdac_widget_connection_select(w, w->selconn); 4382 } 4383 if ((cfl & HDA_COMMIT_CTRL) && 4384 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4385 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4386 (HDA_DAC_PATH | HDA_ADC_PATH)) 4387 device_printf(sc->dev, "WARNING: node %d " 4388 "participate both for DAC/ADC!\n", w->nid); 4389 if (w->pflags & HDA_DAC_PATH) { 4390 w->wclass.pin.ctrl &= 4391 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4392 if ((w->wclass.pin.config & 4393 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4394 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4395 w->wclass.pin.ctrl &= 4396 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4397 } else if (w->pflags & HDA_ADC_PATH) { 4398 w->wclass.pin.ctrl &= 4399 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4400 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4401 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4402 uint32_t pincap = w->wclass.pin.cap; 4403 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4404 w->wclass.pin.ctrl |= 4405 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4406 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4407 ); 4408 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4409 w->wclass.pin.ctrl |= 4410 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4411 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4412 ); 4413 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4414 w->wclass.pin.ctrl |= 4415 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4416 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4417 ); 4418 } 4419 } else 4420 w->wclass.pin.ctrl &= ~( 4421 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4422 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4423 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4424 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4425 hdac_command(sc, 4426 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4427 w->wclass.pin.ctrl), cad); 4428 } 4429 if ((cfl & HDA_COMMIT_EAPD) && 4430 w->param.eapdbtl != HDAC_INVALID) { 4431 uint32_t val; 4432 4433 val = w->param.eapdbtl; 4434 if (devinfo->function.audio.quirks & 4435 HDA_QUIRK_EAPDINV) 4436 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4437 hdac_command(sc, 4438 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4439 val), cad); 4440 4441 } 4442 DELAY(1000); 4443 } 4444} 4445 4446static void 4447hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4448{ 4449 struct hdac_softc *sc = devinfo->codec->sc; 4450 struct hdac_audio_ctl *ctl; 4451 int i; 4452 4453 devinfo->function.audio.mvol = 100 | (100 << 8); 4454 i = 0; 4455 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4456 if (ctl->enable == 0 || ctl->widget == NULL) { 4457 HDA_BOOTVERBOSE( 4458 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4459 i, (ctl->widget != NULL) ? 4460 ctl->widget->nid : -1); 4461 if (ctl->childwidget != NULL) 4462 printf(" childnid=%d", 4463 ctl->childwidget->nid); 4464 if (ctl->widget == NULL) 4465 printf(" NULL WIDGET!"); 4466 printf(" DISABLED\n"); 4467 ); 4468 continue; 4469 } 4470 HDA_BOOTVERBOSE( 4471 if (ctl->ossmask == 0) { 4472 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4473 i, ctl->widget->nid); 4474 if (ctl->childwidget != NULL) 4475 printf(" childnid=%d", 4476 ctl->childwidget->nid); 4477 printf(" Bind to NONE\n"); 4478 } 4479 ); 4480 if (ctl->step > 0) { 4481 ctl->ossval = (ctl->left * 100) / ctl->step; 4482 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4483 } else 4484 ctl->ossval = 0; 4485 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4486 ctl->left, ctl->right); 4487 } 4488} 4489 4490static int 4491hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4492{ 4493 struct hdac_chan *ch; 4494 struct hdac_widget *w; 4495 uint32_t cap, fmtcap, pcmcap, path; 4496 int i, type, ret, max; 4497 4498 if (dir == PCMDIR_PLAY) { 4499 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4500 ch = &devinfo->codec->sc->play; 4501 path = HDA_DAC_PATH; 4502 } else { 4503 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4504 ch = &devinfo->codec->sc->rec; 4505 path = HDA_ADC_PATH; 4506 } 4507 4508 ch->caps = hdac_caps; 4509 ch->caps.fmtlist = ch->fmtlist; 4510 ch->bit16 = 1; 4511 ch->bit32 = 0; 4512 ch->pcmrates[0] = 48000; 4513 ch->pcmrates[1] = 0; 4514 4515 ret = 0; 4516 fmtcap = devinfo->function.audio.supp_stream_formats; 4517 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4518 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4519 4520 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4521 w = hdac_widget_get(devinfo, i); 4522 if (w == NULL || w->enable == 0 || w->type != type || 4523 !(w->pflags & path)) 4524 continue; 4525 cap = w->param.widget_cap; 4526 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4527 continue;*/ 4528 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4529 continue; 4530 cap = w->param.supp_stream_formats; 4531 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4532 } 4533 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4534 }*/ 4535 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4536 continue; 4537 if (ret == 0) { 4538 fmtcap = w->param.supp_stream_formats; 4539 pcmcap = w->param.supp_pcm_size_rate; 4540 } else { 4541 fmtcap &= w->param.supp_stream_formats; 4542 pcmcap &= w->param.supp_pcm_size_rate; 4543 } 4544 ch->io[ret++] = i; 4545 } 4546 ch->io[ret] = -1; 4547 4548 ch->supp_stream_formats = fmtcap; 4549 ch->supp_pcm_size_rate = pcmcap; 4550 4551 /* 4552 * 8bit = 0 4553 * 16bit = 1 4554 * 20bit = 2 4555 * 24bit = 3 4556 * 32bit = 4 4557 */ 4558 if (ret > 0) { 4559 cap = pcmcap; 4560 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4561 ch->bit16 = 1; 4562 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4563 ch->bit16 = 0; 4564 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4565 ch->bit32 = 4; 4566 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4567 ch->bit32 = 3; 4568 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4569 ch->bit32 = 2; 4570 i = 0; 4571 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4572 ch->fmtlist[i++] = AFMT_S16_LE; 4573 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4574 if (ch->bit32 > 0) { 4575 if (!(devinfo->function.audio.quirks & 4576 HDA_QUIRK_FORCESTEREO)) 4577 ch->fmtlist[i++] = AFMT_S32_LE; 4578 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4579 } 4580 ch->fmtlist[i] = 0; 4581 i = 0; 4582 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4583 ch->pcmrates[i++] = 8000; 4584 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4585 ch->pcmrates[i++] = 11025; 4586 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4587 ch->pcmrates[i++] = 16000; 4588 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4589 ch->pcmrates[i++] = 22050; 4590 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4591 ch->pcmrates[i++] = 32000; 4592 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4593 ch->pcmrates[i++] = 44100; 4594 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4595 ch->pcmrates[i++] = 48000; 4596 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4597 ch->pcmrates[i++] = 88200; 4598 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4599 ch->pcmrates[i++] = 96000; 4600 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4601 ch->pcmrates[i++] = 176400; 4602 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4603 ch->pcmrates[i++] = 192000; 4604 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4605 ch->pcmrates[i] = 0; 4606 if (i > 0) { 4607 ch->caps.minspeed = ch->pcmrates[0]; 4608 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4609 } 4610 } 4611 4612 return (ret); 4613} 4614 4615static void 4616hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4617{ 4618 struct hdac_audio_ctl *ctl; 4619 struct hdac_softc *sc = devinfo->codec->sc; 4620 int i; 4621 uint32_t fl = 0; 4622 4623 4624 if (flag == 0) { 4625 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4626 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4627 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4628 } 4629 4630 i = 0; 4631 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4632 if (ctl->enable == 0 || ctl->widget == NULL || 4633 ctl->widget->enable == 0) 4634 continue; 4635 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4636 (flag != 0 && (ctl->ossmask & flag))) { 4637 if (banner != NULL) { 4638 device_printf(sc->dev, "\n"); 4639 device_printf(sc->dev, "%s\n", banner); 4640 } 4641 goto hdac_ctl_dump_it_all; 4642 } 4643 } 4644 4645 return; 4646 4647hdac_ctl_dump_it_all: 4648 i = 0; 4649 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4650 if (ctl->enable == 0 || ctl->widget == NULL || 4651 ctl->widget->enable == 0) 4652 continue; 4653 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4654 (flag != 0 && (ctl->ossmask & flag)))) 4655 continue; 4656 if (flag == 0) { 4657 device_printf(sc->dev, "\n"); 4658 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4659 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4660 } 4661 device_printf(sc->dev, " |\n"); 4662 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4663 ctl->widget->nid, ctl->index); 4664 if (ctl->childwidget != NULL) 4665 printf("(nid: %2d) ", ctl->childwidget->nid); 4666 else 4667 printf(" "); 4668 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4669 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4670 ctl->ossmask); 4671 } 4672} 4673 4674static void 4675hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4676{ 4677 uint32_t cap; 4678 4679 cap = fcap; 4680 if (cap != 0) { 4681 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4682 device_printf(sc->dev, " Format:"); 4683 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4684 printf(" AC3"); 4685 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4686 printf(" FLOAT32"); 4687 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4688 printf(" PCM"); 4689 printf("\n"); 4690 } 4691 cap = pcmcap; 4692 if (cap != 0) { 4693 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4694 device_printf(sc->dev, " PCM size:"); 4695 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4696 printf(" 8"); 4697 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4698 printf(" 16"); 4699 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4700 printf(" 20"); 4701 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4702 printf(" 24"); 4703 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4704 printf(" 32"); 4705 printf("\n"); 4706 device_printf(sc->dev, " PCM rate:"); 4707 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4708 printf(" 8"); 4709 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4710 printf(" 11"); 4711 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4712 printf(" 16"); 4713 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4714 printf(" 22"); 4715 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4716 printf(" 32"); 4717 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4718 printf(" 44"); 4719 printf(" 48"); 4720 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4721 printf(" 88"); 4722 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4723 printf(" 96"); 4724 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4725 printf(" 176"); 4726 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4727 printf(" 192"); 4728 printf("\n"); 4729 } 4730} 4731 4732static void 4733hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4734{ 4735 uint32_t pincap, wcap; 4736 4737 pincap = w->wclass.pin.cap; 4738 wcap = w->param.widget_cap; 4739 4740 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4741 device_printf(sc->dev, " "); 4742 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4743 printf(" ISC"); 4744 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4745 printf(" TRQD"); 4746 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4747 printf(" PDC"); 4748 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4749 printf(" HP"); 4750 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4751 printf(" OUT"); 4752 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4753 printf(" IN"); 4754 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4755 printf(" BAL"); 4756 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4757 printf(" VREF["); 4758 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4759 printf(" 50"); 4760 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4761 printf(" 80"); 4762 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4763 printf(" 100"); 4764 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4765 printf(" GROUND"); 4766 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4767 printf(" HIZ"); 4768 printf(" ]"); 4769 } 4770 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4771 printf(" EAPD"); 4772 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4773 printf(" : UNSOL"); 4774 printf("\n"); 4775 device_printf(sc->dev, " Pin config: 0x%08x\n", 4776 w->wclass.pin.config); 4777 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4778 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4779 printf(" HP"); 4780 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4781 printf(" IN"); 4782 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4783 printf(" OUT"); 4784 printf("\n"); 4785} 4786 4787static void 4788hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4789{ 4790 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4791 device_printf(sc->dev, " " 4792 "mute=%d step=%d size=%d offset=%d\n", 4793 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4794 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4795 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4796 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4797} 4798 4799static void 4800hdac_dump_nodes(struct hdac_devinfo *devinfo) 4801{ 4802 struct hdac_softc *sc = devinfo->codec->sc; 4803 struct hdac_widget *w, *cw; 4804 int i, j; 4805 4806 device_printf(sc->dev, "\n"); 4807 device_printf(sc->dev, "Default Parameter\n"); 4808 device_printf(sc->dev, "-----------------\n"); 4809 hdac_dump_audio_formats(sc, 4810 devinfo->function.audio.supp_stream_formats, 4811 devinfo->function.audio.supp_pcm_size_rate); 4812 device_printf(sc->dev, " IN amp: 0x%08x\n", 4813 devinfo->function.audio.inamp_cap); 4814 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4815 devinfo->function.audio.outamp_cap); 4816 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4817 w = hdac_widget_get(devinfo, i); 4818 if (w == NULL) { 4819 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4820 continue; 4821 } 4822 device_printf(sc->dev, "\n"); 4823 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4824 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4825 "DIGITAL" : "ANALOG", 4826 (w->enable == 0) ? " [DISABLED]" : ""); 4827 device_printf(sc->dev, " name: %s\n", w->name); 4828 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4829 w->param.widget_cap); 4830 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4831 w->pflags); 4832 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4833 w->ctlflags); 4834 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4835 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4836 hdac_dump_audio_formats(sc, 4837 w->param.supp_stream_formats, 4838 w->param.supp_pcm_size_rate); 4839 } else if (w->type == 4840 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4841 hdac_dump_pin(sc, w); 4842 if (w->param.eapdbtl != HDAC_INVALID) 4843 device_printf(sc->dev, " EAPD: 0x%08x\n", 4844 w->param.eapdbtl); 4845 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4846 w->param.outamp_cap != 0) 4847 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4848 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4849 w->param.inamp_cap != 0) 4850 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4851 device_printf(sc->dev, " connections: %d\n", w->nconns); 4852 for (j = 0; j < w->nconns; j++) { 4853 cw = hdac_widget_get(devinfo, w->conns[j]); 4854 device_printf(sc->dev, " |\n"); 4855 device_printf(sc->dev, " + <- nid=%d [%s]", 4856 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4857 if (cw == NULL) 4858 printf(" [UNKNOWN]"); 4859 else if (cw->enable == 0) 4860 printf(" [DISABLED]"); 4861 if (w->nconns > 1 && w->selconn == j && w->type != 4862 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4863 printf(" (selected)"); 4864 printf("\n"); 4865 } 4866 } 4867 4868} 4869 4870static int 4871hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4872{ 4873 struct hdac_widget *w, *cw; 4874 struct hdac_softc *sc = devinfo->codec->sc; 4875 int i; 4876 4877 if (depth > HDA_PARSE_MAXDEPTH) 4878 return (0); 4879 4880 w = hdac_widget_get(devinfo, nid); 4881 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4882 return (0); 4883 4884 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4885 device_printf(sc->dev, "\n"); 4886 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4887 device_printf(sc->dev, " ^\n"); 4888 device_printf(sc->dev, " |\n"); 4889 device_printf(sc->dev, " +-----<------+\n"); 4890 } else { 4891 device_printf(sc->dev, " ^\n"); 4892 device_printf(sc->dev, " |\n"); 4893 device_printf(sc->dev, " "); 4894 printf(" nid=%d [%s]\n", w->nid, w->name); 4895 } 4896 4897 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4898 return (1); 4899 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4900 for (i = 0; i < w->nconns; i++) { 4901 cw = hdac_widget_get(devinfo, w->conns[i]); 4902 if (cw == NULL || cw->enable == 0 || cw->type == 4903 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4904 continue; 4905 if (hdac_dump_dac_internal(devinfo, cw->nid, 4906 depth + 1) != 0) 4907 return (1); 4908 } 4909 } else if ((w->type == 4910 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4911 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4912 w->selconn > -1 && w->selconn < w->nconns) { 4913 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4914 depth + 1) != 0) 4915 return (1); 4916 } 4917 4918 return (0); 4919} 4920 4921static void 4922hdac_dump_dac(struct hdac_devinfo *devinfo) 4923{ 4924 struct hdac_widget *w; 4925 struct hdac_softc *sc = devinfo->codec->sc; 4926 int i, printed = 0; 4927 4928 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4929 w = hdac_widget_get(devinfo, i); 4930 if (w == NULL || w->enable == 0) 4931 continue; 4932 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4933 !(w->pflags & HDA_DAC_PATH)) 4934 continue; 4935 if (printed == 0) { 4936 printed = 1; 4937 device_printf(sc->dev, "\n"); 4938 device_printf(sc->dev, "Playback path:\n"); 4939 } 4940 hdac_dump_dac_internal(devinfo, w->nid, 0); 4941 } 4942} 4943 4944static void 4945hdac_dump_adc(struct hdac_devinfo *devinfo) 4946{ 4947 struct hdac_widget *w, *cw; 4948 struct hdac_softc *sc = devinfo->codec->sc; 4949 int i, j; 4950 int printed = 0; 4951 char ossdevs[256]; 4952 4953 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4954 w = hdac_widget_get(devinfo, i); 4955 if (w == NULL || w->enable == 0) 4956 continue; 4957 if (!(w->pflags & HDA_ADC_RECSEL)) 4958 continue; 4959 if (printed == 0) { 4960 printed = 1; 4961 device_printf(sc->dev, "\n"); 4962 device_printf(sc->dev, "Recording sources:\n"); 4963 } 4964 device_printf(sc->dev, "\n"); 4965 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4966 for (j = 0; j < w->nconns; j++) { 4967 cw = hdac_widget_get(devinfo, w->conns[j]); 4968 if (cw == NULL || cw->enable == 0) 4969 continue; 4970 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4971 ossdevs, sizeof(ossdevs)); 4972 device_printf(sc->dev, " |\n"); 4973 device_printf(sc->dev, " + <- nid=%d [%s]", 4974 cw->nid, cw->name); 4975 if (strlen(ossdevs) > 0) { 4976 printf(" [recsrc: %s]", ossdevs); 4977 } 4978 printf("\n"); 4979 } 4980 } 4981} 4982 4983static void 4984hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4985{ 4986 nid_t *nids; 4987 4988 if (pcnt > 0) { 4989 device_printf(sc->dev, "\n"); 4990 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4991 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4992 sc->play.supp_pcm_size_rate); 4993 device_printf(sc->dev, " DAC:"); 4994 for (nids = sc->play.io; *nids != -1; nids++) 4995 printf(" %d", *nids); 4996 printf("\n"); 4997 } 4998 4999 if (rcnt > 0) { 5000 device_printf(sc->dev, "\n"); 5001 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5002 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5003 sc->rec.supp_pcm_size_rate); 5004 device_printf(sc->dev, " ADC:"); 5005 for (nids = sc->rec.io; *nids != -1; nids++) 5006 printf(" %d", *nids); 5007 printf("\n"); 5008 } 5009} 5010 5011static void 5012hdac_release_resources(struct hdac_softc *sc) 5013{ 5014 struct hdac_devinfo *devinfo = NULL; 5015 device_t *devlist = NULL; 5016 int i, devcount; 5017 5018 if (sc == NULL) 5019 return; 5020 5021 hdac_lock(sc); 5022 if (sc->polling != 0) 5023 callout_stop(&sc->poll_hdac); 5024 hdac_reset(sc); 5025 hdac_unlock(sc); 5026 snd_mtxfree(sc->lock); 5027 5028 device_get_children(sc->dev, &devlist, &devcount); 5029 for (i = 0; devlist != NULL && i < devcount; i++) { 5030 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5031 if (devinfo == NULL) 5032 continue; 5033 if (devinfo->widget != NULL) 5034 free(devinfo->widget, M_HDAC); 5035 if (devinfo->node_type == 5036 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5037 devinfo->function.audio.ctl != NULL) 5038 free(devinfo->function.audio.ctl, M_HDAC); 5039 free(devinfo, M_HDAC); 5040 device_delete_child(sc->dev, devlist[i]); 5041 } 5042 if (devlist != NULL) 5043 free(devlist, M_TEMP); 5044 5045 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5046 if (sc->codecs[i] != NULL) 5047 free(sc->codecs[i], M_HDAC); 5048 sc->codecs[i] = NULL; 5049 } 5050 5051 hdac_dma_free(&sc->rirb_dma); 5052 hdac_dma_free(&sc->corb_dma); 5053 if (sc->play.blkcnt > 0) 5054 hdac_dma_free(&sc->play.bdl_dma); 5055 if (sc->rec.blkcnt > 0) 5056 hdac_dma_free(&sc->rec.bdl_dma); 5057 hdac_irq_free(sc); 5058 hdac_mem_free(sc); 5059 free(sc, M_DEVBUF); 5060 5061} 5062 5063/* This function surely going to make its way into upper level someday. */ 5064static void 5065hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5066{ 5067 const char *res = NULL; 5068 int i = 0, j, k, len, inv; 5069 5070 if (on != NULL) 5071 *on = 0; 5072 if (off != NULL) 5073 *off = 0; 5074 if (sc == NULL) 5075 return; 5076 if (resource_string_value(device_get_name(sc->dev), 5077 device_get_unit(sc->dev), "config", &res) != 0) 5078 return; 5079 if (!(res != NULL && strlen(res) > 0)) 5080 return; 5081 HDA_BOOTVERBOSE( 5082 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5083 ); 5084 for (;;) { 5085 while (res[i] != '\0' && 5086 (res[i] == ',' || isspace(res[i]) != 0)) 5087 i++; 5088 if (res[i] == '\0') { 5089 HDA_BOOTVERBOSE( 5090 printf("\n"); 5091 ); 5092 return; 5093 } 5094 j = i; 5095 while (res[j] != '\0' && 5096 !(res[j] == ',' || isspace(res[j]) != 0)) 5097 j++; 5098 len = j - i; 5099 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5100 inv = 2; 5101 else 5102 inv = 0; 5103 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5104 if (strncmp(res + i + inv, 5105 hdac_quirks_tab[k].key, len - inv) != 0) 5106 continue; 5107 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5108 break; 5109 HDA_BOOTVERBOSE( 5110 printf(" %s%s", (inv != 0) ? "no" : "", 5111 hdac_quirks_tab[k].key); 5112 ); 5113 if (inv == 0 && on != NULL) 5114 *on |= hdac_quirks_tab[k].value; 5115 else if (inv != 0 && off != NULL) 5116 *off |= hdac_quirks_tab[k].value; 5117 break; 5118 } 5119 i = j; 5120 } 5121} 5122 5123#ifdef SND_DYNSYSCTL 5124static int 5125sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5126{ 5127 struct hdac_softc *sc; 5128 struct hdac_devinfo *devinfo; 5129 device_t dev; 5130 uint32_t ctl; 5131 int err, val; 5132 5133 dev = oidp->oid_arg1; 5134 devinfo = pcm_getdevinfo(dev); 5135 if (devinfo == NULL || devinfo->codec == NULL || 5136 devinfo->codec->sc == NULL) 5137 return (EINVAL); 5138 sc = devinfo->codec->sc; 5139 hdac_lock(sc); 5140 val = sc->polling; 5141 hdac_unlock(sc); 5142 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5143 5144 if (err || req->newptr == NULL) 5145 return (err); 5146 if (val < 0 || val > 1) 5147 return (EINVAL); 5148 5149 hdac_lock(sc); 5150 if (val != sc->polling) { 5151 if (hda_chan_active(sc) != 0) 5152 err = EBUSY; 5153 else if (val == 0) { 5154 callout_stop(&sc->poll_hdac); 5155 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5156 sc->rirb_size / 2); 5157 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5158 ctl |= HDAC_RIRBCTL_RINTCTL; 5159 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5160 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5161 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5162 sc->polling = 0; 5163 DELAY(1000); 5164 } else { 5165 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5166 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5167 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5168 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5169 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5170 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5171 sc); 5172 sc->polling = 1; 5173 DELAY(1000); 5174 } 5175 } 5176 hdac_unlock(sc); 5177 5178 return (err); 5179} 5180#endif 5181 5182static void 5183hdac_attach2(void *arg) 5184{ 5185 struct hdac_softc *sc; 5186 struct hdac_widget *w; 5187 struct hdac_audio_ctl *ctl; 5188 uint32_t quirks_on, quirks_off; 5189 int pcnt, rcnt; 5190 int i; 5191 char status[SND_STATUSLEN]; 5192 device_t *devlist = NULL; 5193 int devcount; 5194 struct hdac_devinfo *devinfo = NULL; 5195 5196 sc = (struct hdac_softc *)arg; 5197 5198 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5199 5200 HDA_BOOTVERBOSE( 5201 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5202 quirks_on, quirks_off); 5203 ); 5204 5205 hdac_lock(sc); 5206 5207 /* Remove ourselves from the config hooks */ 5208 if (sc->intrhook.ich_func != NULL) { 5209 config_intrhook_disestablish(&sc->intrhook); 5210 sc->intrhook.ich_func = NULL; 5211 } 5212 5213 /* Start the corb and rirb engines */ 5214 HDA_BOOTVERBOSE( 5215 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5216 ); 5217 hdac_corb_start(sc); 5218 HDA_BOOTVERBOSE( 5219 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5220 ); 5221 hdac_rirb_start(sc); 5222 5223 HDA_BOOTVERBOSE( 5224 device_printf(sc->dev, 5225 "HDA_DEBUG: Enabling controller interrupt...\n"); 5226 ); 5227 if (sc->polling == 0) 5228 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5229 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5230 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5231 HDAC_GCTL_UNSOL); 5232 5233 DELAY(1000); 5234 5235 HDA_BOOTVERBOSE( 5236 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5237 ); 5238 hdac_scan_codecs(sc); 5239 5240 device_get_children(sc->dev, &devlist, &devcount); 5241 for (i = 0; devlist != NULL && i < devcount; i++) { 5242 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5243 if (devinfo != NULL && devinfo->node_type == 5244 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5245 break; 5246 } else 5247 devinfo = NULL; 5248 } 5249 if (devlist != NULL) 5250 free(devlist, M_TEMP); 5251 5252 if (devinfo == NULL) { 5253 hdac_unlock(sc); 5254 device_printf(sc->dev, "Audio Function Group not found!\n"); 5255 hdac_release_resources(sc); 5256 return; 5257 } 5258 5259 HDA_BOOTVERBOSE( 5260 device_printf(sc->dev, 5261 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5262 devinfo->nid, devinfo->codec->cad); 5263 ); 5264 hdac_audio_parse(devinfo); 5265 HDA_BOOTVERBOSE( 5266 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5267 ); 5268 hdac_audio_ctl_parse(devinfo); 5269 HDA_BOOTVERBOSE( 5270 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5271 ); 5272 hdac_vendor_patch_parse(devinfo); 5273 if (quirks_on != 0) 5274 devinfo->function.audio.quirks |= quirks_on; 5275 if (quirks_off != 0) 5276 devinfo->function.audio.quirks &= ~quirks_off; 5277 5278 /* XXX Disable all DIGITAL path. */ 5279 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5280 w = hdac_widget_get(devinfo, i); 5281 if (w == NULL) 5282 continue; 5283 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5284 w->enable = 0; 5285 continue; 5286 } 5287 /* XXX Disable useless pin ? */ 5288 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5289 (w->wclass.pin.config & 5290 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5291 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5292 w->enable = 0; 5293 } 5294 i = 0; 5295 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5296 if (ctl->widget == NULL) 5297 continue; 5298 w = ctl->widget; 5299 if (w->enable == 0) 5300 ctl->enable = 0; 5301 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5302 ctl->enable = 0; 5303 w = ctl->childwidget; 5304 if (w == NULL) 5305 continue; 5306 if (w->enable == 0 || 5307 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5308 ctl->enable = 0; 5309 } 5310 5311 HDA_BOOTVERBOSE( 5312 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5313 ); 5314 hdac_audio_build_tree(devinfo); 5315 5316 HDA_BOOTVERBOSE( 5317 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5318 ); 5319 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5320 HDA_BOOTVERBOSE( 5321 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5322 ); 5323 hdac_audio_ctl_commit(devinfo); 5324 5325 HDA_BOOTVERBOSE( 5326 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5327 ); 5328 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5329 HDA_BOOTVERBOSE( 5330 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5331 ); 5332 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5333 5334 hdac_unlock(sc); 5335 HDA_BOOTVERBOSE( 5336 device_printf(sc->dev, 5337 "HDA_DEBUG: OSS mixer initialization...\n"); 5338 ); 5339 5340 /* 5341 * There is no point of return after this. If the driver failed, 5342 * so be it. Let the detach procedure do all the cleanup. 5343 */ 5344 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5345 device_printf(sc->dev, "Can't register mixer\n"); 5346 5347 if (pcnt > 0) 5348 pcnt = 1; 5349 if (rcnt > 0) 5350 rcnt = 1; 5351 5352 HDA_BOOTVERBOSE( 5353 device_printf(sc->dev, 5354 "HDA_DEBUG: Registering PCM channels...\n"); 5355 ); 5356 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5357 device_printf(sc->dev, "Can't register PCM\n"); 5358 5359 sc->registered++; 5360 5361 for (i = 0; i < pcnt; i++) 5362 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5363 for (i = 0; i < rcnt; i++) 5364 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5365 5366#ifdef SND_DYNSYSCTL 5367 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5368 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5369 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5370 sysctl_hdac_polling, "I", "Enable polling mode"); 5371#endif 5372 5373 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5374 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5375 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5376 pcm_setstatus(sc->dev, status); 5377 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5378 HDA_BOOTVERBOSE( 5379 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5380 hdac_codec_id(devinfo)); 5381 ); 5382 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5383 HDA_DRV_TEST_REV); 5384 5385 HDA_BOOTVERBOSE( 5386 if (devinfo->function.audio.quirks != 0) { 5387 device_printf(sc->dev, "\n"); 5388 device_printf(sc->dev, "HDA config/quirks:"); 5389 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5390 if (devinfo->function.audio.quirks & 5391 hdac_quirks_tab[i].value) 5392 printf(" %s", hdac_quirks_tab[i].key); 5393 } 5394 printf("\n"); 5395 } 5396 device_printf(sc->dev, "\n"); 5397 device_printf(sc->dev, "+-------------------+\n"); 5398 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5399 device_printf(sc->dev, "+-------------------+\n"); 5400 hdac_dump_nodes(devinfo); 5401 device_printf(sc->dev, "\n"); 5402 device_printf(sc->dev, "+------------------------+\n"); 5403 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5404 device_printf(sc->dev, "+------------------------+\n"); 5405 device_printf(sc->dev, "\n"); 5406 i = 0; 5407 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5408 device_printf(sc->dev, "%3d: nid=%d", i, 5409 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5410 if (ctl->childwidget != NULL) 5411 printf(" cnid=%d", ctl->childwidget->nid); 5412 printf(" dir=0x%x index=%d " 5413 "ossmask=0x%08x ossdev=%d%s\n", 5414 ctl->dir, ctl->index, 5415 ctl->ossmask, ctl->ossdev, 5416 (ctl->enable == 0) ? " [DISABLED]" : ""); 5417 } 5418 device_printf(sc->dev, "\n"); 5419 device_printf(sc->dev, "+-----------------------------------+\n"); 5420 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5421 device_printf(sc->dev, "+-----------------------------------+\n"); 5422 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5423 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5424 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5425 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5426 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5427 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5428 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5429 hdac_dump_ctls(devinfo, NULL, 0); 5430 hdac_dump_dac(devinfo); 5431 hdac_dump_adc(devinfo); 5432 device_printf(sc->dev, "\n"); 5433 device_printf(sc->dev, "+--------------------------------------+\n"); 5434 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5435 device_printf(sc->dev, "+--------------------------------------+\n"); 5436 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5437 ); 5438 5439 if (sc->polling != 0) { 5440 hdac_lock(sc); 5441 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5442 hdac_unlock(sc); 5443 } 5444} 5445 5446/**************************************************************************** 5447 * int hdac_detach(device_t) 5448 * 5449 * Detach and free up resources utilized by the hdac device. 5450 ****************************************************************************/ 5451static int 5452hdac_detach(device_t dev) 5453{ 5454 struct hdac_softc *sc = NULL; 5455 struct hdac_devinfo *devinfo = NULL; 5456 int err; 5457 5458 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5459 if (devinfo != NULL && devinfo->codec != NULL) 5460 sc = devinfo->codec->sc; 5461 if (sc == NULL) 5462 return (0); 5463 5464 if (sc->registered > 0) { 5465 err = pcm_unregister(dev); 5466 if (err != 0) 5467 return (err); 5468 } 5469 5470 hdac_release_resources(sc); 5471 5472 return (0); 5473} 5474 5475static device_method_t hdac_methods[] = { 5476 /* device interface */ 5477 DEVMETHOD(device_probe, hdac_probe), 5478 DEVMETHOD(device_attach, hdac_attach), 5479 DEVMETHOD(device_detach, hdac_detach), 5480 { 0, 0 } 5481}; 5482 5483static driver_t hdac_driver = { 5484 "pcm", 5485 hdac_methods, 5486 PCM_SOFTC_SIZE, 5487}; 5488 5489DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5490MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5491MODULE_VERSION(snd_hda, 1); 5492