hdac.c revision 167610
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20070316_0041" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 167610 2007-03-15 17:35:04Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* Intel */ 167#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168 169/* HP/Compaq */ 170#define HP_VENDORID 0x103c 171#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 176#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 177/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 178#define HP_NX6325_SUBVENDORX 0x103c30b0 179 180/* Dell */ 181#define DELL_VENDORID 0x1028 182#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 183#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 184#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 185 186/* Clevo */ 187#define CLEVO_VENDORID 0x1558 188#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 189#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 190 191/* Acer */ 192#define ACER_VENDORID 0x1025 193#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 194#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 195 196/* Asus */ 197#define ASUS_VENDORID 0x1043 198#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 199#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 200#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 201#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 202#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 203#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 204 205/* IBM / Lenovo */ 206#define IBM_VENDORID 0x1014 207#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 208#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 209 210/* Lenovo */ 211#define LENOVO_VENDORID 0x17aa 212#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 213#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 214 215/* Samsung */ 216#define SAMSUNG_VENDORID 0x144d 217#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 218#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 219 220/* Medion ? */ 221#define MEDION_VENDORID 0x161f 222#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 223#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 224 225/* 226 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 227 * instead of their own, which is beyond my comprehension 228 * (see HDA_CODEC_STAC9221 below). 229 */ 230#define APPLE_INTEL_MAC 0x76808384 231 232/* LG Electronics */ 233#define LG_VENDORID 0x1854 234#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 235#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 236 237/* Fujitsu Siemens */ 238#define FS_VENDORID 0x1734 239#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 240#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 241 242/* Toshiba */ 243#define TOSHIBA_VENDORID 0x1179 244#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 245#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 246 247/* Micro-Star International (MSI) */ 248#define MSI_VENDORID 0x1462 249#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 250#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 251 252/* Misc constants.. */ 253#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 254#define HDA_AMP_MUTE_NONE (0) 255#define HDA_AMP_MUTE_LEFT (1 << 0) 256#define HDA_AMP_MUTE_RIGHT (1 << 1) 257#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 258 259#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 260#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 261 262#define HDA_DAC_PATH (1 << 0) 263#define HDA_ADC_PATH (1 << 1) 264#define HDA_ADC_RECSEL (1 << 2) 265 266#define HDA_CTL_OUT (1 << 0) 267#define HDA_CTL_IN (1 << 1) 268#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 269 270#define HDA_GPIO_MAX 15 271/* 0 - 14 = GPIO */ 272#define HDA_QUIRK_GPIO0 (1 << 0) 273#define HDA_QUIRK_GPIO1 (1 << 1) 274#define HDA_QUIRK_GPIO2 (1 << 2) 275#define HDA_QUIRK_GPIOFLUSH (1 << 15) 276#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 277#define HDA_QUIRK_FIXEDRATE (1 << 17) 278#define HDA_QUIRK_FORCESTEREO (1 << 18) 279#define HDA_QUIRK_EAPDINV (1 << 19) 280#define HDA_QUIRK_VREF (1 << 20) 281 282static const struct { 283 char *key; 284 uint32_t value; 285} hdac_quirks_tab[] = { 286 { "gpio0", HDA_QUIRK_GPIO0 }, 287 { "gpio1", HDA_QUIRK_GPIO1 }, 288 { "gpio2", HDA_QUIRK_GPIO2 }, 289 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 290 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 291 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 292 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 293 { "eapdinv", HDA_QUIRK_EAPDINV }, 294 { "vref", HDA_QUIRK_VREF }, 295}; 296#define HDAC_QUIRKS_TAB_LEN \ 297 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 298 299#define HDA_BDL_MIN 2 300#define HDA_BDL_MAX 256 301#define HDA_BDL_DEFAULT HDA_BDL_MIN 302 303#define HDA_BUFSZ_MIN 4096 304#define HDA_BUFSZ_MAX 65536 305#define HDA_BUFSZ_DEFAULT 16384 306 307#define HDA_PARSE_MAXDEPTH 10 308 309#define HDAC_UNSOLTAG_EVENT_HP 0x00 310 311MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 312 313enum { 314 HDA_PARSE_MIXER, 315 HDA_PARSE_DIRECT 316}; 317 318/* Default */ 319static uint32_t hdac_fmt[] = { 320 AFMT_STEREO | AFMT_S16_LE, 321 0 322}; 323 324static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 325 326static const struct { 327 uint32_t model; 328 char *desc; 329} hdac_devices[] = { 330 { HDA_INTEL_82801F, "Intel 82801F" }, 331 { HDA_INTEL_82801G, "Intel 82801G" }, 332 { HDA_INTEL_82801H, "Intel 82801H" }, 333 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 334 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 335 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 336 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 337 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 338 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 339 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 340 { HDA_ATI_SB450, "ATI SB450" }, 341 { HDA_ATI_SB600, "ATI SB600" }, 342 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 343 { HDA_SIS_966, "SiS 966" }, 344 /* Unknown */ 345 { HDA_INTEL_ALL, "Intel (Unknown)" }, 346 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 347 { HDA_ATI_ALL, "ATI (Unknown)" }, 348 { HDA_VIA_ALL, "VIA (Unknown)" }, 349 { HDA_SIS_ALL, "SiS (Unknown)" }, 350}; 351#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 352 353static const struct { 354 uint32_t rate; 355 int valid; 356 uint16_t base; 357 uint16_t mul; 358 uint16_t div; 359} hda_rate_tab[] = { 360 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 361 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 362 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 363 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 364 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 365 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 366 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 367 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 368 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 369 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 370 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 371 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 372 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 373 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 374 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 375 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 376 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 377 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 378 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 379 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 380 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 381 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 382 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 383 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 384 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 385 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 386 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 387 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 388 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 389 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 390 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 391 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 392 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 393 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 394 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 395}; 396#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 397 398/* All codecs you can eat... */ 399#define HDA_CODEC_CONSTRUCT(vendor, id) \ 400 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 401 402/* Realtek */ 403#define REALTEK_VENDORID 0x10ec 404#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 405#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 406#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 407#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 408#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 409#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 410#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 411 412/* Analog Device */ 413#define ANALOGDEVICE_VENDORID 0x11d4 414#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 415#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 416#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 417#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 418 419/* CMedia */ 420#define CMEDIA_VENDORID 0x434d 421#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 422#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 423 424/* Sigmatel */ 425#define SIGMATEL_VENDORID 0x8384 426#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 427#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 428#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 429#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 430#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 431#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 432#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 433 434/* 435 * Conexant 436 * 437 * Ok, the truth is, I don't have any idea at all whether 438 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 439 * place that tell me it is "Venice" is from its Windows driver INF. 440 * 441 * Venice - CX????? 442 * Waikiki - CX20551-22 443 */ 444#define CONEXANT_VENDORID 0x14f1 445#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 446#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 447#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 448 449 450/* Codecs */ 451static const struct { 452 uint32_t id; 453 char *name; 454} hdac_codecs[] = { 455 { HDA_CODEC_ALC260, "Realtek ALC260" }, 456 { HDA_CODEC_ALC861, "Realtek ALC861" }, 457 { HDA_CODEC_ALC880, "Realtek ALC880" }, 458 { HDA_CODEC_ALC882, "Realtek ALC882" }, 459 { HDA_CODEC_ALC883, "Realtek ALC883" }, 460 { HDA_CODEC_ALC888, "Realtek ALC888" }, 461 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 462 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 463 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 464 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 465 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 466 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 467 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 468 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 469 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 470 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 471 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 472 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 473 /* Unknown codec */ 474 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 475 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 476 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 477 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 478 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 479}; 480#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 481 482enum { 483 HDAC_HP_SWITCH_CTL, 484 HDAC_HP_SWITCH_CTRL 485}; 486 487static const struct { 488 uint32_t model; 489 uint32_t id; 490 int type; 491 int inverted; 492 nid_t hpnid; 493 nid_t spkrnid[8]; 494 nid_t eapdnid; 495} hdac_hp_switch[] = { 496 /* Specific OEM models */ 497 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 498 17, { 16, -1 }, 16 }, 499 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 500 6, { 5, -1 }, 5 }, 501 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 502 6, { 5, -1 }, 5 }, 503 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 504 6, { 5, -1 }, 5 }, 505 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 506 6, { 5, -1 }, -1 }, 507 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 508 13, { 14, -1 }, -1 }, 509 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 510 13, { 14, -1 }, -1 }, 511 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 512 10, { 13, -1 }, -1 }, 513 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 514 26, { 27, -1 }, -1 }, 515 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 516 27, { 20, -1 }, -1 }, 517 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 518 20, { 21, -1 }, -1 }, 519 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 520 20, { 27, -1 }, -1 }, 521 /* 522 * All models that at least come from the same vendor with 523 * simmilar codec. 524 */ 525 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 526 17, { 16, -1 }, 16 }, 527 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 528 6, { 5, -1 }, 5 }, 529 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 530 6, { 5, -1 }, -1 }, 531 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 532 13, { 14, -1 }, -1 }, 533 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 534 26, { 27, -1 }, -1 }, 535#if 0 536 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 537 20, { 21, -1 }, -1 }, 538#endif 539}; 540#define HDAC_HP_SWITCH_LEN \ 541 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 542 543static const struct { 544 uint32_t model; 545 uint32_t id; 546 nid_t eapdnid; 547 int hp_switch; 548} hdac_eapd_switch[] = { 549 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 550 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 551 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 552}; 553#define HDAC_EAPD_SWITCH_LEN \ 554 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 555 556/**************************************************************************** 557 * Function prototypes 558 ****************************************************************************/ 559static void hdac_intr_handler(void *); 560static int hdac_reset(struct hdac_softc *); 561static int hdac_get_capabilities(struct hdac_softc *); 562static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 563static int hdac_dma_alloc(struct hdac_softc *, 564 struct hdac_dma *, bus_size_t); 565static void hdac_dma_free(struct hdac_dma *); 566static int hdac_mem_alloc(struct hdac_softc *); 567static void hdac_mem_free(struct hdac_softc *); 568static int hdac_irq_alloc(struct hdac_softc *); 569static void hdac_irq_free(struct hdac_softc *); 570static void hdac_corb_init(struct hdac_softc *); 571static void hdac_rirb_init(struct hdac_softc *); 572static void hdac_corb_start(struct hdac_softc *); 573static void hdac_rirb_start(struct hdac_softc *); 574static void hdac_scan_codecs(struct hdac_softc *); 575static int hdac_probe_codec(struct hdac_codec *); 576static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 577static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 578 579static void hdac_attach2(void *); 580 581static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 582 uint32_t, int); 583static void hdac_command_send_internal(struct hdac_softc *, 584 struct hdac_command_list *, int); 585 586static int hdac_probe(device_t); 587static int hdac_attach(device_t); 588static int hdac_detach(device_t); 589static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 590static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 591 uint32_t, int, int); 592static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 593 nid_t, int, int); 594static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 595 nid_t, nid_t, int, int, int, int, int, int); 596static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 597static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 598 599static int hdac_rirb_flush(struct hdac_softc *sc); 600static int hdac_unsolq_flush(struct hdac_softc *sc); 601 602#define hdac_command(a1, a2, a3) \ 603 hdac_command_sendone_internal(a1, a2, a3) 604 605#define hdac_codec_id(d) \ 606 ((uint32_t)((d == NULL) ? 0x00000000 : \ 607 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 608 ((uint32_t)(d)->device_id & 0x0000ffff)))) 609 610static char * 611hdac_codec_name(struct hdac_devinfo *devinfo) 612{ 613 uint32_t id; 614 int i; 615 616 id = hdac_codec_id(devinfo); 617 618 for (i = 0; i < HDAC_CODECS_LEN; i++) { 619 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 620 return (hdac_codecs[i].name); 621 } 622 623 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 624} 625 626static char * 627hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 628{ 629 static char *ossname[] = SOUND_DEVICE_NAMES; 630 static char *unknown = "???"; 631 int i; 632 633 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 634 if (devmask & (1 << i)) 635 return (ossname[i]); 636 } 637 return (unknown); 638} 639 640static void 641hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 642{ 643 static char *ossname[] = SOUND_DEVICE_NAMES; 644 int i, first = 1; 645 646 bzero(buf, len); 647 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 648 if (mask & (1 << i)) { 649 if (first == 0) 650 strlcat(buf, ", ", len); 651 strlcat(buf, ossname[i], len); 652 first = 0; 653 } 654 } 655} 656 657static struct hdac_audio_ctl * 658hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 659{ 660 if (devinfo == NULL || 661 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 662 index == NULL || devinfo->function.audio.ctl == NULL || 663 devinfo->function.audio.ctlcnt < 1 || 664 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 665 return (NULL); 666 return (&devinfo->function.audio.ctl[(*index)++]); 667} 668 669static struct hdac_audio_ctl * 670hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 671 int index, int cnt) 672{ 673 struct hdac_audio_ctl *ctl, *retctl = NULL; 674 int i, at, atindex, found = 0; 675 676 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 677 return (NULL); 678 679 at = cnt; 680 if (at == 0) 681 at = 1; 682 else if (at < 0) 683 at = -1; 684 atindex = index; 685 if (atindex < 0) 686 atindex = -1; 687 688 i = 0; 689 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 690 if (ctl->enable == 0 || ctl->widget == NULL) 691 continue; 692 if (!(ctl->widget->nid == nid && (atindex == -1 || 693 ctl->index == atindex))) 694 continue; 695 found++; 696 if (found == cnt) 697 return (ctl); 698 retctl = ctl; 699 } 700 701 return ((at == -1) ? retctl : NULL); 702} 703 704static void 705hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 706{ 707 struct hdac_softc *sc; 708 struct hdac_widget *w; 709 struct hdac_audio_ctl *ctl; 710 uint32_t id, res; 711 int i = 0, j, forcemute; 712 nid_t cad; 713 714 if (devinfo == NULL || devinfo->codec == NULL || 715 devinfo->codec->sc == NULL) 716 return; 717 718 sc = devinfo->codec->sc; 719 cad = devinfo->codec->cad; 720 id = hdac_codec_id(devinfo); 721 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 722 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 723 sc->pci_subvendor) && 724 hdac_hp_switch[i].id == id) 725 break; 726 } 727 728 if (i >= HDAC_HP_SWITCH_LEN) 729 return; 730 731 forcemute = 0; 732 if (hdac_hp_switch[i].eapdnid != -1) { 733 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 734 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 735 forcemute = (w->param.eapdbtl & 736 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 737 } 738 739 res = hdac_command(sc, 740 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 741 HDA_BOOTVERBOSE( 742 device_printf(sc->dev, 743 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 744 hdac_hp_switch[i].hpnid, res); 745 ); 746 res >>= 31; 747 res ^= hdac_hp_switch[i].inverted; 748 749 switch (hdac_hp_switch[i].type) { 750 case HDAC_HP_SWITCH_CTL: 751 ctl = hdac_audio_ctl_amp_get(devinfo, 752 hdac_hp_switch[i].hpnid, 0, 1); 753 if (ctl != NULL) { 754 ctl->muted = (res != 0 && forcemute == 0) ? 755 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 756 hdac_audio_ctl_amp_set(ctl, 757 HDA_AMP_MUTE_DEFAULT, ctl->left, 758 ctl->right); 759 } 760 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 761 ctl = hdac_audio_ctl_amp_get(devinfo, 762 hdac_hp_switch[i].spkrnid[j], 0, 1); 763 if (ctl != NULL) { 764 ctl->muted = (res != 0 || forcemute == 1) ? 765 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 766 hdac_audio_ctl_amp_set(ctl, 767 HDA_AMP_MUTE_DEFAULT, ctl->left, 768 ctl->right); 769 } 770 } 771 break; 772 case HDAC_HP_SWITCH_CTRL: 773 if (res != 0) { 774 /* HP in */ 775 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 776 if (w != NULL && w->type == 777 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 778 if (forcemute == 0) 779 w->wclass.pin.ctrl |= 780 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 781 else 782 w->wclass.pin.ctrl &= 783 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 784 hdac_command(sc, 785 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 786 w->wclass.pin.ctrl), cad); 787 } 788 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 789 w = hdac_widget_get(devinfo, 790 hdac_hp_switch[i].spkrnid[j]); 791 if (w != NULL && w->type == 792 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 793 w->wclass.pin.ctrl &= 794 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 795 hdac_command(sc, 796 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 797 w->nid, 798 w->wclass.pin.ctrl), cad); 799 } 800 } 801 } else { 802 /* HP out */ 803 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 804 if (w != NULL && w->type == 805 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 806 w->wclass.pin.ctrl &= 807 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 808 hdac_command(sc, 809 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 810 w->wclass.pin.ctrl), cad); 811 } 812 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 813 w = hdac_widget_get(devinfo, 814 hdac_hp_switch[i].spkrnid[j]); 815 if (w != NULL && w->type == 816 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 817 if (forcemute == 0) 818 w->wclass.pin.ctrl |= 819 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 820 else 821 w->wclass.pin.ctrl &= 822 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 823 hdac_command(sc, 824 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 825 w->nid, 826 w->wclass.pin.ctrl), cad); 827 } 828 } 829 } 830 break; 831 default: 832 break; 833 } 834} 835 836static void 837hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 838{ 839 struct hdac_softc *sc; 840 struct hdac_devinfo *devinfo = NULL; 841 device_t *devlist = NULL; 842 int devcount, i; 843 844 if (codec == NULL || codec->sc == NULL) 845 return; 846 847 sc = codec->sc; 848 849 HDA_BOOTVERBOSE( 850 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 851 ); 852 853 device_get_children(sc->dev, &devlist, &devcount); 854 for (i = 0; devlist != NULL && i < devcount; i++) { 855 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 856 if (devinfo != NULL && devinfo->node_type == 857 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 858 devinfo->codec != NULL && 859 devinfo->codec->cad == codec->cad) { 860 break; 861 } else 862 devinfo = NULL; 863 } 864 if (devlist != NULL) 865 free(devlist, M_TEMP); 866 867 if (devinfo == NULL) 868 return; 869 870 switch (tag) { 871 case HDAC_UNSOLTAG_EVENT_HP: 872 hdac_hp_switch_handler(devinfo); 873 break; 874 default: 875 break; 876 } 877} 878 879static int 880hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 881{ 882 /* XXX to be removed */ 883#ifdef HDAC_INTR_EXTRA 884 uint32_t res; 885#endif 886 887 if (ch->blkcnt == 0) 888 return (0); 889 890 /* XXX to be removed */ 891#ifdef HDAC_INTR_EXTRA 892 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 893#endif 894 895 /* XXX to be removed */ 896#ifdef HDAC_INTR_EXTRA 897 HDA_BOOTVERBOSE( 898 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 899 device_printf(sc->dev, 900 "PCMDIR_%s intr triggered beyond stream boundary:" 901 "%08x\n", 902 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 903 ); 904#endif 905 906 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 907 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 908 909 /* XXX to be removed */ 910#ifdef HDAC_INTR_EXTRA 911 if (res & HDAC_SDSTS_BCIS) { 912#endif 913 return (1); 914 /* XXX to be removed */ 915#ifdef HDAC_INTR_EXTRA 916 } 917#endif 918 919 return (0); 920} 921 922/**************************************************************************** 923 * void hdac_intr_handler(void *) 924 * 925 * Interrupt handler. Processes interrupts received from the hdac. 926 ****************************************************************************/ 927static void 928hdac_intr_handler(void *context) 929{ 930 struct hdac_softc *sc; 931 uint32_t intsts; 932 uint8_t rirbsts; 933 struct hdac_rirb *rirb_base; 934 uint32_t trigger = 0; 935 936 sc = (struct hdac_softc *)context; 937 938 hdac_lock(sc); 939 if (sc->polling != 0) { 940 hdac_unlock(sc); 941 return; 942 } 943 /* Do we have anything to do? */ 944 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 945 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 946 hdac_unlock(sc); 947 return; 948 } 949 950 /* Was this a controller interrupt? */ 951 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 952 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 953 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 954 /* Get as many responses that we can */ 955 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 956 HDAC_WRITE_1(&sc->mem, 957 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 958 hdac_rirb_flush(sc); 959 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 960 } 961 /* XXX to be removed */ 962 /* Clear interrupt and exit */ 963#ifdef HDAC_INTR_EXTRA 964 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 965#endif 966 } 967 968 hdac_unsolq_flush(sc); 969 970 if (intsts & HDAC_INTSTS_SIS_MASK) { 971 if ((intsts & (1 << sc->num_iss)) && 972 hdac_stream_intr(sc, &sc->play) != 0) 973 trigger |= 1; 974 if ((intsts & (1 << 0)) && 975 hdac_stream_intr(sc, &sc->rec) != 0) 976 trigger |= 2; 977 /* XXX to be removed */ 978#ifdef HDAC_INTR_EXTRA 979 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 980 HDAC_INTSTS_SIS_MASK); 981#endif 982 } 983 984 hdac_unlock(sc); 985 986 if (trigger & 1) 987 chn_intr(sc->play.c); 988 if (trigger & 2) 989 chn_intr(sc->rec.c); 990} 991 992/**************************************************************************** 993 * int hdac_reset(hdac_softc *) 994 * 995 * Reset the hdac to a quiescent and known state. 996 ****************************************************************************/ 997static int 998hdac_reset(struct hdac_softc *sc) 999{ 1000 uint32_t gctl; 1001 int count, i; 1002 1003 /* 1004 * Stop all Streams DMA engine 1005 */ 1006 for (i = 0; i < sc->num_iss; i++) 1007 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1008 for (i = 0; i < sc->num_oss; i++) 1009 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1010 for (i = 0; i < sc->num_bss; i++) 1011 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1012 1013 /* 1014 * Stop Control DMA engines 1015 */ 1016 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1017 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1018 1019 /* 1020 * Reset the controller. The reset must remain asserted for 1021 * a minimum of 100us. 1022 */ 1023 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1024 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1025 count = 10000; 1026 do { 1027 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1028 if (!(gctl & HDAC_GCTL_CRST)) 1029 break; 1030 DELAY(10); 1031 } while (--count); 1032 if (gctl & HDAC_GCTL_CRST) { 1033 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1034 return (ENXIO); 1035 } 1036 DELAY(100); 1037 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1038 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1039 count = 10000; 1040 do { 1041 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1042 if (gctl & HDAC_GCTL_CRST) 1043 break; 1044 DELAY(10); 1045 } while (--count); 1046 if (!(gctl & HDAC_GCTL_CRST)) { 1047 device_printf(sc->dev, "Device stuck in reset\n"); 1048 return (ENXIO); 1049 } 1050 1051 /* 1052 * Wait for codecs to finish their own reset sequence. The delay here 1053 * should be of 250us but for some reasons, on it's not enough on my 1054 * computer. Let's use twice as much as necessary to make sure that 1055 * it's reset properly. 1056 */ 1057 DELAY(1000); 1058 1059 return (0); 1060} 1061 1062 1063/**************************************************************************** 1064 * int hdac_get_capabilities(struct hdac_softc *); 1065 * 1066 * Retreive the general capabilities of the hdac; 1067 * Number of Input Streams 1068 * Number of Output Streams 1069 * Number of bidirectional Streams 1070 * 64bit ready 1071 * CORB and RIRB sizes 1072 ****************************************************************************/ 1073static int 1074hdac_get_capabilities(struct hdac_softc *sc) 1075{ 1076 uint16_t gcap; 1077 uint8_t corbsize, rirbsize; 1078 1079 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1080 sc->num_iss = HDAC_GCAP_ISS(gcap); 1081 sc->num_oss = HDAC_GCAP_OSS(gcap); 1082 sc->num_bss = HDAC_GCAP_BSS(gcap); 1083 1084 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1085 1086 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1087 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1088 HDAC_CORBSIZE_CORBSZCAP_256) 1089 sc->corb_size = 256; 1090 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1091 HDAC_CORBSIZE_CORBSZCAP_16) 1092 sc->corb_size = 16; 1093 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1094 HDAC_CORBSIZE_CORBSZCAP_2) 1095 sc->corb_size = 2; 1096 else { 1097 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1098 __func__, corbsize); 1099 return (ENXIO); 1100 } 1101 1102 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1103 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1104 HDAC_RIRBSIZE_RIRBSZCAP_256) 1105 sc->rirb_size = 256; 1106 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1107 HDAC_RIRBSIZE_RIRBSZCAP_16) 1108 sc->rirb_size = 16; 1109 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1110 HDAC_RIRBSIZE_RIRBSZCAP_2) 1111 sc->rirb_size = 2; 1112 else { 1113 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1114 __func__, rirbsize); 1115 return (ENXIO); 1116 } 1117 1118 return (0); 1119} 1120 1121 1122/**************************************************************************** 1123 * void hdac_dma_cb 1124 * 1125 * This function is called by bus_dmamap_load when the mapping has been 1126 * established. We just record the physical address of the mapping into 1127 * the struct hdac_dma passed in. 1128 ****************************************************************************/ 1129static void 1130hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1131{ 1132 struct hdac_dma *dma; 1133 1134 if (error == 0) { 1135 dma = (struct hdac_dma *)callback_arg; 1136 dma->dma_paddr = segs[0].ds_addr; 1137 } 1138} 1139 1140static void 1141hdac_dma_nocache(void *ptr) 1142{ 1143#if 0 1144#if defined(__i386__) || defined(__amd64__) 1145 pt_entry_t *pte; 1146 vm_offset_t va; 1147 1148 va = (vm_offset_t)ptr; 1149 pte = vtopte(va); 1150 if (pte) { 1151 *pte |= PG_N; 1152 invltlb(); 1153 } 1154#endif 1155#endif 1156} 1157 1158/**************************************************************************** 1159 * int hdac_dma_alloc 1160 * 1161 * This function allocate and setup a dma region (struct hdac_dma). 1162 * It must be freed by a corresponding hdac_dma_free. 1163 ****************************************************************************/ 1164static int 1165hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1166{ 1167 int result; 1168 int lowaddr; 1169 1170 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1171 BUS_SPACE_MAXADDR_32BIT; 1172 bzero(dma, sizeof(*dma)); 1173 1174 /* 1175 * Create a DMA tag 1176 */ 1177 result = bus_dma_tag_create(NULL, /* parent */ 1178 HDAC_DMA_ALIGNMENT, /* alignment */ 1179 0, /* boundary */ 1180 lowaddr, /* lowaddr */ 1181 BUS_SPACE_MAXADDR, /* highaddr */ 1182 NULL, /* filtfunc */ 1183 NULL, /* fistfuncarg */ 1184 size, /* maxsize */ 1185 1, /* nsegments */ 1186 size, /* maxsegsz */ 1187 0, /* flags */ 1188 NULL, /* lockfunc */ 1189 NULL, /* lockfuncarg */ 1190 &dma->dma_tag); /* dmat */ 1191 if (result != 0) { 1192 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1193 __func__, result); 1194 goto fail; 1195 } 1196 1197 /* 1198 * Allocate DMA memory 1199 */ 1200 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1201 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1202 if (result != 0) { 1203 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1204 __func__, result); 1205 goto fail; 1206 } 1207 1208 /* 1209 * Map the memory 1210 */ 1211 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1212 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1213 BUS_DMA_NOWAIT); 1214 if (result != 0 || dma->dma_paddr == 0) { 1215 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1216 __func__, result); 1217 goto fail; 1218 } 1219 bzero((void *)dma->dma_vaddr, size); 1220 hdac_dma_nocache(dma->dma_vaddr); 1221 1222 return (0); 1223fail: 1224 if (dma->dma_map != NULL) 1225 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1226 if (dma->dma_tag != NULL) 1227 bus_dma_tag_destroy(dma->dma_tag); 1228 return (result); 1229} 1230 1231 1232/**************************************************************************** 1233 * void hdac_dma_free(struct hdac_dma *) 1234 * 1235 * Free a struct dhac_dma that has been previously allocated via the 1236 * hdac_dma_alloc function. 1237 ****************************************************************************/ 1238static void 1239hdac_dma_free(struct hdac_dma *dma) 1240{ 1241 if (dma->dma_tag != NULL) { 1242 /* Flush caches */ 1243 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1244 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1245 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1246 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1247 bus_dma_tag_destroy(dma->dma_tag); 1248 } 1249} 1250 1251/**************************************************************************** 1252 * int hdac_mem_alloc(struct hdac_softc *) 1253 * 1254 * Allocate all the bus resources necessary to speak with the physical 1255 * controller. 1256 ****************************************************************************/ 1257static int 1258hdac_mem_alloc(struct hdac_softc *sc) 1259{ 1260 struct hdac_mem *mem; 1261 1262 mem = &sc->mem; 1263 mem->mem_rid = PCIR_BAR(0); 1264 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1265 &mem->mem_rid, RF_ACTIVE); 1266 if (mem->mem_res == NULL) { 1267 device_printf(sc->dev, 1268 "%s: Unable to allocate memory resource\n", __func__); 1269 return (ENOMEM); 1270 } 1271 mem->mem_tag = rman_get_bustag(mem->mem_res); 1272 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1273 1274 return (0); 1275} 1276 1277/**************************************************************************** 1278 * void hdac_mem_free(struct hdac_softc *) 1279 * 1280 * Free up resources previously allocated by hdac_mem_alloc. 1281 ****************************************************************************/ 1282static void 1283hdac_mem_free(struct hdac_softc *sc) 1284{ 1285 struct hdac_mem *mem; 1286 1287 mem = &sc->mem; 1288 if (mem->mem_res != NULL) 1289 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1290 mem->mem_res); 1291 mem->mem_res = NULL; 1292} 1293 1294/**************************************************************************** 1295 * int hdac_irq_alloc(struct hdac_softc *) 1296 * 1297 * Allocate and setup the resources necessary for interrupt handling. 1298 ****************************************************************************/ 1299static int 1300hdac_irq_alloc(struct hdac_softc *sc) 1301{ 1302 struct hdac_irq *irq; 1303 int result; 1304 1305 irq = &sc->irq; 1306 irq->irq_rid = 0x0; 1307 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1308 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1309 if (irq->irq_res == NULL) { 1310 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1311 __func__); 1312 goto fail; 1313 } 1314 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1315 hdac_intr_handler, sc, &irq->irq_handle); 1316 if (result != 0) { 1317 device_printf(sc->dev, 1318 "%s: Unable to setup interrupt handler (%x)\n", 1319 __func__, result); 1320 goto fail; 1321 } 1322 1323 return (0); 1324 1325fail: 1326 hdac_irq_free(sc); 1327 1328 return (ENXIO); 1329} 1330 1331/**************************************************************************** 1332 * void hdac_irq_free(struct hdac_softc *) 1333 * 1334 * Free up resources previously allocated by hdac_irq_alloc. 1335 ****************************************************************************/ 1336static void 1337hdac_irq_free(struct hdac_softc *sc) 1338{ 1339 struct hdac_irq *irq; 1340 1341 irq = &sc->irq; 1342 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1343 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1344 if (irq->irq_res != NULL) 1345 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1346 irq->irq_res); 1347 irq->irq_handle = NULL; 1348 irq->irq_res = NULL; 1349} 1350 1351/**************************************************************************** 1352 * void hdac_corb_init(struct hdac_softc *) 1353 * 1354 * Initialize the corb registers for operations but do not start it up yet. 1355 * The CORB engine must not be running when this function is called. 1356 ****************************************************************************/ 1357static void 1358hdac_corb_init(struct hdac_softc *sc) 1359{ 1360 uint8_t corbsize; 1361 uint64_t corbpaddr; 1362 1363 /* Setup the CORB size. */ 1364 switch (sc->corb_size) { 1365 case 256: 1366 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1367 break; 1368 case 16: 1369 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1370 break; 1371 case 2: 1372 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1373 break; 1374 default: 1375 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1376 } 1377 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1378 1379 /* Setup the CORB Address in the hdac */ 1380 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1381 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1382 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1383 1384 /* Set the WP and RP */ 1385 sc->corb_wp = 0; 1386 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1387 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1388 /* 1389 * The HDA specification indicates that the CORBRPRST bit will always 1390 * read as zero. Unfortunately, it seems that at least the 82801G 1391 * doesn't reset the bit to zero, which stalls the corb engine. 1392 * manually reset the bit to zero before continuing. 1393 */ 1394 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1395 1396 /* Enable CORB error reporting */ 1397#if 0 1398 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1399#endif 1400} 1401 1402/**************************************************************************** 1403 * void hdac_rirb_init(struct hdac_softc *) 1404 * 1405 * Initialize the rirb registers for operations but do not start it up yet. 1406 * The RIRB engine must not be running when this function is called. 1407 ****************************************************************************/ 1408static void 1409hdac_rirb_init(struct hdac_softc *sc) 1410{ 1411 uint8_t rirbsize; 1412 uint64_t rirbpaddr; 1413 1414 /* Setup the RIRB size. */ 1415 switch (sc->rirb_size) { 1416 case 256: 1417 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1418 break; 1419 case 16: 1420 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1421 break; 1422 case 2: 1423 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1424 break; 1425 default: 1426 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1427 } 1428 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1429 1430 /* Setup the RIRB Address in the hdac */ 1431 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1432 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1433 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1434 1435 /* Setup the WP and RP */ 1436 sc->rirb_rp = 0; 1437 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1438 1439 if (sc->polling == 0) { 1440 /* Setup the interrupt threshold */ 1441 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1442 1443 /* Enable Overrun and response received reporting */ 1444#if 0 1445 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1446 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1447#else 1448 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1449#endif 1450 } 1451 1452 /* 1453 * Make sure that the Host CPU cache doesn't contain any dirty 1454 * cache lines that falls in the rirb. If I understood correctly, it 1455 * should be sufficient to do this only once as the rirb is purely 1456 * read-only from now on. 1457 */ 1458 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1459 BUS_DMASYNC_PREREAD); 1460} 1461 1462/**************************************************************************** 1463 * void hdac_corb_start(hdac_softc *) 1464 * 1465 * Startup the corb DMA engine 1466 ****************************************************************************/ 1467static void 1468hdac_corb_start(struct hdac_softc *sc) 1469{ 1470 uint32_t corbctl; 1471 1472 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1473 corbctl |= HDAC_CORBCTL_CORBRUN; 1474 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1475} 1476 1477/**************************************************************************** 1478 * void hdac_rirb_start(hdac_softc *) 1479 * 1480 * Startup the rirb DMA engine 1481 ****************************************************************************/ 1482static void 1483hdac_rirb_start(struct hdac_softc *sc) 1484{ 1485 uint32_t rirbctl; 1486 1487 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1488 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1489 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1490} 1491 1492 1493/**************************************************************************** 1494 * void hdac_scan_codecs(struct hdac_softc *) 1495 * 1496 * Scan the bus for available codecs. 1497 ****************************************************************************/ 1498static void 1499hdac_scan_codecs(struct hdac_softc *sc) 1500{ 1501 struct hdac_codec *codec; 1502 int i; 1503 uint16_t statests; 1504 1505 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1506 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1507 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1508 /* We have found a codec. */ 1509 hdac_unlock(sc); 1510 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1511 M_HDAC, M_ZERO | M_NOWAIT); 1512 hdac_lock(sc); 1513 if (codec == NULL) { 1514 device_printf(sc->dev, 1515 "Unable to allocate memory for codec\n"); 1516 continue; 1517 } 1518 codec->commands = NULL; 1519 codec->responses_received = 0; 1520 codec->verbs_sent = 0; 1521 codec->sc = sc; 1522 codec->cad = i; 1523 sc->codecs[i] = codec; 1524 if (hdac_probe_codec(codec) != 0) 1525 break; 1526 } 1527 } 1528 /* All codecs have been probed, now try to attach drivers to them */ 1529 /* bus_generic_attach(sc->dev); */ 1530} 1531 1532/**************************************************************************** 1533 * void hdac_probe_codec(struct hdac_softc *, int) 1534 * 1535 * Probe a the given codec_id for available function groups. 1536 ****************************************************************************/ 1537static int 1538hdac_probe_codec(struct hdac_codec *codec) 1539{ 1540 struct hdac_softc *sc = codec->sc; 1541 struct hdac_devinfo *devinfo; 1542 uint32_t vendorid, revisionid, subnode; 1543 int startnode; 1544 int endnode; 1545 int i; 1546 nid_t cad = codec->cad; 1547 1548 HDA_BOOTVERBOSE( 1549 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1550 ); 1551 vendorid = hdac_command(sc, 1552 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1553 cad); 1554 revisionid = hdac_command(sc, 1555 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1556 cad); 1557 subnode = hdac_command(sc, 1558 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1559 cad); 1560 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1561 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1562 1563 HDA_BOOTVERBOSE( 1564 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1565 startnode, endnode); 1566 ); 1567 for (i = startnode; i < endnode; i++) { 1568 devinfo = hdac_probe_function(codec, i); 1569 if (devinfo != NULL) { 1570 /* XXX Ignore other FG. */ 1571 devinfo->vendor_id = 1572 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1573 devinfo->device_id = 1574 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1575 devinfo->revision_id = 1576 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1577 devinfo->stepping_id = 1578 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1579 HDA_BOOTVERBOSE( 1580 device_printf(sc->dev, 1581 "HDA_DEBUG: \tFound AFG nid=%d " 1582 "[startnode=%d endnode=%d]\n", 1583 devinfo->nid, startnode, endnode); 1584 ); 1585 return (1); 1586 } 1587 } 1588 1589 HDA_BOOTVERBOSE( 1590 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1591 ); 1592 return (0); 1593} 1594 1595static struct hdac_devinfo * 1596hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1597{ 1598 struct hdac_softc *sc = codec->sc; 1599 struct hdac_devinfo *devinfo; 1600 uint32_t fctgrptype; 1601 nid_t cad = codec->cad; 1602 1603 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1604 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1605 1606 /* XXX For now, ignore other FG. */ 1607 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1608 return (NULL); 1609 1610 hdac_unlock(sc); 1611 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1612 M_NOWAIT | M_ZERO); 1613 hdac_lock(sc); 1614 if (devinfo == NULL) { 1615 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1616 __func__); 1617 return (NULL); 1618 } 1619 1620 devinfo->nid = nid; 1621 devinfo->node_type = fctgrptype; 1622 devinfo->codec = codec; 1623 1624 hdac_add_child(sc, devinfo); 1625 1626 return (devinfo); 1627} 1628 1629static void 1630hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1631{ 1632 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1633 device_set_ivars(devinfo->dev, (void *)devinfo); 1634 /* XXX - Print more information when booting verbose??? */ 1635} 1636 1637static void 1638hdac_widget_connection_parse(struct hdac_widget *w) 1639{ 1640 struct hdac_softc *sc = w->devinfo->codec->sc; 1641 uint32_t res; 1642 int i, j, max, found, entnum, cnid; 1643 nid_t cad = w->devinfo->codec->cad; 1644 nid_t nid = w->nid; 1645 1646 res = hdac_command(sc, 1647 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1648 1649 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1650 1651 if (w->nconns < 1) 1652 return; 1653 1654 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1655 res = 0; 1656 i = 0; 1657 found = 0; 1658 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1659 1660 while (i < w->nconns) { 1661 res = hdac_command(sc, 1662 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1663 for (j = 0; j < entnum; j++) { 1664 cnid = res; 1665 cnid >>= (32 / entnum) * j; 1666 cnid &= (1 << (32 / entnum)) - 1; 1667 if (cnid == 0) 1668 continue; 1669 if (found > max) { 1670 device_printf(sc->dev, 1671 "node %d: Adding %d: " 1672 "Max connection reached!\n", 1673 nid, cnid); 1674 continue; 1675 } 1676 w->conns[found++] = cnid; 1677 } 1678 i += entnum; 1679 } 1680 1681 HDA_BOOTVERBOSE( 1682 if (w->nconns != found) { 1683 device_printf(sc->dev, 1684 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1685 "length=%d != found=%d\n", 1686 nid, w->nconns, found); 1687 } 1688 ); 1689} 1690 1691static uint32_t 1692hdac_widget_pin_getconfig(struct hdac_widget *w) 1693{ 1694 struct hdac_softc *sc; 1695 uint32_t config, orig, id; 1696 nid_t cad, nid; 1697 1698 sc = w->devinfo->codec->sc; 1699 cad = w->devinfo->codec->cad; 1700 nid = w->nid; 1701 id = hdac_codec_id(w->devinfo); 1702 1703 config = hdac_command(sc, 1704 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1705 cad); 1706 orig = config; 1707 1708 /* 1709 * XXX REWRITE!!!! Don't argue! 1710 */ 1711 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1712 switch (nid) { 1713 case 26: 1714 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1715 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1716 break; 1717 case 27: 1718 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1719 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1720 break; 1721 default: 1722 break; 1723 } 1724 } else if (id == HDA_CODEC_ALC880 && 1725 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1726 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1727 /* 1728 * Super broken BIOS 1729 */ 1730 switch (nid) { 1731 case 20: 1732 break; 1733 case 21: 1734 break; 1735 case 22: 1736 break; 1737 case 23: 1738 break; 1739 case 24: /* MIC1 */ 1740 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1741 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1742 break; 1743 case 25: /* XXX MIC2 */ 1744 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1745 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1746 break; 1747 case 26: /* LINE1 */ 1748 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1749 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1750 break; 1751 case 27: /* XXX LINE2 */ 1752 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1753 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1754 break; 1755 case 28: /* CD */ 1756 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1757 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1758 break; 1759 case 30: 1760 break; 1761 case 31: 1762 break; 1763 default: 1764 break; 1765 } 1766 } else if (id == HDA_CODEC_ALC883 && 1767 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1768 switch (nid) { 1769 case 25: 1770 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1771 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1772 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1773 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1774 break; 1775 default: 1776 break; 1777 } 1778 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1779 HP_V3000_SUBVENDOR) { 1780 switch (nid) { 1781 case 18: 1782 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1783 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1784 break; 1785 case 20: 1786 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1787 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1788 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1789 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1790 break; 1791 case 21: 1792 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1793 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1794 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1795 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1796 break; 1797 default: 1798 break; 1799 } 1800 } 1801 1802 HDA_BOOTVERBOSE( 1803 if (config != orig) 1804 device_printf(sc->dev, 1805 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 1806 nid, orig, config); 1807 ); 1808 1809 return (config); 1810} 1811 1812static uint32_t 1813hdac_widget_pin_getcaps(struct hdac_widget *w) 1814{ 1815 struct hdac_softc *sc; 1816 uint32_t caps, orig, id; 1817 nid_t cad, nid; 1818 1819 sc = w->devinfo->codec->sc; 1820 cad = w->devinfo->codec->cad; 1821 nid = w->nid; 1822 id = hdac_codec_id(w->devinfo); 1823 1824 caps = hdac_command(sc, 1825 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1826 orig = caps; 1827 1828 HDA_BOOTVERBOSE( 1829 if (caps != orig) 1830 device_printf(sc->dev, 1831 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 1832 nid, orig, caps); 1833 ); 1834 1835 return (caps); 1836} 1837 1838static void 1839hdac_widget_pin_parse(struct hdac_widget *w) 1840{ 1841 struct hdac_softc *sc = w->devinfo->codec->sc; 1842 uint32_t config, pincap; 1843 char *devstr, *connstr; 1844 nid_t cad = w->devinfo->codec->cad; 1845 nid_t nid = w->nid; 1846 1847 config = hdac_widget_pin_getconfig(w); 1848 w->wclass.pin.config = config; 1849 1850 pincap = hdac_widget_pin_getcaps(w); 1851 w->wclass.pin.cap = pincap; 1852 1853 w->wclass.pin.ctrl = hdac_command(sc, 1854 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1855 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1856 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1857 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1858 1859 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1860 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1861 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1862 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1863 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1864 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1865 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1866 w->param.eapdbtl = hdac_command(sc, 1867 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1868 w->param.eapdbtl &= 0x7; 1869 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1870 } else 1871 w->param.eapdbtl = HDAC_INVALID; 1872 1873 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1874 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1875 devstr = "line out"; 1876 break; 1877 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1878 devstr = "speaker"; 1879 break; 1880 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1881 devstr = "headphones out"; 1882 break; 1883 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1884 devstr = "CD"; 1885 break; 1886 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1887 devstr = "SPDIF out"; 1888 break; 1889 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1890 devstr = "digital (other) out"; 1891 break; 1892 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1893 devstr = "modem, line side"; 1894 break; 1895 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1896 devstr = "modem, handset side"; 1897 break; 1898 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1899 devstr = "line in"; 1900 break; 1901 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1902 devstr = "AUX"; 1903 break; 1904 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1905 devstr = "Mic in"; 1906 break; 1907 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1908 devstr = "telephony"; 1909 break; 1910 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1911 devstr = "SPDIF in"; 1912 break; 1913 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1914 devstr = "digital (other) in"; 1915 break; 1916 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1917 devstr = "other"; 1918 break; 1919 default: 1920 devstr = "unknown"; 1921 break; 1922 } 1923 1924 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1925 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1926 connstr = "jack"; 1927 break; 1928 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1929 connstr = "none"; 1930 break; 1931 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1932 connstr = "fixed"; 1933 break; 1934 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1935 connstr = "jack / fixed"; 1936 break; 1937 default: 1938 connstr = "unknown"; 1939 break; 1940 } 1941 1942 strlcat(w->name, ": ", sizeof(w->name)); 1943 strlcat(w->name, devstr, sizeof(w->name)); 1944 strlcat(w->name, " (", sizeof(w->name)); 1945 strlcat(w->name, connstr, sizeof(w->name)); 1946 strlcat(w->name, ")", sizeof(w->name)); 1947} 1948 1949static void 1950hdac_widget_parse(struct hdac_widget *w) 1951{ 1952 struct hdac_softc *sc = w->devinfo->codec->sc; 1953 uint32_t wcap, cap; 1954 char *typestr; 1955 nid_t cad = w->devinfo->codec->cad; 1956 nid_t nid = w->nid; 1957 1958 wcap = hdac_command(sc, 1959 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1960 cad); 1961 w->param.widget_cap = wcap; 1962 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1963 1964 switch (w->type) { 1965 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1966 typestr = "audio output"; 1967 break; 1968 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1969 typestr = "audio input"; 1970 break; 1971 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1972 typestr = "audio mixer"; 1973 break; 1974 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1975 typestr = "audio selector"; 1976 break; 1977 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1978 typestr = "pin"; 1979 break; 1980 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1981 typestr = "power widget"; 1982 break; 1983 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1984 typestr = "volume widget"; 1985 break; 1986 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1987 typestr = "beep widget"; 1988 break; 1989 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1990 typestr = "vendor widget"; 1991 break; 1992 default: 1993 typestr = "unknown type"; 1994 break; 1995 } 1996 1997 strlcpy(w->name, typestr, sizeof(w->name)); 1998 1999 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 2000 hdac_command(sc, 2001 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2002 cad); 2003 DELAY(1000); 2004 } 2005 2006 hdac_widget_connection_parse(w); 2007 2008 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2009 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2010 w->param.outamp_cap = 2011 hdac_command(sc, 2012 HDA_CMD_GET_PARAMETER(cad, nid, 2013 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2014 else 2015 w->param.outamp_cap = 2016 w->devinfo->function.audio.outamp_cap; 2017 } else 2018 w->param.outamp_cap = 0; 2019 2020 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2021 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2022 w->param.inamp_cap = 2023 hdac_command(sc, 2024 HDA_CMD_GET_PARAMETER(cad, nid, 2025 HDA_PARAM_INPUT_AMP_CAP), cad); 2026 else 2027 w->param.inamp_cap = 2028 w->devinfo->function.audio.inamp_cap; 2029 } else 2030 w->param.inamp_cap = 0; 2031 2032 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2033 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2034 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2035 cap = hdac_command(sc, 2036 HDA_CMD_GET_PARAMETER(cad, nid, 2037 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2038 w->param.supp_stream_formats = (cap != 0) ? cap : 2039 w->devinfo->function.audio.supp_stream_formats; 2040 cap = hdac_command(sc, 2041 HDA_CMD_GET_PARAMETER(cad, nid, 2042 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2043 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2044 w->devinfo->function.audio.supp_pcm_size_rate; 2045 } else { 2046 w->param.supp_stream_formats = 2047 w->devinfo->function.audio.supp_stream_formats; 2048 w->param.supp_pcm_size_rate = 2049 w->devinfo->function.audio.supp_pcm_size_rate; 2050 } 2051 } else { 2052 w->param.supp_stream_formats = 0; 2053 w->param.supp_pcm_size_rate = 0; 2054 } 2055 2056 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2057 hdac_widget_pin_parse(w); 2058} 2059 2060static struct hdac_widget * 2061hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2062{ 2063 if (devinfo == NULL || devinfo->widget == NULL || 2064 nid < devinfo->startnode || nid >= devinfo->endnode) 2065 return (NULL); 2066 return (&devinfo->widget[nid - devinfo->startnode]); 2067} 2068 2069static __inline int 2070hda_poll_channel(struct hdac_chan *ch) 2071{ 2072 uint32_t sz, delta; 2073 volatile uint32_t ptr; 2074 2075 if (ch->active == 0) 2076 return (0); 2077 2078 sz = ch->blksz * ch->blkcnt; 2079 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2080 ch->ptr = ptr; 2081 ptr %= sz; 2082 ptr &= ~(ch->blksz - 1); 2083 delta = (sz + ptr - ch->prevptr) % sz; 2084 2085 if (delta < ch->blksz) 2086 return (0); 2087 2088 ch->prevptr = ptr; 2089 2090 return (1); 2091} 2092 2093#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2094 2095static void 2096hda_poll_callback(void *arg) 2097{ 2098 struct hdac_softc *sc = arg; 2099 uint32_t trigger = 0; 2100 2101 if (sc == NULL) 2102 return; 2103 2104 hdac_lock(sc); 2105 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2106 hdac_unlock(sc); 2107 return; 2108 } 2109 2110 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2111 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2112 2113 /* XXX */ 2114 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2115 hda_poll_callback, sc); 2116 2117 hdac_unlock(sc); 2118 2119 if (trigger & 1) 2120 chn_intr(sc->play.c); 2121 if (trigger & 2) 2122 chn_intr(sc->rec.c); 2123} 2124 2125static int 2126hdac_rirb_flush(struct hdac_softc *sc) 2127{ 2128 struct hdac_rirb *rirb_base, *rirb; 2129 struct hdac_codec *codec; 2130 struct hdac_command_list *commands; 2131 nid_t cad; 2132 uint32_t resp; 2133 uint8_t rirbwp; 2134 int ret = 0; 2135 2136 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2137 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2138 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2139 BUS_DMASYNC_POSTREAD); 2140 2141 while (sc->rirb_rp != rirbwp) { 2142 sc->rirb_rp++; 2143 sc->rirb_rp %= sc->rirb_size; 2144 rirb = &rirb_base[sc->rirb_rp]; 2145 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2146 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2147 sc->codecs[cad] == NULL) 2148 continue; 2149 resp = rirb->response; 2150 codec = sc->codecs[cad]; 2151 commands = codec->commands; 2152 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2153 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2154 ((resp >> 26) & 0xffff); 2155 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2156 } else if (commands != NULL && commands->num_commands > 0 && 2157 codec->responses_received < commands->num_commands) 2158 commands->responses[codec->responses_received++] = 2159 resp; 2160 ret++; 2161 } 2162 2163 return (ret); 2164} 2165 2166static int 2167hdac_unsolq_flush(struct hdac_softc *sc) 2168{ 2169 nid_t cad; 2170 uint32_t tag; 2171 int ret = 0; 2172 2173 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2174 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2175 while (sc->unsolq_rp != sc->unsolq_wp) { 2176 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2177 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2178 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2179 hdac_unsolicited_handler(sc->codecs[cad], tag); 2180 ret++; 2181 } 2182 sc->unsolq_st = HDAC_UNSOLQ_READY; 2183 } 2184 2185 return (ret); 2186} 2187 2188static void 2189hdac_poll_callback(void *arg) 2190{ 2191 struct hdac_softc *sc = arg; 2192 if (sc == NULL) 2193 return; 2194 2195 hdac_lock(sc); 2196 if (sc->polling == 0) { 2197 hdac_unlock(sc); 2198 return; 2199 } 2200 hdac_rirb_flush(sc); 2201 hdac_unsolq_flush(sc); 2202 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2203 hdac_poll_callback, sc); 2204 hdac_unlock(sc); 2205} 2206 2207static void 2208hdac_stream_stop(struct hdac_chan *ch) 2209{ 2210 struct hdac_softc *sc = ch->devinfo->codec->sc; 2211 uint32_t ctl; 2212 2213 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2214 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2215 HDAC_SDCTL_RUN); 2216 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2217 2218 ch->active = 0; 2219 2220 if (sc->polling != 0) { 2221 int pollticks; 2222 2223 if (hda_chan_active(sc) == 0) { 2224 callout_stop(&sc->poll_hda); 2225 sc->poll_ticks = 1; 2226 } else { 2227 if (sc->play.active != 0) 2228 ch = &sc->play; 2229 else 2230 ch = &sc->rec; 2231 pollticks = ((uint64_t)hz * ch->blksz) / 2232 ((uint64_t)sndbuf_getbps(ch->b) * 2233 sndbuf_getspd(ch->b)); 2234 pollticks >>= 2; 2235 if (pollticks > hz) 2236 pollticks = hz; 2237 if (pollticks < 1) { 2238 HDA_BOOTVERBOSE( 2239 device_printf(sc->dev, 2240 "%s: pollticks=%d < 1 !\n", 2241 __func__, pollticks); 2242 ); 2243 pollticks = 1; 2244 } 2245 if (pollticks > sc->poll_ticks) { 2246 HDA_BOOTVERBOSE( 2247 device_printf(sc->dev, 2248 "%s: pollticks %d -> %d\n", 2249 __func__, sc->poll_ticks, 2250 pollticks); 2251 ); 2252 sc->poll_ticks = pollticks; 2253 callout_reset(&sc->poll_hda, 1, 2254 hda_poll_callback, sc); 2255 } 2256 } 2257 } else { 2258 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2259 ctl &= ~(1 << (ch->off >> 5)); 2260 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2261 } 2262} 2263 2264static void 2265hdac_stream_start(struct hdac_chan *ch) 2266{ 2267 struct hdac_softc *sc = ch->devinfo->codec->sc; 2268 uint32_t ctl; 2269 2270 if (sc->polling != 0) { 2271 int pollticks; 2272 2273 pollticks = ((uint64_t)hz * ch->blksz) / 2274 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2275 pollticks >>= 2; 2276 if (pollticks > hz) 2277 pollticks = hz; 2278 if (pollticks < 1) { 2279 HDA_BOOTVERBOSE( 2280 device_printf(sc->dev, 2281 "%s: pollticks=%d < 1 !\n", 2282 __func__, pollticks); 2283 ); 2284 pollticks = 1; 2285 } 2286 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2287 HDA_BOOTVERBOSE( 2288 if (hda_chan_active(sc) == 0) { 2289 device_printf(sc->dev, 2290 "%s: pollticks=%d\n", 2291 __func__, pollticks); 2292 } else { 2293 device_printf(sc->dev, 2294 "%s: pollticks %d -> %d\n", 2295 __func__, sc->poll_ticks, 2296 pollticks); 2297 } 2298 ); 2299 sc->poll_ticks = pollticks; 2300 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2301 sc); 2302 } 2303 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2304 ctl |= HDAC_SDCTL_RUN; 2305 } else { 2306 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2307 ctl |= 1 << (ch->off >> 5); 2308 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2309 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2310 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2311 HDAC_SDCTL_RUN; 2312 } 2313 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2314 2315 ch->active = 1; 2316} 2317 2318static void 2319hdac_stream_reset(struct hdac_chan *ch) 2320{ 2321 struct hdac_softc *sc = ch->devinfo->codec->sc; 2322 int timeout = 1000; 2323 int to = timeout; 2324 uint32_t ctl; 2325 2326 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2327 ctl |= HDAC_SDCTL_SRST; 2328 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2329 do { 2330 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2331 if (ctl & HDAC_SDCTL_SRST) 2332 break; 2333 DELAY(10); 2334 } while (--to); 2335 if (!(ctl & HDAC_SDCTL_SRST)) { 2336 device_printf(sc->dev, "timeout in reset\n"); 2337 } 2338 ctl &= ~HDAC_SDCTL_SRST; 2339 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2340 to = timeout; 2341 do { 2342 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2343 if (!(ctl & HDAC_SDCTL_SRST)) 2344 break; 2345 DELAY(10); 2346 } while (--to); 2347 if (ctl & HDAC_SDCTL_SRST) 2348 device_printf(sc->dev, "can't reset!\n"); 2349} 2350 2351static void 2352hdac_stream_setid(struct hdac_chan *ch) 2353{ 2354 struct hdac_softc *sc = ch->devinfo->codec->sc; 2355 uint32_t ctl; 2356 2357 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2358 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2359 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2360 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2361} 2362 2363static void 2364hdac_bdl_setup(struct hdac_chan *ch) 2365{ 2366 struct hdac_softc *sc = ch->devinfo->codec->sc; 2367 struct hdac_bdle *bdle; 2368 uint64_t addr; 2369 uint32_t blksz, blkcnt; 2370 int i; 2371 2372 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2373 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2374 2375 if (sc->polling != 0) { 2376 blksz = ch->blksz * ch->blkcnt; 2377 blkcnt = 1; 2378 } else { 2379 blksz = ch->blksz; 2380 blkcnt = ch->blkcnt; 2381 } 2382 2383 for (i = 0; i < blkcnt; i++, bdle++) { 2384 bdle->addrl = (uint32_t)addr; 2385 bdle->addrh = (uint32_t)(addr >> 32); 2386 bdle->len = blksz; 2387 bdle->ioc = 1 ^ sc->polling; 2388 addr += blksz; 2389 } 2390 2391 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2392 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2393 addr = ch->bdl_dma.dma_paddr; 2394 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2395 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2396} 2397 2398static int 2399hdac_bdl_alloc(struct hdac_chan *ch) 2400{ 2401 struct hdac_softc *sc = ch->devinfo->codec->sc; 2402 int rc; 2403 2404 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2405 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2406 if (rc) { 2407 device_printf(sc->dev, "can't alloc bdl\n"); 2408 return (rc); 2409 } 2410 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2411 2412 return (0); 2413} 2414 2415static void 2416hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2417 int index, int lmute, int rmute, 2418 int left, int right, int dir) 2419{ 2420 uint16_t v = 0; 2421 2422 if (sc == NULL) 2423 return; 2424 2425 if (left != right || lmute != rmute) { 2426 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2427 (lmute << 7) | left; 2428 hdac_command(sc, 2429 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2430 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2431 (rmute << 7) | right; 2432 } else 2433 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2434 (lmute << 7) | left; 2435 2436 hdac_command(sc, 2437 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2438} 2439 2440static void 2441hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2442 int left, int right) 2443{ 2444 struct hdac_softc *sc; 2445 nid_t nid, cad; 2446 int lmute, rmute; 2447 2448 if (ctl == NULL || ctl->widget == NULL || 2449 ctl->widget->devinfo == NULL || 2450 ctl->widget->devinfo->codec == NULL || 2451 ctl->widget->devinfo->codec->sc == NULL) 2452 return; 2453 2454 sc = ctl->widget->devinfo->codec->sc; 2455 cad = ctl->widget->devinfo->codec->cad; 2456 nid = ctl->widget->nid; 2457 2458 if (mute == HDA_AMP_MUTE_DEFAULT) { 2459 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2460 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2461 } else { 2462 lmute = HDA_AMP_LEFT_MUTED(mute); 2463 rmute = HDA_AMP_RIGHT_MUTED(mute); 2464 } 2465 2466 if (ctl->dir & HDA_CTL_OUT) 2467 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2468 lmute, rmute, left, right, 0); 2469 if (ctl->dir & HDA_CTL_IN) 2470 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2471 lmute, rmute, left, right, 1); 2472 ctl->left = left; 2473 ctl->right = right; 2474} 2475 2476static void 2477hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2478{ 2479 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2480 return; 2481 hdac_command(w->devinfo->codec->sc, 2482 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2483 w->nid, index), w->devinfo->codec->cad); 2484 w->selconn = index; 2485} 2486 2487 2488/**************************************************************************** 2489 * uint32_t hdac_command_sendone_internal 2490 * 2491 * Wrapper function that sends only one command to a given codec 2492 ****************************************************************************/ 2493static uint32_t 2494hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2495{ 2496 struct hdac_command_list cl; 2497 uint32_t response = HDAC_INVALID; 2498 2499 if (!hdac_lockowned(sc)) 2500 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2501 cl.num_commands = 1; 2502 cl.verbs = &verb; 2503 cl.responses = &response; 2504 2505 hdac_command_send_internal(sc, &cl, cad); 2506 2507 return (response); 2508} 2509 2510/**************************************************************************** 2511 * hdac_command_send_internal 2512 * 2513 * Send a command list to the codec via the corb. We queue as much verbs as 2514 * we can and msleep on the codec. When the interrupt get the responses 2515 * back from the rirb, it will wake us up so we can queue the remaining verbs 2516 * if any. 2517 ****************************************************************************/ 2518static void 2519hdac_command_send_internal(struct hdac_softc *sc, 2520 struct hdac_command_list *commands, nid_t cad) 2521{ 2522 struct hdac_codec *codec; 2523 int corbrp; 2524 uint32_t *corb; 2525 int timeout; 2526 int retry = 10; 2527 struct hdac_rirb *rirb_base; 2528 2529 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2530 commands->num_commands < 1) 2531 return; 2532 2533 codec = sc->codecs[cad]; 2534 codec->commands = commands; 2535 codec->responses_received = 0; 2536 codec->verbs_sent = 0; 2537 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2538 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2539 2540 do { 2541 if (codec->verbs_sent != commands->num_commands) { 2542 /* Queue as many verbs as possible */ 2543 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2544 bus_dmamap_sync(sc->corb_dma.dma_tag, 2545 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2546 while (codec->verbs_sent != commands->num_commands && 2547 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2548 sc->corb_wp++; 2549 sc->corb_wp %= sc->corb_size; 2550 corb[sc->corb_wp] = 2551 commands->verbs[codec->verbs_sent++]; 2552 } 2553 2554 /* Send the verbs to the codecs */ 2555 bus_dmamap_sync(sc->corb_dma.dma_tag, 2556 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2557 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2558 } 2559 2560 timeout = 1000; 2561 while (hdac_rirb_flush(sc) == 0 && --timeout) 2562 DELAY(10); 2563 } while ((codec->verbs_sent != commands->num_commands || 2564 codec->responses_received != commands->num_commands) && --retry); 2565 2566 if (retry == 0) 2567 device_printf(sc->dev, 2568 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2569 __func__, commands->num_commands, codec->verbs_sent, 2570 codec->responses_received); 2571 2572 codec->commands = NULL; 2573 codec->responses_received = 0; 2574 codec->verbs_sent = 0; 2575 2576 hdac_unsolq_flush(sc); 2577} 2578 2579 2580/**************************************************************************** 2581 * Device Methods 2582 ****************************************************************************/ 2583 2584/**************************************************************************** 2585 * int hdac_probe(device_t) 2586 * 2587 * Probe for the presence of an hdac. If none is found, check for a generic 2588 * match using the subclass of the device. 2589 ****************************************************************************/ 2590static int 2591hdac_probe(device_t dev) 2592{ 2593 int i, result; 2594 uint32_t model; 2595 uint16_t class, subclass; 2596 char desc[64]; 2597 2598 model = (uint32_t)pci_get_device(dev) << 16; 2599 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2600 class = pci_get_class(dev); 2601 subclass = pci_get_subclass(dev); 2602 2603 bzero(desc, sizeof(desc)); 2604 result = ENXIO; 2605 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2606 if (hdac_devices[i].model == model) { 2607 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2608 result = BUS_PROBE_DEFAULT; 2609 break; 2610 } 2611 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2612 class == PCIC_MULTIMEDIA && 2613 subclass == PCIS_MULTIMEDIA_HDA) { 2614 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2615 result = BUS_PROBE_GENERIC; 2616 break; 2617 } 2618 } 2619 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2620 subclass == PCIS_MULTIMEDIA_HDA) { 2621 strlcpy(desc, "Generic", sizeof(desc)); 2622 result = BUS_PROBE_GENERIC; 2623 } 2624 if (result != ENXIO) { 2625 strlcat(desc, " High Definition Audio Controller", 2626 sizeof(desc)); 2627 device_set_desc_copy(dev, desc); 2628 } 2629 2630 return (result); 2631} 2632 2633static void * 2634hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2635 struct pcm_channel *c, int dir) 2636{ 2637 struct hdac_devinfo *devinfo = data; 2638 struct hdac_softc *sc = devinfo->codec->sc; 2639 struct hdac_chan *ch; 2640 2641 hdac_lock(sc); 2642 if (dir == PCMDIR_PLAY) { 2643 ch = &sc->play; 2644 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2645 ch->dir = PCMDIR_PLAY; 2646 ch->sid = ++sc->streamcnt; 2647 devinfo->function.audio.playcnt++; 2648 } else { 2649 ch = &sc->rec; 2650 ch->off = devinfo->function.audio.reccnt << 5; 2651 ch->dir = PCMDIR_REC; 2652 ch->sid = ++sc->streamcnt; 2653 devinfo->function.audio.reccnt++; 2654 } 2655 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2656 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2657 ch->pcmrates[0] = 48000; 2658 ch->pcmrates[1] = 0; 2659 } 2660 ch->b = b; 2661 ch->c = c; 2662 ch->devinfo = devinfo; 2663 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2664 ch->blkcnt = sc->chan_blkcnt; 2665 hdac_unlock(sc); 2666 2667 if (hdac_bdl_alloc(ch) != 0) { 2668 ch->blkcnt = 0; 2669 return (NULL); 2670 } 2671 2672 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2673 return (NULL); 2674 2675 hdac_dma_nocache(ch->b->buf); 2676 2677 return (ch); 2678} 2679 2680static int 2681hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2682{ 2683 struct hdac_chan *ch = data; 2684 int i; 2685 2686 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2687 if (format == ch->caps.fmtlist[i]) { 2688 ch->fmt = format; 2689 return (0); 2690 } 2691 } 2692 2693 return (EINVAL); 2694} 2695 2696static int 2697hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2698{ 2699 struct hdac_chan *ch = data; 2700 uint32_t spd = 0, threshold; 2701 int i; 2702 2703 for (i = 0; ch->pcmrates[i] != 0; i++) { 2704 spd = ch->pcmrates[i]; 2705 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2706 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2707 if (speed < threshold) 2708 break; 2709 } 2710 2711 if (spd == 0) /* impossible */ 2712 ch->spd = 48000; 2713 else 2714 ch->spd = spd; 2715 2716 return (ch->spd); 2717} 2718 2719static void 2720hdac_stream_setup(struct hdac_chan *ch) 2721{ 2722 struct hdac_softc *sc = ch->devinfo->codec->sc; 2723 int i; 2724 nid_t cad = ch->devinfo->codec->cad; 2725 uint16_t fmt; 2726 2727 fmt = 0; 2728 if (ch->fmt & AFMT_S16_LE) 2729 fmt |= ch->bit16 << 4; 2730 else if (ch->fmt & AFMT_S32_LE) 2731 fmt |= ch->bit32 << 4; 2732 else 2733 fmt |= 1 << 4; 2734 2735 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2736 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2737 fmt |= hda_rate_tab[i].base; 2738 fmt |= hda_rate_tab[i].mul; 2739 fmt |= hda_rate_tab[i].div; 2740 break; 2741 } 2742 } 2743 2744 if (ch->fmt & AFMT_STEREO) 2745 fmt |= 1; 2746 2747 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2748 2749 for (i = 0; ch->io[i] != -1; i++) { 2750 HDA_BOOTVERBOSE( 2751 device_printf(sc->dev, 2752 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2753 "fmt=0x%08x\n", 2754 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2755 ch->io[i], fmt); 2756 ); 2757 hdac_command(sc, 2758 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2759 hdac_command(sc, 2760 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2761 ch->sid << 4), cad); 2762 } 2763} 2764 2765static int 2766hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2767{ 2768 struct hdac_chan *ch = data; 2769 struct hdac_softc *sc = ch->devinfo->codec->sc; 2770 2771 blksz &= ~0x7f; 2772 if (blksz < 0x80) 2773 blksz = 0x80; 2774 2775 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2776 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2777 2778 if ((sndbuf_getblksz(ch->b) != blksz || 2779 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2780 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2781 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2782 __func__, blksz, ch->blkcnt); 2783 2784 ch->blksz = sndbuf_getblksz(ch->b); 2785 2786 return (ch->blksz); 2787} 2788 2789static void 2790hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2791{ 2792 struct hdac_devinfo *devinfo = ch->devinfo; 2793 nid_t cad = devinfo->codec->cad; 2794 int i; 2795 2796 hdac_stream_stop(ch); 2797 2798 for (i = 0; ch->io[i] != -1; i++) { 2799 hdac_command(sc, 2800 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2801 0), cad); 2802 } 2803} 2804 2805static void 2806hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2807{ 2808 ch->ptr = 0; 2809 ch->prevptr = 0; 2810 hdac_stream_stop(ch); 2811 hdac_stream_reset(ch); 2812 hdac_bdl_setup(ch); 2813 hdac_stream_setid(ch); 2814 hdac_stream_setup(ch); 2815 hdac_stream_start(ch); 2816} 2817 2818static int 2819hdac_channel_trigger(kobj_t obj, void *data, int go) 2820{ 2821 struct hdac_chan *ch = data; 2822 struct hdac_softc *sc = ch->devinfo->codec->sc; 2823 2824 hdac_lock(sc); 2825 switch (go) { 2826 case PCMTRIG_START: 2827 hdac_channel_start(sc, ch); 2828 break; 2829 case PCMTRIG_STOP: 2830 case PCMTRIG_ABORT: 2831 hdac_channel_stop(sc, ch); 2832 break; 2833 default: 2834 break; 2835 } 2836 hdac_unlock(sc); 2837 2838 return (0); 2839} 2840 2841static int 2842hdac_channel_getptr(kobj_t obj, void *data) 2843{ 2844 struct hdac_chan *ch = data; 2845 struct hdac_softc *sc = ch->devinfo->codec->sc; 2846 uint32_t ptr; 2847 2848 hdac_lock(sc); 2849 if (sc->polling != 0) 2850 ptr = ch->ptr; 2851 else 2852 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2853 hdac_unlock(sc); 2854 2855 /* 2856 * Round to available space and force 128 bytes aligment. 2857 */ 2858 ptr %= ch->blksz * ch->blkcnt; 2859 ptr &= ~0x7f; 2860 2861 return (ptr); 2862} 2863 2864static struct pcmchan_caps * 2865hdac_channel_getcaps(kobj_t obj, void *data) 2866{ 2867 return (&((struct hdac_chan *)data)->caps); 2868} 2869 2870static kobj_method_t hdac_channel_methods[] = { 2871 KOBJMETHOD(channel_init, hdac_channel_init), 2872 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2873 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2874 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2875 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2876 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2877 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2878 { 0, 0 } 2879}; 2880CHANNEL_DECLARE(hdac_channel); 2881 2882static int 2883hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2884{ 2885 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2886 struct hdac_softc *sc = devinfo->codec->sc; 2887 struct hdac_widget *w, *cw; 2888 struct hdac_audio_ctl *ctl; 2889 uint32_t mask, recmask, id; 2890 int i, j, softpcmvol; 2891 nid_t cad; 2892 2893 hdac_lock(sc); 2894 2895 mask = 0; 2896 recmask = 0; 2897 2898 id = hdac_codec_id(devinfo); 2899 cad = devinfo->codec->cad; 2900 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2901 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2902 sc->pci_subvendor) && 2903 hdac_hp_switch[i].id == id)) 2904 continue; 2905 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2906 if (w != NULL && w->enable != 0 2907 && w->type == 2908 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2909 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2910 hdac_command(sc, 2911 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2912 w->nid, 2913 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2914 HDAC_UNSOLTAG_EVENT_HP), cad); 2915 hdac_hp_switch_handler(devinfo); 2916 HDA_BOOTVERBOSE( 2917 device_printf(sc->dev, 2918 "HDA_DEBUG: Enabling headphone/speaker " 2919 "audio routing switching:\n"); 2920 device_printf(sc->dev, 2921 "HDA_DEBUG: \tindex=%d nid=%d " 2922 "pci_subvendor=0x%08x " 2923 "codec=0x%08x\n", 2924 i, w->nid, sc->pci_subvendor, id); 2925 ); 2926 } 2927 break; 2928 } 2929 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2930 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2931 sc->pci_subvendor) && 2932 hdac_eapd_switch[i].id == id)) 2933 continue; 2934 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2935 if (w == NULL || w->enable == 0) 2936 break; 2937 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2938 w->param.eapdbtl == HDAC_INVALID) 2939 break; 2940 mask |= SOUND_MASK_OGAIN; 2941 break; 2942 } 2943 2944 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2945 w = hdac_widget_get(devinfo, i); 2946 if (w == NULL || w->enable == 0) 2947 continue; 2948 mask |= w->ctlflags; 2949 if (!(w->pflags & HDA_ADC_RECSEL)) 2950 continue; 2951 for (j = 0; j < w->nconns; j++) { 2952 cw = hdac_widget_get(devinfo, w->conns[j]); 2953 if (cw == NULL || cw->enable == 0) 2954 continue; 2955 recmask |= cw->ctlflags; 2956 } 2957 } 2958 2959 if (!(mask & SOUND_MASK_PCM)) { 2960 softpcmvol = 1; 2961 mask |= SOUND_MASK_PCM; 2962 } else 2963 softpcmvol = (devinfo->function.audio.quirks & 2964 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2965 2966 i = 0; 2967 ctl = NULL; 2968 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2969 if (ctl->widget == NULL || ctl->enable == 0) 2970 continue; 2971 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2972 continue; 2973 if (ctl->step > 0) 2974 break; 2975 } 2976 2977 if (softpcmvol == 1 || ctl == NULL) { 2978 struct snddev_info *d = NULL; 2979 d = device_get_softc(sc->dev); 2980 if (d != NULL) { 2981 d->flags |= SD_F_SOFTPCMVOL; 2982 HDA_BOOTVERBOSE( 2983 device_printf(sc->dev, 2984 "HDA_DEBUG: %s Soft PCM volume\n", 2985 (softpcmvol == 1) ? 2986 "Forcing" : "Enabling"); 2987 ); 2988 } 2989 i = 0; 2990 /* 2991 * XXX Temporary quirk for STAC9220, until the parser 2992 * become smarter. 2993 */ 2994 if (id == HDA_CODEC_STAC9220) { 2995 mask |= SOUND_MASK_VOLUME; 2996 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2997 NULL) { 2998 if (ctl->widget == NULL || ctl->enable == 0) 2999 continue; 3000 if (ctl->widget->nid == 11 && ctl->index == 0) { 3001 ctl->ossmask = SOUND_MASK_VOLUME; 3002 ctl->ossval = 100 | (100 << 8); 3003 } else 3004 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3005 } 3006 } else if (id == HDA_CODEC_STAC9221) { 3007 mask |= SOUND_MASK_VOLUME; 3008 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3009 NULL) { 3010 if (ctl->widget == NULL) 3011 continue; 3012 if (ctl->widget->nid == 2 && ctl->index == 0) { 3013 ctl->enable = 1; 3014 ctl->ossmask = SOUND_MASK_VOLUME; 3015 ctl->ossval = 100 | (100 << 8); 3016 } else if (ctl->enable == 0) 3017 continue; 3018 else 3019 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3020 } 3021 } else { 3022 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3023 SOUND_MASK_PCM); 3024 if (!(mask & SOUND_MASK_VOLUME)) 3025 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3026 SOUND_MIXER_NONE); 3027 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3028 NULL) { 3029 if (ctl->widget == NULL || ctl->enable == 0) 3030 continue; 3031 if (!HDA_FLAG_MATCH(ctl->ossmask, 3032 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3033 continue; 3034 if (!(ctl->mute == 1 && ctl->step == 0)) 3035 ctl->enable = 0; 3036 } 3037 } 3038 } 3039 3040 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 3041 3042 mix_setrecdevs(m, recmask); 3043 mix_setdevs(m, mask); 3044 3045 hdac_unlock(sc); 3046 3047 return (0); 3048} 3049 3050static int 3051hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3052 unsigned left, unsigned right) 3053{ 3054 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3055 struct hdac_softc *sc = devinfo->codec->sc; 3056 struct hdac_widget *w; 3057 struct hdac_audio_ctl *ctl; 3058 uint32_t id, mute; 3059 int lvol, rvol, mlvol, mrvol; 3060 int i = 0; 3061 3062 hdac_lock(sc); 3063 if (dev == SOUND_MIXER_OGAIN) { 3064 uint32_t orig; 3065 /*if (left != right || !(left == 0 || left == 1)) { 3066 hdac_unlock(sc); 3067 return (-1); 3068 }*/ 3069 id = hdac_codec_id(devinfo); 3070 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3071 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3072 sc->pci_subvendor) && 3073 hdac_eapd_switch[i].id == id) 3074 break; 3075 } 3076 if (i >= HDAC_EAPD_SWITCH_LEN) { 3077 hdac_unlock(sc); 3078 return (-1); 3079 } 3080 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3081 if (w == NULL || 3082 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3083 w->param.eapdbtl == HDAC_INVALID) { 3084 hdac_unlock(sc); 3085 return (-1); 3086 } 3087 orig = w->param.eapdbtl; 3088 if (left == 0) 3089 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3090 else 3091 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3092 if (orig != w->param.eapdbtl) { 3093 uint32_t val; 3094 3095 if (hdac_eapd_switch[i].hp_switch != 0) 3096 hdac_hp_switch_handler(devinfo); 3097 val = w->param.eapdbtl; 3098 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3099 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3100 hdac_command(sc, 3101 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3102 w->nid, val), devinfo->codec->cad); 3103 } 3104 hdac_unlock(sc); 3105 return (left | (left << 8)); 3106 } 3107 if (dev == SOUND_MIXER_VOLUME) 3108 devinfo->function.audio.mvol = left | (right << 8); 3109 3110 mlvol = devinfo->function.audio.mvol & 0x7f; 3111 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3112 lvol = 0; 3113 rvol = 0; 3114 3115 i = 0; 3116 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3117 if (ctl->widget == NULL || ctl->enable == 0 || 3118 !(ctl->ossmask & (1 << dev))) 3119 continue; 3120 switch (dev) { 3121 case SOUND_MIXER_VOLUME: 3122 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3123 lvol = (lvol * ctl->step) / 100; 3124 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3125 rvol = (rvol * ctl->step) / 100; 3126 break; 3127 default: 3128 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3129 lvol = (left * mlvol) / 100; 3130 lvol = (lvol * ctl->step) / 100; 3131 rvol = (right * mrvol) / 100; 3132 rvol = (rvol * ctl->step) / 100; 3133 } else { 3134 lvol = (left * ctl->step) / 100; 3135 rvol = (right * ctl->step) / 100; 3136 } 3137 ctl->ossval = left | (right << 8); 3138 break; 3139 } 3140 mute = 0; 3141 if (ctl->step < 1) { 3142 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3143 (ctl->muted & HDA_AMP_MUTE_LEFT); 3144 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3145 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3146 } else { 3147 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3148 (ctl->muted & HDA_AMP_MUTE_LEFT); 3149 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3150 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3151 } 3152 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3153 } 3154 hdac_unlock(sc); 3155 3156 return (left | (right << 8)); 3157} 3158 3159static int 3160hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3161{ 3162 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3163 struct hdac_widget *w, *cw; 3164 struct hdac_softc *sc = devinfo->codec->sc; 3165 uint32_t ret = src, target; 3166 int i, j; 3167 3168 target = 0; 3169 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3170 if (src & (1 << i)) { 3171 target = 1 << i; 3172 break; 3173 } 3174 } 3175 3176 hdac_lock(sc); 3177 3178 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3179 w = hdac_widget_get(devinfo, i); 3180 if (w == NULL || w->enable == 0) 3181 continue; 3182 if (!(w->pflags & HDA_ADC_RECSEL)) 3183 continue; 3184 for (j = 0; j < w->nconns; j++) { 3185 cw = hdac_widget_get(devinfo, w->conns[j]); 3186 if (cw == NULL || cw->enable == 0) 3187 continue; 3188 if ((target == SOUND_MASK_VOLUME && 3189 cw->type != 3190 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3191 (target != SOUND_MASK_VOLUME && 3192 cw->type == 3193 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3194 continue; 3195 if (cw->ctlflags & target) { 3196 hdac_widget_connection_select(w, j); 3197 ret = target; 3198 j += w->nconns; 3199 } 3200 } 3201 } 3202 3203 hdac_unlock(sc); 3204 3205 return (ret); 3206} 3207 3208static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3209 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3210 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3211 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3212 { 0, 0 } 3213}; 3214MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3215 3216/**************************************************************************** 3217 * int hdac_attach(device_t) 3218 * 3219 * Attach the device into the kernel. Interrupts usually won't be enabled 3220 * when this function is called. Setup everything that doesn't require 3221 * interrupts and defer probing of codecs until interrupts are enabled. 3222 ****************************************************************************/ 3223static int 3224hdac_attach(device_t dev) 3225{ 3226 struct hdac_softc *sc; 3227 int result; 3228 int i = 0; 3229 3230 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3231 if (sc == NULL) { 3232 device_printf(dev, "cannot allocate softc\n"); 3233 return (ENOMEM); 3234 } 3235 3236 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3237 sc->dev = dev; 3238 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3239 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3240 3241 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3242 /* Screw nx6325 - subdevice/subvendor swapped */ 3243 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3244 } 3245 3246 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3247 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3248 3249 sc->poll_ticks = 1; 3250 if (resource_int_value(device_get_name(sc->dev), 3251 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3252 sc->polling = 1; 3253 else 3254 sc->polling = 0; 3255 3256 sc->chan_size = pcm_getbuffersize(dev, 3257 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3258 3259 if (resource_int_value(device_get_name(sc->dev), 3260 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3261 i &= ~0x7f; 3262 if (i < 0x80) 3263 i = 0x80; 3264 sc->chan_blkcnt = sc->chan_size / i; 3265 i = 0; 3266 while (sc->chan_blkcnt >> i) 3267 i++; 3268 sc->chan_blkcnt = 1 << (i - 1); 3269 if (sc->chan_blkcnt < HDA_BDL_MIN) 3270 sc->chan_blkcnt = HDA_BDL_MIN; 3271 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3272 sc->chan_blkcnt = HDA_BDL_MAX; 3273 } else 3274 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3275 3276 result = bus_dma_tag_create(NULL, /* parent */ 3277 HDAC_DMA_ALIGNMENT, /* alignment */ 3278 0, /* boundary */ 3279 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3280 BUS_SPACE_MAXADDR, /* highaddr */ 3281 NULL, /* filtfunc */ 3282 NULL, /* fistfuncarg */ 3283 sc->chan_size, /* maxsize */ 3284 1, /* nsegments */ 3285 sc->chan_size, /* maxsegsz */ 3286 0, /* flags */ 3287 NULL, /* lockfunc */ 3288 NULL, /* lockfuncarg */ 3289 &sc->chan_dmat); /* dmat */ 3290 if (result != 0) { 3291 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3292 __func__, result); 3293 snd_mtxfree(sc->lock); 3294 free(sc, M_DEVBUF); 3295 return (ENXIO); 3296 } 3297 3298 3299 sc->hdabus = NULL; 3300 for (i = 0; i < HDAC_CODEC_MAX; i++) 3301 sc->codecs[i] = NULL; 3302 3303 pci_enable_busmaster(dev); 3304 3305 /* Allocate resources */ 3306 result = hdac_mem_alloc(sc); 3307 if (result != 0) 3308 goto hdac_attach_fail; 3309 result = hdac_irq_alloc(sc); 3310 if (result != 0) 3311 goto hdac_attach_fail; 3312 3313 /* Get Capabilities */ 3314 result = hdac_get_capabilities(sc); 3315 if (result != 0) 3316 goto hdac_attach_fail; 3317 3318 /* Allocate CORB and RIRB dma memory */ 3319 result = hdac_dma_alloc(sc, &sc->corb_dma, 3320 sc->corb_size * sizeof(uint32_t)); 3321 if (result != 0) 3322 goto hdac_attach_fail; 3323 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3324 sc->rirb_size * sizeof(struct hdac_rirb)); 3325 if (result != 0) 3326 goto hdac_attach_fail; 3327 3328 /* Quiesce everything */ 3329 hdac_reset(sc); 3330 3331 /* Disable PCI-Express QOS */ 3332 pci_write_config(sc->dev, 0x44, 3333 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3334 3335 /* Initialize the CORB and RIRB */ 3336 hdac_corb_init(sc); 3337 hdac_rirb_init(sc); 3338 3339 /* Defer remaining of initialization until interrupts are enabled */ 3340 sc->intrhook.ich_func = hdac_attach2; 3341 sc->intrhook.ich_arg = (void *)sc; 3342 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3343 sc->intrhook.ich_func = NULL; 3344 hdac_attach2((void *)sc); 3345 } 3346 3347 return (0); 3348 3349hdac_attach_fail: 3350 hdac_dma_free(&sc->rirb_dma); 3351 hdac_dma_free(&sc->corb_dma); 3352 hdac_irq_free(sc); 3353 hdac_mem_free(sc); 3354 snd_mtxfree(sc->lock); 3355 free(sc, M_DEVBUF); 3356 3357 return (ENXIO); 3358} 3359 3360static void 3361hdac_audio_parse(struct hdac_devinfo *devinfo) 3362{ 3363 struct hdac_softc *sc = devinfo->codec->sc; 3364 struct hdac_widget *w; 3365 uint32_t res; 3366 int i; 3367 nid_t cad, nid; 3368 3369 cad = devinfo->codec->cad; 3370 nid = devinfo->nid; 3371 3372 hdac_command(sc, 3373 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3374 3375 DELAY(100); 3376 3377 res = hdac_command(sc, 3378 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3379 3380 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3381 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3382 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3383 3384 HDA_BOOTVERBOSE( 3385 device_printf(sc->dev, " Vendor: 0x%08x\n", 3386 devinfo->vendor_id); 3387 device_printf(sc->dev, " Device: 0x%08x\n", 3388 devinfo->device_id); 3389 device_printf(sc->dev, " Revision: 0x%08x\n", 3390 devinfo->revision_id); 3391 device_printf(sc->dev, " Stepping: 0x%08x\n", 3392 devinfo->stepping_id); 3393 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3394 sc->pci_subvendor); 3395 device_printf(sc->dev, " Nodes: start=%d " 3396 "endnode=%d total=%d\n", 3397 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3398 ); 3399 3400 res = hdac_command(sc, 3401 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3402 cad); 3403 devinfo->function.audio.supp_stream_formats = res; 3404 3405 res = hdac_command(sc, 3406 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3407 cad); 3408 devinfo->function.audio.supp_pcm_size_rate = res; 3409 3410 res = hdac_command(sc, 3411 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3412 cad); 3413 devinfo->function.audio.outamp_cap = res; 3414 3415 res = hdac_command(sc, 3416 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3417 cad); 3418 devinfo->function.audio.inamp_cap = res; 3419 3420 if (devinfo->nodecnt > 0) { 3421 hdac_unlock(sc); 3422 devinfo->widget = (struct hdac_widget *)malloc( 3423 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3424 M_NOWAIT | M_ZERO); 3425 hdac_lock(sc); 3426 } else 3427 devinfo->widget = NULL; 3428 3429 if (devinfo->widget == NULL) { 3430 device_printf(sc->dev, "unable to allocate widgets!\n"); 3431 devinfo->endnode = devinfo->startnode; 3432 devinfo->nodecnt = 0; 3433 return; 3434 } 3435 3436 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3437 w = hdac_widget_get(devinfo, i); 3438 if (w == NULL) 3439 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3440 else { 3441 w->devinfo = devinfo; 3442 w->nid = i; 3443 w->enable = 1; 3444 w->selconn = -1; 3445 w->pflags = 0; 3446 w->ctlflags = 0; 3447 w->param.eapdbtl = HDAC_INVALID; 3448 hdac_widget_parse(w); 3449 } 3450 } 3451} 3452 3453static void 3454hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3455{ 3456 struct hdac_softc *sc = devinfo->codec->sc; 3457 struct hdac_audio_ctl *ctls; 3458 struct hdac_widget *w, *cw; 3459 int i, j, cnt, max, ocap, icap; 3460 int mute, offset, step, size; 3461 3462 /* XXX This is redundant */ 3463 max = 0; 3464 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3465 w = hdac_widget_get(devinfo, i); 3466 if (w == NULL || w->enable == 0) 3467 continue; 3468 if (w->param.outamp_cap != 0) 3469 max++; 3470 if (w->param.inamp_cap != 0) { 3471 switch (w->type) { 3472 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3473 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3474 for (j = 0; j < w->nconns; j++) { 3475 cw = hdac_widget_get(devinfo, 3476 w->conns[j]); 3477 if (cw == NULL || cw->enable == 0) 3478 continue; 3479 max++; 3480 } 3481 break; 3482 default: 3483 max++; 3484 break; 3485 } 3486 } 3487 } 3488 3489 devinfo->function.audio.ctlcnt = max; 3490 3491 if (max < 1) 3492 return; 3493 3494 hdac_unlock(sc); 3495 ctls = (struct hdac_audio_ctl *)malloc( 3496 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3497 hdac_lock(sc); 3498 3499 if (ctls == NULL) { 3500 /* Blekh! */ 3501 device_printf(sc->dev, "unable to allocate ctls!\n"); 3502 devinfo->function.audio.ctlcnt = 0; 3503 return; 3504 } 3505 3506 cnt = 0; 3507 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3508 if (cnt >= max) { 3509 device_printf(sc->dev, "%s: Ctl overflow!\n", 3510 __func__); 3511 break; 3512 } 3513 w = hdac_widget_get(devinfo, i); 3514 if (w == NULL || w->enable == 0) 3515 continue; 3516 ocap = w->param.outamp_cap; 3517 icap = w->param.inamp_cap; 3518 if (ocap != 0) { 3519 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3520 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3521 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3522 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3523 /*if (offset > step) { 3524 HDA_BOOTVERBOSE( 3525 device_printf(sc->dev, 3526 "HDA_DEBUG: BUGGY outamp: nid=%d " 3527 "[offset=%d > step=%d]\n", 3528 w->nid, offset, step); 3529 ); 3530 offset = step; 3531 }*/ 3532 ctls[cnt].enable = 1; 3533 ctls[cnt].widget = w; 3534 ctls[cnt].mute = mute; 3535 ctls[cnt].step = step; 3536 ctls[cnt].size = size; 3537 ctls[cnt].offset = offset; 3538 ctls[cnt].left = offset; 3539 ctls[cnt].right = offset; 3540 ctls[cnt++].dir = HDA_CTL_OUT; 3541 } 3542 3543 if (icap != 0) { 3544 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3545 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3546 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3547 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3548 /*if (offset > step) { 3549 HDA_BOOTVERBOSE( 3550 device_printf(sc->dev, 3551 "HDA_DEBUG: BUGGY inamp: nid=%d " 3552 "[offset=%d > step=%d]\n", 3553 w->nid, offset, step); 3554 ); 3555 offset = step; 3556 }*/ 3557 switch (w->type) { 3558 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3559 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3560 for (j = 0; j < w->nconns; j++) { 3561 if (cnt >= max) { 3562 device_printf(sc->dev, 3563 "%s: Ctl overflow!\n", 3564 __func__); 3565 break; 3566 } 3567 cw = hdac_widget_get(devinfo, 3568 w->conns[j]); 3569 if (cw == NULL || cw->enable == 0) 3570 continue; 3571 ctls[cnt].enable = 1; 3572 ctls[cnt].widget = w; 3573 ctls[cnt].childwidget = cw; 3574 ctls[cnt].index = j; 3575 ctls[cnt].mute = mute; 3576 ctls[cnt].step = step; 3577 ctls[cnt].size = size; 3578 ctls[cnt].offset = offset; 3579 ctls[cnt].left = offset; 3580 ctls[cnt].right = offset; 3581 ctls[cnt++].dir = HDA_CTL_IN; 3582 } 3583 break; 3584 default: 3585 if (cnt >= max) { 3586 device_printf(sc->dev, 3587 "%s: Ctl overflow!\n", 3588 __func__); 3589 break; 3590 } 3591 ctls[cnt].enable = 1; 3592 ctls[cnt].widget = w; 3593 ctls[cnt].mute = mute; 3594 ctls[cnt].step = step; 3595 ctls[cnt].size = size; 3596 ctls[cnt].offset = offset; 3597 ctls[cnt].left = offset; 3598 ctls[cnt].right = offset; 3599 ctls[cnt++].dir = HDA_CTL_IN; 3600 break; 3601 } 3602 } 3603 } 3604 3605 devinfo->function.audio.ctl = ctls; 3606} 3607 3608static const struct { 3609 uint32_t model; 3610 uint32_t id; 3611 uint32_t set, unset; 3612} hdac_quirks[] = { 3613 /* 3614 * XXX Force stereo quirk. Monoural recording / playback 3615 * on few codecs (especially ALC880) seems broken or 3616 * perhaps unsupported. 3617 */ 3618 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3619 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3620 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3621 HDA_QUIRK_GPIO0, 0 }, 3622 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3623 HDA_QUIRK_GPIO0, 0 }, 3624 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3625 HDA_QUIRK_GPIO0, 0 }, 3626 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3627 HDA_QUIRK_EAPDINV, 0 }, 3628 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3629 HDA_QUIRK_EAPDINV, 0 }, 3630 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3631 HDA_QUIRK_GPIO1, 0 }, 3632 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3633 HDA_QUIRK_EAPDINV, 0 }, 3634 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3635 HDA_QUIRK_EAPDINV, 0 }, 3636 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3637 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3638 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3639 0, HDA_QUIRK_FORCESTEREO }, 3640 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3641 HDA_QUIRK_SOFTPCMVOL, 0 } 3642}; 3643#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3644 3645static void 3646hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3647{ 3648 struct hdac_widget *w; 3649 struct hdac_audio_ctl *ctl; 3650 uint32_t id, subvendor; 3651 int i; 3652 3653 id = hdac_codec_id(devinfo); 3654 subvendor = devinfo->codec->sc->pci_subvendor; 3655 3656 /* 3657 * Quirks 3658 */ 3659 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3660 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3661 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3662 continue; 3663 if (hdac_quirks[i].set != 0) 3664 devinfo->function.audio.quirks |= 3665 hdac_quirks[i].set; 3666 if (hdac_quirks[i].unset != 0) 3667 devinfo->function.audio.quirks &= 3668 ~(hdac_quirks[i].unset); 3669 } 3670 3671 switch (id) { 3672 case HDA_CODEC_ALC260: 3673 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3674 w = hdac_widget_get(devinfo, i); 3675 if (w == NULL || w->enable == 0) 3676 continue; 3677 if (w->type != 3678 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3679 continue; 3680 if (w->nid != 5) 3681 w->enable = 0; 3682 } 3683 if (subvendor == HP_XW4300_SUBVENDOR) { 3684 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3685 if (ctl != NULL && ctl->widget != NULL) { 3686 ctl->ossmask = SOUND_MASK_SPEAKER; 3687 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3688 } 3689 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3690 if (ctl != NULL && ctl->widget != NULL) { 3691 ctl->ossmask = SOUND_MASK_SPEAKER; 3692 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3693 } 3694 } 3695 break; 3696 case HDA_CODEC_ALC861: 3697 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3698 if (ctl != NULL) 3699 ctl->muted = HDA_AMP_MUTE_ALL; 3700 break; 3701 case HDA_CODEC_ALC880: 3702 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3703 w = hdac_widget_get(devinfo, i); 3704 if (w == NULL || w->enable == 0) 3705 continue; 3706 if (w->type == 3707 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3708 w->nid != 9 && w->nid != 29) { 3709 w->enable = 0; 3710 } else if (w->type != 3711 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3712 w->nid == 29) { 3713 w->type = 3714 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3715 w->param.widget_cap &= 3716 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3717 w->param.widget_cap |= 3718 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3719 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3720 strlcpy(w->name, "beep widget", sizeof(w->name)); 3721 } 3722 } 3723 break; 3724 case HDA_CODEC_ALC883: 3725 /* 3726 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 3727 * Clear vref cap for jack connectivity. 3728 */ 3729 w = hdac_widget_get(devinfo, 24); 3730 if (w != NULL && w->enable != 0 && w->type == 3731 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3732 (w->wclass.pin.config & 3733 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3734 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3735 w->wclass.pin.cap &= ~( 3736 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3737 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3738 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3739 w = hdac_widget_get(devinfo, 25); 3740 if (w != NULL && w->enable != 0 && w->type == 3741 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3742 (w->wclass.pin.config & 3743 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3744 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3745 w->wclass.pin.cap &= ~( 3746 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3747 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3748 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3749 /* 3750 * nid: 26 = Line-in, leave it alone. 3751 */ 3752 break; 3753 case HDA_CODEC_AD1981HD: 3754 w = hdac_widget_get(devinfo, 11); 3755 if (w != NULL && w->enable != 0 && w->nconns > 3) 3756 w->selconn = 3; 3757 if (subvendor == IBM_M52_SUBVENDOR) { 3758 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3759 if (ctl != NULL) 3760 ctl->ossmask = SOUND_MASK_SPEAKER; 3761 } 3762 break; 3763 case HDA_CODEC_AD1986A: 3764 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3765 w = hdac_widget_get(devinfo, i); 3766 if (w == NULL || w->enable == 0) 3767 continue; 3768 if (w->type != 3769 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3770 continue; 3771 if (w->nid != 3) 3772 w->enable = 0; 3773 } 3774 break; 3775 case HDA_CODEC_STAC9221: 3776 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3777 w = hdac_widget_get(devinfo, i); 3778 if (w == NULL || w->enable == 0) 3779 continue; 3780 if (w->type != 3781 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3782 continue; 3783 if (w->nid != 2) 3784 w->enable = 0; 3785 } 3786 break; 3787 case HDA_CODEC_STAC9221D: 3788 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3789 w = hdac_widget_get(devinfo, i); 3790 if (w == NULL || w->enable == 0) 3791 continue; 3792 if (w->type == 3793 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3794 w->nid != 6) 3795 w->enable = 0; 3796 3797 } 3798 break; 3799 default: 3800 break; 3801 } 3802} 3803 3804static int 3805hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3806{ 3807 int *dev = &devinfo->function.audio.ossidx; 3808 3809 while (*dev < SOUND_MIXER_NRDEVICES) { 3810 switch (*dev) { 3811 case SOUND_MIXER_VOLUME: 3812 case SOUND_MIXER_BASS: 3813 case SOUND_MIXER_TREBLE: 3814 case SOUND_MIXER_PCM: 3815 case SOUND_MIXER_SPEAKER: 3816 case SOUND_MIXER_LINE: 3817 case SOUND_MIXER_MIC: 3818 case SOUND_MIXER_CD: 3819 case SOUND_MIXER_RECLEV: 3820 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3821 (*dev)++; 3822 break; 3823 default: 3824 return (*dev)++; 3825 break; 3826 } 3827 } 3828 3829 return (-1); 3830} 3831 3832static int 3833hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3834{ 3835 struct hdac_widget *w; 3836 int i, ret = 0; 3837 3838 if (depth > HDA_PARSE_MAXDEPTH) 3839 return (0); 3840 w = hdac_widget_get(devinfo, nid); 3841 if (w == NULL || w->enable == 0) 3842 return (0); 3843 switch (w->type) { 3844 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3845 w->pflags |= HDA_DAC_PATH; 3846 ret = 1; 3847 break; 3848 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3849 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3850 for (i = 0; i < w->nconns; i++) { 3851 if (hdac_widget_find_dac_path(devinfo, 3852 w->conns[i], depth + 1) != 0) { 3853 if (w->selconn == -1) 3854 w->selconn = i; 3855 ret = 1; 3856 w->pflags |= HDA_DAC_PATH; 3857 } 3858 } 3859 break; 3860 default: 3861 break; 3862 } 3863 return (ret); 3864} 3865 3866static int 3867hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3868{ 3869 struct hdac_widget *w; 3870 int i, conndev, ret = 0; 3871 3872 if (depth > HDA_PARSE_MAXDEPTH) 3873 return (0); 3874 w = hdac_widget_get(devinfo, nid); 3875 if (w == NULL || w->enable == 0) 3876 return (0); 3877 switch (w->type) { 3878 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3879 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3880 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3881 for (i = 0; i < w->nconns; i++) { 3882 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3883 depth + 1) != 0) { 3884 if (w->selconn == -1) 3885 w->selconn = i; 3886 w->pflags |= HDA_ADC_PATH; 3887 ret = 1; 3888 } 3889 } 3890 break; 3891 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3892 conndev = w->wclass.pin.config & 3893 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3894 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3895 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3896 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3897 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3898 w->pflags |= HDA_ADC_PATH; 3899 ret = 1; 3900 } 3901 break; 3902 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3903 if (w->pflags & HDA_DAC_PATH) { 3904 w->pflags |= HDA_ADC_PATH; 3905 ret = 1; 3906 } 3907 break;*/ 3908 default: 3909 break; 3910 } 3911 return (ret); 3912} 3913 3914static uint32_t 3915hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3916 nid_t nid, nid_t pnid, int index, int depth) 3917{ 3918 struct hdac_widget *w, *pw; 3919 struct hdac_audio_ctl *ctl; 3920 uint32_t fl = 0; 3921 int i, ossdev, conndev, strategy; 3922 3923 if (depth > HDA_PARSE_MAXDEPTH) 3924 return (0); 3925 3926 w = hdac_widget_get(devinfo, nid); 3927 if (w == NULL || w->enable == 0) 3928 return (0); 3929 3930 pw = hdac_widget_get(devinfo, pnid); 3931 strategy = devinfo->function.audio.parsing_strategy; 3932 3933 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3934 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3935 for (i = 0; i < w->nconns; i++) { 3936 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3937 w->nid, i, depth + 1); 3938 } 3939 w->ctlflags |= fl; 3940 return (fl); 3941 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3942 (w->pflags & HDA_DAC_PATH)) { 3943 i = 0; 3944 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3945 if (ctl->enable == 0 || ctl->widget == NULL) 3946 continue; 3947 /* XXX This should be compressed! */ 3948 if ((ctl->widget->nid == w->nid) || 3949 (ctl->widget->nid == pnid && ctl->index == index && 3950 (ctl->dir & HDA_CTL_IN)) || 3951 (ctl->widget->nid == pnid && pw != NULL && 3952 pw->type == 3953 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3954 (pw->nconns < 2 || pw->selconn == index || 3955 pw->selconn == -1) && 3956 (ctl->dir & HDA_CTL_OUT)) || 3957 (strategy == HDA_PARSE_DIRECT && 3958 ctl->widget->nid == w->nid)) { 3959 /*if (pw != NULL && pw->selconn == -1) 3960 pw->selconn = index; 3961 fl |= SOUND_MASK_VOLUME; 3962 fl |= SOUND_MASK_PCM; 3963 ctl->ossmask |= SOUND_MASK_VOLUME; 3964 ctl->ossmask |= SOUND_MASK_PCM; 3965 ctl->ossdev = SOUND_MIXER_PCM;*/ 3966 if (!(w->ctlflags & SOUND_MASK_PCM) || 3967 (pw != NULL && 3968 !(pw->ctlflags & SOUND_MASK_PCM))) { 3969 fl |= SOUND_MASK_VOLUME; 3970 fl |= SOUND_MASK_PCM; 3971 ctl->ossmask |= SOUND_MASK_VOLUME; 3972 ctl->ossmask |= SOUND_MASK_PCM; 3973 ctl->ossdev = SOUND_MIXER_PCM; 3974 w->ctlflags |= SOUND_MASK_VOLUME; 3975 w->ctlflags |= SOUND_MASK_PCM; 3976 if (pw != NULL) { 3977 if (pw->selconn == -1) 3978 pw->selconn = index; 3979 pw->ctlflags |= 3980 SOUND_MASK_VOLUME; 3981 pw->ctlflags |= 3982 SOUND_MASK_PCM; 3983 } 3984 } 3985 } 3986 } 3987 w->ctlflags |= fl; 3988 return (fl); 3989 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3990 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3991 (w->pflags & HDA_ADC_PATH)) { 3992 conndev = w->wclass.pin.config & 3993 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3994 i = 0; 3995 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3996 if (ctl->enable == 0 || ctl->widget == NULL) 3997 continue; 3998 /* XXX This should be compressed! */ 3999 if (((ctl->widget->nid == pnid && ctl->index == index && 4000 (ctl->dir & HDA_CTL_IN)) || 4001 (ctl->widget->nid == pnid && pw != NULL && 4002 pw->type == 4003 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4004 (pw->nconns < 2 || pw->selconn == index || 4005 pw->selconn == -1) && 4006 (ctl->dir & HDA_CTL_OUT)) || 4007 (strategy == HDA_PARSE_DIRECT && 4008 ctl->widget->nid == w->nid)) && 4009 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4010 if (pw != NULL && pw->selconn == -1) 4011 pw->selconn = index; 4012 ossdev = 0; 4013 switch (conndev) { 4014 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4015 ossdev = SOUND_MIXER_MIC; 4016 break; 4017 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4018 ossdev = SOUND_MIXER_LINE; 4019 break; 4020 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4021 ossdev = SOUND_MIXER_CD; 4022 break; 4023 default: 4024 ossdev = 4025 hdac_audio_ctl_ossmixer_getnextdev( 4026 devinfo); 4027 if (ossdev < 0) 4028 ossdev = 0; 4029 break; 4030 } 4031 if (strategy == HDA_PARSE_MIXER) { 4032 fl |= SOUND_MASK_VOLUME; 4033 ctl->ossmask |= SOUND_MASK_VOLUME; 4034 } 4035 fl |= 1 << ossdev; 4036 ctl->ossmask |= 1 << ossdev; 4037 ctl->ossdev = ossdev; 4038 } 4039 } 4040 w->ctlflags |= fl; 4041 return (fl); 4042 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4043 i = 0; 4044 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4045 if (ctl->enable == 0 || ctl->widget == NULL) 4046 continue; 4047 /* XXX This should be compressed! */ 4048 if (((ctl->widget->nid == pnid && ctl->index == index && 4049 (ctl->dir & HDA_CTL_IN)) || 4050 (ctl->widget->nid == pnid && pw != NULL && 4051 pw->type == 4052 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4053 (pw->nconns < 2 || pw->selconn == index || 4054 pw->selconn == -1) && 4055 (ctl->dir & HDA_CTL_OUT)) || 4056 (strategy == HDA_PARSE_DIRECT && 4057 ctl->widget->nid == w->nid)) && 4058 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4059 if (pw != NULL && pw->selconn == -1) 4060 pw->selconn = index; 4061 fl |= SOUND_MASK_VOLUME; 4062 fl |= SOUND_MASK_SPEAKER; 4063 ctl->ossmask |= SOUND_MASK_VOLUME; 4064 ctl->ossmask |= SOUND_MASK_SPEAKER; 4065 ctl->ossdev = SOUND_MIXER_SPEAKER; 4066 } 4067 } 4068 w->ctlflags |= fl; 4069 return (fl); 4070 } 4071 return (0); 4072} 4073 4074static uint32_t 4075hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4076{ 4077 struct hdac_widget *w, *cw; 4078 struct hdac_audio_ctl *ctl; 4079 uint32_t fl; 4080 int i; 4081 4082 if (depth > HDA_PARSE_MAXDEPTH) 4083 return (0); 4084 4085 w = hdac_widget_get(devinfo, nid); 4086 if (w == NULL || w->enable == 0) 4087 return (0); 4088 /*if (!(w->pflags & HDA_ADC_PATH)) 4089 return (0); 4090 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4091 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4092 return (0);*/ 4093 i = 0; 4094 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4095 if (ctl->enable == 0 || ctl->widget == NULL) 4096 continue; 4097 if (ctl->widget->nid == nid) { 4098 ctl->ossmask |= SOUND_MASK_RECLEV; 4099 w->ctlflags |= SOUND_MASK_RECLEV; 4100 return (SOUND_MASK_RECLEV); 4101 } 4102 } 4103 for (i = 0; i < w->nconns; i++) { 4104 cw = hdac_widget_get(devinfo, w->conns[i]); 4105 if (cw == NULL || cw->enable == 0) 4106 continue; 4107 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4108 continue; 4109 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4110 if (fl != 0) { 4111 cw->ctlflags |= fl; 4112 w->ctlflags |= fl; 4113 return (fl); 4114 } 4115 } 4116 return (0); 4117} 4118 4119static int 4120hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4121{ 4122 struct hdac_widget *w, *cw; 4123 int i, child = 0; 4124 4125 if (depth > HDA_PARSE_MAXDEPTH) 4126 return (0); 4127 4128 w = hdac_widget_get(devinfo, nid); 4129 if (w == NULL || w->enable == 0) 4130 return (0); 4131 /*if (!(w->pflags & HDA_ADC_PATH)) 4132 return (0); 4133 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4134 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4135 return (0);*/ 4136 /* XXX weak! */ 4137 for (i = 0; i < w->nconns; i++) { 4138 cw = hdac_widget_get(devinfo, w->conns[i]); 4139 if (cw == NULL) 4140 continue; 4141 if (++child > 1) { 4142 w->pflags |= HDA_ADC_RECSEL; 4143 return (1); 4144 } 4145 } 4146 for (i = 0; i < w->nconns; i++) { 4147 if (hdac_audio_ctl_recsel_build(devinfo, 4148 w->conns[i], depth + 1) != 0) 4149 return (1); 4150 } 4151 return (0); 4152} 4153 4154static int 4155hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4156{ 4157 struct hdac_widget *w, *cw; 4158 int i, j, conndev, found_dac = 0; 4159 int strategy; 4160 4161 strategy = devinfo->function.audio.parsing_strategy; 4162 4163 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4164 w = hdac_widget_get(devinfo, i); 4165 if (w == NULL || w->enable == 0) 4166 continue; 4167 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4168 continue; 4169 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4170 continue; 4171 conndev = w->wclass.pin.config & 4172 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4173 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4174 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4175 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4176 continue; 4177 for (j = 0; j < w->nconns; j++) { 4178 cw = hdac_widget_get(devinfo, w->conns[j]); 4179 if (cw == NULL || cw->enable == 0) 4180 continue; 4181 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4182 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4183 cw->type == 4184 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4185 continue; 4186 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4187 != 0) { 4188 if (w->selconn == -1) 4189 w->selconn = j; 4190 w->pflags |= HDA_DAC_PATH; 4191 found_dac++; 4192 } 4193 } 4194 } 4195 4196 return (found_dac); 4197} 4198 4199static void 4200hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4201{ 4202 struct hdac_widget *w; 4203 struct hdac_audio_ctl *ctl; 4204 int i, j, dacs, strategy; 4205 4206 /* Construct DAC path */ 4207 strategy = HDA_PARSE_MIXER; 4208 devinfo->function.audio.parsing_strategy = strategy; 4209 HDA_BOOTVERBOSE( 4210 device_printf(devinfo->codec->sc->dev, 4211 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4212 HDA_WIDGET_PARSER_REV); 4213 ); 4214 dacs = hdac_audio_build_tree_strategy(devinfo); 4215 if (dacs == 0) { 4216 HDA_BOOTVERBOSE( 4217 device_printf(devinfo->codec->sc->dev, 4218 "HDA_DEBUG: HWiP: 0 DAC path found! " 4219 "Retrying parser " 4220 "using HDA_PARSE_DIRECT strategy.\n"); 4221 ); 4222 strategy = HDA_PARSE_DIRECT; 4223 devinfo->function.audio.parsing_strategy = strategy; 4224 dacs = hdac_audio_build_tree_strategy(devinfo); 4225 } 4226 4227 HDA_BOOTVERBOSE( 4228 device_printf(devinfo->codec->sc->dev, 4229 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4230 "strategy.\n", 4231 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4232 ); 4233 4234 /* Construct ADC path */ 4235 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4236 w = hdac_widget_get(devinfo, i); 4237 if (w == NULL || w->enable == 0) 4238 continue; 4239 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4240 continue; 4241 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4242 } 4243 4244 /* Output mixers */ 4245 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4246 w = hdac_widget_get(devinfo, i); 4247 if (w == NULL || w->enable == 0) 4248 continue; 4249 if ((strategy == HDA_PARSE_MIXER && 4250 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4251 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4252 && (w->pflags & HDA_DAC_PATH)) || 4253 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4254 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4255 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4256 w->nid, devinfo->startnode - 1, 0, 0); 4257 } else if (w->type == 4258 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4259 j = 0; 4260 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4261 NULL) { 4262 if (ctl->enable == 0 || ctl->widget == NULL) 4263 continue; 4264 if (ctl->widget->nid != w->nid) 4265 continue; 4266 ctl->ossmask |= SOUND_MASK_VOLUME; 4267 ctl->ossmask |= SOUND_MASK_SPEAKER; 4268 ctl->ossdev = SOUND_MIXER_SPEAKER; 4269 w->ctlflags |= SOUND_MASK_VOLUME; 4270 w->ctlflags |= SOUND_MASK_SPEAKER; 4271 } 4272 } 4273 } 4274 4275 /* Input mixers (rec) */ 4276 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4277 w = hdac_widget_get(devinfo, i); 4278 if (w == NULL || w->enable == 0) 4279 continue; 4280 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4281 w->pflags & HDA_ADC_PATH)) 4282 continue; 4283 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4284 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4285 } 4286} 4287 4288#define HDA_COMMIT_CONN (1 << 0) 4289#define HDA_COMMIT_CTRL (1 << 1) 4290#define HDA_COMMIT_EAPD (1 << 2) 4291#define HDA_COMMIT_GPIO (1 << 3) 4292#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4293 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4294 4295static void 4296hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4297{ 4298 struct hdac_softc *sc = devinfo->codec->sc; 4299 struct hdac_widget *w; 4300 nid_t cad; 4301 int i; 4302 4303 if (!(cfl & HDA_COMMIT_ALL)) 4304 return; 4305 4306 cad = devinfo->codec->cad; 4307 4308 if (cfl & HDA_COMMIT_GPIO) { 4309 uint32_t gdata, gmask, gdir; 4310 int commitgpio = 0; 4311 4312 gdata = 0; 4313 gmask = 0; 4314 gdir = 0; 4315 4316 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4317 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4318 0x7e7, 0), cad); 4319 4320 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4321 commitgpio = 1; 4322 else { 4323 for (i = 0; i < HDA_GPIO_MAX; i++) { 4324 if (!(devinfo->function.audio.quirks & 4325 (1 << i))) 4326 continue; 4327 if (commitgpio == 0) { 4328 commitgpio = 1; 4329 gdata = hdac_command(sc, 4330 HDA_CMD_GET_GPIO_DATA(cad, 4331 devinfo->nid), cad); 4332 gmask = hdac_command(sc, 4333 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4334 devinfo->nid), cad); 4335 gdir = hdac_command(sc, 4336 HDA_CMD_GET_GPIO_DIRECTION(cad, 4337 devinfo->nid), cad); 4338 HDA_BOOTVERBOSE( 4339 device_printf(sc->dev, 4340 "GPIO init: data=0x%08x " 4341 "mask=0x%08x dir=0x%08x\n", 4342 gdata, gmask, gdir); 4343 ); 4344 } 4345 gdata |= 1 << i; 4346 gmask |= 1 << i; 4347 gdir |= 1 << i; 4348 } 4349 } 4350 4351 if (commitgpio != 0) { 4352 HDA_BOOTVERBOSE( 4353 device_printf(sc->dev, 4354 "GPIO commit: data=0x%08x mask=0x%08x " 4355 "dir=0x%08x\n", 4356 gdata, gmask, gdir); 4357 ); 4358 hdac_command(sc, 4359 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4360 gmask), cad); 4361 hdac_command(sc, 4362 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4363 gdir), cad); 4364 hdac_command(sc, 4365 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4366 gdata), cad); 4367 } 4368 } 4369 4370 for (i = 0; i < devinfo->nodecnt; i++) { 4371 w = &devinfo->widget[i]; 4372 if (w == NULL || w->enable == 0) 4373 continue; 4374 if (cfl & HDA_COMMIT_CONN) { 4375 if (w->selconn == -1) 4376 w->selconn = 0; 4377 if (w->nconns > 0) 4378 hdac_widget_connection_select(w, w->selconn); 4379 } 4380 if ((cfl & HDA_COMMIT_CTRL) && 4381 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4382 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4383 (HDA_DAC_PATH | HDA_ADC_PATH)) 4384 device_printf(sc->dev, "WARNING: node %d " 4385 "participate both for DAC/ADC!\n", w->nid); 4386 if (w->pflags & HDA_DAC_PATH) { 4387 w->wclass.pin.ctrl &= 4388 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4389 if ((w->wclass.pin.config & 4390 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4391 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4392 w->wclass.pin.ctrl &= 4393 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4394 } else if (w->pflags & HDA_ADC_PATH) { 4395 w->wclass.pin.ctrl &= 4396 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4397 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4398 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4399 uint32_t pincap = w->wclass.pin.cap; 4400 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4401 w->wclass.pin.ctrl |= 4402 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4403 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4404 ); 4405 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4406 w->wclass.pin.ctrl |= 4407 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4408 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4409 ); 4410 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4411 w->wclass.pin.ctrl |= 4412 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4413 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4414 ); 4415 } 4416 } else 4417 w->wclass.pin.ctrl &= ~( 4418 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4419 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4420 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4421 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4422 hdac_command(sc, 4423 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4424 w->wclass.pin.ctrl), cad); 4425 } 4426 if ((cfl & HDA_COMMIT_EAPD) && 4427 w->param.eapdbtl != HDAC_INVALID) { 4428 uint32_t val; 4429 4430 val = w->param.eapdbtl; 4431 if (devinfo->function.audio.quirks & 4432 HDA_QUIRK_EAPDINV) 4433 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4434 hdac_command(sc, 4435 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4436 val), cad); 4437 4438 } 4439 DELAY(1000); 4440 } 4441} 4442 4443static void 4444hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4445{ 4446 struct hdac_softc *sc = devinfo->codec->sc; 4447 struct hdac_audio_ctl *ctl; 4448 int i; 4449 4450 devinfo->function.audio.mvol = 100 | (100 << 8); 4451 i = 0; 4452 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4453 if (ctl->enable == 0 || ctl->widget == NULL) { 4454 HDA_BOOTVERBOSE( 4455 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4456 i, (ctl->widget != NULL) ? 4457 ctl->widget->nid : -1); 4458 if (ctl->childwidget != NULL) 4459 printf(" childnid=%d", 4460 ctl->childwidget->nid); 4461 if (ctl->widget == NULL) 4462 printf(" NULL WIDGET!"); 4463 printf(" DISABLED\n"); 4464 ); 4465 continue; 4466 } 4467 HDA_BOOTVERBOSE( 4468 if (ctl->ossmask == 0) { 4469 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4470 i, ctl->widget->nid); 4471 if (ctl->childwidget != NULL) 4472 printf(" childnid=%d", 4473 ctl->childwidget->nid); 4474 printf(" Bind to NONE\n"); 4475 } 4476 ); 4477 if (ctl->step > 0) { 4478 ctl->ossval = (ctl->left * 100) / ctl->step; 4479 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4480 } else 4481 ctl->ossval = 0; 4482 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4483 ctl->left, ctl->right); 4484 } 4485} 4486 4487static int 4488hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4489{ 4490 struct hdac_chan *ch; 4491 struct hdac_widget *w; 4492 uint32_t cap, fmtcap, pcmcap, path; 4493 int i, type, ret, max; 4494 4495 if (dir == PCMDIR_PLAY) { 4496 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4497 ch = &devinfo->codec->sc->play; 4498 path = HDA_DAC_PATH; 4499 } else { 4500 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4501 ch = &devinfo->codec->sc->rec; 4502 path = HDA_ADC_PATH; 4503 } 4504 4505 ch->caps = hdac_caps; 4506 ch->caps.fmtlist = ch->fmtlist; 4507 ch->bit16 = 1; 4508 ch->bit32 = 0; 4509 ch->pcmrates[0] = 48000; 4510 ch->pcmrates[1] = 0; 4511 4512 ret = 0; 4513 fmtcap = devinfo->function.audio.supp_stream_formats; 4514 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4515 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4516 4517 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4518 w = hdac_widget_get(devinfo, i); 4519 if (w == NULL || w->enable == 0 || w->type != type || 4520 !(w->pflags & path)) 4521 continue; 4522 cap = w->param.widget_cap; 4523 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4524 continue;*/ 4525 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4526 continue; 4527 cap = w->param.supp_stream_formats; 4528 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4529 } 4530 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4531 }*/ 4532 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4533 continue; 4534 if (ret == 0) { 4535 fmtcap = w->param.supp_stream_formats; 4536 pcmcap = w->param.supp_pcm_size_rate; 4537 } else { 4538 fmtcap &= w->param.supp_stream_formats; 4539 pcmcap &= w->param.supp_pcm_size_rate; 4540 } 4541 ch->io[ret++] = i; 4542 } 4543 ch->io[ret] = -1; 4544 4545 ch->supp_stream_formats = fmtcap; 4546 ch->supp_pcm_size_rate = pcmcap; 4547 4548 /* 4549 * 8bit = 0 4550 * 16bit = 1 4551 * 20bit = 2 4552 * 24bit = 3 4553 * 32bit = 4 4554 */ 4555 if (ret > 0) { 4556 cap = pcmcap; 4557 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4558 ch->bit16 = 1; 4559 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4560 ch->bit16 = 0; 4561 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4562 ch->bit32 = 4; 4563 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4564 ch->bit32 = 3; 4565 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4566 ch->bit32 = 2; 4567 i = 0; 4568 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4569 ch->fmtlist[i++] = AFMT_S16_LE; 4570 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4571 if (ch->bit32 > 0) { 4572 if (!(devinfo->function.audio.quirks & 4573 HDA_QUIRK_FORCESTEREO)) 4574 ch->fmtlist[i++] = AFMT_S32_LE; 4575 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4576 } 4577 ch->fmtlist[i] = 0; 4578 i = 0; 4579 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4580 ch->pcmrates[i++] = 8000; 4581 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4582 ch->pcmrates[i++] = 11025; 4583 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4584 ch->pcmrates[i++] = 16000; 4585 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4586 ch->pcmrates[i++] = 22050; 4587 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4588 ch->pcmrates[i++] = 32000; 4589 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4590 ch->pcmrates[i++] = 44100; 4591 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4592 ch->pcmrates[i++] = 48000; 4593 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4594 ch->pcmrates[i++] = 88200; 4595 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4596 ch->pcmrates[i++] = 96000; 4597 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4598 ch->pcmrates[i++] = 176400; 4599 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4600 ch->pcmrates[i++] = 192000; 4601 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4602 ch->pcmrates[i] = 0; 4603 if (i > 0) { 4604 ch->caps.minspeed = ch->pcmrates[0]; 4605 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4606 } 4607 } 4608 4609 return (ret); 4610} 4611 4612static void 4613hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4614{ 4615 struct hdac_audio_ctl *ctl; 4616 struct hdac_softc *sc = devinfo->codec->sc; 4617 int i; 4618 uint32_t fl = 0; 4619 4620 4621 if (flag == 0) { 4622 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4623 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4624 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4625 } 4626 4627 i = 0; 4628 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4629 if (ctl->enable == 0 || ctl->widget == NULL || 4630 ctl->widget->enable == 0) 4631 continue; 4632 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4633 (flag != 0 && (ctl->ossmask & flag))) { 4634 if (banner != NULL) { 4635 device_printf(sc->dev, "\n"); 4636 device_printf(sc->dev, "%s\n", banner); 4637 } 4638 goto hdac_ctl_dump_it_all; 4639 } 4640 } 4641 4642 return; 4643 4644hdac_ctl_dump_it_all: 4645 i = 0; 4646 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4647 if (ctl->enable == 0 || ctl->widget == NULL || 4648 ctl->widget->enable == 0) 4649 continue; 4650 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4651 (flag != 0 && (ctl->ossmask & flag)))) 4652 continue; 4653 if (flag == 0) { 4654 device_printf(sc->dev, "\n"); 4655 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4656 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4657 } 4658 device_printf(sc->dev, " |\n"); 4659 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4660 ctl->widget->nid, ctl->index); 4661 if (ctl->childwidget != NULL) 4662 printf("(nid: %2d) ", ctl->childwidget->nid); 4663 else 4664 printf(" "); 4665 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4666 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4667 ctl->ossmask); 4668 } 4669} 4670 4671static void 4672hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4673{ 4674 uint32_t cap; 4675 4676 cap = fcap; 4677 if (cap != 0) { 4678 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4679 device_printf(sc->dev, " Format:"); 4680 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4681 printf(" AC3"); 4682 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4683 printf(" FLOAT32"); 4684 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4685 printf(" PCM"); 4686 printf("\n"); 4687 } 4688 cap = pcmcap; 4689 if (cap != 0) { 4690 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4691 device_printf(sc->dev, " PCM size:"); 4692 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4693 printf(" 8"); 4694 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4695 printf(" 16"); 4696 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4697 printf(" 20"); 4698 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4699 printf(" 24"); 4700 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4701 printf(" 32"); 4702 printf("\n"); 4703 device_printf(sc->dev, " PCM rate:"); 4704 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4705 printf(" 8"); 4706 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4707 printf(" 11"); 4708 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4709 printf(" 16"); 4710 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4711 printf(" 22"); 4712 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4713 printf(" 32"); 4714 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4715 printf(" 44"); 4716 printf(" 48"); 4717 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4718 printf(" 88"); 4719 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4720 printf(" 96"); 4721 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4722 printf(" 176"); 4723 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4724 printf(" 192"); 4725 printf("\n"); 4726 } 4727} 4728 4729static void 4730hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4731{ 4732 uint32_t pincap, wcap; 4733 4734 pincap = w->wclass.pin.cap; 4735 wcap = w->param.widget_cap; 4736 4737 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4738 device_printf(sc->dev, " "); 4739 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4740 printf(" ISC"); 4741 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4742 printf(" TRQD"); 4743 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4744 printf(" PDC"); 4745 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4746 printf(" HP"); 4747 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4748 printf(" OUT"); 4749 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4750 printf(" IN"); 4751 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4752 printf(" BAL"); 4753 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4754 printf(" VREF["); 4755 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4756 printf(" 50"); 4757 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4758 printf(" 80"); 4759 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4760 printf(" 100"); 4761 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4762 printf(" GROUND"); 4763 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4764 printf(" HIZ"); 4765 printf(" ]"); 4766 } 4767 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4768 printf(" EAPD"); 4769 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4770 printf(" : UNSOL"); 4771 printf("\n"); 4772 device_printf(sc->dev, " Pin config: 0x%08x\n", 4773 w->wclass.pin.config); 4774 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4775 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4776 printf(" HP"); 4777 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4778 printf(" IN"); 4779 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4780 printf(" OUT"); 4781 printf("\n"); 4782} 4783 4784static void 4785hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4786{ 4787 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4788 device_printf(sc->dev, " " 4789 "mute=%d step=%d size=%d offset=%d\n", 4790 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4791 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4792 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4793 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4794} 4795 4796static void 4797hdac_dump_nodes(struct hdac_devinfo *devinfo) 4798{ 4799 struct hdac_softc *sc = devinfo->codec->sc; 4800 struct hdac_widget *w, *cw; 4801 int i, j; 4802 4803 device_printf(sc->dev, "\n"); 4804 device_printf(sc->dev, "Default Parameter\n"); 4805 device_printf(sc->dev, "-----------------\n"); 4806 hdac_dump_audio_formats(sc, 4807 devinfo->function.audio.supp_stream_formats, 4808 devinfo->function.audio.supp_pcm_size_rate); 4809 device_printf(sc->dev, " IN amp: 0x%08x\n", 4810 devinfo->function.audio.inamp_cap); 4811 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4812 devinfo->function.audio.outamp_cap); 4813 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4814 w = hdac_widget_get(devinfo, i); 4815 if (w == NULL) { 4816 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4817 continue; 4818 } 4819 device_printf(sc->dev, "\n"); 4820 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4821 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4822 "DIGITAL" : "ANALOG", 4823 (w->enable == 0) ? " [DISABLED]" : ""); 4824 device_printf(sc->dev, " name: %s\n", w->name); 4825 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4826 w->param.widget_cap); 4827 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4828 w->pflags); 4829 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4830 w->ctlflags); 4831 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4832 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4833 hdac_dump_audio_formats(sc, 4834 w->param.supp_stream_formats, 4835 w->param.supp_pcm_size_rate); 4836 } else if (w->type == 4837 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4838 hdac_dump_pin(sc, w); 4839 if (w->param.eapdbtl != HDAC_INVALID) 4840 device_printf(sc->dev, " EAPD: 0x%08x\n", 4841 w->param.eapdbtl); 4842 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4843 w->param.outamp_cap != 0) 4844 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4845 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4846 w->param.inamp_cap != 0) 4847 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4848 device_printf(sc->dev, " connections: %d\n", w->nconns); 4849 for (j = 0; j < w->nconns; j++) { 4850 cw = hdac_widget_get(devinfo, w->conns[j]); 4851 device_printf(sc->dev, " |\n"); 4852 device_printf(sc->dev, " + <- nid=%d [%s]", 4853 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4854 if (cw == NULL) 4855 printf(" [UNKNOWN]"); 4856 else if (cw->enable == 0) 4857 printf(" [DISABLED]"); 4858 if (w->nconns > 1 && w->selconn == j && w->type != 4859 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4860 printf(" (selected)"); 4861 printf("\n"); 4862 } 4863 } 4864 4865} 4866 4867static int 4868hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4869{ 4870 struct hdac_widget *w, *cw; 4871 struct hdac_softc *sc = devinfo->codec->sc; 4872 int i; 4873 4874 if (depth > HDA_PARSE_MAXDEPTH) 4875 return (0); 4876 4877 w = hdac_widget_get(devinfo, nid); 4878 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4879 return (0); 4880 4881 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4882 device_printf(sc->dev, "\n"); 4883 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4884 device_printf(sc->dev, " ^\n"); 4885 device_printf(sc->dev, " |\n"); 4886 device_printf(sc->dev, " +-----<------+\n"); 4887 } else { 4888 device_printf(sc->dev, " ^\n"); 4889 device_printf(sc->dev, " |\n"); 4890 device_printf(sc->dev, " "); 4891 printf(" nid=%d [%s]\n", w->nid, w->name); 4892 } 4893 4894 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4895 return (1); 4896 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4897 for (i = 0; i < w->nconns; i++) { 4898 cw = hdac_widget_get(devinfo, w->conns[i]); 4899 if (cw == NULL || cw->enable == 0 || cw->type == 4900 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4901 continue; 4902 if (hdac_dump_dac_internal(devinfo, cw->nid, 4903 depth + 1) != 0) 4904 return (1); 4905 } 4906 } else if ((w->type == 4907 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4908 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4909 w->selconn > -1 && w->selconn < w->nconns) { 4910 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4911 depth + 1) != 0) 4912 return (1); 4913 } 4914 4915 return (0); 4916} 4917 4918static void 4919hdac_dump_dac(struct hdac_devinfo *devinfo) 4920{ 4921 struct hdac_widget *w; 4922 struct hdac_softc *sc = devinfo->codec->sc; 4923 int i, printed = 0; 4924 4925 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4926 w = hdac_widget_get(devinfo, i); 4927 if (w == NULL || w->enable == 0) 4928 continue; 4929 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4930 !(w->pflags & HDA_DAC_PATH)) 4931 continue; 4932 if (printed == 0) { 4933 printed = 1; 4934 device_printf(sc->dev, "\n"); 4935 device_printf(sc->dev, "Playback path:\n"); 4936 } 4937 hdac_dump_dac_internal(devinfo, w->nid, 0); 4938 } 4939} 4940 4941static void 4942hdac_dump_adc(struct hdac_devinfo *devinfo) 4943{ 4944 struct hdac_widget *w, *cw; 4945 struct hdac_softc *sc = devinfo->codec->sc; 4946 int i, j; 4947 int printed = 0; 4948 char ossdevs[256]; 4949 4950 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4951 w = hdac_widget_get(devinfo, i); 4952 if (w == NULL || w->enable == 0) 4953 continue; 4954 if (!(w->pflags & HDA_ADC_RECSEL)) 4955 continue; 4956 if (printed == 0) { 4957 printed = 1; 4958 device_printf(sc->dev, "\n"); 4959 device_printf(sc->dev, "Recording sources:\n"); 4960 } 4961 device_printf(sc->dev, "\n"); 4962 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4963 for (j = 0; j < w->nconns; j++) { 4964 cw = hdac_widget_get(devinfo, w->conns[j]); 4965 if (cw == NULL || cw->enable == 0) 4966 continue; 4967 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4968 ossdevs, sizeof(ossdevs)); 4969 device_printf(sc->dev, " |\n"); 4970 device_printf(sc->dev, " + <- nid=%d [%s]", 4971 cw->nid, cw->name); 4972 if (strlen(ossdevs) > 0) { 4973 printf(" [recsrc: %s]", ossdevs); 4974 } 4975 printf("\n"); 4976 } 4977 } 4978} 4979 4980static void 4981hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4982{ 4983 nid_t *nids; 4984 4985 if (pcnt > 0) { 4986 device_printf(sc->dev, "\n"); 4987 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4988 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4989 sc->play.supp_pcm_size_rate); 4990 device_printf(sc->dev, " DAC:"); 4991 for (nids = sc->play.io; *nids != -1; nids++) 4992 printf(" %d", *nids); 4993 printf("\n"); 4994 } 4995 4996 if (rcnt > 0) { 4997 device_printf(sc->dev, "\n"); 4998 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4999 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5000 sc->rec.supp_pcm_size_rate); 5001 device_printf(sc->dev, " ADC:"); 5002 for (nids = sc->rec.io; *nids != -1; nids++) 5003 printf(" %d", *nids); 5004 printf("\n"); 5005 } 5006} 5007 5008static void 5009hdac_release_resources(struct hdac_softc *sc) 5010{ 5011 struct hdac_devinfo *devinfo = NULL; 5012 device_t *devlist = NULL; 5013 int i, devcount; 5014 5015 if (sc == NULL) 5016 return; 5017 5018 hdac_lock(sc); 5019 if (sc->polling != 0) 5020 callout_stop(&sc->poll_hdac); 5021 hdac_reset(sc); 5022 hdac_unlock(sc); 5023 snd_mtxfree(sc->lock); 5024 5025 device_get_children(sc->dev, &devlist, &devcount); 5026 for (i = 0; devlist != NULL && i < devcount; i++) { 5027 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5028 if (devinfo == NULL) 5029 continue; 5030 if (devinfo->widget != NULL) 5031 free(devinfo->widget, M_HDAC); 5032 if (devinfo->node_type == 5033 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5034 devinfo->function.audio.ctl != NULL) 5035 free(devinfo->function.audio.ctl, M_HDAC); 5036 free(devinfo, M_HDAC); 5037 device_delete_child(sc->dev, devlist[i]); 5038 } 5039 if (devlist != NULL) 5040 free(devlist, M_TEMP); 5041 5042 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5043 if (sc->codecs[i] != NULL) 5044 free(sc->codecs[i], M_HDAC); 5045 sc->codecs[i] = NULL; 5046 } 5047 5048 hdac_dma_free(&sc->rirb_dma); 5049 hdac_dma_free(&sc->corb_dma); 5050 if (sc->play.blkcnt > 0) 5051 hdac_dma_free(&sc->play.bdl_dma); 5052 if (sc->rec.blkcnt > 0) 5053 hdac_dma_free(&sc->rec.bdl_dma); 5054 hdac_irq_free(sc); 5055 hdac_mem_free(sc); 5056 free(sc, M_DEVBUF); 5057 5058} 5059 5060/* This function surely going to make its way into upper level someday. */ 5061static void 5062hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5063{ 5064 const char *res = NULL; 5065 int i = 0, j, k, len, inv; 5066 5067 if (on != NULL) 5068 *on = 0; 5069 if (off != NULL) 5070 *off = 0; 5071 if (sc == NULL) 5072 return; 5073 if (resource_string_value(device_get_name(sc->dev), 5074 device_get_unit(sc->dev), "config", &res) != 0) 5075 return; 5076 if (!(res != NULL && strlen(res) > 0)) 5077 return; 5078 HDA_BOOTVERBOSE( 5079 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5080 ); 5081 for (;;) { 5082 while (res[i] != '\0' && 5083 (res[i] == ',' || isspace(res[i]) != 0)) 5084 i++; 5085 if (res[i] == '\0') { 5086 HDA_BOOTVERBOSE( 5087 printf("\n"); 5088 ); 5089 return; 5090 } 5091 j = i; 5092 while (res[j] != '\0' && 5093 !(res[j] == ',' || isspace(res[j]) != 0)) 5094 j++; 5095 len = j - i; 5096 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5097 inv = 2; 5098 else 5099 inv = 0; 5100 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5101 if (strncmp(res + i + inv, 5102 hdac_quirks_tab[k].key, len - inv) != 0) 5103 continue; 5104 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5105 break; 5106 HDA_BOOTVERBOSE( 5107 printf(" %s%s", (inv != 0) ? "no" : "", 5108 hdac_quirks_tab[k].key); 5109 ); 5110 if (inv == 0 && on != NULL) 5111 *on |= hdac_quirks_tab[k].value; 5112 else if (inv != 0 && off != NULL) 5113 *off |= hdac_quirks_tab[k].value; 5114 break; 5115 } 5116 i = j; 5117 } 5118} 5119 5120#ifdef SND_DYNSYSCTL 5121static int 5122sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5123{ 5124 struct hdac_softc *sc; 5125 struct hdac_devinfo *devinfo; 5126 device_t dev; 5127 uint32_t ctl; 5128 int err, val; 5129 5130 dev = oidp->oid_arg1; 5131 devinfo = pcm_getdevinfo(dev); 5132 if (devinfo == NULL || devinfo->codec == NULL || 5133 devinfo->codec->sc == NULL) 5134 return (EINVAL); 5135 sc = devinfo->codec->sc; 5136 hdac_lock(sc); 5137 val = sc->polling; 5138 hdac_unlock(sc); 5139 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5140 5141 if (err || req->newptr == NULL) 5142 return (err); 5143 if (val < 0 || val > 1) 5144 return (EINVAL); 5145 5146 hdac_lock(sc); 5147 if (val != sc->polling) { 5148 if (hda_chan_active(sc) != 0) 5149 err = EBUSY; 5150 else if (val == 0) { 5151 callout_stop(&sc->poll_hdac); 5152 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5153 sc->rirb_size / 2); 5154 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5155 ctl |= HDAC_RIRBCTL_RINTCTL; 5156 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5157 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5158 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5159 sc->polling = 0; 5160 DELAY(1000); 5161 } else { 5162 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5163 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5164 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5165 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5166 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5167 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5168 sc); 5169 sc->polling = 1; 5170 DELAY(1000); 5171 } 5172 } 5173 hdac_unlock(sc); 5174 5175 return (err); 5176} 5177#endif 5178 5179static void 5180hdac_attach2(void *arg) 5181{ 5182 struct hdac_softc *sc; 5183 struct hdac_widget *w; 5184 struct hdac_audio_ctl *ctl; 5185 uint32_t quirks_on, quirks_off; 5186 int pcnt, rcnt; 5187 int i; 5188 char status[SND_STATUSLEN]; 5189 device_t *devlist = NULL; 5190 int devcount; 5191 struct hdac_devinfo *devinfo = NULL; 5192 5193 sc = (struct hdac_softc *)arg; 5194 5195 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5196 5197 HDA_BOOTVERBOSE( 5198 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5199 quirks_on, quirks_off); 5200 ); 5201 5202 hdac_lock(sc); 5203 5204 /* Remove ourselves from the config hooks */ 5205 if (sc->intrhook.ich_func != NULL) { 5206 config_intrhook_disestablish(&sc->intrhook); 5207 sc->intrhook.ich_func = NULL; 5208 } 5209 5210 /* Start the corb and rirb engines */ 5211 HDA_BOOTVERBOSE( 5212 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5213 ); 5214 hdac_corb_start(sc); 5215 HDA_BOOTVERBOSE( 5216 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5217 ); 5218 hdac_rirb_start(sc); 5219 5220 HDA_BOOTVERBOSE( 5221 device_printf(sc->dev, 5222 "HDA_DEBUG: Enabling controller interrupt...\n"); 5223 ); 5224 if (sc->polling == 0) 5225 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5226 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5227 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5228 HDAC_GCTL_UNSOL); 5229 5230 DELAY(1000); 5231 5232 HDA_BOOTVERBOSE( 5233 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5234 ); 5235 hdac_scan_codecs(sc); 5236 5237 device_get_children(sc->dev, &devlist, &devcount); 5238 for (i = 0; devlist != NULL && i < devcount; i++) { 5239 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5240 if (devinfo != NULL && devinfo->node_type == 5241 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5242 break; 5243 } else 5244 devinfo = NULL; 5245 } 5246 if (devlist != NULL) 5247 free(devlist, M_TEMP); 5248 5249 if (devinfo == NULL) { 5250 hdac_unlock(sc); 5251 device_printf(sc->dev, "Audio Function Group not found!\n"); 5252 hdac_release_resources(sc); 5253 return; 5254 } 5255 5256 HDA_BOOTVERBOSE( 5257 device_printf(sc->dev, 5258 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5259 devinfo->nid, devinfo->codec->cad); 5260 ); 5261 hdac_audio_parse(devinfo); 5262 HDA_BOOTVERBOSE( 5263 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5264 ); 5265 hdac_audio_ctl_parse(devinfo); 5266 HDA_BOOTVERBOSE( 5267 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5268 ); 5269 hdac_vendor_patch_parse(devinfo); 5270 if (quirks_on != 0) 5271 devinfo->function.audio.quirks |= quirks_on; 5272 if (quirks_off != 0) 5273 devinfo->function.audio.quirks &= ~quirks_off; 5274 5275 /* XXX Disable all DIGITAL path. */ 5276 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5277 w = hdac_widget_get(devinfo, i); 5278 if (w == NULL) 5279 continue; 5280 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5281 w->enable = 0; 5282 continue; 5283 } 5284 /* XXX Disable useless pin ? */ 5285 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5286 (w->wclass.pin.config & 5287 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5288 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5289 w->enable = 0; 5290 } 5291 i = 0; 5292 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5293 if (ctl->widget == NULL) 5294 continue; 5295 w = ctl->widget; 5296 if (w->enable == 0) 5297 ctl->enable = 0; 5298 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5299 ctl->enable = 0; 5300 w = ctl->childwidget; 5301 if (w == NULL) 5302 continue; 5303 if (w->enable == 0 || 5304 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5305 ctl->enable = 0; 5306 } 5307 5308 HDA_BOOTVERBOSE( 5309 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5310 ); 5311 hdac_audio_build_tree(devinfo); 5312 5313 HDA_BOOTVERBOSE( 5314 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5315 ); 5316 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5317 HDA_BOOTVERBOSE( 5318 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5319 ); 5320 hdac_audio_ctl_commit(devinfo); 5321 5322 HDA_BOOTVERBOSE( 5323 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5324 ); 5325 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5326 HDA_BOOTVERBOSE( 5327 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5328 ); 5329 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5330 5331 hdac_unlock(sc); 5332 HDA_BOOTVERBOSE( 5333 device_printf(sc->dev, 5334 "HDA_DEBUG: OSS mixer initialization...\n"); 5335 ); 5336 5337 /* 5338 * There is no point of return after this. If the driver failed, 5339 * so be it. Let the detach procedure do all the cleanup. 5340 */ 5341 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5342 device_printf(sc->dev, "Can't register mixer\n"); 5343 5344 if (pcnt > 0) 5345 pcnt = 1; 5346 if (rcnt > 0) 5347 rcnt = 1; 5348 5349 HDA_BOOTVERBOSE( 5350 device_printf(sc->dev, 5351 "HDA_DEBUG: Registering PCM channels...\n"); 5352 ); 5353 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5354 device_printf(sc->dev, "Can't register PCM\n"); 5355 5356 sc->registered++; 5357 5358 for (i = 0; i < pcnt; i++) 5359 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5360 for (i = 0; i < rcnt; i++) 5361 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5362 5363#ifdef SND_DYNSYSCTL 5364 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5365 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5366 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5367 sysctl_hdac_polling, "I", "Enable polling mode"); 5368#endif 5369 5370 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5371 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5372 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5373 pcm_setstatus(sc->dev, status); 5374 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5375 HDA_BOOTVERBOSE( 5376 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5377 hdac_codec_id(devinfo)); 5378 ); 5379 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5380 HDA_DRV_TEST_REV); 5381 5382 HDA_BOOTVERBOSE( 5383 if (devinfo->function.audio.quirks != 0) { 5384 device_printf(sc->dev, "\n"); 5385 device_printf(sc->dev, "HDA config/quirks:"); 5386 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5387 if (devinfo->function.audio.quirks & 5388 hdac_quirks_tab[i].value) 5389 printf(" %s", hdac_quirks_tab[i].key); 5390 } 5391 printf("\n"); 5392 } 5393 device_printf(sc->dev, "\n"); 5394 device_printf(sc->dev, "+-------------------+\n"); 5395 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5396 device_printf(sc->dev, "+-------------------+\n"); 5397 hdac_dump_nodes(devinfo); 5398 device_printf(sc->dev, "\n"); 5399 device_printf(sc->dev, "+------------------------+\n"); 5400 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5401 device_printf(sc->dev, "+------------------------+\n"); 5402 device_printf(sc->dev, "\n"); 5403 i = 0; 5404 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5405 device_printf(sc->dev, "%3d: nid=%d", i, 5406 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5407 if (ctl->childwidget != NULL) 5408 printf(" cnid=%d", ctl->childwidget->nid); 5409 printf(" dir=0x%x index=%d " 5410 "ossmask=0x%08x ossdev=%d%s\n", 5411 ctl->dir, ctl->index, 5412 ctl->ossmask, ctl->ossdev, 5413 (ctl->enable == 0) ? " [DISABLED]" : ""); 5414 } 5415 device_printf(sc->dev, "\n"); 5416 device_printf(sc->dev, "+-----------------------------------+\n"); 5417 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5418 device_printf(sc->dev, "+-----------------------------------+\n"); 5419 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5420 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5421 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5422 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5423 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5424 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5425 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5426 hdac_dump_ctls(devinfo, NULL, 0); 5427 hdac_dump_dac(devinfo); 5428 hdac_dump_adc(devinfo); 5429 device_printf(sc->dev, "\n"); 5430 device_printf(sc->dev, "+--------------------------------------+\n"); 5431 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5432 device_printf(sc->dev, "+--------------------------------------+\n"); 5433 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5434 ); 5435 5436 if (sc->polling != 0) { 5437 hdac_lock(sc); 5438 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5439 hdac_unlock(sc); 5440 } 5441} 5442 5443/**************************************************************************** 5444 * int hdac_detach(device_t) 5445 * 5446 * Detach and free up resources utilized by the hdac device. 5447 ****************************************************************************/ 5448static int 5449hdac_detach(device_t dev) 5450{ 5451 struct hdac_softc *sc = NULL; 5452 struct hdac_devinfo *devinfo = NULL; 5453 int err; 5454 5455 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5456 if (devinfo != NULL && devinfo->codec != NULL) 5457 sc = devinfo->codec->sc; 5458 if (sc == NULL) 5459 return (0); 5460 5461 if (sc->registered > 0) { 5462 err = pcm_unregister(dev); 5463 if (err != 0) 5464 return (err); 5465 } 5466 5467 hdac_release_resources(sc); 5468 5469 return (0); 5470} 5471 5472static device_method_t hdac_methods[] = { 5473 /* device interface */ 5474 DEVMETHOD(device_probe, hdac_probe), 5475 DEVMETHOD(device_attach, hdac_attach), 5476 DEVMETHOD(device_detach, hdac_detach), 5477 { 0, 0 } 5478}; 5479 5480static driver_t hdac_driver = { 5481 "pcm", 5482 hdac_methods, 5483 PCM_SOFTC_SIZE, 5484}; 5485 5486DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5487MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5488MODULE_VERSION(snd_hda, 1); 5489