hdac.c revision 166796
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20070128_0039" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 166796 2007-02-16 17:43:29Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* Intel */ 167#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168 169/* HP/Compaq */ 170#define HP_VENDORID 0x103c 171#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 176#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 177/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 178#define HP_NX6325_SUBVENDORX 0x103c30b0 179 180/* Dell */ 181#define DELL_VENDORID 0x1028 182#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 183#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 184#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 185 186/* Clevo */ 187#define CLEVO_VENDORID 0x1558 188#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 189#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 190 191/* Acer */ 192#define ACER_VENDORID 0x1025 193#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 194#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 195 196/* Asus */ 197#define ASUS_VENDORID 0x1043 198#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 199#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 200#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 201#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 202#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 203#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 204 205/* IBM / Lenovo */ 206#define IBM_VENDORID 0x1014 207#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 208#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 209 210/* Lenovo */ 211#define LENOVO_VENDORID 0x17aa 212#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 213#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 214 215/* Samsung */ 216#define SAMSUNG_VENDORID 0x144d 217#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 218#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 219 220/* Medion ? */ 221#define MEDION_VENDORID 0x161f 222#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 223#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 224 225/* 226 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 227 * instead of their own, which is beyond my comprehension 228 * (see HDA_CODEC_STAC9221 below). 229 */ 230#define APPLE_INTEL_MAC 0x76808384 231 232/* LG Electronics */ 233#define LG_VENDORID 0x1854 234#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 235#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 236 237/* Fujitsu Siemens */ 238#define FS_VENDORID 0x1734 239#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 240#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 241 242/* Toshiba */ 243#define TOSHIBA_VENDORID 0x1179 244#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 245#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 246 247/* Micro-Star International (MSI) */ 248#define MSI_VENDORID 0x1462 249#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 250#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 251 252/* Misc constants.. */ 253#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 254#define HDA_AMP_MUTE_NONE (0) 255#define HDA_AMP_MUTE_LEFT (1 << 0) 256#define HDA_AMP_MUTE_RIGHT (1 << 1) 257#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 258 259#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 260#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 261 262#define HDA_DAC_PATH (1 << 0) 263#define HDA_ADC_PATH (1 << 1) 264#define HDA_ADC_RECSEL (1 << 2) 265 266#define HDA_CTL_OUT (1 << 0) 267#define HDA_CTL_IN (1 << 1) 268#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 269 270#define HDA_GPIO_MAX 15 271/* 0 - 14 = GPIO */ 272#define HDA_QUIRK_GPIO0 (1 << 0) 273#define HDA_QUIRK_GPIO1 (1 << 1) 274#define HDA_QUIRK_GPIO2 (1 << 2) 275#define HDA_QUIRK_GPIOFLUSH (1 << 15) 276#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 277#define HDA_QUIRK_FIXEDRATE (1 << 17) 278#define HDA_QUIRK_FORCESTEREO (1 << 18) 279#define HDA_QUIRK_EAPDINV (1 << 19) 280#define HDA_QUIRK_VREF (1 << 20) 281 282static const struct { 283 char *key; 284 uint32_t value; 285} hdac_quirks_tab[] = { 286 { "gpio0", HDA_QUIRK_GPIO0 }, 287 { "gpio1", HDA_QUIRK_GPIO1 }, 288 { "gpio2", HDA_QUIRK_GPIO2 }, 289 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 290 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 291 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 292 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 293 { "eapdinv", HDA_QUIRK_EAPDINV }, 294 { "vref", HDA_QUIRK_VREF }, 295}; 296#define HDAC_QUIRKS_TAB_LEN \ 297 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 298 299#define HDA_BDL_MIN 2 300#define HDA_BDL_MAX 256 301#define HDA_BDL_DEFAULT HDA_BDL_MIN 302 303#define HDA_BUFSZ_MIN 4096 304#define HDA_BUFSZ_MAX 65536 305#define HDA_BUFSZ_DEFAULT 16384 306 307#define HDA_PARSE_MAXDEPTH 10 308 309#define HDAC_UNSOLTAG_EVENT_HP 0x00 310 311MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 312 313enum { 314 HDA_PARSE_MIXER, 315 HDA_PARSE_DIRECT 316}; 317 318/* Default */ 319static uint32_t hdac_fmt[] = { 320 AFMT_STEREO | AFMT_S16_LE, 321 0 322}; 323 324static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 325 326static const struct { 327 uint32_t model; 328 char *desc; 329} hdac_devices[] = { 330 { HDA_INTEL_82801F, "Intel 82801F" }, 331 { HDA_INTEL_82801G, "Intel 82801G" }, 332 { HDA_INTEL_82801H, "Intel 82801H" }, 333 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 334 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 335 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 336 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 337 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 338 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 339 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 340 { HDA_ATI_SB450, "ATI SB450" }, 341 { HDA_ATI_SB600, "ATI SB600" }, 342 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 343 { HDA_SIS_966, "SiS 966" }, 344 /* Unknown */ 345 { HDA_INTEL_ALL, "Intel (Unknown)" }, 346 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 347 { HDA_ATI_ALL, "ATI (Unknown)" }, 348 { HDA_VIA_ALL, "VIA (Unknown)" }, 349 { HDA_SIS_ALL, "SiS (Unknown)" }, 350}; 351#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 352 353static const struct { 354 uint32_t rate; 355 int valid; 356 uint16_t base; 357 uint16_t mul; 358 uint16_t div; 359} hda_rate_tab[] = { 360 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 361 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 362 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 363 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 364 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 365 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 366 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 367 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 368 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 369 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 370 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 371 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 372 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 373 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 374 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 375 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 376 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 377 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 378 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 379 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 380 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 381 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 382 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 383 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 384 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 385 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 386 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 387 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 388 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 389 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 390 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 391 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 392 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 393 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 394 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 395}; 396#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 397 398/* All codecs you can eat... */ 399#define HDA_CODEC_CONSTRUCT(vendor, id) \ 400 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 401 402/* Realtek */ 403#define REALTEK_VENDORID 0x10ec 404#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 405#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 406#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 407#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 408#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 409#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 410#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 411 412/* Analog Device */ 413#define ANALOGDEVICE_VENDORID 0x11d4 414#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 415#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 416#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 417#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 418 419/* CMedia */ 420#define CMEDIA_VENDORID 0x434d 421#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 422#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 423 424/* Sigmatel */ 425#define SIGMATEL_VENDORID 0x8384 426#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 427#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 428#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 429#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 430#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 431#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 432#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 433 434/* 435 * Conexant 436 * 437 * Ok, the truth is, I don't have any idea at all whether 438 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 439 * place that tell me it is "Venice" is from its Windows driver INF. 440 * 441 * Venice - CX????? 442 * Waikiki - CX20551-22 443 */ 444#define CONEXANT_VENDORID 0x14f1 445#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 446#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 447#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 448 449 450/* Codecs */ 451static const struct { 452 uint32_t id; 453 char *name; 454} hdac_codecs[] = { 455 { HDA_CODEC_ALC260, "Realtek ALC260" }, 456 { HDA_CODEC_ALC861, "Realtek ALC861" }, 457 { HDA_CODEC_ALC880, "Realtek ALC880" }, 458 { HDA_CODEC_ALC882, "Realtek ALC882" }, 459 { HDA_CODEC_ALC883, "Realtek ALC883" }, 460 { HDA_CODEC_ALC888, "Realtek ALC888" }, 461 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 462 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 463 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 464 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 465 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 466 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 467 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 468 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 469 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 470 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 471 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 472 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 473 /* Unknown codec */ 474 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 475 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 476 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 477 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 478 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 479}; 480#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 481 482enum { 483 HDAC_HP_SWITCH_CTL, 484 HDAC_HP_SWITCH_CTRL 485}; 486 487static const struct { 488 uint32_t model; 489 uint32_t id; 490 int type; 491 int inverted; 492 nid_t hpnid; 493 nid_t spkrnid[8]; 494 nid_t eapdnid; 495} hdac_hp_switch[] = { 496 /* Specific OEM models */ 497 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 498 17, { 16, -1 }, 16 }, 499 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 500 6, { 5, -1 }, 5 }, 501 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 502 6, { 5, -1 }, 5 }, 503 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 504 6, { 5, -1 }, 5 }, 505 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 506 6, { 5, -1 }, -1 }, 507 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 508 13, { 14, -1 }, -1 }, 509 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 510 13, { 14, -1 }, -1 }, 511 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 512 10, { 13, -1 }, -1 }, 513 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 514 26, { 27, -1 }, -1 }, 515 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 516 27, { 20, -1 }, -1 }, 517 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 518 20, { 21, -1 }, -1 }, 519 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 520 20, { 27, -1 }, -1 }, 521 /* 522 * All models that at least come from the same vendor with 523 * simmilar codec. 524 */ 525 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 526 17, { 16, -1 }, 16 }, 527 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 528 6, { 5, -1 }, 5 }, 529 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 530 6, { 5, -1 }, -1 }, 531 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 532 13, { 14, -1 }, -1 }, 533 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 534 26, { 27, -1 }, -1 }, 535#if 0 536 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 537 20, { 21, -1 }, -1 }, 538#endif 539}; 540#define HDAC_HP_SWITCH_LEN \ 541 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 542 543static const struct { 544 uint32_t model; 545 uint32_t id; 546 nid_t eapdnid; 547 int hp_switch; 548} hdac_eapd_switch[] = { 549 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 550 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 551 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 552}; 553#define HDAC_EAPD_SWITCH_LEN \ 554 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 555 556/**************************************************************************** 557 * Function prototypes 558 ****************************************************************************/ 559static void hdac_intr_handler(void *); 560static int hdac_reset(struct hdac_softc *); 561static int hdac_get_capabilities(struct hdac_softc *); 562static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 563static int hdac_dma_alloc(struct hdac_softc *, 564 struct hdac_dma *, bus_size_t); 565static void hdac_dma_free(struct hdac_dma *); 566static int hdac_mem_alloc(struct hdac_softc *); 567static void hdac_mem_free(struct hdac_softc *); 568static int hdac_irq_alloc(struct hdac_softc *); 569static void hdac_irq_free(struct hdac_softc *); 570static void hdac_corb_init(struct hdac_softc *); 571static void hdac_rirb_init(struct hdac_softc *); 572static void hdac_corb_start(struct hdac_softc *); 573static void hdac_rirb_start(struct hdac_softc *); 574static void hdac_scan_codecs(struct hdac_softc *); 575static int hdac_probe_codec(struct hdac_codec *); 576static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 577static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 578 579static void hdac_attach2(void *); 580 581static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 582 uint32_t, int); 583static void hdac_command_send_internal(struct hdac_softc *, 584 struct hdac_command_list *, int); 585 586static int hdac_probe(device_t); 587static int hdac_attach(device_t); 588static int hdac_detach(device_t); 589static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 590static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 591 uint32_t, int, int); 592static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 593 nid_t, int, int); 594static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 595 nid_t, nid_t, int, int, int, int, int, int); 596static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 597static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 598 599static int hdac_rirb_flush(struct hdac_softc *sc); 600static int hdac_unsolq_flush(struct hdac_softc *sc); 601 602#define hdac_command(a1, a2, a3) \ 603 hdac_command_sendone_internal(a1, a2, a3) 604 605#define hdac_codec_id(d) \ 606 ((uint32_t)((d == NULL) ? 0x00000000 : \ 607 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 608 ((uint32_t)(d)->device_id & 0x0000ffff)))) 609 610static char * 611hdac_codec_name(struct hdac_devinfo *devinfo) 612{ 613 uint32_t id; 614 int i; 615 616 id = hdac_codec_id(devinfo); 617 618 for (i = 0; i < HDAC_CODECS_LEN; i++) { 619 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 620 return (hdac_codecs[i].name); 621 } 622 623 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 624} 625 626static char * 627hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 628{ 629 static char *ossname[] = SOUND_DEVICE_NAMES; 630 static char *unknown = "???"; 631 int i; 632 633 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 634 if (devmask & (1 << i)) 635 return (ossname[i]); 636 } 637 return (unknown); 638} 639 640static void 641hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 642{ 643 static char *ossname[] = SOUND_DEVICE_NAMES; 644 int i, first = 1; 645 646 bzero(buf, len); 647 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 648 if (mask & (1 << i)) { 649 if (first == 0) 650 strlcat(buf, ", ", len); 651 strlcat(buf, ossname[i], len); 652 first = 0; 653 } 654 } 655} 656 657static struct hdac_audio_ctl * 658hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 659{ 660 if (devinfo == NULL || 661 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 662 index == NULL || devinfo->function.audio.ctl == NULL || 663 devinfo->function.audio.ctlcnt < 1 || 664 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 665 return (NULL); 666 return (&devinfo->function.audio.ctl[(*index)++]); 667} 668 669static struct hdac_audio_ctl * 670hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 671 int index, int cnt) 672{ 673 struct hdac_audio_ctl *ctl, *retctl = NULL; 674 int i, at, atindex, found = 0; 675 676 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 677 return (NULL); 678 679 at = cnt; 680 if (at == 0) 681 at = 1; 682 else if (at < 0) 683 at = -1; 684 atindex = index; 685 if (atindex < 0) 686 atindex = -1; 687 688 i = 0; 689 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 690 if (ctl->enable == 0 || ctl->widget == NULL) 691 continue; 692 if (!(ctl->widget->nid == nid && (atindex == -1 || 693 ctl->index == atindex))) 694 continue; 695 found++; 696 if (found == cnt) 697 return (ctl); 698 retctl = ctl; 699 } 700 701 return ((at == -1) ? retctl : NULL); 702} 703 704static void 705hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 706{ 707 struct hdac_softc *sc; 708 struct hdac_widget *w; 709 struct hdac_audio_ctl *ctl; 710 uint32_t id, res; 711 int i = 0, j, forcemute; 712 nid_t cad; 713 714 if (devinfo == NULL || devinfo->codec == NULL || 715 devinfo->codec->sc == NULL) 716 return; 717 718 sc = devinfo->codec->sc; 719 cad = devinfo->codec->cad; 720 id = hdac_codec_id(devinfo); 721 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 722 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 723 sc->pci_subvendor) && 724 hdac_hp_switch[i].id == id) 725 break; 726 } 727 728 if (i >= HDAC_HP_SWITCH_LEN) 729 return; 730 731 forcemute = 0; 732 if (hdac_hp_switch[i].eapdnid != -1) { 733 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 734 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 735 forcemute = (w->param.eapdbtl & 736 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 737 } 738 739 res = hdac_command(sc, 740 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 741 HDA_BOOTVERBOSE( 742 device_printf(sc->dev, 743 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 744 hdac_hp_switch[i].hpnid, res); 745 ); 746 res >>= 31; 747 res ^= hdac_hp_switch[i].inverted; 748 749 switch (hdac_hp_switch[i].type) { 750 case HDAC_HP_SWITCH_CTL: 751 ctl = hdac_audio_ctl_amp_get(devinfo, 752 hdac_hp_switch[i].hpnid, 0, 1); 753 if (ctl != NULL) { 754 ctl->muted = (res != 0 && forcemute == 0) ? 755 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 756 hdac_audio_ctl_amp_set(ctl, 757 HDA_AMP_MUTE_DEFAULT, ctl->left, 758 ctl->right); 759 } 760 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 761 ctl = hdac_audio_ctl_amp_get(devinfo, 762 hdac_hp_switch[i].spkrnid[j], 0, 1); 763 if (ctl != NULL) { 764 ctl->muted = (res != 0 || forcemute == 1) ? 765 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 766 hdac_audio_ctl_amp_set(ctl, 767 HDA_AMP_MUTE_DEFAULT, ctl->left, 768 ctl->right); 769 } 770 } 771 break; 772 case HDAC_HP_SWITCH_CTRL: 773 if (res != 0) { 774 /* HP in */ 775 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 776 if (w != NULL && w->type == 777 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 778 if (forcemute == 0) 779 w->wclass.pin.ctrl |= 780 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 781 else 782 w->wclass.pin.ctrl &= 783 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 784 hdac_command(sc, 785 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 786 w->wclass.pin.ctrl), cad); 787 } 788 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 789 w = hdac_widget_get(devinfo, 790 hdac_hp_switch[i].spkrnid[j]); 791 if (w != NULL && w->type == 792 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 793 w->wclass.pin.ctrl &= 794 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 795 hdac_command(sc, 796 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 797 w->nid, 798 w->wclass.pin.ctrl), cad); 799 } 800 } 801 } else { 802 /* HP out */ 803 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 804 if (w != NULL && w->type == 805 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 806 w->wclass.pin.ctrl &= 807 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 808 hdac_command(sc, 809 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 810 w->wclass.pin.ctrl), cad); 811 } 812 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 813 w = hdac_widget_get(devinfo, 814 hdac_hp_switch[i].spkrnid[j]); 815 if (w != NULL && w->type == 816 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 817 if (forcemute == 0) 818 w->wclass.pin.ctrl |= 819 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 820 else 821 w->wclass.pin.ctrl &= 822 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 823 hdac_command(sc, 824 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 825 w->nid, 826 w->wclass.pin.ctrl), cad); 827 } 828 } 829 } 830 break; 831 default: 832 break; 833 } 834} 835 836static void 837hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 838{ 839 struct hdac_softc *sc; 840 struct hdac_devinfo *devinfo = NULL; 841 device_t *devlist = NULL; 842 int devcount, i; 843 844 if (codec == NULL || codec->sc == NULL) 845 return; 846 847 sc = codec->sc; 848 849 HDA_BOOTVERBOSE( 850 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 851 ); 852 853 device_get_children(sc->dev, &devlist, &devcount); 854 for (i = 0; devlist != NULL && i < devcount; i++) { 855 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 856 if (devinfo != NULL && devinfo->node_type == 857 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 858 devinfo->codec != NULL && 859 devinfo->codec->cad == codec->cad) { 860 break; 861 } else 862 devinfo = NULL; 863 } 864 if (devlist != NULL) 865 free(devlist, M_TEMP); 866 867 if (devinfo == NULL) 868 return; 869 870 switch (tag) { 871 case HDAC_UNSOLTAG_EVENT_HP: 872 hdac_hp_switch_handler(devinfo); 873 break; 874 default: 875 break; 876 } 877} 878 879static int 880hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 881{ 882 /* XXX to be removed */ 883#ifdef HDAC_INTR_EXTRA 884 uint32_t res; 885#endif 886 887 if (ch->blkcnt == 0) 888 return (0); 889 890 /* XXX to be removed */ 891#ifdef HDAC_INTR_EXTRA 892 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 893#endif 894 895 /* XXX to be removed */ 896#ifdef HDAC_INTR_EXTRA 897 HDA_BOOTVERBOSE( 898 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 899 device_printf(sc->dev, 900 "PCMDIR_%s intr triggered beyond stream boundary:" 901 "%08x\n", 902 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 903 ); 904#endif 905 906 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 907 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 908 909 /* XXX to be removed */ 910#ifdef HDAC_INTR_EXTRA 911 if (res & HDAC_SDSTS_BCIS) { 912#endif 913 return (1); 914 /* XXX to be removed */ 915#ifdef HDAC_INTR_EXTRA 916 } 917#endif 918 919 return (0); 920} 921 922/**************************************************************************** 923 * void hdac_intr_handler(void *) 924 * 925 * Interrupt handler. Processes interrupts received from the hdac. 926 ****************************************************************************/ 927static void 928hdac_intr_handler(void *context) 929{ 930 struct hdac_softc *sc; 931 uint32_t intsts; 932 uint8_t rirbsts; 933 struct hdac_rirb *rirb_base; 934 uint32_t trigger = 0; 935 936 sc = (struct hdac_softc *)context; 937 938 hdac_lock(sc); 939 if (sc->polling != 0) { 940 hdac_unlock(sc); 941 return; 942 } 943 /* Do we have anything to do? */ 944 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 945 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 946 hdac_unlock(sc); 947 return; 948 } 949 950 /* Was this a controller interrupt? */ 951 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 952 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 953 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 954 /* Get as many responses that we can */ 955 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 956 HDAC_WRITE_1(&sc->mem, 957 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 958 hdac_rirb_flush(sc); 959 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 960 } 961 /* XXX to be removed */ 962 /* Clear interrupt and exit */ 963#ifdef HDAC_INTR_EXTRA 964 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 965#endif 966 } 967 968 hdac_unsolq_flush(sc); 969 970 if (intsts & HDAC_INTSTS_SIS_MASK) { 971 if ((intsts & (1 << sc->num_iss)) && 972 hdac_stream_intr(sc, &sc->play) != 0) 973 trigger |= 1; 974 if ((intsts & (1 << 0)) && 975 hdac_stream_intr(sc, &sc->rec) != 0) 976 trigger |= 2; 977 /* XXX to be removed */ 978#ifdef HDAC_INTR_EXTRA 979 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 980 HDAC_INTSTS_SIS_MASK); 981#endif 982 } 983 984 hdac_unlock(sc); 985 986 if (trigger & 1) 987 chn_intr(sc->play.c); 988 if (trigger & 2) 989 chn_intr(sc->rec.c); 990} 991 992/**************************************************************************** 993 * int hdac_reset(hdac_softc *) 994 * 995 * Reset the hdac to a quiescent and known state. 996 ****************************************************************************/ 997static int 998hdac_reset(struct hdac_softc *sc) 999{ 1000 uint32_t gctl; 1001 int count, i; 1002 1003 /* 1004 * Stop all Streams DMA engine 1005 */ 1006 for (i = 0; i < sc->num_iss; i++) 1007 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1008 for (i = 0; i < sc->num_oss; i++) 1009 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1010 for (i = 0; i < sc->num_bss; i++) 1011 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1012 1013 /* 1014 * Stop Control DMA engines 1015 */ 1016 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1017 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1018 1019 /* 1020 * Reset the controller. The reset must remain asserted for 1021 * a minimum of 100us. 1022 */ 1023 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1024 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1025 count = 10000; 1026 do { 1027 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1028 if (!(gctl & HDAC_GCTL_CRST)) 1029 break; 1030 DELAY(10); 1031 } while (--count); 1032 if (gctl & HDAC_GCTL_CRST) { 1033 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1034 return (ENXIO); 1035 } 1036 DELAY(100); 1037 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1038 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1039 count = 10000; 1040 do { 1041 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1042 if (gctl & HDAC_GCTL_CRST) 1043 break; 1044 DELAY(10); 1045 } while (--count); 1046 if (!(gctl & HDAC_GCTL_CRST)) { 1047 device_printf(sc->dev, "Device stuck in reset\n"); 1048 return (ENXIO); 1049 } 1050 1051 /* 1052 * Wait for codecs to finish their own reset sequence. The delay here 1053 * should be of 250us but for some reasons, on it's not enough on my 1054 * computer. Let's use twice as much as necessary to make sure that 1055 * it's reset properly. 1056 */ 1057 DELAY(1000); 1058 1059 return (0); 1060} 1061 1062 1063/**************************************************************************** 1064 * int hdac_get_capabilities(struct hdac_softc *); 1065 * 1066 * Retreive the general capabilities of the hdac; 1067 * Number of Input Streams 1068 * Number of Output Streams 1069 * Number of bidirectional Streams 1070 * 64bit ready 1071 * CORB and RIRB sizes 1072 ****************************************************************************/ 1073static int 1074hdac_get_capabilities(struct hdac_softc *sc) 1075{ 1076 uint16_t gcap; 1077 uint8_t corbsize, rirbsize; 1078 1079 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1080 sc->num_iss = HDAC_GCAP_ISS(gcap); 1081 sc->num_oss = HDAC_GCAP_OSS(gcap); 1082 sc->num_bss = HDAC_GCAP_BSS(gcap); 1083 1084 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1085 1086 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1087 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1088 HDAC_CORBSIZE_CORBSZCAP_256) 1089 sc->corb_size = 256; 1090 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1091 HDAC_CORBSIZE_CORBSZCAP_16) 1092 sc->corb_size = 16; 1093 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1094 HDAC_CORBSIZE_CORBSZCAP_2) 1095 sc->corb_size = 2; 1096 else { 1097 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1098 __func__, corbsize); 1099 return (ENXIO); 1100 } 1101 1102 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1103 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1104 HDAC_RIRBSIZE_RIRBSZCAP_256) 1105 sc->rirb_size = 256; 1106 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1107 HDAC_RIRBSIZE_RIRBSZCAP_16) 1108 sc->rirb_size = 16; 1109 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1110 HDAC_RIRBSIZE_RIRBSZCAP_2) 1111 sc->rirb_size = 2; 1112 else { 1113 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1114 __func__, rirbsize); 1115 return (ENXIO); 1116 } 1117 1118 return (0); 1119} 1120 1121 1122/**************************************************************************** 1123 * void hdac_dma_cb 1124 * 1125 * This function is called by bus_dmamap_load when the mapping has been 1126 * established. We just record the physical address of the mapping into 1127 * the struct hdac_dma passed in. 1128 ****************************************************************************/ 1129static void 1130hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1131{ 1132 struct hdac_dma *dma; 1133 1134 if (error == 0) { 1135 dma = (struct hdac_dma *)callback_arg; 1136 dma->dma_paddr = segs[0].ds_addr; 1137 } 1138} 1139 1140static void 1141hdac_dma_nocache(void *ptr) 1142{ 1143#if defined(__i386__) || defined(__amd64__) 1144 pt_entry_t *pte; 1145 vm_offset_t va; 1146 1147 va = (vm_offset_t)ptr; 1148 pte = vtopte(va); 1149 if (pte) { 1150 *pte |= PG_N; 1151 invltlb(); 1152 } 1153#endif 1154} 1155 1156/**************************************************************************** 1157 * int hdac_dma_alloc 1158 * 1159 * This function allocate and setup a dma region (struct hdac_dma). 1160 * It must be freed by a corresponding hdac_dma_free. 1161 ****************************************************************************/ 1162static int 1163hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1164{ 1165 int result; 1166 int lowaddr; 1167 1168 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1169 BUS_SPACE_MAXADDR_32BIT; 1170 bzero(dma, sizeof(*dma)); 1171 1172 /* 1173 * Create a DMA tag 1174 */ 1175 result = bus_dma_tag_create(NULL, /* parent */ 1176 HDAC_DMA_ALIGNMENT, /* alignment */ 1177 0, /* boundary */ 1178 lowaddr, /* lowaddr */ 1179 BUS_SPACE_MAXADDR, /* highaddr */ 1180 NULL, /* filtfunc */ 1181 NULL, /* fistfuncarg */ 1182 size, /* maxsize */ 1183 1, /* nsegments */ 1184 size, /* maxsegsz */ 1185 0, /* flags */ 1186 NULL, /* lockfunc */ 1187 NULL, /* lockfuncarg */ 1188 &dma->dma_tag); /* dmat */ 1189 if (result != 0) { 1190 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1191 __func__, result); 1192 goto fail; 1193 } 1194 1195 /* 1196 * Allocate DMA memory 1197 */ 1198 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1199 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1200 if (result != 0) { 1201 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1202 __func__, result); 1203 goto fail; 1204 } 1205 1206 /* 1207 * Map the memory 1208 */ 1209 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1210 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1211 BUS_DMA_NOWAIT); 1212 if (result != 0 || dma->dma_paddr == 0) { 1213 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1214 __func__, result); 1215 goto fail; 1216 } 1217 bzero((void *)dma->dma_vaddr, size); 1218 hdac_dma_nocache(dma->dma_vaddr); 1219 1220 return (0); 1221fail: 1222 if (dma->dma_map != NULL) 1223 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1224 if (dma->dma_tag != NULL) 1225 bus_dma_tag_destroy(dma->dma_tag); 1226 return (result); 1227} 1228 1229 1230/**************************************************************************** 1231 * void hdac_dma_free(struct hdac_dma *) 1232 * 1233 * Free a struct dhac_dma that has been previously allocated via the 1234 * hdac_dma_alloc function. 1235 ****************************************************************************/ 1236static void 1237hdac_dma_free(struct hdac_dma *dma) 1238{ 1239 if (dma->dma_tag != NULL) { 1240 /* Flush caches */ 1241 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1242 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1243 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1244 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1245 bus_dma_tag_destroy(dma->dma_tag); 1246 } 1247} 1248 1249/**************************************************************************** 1250 * int hdac_mem_alloc(struct hdac_softc *) 1251 * 1252 * Allocate all the bus resources necessary to speak with the physical 1253 * controller. 1254 ****************************************************************************/ 1255static int 1256hdac_mem_alloc(struct hdac_softc *sc) 1257{ 1258 struct hdac_mem *mem; 1259 1260 mem = &sc->mem; 1261 mem->mem_rid = PCIR_BAR(0); 1262 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1263 &mem->mem_rid, RF_ACTIVE); 1264 if (mem->mem_res == NULL) { 1265 device_printf(sc->dev, 1266 "%s: Unable to allocate memory resource\n", __func__); 1267 return (ENOMEM); 1268 } 1269 mem->mem_tag = rman_get_bustag(mem->mem_res); 1270 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1271 1272 return (0); 1273} 1274 1275/**************************************************************************** 1276 * void hdac_mem_free(struct hdac_softc *) 1277 * 1278 * Free up resources previously allocated by hdac_mem_alloc. 1279 ****************************************************************************/ 1280static void 1281hdac_mem_free(struct hdac_softc *sc) 1282{ 1283 struct hdac_mem *mem; 1284 1285 mem = &sc->mem; 1286 if (mem->mem_res != NULL) 1287 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1288 mem->mem_res); 1289 mem->mem_res = NULL; 1290} 1291 1292/**************************************************************************** 1293 * int hdac_irq_alloc(struct hdac_softc *) 1294 * 1295 * Allocate and setup the resources necessary for interrupt handling. 1296 ****************************************************************************/ 1297static int 1298hdac_irq_alloc(struct hdac_softc *sc) 1299{ 1300 struct hdac_irq *irq; 1301 int result; 1302 1303 irq = &sc->irq; 1304 irq->irq_rid = 0x0; 1305 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1306 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1307 if (irq->irq_res == NULL) { 1308 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1309 __func__); 1310 goto fail; 1311 } 1312 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1313 hdac_intr_handler, sc, &irq->irq_handle); 1314 if (result != 0) { 1315 device_printf(sc->dev, 1316 "%s: Unable to setup interrupt handler (%x)\n", 1317 __func__, result); 1318 goto fail; 1319 } 1320 1321 return (0); 1322 1323fail: 1324 hdac_irq_free(sc); 1325 1326 return (ENXIO); 1327} 1328 1329/**************************************************************************** 1330 * void hdac_irq_free(struct hdac_softc *) 1331 * 1332 * Free up resources previously allocated by hdac_irq_alloc. 1333 ****************************************************************************/ 1334static void 1335hdac_irq_free(struct hdac_softc *sc) 1336{ 1337 struct hdac_irq *irq; 1338 1339 irq = &sc->irq; 1340 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1341 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1342 if (irq->irq_res != NULL) 1343 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1344 irq->irq_res); 1345 irq->irq_handle = NULL; 1346 irq->irq_res = NULL; 1347} 1348 1349/**************************************************************************** 1350 * void hdac_corb_init(struct hdac_softc *) 1351 * 1352 * Initialize the corb registers for operations but do not start it up yet. 1353 * The CORB engine must not be running when this function is called. 1354 ****************************************************************************/ 1355static void 1356hdac_corb_init(struct hdac_softc *sc) 1357{ 1358 uint8_t corbsize; 1359 uint64_t corbpaddr; 1360 1361 /* Setup the CORB size. */ 1362 switch (sc->corb_size) { 1363 case 256: 1364 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1365 break; 1366 case 16: 1367 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1368 break; 1369 case 2: 1370 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1371 break; 1372 default: 1373 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1374 } 1375 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1376 1377 /* Setup the CORB Address in the hdac */ 1378 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1379 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1380 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1381 1382 /* Set the WP and RP */ 1383 sc->corb_wp = 0; 1384 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1385 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1386 /* 1387 * The HDA specification indicates that the CORBRPRST bit will always 1388 * read as zero. Unfortunately, it seems that at least the 82801G 1389 * doesn't reset the bit to zero, which stalls the corb engine. 1390 * manually reset the bit to zero before continuing. 1391 */ 1392 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1393 1394 /* Enable CORB error reporting */ 1395#if 0 1396 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1397#endif 1398} 1399 1400/**************************************************************************** 1401 * void hdac_rirb_init(struct hdac_softc *) 1402 * 1403 * Initialize the rirb registers for operations but do not start it up yet. 1404 * The RIRB engine must not be running when this function is called. 1405 ****************************************************************************/ 1406static void 1407hdac_rirb_init(struct hdac_softc *sc) 1408{ 1409 uint8_t rirbsize; 1410 uint64_t rirbpaddr; 1411 1412 /* Setup the RIRB size. */ 1413 switch (sc->rirb_size) { 1414 case 256: 1415 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1416 break; 1417 case 16: 1418 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1419 break; 1420 case 2: 1421 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1422 break; 1423 default: 1424 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1425 } 1426 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1427 1428 /* Setup the RIRB Address in the hdac */ 1429 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1430 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1431 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1432 1433 /* Setup the WP and RP */ 1434 sc->rirb_rp = 0; 1435 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1436 1437 if (sc->polling == 0) { 1438 /* Setup the interrupt threshold */ 1439 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1440 1441 /* Enable Overrun and response received reporting */ 1442#if 0 1443 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1444 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1445#else 1446 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1447#endif 1448 } 1449 1450 /* 1451 * Make sure that the Host CPU cache doesn't contain any dirty 1452 * cache lines that falls in the rirb. If I understood correctly, it 1453 * should be sufficient to do this only once as the rirb is purely 1454 * read-only from now on. 1455 */ 1456 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1457 BUS_DMASYNC_PREREAD); 1458} 1459 1460/**************************************************************************** 1461 * void hdac_corb_start(hdac_softc *) 1462 * 1463 * Startup the corb DMA engine 1464 ****************************************************************************/ 1465static void 1466hdac_corb_start(struct hdac_softc *sc) 1467{ 1468 uint32_t corbctl; 1469 1470 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1471 corbctl |= HDAC_CORBCTL_CORBRUN; 1472 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1473} 1474 1475/**************************************************************************** 1476 * void hdac_rirb_start(hdac_softc *) 1477 * 1478 * Startup the rirb DMA engine 1479 ****************************************************************************/ 1480static void 1481hdac_rirb_start(struct hdac_softc *sc) 1482{ 1483 uint32_t rirbctl; 1484 1485 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1486 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1487 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1488} 1489 1490 1491/**************************************************************************** 1492 * void hdac_scan_codecs(struct hdac_softc *) 1493 * 1494 * Scan the bus for available codecs. 1495 ****************************************************************************/ 1496static void 1497hdac_scan_codecs(struct hdac_softc *sc) 1498{ 1499 struct hdac_codec *codec; 1500 int i; 1501 uint16_t statests; 1502 1503 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1504 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1505 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1506 /* We have found a codec. */ 1507 hdac_unlock(sc); 1508 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1509 M_HDAC, M_ZERO | M_NOWAIT); 1510 hdac_lock(sc); 1511 if (codec == NULL) { 1512 device_printf(sc->dev, 1513 "Unable to allocate memory for codec\n"); 1514 continue; 1515 } 1516 codec->commands = NULL; 1517 codec->responses_received = 0; 1518 codec->verbs_sent = 0; 1519 codec->sc = sc; 1520 codec->cad = i; 1521 sc->codecs[i] = codec; 1522 if (hdac_probe_codec(codec) != 0) 1523 break; 1524 } 1525 } 1526 /* All codecs have been probed, now try to attach drivers to them */ 1527 /* bus_generic_attach(sc->dev); */ 1528} 1529 1530/**************************************************************************** 1531 * void hdac_probe_codec(struct hdac_softc *, int) 1532 * 1533 * Probe a the given codec_id for available function groups. 1534 ****************************************************************************/ 1535static int 1536hdac_probe_codec(struct hdac_codec *codec) 1537{ 1538 struct hdac_softc *sc = codec->sc; 1539 struct hdac_devinfo *devinfo; 1540 uint32_t vendorid, revisionid, subnode; 1541 int startnode; 1542 int endnode; 1543 int i; 1544 nid_t cad = codec->cad; 1545 1546 HDA_BOOTVERBOSE( 1547 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1548 ); 1549 vendorid = hdac_command(sc, 1550 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1551 cad); 1552 revisionid = hdac_command(sc, 1553 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1554 cad); 1555 subnode = hdac_command(sc, 1556 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1557 cad); 1558 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1559 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1560 1561 HDA_BOOTVERBOSE( 1562 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1563 startnode, endnode); 1564 ); 1565 for (i = startnode; i < endnode; i++) { 1566 devinfo = hdac_probe_function(codec, i); 1567 if (devinfo != NULL) { 1568 /* XXX Ignore other FG. */ 1569 devinfo->vendor_id = 1570 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1571 devinfo->device_id = 1572 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1573 devinfo->revision_id = 1574 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1575 devinfo->stepping_id = 1576 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1577 HDA_BOOTVERBOSE( 1578 device_printf(sc->dev, 1579 "HDA_DEBUG: \tFound AFG nid=%d " 1580 "[startnode=%d endnode=%d]\n", 1581 devinfo->nid, startnode, endnode); 1582 ); 1583 return (1); 1584 } 1585 } 1586 1587 HDA_BOOTVERBOSE( 1588 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1589 ); 1590 return (0); 1591} 1592 1593static struct hdac_devinfo * 1594hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1595{ 1596 struct hdac_softc *sc = codec->sc; 1597 struct hdac_devinfo *devinfo; 1598 uint32_t fctgrptype; 1599 nid_t cad = codec->cad; 1600 1601 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1602 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1603 1604 /* XXX For now, ignore other FG. */ 1605 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1606 return (NULL); 1607 1608 hdac_unlock(sc); 1609 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1610 M_NOWAIT | M_ZERO); 1611 hdac_lock(sc); 1612 if (devinfo == NULL) { 1613 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1614 __func__); 1615 return (NULL); 1616 } 1617 1618 devinfo->nid = nid; 1619 devinfo->node_type = fctgrptype; 1620 devinfo->codec = codec; 1621 1622 hdac_add_child(sc, devinfo); 1623 1624 return (devinfo); 1625} 1626 1627static void 1628hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1629{ 1630 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1631 device_set_ivars(devinfo->dev, (void *)devinfo); 1632 /* XXX - Print more information when booting verbose??? */ 1633} 1634 1635static void 1636hdac_widget_connection_parse(struct hdac_widget *w) 1637{ 1638 struct hdac_softc *sc = w->devinfo->codec->sc; 1639 uint32_t res; 1640 int i, j, max, found, entnum, cnid; 1641 nid_t cad = w->devinfo->codec->cad; 1642 nid_t nid = w->nid; 1643 1644 res = hdac_command(sc, 1645 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1646 1647 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1648 1649 if (w->nconns < 1) 1650 return; 1651 1652 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1653 res = 0; 1654 i = 0; 1655 found = 0; 1656 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1657 1658 while (i < w->nconns) { 1659 res = hdac_command(sc, 1660 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1661 for (j = 0; j < entnum; j++) { 1662 cnid = res; 1663 cnid >>= (32 / entnum) * j; 1664 cnid &= (1 << (32 / entnum)) - 1; 1665 if (cnid == 0) 1666 continue; 1667 if (found > max) { 1668 device_printf(sc->dev, 1669 "node %d: Adding %d: " 1670 "Max connection reached!\n", 1671 nid, cnid); 1672 continue; 1673 } 1674 w->conns[found++] = cnid; 1675 } 1676 i += entnum; 1677 } 1678 1679 HDA_BOOTVERBOSE( 1680 if (w->nconns != found) { 1681 device_printf(sc->dev, 1682 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1683 "length=%d != found=%d\n", 1684 nid, w->nconns, found); 1685 } 1686 ); 1687} 1688 1689static uint32_t 1690hdac_widget_pin_getconfig(struct hdac_widget *w) 1691{ 1692 struct hdac_softc *sc; 1693 uint32_t config, id; 1694 nid_t cad, nid; 1695 1696 sc = w->devinfo->codec->sc; 1697 cad = w->devinfo->codec->cad; 1698 nid = w->nid; 1699 id = hdac_codec_id(w->devinfo); 1700 1701 config = hdac_command(sc, 1702 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1703 cad); 1704 /* 1705 * XXX REWRITE!!!! Don't argue! 1706 */ 1707 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1708 switch (nid) { 1709 case 26: 1710 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1711 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1712 break; 1713 case 27: 1714 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1715 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1716 break; 1717 } 1718 } else if (id == HDA_CODEC_ALC880 && 1719 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1720 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1721 /* 1722 * Super broken BIOS 1723 */ 1724 switch (nid) { 1725 case 20: 1726 break; 1727 case 21: 1728 break; 1729 case 22: 1730 break; 1731 case 23: 1732 break; 1733 case 24: /* MIC1 */ 1734 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1735 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1736 break; 1737 case 25: /* XXX MIC2 */ 1738 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1739 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1740 break; 1741 case 26: /* LINE1 */ 1742 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1743 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1744 break; 1745 case 27: /* XXX LINE2 */ 1746 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1747 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1748 break; 1749 case 28: /* CD */ 1750 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1751 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1752 break; 1753 case 30: 1754 break; 1755 case 31: 1756 break; 1757 default: 1758 break; 1759 } 1760 } 1761 1762 return (config); 1763} 1764 1765static void 1766hdac_widget_pin_parse(struct hdac_widget *w) 1767{ 1768 struct hdac_softc *sc = w->devinfo->codec->sc; 1769 uint32_t config, pincap; 1770 char *devstr, *connstr; 1771 nid_t cad = w->devinfo->codec->cad; 1772 nid_t nid = w->nid; 1773 1774 config = hdac_widget_pin_getconfig(w); 1775 w->wclass.pin.config = config; 1776 1777 pincap = hdac_command(sc, 1778 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1779 w->wclass.pin.cap = pincap; 1780 1781 w->wclass.pin.ctrl = hdac_command(sc, 1782 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1783 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1784 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1785 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1786 1787 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1788 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1789 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1790 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1791 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1792 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1793 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1794 w->param.eapdbtl = hdac_command(sc, 1795 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1796 w->param.eapdbtl &= 0x7; 1797 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1798 } else 1799 w->param.eapdbtl = HDAC_INVALID; 1800 1801 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1802 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1803 devstr = "line out"; 1804 break; 1805 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1806 devstr = "speaker"; 1807 break; 1808 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1809 devstr = "headphones out"; 1810 break; 1811 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1812 devstr = "CD"; 1813 break; 1814 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1815 devstr = "SPDIF out"; 1816 break; 1817 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1818 devstr = "digital (other) out"; 1819 break; 1820 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1821 devstr = "modem, line side"; 1822 break; 1823 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1824 devstr = "modem, handset side"; 1825 break; 1826 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1827 devstr = "line in"; 1828 break; 1829 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1830 devstr = "AUX"; 1831 break; 1832 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1833 devstr = "Mic in"; 1834 break; 1835 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1836 devstr = "telephony"; 1837 break; 1838 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1839 devstr = "SPDIF in"; 1840 break; 1841 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1842 devstr = "digital (other) in"; 1843 break; 1844 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1845 devstr = "other"; 1846 break; 1847 default: 1848 devstr = "unknown"; 1849 break; 1850 } 1851 1852 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1853 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1854 connstr = "jack"; 1855 break; 1856 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1857 connstr = "none"; 1858 break; 1859 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1860 connstr = "fixed"; 1861 break; 1862 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1863 connstr = "jack / fixed"; 1864 break; 1865 default: 1866 connstr = "unknown"; 1867 break; 1868 } 1869 1870 strlcat(w->name, ": ", sizeof(w->name)); 1871 strlcat(w->name, devstr, sizeof(w->name)); 1872 strlcat(w->name, " (", sizeof(w->name)); 1873 strlcat(w->name, connstr, sizeof(w->name)); 1874 strlcat(w->name, ")", sizeof(w->name)); 1875} 1876 1877static void 1878hdac_widget_parse(struct hdac_widget *w) 1879{ 1880 struct hdac_softc *sc = w->devinfo->codec->sc; 1881 uint32_t wcap, cap; 1882 char *typestr; 1883 nid_t cad = w->devinfo->codec->cad; 1884 nid_t nid = w->nid; 1885 1886 wcap = hdac_command(sc, 1887 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1888 cad); 1889 w->param.widget_cap = wcap; 1890 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1891 1892 switch (w->type) { 1893 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1894 typestr = "audio output"; 1895 break; 1896 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1897 typestr = "audio input"; 1898 break; 1899 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1900 typestr = "audio mixer"; 1901 break; 1902 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1903 typestr = "audio selector"; 1904 break; 1905 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1906 typestr = "pin"; 1907 break; 1908 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1909 typestr = "power widget"; 1910 break; 1911 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1912 typestr = "volume widget"; 1913 break; 1914 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1915 typestr = "beep widget"; 1916 break; 1917 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1918 typestr = "vendor widget"; 1919 break; 1920 default: 1921 typestr = "unknown type"; 1922 break; 1923 } 1924 1925 strlcpy(w->name, typestr, sizeof(w->name)); 1926 1927 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1928 hdac_command(sc, 1929 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1930 cad); 1931 DELAY(1000); 1932 } 1933 1934 hdac_widget_connection_parse(w); 1935 1936 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1937 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1938 w->param.outamp_cap = 1939 hdac_command(sc, 1940 HDA_CMD_GET_PARAMETER(cad, nid, 1941 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1942 else 1943 w->param.outamp_cap = 1944 w->devinfo->function.audio.outamp_cap; 1945 } else 1946 w->param.outamp_cap = 0; 1947 1948 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1949 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1950 w->param.inamp_cap = 1951 hdac_command(sc, 1952 HDA_CMD_GET_PARAMETER(cad, nid, 1953 HDA_PARAM_INPUT_AMP_CAP), cad); 1954 else 1955 w->param.inamp_cap = 1956 w->devinfo->function.audio.inamp_cap; 1957 } else 1958 w->param.inamp_cap = 0; 1959 1960 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1961 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1962 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1963 cap = hdac_command(sc, 1964 HDA_CMD_GET_PARAMETER(cad, nid, 1965 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1966 w->param.supp_stream_formats = (cap != 0) ? cap : 1967 w->devinfo->function.audio.supp_stream_formats; 1968 cap = hdac_command(sc, 1969 HDA_CMD_GET_PARAMETER(cad, nid, 1970 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1971 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1972 w->devinfo->function.audio.supp_pcm_size_rate; 1973 } else { 1974 w->param.supp_stream_formats = 1975 w->devinfo->function.audio.supp_stream_formats; 1976 w->param.supp_pcm_size_rate = 1977 w->devinfo->function.audio.supp_pcm_size_rate; 1978 } 1979 } else { 1980 w->param.supp_stream_formats = 0; 1981 w->param.supp_pcm_size_rate = 0; 1982 } 1983 1984 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1985 hdac_widget_pin_parse(w); 1986} 1987 1988static struct hdac_widget * 1989hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1990{ 1991 if (devinfo == NULL || devinfo->widget == NULL || 1992 nid < devinfo->startnode || nid >= devinfo->endnode) 1993 return (NULL); 1994 return (&devinfo->widget[nid - devinfo->startnode]); 1995} 1996 1997static __inline int 1998hda_poll_channel(struct hdac_chan *ch) 1999{ 2000 uint32_t sz, delta; 2001 volatile uint32_t ptr; 2002 2003 if (ch->active == 0) 2004 return (0); 2005 2006 sz = ch->blksz * ch->blkcnt; 2007 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2008 ch->ptr = ptr; 2009 ptr %= sz; 2010 ptr &= ~(ch->blksz - 1); 2011 delta = (sz + ptr - ch->prevptr) % sz; 2012 2013 if (delta < ch->blksz) 2014 return (0); 2015 2016 ch->prevptr = ptr; 2017 2018 return (1); 2019} 2020 2021#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2022 2023static void 2024hda_poll_callback(void *arg) 2025{ 2026 struct hdac_softc *sc = arg; 2027 uint32_t trigger = 0; 2028 2029 if (sc == NULL) 2030 return; 2031 2032 hdac_lock(sc); 2033 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2034 hdac_unlock(sc); 2035 return; 2036 } 2037 2038 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2039 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2040 2041 /* XXX */ 2042 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2043 hda_poll_callback, sc); 2044 2045 hdac_unlock(sc); 2046 2047 if (trigger & 1) 2048 chn_intr(sc->play.c); 2049 if (trigger & 2) 2050 chn_intr(sc->rec.c); 2051} 2052 2053static int 2054hdac_rirb_flush(struct hdac_softc *sc) 2055{ 2056 struct hdac_rirb *rirb_base, *rirb; 2057 struct hdac_codec *codec; 2058 struct hdac_command_list *commands; 2059 nid_t cad; 2060 uint32_t resp; 2061 uint8_t rirbwp; 2062 int ret = 0; 2063 2064 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2065 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2066 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2067 BUS_DMASYNC_POSTREAD); 2068 2069 while (sc->rirb_rp != rirbwp) { 2070 sc->rirb_rp++; 2071 sc->rirb_rp %= sc->rirb_size; 2072 rirb = &rirb_base[sc->rirb_rp]; 2073 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2074 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2075 sc->codecs[cad] == NULL) 2076 continue; 2077 resp = rirb->response; 2078 codec = sc->codecs[cad]; 2079 commands = codec->commands; 2080 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2081 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2082 ((resp >> 26) & 0xffff); 2083 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2084 } else if (commands != NULL && commands->num_commands > 0 && 2085 codec->responses_received < commands->num_commands) 2086 commands->responses[codec->responses_received++] = 2087 resp; 2088 ret++; 2089 } 2090 2091 return (ret); 2092} 2093 2094static int 2095hdac_unsolq_flush(struct hdac_softc *sc) 2096{ 2097 nid_t cad; 2098 uint32_t tag; 2099 int ret = 0; 2100 2101 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2102 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2103 while (sc->unsolq_rp != sc->unsolq_wp) { 2104 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2105 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2106 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2107 hdac_unsolicited_handler(sc->codecs[cad], tag); 2108 ret++; 2109 } 2110 sc->unsolq_st = HDAC_UNSOLQ_READY; 2111 } 2112 2113 return (ret); 2114} 2115 2116static void 2117hdac_poll_callback(void *arg) 2118{ 2119 struct hdac_softc *sc = arg; 2120 if (sc == NULL) 2121 return; 2122 2123 hdac_lock(sc); 2124 if (sc->polling == 0) { 2125 hdac_unlock(sc); 2126 return; 2127 } 2128 hdac_rirb_flush(sc); 2129 hdac_unsolq_flush(sc); 2130 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2131 hdac_poll_callback, sc); 2132 hdac_unlock(sc); 2133} 2134 2135static void 2136hdac_stream_stop(struct hdac_chan *ch) 2137{ 2138 struct hdac_softc *sc = ch->devinfo->codec->sc; 2139 uint32_t ctl; 2140 2141 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2142 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2143 HDAC_SDCTL_RUN); 2144 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2145 2146 ch->active = 0; 2147 2148 if (sc->polling != 0) { 2149 int pollticks; 2150 2151 if (hda_chan_active(sc) == 0) { 2152 callout_stop(&sc->poll_hda); 2153 sc->poll_ticks = 1; 2154 } else { 2155 if (sc->play.active != 0) 2156 ch = &sc->play; 2157 else 2158 ch = &sc->rec; 2159 pollticks = ((uint64_t)hz * ch->blksz) / 2160 ((uint64_t)sndbuf_getbps(ch->b) * 2161 sndbuf_getspd(ch->b)); 2162 pollticks >>= 2; 2163 if (pollticks > hz) 2164 pollticks = hz; 2165 if (pollticks < 1) { 2166 HDA_BOOTVERBOSE( 2167 device_printf(sc->dev, 2168 "%s: pollticks=%d < 1 !\n", 2169 __func__, pollticks); 2170 ); 2171 pollticks = 1; 2172 } 2173 if (pollticks > sc->poll_ticks) { 2174 HDA_BOOTVERBOSE( 2175 device_printf(sc->dev, 2176 "%s: pollticks %d -> %d\n", 2177 __func__, sc->poll_ticks, 2178 pollticks); 2179 ); 2180 sc->poll_ticks = pollticks; 2181 callout_reset(&sc->poll_hda, 1, 2182 hda_poll_callback, sc); 2183 } 2184 } 2185 } else { 2186 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2187 ctl &= ~(1 << (ch->off >> 5)); 2188 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2189 } 2190} 2191 2192static void 2193hdac_stream_start(struct hdac_chan *ch) 2194{ 2195 struct hdac_softc *sc = ch->devinfo->codec->sc; 2196 uint32_t ctl; 2197 2198 if (sc->polling != 0) { 2199 int pollticks; 2200 2201 pollticks = ((uint64_t)hz * ch->blksz) / 2202 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2203 pollticks >>= 2; 2204 if (pollticks > hz) 2205 pollticks = hz; 2206 if (pollticks < 1) { 2207 HDA_BOOTVERBOSE( 2208 device_printf(sc->dev, 2209 "%s: pollticks=%d < 1 !\n", 2210 __func__, pollticks); 2211 ); 2212 pollticks = 1; 2213 } 2214 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2215 HDA_BOOTVERBOSE( 2216 if (hda_chan_active(sc) == 0) { 2217 device_printf(sc->dev, 2218 "%s: pollticks=%d\n", 2219 __func__, pollticks); 2220 } else { 2221 device_printf(sc->dev, 2222 "%s: pollticks %d -> %d\n", 2223 __func__, sc->poll_ticks, 2224 pollticks); 2225 } 2226 ); 2227 sc->poll_ticks = pollticks; 2228 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2229 sc); 2230 } 2231 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2232 ctl |= HDAC_SDCTL_RUN; 2233 } else { 2234 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2235 ctl |= 1 << (ch->off >> 5); 2236 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2237 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2238 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2239 HDAC_SDCTL_RUN; 2240 } 2241 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2242 2243 ch->active = 1; 2244} 2245 2246static void 2247hdac_stream_reset(struct hdac_chan *ch) 2248{ 2249 struct hdac_softc *sc = ch->devinfo->codec->sc; 2250 int timeout = 1000; 2251 int to = timeout; 2252 uint32_t ctl; 2253 2254 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2255 ctl |= HDAC_SDCTL_SRST; 2256 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2257 do { 2258 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2259 if (ctl & HDAC_SDCTL_SRST) 2260 break; 2261 DELAY(10); 2262 } while (--to); 2263 if (!(ctl & HDAC_SDCTL_SRST)) { 2264 device_printf(sc->dev, "timeout in reset\n"); 2265 } 2266 ctl &= ~HDAC_SDCTL_SRST; 2267 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2268 to = timeout; 2269 do { 2270 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2271 if (!(ctl & HDAC_SDCTL_SRST)) 2272 break; 2273 DELAY(10); 2274 } while (--to); 2275 if (ctl & HDAC_SDCTL_SRST) 2276 device_printf(sc->dev, "can't reset!\n"); 2277} 2278 2279static void 2280hdac_stream_setid(struct hdac_chan *ch) 2281{ 2282 struct hdac_softc *sc = ch->devinfo->codec->sc; 2283 uint32_t ctl; 2284 2285 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2286 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2287 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2288 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2289} 2290 2291static void 2292hdac_bdl_setup(struct hdac_chan *ch) 2293{ 2294 struct hdac_softc *sc = ch->devinfo->codec->sc; 2295 struct hdac_bdle *bdle; 2296 uint64_t addr; 2297 uint32_t blksz, blkcnt; 2298 int i; 2299 2300 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2301 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2302 2303 if (sc->polling != 0) { 2304 blksz = ch->blksz * ch->blkcnt; 2305 blkcnt = 1; 2306 } else { 2307 blksz = ch->blksz; 2308 blkcnt = ch->blkcnt; 2309 } 2310 2311 for (i = 0; i < blkcnt; i++, bdle++) { 2312 bdle->addrl = (uint32_t)addr; 2313 bdle->addrh = (uint32_t)(addr >> 32); 2314 bdle->len = blksz; 2315 bdle->ioc = 1 ^ sc->polling; 2316 addr += blksz; 2317 } 2318 2319 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2320 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2321 addr = ch->bdl_dma.dma_paddr; 2322 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2323 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2324} 2325 2326static int 2327hdac_bdl_alloc(struct hdac_chan *ch) 2328{ 2329 struct hdac_softc *sc = ch->devinfo->codec->sc; 2330 int rc; 2331 2332 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2333 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2334 if (rc) { 2335 device_printf(sc->dev, "can't alloc bdl\n"); 2336 return (rc); 2337 } 2338 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2339 2340 return (0); 2341} 2342 2343static void 2344hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2345 int index, int lmute, int rmute, 2346 int left, int right, int dir) 2347{ 2348 uint16_t v = 0; 2349 2350 if (sc == NULL) 2351 return; 2352 2353 if (left != right || lmute != rmute) { 2354 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2355 (lmute << 7) | left; 2356 hdac_command(sc, 2357 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2358 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2359 (rmute << 7) | right; 2360 } else 2361 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2362 (lmute << 7) | left; 2363 2364 hdac_command(sc, 2365 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2366} 2367 2368static void 2369hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2370 int left, int right) 2371{ 2372 struct hdac_softc *sc; 2373 nid_t nid, cad; 2374 int lmute, rmute; 2375 2376 if (ctl == NULL || ctl->widget == NULL || 2377 ctl->widget->devinfo == NULL || 2378 ctl->widget->devinfo->codec == NULL || 2379 ctl->widget->devinfo->codec->sc == NULL) 2380 return; 2381 2382 sc = ctl->widget->devinfo->codec->sc; 2383 cad = ctl->widget->devinfo->codec->cad; 2384 nid = ctl->widget->nid; 2385 2386 if (mute == HDA_AMP_MUTE_DEFAULT) { 2387 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2388 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2389 } else { 2390 lmute = HDA_AMP_LEFT_MUTED(mute); 2391 rmute = HDA_AMP_RIGHT_MUTED(mute); 2392 } 2393 2394 if (ctl->dir & HDA_CTL_OUT) 2395 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2396 lmute, rmute, left, right, 0); 2397 if (ctl->dir & HDA_CTL_IN) 2398 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2399 lmute, rmute, left, right, 1); 2400 ctl->left = left; 2401 ctl->right = right; 2402} 2403 2404static void 2405hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2406{ 2407 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2408 return; 2409 hdac_command(w->devinfo->codec->sc, 2410 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2411 w->nid, index), w->devinfo->codec->cad); 2412 w->selconn = index; 2413} 2414 2415 2416/**************************************************************************** 2417 * uint32_t hdac_command_sendone_internal 2418 * 2419 * Wrapper function that sends only one command to a given codec 2420 ****************************************************************************/ 2421static uint32_t 2422hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2423{ 2424 struct hdac_command_list cl; 2425 uint32_t response = HDAC_INVALID; 2426 2427 if (!hdac_lockowned(sc)) 2428 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2429 cl.num_commands = 1; 2430 cl.verbs = &verb; 2431 cl.responses = &response; 2432 2433 hdac_command_send_internal(sc, &cl, cad); 2434 2435 return (response); 2436} 2437 2438/**************************************************************************** 2439 * hdac_command_send_internal 2440 * 2441 * Send a command list to the codec via the corb. We queue as much verbs as 2442 * we can and msleep on the codec. When the interrupt get the responses 2443 * back from the rirb, it will wake us up so we can queue the remaining verbs 2444 * if any. 2445 ****************************************************************************/ 2446static void 2447hdac_command_send_internal(struct hdac_softc *sc, 2448 struct hdac_command_list *commands, nid_t cad) 2449{ 2450 struct hdac_codec *codec; 2451 int corbrp; 2452 uint32_t *corb; 2453 int timeout; 2454 int retry = 10; 2455 struct hdac_rirb *rirb_base; 2456 2457 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2458 commands->num_commands < 1) 2459 return; 2460 2461 codec = sc->codecs[cad]; 2462 codec->commands = commands; 2463 codec->responses_received = 0; 2464 codec->verbs_sent = 0; 2465 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2466 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2467 2468 do { 2469 if (codec->verbs_sent != commands->num_commands) { 2470 /* Queue as many verbs as possible */ 2471 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2472 bus_dmamap_sync(sc->corb_dma.dma_tag, 2473 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2474 while (codec->verbs_sent != commands->num_commands && 2475 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2476 sc->corb_wp++; 2477 sc->corb_wp %= sc->corb_size; 2478 corb[sc->corb_wp] = 2479 commands->verbs[codec->verbs_sent++]; 2480 } 2481 2482 /* Send the verbs to the codecs */ 2483 bus_dmamap_sync(sc->corb_dma.dma_tag, 2484 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2485 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2486 } 2487 2488 timeout = 1000; 2489 while (hdac_rirb_flush(sc) == 0 && --timeout) 2490 DELAY(10); 2491 } while ((codec->verbs_sent != commands->num_commands || 2492 codec->responses_received != commands->num_commands) && --retry); 2493 2494 if (retry == 0) 2495 device_printf(sc->dev, 2496 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2497 __func__, commands->num_commands, codec->verbs_sent, 2498 codec->responses_received); 2499 2500 codec->commands = NULL; 2501 codec->responses_received = 0; 2502 codec->verbs_sent = 0; 2503 2504 hdac_unsolq_flush(sc); 2505} 2506 2507 2508/**************************************************************************** 2509 * Device Methods 2510 ****************************************************************************/ 2511 2512/**************************************************************************** 2513 * int hdac_probe(device_t) 2514 * 2515 * Probe for the presence of an hdac. If none is found, check for a generic 2516 * match using the subclass of the device. 2517 ****************************************************************************/ 2518static int 2519hdac_probe(device_t dev) 2520{ 2521 int i, result; 2522 uint32_t model; 2523 uint16_t class, subclass; 2524 char desc[64]; 2525 2526 model = (uint32_t)pci_get_device(dev) << 16; 2527 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2528 class = pci_get_class(dev); 2529 subclass = pci_get_subclass(dev); 2530 2531 bzero(desc, sizeof(desc)); 2532 result = ENXIO; 2533 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2534 if (hdac_devices[i].model == model) { 2535 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2536 result = BUS_PROBE_DEFAULT; 2537 break; 2538 } 2539 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2540 class == PCIC_MULTIMEDIA && 2541 subclass == PCIS_MULTIMEDIA_HDA) { 2542 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2543 result = BUS_PROBE_GENERIC; 2544 break; 2545 } 2546 } 2547 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2548 subclass == PCIS_MULTIMEDIA_HDA) { 2549 strlcpy(desc, "Generic", sizeof(desc)); 2550 result = BUS_PROBE_GENERIC; 2551 } 2552 if (result != ENXIO) { 2553 strlcat(desc, " High Definition Audio Controller", 2554 sizeof(desc)); 2555 device_set_desc_copy(dev, desc); 2556 } 2557 2558 return (result); 2559} 2560 2561static void * 2562hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2563 struct pcm_channel *c, int dir) 2564{ 2565 struct hdac_devinfo *devinfo = data; 2566 struct hdac_softc *sc = devinfo->codec->sc; 2567 struct hdac_chan *ch; 2568 2569 hdac_lock(sc); 2570 if (dir == PCMDIR_PLAY) { 2571 ch = &sc->play; 2572 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2573 ch->dir = PCMDIR_PLAY; 2574 ch->sid = ++sc->streamcnt; 2575 devinfo->function.audio.playcnt++; 2576 } else { 2577 ch = &sc->rec; 2578 ch->off = devinfo->function.audio.reccnt << 5; 2579 ch->dir = PCMDIR_REC; 2580 ch->sid = ++sc->streamcnt; 2581 devinfo->function.audio.reccnt++; 2582 } 2583 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2584 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2585 ch->pcmrates[0] = 48000; 2586 ch->pcmrates[1] = 0; 2587 } 2588 ch->b = b; 2589 ch->c = c; 2590 ch->devinfo = devinfo; 2591 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2592 ch->blkcnt = sc->chan_blkcnt; 2593 hdac_unlock(sc); 2594 2595 if (hdac_bdl_alloc(ch) != 0) { 2596 ch->blkcnt = 0; 2597 return (NULL); 2598 } 2599 2600 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2601 return (NULL); 2602 2603 hdac_dma_nocache(ch->b->buf); 2604 2605 return (ch); 2606} 2607 2608static int 2609hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2610{ 2611 struct hdac_chan *ch = data; 2612 int i; 2613 2614 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2615 if (format == ch->caps.fmtlist[i]) { 2616 ch->fmt = format; 2617 return (0); 2618 } 2619 } 2620 2621 return (EINVAL); 2622} 2623 2624static int 2625hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2626{ 2627 struct hdac_chan *ch = data; 2628 uint32_t spd = 0, threshold; 2629 int i; 2630 2631 for (i = 0; ch->pcmrates[i] != 0; i++) { 2632 spd = ch->pcmrates[i]; 2633 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2634 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2635 if (speed < threshold) 2636 break; 2637 } 2638 2639 if (spd == 0) /* impossible */ 2640 ch->spd = 48000; 2641 else 2642 ch->spd = spd; 2643 2644 return (ch->spd); 2645} 2646 2647static void 2648hdac_stream_setup(struct hdac_chan *ch) 2649{ 2650 struct hdac_softc *sc = ch->devinfo->codec->sc; 2651 int i; 2652 nid_t cad = ch->devinfo->codec->cad; 2653 uint16_t fmt; 2654 2655 fmt = 0; 2656 if (ch->fmt & AFMT_S16_LE) 2657 fmt |= ch->bit16 << 4; 2658 else if (ch->fmt & AFMT_S32_LE) 2659 fmt |= ch->bit32 << 4; 2660 else 2661 fmt |= 1 << 4; 2662 2663 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2664 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2665 fmt |= hda_rate_tab[i].base; 2666 fmt |= hda_rate_tab[i].mul; 2667 fmt |= hda_rate_tab[i].div; 2668 break; 2669 } 2670 } 2671 2672 if (ch->fmt & AFMT_STEREO) 2673 fmt |= 1; 2674 2675 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2676 2677 for (i = 0; ch->io[i] != -1; i++) { 2678 HDA_BOOTVERBOSE( 2679 device_printf(sc->dev, 2680 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2681 "fmt=0x%08x\n", 2682 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2683 ch->io[i], fmt); 2684 ); 2685 hdac_command(sc, 2686 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2687 hdac_command(sc, 2688 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2689 ch->sid << 4), cad); 2690 } 2691} 2692 2693static int 2694hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2695{ 2696 struct hdac_chan *ch = data; 2697 struct hdac_softc *sc = ch->devinfo->codec->sc; 2698 2699 blksz &= ~0x7f; 2700 if (blksz < 0x80) 2701 blksz = 0x80; 2702 2703 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2704 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2705 2706 if ((sndbuf_getblksz(ch->b) != blksz || 2707 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2708 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2709 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2710 __func__, blksz, ch->blkcnt); 2711 2712 ch->blksz = sndbuf_getblksz(ch->b); 2713 2714 return (ch->blksz); 2715} 2716 2717static void 2718hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2719{ 2720 struct hdac_devinfo *devinfo = ch->devinfo; 2721 nid_t cad = devinfo->codec->cad; 2722 int i; 2723 2724 hdac_stream_stop(ch); 2725 2726 for (i = 0; ch->io[i] != -1; i++) { 2727 hdac_command(sc, 2728 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2729 0), cad); 2730 } 2731} 2732 2733static void 2734hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2735{ 2736 ch->ptr = 0; 2737 ch->prevptr = 0; 2738 hdac_stream_stop(ch); 2739 hdac_stream_reset(ch); 2740 hdac_bdl_setup(ch); 2741 hdac_stream_setid(ch); 2742 hdac_stream_setup(ch); 2743 hdac_stream_start(ch); 2744} 2745 2746static int 2747hdac_channel_trigger(kobj_t obj, void *data, int go) 2748{ 2749 struct hdac_chan *ch = data; 2750 struct hdac_softc *sc = ch->devinfo->codec->sc; 2751 2752 hdac_lock(sc); 2753 switch (go) { 2754 case PCMTRIG_START: 2755 hdac_channel_start(sc, ch); 2756 break; 2757 case PCMTRIG_STOP: 2758 case PCMTRIG_ABORT: 2759 hdac_channel_stop(sc, ch); 2760 break; 2761 } 2762 hdac_unlock(sc); 2763 2764 return (0); 2765} 2766 2767static int 2768hdac_channel_getptr(kobj_t obj, void *data) 2769{ 2770 struct hdac_chan *ch = data; 2771 struct hdac_softc *sc = ch->devinfo->codec->sc; 2772 uint32_t ptr; 2773 2774 hdac_lock(sc); 2775 if (sc->polling != 0) 2776 ptr = ch->ptr; 2777 else 2778 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2779 hdac_unlock(sc); 2780 2781 /* 2782 * Round to available space and force 128 bytes aligment. 2783 */ 2784 ptr %= ch->blksz * ch->blkcnt; 2785 ptr &= ~0x7f; 2786 2787 return (ptr); 2788} 2789 2790static struct pcmchan_caps * 2791hdac_channel_getcaps(kobj_t obj, void *data) 2792{ 2793 return (&((struct hdac_chan *)data)->caps); 2794} 2795 2796static kobj_method_t hdac_channel_methods[] = { 2797 KOBJMETHOD(channel_init, hdac_channel_init), 2798 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2799 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2800 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2801 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2802 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2803 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2804 { 0, 0 } 2805}; 2806CHANNEL_DECLARE(hdac_channel); 2807 2808static int 2809hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2810{ 2811 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2812 struct hdac_softc *sc = devinfo->codec->sc; 2813 struct hdac_widget *w, *cw; 2814 struct hdac_audio_ctl *ctl; 2815 uint32_t mask, recmask, id; 2816 int i, j, softpcmvol; 2817 nid_t cad; 2818 2819 hdac_lock(sc); 2820 2821 mask = 0; 2822 recmask = 0; 2823 2824 id = hdac_codec_id(devinfo); 2825 cad = devinfo->codec->cad; 2826 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2827 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2828 sc->pci_subvendor) && 2829 hdac_hp_switch[i].id == id)) 2830 continue; 2831 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2832 if (w != NULL && w->enable != 0 2833 && w->type == 2834 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2835 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2836 hdac_command(sc, 2837 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2838 w->nid, 2839 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2840 HDAC_UNSOLTAG_EVENT_HP), cad); 2841 hdac_hp_switch_handler(devinfo); 2842 HDA_BOOTVERBOSE( 2843 device_printf(sc->dev, 2844 "HDA_DEBUG: Enabling headphone/speaker " 2845 "audio routing switching:\n"); 2846 device_printf(sc->dev, 2847 "HDA_DEBUG: \tindex=%d nid=%d " 2848 "pci_subvendor=0x%08x " 2849 "codec=0x%08x\n", 2850 i, w->nid, sc->pci_subvendor, id); 2851 ); 2852 } 2853 break; 2854 } 2855 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2856 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2857 sc->pci_subvendor) && 2858 hdac_eapd_switch[i].id == id)) 2859 continue; 2860 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2861 if (w == NULL || w->enable == 0) 2862 break; 2863 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2864 w->param.eapdbtl == HDAC_INVALID) 2865 break; 2866 mask |= SOUND_MASK_OGAIN; 2867 break; 2868 } 2869 2870 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2871 w = hdac_widget_get(devinfo, i); 2872 if (w == NULL || w->enable == 0) 2873 continue; 2874 mask |= w->ctlflags; 2875 if (!(w->pflags & HDA_ADC_RECSEL)) 2876 continue; 2877 for (j = 0; j < w->nconns; j++) { 2878 cw = hdac_widget_get(devinfo, w->conns[j]); 2879 if (cw == NULL || cw->enable == 0) 2880 continue; 2881 recmask |= cw->ctlflags; 2882 } 2883 } 2884 2885 if (!(mask & SOUND_MASK_PCM)) { 2886 softpcmvol = 1; 2887 mask |= SOUND_MASK_PCM; 2888 } else 2889 softpcmvol = (devinfo->function.audio.quirks & 2890 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2891 2892 i = 0; 2893 ctl = NULL; 2894 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2895 if (ctl->widget == NULL || ctl->enable == 0) 2896 continue; 2897 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2898 continue; 2899 if (ctl->step > 0) 2900 break; 2901 } 2902 2903 if (softpcmvol == 1 || ctl == NULL) { 2904 struct snddev_info *d = NULL; 2905 d = device_get_softc(sc->dev); 2906 if (d != NULL) { 2907 d->flags |= SD_F_SOFTPCMVOL; 2908 HDA_BOOTVERBOSE( 2909 device_printf(sc->dev, 2910 "HDA_DEBUG: %s Soft PCM volume\n", 2911 (softpcmvol == 1) ? 2912 "Forcing" : "Enabling"); 2913 ); 2914 } 2915 i = 0; 2916 /* 2917 * XXX Temporary quirk for STAC9220, until the parser 2918 * become smarter. 2919 */ 2920 if (id == HDA_CODEC_STAC9220) { 2921 mask |= SOUND_MASK_VOLUME; 2922 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2923 NULL) { 2924 if (ctl->widget == NULL || ctl->enable == 0) 2925 continue; 2926 if (ctl->widget->nid == 11 && ctl->index == 0) { 2927 ctl->ossmask = SOUND_MASK_VOLUME; 2928 ctl->ossval = 100 | (100 << 8); 2929 } else 2930 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2931 } 2932 } else if (id == HDA_CODEC_STAC9221) { 2933 mask |= SOUND_MASK_VOLUME; 2934 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2935 NULL) { 2936 if (ctl->widget == NULL) 2937 continue; 2938 if (ctl->widget->nid == 2 && ctl->index == 0) { 2939 ctl->enable = 1; 2940 ctl->ossmask = SOUND_MASK_VOLUME; 2941 ctl->ossval = 100 | (100 << 8); 2942 } else if (ctl->enable == 0) 2943 continue; 2944 else 2945 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2946 } 2947 } else { 2948 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2949 SOUND_MASK_PCM); 2950 if (!(mask & SOUND_MASK_VOLUME)) 2951 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2952 SOUND_MIXER_NONE); 2953 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2954 NULL) { 2955 if (ctl->widget == NULL || ctl->enable == 0) 2956 continue; 2957 if (!HDA_FLAG_MATCH(ctl->ossmask, 2958 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2959 continue; 2960 if (!(ctl->mute == 1 && ctl->step == 0)) 2961 ctl->enable = 0; 2962 } 2963 } 2964 } 2965 2966 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2967 2968 mix_setrecdevs(m, recmask); 2969 mix_setdevs(m, mask); 2970 2971 hdac_unlock(sc); 2972 2973 return (0); 2974} 2975 2976static int 2977hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2978 unsigned left, unsigned right) 2979{ 2980 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2981 struct hdac_softc *sc = devinfo->codec->sc; 2982 struct hdac_widget *w; 2983 struct hdac_audio_ctl *ctl; 2984 uint32_t id, mute; 2985 int lvol, rvol, mlvol, mrvol; 2986 int i = 0; 2987 2988 hdac_lock(sc); 2989 if (dev == SOUND_MIXER_OGAIN) { 2990 uint32_t orig; 2991 /*if (left != right || !(left == 0 || left == 1)) { 2992 hdac_unlock(sc); 2993 return (-1); 2994 }*/ 2995 id = hdac_codec_id(devinfo); 2996 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2997 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2998 sc->pci_subvendor) && 2999 hdac_eapd_switch[i].id == id) 3000 break; 3001 } 3002 if (i >= HDAC_EAPD_SWITCH_LEN) { 3003 hdac_unlock(sc); 3004 return (-1); 3005 } 3006 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3007 if (w == NULL || 3008 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3009 w->param.eapdbtl == HDAC_INVALID) { 3010 hdac_unlock(sc); 3011 return (-1); 3012 } 3013 orig = w->param.eapdbtl; 3014 if (left == 0) 3015 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3016 else 3017 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3018 if (orig != w->param.eapdbtl) { 3019 uint32_t val; 3020 3021 if (hdac_eapd_switch[i].hp_switch != 0) 3022 hdac_hp_switch_handler(devinfo); 3023 val = w->param.eapdbtl; 3024 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3025 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3026 hdac_command(sc, 3027 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3028 w->nid, val), devinfo->codec->cad); 3029 } 3030 hdac_unlock(sc); 3031 return (left | (left << 8)); 3032 } 3033 if (dev == SOUND_MIXER_VOLUME) 3034 devinfo->function.audio.mvol = left | (right << 8); 3035 3036 mlvol = devinfo->function.audio.mvol & 0x7f; 3037 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3038 lvol = 0; 3039 rvol = 0; 3040 3041 i = 0; 3042 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3043 if (ctl->widget == NULL || ctl->enable == 0 || 3044 !(ctl->ossmask & (1 << dev))) 3045 continue; 3046 switch (dev) { 3047 case SOUND_MIXER_VOLUME: 3048 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3049 lvol = (lvol * ctl->step) / 100; 3050 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3051 rvol = (rvol * ctl->step) / 100; 3052 break; 3053 default: 3054 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3055 lvol = (left * mlvol) / 100; 3056 lvol = (lvol * ctl->step) / 100; 3057 rvol = (right * mrvol) / 100; 3058 rvol = (rvol * ctl->step) / 100; 3059 } else { 3060 lvol = (left * ctl->step) / 100; 3061 rvol = (right * ctl->step) / 100; 3062 } 3063 ctl->ossval = left | (right << 8); 3064 break; 3065 } 3066 mute = 0; 3067 if (ctl->step < 1) { 3068 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3069 (ctl->muted & HDA_AMP_MUTE_LEFT); 3070 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3071 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3072 } else { 3073 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3074 (ctl->muted & HDA_AMP_MUTE_LEFT); 3075 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3076 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3077 } 3078 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3079 } 3080 hdac_unlock(sc); 3081 3082 return (left | (right << 8)); 3083} 3084 3085static int 3086hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3087{ 3088 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3089 struct hdac_widget *w, *cw; 3090 struct hdac_softc *sc = devinfo->codec->sc; 3091 uint32_t ret = src, target; 3092 int i, j; 3093 3094 target = 0; 3095 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3096 if (src & (1 << i)) { 3097 target = 1 << i; 3098 break; 3099 } 3100 } 3101 3102 hdac_lock(sc); 3103 3104 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3105 w = hdac_widget_get(devinfo, i); 3106 if (w == NULL || w->enable == 0) 3107 continue; 3108 if (!(w->pflags & HDA_ADC_RECSEL)) 3109 continue; 3110 for (j = 0; j < w->nconns; j++) { 3111 cw = hdac_widget_get(devinfo, w->conns[j]); 3112 if (cw == NULL || cw->enable == 0) 3113 continue; 3114 if ((target == SOUND_MASK_VOLUME && 3115 cw->type != 3116 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3117 (target != SOUND_MASK_VOLUME && 3118 cw->type == 3119 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3120 continue; 3121 if (cw->ctlflags & target) { 3122 hdac_widget_connection_select(w, j); 3123 ret = target; 3124 j += w->nconns; 3125 } 3126 } 3127 } 3128 3129 hdac_unlock(sc); 3130 3131 return (ret); 3132} 3133 3134static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3135 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3136 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3137 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3138 { 0, 0 } 3139}; 3140MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3141 3142/**************************************************************************** 3143 * int hdac_attach(device_t) 3144 * 3145 * Attach the device into the kernel. Interrupts usually won't be enabled 3146 * when this function is called. Setup everything that doesn't require 3147 * interrupts and defer probing of codecs until interrupts are enabled. 3148 ****************************************************************************/ 3149static int 3150hdac_attach(device_t dev) 3151{ 3152 struct hdac_softc *sc; 3153 int result; 3154 int i = 0; 3155 3156 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3157 if (sc == NULL) { 3158 device_printf(dev, "cannot allocate softc\n"); 3159 return (ENOMEM); 3160 } 3161 3162 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3163 if (sc->lock == NULL) { 3164 device_printf(dev, "mutex creation failed\n"); 3165 free(sc, M_DEVBUF); 3166 return (ENOMEM); 3167 } 3168 3169 sc->dev = dev; 3170 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3171 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3172 3173 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3174 /* Screw nx6325 - subdevice/subvendor swapped */ 3175 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3176 } 3177 3178 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3179 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3180 3181 sc->poll_ticks = 1; 3182 if (resource_int_value(device_get_name(sc->dev), 3183 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3184 sc->polling = 1; 3185 else 3186 sc->polling = 0; 3187 3188 sc->chan_size = pcm_getbuffersize(dev, 3189 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3190 3191 if (resource_int_value(device_get_name(sc->dev), 3192 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3193 i &= ~0x7f; 3194 if (i < 0x80) 3195 i = 0x80; 3196 sc->chan_blkcnt = sc->chan_size / i; 3197 i = 0; 3198 while (sc->chan_blkcnt >> i) 3199 i++; 3200 sc->chan_blkcnt = 1 << (i - 1); 3201 if (sc->chan_blkcnt < HDA_BDL_MIN) 3202 sc->chan_blkcnt = HDA_BDL_MIN; 3203 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3204 sc->chan_blkcnt = HDA_BDL_MAX; 3205 } else 3206 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3207 3208 result = bus_dma_tag_create(NULL, /* parent */ 3209 HDAC_DMA_ALIGNMENT, /* alignment */ 3210 0, /* boundary */ 3211 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3212 BUS_SPACE_MAXADDR, /* highaddr */ 3213 NULL, /* filtfunc */ 3214 NULL, /* fistfuncarg */ 3215 sc->chan_size, /* maxsize */ 3216 1, /* nsegments */ 3217 sc->chan_size, /* maxsegsz */ 3218 0, /* flags */ 3219 NULL, /* lockfunc */ 3220 NULL, /* lockfuncarg */ 3221 &sc->chan_dmat); /* dmat */ 3222 if (result != 0) { 3223 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3224 __func__, result); 3225 snd_mtxfree(sc->lock); 3226 free(sc, M_DEVBUF); 3227 return (ENXIO); 3228 } 3229 3230 3231 sc->hdabus = NULL; 3232 for (i = 0; i < HDAC_CODEC_MAX; i++) 3233 sc->codecs[i] = NULL; 3234 3235 pci_enable_busmaster(dev); 3236 3237 /* Allocate resources */ 3238 result = hdac_mem_alloc(sc); 3239 if (result != 0) 3240 goto hdac_attach_fail; 3241 result = hdac_irq_alloc(sc); 3242 if (result != 0) 3243 goto hdac_attach_fail; 3244 3245 /* Get Capabilities */ 3246 result = hdac_get_capabilities(sc); 3247 if (result != 0) 3248 goto hdac_attach_fail; 3249 3250 /* Allocate CORB and RIRB dma memory */ 3251 result = hdac_dma_alloc(sc, &sc->corb_dma, 3252 sc->corb_size * sizeof(uint32_t)); 3253 if (result != 0) 3254 goto hdac_attach_fail; 3255 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3256 sc->rirb_size * sizeof(struct hdac_rirb)); 3257 if (result != 0) 3258 goto hdac_attach_fail; 3259 3260 /* Quiesce everything */ 3261 hdac_reset(sc); 3262 3263 /* Disable PCI-Express QOS */ 3264 pci_write_config(sc->dev, 0x44, 3265 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3266 3267 /* Initialize the CORB and RIRB */ 3268 hdac_corb_init(sc); 3269 hdac_rirb_init(sc); 3270 3271 /* Defer remaining of initialization until interrupts are enabled */ 3272 sc->intrhook.ich_func = hdac_attach2; 3273 sc->intrhook.ich_arg = (void *)sc; 3274 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3275 sc->intrhook.ich_func = NULL; 3276 hdac_attach2((void *)sc); 3277 } 3278 3279 return (0); 3280 3281hdac_attach_fail: 3282 hdac_dma_free(&sc->rirb_dma); 3283 hdac_dma_free(&sc->corb_dma); 3284 hdac_irq_free(sc); 3285 hdac_mem_free(sc); 3286 snd_mtxfree(sc->lock); 3287 free(sc, M_DEVBUF); 3288 3289 return (ENXIO); 3290} 3291 3292static void 3293hdac_audio_parse(struct hdac_devinfo *devinfo) 3294{ 3295 struct hdac_softc *sc = devinfo->codec->sc; 3296 struct hdac_widget *w; 3297 uint32_t res; 3298 int i; 3299 nid_t cad, nid; 3300 3301 cad = devinfo->codec->cad; 3302 nid = devinfo->nid; 3303 3304 hdac_command(sc, 3305 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3306 3307 DELAY(100); 3308 3309 res = hdac_command(sc, 3310 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3311 3312 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3313 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3314 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3315 3316 HDA_BOOTVERBOSE( 3317 device_printf(sc->dev, " Vendor: 0x%08x\n", 3318 devinfo->vendor_id); 3319 device_printf(sc->dev, " Device: 0x%08x\n", 3320 devinfo->device_id); 3321 device_printf(sc->dev, " Revision: 0x%08x\n", 3322 devinfo->revision_id); 3323 device_printf(sc->dev, " Stepping: 0x%08x\n", 3324 devinfo->stepping_id); 3325 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3326 sc->pci_subvendor); 3327 device_printf(sc->dev, " Nodes: start=%d " 3328 "endnode=%d total=%d\n", 3329 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3330 ); 3331 3332 res = hdac_command(sc, 3333 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3334 cad); 3335 devinfo->function.audio.supp_stream_formats = res; 3336 3337 res = hdac_command(sc, 3338 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3339 cad); 3340 devinfo->function.audio.supp_pcm_size_rate = res; 3341 3342 res = hdac_command(sc, 3343 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3344 cad); 3345 devinfo->function.audio.outamp_cap = res; 3346 3347 res = hdac_command(sc, 3348 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3349 cad); 3350 devinfo->function.audio.inamp_cap = res; 3351 3352 if (devinfo->nodecnt > 0) { 3353 hdac_unlock(sc); 3354 devinfo->widget = (struct hdac_widget *)malloc( 3355 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3356 M_NOWAIT | M_ZERO); 3357 hdac_lock(sc); 3358 } else 3359 devinfo->widget = NULL; 3360 3361 if (devinfo->widget == NULL) { 3362 device_printf(sc->dev, "unable to allocate widgets!\n"); 3363 devinfo->endnode = devinfo->startnode; 3364 devinfo->nodecnt = 0; 3365 return; 3366 } 3367 3368 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3369 w = hdac_widget_get(devinfo, i); 3370 if (w == NULL) 3371 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3372 else { 3373 w->devinfo = devinfo; 3374 w->nid = i; 3375 w->enable = 1; 3376 w->selconn = -1; 3377 w->pflags = 0; 3378 w->ctlflags = 0; 3379 w->param.eapdbtl = HDAC_INVALID; 3380 hdac_widget_parse(w); 3381 } 3382 } 3383} 3384 3385static void 3386hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3387{ 3388 struct hdac_softc *sc = devinfo->codec->sc; 3389 struct hdac_audio_ctl *ctls; 3390 struct hdac_widget *w, *cw; 3391 int i, j, cnt, max, ocap, icap; 3392 int mute, offset, step, size; 3393 3394 /* XXX This is redundant */ 3395 max = 0; 3396 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3397 w = hdac_widget_get(devinfo, i); 3398 if (w == NULL || w->enable == 0) 3399 continue; 3400 if (w->param.outamp_cap != 0) 3401 max++; 3402 if (w->param.inamp_cap != 0) { 3403 switch (w->type) { 3404 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3405 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3406 for (j = 0; j < w->nconns; j++) { 3407 cw = hdac_widget_get(devinfo, 3408 w->conns[j]); 3409 if (cw == NULL || cw->enable == 0) 3410 continue; 3411 max++; 3412 } 3413 break; 3414 default: 3415 max++; 3416 break; 3417 } 3418 } 3419 } 3420 3421 devinfo->function.audio.ctlcnt = max; 3422 3423 if (max < 1) 3424 return; 3425 3426 hdac_unlock(sc); 3427 ctls = (struct hdac_audio_ctl *)malloc( 3428 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3429 hdac_lock(sc); 3430 3431 if (ctls == NULL) { 3432 /* Blekh! */ 3433 device_printf(sc->dev, "unable to allocate ctls!\n"); 3434 devinfo->function.audio.ctlcnt = 0; 3435 return; 3436 } 3437 3438 cnt = 0; 3439 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3440 if (cnt >= max) { 3441 device_printf(sc->dev, "%s: Ctl overflow!\n", 3442 __func__); 3443 break; 3444 } 3445 w = hdac_widget_get(devinfo, i); 3446 if (w == NULL || w->enable == 0) 3447 continue; 3448 ocap = w->param.outamp_cap; 3449 icap = w->param.inamp_cap; 3450 if (ocap != 0) { 3451 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3452 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3453 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3454 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3455 /*if (offset > step) { 3456 HDA_BOOTVERBOSE( 3457 device_printf(sc->dev, 3458 "HDA_DEBUG: BUGGY outamp: nid=%d " 3459 "[offset=%d > step=%d]\n", 3460 w->nid, offset, step); 3461 ); 3462 offset = step; 3463 }*/ 3464 ctls[cnt].enable = 1; 3465 ctls[cnt].widget = w; 3466 ctls[cnt].mute = mute; 3467 ctls[cnt].step = step; 3468 ctls[cnt].size = size; 3469 ctls[cnt].offset = offset; 3470 ctls[cnt].left = offset; 3471 ctls[cnt].right = offset; 3472 ctls[cnt++].dir = HDA_CTL_OUT; 3473 } 3474 3475 if (icap != 0) { 3476 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3477 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3478 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3479 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3480 /*if (offset > step) { 3481 HDA_BOOTVERBOSE( 3482 device_printf(sc->dev, 3483 "HDA_DEBUG: BUGGY inamp: nid=%d " 3484 "[offset=%d > step=%d]\n", 3485 w->nid, offset, step); 3486 ); 3487 offset = step; 3488 }*/ 3489 switch (w->type) { 3490 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3491 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3492 for (j = 0; j < w->nconns; j++) { 3493 if (cnt >= max) { 3494 device_printf(sc->dev, 3495 "%s: Ctl overflow!\n", 3496 __func__); 3497 break; 3498 } 3499 cw = hdac_widget_get(devinfo, 3500 w->conns[j]); 3501 if (cw == NULL || cw->enable == 0) 3502 continue; 3503 ctls[cnt].enable = 1; 3504 ctls[cnt].widget = w; 3505 ctls[cnt].childwidget = cw; 3506 ctls[cnt].index = j; 3507 ctls[cnt].mute = mute; 3508 ctls[cnt].step = step; 3509 ctls[cnt].size = size; 3510 ctls[cnt].offset = offset; 3511 ctls[cnt].left = offset; 3512 ctls[cnt].right = offset; 3513 ctls[cnt++].dir = HDA_CTL_IN; 3514 } 3515 break; 3516 default: 3517 if (cnt >= max) { 3518 device_printf(sc->dev, 3519 "%s: Ctl overflow!\n", 3520 __func__); 3521 break; 3522 } 3523 ctls[cnt].enable = 1; 3524 ctls[cnt].widget = w; 3525 ctls[cnt].mute = mute; 3526 ctls[cnt].step = step; 3527 ctls[cnt].size = size; 3528 ctls[cnt].offset = offset; 3529 ctls[cnt].left = offset; 3530 ctls[cnt].right = offset; 3531 ctls[cnt++].dir = HDA_CTL_IN; 3532 break; 3533 } 3534 } 3535 } 3536 3537 devinfo->function.audio.ctl = ctls; 3538} 3539 3540static const struct { 3541 uint32_t model; 3542 uint32_t id; 3543 uint32_t set, unset; 3544} hdac_quirks[] = { 3545 /* 3546 * XXX Force stereo quirk. Monoural recording / playback 3547 * on few codecs (especially ALC880) seems broken or 3548 * perhaps unsupported. 3549 */ 3550 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3551 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3552 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3553 HDA_QUIRK_GPIO0, 0 }, 3554 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3555 HDA_QUIRK_GPIO0, 0 }, 3556 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3557 HDA_QUIRK_GPIO0, 0 }, 3558 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3559 HDA_QUIRK_EAPDINV, 0 }, 3560 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3561 HDA_QUIRK_EAPDINV, 0 }, 3562 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3563 HDA_QUIRK_GPIO1, 0 }, 3564 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3565 HDA_QUIRK_EAPDINV, 0 }, 3566 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3567 HDA_QUIRK_EAPDINV, 0 }, 3568 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3569 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3570 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3571 0, HDA_QUIRK_FORCESTEREO }, 3572 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3573 HDA_QUIRK_SOFTPCMVOL, 0 } 3574}; 3575#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3576 3577static void 3578hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3579{ 3580 struct hdac_widget *w; 3581 struct hdac_audio_ctl *ctl; 3582 uint32_t id, subvendor; 3583 int i; 3584 3585 id = hdac_codec_id(devinfo); 3586 subvendor = devinfo->codec->sc->pci_subvendor; 3587 3588 /* 3589 * Quirks 3590 */ 3591 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3592 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3593 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3594 continue; 3595 if (hdac_quirks[i].set != 0) 3596 devinfo->function.audio.quirks |= 3597 hdac_quirks[i].set; 3598 if (hdac_quirks[i].unset != 0) 3599 devinfo->function.audio.quirks &= 3600 ~(hdac_quirks[i].unset); 3601 } 3602 3603 switch (id) { 3604 case HDA_CODEC_ALC260: 3605 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3606 w = hdac_widget_get(devinfo, i); 3607 if (w == NULL || w->enable == 0) 3608 continue; 3609 if (w->type != 3610 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3611 continue; 3612 if (w->nid != 5) 3613 w->enable = 0; 3614 } 3615 if (subvendor == HP_XW4300_SUBVENDOR) { 3616 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3617 if (ctl != NULL && ctl->widget != NULL) { 3618 ctl->ossmask = SOUND_MASK_SPEAKER; 3619 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3620 } 3621 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3622 if (ctl != NULL && ctl->widget != NULL) { 3623 ctl->ossmask = SOUND_MASK_SPEAKER; 3624 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3625 } 3626 } 3627 break; 3628 case HDA_CODEC_ALC861: 3629 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3630 if (ctl != NULL) 3631 ctl->muted = HDA_AMP_MUTE_ALL; 3632 break; 3633 case HDA_CODEC_ALC880: 3634 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3635 w = hdac_widget_get(devinfo, i); 3636 if (w == NULL || w->enable == 0) 3637 continue; 3638 if (w->type == 3639 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3640 w->nid != 9 && w->nid != 29) { 3641 w->enable = 0; 3642 } else if (w->type != 3643 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3644 w->nid == 29) { 3645 w->type = 3646 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3647 w->param.widget_cap &= 3648 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3649 w->param.widget_cap |= 3650 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3651 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3652 strlcpy(w->name, "beep widget", sizeof(w->name)); 3653 } 3654 } 3655 break; 3656 case HDA_CODEC_AD1981HD: 3657 w = hdac_widget_get(devinfo, 11); 3658 if (w != NULL && w->enable != 0 && w->nconns > 3) 3659 w->selconn = 3; 3660 if (subvendor == IBM_M52_SUBVENDOR) { 3661 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3662 if (ctl != NULL) 3663 ctl->ossmask = SOUND_MASK_SPEAKER; 3664 } 3665 break; 3666 case HDA_CODEC_AD1986A: 3667 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3668 w = hdac_widget_get(devinfo, i); 3669 if (w == NULL || w->enable == 0) 3670 continue; 3671 if (w->type != 3672 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3673 continue; 3674 if (w->nid != 3) 3675 w->enable = 0; 3676 } 3677 break; 3678 case HDA_CODEC_STAC9221: 3679 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3680 w = hdac_widget_get(devinfo, i); 3681 if (w == NULL || w->enable == 0) 3682 continue; 3683 if (w->type != 3684 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3685 continue; 3686 if (w->nid != 2) 3687 w->enable = 0; 3688 } 3689 break; 3690 case HDA_CODEC_STAC9221D: 3691 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3692 w = hdac_widget_get(devinfo, i); 3693 if (w == NULL || w->enable == 0) 3694 continue; 3695 if (w->type == 3696 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3697 w->nid != 6) 3698 w->enable = 0; 3699 3700 } 3701 break; 3702 default: 3703 break; 3704 } 3705} 3706 3707static int 3708hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3709{ 3710 int *dev = &devinfo->function.audio.ossidx; 3711 3712 while (*dev < SOUND_MIXER_NRDEVICES) { 3713 switch (*dev) { 3714 case SOUND_MIXER_VOLUME: 3715 case SOUND_MIXER_BASS: 3716 case SOUND_MIXER_TREBLE: 3717 case SOUND_MIXER_PCM: 3718 case SOUND_MIXER_SPEAKER: 3719 case SOUND_MIXER_LINE: 3720 case SOUND_MIXER_MIC: 3721 case SOUND_MIXER_CD: 3722 case SOUND_MIXER_RECLEV: 3723 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3724 (*dev)++; 3725 break; 3726 default: 3727 return (*dev)++; 3728 break; 3729 } 3730 } 3731 3732 return (-1); 3733} 3734 3735static int 3736hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3737{ 3738 struct hdac_widget *w; 3739 int i, ret = 0; 3740 3741 if (depth > HDA_PARSE_MAXDEPTH) 3742 return (0); 3743 w = hdac_widget_get(devinfo, nid); 3744 if (w == NULL || w->enable == 0) 3745 return (0); 3746 switch (w->type) { 3747 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3748 w->pflags |= HDA_DAC_PATH; 3749 ret = 1; 3750 break; 3751 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3752 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3753 for (i = 0; i < w->nconns; i++) { 3754 if (hdac_widget_find_dac_path(devinfo, 3755 w->conns[i], depth + 1) != 0) { 3756 if (w->selconn == -1) 3757 w->selconn = i; 3758 ret = 1; 3759 w->pflags |= HDA_DAC_PATH; 3760 } 3761 } 3762 break; 3763 default: 3764 break; 3765 } 3766 return (ret); 3767} 3768 3769static int 3770hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3771{ 3772 struct hdac_widget *w; 3773 int i, conndev, ret = 0; 3774 3775 if (depth > HDA_PARSE_MAXDEPTH) 3776 return (0); 3777 w = hdac_widget_get(devinfo, nid); 3778 if (w == NULL || w->enable == 0) 3779 return (0); 3780 switch (w->type) { 3781 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3782 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3783 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3784 for (i = 0; i < w->nconns; i++) { 3785 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3786 depth + 1) != 0) { 3787 if (w->selconn == -1) 3788 w->selconn = i; 3789 w->pflags |= HDA_ADC_PATH; 3790 ret = 1; 3791 } 3792 } 3793 break; 3794 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3795 conndev = w->wclass.pin.config & 3796 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3797 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3798 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3799 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3800 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3801 w->pflags |= HDA_ADC_PATH; 3802 ret = 1; 3803 } 3804 break; 3805 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3806 if (w->pflags & HDA_DAC_PATH) { 3807 w->pflags |= HDA_ADC_PATH; 3808 ret = 1; 3809 } 3810 break;*/ 3811 default: 3812 break; 3813 } 3814 return (ret); 3815} 3816 3817static uint32_t 3818hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3819 nid_t nid, nid_t pnid, int index, int depth) 3820{ 3821 struct hdac_widget *w, *pw; 3822 struct hdac_audio_ctl *ctl; 3823 uint32_t fl = 0; 3824 int i, ossdev, conndev, strategy; 3825 3826 if (depth > HDA_PARSE_MAXDEPTH) 3827 return (0); 3828 3829 w = hdac_widget_get(devinfo, nid); 3830 if (w == NULL || w->enable == 0) 3831 return (0); 3832 3833 pw = hdac_widget_get(devinfo, pnid); 3834 strategy = devinfo->function.audio.parsing_strategy; 3835 3836 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3837 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3838 for (i = 0; i < w->nconns; i++) { 3839 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3840 w->nid, i, depth + 1); 3841 } 3842 w->ctlflags |= fl; 3843 return (fl); 3844 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3845 (w->pflags & HDA_DAC_PATH)) { 3846 i = 0; 3847 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3848 if (ctl->enable == 0 || ctl->widget == NULL) 3849 continue; 3850 /* XXX This should be compressed! */ 3851 if ((ctl->widget->nid == w->nid) || 3852 (ctl->widget->nid == pnid && ctl->index == index && 3853 (ctl->dir & HDA_CTL_IN)) || 3854 (ctl->widget->nid == pnid && pw != NULL && 3855 pw->type == 3856 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3857 (pw->nconns < 2 || pw->selconn == index || 3858 pw->selconn == -1) && 3859 (ctl->dir & HDA_CTL_OUT)) || 3860 (strategy == HDA_PARSE_DIRECT && 3861 ctl->widget->nid == w->nid)) { 3862 /*if (pw != NULL && pw->selconn == -1) 3863 pw->selconn = index; 3864 fl |= SOUND_MASK_VOLUME; 3865 fl |= SOUND_MASK_PCM; 3866 ctl->ossmask |= SOUND_MASK_VOLUME; 3867 ctl->ossmask |= SOUND_MASK_PCM; 3868 ctl->ossdev = SOUND_MIXER_PCM;*/ 3869 if (!(w->ctlflags & SOUND_MASK_PCM) || 3870 (pw != NULL && 3871 !(pw->ctlflags & SOUND_MASK_PCM))) { 3872 fl |= SOUND_MASK_VOLUME; 3873 fl |= SOUND_MASK_PCM; 3874 ctl->ossmask |= SOUND_MASK_VOLUME; 3875 ctl->ossmask |= SOUND_MASK_PCM; 3876 ctl->ossdev = SOUND_MIXER_PCM; 3877 w->ctlflags |= SOUND_MASK_VOLUME; 3878 w->ctlflags |= SOUND_MASK_PCM; 3879 if (pw != NULL) { 3880 if (pw->selconn == -1) 3881 pw->selconn = index; 3882 pw->ctlflags |= 3883 SOUND_MASK_VOLUME; 3884 pw->ctlflags |= 3885 SOUND_MASK_PCM; 3886 } 3887 } 3888 } 3889 } 3890 w->ctlflags |= fl; 3891 return (fl); 3892 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3893 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3894 (w->pflags & HDA_ADC_PATH)) { 3895 conndev = w->wclass.pin.config & 3896 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3897 i = 0; 3898 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3899 if (ctl->enable == 0 || ctl->widget == NULL) 3900 continue; 3901 /* XXX This should be compressed! */ 3902 if (((ctl->widget->nid == pnid && ctl->index == index && 3903 (ctl->dir & HDA_CTL_IN)) || 3904 (ctl->widget->nid == pnid && pw != NULL && 3905 pw->type == 3906 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3907 (pw->nconns < 2 || pw->selconn == index || 3908 pw->selconn == -1) && 3909 (ctl->dir & HDA_CTL_OUT)) || 3910 (strategy == HDA_PARSE_DIRECT && 3911 ctl->widget->nid == w->nid)) && 3912 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3913 if (pw != NULL && pw->selconn == -1) 3914 pw->selconn = index; 3915 ossdev = 0; 3916 switch (conndev) { 3917 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3918 ossdev = SOUND_MIXER_MIC; 3919 break; 3920 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3921 ossdev = SOUND_MIXER_LINE; 3922 break; 3923 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3924 ossdev = SOUND_MIXER_CD; 3925 break; 3926 default: 3927 ossdev = 3928 hdac_audio_ctl_ossmixer_getnextdev( 3929 devinfo); 3930 if (ossdev < 0) 3931 ossdev = 0; 3932 break; 3933 } 3934 if (strategy == HDA_PARSE_MIXER) { 3935 fl |= SOUND_MASK_VOLUME; 3936 ctl->ossmask |= SOUND_MASK_VOLUME; 3937 } 3938 fl |= 1 << ossdev; 3939 ctl->ossmask |= 1 << ossdev; 3940 ctl->ossdev = ossdev; 3941 } 3942 } 3943 w->ctlflags |= fl; 3944 return (fl); 3945 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3946 i = 0; 3947 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3948 if (ctl->enable == 0 || ctl->widget == NULL) 3949 continue; 3950 /* XXX This should be compressed! */ 3951 if (((ctl->widget->nid == pnid && ctl->index == index && 3952 (ctl->dir & HDA_CTL_IN)) || 3953 (ctl->widget->nid == pnid && pw != NULL && 3954 pw->type == 3955 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3956 (pw->nconns < 2 || pw->selconn == index || 3957 pw->selconn == -1) && 3958 (ctl->dir & HDA_CTL_OUT)) || 3959 (strategy == HDA_PARSE_DIRECT && 3960 ctl->widget->nid == w->nid)) && 3961 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3962 if (pw != NULL && pw->selconn == -1) 3963 pw->selconn = index; 3964 fl |= SOUND_MASK_VOLUME; 3965 fl |= SOUND_MASK_SPEAKER; 3966 ctl->ossmask |= SOUND_MASK_VOLUME; 3967 ctl->ossmask |= SOUND_MASK_SPEAKER; 3968 ctl->ossdev = SOUND_MIXER_SPEAKER; 3969 } 3970 } 3971 w->ctlflags |= fl; 3972 return (fl); 3973 } 3974 return (0); 3975} 3976 3977static uint32_t 3978hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3979{ 3980 struct hdac_widget *w, *cw; 3981 struct hdac_audio_ctl *ctl; 3982 uint32_t fl; 3983 int i; 3984 3985 if (depth > HDA_PARSE_MAXDEPTH) 3986 return (0); 3987 3988 w = hdac_widget_get(devinfo, nid); 3989 if (w == NULL || w->enable == 0) 3990 return (0); 3991 /*if (!(w->pflags & HDA_ADC_PATH)) 3992 return (0); 3993 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3994 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3995 return (0);*/ 3996 i = 0; 3997 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3998 if (ctl->enable == 0 || ctl->widget == NULL) 3999 continue; 4000 if (ctl->widget->nid == nid) { 4001 ctl->ossmask |= SOUND_MASK_RECLEV; 4002 w->ctlflags |= SOUND_MASK_RECLEV; 4003 return (SOUND_MASK_RECLEV); 4004 } 4005 } 4006 for (i = 0; i < w->nconns; i++) { 4007 cw = hdac_widget_get(devinfo, w->conns[i]); 4008 if (cw == NULL || cw->enable == 0) 4009 continue; 4010 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4011 continue; 4012 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4013 if (fl != 0) { 4014 cw->ctlflags |= fl; 4015 w->ctlflags |= fl; 4016 return (fl); 4017 } 4018 } 4019 return (0); 4020} 4021 4022static int 4023hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4024{ 4025 struct hdac_widget *w, *cw; 4026 int i, child = 0; 4027 4028 if (depth > HDA_PARSE_MAXDEPTH) 4029 return (0); 4030 4031 w = hdac_widget_get(devinfo, nid); 4032 if (w == NULL || w->enable == 0) 4033 return (0); 4034 /*if (!(w->pflags & HDA_ADC_PATH)) 4035 return (0); 4036 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4037 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4038 return (0);*/ 4039 /* XXX weak! */ 4040 for (i = 0; i < w->nconns; i++) { 4041 cw = hdac_widget_get(devinfo, w->conns[i]); 4042 if (cw == NULL) 4043 continue; 4044 if (++child > 1) { 4045 w->pflags |= HDA_ADC_RECSEL; 4046 return (1); 4047 } 4048 } 4049 for (i = 0; i < w->nconns; i++) { 4050 if (hdac_audio_ctl_recsel_build(devinfo, 4051 w->conns[i], depth + 1) != 0) 4052 return (1); 4053 } 4054 return (0); 4055} 4056 4057static int 4058hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4059{ 4060 struct hdac_widget *w, *cw; 4061 int i, j, conndev, found_dac = 0; 4062 int strategy; 4063 4064 strategy = devinfo->function.audio.parsing_strategy; 4065 4066 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4067 w = hdac_widget_get(devinfo, i); 4068 if (w == NULL || w->enable == 0) 4069 continue; 4070 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4071 continue; 4072 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4073 continue; 4074 conndev = w->wclass.pin.config & 4075 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4076 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4077 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4078 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4079 continue; 4080 for (j = 0; j < w->nconns; j++) { 4081 cw = hdac_widget_get(devinfo, w->conns[j]); 4082 if (cw == NULL || cw->enable == 0) 4083 continue; 4084 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4085 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4086 cw->type == 4087 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4088 continue; 4089 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4090 != 0) { 4091 if (w->selconn == -1) 4092 w->selconn = j; 4093 w->pflags |= HDA_DAC_PATH; 4094 found_dac++; 4095 } 4096 } 4097 } 4098 4099 return (found_dac); 4100} 4101 4102static void 4103hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4104{ 4105 struct hdac_widget *w; 4106 struct hdac_audio_ctl *ctl; 4107 int i, j, dacs, strategy; 4108 4109 /* Construct DAC path */ 4110 strategy = HDA_PARSE_MIXER; 4111 devinfo->function.audio.parsing_strategy = strategy; 4112 HDA_BOOTVERBOSE( 4113 device_printf(devinfo->codec->sc->dev, 4114 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4115 HDA_WIDGET_PARSER_REV); 4116 ); 4117 dacs = hdac_audio_build_tree_strategy(devinfo); 4118 if (dacs == 0) { 4119 HDA_BOOTVERBOSE( 4120 device_printf(devinfo->codec->sc->dev, 4121 "HDA_DEBUG: HWiP: 0 DAC path found! " 4122 "Retrying parser " 4123 "using HDA_PARSE_DIRECT strategy.\n"); 4124 ); 4125 strategy = HDA_PARSE_DIRECT; 4126 devinfo->function.audio.parsing_strategy = strategy; 4127 dacs = hdac_audio_build_tree_strategy(devinfo); 4128 } 4129 4130 HDA_BOOTVERBOSE( 4131 device_printf(devinfo->codec->sc->dev, 4132 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4133 "strategy.\n", 4134 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4135 ); 4136 4137 /* Construct ADC path */ 4138 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4139 w = hdac_widget_get(devinfo, i); 4140 if (w == NULL || w->enable == 0) 4141 continue; 4142 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4143 continue; 4144 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4145 } 4146 4147 /* Output mixers */ 4148 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4149 w = hdac_widget_get(devinfo, i); 4150 if (w == NULL || w->enable == 0) 4151 continue; 4152 if ((strategy == HDA_PARSE_MIXER && 4153 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4154 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4155 && (w->pflags & HDA_DAC_PATH)) || 4156 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4157 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4158 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4159 w->nid, devinfo->startnode - 1, 0, 0); 4160 } else if (w->type == 4161 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4162 j = 0; 4163 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4164 NULL) { 4165 if (ctl->enable == 0 || ctl->widget == NULL) 4166 continue; 4167 if (ctl->widget->nid != w->nid) 4168 continue; 4169 ctl->ossmask |= SOUND_MASK_VOLUME; 4170 ctl->ossmask |= SOUND_MASK_SPEAKER; 4171 ctl->ossdev = SOUND_MIXER_SPEAKER; 4172 w->ctlflags |= SOUND_MASK_VOLUME; 4173 w->ctlflags |= SOUND_MASK_SPEAKER; 4174 } 4175 } 4176 } 4177 4178 /* Input mixers (rec) */ 4179 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4180 w = hdac_widget_get(devinfo, i); 4181 if (w == NULL || w->enable == 0) 4182 continue; 4183 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4184 w->pflags & HDA_ADC_PATH)) 4185 continue; 4186 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4187 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4188 } 4189} 4190 4191#define HDA_COMMIT_CONN (1 << 0) 4192#define HDA_COMMIT_CTRL (1 << 1) 4193#define HDA_COMMIT_EAPD (1 << 2) 4194#define HDA_COMMIT_GPIO (1 << 3) 4195#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4196 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4197 4198static void 4199hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4200{ 4201 struct hdac_softc *sc = devinfo->codec->sc; 4202 struct hdac_widget *w; 4203 nid_t cad; 4204 int i; 4205 4206 if (!(cfl & HDA_COMMIT_ALL)) 4207 return; 4208 4209 cad = devinfo->codec->cad; 4210 4211 if (cfl & HDA_COMMIT_GPIO) { 4212 uint32_t gdata, gmask, gdir; 4213 int commitgpio = 0; 4214 4215 gdata = 0; 4216 gmask = 0; 4217 gdir = 0; 4218 4219 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4220 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4221 0x7e7, 0), cad); 4222 4223 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4224 commitgpio = 1; 4225 else { 4226 for (i = 0; i < HDA_GPIO_MAX; i++) { 4227 if (!(devinfo->function.audio.quirks & 4228 (1 << i))) 4229 continue; 4230 if (commitgpio == 0) { 4231 commitgpio = 1; 4232 gdata = hdac_command(sc, 4233 HDA_CMD_GET_GPIO_DATA(cad, 4234 devinfo->nid), cad); 4235 gmask = hdac_command(sc, 4236 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4237 devinfo->nid), cad); 4238 gdir = hdac_command(sc, 4239 HDA_CMD_GET_GPIO_DIRECTION(cad, 4240 devinfo->nid), cad); 4241 HDA_BOOTVERBOSE( 4242 device_printf(sc->dev, 4243 "GPIO init: data=0x%08x " 4244 "mask=0x%08x dir=0x%08x\n", 4245 gdata, gmask, gdir); 4246 ); 4247 } 4248 gdata |= 1 << i; 4249 gmask |= 1 << i; 4250 gdir |= 1 << i; 4251 } 4252 } 4253 4254 if (commitgpio != 0) { 4255 HDA_BOOTVERBOSE( 4256 device_printf(sc->dev, 4257 "GPIO commit: data=0x%08x mask=0x%08x " 4258 "dir=0x%08x\n", 4259 gdata, gmask, gdir); 4260 ); 4261 hdac_command(sc, 4262 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4263 gmask), cad); 4264 hdac_command(sc, 4265 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4266 gdir), cad); 4267 hdac_command(sc, 4268 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4269 gdata), cad); 4270 } 4271 } 4272 4273 for (i = 0; i < devinfo->nodecnt; i++) { 4274 w = &devinfo->widget[i]; 4275 if (w == NULL || w->enable == 0) 4276 continue; 4277 if (cfl & HDA_COMMIT_CONN) { 4278 if (w->selconn == -1) 4279 w->selconn = 0; 4280 if (w->nconns > 0) 4281 hdac_widget_connection_select(w, w->selconn); 4282 } 4283 if ((cfl & HDA_COMMIT_CTRL) && 4284 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4285 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4286 (HDA_DAC_PATH | HDA_ADC_PATH)) 4287 device_printf(sc->dev, "WARNING: node %d " 4288 "participate both for DAC/ADC!\n", w->nid); 4289 if (w->pflags & HDA_DAC_PATH) { 4290 w->wclass.pin.ctrl &= 4291 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4292 if ((w->wclass.pin.config & 4293 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4294 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4295 w->wclass.pin.ctrl &= 4296 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4297 } else if (w->pflags & HDA_ADC_PATH) { 4298 w->wclass.pin.ctrl &= 4299 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4300 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4301 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4302 uint32_t pincap = w->wclass.pin.cap; 4303 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4304 w->wclass.pin.ctrl |= 4305 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4306 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4307 ); 4308 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4309 w->wclass.pin.ctrl |= 4310 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4311 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4312 ); 4313 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4314 w->wclass.pin.ctrl |= 4315 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4316 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4317 ); 4318 } 4319 } else 4320 w->wclass.pin.ctrl &= ~( 4321 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4322 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4323 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4324 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4325 hdac_command(sc, 4326 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4327 w->wclass.pin.ctrl), cad); 4328 } 4329 if ((cfl & HDA_COMMIT_EAPD) && 4330 w->param.eapdbtl != HDAC_INVALID) { 4331 uint32_t val; 4332 4333 val = w->param.eapdbtl; 4334 if (devinfo->function.audio.quirks & 4335 HDA_QUIRK_EAPDINV) 4336 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4337 hdac_command(sc, 4338 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4339 val), cad); 4340 4341 } 4342 DELAY(1000); 4343 } 4344} 4345 4346static void 4347hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4348{ 4349 struct hdac_softc *sc = devinfo->codec->sc; 4350 struct hdac_audio_ctl *ctl; 4351 int i; 4352 4353 devinfo->function.audio.mvol = 100 | (100 << 8); 4354 i = 0; 4355 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4356 if (ctl->enable == 0 || ctl->widget == NULL) { 4357 HDA_BOOTVERBOSE( 4358 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4359 i, (ctl->widget != NULL) ? 4360 ctl->widget->nid : -1); 4361 if (ctl->childwidget != NULL) 4362 printf(" childnid=%d", 4363 ctl->childwidget->nid); 4364 if (ctl->widget == NULL) 4365 printf(" NULL WIDGET!"); 4366 printf(" DISABLED\n"); 4367 ); 4368 continue; 4369 } 4370 HDA_BOOTVERBOSE( 4371 if (ctl->ossmask == 0) { 4372 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4373 i, ctl->widget->nid); 4374 if (ctl->childwidget != NULL) 4375 printf(" childnid=%d", 4376 ctl->childwidget->nid); 4377 printf(" Bind to NONE\n"); 4378 } 4379 ); 4380 if (ctl->step > 0) { 4381 ctl->ossval = (ctl->left * 100) / ctl->step; 4382 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4383 } else 4384 ctl->ossval = 0; 4385 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4386 ctl->left, ctl->right); 4387 } 4388} 4389 4390static int 4391hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4392{ 4393 struct hdac_chan *ch; 4394 struct hdac_widget *w; 4395 uint32_t cap, fmtcap, pcmcap, path; 4396 int i, type, ret, max; 4397 4398 if (dir == PCMDIR_PLAY) { 4399 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4400 ch = &devinfo->codec->sc->play; 4401 path = HDA_DAC_PATH; 4402 } else { 4403 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4404 ch = &devinfo->codec->sc->rec; 4405 path = HDA_ADC_PATH; 4406 } 4407 4408 ch->caps = hdac_caps; 4409 ch->caps.fmtlist = ch->fmtlist; 4410 ch->bit16 = 1; 4411 ch->bit32 = 0; 4412 ch->pcmrates[0] = 48000; 4413 ch->pcmrates[1] = 0; 4414 4415 ret = 0; 4416 fmtcap = devinfo->function.audio.supp_stream_formats; 4417 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4418 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4419 4420 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4421 w = hdac_widget_get(devinfo, i); 4422 if (w == NULL || w->enable == 0 || w->type != type || 4423 !(w->pflags & path)) 4424 continue; 4425 cap = w->param.widget_cap; 4426 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4427 continue;*/ 4428 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4429 continue; 4430 cap = w->param.supp_stream_formats; 4431 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4432 } 4433 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4434 }*/ 4435 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4436 continue; 4437 if (ret == 0) { 4438 fmtcap = w->param.supp_stream_formats; 4439 pcmcap = w->param.supp_pcm_size_rate; 4440 } else { 4441 fmtcap &= w->param.supp_stream_formats; 4442 pcmcap &= w->param.supp_pcm_size_rate; 4443 } 4444 ch->io[ret++] = i; 4445 } 4446 ch->io[ret] = -1; 4447 4448 ch->supp_stream_formats = fmtcap; 4449 ch->supp_pcm_size_rate = pcmcap; 4450 4451 /* 4452 * 8bit = 0 4453 * 16bit = 1 4454 * 20bit = 2 4455 * 24bit = 3 4456 * 32bit = 4 4457 */ 4458 if (ret > 0) { 4459 cap = pcmcap; 4460 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4461 ch->bit16 = 1; 4462 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4463 ch->bit16 = 0; 4464 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4465 ch->bit32 = 4; 4466 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4467 ch->bit32 = 3; 4468 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4469 ch->bit32 = 2; 4470 i = 0; 4471 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4472 ch->fmtlist[i++] = AFMT_S16_LE; 4473 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4474 if (ch->bit32 > 0) { 4475 if (!(devinfo->function.audio.quirks & 4476 HDA_QUIRK_FORCESTEREO)) 4477 ch->fmtlist[i++] = AFMT_S32_LE; 4478 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4479 } 4480 ch->fmtlist[i] = 0; 4481 i = 0; 4482 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4483 ch->pcmrates[i++] = 8000; 4484 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4485 ch->pcmrates[i++] = 11025; 4486 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4487 ch->pcmrates[i++] = 16000; 4488 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4489 ch->pcmrates[i++] = 22050; 4490 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4491 ch->pcmrates[i++] = 32000; 4492 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4493 ch->pcmrates[i++] = 44100; 4494 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4495 ch->pcmrates[i++] = 48000; 4496 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4497 ch->pcmrates[i++] = 88200; 4498 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4499 ch->pcmrates[i++] = 96000; 4500 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4501 ch->pcmrates[i++] = 176400; 4502 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4503 ch->pcmrates[i++] = 192000; 4504 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4505 ch->pcmrates[i] = 0; 4506 if (i > 0) { 4507 ch->caps.minspeed = ch->pcmrates[0]; 4508 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4509 } 4510 } 4511 4512 return (ret); 4513} 4514 4515static void 4516hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4517{ 4518 struct hdac_audio_ctl *ctl; 4519 struct hdac_softc *sc = devinfo->codec->sc; 4520 int i; 4521 uint32_t fl = 0; 4522 4523 4524 if (flag == 0) { 4525 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4526 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4527 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4528 } 4529 4530 i = 0; 4531 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4532 if (ctl->enable == 0 || ctl->widget == NULL || 4533 ctl->widget->enable == 0) 4534 continue; 4535 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4536 (flag != 0 && (ctl->ossmask & flag))) { 4537 if (banner != NULL) { 4538 device_printf(sc->dev, "\n"); 4539 device_printf(sc->dev, "%s\n", banner); 4540 } 4541 goto hdac_ctl_dump_it_all; 4542 } 4543 } 4544 4545 return; 4546 4547hdac_ctl_dump_it_all: 4548 i = 0; 4549 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4550 if (ctl->enable == 0 || ctl->widget == NULL || 4551 ctl->widget->enable == 0) 4552 continue; 4553 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4554 (flag != 0 && (ctl->ossmask & flag)))) 4555 continue; 4556 if (flag == 0) { 4557 device_printf(sc->dev, "\n"); 4558 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4559 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4560 } 4561 device_printf(sc->dev, " |\n"); 4562 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4563 ctl->widget->nid, ctl->index); 4564 if (ctl->childwidget != NULL) 4565 printf("(nid: %2d) ", ctl->childwidget->nid); 4566 else 4567 printf(" "); 4568 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4569 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4570 ctl->ossmask); 4571 } 4572} 4573 4574static void 4575hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4576{ 4577 uint32_t cap; 4578 4579 cap = fcap; 4580 if (cap != 0) { 4581 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4582 device_printf(sc->dev, " Format:"); 4583 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4584 printf(" AC3"); 4585 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4586 printf(" FLOAT32"); 4587 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4588 printf(" PCM"); 4589 printf("\n"); 4590 } 4591 cap = pcmcap; 4592 if (cap != 0) { 4593 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4594 device_printf(sc->dev, " PCM size:"); 4595 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4596 printf(" 8"); 4597 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4598 printf(" 16"); 4599 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4600 printf(" 20"); 4601 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4602 printf(" 24"); 4603 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4604 printf(" 32"); 4605 printf("\n"); 4606 device_printf(sc->dev, " PCM rate:"); 4607 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4608 printf(" 8"); 4609 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4610 printf(" 11"); 4611 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4612 printf(" 16"); 4613 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4614 printf(" 22"); 4615 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4616 printf(" 32"); 4617 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4618 printf(" 44"); 4619 printf(" 48"); 4620 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4621 printf(" 88"); 4622 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4623 printf(" 96"); 4624 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4625 printf(" 176"); 4626 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4627 printf(" 192"); 4628 printf("\n"); 4629 } 4630} 4631 4632static void 4633hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4634{ 4635 uint32_t pincap, wcap; 4636 4637 pincap = w->wclass.pin.cap; 4638 wcap = w->param.widget_cap; 4639 4640 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4641 device_printf(sc->dev, " "); 4642 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4643 printf(" ISC"); 4644 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4645 printf(" TRQD"); 4646 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4647 printf(" PDC"); 4648 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4649 printf(" HP"); 4650 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4651 printf(" OUT"); 4652 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4653 printf(" IN"); 4654 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4655 printf(" BAL"); 4656 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4657 printf(" VREF["); 4658 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4659 printf(" 50"); 4660 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4661 printf(" 80"); 4662 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4663 printf(" 100"); 4664 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4665 printf(" GROUND"); 4666 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4667 printf(" HIZ"); 4668 printf(" ]"); 4669 } 4670 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4671 printf(" EAPD"); 4672 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4673 printf(" : UNSOL"); 4674 printf("\n"); 4675 device_printf(sc->dev, " Pin config: 0x%08x\n", 4676 w->wclass.pin.config); 4677 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4678 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4679 printf(" HP"); 4680 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4681 printf(" IN"); 4682 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4683 printf(" OUT"); 4684 printf("\n"); 4685} 4686 4687static void 4688hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4689{ 4690 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4691 device_printf(sc->dev, " " 4692 "mute=%d step=%d size=%d offset=%d\n", 4693 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4694 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4695 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4696 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4697} 4698 4699static void 4700hdac_dump_nodes(struct hdac_devinfo *devinfo) 4701{ 4702 struct hdac_softc *sc = devinfo->codec->sc; 4703 struct hdac_widget *w, *cw; 4704 int i, j; 4705 4706 device_printf(sc->dev, "\n"); 4707 device_printf(sc->dev, "Default Parameter\n"); 4708 device_printf(sc->dev, "-----------------\n"); 4709 hdac_dump_audio_formats(sc, 4710 devinfo->function.audio.supp_stream_formats, 4711 devinfo->function.audio.supp_pcm_size_rate); 4712 device_printf(sc->dev, " IN amp: 0x%08x\n", 4713 devinfo->function.audio.inamp_cap); 4714 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4715 devinfo->function.audio.outamp_cap); 4716 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4717 w = hdac_widget_get(devinfo, i); 4718 if (w == NULL) { 4719 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4720 continue; 4721 } 4722 device_printf(sc->dev, "\n"); 4723 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4724 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4725 "DIGITAL" : "ANALOG", 4726 (w->enable == 0) ? " [DISABLED]" : ""); 4727 device_printf(sc->dev, " name: %s\n", w->name); 4728 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4729 w->param.widget_cap); 4730 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4731 w->pflags); 4732 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4733 w->ctlflags); 4734 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4735 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4736 hdac_dump_audio_formats(sc, 4737 w->param.supp_stream_formats, 4738 w->param.supp_pcm_size_rate); 4739 } else if (w->type == 4740 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4741 hdac_dump_pin(sc, w); 4742 if (w->param.eapdbtl != HDAC_INVALID) 4743 device_printf(sc->dev, " EAPD: 0x%08x\n", 4744 w->param.eapdbtl); 4745 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4746 w->param.outamp_cap != 0) 4747 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4748 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4749 w->param.inamp_cap != 0) 4750 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4751 device_printf(sc->dev, " connections: %d\n", w->nconns); 4752 for (j = 0; j < w->nconns; j++) { 4753 cw = hdac_widget_get(devinfo, w->conns[j]); 4754 device_printf(sc->dev, " |\n"); 4755 device_printf(sc->dev, " + <- nid=%d [%s]", 4756 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4757 if (cw == NULL) 4758 printf(" [UNKNOWN]"); 4759 else if (cw->enable == 0) 4760 printf(" [DISABLED]"); 4761 if (w->nconns > 1 && w->selconn == j && w->type != 4762 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4763 printf(" (selected)"); 4764 printf("\n"); 4765 } 4766 } 4767 4768} 4769 4770static int 4771hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4772{ 4773 struct hdac_widget *w, *cw; 4774 struct hdac_softc *sc = devinfo->codec->sc; 4775 int i; 4776 4777 if (depth > HDA_PARSE_MAXDEPTH) 4778 return (0); 4779 4780 w = hdac_widget_get(devinfo, nid); 4781 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4782 return (0); 4783 4784 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4785 device_printf(sc->dev, "\n"); 4786 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4787 device_printf(sc->dev, " ^\n"); 4788 device_printf(sc->dev, " |\n"); 4789 device_printf(sc->dev, " +-----<------+\n"); 4790 } else { 4791 device_printf(sc->dev, " ^\n"); 4792 device_printf(sc->dev, " |\n"); 4793 device_printf(sc->dev, " "); 4794 printf(" nid=%d [%s]\n", w->nid, w->name); 4795 } 4796 4797 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4798 return (1); 4799 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4800 for (i = 0; i < w->nconns; i++) { 4801 cw = hdac_widget_get(devinfo, w->conns[i]); 4802 if (cw == NULL || cw->enable == 0 || cw->type == 4803 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4804 continue; 4805 if (hdac_dump_dac_internal(devinfo, cw->nid, 4806 depth + 1) != 0) 4807 return (1); 4808 } 4809 } else if ((w->type == 4810 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4811 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4812 w->selconn > -1 && w->selconn < w->nconns) { 4813 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4814 depth + 1) != 0) 4815 return (1); 4816 } 4817 4818 return (0); 4819} 4820 4821static void 4822hdac_dump_dac(struct hdac_devinfo *devinfo) 4823{ 4824 struct hdac_widget *w; 4825 struct hdac_softc *sc = devinfo->codec->sc; 4826 int i, printed = 0; 4827 4828 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4829 w = hdac_widget_get(devinfo, i); 4830 if (w == NULL || w->enable == 0) 4831 continue; 4832 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4833 !(w->pflags & HDA_DAC_PATH)) 4834 continue; 4835 if (printed == 0) { 4836 printed = 1; 4837 device_printf(sc->dev, "\n"); 4838 device_printf(sc->dev, "Playback path:\n"); 4839 } 4840 hdac_dump_dac_internal(devinfo, w->nid, 0); 4841 } 4842} 4843 4844static void 4845hdac_dump_adc(struct hdac_devinfo *devinfo) 4846{ 4847 struct hdac_widget *w, *cw; 4848 struct hdac_softc *sc = devinfo->codec->sc; 4849 int i, j; 4850 int printed = 0; 4851 char ossdevs[256]; 4852 4853 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4854 w = hdac_widget_get(devinfo, i); 4855 if (w == NULL || w->enable == 0) 4856 continue; 4857 if (!(w->pflags & HDA_ADC_RECSEL)) 4858 continue; 4859 if (printed == 0) { 4860 printed = 1; 4861 device_printf(sc->dev, "\n"); 4862 device_printf(sc->dev, "Recording sources:\n"); 4863 } 4864 device_printf(sc->dev, "\n"); 4865 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4866 for (j = 0; j < w->nconns; j++) { 4867 cw = hdac_widget_get(devinfo, w->conns[j]); 4868 if (cw == NULL || cw->enable == 0) 4869 continue; 4870 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4871 ossdevs, sizeof(ossdevs)); 4872 device_printf(sc->dev, " |\n"); 4873 device_printf(sc->dev, " + <- nid=%d [%s]", 4874 cw->nid, cw->name); 4875 if (strlen(ossdevs) > 0) { 4876 printf(" [recsrc: %s]", ossdevs); 4877 } 4878 printf("\n"); 4879 } 4880 } 4881} 4882 4883static void 4884hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4885{ 4886 nid_t *nids; 4887 4888 if (pcnt > 0) { 4889 device_printf(sc->dev, "\n"); 4890 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4891 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4892 sc->play.supp_pcm_size_rate); 4893 device_printf(sc->dev, " DAC:"); 4894 for (nids = sc->play.io; *nids != -1; nids++) 4895 printf(" %d", *nids); 4896 printf("\n"); 4897 } 4898 4899 if (rcnt > 0) { 4900 device_printf(sc->dev, "\n"); 4901 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4902 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4903 sc->rec.supp_pcm_size_rate); 4904 device_printf(sc->dev, " ADC:"); 4905 for (nids = sc->rec.io; *nids != -1; nids++) 4906 printf(" %d", *nids); 4907 printf("\n"); 4908 } 4909} 4910 4911static void 4912hdac_release_resources(struct hdac_softc *sc) 4913{ 4914 struct hdac_devinfo *devinfo = NULL; 4915 device_t *devlist = NULL; 4916 int i, devcount; 4917 4918 if (sc == NULL) 4919 return; 4920 4921 hdac_lock(sc); 4922 if (sc->polling != 0) 4923 callout_stop(&sc->poll_hdac); 4924 hdac_reset(sc); 4925 hdac_unlock(sc); 4926 snd_mtxfree(sc->lock); 4927 4928 device_get_children(sc->dev, &devlist, &devcount); 4929 for (i = 0; devlist != NULL && i < devcount; i++) { 4930 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4931 if (devinfo == NULL) 4932 continue; 4933 if (devinfo->widget != NULL) 4934 free(devinfo->widget, M_HDAC); 4935 if (devinfo->node_type == 4936 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4937 devinfo->function.audio.ctl != NULL) 4938 free(devinfo->function.audio.ctl, M_HDAC); 4939 free(devinfo, M_HDAC); 4940 device_delete_child(sc->dev, devlist[i]); 4941 } 4942 if (devlist != NULL) 4943 free(devlist, M_TEMP); 4944 4945 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4946 if (sc->codecs[i] != NULL) 4947 free(sc->codecs[i], M_HDAC); 4948 sc->codecs[i] = NULL; 4949 } 4950 4951 hdac_dma_free(&sc->rirb_dma); 4952 hdac_dma_free(&sc->corb_dma); 4953 if (sc->play.blkcnt > 0) 4954 hdac_dma_free(&sc->play.bdl_dma); 4955 if (sc->rec.blkcnt > 0) 4956 hdac_dma_free(&sc->rec.bdl_dma); 4957 hdac_irq_free(sc); 4958 hdac_mem_free(sc); 4959 free(sc, M_DEVBUF); 4960 4961} 4962 4963/* This function surely going to make its way into upper level someday. */ 4964static void 4965hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4966{ 4967 const char *res = NULL; 4968 int i = 0, j, k, len, inv; 4969 4970 if (on != NULL) 4971 *on = 0; 4972 if (off != NULL) 4973 *off = 0; 4974 if (sc == NULL) 4975 return; 4976 if (resource_string_value(device_get_name(sc->dev), 4977 device_get_unit(sc->dev), "config", &res) != 0) 4978 return; 4979 if (!(res != NULL && strlen(res) > 0)) 4980 return; 4981 HDA_BOOTVERBOSE( 4982 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4983 ); 4984 for (;;) { 4985 while (res[i] != '\0' && 4986 (res[i] == ',' || isspace(res[i]) != 0)) 4987 i++; 4988 if (res[i] == '\0') { 4989 HDA_BOOTVERBOSE( 4990 printf("\n"); 4991 ); 4992 return; 4993 } 4994 j = i; 4995 while (res[j] != '\0' && 4996 !(res[j] == ',' || isspace(res[j]) != 0)) 4997 j++; 4998 len = j - i; 4999 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5000 inv = 2; 5001 else 5002 inv = 0; 5003 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5004 if (strncmp(res + i + inv, 5005 hdac_quirks_tab[k].key, len - inv) != 0) 5006 continue; 5007 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5008 break; 5009 HDA_BOOTVERBOSE( 5010 printf(" %s%s", (inv != 0) ? "no" : "", 5011 hdac_quirks_tab[k].key); 5012 ); 5013 if (inv == 0 && on != NULL) 5014 *on |= hdac_quirks_tab[k].value; 5015 else if (inv != 0 && off != NULL) 5016 *off |= hdac_quirks_tab[k].value; 5017 break; 5018 } 5019 i = j; 5020 } 5021} 5022 5023#ifdef SND_DYNSYSCTL 5024static int 5025sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5026{ 5027 struct hdac_softc *sc; 5028 struct hdac_devinfo *devinfo; 5029 device_t dev; 5030 uint32_t ctl; 5031 int err, val; 5032 5033 dev = oidp->oid_arg1; 5034 devinfo = pcm_getdevinfo(dev); 5035 if (devinfo == NULL || devinfo->codec == NULL || 5036 devinfo->codec->sc == NULL) 5037 return (EINVAL); 5038 sc = devinfo->codec->sc; 5039 hdac_lock(sc); 5040 val = sc->polling; 5041 hdac_unlock(sc); 5042 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5043 5044 if (err || req->newptr == NULL) 5045 return (err); 5046 if (val < 0 || val > 1) 5047 return (EINVAL); 5048 5049 hdac_lock(sc); 5050 if (val != sc->polling) { 5051 if (hda_chan_active(sc) != 0) 5052 err = EBUSY; 5053 else if (val == 0) { 5054 callout_stop(&sc->poll_hdac); 5055 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5056 sc->rirb_size / 2); 5057 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5058 ctl |= HDAC_RIRBCTL_RINTCTL; 5059 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5060 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5061 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5062 sc->polling = 0; 5063 DELAY(1000); 5064 } else { 5065 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5066 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5067 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5068 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5069 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5070 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5071 sc); 5072 sc->polling = 1; 5073 DELAY(1000); 5074 } 5075 } 5076 hdac_unlock(sc); 5077 5078 return (err); 5079} 5080#endif 5081 5082static void 5083hdac_attach2(void *arg) 5084{ 5085 struct hdac_softc *sc; 5086 struct hdac_widget *w; 5087 struct hdac_audio_ctl *ctl; 5088 uint32_t quirks_on, quirks_off; 5089 int pcnt, rcnt; 5090 int i; 5091 char status[SND_STATUSLEN]; 5092 device_t *devlist = NULL; 5093 int devcount; 5094 struct hdac_devinfo *devinfo = NULL; 5095 5096 sc = (struct hdac_softc *)arg; 5097 5098 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5099 5100 HDA_BOOTVERBOSE( 5101 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5102 quirks_on, quirks_off); 5103 ); 5104 5105 hdac_lock(sc); 5106 5107 /* Remove ourselves from the config hooks */ 5108 if (sc->intrhook.ich_func != NULL) { 5109 config_intrhook_disestablish(&sc->intrhook); 5110 sc->intrhook.ich_func = NULL; 5111 } 5112 5113 /* Start the corb and rirb engines */ 5114 HDA_BOOTVERBOSE( 5115 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5116 ); 5117 hdac_corb_start(sc); 5118 HDA_BOOTVERBOSE( 5119 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5120 ); 5121 hdac_rirb_start(sc); 5122 5123 HDA_BOOTVERBOSE( 5124 device_printf(sc->dev, 5125 "HDA_DEBUG: Enabling controller interrupt...\n"); 5126 ); 5127 if (sc->polling == 0) 5128 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5129 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5130 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5131 HDAC_GCTL_UNSOL); 5132 5133 DELAY(1000); 5134 5135 HDA_BOOTVERBOSE( 5136 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5137 ); 5138 hdac_scan_codecs(sc); 5139 5140 device_get_children(sc->dev, &devlist, &devcount); 5141 for (i = 0; devlist != NULL && i < devcount; i++) { 5142 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5143 if (devinfo != NULL && devinfo->node_type == 5144 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5145 break; 5146 } else 5147 devinfo = NULL; 5148 } 5149 if (devlist != NULL) 5150 free(devlist, M_TEMP); 5151 5152 if (devinfo == NULL) { 5153 hdac_unlock(sc); 5154 device_printf(sc->dev, "Audio Function Group not found!\n"); 5155 hdac_release_resources(sc); 5156 return; 5157 } 5158 5159 HDA_BOOTVERBOSE( 5160 device_printf(sc->dev, 5161 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5162 devinfo->nid, devinfo->codec->cad); 5163 ); 5164 hdac_audio_parse(devinfo); 5165 HDA_BOOTVERBOSE( 5166 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5167 ); 5168 hdac_audio_ctl_parse(devinfo); 5169 HDA_BOOTVERBOSE( 5170 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5171 ); 5172 hdac_vendor_patch_parse(devinfo); 5173 if (quirks_on != 0) 5174 devinfo->function.audio.quirks |= quirks_on; 5175 if (quirks_off != 0) 5176 devinfo->function.audio.quirks &= ~quirks_off; 5177 5178 /* XXX Disable all DIGITAL path. */ 5179 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5180 w = hdac_widget_get(devinfo, i); 5181 if (w == NULL) 5182 continue; 5183 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5184 w->enable = 0; 5185 continue; 5186 } 5187 /* XXX Disable useless pin ? */ 5188 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5189 (w->wclass.pin.config & 5190 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5191 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5192 w->enable = 0; 5193 } 5194 i = 0; 5195 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5196 if (ctl->widget == NULL) 5197 continue; 5198 w = ctl->widget; 5199 if (w->enable == 0) 5200 ctl->enable = 0; 5201 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5202 ctl->enable = 0; 5203 w = ctl->childwidget; 5204 if (w == NULL) 5205 continue; 5206 if (w->enable == 0 || 5207 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5208 ctl->enable = 0; 5209 } 5210 5211 HDA_BOOTVERBOSE( 5212 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5213 ); 5214 hdac_audio_build_tree(devinfo); 5215 5216 HDA_BOOTVERBOSE( 5217 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5218 ); 5219 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5220 HDA_BOOTVERBOSE( 5221 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5222 ); 5223 hdac_audio_ctl_commit(devinfo); 5224 5225 HDA_BOOTVERBOSE( 5226 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5227 ); 5228 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5229 HDA_BOOTVERBOSE( 5230 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5231 ); 5232 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5233 5234 hdac_unlock(sc); 5235 HDA_BOOTVERBOSE( 5236 device_printf(sc->dev, 5237 "HDA_DEBUG: OSS mixer initialization...\n"); 5238 ); 5239 5240 /* 5241 * There is no point of return after this. If the driver failed, 5242 * so be it. Let the detach procedure do all the cleanup. 5243 */ 5244 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5245 device_printf(sc->dev, "Can't register mixer\n"); 5246 5247 if (pcnt > 0) 5248 pcnt = 1; 5249 if (rcnt > 0) 5250 rcnt = 1; 5251 5252 HDA_BOOTVERBOSE( 5253 device_printf(sc->dev, 5254 "HDA_DEBUG: Registering PCM channels...\n"); 5255 ); 5256 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5257 device_printf(sc->dev, "Can't register PCM\n"); 5258 5259 sc->registered++; 5260 5261 for (i = 0; i < pcnt; i++) 5262 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5263 for (i = 0; i < rcnt; i++) 5264 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5265 5266#ifdef SND_DYNSYSCTL 5267 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5268 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5269 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5270 sysctl_hdac_polling, "I", "Enable polling mode"); 5271#endif 5272 5273 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5274 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5275 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5276 pcm_setstatus(sc->dev, status); 5277 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5278 HDA_BOOTVERBOSE( 5279 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5280 hdac_codec_id(devinfo)); 5281 ); 5282 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5283 HDA_DRV_TEST_REV); 5284 5285 HDA_BOOTVERBOSE( 5286 if (devinfo->function.audio.quirks != 0) { 5287 device_printf(sc->dev, "\n"); 5288 device_printf(sc->dev, "HDA config/quirks:"); 5289 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5290 if (devinfo->function.audio.quirks & 5291 hdac_quirks_tab[i].value) 5292 printf(" %s", hdac_quirks_tab[i].key); 5293 } 5294 printf("\n"); 5295 } 5296 device_printf(sc->dev, "\n"); 5297 device_printf(sc->dev, "+-------------------+\n"); 5298 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5299 device_printf(sc->dev, "+-------------------+\n"); 5300 hdac_dump_nodes(devinfo); 5301 device_printf(sc->dev, "\n"); 5302 device_printf(sc->dev, "+------------------------+\n"); 5303 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5304 device_printf(sc->dev, "+------------------------+\n"); 5305 device_printf(sc->dev, "\n"); 5306 i = 0; 5307 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5308 device_printf(sc->dev, "%3d: nid=%d", i, 5309 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5310 if (ctl->childwidget != NULL) 5311 printf(" cnid=%d", ctl->childwidget->nid); 5312 printf(" dir=0x%x index=%d " 5313 "ossmask=0x%08x ossdev=%d%s\n", 5314 ctl->dir, ctl->index, 5315 ctl->ossmask, ctl->ossdev, 5316 (ctl->enable == 0) ? " [DISABLED]" : ""); 5317 } 5318 device_printf(sc->dev, "\n"); 5319 device_printf(sc->dev, "+-----------------------------------+\n"); 5320 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5321 device_printf(sc->dev, "+-----------------------------------+\n"); 5322 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5323 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5324 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5325 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5326 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5327 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5328 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5329 hdac_dump_ctls(devinfo, NULL, 0); 5330 hdac_dump_dac(devinfo); 5331 hdac_dump_adc(devinfo); 5332 device_printf(sc->dev, "\n"); 5333 device_printf(sc->dev, "+--------------------------------------+\n"); 5334 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5335 device_printf(sc->dev, "+--------------------------------------+\n"); 5336 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5337 ); 5338 5339 if (sc->polling != 0) { 5340 hdac_lock(sc); 5341 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5342 hdac_unlock(sc); 5343 } 5344} 5345 5346/**************************************************************************** 5347 * int hdac_detach(device_t) 5348 * 5349 * Detach and free up resources utilized by the hdac device. 5350 ****************************************************************************/ 5351static int 5352hdac_detach(device_t dev) 5353{ 5354 struct hdac_softc *sc = NULL; 5355 struct hdac_devinfo *devinfo = NULL; 5356 int err; 5357 5358 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5359 if (devinfo != NULL && devinfo->codec != NULL) 5360 sc = devinfo->codec->sc; 5361 if (sc == NULL) 5362 return (0); 5363 5364 if (sc->registered > 0) { 5365 err = pcm_unregister(dev); 5366 if (err != 0) 5367 return (err); 5368 } 5369 5370 hdac_release_resources(sc); 5371 5372 return (0); 5373} 5374 5375static device_method_t hdac_methods[] = { 5376 /* device interface */ 5377 DEVMETHOD(device_probe, hdac_probe), 5378 DEVMETHOD(device_attach, hdac_attach), 5379 DEVMETHOD(device_detach, hdac_detach), 5380 { 0, 0 } 5381}; 5382 5383static driver_t hdac_driver = { 5384 "pcm", 5385 hdac_methods, 5386 PCM_SOFTC_SIZE, 5387}; 5388 5389DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5390MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5391MODULE_VERSION(snd_hda, 1); 5392