hdac.c revision 165992
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20070105_0038" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 165992 2007-01-13 00:24:44Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* Intel */ 167#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168 169/* HP/Compaq */ 170#define HP_VENDORID 0x103c 171#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 176/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 177#define HP_NX6325_SUBVENDORX 0x103c30b0 178 179/* Dell */ 180#define DELL_VENDORID 0x1028 181#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 182#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 183#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 184 185/* Clevo */ 186#define CLEVO_VENDORID 0x1558 187#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 188#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 189 190/* Acer */ 191#define ACER_VENDORID 0x1025 192#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 193#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 194 195/* Asus */ 196#define ASUS_VENDORID 0x1043 197#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 198#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 199#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 200#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 201#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 202#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 203 204/* IBM / Lenovo */ 205#define IBM_VENDORID 0x1014 206#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 207#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 208 209/* Lenovo */ 210#define LENOVO_VENDORID 0x17aa 211#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 212#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 213 214/* Samsung */ 215#define SAMSUNG_VENDORID 0x144d 216#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 217#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 218 219/* Medion ? */ 220#define MEDION_VENDORID 0x161f 221#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 222#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 223 224/* 225 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 226 * instead of their own, which is beyond my comprehension 227 * (see HDA_CODEC_STAC9221 below). 228 */ 229#define APPLE_INTEL_MAC 0x76808384 230 231/* LG Electronics */ 232#define LG_VENDORID 0x1854 233#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 234#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 235 236/* Fujitsu Siemens */ 237#define FS_VENDORID 0x1734 238#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 239#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 240 241/* Toshiba */ 242#define TOSHIBA_VENDORID 0x1179 243#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 244#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 245 246/* Micro-Star International (MSI) */ 247#define MSI_VENDORID 0x1462 248#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 249#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 250 251/* Misc constants.. */ 252#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 253#define HDA_AMP_MUTE_NONE (0) 254#define HDA_AMP_MUTE_LEFT (1 << 0) 255#define HDA_AMP_MUTE_RIGHT (1 << 1) 256#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 257 258#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 259#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 260 261#define HDA_DAC_PATH (1 << 0) 262#define HDA_ADC_PATH (1 << 1) 263#define HDA_ADC_RECSEL (1 << 2) 264 265#define HDA_CTL_OUT (1 << 0) 266#define HDA_CTL_IN (1 << 1) 267#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 268 269#define HDA_GPIO_MAX 15 270/* 0 - 14 = GPIO */ 271#define HDA_QUIRK_GPIO0 (1 << 0) 272#define HDA_QUIRK_GPIO1 (1 << 1) 273#define HDA_QUIRK_GPIO2 (1 << 2) 274#define HDA_QUIRK_GPIOFLUSH (1 << 15) 275#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 276#define HDA_QUIRK_FIXEDRATE (1 << 17) 277#define HDA_QUIRK_FORCESTEREO (1 << 18) 278#define HDA_QUIRK_EAPDINV (1 << 19) 279#define HDA_QUIRK_VREF (1 << 20) 280 281static const struct { 282 char *key; 283 uint32_t value; 284} hdac_quirks_tab[] = { 285 { "gpio0", HDA_QUIRK_GPIO0 }, 286 { "gpio1", HDA_QUIRK_GPIO1 }, 287 { "gpio2", HDA_QUIRK_GPIO2 }, 288 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 289 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 290 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 291 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 292 { "eapdinv", HDA_QUIRK_EAPDINV }, 293 { "vref", HDA_QUIRK_VREF }, 294}; 295#define HDAC_QUIRKS_TAB_LEN \ 296 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 297 298#define HDA_BDL_MIN 2 299#define HDA_BDL_MAX 256 300#define HDA_BDL_DEFAULT HDA_BDL_MIN 301 302#define HDA_BUFSZ_MIN 4096 303#define HDA_BUFSZ_MAX 65536 304#define HDA_BUFSZ_DEFAULT 16384 305 306#define HDA_PARSE_MAXDEPTH 10 307 308#define HDAC_UNSOLTAG_EVENT_HP 0x00 309 310MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 311 312enum { 313 HDA_PARSE_MIXER, 314 HDA_PARSE_DIRECT 315}; 316 317/* Default */ 318static uint32_t hdac_fmt[] = { 319 AFMT_STEREO | AFMT_S16_LE, 320 0 321}; 322 323static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 324 325static const struct { 326 uint32_t model; 327 char *desc; 328} hdac_devices[] = { 329 { HDA_INTEL_82801F, "Intel 82801F" }, 330 { HDA_INTEL_82801G, "Intel 82801G" }, 331 { HDA_INTEL_82801H, "Intel 82801H" }, 332 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 333 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 334 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 335 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 336 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 337 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 338 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 339 { HDA_ATI_SB450, "ATI SB450" }, 340 { HDA_ATI_SB600, "ATI SB600" }, 341 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 342 { HDA_SIS_966, "SiS 966" }, 343 /* Unknown */ 344 { HDA_INTEL_ALL, "Intel (Unknown)" }, 345 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 346 { HDA_ATI_ALL, "ATI (Unknown)" }, 347 { HDA_VIA_ALL, "VIA (Unknown)" }, 348 { HDA_SIS_ALL, "SiS (Unknown)" }, 349}; 350#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 351 352static const struct { 353 uint32_t rate; 354 int valid; 355 uint16_t base; 356 uint16_t mul; 357 uint16_t div; 358} hda_rate_tab[] = { 359 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 360 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 361 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 362 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 363 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 364 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 365 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 366 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 367 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 368 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 369 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 370 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 371 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 372 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 373 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 374 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 375 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 376 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 377 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 378 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 379 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 380 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 381 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 382 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 383 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 384 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 385 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 386 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 387 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 388 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 389 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 390 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 391 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 392 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 393 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 394}; 395#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 396 397/* All codecs you can eat... */ 398#define HDA_CODEC_CONSTRUCT(vendor, id) \ 399 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 400 401/* Realtek */ 402#define REALTEK_VENDORID 0x10ec 403#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 404#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 405#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 406#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 407#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 408#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 409#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 410 411/* Analog Device */ 412#define ANALOGDEVICE_VENDORID 0x11d4 413#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 414#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 415#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 416#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 417 418/* CMedia */ 419#define CMEDIA_VENDORID 0x434d 420#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 421#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 422 423/* Sigmatel */ 424#define SIGMATEL_VENDORID 0x8384 425#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 426#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 427#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 428#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 429#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 430#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 431 432/* 433 * Conexant 434 * 435 * Ok, the truth is, I don't have any idea at all whether 436 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 437 * place that tell me it is "Venice" is from its Windows driver INF. 438 * 439 * Venice - CX????? 440 * Waikiki - CX20551-22 441 */ 442#define CONEXANT_VENDORID 0x14f1 443#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 444#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 445#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 446 447 448/* Codecs */ 449static const struct { 450 uint32_t id; 451 char *name; 452} hdac_codecs[] = { 453 { HDA_CODEC_ALC260, "Realtek ALC260" }, 454 { HDA_CODEC_ALC861, "Realtek ALC861" }, 455 { HDA_CODEC_ALC880, "Realtek ALC880" }, 456 { HDA_CODEC_ALC882, "Realtek ALC882" }, 457 { HDA_CODEC_ALC883, "Realtek ALC883" }, 458 { HDA_CODEC_ALC888, "Realtek ALC888" }, 459 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 460 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 461 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 462 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 463 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 464 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 465 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 466 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 467 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 468 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 469 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 470 /* Unknown codec */ 471 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 472 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 473 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 474 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 475 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 476}; 477#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 478 479enum { 480 HDAC_HP_SWITCH_CTL, 481 HDAC_HP_SWITCH_CTRL 482}; 483 484static const struct { 485 uint32_t model; 486 uint32_t id; 487 int type; 488 int inverted; 489 nid_t hpnid; 490 nid_t spkrnid[8]; 491 nid_t eapdnid; 492} hdac_hp_switch[] = { 493 /* Specific OEM models */ 494 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 495 17, { 16, -1 }, 16 }, 496 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 497 6, { 5, -1 }, 5 }, 498 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 499 6, { 5, -1 }, 5 }, 500 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 501 6, { 5, -1 }, 5 }, 502 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 503 6, { 5, -1 }, -1 }, 504 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 505 13, { 14, -1 }, -1 }, 506 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 507 13, { 14, -1 }, -1 }, 508 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 509 10, { 13, -1 }, -1 }, 510 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 511 26, { 27, -1 }, -1 }, 512 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 513 27, { 20, -1 }, -1 }, 514 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 515 20, { 21, -1 }, -1 }, 516 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 517 20, { 27, -1 }, -1 }, 518 /* 519 * All models that at least come from the same vendor with 520 * simmilar codec. 521 */ 522 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 523 17, { 16, -1 }, 16 }, 524 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 525 6, { 5, -1 }, 5 }, 526 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 527 6, { 5, -1 }, -1 }, 528 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 529 13, { 14, -1 }, -1 }, 530 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 531 26, { 27, -1 }, -1 }, 532 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 533 20, { 21, -1 }, -1 }, 534}; 535#define HDAC_HP_SWITCH_LEN \ 536 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 537 538static const struct { 539 uint32_t model; 540 uint32_t id; 541 nid_t eapdnid; 542 int hp_switch; 543} hdac_eapd_switch[] = { 544 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 545 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 546 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 547}; 548#define HDAC_EAPD_SWITCH_LEN \ 549 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 550 551/**************************************************************************** 552 * Function prototypes 553 ****************************************************************************/ 554static void hdac_intr_handler(void *); 555static int hdac_reset(struct hdac_softc *); 556static int hdac_get_capabilities(struct hdac_softc *); 557static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 558static int hdac_dma_alloc(struct hdac_softc *, 559 struct hdac_dma *, bus_size_t); 560static void hdac_dma_free(struct hdac_dma *); 561static int hdac_mem_alloc(struct hdac_softc *); 562static void hdac_mem_free(struct hdac_softc *); 563static int hdac_irq_alloc(struct hdac_softc *); 564static void hdac_irq_free(struct hdac_softc *); 565static void hdac_corb_init(struct hdac_softc *); 566static void hdac_rirb_init(struct hdac_softc *); 567static void hdac_corb_start(struct hdac_softc *); 568static void hdac_rirb_start(struct hdac_softc *); 569static void hdac_scan_codecs(struct hdac_softc *); 570static int hdac_probe_codec(struct hdac_codec *); 571static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 572static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 573 574static void hdac_attach2(void *); 575 576static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 577 uint32_t, int); 578static void hdac_command_send_internal(struct hdac_softc *, 579 struct hdac_command_list *, int); 580 581static int hdac_probe(device_t); 582static int hdac_attach(device_t); 583static int hdac_detach(device_t); 584static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 585static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 586 uint32_t, int, int); 587static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 588 nid_t, int, int); 589static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 590 nid_t, nid_t, int, int, int, int, int, int); 591static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 592static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 593 594static int hdac_rirb_flush(struct hdac_softc *sc); 595static int hdac_unsolq_flush(struct hdac_softc *sc); 596 597#define hdac_command(a1, a2, a3) \ 598 hdac_command_sendone_internal(a1, a2, a3) 599 600#define hdac_codec_id(d) \ 601 ((uint32_t)((d == NULL) ? 0x00000000 : \ 602 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 603 ((uint32_t)(d)->device_id & 0x0000ffff)))) 604 605static char * 606hdac_codec_name(struct hdac_devinfo *devinfo) 607{ 608 uint32_t id; 609 int i; 610 611 id = hdac_codec_id(devinfo); 612 613 for (i = 0; i < HDAC_CODECS_LEN; i++) { 614 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 615 return (hdac_codecs[i].name); 616 } 617 618 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 619} 620 621static char * 622hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 623{ 624 static char *ossname[] = SOUND_DEVICE_NAMES; 625 static char *unknown = "???"; 626 int i; 627 628 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 629 if (devmask & (1 << i)) 630 return (ossname[i]); 631 } 632 return (unknown); 633} 634 635static void 636hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 637{ 638 static char *ossname[] = SOUND_DEVICE_NAMES; 639 int i, first = 1; 640 641 bzero(buf, len); 642 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 643 if (mask & (1 << i)) { 644 if (first == 0) 645 strlcat(buf, ", ", len); 646 strlcat(buf, ossname[i], len); 647 first = 0; 648 } 649 } 650} 651 652static struct hdac_audio_ctl * 653hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 654{ 655 if (devinfo == NULL || 656 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 657 index == NULL || devinfo->function.audio.ctl == NULL || 658 devinfo->function.audio.ctlcnt < 1 || 659 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 660 return (NULL); 661 return (&devinfo->function.audio.ctl[(*index)++]); 662} 663 664static struct hdac_audio_ctl * 665hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 666 int index, int cnt) 667{ 668 struct hdac_audio_ctl *ctl, *retctl = NULL; 669 int i, at, atindex, found = 0; 670 671 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 672 return (NULL); 673 674 at = cnt; 675 if (at == 0) 676 at = 1; 677 else if (at < 0) 678 at = -1; 679 atindex = index; 680 if (atindex < 0) 681 atindex = -1; 682 683 i = 0; 684 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 685 if (ctl->enable == 0 || ctl->widget == NULL) 686 continue; 687 if (!(ctl->widget->nid == nid && (atindex == -1 || 688 ctl->index == atindex))) 689 continue; 690 found++; 691 if (found == cnt) 692 return (ctl); 693 retctl = ctl; 694 } 695 696 return ((at == -1) ? retctl : NULL); 697} 698 699static void 700hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 701{ 702 struct hdac_softc *sc; 703 struct hdac_widget *w; 704 struct hdac_audio_ctl *ctl; 705 uint32_t id, res; 706 int i = 0, j, forcemute; 707 nid_t cad; 708 709 if (devinfo == NULL || devinfo->codec == NULL || 710 devinfo->codec->sc == NULL) 711 return; 712 713 sc = devinfo->codec->sc; 714 cad = devinfo->codec->cad; 715 id = hdac_codec_id(devinfo); 716 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 717 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 718 sc->pci_subvendor) && 719 hdac_hp_switch[i].id == id) 720 break; 721 } 722 723 if (i >= HDAC_HP_SWITCH_LEN) 724 return; 725 726 forcemute = 0; 727 if (hdac_hp_switch[i].eapdnid != -1) { 728 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 729 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 730 forcemute = (w->param.eapdbtl & 731 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 732 } 733 734 res = hdac_command(sc, 735 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 736 HDA_BOOTVERBOSE( 737 device_printf(sc->dev, 738 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 739 hdac_hp_switch[i].hpnid, res); 740 ); 741 res >>= 31; 742 res ^= hdac_hp_switch[i].inverted; 743 744 switch (hdac_hp_switch[i].type) { 745 case HDAC_HP_SWITCH_CTL: 746 ctl = hdac_audio_ctl_amp_get(devinfo, 747 hdac_hp_switch[i].hpnid, 0, 1); 748 if (ctl != NULL) { 749 ctl->muted = (res != 0 && forcemute == 0) ? 750 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 751 hdac_audio_ctl_amp_set(ctl, 752 HDA_AMP_MUTE_DEFAULT, ctl->left, 753 ctl->right); 754 } 755 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 756 ctl = hdac_audio_ctl_amp_get(devinfo, 757 hdac_hp_switch[i].spkrnid[j], 0, 1); 758 if (ctl != NULL) { 759 ctl->muted = (res != 0 || forcemute == 1) ? 760 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 761 hdac_audio_ctl_amp_set(ctl, 762 HDA_AMP_MUTE_DEFAULT, ctl->left, 763 ctl->right); 764 } 765 } 766 break; 767 case HDAC_HP_SWITCH_CTRL: 768 if (res != 0) { 769 /* HP in */ 770 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 771 if (w != NULL && w->type == 772 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 773 if (forcemute == 0) 774 w->wclass.pin.ctrl |= 775 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 776 else 777 w->wclass.pin.ctrl &= 778 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 779 hdac_command(sc, 780 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 781 w->wclass.pin.ctrl), cad); 782 } 783 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 784 w = hdac_widget_get(devinfo, 785 hdac_hp_switch[i].spkrnid[j]); 786 if (w != NULL && w->type == 787 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 788 w->wclass.pin.ctrl &= 789 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 790 hdac_command(sc, 791 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 792 w->nid, 793 w->wclass.pin.ctrl), cad); 794 } 795 } 796 } else { 797 /* HP out */ 798 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 799 if (w != NULL && w->type == 800 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 801 w->wclass.pin.ctrl &= 802 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 803 hdac_command(sc, 804 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 805 w->wclass.pin.ctrl), cad); 806 } 807 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 808 w = hdac_widget_get(devinfo, 809 hdac_hp_switch[i].spkrnid[j]); 810 if (w != NULL && w->type == 811 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 812 if (forcemute == 0) 813 w->wclass.pin.ctrl |= 814 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 815 else 816 w->wclass.pin.ctrl &= 817 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 818 hdac_command(sc, 819 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 820 w->nid, 821 w->wclass.pin.ctrl), cad); 822 } 823 } 824 } 825 break; 826 default: 827 break; 828 } 829} 830 831static void 832hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 833{ 834 struct hdac_softc *sc; 835 struct hdac_devinfo *devinfo = NULL; 836 device_t *devlist = NULL; 837 int devcount, i; 838 839 if (codec == NULL || codec->sc == NULL) 840 return; 841 842 sc = codec->sc; 843 844 HDA_BOOTVERBOSE( 845 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 846 ); 847 848 device_get_children(sc->dev, &devlist, &devcount); 849 for (i = 0; devlist != NULL && i < devcount; i++) { 850 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 851 if (devinfo != NULL && devinfo->node_type == 852 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 853 devinfo->codec != NULL && 854 devinfo->codec->cad == codec->cad) { 855 break; 856 } else 857 devinfo = NULL; 858 } 859 if (devlist != NULL) 860 free(devlist, M_TEMP); 861 862 if (devinfo == NULL) 863 return; 864 865 switch (tag) { 866 case HDAC_UNSOLTAG_EVENT_HP: 867 hdac_hp_switch_handler(devinfo); 868 break; 869 default: 870 break; 871 } 872} 873 874static int 875hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 876{ 877 /* XXX to be removed */ 878#ifdef HDAC_INTR_EXTRA 879 uint32_t res; 880#endif 881 882 if (ch->blkcnt == 0) 883 return (0); 884 885 /* XXX to be removed */ 886#ifdef HDAC_INTR_EXTRA 887 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 888#endif 889 890 /* XXX to be removed */ 891#ifdef HDAC_INTR_EXTRA 892 HDA_BOOTVERBOSE( 893 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 894 device_printf(sc->dev, 895 "PCMDIR_%s intr triggered beyond stream boundary:" 896 "%08x\n", 897 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 898 ); 899#endif 900 901 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 902 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 903 904 /* XXX to be removed */ 905#ifdef HDAC_INTR_EXTRA 906 if (res & HDAC_SDSTS_BCIS) { 907#endif 908 return (1); 909 /* XXX to be removed */ 910#ifdef HDAC_INTR_EXTRA 911 } 912#endif 913 914 return (0); 915} 916 917/**************************************************************************** 918 * void hdac_intr_handler(void *) 919 * 920 * Interrupt handler. Processes interrupts received from the hdac. 921 ****************************************************************************/ 922static void 923hdac_intr_handler(void *context) 924{ 925 struct hdac_softc *sc; 926 uint32_t intsts; 927 uint8_t rirbsts; 928 struct hdac_rirb *rirb_base; 929 uint32_t trigger = 0; 930 931 sc = (struct hdac_softc *)context; 932 933 hdac_lock(sc); 934 if (sc->polling != 0) { 935 hdac_unlock(sc); 936 return; 937 } 938 /* Do we have anything to do? */ 939 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 940 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 941 hdac_unlock(sc); 942 return; 943 } 944 945 /* Was this a controller interrupt? */ 946 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 947 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 948 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 949 /* Get as many responses that we can */ 950 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 951 HDAC_WRITE_1(&sc->mem, 952 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 953 hdac_rirb_flush(sc); 954 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 955 } 956 /* XXX to be removed */ 957 /* Clear interrupt and exit */ 958#ifdef HDAC_INTR_EXTRA 959 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 960#endif 961 } 962 963 hdac_unsolq_flush(sc); 964 965 if (intsts & HDAC_INTSTS_SIS_MASK) { 966 if ((intsts & (1 << sc->num_iss)) && 967 hdac_stream_intr(sc, &sc->play) != 0) 968 trigger |= 1; 969 if ((intsts & (1 << 0)) && 970 hdac_stream_intr(sc, &sc->rec) != 0) 971 trigger |= 2; 972 /* XXX to be removed */ 973#ifdef HDAC_INTR_EXTRA 974 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 975 HDAC_INTSTS_SIS_MASK); 976#endif 977 } 978 979 hdac_unlock(sc); 980 981 if (trigger & 1) 982 chn_intr(sc->play.c); 983 if (trigger & 2) 984 chn_intr(sc->rec.c); 985} 986 987/**************************************************************************** 988 * int hdac_reset(hdac_softc *) 989 * 990 * Reset the hdac to a quiescent and known state. 991 ****************************************************************************/ 992static int 993hdac_reset(struct hdac_softc *sc) 994{ 995 uint32_t gctl; 996 int count, i; 997 998 /* 999 * Stop all Streams DMA engine 1000 */ 1001 for (i = 0; i < sc->num_iss; i++) 1002 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1003 for (i = 0; i < sc->num_oss; i++) 1004 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1005 for (i = 0; i < sc->num_bss; i++) 1006 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1007 1008 /* 1009 * Stop Control DMA engines 1010 */ 1011 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1012 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1013 1014 /* 1015 * Reset the controller. The reset must remain asserted for 1016 * a minimum of 100us. 1017 */ 1018 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1019 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1020 count = 10000; 1021 do { 1022 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1023 if (!(gctl & HDAC_GCTL_CRST)) 1024 break; 1025 DELAY(10); 1026 } while (--count); 1027 if (gctl & HDAC_GCTL_CRST) { 1028 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1029 return (ENXIO); 1030 } 1031 DELAY(100); 1032 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1033 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1034 count = 10000; 1035 do { 1036 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1037 if (gctl & HDAC_GCTL_CRST) 1038 break; 1039 DELAY(10); 1040 } while (--count); 1041 if (!(gctl & HDAC_GCTL_CRST)) { 1042 device_printf(sc->dev, "Device stuck in reset\n"); 1043 return (ENXIO); 1044 } 1045 1046 /* 1047 * Wait for codecs to finish their own reset sequence. The delay here 1048 * should be of 250us but for some reasons, on it's not enough on my 1049 * computer. Let's use twice as much as necessary to make sure that 1050 * it's reset properly. 1051 */ 1052 DELAY(1000); 1053 1054 return (0); 1055} 1056 1057 1058/**************************************************************************** 1059 * int hdac_get_capabilities(struct hdac_softc *); 1060 * 1061 * Retreive the general capabilities of the hdac; 1062 * Number of Input Streams 1063 * Number of Output Streams 1064 * Number of bidirectional Streams 1065 * 64bit ready 1066 * CORB and RIRB sizes 1067 ****************************************************************************/ 1068static int 1069hdac_get_capabilities(struct hdac_softc *sc) 1070{ 1071 uint16_t gcap; 1072 uint8_t corbsize, rirbsize; 1073 1074 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1075 sc->num_iss = HDAC_GCAP_ISS(gcap); 1076 sc->num_oss = HDAC_GCAP_OSS(gcap); 1077 sc->num_bss = HDAC_GCAP_BSS(gcap); 1078 1079 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1080 1081 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1082 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1083 HDAC_CORBSIZE_CORBSZCAP_256) 1084 sc->corb_size = 256; 1085 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1086 HDAC_CORBSIZE_CORBSZCAP_16) 1087 sc->corb_size = 16; 1088 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1089 HDAC_CORBSIZE_CORBSZCAP_2) 1090 sc->corb_size = 2; 1091 else { 1092 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1093 __func__, corbsize); 1094 return (ENXIO); 1095 } 1096 1097 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1098 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1099 HDAC_RIRBSIZE_RIRBSZCAP_256) 1100 sc->rirb_size = 256; 1101 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1102 HDAC_RIRBSIZE_RIRBSZCAP_16) 1103 sc->rirb_size = 16; 1104 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1105 HDAC_RIRBSIZE_RIRBSZCAP_2) 1106 sc->rirb_size = 2; 1107 else { 1108 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1109 __func__, rirbsize); 1110 return (ENXIO); 1111 } 1112 1113 return (0); 1114} 1115 1116 1117/**************************************************************************** 1118 * void hdac_dma_cb 1119 * 1120 * This function is called by bus_dmamap_load when the mapping has been 1121 * established. We just record the physical address of the mapping into 1122 * the struct hdac_dma passed in. 1123 ****************************************************************************/ 1124static void 1125hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1126{ 1127 struct hdac_dma *dma; 1128 1129 if (error == 0) { 1130 dma = (struct hdac_dma *)callback_arg; 1131 dma->dma_paddr = segs[0].ds_addr; 1132 } 1133} 1134 1135static void 1136hdac_dma_nocache(void *ptr) 1137{ 1138#if defined(__i386__) || defined(__amd64__) 1139 pt_entry_t *pte; 1140 vm_offset_t va; 1141 1142 va = (vm_offset_t)ptr; 1143 pte = vtopte(va); 1144 if (pte) { 1145 *pte |= PG_N; 1146 invltlb(); 1147 } 1148#endif 1149} 1150 1151/**************************************************************************** 1152 * int hdac_dma_alloc 1153 * 1154 * This function allocate and setup a dma region (struct hdac_dma). 1155 * It must be freed by a corresponding hdac_dma_free. 1156 ****************************************************************************/ 1157static int 1158hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1159{ 1160 int result; 1161 int lowaddr; 1162 1163 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1164 BUS_SPACE_MAXADDR_32BIT; 1165 bzero(dma, sizeof(*dma)); 1166 1167 /* 1168 * Create a DMA tag 1169 */ 1170 result = bus_dma_tag_create(NULL, /* parent */ 1171 HDAC_DMA_ALIGNMENT, /* alignment */ 1172 0, /* boundary */ 1173 lowaddr, /* lowaddr */ 1174 BUS_SPACE_MAXADDR, /* highaddr */ 1175 NULL, /* filtfunc */ 1176 NULL, /* fistfuncarg */ 1177 size, /* maxsize */ 1178 1, /* nsegments */ 1179 size, /* maxsegsz */ 1180 0, /* flags */ 1181 NULL, /* lockfunc */ 1182 NULL, /* lockfuncarg */ 1183 &dma->dma_tag); /* dmat */ 1184 if (result != 0) { 1185 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1186 __func__, result); 1187 goto fail; 1188 } 1189 1190 /* 1191 * Allocate DMA memory 1192 */ 1193 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1194 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1195 if (result != 0) { 1196 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1197 __func__, result); 1198 goto fail; 1199 } 1200 1201 /* 1202 * Map the memory 1203 */ 1204 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1205 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1206 BUS_DMA_NOWAIT); 1207 if (result != 0 || dma->dma_paddr == 0) { 1208 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1209 __func__, result); 1210 goto fail; 1211 } 1212 bzero((void *)dma->dma_vaddr, size); 1213 hdac_dma_nocache(dma->dma_vaddr); 1214 1215 return (0); 1216fail: 1217 if (dma->dma_map != NULL) 1218 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1219 if (dma->dma_tag != NULL) 1220 bus_dma_tag_destroy(dma->dma_tag); 1221 return (result); 1222} 1223 1224 1225/**************************************************************************** 1226 * void hdac_dma_free(struct hdac_dma *) 1227 * 1228 * Free a struct dhac_dma that has been previously allocated via the 1229 * hdac_dma_alloc function. 1230 ****************************************************************************/ 1231static void 1232hdac_dma_free(struct hdac_dma *dma) 1233{ 1234 if (dma->dma_tag != NULL) { 1235 /* Flush caches */ 1236 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1237 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1238 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1239 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1240 bus_dma_tag_destroy(dma->dma_tag); 1241 } 1242} 1243 1244/**************************************************************************** 1245 * int hdac_mem_alloc(struct hdac_softc *) 1246 * 1247 * Allocate all the bus resources necessary to speak with the physical 1248 * controller. 1249 ****************************************************************************/ 1250static int 1251hdac_mem_alloc(struct hdac_softc *sc) 1252{ 1253 struct hdac_mem *mem; 1254 1255 mem = &sc->mem; 1256 mem->mem_rid = PCIR_BAR(0); 1257 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1258 &mem->mem_rid, RF_ACTIVE); 1259 if (mem->mem_res == NULL) { 1260 device_printf(sc->dev, 1261 "%s: Unable to allocate memory resource\n", __func__); 1262 return (ENOMEM); 1263 } 1264 mem->mem_tag = rman_get_bustag(mem->mem_res); 1265 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1266 1267 return (0); 1268} 1269 1270/**************************************************************************** 1271 * void hdac_mem_free(struct hdac_softc *) 1272 * 1273 * Free up resources previously allocated by hdac_mem_alloc. 1274 ****************************************************************************/ 1275static void 1276hdac_mem_free(struct hdac_softc *sc) 1277{ 1278 struct hdac_mem *mem; 1279 1280 mem = &sc->mem; 1281 if (mem->mem_res != NULL) 1282 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1283 mem->mem_res); 1284 mem->mem_res = NULL; 1285} 1286 1287/**************************************************************************** 1288 * int hdac_irq_alloc(struct hdac_softc *) 1289 * 1290 * Allocate and setup the resources necessary for interrupt handling. 1291 ****************************************************************************/ 1292static int 1293hdac_irq_alloc(struct hdac_softc *sc) 1294{ 1295 struct hdac_irq *irq; 1296 int result; 1297 1298 irq = &sc->irq; 1299 irq->irq_rid = 0x0; 1300 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1301 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1302 if (irq->irq_res == NULL) { 1303 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1304 __func__); 1305 goto fail; 1306 } 1307 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1308 hdac_intr_handler, sc, &irq->irq_handle); 1309 if (result != 0) { 1310 device_printf(sc->dev, 1311 "%s: Unable to setup interrupt handler (%x)\n", 1312 __func__, result); 1313 goto fail; 1314 } 1315 1316 return (0); 1317 1318fail: 1319 hdac_irq_free(sc); 1320 1321 return (ENXIO); 1322} 1323 1324/**************************************************************************** 1325 * void hdac_irq_free(struct hdac_softc *) 1326 * 1327 * Free up resources previously allocated by hdac_irq_alloc. 1328 ****************************************************************************/ 1329static void 1330hdac_irq_free(struct hdac_softc *sc) 1331{ 1332 struct hdac_irq *irq; 1333 1334 irq = &sc->irq; 1335 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1336 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1337 if (irq->irq_res != NULL) 1338 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1339 irq->irq_res); 1340 irq->irq_handle = NULL; 1341 irq->irq_res = NULL; 1342} 1343 1344/**************************************************************************** 1345 * void hdac_corb_init(struct hdac_softc *) 1346 * 1347 * Initialize the corb registers for operations but do not start it up yet. 1348 * The CORB engine must not be running when this function is called. 1349 ****************************************************************************/ 1350static void 1351hdac_corb_init(struct hdac_softc *sc) 1352{ 1353 uint8_t corbsize; 1354 uint64_t corbpaddr; 1355 1356 /* Setup the CORB size. */ 1357 switch (sc->corb_size) { 1358 case 256: 1359 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1360 break; 1361 case 16: 1362 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1363 break; 1364 case 2: 1365 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1366 break; 1367 default: 1368 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1369 } 1370 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1371 1372 /* Setup the CORB Address in the hdac */ 1373 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1374 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1375 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1376 1377 /* Set the WP and RP */ 1378 sc->corb_wp = 0; 1379 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1380 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1381 /* 1382 * The HDA specification indicates that the CORBRPRST bit will always 1383 * read as zero. Unfortunately, it seems that at least the 82801G 1384 * doesn't reset the bit to zero, which stalls the corb engine. 1385 * manually reset the bit to zero before continuing. 1386 */ 1387 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1388 1389 /* Enable CORB error reporting */ 1390#if 0 1391 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1392#endif 1393} 1394 1395/**************************************************************************** 1396 * void hdac_rirb_init(struct hdac_softc *) 1397 * 1398 * Initialize the rirb registers for operations but do not start it up yet. 1399 * The RIRB engine must not be running when this function is called. 1400 ****************************************************************************/ 1401static void 1402hdac_rirb_init(struct hdac_softc *sc) 1403{ 1404 uint8_t rirbsize; 1405 uint64_t rirbpaddr; 1406 1407 /* Setup the RIRB size. */ 1408 switch (sc->rirb_size) { 1409 case 256: 1410 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1411 break; 1412 case 16: 1413 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1414 break; 1415 case 2: 1416 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1417 break; 1418 default: 1419 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1420 } 1421 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1422 1423 /* Setup the RIRB Address in the hdac */ 1424 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1425 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1426 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1427 1428 /* Setup the WP and RP */ 1429 sc->rirb_rp = 0; 1430 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1431 1432 if (sc->polling == 0) { 1433 /* Setup the interrupt threshold */ 1434 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1435 1436 /* Enable Overrun and response received reporting */ 1437#if 0 1438 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1439 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1440#else 1441 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1442#endif 1443 } 1444 1445 /* 1446 * Make sure that the Host CPU cache doesn't contain any dirty 1447 * cache lines that falls in the rirb. If I understood correctly, it 1448 * should be sufficient to do this only once as the rirb is purely 1449 * read-only from now on. 1450 */ 1451 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1452 BUS_DMASYNC_PREREAD); 1453} 1454 1455/**************************************************************************** 1456 * void hdac_corb_start(hdac_softc *) 1457 * 1458 * Startup the corb DMA engine 1459 ****************************************************************************/ 1460static void 1461hdac_corb_start(struct hdac_softc *sc) 1462{ 1463 uint32_t corbctl; 1464 1465 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1466 corbctl |= HDAC_CORBCTL_CORBRUN; 1467 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1468} 1469 1470/**************************************************************************** 1471 * void hdac_rirb_start(hdac_softc *) 1472 * 1473 * Startup the rirb DMA engine 1474 ****************************************************************************/ 1475static void 1476hdac_rirb_start(struct hdac_softc *sc) 1477{ 1478 uint32_t rirbctl; 1479 1480 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1481 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1482 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1483} 1484 1485 1486/**************************************************************************** 1487 * void hdac_scan_codecs(struct hdac_softc *) 1488 * 1489 * Scan the bus for available codecs. 1490 ****************************************************************************/ 1491static void 1492hdac_scan_codecs(struct hdac_softc *sc) 1493{ 1494 struct hdac_codec *codec; 1495 int i; 1496 uint16_t statests; 1497 1498 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1499 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1500 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1501 /* We have found a codec. */ 1502 hdac_unlock(sc); 1503 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1504 M_HDAC, M_ZERO | M_NOWAIT); 1505 hdac_lock(sc); 1506 if (codec == NULL) { 1507 device_printf(sc->dev, 1508 "Unable to allocate memory for codec\n"); 1509 continue; 1510 } 1511 codec->commands = NULL; 1512 codec->responses_received = 0; 1513 codec->verbs_sent = 0; 1514 codec->sc = sc; 1515 codec->cad = i; 1516 sc->codecs[i] = codec; 1517 if (hdac_probe_codec(codec) != 0) 1518 break; 1519 } 1520 } 1521 /* All codecs have been probed, now try to attach drivers to them */ 1522 /* bus_generic_attach(sc->dev); */ 1523} 1524 1525/**************************************************************************** 1526 * void hdac_probe_codec(struct hdac_softc *, int) 1527 * 1528 * Probe a the given codec_id for available function groups. 1529 ****************************************************************************/ 1530static int 1531hdac_probe_codec(struct hdac_codec *codec) 1532{ 1533 struct hdac_softc *sc = codec->sc; 1534 struct hdac_devinfo *devinfo; 1535 uint32_t vendorid, revisionid, subnode; 1536 int startnode; 1537 int endnode; 1538 int i; 1539 nid_t cad = codec->cad; 1540 1541 HDA_BOOTVERBOSE( 1542 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1543 ); 1544 vendorid = hdac_command(sc, 1545 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1546 cad); 1547 revisionid = hdac_command(sc, 1548 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1549 cad); 1550 subnode = hdac_command(sc, 1551 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1552 cad); 1553 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1554 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1555 1556 HDA_BOOTVERBOSE( 1557 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1558 startnode, endnode); 1559 ); 1560 for (i = startnode; i < endnode; i++) { 1561 devinfo = hdac_probe_function(codec, i); 1562 if (devinfo != NULL) { 1563 /* XXX Ignore other FG. */ 1564 devinfo->vendor_id = 1565 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1566 devinfo->device_id = 1567 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1568 devinfo->revision_id = 1569 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1570 devinfo->stepping_id = 1571 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1572 HDA_BOOTVERBOSE( 1573 device_printf(sc->dev, 1574 "HDA_DEBUG: \tFound AFG nid=%d " 1575 "[startnode=%d endnode=%d]\n", 1576 devinfo->nid, startnode, endnode); 1577 ); 1578 return (1); 1579 } 1580 } 1581 1582 HDA_BOOTVERBOSE( 1583 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1584 ); 1585 return (0); 1586} 1587 1588static struct hdac_devinfo * 1589hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1590{ 1591 struct hdac_softc *sc = codec->sc; 1592 struct hdac_devinfo *devinfo; 1593 uint32_t fctgrptype; 1594 nid_t cad = codec->cad; 1595 1596 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1597 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1598 1599 /* XXX For now, ignore other FG. */ 1600 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1601 return (NULL); 1602 1603 hdac_unlock(sc); 1604 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1605 M_NOWAIT | M_ZERO); 1606 hdac_lock(sc); 1607 if (devinfo == NULL) { 1608 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1609 __func__); 1610 return (NULL); 1611 } 1612 1613 devinfo->nid = nid; 1614 devinfo->node_type = fctgrptype; 1615 devinfo->codec = codec; 1616 1617 hdac_add_child(sc, devinfo); 1618 1619 return (devinfo); 1620} 1621 1622static void 1623hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1624{ 1625 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1626 device_set_ivars(devinfo->dev, (void *)devinfo); 1627 /* XXX - Print more information when booting verbose??? */ 1628} 1629 1630static void 1631hdac_widget_connection_parse(struct hdac_widget *w) 1632{ 1633 struct hdac_softc *sc = w->devinfo->codec->sc; 1634 uint32_t res; 1635 int i, j, max, found, entnum, cnid; 1636 nid_t cad = w->devinfo->codec->cad; 1637 nid_t nid = w->nid; 1638 1639 res = hdac_command(sc, 1640 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1641 1642 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1643 1644 if (w->nconns < 1) 1645 return; 1646 1647 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1648 res = 0; 1649 i = 0; 1650 found = 0; 1651 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1652 1653 while (i < w->nconns) { 1654 res = hdac_command(sc, 1655 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1656 for (j = 0; j < entnum; j++) { 1657 cnid = res; 1658 cnid >>= (32 / entnum) * j; 1659 cnid &= (1 << (32 / entnum)) - 1; 1660 if (cnid == 0) 1661 continue; 1662 if (found > max) { 1663 device_printf(sc->dev, 1664 "node %d: Adding %d: " 1665 "Max connection reached!\n", 1666 nid, cnid); 1667 continue; 1668 } 1669 w->conns[found++] = cnid; 1670 } 1671 i += entnum; 1672 } 1673 1674 HDA_BOOTVERBOSE( 1675 if (w->nconns != found) { 1676 device_printf(sc->dev, 1677 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1678 "length=%d != found=%d\n", 1679 nid, w->nconns, found); 1680 } 1681 ); 1682} 1683 1684static uint32_t 1685hdac_widget_pin_getconfig(struct hdac_widget *w) 1686{ 1687 struct hdac_softc *sc; 1688 uint32_t config, id; 1689 nid_t cad, nid; 1690 1691 sc = w->devinfo->codec->sc; 1692 cad = w->devinfo->codec->cad; 1693 nid = w->nid; 1694 id = hdac_codec_id(w->devinfo); 1695 1696 config = hdac_command(sc, 1697 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1698 cad); 1699 /* 1700 * XXX REWRITE!!!! Don't argue! 1701 */ 1702 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1703 switch (nid) { 1704 case 26: 1705 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1706 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1707 break; 1708 case 27: 1709 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1710 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1711 break; 1712 } 1713 } else if (id == HDA_CODEC_ALC880 && 1714 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1715 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1716 /* 1717 * Super broken BIOS 1718 */ 1719 switch (nid) { 1720 case 20: 1721 break; 1722 case 21: 1723 break; 1724 case 22: 1725 break; 1726 case 23: 1727 break; 1728 case 24: /* MIC1 */ 1729 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1730 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1731 break; 1732 case 25: /* XXX MIC2 */ 1733 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1734 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1735 break; 1736 case 26: /* LINE1 */ 1737 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1738 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1739 break; 1740 case 27: /* XXX LINE2 */ 1741 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1742 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1743 break; 1744 case 28: /* CD */ 1745 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1746 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1747 break; 1748 case 30: 1749 break; 1750 case 31: 1751 break; 1752 default: 1753 break; 1754 } 1755 } 1756 1757 return (config); 1758} 1759 1760static void 1761hdac_widget_pin_parse(struct hdac_widget *w) 1762{ 1763 struct hdac_softc *sc = w->devinfo->codec->sc; 1764 uint32_t config, pincap; 1765 char *devstr, *connstr; 1766 nid_t cad = w->devinfo->codec->cad; 1767 nid_t nid = w->nid; 1768 1769 config = hdac_widget_pin_getconfig(w); 1770 w->wclass.pin.config = config; 1771 1772 pincap = hdac_command(sc, 1773 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1774 w->wclass.pin.cap = pincap; 1775 1776 w->wclass.pin.ctrl = hdac_command(sc, 1777 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1778 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1779 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1780 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1781 1782 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1783 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1784 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1785 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1786 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1787 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1788 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1789 w->param.eapdbtl = hdac_command(sc, 1790 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1791 w->param.eapdbtl &= 0x7; 1792 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1793 } else 1794 w->param.eapdbtl = HDAC_INVALID; 1795 1796 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1797 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1798 devstr = "line out"; 1799 break; 1800 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1801 devstr = "speaker"; 1802 break; 1803 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1804 devstr = "headphones out"; 1805 break; 1806 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1807 devstr = "CD"; 1808 break; 1809 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1810 devstr = "SPDIF out"; 1811 break; 1812 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1813 devstr = "digital (other) out"; 1814 break; 1815 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1816 devstr = "modem, line side"; 1817 break; 1818 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1819 devstr = "modem, handset side"; 1820 break; 1821 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1822 devstr = "line in"; 1823 break; 1824 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1825 devstr = "AUX"; 1826 break; 1827 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1828 devstr = "Mic in"; 1829 break; 1830 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1831 devstr = "telephony"; 1832 break; 1833 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1834 devstr = "SPDIF in"; 1835 break; 1836 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1837 devstr = "digital (other) in"; 1838 break; 1839 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1840 devstr = "other"; 1841 break; 1842 default: 1843 devstr = "unknown"; 1844 break; 1845 } 1846 1847 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1848 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1849 connstr = "jack"; 1850 break; 1851 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1852 connstr = "none"; 1853 break; 1854 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1855 connstr = "fixed"; 1856 break; 1857 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1858 connstr = "jack / fixed"; 1859 break; 1860 default: 1861 connstr = "unknown"; 1862 break; 1863 } 1864 1865 strlcat(w->name, ": ", sizeof(w->name)); 1866 strlcat(w->name, devstr, sizeof(w->name)); 1867 strlcat(w->name, " (", sizeof(w->name)); 1868 strlcat(w->name, connstr, sizeof(w->name)); 1869 strlcat(w->name, ")", sizeof(w->name)); 1870} 1871 1872static void 1873hdac_widget_parse(struct hdac_widget *w) 1874{ 1875 struct hdac_softc *sc = w->devinfo->codec->sc; 1876 uint32_t wcap, cap; 1877 char *typestr; 1878 nid_t cad = w->devinfo->codec->cad; 1879 nid_t nid = w->nid; 1880 1881 wcap = hdac_command(sc, 1882 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1883 cad); 1884 w->param.widget_cap = wcap; 1885 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1886 1887 switch (w->type) { 1888 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1889 typestr = "audio output"; 1890 break; 1891 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1892 typestr = "audio input"; 1893 break; 1894 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1895 typestr = "audio mixer"; 1896 break; 1897 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1898 typestr = "audio selector"; 1899 break; 1900 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1901 typestr = "pin"; 1902 break; 1903 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1904 typestr = "power widget"; 1905 break; 1906 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1907 typestr = "volume widget"; 1908 break; 1909 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1910 typestr = "beep widget"; 1911 break; 1912 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1913 typestr = "vendor widget"; 1914 break; 1915 default: 1916 typestr = "unknown type"; 1917 break; 1918 } 1919 1920 strlcpy(w->name, typestr, sizeof(w->name)); 1921 1922 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1923 hdac_command(sc, 1924 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1925 cad); 1926 DELAY(1000); 1927 } 1928 1929 hdac_widget_connection_parse(w); 1930 1931 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1932 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1933 w->param.outamp_cap = 1934 hdac_command(sc, 1935 HDA_CMD_GET_PARAMETER(cad, nid, 1936 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1937 else 1938 w->param.outamp_cap = 1939 w->devinfo->function.audio.outamp_cap; 1940 } else 1941 w->param.outamp_cap = 0; 1942 1943 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1944 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1945 w->param.inamp_cap = 1946 hdac_command(sc, 1947 HDA_CMD_GET_PARAMETER(cad, nid, 1948 HDA_PARAM_INPUT_AMP_CAP), cad); 1949 else 1950 w->param.inamp_cap = 1951 w->devinfo->function.audio.inamp_cap; 1952 } else 1953 w->param.inamp_cap = 0; 1954 1955 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1956 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1957 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1958 cap = hdac_command(sc, 1959 HDA_CMD_GET_PARAMETER(cad, nid, 1960 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1961 w->param.supp_stream_formats = (cap != 0) ? cap : 1962 w->devinfo->function.audio.supp_stream_formats; 1963 cap = hdac_command(sc, 1964 HDA_CMD_GET_PARAMETER(cad, nid, 1965 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1966 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1967 w->devinfo->function.audio.supp_pcm_size_rate; 1968 } else { 1969 w->param.supp_stream_formats = 1970 w->devinfo->function.audio.supp_stream_formats; 1971 w->param.supp_pcm_size_rate = 1972 w->devinfo->function.audio.supp_pcm_size_rate; 1973 } 1974 } else { 1975 w->param.supp_stream_formats = 0; 1976 w->param.supp_pcm_size_rate = 0; 1977 } 1978 1979 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1980 hdac_widget_pin_parse(w); 1981} 1982 1983static struct hdac_widget * 1984hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1985{ 1986 if (devinfo == NULL || devinfo->widget == NULL || 1987 nid < devinfo->startnode || nid >= devinfo->endnode) 1988 return (NULL); 1989 return (&devinfo->widget[nid - devinfo->startnode]); 1990} 1991 1992static __inline int 1993hda_poll_channel(struct hdac_chan *ch) 1994{ 1995 uint32_t sz, delta; 1996 volatile uint32_t ptr; 1997 1998 if (ch->active == 0) 1999 return (0); 2000 2001 sz = ch->blksz * ch->blkcnt; 2002 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2003 ch->ptr = ptr; 2004 ptr %= sz; 2005 ptr &= ~(ch->blksz - 1); 2006 delta = (sz + ptr - ch->prevptr) % sz; 2007 2008 if (delta < ch->blksz) 2009 return (0); 2010 2011 ch->prevptr = ptr; 2012 2013 return (1); 2014} 2015 2016#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2017 2018static void 2019hda_poll_callback(void *arg) 2020{ 2021 struct hdac_softc *sc = arg; 2022 uint32_t trigger = 0; 2023 2024 if (sc == NULL) 2025 return; 2026 2027 hdac_lock(sc); 2028 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2029 hdac_unlock(sc); 2030 return; 2031 } 2032 2033 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2034 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2035 2036 /* XXX */ 2037 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2038 hda_poll_callback, sc); 2039 2040 hdac_unlock(sc); 2041 2042 if (trigger & 1) 2043 chn_intr(sc->play.c); 2044 if (trigger & 2) 2045 chn_intr(sc->rec.c); 2046} 2047 2048static int 2049hdac_rirb_flush(struct hdac_softc *sc) 2050{ 2051 struct hdac_rirb *rirb_base, *rirb; 2052 struct hdac_codec *codec; 2053 struct hdac_command_list *commands; 2054 nid_t cad; 2055 uint32_t resp; 2056 uint8_t rirbwp; 2057 int ret = 0; 2058 2059 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2060 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2061 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2062 BUS_DMASYNC_POSTREAD); 2063 2064 while (sc->rirb_rp != rirbwp) { 2065 sc->rirb_rp++; 2066 sc->rirb_rp %= sc->rirb_size; 2067 rirb = &rirb_base[sc->rirb_rp]; 2068 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2069 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2070 sc->codecs[cad] == NULL) 2071 continue; 2072 resp = rirb->response; 2073 codec = sc->codecs[cad]; 2074 commands = codec->commands; 2075 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2076 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2077 ((resp >> 26) & 0xffff); 2078 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2079 } else if (commands != NULL && commands->num_commands > 0 && 2080 codec->responses_received < commands->num_commands) 2081 commands->responses[codec->responses_received++] = 2082 resp; 2083 ret++; 2084 } 2085 2086 return (ret); 2087} 2088 2089static int 2090hdac_unsolq_flush(struct hdac_softc *sc) 2091{ 2092 nid_t cad; 2093 uint32_t tag; 2094 int ret = 0; 2095 2096 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2097 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2098 while (sc->unsolq_rp != sc->unsolq_wp) { 2099 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2100 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2101 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2102 hdac_unsolicited_handler(sc->codecs[cad], tag); 2103 ret++; 2104 } 2105 sc->unsolq_st = HDAC_UNSOLQ_READY; 2106 } 2107 2108 return (ret); 2109} 2110 2111static void 2112hdac_poll_callback(void *arg) 2113{ 2114 struct hdac_softc *sc = arg; 2115 if (sc == NULL) 2116 return; 2117 2118 hdac_lock(sc); 2119 if (sc->polling == 0) { 2120 hdac_unlock(sc); 2121 return; 2122 } 2123 hdac_rirb_flush(sc); 2124 hdac_unsolq_flush(sc); 2125 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2126 hdac_poll_callback, sc); 2127 hdac_unlock(sc); 2128} 2129 2130static void 2131hdac_stream_stop(struct hdac_chan *ch) 2132{ 2133 struct hdac_softc *sc = ch->devinfo->codec->sc; 2134 uint32_t ctl; 2135 2136 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2137 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2138 HDAC_SDCTL_RUN); 2139 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2140 2141 ch->active = 0; 2142 2143 if (sc->polling != 0) { 2144 int pollticks; 2145 2146 if (hda_chan_active(sc) == 0) { 2147 callout_stop(&sc->poll_hda); 2148 sc->poll_ticks = 1; 2149 } else { 2150 if (sc->play.active != 0) 2151 ch = &sc->play; 2152 else 2153 ch = &sc->rec; 2154 pollticks = ((uint64_t)hz * ch->blksz) / 2155 ((uint64_t)sndbuf_getbps(ch->b) * 2156 sndbuf_getspd(ch->b)); 2157 pollticks >>= 2; 2158 if (pollticks > hz) 2159 pollticks = hz; 2160 if (pollticks < 1) { 2161 HDA_BOOTVERBOSE( 2162 device_printf(sc->dev, 2163 "%s: pollticks=%d < 1 !\n", 2164 __func__, pollticks); 2165 ); 2166 pollticks = 1; 2167 } 2168 if (pollticks > sc->poll_ticks) { 2169 HDA_BOOTVERBOSE( 2170 device_printf(sc->dev, 2171 "%s: pollticks %d -> %d\n", 2172 __func__, sc->poll_ticks, 2173 pollticks); 2174 ); 2175 sc->poll_ticks = pollticks; 2176 callout_reset(&sc->poll_hda, 1, 2177 hda_poll_callback, sc); 2178 } 2179 } 2180 } else { 2181 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2182 ctl &= ~(1 << (ch->off >> 5)); 2183 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2184 } 2185} 2186 2187static void 2188hdac_stream_start(struct hdac_chan *ch) 2189{ 2190 struct hdac_softc *sc = ch->devinfo->codec->sc; 2191 uint32_t ctl; 2192 2193 if (sc->polling != 0) { 2194 int pollticks; 2195 2196 pollticks = ((uint64_t)hz * ch->blksz) / 2197 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2198 pollticks >>= 2; 2199 if (pollticks > hz) 2200 pollticks = hz; 2201 if (pollticks < 1) { 2202 HDA_BOOTVERBOSE( 2203 device_printf(sc->dev, 2204 "%s: pollticks=%d < 1 !\n", 2205 __func__, pollticks); 2206 ); 2207 pollticks = 1; 2208 } 2209 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2210 HDA_BOOTVERBOSE( 2211 if (hda_chan_active(sc) == 0) { 2212 device_printf(sc->dev, 2213 "%s: pollticks=%d\n", 2214 __func__, pollticks); 2215 } else { 2216 device_printf(sc->dev, 2217 "%s: pollticks %d -> %d\n", 2218 __func__, sc->poll_ticks, 2219 pollticks); 2220 } 2221 ); 2222 sc->poll_ticks = pollticks; 2223 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2224 sc); 2225 } 2226 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2227 ctl |= HDAC_SDCTL_RUN; 2228 } else { 2229 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2230 ctl |= 1 << (ch->off >> 5); 2231 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2232 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2233 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2234 HDAC_SDCTL_RUN; 2235 } 2236 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2237 2238 ch->active = 1; 2239} 2240 2241static void 2242hdac_stream_reset(struct hdac_chan *ch) 2243{ 2244 struct hdac_softc *sc = ch->devinfo->codec->sc; 2245 int timeout = 1000; 2246 int to = timeout; 2247 uint32_t ctl; 2248 2249 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2250 ctl |= HDAC_SDCTL_SRST; 2251 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2252 do { 2253 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2254 if (ctl & HDAC_SDCTL_SRST) 2255 break; 2256 DELAY(10); 2257 } while (--to); 2258 if (!(ctl & HDAC_SDCTL_SRST)) { 2259 device_printf(sc->dev, "timeout in reset\n"); 2260 } 2261 ctl &= ~HDAC_SDCTL_SRST; 2262 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2263 to = timeout; 2264 do { 2265 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2266 if (!(ctl & HDAC_SDCTL_SRST)) 2267 break; 2268 DELAY(10); 2269 } while (--to); 2270 if (ctl & HDAC_SDCTL_SRST) 2271 device_printf(sc->dev, "can't reset!\n"); 2272} 2273 2274static void 2275hdac_stream_setid(struct hdac_chan *ch) 2276{ 2277 struct hdac_softc *sc = ch->devinfo->codec->sc; 2278 uint32_t ctl; 2279 2280 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2281 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2282 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2283 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2284} 2285 2286static void 2287hdac_bdl_setup(struct hdac_chan *ch) 2288{ 2289 struct hdac_softc *sc = ch->devinfo->codec->sc; 2290 struct hdac_bdle *bdle; 2291 uint64_t addr; 2292 uint32_t blksz, blkcnt; 2293 int i; 2294 2295 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2296 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2297 2298 if (sc->polling != 0) { 2299 blksz = ch->blksz * ch->blkcnt; 2300 blkcnt = 1; 2301 } else { 2302 blksz = ch->blksz; 2303 blkcnt = ch->blkcnt; 2304 } 2305 2306 for (i = 0; i < blkcnt; i++, bdle++) { 2307 bdle->addrl = (uint32_t)addr; 2308 bdle->addrh = (uint32_t)(addr >> 32); 2309 bdle->len = blksz; 2310 bdle->ioc = 1 ^ sc->polling; 2311 addr += blksz; 2312 } 2313 2314 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2315 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2316 addr = ch->bdl_dma.dma_paddr; 2317 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2318 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2319} 2320 2321static int 2322hdac_bdl_alloc(struct hdac_chan *ch) 2323{ 2324 struct hdac_softc *sc = ch->devinfo->codec->sc; 2325 int rc; 2326 2327 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2328 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2329 if (rc) { 2330 device_printf(sc->dev, "can't alloc bdl\n"); 2331 return (rc); 2332 } 2333 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2334 2335 return (0); 2336} 2337 2338static void 2339hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2340 int index, int lmute, int rmute, 2341 int left, int right, int dir) 2342{ 2343 uint16_t v = 0; 2344 2345 if (sc == NULL) 2346 return; 2347 2348 if (left != right || lmute != rmute) { 2349 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2350 (lmute << 7) | left; 2351 hdac_command(sc, 2352 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2353 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2354 (rmute << 7) | right; 2355 } else 2356 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2357 (lmute << 7) | left; 2358 2359 hdac_command(sc, 2360 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2361} 2362 2363static void 2364hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2365 int left, int right) 2366{ 2367 struct hdac_softc *sc; 2368 nid_t nid, cad; 2369 int lmute, rmute; 2370 2371 if (ctl == NULL || ctl->widget == NULL || 2372 ctl->widget->devinfo == NULL || 2373 ctl->widget->devinfo->codec == NULL || 2374 ctl->widget->devinfo->codec->sc == NULL) 2375 return; 2376 2377 sc = ctl->widget->devinfo->codec->sc; 2378 cad = ctl->widget->devinfo->codec->cad; 2379 nid = ctl->widget->nid; 2380 2381 if (mute == HDA_AMP_MUTE_DEFAULT) { 2382 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2383 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2384 } else { 2385 lmute = HDA_AMP_LEFT_MUTED(mute); 2386 rmute = HDA_AMP_RIGHT_MUTED(mute); 2387 } 2388 2389 if (ctl->dir & HDA_CTL_OUT) 2390 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2391 lmute, rmute, left, right, 0); 2392 if (ctl->dir & HDA_CTL_IN) 2393 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2394 lmute, rmute, left, right, 1); 2395 ctl->left = left; 2396 ctl->right = right; 2397} 2398 2399static void 2400hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2401{ 2402 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2403 return; 2404 hdac_command(w->devinfo->codec->sc, 2405 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2406 w->nid, index), w->devinfo->codec->cad); 2407 w->selconn = index; 2408} 2409 2410 2411/**************************************************************************** 2412 * uint32_t hdac_command_sendone_internal 2413 * 2414 * Wrapper function that sends only one command to a given codec 2415 ****************************************************************************/ 2416static uint32_t 2417hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2418{ 2419 struct hdac_command_list cl; 2420 uint32_t response = HDAC_INVALID; 2421 2422 if (!hdac_lockowned(sc)) 2423 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2424 cl.num_commands = 1; 2425 cl.verbs = &verb; 2426 cl.responses = &response; 2427 2428 hdac_command_send_internal(sc, &cl, cad); 2429 2430 return (response); 2431} 2432 2433/**************************************************************************** 2434 * hdac_command_send_internal 2435 * 2436 * Send a command list to the codec via the corb. We queue as much verbs as 2437 * we can and msleep on the codec. When the interrupt get the responses 2438 * back from the rirb, it will wake us up so we can queue the remaining verbs 2439 * if any. 2440 ****************************************************************************/ 2441static void 2442hdac_command_send_internal(struct hdac_softc *sc, 2443 struct hdac_command_list *commands, nid_t cad) 2444{ 2445 struct hdac_codec *codec; 2446 int corbrp; 2447 uint32_t *corb; 2448 int timeout; 2449 int retry = 10; 2450 struct hdac_rirb *rirb_base; 2451 2452 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2453 commands->num_commands < 1) 2454 return; 2455 2456 codec = sc->codecs[cad]; 2457 codec->commands = commands; 2458 codec->responses_received = 0; 2459 codec->verbs_sent = 0; 2460 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2461 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2462 2463 do { 2464 if (codec->verbs_sent != commands->num_commands) { 2465 /* Queue as many verbs as possible */ 2466 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2467 bus_dmamap_sync(sc->corb_dma.dma_tag, 2468 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2469 while (codec->verbs_sent != commands->num_commands && 2470 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2471 sc->corb_wp++; 2472 sc->corb_wp %= sc->corb_size; 2473 corb[sc->corb_wp] = 2474 commands->verbs[codec->verbs_sent++]; 2475 } 2476 2477 /* Send the verbs to the codecs */ 2478 bus_dmamap_sync(sc->corb_dma.dma_tag, 2479 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2480 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2481 } 2482 2483 timeout = 1000; 2484 while (hdac_rirb_flush(sc) == 0 && --timeout) 2485 DELAY(10); 2486 } while ((codec->verbs_sent != commands->num_commands || 2487 codec->responses_received != commands->num_commands) && --retry); 2488 2489 if (retry == 0) 2490 device_printf(sc->dev, 2491 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2492 __func__, commands->num_commands, codec->verbs_sent, 2493 codec->responses_received); 2494 2495 codec->commands = NULL; 2496 codec->responses_received = 0; 2497 codec->verbs_sent = 0; 2498 2499 hdac_unsolq_flush(sc); 2500} 2501 2502 2503/**************************************************************************** 2504 * Device Methods 2505 ****************************************************************************/ 2506 2507/**************************************************************************** 2508 * int hdac_probe(device_t) 2509 * 2510 * Probe for the presence of an hdac. If none is found, check for a generic 2511 * match using the subclass of the device. 2512 ****************************************************************************/ 2513static int 2514hdac_probe(device_t dev) 2515{ 2516 int i, result; 2517 uint32_t model; 2518 uint16_t class, subclass; 2519 char desc[64]; 2520 2521 model = (uint32_t)pci_get_device(dev) << 16; 2522 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2523 class = pci_get_class(dev); 2524 subclass = pci_get_subclass(dev); 2525 2526 bzero(desc, sizeof(desc)); 2527 result = ENXIO; 2528 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2529 if (hdac_devices[i].model == model) { 2530 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2531 result = BUS_PROBE_DEFAULT; 2532 break; 2533 } 2534 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2535 class == PCIC_MULTIMEDIA && 2536 subclass == PCIS_MULTIMEDIA_HDA) { 2537 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2538 result = BUS_PROBE_GENERIC; 2539 break; 2540 } 2541 } 2542 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2543 subclass == PCIS_MULTIMEDIA_HDA) { 2544 strlcpy(desc, "Generic", sizeof(desc)); 2545 result = BUS_PROBE_GENERIC; 2546 } 2547 if (result != ENXIO) { 2548 strlcat(desc, " High Definition Audio Controller", 2549 sizeof(desc)); 2550 device_set_desc_copy(dev, desc); 2551 } 2552 2553 return (result); 2554} 2555 2556static void * 2557hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2558 struct pcm_channel *c, int dir) 2559{ 2560 struct hdac_devinfo *devinfo = data; 2561 struct hdac_softc *sc = devinfo->codec->sc; 2562 struct hdac_chan *ch; 2563 2564 hdac_lock(sc); 2565 if (dir == PCMDIR_PLAY) { 2566 ch = &sc->play; 2567 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2568 ch->dir = PCMDIR_PLAY; 2569 ch->sid = ++sc->streamcnt; 2570 devinfo->function.audio.playcnt++; 2571 } else { 2572 ch = &sc->rec; 2573 ch->off = devinfo->function.audio.reccnt << 5; 2574 ch->dir = PCMDIR_REC; 2575 ch->sid = ++sc->streamcnt; 2576 devinfo->function.audio.reccnt++; 2577 } 2578 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2579 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2580 ch->pcmrates[0] = 48000; 2581 ch->pcmrates[1] = 0; 2582 } 2583 ch->b = b; 2584 ch->c = c; 2585 ch->devinfo = devinfo; 2586 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2587 ch->blkcnt = sc->chan_blkcnt; 2588 hdac_unlock(sc); 2589 2590 if (hdac_bdl_alloc(ch) != 0) { 2591 ch->blkcnt = 0; 2592 return (NULL); 2593 } 2594 2595 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2596 return (NULL); 2597 2598 hdac_dma_nocache(ch->b->buf); 2599 2600 return (ch); 2601} 2602 2603static int 2604hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2605{ 2606 struct hdac_chan *ch = data; 2607 int i; 2608 2609 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2610 if (format == ch->caps.fmtlist[i]) { 2611 ch->fmt = format; 2612 return (0); 2613 } 2614 } 2615 2616 return (EINVAL); 2617} 2618 2619static int 2620hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2621{ 2622 struct hdac_chan *ch = data; 2623 uint32_t spd = 0, threshold; 2624 int i; 2625 2626 for (i = 0; ch->pcmrates[i] != 0; i++) { 2627 spd = ch->pcmrates[i]; 2628 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2629 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2630 if (speed < threshold) 2631 break; 2632 } 2633 2634 if (spd == 0) /* impossible */ 2635 ch->spd = 48000; 2636 else 2637 ch->spd = spd; 2638 2639 return (ch->spd); 2640} 2641 2642static void 2643hdac_stream_setup(struct hdac_chan *ch) 2644{ 2645 struct hdac_softc *sc = ch->devinfo->codec->sc; 2646 int i; 2647 nid_t cad = ch->devinfo->codec->cad; 2648 uint16_t fmt; 2649 2650 fmt = 0; 2651 if (ch->fmt & AFMT_S16_LE) 2652 fmt |= ch->bit16 << 4; 2653 else if (ch->fmt & AFMT_S32_LE) 2654 fmt |= ch->bit32 << 4; 2655 else 2656 fmt |= 1 << 4; 2657 2658 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2659 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2660 fmt |= hda_rate_tab[i].base; 2661 fmt |= hda_rate_tab[i].mul; 2662 fmt |= hda_rate_tab[i].div; 2663 break; 2664 } 2665 } 2666 2667 if (ch->fmt & AFMT_STEREO) 2668 fmt |= 1; 2669 2670 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2671 2672 for (i = 0; ch->io[i] != -1; i++) { 2673 HDA_BOOTVERBOSE( 2674 device_printf(sc->dev, 2675 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2676 "fmt=0x%08x\n", 2677 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2678 ch->io[i], fmt); 2679 ); 2680 hdac_command(sc, 2681 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2682 hdac_command(sc, 2683 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2684 ch->sid << 4), cad); 2685 } 2686} 2687 2688static int 2689hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2690{ 2691 struct hdac_chan *ch = data; 2692 struct hdac_softc *sc = ch->devinfo->codec->sc; 2693 2694 blksz &= ~0x7f; 2695 if (blksz < 0x80) 2696 blksz = 0x80; 2697 2698 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2699 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2700 2701 if ((sndbuf_getblksz(ch->b) != blksz || 2702 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2703 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2704 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2705 __func__, blksz, ch->blkcnt); 2706 2707 ch->blksz = sndbuf_getblksz(ch->b); 2708 2709 return (ch->blksz); 2710} 2711 2712static void 2713hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2714{ 2715 struct hdac_devinfo *devinfo = ch->devinfo; 2716 nid_t cad = devinfo->codec->cad; 2717 int i; 2718 2719 hdac_stream_stop(ch); 2720 2721 for (i = 0; ch->io[i] != -1; i++) { 2722 hdac_command(sc, 2723 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2724 0), cad); 2725 } 2726} 2727 2728static void 2729hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2730{ 2731 ch->ptr = 0; 2732 ch->prevptr = 0; 2733 hdac_stream_stop(ch); 2734 hdac_stream_reset(ch); 2735 hdac_bdl_setup(ch); 2736 hdac_stream_setid(ch); 2737 hdac_stream_setup(ch); 2738 hdac_stream_start(ch); 2739} 2740 2741static int 2742hdac_channel_trigger(kobj_t obj, void *data, int go) 2743{ 2744 struct hdac_chan *ch = data; 2745 struct hdac_softc *sc = ch->devinfo->codec->sc; 2746 2747 hdac_lock(sc); 2748 switch (go) { 2749 case PCMTRIG_START: 2750 hdac_channel_start(sc, ch); 2751 break; 2752 case PCMTRIG_STOP: 2753 case PCMTRIG_ABORT: 2754 hdac_channel_stop(sc, ch); 2755 break; 2756 } 2757 hdac_unlock(sc); 2758 2759 return (0); 2760} 2761 2762static int 2763hdac_channel_getptr(kobj_t obj, void *data) 2764{ 2765 struct hdac_chan *ch = data; 2766 struct hdac_softc *sc = ch->devinfo->codec->sc; 2767 uint32_t ptr; 2768 2769 hdac_lock(sc); 2770 if (sc->polling != 0) 2771 ptr = ch->ptr; 2772 else 2773 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2774 hdac_unlock(sc); 2775 2776 /* 2777 * Round to available space and force 128 bytes aligment. 2778 */ 2779 ptr %= ch->blksz * ch->blkcnt; 2780 ptr &= ~0x7f; 2781 2782 return (ptr); 2783} 2784 2785static struct pcmchan_caps * 2786hdac_channel_getcaps(kobj_t obj, void *data) 2787{ 2788 return (&((struct hdac_chan *)data)->caps); 2789} 2790 2791static kobj_method_t hdac_channel_methods[] = { 2792 KOBJMETHOD(channel_init, hdac_channel_init), 2793 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2794 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2795 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2796 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2797 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2798 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2799 { 0, 0 } 2800}; 2801CHANNEL_DECLARE(hdac_channel); 2802 2803static int 2804hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2805{ 2806 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2807 struct hdac_softc *sc = devinfo->codec->sc; 2808 struct hdac_widget *w, *cw; 2809 struct hdac_audio_ctl *ctl; 2810 uint32_t mask, recmask, id; 2811 int i, j, softpcmvol; 2812 nid_t cad; 2813 2814 hdac_lock(sc); 2815 2816 mask = 0; 2817 recmask = 0; 2818 2819 id = hdac_codec_id(devinfo); 2820 cad = devinfo->codec->cad; 2821 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2822 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2823 sc->pci_subvendor) && 2824 hdac_hp_switch[i].id == id)) 2825 continue; 2826 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2827 if (w != NULL && w->enable != 0 2828 && w->type == 2829 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2830 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2831 hdac_command(sc, 2832 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2833 w->nid, 2834 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2835 HDAC_UNSOLTAG_EVENT_HP), cad); 2836 hdac_hp_switch_handler(devinfo); 2837 HDA_BOOTVERBOSE( 2838 device_printf(sc->dev, 2839 "HDA_DEBUG: Enabling headphone/speaker " 2840 "audio routing switching:\n"); 2841 device_printf(sc->dev, 2842 "HDA_DEBUG: \tindex=%d nid=%d " 2843 "pci_subvendor=0x%08x " 2844 "codec=0x%08x\n", 2845 i, w->nid, sc->pci_subvendor, id); 2846 ); 2847 } 2848 break; 2849 } 2850 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2851 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2852 sc->pci_subvendor) && 2853 hdac_eapd_switch[i].id == id)) 2854 continue; 2855 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2856 if (w == NULL || w->enable == 0) 2857 break; 2858 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2859 w->param.eapdbtl == HDAC_INVALID) 2860 break; 2861 mask |= SOUND_MASK_OGAIN; 2862 break; 2863 } 2864 2865 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2866 w = hdac_widget_get(devinfo, i); 2867 if (w == NULL || w->enable == 0) 2868 continue; 2869 mask |= w->ctlflags; 2870 if (!(w->pflags & HDA_ADC_RECSEL)) 2871 continue; 2872 for (j = 0; j < w->nconns; j++) { 2873 cw = hdac_widget_get(devinfo, w->conns[j]); 2874 if (cw == NULL || cw->enable == 0) 2875 continue; 2876 recmask |= cw->ctlflags; 2877 } 2878 } 2879 2880 if (!(mask & SOUND_MASK_PCM)) { 2881 softpcmvol = 1; 2882 mask |= SOUND_MASK_PCM; 2883 } else 2884 softpcmvol = (devinfo->function.audio.quirks & 2885 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2886 2887 i = 0; 2888 ctl = NULL; 2889 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2890 if (ctl->widget == NULL || ctl->enable == 0) 2891 continue; 2892 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2893 continue; 2894 if (ctl->step > 0) 2895 break; 2896 } 2897 2898 if (softpcmvol == 1 || ctl == NULL) { 2899 struct snddev_info *d = NULL; 2900 d = device_get_softc(sc->dev); 2901 if (d != NULL) { 2902 d->flags |= SD_F_SOFTPCMVOL; 2903 HDA_BOOTVERBOSE( 2904 device_printf(sc->dev, 2905 "HDA_DEBUG: %s Soft PCM volume\n", 2906 (softpcmvol == 1) ? 2907 "Forcing" : "Enabling"); 2908 ); 2909 } 2910 i = 0; 2911 /* 2912 * XXX Temporary quirk for STAC9220, until the parser 2913 * become smarter. 2914 */ 2915 if (id == HDA_CODEC_STAC9220) { 2916 mask |= SOUND_MASK_VOLUME; 2917 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2918 NULL) { 2919 if (ctl->widget == NULL || ctl->enable == 0) 2920 continue; 2921 if (ctl->widget->nid == 11 && ctl->index == 0) { 2922 ctl->ossmask = SOUND_MASK_VOLUME; 2923 ctl->ossval = 100 | (100 << 8); 2924 } else 2925 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2926 } 2927 } else if (id == HDA_CODEC_STAC9221) { 2928 mask |= SOUND_MASK_VOLUME; 2929 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2930 NULL) { 2931 if (ctl->widget == NULL) 2932 continue; 2933 if (ctl->widget->nid == 2 && ctl->index == 0) { 2934 ctl->enable = 1; 2935 ctl->ossmask = SOUND_MASK_VOLUME; 2936 ctl->ossval = 100 | (100 << 8); 2937 } else if (ctl->enable == 0) 2938 continue; 2939 else 2940 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2941 } 2942 } else { 2943 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2944 SOUND_MASK_PCM); 2945 if (!(mask & SOUND_MASK_VOLUME)) 2946 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2947 SOUND_MIXER_NONE); 2948 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2949 NULL) { 2950 if (ctl->widget == NULL || ctl->enable == 0) 2951 continue; 2952 if (!HDA_FLAG_MATCH(ctl->ossmask, 2953 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2954 continue; 2955 if (!(ctl->mute == 1 && ctl->step == 0)) 2956 ctl->enable = 0; 2957 } 2958 } 2959 } 2960 2961 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2962 2963 mix_setrecdevs(m, recmask); 2964 mix_setdevs(m, mask); 2965 2966 hdac_unlock(sc); 2967 2968 return (0); 2969} 2970 2971static int 2972hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2973 unsigned left, unsigned right) 2974{ 2975 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2976 struct hdac_softc *sc = devinfo->codec->sc; 2977 struct hdac_widget *w; 2978 struct hdac_audio_ctl *ctl; 2979 uint32_t id, mute; 2980 int lvol, rvol, mlvol, mrvol; 2981 int i = 0; 2982 2983 hdac_lock(sc); 2984 if (dev == SOUND_MIXER_OGAIN) { 2985 uint32_t orig; 2986 /*if (left != right || !(left == 0 || left == 1)) { 2987 hdac_unlock(sc); 2988 return (-1); 2989 }*/ 2990 id = hdac_codec_id(devinfo); 2991 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2992 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2993 sc->pci_subvendor) && 2994 hdac_eapd_switch[i].id == id) 2995 break; 2996 } 2997 if (i >= HDAC_EAPD_SWITCH_LEN) { 2998 hdac_unlock(sc); 2999 return (-1); 3000 } 3001 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3002 if (w == NULL || 3003 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3004 w->param.eapdbtl == HDAC_INVALID) { 3005 hdac_unlock(sc); 3006 return (-1); 3007 } 3008 orig = w->param.eapdbtl; 3009 if (left == 0) 3010 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3011 else 3012 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3013 if (orig != w->param.eapdbtl) { 3014 uint32_t val; 3015 3016 if (hdac_eapd_switch[i].hp_switch != 0) 3017 hdac_hp_switch_handler(devinfo); 3018 val = w->param.eapdbtl; 3019 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3020 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3021 hdac_command(sc, 3022 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3023 w->nid, val), devinfo->codec->cad); 3024 } 3025 hdac_unlock(sc); 3026 return (left | (left << 8)); 3027 } 3028 if (dev == SOUND_MIXER_VOLUME) 3029 devinfo->function.audio.mvol = left | (right << 8); 3030 3031 mlvol = devinfo->function.audio.mvol & 0x7f; 3032 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3033 lvol = 0; 3034 rvol = 0; 3035 3036 i = 0; 3037 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3038 if (ctl->widget == NULL || ctl->enable == 0 || 3039 !(ctl->ossmask & (1 << dev))) 3040 continue; 3041 switch (dev) { 3042 case SOUND_MIXER_VOLUME: 3043 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3044 lvol = (lvol * ctl->step) / 100; 3045 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3046 rvol = (rvol * ctl->step) / 100; 3047 break; 3048 default: 3049 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3050 lvol = (left * mlvol) / 100; 3051 lvol = (lvol * ctl->step) / 100; 3052 rvol = (right * mrvol) / 100; 3053 rvol = (rvol * ctl->step) / 100; 3054 } else { 3055 lvol = (left * ctl->step) / 100; 3056 rvol = (right * ctl->step) / 100; 3057 } 3058 ctl->ossval = left | (right << 8); 3059 break; 3060 } 3061 mute = 0; 3062 if (ctl->step < 1) { 3063 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3064 (ctl->muted & HDA_AMP_MUTE_LEFT); 3065 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3066 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3067 } else { 3068 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3069 (ctl->muted & HDA_AMP_MUTE_LEFT); 3070 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3071 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3072 } 3073 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3074 } 3075 hdac_unlock(sc); 3076 3077 return (left | (right << 8)); 3078} 3079 3080static int 3081hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3082{ 3083 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3084 struct hdac_widget *w, *cw; 3085 struct hdac_softc *sc = devinfo->codec->sc; 3086 uint32_t ret = src, target; 3087 int i, j; 3088 3089 target = 0; 3090 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3091 if (src & (1 << i)) { 3092 target = 1 << i; 3093 break; 3094 } 3095 } 3096 3097 hdac_lock(sc); 3098 3099 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3100 w = hdac_widget_get(devinfo, i); 3101 if (w == NULL || w->enable == 0) 3102 continue; 3103 if (!(w->pflags & HDA_ADC_RECSEL)) 3104 continue; 3105 for (j = 0; j < w->nconns; j++) { 3106 cw = hdac_widget_get(devinfo, w->conns[j]); 3107 if (cw == NULL || cw->enable == 0) 3108 continue; 3109 if ((target == SOUND_MASK_VOLUME && 3110 cw->type != 3111 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3112 (target != SOUND_MASK_VOLUME && 3113 cw->type == 3114 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3115 continue; 3116 if (cw->ctlflags & target) { 3117 hdac_widget_connection_select(w, j); 3118 ret = target; 3119 j += w->nconns; 3120 } 3121 } 3122 } 3123 3124 hdac_unlock(sc); 3125 3126 return (ret); 3127} 3128 3129static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3130 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3131 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3132 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3133 { 0, 0 } 3134}; 3135MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3136 3137/**************************************************************************** 3138 * int hdac_attach(device_t) 3139 * 3140 * Attach the device into the kernel. Interrupts usually won't be enabled 3141 * when this function is called. Setup everything that doesn't require 3142 * interrupts and defer probing of codecs until interrupts are enabled. 3143 ****************************************************************************/ 3144static int 3145hdac_attach(device_t dev) 3146{ 3147 struct hdac_softc *sc; 3148 int result; 3149 int i = 0; 3150 3151 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3152 if (sc == NULL) { 3153 device_printf(dev, "cannot allocate softc\n"); 3154 return (ENOMEM); 3155 } 3156 3157 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3158 if (sc->lock == NULL) { 3159 device_printf(dev, "mutex creation failed\n"); 3160 free(sc, M_DEVBUF); 3161 return (ENOMEM); 3162 } 3163 3164 sc->dev = dev; 3165 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3166 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3167 3168 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3169 /* Screw nx6325 - subdevice/subvendor swapped */ 3170 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3171 } 3172 3173 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3174 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3175 3176 sc->poll_ticks = 1; 3177 if (resource_int_value(device_get_name(sc->dev), 3178 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3179 sc->polling = 1; 3180 else 3181 sc->polling = 0; 3182 3183 sc->chan_size = pcm_getbuffersize(dev, 3184 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3185 3186 if (resource_int_value(device_get_name(sc->dev), 3187 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3188 i &= ~0x7f; 3189 if (i < 0x80) 3190 i = 0x80; 3191 sc->chan_blkcnt = sc->chan_size / i; 3192 i = 0; 3193 while (sc->chan_blkcnt >> i) 3194 i++; 3195 sc->chan_blkcnt = 1 << (i - 1); 3196 if (sc->chan_blkcnt < HDA_BDL_MIN) 3197 sc->chan_blkcnt = HDA_BDL_MIN; 3198 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3199 sc->chan_blkcnt = HDA_BDL_MAX; 3200 } else 3201 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3202 3203 result = bus_dma_tag_create(NULL, /* parent */ 3204 HDAC_DMA_ALIGNMENT, /* alignment */ 3205 0, /* boundary */ 3206 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3207 BUS_SPACE_MAXADDR, /* highaddr */ 3208 NULL, /* filtfunc */ 3209 NULL, /* fistfuncarg */ 3210 sc->chan_size, /* maxsize */ 3211 1, /* nsegments */ 3212 sc->chan_size, /* maxsegsz */ 3213 0, /* flags */ 3214 NULL, /* lockfunc */ 3215 NULL, /* lockfuncarg */ 3216 &sc->chan_dmat); /* dmat */ 3217 if (result != 0) { 3218 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3219 __func__, result); 3220 snd_mtxfree(sc->lock); 3221 free(sc, M_DEVBUF); 3222 return (ENXIO); 3223 } 3224 3225 3226 sc->hdabus = NULL; 3227 for (i = 0; i < HDAC_CODEC_MAX; i++) 3228 sc->codecs[i] = NULL; 3229 3230 pci_enable_busmaster(dev); 3231 3232 /* Allocate resources */ 3233 result = hdac_mem_alloc(sc); 3234 if (result != 0) 3235 goto hdac_attach_fail; 3236 result = hdac_irq_alloc(sc); 3237 if (result != 0) 3238 goto hdac_attach_fail; 3239 3240 /* Get Capabilities */ 3241 result = hdac_get_capabilities(sc); 3242 if (result != 0) 3243 goto hdac_attach_fail; 3244 3245 /* Allocate CORB and RIRB dma memory */ 3246 result = hdac_dma_alloc(sc, &sc->corb_dma, 3247 sc->corb_size * sizeof(uint32_t)); 3248 if (result != 0) 3249 goto hdac_attach_fail; 3250 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3251 sc->rirb_size * sizeof(struct hdac_rirb)); 3252 if (result != 0) 3253 goto hdac_attach_fail; 3254 3255 /* Quiesce everything */ 3256 hdac_reset(sc); 3257 3258 /* Disable PCI-Express QOS */ 3259 pci_write_config(sc->dev, 0x44, 3260 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3261 3262 /* Initialize the CORB and RIRB */ 3263 hdac_corb_init(sc); 3264 hdac_rirb_init(sc); 3265 3266 /* Defer remaining of initialization until interrupts are enabled */ 3267 sc->intrhook.ich_func = hdac_attach2; 3268 sc->intrhook.ich_arg = (void *)sc; 3269 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3270 sc->intrhook.ich_func = NULL; 3271 hdac_attach2((void *)sc); 3272 } 3273 3274 return (0); 3275 3276hdac_attach_fail: 3277 hdac_dma_free(&sc->rirb_dma); 3278 hdac_dma_free(&sc->corb_dma); 3279 hdac_irq_free(sc); 3280 hdac_mem_free(sc); 3281 snd_mtxfree(sc->lock); 3282 free(sc, M_DEVBUF); 3283 3284 return (ENXIO); 3285} 3286 3287static void 3288hdac_audio_parse(struct hdac_devinfo *devinfo) 3289{ 3290 struct hdac_softc *sc = devinfo->codec->sc; 3291 struct hdac_widget *w; 3292 uint32_t res; 3293 int i; 3294 nid_t cad, nid; 3295 3296 cad = devinfo->codec->cad; 3297 nid = devinfo->nid; 3298 3299 hdac_command(sc, 3300 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3301 3302 DELAY(100); 3303 3304 res = hdac_command(sc, 3305 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3306 3307 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3308 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3309 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3310 3311 HDA_BOOTVERBOSE( 3312 device_printf(sc->dev, " Vendor: 0x%08x\n", 3313 devinfo->vendor_id); 3314 device_printf(sc->dev, " Device: 0x%08x\n", 3315 devinfo->device_id); 3316 device_printf(sc->dev, " Revision: 0x%08x\n", 3317 devinfo->revision_id); 3318 device_printf(sc->dev, " Stepping: 0x%08x\n", 3319 devinfo->stepping_id); 3320 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3321 sc->pci_subvendor); 3322 device_printf(sc->dev, " Nodes: start=%d " 3323 "endnode=%d total=%d\n", 3324 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3325 ); 3326 3327 res = hdac_command(sc, 3328 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3329 cad); 3330 devinfo->function.audio.supp_stream_formats = res; 3331 3332 res = hdac_command(sc, 3333 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3334 cad); 3335 devinfo->function.audio.supp_pcm_size_rate = res; 3336 3337 res = hdac_command(sc, 3338 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3339 cad); 3340 devinfo->function.audio.outamp_cap = res; 3341 3342 res = hdac_command(sc, 3343 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3344 cad); 3345 devinfo->function.audio.inamp_cap = res; 3346 3347 if (devinfo->nodecnt > 0) { 3348 hdac_unlock(sc); 3349 devinfo->widget = (struct hdac_widget *)malloc( 3350 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3351 M_NOWAIT | M_ZERO); 3352 hdac_lock(sc); 3353 } else 3354 devinfo->widget = NULL; 3355 3356 if (devinfo->widget == NULL) { 3357 device_printf(sc->dev, "unable to allocate widgets!\n"); 3358 devinfo->endnode = devinfo->startnode; 3359 devinfo->nodecnt = 0; 3360 return; 3361 } 3362 3363 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3364 w = hdac_widget_get(devinfo, i); 3365 if (w == NULL) 3366 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3367 else { 3368 w->devinfo = devinfo; 3369 w->nid = i; 3370 w->enable = 1; 3371 w->selconn = -1; 3372 w->pflags = 0; 3373 w->ctlflags = 0; 3374 w->param.eapdbtl = HDAC_INVALID; 3375 hdac_widget_parse(w); 3376 } 3377 } 3378} 3379 3380static void 3381hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3382{ 3383 struct hdac_softc *sc = devinfo->codec->sc; 3384 struct hdac_audio_ctl *ctls; 3385 struct hdac_widget *w, *cw; 3386 int i, j, cnt, max, ocap, icap; 3387 int mute, offset, step, size; 3388 3389 /* XXX This is redundant */ 3390 max = 0; 3391 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3392 w = hdac_widget_get(devinfo, i); 3393 if (w == NULL || w->enable == 0) 3394 continue; 3395 if (w->param.outamp_cap != 0) 3396 max++; 3397 if (w->param.inamp_cap != 0) { 3398 switch (w->type) { 3399 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3400 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3401 for (j = 0; j < w->nconns; j++) { 3402 cw = hdac_widget_get(devinfo, 3403 w->conns[j]); 3404 if (cw == NULL || cw->enable == 0) 3405 continue; 3406 max++; 3407 } 3408 break; 3409 default: 3410 max++; 3411 break; 3412 } 3413 } 3414 } 3415 3416 devinfo->function.audio.ctlcnt = max; 3417 3418 if (max < 1) 3419 return; 3420 3421 hdac_unlock(sc); 3422 ctls = (struct hdac_audio_ctl *)malloc( 3423 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3424 hdac_lock(sc); 3425 3426 if (ctls == NULL) { 3427 /* Blekh! */ 3428 device_printf(sc->dev, "unable to allocate ctls!\n"); 3429 devinfo->function.audio.ctlcnt = 0; 3430 return; 3431 } 3432 3433 cnt = 0; 3434 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3435 if (cnt >= max) { 3436 device_printf(sc->dev, "%s: Ctl overflow!\n", 3437 __func__); 3438 break; 3439 } 3440 w = hdac_widget_get(devinfo, i); 3441 if (w == NULL || w->enable == 0) 3442 continue; 3443 ocap = w->param.outamp_cap; 3444 icap = w->param.inamp_cap; 3445 if (ocap != 0) { 3446 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3447 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3448 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3449 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3450 /*if (offset > step) { 3451 HDA_BOOTVERBOSE( 3452 device_printf(sc->dev, 3453 "HDA_DEBUG: BUGGY outamp: nid=%d " 3454 "[offset=%d > step=%d]\n", 3455 w->nid, offset, step); 3456 ); 3457 offset = step; 3458 }*/ 3459 ctls[cnt].enable = 1; 3460 ctls[cnt].widget = w; 3461 ctls[cnt].mute = mute; 3462 ctls[cnt].step = step; 3463 ctls[cnt].size = size; 3464 ctls[cnt].offset = offset; 3465 ctls[cnt].left = offset; 3466 ctls[cnt].right = offset; 3467 ctls[cnt++].dir = HDA_CTL_OUT; 3468 } 3469 3470 if (icap != 0) { 3471 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3472 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3473 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3474 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3475 /*if (offset > step) { 3476 HDA_BOOTVERBOSE( 3477 device_printf(sc->dev, 3478 "HDA_DEBUG: BUGGY inamp: nid=%d " 3479 "[offset=%d > step=%d]\n", 3480 w->nid, offset, step); 3481 ); 3482 offset = step; 3483 }*/ 3484 switch (w->type) { 3485 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3486 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3487 for (j = 0; j < w->nconns; j++) { 3488 if (cnt >= max) { 3489 device_printf(sc->dev, 3490 "%s: Ctl overflow!\n", 3491 __func__); 3492 break; 3493 } 3494 cw = hdac_widget_get(devinfo, 3495 w->conns[j]); 3496 if (cw == NULL || cw->enable == 0) 3497 continue; 3498 ctls[cnt].enable = 1; 3499 ctls[cnt].widget = w; 3500 ctls[cnt].childwidget = cw; 3501 ctls[cnt].index = j; 3502 ctls[cnt].mute = mute; 3503 ctls[cnt].step = step; 3504 ctls[cnt].size = size; 3505 ctls[cnt].offset = offset; 3506 ctls[cnt].left = offset; 3507 ctls[cnt].right = offset; 3508 ctls[cnt++].dir = HDA_CTL_IN; 3509 } 3510 break; 3511 default: 3512 if (cnt >= max) { 3513 device_printf(sc->dev, 3514 "%s: Ctl overflow!\n", 3515 __func__); 3516 break; 3517 } 3518 ctls[cnt].enable = 1; 3519 ctls[cnt].widget = w; 3520 ctls[cnt].mute = mute; 3521 ctls[cnt].step = step; 3522 ctls[cnt].size = size; 3523 ctls[cnt].offset = offset; 3524 ctls[cnt].left = offset; 3525 ctls[cnt].right = offset; 3526 ctls[cnt++].dir = HDA_CTL_IN; 3527 break; 3528 } 3529 } 3530 } 3531 3532 devinfo->function.audio.ctl = ctls; 3533} 3534 3535static const struct { 3536 uint32_t model; 3537 uint32_t id; 3538 uint32_t set, unset; 3539} hdac_quirks[] = { 3540 /* 3541 * XXX Force stereo quirk. Monoural recording / playback 3542 * on few codecs (especially ALC880) seems broken or 3543 * perhaps unsupported. 3544 */ 3545 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3546 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3547 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3548 HDA_QUIRK_GPIO0, 0 }, 3549 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3550 HDA_QUIRK_GPIO0, 0 }, 3551 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3552 HDA_QUIRK_GPIO0, 0 }, 3553 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3554 HDA_QUIRK_EAPDINV, 0 }, 3555 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3556 HDA_QUIRK_EAPDINV, 0 }, 3557 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3558 HDA_QUIRK_GPIO1, 0 }, 3559 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3560 HDA_QUIRK_EAPDINV, 0 }, 3561 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3562 HDA_QUIRK_EAPDINV, 0 }, 3563 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3564 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3565 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3566 0, HDA_QUIRK_FORCESTEREO }, 3567 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3568 HDA_QUIRK_SOFTPCMVOL, 0 } 3569}; 3570#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3571 3572static void 3573hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3574{ 3575 struct hdac_widget *w; 3576 struct hdac_audio_ctl *ctl; 3577 uint32_t id, subvendor; 3578 int i; 3579 3580 id = hdac_codec_id(devinfo); 3581 subvendor = devinfo->codec->sc->pci_subvendor; 3582 3583 /* 3584 * Quirks 3585 */ 3586 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3587 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3588 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3589 continue; 3590 if (hdac_quirks[i].set != 0) 3591 devinfo->function.audio.quirks |= 3592 hdac_quirks[i].set; 3593 if (hdac_quirks[i].unset != 0) 3594 devinfo->function.audio.quirks &= 3595 ~(hdac_quirks[i].unset); 3596 } 3597 3598 switch (id) { 3599 case HDA_CODEC_ALC260: 3600 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3601 w = hdac_widget_get(devinfo, i); 3602 if (w == NULL || w->enable == 0) 3603 continue; 3604 if (w->type != 3605 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3606 continue; 3607 if (w->nid != 5) 3608 w->enable = 0; 3609 } 3610 break; 3611 case HDA_CODEC_ALC861: 3612 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3613 if (ctl != NULL) 3614 ctl->muted = HDA_AMP_MUTE_ALL; 3615 break; 3616 case HDA_CODEC_ALC880: 3617 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3618 w = hdac_widget_get(devinfo, i); 3619 if (w == NULL || w->enable == 0) 3620 continue; 3621 if (w->type == 3622 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3623 w->nid != 9 && w->nid != 29) { 3624 w->enable = 0; 3625 } else if (w->type != 3626 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3627 w->nid == 29) { 3628 w->type = 3629 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3630 w->param.widget_cap &= 3631 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3632 w->param.widget_cap |= 3633 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3634 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3635 strlcpy(w->name, "beep widget", sizeof(w->name)); 3636 } 3637 } 3638 break; 3639 case HDA_CODEC_AD1981HD: 3640 w = hdac_widget_get(devinfo, 11); 3641 if (w != NULL && w->enable != 0 && w->nconns > 3) 3642 w->selconn = 3; 3643 if (subvendor == IBM_M52_SUBVENDOR) { 3644 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3645 if (ctl != NULL) 3646 ctl->ossmask = SOUND_MASK_SPEAKER; 3647 } 3648 break; 3649 case HDA_CODEC_AD1986A: 3650 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3651 w = hdac_widget_get(devinfo, i); 3652 if (w == NULL || w->enable == 0) 3653 continue; 3654 if (w->type != 3655 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3656 continue; 3657 if (w->nid != 3) 3658 w->enable = 0; 3659 } 3660 break; 3661 case HDA_CODEC_STAC9221: 3662 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3663 w = hdac_widget_get(devinfo, i); 3664 if (w == NULL || w->enable == 0) 3665 continue; 3666 if (w->type != 3667 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3668 continue; 3669 if (w->nid != 2) 3670 w->enable = 0; 3671 } 3672 break; 3673 case HDA_CODEC_STAC9221D: 3674 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3675 w = hdac_widget_get(devinfo, i); 3676 if (w == NULL || w->enable == 0) 3677 continue; 3678 if (w->type == 3679 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3680 w->nid != 6) 3681 w->enable = 0; 3682 3683 } 3684 break; 3685 default: 3686 break; 3687 } 3688} 3689 3690static int 3691hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3692{ 3693 int *dev = &devinfo->function.audio.ossidx; 3694 3695 while (*dev < SOUND_MIXER_NRDEVICES) { 3696 switch (*dev) { 3697 case SOUND_MIXER_VOLUME: 3698 case SOUND_MIXER_BASS: 3699 case SOUND_MIXER_TREBLE: 3700 case SOUND_MIXER_PCM: 3701 case SOUND_MIXER_SPEAKER: 3702 case SOUND_MIXER_LINE: 3703 case SOUND_MIXER_MIC: 3704 case SOUND_MIXER_CD: 3705 case SOUND_MIXER_RECLEV: 3706 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3707 (*dev)++; 3708 break; 3709 default: 3710 return (*dev)++; 3711 break; 3712 } 3713 } 3714 3715 return (-1); 3716} 3717 3718static int 3719hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3720{ 3721 struct hdac_widget *w; 3722 int i, ret = 0; 3723 3724 if (depth > HDA_PARSE_MAXDEPTH) 3725 return (0); 3726 w = hdac_widget_get(devinfo, nid); 3727 if (w == NULL || w->enable == 0) 3728 return (0); 3729 switch (w->type) { 3730 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3731 w->pflags |= HDA_DAC_PATH; 3732 ret = 1; 3733 break; 3734 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3735 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3736 for (i = 0; i < w->nconns; i++) { 3737 if (hdac_widget_find_dac_path(devinfo, 3738 w->conns[i], depth + 1) != 0) { 3739 if (w->selconn == -1) 3740 w->selconn = i; 3741 ret = 1; 3742 w->pflags |= HDA_DAC_PATH; 3743 } 3744 } 3745 break; 3746 default: 3747 break; 3748 } 3749 return (ret); 3750} 3751 3752static int 3753hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3754{ 3755 struct hdac_widget *w; 3756 int i, conndev, ret = 0; 3757 3758 if (depth > HDA_PARSE_MAXDEPTH) 3759 return (0); 3760 w = hdac_widget_get(devinfo, nid); 3761 if (w == NULL || w->enable == 0) 3762 return (0); 3763 switch (w->type) { 3764 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3765 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3766 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3767 for (i = 0; i < w->nconns; i++) { 3768 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3769 depth + 1) != 0) { 3770 if (w->selconn == -1) 3771 w->selconn = i; 3772 w->pflags |= HDA_ADC_PATH; 3773 ret = 1; 3774 } 3775 } 3776 break; 3777 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3778 conndev = w->wclass.pin.config & 3779 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3780 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3781 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3782 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3783 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3784 w->pflags |= HDA_ADC_PATH; 3785 ret = 1; 3786 } 3787 break; 3788 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3789 if (w->pflags & HDA_DAC_PATH) { 3790 w->pflags |= HDA_ADC_PATH; 3791 ret = 1; 3792 } 3793 break;*/ 3794 default: 3795 break; 3796 } 3797 return (ret); 3798} 3799 3800static uint32_t 3801hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3802 nid_t nid, nid_t pnid, int index, int depth) 3803{ 3804 struct hdac_widget *w, *pw; 3805 struct hdac_audio_ctl *ctl; 3806 uint32_t fl = 0; 3807 int i, ossdev, conndev, strategy; 3808 3809 if (depth > HDA_PARSE_MAXDEPTH) 3810 return (0); 3811 3812 w = hdac_widget_get(devinfo, nid); 3813 if (w == NULL || w->enable == 0) 3814 return (0); 3815 3816 pw = hdac_widget_get(devinfo, pnid); 3817 strategy = devinfo->function.audio.parsing_strategy; 3818 3819 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3820 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3821 for (i = 0; i < w->nconns; i++) { 3822 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3823 w->nid, i, depth + 1); 3824 } 3825 w->ctlflags |= fl; 3826 return (fl); 3827 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3828 (w->pflags & HDA_DAC_PATH)) { 3829 i = 0; 3830 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3831 if (ctl->enable == 0 || ctl->widget == NULL) 3832 continue; 3833 /* XXX This should be compressed! */ 3834 if ((ctl->widget->nid == w->nid) || 3835 (ctl->widget->nid == pnid && ctl->index == index && 3836 (ctl->dir & HDA_CTL_IN)) || 3837 (ctl->widget->nid == pnid && pw != NULL && 3838 pw->type == 3839 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3840 (pw->nconns < 2 || pw->selconn == index || 3841 pw->selconn == -1) && 3842 (ctl->dir & HDA_CTL_OUT)) || 3843 (strategy == HDA_PARSE_DIRECT && 3844 ctl->widget->nid == w->nid)) { 3845 /*if (pw != NULL && pw->selconn == -1) 3846 pw->selconn = index; 3847 fl |= SOUND_MASK_VOLUME; 3848 fl |= SOUND_MASK_PCM; 3849 ctl->ossmask |= SOUND_MASK_VOLUME; 3850 ctl->ossmask |= SOUND_MASK_PCM; 3851 ctl->ossdev = SOUND_MIXER_PCM;*/ 3852 if (!(w->ctlflags & SOUND_MASK_PCM) || 3853 (pw != NULL && 3854 !(pw->ctlflags & SOUND_MASK_PCM))) { 3855 fl |= SOUND_MASK_VOLUME; 3856 fl |= SOUND_MASK_PCM; 3857 ctl->ossmask |= SOUND_MASK_VOLUME; 3858 ctl->ossmask |= SOUND_MASK_PCM; 3859 ctl->ossdev = SOUND_MIXER_PCM; 3860 w->ctlflags |= SOUND_MASK_VOLUME; 3861 w->ctlflags |= SOUND_MASK_PCM; 3862 if (pw != NULL) { 3863 if (pw->selconn == -1) 3864 pw->selconn = index; 3865 pw->ctlflags |= 3866 SOUND_MASK_VOLUME; 3867 pw->ctlflags |= 3868 SOUND_MASK_PCM; 3869 } 3870 } 3871 } 3872 } 3873 w->ctlflags |= fl; 3874 return (fl); 3875 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3876 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3877 (w->pflags & HDA_ADC_PATH)) { 3878 conndev = w->wclass.pin.config & 3879 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3880 i = 0; 3881 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3882 if (ctl->enable == 0 || ctl->widget == NULL) 3883 continue; 3884 /* XXX This should be compressed! */ 3885 if (((ctl->widget->nid == pnid && ctl->index == index && 3886 (ctl->dir & HDA_CTL_IN)) || 3887 (ctl->widget->nid == pnid && pw != NULL && 3888 pw->type == 3889 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3890 (pw->nconns < 2 || pw->selconn == index || 3891 pw->selconn == -1) && 3892 (ctl->dir & HDA_CTL_OUT)) || 3893 (strategy == HDA_PARSE_DIRECT && 3894 ctl->widget->nid == w->nid)) && 3895 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3896 if (pw != NULL && pw->selconn == -1) 3897 pw->selconn = index; 3898 ossdev = 0; 3899 switch (conndev) { 3900 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3901 ossdev = SOUND_MIXER_MIC; 3902 break; 3903 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3904 ossdev = SOUND_MIXER_LINE; 3905 break; 3906 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3907 ossdev = SOUND_MIXER_CD; 3908 break; 3909 default: 3910 ossdev = 3911 hdac_audio_ctl_ossmixer_getnextdev( 3912 devinfo); 3913 if (ossdev < 0) 3914 ossdev = 0; 3915 break; 3916 } 3917 if (strategy == HDA_PARSE_MIXER) { 3918 fl |= SOUND_MASK_VOLUME; 3919 ctl->ossmask |= SOUND_MASK_VOLUME; 3920 } 3921 fl |= 1 << ossdev; 3922 ctl->ossmask |= 1 << ossdev; 3923 ctl->ossdev = ossdev; 3924 } 3925 } 3926 w->ctlflags |= fl; 3927 return (fl); 3928 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3929 i = 0; 3930 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3931 if (ctl->enable == 0 || ctl->widget == NULL) 3932 continue; 3933 /* XXX This should be compressed! */ 3934 if (((ctl->widget->nid == pnid && ctl->index == index && 3935 (ctl->dir & HDA_CTL_IN)) || 3936 (ctl->widget->nid == pnid && pw != NULL && 3937 pw->type == 3938 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3939 (pw->nconns < 2 || pw->selconn == index || 3940 pw->selconn == -1) && 3941 (ctl->dir & HDA_CTL_OUT)) || 3942 (strategy == HDA_PARSE_DIRECT && 3943 ctl->widget->nid == w->nid)) && 3944 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3945 if (pw != NULL && pw->selconn == -1) 3946 pw->selconn = index; 3947 fl |= SOUND_MASK_VOLUME; 3948 fl |= SOUND_MASK_SPEAKER; 3949 ctl->ossmask |= SOUND_MASK_VOLUME; 3950 ctl->ossmask |= SOUND_MASK_SPEAKER; 3951 ctl->ossdev = SOUND_MIXER_SPEAKER; 3952 } 3953 } 3954 w->ctlflags |= fl; 3955 return (fl); 3956 } 3957 return (0); 3958} 3959 3960static uint32_t 3961hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3962{ 3963 struct hdac_widget *w, *cw; 3964 struct hdac_audio_ctl *ctl; 3965 uint32_t fl; 3966 int i; 3967 3968 if (depth > HDA_PARSE_MAXDEPTH) 3969 return (0); 3970 3971 w = hdac_widget_get(devinfo, nid); 3972 if (w == NULL || w->enable == 0) 3973 return (0); 3974 /*if (!(w->pflags & HDA_ADC_PATH)) 3975 return (0); 3976 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3977 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3978 return (0);*/ 3979 i = 0; 3980 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3981 if (ctl->enable == 0 || ctl->widget == NULL) 3982 continue; 3983 if (ctl->widget->nid == nid) { 3984 ctl->ossmask |= SOUND_MASK_RECLEV; 3985 w->ctlflags |= SOUND_MASK_RECLEV; 3986 return (SOUND_MASK_RECLEV); 3987 } 3988 } 3989 for (i = 0; i < w->nconns; i++) { 3990 cw = hdac_widget_get(devinfo, w->conns[i]); 3991 if (cw == NULL || cw->enable == 0) 3992 continue; 3993 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3994 continue; 3995 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3996 if (fl != 0) { 3997 cw->ctlflags |= fl; 3998 w->ctlflags |= fl; 3999 return (fl); 4000 } 4001 } 4002 return (0); 4003} 4004 4005static int 4006hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4007{ 4008 struct hdac_widget *w, *cw; 4009 int i, child = 0; 4010 4011 if (depth > HDA_PARSE_MAXDEPTH) 4012 return (0); 4013 4014 w = hdac_widget_get(devinfo, nid); 4015 if (w == NULL || w->enable == 0) 4016 return (0); 4017 /*if (!(w->pflags & HDA_ADC_PATH)) 4018 return (0); 4019 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4020 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4021 return (0);*/ 4022 /* XXX weak! */ 4023 for (i = 0; i < w->nconns; i++) { 4024 cw = hdac_widget_get(devinfo, w->conns[i]); 4025 if (cw == NULL) 4026 continue; 4027 if (++child > 1) { 4028 w->pflags |= HDA_ADC_RECSEL; 4029 return (1); 4030 } 4031 } 4032 for (i = 0; i < w->nconns; i++) { 4033 if (hdac_audio_ctl_recsel_build(devinfo, 4034 w->conns[i], depth + 1) != 0) 4035 return (1); 4036 } 4037 return (0); 4038} 4039 4040static int 4041hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4042{ 4043 struct hdac_widget *w, *cw; 4044 int i, j, conndev, found_dac = 0; 4045 int strategy; 4046 4047 strategy = devinfo->function.audio.parsing_strategy; 4048 4049 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4050 w = hdac_widget_get(devinfo, i); 4051 if (w == NULL || w->enable == 0) 4052 continue; 4053 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4054 continue; 4055 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4056 continue; 4057 conndev = w->wclass.pin.config & 4058 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4059 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4060 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4061 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4062 continue; 4063 for (j = 0; j < w->nconns; j++) { 4064 cw = hdac_widget_get(devinfo, w->conns[j]); 4065 if (cw == NULL || cw->enable == 0) 4066 continue; 4067 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4068 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4069 cw->type == 4070 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4071 continue; 4072 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4073 != 0) { 4074 if (w->selconn == -1) 4075 w->selconn = j; 4076 w->pflags |= HDA_DAC_PATH; 4077 found_dac++; 4078 } 4079 } 4080 } 4081 4082 return (found_dac); 4083} 4084 4085static void 4086hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4087{ 4088 struct hdac_widget *w; 4089 struct hdac_audio_ctl *ctl; 4090 int i, j, dacs, strategy; 4091 4092 /* Construct DAC path */ 4093 strategy = HDA_PARSE_MIXER; 4094 devinfo->function.audio.parsing_strategy = strategy; 4095 HDA_BOOTVERBOSE( 4096 device_printf(devinfo->codec->sc->dev, 4097 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4098 HDA_WIDGET_PARSER_REV); 4099 ); 4100 dacs = hdac_audio_build_tree_strategy(devinfo); 4101 if (dacs == 0) { 4102 HDA_BOOTVERBOSE( 4103 device_printf(devinfo->codec->sc->dev, 4104 "HDA_DEBUG: HWiP: 0 DAC path found! " 4105 "Retrying parser " 4106 "using HDA_PARSE_DIRECT strategy.\n"); 4107 ); 4108 strategy = HDA_PARSE_DIRECT; 4109 devinfo->function.audio.parsing_strategy = strategy; 4110 dacs = hdac_audio_build_tree_strategy(devinfo); 4111 } 4112 4113 HDA_BOOTVERBOSE( 4114 device_printf(devinfo->codec->sc->dev, 4115 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4116 "strategy.\n", 4117 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4118 ); 4119 4120 /* Construct ADC path */ 4121 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4122 w = hdac_widget_get(devinfo, i); 4123 if (w == NULL || w->enable == 0) 4124 continue; 4125 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4126 continue; 4127 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4128 } 4129 4130 /* Output mixers */ 4131 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4132 w = hdac_widget_get(devinfo, i); 4133 if (w == NULL || w->enable == 0) 4134 continue; 4135 if ((strategy == HDA_PARSE_MIXER && 4136 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4137 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4138 && (w->pflags & HDA_DAC_PATH)) || 4139 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4140 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4141 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4142 w->nid, devinfo->startnode - 1, 0, 0); 4143 } else if (w->type == 4144 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4145 j = 0; 4146 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4147 NULL) { 4148 if (ctl->enable == 0 || ctl->widget == NULL) 4149 continue; 4150 if (ctl->widget->nid != w->nid) 4151 continue; 4152 ctl->ossmask |= SOUND_MASK_VOLUME; 4153 ctl->ossmask |= SOUND_MASK_SPEAKER; 4154 ctl->ossdev = SOUND_MIXER_SPEAKER; 4155 w->ctlflags |= SOUND_MASK_VOLUME; 4156 w->ctlflags |= SOUND_MASK_SPEAKER; 4157 } 4158 } 4159 } 4160 4161 /* Input mixers (rec) */ 4162 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4163 w = hdac_widget_get(devinfo, i); 4164 if (w == NULL || w->enable == 0) 4165 continue; 4166 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4167 w->pflags & HDA_ADC_PATH)) 4168 continue; 4169 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4170 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4171 } 4172} 4173 4174#define HDA_COMMIT_CONN (1 << 0) 4175#define HDA_COMMIT_CTRL (1 << 1) 4176#define HDA_COMMIT_EAPD (1 << 2) 4177#define HDA_COMMIT_GPIO (1 << 3) 4178#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4179 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4180 4181static void 4182hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4183{ 4184 struct hdac_softc *sc = devinfo->codec->sc; 4185 struct hdac_widget *w; 4186 nid_t cad; 4187 int i; 4188 4189 if (!(cfl & HDA_COMMIT_ALL)) 4190 return; 4191 4192 cad = devinfo->codec->cad; 4193 4194 if (cfl & HDA_COMMIT_GPIO) { 4195 uint32_t gdata, gmask, gdir; 4196 int commitgpio = 0; 4197 4198 gdata = 0; 4199 gmask = 0; 4200 gdir = 0; 4201 4202 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4203 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4204 0x7e7, 0), cad); 4205 4206 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4207 commitgpio = 1; 4208 else { 4209 for (i = 0; i < HDA_GPIO_MAX; i++) { 4210 if (!(devinfo->function.audio.quirks & 4211 (1 << i))) 4212 continue; 4213 if (commitgpio == 0) { 4214 commitgpio = 1; 4215 gdata = hdac_command(sc, 4216 HDA_CMD_GET_GPIO_DATA(cad, 4217 devinfo->nid), cad); 4218 gmask = hdac_command(sc, 4219 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4220 devinfo->nid), cad); 4221 gdir = hdac_command(sc, 4222 HDA_CMD_GET_GPIO_DIRECTION(cad, 4223 devinfo->nid), cad); 4224 HDA_BOOTVERBOSE( 4225 device_printf(sc->dev, 4226 "GPIO init: data=0x%08x " 4227 "mask=0x%08x dir=0x%08x\n", 4228 gdata, gmask, gdir); 4229 ); 4230 } 4231 gdata |= 1 << i; 4232 gmask |= 1 << i; 4233 gdir |= 1 << i; 4234 } 4235 } 4236 4237 if (commitgpio != 0) { 4238 HDA_BOOTVERBOSE( 4239 device_printf(sc->dev, 4240 "GPIO commit: data=0x%08x mask=0x%08x " 4241 "dir=0x%08x\n", 4242 gdata, gmask, gdir); 4243 ); 4244 hdac_command(sc, 4245 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4246 gmask), cad); 4247 hdac_command(sc, 4248 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4249 gdir), cad); 4250 hdac_command(sc, 4251 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4252 gdata), cad); 4253 } 4254 } 4255 4256 for (i = 0; i < devinfo->nodecnt; i++) { 4257 w = &devinfo->widget[i]; 4258 if (w == NULL || w->enable == 0) 4259 continue; 4260 if (cfl & HDA_COMMIT_CONN) { 4261 if (w->selconn == -1) 4262 w->selconn = 0; 4263 if (w->nconns > 0) 4264 hdac_widget_connection_select(w, w->selconn); 4265 } 4266 if ((cfl & HDA_COMMIT_CTRL) && 4267 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4268 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4269 (HDA_DAC_PATH | HDA_ADC_PATH)) 4270 device_printf(sc->dev, "WARNING: node %d " 4271 "participate both for DAC/ADC!\n", w->nid); 4272 if (w->pflags & HDA_DAC_PATH) { 4273 w->wclass.pin.ctrl &= 4274 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4275 if ((w->wclass.pin.config & 4276 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4277 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4278 w->wclass.pin.ctrl &= 4279 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4280 } else if (w->pflags & HDA_ADC_PATH) { 4281 w->wclass.pin.ctrl &= 4282 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4283 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4284 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4285 uint32_t pincap = w->wclass.pin.cap; 4286 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4287 w->wclass.pin.ctrl |= 4288 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4289 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4290 ); 4291 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4292 w->wclass.pin.ctrl |= 4293 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4294 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4295 ); 4296 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4297 w->wclass.pin.ctrl |= 4298 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4299 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4300 ); 4301 } 4302 } else 4303 w->wclass.pin.ctrl &= ~( 4304 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4305 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4306 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4307 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4308 hdac_command(sc, 4309 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4310 w->wclass.pin.ctrl), cad); 4311 } 4312 if ((cfl & HDA_COMMIT_EAPD) && 4313 w->param.eapdbtl != HDAC_INVALID) { 4314 uint32_t val; 4315 4316 val = w->param.eapdbtl; 4317 if (devinfo->function.audio.quirks & 4318 HDA_QUIRK_EAPDINV) 4319 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4320 hdac_command(sc, 4321 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4322 val), cad); 4323 4324 } 4325 DELAY(1000); 4326 } 4327} 4328 4329static void 4330hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4331{ 4332 struct hdac_softc *sc = devinfo->codec->sc; 4333 struct hdac_audio_ctl *ctl; 4334 int i; 4335 4336 devinfo->function.audio.mvol = 100 | (100 << 8); 4337 i = 0; 4338 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4339 if (ctl->enable == 0 || ctl->widget == NULL) { 4340 HDA_BOOTVERBOSE( 4341 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4342 i, (ctl->widget != NULL) ? 4343 ctl->widget->nid : -1); 4344 if (ctl->childwidget != NULL) 4345 printf(" childnid=%d", 4346 ctl->childwidget->nid); 4347 if (ctl->widget == NULL) 4348 printf(" NULL WIDGET!"); 4349 printf(" DISABLED\n"); 4350 ); 4351 continue; 4352 } 4353 HDA_BOOTVERBOSE( 4354 if (ctl->ossmask == 0) { 4355 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4356 i, ctl->widget->nid); 4357 if (ctl->childwidget != NULL) 4358 printf(" childnid=%d", 4359 ctl->childwidget->nid); 4360 printf(" Bind to NONE\n"); 4361 } 4362 ); 4363 if (ctl->step > 0) { 4364 ctl->ossval = (ctl->left * 100) / ctl->step; 4365 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4366 } else 4367 ctl->ossval = 0; 4368 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4369 ctl->left, ctl->right); 4370 } 4371} 4372 4373static int 4374hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4375{ 4376 struct hdac_chan *ch; 4377 struct hdac_widget *w; 4378 uint32_t cap, fmtcap, pcmcap, path; 4379 int i, type, ret, max; 4380 4381 if (dir == PCMDIR_PLAY) { 4382 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4383 ch = &devinfo->codec->sc->play; 4384 path = HDA_DAC_PATH; 4385 } else { 4386 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4387 ch = &devinfo->codec->sc->rec; 4388 path = HDA_ADC_PATH; 4389 } 4390 4391 ch->caps = hdac_caps; 4392 ch->caps.fmtlist = ch->fmtlist; 4393 ch->bit16 = 1; 4394 ch->bit32 = 0; 4395 ch->pcmrates[0] = 48000; 4396 ch->pcmrates[1] = 0; 4397 4398 ret = 0; 4399 fmtcap = devinfo->function.audio.supp_stream_formats; 4400 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4401 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4402 4403 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4404 w = hdac_widget_get(devinfo, i); 4405 if (w == NULL || w->enable == 0 || w->type != type || 4406 !(w->pflags & path)) 4407 continue; 4408 cap = w->param.widget_cap; 4409 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4410 continue;*/ 4411 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4412 continue; 4413 cap = w->param.supp_stream_formats; 4414 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4415 } 4416 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4417 }*/ 4418 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4419 continue; 4420 if (ret == 0) { 4421 fmtcap = w->param.supp_stream_formats; 4422 pcmcap = w->param.supp_pcm_size_rate; 4423 } else { 4424 fmtcap &= w->param.supp_stream_formats; 4425 pcmcap &= w->param.supp_pcm_size_rate; 4426 } 4427 ch->io[ret++] = i; 4428 } 4429 ch->io[ret] = -1; 4430 4431 ch->supp_stream_formats = fmtcap; 4432 ch->supp_pcm_size_rate = pcmcap; 4433 4434 /* 4435 * 8bit = 0 4436 * 16bit = 1 4437 * 20bit = 2 4438 * 24bit = 3 4439 * 32bit = 4 4440 */ 4441 if (ret > 0) { 4442 cap = pcmcap; 4443 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4444 ch->bit16 = 1; 4445 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4446 ch->bit16 = 0; 4447 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4448 ch->bit32 = 4; 4449 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4450 ch->bit32 = 3; 4451 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4452 ch->bit32 = 2; 4453 i = 0; 4454 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4455 ch->fmtlist[i++] = AFMT_S16_LE; 4456 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4457 if (ch->bit32 > 0) { 4458 if (!(devinfo->function.audio.quirks & 4459 HDA_QUIRK_FORCESTEREO)) 4460 ch->fmtlist[i++] = AFMT_S32_LE; 4461 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4462 } 4463 ch->fmtlist[i] = 0; 4464 i = 0; 4465 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4466 ch->pcmrates[i++] = 8000; 4467 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4468 ch->pcmrates[i++] = 11025; 4469 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4470 ch->pcmrates[i++] = 16000; 4471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4472 ch->pcmrates[i++] = 22050; 4473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4474 ch->pcmrates[i++] = 32000; 4475 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4476 ch->pcmrates[i++] = 44100; 4477 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4478 ch->pcmrates[i++] = 48000; 4479 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4480 ch->pcmrates[i++] = 88200; 4481 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4482 ch->pcmrates[i++] = 96000; 4483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4484 ch->pcmrates[i++] = 176400; 4485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4486 ch->pcmrates[i++] = 192000; 4487 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4488 ch->pcmrates[i] = 0; 4489 if (i > 0) { 4490 ch->caps.minspeed = ch->pcmrates[0]; 4491 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4492 } 4493 } 4494 4495 return (ret); 4496} 4497 4498static void 4499hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4500{ 4501 struct hdac_audio_ctl *ctl; 4502 struct hdac_softc *sc = devinfo->codec->sc; 4503 int i; 4504 uint32_t fl = 0; 4505 4506 4507 if (flag == 0) { 4508 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4509 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4510 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4511 } 4512 4513 i = 0; 4514 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4515 if (ctl->enable == 0 || ctl->widget == NULL || 4516 ctl->widget->enable == 0) 4517 continue; 4518 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4519 (flag != 0 && (ctl->ossmask & flag))) { 4520 if (banner != NULL) { 4521 device_printf(sc->dev, "\n"); 4522 device_printf(sc->dev, "%s\n", banner); 4523 } 4524 goto hdac_ctl_dump_it_all; 4525 } 4526 } 4527 4528 return; 4529 4530hdac_ctl_dump_it_all: 4531 i = 0; 4532 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4533 if (ctl->enable == 0 || ctl->widget == NULL || 4534 ctl->widget->enable == 0) 4535 continue; 4536 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4537 (flag != 0 && (ctl->ossmask & flag)))) 4538 continue; 4539 if (flag == 0) { 4540 device_printf(sc->dev, "\n"); 4541 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4542 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4543 } 4544 device_printf(sc->dev, " |\n"); 4545 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4546 ctl->widget->nid, ctl->index); 4547 if (ctl->childwidget != NULL) 4548 printf("(nid: %2d) ", ctl->childwidget->nid); 4549 else 4550 printf(" "); 4551 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4552 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4553 ctl->ossmask); 4554 } 4555} 4556 4557static void 4558hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4559{ 4560 uint32_t cap; 4561 4562 cap = fcap; 4563 if (cap != 0) { 4564 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4565 device_printf(sc->dev, " Format:"); 4566 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4567 printf(" AC3"); 4568 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4569 printf(" FLOAT32"); 4570 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4571 printf(" PCM"); 4572 printf("\n"); 4573 } 4574 cap = pcmcap; 4575 if (cap != 0) { 4576 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4577 device_printf(sc->dev, " PCM size:"); 4578 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4579 printf(" 8"); 4580 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4581 printf(" 16"); 4582 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4583 printf(" 20"); 4584 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4585 printf(" 24"); 4586 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4587 printf(" 32"); 4588 printf("\n"); 4589 device_printf(sc->dev, " PCM rate:"); 4590 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4591 printf(" 8"); 4592 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4593 printf(" 11"); 4594 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4595 printf(" 16"); 4596 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4597 printf(" 22"); 4598 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4599 printf(" 32"); 4600 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4601 printf(" 44"); 4602 printf(" 48"); 4603 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4604 printf(" 88"); 4605 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4606 printf(" 96"); 4607 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4608 printf(" 176"); 4609 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4610 printf(" 192"); 4611 printf("\n"); 4612 } 4613} 4614 4615static void 4616hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4617{ 4618 uint32_t pincap, wcap; 4619 4620 pincap = w->wclass.pin.cap; 4621 wcap = w->param.widget_cap; 4622 4623 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4624 device_printf(sc->dev, " "); 4625 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4626 printf(" ISC"); 4627 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4628 printf(" TRQD"); 4629 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4630 printf(" PDC"); 4631 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4632 printf(" HP"); 4633 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4634 printf(" OUT"); 4635 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4636 printf(" IN"); 4637 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4638 printf(" BAL"); 4639 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4640 printf(" VREF["); 4641 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4642 printf(" 50"); 4643 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4644 printf(" 80"); 4645 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4646 printf(" 100"); 4647 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4648 printf(" GROUND"); 4649 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4650 printf(" HIZ"); 4651 printf(" ]"); 4652 } 4653 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4654 printf(" EAPD"); 4655 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4656 printf(" : UNSOL"); 4657 printf("\n"); 4658 device_printf(sc->dev, " Pin config: 0x%08x\n", 4659 w->wclass.pin.config); 4660 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4661 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4662 printf(" HP"); 4663 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4664 printf(" IN"); 4665 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4666 printf(" OUT"); 4667 printf("\n"); 4668} 4669 4670static void 4671hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4672{ 4673 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4674 device_printf(sc->dev, " " 4675 "mute=%d step=%d size=%d offset=%d\n", 4676 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4677 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4678 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4679 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4680} 4681 4682static void 4683hdac_dump_nodes(struct hdac_devinfo *devinfo) 4684{ 4685 struct hdac_softc *sc = devinfo->codec->sc; 4686 struct hdac_widget *w, *cw; 4687 int i, j; 4688 4689 device_printf(sc->dev, "\n"); 4690 device_printf(sc->dev, "Default Parameter\n"); 4691 device_printf(sc->dev, "-----------------\n"); 4692 hdac_dump_audio_formats(sc, 4693 devinfo->function.audio.supp_stream_formats, 4694 devinfo->function.audio.supp_pcm_size_rate); 4695 device_printf(sc->dev, " IN amp: 0x%08x\n", 4696 devinfo->function.audio.inamp_cap); 4697 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4698 devinfo->function.audio.outamp_cap); 4699 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4700 w = hdac_widget_get(devinfo, i); 4701 if (w == NULL) { 4702 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4703 continue; 4704 } 4705 device_printf(sc->dev, "\n"); 4706 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4707 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4708 "DIGITAL" : "ANALOG", 4709 (w->enable == 0) ? " [DISABLED]" : ""); 4710 device_printf(sc->dev, " name: %s\n", w->name); 4711 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4712 w->param.widget_cap); 4713 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4714 w->pflags); 4715 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4716 w->ctlflags); 4717 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4718 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4719 hdac_dump_audio_formats(sc, 4720 w->param.supp_stream_formats, 4721 w->param.supp_pcm_size_rate); 4722 } else if (w->type == 4723 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4724 hdac_dump_pin(sc, w); 4725 if (w->param.eapdbtl != HDAC_INVALID) 4726 device_printf(sc->dev, " EAPD: 0x%08x\n", 4727 w->param.eapdbtl); 4728 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4729 w->param.outamp_cap != 0) 4730 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4731 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4732 w->param.inamp_cap != 0) 4733 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4734 device_printf(sc->dev, " connections: %d\n", w->nconns); 4735 for (j = 0; j < w->nconns; j++) { 4736 cw = hdac_widget_get(devinfo, w->conns[j]); 4737 device_printf(sc->dev, " |\n"); 4738 device_printf(sc->dev, " + <- nid=%d [%s]", 4739 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4740 if (cw == NULL) 4741 printf(" [UNKNOWN]"); 4742 else if (cw->enable == 0) 4743 printf(" [DISABLED]"); 4744 if (w->nconns > 1 && w->selconn == j && w->type != 4745 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4746 printf(" (selected)"); 4747 printf("\n"); 4748 } 4749 } 4750 4751} 4752 4753static int 4754hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4755{ 4756 struct hdac_widget *w, *cw; 4757 struct hdac_softc *sc = devinfo->codec->sc; 4758 int i; 4759 4760 if (depth > HDA_PARSE_MAXDEPTH) 4761 return (0); 4762 4763 w = hdac_widget_get(devinfo, nid); 4764 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4765 return (0); 4766 4767 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4768 device_printf(sc->dev, "\n"); 4769 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4770 device_printf(sc->dev, " ^\n"); 4771 device_printf(sc->dev, " |\n"); 4772 device_printf(sc->dev, " +-----<------+\n"); 4773 } else { 4774 device_printf(sc->dev, " ^\n"); 4775 device_printf(sc->dev, " |\n"); 4776 device_printf(sc->dev, " "); 4777 printf(" nid=%d [%s]\n", w->nid, w->name); 4778 } 4779 4780 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4781 return (1); 4782 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4783 for (i = 0; i < w->nconns; i++) { 4784 cw = hdac_widget_get(devinfo, w->conns[i]); 4785 if (cw == NULL || cw->enable == 0 || cw->type == 4786 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4787 continue; 4788 if (hdac_dump_dac_internal(devinfo, cw->nid, 4789 depth + 1) != 0) 4790 return (1); 4791 } 4792 } else if ((w->type == 4793 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4794 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4795 w->selconn > -1 && w->selconn < w->nconns) { 4796 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4797 depth + 1) != 0) 4798 return (1); 4799 } 4800 4801 return (0); 4802} 4803 4804static void 4805hdac_dump_dac(struct hdac_devinfo *devinfo) 4806{ 4807 struct hdac_widget *w; 4808 struct hdac_softc *sc = devinfo->codec->sc; 4809 int i, printed = 0; 4810 4811 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4812 w = hdac_widget_get(devinfo, i); 4813 if (w == NULL || w->enable == 0) 4814 continue; 4815 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4816 !(w->pflags & HDA_DAC_PATH)) 4817 continue; 4818 if (printed == 0) { 4819 printed = 1; 4820 device_printf(sc->dev, "\n"); 4821 device_printf(sc->dev, "Playback path:\n"); 4822 } 4823 hdac_dump_dac_internal(devinfo, w->nid, 0); 4824 } 4825} 4826 4827static void 4828hdac_dump_adc(struct hdac_devinfo *devinfo) 4829{ 4830 struct hdac_widget *w, *cw; 4831 struct hdac_softc *sc = devinfo->codec->sc; 4832 int i, j; 4833 int printed = 0; 4834 char ossdevs[256]; 4835 4836 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4837 w = hdac_widget_get(devinfo, i); 4838 if (w == NULL || w->enable == 0) 4839 continue; 4840 if (!(w->pflags & HDA_ADC_RECSEL)) 4841 continue; 4842 if (printed == 0) { 4843 printed = 1; 4844 device_printf(sc->dev, "\n"); 4845 device_printf(sc->dev, "Recording sources:\n"); 4846 } 4847 device_printf(sc->dev, "\n"); 4848 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4849 for (j = 0; j < w->nconns; j++) { 4850 cw = hdac_widget_get(devinfo, w->conns[j]); 4851 if (cw == NULL || cw->enable == 0) 4852 continue; 4853 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4854 ossdevs, sizeof(ossdevs)); 4855 device_printf(sc->dev, " |\n"); 4856 device_printf(sc->dev, " + <- nid=%d [%s]", 4857 cw->nid, cw->name); 4858 if (strlen(ossdevs) > 0) { 4859 printf(" [recsrc: %s]", ossdevs); 4860 } 4861 printf("\n"); 4862 } 4863 } 4864} 4865 4866static void 4867hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4868{ 4869 nid_t *nids; 4870 4871 if (pcnt > 0) { 4872 device_printf(sc->dev, "\n"); 4873 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4874 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4875 sc->play.supp_pcm_size_rate); 4876 device_printf(sc->dev, " DAC:"); 4877 for (nids = sc->play.io; *nids != -1; nids++) 4878 printf(" %d", *nids); 4879 printf("\n"); 4880 } 4881 4882 if (rcnt > 0) { 4883 device_printf(sc->dev, "\n"); 4884 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4885 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4886 sc->rec.supp_pcm_size_rate); 4887 device_printf(sc->dev, " ADC:"); 4888 for (nids = sc->rec.io; *nids != -1; nids++) 4889 printf(" %d", *nids); 4890 printf("\n"); 4891 } 4892} 4893 4894static void 4895hdac_release_resources(struct hdac_softc *sc) 4896{ 4897 struct hdac_devinfo *devinfo = NULL; 4898 device_t *devlist = NULL; 4899 int i, devcount; 4900 4901 if (sc == NULL) 4902 return; 4903 4904 hdac_lock(sc); 4905 if (sc->polling != 0) 4906 callout_stop(&sc->poll_hdac); 4907 hdac_reset(sc); 4908 hdac_unlock(sc); 4909 snd_mtxfree(sc->lock); 4910 4911 device_get_children(sc->dev, &devlist, &devcount); 4912 for (i = 0; devlist != NULL && i < devcount; i++) { 4913 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4914 if (devinfo == NULL) 4915 continue; 4916 if (devinfo->widget != NULL) 4917 free(devinfo->widget, M_HDAC); 4918 if (devinfo->node_type == 4919 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4920 devinfo->function.audio.ctl != NULL) 4921 free(devinfo->function.audio.ctl, M_HDAC); 4922 free(devinfo, M_HDAC); 4923 device_delete_child(sc->dev, devlist[i]); 4924 } 4925 if (devlist != NULL) 4926 free(devlist, M_TEMP); 4927 4928 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4929 if (sc->codecs[i] != NULL) 4930 free(sc->codecs[i], M_HDAC); 4931 sc->codecs[i] = NULL; 4932 } 4933 4934 hdac_dma_free(&sc->rirb_dma); 4935 hdac_dma_free(&sc->corb_dma); 4936 if (sc->play.blkcnt > 0) 4937 hdac_dma_free(&sc->play.bdl_dma); 4938 if (sc->rec.blkcnt > 0) 4939 hdac_dma_free(&sc->rec.bdl_dma); 4940 hdac_irq_free(sc); 4941 hdac_mem_free(sc); 4942 free(sc, M_DEVBUF); 4943 4944} 4945 4946/* This function surely going to make its way into upper level someday. */ 4947static void 4948hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4949{ 4950 const char *res = NULL; 4951 int i = 0, j, k, len, inv; 4952 4953 if (on != NULL) 4954 *on = 0; 4955 if (off != NULL) 4956 *off = 0; 4957 if (sc == NULL) 4958 return; 4959 if (resource_string_value(device_get_name(sc->dev), 4960 device_get_unit(sc->dev), "config", &res) != 0) 4961 return; 4962 if (!(res != NULL && strlen(res) > 0)) 4963 return; 4964 HDA_BOOTVERBOSE( 4965 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4966 ); 4967 for (;;) { 4968 while (res[i] != '\0' && 4969 (res[i] == ',' || isspace(res[i]) != 0)) 4970 i++; 4971 if (res[i] == '\0') { 4972 HDA_BOOTVERBOSE( 4973 printf("\n"); 4974 ); 4975 return; 4976 } 4977 j = i; 4978 while (res[j] != '\0' && 4979 !(res[j] == ',' || isspace(res[j]) != 0)) 4980 j++; 4981 len = j - i; 4982 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4983 inv = 2; 4984 else 4985 inv = 0; 4986 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4987 if (strncmp(res + i + inv, 4988 hdac_quirks_tab[k].key, len - inv) != 0) 4989 continue; 4990 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4991 break; 4992 HDA_BOOTVERBOSE( 4993 printf(" %s%s", (inv != 0) ? "no" : "", 4994 hdac_quirks_tab[k].key); 4995 ); 4996 if (inv == 0 && on != NULL) 4997 *on |= hdac_quirks_tab[k].value; 4998 else if (inv != 0 && off != NULL) 4999 *off |= hdac_quirks_tab[k].value; 5000 break; 5001 } 5002 i = j; 5003 } 5004} 5005 5006#ifdef SND_DYNSYSCTL 5007static int 5008sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5009{ 5010 struct hdac_softc *sc; 5011 struct hdac_devinfo *devinfo; 5012 device_t dev; 5013 uint32_t ctl; 5014 int err, val; 5015 5016 dev = oidp->oid_arg1; 5017 devinfo = pcm_getdevinfo(dev); 5018 if (devinfo == NULL || devinfo->codec == NULL || 5019 devinfo->codec->sc == NULL) 5020 return (EINVAL); 5021 sc = devinfo->codec->sc; 5022 hdac_lock(sc); 5023 val = sc->polling; 5024 hdac_unlock(sc); 5025 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5026 5027 if (err || req->newptr == NULL) 5028 return (err); 5029 if (val < 0 || val > 1) 5030 return (EINVAL); 5031 5032 hdac_lock(sc); 5033 if (val != sc->polling) { 5034 if (hda_chan_active(sc) != 0) 5035 err = EBUSY; 5036 else if (val == 0) { 5037 callout_stop(&sc->poll_hdac); 5038 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5039 sc->rirb_size / 2); 5040 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5041 ctl |= HDAC_RIRBCTL_RINTCTL; 5042 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5043 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5044 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5045 sc->polling = 0; 5046 DELAY(1000); 5047 } else { 5048 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5049 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5050 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5051 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5052 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5053 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5054 sc); 5055 sc->polling = 1; 5056 DELAY(1000); 5057 } 5058 } 5059 hdac_unlock(sc); 5060 5061 return (err); 5062} 5063#endif 5064 5065static void 5066hdac_attach2(void *arg) 5067{ 5068 struct hdac_softc *sc; 5069 struct hdac_widget *w; 5070 struct hdac_audio_ctl *ctl; 5071 uint32_t quirks_on, quirks_off; 5072 int pcnt, rcnt; 5073 int i; 5074 char status[SND_STATUSLEN]; 5075 device_t *devlist = NULL; 5076 int devcount; 5077 struct hdac_devinfo *devinfo = NULL; 5078 5079 sc = (struct hdac_softc *)arg; 5080 5081 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5082 5083 HDA_BOOTVERBOSE( 5084 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5085 quirks_on, quirks_off); 5086 ); 5087 5088 hdac_lock(sc); 5089 5090 /* Remove ourselves from the config hooks */ 5091 if (sc->intrhook.ich_func != NULL) { 5092 config_intrhook_disestablish(&sc->intrhook); 5093 sc->intrhook.ich_func = NULL; 5094 } 5095 5096 /* Start the corb and rirb engines */ 5097 HDA_BOOTVERBOSE( 5098 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5099 ); 5100 hdac_corb_start(sc); 5101 HDA_BOOTVERBOSE( 5102 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5103 ); 5104 hdac_rirb_start(sc); 5105 5106 HDA_BOOTVERBOSE( 5107 device_printf(sc->dev, 5108 "HDA_DEBUG: Enabling controller interrupt...\n"); 5109 ); 5110 if (sc->polling == 0) 5111 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5112 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5113 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5114 HDAC_GCTL_UNSOL); 5115 5116 DELAY(1000); 5117 5118 HDA_BOOTVERBOSE( 5119 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5120 ); 5121 hdac_scan_codecs(sc); 5122 5123 device_get_children(sc->dev, &devlist, &devcount); 5124 for (i = 0; devlist != NULL && i < devcount; i++) { 5125 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5126 if (devinfo != NULL && devinfo->node_type == 5127 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5128 break; 5129 } else 5130 devinfo = NULL; 5131 } 5132 if (devlist != NULL) 5133 free(devlist, M_TEMP); 5134 5135 if (devinfo == NULL) { 5136 hdac_unlock(sc); 5137 device_printf(sc->dev, "Audio Function Group not found!\n"); 5138 hdac_release_resources(sc); 5139 return; 5140 } 5141 5142 HDA_BOOTVERBOSE( 5143 device_printf(sc->dev, 5144 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5145 devinfo->nid, devinfo->codec->cad); 5146 ); 5147 hdac_audio_parse(devinfo); 5148 HDA_BOOTVERBOSE( 5149 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5150 ); 5151 hdac_audio_ctl_parse(devinfo); 5152 HDA_BOOTVERBOSE( 5153 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5154 ); 5155 hdac_vendor_patch_parse(devinfo); 5156 if (quirks_on != 0) 5157 devinfo->function.audio.quirks |= quirks_on; 5158 if (quirks_off != 0) 5159 devinfo->function.audio.quirks &= ~quirks_off; 5160 5161 /* XXX Disable all DIGITAL path. */ 5162 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5163 w = hdac_widget_get(devinfo, i); 5164 if (w == NULL) 5165 continue; 5166 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5167 w->enable = 0; 5168 continue; 5169 } 5170 /* XXX Disable useless pin ? */ 5171 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5172 (w->wclass.pin.config & 5173 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5174 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5175 w->enable = 0; 5176 } 5177 i = 0; 5178 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5179 if (ctl->widget == NULL) 5180 continue; 5181 w = ctl->widget; 5182 if (w->enable == 0) 5183 ctl->enable = 0; 5184 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5185 ctl->enable = 0; 5186 w = ctl->childwidget; 5187 if (w == NULL) 5188 continue; 5189 if (w->enable == 0 || 5190 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5191 ctl->enable = 0; 5192 } 5193 5194 HDA_BOOTVERBOSE( 5195 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5196 ); 5197 hdac_audio_build_tree(devinfo); 5198 5199 HDA_BOOTVERBOSE( 5200 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5201 ); 5202 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5203 HDA_BOOTVERBOSE( 5204 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5205 ); 5206 hdac_audio_ctl_commit(devinfo); 5207 5208 HDA_BOOTVERBOSE( 5209 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5210 ); 5211 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5212 HDA_BOOTVERBOSE( 5213 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5214 ); 5215 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5216 5217 hdac_unlock(sc); 5218 HDA_BOOTVERBOSE( 5219 device_printf(sc->dev, 5220 "HDA_DEBUG: OSS mixer initialization...\n"); 5221 ); 5222 5223 /* 5224 * There is no point of return after this. If the driver failed, 5225 * so be it. Let the detach procedure do all the cleanup. 5226 */ 5227 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5228 device_printf(sc->dev, "Can't register mixer\n"); 5229 5230 if (pcnt > 0) 5231 pcnt = 1; 5232 if (rcnt > 0) 5233 rcnt = 1; 5234 5235 HDA_BOOTVERBOSE( 5236 device_printf(sc->dev, 5237 "HDA_DEBUG: Registering PCM channels...\n"); 5238 ); 5239 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5240 device_printf(sc->dev, "Can't register PCM\n"); 5241 5242 sc->registered++; 5243 5244 for (i = 0; i < pcnt; i++) 5245 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5246 for (i = 0; i < rcnt; i++) 5247 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5248 5249#ifdef SND_DYNSYSCTL 5250 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5251 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5252 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5253 sysctl_hdac_polling, "I", "Enable polling mode"); 5254#endif 5255 5256 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5257 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5258 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5259 pcm_setstatus(sc->dev, status); 5260 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5261 HDA_BOOTVERBOSE( 5262 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5263 hdac_codec_id(devinfo)); 5264 ); 5265 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5266 HDA_DRV_TEST_REV); 5267 5268 HDA_BOOTVERBOSE( 5269 if (devinfo->function.audio.quirks != 0) { 5270 device_printf(sc->dev, "\n"); 5271 device_printf(sc->dev, "HDA config/quirks:"); 5272 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5273 if (devinfo->function.audio.quirks & 5274 hdac_quirks_tab[i].value) 5275 printf(" %s", hdac_quirks_tab[i].key); 5276 } 5277 printf("\n"); 5278 } 5279 device_printf(sc->dev, "\n"); 5280 device_printf(sc->dev, "+-------------------+\n"); 5281 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5282 device_printf(sc->dev, "+-------------------+\n"); 5283 hdac_dump_nodes(devinfo); 5284 device_printf(sc->dev, "\n"); 5285 device_printf(sc->dev, "+------------------------+\n"); 5286 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5287 device_printf(sc->dev, "+------------------------+\n"); 5288 device_printf(sc->dev, "\n"); 5289 i = 0; 5290 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5291 device_printf(sc->dev, "%3d: nid=%d", i, 5292 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5293 if (ctl->childwidget != NULL) 5294 printf(" cnid=%d", ctl->childwidget->nid); 5295 printf(" dir=0x%x index=%d " 5296 "ossmask=0x%08x ossdev=%d%s\n", 5297 ctl->dir, ctl->index, 5298 ctl->ossmask, ctl->ossdev, 5299 (ctl->enable == 0) ? " [DISABLED]" : ""); 5300 } 5301 device_printf(sc->dev, "\n"); 5302 device_printf(sc->dev, "+-----------------------------------+\n"); 5303 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5304 device_printf(sc->dev, "+-----------------------------------+\n"); 5305 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5306 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5307 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5308 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5309 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5310 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5311 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5312 hdac_dump_ctls(devinfo, NULL, 0); 5313 hdac_dump_dac(devinfo); 5314 hdac_dump_adc(devinfo); 5315 device_printf(sc->dev, "\n"); 5316 device_printf(sc->dev, "+--------------------------------------+\n"); 5317 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5318 device_printf(sc->dev, "+--------------------------------------+\n"); 5319 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5320 ); 5321 5322 if (sc->polling != 0) { 5323 hdac_lock(sc); 5324 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5325 hdac_unlock(sc); 5326 } 5327} 5328 5329/**************************************************************************** 5330 * int hdac_detach(device_t) 5331 * 5332 * Detach and free up resources utilized by the hdac device. 5333 ****************************************************************************/ 5334static int 5335hdac_detach(device_t dev) 5336{ 5337 struct hdac_softc *sc = NULL; 5338 struct hdac_devinfo *devinfo = NULL; 5339 int err; 5340 5341 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5342 if (devinfo != NULL && devinfo->codec != NULL) 5343 sc = devinfo->codec->sc; 5344 if (sc == NULL) 5345 return (0); 5346 5347 if (sc->registered > 0) { 5348 err = pcm_unregister(dev); 5349 if (err != 0) 5350 return (err); 5351 } 5352 5353 hdac_release_resources(sc); 5354 5355 return (0); 5356} 5357 5358static device_method_t hdac_methods[] = { 5359 /* device interface */ 5360 DEVMETHOD(device_probe, hdac_probe), 5361 DEVMETHOD(device_attach, hdac_attach), 5362 DEVMETHOD(device_detach, hdac_detach), 5363 { 0, 0 } 5364}; 5365 5366static driver_t hdac_driver = { 5367 "pcm", 5368 hdac_methods, 5369 PCM_SOFTC_SIZE, 5370}; 5371 5372DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5373MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5374MODULE_VERSION(snd_hda, 1); 5375