hdac.c revision 165770
1151497Sru/*- 279543Sru * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 375584Sru * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 475584Sru * All rights reserved. 575584Sru * 675584Sru * Redistribution and use in source and binary forms, with or without 775584Sru * modification, are permitted provided that the following conditions 875584Sru * are met: 975584Sru * 1. Redistributions of source code must retain the above copyright 1075584Sru * notice, this list of conditions and the following disclaimer. 1175584Sru * 2. Redistributions in binary form must reproduce the above copyright 1275584Sru * notice, this list of conditions and the following disclaimer in the 1375584Sru * documentation and/or other materials provided with the distribution. 1475584Sru * 1575584Sru * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1675584Sru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1775584Sru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1875584Sru * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151497Sru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2075584Sru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21104862Sru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22104862Sru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23104862Sru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2475584Sru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2575584Sru * SUCH DAMAGE. 2675584Sru */ 2775584Sru 2875584Sru/* 2975584Sru * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 3075584Sru * that this driver still in its early stage, and possible of rewrite are 3175584Sru * pretty much guaranteed. There are supposedly several distinct parent/child 3275584Sru * busses to make this "perfect", but as for now and for the sake of 3379543Sru * simplicity, everything is gobble up within single source. 3479543Sru * 3579543Sru * List of subsys: 3675584Sru * 1) HDA Controller support 3779543Sru * 2) HDA Codecs support, which may include 3875584Sru * - HDA 3975584Sru * - Modem 4075584Sru * - HDMI 4175584Sru * 3) Widget parser - the real magic of why this driver works on so 4275584Sru * many hardwares with minimal vendor specific quirk. The original 4375584Sru * parser was written using Ruby and can be found at 4475584Sru * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 4575584Sru * ruby parser take the verbose dmesg dump as its input. Refer to 4675584Sru * http://www.microsoft.com/whdc/device/audio/default.mspx for various 4775584Sru * interesting documents, especially UAA (Universal Audio Architecture). 4875584Sru * 4) Possible vendor specific support. 4975584Sru * (snd_hda_intel, snd_hda_ati, etc..) 5075584Sru * 5175584Sru * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 5275584Sru * Compaq V3000 with Conexant HDA. 5375584Sru * 5475584Sru * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 5575584Sru * * * 5675584Sru * * This driver is a collaborative effort made by: * 5775584Sru * * * 5875584Sru * * Stephane E. Potvin <sepotvin@videotron.ca> * 5975584Sru * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 6075584Sru * * Wesley Morgan <morganw@chemikals.org> * 6175584Sru * * Daniel Eischen <deischen@FreeBSD.org> * 6275584Sru * * Maxime Guillaud <bsd-ports@mguillaud.net> * 6375584Sru * * Ariff Abdullah <ariff@FreeBSD.org> * 6475584Sru * * * 6575584Sru * * ....and various people from freebsd-multimedia@FreeBSD.org * 6675584Sru * * * 6775584Sru * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 6875584Sru */ 6975584Sru 7075584Sru#include <sys/ctype.h> 7175584Sru 7275584Sru#include <dev/sound/pcm/sound.h> 7375584Sru#include <dev/pci/pcireg.h> 7475584Sru#include <dev/pci/pcivar.h> 7575584Sru 7675584Sru#include <dev/sound/pci/hda/hdac_private.h> 7775584Sru#include <dev/sound/pci/hda/hdac_reg.h> 7875584Sru#include <dev/sound/pci/hda/hda_reg.h> 7975584Sru#include <dev/sound/pci/hda/hdac.h> 80151497Sru 81151497Sru#include "mixer_if.h" 82151497Sru 83151497Sru#define HDA_DRV_TEST_REV "20070105_0038" 8475584Sru#define HDA_WIDGET_PARSER_REV 1 85151497Sru 86151497SruSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 165770 2007-01-04 18:13:04Z ariff $"); 87151497Sru 88151497Sru#undef HDA_DEBUG_ENABLED 89151497Sru#define HDA_DEBUG_ENABLED 1 90151497Sru 91151497Sru#ifdef HDA_DEBUG_ENABLED 92114402Sru#define HDA_DEBUG(stmt) do { \ 9375584Sru stmt \ 94151497Sru} while(0) 95151497Sru#else 9675584Sru#define HDA_DEBUG(stmt) 9775584Sru#endif 9879543Sru 99104862Sru#define HDA_BOOTVERBOSE(stmt) do { \ 100104862Sru if (bootverbose) { \ 10175584Sru stmt \ 10275584Sru } \ 10375584Sru} while(0) 10475584Sru 105151497Sru#if 1 10675584Sru#undef HDAC_INTR_EXTRA 10775584Sru#define HDAC_INTR_EXTRA 1 10875584Sru#endif 109151497Sru 110151497Sru#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111151497Sru#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 11275584Sru#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113151497Sru#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114151497Sru 115151497Sru#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 11675584Sru#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117151497Sru (fl) == 0xffffffff || \ 118151497Sru (((fl) & 0xffff0000) == 0xffff0000 && \ 119151497Sru ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120151497Sru (((fl) & 0x0000ffff) == 0x0000ffff && \ 121151497Sru ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122151497Sru#define HDA_MATCH_ALL 0xffffffff 123151497Sru#define HDAC_INVALID 0xffffffff 124151497Sru 125151497Sru#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126151497Sru (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127151497Sru 128151497Sru/* Controller models */ 129151497Sru 130151497Sru/* Intel */ 131151497Sru#define INTEL_VENDORID 0x8086 132151497Sru#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133151497Sru#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134151497Sru#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135151497Sru#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136151497Sru#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 13775584Sru 13875584Sru/* Nvidia */ 139151497Sru#define NVIDIA_VENDORID 0x10de 140151497Sru#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 14175584Sru#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142151497Sru#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 14375584Sru#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144151497Sru#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145151497Sru#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146151497Sru#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147151497Sru 148151497Sru/* ATI */ 14975584Sru#define ATI_VENDORID 0x1002 150151497Sru#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151151497Sru#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152151497Sru#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153151497Sru 154151497Sru/* VIA */ 155151497Sru#define VIA_VENDORID 0x1106 156151497Sru#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157151497Sru#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158151497Sru 159151497Sru/* SiS */ 160151497Sru#define SIS_VENDORID 0x1039 161151497Sru#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 16275584Sru#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 16375584Sru 164151497Sru/* OEM/subvendors */ 16575584Sru 166151497Sru/* Intel */ 167151497Sru#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168151497Sru 169151497Sru/* HP/Compaq */ 170151497Sru#define HP_VENDORID 0x103c 171151497Sru#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172151497Sru#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173151497Sru#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 17475584Sru#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175151497Sru#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 176151497Sru/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 177151497Sru#define HP_NX6325_SUBVENDORX 0x103c30b0 178151497Sru 17975584Sru/* Dell */ 18075584Sru#define DELL_VENDORID 0x1028 181151497Sru#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 18275584Sru#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 183151497Sru#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 184151497Sru 18575584Sru/* Clevo */ 186151497Sru#define CLEVO_VENDORID 0x1558 18775584Sru#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 18875584Sru#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 189151497Sru 190151497Sru/* Acer */ 19175584Sru#define ACER_VENDORID 0x1025 192151497Sru#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 193151497Sru 194151497Sru/* Asus */ 195151497Sru#define ASUS_VENDORID 0x1043 196151497Sru#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 197151497Sru#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 19875584Sru#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 19975584Sru#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 200114402Sru#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 20175584Sru#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 202151497Sru 203151497Sru/* IBM / Lenovo */ 204151497Sru#define IBM_VENDORID 0x1014 205151497Sru#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 206151497Sru#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 207151497Sru 208151497Sru/* Lenovo */ 209151497Sru#define LENOVO_VENDORID 0x17aa 210151497Sru#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 211114402Sru#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 212151497Sru 21375584Sru/* Samsung */ 214114402Sru#define SAMSUNG_VENDORID 0x144d 215151497Sru#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 216151497Sru#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 217151497Sru 218114402Sru/* Medion ? */ 219114402Sru#define MEDION_VENDORID 0x161f 220114402Sru#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 221114402Sru#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 222114402Sru 223114402Sru/* 224114402Sru * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 225114402Sru * instead of their own, which is beyond my comprehension 226114402Sru * (see HDA_CODEC_STAC9221 below). 227114402Sru */ 228114402Sru#define APPLE_INTEL_MAC 0x76808384 229114402Sru 230114402Sru/* LG Electronics */ 231151497Sru#define LG_VENDORID 0x1854 232151497Sru#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 233151497Sru#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 234151497Sru 235114402Sru/* Fujitsu Siemens */ 236114402Sru#define FS_VENDORID 0x1734 237114402Sru#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 238151497Sru#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 239151497Sru 240151497Sru/* Toshiba */ 241114402Sru#define TOSHIBA_VENDORID 0x1179 242151497Sru#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 243114402Sru#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 244151497Sru 245114402Sru/* Misc constants.. */ 246151497Sru#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 247114402Sru#define HDA_AMP_MUTE_NONE (0) 248114402Sru#define HDA_AMP_MUTE_LEFT (1 << 0) 249114402Sru#define HDA_AMP_MUTE_RIGHT (1 << 1) 250114402Sru#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 251114402Sru 252114402Sru#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 253114402Sru#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 254151497Sru 255151497Sru#define HDA_DAC_PATH (1 << 0) 256151497Sru#define HDA_ADC_PATH (1 << 1) 257151497Sru#define HDA_ADC_RECSEL (1 << 2) 258151497Sru 259114402Sru#define HDA_CTL_OUT (1 << 0) 260114402Sru#define HDA_CTL_IN (1 << 1) 261114402Sru#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 262114402Sru 263114402Sru#define HDA_GPIO_MAX 15 264151497Sru/* 0 - 14 = GPIO */ 265114402Sru#define HDA_QUIRK_GPIO0 (1 << 0) 266151497Sru#define HDA_QUIRK_GPIO1 (1 << 1) 267114402Sru#define HDA_QUIRK_GPIO2 (1 << 2) 268151497Sru#define HDA_QUIRK_GPIOFLUSH (1 << 15) 269151497Sru#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 270151497Sru#define HDA_QUIRK_FIXEDRATE (1 << 17) 271151497Sru#define HDA_QUIRK_FORCESTEREO (1 << 18) 272114402Sru#define HDA_QUIRK_EAPDINV (1 << 19) 273151497Sru#define HDA_QUIRK_VREF (1 << 20) 274114402Sru 275151497Srustatic const struct { 276114402Sru char *key; 277114402Sru uint32_t value; 278114402Sru} hdac_quirks_tab[] = { 279114402Sru { "gpio0", HDA_QUIRK_GPIO0 }, 280114402Sru { "gpio1", HDA_QUIRK_GPIO1 }, 281114402Sru { "gpio2", HDA_QUIRK_GPIO2 }, 282114402Sru { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 283114402Sru { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 284114402Sru { "fixedrate", HDA_QUIRK_FIXEDRATE }, 285114402Sru { "forcestereo", HDA_QUIRK_FORCESTEREO }, 286151497Sru { "eapdinv", HDA_QUIRK_EAPDINV }, 287114402Sru { "vref", HDA_QUIRK_VREF }, 288151497Sru}; 289114402Sru#define HDAC_QUIRKS_TAB_LEN \ 290114402Sru (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 291151497Sru 292114402Sru#define HDA_BDL_MIN 2 293114402Sru#define HDA_BDL_MAX 256 294114402Sru#define HDA_BDL_DEFAULT HDA_BDL_MIN 295151497Sru 296151497Sru#define HDA_BUFSZ_MIN 4096 297114402Sru#define HDA_BUFSZ_MAX 65536 298114402Sru#define HDA_BUFSZ_DEFAULT 16384 299151497Sru 300151497Sru#define HDA_PARSE_MAXDEPTH 10 301151497Sru 302151497Sru#define HDAC_UNSOLTAG_EVENT_HP 0x00 303151497Sru 304114402SruMALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 305114402Sru 306151497Sruenum { 307114402Sru HDA_PARSE_MIXER, 308114402Sru HDA_PARSE_DIRECT 309114402Sru}; 310114402Sru 311114402Sru/* Default */ 312114402Srustatic uint32_t hdac_fmt[] = { 313114402Sru AFMT_STEREO | AFMT_S16_LE, 314151497Sru 0 315151497Sru}; 316151497Sru 317151497Srustatic struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 318151497Sru 319151497Srustatic const struct { 320151497Sru uint32_t model; 321151497Sru char *desc; 322151497Sru} hdac_devices[] = { 323151497Sru { HDA_INTEL_82801F, "Intel 82801F" }, 324151497Sru { HDA_INTEL_82801G, "Intel 82801G" }, 325151497Sru { HDA_INTEL_82801H, "Intel 82801H" }, 326151497Sru { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 327151497Sru { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 328114402Sru { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 329114402Sru { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 330151497Sru { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 331114402Sru { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 332114402Sru { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 333151497Sru { HDA_ATI_SB450, "ATI SB450" }, 334151497Sru { HDA_ATI_SB600, "ATI SB600" }, 335151497Sru { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 336114402Sru { HDA_SIS_966, "SiS 966" }, 337151497Sru /* Unknown */ 338151497Sru { HDA_INTEL_ALL, "Intel (Unknown)" }, 339114402Sru { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 340114402Sru { HDA_ATI_ALL, "ATI (Unknown)" }, 341114402Sru { HDA_VIA_ALL, "VIA (Unknown)" }, 342114402Sru { HDA_SIS_ALL, "SiS (Unknown)" }, 343151497Sru}; 344114402Sru#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 345114402Sru 346151497Srustatic const struct { 347114402Sru uint32_t rate; 348114402Sru int valid; 349114402Sru uint16_t base; 350151497Sru uint16_t mul; 351151497Sru uint16_t div; 352151497Sru} hda_rate_tab[] = { 353151497Sru { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 354151497Sru { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 355114402Sru { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 356151497Sru { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 357151497Sru { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 358151497Sru { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 359151497Sru { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 360151497Sru { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 36175584Sru { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 36275584Sru { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 36375584Sru { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 36475584Sru { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 36575584Sru { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 36675584Sru { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 36775584Sru { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 368151497Sru { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 369151497Sru { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 370151497Sru { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 371151497Sru { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 372151497Sru { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 373151497Sru { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 374151497Sru { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 375151497Sru { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 376151497Sru { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 37775584Sru { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 378151497Sru { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 379151497Sru { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 380151497Sru { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 381151497Sru { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 382151497Sru { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 383151497Sru { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 384114402Sru { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 385114402Sru { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 386114402Sru { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 38775584Sru { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 388151497Sru}; 389114402Sru#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 390114402Sru 391114402Sru/* All codecs you can eat... */ 392114402Sru#define HDA_CODEC_CONSTRUCT(vendor, id) \ 393114402Sru (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 394114402Sru 395114402Sru/* Realtek */ 396114402Sru#define REALTEK_VENDORID 0x10ec 397114402Sru#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 398114402Sru#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 399114402Sru#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 400114402Sru#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 401114402Sru#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 402114402Sru#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 403114402Sru#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 404114402Sru 405114402Sru/* Analog Device */ 406114402Sru#define ANALOGDEVICE_VENDORID 0x11d4 407114402Sru#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 408114402Sru#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 409114402Sru#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 41075584Sru#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 411114402Sru 412114402Sru/* CMedia */ 413114402Sru#define CMEDIA_VENDORID 0x434d 414114402Sru#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 415114402Sru#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 416114402Sru 417114402Sru/* Sigmatel */ 418114402Sru#define SIGMATEL_VENDORID 0x8384 41975584Sru#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 420114402Sru#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 421114402Sru#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 422114402Sru#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 423114402Sru#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 424114402Sru#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 425114402Sru 426114402Sru/* 427114402Sru * Conexant 428114402Sru * 429114402Sru * Ok, the truth is, I don't have any idea at all whether 430114402Sru * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 431114402Sru * place that tell me it is "Venice" is from its Windows driver INF. 432114402Sru * 433114402Sru * Venice - CX????? 434114402Sru * Waikiki - CX20551-22 435114402Sru */ 43675584Sru#define CONEXANT_VENDORID 0x14f1 43775584Sru#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 43875584Sru#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 43975584Sru#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 44075584Sru 44175584Sru 44275584Sru/* Codecs */ 443151497Srustatic const struct { 44475584Sru uint32_t id; 445114402Sru char *name; 446114402Sru} hdac_codecs[] = { 447151497Sru { HDA_CODEC_ALC260, "Realtek ALC260" }, 44875584Sru { HDA_CODEC_ALC861, "Realtek ALC861" }, 44975584Sru { HDA_CODEC_ALC880, "Realtek ALC880" }, 45075584Sru { HDA_CODEC_ALC882, "Realtek ALC882" }, 45175584Sru { HDA_CODEC_ALC883, "Realtek ALC883" }, 45275584Sru { HDA_CODEC_ALC888, "Realtek ALC888" }, 45375584Sru { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 45475584Sru { HDA_CODEC_AD1983, "Analog Device AD1983" }, 45575584Sru { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 456114402Sru { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 457114402Sru { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 458114402Sru { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 459114402Sru { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 460114402Sru { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 461114402Sru { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 462114402Sru { HDA_CODEC_CXVENICE, "Conexant Venice" }, 463114402Sru { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 464114402Sru /* Unknown codec */ 465114402Sru { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 466114402Sru { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 467114402Sru { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 46875584Sru { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 469114402Sru { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 470114402Sru}; 471114402Sru#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 472114402Sru 47375584Sruenum { 47475584Sru HDAC_HP_SWITCH_CTL, 47575584Sru HDAC_HP_SWITCH_CTRL 47675584Sru}; 477114402Sru 478114402Srustatic const struct { 479114402Sru uint32_t model; 480114402Sru uint32_t id; 48175584Sru int type; 48275584Sru int inverted; 483114402Sru nid_t hpnid; 484114402Sru nid_t spkrnid[8]; 48575584Sru nid_t eapdnid; 486114402Sru} hdac_hp_switch[] = { 487114402Sru /* Specific OEM models */ 488114402Sru { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 489114402Sru 17, { 16, -1 }, 16 }, 490114402Sru { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 49175584Sru 6, { 5, -1 }, 5 }, 492114402Sru { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 493114402Sru 6, { 5, -1 }, 5 }, 494114402Sru { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 495114402Sru 6, { 5, -1 }, 5 }, 496114402Sru { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 497114402Sru 6, { 5, -1 }, -1 }, 498114402Sru { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 499114402Sru 13, { 14, -1 }, -1 }, 500114402Sru { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 501114402Sru 13, { 14, -1 }, -1 }, 502114402Sru { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 503114402Sru 10, { 13, -1 }, -1 }, 50475584Sru { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 50575584Sru 26, { 27, -1 }, -1 }, 50675584Sru { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 507114402Sru 27, { 20, -1 }, -1 }, 50875584Sru /* 50975584Sru * All models that at least come from the same vendor with 51075584Sru * simmilar codec. 51175584Sru */ 51275584Sru { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 51375584Sru 17, { 16, -1 }, 16 }, 51475584Sru { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 51575584Sru 6, { 5, -1 }, 5 }, 51675584Sru { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 51775584Sru 6, { 5, -1 }, -1 }, 51875584Sru { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 51975584Sru 13, { 14, -1 }, -1 }, 52075584Sru { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 52175584Sru 26, { 27, -1 }, -1 }, 52275584Sru}; 52375584Sru#define HDAC_HP_SWITCH_LEN \ 52475584Sru (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 52575584Sru 52675584Srustatic const struct { 52775584Sru uint32_t model; 528114402Sru uint32_t id; 52975584Sru nid_t eapdnid; 53075584Sru int hp_switch; 53175584Sru} hdac_eapd_switch[] = { 53275584Sru { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 53375584Sru { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 53475584Sru { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 53575584Sru}; 53675584Sru#define HDAC_EAPD_SWITCH_LEN \ 53775584Sru (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 53875584Sru 53975584Sru/**************************************************************************** 54075584Sru * Function prototypes 54175584Sru ****************************************************************************/ 54275584Srustatic void hdac_intr_handler(void *); 54375584Srustatic int hdac_reset(struct hdac_softc *); 54475584Srustatic int hdac_get_capabilities(struct hdac_softc *); 54575584Srustatic void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 546114402Srustatic int hdac_dma_alloc(struct hdac_softc *, 54775584Sru struct hdac_dma *, bus_size_t); 54875584Srustatic void hdac_dma_free(struct hdac_dma *); 54975584Srustatic int hdac_mem_alloc(struct hdac_softc *); 55075584Srustatic void hdac_mem_free(struct hdac_softc *); 55175584Srustatic int hdac_irq_alloc(struct hdac_softc *); 55275584Srustatic void hdac_irq_free(struct hdac_softc *); 553114402Srustatic void hdac_corb_init(struct hdac_softc *); 55475584Srustatic void hdac_rirb_init(struct hdac_softc *); 55575584Srustatic void hdac_corb_start(struct hdac_softc *); 55675584Srustatic void hdac_rirb_start(struct hdac_softc *); 55775584Srustatic void hdac_scan_codecs(struct hdac_softc *); 55875584Srustatic int hdac_probe_codec(struct hdac_codec *); 55975584Srustatic struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 56075584Srustatic void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 56175584Sru 562151497Srustatic void hdac_attach2(void *); 56375584Sru 56475584Srustatic uint32_t hdac_command_sendone_internal(struct hdac_softc *, 56575584Sru uint32_t, int); 56675584Srustatic void hdac_command_send_internal(struct hdac_softc *, 567151497Sru struct hdac_command_list *, int); 56875584Sru 569114402Srustatic int hdac_probe(device_t); 570114402Srustatic int hdac_attach(device_t); 57175584Srustatic int hdac_detach(device_t); 572151497Srustatic void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 57375584Srustatic void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 57475584Sru uint32_t, int, int); 575151497Srustatic struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 57675584Sru nid_t, int, int); 57775584Srustatic void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 57875584Sru nid_t, nid_t, int, int, int, int, int, int); 57975584Srustatic int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 580static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 581 582static int hdac_rirb_flush(struct hdac_softc *sc); 583static int hdac_unsolq_flush(struct hdac_softc *sc); 584 585#define hdac_command(a1, a2, a3) \ 586 hdac_command_sendone_internal(a1, a2, a3) 587 588#define hdac_codec_id(d) \ 589 ((uint32_t)((d == NULL) ? 0x00000000 : \ 590 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 591 ((uint32_t)(d)->device_id & 0x0000ffff)))) 592 593static char * 594hdac_codec_name(struct hdac_devinfo *devinfo) 595{ 596 uint32_t id; 597 int i; 598 599 id = hdac_codec_id(devinfo); 600 601 for (i = 0; i < HDAC_CODECS_LEN; i++) { 602 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 603 return (hdac_codecs[i].name); 604 } 605 606 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 607} 608 609static char * 610hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 611{ 612 static char *ossname[] = SOUND_DEVICE_NAMES; 613 static char *unknown = "???"; 614 int i; 615 616 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 617 if (devmask & (1 << i)) 618 return (ossname[i]); 619 } 620 return (unknown); 621} 622 623static void 624hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 625{ 626 static char *ossname[] = SOUND_DEVICE_NAMES; 627 int i, first = 1; 628 629 bzero(buf, len); 630 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 631 if (mask & (1 << i)) { 632 if (first == 0) 633 strlcat(buf, ", ", len); 634 strlcat(buf, ossname[i], len); 635 first = 0; 636 } 637 } 638} 639 640static struct hdac_audio_ctl * 641hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 642{ 643 if (devinfo == NULL || 644 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 645 index == NULL || devinfo->function.audio.ctl == NULL || 646 devinfo->function.audio.ctlcnt < 1 || 647 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 648 return (NULL); 649 return (&devinfo->function.audio.ctl[(*index)++]); 650} 651 652static struct hdac_audio_ctl * 653hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 654 int index, int cnt) 655{ 656 struct hdac_audio_ctl *ctl, *retctl = NULL; 657 int i, at, atindex, found = 0; 658 659 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 660 return (NULL); 661 662 at = cnt; 663 if (at == 0) 664 at = 1; 665 else if (at < 0) 666 at = -1; 667 atindex = index; 668 if (atindex < 0) 669 atindex = -1; 670 671 i = 0; 672 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 673 if (ctl->enable == 0 || ctl->widget == NULL) 674 continue; 675 if (!(ctl->widget->nid == nid && (atindex == -1 || 676 ctl->index == atindex))) 677 continue; 678 found++; 679 if (found == cnt) 680 return (ctl); 681 retctl = ctl; 682 } 683 684 return ((at == -1) ? retctl : NULL); 685} 686 687static void 688hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 689{ 690 struct hdac_softc *sc; 691 struct hdac_widget *w; 692 struct hdac_audio_ctl *ctl; 693 uint32_t id, res; 694 int i = 0, j, forcemute; 695 nid_t cad; 696 697 if (devinfo == NULL || devinfo->codec == NULL || 698 devinfo->codec->sc == NULL) 699 return; 700 701 sc = devinfo->codec->sc; 702 cad = devinfo->codec->cad; 703 id = hdac_codec_id(devinfo); 704 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 705 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 706 sc->pci_subvendor) && 707 hdac_hp_switch[i].id == id) 708 break; 709 } 710 711 if (i >= HDAC_HP_SWITCH_LEN) 712 return; 713 714 forcemute = 0; 715 if (hdac_hp_switch[i].eapdnid != -1) { 716 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 717 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 718 forcemute = (w->param.eapdbtl & 719 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 720 } 721 722 res = hdac_command(sc, 723 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 724 HDA_BOOTVERBOSE( 725 device_printf(sc->dev, 726 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 727 hdac_hp_switch[i].hpnid, res); 728 ); 729 res >>= 31; 730 res ^= hdac_hp_switch[i].inverted; 731 732 switch (hdac_hp_switch[i].type) { 733 case HDAC_HP_SWITCH_CTL: 734 ctl = hdac_audio_ctl_amp_get(devinfo, 735 hdac_hp_switch[i].hpnid, 0, 1); 736 if (ctl != NULL) { 737 ctl->muted = (res != 0 && forcemute == 0) ? 738 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 739 hdac_audio_ctl_amp_set(ctl, 740 HDA_AMP_MUTE_DEFAULT, ctl->left, 741 ctl->right); 742 } 743 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 744 ctl = hdac_audio_ctl_amp_get(devinfo, 745 hdac_hp_switch[i].spkrnid[j], 0, 1); 746 if (ctl != NULL) { 747 ctl->muted = (res != 0 || forcemute == 1) ? 748 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 749 hdac_audio_ctl_amp_set(ctl, 750 HDA_AMP_MUTE_DEFAULT, ctl->left, 751 ctl->right); 752 } 753 } 754 break; 755 case HDAC_HP_SWITCH_CTRL: 756 if (res != 0) { 757 /* HP in */ 758 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 759 if (w != NULL && w->type == 760 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 761 if (forcemute == 0) 762 w->wclass.pin.ctrl |= 763 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 764 else 765 w->wclass.pin.ctrl &= 766 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 767 hdac_command(sc, 768 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 769 w->wclass.pin.ctrl), cad); 770 } 771 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 772 w = hdac_widget_get(devinfo, 773 hdac_hp_switch[i].spkrnid[j]); 774 if (w != NULL && w->type == 775 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 776 w->wclass.pin.ctrl &= 777 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 778 hdac_command(sc, 779 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 780 w->nid, 781 w->wclass.pin.ctrl), cad); 782 } 783 } 784 } else { 785 /* HP out */ 786 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 787 if (w != NULL && w->type == 788 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 789 w->wclass.pin.ctrl &= 790 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 791 hdac_command(sc, 792 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 793 w->wclass.pin.ctrl), cad); 794 } 795 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 796 w = hdac_widget_get(devinfo, 797 hdac_hp_switch[i].spkrnid[j]); 798 if (w != NULL && w->type == 799 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 800 if (forcemute == 0) 801 w->wclass.pin.ctrl |= 802 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 803 else 804 w->wclass.pin.ctrl &= 805 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 806 hdac_command(sc, 807 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 808 w->nid, 809 w->wclass.pin.ctrl), cad); 810 } 811 } 812 } 813 break; 814 default: 815 break; 816 } 817} 818 819static void 820hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 821{ 822 struct hdac_softc *sc; 823 struct hdac_devinfo *devinfo = NULL; 824 device_t *devlist = NULL; 825 int devcount, i; 826 827 if (codec == NULL || codec->sc == NULL) 828 return; 829 830 sc = codec->sc; 831 832 HDA_BOOTVERBOSE( 833 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 834 ); 835 836 device_get_children(sc->dev, &devlist, &devcount); 837 for (i = 0; devlist != NULL && i < devcount; i++) { 838 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 839 if (devinfo != NULL && devinfo->node_type == 840 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 841 devinfo->codec != NULL && 842 devinfo->codec->cad == codec->cad) { 843 break; 844 } else 845 devinfo = NULL; 846 } 847 if (devlist != NULL) 848 free(devlist, M_TEMP); 849 850 if (devinfo == NULL) 851 return; 852 853 switch (tag) { 854 case HDAC_UNSOLTAG_EVENT_HP: 855 hdac_hp_switch_handler(devinfo); 856 break; 857 default: 858 break; 859 } 860} 861 862static int 863hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 864{ 865 /* XXX to be removed */ 866#ifdef HDAC_INTR_EXTRA 867 uint32_t res; 868#endif 869 870 if (ch->blkcnt == 0) 871 return (0); 872 873 /* XXX to be removed */ 874#ifdef HDAC_INTR_EXTRA 875 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 876#endif 877 878 /* XXX to be removed */ 879#ifdef HDAC_INTR_EXTRA 880 HDA_BOOTVERBOSE( 881 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 882 device_printf(sc->dev, 883 "PCMDIR_%s intr triggered beyond stream boundary:" 884 "%08x\n", 885 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 886 ); 887#endif 888 889 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 890 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 891 892 /* XXX to be removed */ 893#ifdef HDAC_INTR_EXTRA 894 if (res & HDAC_SDSTS_BCIS) { 895#endif 896 return (1); 897 /* XXX to be removed */ 898#ifdef HDAC_INTR_EXTRA 899 } 900#endif 901 902 return (0); 903} 904 905/**************************************************************************** 906 * void hdac_intr_handler(void *) 907 * 908 * Interrupt handler. Processes interrupts received from the hdac. 909 ****************************************************************************/ 910static void 911hdac_intr_handler(void *context) 912{ 913 struct hdac_softc *sc; 914 uint32_t intsts; 915 uint8_t rirbsts; 916 struct hdac_rirb *rirb_base; 917 uint32_t trigger = 0; 918 919 sc = (struct hdac_softc *)context; 920 921 hdac_lock(sc); 922 if (sc->polling != 0) { 923 hdac_unlock(sc); 924 return; 925 } 926 /* Do we have anything to do? */ 927 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 928 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 929 hdac_unlock(sc); 930 return; 931 } 932 933 /* Was this a controller interrupt? */ 934 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 935 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 936 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 937 /* Get as many responses that we can */ 938 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 939 HDAC_WRITE_1(&sc->mem, 940 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 941 hdac_rirb_flush(sc); 942 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 943 } 944 /* XXX to be removed */ 945 /* Clear interrupt and exit */ 946#ifdef HDAC_INTR_EXTRA 947 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 948#endif 949 } 950 951 hdac_unsolq_flush(sc); 952 953 if (intsts & HDAC_INTSTS_SIS_MASK) { 954 if ((intsts & (1 << sc->num_iss)) && 955 hdac_stream_intr(sc, &sc->play) != 0) 956 trigger |= 1; 957 if ((intsts & (1 << 0)) && 958 hdac_stream_intr(sc, &sc->rec) != 0) 959 trigger |= 2; 960 /* XXX to be removed */ 961#ifdef HDAC_INTR_EXTRA 962 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 963 HDAC_INTSTS_SIS_MASK); 964#endif 965 } 966 967 hdac_unlock(sc); 968 969 if (trigger & 1) 970 chn_intr(sc->play.c); 971 if (trigger & 2) 972 chn_intr(sc->rec.c); 973} 974 975/**************************************************************************** 976 * int hdac_reset(hdac_softc *) 977 * 978 * Reset the hdac to a quiescent and known state. 979 ****************************************************************************/ 980static int 981hdac_reset(struct hdac_softc *sc) 982{ 983 uint32_t gctl; 984 int count, i; 985 986 /* 987 * Stop all Streams DMA engine 988 */ 989 for (i = 0; i < sc->num_iss; i++) 990 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 991 for (i = 0; i < sc->num_oss; i++) 992 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 993 for (i = 0; i < sc->num_bss; i++) 994 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 995 996 /* 997 * Stop Control DMA engines 998 */ 999 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1000 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1001 1002 /* 1003 * Reset the controller. The reset must remain asserted for 1004 * a minimum of 100us. 1005 */ 1006 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1007 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1008 count = 10000; 1009 do { 1010 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1011 if (!(gctl & HDAC_GCTL_CRST)) 1012 break; 1013 DELAY(10); 1014 } while (--count); 1015 if (gctl & HDAC_GCTL_CRST) { 1016 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1017 return (ENXIO); 1018 } 1019 DELAY(100); 1020 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1021 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1022 count = 10000; 1023 do { 1024 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1025 if (gctl & HDAC_GCTL_CRST) 1026 break; 1027 DELAY(10); 1028 } while (--count); 1029 if (!(gctl & HDAC_GCTL_CRST)) { 1030 device_printf(sc->dev, "Device stuck in reset\n"); 1031 return (ENXIO); 1032 } 1033 1034 /* 1035 * Wait for codecs to finish their own reset sequence. The delay here 1036 * should be of 250us but for some reasons, on it's not enough on my 1037 * computer. Let's use twice as much as necessary to make sure that 1038 * it's reset properly. 1039 */ 1040 DELAY(1000); 1041 1042 return (0); 1043} 1044 1045 1046/**************************************************************************** 1047 * int hdac_get_capabilities(struct hdac_softc *); 1048 * 1049 * Retreive the general capabilities of the hdac; 1050 * Number of Input Streams 1051 * Number of Output Streams 1052 * Number of bidirectional Streams 1053 * 64bit ready 1054 * CORB and RIRB sizes 1055 ****************************************************************************/ 1056static int 1057hdac_get_capabilities(struct hdac_softc *sc) 1058{ 1059 uint16_t gcap; 1060 uint8_t corbsize, rirbsize; 1061 1062 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1063 sc->num_iss = HDAC_GCAP_ISS(gcap); 1064 sc->num_oss = HDAC_GCAP_OSS(gcap); 1065 sc->num_bss = HDAC_GCAP_BSS(gcap); 1066 1067 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1068 1069 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1070 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1071 HDAC_CORBSIZE_CORBSZCAP_256) 1072 sc->corb_size = 256; 1073 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1074 HDAC_CORBSIZE_CORBSZCAP_16) 1075 sc->corb_size = 16; 1076 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1077 HDAC_CORBSIZE_CORBSZCAP_2) 1078 sc->corb_size = 2; 1079 else { 1080 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1081 __func__, corbsize); 1082 return (ENXIO); 1083 } 1084 1085 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1086 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1087 HDAC_RIRBSIZE_RIRBSZCAP_256) 1088 sc->rirb_size = 256; 1089 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1090 HDAC_RIRBSIZE_RIRBSZCAP_16) 1091 sc->rirb_size = 16; 1092 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1093 HDAC_RIRBSIZE_RIRBSZCAP_2) 1094 sc->rirb_size = 2; 1095 else { 1096 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1097 __func__, rirbsize); 1098 return (ENXIO); 1099 } 1100 1101 return (0); 1102} 1103 1104 1105/**************************************************************************** 1106 * void hdac_dma_cb 1107 * 1108 * This function is called by bus_dmamap_load when the mapping has been 1109 * established. We just record the physical address of the mapping into 1110 * the struct hdac_dma passed in. 1111 ****************************************************************************/ 1112static void 1113hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1114{ 1115 struct hdac_dma *dma; 1116 1117 if (error == 0) { 1118 dma = (struct hdac_dma *)callback_arg; 1119 dma->dma_paddr = segs[0].ds_addr; 1120 } 1121} 1122 1123static void 1124hdac_dma_nocache(void *ptr) 1125{ 1126#if defined(__i386__) || defined(__amd64__) 1127 pt_entry_t *pte; 1128 vm_offset_t va; 1129 1130 va = (vm_offset_t)ptr; 1131 pte = vtopte(va); 1132 if (pte) { 1133 *pte |= PG_N; 1134 invltlb(); 1135 } 1136#endif 1137} 1138 1139/**************************************************************************** 1140 * int hdac_dma_alloc 1141 * 1142 * This function allocate and setup a dma region (struct hdac_dma). 1143 * It must be freed by a corresponding hdac_dma_free. 1144 ****************************************************************************/ 1145static int 1146hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1147{ 1148 int result; 1149 int lowaddr; 1150 1151 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1152 BUS_SPACE_MAXADDR_32BIT; 1153 bzero(dma, sizeof(*dma)); 1154 1155 /* 1156 * Create a DMA tag 1157 */ 1158 result = bus_dma_tag_create(NULL, /* parent */ 1159 HDAC_DMA_ALIGNMENT, /* alignment */ 1160 0, /* boundary */ 1161 lowaddr, /* lowaddr */ 1162 BUS_SPACE_MAXADDR, /* highaddr */ 1163 NULL, /* filtfunc */ 1164 NULL, /* fistfuncarg */ 1165 size, /* maxsize */ 1166 1, /* nsegments */ 1167 size, /* maxsegsz */ 1168 0, /* flags */ 1169 NULL, /* lockfunc */ 1170 NULL, /* lockfuncarg */ 1171 &dma->dma_tag); /* dmat */ 1172 if (result != 0) { 1173 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1174 __func__, result); 1175 goto fail; 1176 } 1177 1178 /* 1179 * Allocate DMA memory 1180 */ 1181 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1182 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1183 if (result != 0) { 1184 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1185 __func__, result); 1186 goto fail; 1187 } 1188 1189 /* 1190 * Map the memory 1191 */ 1192 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1193 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1194 BUS_DMA_NOWAIT); 1195 if (result != 0 || dma->dma_paddr == 0) { 1196 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1197 __func__, result); 1198 goto fail; 1199 } 1200 bzero((void *)dma->dma_vaddr, size); 1201 hdac_dma_nocache(dma->dma_vaddr); 1202 1203 return (0); 1204fail: 1205 if (dma->dma_map != NULL) 1206 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1207 if (dma->dma_tag != NULL) 1208 bus_dma_tag_destroy(dma->dma_tag); 1209 return (result); 1210} 1211 1212 1213/**************************************************************************** 1214 * void hdac_dma_free(struct hdac_dma *) 1215 * 1216 * Free a struct dhac_dma that has been previously allocated via the 1217 * hdac_dma_alloc function. 1218 ****************************************************************************/ 1219static void 1220hdac_dma_free(struct hdac_dma *dma) 1221{ 1222 if (dma->dma_tag != NULL) { 1223 /* Flush caches */ 1224 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1225 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1226 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1227 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1228 bus_dma_tag_destroy(dma->dma_tag); 1229 } 1230} 1231 1232/**************************************************************************** 1233 * int hdac_mem_alloc(struct hdac_softc *) 1234 * 1235 * Allocate all the bus resources necessary to speak with the physical 1236 * controller. 1237 ****************************************************************************/ 1238static int 1239hdac_mem_alloc(struct hdac_softc *sc) 1240{ 1241 struct hdac_mem *mem; 1242 1243 mem = &sc->mem; 1244 mem->mem_rid = PCIR_BAR(0); 1245 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1246 &mem->mem_rid, RF_ACTIVE); 1247 if (mem->mem_res == NULL) { 1248 device_printf(sc->dev, 1249 "%s: Unable to allocate memory resource\n", __func__); 1250 return (ENOMEM); 1251 } 1252 mem->mem_tag = rman_get_bustag(mem->mem_res); 1253 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1254 1255 return (0); 1256} 1257 1258/**************************************************************************** 1259 * void hdac_mem_free(struct hdac_softc *) 1260 * 1261 * Free up resources previously allocated by hdac_mem_alloc. 1262 ****************************************************************************/ 1263static void 1264hdac_mem_free(struct hdac_softc *sc) 1265{ 1266 struct hdac_mem *mem; 1267 1268 mem = &sc->mem; 1269 if (mem->mem_res != NULL) 1270 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1271 mem->mem_res); 1272 mem->mem_res = NULL; 1273} 1274 1275/**************************************************************************** 1276 * int hdac_irq_alloc(struct hdac_softc *) 1277 * 1278 * Allocate and setup the resources necessary for interrupt handling. 1279 ****************************************************************************/ 1280static int 1281hdac_irq_alloc(struct hdac_softc *sc) 1282{ 1283 struct hdac_irq *irq; 1284 int result; 1285 1286 irq = &sc->irq; 1287 irq->irq_rid = 0x0; 1288 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1289 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1290 if (irq->irq_res == NULL) { 1291 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1292 __func__); 1293 goto fail; 1294 } 1295 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1296 hdac_intr_handler, sc, &irq->irq_handle); 1297 if (result != 0) { 1298 device_printf(sc->dev, 1299 "%s: Unable to setup interrupt handler (%x)\n", 1300 __func__, result); 1301 goto fail; 1302 } 1303 1304 return (0); 1305 1306fail: 1307 hdac_irq_free(sc); 1308 1309 return (ENXIO); 1310} 1311 1312/**************************************************************************** 1313 * void hdac_irq_free(struct hdac_softc *) 1314 * 1315 * Free up resources previously allocated by hdac_irq_alloc. 1316 ****************************************************************************/ 1317static void 1318hdac_irq_free(struct hdac_softc *sc) 1319{ 1320 struct hdac_irq *irq; 1321 1322 irq = &sc->irq; 1323 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1324 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1325 if (irq->irq_res != NULL) 1326 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1327 irq->irq_res); 1328 irq->irq_handle = NULL; 1329 irq->irq_res = NULL; 1330} 1331 1332/**************************************************************************** 1333 * void hdac_corb_init(struct hdac_softc *) 1334 * 1335 * Initialize the corb registers for operations but do not start it up yet. 1336 * The CORB engine must not be running when this function is called. 1337 ****************************************************************************/ 1338static void 1339hdac_corb_init(struct hdac_softc *sc) 1340{ 1341 uint8_t corbsize; 1342 uint64_t corbpaddr; 1343 1344 /* Setup the CORB size. */ 1345 switch (sc->corb_size) { 1346 case 256: 1347 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1348 break; 1349 case 16: 1350 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1351 break; 1352 case 2: 1353 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1354 break; 1355 default: 1356 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1357 } 1358 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1359 1360 /* Setup the CORB Address in the hdac */ 1361 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1362 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1363 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1364 1365 /* Set the WP and RP */ 1366 sc->corb_wp = 0; 1367 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1368 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1369 /* 1370 * The HDA specification indicates that the CORBRPRST bit will always 1371 * read as zero. Unfortunately, it seems that at least the 82801G 1372 * doesn't reset the bit to zero, which stalls the corb engine. 1373 * manually reset the bit to zero before continuing. 1374 */ 1375 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1376 1377 /* Enable CORB error reporting */ 1378#if 0 1379 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1380#endif 1381} 1382 1383/**************************************************************************** 1384 * void hdac_rirb_init(struct hdac_softc *) 1385 * 1386 * Initialize the rirb registers for operations but do not start it up yet. 1387 * The RIRB engine must not be running when this function is called. 1388 ****************************************************************************/ 1389static void 1390hdac_rirb_init(struct hdac_softc *sc) 1391{ 1392 uint8_t rirbsize; 1393 uint64_t rirbpaddr; 1394 1395 /* Setup the RIRB size. */ 1396 switch (sc->rirb_size) { 1397 case 256: 1398 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1399 break; 1400 case 16: 1401 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1402 break; 1403 case 2: 1404 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1405 break; 1406 default: 1407 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1408 } 1409 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1410 1411 /* Setup the RIRB Address in the hdac */ 1412 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1413 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1414 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1415 1416 /* Setup the WP and RP */ 1417 sc->rirb_rp = 0; 1418 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1419 1420 if (sc->polling == 0) { 1421 /* Setup the interrupt threshold */ 1422 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1423 1424 /* Enable Overrun and response received reporting */ 1425#if 0 1426 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1427 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1428#else 1429 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1430#endif 1431 } 1432 1433 /* 1434 * Make sure that the Host CPU cache doesn't contain any dirty 1435 * cache lines that falls in the rirb. If I understood correctly, it 1436 * should be sufficient to do this only once as the rirb is purely 1437 * read-only from now on. 1438 */ 1439 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1440 BUS_DMASYNC_PREREAD); 1441} 1442 1443/**************************************************************************** 1444 * void hdac_corb_start(hdac_softc *) 1445 * 1446 * Startup the corb DMA engine 1447 ****************************************************************************/ 1448static void 1449hdac_corb_start(struct hdac_softc *sc) 1450{ 1451 uint32_t corbctl; 1452 1453 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1454 corbctl |= HDAC_CORBCTL_CORBRUN; 1455 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1456} 1457 1458/**************************************************************************** 1459 * void hdac_rirb_start(hdac_softc *) 1460 * 1461 * Startup the rirb DMA engine 1462 ****************************************************************************/ 1463static void 1464hdac_rirb_start(struct hdac_softc *sc) 1465{ 1466 uint32_t rirbctl; 1467 1468 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1469 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1470 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1471} 1472 1473 1474/**************************************************************************** 1475 * void hdac_scan_codecs(struct hdac_softc *) 1476 * 1477 * Scan the bus for available codecs. 1478 ****************************************************************************/ 1479static void 1480hdac_scan_codecs(struct hdac_softc *sc) 1481{ 1482 struct hdac_codec *codec; 1483 int i; 1484 uint16_t statests; 1485 1486 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1487 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1488 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1489 /* We have found a codec. */ 1490 hdac_unlock(sc); 1491 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1492 M_HDAC, M_ZERO | M_NOWAIT); 1493 hdac_lock(sc); 1494 if (codec == NULL) { 1495 device_printf(sc->dev, 1496 "Unable to allocate memory for codec\n"); 1497 continue; 1498 } 1499 codec->commands = NULL; 1500 codec->responses_received = 0; 1501 codec->verbs_sent = 0; 1502 codec->sc = sc; 1503 codec->cad = i; 1504 sc->codecs[i] = codec; 1505 if (hdac_probe_codec(codec) != 0) 1506 break; 1507 } 1508 } 1509 /* All codecs have been probed, now try to attach drivers to them */ 1510 /* bus_generic_attach(sc->dev); */ 1511} 1512 1513/**************************************************************************** 1514 * void hdac_probe_codec(struct hdac_softc *, int) 1515 * 1516 * Probe a the given codec_id for available function groups. 1517 ****************************************************************************/ 1518static int 1519hdac_probe_codec(struct hdac_codec *codec) 1520{ 1521 struct hdac_softc *sc = codec->sc; 1522 struct hdac_devinfo *devinfo; 1523 uint32_t vendorid, revisionid, subnode; 1524 int startnode; 1525 int endnode; 1526 int i; 1527 nid_t cad = codec->cad; 1528 1529 HDA_BOOTVERBOSE( 1530 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1531 ); 1532 vendorid = hdac_command(sc, 1533 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1534 cad); 1535 revisionid = hdac_command(sc, 1536 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1537 cad); 1538 subnode = hdac_command(sc, 1539 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1540 cad); 1541 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1542 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1543 1544 HDA_BOOTVERBOSE( 1545 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1546 startnode, endnode); 1547 ); 1548 for (i = startnode; i < endnode; i++) { 1549 devinfo = hdac_probe_function(codec, i); 1550 if (devinfo != NULL) { 1551 /* XXX Ignore other FG. */ 1552 devinfo->vendor_id = 1553 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1554 devinfo->device_id = 1555 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1556 devinfo->revision_id = 1557 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1558 devinfo->stepping_id = 1559 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1560 HDA_BOOTVERBOSE( 1561 device_printf(sc->dev, 1562 "HDA_DEBUG: \tFound AFG nid=%d " 1563 "[startnode=%d endnode=%d]\n", 1564 devinfo->nid, startnode, endnode); 1565 ); 1566 return (1); 1567 } 1568 } 1569 1570 HDA_BOOTVERBOSE( 1571 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1572 ); 1573 return (0); 1574} 1575 1576static struct hdac_devinfo * 1577hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1578{ 1579 struct hdac_softc *sc = codec->sc; 1580 struct hdac_devinfo *devinfo; 1581 uint32_t fctgrptype; 1582 nid_t cad = codec->cad; 1583 1584 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1585 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1586 1587 /* XXX For now, ignore other FG. */ 1588 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1589 return (NULL); 1590 1591 hdac_unlock(sc); 1592 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1593 M_NOWAIT | M_ZERO); 1594 hdac_lock(sc); 1595 if (devinfo == NULL) { 1596 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1597 __func__); 1598 return (NULL); 1599 } 1600 1601 devinfo->nid = nid; 1602 devinfo->node_type = fctgrptype; 1603 devinfo->codec = codec; 1604 1605 hdac_add_child(sc, devinfo); 1606 1607 return (devinfo); 1608} 1609 1610static void 1611hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1612{ 1613 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1614 device_set_ivars(devinfo->dev, (void *)devinfo); 1615 /* XXX - Print more information when booting verbose??? */ 1616} 1617 1618static void 1619hdac_widget_connection_parse(struct hdac_widget *w) 1620{ 1621 struct hdac_softc *sc = w->devinfo->codec->sc; 1622 uint32_t res; 1623 int i, j, max, found, entnum, cnid; 1624 nid_t cad = w->devinfo->codec->cad; 1625 nid_t nid = w->nid; 1626 1627 res = hdac_command(sc, 1628 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1629 1630 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1631 1632 if (w->nconns < 1) 1633 return; 1634 1635 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1636 res = 0; 1637 i = 0; 1638 found = 0; 1639 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1640 1641 while (i < w->nconns) { 1642 res = hdac_command(sc, 1643 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1644 for (j = 0; j < entnum; j++) { 1645 cnid = res; 1646 cnid >>= (32 / entnum) * j; 1647 cnid &= (1 << (32 / entnum)) - 1; 1648 if (cnid == 0) 1649 continue; 1650 if (found > max) { 1651 device_printf(sc->dev, 1652 "node %d: Adding %d: " 1653 "Max connection reached!\n", 1654 nid, cnid); 1655 continue; 1656 } 1657 w->conns[found++] = cnid; 1658 } 1659 i += entnum; 1660 } 1661 1662 HDA_BOOTVERBOSE( 1663 if (w->nconns != found) { 1664 device_printf(sc->dev, 1665 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1666 "length=%d != found=%d\n", 1667 nid, w->nconns, found); 1668 } 1669 ); 1670} 1671 1672static uint32_t 1673hdac_widget_pin_getconfig(struct hdac_widget *w) 1674{ 1675 struct hdac_softc *sc; 1676 uint32_t config, id; 1677 nid_t cad, nid; 1678 1679 sc = w->devinfo->codec->sc; 1680 cad = w->devinfo->codec->cad; 1681 nid = w->nid; 1682 id = hdac_codec_id(w->devinfo); 1683 1684 config = hdac_command(sc, 1685 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1686 cad); 1687 /* 1688 * XXX REWRITE!!!! Don't argue! 1689 */ 1690 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1691 switch (nid) { 1692 case 26: 1693 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1694 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1695 break; 1696 case 27: 1697 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1698 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1699 break; 1700 } 1701 } else if (id == HDA_CODEC_ALC880 && 1702 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1703 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1704 /* 1705 * Super broken BIOS 1706 */ 1707 switch (nid) { 1708 case 20: 1709 break; 1710 case 21: 1711 break; 1712 case 22: 1713 break; 1714 case 23: 1715 break; 1716 case 24: /* MIC1 */ 1717 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1718 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1719 break; 1720 case 25: /* XXX MIC2 */ 1721 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1722 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1723 break; 1724 case 26: /* LINE1 */ 1725 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1726 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1727 break; 1728 case 27: /* XXX LINE2 */ 1729 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1730 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1731 break; 1732 case 28: /* CD */ 1733 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1734 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1735 break; 1736 case 30: 1737 break; 1738 case 31: 1739 break; 1740 default: 1741 break; 1742 } 1743 } 1744 1745 return (config); 1746} 1747 1748static void 1749hdac_widget_pin_parse(struct hdac_widget *w) 1750{ 1751 struct hdac_softc *sc = w->devinfo->codec->sc; 1752 uint32_t config, pincap; 1753 char *devstr, *connstr; 1754 nid_t cad = w->devinfo->codec->cad; 1755 nid_t nid = w->nid; 1756 1757 config = hdac_widget_pin_getconfig(w); 1758 w->wclass.pin.config = config; 1759 1760 pincap = hdac_command(sc, 1761 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1762 w->wclass.pin.cap = pincap; 1763 1764 w->wclass.pin.ctrl = hdac_command(sc, 1765 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1766 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1767 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1768 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1769 1770 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1771 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1772 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1773 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1774 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1775 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1776 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1777 w->param.eapdbtl = hdac_command(sc, 1778 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1779 w->param.eapdbtl &= 0x7; 1780 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1781 } else 1782 w->param.eapdbtl = HDAC_INVALID; 1783 1784 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1785 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1786 devstr = "line out"; 1787 break; 1788 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1789 devstr = "speaker"; 1790 break; 1791 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1792 devstr = "headphones out"; 1793 break; 1794 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1795 devstr = "CD"; 1796 break; 1797 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1798 devstr = "SPDIF out"; 1799 break; 1800 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1801 devstr = "digital (other) out"; 1802 break; 1803 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1804 devstr = "modem, line side"; 1805 break; 1806 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1807 devstr = "modem, handset side"; 1808 break; 1809 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1810 devstr = "line in"; 1811 break; 1812 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1813 devstr = "AUX"; 1814 break; 1815 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1816 devstr = "Mic in"; 1817 break; 1818 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1819 devstr = "telephony"; 1820 break; 1821 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1822 devstr = "SPDIF in"; 1823 break; 1824 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1825 devstr = "digital (other) in"; 1826 break; 1827 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1828 devstr = "other"; 1829 break; 1830 default: 1831 devstr = "unknown"; 1832 break; 1833 } 1834 1835 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1836 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1837 connstr = "jack"; 1838 break; 1839 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1840 connstr = "none"; 1841 break; 1842 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1843 connstr = "fixed"; 1844 break; 1845 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1846 connstr = "jack / fixed"; 1847 break; 1848 default: 1849 connstr = "unknown"; 1850 break; 1851 } 1852 1853 strlcat(w->name, ": ", sizeof(w->name)); 1854 strlcat(w->name, devstr, sizeof(w->name)); 1855 strlcat(w->name, " (", sizeof(w->name)); 1856 strlcat(w->name, connstr, sizeof(w->name)); 1857 strlcat(w->name, ")", sizeof(w->name)); 1858} 1859 1860static void 1861hdac_widget_parse(struct hdac_widget *w) 1862{ 1863 struct hdac_softc *sc = w->devinfo->codec->sc; 1864 uint32_t wcap, cap; 1865 char *typestr; 1866 nid_t cad = w->devinfo->codec->cad; 1867 nid_t nid = w->nid; 1868 1869 wcap = hdac_command(sc, 1870 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1871 cad); 1872 w->param.widget_cap = wcap; 1873 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1874 1875 switch (w->type) { 1876 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1877 typestr = "audio output"; 1878 break; 1879 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1880 typestr = "audio input"; 1881 break; 1882 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1883 typestr = "audio mixer"; 1884 break; 1885 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1886 typestr = "audio selector"; 1887 break; 1888 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1889 typestr = "pin"; 1890 break; 1891 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1892 typestr = "power widget"; 1893 break; 1894 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1895 typestr = "volume widget"; 1896 break; 1897 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1898 typestr = "beep widget"; 1899 break; 1900 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1901 typestr = "vendor widget"; 1902 break; 1903 default: 1904 typestr = "unknown type"; 1905 break; 1906 } 1907 1908 strlcpy(w->name, typestr, sizeof(w->name)); 1909 1910 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1911 hdac_command(sc, 1912 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1913 cad); 1914 DELAY(1000); 1915 } 1916 1917 hdac_widget_connection_parse(w); 1918 1919 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1920 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1921 w->param.outamp_cap = 1922 hdac_command(sc, 1923 HDA_CMD_GET_PARAMETER(cad, nid, 1924 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1925 else 1926 w->param.outamp_cap = 1927 w->devinfo->function.audio.outamp_cap; 1928 } else 1929 w->param.outamp_cap = 0; 1930 1931 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1932 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1933 w->param.inamp_cap = 1934 hdac_command(sc, 1935 HDA_CMD_GET_PARAMETER(cad, nid, 1936 HDA_PARAM_INPUT_AMP_CAP), cad); 1937 else 1938 w->param.inamp_cap = 1939 w->devinfo->function.audio.inamp_cap; 1940 } else 1941 w->param.inamp_cap = 0; 1942 1943 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1944 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1945 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1946 cap = hdac_command(sc, 1947 HDA_CMD_GET_PARAMETER(cad, nid, 1948 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1949 w->param.supp_stream_formats = (cap != 0) ? cap : 1950 w->devinfo->function.audio.supp_stream_formats; 1951 cap = hdac_command(sc, 1952 HDA_CMD_GET_PARAMETER(cad, nid, 1953 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1954 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1955 w->devinfo->function.audio.supp_pcm_size_rate; 1956 } else { 1957 w->param.supp_stream_formats = 1958 w->devinfo->function.audio.supp_stream_formats; 1959 w->param.supp_pcm_size_rate = 1960 w->devinfo->function.audio.supp_pcm_size_rate; 1961 } 1962 } else { 1963 w->param.supp_stream_formats = 0; 1964 w->param.supp_pcm_size_rate = 0; 1965 } 1966 1967 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1968 hdac_widget_pin_parse(w); 1969} 1970 1971static struct hdac_widget * 1972hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1973{ 1974 if (devinfo == NULL || devinfo->widget == NULL || 1975 nid < devinfo->startnode || nid >= devinfo->endnode) 1976 return (NULL); 1977 return (&devinfo->widget[nid - devinfo->startnode]); 1978} 1979 1980static __inline int 1981hda_poll_channel(struct hdac_chan *ch) 1982{ 1983 uint32_t sz, delta; 1984 volatile uint32_t ptr; 1985 1986 if (ch->active == 0) 1987 return (0); 1988 1989 sz = ch->blksz * ch->blkcnt; 1990 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1991 ch->ptr = ptr; 1992 ptr %= sz; 1993 ptr &= ~(ch->blksz - 1); 1994 delta = (sz + ptr - ch->prevptr) % sz; 1995 1996 if (delta < ch->blksz) 1997 return (0); 1998 1999 ch->prevptr = ptr; 2000 2001 return (1); 2002} 2003 2004#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2005 2006static void 2007hda_poll_callback(void *arg) 2008{ 2009 struct hdac_softc *sc = arg; 2010 uint32_t trigger = 0; 2011 2012 if (sc == NULL) 2013 return; 2014 2015 hdac_lock(sc); 2016 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2017 hdac_unlock(sc); 2018 return; 2019 } 2020 2021 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2022 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2023 2024 /* XXX */ 2025 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2026 hda_poll_callback, sc); 2027 2028 hdac_unlock(sc); 2029 2030 if (trigger & 1) 2031 chn_intr(sc->play.c); 2032 if (trigger & 2) 2033 chn_intr(sc->rec.c); 2034} 2035 2036static int 2037hdac_rirb_flush(struct hdac_softc *sc) 2038{ 2039 struct hdac_rirb *rirb_base, *rirb; 2040 struct hdac_codec *codec; 2041 struct hdac_command_list *commands; 2042 nid_t cad; 2043 uint32_t resp; 2044 uint8_t rirbwp; 2045 int ret = 0; 2046 2047 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2048 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2049 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2050 BUS_DMASYNC_POSTREAD); 2051 2052 while (sc->rirb_rp != rirbwp) { 2053 sc->rirb_rp++; 2054 sc->rirb_rp %= sc->rirb_size; 2055 rirb = &rirb_base[sc->rirb_rp]; 2056 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2057 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2058 sc->codecs[cad] == NULL) 2059 continue; 2060 resp = rirb->response; 2061 codec = sc->codecs[cad]; 2062 commands = codec->commands; 2063 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2064 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2065 ((resp >> 26) & 0xffff); 2066 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2067 } else if (commands != NULL && commands->num_commands > 0 && 2068 codec->responses_received < commands->num_commands) 2069 commands->responses[codec->responses_received++] = 2070 resp; 2071 ret++; 2072 } 2073 2074 return (ret); 2075} 2076 2077static int 2078hdac_unsolq_flush(struct hdac_softc *sc) 2079{ 2080 nid_t cad; 2081 uint32_t tag; 2082 int ret = 0; 2083 2084 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2085 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2086 while (sc->unsolq_rp != sc->unsolq_wp) { 2087 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2088 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2089 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2090 hdac_unsolicited_handler(sc->codecs[cad], tag); 2091 ret++; 2092 } 2093 sc->unsolq_st = HDAC_UNSOLQ_READY; 2094 } 2095 2096 return (ret); 2097} 2098 2099static void 2100hdac_poll_callback(void *arg) 2101{ 2102 struct hdac_softc *sc = arg; 2103 if (sc == NULL) 2104 return; 2105 2106 hdac_lock(sc); 2107 if (sc->polling == 0) { 2108 hdac_unlock(sc); 2109 return; 2110 } 2111 hdac_rirb_flush(sc); 2112 hdac_unsolq_flush(sc); 2113 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2114 hdac_poll_callback, sc); 2115 hdac_unlock(sc); 2116} 2117 2118static void 2119hdac_stream_stop(struct hdac_chan *ch) 2120{ 2121 struct hdac_softc *sc = ch->devinfo->codec->sc; 2122 uint32_t ctl; 2123 2124 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2125 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2126 HDAC_SDCTL_RUN); 2127 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2128 2129 ch->active = 0; 2130 2131 if (sc->polling != 0) { 2132 int pollticks; 2133 2134 if (hda_chan_active(sc) == 0) { 2135 callout_stop(&sc->poll_hda); 2136 sc->poll_ticks = 1; 2137 } else { 2138 if (sc->play.active != 0) 2139 ch = &sc->play; 2140 else 2141 ch = &sc->rec; 2142 pollticks = ((uint64_t)hz * ch->blksz) / 2143 ((uint64_t)sndbuf_getbps(ch->b) * 2144 sndbuf_getspd(ch->b)); 2145 pollticks >>= 2; 2146 if (pollticks > hz) 2147 pollticks = hz; 2148 if (pollticks < 1) { 2149 HDA_BOOTVERBOSE( 2150 device_printf(sc->dev, 2151 "%s: pollticks=%d < 1 !\n", 2152 __func__, pollticks); 2153 ); 2154 pollticks = 1; 2155 } 2156 if (pollticks > sc->poll_ticks) { 2157 HDA_BOOTVERBOSE( 2158 device_printf(sc->dev, 2159 "%s: pollticks %d -> %d\n", 2160 __func__, sc->poll_ticks, 2161 pollticks); 2162 ); 2163 sc->poll_ticks = pollticks; 2164 callout_reset(&sc->poll_hda, 1, 2165 hda_poll_callback, sc); 2166 } 2167 } 2168 } else { 2169 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2170 ctl &= ~(1 << (ch->off >> 5)); 2171 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2172 } 2173} 2174 2175static void 2176hdac_stream_start(struct hdac_chan *ch) 2177{ 2178 struct hdac_softc *sc = ch->devinfo->codec->sc; 2179 uint32_t ctl; 2180 2181 if (sc->polling != 0) { 2182 int pollticks; 2183 2184 pollticks = ((uint64_t)hz * ch->blksz) / 2185 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2186 pollticks >>= 2; 2187 if (pollticks > hz) 2188 pollticks = hz; 2189 if (pollticks < 1) { 2190 HDA_BOOTVERBOSE( 2191 device_printf(sc->dev, 2192 "%s: pollticks=%d < 1 !\n", 2193 __func__, pollticks); 2194 ); 2195 pollticks = 1; 2196 } 2197 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2198 HDA_BOOTVERBOSE( 2199 if (hda_chan_active(sc) == 0) { 2200 device_printf(sc->dev, 2201 "%s: pollticks=%d\n", 2202 __func__, pollticks); 2203 } else { 2204 device_printf(sc->dev, 2205 "%s: pollticks %d -> %d\n", 2206 __func__, sc->poll_ticks, 2207 pollticks); 2208 } 2209 ); 2210 sc->poll_ticks = pollticks; 2211 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2212 sc); 2213 } 2214 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2215 ctl |= HDAC_SDCTL_RUN; 2216 } else { 2217 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2218 ctl |= 1 << (ch->off >> 5); 2219 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2220 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2221 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2222 HDAC_SDCTL_RUN; 2223 } 2224 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2225 2226 ch->active = 1; 2227} 2228 2229static void 2230hdac_stream_reset(struct hdac_chan *ch) 2231{ 2232 struct hdac_softc *sc = ch->devinfo->codec->sc; 2233 int timeout = 1000; 2234 int to = timeout; 2235 uint32_t ctl; 2236 2237 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2238 ctl |= HDAC_SDCTL_SRST; 2239 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2240 do { 2241 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2242 if (ctl & HDAC_SDCTL_SRST) 2243 break; 2244 DELAY(10); 2245 } while (--to); 2246 if (!(ctl & HDAC_SDCTL_SRST)) { 2247 device_printf(sc->dev, "timeout in reset\n"); 2248 } 2249 ctl &= ~HDAC_SDCTL_SRST; 2250 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2251 to = timeout; 2252 do { 2253 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2254 if (!(ctl & HDAC_SDCTL_SRST)) 2255 break; 2256 DELAY(10); 2257 } while (--to); 2258 if (ctl & HDAC_SDCTL_SRST) 2259 device_printf(sc->dev, "can't reset!\n"); 2260} 2261 2262static void 2263hdac_stream_setid(struct hdac_chan *ch) 2264{ 2265 struct hdac_softc *sc = ch->devinfo->codec->sc; 2266 uint32_t ctl; 2267 2268 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2269 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2270 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2271 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2272} 2273 2274static void 2275hdac_bdl_setup(struct hdac_chan *ch) 2276{ 2277 struct hdac_softc *sc = ch->devinfo->codec->sc; 2278 struct hdac_bdle *bdle; 2279 uint64_t addr; 2280 uint32_t blksz, blkcnt; 2281 int i; 2282 2283 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2284 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2285 2286 if (sc->polling != 0) { 2287 blksz = ch->blksz * ch->blkcnt; 2288 blkcnt = 1; 2289 } else { 2290 blksz = ch->blksz; 2291 blkcnt = ch->blkcnt; 2292 } 2293 2294 for (i = 0; i < blkcnt; i++, bdle++) { 2295 bdle->addrl = (uint32_t)addr; 2296 bdle->addrh = (uint32_t)(addr >> 32); 2297 bdle->len = blksz; 2298 bdle->ioc = 1 ^ sc->polling; 2299 addr += blksz; 2300 } 2301 2302 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2303 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2304 addr = ch->bdl_dma.dma_paddr; 2305 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2306 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2307} 2308 2309static int 2310hdac_bdl_alloc(struct hdac_chan *ch) 2311{ 2312 struct hdac_softc *sc = ch->devinfo->codec->sc; 2313 int rc; 2314 2315 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2316 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2317 if (rc) { 2318 device_printf(sc->dev, "can't alloc bdl\n"); 2319 return (rc); 2320 } 2321 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2322 2323 return (0); 2324} 2325 2326static void 2327hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2328 int index, int lmute, int rmute, 2329 int left, int right, int dir) 2330{ 2331 uint16_t v = 0; 2332 2333 if (sc == NULL) 2334 return; 2335 2336 if (left != right || lmute != rmute) { 2337 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2338 (lmute << 7) | left; 2339 hdac_command(sc, 2340 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2341 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2342 (rmute << 7) | right; 2343 } else 2344 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2345 (lmute << 7) | left; 2346 2347 hdac_command(sc, 2348 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2349} 2350 2351static void 2352hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2353 int left, int right) 2354{ 2355 struct hdac_softc *sc; 2356 nid_t nid, cad; 2357 int lmute, rmute; 2358 2359 if (ctl == NULL || ctl->widget == NULL || 2360 ctl->widget->devinfo == NULL || 2361 ctl->widget->devinfo->codec == NULL || 2362 ctl->widget->devinfo->codec->sc == NULL) 2363 return; 2364 2365 sc = ctl->widget->devinfo->codec->sc; 2366 cad = ctl->widget->devinfo->codec->cad; 2367 nid = ctl->widget->nid; 2368 2369 if (mute == HDA_AMP_MUTE_DEFAULT) { 2370 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2371 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2372 } else { 2373 lmute = HDA_AMP_LEFT_MUTED(mute); 2374 rmute = HDA_AMP_RIGHT_MUTED(mute); 2375 } 2376 2377 if (ctl->dir & HDA_CTL_OUT) 2378 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2379 lmute, rmute, left, right, 0); 2380 if (ctl->dir & HDA_CTL_IN) 2381 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2382 lmute, rmute, left, right, 1); 2383 ctl->left = left; 2384 ctl->right = right; 2385} 2386 2387static void 2388hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2389{ 2390 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2391 return; 2392 hdac_command(w->devinfo->codec->sc, 2393 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2394 w->nid, index), w->devinfo->codec->cad); 2395 w->selconn = index; 2396} 2397 2398 2399/**************************************************************************** 2400 * uint32_t hdac_command_sendone_internal 2401 * 2402 * Wrapper function that sends only one command to a given codec 2403 ****************************************************************************/ 2404static uint32_t 2405hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2406{ 2407 struct hdac_command_list cl; 2408 uint32_t response = HDAC_INVALID; 2409 2410 if (!hdac_lockowned(sc)) 2411 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2412 cl.num_commands = 1; 2413 cl.verbs = &verb; 2414 cl.responses = &response; 2415 2416 hdac_command_send_internal(sc, &cl, cad); 2417 2418 return (response); 2419} 2420 2421/**************************************************************************** 2422 * hdac_command_send_internal 2423 * 2424 * Send a command list to the codec via the corb. We queue as much verbs as 2425 * we can and msleep on the codec. When the interrupt get the responses 2426 * back from the rirb, it will wake us up so we can queue the remaining verbs 2427 * if any. 2428 ****************************************************************************/ 2429static void 2430hdac_command_send_internal(struct hdac_softc *sc, 2431 struct hdac_command_list *commands, nid_t cad) 2432{ 2433 struct hdac_codec *codec; 2434 int corbrp; 2435 uint32_t *corb; 2436 int timeout; 2437 int retry = 10; 2438 struct hdac_rirb *rirb_base; 2439 2440 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2441 commands->num_commands < 1) 2442 return; 2443 2444 codec = sc->codecs[cad]; 2445 codec->commands = commands; 2446 codec->responses_received = 0; 2447 codec->verbs_sent = 0; 2448 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2449 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2450 2451 do { 2452 if (codec->verbs_sent != commands->num_commands) { 2453 /* Queue as many verbs as possible */ 2454 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2455 bus_dmamap_sync(sc->corb_dma.dma_tag, 2456 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2457 while (codec->verbs_sent != commands->num_commands && 2458 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2459 sc->corb_wp++; 2460 sc->corb_wp %= sc->corb_size; 2461 corb[sc->corb_wp] = 2462 commands->verbs[codec->verbs_sent++]; 2463 } 2464 2465 /* Send the verbs to the codecs */ 2466 bus_dmamap_sync(sc->corb_dma.dma_tag, 2467 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2468 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2469 } 2470 2471 timeout = 1000; 2472 while (hdac_rirb_flush(sc) == 0 && --timeout) 2473 DELAY(10); 2474 } while ((codec->verbs_sent != commands->num_commands || 2475 codec->responses_received != commands->num_commands) && --retry); 2476 2477 if (retry == 0) 2478 device_printf(sc->dev, 2479 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2480 __func__, commands->num_commands, codec->verbs_sent, 2481 codec->responses_received); 2482 2483 codec->commands = NULL; 2484 codec->responses_received = 0; 2485 codec->verbs_sent = 0; 2486 2487 hdac_unsolq_flush(sc); 2488} 2489 2490 2491/**************************************************************************** 2492 * Device Methods 2493 ****************************************************************************/ 2494 2495/**************************************************************************** 2496 * int hdac_probe(device_t) 2497 * 2498 * Probe for the presence of an hdac. If none is found, check for a generic 2499 * match using the subclass of the device. 2500 ****************************************************************************/ 2501static int 2502hdac_probe(device_t dev) 2503{ 2504 int i, result; 2505 uint32_t model; 2506 uint16_t class, subclass; 2507 char desc[64]; 2508 2509 model = (uint32_t)pci_get_device(dev) << 16; 2510 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2511 class = pci_get_class(dev); 2512 subclass = pci_get_subclass(dev); 2513 2514 bzero(desc, sizeof(desc)); 2515 result = ENXIO; 2516 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2517 if (hdac_devices[i].model == model) { 2518 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2519 result = BUS_PROBE_DEFAULT; 2520 break; 2521 } 2522 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2523 class == PCIC_MULTIMEDIA && 2524 subclass == PCIS_MULTIMEDIA_HDA) { 2525 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2526 result = BUS_PROBE_GENERIC; 2527 break; 2528 } 2529 } 2530 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2531 subclass == PCIS_MULTIMEDIA_HDA) { 2532 strlcpy(desc, "Generic", sizeof(desc)); 2533 result = BUS_PROBE_GENERIC; 2534 } 2535 if (result != ENXIO) { 2536 strlcat(desc, " High Definition Audio Controller", 2537 sizeof(desc)); 2538 device_set_desc_copy(dev, desc); 2539 } 2540 2541 return (result); 2542} 2543 2544static void * 2545hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2546 struct pcm_channel *c, int dir) 2547{ 2548 struct hdac_devinfo *devinfo = data; 2549 struct hdac_softc *sc = devinfo->codec->sc; 2550 struct hdac_chan *ch; 2551 2552 hdac_lock(sc); 2553 if (dir == PCMDIR_PLAY) { 2554 ch = &sc->play; 2555 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2556 ch->dir = PCMDIR_PLAY; 2557 ch->sid = ++sc->streamcnt; 2558 devinfo->function.audio.playcnt++; 2559 } else { 2560 ch = &sc->rec; 2561 ch->off = devinfo->function.audio.reccnt << 5; 2562 ch->dir = PCMDIR_REC; 2563 ch->sid = ++sc->streamcnt; 2564 devinfo->function.audio.reccnt++; 2565 } 2566 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2567 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2568 ch->pcmrates[0] = 48000; 2569 ch->pcmrates[1] = 0; 2570 } 2571 ch->b = b; 2572 ch->c = c; 2573 ch->devinfo = devinfo; 2574 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2575 ch->blkcnt = sc->chan_blkcnt; 2576 hdac_unlock(sc); 2577 2578 if (hdac_bdl_alloc(ch) != 0) { 2579 ch->blkcnt = 0; 2580 return (NULL); 2581 } 2582 2583 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2584 return (NULL); 2585 2586 hdac_dma_nocache(ch->b->buf); 2587 2588 return (ch); 2589} 2590 2591static int 2592hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2593{ 2594 struct hdac_chan *ch = data; 2595 int i; 2596 2597 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2598 if (format == ch->caps.fmtlist[i]) { 2599 ch->fmt = format; 2600 return (0); 2601 } 2602 } 2603 2604 return (EINVAL); 2605} 2606 2607static int 2608hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2609{ 2610 struct hdac_chan *ch = data; 2611 uint32_t spd = 0, threshold; 2612 int i; 2613 2614 for (i = 0; ch->pcmrates[i] != 0; i++) { 2615 spd = ch->pcmrates[i]; 2616 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2617 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2618 if (speed < threshold) 2619 break; 2620 } 2621 2622 if (spd == 0) /* impossible */ 2623 ch->spd = 48000; 2624 else 2625 ch->spd = spd; 2626 2627 return (ch->spd); 2628} 2629 2630static void 2631hdac_stream_setup(struct hdac_chan *ch) 2632{ 2633 struct hdac_softc *sc = ch->devinfo->codec->sc; 2634 int i; 2635 nid_t cad = ch->devinfo->codec->cad; 2636 uint16_t fmt; 2637 2638 fmt = 0; 2639 if (ch->fmt & AFMT_S16_LE) 2640 fmt |= ch->bit16 << 4; 2641 else if (ch->fmt & AFMT_S32_LE) 2642 fmt |= ch->bit32 << 4; 2643 else 2644 fmt |= 1 << 4; 2645 2646 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2647 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2648 fmt |= hda_rate_tab[i].base; 2649 fmt |= hda_rate_tab[i].mul; 2650 fmt |= hda_rate_tab[i].div; 2651 break; 2652 } 2653 } 2654 2655 if (ch->fmt & AFMT_STEREO) 2656 fmt |= 1; 2657 2658 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2659 2660 for (i = 0; ch->io[i] != -1; i++) { 2661 HDA_BOOTVERBOSE( 2662 device_printf(sc->dev, 2663 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2664 "fmt=0x%08x\n", 2665 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2666 ch->io[i], fmt); 2667 ); 2668 hdac_command(sc, 2669 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2670 hdac_command(sc, 2671 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2672 ch->sid << 4), cad); 2673 } 2674} 2675 2676static int 2677hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2678{ 2679 struct hdac_chan *ch = data; 2680 struct hdac_softc *sc = ch->devinfo->codec->sc; 2681 2682 blksz &= ~0x7f; 2683 if (blksz < 0x80) 2684 blksz = 0x80; 2685 2686 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2687 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2688 2689 if ((sndbuf_getblksz(ch->b) != blksz || 2690 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2691 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2692 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2693 __func__, blksz, ch->blkcnt); 2694 2695 ch->blksz = sndbuf_getblksz(ch->b); 2696 2697 return (ch->blksz); 2698} 2699 2700static void 2701hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2702{ 2703 struct hdac_devinfo *devinfo = ch->devinfo; 2704 nid_t cad = devinfo->codec->cad; 2705 int i; 2706 2707 hdac_stream_stop(ch); 2708 2709 for (i = 0; ch->io[i] != -1; i++) { 2710 hdac_command(sc, 2711 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2712 0), cad); 2713 } 2714} 2715 2716static void 2717hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2718{ 2719 ch->ptr = 0; 2720 ch->prevptr = 0; 2721 hdac_stream_stop(ch); 2722 hdac_stream_reset(ch); 2723 hdac_bdl_setup(ch); 2724 hdac_stream_setid(ch); 2725 hdac_stream_setup(ch); 2726 hdac_stream_start(ch); 2727} 2728 2729static int 2730hdac_channel_trigger(kobj_t obj, void *data, int go) 2731{ 2732 struct hdac_chan *ch = data; 2733 struct hdac_softc *sc = ch->devinfo->codec->sc; 2734 2735 hdac_lock(sc); 2736 switch (go) { 2737 case PCMTRIG_START: 2738 hdac_channel_start(sc, ch); 2739 break; 2740 case PCMTRIG_STOP: 2741 case PCMTRIG_ABORT: 2742 hdac_channel_stop(sc, ch); 2743 break; 2744 } 2745 hdac_unlock(sc); 2746 2747 return (0); 2748} 2749 2750static int 2751hdac_channel_getptr(kobj_t obj, void *data) 2752{ 2753 struct hdac_chan *ch = data; 2754 struct hdac_softc *sc = ch->devinfo->codec->sc; 2755 uint32_t ptr; 2756 2757 hdac_lock(sc); 2758 if (sc->polling != 0) 2759 ptr = ch->ptr; 2760 else 2761 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2762 hdac_unlock(sc); 2763 2764 /* 2765 * Round to available space and force 128 bytes aligment. 2766 */ 2767 ptr %= ch->blksz * ch->blkcnt; 2768 ptr &= ~0x7f; 2769 2770 return (ptr); 2771} 2772 2773static struct pcmchan_caps * 2774hdac_channel_getcaps(kobj_t obj, void *data) 2775{ 2776 return (&((struct hdac_chan *)data)->caps); 2777} 2778 2779static kobj_method_t hdac_channel_methods[] = { 2780 KOBJMETHOD(channel_init, hdac_channel_init), 2781 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2782 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2783 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2784 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2785 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2786 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2787 { 0, 0 } 2788}; 2789CHANNEL_DECLARE(hdac_channel); 2790 2791static int 2792hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2793{ 2794 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2795 struct hdac_softc *sc = devinfo->codec->sc; 2796 struct hdac_widget *w, *cw; 2797 struct hdac_audio_ctl *ctl; 2798 uint32_t mask, recmask, id; 2799 int i, j, softpcmvol; 2800 nid_t cad; 2801 2802 hdac_lock(sc); 2803 2804 mask = 0; 2805 recmask = 0; 2806 2807 id = hdac_codec_id(devinfo); 2808 cad = devinfo->codec->cad; 2809 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2810 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2811 sc->pci_subvendor) && 2812 hdac_hp_switch[i].id == id)) 2813 continue; 2814 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2815 if (w != NULL && w->enable != 0 2816 && w->type == 2817 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2818 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2819 hdac_command(sc, 2820 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2821 w->nid, 2822 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2823 HDAC_UNSOLTAG_EVENT_HP), cad); 2824 hdac_hp_switch_handler(devinfo); 2825 HDA_BOOTVERBOSE( 2826 device_printf(sc->dev, 2827 "HDA_DEBUG: Enabling headphone/speaker " 2828 "audio routing switching:\n"); 2829 device_printf(sc->dev, 2830 "HDA_DEBUG: \tindex=%d nid=%d " 2831 "pci_subvendor=0x%08x " 2832 "codec=0x%08x\n", 2833 i, w->nid, sc->pci_subvendor, id); 2834 ); 2835 } 2836 break; 2837 } 2838 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2839 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2840 sc->pci_subvendor) && 2841 hdac_eapd_switch[i].id == id)) 2842 continue; 2843 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2844 if (w == NULL || w->enable == 0) 2845 break; 2846 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2847 w->param.eapdbtl == HDAC_INVALID) 2848 break; 2849 mask |= SOUND_MASK_OGAIN; 2850 break; 2851 } 2852 2853 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2854 w = hdac_widget_get(devinfo, i); 2855 if (w == NULL || w->enable == 0) 2856 continue; 2857 mask |= w->ctlflags; 2858 if (!(w->pflags & HDA_ADC_RECSEL)) 2859 continue; 2860 for (j = 0; j < w->nconns; j++) { 2861 cw = hdac_widget_get(devinfo, w->conns[j]); 2862 if (cw == NULL || cw->enable == 0) 2863 continue; 2864 recmask |= cw->ctlflags; 2865 } 2866 } 2867 2868 if (!(mask & SOUND_MASK_PCM)) { 2869 softpcmvol = 1; 2870 mask |= SOUND_MASK_PCM; 2871 } else 2872 softpcmvol = (devinfo->function.audio.quirks & 2873 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2874 2875 i = 0; 2876 ctl = NULL; 2877 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2878 if (ctl->widget == NULL || ctl->enable == 0) 2879 continue; 2880 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2881 continue; 2882 if (ctl->step > 0) 2883 break; 2884 } 2885 2886 if (softpcmvol == 1 || ctl == NULL) { 2887 struct snddev_info *d = NULL; 2888 d = device_get_softc(sc->dev); 2889 if (d != NULL) { 2890 d->flags |= SD_F_SOFTPCMVOL; 2891 HDA_BOOTVERBOSE( 2892 device_printf(sc->dev, 2893 "HDA_DEBUG: %s Soft PCM volume\n", 2894 (softpcmvol == 1) ? 2895 "Forcing" : "Enabling"); 2896 ); 2897 } 2898 i = 0; 2899 /* 2900 * XXX Temporary quirk for STAC9220, until the parser 2901 * become smarter. 2902 */ 2903 if (id == HDA_CODEC_STAC9220) { 2904 mask |= SOUND_MASK_VOLUME; 2905 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2906 NULL) { 2907 if (ctl->widget == NULL || ctl->enable == 0) 2908 continue; 2909 if (ctl->widget->nid == 11 && ctl->index == 0) { 2910 ctl->ossmask = SOUND_MASK_VOLUME; 2911 ctl->ossval = 100 | (100 << 8); 2912 } else 2913 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2914 } 2915 } else { 2916 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2917 SOUND_MASK_PCM); 2918 if (!(mask & SOUND_MASK_VOLUME)) 2919 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2920 SOUND_MIXER_NONE); 2921 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2922 NULL) { 2923 if (ctl->widget == NULL || ctl->enable == 0) 2924 continue; 2925 if (!HDA_FLAG_MATCH(ctl->ossmask, 2926 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2927 continue; 2928 if (!(ctl->mute == 1 && ctl->step == 0)) 2929 ctl->enable = 0; 2930 } 2931 } 2932 } 2933 2934 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2935 2936 mix_setrecdevs(m, recmask); 2937 mix_setdevs(m, mask); 2938 2939 hdac_unlock(sc); 2940 2941 return (0); 2942} 2943 2944static int 2945hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2946 unsigned left, unsigned right) 2947{ 2948 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2949 struct hdac_softc *sc = devinfo->codec->sc; 2950 struct hdac_widget *w; 2951 struct hdac_audio_ctl *ctl; 2952 uint32_t id, mute; 2953 int lvol, rvol, mlvol, mrvol; 2954 int i = 0; 2955 2956 hdac_lock(sc); 2957 if (dev == SOUND_MIXER_OGAIN) { 2958 uint32_t orig; 2959 /*if (left != right || !(left == 0 || left == 1)) { 2960 hdac_unlock(sc); 2961 return (-1); 2962 }*/ 2963 id = hdac_codec_id(devinfo); 2964 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2965 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2966 sc->pci_subvendor) && 2967 hdac_eapd_switch[i].id == id) 2968 break; 2969 } 2970 if (i >= HDAC_EAPD_SWITCH_LEN) { 2971 hdac_unlock(sc); 2972 return (-1); 2973 } 2974 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2975 if (w == NULL || 2976 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2977 w->param.eapdbtl == HDAC_INVALID) { 2978 hdac_unlock(sc); 2979 return (-1); 2980 } 2981 orig = w->param.eapdbtl; 2982 if (left == 0) 2983 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2984 else 2985 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2986 if (orig != w->param.eapdbtl) { 2987 uint32_t val; 2988 2989 if (hdac_eapd_switch[i].hp_switch != 0) 2990 hdac_hp_switch_handler(devinfo); 2991 val = w->param.eapdbtl; 2992 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2993 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2994 hdac_command(sc, 2995 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2996 w->nid, val), devinfo->codec->cad); 2997 } 2998 hdac_unlock(sc); 2999 return (left | (left << 8)); 3000 } 3001 if (dev == SOUND_MIXER_VOLUME) 3002 devinfo->function.audio.mvol = left | (right << 8); 3003 3004 mlvol = devinfo->function.audio.mvol & 0x7f; 3005 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3006 lvol = 0; 3007 rvol = 0; 3008 3009 i = 0; 3010 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3011 if (ctl->widget == NULL || ctl->enable == 0 || 3012 !(ctl->ossmask & (1 << dev))) 3013 continue; 3014 switch (dev) { 3015 case SOUND_MIXER_VOLUME: 3016 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3017 lvol = (lvol * ctl->step) / 100; 3018 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3019 rvol = (rvol * ctl->step) / 100; 3020 break; 3021 default: 3022 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3023 lvol = (left * mlvol) / 100; 3024 lvol = (lvol * ctl->step) / 100; 3025 rvol = (right * mrvol) / 100; 3026 rvol = (rvol * ctl->step) / 100; 3027 } else { 3028 lvol = (left * ctl->step) / 100; 3029 rvol = (right * ctl->step) / 100; 3030 } 3031 ctl->ossval = left | (right << 8); 3032 break; 3033 } 3034 mute = 0; 3035 if (ctl->step < 1) { 3036 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3037 (ctl->muted & HDA_AMP_MUTE_LEFT); 3038 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3039 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3040 } else { 3041 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3042 (ctl->muted & HDA_AMP_MUTE_LEFT); 3043 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3044 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3045 } 3046 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3047 } 3048 hdac_unlock(sc); 3049 3050 return (left | (right << 8)); 3051} 3052 3053static int 3054hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3055{ 3056 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3057 struct hdac_widget *w, *cw; 3058 struct hdac_softc *sc = devinfo->codec->sc; 3059 uint32_t ret = src, target; 3060 int i, j; 3061 3062 target = 0; 3063 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3064 if (src & (1 << i)) { 3065 target = 1 << i; 3066 break; 3067 } 3068 } 3069 3070 hdac_lock(sc); 3071 3072 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3073 w = hdac_widget_get(devinfo, i); 3074 if (w == NULL || w->enable == 0) 3075 continue; 3076 if (!(w->pflags & HDA_ADC_RECSEL)) 3077 continue; 3078 for (j = 0; j < w->nconns; j++) { 3079 cw = hdac_widget_get(devinfo, w->conns[j]); 3080 if (cw == NULL || cw->enable == 0) 3081 continue; 3082 if ((target == SOUND_MASK_VOLUME && 3083 cw->type != 3084 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3085 (target != SOUND_MASK_VOLUME && 3086 cw->type == 3087 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3088 continue; 3089 if (cw->ctlflags & target) { 3090 hdac_widget_connection_select(w, j); 3091 ret = target; 3092 j += w->nconns; 3093 } 3094 } 3095 } 3096 3097 hdac_unlock(sc); 3098 3099 return (ret); 3100} 3101 3102static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3103 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3104 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3105 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3106 { 0, 0 } 3107}; 3108MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3109 3110/**************************************************************************** 3111 * int hdac_attach(device_t) 3112 * 3113 * Attach the device into the kernel. Interrupts usually won't be enabled 3114 * when this function is called. Setup everything that doesn't require 3115 * interrupts and defer probing of codecs until interrupts are enabled. 3116 ****************************************************************************/ 3117static int 3118hdac_attach(device_t dev) 3119{ 3120 struct hdac_softc *sc; 3121 int result; 3122 int i = 0; 3123 3124 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3125 if (sc == NULL) { 3126 device_printf(dev, "cannot allocate softc\n"); 3127 return (ENOMEM); 3128 } 3129 3130 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3131 if (sc->lock == NULL) { 3132 device_printf(dev, "mutex creation failed\n"); 3133 free(sc, M_DEVBUF); 3134 return (ENOMEM); 3135 } 3136 3137 sc->dev = dev; 3138 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3139 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3140 3141 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3142 /* Screw nx6325 - subdevice/subvendor swapped */ 3143 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3144 } 3145 3146 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3147 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3148 3149 sc->poll_ticks = 1; 3150 if (resource_int_value(device_get_name(sc->dev), 3151 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3152 sc->polling = 1; 3153 else 3154 sc->polling = 0; 3155 3156 sc->chan_size = pcm_getbuffersize(dev, 3157 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3158 3159 if (resource_int_value(device_get_name(sc->dev), 3160 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3161 i &= ~0x7f; 3162 if (i < 0x80) 3163 i = 0x80; 3164 sc->chan_blkcnt = sc->chan_size / i; 3165 i = 0; 3166 while (sc->chan_blkcnt >> i) 3167 i++; 3168 sc->chan_blkcnt = 1 << (i - 1); 3169 if (sc->chan_blkcnt < HDA_BDL_MIN) 3170 sc->chan_blkcnt = HDA_BDL_MIN; 3171 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3172 sc->chan_blkcnt = HDA_BDL_MAX; 3173 } else 3174 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3175 3176 result = bus_dma_tag_create(NULL, /* parent */ 3177 HDAC_DMA_ALIGNMENT, /* alignment */ 3178 0, /* boundary */ 3179 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3180 BUS_SPACE_MAXADDR, /* highaddr */ 3181 NULL, /* filtfunc */ 3182 NULL, /* fistfuncarg */ 3183 sc->chan_size, /* maxsize */ 3184 1, /* nsegments */ 3185 sc->chan_size, /* maxsegsz */ 3186 0, /* flags */ 3187 NULL, /* lockfunc */ 3188 NULL, /* lockfuncarg */ 3189 &sc->chan_dmat); /* dmat */ 3190 if (result != 0) { 3191 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3192 __func__, result); 3193 snd_mtxfree(sc->lock); 3194 free(sc, M_DEVBUF); 3195 return (ENXIO); 3196 } 3197 3198 3199 sc->hdabus = NULL; 3200 for (i = 0; i < HDAC_CODEC_MAX; i++) 3201 sc->codecs[i] = NULL; 3202 3203 pci_enable_busmaster(dev); 3204 3205 /* Allocate resources */ 3206 result = hdac_mem_alloc(sc); 3207 if (result != 0) 3208 goto hdac_attach_fail; 3209 result = hdac_irq_alloc(sc); 3210 if (result != 0) 3211 goto hdac_attach_fail; 3212 3213 /* Get Capabilities */ 3214 result = hdac_get_capabilities(sc); 3215 if (result != 0) 3216 goto hdac_attach_fail; 3217 3218 /* Allocate CORB and RIRB dma memory */ 3219 result = hdac_dma_alloc(sc, &sc->corb_dma, 3220 sc->corb_size * sizeof(uint32_t)); 3221 if (result != 0) 3222 goto hdac_attach_fail; 3223 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3224 sc->rirb_size * sizeof(struct hdac_rirb)); 3225 if (result != 0) 3226 goto hdac_attach_fail; 3227 3228 /* Quiesce everything */ 3229 hdac_reset(sc); 3230 3231 /* Disable PCI-Express QOS */ 3232 pci_write_config(sc->dev, 0x44, 3233 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3234 3235 /* Initialize the CORB and RIRB */ 3236 hdac_corb_init(sc); 3237 hdac_rirb_init(sc); 3238 3239 /* Defer remaining of initialization until interrupts are enabled */ 3240 sc->intrhook.ich_func = hdac_attach2; 3241 sc->intrhook.ich_arg = (void *)sc; 3242 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3243 sc->intrhook.ich_func = NULL; 3244 hdac_attach2((void *)sc); 3245 } 3246 3247 return (0); 3248 3249hdac_attach_fail: 3250 hdac_dma_free(&sc->rirb_dma); 3251 hdac_dma_free(&sc->corb_dma); 3252 hdac_irq_free(sc); 3253 hdac_mem_free(sc); 3254 snd_mtxfree(sc->lock); 3255 free(sc, M_DEVBUF); 3256 3257 return (ENXIO); 3258} 3259 3260static void 3261hdac_audio_parse(struct hdac_devinfo *devinfo) 3262{ 3263 struct hdac_softc *sc = devinfo->codec->sc; 3264 struct hdac_widget *w; 3265 uint32_t res; 3266 int i; 3267 nid_t cad, nid; 3268 3269 cad = devinfo->codec->cad; 3270 nid = devinfo->nid; 3271 3272 hdac_command(sc, 3273 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3274 3275 DELAY(100); 3276 3277 res = hdac_command(sc, 3278 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3279 3280 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3281 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3282 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3283 3284 HDA_BOOTVERBOSE( 3285 device_printf(sc->dev, " Vendor: 0x%08x\n", 3286 devinfo->vendor_id); 3287 device_printf(sc->dev, " Device: 0x%08x\n", 3288 devinfo->device_id); 3289 device_printf(sc->dev, " Revision: 0x%08x\n", 3290 devinfo->revision_id); 3291 device_printf(sc->dev, " Stepping: 0x%08x\n", 3292 devinfo->stepping_id); 3293 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3294 sc->pci_subvendor); 3295 device_printf(sc->dev, " Nodes: start=%d " 3296 "endnode=%d total=%d\n", 3297 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3298 ); 3299 3300 res = hdac_command(sc, 3301 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3302 cad); 3303 devinfo->function.audio.supp_stream_formats = res; 3304 3305 res = hdac_command(sc, 3306 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3307 cad); 3308 devinfo->function.audio.supp_pcm_size_rate = res; 3309 3310 res = hdac_command(sc, 3311 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3312 cad); 3313 devinfo->function.audio.outamp_cap = res; 3314 3315 res = hdac_command(sc, 3316 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3317 cad); 3318 devinfo->function.audio.inamp_cap = res; 3319 3320 if (devinfo->nodecnt > 0) { 3321 hdac_unlock(sc); 3322 devinfo->widget = (struct hdac_widget *)malloc( 3323 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3324 M_NOWAIT | M_ZERO); 3325 hdac_lock(sc); 3326 } else 3327 devinfo->widget = NULL; 3328 3329 if (devinfo->widget == NULL) { 3330 device_printf(sc->dev, "unable to allocate widgets!\n"); 3331 devinfo->endnode = devinfo->startnode; 3332 devinfo->nodecnt = 0; 3333 return; 3334 } 3335 3336 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3337 w = hdac_widget_get(devinfo, i); 3338 if (w == NULL) 3339 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3340 else { 3341 w->devinfo = devinfo; 3342 w->nid = i; 3343 w->enable = 1; 3344 w->selconn = -1; 3345 w->pflags = 0; 3346 w->ctlflags = 0; 3347 w->param.eapdbtl = HDAC_INVALID; 3348 hdac_widget_parse(w); 3349 } 3350 } 3351} 3352 3353static void 3354hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3355{ 3356 struct hdac_softc *sc = devinfo->codec->sc; 3357 struct hdac_audio_ctl *ctls; 3358 struct hdac_widget *w, *cw; 3359 int i, j, cnt, max, ocap, icap; 3360 int mute, offset, step, size; 3361 3362 /* XXX This is redundant */ 3363 max = 0; 3364 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3365 w = hdac_widget_get(devinfo, i); 3366 if (w == NULL || w->enable == 0) 3367 continue; 3368 if (w->param.outamp_cap != 0) 3369 max++; 3370 if (w->param.inamp_cap != 0) { 3371 switch (w->type) { 3372 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3373 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3374 for (j = 0; j < w->nconns; j++) { 3375 cw = hdac_widget_get(devinfo, 3376 w->conns[j]); 3377 if (cw == NULL || cw->enable == 0) 3378 continue; 3379 max++; 3380 } 3381 break; 3382 default: 3383 max++; 3384 break; 3385 } 3386 } 3387 } 3388 3389 devinfo->function.audio.ctlcnt = max; 3390 3391 if (max < 1) 3392 return; 3393 3394 hdac_unlock(sc); 3395 ctls = (struct hdac_audio_ctl *)malloc( 3396 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3397 hdac_lock(sc); 3398 3399 if (ctls == NULL) { 3400 /* Blekh! */ 3401 device_printf(sc->dev, "unable to allocate ctls!\n"); 3402 devinfo->function.audio.ctlcnt = 0; 3403 return; 3404 } 3405 3406 cnt = 0; 3407 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3408 if (cnt >= max) { 3409 device_printf(sc->dev, "%s: Ctl overflow!\n", 3410 __func__); 3411 break; 3412 } 3413 w = hdac_widget_get(devinfo, i); 3414 if (w == NULL || w->enable == 0) 3415 continue; 3416 ocap = w->param.outamp_cap; 3417 icap = w->param.inamp_cap; 3418 if (ocap != 0) { 3419 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3420 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3421 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3422 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3423 /*if (offset > step) { 3424 HDA_BOOTVERBOSE( 3425 device_printf(sc->dev, 3426 "HDA_DEBUG: BUGGY outamp: nid=%d " 3427 "[offset=%d > step=%d]\n", 3428 w->nid, offset, step); 3429 ); 3430 offset = step; 3431 }*/ 3432 ctls[cnt].enable = 1; 3433 ctls[cnt].widget = w; 3434 ctls[cnt].mute = mute; 3435 ctls[cnt].step = step; 3436 ctls[cnt].size = size; 3437 ctls[cnt].offset = offset; 3438 ctls[cnt].left = offset; 3439 ctls[cnt].right = offset; 3440 ctls[cnt++].dir = HDA_CTL_OUT; 3441 } 3442 3443 if (icap != 0) { 3444 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3445 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3446 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3447 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3448 /*if (offset > step) { 3449 HDA_BOOTVERBOSE( 3450 device_printf(sc->dev, 3451 "HDA_DEBUG: BUGGY inamp: nid=%d " 3452 "[offset=%d > step=%d]\n", 3453 w->nid, offset, step); 3454 ); 3455 offset = step; 3456 }*/ 3457 switch (w->type) { 3458 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3459 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3460 for (j = 0; j < w->nconns; j++) { 3461 if (cnt >= max) { 3462 device_printf(sc->dev, 3463 "%s: Ctl overflow!\n", 3464 __func__); 3465 break; 3466 } 3467 cw = hdac_widget_get(devinfo, 3468 w->conns[j]); 3469 if (cw == NULL || cw->enable == 0) 3470 continue; 3471 ctls[cnt].enable = 1; 3472 ctls[cnt].widget = w; 3473 ctls[cnt].childwidget = cw; 3474 ctls[cnt].index = j; 3475 ctls[cnt].mute = mute; 3476 ctls[cnt].step = step; 3477 ctls[cnt].size = size; 3478 ctls[cnt].offset = offset; 3479 ctls[cnt].left = offset; 3480 ctls[cnt].right = offset; 3481 ctls[cnt++].dir = HDA_CTL_IN; 3482 } 3483 break; 3484 default: 3485 if (cnt >= max) { 3486 device_printf(sc->dev, 3487 "%s: Ctl overflow!\n", 3488 __func__); 3489 break; 3490 } 3491 ctls[cnt].enable = 1; 3492 ctls[cnt].widget = w; 3493 ctls[cnt].mute = mute; 3494 ctls[cnt].step = step; 3495 ctls[cnt].size = size; 3496 ctls[cnt].offset = offset; 3497 ctls[cnt].left = offset; 3498 ctls[cnt].right = offset; 3499 ctls[cnt++].dir = HDA_CTL_IN; 3500 break; 3501 } 3502 } 3503 } 3504 3505 devinfo->function.audio.ctl = ctls; 3506} 3507 3508static const struct { 3509 uint32_t model; 3510 uint32_t id; 3511 uint32_t set, unset; 3512} hdac_quirks[] = { 3513 /* 3514 * XXX Force stereo quirk. Monoural recording / playback 3515 * on few codecs (especially ALC880) seems broken or 3516 * perhaps unsupported. 3517 */ 3518 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3519 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3520 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3521 HDA_QUIRK_GPIO0, 0 }, 3522 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3523 HDA_QUIRK_GPIO0, 0 }, 3524 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3525 HDA_QUIRK_GPIO0, 0 }, 3526 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3527 HDA_QUIRK_EAPDINV, 0 }, 3528 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3529 HDA_QUIRK_EAPDINV, 0 }, 3530 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3531 HDA_QUIRK_GPIO1, 0 }, 3532 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3533 HDA_QUIRK_EAPDINV, 0 }, 3534 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3535 HDA_QUIRK_EAPDINV, 0 }, 3536 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3537 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3538 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3539 0, HDA_QUIRK_FORCESTEREO }, 3540 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3541 HDA_QUIRK_SOFTPCMVOL, 0 } 3542}; 3543#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3544 3545static void 3546hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3547{ 3548 struct hdac_widget *w; 3549 struct hdac_audio_ctl *ctl; 3550 uint32_t id, subvendor; 3551 int i; 3552 3553 id = hdac_codec_id(devinfo); 3554 subvendor = devinfo->codec->sc->pci_subvendor; 3555 3556 /* 3557 * Quirks 3558 */ 3559 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3560 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3561 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3562 continue; 3563 if (hdac_quirks[i].set != 0) 3564 devinfo->function.audio.quirks |= 3565 hdac_quirks[i].set; 3566 if (hdac_quirks[i].unset != 0) 3567 devinfo->function.audio.quirks &= 3568 ~(hdac_quirks[i].unset); 3569 } 3570 3571 switch (id) { 3572 case HDA_CODEC_ALC260: 3573 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3574 w = hdac_widget_get(devinfo, i); 3575 if (w == NULL || w->enable == 0) 3576 continue; 3577 if (w->type != 3578 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3579 continue; 3580 if (w->nid != 5) 3581 w->enable = 0; 3582 } 3583 break; 3584 case HDA_CODEC_ALC861: 3585 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3586 if (ctl != NULL) 3587 ctl->muted = HDA_AMP_MUTE_ALL; 3588 break; 3589 case HDA_CODEC_ALC880: 3590 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3591 w = hdac_widget_get(devinfo, i); 3592 if (w == NULL || w->enable == 0) 3593 continue; 3594 if (w->type == 3595 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3596 w->nid != 9 && w->nid != 29) { 3597 w->enable = 0; 3598 } else if (w->type != 3599 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3600 w->nid == 29) { 3601 w->type = 3602 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3603 w->param.widget_cap &= 3604 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3605 w->param.widget_cap |= 3606 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3607 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3608 strlcpy(w->name, "beep widget", sizeof(w->name)); 3609 } 3610 } 3611 break; 3612 case HDA_CODEC_AD1981HD: 3613 w = hdac_widget_get(devinfo, 11); 3614 if (w != NULL && w->enable != 0 && w->nconns > 3) 3615 w->selconn = 3; 3616 if (subvendor == IBM_M52_SUBVENDOR) { 3617 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3618 if (ctl != NULL) 3619 ctl->ossmask = SOUND_MASK_SPEAKER; 3620 } 3621 break; 3622 case HDA_CODEC_AD1986A: 3623 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3624 w = hdac_widget_get(devinfo, i); 3625 if (w == NULL || w->enable == 0) 3626 continue; 3627 if (w->type != 3628 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3629 continue; 3630 if (w->nid != 3) 3631 w->enable = 0; 3632 } 3633 break; 3634 case HDA_CODEC_STAC9221: 3635 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3636 w = hdac_widget_get(devinfo, i); 3637 if (w == NULL || w->enable == 0) 3638 continue; 3639 if (w->type != 3640 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3641 continue; 3642 if (w->nid != 2) 3643 w->enable = 0; 3644 } 3645 break; 3646 case HDA_CODEC_STAC9221D: 3647 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3648 w = hdac_widget_get(devinfo, i); 3649 if (w == NULL || w->enable == 0) 3650 continue; 3651 if (w->type == 3652 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3653 w->nid != 6) 3654 w->enable = 0; 3655 3656 } 3657 break; 3658 default: 3659 break; 3660 } 3661} 3662 3663static int 3664hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3665{ 3666 int *dev = &devinfo->function.audio.ossidx; 3667 3668 while (*dev < SOUND_MIXER_NRDEVICES) { 3669 switch (*dev) { 3670 case SOUND_MIXER_VOLUME: 3671 case SOUND_MIXER_BASS: 3672 case SOUND_MIXER_TREBLE: 3673 case SOUND_MIXER_PCM: 3674 case SOUND_MIXER_SPEAKER: 3675 case SOUND_MIXER_LINE: 3676 case SOUND_MIXER_MIC: 3677 case SOUND_MIXER_CD: 3678 case SOUND_MIXER_RECLEV: 3679 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3680 (*dev)++; 3681 break; 3682 default: 3683 return (*dev)++; 3684 break; 3685 } 3686 } 3687 3688 return (-1); 3689} 3690 3691static int 3692hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3693{ 3694 struct hdac_widget *w; 3695 int i, ret = 0; 3696 3697 if (depth > HDA_PARSE_MAXDEPTH) 3698 return (0); 3699 w = hdac_widget_get(devinfo, nid); 3700 if (w == NULL || w->enable == 0) 3701 return (0); 3702 switch (w->type) { 3703 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3704 w->pflags |= HDA_DAC_PATH; 3705 ret = 1; 3706 break; 3707 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3708 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3709 for (i = 0; i < w->nconns; i++) { 3710 if (hdac_widget_find_dac_path(devinfo, 3711 w->conns[i], depth + 1) != 0) { 3712 if (w->selconn == -1) 3713 w->selconn = i; 3714 ret = 1; 3715 w->pflags |= HDA_DAC_PATH; 3716 } 3717 } 3718 break; 3719 default: 3720 break; 3721 } 3722 return (ret); 3723} 3724 3725static int 3726hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3727{ 3728 struct hdac_widget *w; 3729 int i, conndev, ret = 0; 3730 3731 if (depth > HDA_PARSE_MAXDEPTH) 3732 return (0); 3733 w = hdac_widget_get(devinfo, nid); 3734 if (w == NULL || w->enable == 0) 3735 return (0); 3736 switch (w->type) { 3737 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3738 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3739 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3740 for (i = 0; i < w->nconns; i++) { 3741 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3742 depth + 1) != 0) { 3743 if (w->selconn == -1) 3744 w->selconn = i; 3745 w->pflags |= HDA_ADC_PATH; 3746 ret = 1; 3747 } 3748 } 3749 break; 3750 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3751 conndev = w->wclass.pin.config & 3752 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3753 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3754 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3755 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3756 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3757 w->pflags |= HDA_ADC_PATH; 3758 ret = 1; 3759 } 3760 break; 3761 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3762 if (w->pflags & HDA_DAC_PATH) { 3763 w->pflags |= HDA_ADC_PATH; 3764 ret = 1; 3765 } 3766 break;*/ 3767 default: 3768 break; 3769 } 3770 return (ret); 3771} 3772 3773static uint32_t 3774hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3775 nid_t nid, nid_t pnid, int index, int depth) 3776{ 3777 struct hdac_widget *w, *pw; 3778 struct hdac_audio_ctl *ctl; 3779 uint32_t fl = 0; 3780 int i, ossdev, conndev, strategy; 3781 3782 if (depth > HDA_PARSE_MAXDEPTH) 3783 return (0); 3784 3785 w = hdac_widget_get(devinfo, nid); 3786 if (w == NULL || w->enable == 0) 3787 return (0); 3788 3789 pw = hdac_widget_get(devinfo, pnid); 3790 strategy = devinfo->function.audio.parsing_strategy; 3791 3792 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3793 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3794 for (i = 0; i < w->nconns; i++) { 3795 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3796 w->nid, i, depth + 1); 3797 } 3798 w->ctlflags |= fl; 3799 return (fl); 3800 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3801 (w->pflags & HDA_DAC_PATH)) { 3802 i = 0; 3803 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3804 if (ctl->enable == 0 || ctl->widget == NULL) 3805 continue; 3806 /* XXX This should be compressed! */ 3807 if ((ctl->widget->nid == w->nid) || 3808 (ctl->widget->nid == pnid && ctl->index == index && 3809 (ctl->dir & HDA_CTL_IN)) || 3810 (ctl->widget->nid == pnid && pw != NULL && 3811 pw->type == 3812 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3813 (pw->nconns < 2 || pw->selconn == index || 3814 pw->selconn == -1) && 3815 (ctl->dir & HDA_CTL_OUT)) || 3816 (strategy == HDA_PARSE_DIRECT && 3817 ctl->widget->nid == w->nid)) { 3818 /*if (pw != NULL && pw->selconn == -1) 3819 pw->selconn = index; 3820 fl |= SOUND_MASK_VOLUME; 3821 fl |= SOUND_MASK_PCM; 3822 ctl->ossmask |= SOUND_MASK_VOLUME; 3823 ctl->ossmask |= SOUND_MASK_PCM; 3824 ctl->ossdev = SOUND_MIXER_PCM;*/ 3825 if (!(w->ctlflags & SOUND_MASK_PCM) || 3826 (pw != NULL && 3827 !(pw->ctlflags & SOUND_MASK_PCM))) { 3828 fl |= SOUND_MASK_VOLUME; 3829 fl |= SOUND_MASK_PCM; 3830 ctl->ossmask |= SOUND_MASK_VOLUME; 3831 ctl->ossmask |= SOUND_MASK_PCM; 3832 ctl->ossdev = SOUND_MIXER_PCM; 3833 w->ctlflags |= SOUND_MASK_VOLUME; 3834 w->ctlflags |= SOUND_MASK_PCM; 3835 if (pw != NULL) { 3836 if (pw->selconn == -1) 3837 pw->selconn = index; 3838 pw->ctlflags |= 3839 SOUND_MASK_VOLUME; 3840 pw->ctlflags |= 3841 SOUND_MASK_PCM; 3842 } 3843 } 3844 } 3845 } 3846 w->ctlflags |= fl; 3847 return (fl); 3848 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3849 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3850 (w->pflags & HDA_ADC_PATH)) { 3851 conndev = w->wclass.pin.config & 3852 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3853 i = 0; 3854 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3855 if (ctl->enable == 0 || ctl->widget == NULL) 3856 continue; 3857 /* XXX This should be compressed! */ 3858 if (((ctl->widget->nid == pnid && ctl->index == index && 3859 (ctl->dir & HDA_CTL_IN)) || 3860 (ctl->widget->nid == pnid && pw != NULL && 3861 pw->type == 3862 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3863 (pw->nconns < 2 || pw->selconn == index || 3864 pw->selconn == -1) && 3865 (ctl->dir & HDA_CTL_OUT)) || 3866 (strategy == HDA_PARSE_DIRECT && 3867 ctl->widget->nid == w->nid)) && 3868 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3869 if (pw != NULL && pw->selconn == -1) 3870 pw->selconn = index; 3871 ossdev = 0; 3872 switch (conndev) { 3873 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3874 ossdev = SOUND_MIXER_MIC; 3875 break; 3876 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3877 ossdev = SOUND_MIXER_LINE; 3878 break; 3879 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3880 ossdev = SOUND_MIXER_CD; 3881 break; 3882 default: 3883 ossdev = 3884 hdac_audio_ctl_ossmixer_getnextdev( 3885 devinfo); 3886 if (ossdev < 0) 3887 ossdev = 0; 3888 break; 3889 } 3890 if (strategy == HDA_PARSE_MIXER) { 3891 fl |= SOUND_MASK_VOLUME; 3892 ctl->ossmask |= SOUND_MASK_VOLUME; 3893 } 3894 fl |= 1 << ossdev; 3895 ctl->ossmask |= 1 << ossdev; 3896 ctl->ossdev = ossdev; 3897 } 3898 } 3899 w->ctlflags |= fl; 3900 return (fl); 3901 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3902 i = 0; 3903 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3904 if (ctl->enable == 0 || ctl->widget == NULL) 3905 continue; 3906 /* XXX This should be compressed! */ 3907 if (((ctl->widget->nid == pnid && ctl->index == index && 3908 (ctl->dir & HDA_CTL_IN)) || 3909 (ctl->widget->nid == pnid && pw != NULL && 3910 pw->type == 3911 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3912 (pw->nconns < 2 || pw->selconn == index || 3913 pw->selconn == -1) && 3914 (ctl->dir & HDA_CTL_OUT)) || 3915 (strategy == HDA_PARSE_DIRECT && 3916 ctl->widget->nid == w->nid)) && 3917 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3918 if (pw != NULL && pw->selconn == -1) 3919 pw->selconn = index; 3920 fl |= SOUND_MASK_VOLUME; 3921 fl |= SOUND_MASK_SPEAKER; 3922 ctl->ossmask |= SOUND_MASK_VOLUME; 3923 ctl->ossmask |= SOUND_MASK_SPEAKER; 3924 ctl->ossdev = SOUND_MIXER_SPEAKER; 3925 } 3926 } 3927 w->ctlflags |= fl; 3928 return (fl); 3929 } 3930 return (0); 3931} 3932 3933static uint32_t 3934hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3935{ 3936 struct hdac_widget *w, *cw; 3937 struct hdac_audio_ctl *ctl; 3938 uint32_t fl; 3939 int i; 3940 3941 if (depth > HDA_PARSE_MAXDEPTH) 3942 return (0); 3943 3944 w = hdac_widget_get(devinfo, nid); 3945 if (w == NULL || w->enable == 0) 3946 return (0); 3947 /*if (!(w->pflags & HDA_ADC_PATH)) 3948 return (0); 3949 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3950 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3951 return (0);*/ 3952 i = 0; 3953 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3954 if (ctl->enable == 0 || ctl->widget == NULL) 3955 continue; 3956 if (ctl->widget->nid == nid) { 3957 ctl->ossmask |= SOUND_MASK_RECLEV; 3958 w->ctlflags |= SOUND_MASK_RECLEV; 3959 return (SOUND_MASK_RECLEV); 3960 } 3961 } 3962 for (i = 0; i < w->nconns; i++) { 3963 cw = hdac_widget_get(devinfo, w->conns[i]); 3964 if (cw == NULL || cw->enable == 0) 3965 continue; 3966 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3967 continue; 3968 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3969 if (fl != 0) { 3970 cw->ctlflags |= fl; 3971 w->ctlflags |= fl; 3972 return (fl); 3973 } 3974 } 3975 return (0); 3976} 3977 3978static int 3979hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3980{ 3981 struct hdac_widget *w, *cw; 3982 int i, child = 0; 3983 3984 if (depth > HDA_PARSE_MAXDEPTH) 3985 return (0); 3986 3987 w = hdac_widget_get(devinfo, nid); 3988 if (w == NULL || w->enable == 0) 3989 return (0); 3990 /*if (!(w->pflags & HDA_ADC_PATH)) 3991 return (0); 3992 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3993 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3994 return (0);*/ 3995 /* XXX weak! */ 3996 for (i = 0; i < w->nconns; i++) { 3997 cw = hdac_widget_get(devinfo, w->conns[i]); 3998 if (cw == NULL) 3999 continue; 4000 if (++child > 1) { 4001 w->pflags |= HDA_ADC_RECSEL; 4002 return (1); 4003 } 4004 } 4005 for (i = 0; i < w->nconns; i++) { 4006 if (hdac_audio_ctl_recsel_build(devinfo, 4007 w->conns[i], depth + 1) != 0) 4008 return (1); 4009 } 4010 return (0); 4011} 4012 4013static int 4014hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4015{ 4016 struct hdac_widget *w, *cw; 4017 int i, j, conndev, found_dac = 0; 4018 int strategy; 4019 4020 strategy = devinfo->function.audio.parsing_strategy; 4021 4022 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4023 w = hdac_widget_get(devinfo, i); 4024 if (w == NULL || w->enable == 0) 4025 continue; 4026 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4027 continue; 4028 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4029 continue; 4030 conndev = w->wclass.pin.config & 4031 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4032 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4033 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4034 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4035 continue; 4036 for (j = 0; j < w->nconns; j++) { 4037 cw = hdac_widget_get(devinfo, w->conns[j]); 4038 if (cw == NULL || cw->enable == 0) 4039 continue; 4040 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4041 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4042 cw->type == 4043 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4044 continue; 4045 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4046 != 0) { 4047 if (w->selconn == -1) 4048 w->selconn = j; 4049 w->pflags |= HDA_DAC_PATH; 4050 found_dac++; 4051 } 4052 } 4053 } 4054 4055 return (found_dac); 4056} 4057 4058static void 4059hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4060{ 4061 struct hdac_widget *w; 4062 struct hdac_audio_ctl *ctl; 4063 int i, j, dacs, strategy; 4064 4065 /* Construct DAC path */ 4066 strategy = HDA_PARSE_MIXER; 4067 devinfo->function.audio.parsing_strategy = strategy; 4068 HDA_BOOTVERBOSE( 4069 device_printf(devinfo->codec->sc->dev, 4070 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4071 HDA_WIDGET_PARSER_REV); 4072 ); 4073 dacs = hdac_audio_build_tree_strategy(devinfo); 4074 if (dacs == 0) { 4075 HDA_BOOTVERBOSE( 4076 device_printf(devinfo->codec->sc->dev, 4077 "HDA_DEBUG: HWiP: 0 DAC path found! " 4078 "Retrying parser " 4079 "using HDA_PARSE_DIRECT strategy.\n"); 4080 ); 4081 strategy = HDA_PARSE_DIRECT; 4082 devinfo->function.audio.parsing_strategy = strategy; 4083 dacs = hdac_audio_build_tree_strategy(devinfo); 4084 } 4085 4086 HDA_BOOTVERBOSE( 4087 device_printf(devinfo->codec->sc->dev, 4088 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4089 "strategy.\n", 4090 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4091 ); 4092 4093 /* Construct ADC path */ 4094 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4095 w = hdac_widget_get(devinfo, i); 4096 if (w == NULL || w->enable == 0) 4097 continue; 4098 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4099 continue; 4100 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4101 } 4102 4103 /* Output mixers */ 4104 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4105 w = hdac_widget_get(devinfo, i); 4106 if (w == NULL || w->enable == 0) 4107 continue; 4108 if ((strategy == HDA_PARSE_MIXER && 4109 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4110 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4111 && (w->pflags & HDA_DAC_PATH)) || 4112 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4113 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4114 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4115 w->nid, devinfo->startnode - 1, 0, 0); 4116 } else if (w->type == 4117 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4118 j = 0; 4119 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4120 NULL) { 4121 if (ctl->enable == 0 || ctl->widget == NULL) 4122 continue; 4123 if (ctl->widget->nid != w->nid) 4124 continue; 4125 ctl->ossmask |= SOUND_MASK_VOLUME; 4126 ctl->ossmask |= SOUND_MASK_SPEAKER; 4127 ctl->ossdev = SOUND_MIXER_SPEAKER; 4128 w->ctlflags |= SOUND_MASK_VOLUME; 4129 w->ctlflags |= SOUND_MASK_SPEAKER; 4130 } 4131 } 4132 } 4133 4134 /* Input mixers (rec) */ 4135 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4136 w = hdac_widget_get(devinfo, i); 4137 if (w == NULL || w->enable == 0) 4138 continue; 4139 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4140 w->pflags & HDA_ADC_PATH)) 4141 continue; 4142 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4143 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4144 } 4145} 4146 4147#define HDA_COMMIT_CONN (1 << 0) 4148#define HDA_COMMIT_CTRL (1 << 1) 4149#define HDA_COMMIT_EAPD (1 << 2) 4150#define HDA_COMMIT_GPIO (1 << 3) 4151#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4152 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4153 4154static void 4155hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4156{ 4157 struct hdac_softc *sc = devinfo->codec->sc; 4158 struct hdac_widget *w; 4159 nid_t cad; 4160 int i; 4161 4162 if (!(cfl & HDA_COMMIT_ALL)) 4163 return; 4164 4165 cad = devinfo->codec->cad; 4166 4167 if (cfl & HDA_COMMIT_GPIO) { 4168 uint32_t gdata, gmask, gdir; 4169 int commitgpio = 0; 4170 4171 gdata = 0; 4172 gmask = 0; 4173 gdir = 0; 4174 4175 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4176 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4177 0x7e7, 0), cad); 4178 4179 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4180 commitgpio = 1; 4181 else { 4182 for (i = 0; i < HDA_GPIO_MAX; i++) { 4183 if (!(devinfo->function.audio.quirks & 4184 (1 << i))) 4185 continue; 4186 if (commitgpio == 0) { 4187 commitgpio = 1; 4188 gdata = hdac_command(sc, 4189 HDA_CMD_GET_GPIO_DATA(cad, 4190 devinfo->nid), cad); 4191 gmask = hdac_command(sc, 4192 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4193 devinfo->nid), cad); 4194 gdir = hdac_command(sc, 4195 HDA_CMD_GET_GPIO_DIRECTION(cad, 4196 devinfo->nid), cad); 4197 HDA_BOOTVERBOSE( 4198 device_printf(sc->dev, 4199 "GPIO init: data=0x%08x " 4200 "mask=0x%08x dir=0x%08x\n", 4201 gdata, gmask, gdir); 4202 ); 4203 } 4204 gdata |= 1 << i; 4205 gmask |= 1 << i; 4206 gdir |= 1 << i; 4207 } 4208 } 4209 4210 if (commitgpio != 0) { 4211 HDA_BOOTVERBOSE( 4212 device_printf(sc->dev, 4213 "GPIO commit: data=0x%08x mask=0x%08x " 4214 "dir=0x%08x\n", 4215 gdata, gmask, gdir); 4216 ); 4217 hdac_command(sc, 4218 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4219 gmask), cad); 4220 hdac_command(sc, 4221 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4222 gdir), cad); 4223 hdac_command(sc, 4224 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4225 gdata), cad); 4226 } 4227 } 4228 4229 for (i = 0; i < devinfo->nodecnt; i++) { 4230 w = &devinfo->widget[i]; 4231 if (w == NULL || w->enable == 0) 4232 continue; 4233 if (cfl & HDA_COMMIT_CONN) { 4234 if (w->selconn == -1) 4235 w->selconn = 0; 4236 if (w->nconns > 0) 4237 hdac_widget_connection_select(w, w->selconn); 4238 } 4239 if ((cfl & HDA_COMMIT_CTRL) && 4240 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4241 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4242 (HDA_DAC_PATH | HDA_ADC_PATH)) 4243 device_printf(sc->dev, "WARNING: node %d " 4244 "participate both for DAC/ADC!\n", w->nid); 4245 if (w->pflags & HDA_DAC_PATH) { 4246 w->wclass.pin.ctrl &= 4247 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4248 if ((w->wclass.pin.config & 4249 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4250 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4251 w->wclass.pin.ctrl &= 4252 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4253 } else if (w->pflags & HDA_ADC_PATH) { 4254 w->wclass.pin.ctrl &= 4255 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4256 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4257 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4258 uint32_t pincap = w->wclass.pin.cap; 4259 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4260 w->wclass.pin.ctrl |= 4261 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4262 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4263 ); 4264 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4265 w->wclass.pin.ctrl |= 4266 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4267 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4268 ); 4269 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4270 w->wclass.pin.ctrl |= 4271 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4272 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4273 ); 4274 } 4275 } else 4276 w->wclass.pin.ctrl &= ~( 4277 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4278 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4279 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4280 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4281 hdac_command(sc, 4282 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4283 w->wclass.pin.ctrl), cad); 4284 } 4285 if ((cfl & HDA_COMMIT_EAPD) && 4286 w->param.eapdbtl != HDAC_INVALID) { 4287 uint32_t val; 4288 4289 val = w->param.eapdbtl; 4290 if (devinfo->function.audio.quirks & 4291 HDA_QUIRK_EAPDINV) 4292 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4293 hdac_command(sc, 4294 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4295 val), cad); 4296 4297 } 4298 DELAY(1000); 4299 } 4300} 4301 4302static void 4303hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4304{ 4305 struct hdac_softc *sc = devinfo->codec->sc; 4306 struct hdac_audio_ctl *ctl; 4307 int i; 4308 4309 devinfo->function.audio.mvol = 100 | (100 << 8); 4310 i = 0; 4311 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4312 if (ctl->enable == 0 || ctl->widget == NULL) { 4313 HDA_BOOTVERBOSE( 4314 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4315 i, (ctl->widget != NULL) ? 4316 ctl->widget->nid : -1); 4317 if (ctl->childwidget != NULL) 4318 printf(" childnid=%d", 4319 ctl->childwidget->nid); 4320 if (ctl->widget == NULL) 4321 printf(" NULL WIDGET!"); 4322 printf(" DISABLED\n"); 4323 ); 4324 continue; 4325 } 4326 HDA_BOOTVERBOSE( 4327 if (ctl->ossmask == 0) { 4328 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4329 i, ctl->widget->nid); 4330 if (ctl->childwidget != NULL) 4331 printf(" childnid=%d", 4332 ctl->childwidget->nid); 4333 printf(" Bind to NONE\n"); 4334 } 4335 ); 4336 if (ctl->step > 0) { 4337 ctl->ossval = (ctl->left * 100) / ctl->step; 4338 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4339 } else 4340 ctl->ossval = 0; 4341 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4342 ctl->left, ctl->right); 4343 } 4344} 4345 4346static int 4347hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4348{ 4349 struct hdac_chan *ch; 4350 struct hdac_widget *w; 4351 uint32_t cap, fmtcap, pcmcap, path; 4352 int i, type, ret, max; 4353 4354 if (dir == PCMDIR_PLAY) { 4355 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4356 ch = &devinfo->codec->sc->play; 4357 path = HDA_DAC_PATH; 4358 } else { 4359 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4360 ch = &devinfo->codec->sc->rec; 4361 path = HDA_ADC_PATH; 4362 } 4363 4364 ch->caps = hdac_caps; 4365 ch->caps.fmtlist = ch->fmtlist; 4366 ch->bit16 = 1; 4367 ch->bit32 = 0; 4368 ch->pcmrates[0] = 48000; 4369 ch->pcmrates[1] = 0; 4370 4371 ret = 0; 4372 fmtcap = devinfo->function.audio.supp_stream_formats; 4373 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4374 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4375 4376 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4377 w = hdac_widget_get(devinfo, i); 4378 if (w == NULL || w->enable == 0 || w->type != type || 4379 !(w->pflags & path)) 4380 continue; 4381 cap = w->param.widget_cap; 4382 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4383 continue;*/ 4384 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4385 continue; 4386 cap = w->param.supp_stream_formats; 4387 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4388 } 4389 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4390 }*/ 4391 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4392 continue; 4393 if (ret == 0) { 4394 fmtcap = w->param.supp_stream_formats; 4395 pcmcap = w->param.supp_pcm_size_rate; 4396 } else { 4397 fmtcap &= w->param.supp_stream_formats; 4398 pcmcap &= w->param.supp_pcm_size_rate; 4399 } 4400 ch->io[ret++] = i; 4401 } 4402 ch->io[ret] = -1; 4403 4404 ch->supp_stream_formats = fmtcap; 4405 ch->supp_pcm_size_rate = pcmcap; 4406 4407 /* 4408 * 8bit = 0 4409 * 16bit = 1 4410 * 20bit = 2 4411 * 24bit = 3 4412 * 32bit = 4 4413 */ 4414 if (ret > 0) { 4415 cap = pcmcap; 4416 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4417 ch->bit16 = 1; 4418 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4419 ch->bit16 = 0; 4420 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4421 ch->bit32 = 4; 4422 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4423 ch->bit32 = 3; 4424 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4425 ch->bit32 = 2; 4426 i = 0; 4427 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4428 ch->fmtlist[i++] = AFMT_S16_LE; 4429 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4430 if (ch->bit32 > 0) { 4431 if (!(devinfo->function.audio.quirks & 4432 HDA_QUIRK_FORCESTEREO)) 4433 ch->fmtlist[i++] = AFMT_S32_LE; 4434 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4435 } 4436 ch->fmtlist[i] = 0; 4437 i = 0; 4438 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4439 ch->pcmrates[i++] = 8000; 4440 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4441 ch->pcmrates[i++] = 11025; 4442 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4443 ch->pcmrates[i++] = 16000; 4444 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4445 ch->pcmrates[i++] = 22050; 4446 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4447 ch->pcmrates[i++] = 32000; 4448 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4449 ch->pcmrates[i++] = 44100; 4450 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4451 ch->pcmrates[i++] = 48000; 4452 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4453 ch->pcmrates[i++] = 88200; 4454 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4455 ch->pcmrates[i++] = 96000; 4456 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4457 ch->pcmrates[i++] = 176400; 4458 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4459 ch->pcmrates[i++] = 192000; 4460 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4461 ch->pcmrates[i] = 0; 4462 if (i > 0) { 4463 ch->caps.minspeed = ch->pcmrates[0]; 4464 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4465 } 4466 } 4467 4468 return (ret); 4469} 4470 4471static void 4472hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4473{ 4474 struct hdac_audio_ctl *ctl; 4475 struct hdac_softc *sc = devinfo->codec->sc; 4476 int i; 4477 uint32_t fl = 0; 4478 4479 4480 if (flag == 0) { 4481 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4482 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4483 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4484 } 4485 4486 i = 0; 4487 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4488 if (ctl->enable == 0 || ctl->widget == NULL || 4489 ctl->widget->enable == 0) 4490 continue; 4491 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4492 (flag != 0 && (ctl->ossmask & flag))) { 4493 if (banner != NULL) { 4494 device_printf(sc->dev, "\n"); 4495 device_printf(sc->dev, "%s\n", banner); 4496 } 4497 goto hdac_ctl_dump_it_all; 4498 } 4499 } 4500 4501 return; 4502 4503hdac_ctl_dump_it_all: 4504 i = 0; 4505 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4506 if (ctl->enable == 0 || ctl->widget == NULL || 4507 ctl->widget->enable == 0) 4508 continue; 4509 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4510 (flag != 0 && (ctl->ossmask & flag)))) 4511 continue; 4512 if (flag == 0) { 4513 device_printf(sc->dev, "\n"); 4514 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4515 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4516 } 4517 device_printf(sc->dev, " |\n"); 4518 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4519 ctl->widget->nid, ctl->index); 4520 if (ctl->childwidget != NULL) 4521 printf("(nid: %2d) ", ctl->childwidget->nid); 4522 else 4523 printf(" "); 4524 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4525 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4526 ctl->ossmask); 4527 } 4528} 4529 4530static void 4531hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4532{ 4533 uint32_t cap; 4534 4535 cap = fcap; 4536 if (cap != 0) { 4537 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4538 device_printf(sc->dev, " Format:"); 4539 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4540 printf(" AC3"); 4541 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4542 printf(" FLOAT32"); 4543 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4544 printf(" PCM"); 4545 printf("\n"); 4546 } 4547 cap = pcmcap; 4548 if (cap != 0) { 4549 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4550 device_printf(sc->dev, " PCM size:"); 4551 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4552 printf(" 8"); 4553 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4554 printf(" 16"); 4555 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4556 printf(" 20"); 4557 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4558 printf(" 24"); 4559 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4560 printf(" 32"); 4561 printf("\n"); 4562 device_printf(sc->dev, " PCM rate:"); 4563 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4564 printf(" 8"); 4565 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4566 printf(" 11"); 4567 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4568 printf(" 16"); 4569 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4570 printf(" 22"); 4571 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4572 printf(" 32"); 4573 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4574 printf(" 44"); 4575 printf(" 48"); 4576 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4577 printf(" 88"); 4578 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4579 printf(" 96"); 4580 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4581 printf(" 176"); 4582 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4583 printf(" 192"); 4584 printf("\n"); 4585 } 4586} 4587 4588static void 4589hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4590{ 4591 uint32_t pincap, wcap; 4592 4593 pincap = w->wclass.pin.cap; 4594 wcap = w->param.widget_cap; 4595 4596 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4597 device_printf(sc->dev, " "); 4598 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4599 printf(" ISC"); 4600 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4601 printf(" TRQD"); 4602 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4603 printf(" PDC"); 4604 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4605 printf(" HP"); 4606 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4607 printf(" OUT"); 4608 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4609 printf(" IN"); 4610 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4611 printf(" BAL"); 4612 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4613 printf(" VREF["); 4614 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4615 printf(" 50"); 4616 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4617 printf(" 80"); 4618 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4619 printf(" 100"); 4620 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4621 printf(" GROUND"); 4622 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4623 printf(" HIZ"); 4624 printf(" ]"); 4625 } 4626 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4627 printf(" EAPD"); 4628 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4629 printf(" : UNSOL"); 4630 printf("\n"); 4631 device_printf(sc->dev, " Pin config: 0x%08x\n", 4632 w->wclass.pin.config); 4633 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4634 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4635 printf(" HP"); 4636 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4637 printf(" IN"); 4638 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4639 printf(" OUT"); 4640 printf("\n"); 4641} 4642 4643static void 4644hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4645{ 4646 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4647 device_printf(sc->dev, " " 4648 "mute=%d step=%d size=%d offset=%d\n", 4649 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4650 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4651 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4652 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4653} 4654 4655static void 4656hdac_dump_nodes(struct hdac_devinfo *devinfo) 4657{ 4658 struct hdac_softc *sc = devinfo->codec->sc; 4659 struct hdac_widget *w, *cw; 4660 int i, j; 4661 4662 device_printf(sc->dev, "\n"); 4663 device_printf(sc->dev, "Default Parameter\n"); 4664 device_printf(sc->dev, "-----------------\n"); 4665 hdac_dump_audio_formats(sc, 4666 devinfo->function.audio.supp_stream_formats, 4667 devinfo->function.audio.supp_pcm_size_rate); 4668 device_printf(sc->dev, " IN amp: 0x%08x\n", 4669 devinfo->function.audio.inamp_cap); 4670 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4671 devinfo->function.audio.outamp_cap); 4672 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4673 w = hdac_widget_get(devinfo, i); 4674 if (w == NULL) { 4675 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4676 continue; 4677 } 4678 device_printf(sc->dev, "\n"); 4679 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4680 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4681 "DIGITAL" : "ANALOG", 4682 (w->enable == 0) ? " [DISABLED]" : ""); 4683 device_printf(sc->dev, " name: %s\n", w->name); 4684 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4685 w->param.widget_cap); 4686 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4687 w->pflags); 4688 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4689 w->ctlflags); 4690 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4691 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4692 hdac_dump_audio_formats(sc, 4693 w->param.supp_stream_formats, 4694 w->param.supp_pcm_size_rate); 4695 } else if (w->type == 4696 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4697 hdac_dump_pin(sc, w); 4698 if (w->param.eapdbtl != HDAC_INVALID) 4699 device_printf(sc->dev, " EAPD: 0x%08x\n", 4700 w->param.eapdbtl); 4701 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4702 w->param.outamp_cap != 0) 4703 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4704 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4705 w->param.inamp_cap != 0) 4706 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4707 device_printf(sc->dev, " connections: %d\n", w->nconns); 4708 for (j = 0; j < w->nconns; j++) { 4709 cw = hdac_widget_get(devinfo, w->conns[j]); 4710 device_printf(sc->dev, " |\n"); 4711 device_printf(sc->dev, " + <- nid=%d [%s]", 4712 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4713 if (cw == NULL) 4714 printf(" [UNKNOWN]"); 4715 else if (cw->enable == 0) 4716 printf(" [DISABLED]"); 4717 if (w->nconns > 1 && w->selconn == j && w->type != 4718 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4719 printf(" (selected)"); 4720 printf("\n"); 4721 } 4722 } 4723 4724} 4725 4726static int 4727hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4728{ 4729 struct hdac_widget *w, *cw; 4730 struct hdac_softc *sc = devinfo->codec->sc; 4731 int i; 4732 4733 if (depth > HDA_PARSE_MAXDEPTH) 4734 return (0); 4735 4736 w = hdac_widget_get(devinfo, nid); 4737 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4738 return (0); 4739 4740 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4741 device_printf(sc->dev, "\n"); 4742 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4743 device_printf(sc->dev, " ^\n"); 4744 device_printf(sc->dev, " |\n"); 4745 device_printf(sc->dev, " +-----<------+\n"); 4746 } else { 4747 device_printf(sc->dev, " ^\n"); 4748 device_printf(sc->dev, " |\n"); 4749 device_printf(sc->dev, " "); 4750 printf(" nid=%d [%s]\n", w->nid, w->name); 4751 } 4752 4753 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4754 return (1); 4755 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4756 for (i = 0; i < w->nconns; i++) { 4757 cw = hdac_widget_get(devinfo, w->conns[i]); 4758 if (cw == NULL || cw->enable == 0 || cw->type == 4759 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4760 continue; 4761 if (hdac_dump_dac_internal(devinfo, cw->nid, 4762 depth + 1) != 0) 4763 return (1); 4764 } 4765 } else if ((w->type == 4766 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4767 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4768 w->selconn > -1 && w->selconn < w->nconns) { 4769 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4770 depth + 1) != 0) 4771 return (1); 4772 } 4773 4774 return (0); 4775} 4776 4777static void 4778hdac_dump_dac(struct hdac_devinfo *devinfo) 4779{ 4780 struct hdac_widget *w; 4781 struct hdac_softc *sc = devinfo->codec->sc; 4782 int i, printed = 0; 4783 4784 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4785 w = hdac_widget_get(devinfo, i); 4786 if (w == NULL || w->enable == 0) 4787 continue; 4788 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4789 !(w->pflags & HDA_DAC_PATH)) 4790 continue; 4791 if (printed == 0) { 4792 printed = 1; 4793 device_printf(sc->dev, "\n"); 4794 device_printf(sc->dev, "Playback path:\n"); 4795 } 4796 hdac_dump_dac_internal(devinfo, w->nid, 0); 4797 } 4798} 4799 4800static void 4801hdac_dump_adc(struct hdac_devinfo *devinfo) 4802{ 4803 struct hdac_widget *w, *cw; 4804 struct hdac_softc *sc = devinfo->codec->sc; 4805 int i, j; 4806 int printed = 0; 4807 char ossdevs[256]; 4808 4809 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4810 w = hdac_widget_get(devinfo, i); 4811 if (w == NULL || w->enable == 0) 4812 continue; 4813 if (!(w->pflags & HDA_ADC_RECSEL)) 4814 continue; 4815 if (printed == 0) { 4816 printed = 1; 4817 device_printf(sc->dev, "\n"); 4818 device_printf(sc->dev, "Recording sources:\n"); 4819 } 4820 device_printf(sc->dev, "\n"); 4821 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4822 for (j = 0; j < w->nconns; j++) { 4823 cw = hdac_widget_get(devinfo, w->conns[j]); 4824 if (cw == NULL || cw->enable == 0) 4825 continue; 4826 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4827 ossdevs, sizeof(ossdevs)); 4828 device_printf(sc->dev, " |\n"); 4829 device_printf(sc->dev, " + <- nid=%d [%s]", 4830 cw->nid, cw->name); 4831 if (strlen(ossdevs) > 0) { 4832 printf(" [recsrc: %s]", ossdevs); 4833 } 4834 printf("\n"); 4835 } 4836 } 4837} 4838 4839static void 4840hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4841{ 4842 nid_t *nids; 4843 4844 if (pcnt > 0) { 4845 device_printf(sc->dev, "\n"); 4846 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4847 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4848 sc->play.supp_pcm_size_rate); 4849 device_printf(sc->dev, " DAC:"); 4850 for (nids = sc->play.io; *nids != -1; nids++) 4851 printf(" %d", *nids); 4852 printf("\n"); 4853 } 4854 4855 if (rcnt > 0) { 4856 device_printf(sc->dev, "\n"); 4857 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4858 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4859 sc->rec.supp_pcm_size_rate); 4860 device_printf(sc->dev, " ADC:"); 4861 for (nids = sc->rec.io; *nids != -1; nids++) 4862 printf(" %d", *nids); 4863 printf("\n"); 4864 } 4865} 4866 4867static void 4868hdac_release_resources(struct hdac_softc *sc) 4869{ 4870 struct hdac_devinfo *devinfo = NULL; 4871 device_t *devlist = NULL; 4872 int i, devcount; 4873 4874 if (sc == NULL) 4875 return; 4876 4877 hdac_lock(sc); 4878 if (sc->polling != 0) 4879 callout_stop(&sc->poll_hdac); 4880 hdac_reset(sc); 4881 hdac_unlock(sc); 4882 snd_mtxfree(sc->lock); 4883 4884 device_get_children(sc->dev, &devlist, &devcount); 4885 for (i = 0; devlist != NULL && i < devcount; i++) { 4886 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4887 if (devinfo == NULL) 4888 continue; 4889 if (devinfo->widget != NULL) 4890 free(devinfo->widget, M_HDAC); 4891 if (devinfo->node_type == 4892 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4893 devinfo->function.audio.ctl != NULL) 4894 free(devinfo->function.audio.ctl, M_HDAC); 4895 free(devinfo, M_HDAC); 4896 device_delete_child(sc->dev, devlist[i]); 4897 } 4898 if (devlist != NULL) 4899 free(devlist, M_TEMP); 4900 4901 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4902 if (sc->codecs[i] != NULL) 4903 free(sc->codecs[i], M_HDAC); 4904 sc->codecs[i] = NULL; 4905 } 4906 4907 hdac_dma_free(&sc->rirb_dma); 4908 hdac_dma_free(&sc->corb_dma); 4909 if (sc->play.blkcnt > 0) 4910 hdac_dma_free(&sc->play.bdl_dma); 4911 if (sc->rec.blkcnt > 0) 4912 hdac_dma_free(&sc->rec.bdl_dma); 4913 hdac_irq_free(sc); 4914 hdac_mem_free(sc); 4915 free(sc, M_DEVBUF); 4916 4917} 4918 4919/* This function surely going to make its way into upper level someday. */ 4920static void 4921hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4922{ 4923 const char *res = NULL; 4924 int i = 0, j, k, len, inv; 4925 4926 if (on != NULL) 4927 *on = 0; 4928 if (off != NULL) 4929 *off = 0; 4930 if (sc == NULL) 4931 return; 4932 if (resource_string_value(device_get_name(sc->dev), 4933 device_get_unit(sc->dev), "config", &res) != 0) 4934 return; 4935 if (!(res != NULL && strlen(res) > 0)) 4936 return; 4937 HDA_BOOTVERBOSE( 4938 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4939 ); 4940 for (;;) { 4941 while (res[i] != '\0' && 4942 (res[i] == ',' || isspace(res[i]) != 0)) 4943 i++; 4944 if (res[i] == '\0') { 4945 HDA_BOOTVERBOSE( 4946 printf("\n"); 4947 ); 4948 return; 4949 } 4950 j = i; 4951 while (res[j] != '\0' && 4952 !(res[j] == ',' || isspace(res[j]) != 0)) 4953 j++; 4954 len = j - i; 4955 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4956 inv = 2; 4957 else 4958 inv = 0; 4959 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4960 if (strncmp(res + i + inv, 4961 hdac_quirks_tab[k].key, len - inv) != 0) 4962 continue; 4963 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4964 break; 4965 HDA_BOOTVERBOSE( 4966 printf(" %s%s", (inv != 0) ? "no" : "", 4967 hdac_quirks_tab[k].key); 4968 ); 4969 if (inv == 0 && on != NULL) 4970 *on |= hdac_quirks_tab[k].value; 4971 else if (inv != 0 && off != NULL) 4972 *off |= hdac_quirks_tab[k].value; 4973 break; 4974 } 4975 i = j; 4976 } 4977} 4978 4979#ifdef SND_DYNSYSCTL 4980static int 4981sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4982{ 4983 struct hdac_softc *sc; 4984 struct hdac_devinfo *devinfo; 4985 device_t dev; 4986 uint32_t ctl; 4987 int err, val; 4988 4989 dev = oidp->oid_arg1; 4990 devinfo = pcm_getdevinfo(dev); 4991 if (devinfo == NULL || devinfo->codec == NULL || 4992 devinfo->codec->sc == NULL) 4993 return (EINVAL); 4994 sc = devinfo->codec->sc; 4995 hdac_lock(sc); 4996 val = sc->polling; 4997 hdac_unlock(sc); 4998 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4999 5000 if (err || req->newptr == NULL) 5001 return (err); 5002 if (val < 0 || val > 1) 5003 return (EINVAL); 5004 5005 hdac_lock(sc); 5006 if (val != sc->polling) { 5007 if (hda_chan_active(sc) != 0) 5008 err = EBUSY; 5009 else if (val == 0) { 5010 callout_stop(&sc->poll_hdac); 5011 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5012 sc->rirb_size / 2); 5013 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5014 ctl |= HDAC_RIRBCTL_RINTCTL; 5015 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5016 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5017 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5018 sc->polling = 0; 5019 DELAY(1000); 5020 } else { 5021 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5022 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5023 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5024 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5025 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5026 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5027 sc); 5028 sc->polling = 1; 5029 DELAY(1000); 5030 } 5031 } 5032 hdac_unlock(sc); 5033 5034 return (err); 5035} 5036#endif 5037 5038static void 5039hdac_attach2(void *arg) 5040{ 5041 struct hdac_softc *sc; 5042 struct hdac_widget *w; 5043 struct hdac_audio_ctl *ctl; 5044 uint32_t quirks_on, quirks_off; 5045 int pcnt, rcnt; 5046 int i; 5047 char status[SND_STATUSLEN]; 5048 device_t *devlist = NULL; 5049 int devcount; 5050 struct hdac_devinfo *devinfo = NULL; 5051 5052 sc = (struct hdac_softc *)arg; 5053 5054 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5055 5056 HDA_BOOTVERBOSE( 5057 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5058 quirks_on, quirks_off); 5059 ); 5060 5061 hdac_lock(sc); 5062 5063 /* Remove ourselves from the config hooks */ 5064 if (sc->intrhook.ich_func != NULL) { 5065 config_intrhook_disestablish(&sc->intrhook); 5066 sc->intrhook.ich_func = NULL; 5067 } 5068 5069 /* Start the corb and rirb engines */ 5070 HDA_BOOTVERBOSE( 5071 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5072 ); 5073 hdac_corb_start(sc); 5074 HDA_BOOTVERBOSE( 5075 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5076 ); 5077 hdac_rirb_start(sc); 5078 5079 HDA_BOOTVERBOSE( 5080 device_printf(sc->dev, 5081 "HDA_DEBUG: Enabling controller interrupt...\n"); 5082 ); 5083 if (sc->polling == 0) 5084 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5085 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5086 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5087 HDAC_GCTL_UNSOL); 5088 5089 DELAY(1000); 5090 5091 HDA_BOOTVERBOSE( 5092 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5093 ); 5094 hdac_scan_codecs(sc); 5095 5096 device_get_children(sc->dev, &devlist, &devcount); 5097 for (i = 0; devlist != NULL && i < devcount; i++) { 5098 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5099 if (devinfo != NULL && devinfo->node_type == 5100 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5101 break; 5102 } else 5103 devinfo = NULL; 5104 } 5105 if (devlist != NULL) 5106 free(devlist, M_TEMP); 5107 5108 if (devinfo == NULL) { 5109 hdac_unlock(sc); 5110 device_printf(sc->dev, "Audio Function Group not found!\n"); 5111 hdac_release_resources(sc); 5112 return; 5113 } 5114 5115 HDA_BOOTVERBOSE( 5116 device_printf(sc->dev, 5117 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5118 devinfo->nid, devinfo->codec->cad); 5119 ); 5120 hdac_audio_parse(devinfo); 5121 HDA_BOOTVERBOSE( 5122 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5123 ); 5124 hdac_audio_ctl_parse(devinfo); 5125 HDA_BOOTVERBOSE( 5126 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5127 ); 5128 hdac_vendor_patch_parse(devinfo); 5129 if (quirks_on != 0) 5130 devinfo->function.audio.quirks |= quirks_on; 5131 if (quirks_off != 0) 5132 devinfo->function.audio.quirks &= ~quirks_off; 5133 5134 /* XXX Disable all DIGITAL path. */ 5135 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5136 w = hdac_widget_get(devinfo, i); 5137 if (w == NULL) 5138 continue; 5139 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5140 w->enable = 0; 5141 continue; 5142 } 5143 /* XXX Disable useless pin ? */ 5144 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5145 (w->wclass.pin.config & 5146 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5147 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5148 w->enable = 0; 5149 } 5150 i = 0; 5151 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5152 if (ctl->widget == NULL) 5153 continue; 5154 w = ctl->widget; 5155 if (w->enable == 0) 5156 ctl->enable = 0; 5157 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5158 ctl->enable = 0; 5159 w = ctl->childwidget; 5160 if (w == NULL) 5161 continue; 5162 if (w->enable == 0 || 5163 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5164 ctl->enable = 0; 5165 } 5166 5167 HDA_BOOTVERBOSE( 5168 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5169 ); 5170 hdac_audio_build_tree(devinfo); 5171 5172 HDA_BOOTVERBOSE( 5173 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5174 ); 5175 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5176 HDA_BOOTVERBOSE( 5177 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5178 ); 5179 hdac_audio_ctl_commit(devinfo); 5180 5181 HDA_BOOTVERBOSE( 5182 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5183 ); 5184 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5185 HDA_BOOTVERBOSE( 5186 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5187 ); 5188 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5189 5190 hdac_unlock(sc); 5191 HDA_BOOTVERBOSE( 5192 device_printf(sc->dev, 5193 "HDA_DEBUG: OSS mixer initialization...\n"); 5194 ); 5195 5196 /* 5197 * There is no point of return after this. If the driver failed, 5198 * so be it. Let the detach procedure do all the cleanup. 5199 */ 5200 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5201 device_printf(sc->dev, "Can't register mixer\n"); 5202 5203 if (pcnt > 0) 5204 pcnt = 1; 5205 if (rcnt > 0) 5206 rcnt = 1; 5207 5208 HDA_BOOTVERBOSE( 5209 device_printf(sc->dev, 5210 "HDA_DEBUG: Registering PCM channels...\n"); 5211 ); 5212 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5213 device_printf(sc->dev, "Can't register PCM\n"); 5214 5215 sc->registered++; 5216 5217 for (i = 0; i < pcnt; i++) 5218 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5219 for (i = 0; i < rcnt; i++) 5220 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5221 5222#ifdef SND_DYNSYSCTL 5223 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5224 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5225 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5226 sysctl_hdac_polling, "I", "Enable polling mode"); 5227#endif 5228 5229 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5230 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5231 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5232 pcm_setstatus(sc->dev, status); 5233 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5234 HDA_BOOTVERBOSE( 5235 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5236 hdac_codec_id(devinfo)); 5237 ); 5238 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5239 HDA_DRV_TEST_REV); 5240 5241 HDA_BOOTVERBOSE( 5242 if (devinfo->function.audio.quirks != 0) { 5243 device_printf(sc->dev, "\n"); 5244 device_printf(sc->dev, "HDA config/quirks:"); 5245 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5246 if (devinfo->function.audio.quirks & 5247 hdac_quirks_tab[i].value) 5248 printf(" %s", hdac_quirks_tab[i].key); 5249 } 5250 printf("\n"); 5251 } 5252 device_printf(sc->dev, "\n"); 5253 device_printf(sc->dev, "+-------------------+\n"); 5254 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5255 device_printf(sc->dev, "+-------------------+\n"); 5256 hdac_dump_nodes(devinfo); 5257 device_printf(sc->dev, "\n"); 5258 device_printf(sc->dev, "+------------------------+\n"); 5259 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5260 device_printf(sc->dev, "+------------------------+\n"); 5261 device_printf(sc->dev, "\n"); 5262 i = 0; 5263 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5264 device_printf(sc->dev, "%3d: nid=%d", i, 5265 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5266 if (ctl->childwidget != NULL) 5267 printf(" cnid=%d", ctl->childwidget->nid); 5268 printf(" dir=0x%x index=%d " 5269 "ossmask=0x%08x ossdev=%d%s\n", 5270 ctl->dir, ctl->index, 5271 ctl->ossmask, ctl->ossdev, 5272 (ctl->enable == 0) ? " [DISABLED]" : ""); 5273 } 5274 device_printf(sc->dev, "\n"); 5275 device_printf(sc->dev, "+-----------------------------------+\n"); 5276 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5277 device_printf(sc->dev, "+-----------------------------------+\n"); 5278 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5279 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5280 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5281 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5282 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5283 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5284 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5285 hdac_dump_ctls(devinfo, NULL, 0); 5286 hdac_dump_dac(devinfo); 5287 hdac_dump_adc(devinfo); 5288 device_printf(sc->dev, "\n"); 5289 device_printf(sc->dev, "+--------------------------------------+\n"); 5290 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5291 device_printf(sc->dev, "+--------------------------------------+\n"); 5292 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5293 ); 5294 5295 if (sc->polling != 0) { 5296 hdac_lock(sc); 5297 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5298 hdac_unlock(sc); 5299 } 5300} 5301 5302/**************************************************************************** 5303 * int hdac_detach(device_t) 5304 * 5305 * Detach and free up resources utilized by the hdac device. 5306 ****************************************************************************/ 5307static int 5308hdac_detach(device_t dev) 5309{ 5310 struct hdac_softc *sc = NULL; 5311 struct hdac_devinfo *devinfo = NULL; 5312 int err; 5313 5314 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5315 if (devinfo != NULL && devinfo->codec != NULL) 5316 sc = devinfo->codec->sc; 5317 if (sc == NULL) 5318 return (0); 5319 5320 if (sc->registered > 0) { 5321 err = pcm_unregister(dev); 5322 if (err != 0) 5323 return (err); 5324 } 5325 5326 hdac_release_resources(sc); 5327 5328 return (0); 5329} 5330 5331static device_method_t hdac_methods[] = { 5332 /* device interface */ 5333 DEVMETHOD(device_probe, hdac_probe), 5334 DEVMETHOD(device_attach, hdac_attach), 5335 DEVMETHOD(device_detach, hdac_detach), 5336 { 0, 0 } 5337}; 5338 5339static driver_t hdac_driver = { 5340 "pcm", 5341 hdac_methods, 5342 PCM_SOFTC_SIZE, 5343}; 5344 5345DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5346MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5347MODULE_VERSION(snd_hda, 1); 5348