hdac.c revision 165305
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061210_0037" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 165305 2006-12-17 15:19:33Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 172#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 173/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 174#define HP_NX6325_SUBVENDORX 0x103c30b0 175 176/* Dell */ 177#define DELL_VENDORID 0x1028 178#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 179#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 180#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 181 182/* Clevo */ 183#define CLEVO_VENDORID 0x1558 184#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 185#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 186 187/* Acer */ 188#define ACER_VENDORID 0x1025 189#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 190 191/* Asus */ 192#define ASUS_VENDORID 0x1043 193#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 194#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 195#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 196#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 197#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 198#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 199 200/* IBM / Lenovo */ 201#define IBM_VENDORID 0x1014 202#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 203#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 204 205/* Lenovo */ 206#define LENOVO_VENDORID 0x17aa 207#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 208#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 209 210/* Samsung */ 211#define SAMSUNG_VENDORID 0x144d 212#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 213#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 214 215/* Medion ? */ 216#define MEDION_VENDORID 0x161f 217#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 218#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 219 220/* 221 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 222 * instead of their own, which is beyond my comprehension 223 * (see HDA_CODEC_STAC9221 below). 224 */ 225#define APPLE_INTEL_MAC 0x76808384 226 227/* LG Electronics */ 228#define LG_VENDORID 0x1854 229#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 230#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 231 232/* Misc constants.. */ 233#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 234#define HDA_AMP_MUTE_NONE (0) 235#define HDA_AMP_MUTE_LEFT (1 << 0) 236#define HDA_AMP_MUTE_RIGHT (1 << 1) 237#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 238 239#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 240#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 241 242#define HDA_DAC_PATH (1 << 0) 243#define HDA_ADC_PATH (1 << 1) 244#define HDA_ADC_RECSEL (1 << 2) 245 246#define HDA_CTL_OUT (1 << 0) 247#define HDA_CTL_IN (1 << 1) 248#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 249 250#define HDA_GPIO_MAX 15 251/* 0 - 14 = GPIO */ 252#define HDA_QUIRK_GPIO0 (1 << 0) 253#define HDA_QUIRK_GPIO1 (1 << 1) 254#define HDA_QUIRK_GPIO2 (1 << 2) 255#define HDA_QUIRK_GPIOFLUSH (1 << 15) 256#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 257#define HDA_QUIRK_FIXEDRATE (1 << 17) 258#define HDA_QUIRK_FORCESTEREO (1 << 18) 259#define HDA_QUIRK_EAPDINV (1 << 19) 260#define HDA_QUIRK_VREF (1 << 20) 261 262static const struct { 263 char *key; 264 uint32_t value; 265} hdac_quirks_tab[] = { 266 { "gpio0", HDA_QUIRK_GPIO0 }, 267 { "gpio1", HDA_QUIRK_GPIO1 }, 268 { "gpio2", HDA_QUIRK_GPIO2 }, 269 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 270 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 271 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 272 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 273 { "eapdinv", HDA_QUIRK_EAPDINV }, 274 { "vref", HDA_QUIRK_VREF }, 275}; 276#define HDAC_QUIRKS_TAB_LEN \ 277 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 278 279#define HDA_BDL_MIN 2 280#define HDA_BDL_MAX 256 281#define HDA_BDL_DEFAULT HDA_BDL_MIN 282 283#define HDA_BUFSZ_MIN 4096 284#define HDA_BUFSZ_MAX 65536 285#define HDA_BUFSZ_DEFAULT 16384 286 287#define HDA_PARSE_MAXDEPTH 10 288 289#define HDAC_UNSOLTAG_EVENT_HP 0x00 290 291MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 292 293enum { 294 HDA_PARSE_MIXER, 295 HDA_PARSE_DIRECT 296}; 297 298/* Default */ 299static uint32_t hdac_fmt[] = { 300 AFMT_STEREO | AFMT_S16_LE, 301 0 302}; 303 304static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 305 306static const struct { 307 uint32_t model; 308 char *desc; 309} hdac_devices[] = { 310 { HDA_INTEL_82801F, "Intel 82801F" }, 311 { HDA_INTEL_82801G, "Intel 82801G" }, 312 { HDA_INTEL_82801H, "Intel 82801H" }, 313 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 314 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 315 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 316 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 317 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 318 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 319 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 320 { HDA_ATI_SB450, "ATI SB450" }, 321 { HDA_ATI_SB600, "ATI SB600" }, 322 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 323 { HDA_SIS_966, "SiS 966" }, 324 /* Unknown */ 325 { HDA_INTEL_ALL, "Intel (Unknown)" }, 326 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 327 { HDA_ATI_ALL, "ATI (Unknown)" }, 328 { HDA_VIA_ALL, "VIA (Unknown)" }, 329 { HDA_SIS_ALL, "SiS (Unknown)" }, 330}; 331#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 332 333static const struct { 334 uint32_t rate; 335 int valid; 336 uint16_t base; 337 uint16_t mul; 338 uint16_t div; 339} hda_rate_tab[] = { 340 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 341 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 342 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 343 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 344 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 345 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 346 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 347 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 348 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 349 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 350 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 351 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 352 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 353 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 354 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 355 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 356 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 357 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 358 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 359 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 360 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 361 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 362 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 363 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 364 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 365 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 366 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 367 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 368 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 369 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 370 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 371 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 372 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 373 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 374 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 375}; 376#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 377 378/* All codecs you can eat... */ 379#define HDA_CODEC_CONSTRUCT(vendor, id) \ 380 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 381 382/* Realtek */ 383#define REALTEK_VENDORID 0x10ec 384#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 385#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 386#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 387#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 388#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 389#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 390#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 391 392/* Analog Device */ 393#define ANALOGDEVICE_VENDORID 0x11d4 394#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 395#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 396#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 397#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 398 399/* CMedia */ 400#define CMEDIA_VENDORID 0x434d 401#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 402#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 403 404/* Sigmatel */ 405#define SIGMATEL_VENDORID 0x8384 406#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 407#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 408#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 409#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 410#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 411#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 412 413/* 414 * Conexant 415 * 416 * Ok, the truth is, I don't have any idea at all whether 417 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 418 * place that tell me it is "Venice" is from its Windows driver INF. 419 * 420 * Venice - CX????? 421 * Waikiki - CX20551-22 422 */ 423#define CONEXANT_VENDORID 0x14f1 424#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 425#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 426#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 427 428 429/* Codecs */ 430static const struct { 431 uint32_t id; 432 char *name; 433} hdac_codecs[] = { 434 { HDA_CODEC_ALC260, "Realtek ALC260" }, 435 { HDA_CODEC_ALC861, "Realtek ALC861" }, 436 { HDA_CODEC_ALC880, "Realtek ALC880" }, 437 { HDA_CODEC_ALC882, "Realtek ALC882" }, 438 { HDA_CODEC_ALC883, "Realtek ALC883" }, 439 { HDA_CODEC_ALC888, "Realtek ALC888" }, 440 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 441 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 442 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 443 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 444 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 445 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 446 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 447 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 448 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 449 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 450 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 451 /* Unknown codec */ 452 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 453 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 454 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 455 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 456 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 457}; 458#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 459 460enum { 461 HDAC_HP_SWITCH_CTL, 462 HDAC_HP_SWITCH_CTRL 463}; 464 465static const struct { 466 uint32_t model; 467 uint32_t id; 468 int type; 469 int inverted; 470 nid_t hpnid; 471 nid_t spkrnid[8]; 472 nid_t eapdnid; 473} hdac_hp_switch[] = { 474 /* Specific OEM models */ 475 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 476 17, { 16, -1 }, 16 }, 477 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 478 6, { 5, -1 }, 5 }, 479 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 480 6, { 5, -1 }, 5 }, 481 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 482 6, { 5, -1 }, 5 }, 483 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 484 13, { 14, -1 }, -1 }, 485 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 486 13, { 14, -1 }, -1 }, 487 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 488 10, { 13, -1 }, -1 }, 489 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 490 26, { 27, -1 }, -1 }, 491 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 492 27, { 20, -1 }, -1 }, 493 /* 494 * All models that at least come from the same vendor with 495 * simmilar codec. 496 */ 497 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 498 17, { 16, -1 }, 16 }, 499 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 500 6, { 5, -1 }, 5 }, 501 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 502 13, { 14, -1 }, -1 }, 503 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 504 26, { 27, -1 }, -1 }, 505}; 506#define HDAC_HP_SWITCH_LEN \ 507 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 508 509static const struct { 510 uint32_t model; 511 uint32_t id; 512 nid_t eapdnid; 513 int hp_switch; 514} hdac_eapd_switch[] = { 515 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 516 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 517 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 518}; 519#define HDAC_EAPD_SWITCH_LEN \ 520 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 521 522/**************************************************************************** 523 * Function prototypes 524 ****************************************************************************/ 525static void hdac_intr_handler(void *); 526static int hdac_reset(struct hdac_softc *); 527static int hdac_get_capabilities(struct hdac_softc *); 528static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 529static int hdac_dma_alloc(struct hdac_softc *, 530 struct hdac_dma *, bus_size_t); 531static void hdac_dma_free(struct hdac_dma *); 532static int hdac_mem_alloc(struct hdac_softc *); 533static void hdac_mem_free(struct hdac_softc *); 534static int hdac_irq_alloc(struct hdac_softc *); 535static void hdac_irq_free(struct hdac_softc *); 536static void hdac_corb_init(struct hdac_softc *); 537static void hdac_rirb_init(struct hdac_softc *); 538static void hdac_corb_start(struct hdac_softc *); 539static void hdac_rirb_start(struct hdac_softc *); 540static void hdac_scan_codecs(struct hdac_softc *); 541static int hdac_probe_codec(struct hdac_codec *); 542static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 543static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 544 545static void hdac_attach2(void *); 546 547static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 548 uint32_t, int); 549static void hdac_command_send_internal(struct hdac_softc *, 550 struct hdac_command_list *, int); 551 552static int hdac_probe(device_t); 553static int hdac_attach(device_t); 554static int hdac_detach(device_t); 555static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 556static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 557 uint32_t, int, int); 558static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 559 nid_t, int, int); 560static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 561 nid_t, nid_t, int, int, int, int, int, int); 562static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 563static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 564 565static int hdac_rirb_flush(struct hdac_softc *sc); 566static int hdac_unsolq_flush(struct hdac_softc *sc); 567 568#define hdac_command(a1, a2, a3) \ 569 hdac_command_sendone_internal(a1, a2, a3) 570 571#define hdac_codec_id(d) \ 572 ((uint32_t)((d == NULL) ? 0x00000000 : \ 573 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 574 ((uint32_t)(d)->device_id & 0x0000ffff)))) 575 576static char * 577hdac_codec_name(struct hdac_devinfo *devinfo) 578{ 579 uint32_t id; 580 int i; 581 582 id = hdac_codec_id(devinfo); 583 584 for (i = 0; i < HDAC_CODECS_LEN; i++) { 585 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 586 return (hdac_codecs[i].name); 587 } 588 589 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 590} 591 592static char * 593hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 594{ 595 static char *ossname[] = SOUND_DEVICE_NAMES; 596 static char *unknown = "???"; 597 int i; 598 599 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 600 if (devmask & (1 << i)) 601 return (ossname[i]); 602 } 603 return (unknown); 604} 605 606static void 607hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 608{ 609 static char *ossname[] = SOUND_DEVICE_NAMES; 610 int i, first = 1; 611 612 bzero(buf, len); 613 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 614 if (mask & (1 << i)) { 615 if (first == 0) 616 strlcat(buf, ", ", len); 617 strlcat(buf, ossname[i], len); 618 first = 0; 619 } 620 } 621} 622 623static struct hdac_audio_ctl * 624hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 625{ 626 if (devinfo == NULL || 627 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 628 index == NULL || devinfo->function.audio.ctl == NULL || 629 devinfo->function.audio.ctlcnt < 1 || 630 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 631 return (NULL); 632 return (&devinfo->function.audio.ctl[(*index)++]); 633} 634 635static struct hdac_audio_ctl * 636hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 637 int index, int cnt) 638{ 639 struct hdac_audio_ctl *ctl, *retctl = NULL; 640 int i, at, atindex, found = 0; 641 642 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 643 return (NULL); 644 645 at = cnt; 646 if (at == 0) 647 at = 1; 648 else if (at < 0) 649 at = -1; 650 atindex = index; 651 if (atindex < 0) 652 atindex = -1; 653 654 i = 0; 655 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 656 if (ctl->enable == 0 || ctl->widget == NULL) 657 continue; 658 if (!(ctl->widget->nid == nid && (atindex == -1 || 659 ctl->index == atindex))) 660 continue; 661 found++; 662 if (found == cnt) 663 return (ctl); 664 retctl = ctl; 665 } 666 667 return ((at == -1) ? retctl : NULL); 668} 669 670static void 671hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 672{ 673 struct hdac_softc *sc; 674 struct hdac_widget *w; 675 struct hdac_audio_ctl *ctl; 676 uint32_t id, res; 677 int i = 0, j, forcemute; 678 nid_t cad; 679 680 if (devinfo == NULL || devinfo->codec == NULL || 681 devinfo->codec->sc == NULL) 682 return; 683 684 sc = devinfo->codec->sc; 685 cad = devinfo->codec->cad; 686 id = hdac_codec_id(devinfo); 687 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 688 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 689 sc->pci_subvendor) && 690 hdac_hp_switch[i].id == id) 691 break; 692 } 693 694 if (i >= HDAC_HP_SWITCH_LEN) 695 return; 696 697 forcemute = 0; 698 if (hdac_hp_switch[i].eapdnid != -1) { 699 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 700 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 701 forcemute = (w->param.eapdbtl & 702 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 703 } 704 705 res = hdac_command(sc, 706 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 707 HDA_BOOTVERBOSE( 708 device_printf(sc->dev, 709 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 710 hdac_hp_switch[i].hpnid, res); 711 ); 712 res >>= 31; 713 res ^= hdac_hp_switch[i].inverted; 714 715 switch (hdac_hp_switch[i].type) { 716 case HDAC_HP_SWITCH_CTL: 717 ctl = hdac_audio_ctl_amp_get(devinfo, 718 hdac_hp_switch[i].hpnid, 0, 1); 719 if (ctl != NULL) { 720 ctl->muted = (res != 0 && forcemute == 0) ? 721 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 722 hdac_audio_ctl_amp_set(ctl, 723 HDA_AMP_MUTE_DEFAULT, ctl->left, 724 ctl->right); 725 } 726 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 727 ctl = hdac_audio_ctl_amp_get(devinfo, 728 hdac_hp_switch[i].spkrnid[j], 0, 1); 729 if (ctl != NULL) { 730 ctl->muted = (res != 0 || forcemute == 1) ? 731 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 732 hdac_audio_ctl_amp_set(ctl, 733 HDA_AMP_MUTE_DEFAULT, ctl->left, 734 ctl->right); 735 } 736 } 737 break; 738 case HDAC_HP_SWITCH_CTRL: 739 if (res != 0) { 740 /* HP in */ 741 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 742 if (w != NULL && w->type == 743 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 744 if (forcemute == 0) 745 w->wclass.pin.ctrl |= 746 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 747 else 748 w->wclass.pin.ctrl &= 749 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 750 hdac_command(sc, 751 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 752 w->wclass.pin.ctrl), cad); 753 } 754 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 755 w = hdac_widget_get(devinfo, 756 hdac_hp_switch[i].spkrnid[j]); 757 if (w != NULL && w->type == 758 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 759 w->wclass.pin.ctrl &= 760 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 761 hdac_command(sc, 762 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 763 w->nid, 764 w->wclass.pin.ctrl), cad); 765 } 766 } 767 } else { 768 /* HP out */ 769 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 770 if (w != NULL && w->type == 771 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 772 w->wclass.pin.ctrl &= 773 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 774 hdac_command(sc, 775 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 776 w->wclass.pin.ctrl), cad); 777 } 778 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 779 w = hdac_widget_get(devinfo, 780 hdac_hp_switch[i].spkrnid[j]); 781 if (w != NULL && w->type == 782 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 783 if (forcemute == 0) 784 w->wclass.pin.ctrl |= 785 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 786 else 787 w->wclass.pin.ctrl &= 788 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 789 hdac_command(sc, 790 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 791 w->nid, 792 w->wclass.pin.ctrl), cad); 793 } 794 } 795 } 796 break; 797 default: 798 break; 799 } 800} 801 802static void 803hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 804{ 805 struct hdac_softc *sc; 806 struct hdac_devinfo *devinfo = NULL; 807 device_t *devlist = NULL; 808 int devcount, i; 809 810 if (codec == NULL || codec->sc == NULL) 811 return; 812 813 sc = codec->sc; 814 815 HDA_BOOTVERBOSE( 816 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 817 ); 818 819 device_get_children(sc->dev, &devlist, &devcount); 820 for (i = 0; devlist != NULL && i < devcount; i++) { 821 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 822 if (devinfo != NULL && devinfo->node_type == 823 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 824 devinfo->codec != NULL && 825 devinfo->codec->cad == codec->cad) { 826 break; 827 } else 828 devinfo = NULL; 829 } 830 if (devlist != NULL) 831 free(devlist, M_TEMP); 832 833 if (devinfo == NULL) 834 return; 835 836 switch (tag) { 837 case HDAC_UNSOLTAG_EVENT_HP: 838 hdac_hp_switch_handler(devinfo); 839 break; 840 default: 841 break; 842 } 843} 844 845static int 846hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 847{ 848 /* XXX to be removed */ 849#ifdef HDAC_INTR_EXTRA 850 uint32_t res; 851#endif 852 853 if (ch->blkcnt == 0) 854 return (0); 855 856 /* XXX to be removed */ 857#ifdef HDAC_INTR_EXTRA 858 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 859#endif 860 861 /* XXX to be removed */ 862#ifdef HDAC_INTR_EXTRA 863 HDA_BOOTVERBOSE( 864 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 865 device_printf(sc->dev, 866 "PCMDIR_%s intr triggered beyond stream boundary:" 867 "%08x\n", 868 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 869 ); 870#endif 871 872 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 873 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 874 875 /* XXX to be removed */ 876#ifdef HDAC_INTR_EXTRA 877 if (res & HDAC_SDSTS_BCIS) { 878#endif 879 return (1); 880 /* XXX to be removed */ 881#ifdef HDAC_INTR_EXTRA 882 } 883#endif 884 885 return (0); 886} 887 888/**************************************************************************** 889 * void hdac_intr_handler(void *) 890 * 891 * Interrupt handler. Processes interrupts received from the hdac. 892 ****************************************************************************/ 893static void 894hdac_intr_handler(void *context) 895{ 896 struct hdac_softc *sc; 897 uint32_t intsts; 898 uint8_t rirbsts; 899 struct hdac_rirb *rirb_base; 900 uint32_t trigger = 0; 901 902 sc = (struct hdac_softc *)context; 903 904 hdac_lock(sc); 905 if (sc->polling != 0) { 906 hdac_unlock(sc); 907 return; 908 } 909 /* Do we have anything to do? */ 910 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 911 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 912 hdac_unlock(sc); 913 return; 914 } 915 916 /* Was this a controller interrupt? */ 917 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 918 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 919 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 920 /* Get as many responses that we can */ 921 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 922 HDAC_WRITE_1(&sc->mem, 923 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 924 hdac_rirb_flush(sc); 925 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 926 } 927 /* XXX to be removed */ 928 /* Clear interrupt and exit */ 929#ifdef HDAC_INTR_EXTRA 930 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 931#endif 932 } 933 934 hdac_unsolq_flush(sc); 935 936 if (intsts & HDAC_INTSTS_SIS_MASK) { 937 if ((intsts & (1 << sc->num_iss)) && 938 hdac_stream_intr(sc, &sc->play) != 0) 939 trigger |= 1; 940 if ((intsts & (1 << 0)) && 941 hdac_stream_intr(sc, &sc->rec) != 0) 942 trigger |= 2; 943 /* XXX to be removed */ 944#ifdef HDAC_INTR_EXTRA 945 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 946 HDAC_INTSTS_SIS_MASK); 947#endif 948 } 949 950 hdac_unlock(sc); 951 952 if (trigger & 1) 953 chn_intr(sc->play.c); 954 if (trigger & 2) 955 chn_intr(sc->rec.c); 956} 957 958/**************************************************************************** 959 * int hdac_reset(hdac_softc *) 960 * 961 * Reset the hdac to a quiescent and known state. 962 ****************************************************************************/ 963static int 964hdac_reset(struct hdac_softc *sc) 965{ 966 uint32_t gctl; 967 int count, i; 968 969 /* 970 * Stop all Streams DMA engine 971 */ 972 for (i = 0; i < sc->num_iss; i++) 973 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 974 for (i = 0; i < sc->num_oss; i++) 975 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 976 for (i = 0; i < sc->num_bss; i++) 977 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 978 979 /* 980 * Stop Control DMA engines 981 */ 982 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 983 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 984 985 /* 986 * Reset the controller. The reset must remain asserted for 987 * a minimum of 100us. 988 */ 989 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 990 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 991 count = 10000; 992 do { 993 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 994 if (!(gctl & HDAC_GCTL_CRST)) 995 break; 996 DELAY(10); 997 } while (--count); 998 if (gctl & HDAC_GCTL_CRST) { 999 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1000 return (ENXIO); 1001 } 1002 DELAY(100); 1003 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1004 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1005 count = 10000; 1006 do { 1007 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1008 if (gctl & HDAC_GCTL_CRST) 1009 break; 1010 DELAY(10); 1011 } while (--count); 1012 if (!(gctl & HDAC_GCTL_CRST)) { 1013 device_printf(sc->dev, "Device stuck in reset\n"); 1014 return (ENXIO); 1015 } 1016 1017 /* 1018 * Wait for codecs to finish their own reset sequence. The delay here 1019 * should be of 250us but for some reasons, on it's not enough on my 1020 * computer. Let's use twice as much as necessary to make sure that 1021 * it's reset properly. 1022 */ 1023 DELAY(1000); 1024 1025 return (0); 1026} 1027 1028 1029/**************************************************************************** 1030 * int hdac_get_capabilities(struct hdac_softc *); 1031 * 1032 * Retreive the general capabilities of the hdac; 1033 * Number of Input Streams 1034 * Number of Output Streams 1035 * Number of bidirectional Streams 1036 * 64bit ready 1037 * CORB and RIRB sizes 1038 ****************************************************************************/ 1039static int 1040hdac_get_capabilities(struct hdac_softc *sc) 1041{ 1042 uint16_t gcap; 1043 uint8_t corbsize, rirbsize; 1044 1045 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1046 sc->num_iss = HDAC_GCAP_ISS(gcap); 1047 sc->num_oss = HDAC_GCAP_OSS(gcap); 1048 sc->num_bss = HDAC_GCAP_BSS(gcap); 1049 1050 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1051 1052 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1053 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1054 HDAC_CORBSIZE_CORBSZCAP_256) 1055 sc->corb_size = 256; 1056 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1057 HDAC_CORBSIZE_CORBSZCAP_16) 1058 sc->corb_size = 16; 1059 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1060 HDAC_CORBSIZE_CORBSZCAP_2) 1061 sc->corb_size = 2; 1062 else { 1063 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1064 __func__, corbsize); 1065 return (ENXIO); 1066 } 1067 1068 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1069 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1070 HDAC_RIRBSIZE_RIRBSZCAP_256) 1071 sc->rirb_size = 256; 1072 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1073 HDAC_RIRBSIZE_RIRBSZCAP_16) 1074 sc->rirb_size = 16; 1075 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1076 HDAC_RIRBSIZE_RIRBSZCAP_2) 1077 sc->rirb_size = 2; 1078 else { 1079 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1080 __func__, rirbsize); 1081 return (ENXIO); 1082 } 1083 1084 return (0); 1085} 1086 1087 1088/**************************************************************************** 1089 * void hdac_dma_cb 1090 * 1091 * This function is called by bus_dmamap_load when the mapping has been 1092 * established. We just record the physical address of the mapping into 1093 * the struct hdac_dma passed in. 1094 ****************************************************************************/ 1095static void 1096hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1097{ 1098 struct hdac_dma *dma; 1099 1100 if (error == 0) { 1101 dma = (struct hdac_dma *)callback_arg; 1102 dma->dma_paddr = segs[0].ds_addr; 1103 } 1104} 1105 1106static void 1107hdac_dma_nocache(void *ptr) 1108{ 1109#if defined(__i386__) || defined(__amd64__) 1110 pt_entry_t *pte; 1111 vm_offset_t va; 1112 1113 va = (vm_offset_t)ptr; 1114 pte = vtopte(va); 1115 if (pte) { 1116 *pte |= PG_N; 1117 invltlb(); 1118 } 1119#endif 1120} 1121 1122/**************************************************************************** 1123 * int hdac_dma_alloc 1124 * 1125 * This function allocate and setup a dma region (struct hdac_dma). 1126 * It must be freed by a corresponding hdac_dma_free. 1127 ****************************************************************************/ 1128static int 1129hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1130{ 1131 int result; 1132 int lowaddr; 1133 1134 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1135 BUS_SPACE_MAXADDR_32BIT; 1136 bzero(dma, sizeof(*dma)); 1137 1138 /* 1139 * Create a DMA tag 1140 */ 1141 result = bus_dma_tag_create(NULL, /* parent */ 1142 HDAC_DMA_ALIGNMENT, /* alignment */ 1143 0, /* boundary */ 1144 lowaddr, /* lowaddr */ 1145 BUS_SPACE_MAXADDR, /* highaddr */ 1146 NULL, /* filtfunc */ 1147 NULL, /* fistfuncarg */ 1148 size, /* maxsize */ 1149 1, /* nsegments */ 1150 size, /* maxsegsz */ 1151 0, /* flags */ 1152 NULL, /* lockfunc */ 1153 NULL, /* lockfuncarg */ 1154 &dma->dma_tag); /* dmat */ 1155 if (result != 0) { 1156 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1157 __func__, result); 1158 goto fail; 1159 } 1160 1161 /* 1162 * Allocate DMA memory 1163 */ 1164 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1165 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1166 if (result != 0) { 1167 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1168 __func__, result); 1169 goto fail; 1170 } 1171 1172 /* 1173 * Map the memory 1174 */ 1175 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1176 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1177 BUS_DMA_NOWAIT); 1178 if (result != 0 || dma->dma_paddr == 0) { 1179 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1180 __func__, result); 1181 goto fail; 1182 } 1183 bzero((void *)dma->dma_vaddr, size); 1184 hdac_dma_nocache(dma->dma_vaddr); 1185 1186 return (0); 1187fail: 1188 if (dma->dma_map != NULL) 1189 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1190 if (dma->dma_tag != NULL) 1191 bus_dma_tag_destroy(dma->dma_tag); 1192 return (result); 1193} 1194 1195 1196/**************************************************************************** 1197 * void hdac_dma_free(struct hdac_dma *) 1198 * 1199 * Free a struct dhac_dma that has been previously allocated via the 1200 * hdac_dma_alloc function. 1201 ****************************************************************************/ 1202static void 1203hdac_dma_free(struct hdac_dma *dma) 1204{ 1205 if (dma->dma_tag != NULL) { 1206 /* Flush caches */ 1207 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1208 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1209 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1210 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1211 bus_dma_tag_destroy(dma->dma_tag); 1212 } 1213} 1214 1215/**************************************************************************** 1216 * int hdac_mem_alloc(struct hdac_softc *) 1217 * 1218 * Allocate all the bus resources necessary to speak with the physical 1219 * controller. 1220 ****************************************************************************/ 1221static int 1222hdac_mem_alloc(struct hdac_softc *sc) 1223{ 1224 struct hdac_mem *mem; 1225 1226 mem = &sc->mem; 1227 mem->mem_rid = PCIR_BAR(0); 1228 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1229 &mem->mem_rid, RF_ACTIVE); 1230 if (mem->mem_res == NULL) { 1231 device_printf(sc->dev, 1232 "%s: Unable to allocate memory resource\n", __func__); 1233 return (ENOMEM); 1234 } 1235 mem->mem_tag = rman_get_bustag(mem->mem_res); 1236 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1237 1238 return (0); 1239} 1240 1241/**************************************************************************** 1242 * void hdac_mem_free(struct hdac_softc *) 1243 * 1244 * Free up resources previously allocated by hdac_mem_alloc. 1245 ****************************************************************************/ 1246static void 1247hdac_mem_free(struct hdac_softc *sc) 1248{ 1249 struct hdac_mem *mem; 1250 1251 mem = &sc->mem; 1252 if (mem->mem_res != NULL) 1253 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1254 mem->mem_res); 1255 mem->mem_res = NULL; 1256} 1257 1258/**************************************************************************** 1259 * int hdac_irq_alloc(struct hdac_softc *) 1260 * 1261 * Allocate and setup the resources necessary for interrupt handling. 1262 ****************************************************************************/ 1263static int 1264hdac_irq_alloc(struct hdac_softc *sc) 1265{ 1266 struct hdac_irq *irq; 1267 int result; 1268 1269 irq = &sc->irq; 1270 irq->irq_rid = 0x0; 1271 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1272 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1273 if (irq->irq_res == NULL) { 1274 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1275 __func__); 1276 goto fail; 1277 } 1278 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1279 hdac_intr_handler, sc, &irq->irq_handle); 1280 if (result != 0) { 1281 device_printf(sc->dev, 1282 "%s: Unable to setup interrupt handler (%x)\n", 1283 __func__, result); 1284 goto fail; 1285 } 1286 1287 return (0); 1288 1289fail: 1290 hdac_irq_free(sc); 1291 1292 return (ENXIO); 1293} 1294 1295/**************************************************************************** 1296 * void hdac_irq_free(struct hdac_softc *) 1297 * 1298 * Free up resources previously allocated by hdac_irq_alloc. 1299 ****************************************************************************/ 1300static void 1301hdac_irq_free(struct hdac_softc *sc) 1302{ 1303 struct hdac_irq *irq; 1304 1305 irq = &sc->irq; 1306 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1307 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1308 if (irq->irq_res != NULL) 1309 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1310 irq->irq_res); 1311 irq->irq_handle = NULL; 1312 irq->irq_res = NULL; 1313} 1314 1315/**************************************************************************** 1316 * void hdac_corb_init(struct hdac_softc *) 1317 * 1318 * Initialize the corb registers for operations but do not start it up yet. 1319 * The CORB engine must not be running when this function is called. 1320 ****************************************************************************/ 1321static void 1322hdac_corb_init(struct hdac_softc *sc) 1323{ 1324 uint8_t corbsize; 1325 uint64_t corbpaddr; 1326 1327 /* Setup the CORB size. */ 1328 switch (sc->corb_size) { 1329 case 256: 1330 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1331 break; 1332 case 16: 1333 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1334 break; 1335 case 2: 1336 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1337 break; 1338 default: 1339 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1340 } 1341 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1342 1343 /* Setup the CORB Address in the hdac */ 1344 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1345 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1346 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1347 1348 /* Set the WP and RP */ 1349 sc->corb_wp = 0; 1350 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1351 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1352 /* 1353 * The HDA specification indicates that the CORBRPRST bit will always 1354 * read as zero. Unfortunately, it seems that at least the 82801G 1355 * doesn't reset the bit to zero, which stalls the corb engine. 1356 * manually reset the bit to zero before continuing. 1357 */ 1358 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1359 1360 /* Enable CORB error reporting */ 1361#if 0 1362 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1363#endif 1364} 1365 1366/**************************************************************************** 1367 * void hdac_rirb_init(struct hdac_softc *) 1368 * 1369 * Initialize the rirb registers for operations but do not start it up yet. 1370 * The RIRB engine must not be running when this function is called. 1371 ****************************************************************************/ 1372static void 1373hdac_rirb_init(struct hdac_softc *sc) 1374{ 1375 uint8_t rirbsize; 1376 uint64_t rirbpaddr; 1377 1378 /* Setup the RIRB size. */ 1379 switch (sc->rirb_size) { 1380 case 256: 1381 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1382 break; 1383 case 16: 1384 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1385 break; 1386 case 2: 1387 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1388 break; 1389 default: 1390 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1391 } 1392 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1393 1394 /* Setup the RIRB Address in the hdac */ 1395 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1396 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1397 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1398 1399 /* Setup the WP and RP */ 1400 sc->rirb_rp = 0; 1401 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1402 1403 if (sc->polling == 0) { 1404 /* Setup the interrupt threshold */ 1405 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1406 1407 /* Enable Overrun and response received reporting */ 1408#if 0 1409 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1410 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1411#else 1412 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1413#endif 1414 } 1415 1416 /* 1417 * Make sure that the Host CPU cache doesn't contain any dirty 1418 * cache lines that falls in the rirb. If I understood correctly, it 1419 * should be sufficient to do this only once as the rirb is purely 1420 * read-only from now on. 1421 */ 1422 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1423 BUS_DMASYNC_PREREAD); 1424} 1425 1426/**************************************************************************** 1427 * void hdac_corb_start(hdac_softc *) 1428 * 1429 * Startup the corb DMA engine 1430 ****************************************************************************/ 1431static void 1432hdac_corb_start(struct hdac_softc *sc) 1433{ 1434 uint32_t corbctl; 1435 1436 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1437 corbctl |= HDAC_CORBCTL_CORBRUN; 1438 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1439} 1440 1441/**************************************************************************** 1442 * void hdac_rirb_start(hdac_softc *) 1443 * 1444 * Startup the rirb DMA engine 1445 ****************************************************************************/ 1446static void 1447hdac_rirb_start(struct hdac_softc *sc) 1448{ 1449 uint32_t rirbctl; 1450 1451 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1452 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1453 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1454} 1455 1456 1457/**************************************************************************** 1458 * void hdac_scan_codecs(struct hdac_softc *) 1459 * 1460 * Scan the bus for available codecs. 1461 ****************************************************************************/ 1462static void 1463hdac_scan_codecs(struct hdac_softc *sc) 1464{ 1465 struct hdac_codec *codec; 1466 int i; 1467 uint16_t statests; 1468 1469 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1470 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1471 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1472 /* We have found a codec. */ 1473 hdac_unlock(sc); 1474 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1475 M_HDAC, M_ZERO | M_NOWAIT); 1476 hdac_lock(sc); 1477 if (codec == NULL) { 1478 device_printf(sc->dev, 1479 "Unable to allocate memory for codec\n"); 1480 continue; 1481 } 1482 codec->commands = NULL; 1483 codec->responses_received = 0; 1484 codec->verbs_sent = 0; 1485 codec->sc = sc; 1486 codec->cad = i; 1487 sc->codecs[i] = codec; 1488 if (hdac_probe_codec(codec) != 0) 1489 break; 1490 } 1491 } 1492 /* All codecs have been probed, now try to attach drivers to them */ 1493 /* bus_generic_attach(sc->dev); */ 1494} 1495 1496/**************************************************************************** 1497 * void hdac_probe_codec(struct hdac_softc *, int) 1498 * 1499 * Probe a the given codec_id for available function groups. 1500 ****************************************************************************/ 1501static int 1502hdac_probe_codec(struct hdac_codec *codec) 1503{ 1504 struct hdac_softc *sc = codec->sc; 1505 struct hdac_devinfo *devinfo; 1506 uint32_t vendorid, revisionid, subnode; 1507 int startnode; 1508 int endnode; 1509 int i; 1510 nid_t cad = codec->cad; 1511 1512 HDA_BOOTVERBOSE( 1513 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1514 ); 1515 vendorid = hdac_command(sc, 1516 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1517 cad); 1518 revisionid = hdac_command(sc, 1519 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1520 cad); 1521 subnode = hdac_command(sc, 1522 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1523 cad); 1524 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1525 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1526 1527 HDA_BOOTVERBOSE( 1528 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1529 startnode, endnode); 1530 ); 1531 for (i = startnode; i < endnode; i++) { 1532 devinfo = hdac_probe_function(codec, i); 1533 if (devinfo != NULL) { 1534 /* XXX Ignore other FG. */ 1535 devinfo->vendor_id = 1536 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1537 devinfo->device_id = 1538 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1539 devinfo->revision_id = 1540 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1541 devinfo->stepping_id = 1542 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1543 HDA_BOOTVERBOSE( 1544 device_printf(sc->dev, 1545 "HDA_DEBUG: \tFound AFG nid=%d " 1546 "[startnode=%d endnode=%d]\n", 1547 devinfo->nid, startnode, endnode); 1548 ); 1549 return (1); 1550 } 1551 } 1552 1553 HDA_BOOTVERBOSE( 1554 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1555 ); 1556 return (0); 1557} 1558 1559static struct hdac_devinfo * 1560hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1561{ 1562 struct hdac_softc *sc = codec->sc; 1563 struct hdac_devinfo *devinfo; 1564 uint32_t fctgrptype; 1565 nid_t cad = codec->cad; 1566 1567 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1568 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1569 1570 /* XXX For now, ignore other FG. */ 1571 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1572 return (NULL); 1573 1574 hdac_unlock(sc); 1575 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1576 M_NOWAIT | M_ZERO); 1577 hdac_lock(sc); 1578 if (devinfo == NULL) { 1579 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1580 __func__); 1581 return (NULL); 1582 } 1583 1584 devinfo->nid = nid; 1585 devinfo->node_type = fctgrptype; 1586 devinfo->codec = codec; 1587 1588 hdac_add_child(sc, devinfo); 1589 1590 return (devinfo); 1591} 1592 1593static void 1594hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1595{ 1596 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1597 device_set_ivars(devinfo->dev, (void *)devinfo); 1598 /* XXX - Print more information when booting verbose??? */ 1599} 1600 1601static void 1602hdac_widget_connection_parse(struct hdac_widget *w) 1603{ 1604 struct hdac_softc *sc = w->devinfo->codec->sc; 1605 uint32_t res; 1606 int i, j, max, found, entnum, cnid; 1607 nid_t cad = w->devinfo->codec->cad; 1608 nid_t nid = w->nid; 1609 1610 res = hdac_command(sc, 1611 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1612 1613 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1614 1615 if (w->nconns < 1) 1616 return; 1617 1618 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1619 res = 0; 1620 i = 0; 1621 found = 0; 1622 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1623 1624 while (i < w->nconns) { 1625 res = hdac_command(sc, 1626 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1627 for (j = 0; j < entnum; j++) { 1628 cnid = res; 1629 cnid >>= (32 / entnum) * j; 1630 cnid &= (1 << (32 / entnum)) - 1; 1631 if (cnid == 0) 1632 continue; 1633 if (found > max) { 1634 device_printf(sc->dev, 1635 "node %d: Adding %d: " 1636 "Max connection reached!\n", 1637 nid, cnid); 1638 continue; 1639 } 1640 w->conns[found++] = cnid; 1641 } 1642 i += entnum; 1643 } 1644 1645 HDA_BOOTVERBOSE( 1646 if (w->nconns != found) { 1647 device_printf(sc->dev, 1648 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1649 "length=%d != found=%d\n", 1650 nid, w->nconns, found); 1651 } 1652 ); 1653} 1654 1655static uint32_t 1656hdac_widget_pin_getconfig(struct hdac_widget *w) 1657{ 1658 struct hdac_softc *sc; 1659 uint32_t config, id; 1660 nid_t cad, nid; 1661 1662 sc = w->devinfo->codec->sc; 1663 cad = w->devinfo->codec->cad; 1664 nid = w->nid; 1665 id = hdac_codec_id(w->devinfo); 1666 1667 config = hdac_command(sc, 1668 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1669 cad); 1670 /* 1671 * XXX REWRITE!!!! Don't argue! 1672 */ 1673 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1674 switch (nid) { 1675 case 26: 1676 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1677 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1678 break; 1679 case 27: 1680 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1681 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1682 break; 1683 } 1684 } else if (id == HDA_CODEC_ALC880 && 1685 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1686 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1687 /* 1688 * Super broken BIOS 1689 */ 1690 switch (nid) { 1691 case 20: 1692 break; 1693 case 21: 1694 break; 1695 case 22: 1696 break; 1697 case 23: 1698 break; 1699 case 24: /* MIC1 */ 1700 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1701 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1702 break; 1703 case 25: /* XXX MIC2 */ 1704 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1705 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1706 break; 1707 case 26: /* LINE1 */ 1708 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1709 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1710 break; 1711 case 27: /* XXX LINE2 */ 1712 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1713 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1714 break; 1715 case 28: /* CD */ 1716 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1717 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1718 break; 1719 case 30: 1720 break; 1721 case 31: 1722 break; 1723 default: 1724 break; 1725 } 1726 } 1727 1728 return (config); 1729} 1730 1731static void 1732hdac_widget_pin_parse(struct hdac_widget *w) 1733{ 1734 struct hdac_softc *sc = w->devinfo->codec->sc; 1735 uint32_t config, pincap; 1736 char *devstr, *connstr; 1737 nid_t cad = w->devinfo->codec->cad; 1738 nid_t nid = w->nid; 1739 1740 config = hdac_widget_pin_getconfig(w); 1741 w->wclass.pin.config = config; 1742 1743 pincap = hdac_command(sc, 1744 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1745 w->wclass.pin.cap = pincap; 1746 1747 w->wclass.pin.ctrl = hdac_command(sc, 1748 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1749 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1750 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1751 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1752 1753 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1754 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1755 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1756 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1757 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1758 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1759 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1760 w->param.eapdbtl = hdac_command(sc, 1761 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1762 w->param.eapdbtl &= 0x7; 1763 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1764 } else 1765 w->param.eapdbtl = HDAC_INVALID; 1766 1767 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1768 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1769 devstr = "line out"; 1770 break; 1771 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1772 devstr = "speaker"; 1773 break; 1774 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1775 devstr = "headphones out"; 1776 break; 1777 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1778 devstr = "CD"; 1779 break; 1780 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1781 devstr = "SPDIF out"; 1782 break; 1783 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1784 devstr = "digital (other) out"; 1785 break; 1786 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1787 devstr = "modem, line side"; 1788 break; 1789 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1790 devstr = "modem, handset side"; 1791 break; 1792 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1793 devstr = "line in"; 1794 break; 1795 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1796 devstr = "AUX"; 1797 break; 1798 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1799 devstr = "Mic in"; 1800 break; 1801 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1802 devstr = "telephony"; 1803 break; 1804 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1805 devstr = "SPDIF in"; 1806 break; 1807 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1808 devstr = "digital (other) in"; 1809 break; 1810 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1811 devstr = "other"; 1812 break; 1813 default: 1814 devstr = "unknown"; 1815 break; 1816 } 1817 1818 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1819 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1820 connstr = "jack"; 1821 break; 1822 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1823 connstr = "none"; 1824 break; 1825 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1826 connstr = "fixed"; 1827 break; 1828 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1829 connstr = "jack / fixed"; 1830 break; 1831 default: 1832 connstr = "unknown"; 1833 break; 1834 } 1835 1836 strlcat(w->name, ": ", sizeof(w->name)); 1837 strlcat(w->name, devstr, sizeof(w->name)); 1838 strlcat(w->name, " (", sizeof(w->name)); 1839 strlcat(w->name, connstr, sizeof(w->name)); 1840 strlcat(w->name, ")", sizeof(w->name)); 1841} 1842 1843static void 1844hdac_widget_parse(struct hdac_widget *w) 1845{ 1846 struct hdac_softc *sc = w->devinfo->codec->sc; 1847 uint32_t wcap, cap; 1848 char *typestr; 1849 nid_t cad = w->devinfo->codec->cad; 1850 nid_t nid = w->nid; 1851 1852 wcap = hdac_command(sc, 1853 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1854 cad); 1855 w->param.widget_cap = wcap; 1856 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1857 1858 switch (w->type) { 1859 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1860 typestr = "audio output"; 1861 break; 1862 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1863 typestr = "audio input"; 1864 break; 1865 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1866 typestr = "audio mixer"; 1867 break; 1868 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1869 typestr = "audio selector"; 1870 break; 1871 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1872 typestr = "pin"; 1873 break; 1874 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1875 typestr = "power widget"; 1876 break; 1877 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1878 typestr = "volume widget"; 1879 break; 1880 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1881 typestr = "beep widget"; 1882 break; 1883 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1884 typestr = "vendor widget"; 1885 break; 1886 default: 1887 typestr = "unknown type"; 1888 break; 1889 } 1890 1891 strlcpy(w->name, typestr, sizeof(w->name)); 1892 1893 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1894 hdac_command(sc, 1895 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1896 cad); 1897 DELAY(1000); 1898 } 1899 1900 hdac_widget_connection_parse(w); 1901 1902 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1903 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1904 w->param.outamp_cap = 1905 hdac_command(sc, 1906 HDA_CMD_GET_PARAMETER(cad, nid, 1907 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1908 else 1909 w->param.outamp_cap = 1910 w->devinfo->function.audio.outamp_cap; 1911 } else 1912 w->param.outamp_cap = 0; 1913 1914 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1915 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1916 w->param.inamp_cap = 1917 hdac_command(sc, 1918 HDA_CMD_GET_PARAMETER(cad, nid, 1919 HDA_PARAM_INPUT_AMP_CAP), cad); 1920 else 1921 w->param.inamp_cap = 1922 w->devinfo->function.audio.inamp_cap; 1923 } else 1924 w->param.inamp_cap = 0; 1925 1926 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1927 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1928 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1929 cap = hdac_command(sc, 1930 HDA_CMD_GET_PARAMETER(cad, nid, 1931 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1932 w->param.supp_stream_formats = (cap != 0) ? cap : 1933 w->devinfo->function.audio.supp_stream_formats; 1934 cap = hdac_command(sc, 1935 HDA_CMD_GET_PARAMETER(cad, nid, 1936 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1937 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1938 w->devinfo->function.audio.supp_pcm_size_rate; 1939 } else { 1940 w->param.supp_stream_formats = 1941 w->devinfo->function.audio.supp_stream_formats; 1942 w->param.supp_pcm_size_rate = 1943 w->devinfo->function.audio.supp_pcm_size_rate; 1944 } 1945 } else { 1946 w->param.supp_stream_formats = 0; 1947 w->param.supp_pcm_size_rate = 0; 1948 } 1949 1950 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1951 hdac_widget_pin_parse(w); 1952} 1953 1954static struct hdac_widget * 1955hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1956{ 1957 if (devinfo == NULL || devinfo->widget == NULL || 1958 nid < devinfo->startnode || nid >= devinfo->endnode) 1959 return (NULL); 1960 return (&devinfo->widget[nid - devinfo->startnode]); 1961} 1962 1963static __inline int 1964hda_poll_channel(struct hdac_chan *ch) 1965{ 1966 uint32_t sz, delta; 1967 volatile uint32_t ptr; 1968 1969 if (ch->active == 0) 1970 return (0); 1971 1972 sz = ch->blksz * ch->blkcnt; 1973 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1974 ch->ptr = ptr; 1975 ptr %= sz; 1976 ptr &= ~(ch->blksz - 1); 1977 delta = (sz + ptr - ch->prevptr) % sz; 1978 1979 if (delta < ch->blksz) 1980 return (0); 1981 1982 ch->prevptr = ptr; 1983 1984 return (1); 1985} 1986 1987#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1988 1989static void 1990hda_poll_callback(void *arg) 1991{ 1992 struct hdac_softc *sc = arg; 1993 uint32_t trigger = 0; 1994 1995 if (sc == NULL) 1996 return; 1997 1998 hdac_lock(sc); 1999 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2000 hdac_unlock(sc); 2001 return; 2002 } 2003 2004 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2005 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2006 2007 /* XXX */ 2008 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2009 hda_poll_callback, sc); 2010 2011 hdac_unlock(sc); 2012 2013 if (trigger & 1) 2014 chn_intr(sc->play.c); 2015 if (trigger & 2) 2016 chn_intr(sc->rec.c); 2017} 2018 2019static int 2020hdac_rirb_flush(struct hdac_softc *sc) 2021{ 2022 struct hdac_rirb *rirb_base, *rirb; 2023 struct hdac_codec *codec; 2024 struct hdac_command_list *commands; 2025 nid_t cad; 2026 uint32_t resp; 2027 uint8_t rirbwp; 2028 int ret = 0; 2029 2030 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2031 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2032 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2033 BUS_DMASYNC_POSTREAD); 2034 2035 while (sc->rirb_rp != rirbwp) { 2036 sc->rirb_rp++; 2037 sc->rirb_rp %= sc->rirb_size; 2038 rirb = &rirb_base[sc->rirb_rp]; 2039 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2040 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2041 sc->codecs[cad] == NULL) 2042 continue; 2043 resp = rirb->response; 2044 codec = sc->codecs[cad]; 2045 commands = codec->commands; 2046 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2047 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2048 ((resp >> 26) & 0xffff); 2049 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2050 } else if (commands != NULL && commands->num_commands > 0 && 2051 codec->responses_received < commands->num_commands) 2052 commands->responses[codec->responses_received++] = 2053 resp; 2054 ret++; 2055 } 2056 2057 return (ret); 2058} 2059 2060static int 2061hdac_unsolq_flush(struct hdac_softc *sc) 2062{ 2063 nid_t cad; 2064 uint32_t tag; 2065 int ret = 0; 2066 2067 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2068 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2069 while (sc->unsolq_rp != sc->unsolq_wp) { 2070 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2071 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2072 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2073 hdac_unsolicited_handler(sc->codecs[cad], tag); 2074 ret++; 2075 } 2076 sc->unsolq_st = HDAC_UNSOLQ_READY; 2077 } 2078 2079 return (ret); 2080} 2081 2082static void 2083hdac_poll_callback(void *arg) 2084{ 2085 struct hdac_softc *sc = arg; 2086 if (sc == NULL) 2087 return; 2088 2089 hdac_lock(sc); 2090 if (sc->polling == 0) { 2091 hdac_unlock(sc); 2092 return; 2093 } 2094 hdac_rirb_flush(sc); 2095 hdac_unsolq_flush(sc); 2096 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2097 hdac_poll_callback, sc); 2098 hdac_unlock(sc); 2099} 2100 2101static void 2102hdac_stream_stop(struct hdac_chan *ch) 2103{ 2104 struct hdac_softc *sc = ch->devinfo->codec->sc; 2105 uint32_t ctl; 2106 2107 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2108 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2109 HDAC_SDCTL_RUN); 2110 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2111 2112 ch->active = 0; 2113 2114 if (sc->polling != 0) { 2115 int pollticks; 2116 2117 if (hda_chan_active(sc) == 0) { 2118 callout_stop(&sc->poll_hda); 2119 sc->poll_ticks = 1; 2120 } else { 2121 if (sc->play.active != 0) 2122 ch = &sc->play; 2123 else 2124 ch = &sc->rec; 2125 pollticks = ((uint64_t)hz * ch->blksz) / 2126 ((uint64_t)sndbuf_getbps(ch->b) * 2127 sndbuf_getspd(ch->b)); 2128 pollticks >>= 2; 2129 if (pollticks > hz) 2130 pollticks = hz; 2131 if (pollticks < 1) { 2132 HDA_BOOTVERBOSE( 2133 device_printf(sc->dev, 2134 "%s: pollticks=%d < 1 !\n", 2135 __func__, pollticks); 2136 ); 2137 pollticks = 1; 2138 } 2139 if (pollticks > sc->poll_ticks) { 2140 HDA_BOOTVERBOSE( 2141 device_printf(sc->dev, 2142 "%s: pollticks %d -> %d\n", 2143 __func__, sc->poll_ticks, 2144 pollticks); 2145 ); 2146 sc->poll_ticks = pollticks; 2147 callout_reset(&sc->poll_hda, 1, 2148 hda_poll_callback, sc); 2149 } 2150 } 2151 } else { 2152 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2153 ctl &= ~(1 << (ch->off >> 5)); 2154 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2155 } 2156} 2157 2158static void 2159hdac_stream_start(struct hdac_chan *ch) 2160{ 2161 struct hdac_softc *sc = ch->devinfo->codec->sc; 2162 uint32_t ctl; 2163 2164 if (sc->polling != 0) { 2165 int pollticks; 2166 2167 pollticks = ((uint64_t)hz * ch->blksz) / 2168 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2169 pollticks >>= 2; 2170 if (pollticks > hz) 2171 pollticks = hz; 2172 if (pollticks < 1) { 2173 HDA_BOOTVERBOSE( 2174 device_printf(sc->dev, 2175 "%s: pollticks=%d < 1 !\n", 2176 __func__, pollticks); 2177 ); 2178 pollticks = 1; 2179 } 2180 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2181 HDA_BOOTVERBOSE( 2182 if (hda_chan_active(sc) == 0) { 2183 device_printf(sc->dev, 2184 "%s: pollticks=%d\n", 2185 __func__, pollticks); 2186 } else { 2187 device_printf(sc->dev, 2188 "%s: pollticks %d -> %d\n", 2189 __func__, sc->poll_ticks, 2190 pollticks); 2191 } 2192 ); 2193 sc->poll_ticks = pollticks; 2194 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2195 sc); 2196 } 2197 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2198 ctl |= HDAC_SDCTL_RUN; 2199 } else { 2200 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2201 ctl |= 1 << (ch->off >> 5); 2202 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2203 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2204 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2205 HDAC_SDCTL_RUN; 2206 } 2207 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2208 2209 ch->active = 1; 2210} 2211 2212static void 2213hdac_stream_reset(struct hdac_chan *ch) 2214{ 2215 struct hdac_softc *sc = ch->devinfo->codec->sc; 2216 int timeout = 1000; 2217 int to = timeout; 2218 uint32_t ctl; 2219 2220 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2221 ctl |= HDAC_SDCTL_SRST; 2222 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2223 do { 2224 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2225 if (ctl & HDAC_SDCTL_SRST) 2226 break; 2227 DELAY(10); 2228 } while (--to); 2229 if (!(ctl & HDAC_SDCTL_SRST)) { 2230 device_printf(sc->dev, "timeout in reset\n"); 2231 } 2232 ctl &= ~HDAC_SDCTL_SRST; 2233 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2234 to = timeout; 2235 do { 2236 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2237 if (!(ctl & HDAC_SDCTL_SRST)) 2238 break; 2239 DELAY(10); 2240 } while (--to); 2241 if (ctl & HDAC_SDCTL_SRST) 2242 device_printf(sc->dev, "can't reset!\n"); 2243} 2244 2245static void 2246hdac_stream_setid(struct hdac_chan *ch) 2247{ 2248 struct hdac_softc *sc = ch->devinfo->codec->sc; 2249 uint32_t ctl; 2250 2251 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2252 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2253 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2254 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2255} 2256 2257static void 2258hdac_bdl_setup(struct hdac_chan *ch) 2259{ 2260 struct hdac_softc *sc = ch->devinfo->codec->sc; 2261 struct hdac_bdle *bdle; 2262 uint64_t addr; 2263 uint32_t blksz, blkcnt; 2264 int i; 2265 2266 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2267 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2268 2269 if (sc->polling != 0) { 2270 blksz = ch->blksz * ch->blkcnt; 2271 blkcnt = 1; 2272 } else { 2273 blksz = ch->blksz; 2274 blkcnt = ch->blkcnt; 2275 } 2276 2277 for (i = 0; i < blkcnt; i++, bdle++) { 2278 bdle->addrl = (uint32_t)addr; 2279 bdle->addrh = (uint32_t)(addr >> 32); 2280 bdle->len = blksz; 2281 bdle->ioc = 1 ^ sc->polling; 2282 addr += blksz; 2283 } 2284 2285 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2286 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2287 addr = ch->bdl_dma.dma_paddr; 2288 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2289 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2290} 2291 2292static int 2293hdac_bdl_alloc(struct hdac_chan *ch) 2294{ 2295 struct hdac_softc *sc = ch->devinfo->codec->sc; 2296 int rc; 2297 2298 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2299 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2300 if (rc) { 2301 device_printf(sc->dev, "can't alloc bdl\n"); 2302 return (rc); 2303 } 2304 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2305 2306 return (0); 2307} 2308 2309static void 2310hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2311 int index, int lmute, int rmute, 2312 int left, int right, int dir) 2313{ 2314 uint16_t v = 0; 2315 2316 if (sc == NULL) 2317 return; 2318 2319 if (left != right || lmute != rmute) { 2320 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2321 (lmute << 7) | left; 2322 hdac_command(sc, 2323 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2324 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2325 (rmute << 7) | right; 2326 } else 2327 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2328 (lmute << 7) | left; 2329 2330 hdac_command(sc, 2331 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2332} 2333 2334static void 2335hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2336 int left, int right) 2337{ 2338 struct hdac_softc *sc; 2339 nid_t nid, cad; 2340 int lmute, rmute; 2341 2342 if (ctl == NULL || ctl->widget == NULL || 2343 ctl->widget->devinfo == NULL || 2344 ctl->widget->devinfo->codec == NULL || 2345 ctl->widget->devinfo->codec->sc == NULL) 2346 return; 2347 2348 sc = ctl->widget->devinfo->codec->sc; 2349 cad = ctl->widget->devinfo->codec->cad; 2350 nid = ctl->widget->nid; 2351 2352 if (mute == HDA_AMP_MUTE_DEFAULT) { 2353 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2354 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2355 } else { 2356 lmute = HDA_AMP_LEFT_MUTED(mute); 2357 rmute = HDA_AMP_RIGHT_MUTED(mute); 2358 } 2359 2360 if (ctl->dir & HDA_CTL_OUT) 2361 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2362 lmute, rmute, left, right, 0); 2363 if (ctl->dir & HDA_CTL_IN) 2364 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2365 lmute, rmute, left, right, 1); 2366 ctl->left = left; 2367 ctl->right = right; 2368} 2369 2370static void 2371hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2372{ 2373 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2374 return; 2375 hdac_command(w->devinfo->codec->sc, 2376 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2377 w->nid, index), w->devinfo->codec->cad); 2378 w->selconn = index; 2379} 2380 2381 2382/**************************************************************************** 2383 * uint32_t hdac_command_sendone_internal 2384 * 2385 * Wrapper function that sends only one command to a given codec 2386 ****************************************************************************/ 2387static uint32_t 2388hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2389{ 2390 struct hdac_command_list cl; 2391 uint32_t response = HDAC_INVALID; 2392 2393 if (!hdac_lockowned(sc)) 2394 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2395 cl.num_commands = 1; 2396 cl.verbs = &verb; 2397 cl.responses = &response; 2398 2399 hdac_command_send_internal(sc, &cl, cad); 2400 2401 return (response); 2402} 2403 2404/**************************************************************************** 2405 * hdac_command_send_internal 2406 * 2407 * Send a command list to the codec via the corb. We queue as much verbs as 2408 * we can and msleep on the codec. When the interrupt get the responses 2409 * back from the rirb, it will wake us up so we can queue the remaining verbs 2410 * if any. 2411 ****************************************************************************/ 2412static void 2413hdac_command_send_internal(struct hdac_softc *sc, 2414 struct hdac_command_list *commands, nid_t cad) 2415{ 2416 struct hdac_codec *codec; 2417 int corbrp; 2418 uint32_t *corb; 2419 int timeout; 2420 int retry = 10; 2421 struct hdac_rirb *rirb_base; 2422 2423 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2424 commands->num_commands < 1) 2425 return; 2426 2427 codec = sc->codecs[cad]; 2428 codec->commands = commands; 2429 codec->responses_received = 0; 2430 codec->verbs_sent = 0; 2431 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2432 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2433 2434 do { 2435 if (codec->verbs_sent != commands->num_commands) { 2436 /* Queue as many verbs as possible */ 2437 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2438 bus_dmamap_sync(sc->corb_dma.dma_tag, 2439 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2440 while (codec->verbs_sent != commands->num_commands && 2441 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2442 sc->corb_wp++; 2443 sc->corb_wp %= sc->corb_size; 2444 corb[sc->corb_wp] = 2445 commands->verbs[codec->verbs_sent++]; 2446 } 2447 2448 /* Send the verbs to the codecs */ 2449 bus_dmamap_sync(sc->corb_dma.dma_tag, 2450 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2451 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2452 } 2453 2454 timeout = 1000; 2455 while (hdac_rirb_flush(sc) == 0 && --timeout) 2456 DELAY(10); 2457 } while ((codec->verbs_sent != commands->num_commands || 2458 codec->responses_received != commands->num_commands) && --retry); 2459 2460 if (retry == 0) 2461 device_printf(sc->dev, 2462 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2463 __func__, commands->num_commands, codec->verbs_sent, 2464 codec->responses_received); 2465 2466 codec->commands = NULL; 2467 codec->responses_received = 0; 2468 codec->verbs_sent = 0; 2469 2470 hdac_unsolq_flush(sc); 2471} 2472 2473 2474/**************************************************************************** 2475 * Device Methods 2476 ****************************************************************************/ 2477 2478/**************************************************************************** 2479 * int hdac_probe(device_t) 2480 * 2481 * Probe for the presence of an hdac. If none is found, check for a generic 2482 * match using the subclass of the device. 2483 ****************************************************************************/ 2484static int 2485hdac_probe(device_t dev) 2486{ 2487 int i, result; 2488 uint32_t model; 2489 uint16_t class, subclass; 2490 char desc[64]; 2491 2492 model = (uint32_t)pci_get_device(dev) << 16; 2493 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2494 class = pci_get_class(dev); 2495 subclass = pci_get_subclass(dev); 2496 2497 bzero(desc, sizeof(desc)); 2498 result = ENXIO; 2499 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2500 if (hdac_devices[i].model == model) { 2501 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2502 result = BUS_PROBE_DEFAULT; 2503 break; 2504 } 2505 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2506 class == PCIC_MULTIMEDIA && 2507 subclass == PCIS_MULTIMEDIA_HDA) { 2508 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2509 result = BUS_PROBE_GENERIC; 2510 break; 2511 } 2512 } 2513 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2514 subclass == PCIS_MULTIMEDIA_HDA) { 2515 strlcpy(desc, "Generic", sizeof(desc)); 2516 result = BUS_PROBE_GENERIC; 2517 } 2518 if (result != ENXIO) { 2519 strlcat(desc, " High Definition Audio Controller", 2520 sizeof(desc)); 2521 device_set_desc_copy(dev, desc); 2522 } 2523 2524 return (result); 2525} 2526 2527static void * 2528hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2529 struct pcm_channel *c, int dir) 2530{ 2531 struct hdac_devinfo *devinfo = data; 2532 struct hdac_softc *sc = devinfo->codec->sc; 2533 struct hdac_chan *ch; 2534 2535 hdac_lock(sc); 2536 if (dir == PCMDIR_PLAY) { 2537 ch = &sc->play; 2538 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2539 ch->dir = PCMDIR_PLAY; 2540 ch->sid = ++sc->streamcnt; 2541 devinfo->function.audio.playcnt++; 2542 } else { 2543 ch = &sc->rec; 2544 ch->off = devinfo->function.audio.reccnt << 5; 2545 ch->dir = PCMDIR_REC; 2546 ch->sid = ++sc->streamcnt; 2547 devinfo->function.audio.reccnt++; 2548 } 2549 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2550 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2551 ch->pcmrates[0] = 48000; 2552 ch->pcmrates[1] = 0; 2553 } 2554 ch->b = b; 2555 ch->c = c; 2556 ch->devinfo = devinfo; 2557 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2558 ch->blkcnt = sc->chan_blkcnt; 2559 hdac_unlock(sc); 2560 2561 if (hdac_bdl_alloc(ch) != 0) { 2562 ch->blkcnt = 0; 2563 return (NULL); 2564 } 2565 2566 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2567 return (NULL); 2568 2569 hdac_dma_nocache(ch->b->buf); 2570 2571 return (ch); 2572} 2573 2574static int 2575hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2576{ 2577 struct hdac_chan *ch = data; 2578 int i; 2579 2580 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2581 if (format == ch->caps.fmtlist[i]) { 2582 ch->fmt = format; 2583 return (0); 2584 } 2585 } 2586 2587 return (EINVAL); 2588} 2589 2590static int 2591hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2592{ 2593 struct hdac_chan *ch = data; 2594 uint32_t spd = 0, threshold; 2595 int i; 2596 2597 for (i = 0; ch->pcmrates[i] != 0; i++) { 2598 spd = ch->pcmrates[i]; 2599 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2600 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2601 if (speed < threshold) 2602 break; 2603 } 2604 2605 if (spd == 0) /* impossible */ 2606 ch->spd = 48000; 2607 else 2608 ch->spd = spd; 2609 2610 return (ch->spd); 2611} 2612 2613static void 2614hdac_stream_setup(struct hdac_chan *ch) 2615{ 2616 struct hdac_softc *sc = ch->devinfo->codec->sc; 2617 int i; 2618 nid_t cad = ch->devinfo->codec->cad; 2619 uint16_t fmt; 2620 2621 fmt = 0; 2622 if (ch->fmt & AFMT_S16_LE) 2623 fmt |= ch->bit16 << 4; 2624 else if (ch->fmt & AFMT_S32_LE) 2625 fmt |= ch->bit32 << 4; 2626 else 2627 fmt |= 1 << 4; 2628 2629 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2630 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2631 fmt |= hda_rate_tab[i].base; 2632 fmt |= hda_rate_tab[i].mul; 2633 fmt |= hda_rate_tab[i].div; 2634 break; 2635 } 2636 } 2637 2638 if (ch->fmt & AFMT_STEREO) 2639 fmt |= 1; 2640 2641 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2642 2643 for (i = 0; ch->io[i] != -1; i++) { 2644 HDA_BOOTVERBOSE( 2645 device_printf(sc->dev, 2646 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2647 "fmt=0x%08x\n", 2648 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2649 ch->io[i], fmt); 2650 ); 2651 hdac_command(sc, 2652 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2653 hdac_command(sc, 2654 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2655 ch->sid << 4), cad); 2656 } 2657} 2658 2659static int 2660hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2661{ 2662 struct hdac_chan *ch = data; 2663 struct hdac_softc *sc = ch->devinfo->codec->sc; 2664 2665 blksz &= ~0x7f; 2666 if (blksz < 0x80) 2667 blksz = 0x80; 2668 2669 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2670 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2671 2672 if ((sndbuf_getblksz(ch->b) != blksz || 2673 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2674 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2675 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2676 __func__, blksz, ch->blkcnt); 2677 2678 ch->blksz = sndbuf_getblksz(ch->b); 2679 2680 return (ch->blksz); 2681} 2682 2683static void 2684hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2685{ 2686 struct hdac_devinfo *devinfo = ch->devinfo; 2687 nid_t cad = devinfo->codec->cad; 2688 int i; 2689 2690 hdac_stream_stop(ch); 2691 2692 for (i = 0; ch->io[i] != -1; i++) { 2693 hdac_command(sc, 2694 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2695 0), cad); 2696 } 2697} 2698 2699static void 2700hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2701{ 2702 ch->ptr = 0; 2703 ch->prevptr = 0; 2704 hdac_stream_stop(ch); 2705 hdac_stream_reset(ch); 2706 hdac_bdl_setup(ch); 2707 hdac_stream_setid(ch); 2708 hdac_stream_setup(ch); 2709 hdac_stream_start(ch); 2710} 2711 2712static int 2713hdac_channel_trigger(kobj_t obj, void *data, int go) 2714{ 2715 struct hdac_chan *ch = data; 2716 struct hdac_softc *sc = ch->devinfo->codec->sc; 2717 2718 hdac_lock(sc); 2719 switch (go) { 2720 case PCMTRIG_START: 2721 hdac_channel_start(sc, ch); 2722 break; 2723 case PCMTRIG_STOP: 2724 case PCMTRIG_ABORT: 2725 hdac_channel_stop(sc, ch); 2726 break; 2727 } 2728 hdac_unlock(sc); 2729 2730 return (0); 2731} 2732 2733static int 2734hdac_channel_getptr(kobj_t obj, void *data) 2735{ 2736 struct hdac_chan *ch = data; 2737 struct hdac_softc *sc = ch->devinfo->codec->sc; 2738 uint32_t ptr; 2739 2740 hdac_lock(sc); 2741 if (sc->polling != 0) 2742 ptr = ch->ptr; 2743 else 2744 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2745 hdac_unlock(sc); 2746 2747 /* 2748 * Round to available space and force 128 bytes aligment. 2749 */ 2750 ptr %= ch->blksz * ch->blkcnt; 2751 ptr &= ~0x7f; 2752 2753 return (ptr); 2754} 2755 2756static struct pcmchan_caps * 2757hdac_channel_getcaps(kobj_t obj, void *data) 2758{ 2759 return (&((struct hdac_chan *)data)->caps); 2760} 2761 2762static kobj_method_t hdac_channel_methods[] = { 2763 KOBJMETHOD(channel_init, hdac_channel_init), 2764 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2765 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2766 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2767 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2768 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2769 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2770 { 0, 0 } 2771}; 2772CHANNEL_DECLARE(hdac_channel); 2773 2774static int 2775hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2776{ 2777 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2778 struct hdac_softc *sc = devinfo->codec->sc; 2779 struct hdac_widget *w, *cw; 2780 struct hdac_audio_ctl *ctl; 2781 uint32_t mask, recmask, id; 2782 int i, j, softpcmvol; 2783 nid_t cad; 2784 2785 hdac_lock(sc); 2786 2787 mask = 0; 2788 recmask = 0; 2789 2790 id = hdac_codec_id(devinfo); 2791 cad = devinfo->codec->cad; 2792 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2793 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2794 sc->pci_subvendor) && 2795 hdac_hp_switch[i].id == id)) 2796 continue; 2797 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2798 if (w != NULL && w->enable != 0 2799 && w->type == 2800 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2801 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2802 hdac_command(sc, 2803 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2804 w->nid, 2805 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2806 HDAC_UNSOLTAG_EVENT_HP), cad); 2807 hdac_hp_switch_handler(devinfo); 2808 HDA_BOOTVERBOSE( 2809 device_printf(sc->dev, 2810 "HDA_DEBUG: Enabling headphone/speaker " 2811 "audio routing switching:\n"); 2812 device_printf(sc->dev, 2813 "HDA_DEBUG: \tindex=%d nid=%d " 2814 "pci_subvendor=0x%08x " 2815 "codec=0x%08x\n", 2816 i, w->nid, sc->pci_subvendor, id); 2817 ); 2818 } 2819 break; 2820 } 2821 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2822 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2823 sc->pci_subvendor) && 2824 hdac_eapd_switch[i].id == id)) 2825 continue; 2826 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2827 if (w == NULL || w->enable == 0) 2828 break; 2829 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2830 w->param.eapdbtl == HDAC_INVALID) 2831 break; 2832 mask |= SOUND_MASK_OGAIN; 2833 break; 2834 } 2835 2836 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2837 w = hdac_widget_get(devinfo, i); 2838 if (w == NULL || w->enable == 0) 2839 continue; 2840 mask |= w->ctlflags; 2841 if (!(w->pflags & HDA_ADC_RECSEL)) 2842 continue; 2843 for (j = 0; j < w->nconns; j++) { 2844 cw = hdac_widget_get(devinfo, w->conns[j]); 2845 if (cw == NULL || cw->enable == 0) 2846 continue; 2847 recmask |= cw->ctlflags; 2848 } 2849 } 2850 2851 if (!(mask & SOUND_MASK_PCM)) { 2852 softpcmvol = 1; 2853 mask |= SOUND_MASK_PCM; 2854 } else 2855 softpcmvol = (devinfo->function.audio.quirks & 2856 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2857 2858 i = 0; 2859 ctl = NULL; 2860 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2861 if (ctl->widget == NULL || ctl->enable == 0) 2862 continue; 2863 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2864 continue; 2865 if (ctl->step > 0) 2866 break; 2867 } 2868 2869 if (softpcmvol == 1 || ctl == NULL) { 2870 struct snddev_info *d = NULL; 2871 d = device_get_softc(sc->dev); 2872 if (d != NULL) { 2873 d->flags |= SD_F_SOFTPCMVOL; 2874 HDA_BOOTVERBOSE( 2875 device_printf(sc->dev, 2876 "HDA_DEBUG: %s Soft PCM volume\n", 2877 (softpcmvol == 1) ? 2878 "Forcing" : "Enabling"); 2879 ); 2880 } 2881 i = 0; 2882 /* 2883 * XXX Temporary quirk for STAC9220, until the parser 2884 * become smarter. 2885 */ 2886 if (id == HDA_CODEC_STAC9220) { 2887 mask |= SOUND_MASK_VOLUME; 2888 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2889 NULL) { 2890 if (ctl->widget == NULL || ctl->enable == 0) 2891 continue; 2892 if (ctl->widget->nid == 11 && ctl->index == 0) { 2893 ctl->ossmask = SOUND_MASK_VOLUME; 2894 ctl->ossval = 100 | (100 << 8); 2895 } else 2896 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2897 } 2898 } else { 2899 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2900 SOUND_MASK_PCM); 2901 if (!(mask & SOUND_MASK_VOLUME)) 2902 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2903 SOUND_MIXER_NONE); 2904 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2905 NULL) { 2906 if (ctl->widget == NULL || ctl->enable == 0) 2907 continue; 2908 if (!HDA_FLAG_MATCH(ctl->ossmask, 2909 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2910 continue; 2911 if (!(ctl->mute == 1 && ctl->step == 0)) 2912 ctl->enable = 0; 2913 } 2914 } 2915 } 2916 2917 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2918 2919 mix_setrecdevs(m, recmask); 2920 mix_setdevs(m, mask); 2921 2922 hdac_unlock(sc); 2923 2924 return (0); 2925} 2926 2927static int 2928hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2929 unsigned left, unsigned right) 2930{ 2931 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2932 struct hdac_softc *sc = devinfo->codec->sc; 2933 struct hdac_widget *w; 2934 struct hdac_audio_ctl *ctl; 2935 uint32_t id, mute; 2936 int lvol, rvol, mlvol, mrvol; 2937 int i = 0; 2938 2939 hdac_lock(sc); 2940 if (dev == SOUND_MIXER_OGAIN) { 2941 uint32_t orig; 2942 /*if (left != right || !(left == 0 || left == 1)) { 2943 hdac_unlock(sc); 2944 return (-1); 2945 }*/ 2946 id = hdac_codec_id(devinfo); 2947 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2948 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2949 sc->pci_subvendor) && 2950 hdac_eapd_switch[i].id == id) 2951 break; 2952 } 2953 if (i >= HDAC_EAPD_SWITCH_LEN) { 2954 hdac_unlock(sc); 2955 return (-1); 2956 } 2957 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2958 if (w == NULL || 2959 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2960 w->param.eapdbtl == HDAC_INVALID) { 2961 hdac_unlock(sc); 2962 return (-1); 2963 } 2964 orig = w->param.eapdbtl; 2965 if (left == 0) 2966 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2967 else 2968 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2969 if (orig != w->param.eapdbtl) { 2970 uint32_t val; 2971 2972 if (hdac_eapd_switch[i].hp_switch != 0) 2973 hdac_hp_switch_handler(devinfo); 2974 val = w->param.eapdbtl; 2975 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2976 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2977 hdac_command(sc, 2978 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2979 w->nid, val), devinfo->codec->cad); 2980 } 2981 hdac_unlock(sc); 2982 return (left | (left << 8)); 2983 } 2984 if (dev == SOUND_MIXER_VOLUME) 2985 devinfo->function.audio.mvol = left | (right << 8); 2986 2987 mlvol = devinfo->function.audio.mvol & 0x7f; 2988 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2989 lvol = 0; 2990 rvol = 0; 2991 2992 i = 0; 2993 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2994 if (ctl->widget == NULL || ctl->enable == 0 || 2995 !(ctl->ossmask & (1 << dev))) 2996 continue; 2997 switch (dev) { 2998 case SOUND_MIXER_VOLUME: 2999 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3000 lvol = (lvol * ctl->step) / 100; 3001 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3002 rvol = (rvol * ctl->step) / 100; 3003 break; 3004 default: 3005 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3006 lvol = (left * mlvol) / 100; 3007 lvol = (lvol * ctl->step) / 100; 3008 rvol = (right * mrvol) / 100; 3009 rvol = (rvol * ctl->step) / 100; 3010 } else { 3011 lvol = (left * ctl->step) / 100; 3012 rvol = (right * ctl->step) / 100; 3013 } 3014 ctl->ossval = left | (right << 8); 3015 break; 3016 } 3017 mute = 0; 3018 if (ctl->step < 1) { 3019 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3020 (ctl->muted & HDA_AMP_MUTE_LEFT); 3021 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3022 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3023 } else { 3024 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3025 (ctl->muted & HDA_AMP_MUTE_LEFT); 3026 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3027 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3028 } 3029 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3030 } 3031 hdac_unlock(sc); 3032 3033 return (left | (right << 8)); 3034} 3035 3036static int 3037hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3038{ 3039 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3040 struct hdac_widget *w, *cw; 3041 struct hdac_softc *sc = devinfo->codec->sc; 3042 uint32_t ret = src, target; 3043 int i, j; 3044 3045 target = 0; 3046 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3047 if (src & (1 << i)) { 3048 target = 1 << i; 3049 break; 3050 } 3051 } 3052 3053 hdac_lock(sc); 3054 3055 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3056 w = hdac_widget_get(devinfo, i); 3057 if (w == NULL || w->enable == 0) 3058 continue; 3059 if (!(w->pflags & HDA_ADC_RECSEL)) 3060 continue; 3061 for (j = 0; j < w->nconns; j++) { 3062 cw = hdac_widget_get(devinfo, w->conns[j]); 3063 if (cw == NULL || cw->enable == 0) 3064 continue; 3065 if ((target == SOUND_MASK_VOLUME && 3066 cw->type != 3067 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3068 (target != SOUND_MASK_VOLUME && 3069 cw->type == 3070 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3071 continue; 3072 if (cw->ctlflags & target) { 3073 hdac_widget_connection_select(w, j); 3074 ret = target; 3075 j += w->nconns; 3076 } 3077 } 3078 } 3079 3080 hdac_unlock(sc); 3081 3082 return (ret); 3083} 3084 3085static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3086 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3087 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3088 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3089 { 0, 0 } 3090}; 3091MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3092 3093/**************************************************************************** 3094 * int hdac_attach(device_t) 3095 * 3096 * Attach the device into the kernel. Interrupts usually won't be enabled 3097 * when this function is called. Setup everything that doesn't require 3098 * interrupts and defer probing of codecs until interrupts are enabled. 3099 ****************************************************************************/ 3100static int 3101hdac_attach(device_t dev) 3102{ 3103 struct hdac_softc *sc; 3104 int result; 3105 int i = 0; 3106 3107 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3108 if (sc == NULL) { 3109 device_printf(dev, "cannot allocate softc\n"); 3110 return (ENOMEM); 3111 } 3112 3113 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3114 if (sc->lock == NULL) { 3115 device_printf(dev, "mutex creation failed\n"); 3116 free(sc, M_DEVBUF); 3117 return (ENOMEM); 3118 } 3119 3120 sc->dev = dev; 3121 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3122 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3123 3124 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3125 /* Screw nx6325 - subdevice/subvendor swapped */ 3126 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3127 } 3128 3129 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3130 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3131 3132 sc->poll_ticks = 1; 3133 if (resource_int_value(device_get_name(sc->dev), 3134 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3135 sc->polling = 1; 3136 else 3137 sc->polling = 0; 3138 3139 sc->chan_size = pcm_getbuffersize(dev, 3140 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3141 3142 if (resource_int_value(device_get_name(sc->dev), 3143 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3144 i &= ~0x7f; 3145 if (i < 0x80) 3146 i = 0x80; 3147 sc->chan_blkcnt = sc->chan_size / i; 3148 i = 0; 3149 while (sc->chan_blkcnt >> i) 3150 i++; 3151 sc->chan_blkcnt = 1 << (i - 1); 3152 if (sc->chan_blkcnt < HDA_BDL_MIN) 3153 sc->chan_blkcnt = HDA_BDL_MIN; 3154 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3155 sc->chan_blkcnt = HDA_BDL_MAX; 3156 } else 3157 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3158 3159 result = bus_dma_tag_create(NULL, /* parent */ 3160 HDAC_DMA_ALIGNMENT, /* alignment */ 3161 0, /* boundary */ 3162 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3163 BUS_SPACE_MAXADDR, /* highaddr */ 3164 NULL, /* filtfunc */ 3165 NULL, /* fistfuncarg */ 3166 sc->chan_size, /* maxsize */ 3167 1, /* nsegments */ 3168 sc->chan_size, /* maxsegsz */ 3169 0, /* flags */ 3170 NULL, /* lockfunc */ 3171 NULL, /* lockfuncarg */ 3172 &sc->chan_dmat); /* dmat */ 3173 if (result != 0) { 3174 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3175 __func__, result); 3176 snd_mtxfree(sc->lock); 3177 free(sc, M_DEVBUF); 3178 return (ENXIO); 3179 } 3180 3181 3182 sc->hdabus = NULL; 3183 for (i = 0; i < HDAC_CODEC_MAX; i++) 3184 sc->codecs[i] = NULL; 3185 3186 pci_enable_busmaster(dev); 3187 3188 /* Allocate resources */ 3189 result = hdac_mem_alloc(sc); 3190 if (result != 0) 3191 goto hdac_attach_fail; 3192 result = hdac_irq_alloc(sc); 3193 if (result != 0) 3194 goto hdac_attach_fail; 3195 3196 /* Get Capabilities */ 3197 result = hdac_get_capabilities(sc); 3198 if (result != 0) 3199 goto hdac_attach_fail; 3200 3201 /* Allocate CORB and RIRB dma memory */ 3202 result = hdac_dma_alloc(sc, &sc->corb_dma, 3203 sc->corb_size * sizeof(uint32_t)); 3204 if (result != 0) 3205 goto hdac_attach_fail; 3206 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3207 sc->rirb_size * sizeof(struct hdac_rirb)); 3208 if (result != 0) 3209 goto hdac_attach_fail; 3210 3211 /* Quiesce everything */ 3212 hdac_reset(sc); 3213 3214 /* Disable PCI-Express QOS */ 3215 pci_write_config(sc->dev, 0x44, 3216 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3217 3218 /* Initialize the CORB and RIRB */ 3219 hdac_corb_init(sc); 3220 hdac_rirb_init(sc); 3221 3222 /* Defer remaining of initialization until interrupts are enabled */ 3223 sc->intrhook.ich_func = hdac_attach2; 3224 sc->intrhook.ich_arg = (void *)sc; 3225 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3226 sc->intrhook.ich_func = NULL; 3227 hdac_attach2((void *)sc); 3228 } 3229 3230 return (0); 3231 3232hdac_attach_fail: 3233 hdac_dma_free(&sc->rirb_dma); 3234 hdac_dma_free(&sc->corb_dma); 3235 hdac_irq_free(sc); 3236 hdac_mem_free(sc); 3237 snd_mtxfree(sc->lock); 3238 free(sc, M_DEVBUF); 3239 3240 return (ENXIO); 3241} 3242 3243static void 3244hdac_audio_parse(struct hdac_devinfo *devinfo) 3245{ 3246 struct hdac_softc *sc = devinfo->codec->sc; 3247 struct hdac_widget *w; 3248 uint32_t res; 3249 int i; 3250 nid_t cad, nid; 3251 3252 cad = devinfo->codec->cad; 3253 nid = devinfo->nid; 3254 3255 hdac_command(sc, 3256 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3257 3258 DELAY(100); 3259 3260 res = hdac_command(sc, 3261 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3262 3263 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3264 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3265 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3266 3267 HDA_BOOTVERBOSE( 3268 device_printf(sc->dev, " Vendor: 0x%08x\n", 3269 devinfo->vendor_id); 3270 device_printf(sc->dev, " Device: 0x%08x\n", 3271 devinfo->device_id); 3272 device_printf(sc->dev, " Revision: 0x%08x\n", 3273 devinfo->revision_id); 3274 device_printf(sc->dev, " Stepping: 0x%08x\n", 3275 devinfo->stepping_id); 3276 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3277 sc->pci_subvendor); 3278 device_printf(sc->dev, " Nodes: start=%d " 3279 "endnode=%d total=%d\n", 3280 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3281 ); 3282 3283 res = hdac_command(sc, 3284 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3285 cad); 3286 devinfo->function.audio.supp_stream_formats = res; 3287 3288 res = hdac_command(sc, 3289 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3290 cad); 3291 devinfo->function.audio.supp_pcm_size_rate = res; 3292 3293 res = hdac_command(sc, 3294 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3295 cad); 3296 devinfo->function.audio.outamp_cap = res; 3297 3298 res = hdac_command(sc, 3299 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3300 cad); 3301 devinfo->function.audio.inamp_cap = res; 3302 3303 if (devinfo->nodecnt > 0) { 3304 hdac_unlock(sc); 3305 devinfo->widget = (struct hdac_widget *)malloc( 3306 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3307 M_NOWAIT | M_ZERO); 3308 hdac_lock(sc); 3309 } else 3310 devinfo->widget = NULL; 3311 3312 if (devinfo->widget == NULL) { 3313 device_printf(sc->dev, "unable to allocate widgets!\n"); 3314 devinfo->endnode = devinfo->startnode; 3315 devinfo->nodecnt = 0; 3316 return; 3317 } 3318 3319 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3320 w = hdac_widget_get(devinfo, i); 3321 if (w == NULL) 3322 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3323 else { 3324 w->devinfo = devinfo; 3325 w->nid = i; 3326 w->enable = 1; 3327 w->selconn = -1; 3328 w->pflags = 0; 3329 w->ctlflags = 0; 3330 w->param.eapdbtl = HDAC_INVALID; 3331 hdac_widget_parse(w); 3332 } 3333 } 3334} 3335 3336static void 3337hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3338{ 3339 struct hdac_softc *sc = devinfo->codec->sc; 3340 struct hdac_audio_ctl *ctls; 3341 struct hdac_widget *w, *cw; 3342 int i, j, cnt, max, ocap, icap; 3343 int mute, offset, step, size; 3344 3345 /* XXX This is redundant */ 3346 max = 0; 3347 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3348 w = hdac_widget_get(devinfo, i); 3349 if (w == NULL || w->enable == 0) 3350 continue; 3351 if (w->param.outamp_cap != 0) 3352 max++; 3353 if (w->param.inamp_cap != 0) { 3354 switch (w->type) { 3355 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3356 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3357 for (j = 0; j < w->nconns; j++) { 3358 cw = hdac_widget_get(devinfo, 3359 w->conns[j]); 3360 if (cw == NULL || cw->enable == 0) 3361 continue; 3362 max++; 3363 } 3364 break; 3365 default: 3366 max++; 3367 break; 3368 } 3369 } 3370 } 3371 3372 devinfo->function.audio.ctlcnt = max; 3373 3374 if (max < 1) 3375 return; 3376 3377 hdac_unlock(sc); 3378 ctls = (struct hdac_audio_ctl *)malloc( 3379 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3380 hdac_lock(sc); 3381 3382 if (ctls == NULL) { 3383 /* Blekh! */ 3384 device_printf(sc->dev, "unable to allocate ctls!\n"); 3385 devinfo->function.audio.ctlcnt = 0; 3386 return; 3387 } 3388 3389 cnt = 0; 3390 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3391 if (cnt >= max) { 3392 device_printf(sc->dev, "%s: Ctl overflow!\n", 3393 __func__); 3394 break; 3395 } 3396 w = hdac_widget_get(devinfo, i); 3397 if (w == NULL || w->enable == 0) 3398 continue; 3399 ocap = w->param.outamp_cap; 3400 icap = w->param.inamp_cap; 3401 if (ocap != 0) { 3402 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3403 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3404 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3405 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3406 /*if (offset > step) { 3407 HDA_BOOTVERBOSE( 3408 device_printf(sc->dev, 3409 "HDA_DEBUG: BUGGY outamp: nid=%d " 3410 "[offset=%d > step=%d]\n", 3411 w->nid, offset, step); 3412 ); 3413 offset = step; 3414 }*/ 3415 ctls[cnt].enable = 1; 3416 ctls[cnt].widget = w; 3417 ctls[cnt].mute = mute; 3418 ctls[cnt].step = step; 3419 ctls[cnt].size = size; 3420 ctls[cnt].offset = offset; 3421 ctls[cnt].left = offset; 3422 ctls[cnt].right = offset; 3423 ctls[cnt++].dir = HDA_CTL_OUT; 3424 } 3425 3426 if (icap != 0) { 3427 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3428 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3429 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3430 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3431 /*if (offset > step) { 3432 HDA_BOOTVERBOSE( 3433 device_printf(sc->dev, 3434 "HDA_DEBUG: BUGGY inamp: nid=%d " 3435 "[offset=%d > step=%d]\n", 3436 w->nid, offset, step); 3437 ); 3438 offset = step; 3439 }*/ 3440 switch (w->type) { 3441 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3442 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3443 for (j = 0; j < w->nconns; j++) { 3444 if (cnt >= max) { 3445 device_printf(sc->dev, 3446 "%s: Ctl overflow!\n", 3447 __func__); 3448 break; 3449 } 3450 cw = hdac_widget_get(devinfo, 3451 w->conns[j]); 3452 if (cw == NULL || cw->enable == 0) 3453 continue; 3454 ctls[cnt].enable = 1; 3455 ctls[cnt].widget = w; 3456 ctls[cnt].childwidget = cw; 3457 ctls[cnt].index = j; 3458 ctls[cnt].mute = mute; 3459 ctls[cnt].step = step; 3460 ctls[cnt].size = size; 3461 ctls[cnt].offset = offset; 3462 ctls[cnt].left = offset; 3463 ctls[cnt].right = offset; 3464 ctls[cnt++].dir = HDA_CTL_IN; 3465 } 3466 break; 3467 default: 3468 if (cnt >= max) { 3469 device_printf(sc->dev, 3470 "%s: Ctl overflow!\n", 3471 __func__); 3472 break; 3473 } 3474 ctls[cnt].enable = 1; 3475 ctls[cnt].widget = w; 3476 ctls[cnt].mute = mute; 3477 ctls[cnt].step = step; 3478 ctls[cnt].size = size; 3479 ctls[cnt].offset = offset; 3480 ctls[cnt].left = offset; 3481 ctls[cnt].right = offset; 3482 ctls[cnt++].dir = HDA_CTL_IN; 3483 break; 3484 } 3485 } 3486 } 3487 3488 devinfo->function.audio.ctl = ctls; 3489} 3490 3491static const struct { 3492 uint32_t model; 3493 uint32_t id; 3494 uint32_t set, unset; 3495} hdac_quirks[] = { 3496 /* 3497 * XXX Force stereo quirk. Monoural recording / playback 3498 * on few codecs (especially ALC880) seems broken or 3499 * perhaps unsupported. 3500 */ 3501 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3502 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3503 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3504 HDA_QUIRK_GPIO0, 0 }, 3505 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3506 HDA_QUIRK_GPIO0, 0 }, 3507 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3508 HDA_QUIRK_GPIO0, 0 }, 3509 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3510 HDA_QUIRK_EAPDINV, 0 }, 3511 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3512 HDA_QUIRK_EAPDINV, 0 }, 3513 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3514 HDA_QUIRK_GPIO1, 0 }, 3515 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3516 HDA_QUIRK_EAPDINV, 0 }, 3517 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3518 HDA_QUIRK_EAPDINV, 0 }, 3519 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3520 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3521 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3522 0, HDA_QUIRK_FORCESTEREO }, 3523 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3524 HDA_QUIRK_SOFTPCMVOL, 0 } 3525}; 3526#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3527 3528static void 3529hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3530{ 3531 struct hdac_widget *w; 3532 uint32_t id, subvendor; 3533 int i; 3534 3535 id = hdac_codec_id(devinfo); 3536 subvendor = devinfo->codec->sc->pci_subvendor; 3537 3538 /* 3539 * Quirks 3540 */ 3541 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3542 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3543 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3544 continue; 3545 if (hdac_quirks[i].set != 0) 3546 devinfo->function.audio.quirks |= 3547 hdac_quirks[i].set; 3548 if (hdac_quirks[i].unset != 0) 3549 devinfo->function.audio.quirks &= 3550 ~(hdac_quirks[i].unset); 3551 } 3552 3553 switch (id) { 3554 case HDA_CODEC_ALC260: 3555 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3556 w = hdac_widget_get(devinfo, i); 3557 if (w == NULL || w->enable == 0) 3558 continue; 3559 if (w->type != 3560 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3561 continue; 3562 if (w->nid != 5) 3563 w->enable = 0; 3564 } 3565 break; 3566 case HDA_CODEC_ALC861: 3567 if (subvendor == ASUS_P1AH2_SUBVENDOR) { 3568 struct hdac_audio_ctl *ctl; 3569 3570 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3571 if (ctl != NULL) 3572 ctl->muted = HDA_AMP_MUTE_ALL; 3573 } 3574 break; 3575 case HDA_CODEC_ALC880: 3576 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3577 w = hdac_widget_get(devinfo, i); 3578 if (w == NULL || w->enable == 0) 3579 continue; 3580 if (w->type == 3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3582 w->nid != 9 && w->nid != 29) { 3583 w->enable = 0; 3584 } else if (w->type != 3585 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3586 w->nid == 29) { 3587 w->type = 3588 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3589 w->param.widget_cap &= 3590 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3591 w->param.widget_cap |= 3592 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3593 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3594 strlcpy(w->name, "beep widget", sizeof(w->name)); 3595 } 3596 } 3597 break; 3598 case HDA_CODEC_AD1981HD: 3599 w = hdac_widget_get(devinfo, 11); 3600 if (w != NULL && w->enable != 0 && w->nconns > 3) 3601 w->selconn = 3; 3602 if (subvendor == IBM_M52_SUBVENDOR) { 3603 struct hdac_audio_ctl *ctl; 3604 3605 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3606 if (ctl != NULL) 3607 ctl->ossmask = SOUND_MASK_SPEAKER; 3608 } 3609 break; 3610 case HDA_CODEC_AD1986A: 3611 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3612 w = hdac_widget_get(devinfo, i); 3613 if (w == NULL || w->enable == 0) 3614 continue; 3615 if (w->type != 3616 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3617 continue; 3618 if (w->nid != 3) 3619 w->enable = 0; 3620 } 3621 break; 3622 case HDA_CODEC_STAC9221: 3623 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3624 w = hdac_widget_get(devinfo, i); 3625 if (w == NULL || w->enable == 0) 3626 continue; 3627 if (w->type != 3628 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3629 continue; 3630 if (w->nid != 2) 3631 w->enable = 0; 3632 } 3633 break; 3634 case HDA_CODEC_STAC9221D: 3635 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3636 w = hdac_widget_get(devinfo, i); 3637 if (w == NULL || w->enable == 0) 3638 continue; 3639 if (w->type == 3640 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3641 w->nid != 6) 3642 w->enable = 0; 3643 3644 } 3645 break; 3646 default: 3647 break; 3648 } 3649} 3650 3651static int 3652hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3653{ 3654 int *dev = &devinfo->function.audio.ossidx; 3655 3656 while (*dev < SOUND_MIXER_NRDEVICES) { 3657 switch (*dev) { 3658 case SOUND_MIXER_VOLUME: 3659 case SOUND_MIXER_BASS: 3660 case SOUND_MIXER_TREBLE: 3661 case SOUND_MIXER_PCM: 3662 case SOUND_MIXER_SPEAKER: 3663 case SOUND_MIXER_LINE: 3664 case SOUND_MIXER_MIC: 3665 case SOUND_MIXER_CD: 3666 case SOUND_MIXER_RECLEV: 3667 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3668 (*dev)++; 3669 break; 3670 default: 3671 return (*dev)++; 3672 break; 3673 } 3674 } 3675 3676 return (-1); 3677} 3678 3679static int 3680hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3681{ 3682 struct hdac_widget *w; 3683 int i, ret = 0; 3684 3685 if (depth > HDA_PARSE_MAXDEPTH) 3686 return (0); 3687 w = hdac_widget_get(devinfo, nid); 3688 if (w == NULL || w->enable == 0) 3689 return (0); 3690 switch (w->type) { 3691 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3692 w->pflags |= HDA_DAC_PATH; 3693 ret = 1; 3694 break; 3695 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3696 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3697 for (i = 0; i < w->nconns; i++) { 3698 if (hdac_widget_find_dac_path(devinfo, 3699 w->conns[i], depth + 1) != 0) { 3700 if (w->selconn == -1) 3701 w->selconn = i; 3702 ret = 1; 3703 w->pflags |= HDA_DAC_PATH; 3704 } 3705 } 3706 break; 3707 default: 3708 break; 3709 } 3710 return (ret); 3711} 3712 3713static int 3714hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3715{ 3716 struct hdac_widget *w; 3717 int i, conndev, ret = 0; 3718 3719 if (depth > HDA_PARSE_MAXDEPTH) 3720 return (0); 3721 w = hdac_widget_get(devinfo, nid); 3722 if (w == NULL || w->enable == 0) 3723 return (0); 3724 switch (w->type) { 3725 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3726 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3727 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3728 for (i = 0; i < w->nconns; i++) { 3729 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3730 depth + 1) != 0) { 3731 if (w->selconn == -1) 3732 w->selconn = i; 3733 w->pflags |= HDA_ADC_PATH; 3734 ret = 1; 3735 } 3736 } 3737 break; 3738 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3739 conndev = w->wclass.pin.config & 3740 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3741 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3742 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3743 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3744 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3745 w->pflags |= HDA_ADC_PATH; 3746 ret = 1; 3747 } 3748 break; 3749 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3750 if (w->pflags & HDA_DAC_PATH) { 3751 w->pflags |= HDA_ADC_PATH; 3752 ret = 1; 3753 } 3754 break;*/ 3755 default: 3756 break; 3757 } 3758 return (ret); 3759} 3760 3761static uint32_t 3762hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3763 nid_t nid, nid_t pnid, int index, int depth) 3764{ 3765 struct hdac_widget *w, *pw; 3766 struct hdac_audio_ctl *ctl; 3767 uint32_t fl = 0; 3768 int i, ossdev, conndev, strategy; 3769 3770 if (depth > HDA_PARSE_MAXDEPTH) 3771 return (0); 3772 3773 w = hdac_widget_get(devinfo, nid); 3774 if (w == NULL || w->enable == 0) 3775 return (0); 3776 3777 pw = hdac_widget_get(devinfo, pnid); 3778 strategy = devinfo->function.audio.parsing_strategy; 3779 3780 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3781 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3782 for (i = 0; i < w->nconns; i++) { 3783 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3784 w->nid, i, depth + 1); 3785 } 3786 w->ctlflags |= fl; 3787 return (fl); 3788 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3789 (w->pflags & HDA_DAC_PATH)) { 3790 i = 0; 3791 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3792 if (ctl->enable == 0 || ctl->widget == NULL) 3793 continue; 3794 /* XXX This should be compressed! */ 3795 if ((ctl->widget->nid == w->nid) || 3796 (ctl->widget->nid == pnid && ctl->index == index && 3797 (ctl->dir & HDA_CTL_IN)) || 3798 (ctl->widget->nid == pnid && pw != NULL && 3799 pw->type == 3800 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3801 (pw->nconns < 2 || pw->selconn == index || 3802 pw->selconn == -1) && 3803 (ctl->dir & HDA_CTL_OUT)) || 3804 (strategy == HDA_PARSE_DIRECT && 3805 ctl->widget->nid == w->nid)) { 3806 /*if (pw != NULL && pw->selconn == -1) 3807 pw->selconn = index; 3808 fl |= SOUND_MASK_VOLUME; 3809 fl |= SOUND_MASK_PCM; 3810 ctl->ossmask |= SOUND_MASK_VOLUME; 3811 ctl->ossmask |= SOUND_MASK_PCM; 3812 ctl->ossdev = SOUND_MIXER_PCM;*/ 3813 if (!(w->ctlflags & SOUND_MASK_PCM) || 3814 (pw != NULL && 3815 !(pw->ctlflags & SOUND_MASK_PCM))) { 3816 fl |= SOUND_MASK_VOLUME; 3817 fl |= SOUND_MASK_PCM; 3818 ctl->ossmask |= SOUND_MASK_VOLUME; 3819 ctl->ossmask |= SOUND_MASK_PCM; 3820 ctl->ossdev = SOUND_MIXER_PCM; 3821 w->ctlflags |= SOUND_MASK_VOLUME; 3822 w->ctlflags |= SOUND_MASK_PCM; 3823 if (pw != NULL) { 3824 if (pw->selconn == -1) 3825 pw->selconn = index; 3826 pw->ctlflags |= 3827 SOUND_MASK_VOLUME; 3828 pw->ctlflags |= 3829 SOUND_MASK_PCM; 3830 } 3831 } 3832 } 3833 } 3834 w->ctlflags |= fl; 3835 return (fl); 3836 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3837 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3838 (w->pflags & HDA_ADC_PATH)) { 3839 conndev = w->wclass.pin.config & 3840 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3841 i = 0; 3842 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3843 if (ctl->enable == 0 || ctl->widget == NULL) 3844 continue; 3845 /* XXX This should be compressed! */ 3846 if (((ctl->widget->nid == pnid && ctl->index == index && 3847 (ctl->dir & HDA_CTL_IN)) || 3848 (ctl->widget->nid == pnid && pw != NULL && 3849 pw->type == 3850 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3851 (pw->nconns < 2 || pw->selconn == index || 3852 pw->selconn == -1) && 3853 (ctl->dir & HDA_CTL_OUT)) || 3854 (strategy == HDA_PARSE_DIRECT && 3855 ctl->widget->nid == w->nid)) && 3856 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3857 if (pw != NULL && pw->selconn == -1) 3858 pw->selconn = index; 3859 ossdev = 0; 3860 switch (conndev) { 3861 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3862 ossdev = SOUND_MIXER_MIC; 3863 break; 3864 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3865 ossdev = SOUND_MIXER_LINE; 3866 break; 3867 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3868 ossdev = SOUND_MIXER_CD; 3869 break; 3870 default: 3871 ossdev = 3872 hdac_audio_ctl_ossmixer_getnextdev( 3873 devinfo); 3874 if (ossdev < 0) 3875 ossdev = 0; 3876 break; 3877 } 3878 if (strategy == HDA_PARSE_MIXER) { 3879 fl |= SOUND_MASK_VOLUME; 3880 ctl->ossmask |= SOUND_MASK_VOLUME; 3881 } 3882 fl |= 1 << ossdev; 3883 ctl->ossmask |= 1 << ossdev; 3884 ctl->ossdev = ossdev; 3885 } 3886 } 3887 w->ctlflags |= fl; 3888 return (fl); 3889 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3890 i = 0; 3891 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3892 if (ctl->enable == 0 || ctl->widget == NULL) 3893 continue; 3894 /* XXX This should be compressed! */ 3895 if (((ctl->widget->nid == pnid && ctl->index == index && 3896 (ctl->dir & HDA_CTL_IN)) || 3897 (ctl->widget->nid == pnid && pw != NULL && 3898 pw->type == 3899 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3900 (pw->nconns < 2 || pw->selconn == index || 3901 pw->selconn == -1) && 3902 (ctl->dir & HDA_CTL_OUT)) || 3903 (strategy == HDA_PARSE_DIRECT && 3904 ctl->widget->nid == w->nid)) && 3905 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3906 if (pw != NULL && pw->selconn == -1) 3907 pw->selconn = index; 3908 fl |= SOUND_MASK_VOLUME; 3909 fl |= SOUND_MASK_SPEAKER; 3910 ctl->ossmask |= SOUND_MASK_VOLUME; 3911 ctl->ossmask |= SOUND_MASK_SPEAKER; 3912 ctl->ossdev = SOUND_MIXER_SPEAKER; 3913 } 3914 } 3915 w->ctlflags |= fl; 3916 return (fl); 3917 } 3918 return (0); 3919} 3920 3921static uint32_t 3922hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3923{ 3924 struct hdac_widget *w, *cw; 3925 struct hdac_audio_ctl *ctl; 3926 uint32_t fl; 3927 int i; 3928 3929 if (depth > HDA_PARSE_MAXDEPTH) 3930 return (0); 3931 3932 w = hdac_widget_get(devinfo, nid); 3933 if (w == NULL || w->enable == 0) 3934 return (0); 3935 /*if (!(w->pflags & HDA_ADC_PATH)) 3936 return (0); 3937 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3938 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3939 return (0);*/ 3940 i = 0; 3941 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3942 if (ctl->enable == 0 || ctl->widget == NULL) 3943 continue; 3944 if (ctl->widget->nid == nid) { 3945 ctl->ossmask |= SOUND_MASK_RECLEV; 3946 w->ctlflags |= SOUND_MASK_RECLEV; 3947 return (SOUND_MASK_RECLEV); 3948 } 3949 } 3950 for (i = 0; i < w->nconns; i++) { 3951 cw = hdac_widget_get(devinfo, w->conns[i]); 3952 if (cw == NULL || cw->enable == 0) 3953 continue; 3954 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3955 continue; 3956 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3957 if (fl != 0) { 3958 cw->ctlflags |= fl; 3959 w->ctlflags |= fl; 3960 return (fl); 3961 } 3962 } 3963 return (0); 3964} 3965 3966static int 3967hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3968{ 3969 struct hdac_widget *w, *cw; 3970 int i, child = 0; 3971 3972 if (depth > HDA_PARSE_MAXDEPTH) 3973 return (0); 3974 3975 w = hdac_widget_get(devinfo, nid); 3976 if (w == NULL || w->enable == 0) 3977 return (0); 3978 /*if (!(w->pflags & HDA_ADC_PATH)) 3979 return (0); 3980 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3981 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3982 return (0);*/ 3983 /* XXX weak! */ 3984 for (i = 0; i < w->nconns; i++) { 3985 cw = hdac_widget_get(devinfo, w->conns[i]); 3986 if (cw == NULL) 3987 continue; 3988 if (++child > 1) { 3989 w->pflags |= HDA_ADC_RECSEL; 3990 return (1); 3991 } 3992 } 3993 for (i = 0; i < w->nconns; i++) { 3994 if (hdac_audio_ctl_recsel_build(devinfo, 3995 w->conns[i], depth + 1) != 0) 3996 return (1); 3997 } 3998 return (0); 3999} 4000 4001static int 4002hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4003{ 4004 struct hdac_widget *w, *cw; 4005 int i, j, conndev, found_dac = 0; 4006 int strategy; 4007 4008 strategy = devinfo->function.audio.parsing_strategy; 4009 4010 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4011 w = hdac_widget_get(devinfo, i); 4012 if (w == NULL || w->enable == 0) 4013 continue; 4014 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4015 continue; 4016 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4017 continue; 4018 conndev = w->wclass.pin.config & 4019 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4020 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4021 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4022 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4023 continue; 4024 for (j = 0; j < w->nconns; j++) { 4025 cw = hdac_widget_get(devinfo, w->conns[j]); 4026 if (cw == NULL || cw->enable == 0) 4027 continue; 4028 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4029 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4030 cw->type == 4031 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4032 continue; 4033 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4034 != 0) { 4035 if (w->selconn == -1) 4036 w->selconn = j; 4037 w->pflags |= HDA_DAC_PATH; 4038 found_dac++; 4039 } 4040 } 4041 } 4042 4043 return (found_dac); 4044} 4045 4046static void 4047hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4048{ 4049 struct hdac_widget *w; 4050 struct hdac_audio_ctl *ctl; 4051 int i, j, dacs, strategy; 4052 4053 /* Construct DAC path */ 4054 strategy = HDA_PARSE_MIXER; 4055 devinfo->function.audio.parsing_strategy = strategy; 4056 HDA_BOOTVERBOSE( 4057 device_printf(devinfo->codec->sc->dev, 4058 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4059 HDA_WIDGET_PARSER_REV); 4060 ); 4061 dacs = hdac_audio_build_tree_strategy(devinfo); 4062 if (dacs == 0) { 4063 HDA_BOOTVERBOSE( 4064 device_printf(devinfo->codec->sc->dev, 4065 "HDA_DEBUG: HWiP: 0 DAC path found! " 4066 "Retrying parser " 4067 "using HDA_PARSE_DIRECT strategy.\n"); 4068 ); 4069 strategy = HDA_PARSE_DIRECT; 4070 devinfo->function.audio.parsing_strategy = strategy; 4071 dacs = hdac_audio_build_tree_strategy(devinfo); 4072 } 4073 4074 HDA_BOOTVERBOSE( 4075 device_printf(devinfo->codec->sc->dev, 4076 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4077 "strategy.\n", 4078 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4079 ); 4080 4081 /* Construct ADC path */ 4082 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4083 w = hdac_widget_get(devinfo, i); 4084 if (w == NULL || w->enable == 0) 4085 continue; 4086 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4087 continue; 4088 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4089 } 4090 4091 /* Output mixers */ 4092 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4093 w = hdac_widget_get(devinfo, i); 4094 if (w == NULL || w->enable == 0) 4095 continue; 4096 if ((strategy == HDA_PARSE_MIXER && 4097 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4098 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4099 && (w->pflags & HDA_DAC_PATH)) || 4100 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4101 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4102 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4103 w->nid, devinfo->startnode - 1, 0, 0); 4104 } else if (w->type == 4105 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4106 j = 0; 4107 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4108 NULL) { 4109 if (ctl->enable == 0 || ctl->widget == NULL) 4110 continue; 4111 if (ctl->widget->nid != w->nid) 4112 continue; 4113 ctl->ossmask |= SOUND_MASK_VOLUME; 4114 ctl->ossmask |= SOUND_MASK_SPEAKER; 4115 ctl->ossdev = SOUND_MIXER_SPEAKER; 4116 w->ctlflags |= SOUND_MASK_VOLUME; 4117 w->ctlflags |= SOUND_MASK_SPEAKER; 4118 } 4119 } 4120 } 4121 4122 /* Input mixers (rec) */ 4123 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4124 w = hdac_widget_get(devinfo, i); 4125 if (w == NULL || w->enable == 0) 4126 continue; 4127 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4128 w->pflags & HDA_ADC_PATH)) 4129 continue; 4130 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4131 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4132 } 4133} 4134 4135#define HDA_COMMIT_CONN (1 << 0) 4136#define HDA_COMMIT_CTRL (1 << 1) 4137#define HDA_COMMIT_EAPD (1 << 2) 4138#define HDA_COMMIT_GPIO (1 << 3) 4139#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4140 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4141 4142static void 4143hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4144{ 4145 struct hdac_softc *sc = devinfo->codec->sc; 4146 struct hdac_widget *w; 4147 nid_t cad; 4148 int i; 4149 4150 if (!(cfl & HDA_COMMIT_ALL)) 4151 return; 4152 4153 cad = devinfo->codec->cad; 4154 4155 if (cfl & HDA_COMMIT_GPIO) { 4156 uint32_t gdata, gmask, gdir; 4157 int commitgpio = 0; 4158 4159 gdata = 0; 4160 gmask = 0; 4161 gdir = 0; 4162 4163 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4164 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4165 0x7e7, 0), cad); 4166 4167 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4168 commitgpio = 1; 4169 else { 4170 for (i = 0; i < HDA_GPIO_MAX; i++) { 4171 if (!(devinfo->function.audio.quirks & 4172 (1 << i))) 4173 continue; 4174 if (commitgpio == 0) { 4175 commitgpio = 1; 4176 gdata = hdac_command(sc, 4177 HDA_CMD_GET_GPIO_DATA(cad, 4178 devinfo->nid), cad); 4179 gmask = hdac_command(sc, 4180 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4181 devinfo->nid), cad); 4182 gdir = hdac_command(sc, 4183 HDA_CMD_GET_GPIO_DIRECTION(cad, 4184 devinfo->nid), cad); 4185 HDA_BOOTVERBOSE( 4186 device_printf(sc->dev, 4187 "GPIO init: data=0x%08x " 4188 "mask=0x%08x dir=0x%08x\n", 4189 gdata, gmask, gdir); 4190 ); 4191 } 4192 gdata |= 1 << i; 4193 gmask |= 1 << i; 4194 gdir |= 1 << i; 4195 } 4196 } 4197 4198 if (commitgpio != 0) { 4199 HDA_BOOTVERBOSE( 4200 device_printf(sc->dev, 4201 "GPIO commit: data=0x%08x mask=0x%08x " 4202 "dir=0x%08x\n", 4203 gdata, gmask, gdir); 4204 ); 4205 hdac_command(sc, 4206 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4207 gmask), cad); 4208 hdac_command(sc, 4209 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4210 gdir), cad); 4211 hdac_command(sc, 4212 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4213 gdata), cad); 4214 } 4215 } 4216 4217 for (i = 0; i < devinfo->nodecnt; i++) { 4218 w = &devinfo->widget[i]; 4219 if (w == NULL || w->enable == 0) 4220 continue; 4221 if (cfl & HDA_COMMIT_CONN) { 4222 if (w->selconn == -1) 4223 w->selconn = 0; 4224 if (w->nconns > 0) 4225 hdac_widget_connection_select(w, w->selconn); 4226 } 4227 if ((cfl & HDA_COMMIT_CTRL) && 4228 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4229 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4230 (HDA_DAC_PATH | HDA_ADC_PATH)) 4231 device_printf(sc->dev, "WARNING: node %d " 4232 "participate both for DAC/ADC!\n", w->nid); 4233 if (w->pflags & HDA_DAC_PATH) { 4234 w->wclass.pin.ctrl &= 4235 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4236 if ((w->wclass.pin.config & 4237 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4238 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4239 w->wclass.pin.ctrl &= 4240 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4241 } else if (w->pflags & HDA_ADC_PATH) { 4242 w->wclass.pin.ctrl &= 4243 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4244 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4245 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4246 uint32_t pincap = w->wclass.pin.cap; 4247 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4248 w->wclass.pin.ctrl |= 4249 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4250 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4251 ); 4252 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4253 w->wclass.pin.ctrl |= 4254 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4255 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4256 ); 4257 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4258 w->wclass.pin.ctrl |= 4259 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4260 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4261 ); 4262 } 4263 } else 4264 w->wclass.pin.ctrl &= ~( 4265 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4266 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4267 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4268 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4269 hdac_command(sc, 4270 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4271 w->wclass.pin.ctrl), cad); 4272 } 4273 if ((cfl & HDA_COMMIT_EAPD) && 4274 w->param.eapdbtl != HDAC_INVALID) { 4275 uint32_t val; 4276 4277 val = w->param.eapdbtl; 4278 if (devinfo->function.audio.quirks & 4279 HDA_QUIRK_EAPDINV) 4280 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4281 hdac_command(sc, 4282 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4283 val), cad); 4284 4285 } 4286 DELAY(1000); 4287 } 4288} 4289 4290static void 4291hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4292{ 4293 struct hdac_softc *sc = devinfo->codec->sc; 4294 struct hdac_audio_ctl *ctl; 4295 int i; 4296 4297 devinfo->function.audio.mvol = 100 | (100 << 8); 4298 i = 0; 4299 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4300 if (ctl->enable == 0 || ctl->widget == NULL) { 4301 HDA_BOOTVERBOSE( 4302 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4303 i, (ctl->widget != NULL) ? 4304 ctl->widget->nid : -1); 4305 if (ctl->childwidget != NULL) 4306 printf(" childnid=%d", 4307 ctl->childwidget->nid); 4308 if (ctl->widget == NULL) 4309 printf(" NULL WIDGET!"); 4310 printf(" DISABLED\n"); 4311 ); 4312 continue; 4313 } 4314 HDA_BOOTVERBOSE( 4315 if (ctl->ossmask == 0) { 4316 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4317 i, ctl->widget->nid); 4318 if (ctl->childwidget != NULL) 4319 printf(" childnid=%d", 4320 ctl->childwidget->nid); 4321 printf(" Bind to NONE\n"); 4322 } 4323 ); 4324 if (ctl->step > 0) { 4325 ctl->ossval = (ctl->left * 100) / ctl->step; 4326 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4327 } else 4328 ctl->ossval = 0; 4329 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4330 ctl->left, ctl->right); 4331 } 4332} 4333 4334static int 4335hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4336{ 4337 struct hdac_chan *ch; 4338 struct hdac_widget *w; 4339 uint32_t cap, fmtcap, pcmcap, path; 4340 int i, type, ret, max; 4341 4342 if (dir == PCMDIR_PLAY) { 4343 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4344 ch = &devinfo->codec->sc->play; 4345 path = HDA_DAC_PATH; 4346 } else { 4347 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4348 ch = &devinfo->codec->sc->rec; 4349 path = HDA_ADC_PATH; 4350 } 4351 4352 ch->caps = hdac_caps; 4353 ch->caps.fmtlist = ch->fmtlist; 4354 ch->bit16 = 1; 4355 ch->bit32 = 0; 4356 ch->pcmrates[0] = 48000; 4357 ch->pcmrates[1] = 0; 4358 4359 ret = 0; 4360 fmtcap = devinfo->function.audio.supp_stream_formats; 4361 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4362 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4363 4364 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4365 w = hdac_widget_get(devinfo, i); 4366 if (w == NULL || w->enable == 0 || w->type != type || 4367 !(w->pflags & path)) 4368 continue; 4369 cap = w->param.widget_cap; 4370 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4371 continue;*/ 4372 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4373 continue; 4374 cap = w->param.supp_stream_formats; 4375 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4376 } 4377 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4378 }*/ 4379 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4380 continue; 4381 if (ret == 0) { 4382 fmtcap = w->param.supp_stream_formats; 4383 pcmcap = w->param.supp_pcm_size_rate; 4384 } else { 4385 fmtcap &= w->param.supp_stream_formats; 4386 pcmcap &= w->param.supp_pcm_size_rate; 4387 } 4388 ch->io[ret++] = i; 4389 } 4390 ch->io[ret] = -1; 4391 4392 ch->supp_stream_formats = fmtcap; 4393 ch->supp_pcm_size_rate = pcmcap; 4394 4395 /* 4396 * 8bit = 0 4397 * 16bit = 1 4398 * 20bit = 2 4399 * 24bit = 3 4400 * 32bit = 4 4401 */ 4402 if (ret > 0) { 4403 cap = pcmcap; 4404 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4405 ch->bit16 = 1; 4406 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4407 ch->bit16 = 0; 4408 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4409 ch->bit32 = 4; 4410 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4411 ch->bit32 = 3; 4412 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4413 ch->bit32 = 2; 4414 i = 0; 4415 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4416 ch->fmtlist[i++] = AFMT_S16_LE; 4417 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4418 if (ch->bit32 > 0) { 4419 if (!(devinfo->function.audio.quirks & 4420 HDA_QUIRK_FORCESTEREO)) 4421 ch->fmtlist[i++] = AFMT_S32_LE; 4422 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4423 } 4424 ch->fmtlist[i] = 0; 4425 i = 0; 4426 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4427 ch->pcmrates[i++] = 8000; 4428 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4429 ch->pcmrates[i++] = 11025; 4430 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4431 ch->pcmrates[i++] = 16000; 4432 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4433 ch->pcmrates[i++] = 22050; 4434 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4435 ch->pcmrates[i++] = 32000; 4436 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4437 ch->pcmrates[i++] = 44100; 4438 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4439 ch->pcmrates[i++] = 48000; 4440 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4441 ch->pcmrates[i++] = 88200; 4442 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4443 ch->pcmrates[i++] = 96000; 4444 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4445 ch->pcmrates[i++] = 176400; 4446 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4447 ch->pcmrates[i++] = 192000; 4448 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4449 ch->pcmrates[i] = 0; 4450 if (i > 0) { 4451 ch->caps.minspeed = ch->pcmrates[0]; 4452 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4453 } 4454 } 4455 4456 return (ret); 4457} 4458 4459static void 4460hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4461{ 4462 struct hdac_audio_ctl *ctl; 4463 struct hdac_softc *sc = devinfo->codec->sc; 4464 int i; 4465 uint32_t fl = 0; 4466 4467 4468 if (flag == 0) { 4469 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4470 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4471 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4472 } 4473 4474 i = 0; 4475 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4476 if (ctl->enable == 0 || ctl->widget == NULL || 4477 ctl->widget->enable == 0) 4478 continue; 4479 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4480 (flag != 0 && (ctl->ossmask & flag))) { 4481 if (banner != NULL) { 4482 device_printf(sc->dev, "\n"); 4483 device_printf(sc->dev, "%s\n", banner); 4484 } 4485 goto hdac_ctl_dump_it_all; 4486 } 4487 } 4488 4489 return; 4490 4491hdac_ctl_dump_it_all: 4492 i = 0; 4493 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4494 if (ctl->enable == 0 || ctl->widget == NULL || 4495 ctl->widget->enable == 0) 4496 continue; 4497 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4498 (flag != 0 && (ctl->ossmask & flag)))) 4499 continue; 4500 if (flag == 0) { 4501 device_printf(sc->dev, "\n"); 4502 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4503 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4504 } 4505 device_printf(sc->dev, " |\n"); 4506 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4507 ctl->widget->nid, ctl->index); 4508 if (ctl->childwidget != NULL) 4509 printf("(nid: %2d) ", ctl->childwidget->nid); 4510 else 4511 printf(" "); 4512 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4513 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4514 ctl->ossmask); 4515 } 4516} 4517 4518static void 4519hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4520{ 4521 uint32_t cap; 4522 4523 cap = fcap; 4524 if (cap != 0) { 4525 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4526 device_printf(sc->dev, " Format:"); 4527 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4528 printf(" AC3"); 4529 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4530 printf(" FLOAT32"); 4531 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4532 printf(" PCM"); 4533 printf("\n"); 4534 } 4535 cap = pcmcap; 4536 if (cap != 0) { 4537 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4538 device_printf(sc->dev, " PCM size:"); 4539 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4540 printf(" 8"); 4541 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4542 printf(" 16"); 4543 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4544 printf(" 20"); 4545 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4546 printf(" 24"); 4547 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4548 printf(" 32"); 4549 printf("\n"); 4550 device_printf(sc->dev, " PCM rate:"); 4551 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4552 printf(" 8"); 4553 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4554 printf(" 11"); 4555 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4556 printf(" 16"); 4557 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4558 printf(" 22"); 4559 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4560 printf(" 32"); 4561 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4562 printf(" 44"); 4563 printf(" 48"); 4564 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4565 printf(" 88"); 4566 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4567 printf(" 96"); 4568 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4569 printf(" 176"); 4570 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4571 printf(" 192"); 4572 printf("\n"); 4573 } 4574} 4575 4576static void 4577hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4578{ 4579 uint32_t pincap, wcap; 4580 4581 pincap = w->wclass.pin.cap; 4582 wcap = w->param.widget_cap; 4583 4584 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4585 device_printf(sc->dev, " "); 4586 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4587 printf(" ISC"); 4588 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4589 printf(" TRQD"); 4590 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4591 printf(" PDC"); 4592 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4593 printf(" HP"); 4594 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4595 printf(" OUT"); 4596 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4597 printf(" IN"); 4598 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4599 printf(" BAL"); 4600 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4601 printf(" VREF["); 4602 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4603 printf(" 50"); 4604 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4605 printf(" 80"); 4606 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4607 printf(" 100"); 4608 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4609 printf(" GROUND"); 4610 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4611 printf(" HIZ"); 4612 printf(" ]"); 4613 } 4614 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4615 printf(" EAPD"); 4616 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4617 printf(" : UNSOL"); 4618 printf("\n"); 4619 device_printf(sc->dev, " Pin config: 0x%08x\n", 4620 w->wclass.pin.config); 4621 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4622 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4623 printf(" HP"); 4624 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4625 printf(" IN"); 4626 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4627 printf(" OUT"); 4628 printf("\n"); 4629} 4630 4631static void 4632hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4633{ 4634 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4635 device_printf(sc->dev, " " 4636 "mute=%d step=%d size=%d offset=%d\n", 4637 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4638 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4639 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4640 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4641} 4642 4643static void 4644hdac_dump_nodes(struct hdac_devinfo *devinfo) 4645{ 4646 struct hdac_softc *sc = devinfo->codec->sc; 4647 struct hdac_widget *w, *cw; 4648 int i, j; 4649 4650 device_printf(sc->dev, "\n"); 4651 device_printf(sc->dev, "Default Parameter\n"); 4652 device_printf(sc->dev, "-----------------\n"); 4653 hdac_dump_audio_formats(sc, 4654 devinfo->function.audio.supp_stream_formats, 4655 devinfo->function.audio.supp_pcm_size_rate); 4656 device_printf(sc->dev, " IN amp: 0x%08x\n", 4657 devinfo->function.audio.inamp_cap); 4658 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4659 devinfo->function.audio.outamp_cap); 4660 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4661 w = hdac_widget_get(devinfo, i); 4662 if (w == NULL) { 4663 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4664 continue; 4665 } 4666 device_printf(sc->dev, "\n"); 4667 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4668 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4669 "DIGITAL" : "ANALOG", 4670 (w->enable == 0) ? " [DISABLED]" : ""); 4671 device_printf(sc->dev, " name: %s\n", w->name); 4672 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4673 w->param.widget_cap); 4674 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4675 w->pflags); 4676 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4677 w->ctlflags); 4678 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4679 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4680 hdac_dump_audio_formats(sc, 4681 w->param.supp_stream_formats, 4682 w->param.supp_pcm_size_rate); 4683 } else if (w->type == 4684 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4685 hdac_dump_pin(sc, w); 4686 if (w->param.eapdbtl != HDAC_INVALID) 4687 device_printf(sc->dev, " EAPD: 0x%08x\n", 4688 w->param.eapdbtl); 4689 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4690 w->param.outamp_cap != 0) 4691 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4692 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4693 w->param.inamp_cap != 0) 4694 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4695 device_printf(sc->dev, " connections: %d\n", w->nconns); 4696 for (j = 0; j < w->nconns; j++) { 4697 cw = hdac_widget_get(devinfo, w->conns[j]); 4698 device_printf(sc->dev, " |\n"); 4699 device_printf(sc->dev, " + <- nid=%d [%s]", 4700 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4701 if (cw == NULL) 4702 printf(" [UNKNOWN]"); 4703 else if (cw->enable == 0) 4704 printf(" [DISABLED]"); 4705 if (w->nconns > 1 && w->selconn == j && w->type != 4706 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4707 printf(" (selected)"); 4708 printf("\n"); 4709 } 4710 } 4711 4712} 4713 4714static int 4715hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4716{ 4717 struct hdac_widget *w, *cw; 4718 struct hdac_softc *sc = devinfo->codec->sc; 4719 int i; 4720 4721 if (depth > HDA_PARSE_MAXDEPTH) 4722 return (0); 4723 4724 w = hdac_widget_get(devinfo, nid); 4725 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4726 return (0); 4727 4728 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4729 device_printf(sc->dev, "\n"); 4730 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4731 device_printf(sc->dev, " ^\n"); 4732 device_printf(sc->dev, " |\n"); 4733 device_printf(sc->dev, " +-----<------+\n"); 4734 } else { 4735 device_printf(sc->dev, " ^\n"); 4736 device_printf(sc->dev, " |\n"); 4737 device_printf(sc->dev, " "); 4738 printf(" nid=%d [%s]\n", w->nid, w->name); 4739 } 4740 4741 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4742 return (1); 4743 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4744 for (i = 0; i < w->nconns; i++) { 4745 cw = hdac_widget_get(devinfo, w->conns[i]); 4746 if (cw == NULL || cw->enable == 0 || cw->type == 4747 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4748 continue; 4749 if (hdac_dump_dac_internal(devinfo, cw->nid, 4750 depth + 1) != 0) 4751 return (1); 4752 } 4753 } else if ((w->type == 4754 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4755 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4756 w->selconn > -1 && w->selconn < w->nconns) { 4757 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4758 depth + 1) != 0) 4759 return (1); 4760 } 4761 4762 return (0); 4763} 4764 4765static void 4766hdac_dump_dac(struct hdac_devinfo *devinfo) 4767{ 4768 struct hdac_widget *w; 4769 struct hdac_softc *sc = devinfo->codec->sc; 4770 int i, printed = 0; 4771 4772 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4773 w = hdac_widget_get(devinfo, i); 4774 if (w == NULL || w->enable == 0) 4775 continue; 4776 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4777 !(w->pflags & HDA_DAC_PATH)) 4778 continue; 4779 if (printed == 0) { 4780 printed = 1; 4781 device_printf(sc->dev, "\n"); 4782 device_printf(sc->dev, "Playback path:\n"); 4783 } 4784 hdac_dump_dac_internal(devinfo, w->nid, 0); 4785 } 4786} 4787 4788static void 4789hdac_dump_adc(struct hdac_devinfo *devinfo) 4790{ 4791 struct hdac_widget *w, *cw; 4792 struct hdac_softc *sc = devinfo->codec->sc; 4793 int i, j; 4794 int printed = 0; 4795 char ossdevs[256]; 4796 4797 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4798 w = hdac_widget_get(devinfo, i); 4799 if (w == NULL || w->enable == 0) 4800 continue; 4801 if (!(w->pflags & HDA_ADC_RECSEL)) 4802 continue; 4803 if (printed == 0) { 4804 printed = 1; 4805 device_printf(sc->dev, "\n"); 4806 device_printf(sc->dev, "Recording sources:\n"); 4807 } 4808 device_printf(sc->dev, "\n"); 4809 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4810 for (j = 0; j < w->nconns; j++) { 4811 cw = hdac_widget_get(devinfo, w->conns[j]); 4812 if (cw == NULL || cw->enable == 0) 4813 continue; 4814 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4815 ossdevs, sizeof(ossdevs)); 4816 device_printf(sc->dev, " |\n"); 4817 device_printf(sc->dev, " + <- nid=%d [%s]", 4818 cw->nid, cw->name); 4819 if (strlen(ossdevs) > 0) { 4820 printf(" [recsrc: %s]", ossdevs); 4821 } 4822 printf("\n"); 4823 } 4824 } 4825} 4826 4827static void 4828hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4829{ 4830 nid_t *nids; 4831 4832 if (pcnt > 0) { 4833 device_printf(sc->dev, "\n"); 4834 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4835 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4836 sc->play.supp_pcm_size_rate); 4837 device_printf(sc->dev, " DAC:"); 4838 for (nids = sc->play.io; *nids != -1; nids++) 4839 printf(" %d", *nids); 4840 printf("\n"); 4841 } 4842 4843 if (rcnt > 0) { 4844 device_printf(sc->dev, "\n"); 4845 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4846 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4847 sc->rec.supp_pcm_size_rate); 4848 device_printf(sc->dev, " ADC:"); 4849 for (nids = sc->rec.io; *nids != -1; nids++) 4850 printf(" %d", *nids); 4851 printf("\n"); 4852 } 4853} 4854 4855static void 4856hdac_release_resources(struct hdac_softc *sc) 4857{ 4858 struct hdac_devinfo *devinfo = NULL; 4859 device_t *devlist = NULL; 4860 int i, devcount; 4861 4862 if (sc == NULL) 4863 return; 4864 4865 hdac_lock(sc); 4866 if (sc->polling != 0) 4867 callout_stop(&sc->poll_hdac); 4868 hdac_reset(sc); 4869 hdac_unlock(sc); 4870 snd_mtxfree(sc->lock); 4871 4872 device_get_children(sc->dev, &devlist, &devcount); 4873 for (i = 0; devlist != NULL && i < devcount; i++) { 4874 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4875 if (devinfo == NULL) 4876 continue; 4877 if (devinfo->widget != NULL) 4878 free(devinfo->widget, M_HDAC); 4879 if (devinfo->node_type == 4880 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4881 devinfo->function.audio.ctl != NULL) 4882 free(devinfo->function.audio.ctl, M_HDAC); 4883 free(devinfo, M_HDAC); 4884 device_delete_child(sc->dev, devlist[i]); 4885 } 4886 if (devlist != NULL) 4887 free(devlist, M_TEMP); 4888 4889 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4890 if (sc->codecs[i] != NULL) 4891 free(sc->codecs[i], M_HDAC); 4892 sc->codecs[i] = NULL; 4893 } 4894 4895 hdac_dma_free(&sc->rirb_dma); 4896 hdac_dma_free(&sc->corb_dma); 4897 if (sc->play.blkcnt > 0) 4898 hdac_dma_free(&sc->play.bdl_dma); 4899 if (sc->rec.blkcnt > 0) 4900 hdac_dma_free(&sc->rec.bdl_dma); 4901 hdac_irq_free(sc); 4902 hdac_mem_free(sc); 4903 free(sc, M_DEVBUF); 4904 4905} 4906 4907/* This function surely going to make its way into upper level someday. */ 4908static void 4909hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4910{ 4911 const char *res = NULL; 4912 int i = 0, j, k, len, inv; 4913 4914 if (on != NULL) 4915 *on = 0; 4916 if (off != NULL) 4917 *off = 0; 4918 if (sc == NULL) 4919 return; 4920 if (resource_string_value(device_get_name(sc->dev), 4921 device_get_unit(sc->dev), "config", &res) != 0) 4922 return; 4923 if (!(res != NULL && strlen(res) > 0)) 4924 return; 4925 HDA_BOOTVERBOSE( 4926 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4927 ); 4928 for (;;) { 4929 while (res[i] != '\0' && 4930 (res[i] == ',' || isspace(res[i]) != 0)) 4931 i++; 4932 if (res[i] == '\0') { 4933 HDA_BOOTVERBOSE( 4934 printf("\n"); 4935 ); 4936 return; 4937 } 4938 j = i; 4939 while (res[j] != '\0' && 4940 !(res[j] == ',' || isspace(res[j]) != 0)) 4941 j++; 4942 len = j - i; 4943 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4944 inv = 2; 4945 else 4946 inv = 0; 4947 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4948 if (strncmp(res + i + inv, 4949 hdac_quirks_tab[k].key, len - inv) != 0) 4950 continue; 4951 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4952 break; 4953 HDA_BOOTVERBOSE( 4954 printf(" %s%s", (inv != 0) ? "no" : "", 4955 hdac_quirks_tab[k].key); 4956 ); 4957 if (inv == 0 && on != NULL) 4958 *on |= hdac_quirks_tab[k].value; 4959 else if (inv != 0 && off != NULL) 4960 *off |= hdac_quirks_tab[k].value; 4961 break; 4962 } 4963 i = j; 4964 } 4965} 4966 4967#ifdef SND_DYNSYSCTL 4968static int 4969sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4970{ 4971 struct hdac_softc *sc; 4972 struct hdac_devinfo *devinfo; 4973 device_t dev; 4974 uint32_t ctl; 4975 int err, val; 4976 4977 dev = oidp->oid_arg1; 4978 devinfo = pcm_getdevinfo(dev); 4979 if (devinfo == NULL || devinfo->codec == NULL || 4980 devinfo->codec->sc == NULL) 4981 return (EINVAL); 4982 sc = devinfo->codec->sc; 4983 hdac_lock(sc); 4984 val = sc->polling; 4985 hdac_unlock(sc); 4986 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4987 4988 if (err || req->newptr == NULL) 4989 return (err); 4990 if (val < 0 || val > 1) 4991 return (EINVAL); 4992 4993 hdac_lock(sc); 4994 if (val != sc->polling) { 4995 if (hda_chan_active(sc) != 0) 4996 err = EBUSY; 4997 else if (val == 0) { 4998 callout_stop(&sc->poll_hdac); 4999 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5000 sc->rirb_size / 2); 5001 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5002 ctl |= HDAC_RIRBCTL_RINTCTL; 5003 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5004 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5005 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5006 sc->polling = 0; 5007 DELAY(1000); 5008 } else { 5009 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5010 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5011 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5012 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5013 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5014 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5015 sc); 5016 sc->polling = 1; 5017 DELAY(1000); 5018 } 5019 } 5020 hdac_unlock(sc); 5021 5022 return (err); 5023} 5024#endif 5025 5026static void 5027hdac_attach2(void *arg) 5028{ 5029 struct hdac_softc *sc; 5030 struct hdac_widget *w; 5031 struct hdac_audio_ctl *ctl; 5032 uint32_t quirks_on, quirks_off; 5033 int pcnt, rcnt; 5034 int i; 5035 char status[SND_STATUSLEN]; 5036 device_t *devlist = NULL; 5037 int devcount; 5038 struct hdac_devinfo *devinfo = NULL; 5039 5040 sc = (struct hdac_softc *)arg; 5041 5042 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5043 5044 HDA_BOOTVERBOSE( 5045 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5046 quirks_on, quirks_off); 5047 ); 5048 5049 hdac_lock(sc); 5050 5051 /* Remove ourselves from the config hooks */ 5052 if (sc->intrhook.ich_func != NULL) { 5053 config_intrhook_disestablish(&sc->intrhook); 5054 sc->intrhook.ich_func = NULL; 5055 } 5056 5057 /* Start the corb and rirb engines */ 5058 HDA_BOOTVERBOSE( 5059 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5060 ); 5061 hdac_corb_start(sc); 5062 HDA_BOOTVERBOSE( 5063 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5064 ); 5065 hdac_rirb_start(sc); 5066 5067 HDA_BOOTVERBOSE( 5068 device_printf(sc->dev, 5069 "HDA_DEBUG: Enabling controller interrupt...\n"); 5070 ); 5071 if (sc->polling == 0) 5072 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5073 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5074 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5075 HDAC_GCTL_UNSOL); 5076 5077 DELAY(1000); 5078 5079 HDA_BOOTVERBOSE( 5080 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5081 ); 5082 hdac_scan_codecs(sc); 5083 5084 device_get_children(sc->dev, &devlist, &devcount); 5085 for (i = 0; devlist != NULL && i < devcount; i++) { 5086 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5087 if (devinfo != NULL && devinfo->node_type == 5088 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5089 break; 5090 } else 5091 devinfo = NULL; 5092 } 5093 if (devlist != NULL) 5094 free(devlist, M_TEMP); 5095 5096 if (devinfo == NULL) { 5097 hdac_unlock(sc); 5098 device_printf(sc->dev, "Audio Function Group not found!\n"); 5099 hdac_release_resources(sc); 5100 return; 5101 } 5102 5103 HDA_BOOTVERBOSE( 5104 device_printf(sc->dev, 5105 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5106 devinfo->nid, devinfo->codec->cad); 5107 ); 5108 hdac_audio_parse(devinfo); 5109 HDA_BOOTVERBOSE( 5110 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5111 ); 5112 hdac_audio_ctl_parse(devinfo); 5113 HDA_BOOTVERBOSE( 5114 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5115 ); 5116 hdac_vendor_patch_parse(devinfo); 5117 if (quirks_on != 0) 5118 devinfo->function.audio.quirks |= quirks_on; 5119 if (quirks_off != 0) 5120 devinfo->function.audio.quirks &= ~quirks_off; 5121 5122 /* XXX Disable all DIGITAL path. */ 5123 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5124 w = hdac_widget_get(devinfo, i); 5125 if (w == NULL) 5126 continue; 5127 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5128 w->enable = 0; 5129 continue; 5130 } 5131 /* XXX Disable useless pin ? */ 5132 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5133 (w->wclass.pin.config & 5134 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5135 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5136 w->enable = 0; 5137 } 5138 i = 0; 5139 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5140 if (ctl->widget == NULL) 5141 continue; 5142 w = ctl->widget; 5143 if (w->enable == 0) 5144 ctl->enable = 0; 5145 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5146 ctl->enable = 0; 5147 w = ctl->childwidget; 5148 if (w == NULL) 5149 continue; 5150 if (w->enable == 0 || 5151 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5152 ctl->enable = 0; 5153 } 5154 5155 HDA_BOOTVERBOSE( 5156 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5157 ); 5158 hdac_audio_build_tree(devinfo); 5159 5160 HDA_BOOTVERBOSE( 5161 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5162 ); 5163 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5164 HDA_BOOTVERBOSE( 5165 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5166 ); 5167 hdac_audio_ctl_commit(devinfo); 5168 5169 HDA_BOOTVERBOSE( 5170 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5171 ); 5172 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5173 HDA_BOOTVERBOSE( 5174 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5175 ); 5176 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5177 5178 hdac_unlock(sc); 5179 HDA_BOOTVERBOSE( 5180 device_printf(sc->dev, 5181 "HDA_DEBUG: OSS mixer initialization...\n"); 5182 ); 5183 5184 /* 5185 * There is no point of return after this. If the driver failed, 5186 * so be it. Let the detach procedure do all the cleanup. 5187 */ 5188 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5189 device_printf(sc->dev, "Can't register mixer\n"); 5190 5191 if (pcnt > 0) 5192 pcnt = 1; 5193 if (rcnt > 0) 5194 rcnt = 1; 5195 5196 HDA_BOOTVERBOSE( 5197 device_printf(sc->dev, 5198 "HDA_DEBUG: Registering PCM channels...\n"); 5199 ); 5200 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5201 device_printf(sc->dev, "Can't register PCM\n"); 5202 5203 sc->registered++; 5204 5205 for (i = 0; i < pcnt; i++) 5206 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5207 for (i = 0; i < rcnt; i++) 5208 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5209 5210#ifdef SND_DYNSYSCTL 5211 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5212 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5213 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5214 sysctl_hdac_polling, "I", "Enable polling mode"); 5215#endif 5216 5217 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5218 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5219 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5220 pcm_setstatus(sc->dev, status); 5221 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5222 HDA_BOOTVERBOSE( 5223 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5224 hdac_codec_id(devinfo)); 5225 ); 5226 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5227 HDA_DRV_TEST_REV); 5228 5229 HDA_BOOTVERBOSE( 5230 if (devinfo->function.audio.quirks != 0) { 5231 device_printf(sc->dev, "\n"); 5232 device_printf(sc->dev, "HDA config/quirks:"); 5233 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5234 if (devinfo->function.audio.quirks & 5235 hdac_quirks_tab[i].value) 5236 printf(" %s", hdac_quirks_tab[i].key); 5237 } 5238 printf("\n"); 5239 } 5240 device_printf(sc->dev, "\n"); 5241 device_printf(sc->dev, "+-------------------+\n"); 5242 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5243 device_printf(sc->dev, "+-------------------+\n"); 5244 hdac_dump_nodes(devinfo); 5245 device_printf(sc->dev, "\n"); 5246 device_printf(sc->dev, "+------------------------+\n"); 5247 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5248 device_printf(sc->dev, "+------------------------+\n"); 5249 device_printf(sc->dev, "\n"); 5250 i = 0; 5251 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5252 device_printf(sc->dev, "%3d: nid=%d", i, 5253 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5254 if (ctl->childwidget != NULL) 5255 printf(" cnid=%d", ctl->childwidget->nid); 5256 printf(" dir=0x%x index=%d " 5257 "ossmask=0x%08x ossdev=%d%s\n", 5258 ctl->dir, ctl->index, 5259 ctl->ossmask, ctl->ossdev, 5260 (ctl->enable == 0) ? " [DISABLED]" : ""); 5261 } 5262 device_printf(sc->dev, "\n"); 5263 device_printf(sc->dev, "+-----------------------------------+\n"); 5264 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5265 device_printf(sc->dev, "+-----------------------------------+\n"); 5266 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5267 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5268 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5269 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5270 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5271 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5272 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5273 hdac_dump_ctls(devinfo, NULL, 0); 5274 hdac_dump_dac(devinfo); 5275 hdac_dump_adc(devinfo); 5276 device_printf(sc->dev, "\n"); 5277 device_printf(sc->dev, "+--------------------------------------+\n"); 5278 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5279 device_printf(sc->dev, "+--------------------------------------+\n"); 5280 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5281 ); 5282 5283 if (sc->polling != 0) { 5284 hdac_lock(sc); 5285 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5286 hdac_unlock(sc); 5287 } 5288} 5289 5290/**************************************************************************** 5291 * int hdac_detach(device_t) 5292 * 5293 * Detach and free up resources utilized by the hdac device. 5294 ****************************************************************************/ 5295static int 5296hdac_detach(device_t dev) 5297{ 5298 struct hdac_softc *sc = NULL; 5299 struct hdac_devinfo *devinfo = NULL; 5300 int err; 5301 5302 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5303 if (devinfo != NULL && devinfo->codec != NULL) 5304 sc = devinfo->codec->sc; 5305 if (sc == NULL) 5306 return (0); 5307 5308 if (sc->registered > 0) { 5309 err = pcm_unregister(dev); 5310 if (err != 0) 5311 return (err); 5312 } 5313 5314 hdac_release_resources(sc); 5315 5316 return (0); 5317} 5318 5319static device_method_t hdac_methods[] = { 5320 /* device interface */ 5321 DEVMETHOD(device_probe, hdac_probe), 5322 DEVMETHOD(device_attach, hdac_attach), 5323 DEVMETHOD(device_detach, hdac_detach), 5324 { 0, 0 } 5325}; 5326 5327static driver_t hdac_driver = { 5328 "pcm", 5329 hdac_methods, 5330 PCM_SOFTC_SIZE, 5331}; 5332 5333DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5334MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5335MODULE_VERSION(snd_hda, 1); 5336