hdac.c revision 165281
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061210_0037" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 165281 2006-12-16 09:14:58Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 172#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 173/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 174#define HP_NX6325_SUBVENDORX 0x103c30b0 175 176/* Dell */ 177#define DELL_VENDORID 0x1028 178#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 179#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 180#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 181 182/* Clevo */ 183#define CLEVO_VENDORID 0x1558 184#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 185#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 186 187/* Acer */ 188#define ACER_VENDORID 0x1025 189#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 190 191/* Asus */ 192#define ASUS_VENDORID 0x1043 193#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 194#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 195#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 196#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 197#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 198#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 199 200/* IBM / Lenovo */ 201#define IBM_VENDORID 0x1014 202#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 203#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 204 205/* Lenovo */ 206#define LENOVO_VENDORID 0x17aa 207#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 208#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 209 210/* Samsung */ 211#define SAMSUNG_VENDORID 0x144d 212#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 213#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 214 215/* Medion ? */ 216#define MEDION_VENDORID 0x161f 217#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 218#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 219 220/* 221 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 222 * instead of their own, which is beyond my comprehension 223 * (see HDA_CODEC_STAC9221 below). 224 */ 225#define APPLE_INTEL_MAC 0x76808384 226 227/* LG Electronics */ 228#define LG_VENDORID 0x1854 229#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 230#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 231 232/* Misc constants.. */ 233#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 234#define HDA_AMP_MUTE_NONE (0) 235#define HDA_AMP_MUTE_LEFT (1 << 0) 236#define HDA_AMP_MUTE_RIGHT (1 << 1) 237#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 238 239#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 240#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 241 242#define HDA_DAC_PATH (1 << 0) 243#define HDA_ADC_PATH (1 << 1) 244#define HDA_ADC_RECSEL (1 << 2) 245 246#define HDA_CTL_OUT (1 << 0) 247#define HDA_CTL_IN (1 << 1) 248#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 249 250#define HDA_GPIO_MAX 15 251/* 0 - 14 = GPIO */ 252#define HDA_QUIRK_GPIO0 (1 << 0) 253#define HDA_QUIRK_GPIO1 (1 << 1) 254#define HDA_QUIRK_GPIO2 (1 << 2) 255#define HDA_QUIRK_GPIOFLUSH (1 << 15) 256#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 257#define HDA_QUIRK_FIXEDRATE (1 << 17) 258#define HDA_QUIRK_FORCESTEREO (1 << 18) 259#define HDA_QUIRK_EAPDINV (1 << 19) 260#define HDA_QUIRK_VREF (1 << 20) 261 262static const struct { 263 char *key; 264 uint32_t value; 265} hdac_quirks_tab[] = { 266 { "gpio0", HDA_QUIRK_GPIO0 }, 267 { "gpio1", HDA_QUIRK_GPIO1 }, 268 { "gpio2", HDA_QUIRK_GPIO2 }, 269 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 270 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 271 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 272 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 273 { "eapdinv", HDA_QUIRK_EAPDINV }, 274 { "vref", HDA_QUIRK_VREF }, 275}; 276#define HDAC_QUIRKS_TAB_LEN \ 277 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 278 279#define HDA_BDL_MIN 2 280#define HDA_BDL_MAX 256 281#define HDA_BDL_DEFAULT HDA_BDL_MIN 282 283#define HDA_BUFSZ_MIN 4096 284#define HDA_BUFSZ_MAX 65536 285#define HDA_BUFSZ_DEFAULT 16384 286 287#define HDA_PARSE_MAXDEPTH 10 288 289#define HDAC_UNSOLTAG_EVENT_HP 0x00 290 291MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 292 293enum { 294 HDA_PARSE_MIXER, 295 HDA_PARSE_DIRECT 296}; 297 298/* Default */ 299static uint32_t hdac_fmt[] = { 300 AFMT_STEREO | AFMT_S16_LE, 301 0 302}; 303 304static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 305 306static const struct { 307 uint32_t model; 308 char *desc; 309} hdac_devices[] = { 310 { HDA_INTEL_82801F, "Intel 82801F" }, 311 { HDA_INTEL_82801G, "Intel 82801G" }, 312 { HDA_INTEL_82801H, "Intel 82801H" }, 313 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 314 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 315 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 316 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 317 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 318 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 319 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 320 { HDA_ATI_SB450, "ATI SB450" }, 321 { HDA_ATI_SB600, "ATI SB600" }, 322 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 323 { HDA_SIS_966, "SiS 966" }, 324 /* Unknown */ 325 { HDA_INTEL_ALL, "Intel (Unknown)" }, 326 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 327 { HDA_ATI_ALL, "ATI (Unknown)" }, 328 { HDA_VIA_ALL, "VIA (Unknown)" }, 329 { HDA_SIS_ALL, "SiS (Unknown)" }, 330}; 331#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 332 333static const struct { 334 uint32_t rate; 335 int valid; 336 uint16_t base; 337 uint16_t mul; 338 uint16_t div; 339} hda_rate_tab[] = { 340 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 341 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 342 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 343 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 344 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 345 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 346 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 347 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 348 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 349 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 350 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 351 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 352 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 353 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 354 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 355 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 356 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 357 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 358 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 359 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 360 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 361 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 362 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 363 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 364 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 365 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 366 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 367 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 368 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 369 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 370 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 371 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 372 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 373 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 374 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 375}; 376#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 377 378/* All codecs you can eat... */ 379#define HDA_CODEC_CONSTRUCT(vendor, id) \ 380 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 381 382/* Realtek */ 383#define REALTEK_VENDORID 0x10ec 384#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 385#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 386#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 387#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 388#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 389#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 390 391/* Analog Device */ 392#define ANALOGDEVICE_VENDORID 0x11d4 393#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 394#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 395#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 396#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 397 398/* CMedia */ 399#define CMEDIA_VENDORID 0x434d 400#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 401#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 402 403/* Sigmatel */ 404#define SIGMATEL_VENDORID 0x8384 405#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 406#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 407#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 408#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 409#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 410 411/* 412 * Conexant 413 * 414 * Ok, the truth is, I don't have any idea at all whether 415 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 416 * place that tell me it is "Venice" is from its Windows driver INF. 417 * 418 * Venice - CX????? 419 * Waikiki - CX20551-22 420 */ 421#define CONEXANT_VENDORID 0x14f1 422#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 423#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 424#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 425 426 427/* Codecs */ 428static const struct { 429 uint32_t id; 430 char *name; 431} hdac_codecs[] = { 432 { HDA_CODEC_ALC260, "Realtek ALC260" }, 433 { HDA_CODEC_ALC861, "Realtek ALC861" }, 434 { HDA_CODEC_ALC880, "Realtek ALC880" }, 435 { HDA_CODEC_ALC882, "Realtek ALC882" }, 436 { HDA_CODEC_ALC883, "Realtek ALC883" }, 437 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 438 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 439 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 440 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 441 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 442 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 443 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 444 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 445 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 446 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 447 /* Unknown codec */ 448 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 449 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 450 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 451 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 452 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 453}; 454#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 455 456enum { 457 HDAC_HP_SWITCH_CTL, 458 HDAC_HP_SWITCH_CTRL 459}; 460 461static const struct { 462 uint32_t model; 463 uint32_t id; 464 int type; 465 int inverted; 466 nid_t hpnid; 467 nid_t spkrnid[8]; 468 nid_t eapdnid; 469} hdac_hp_switch[] = { 470 /* Specific OEM models */ 471 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 472 17, { 16, -1 }, 16 }, 473 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 474 6, { 5, -1 }, 5 }, 475 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 476 6, { 5, -1 }, 5 }, 477 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 478 6, { 5, -1 }, 5 }, 479 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 480 13, { 14, -1 }, -1 }, 481 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 482 13, { 14, -1 }, -1 }, 483 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 484 10, { 13, -1 }, -1 }, 485 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 486 26, { 27, -1 }, -1 }, 487 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 488 27, { 20, -1 }, -1 }, 489 /* 490 * All models that at least come from the same vendor with 491 * simmilar codec. 492 */ 493 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 494 17, { 16, -1 }, 16 }, 495 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 496 6, { 5, -1 }, 5 }, 497 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 498 13, { 14, -1 }, -1 }, 499 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 500 26, { 27, -1 }, -1 }, 501}; 502#define HDAC_HP_SWITCH_LEN \ 503 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 504 505static const struct { 506 uint32_t model; 507 uint32_t id; 508 nid_t eapdnid; 509 int hp_switch; 510} hdac_eapd_switch[] = { 511 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 512 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 513 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 514}; 515#define HDAC_EAPD_SWITCH_LEN \ 516 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 517 518/**************************************************************************** 519 * Function prototypes 520 ****************************************************************************/ 521static void hdac_intr_handler(void *); 522static int hdac_reset(struct hdac_softc *); 523static int hdac_get_capabilities(struct hdac_softc *); 524static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 525static int hdac_dma_alloc(struct hdac_softc *, 526 struct hdac_dma *, bus_size_t); 527static void hdac_dma_free(struct hdac_dma *); 528static int hdac_mem_alloc(struct hdac_softc *); 529static void hdac_mem_free(struct hdac_softc *); 530static int hdac_irq_alloc(struct hdac_softc *); 531static void hdac_irq_free(struct hdac_softc *); 532static void hdac_corb_init(struct hdac_softc *); 533static void hdac_rirb_init(struct hdac_softc *); 534static void hdac_corb_start(struct hdac_softc *); 535static void hdac_rirb_start(struct hdac_softc *); 536static void hdac_scan_codecs(struct hdac_softc *); 537static int hdac_probe_codec(struct hdac_codec *); 538static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 539static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 540 541static void hdac_attach2(void *); 542 543static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 544 uint32_t, int); 545static void hdac_command_send_internal(struct hdac_softc *, 546 struct hdac_command_list *, int); 547 548static int hdac_probe(device_t); 549static int hdac_attach(device_t); 550static int hdac_detach(device_t); 551static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 552static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 553 uint32_t, int, int); 554static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 555 nid_t, int, int); 556static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 557 nid_t, nid_t, int, int, int, int, int, int); 558static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 559static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 560 561static int hdac_rirb_flush(struct hdac_softc *sc); 562static int hdac_unsolq_flush(struct hdac_softc *sc); 563 564#define hdac_command(a1, a2, a3) \ 565 hdac_command_sendone_internal(a1, a2, a3) 566 567#define hdac_codec_id(d) \ 568 ((uint32_t)((d == NULL) ? 0x00000000 : \ 569 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 570 ((uint32_t)(d)->device_id & 0x0000ffff)))) 571 572static char * 573hdac_codec_name(struct hdac_devinfo *devinfo) 574{ 575 uint32_t id; 576 int i; 577 578 id = hdac_codec_id(devinfo); 579 580 for (i = 0; i < HDAC_CODECS_LEN; i++) { 581 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 582 return (hdac_codecs[i].name); 583 } 584 585 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 586} 587 588static char * 589hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 590{ 591 static char *ossname[] = SOUND_DEVICE_NAMES; 592 static char *unknown = "???"; 593 int i; 594 595 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 596 if (devmask & (1 << i)) 597 return (ossname[i]); 598 } 599 return (unknown); 600} 601 602static void 603hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 604{ 605 static char *ossname[] = SOUND_DEVICE_NAMES; 606 int i, first = 1; 607 608 bzero(buf, len); 609 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 610 if (mask & (1 << i)) { 611 if (first == 0) 612 strlcat(buf, ", ", len); 613 strlcat(buf, ossname[i], len); 614 first = 0; 615 } 616 } 617} 618 619static struct hdac_audio_ctl * 620hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 621{ 622 if (devinfo == NULL || 623 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 624 index == NULL || devinfo->function.audio.ctl == NULL || 625 devinfo->function.audio.ctlcnt < 1 || 626 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 627 return (NULL); 628 return (&devinfo->function.audio.ctl[(*index)++]); 629} 630 631static struct hdac_audio_ctl * 632hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 633 int index, int cnt) 634{ 635 struct hdac_audio_ctl *ctl, *retctl = NULL; 636 int i, at, atindex, found = 0; 637 638 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 639 return (NULL); 640 641 at = cnt; 642 if (at == 0) 643 at = 1; 644 else if (at < 0) 645 at = -1; 646 atindex = index; 647 if (atindex < 0) 648 atindex = -1; 649 650 i = 0; 651 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 652 if (ctl->enable == 0 || ctl->widget == NULL) 653 continue; 654 if (!(ctl->widget->nid == nid && (atindex == -1 || 655 ctl->index == atindex))) 656 continue; 657 found++; 658 if (found == cnt) 659 return (ctl); 660 retctl = ctl; 661 } 662 663 return ((at == -1) ? retctl : NULL); 664} 665 666static void 667hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 668{ 669 struct hdac_softc *sc; 670 struct hdac_widget *w; 671 struct hdac_audio_ctl *ctl; 672 uint32_t id, res; 673 int i = 0, j, forcemute; 674 nid_t cad; 675 676 if (devinfo == NULL || devinfo->codec == NULL || 677 devinfo->codec->sc == NULL) 678 return; 679 680 sc = devinfo->codec->sc; 681 cad = devinfo->codec->cad; 682 id = hdac_codec_id(devinfo); 683 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 684 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 685 sc->pci_subvendor) && 686 hdac_hp_switch[i].id == id) 687 break; 688 } 689 690 if (i >= HDAC_HP_SWITCH_LEN) 691 return; 692 693 forcemute = 0; 694 if (hdac_hp_switch[i].eapdnid != -1) { 695 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 696 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 697 forcemute = (w->param.eapdbtl & 698 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 699 } 700 701 res = hdac_command(sc, 702 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 703 HDA_BOOTVERBOSE( 704 device_printf(sc->dev, 705 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 706 hdac_hp_switch[i].hpnid, res); 707 ); 708 res >>= 31; 709 res ^= hdac_hp_switch[i].inverted; 710 711 switch (hdac_hp_switch[i].type) { 712 case HDAC_HP_SWITCH_CTL: 713 ctl = hdac_audio_ctl_amp_get(devinfo, 714 hdac_hp_switch[i].hpnid, 0, 1); 715 if (ctl != NULL) { 716 ctl->muted = (res != 0 && forcemute == 0) ? 717 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 718 hdac_audio_ctl_amp_set(ctl, 719 HDA_AMP_MUTE_DEFAULT, ctl->left, 720 ctl->right); 721 } 722 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 723 ctl = hdac_audio_ctl_amp_get(devinfo, 724 hdac_hp_switch[i].spkrnid[j], 0, 1); 725 if (ctl != NULL) { 726 ctl->muted = (res != 0 || forcemute == 1) ? 727 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 728 hdac_audio_ctl_amp_set(ctl, 729 HDA_AMP_MUTE_DEFAULT, ctl->left, 730 ctl->right); 731 } 732 } 733 break; 734 case HDAC_HP_SWITCH_CTRL: 735 if (res != 0) { 736 /* HP in */ 737 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 738 if (w != NULL && w->type == 739 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 740 if (forcemute == 0) 741 w->wclass.pin.ctrl |= 742 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 743 else 744 w->wclass.pin.ctrl &= 745 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 746 hdac_command(sc, 747 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 748 w->wclass.pin.ctrl), cad); 749 } 750 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 751 w = hdac_widget_get(devinfo, 752 hdac_hp_switch[i].spkrnid[j]); 753 if (w != NULL && w->type == 754 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 755 w->wclass.pin.ctrl &= 756 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 757 hdac_command(sc, 758 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 759 w->nid, 760 w->wclass.pin.ctrl), cad); 761 } 762 } 763 } else { 764 /* HP out */ 765 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 766 if (w != NULL && w->type == 767 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 768 w->wclass.pin.ctrl &= 769 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 770 hdac_command(sc, 771 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 772 w->wclass.pin.ctrl), cad); 773 } 774 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 775 w = hdac_widget_get(devinfo, 776 hdac_hp_switch[i].spkrnid[j]); 777 if (w != NULL && w->type == 778 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 779 if (forcemute == 0) 780 w->wclass.pin.ctrl |= 781 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 782 else 783 w->wclass.pin.ctrl &= 784 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 785 hdac_command(sc, 786 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 787 w->nid, 788 w->wclass.pin.ctrl), cad); 789 } 790 } 791 } 792 break; 793 default: 794 break; 795 } 796} 797 798static void 799hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 800{ 801 struct hdac_softc *sc; 802 struct hdac_devinfo *devinfo = NULL; 803 device_t *devlist = NULL; 804 int devcount, i; 805 806 if (codec == NULL || codec->sc == NULL) 807 return; 808 809 sc = codec->sc; 810 811 HDA_BOOTVERBOSE( 812 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 813 ); 814 815 device_get_children(sc->dev, &devlist, &devcount); 816 for (i = 0; devlist != NULL && i < devcount; i++) { 817 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 818 if (devinfo != NULL && devinfo->node_type == 819 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 820 devinfo->codec != NULL && 821 devinfo->codec->cad == codec->cad) { 822 break; 823 } else 824 devinfo = NULL; 825 } 826 if (devlist != NULL) 827 free(devlist, M_TEMP); 828 829 if (devinfo == NULL) 830 return; 831 832 switch (tag) { 833 case HDAC_UNSOLTAG_EVENT_HP: 834 hdac_hp_switch_handler(devinfo); 835 break; 836 default: 837 break; 838 } 839} 840 841static int 842hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 843{ 844 /* XXX to be removed */ 845#ifdef HDAC_INTR_EXTRA 846 uint32_t res; 847#endif 848 849 if (ch->blkcnt == 0) 850 return (0); 851 852 /* XXX to be removed */ 853#ifdef HDAC_INTR_EXTRA 854 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 855#endif 856 857 /* XXX to be removed */ 858#ifdef HDAC_INTR_EXTRA 859 HDA_BOOTVERBOSE( 860 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 861 device_printf(sc->dev, 862 "PCMDIR_%s intr triggered beyond stream boundary:" 863 "%08x\n", 864 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 865 ); 866#endif 867 868 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 869 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 870 871 /* XXX to be removed */ 872#ifdef HDAC_INTR_EXTRA 873 if (res & HDAC_SDSTS_BCIS) { 874#endif 875 return (1); 876 /* XXX to be removed */ 877#ifdef HDAC_INTR_EXTRA 878 } 879#endif 880 881 return (0); 882} 883 884/**************************************************************************** 885 * void hdac_intr_handler(void *) 886 * 887 * Interrupt handler. Processes interrupts received from the hdac. 888 ****************************************************************************/ 889static void 890hdac_intr_handler(void *context) 891{ 892 struct hdac_softc *sc; 893 uint32_t intsts; 894 uint8_t rirbsts; 895 struct hdac_rirb *rirb_base; 896 uint32_t trigger = 0; 897 898 sc = (struct hdac_softc *)context; 899 900 hdac_lock(sc); 901 if (sc->polling != 0) { 902 hdac_unlock(sc); 903 return; 904 } 905 /* Do we have anything to do? */ 906 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 907 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 908 hdac_unlock(sc); 909 return; 910 } 911 912 /* Was this a controller interrupt? */ 913 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 914 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 915 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 916 /* Get as many responses that we can */ 917 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 918 HDAC_WRITE_1(&sc->mem, 919 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 920 hdac_rirb_flush(sc); 921 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 922 } 923 /* XXX to be removed */ 924 /* Clear interrupt and exit */ 925#ifdef HDAC_INTR_EXTRA 926 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 927#endif 928 } 929 930 hdac_unsolq_flush(sc); 931 932 if (intsts & HDAC_INTSTS_SIS_MASK) { 933 if ((intsts & (1 << sc->num_iss)) && 934 hdac_stream_intr(sc, &sc->play) != 0) 935 trigger |= 1; 936 if ((intsts & (1 << 0)) && 937 hdac_stream_intr(sc, &sc->rec) != 0) 938 trigger |= 2; 939 /* XXX to be removed */ 940#ifdef HDAC_INTR_EXTRA 941 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 942 HDAC_INTSTS_SIS_MASK); 943#endif 944 } 945 946 hdac_unlock(sc); 947 948 if (trigger & 1) 949 chn_intr(sc->play.c); 950 if (trigger & 2) 951 chn_intr(sc->rec.c); 952} 953 954/**************************************************************************** 955 * int hdac_reset(hdac_softc *) 956 * 957 * Reset the hdac to a quiescent and known state. 958 ****************************************************************************/ 959static int 960hdac_reset(struct hdac_softc *sc) 961{ 962 uint32_t gctl; 963 int count, i; 964 965 /* 966 * Stop all Streams DMA engine 967 */ 968 for (i = 0; i < sc->num_iss; i++) 969 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 970 for (i = 0; i < sc->num_oss; i++) 971 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 972 for (i = 0; i < sc->num_bss; i++) 973 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 974 975 /* 976 * Stop Control DMA engines 977 */ 978 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 979 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 980 981 /* 982 * Reset the controller. The reset must remain asserted for 983 * a minimum of 100us. 984 */ 985 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 986 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 987 count = 10000; 988 do { 989 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 990 if (!(gctl & HDAC_GCTL_CRST)) 991 break; 992 DELAY(10); 993 } while (--count); 994 if (gctl & HDAC_GCTL_CRST) { 995 device_printf(sc->dev, "Unable to put hdac in reset\n"); 996 return (ENXIO); 997 } 998 DELAY(100); 999 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1000 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1001 count = 10000; 1002 do { 1003 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1004 if (gctl & HDAC_GCTL_CRST) 1005 break; 1006 DELAY(10); 1007 } while (--count); 1008 if (!(gctl & HDAC_GCTL_CRST)) { 1009 device_printf(sc->dev, "Device stuck in reset\n"); 1010 return (ENXIO); 1011 } 1012 1013 /* 1014 * Wait for codecs to finish their own reset sequence. The delay here 1015 * should be of 250us but for some reasons, on it's not enough on my 1016 * computer. Let's use twice as much as necessary to make sure that 1017 * it's reset properly. 1018 */ 1019 DELAY(1000); 1020 1021 return (0); 1022} 1023 1024 1025/**************************************************************************** 1026 * int hdac_get_capabilities(struct hdac_softc *); 1027 * 1028 * Retreive the general capabilities of the hdac; 1029 * Number of Input Streams 1030 * Number of Output Streams 1031 * Number of bidirectional Streams 1032 * 64bit ready 1033 * CORB and RIRB sizes 1034 ****************************************************************************/ 1035static int 1036hdac_get_capabilities(struct hdac_softc *sc) 1037{ 1038 uint16_t gcap; 1039 uint8_t corbsize, rirbsize; 1040 1041 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1042 sc->num_iss = HDAC_GCAP_ISS(gcap); 1043 sc->num_oss = HDAC_GCAP_OSS(gcap); 1044 sc->num_bss = HDAC_GCAP_BSS(gcap); 1045 1046 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1047 1048 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1049 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1050 HDAC_CORBSIZE_CORBSZCAP_256) 1051 sc->corb_size = 256; 1052 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1053 HDAC_CORBSIZE_CORBSZCAP_16) 1054 sc->corb_size = 16; 1055 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1056 HDAC_CORBSIZE_CORBSZCAP_2) 1057 sc->corb_size = 2; 1058 else { 1059 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1060 __func__, corbsize); 1061 return (ENXIO); 1062 } 1063 1064 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1065 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1066 HDAC_RIRBSIZE_RIRBSZCAP_256) 1067 sc->rirb_size = 256; 1068 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1069 HDAC_RIRBSIZE_RIRBSZCAP_16) 1070 sc->rirb_size = 16; 1071 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1072 HDAC_RIRBSIZE_RIRBSZCAP_2) 1073 sc->rirb_size = 2; 1074 else { 1075 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1076 __func__, rirbsize); 1077 return (ENXIO); 1078 } 1079 1080 return (0); 1081} 1082 1083 1084/**************************************************************************** 1085 * void hdac_dma_cb 1086 * 1087 * This function is called by bus_dmamap_load when the mapping has been 1088 * established. We just record the physical address of the mapping into 1089 * the struct hdac_dma passed in. 1090 ****************************************************************************/ 1091static void 1092hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1093{ 1094 struct hdac_dma *dma; 1095 1096 if (error == 0) { 1097 dma = (struct hdac_dma *)callback_arg; 1098 dma->dma_paddr = segs[0].ds_addr; 1099 } 1100} 1101 1102static void 1103hdac_dma_nocache(void *ptr) 1104{ 1105#if defined(__i386__) || defined(__amd64__) 1106 pt_entry_t *pte; 1107 vm_offset_t va; 1108 1109 va = (vm_offset_t)ptr; 1110 pte = vtopte(va); 1111 if (pte) { 1112 *pte |= PG_N; 1113 invltlb(); 1114 } 1115#endif 1116} 1117 1118/**************************************************************************** 1119 * int hdac_dma_alloc 1120 * 1121 * This function allocate and setup a dma region (struct hdac_dma). 1122 * It must be freed by a corresponding hdac_dma_free. 1123 ****************************************************************************/ 1124static int 1125hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1126{ 1127 int result; 1128 int lowaddr; 1129 1130 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1131 BUS_SPACE_MAXADDR_32BIT; 1132 bzero(dma, sizeof(*dma)); 1133 1134 /* 1135 * Create a DMA tag 1136 */ 1137 result = bus_dma_tag_create(NULL, /* parent */ 1138 HDAC_DMA_ALIGNMENT, /* alignment */ 1139 0, /* boundary */ 1140 lowaddr, /* lowaddr */ 1141 BUS_SPACE_MAXADDR, /* highaddr */ 1142 NULL, /* filtfunc */ 1143 NULL, /* fistfuncarg */ 1144 size, /* maxsize */ 1145 1, /* nsegments */ 1146 size, /* maxsegsz */ 1147 0, /* flags */ 1148 NULL, /* lockfunc */ 1149 NULL, /* lockfuncarg */ 1150 &dma->dma_tag); /* dmat */ 1151 if (result != 0) { 1152 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1153 __func__, result); 1154 goto fail; 1155 } 1156 1157 /* 1158 * Allocate DMA memory 1159 */ 1160 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1161 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1162 if (result != 0) { 1163 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1164 __func__, result); 1165 goto fail; 1166 } 1167 1168 /* 1169 * Map the memory 1170 */ 1171 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1172 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1173 BUS_DMA_NOWAIT); 1174 if (result != 0 || dma->dma_paddr == 0) { 1175 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1176 __func__, result); 1177 goto fail; 1178 } 1179 bzero((void *)dma->dma_vaddr, size); 1180 hdac_dma_nocache(dma->dma_vaddr); 1181 1182 return (0); 1183fail: 1184 if (dma->dma_map != NULL) 1185 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1186 if (dma->dma_tag != NULL) 1187 bus_dma_tag_destroy(dma->dma_tag); 1188 return (result); 1189} 1190 1191 1192/**************************************************************************** 1193 * void hdac_dma_free(struct hdac_dma *) 1194 * 1195 * Free a struct dhac_dma that has been previously allocated via the 1196 * hdac_dma_alloc function. 1197 ****************************************************************************/ 1198static void 1199hdac_dma_free(struct hdac_dma *dma) 1200{ 1201 if (dma->dma_tag != NULL) { 1202 /* Flush caches */ 1203 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1204 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1205 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1206 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1207 bus_dma_tag_destroy(dma->dma_tag); 1208 } 1209} 1210 1211/**************************************************************************** 1212 * int hdac_mem_alloc(struct hdac_softc *) 1213 * 1214 * Allocate all the bus resources necessary to speak with the physical 1215 * controller. 1216 ****************************************************************************/ 1217static int 1218hdac_mem_alloc(struct hdac_softc *sc) 1219{ 1220 struct hdac_mem *mem; 1221 1222 mem = &sc->mem; 1223 mem->mem_rid = PCIR_BAR(0); 1224 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1225 &mem->mem_rid, RF_ACTIVE); 1226 if (mem->mem_res == NULL) { 1227 device_printf(sc->dev, 1228 "%s: Unable to allocate memory resource\n", __func__); 1229 return (ENOMEM); 1230 } 1231 mem->mem_tag = rman_get_bustag(mem->mem_res); 1232 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1233 1234 return (0); 1235} 1236 1237/**************************************************************************** 1238 * void hdac_mem_free(struct hdac_softc *) 1239 * 1240 * Free up resources previously allocated by hdac_mem_alloc. 1241 ****************************************************************************/ 1242static void 1243hdac_mem_free(struct hdac_softc *sc) 1244{ 1245 struct hdac_mem *mem; 1246 1247 mem = &sc->mem; 1248 if (mem->mem_res != NULL) 1249 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1250 mem->mem_res); 1251 mem->mem_res = NULL; 1252} 1253 1254/**************************************************************************** 1255 * int hdac_irq_alloc(struct hdac_softc *) 1256 * 1257 * Allocate and setup the resources necessary for interrupt handling. 1258 ****************************************************************************/ 1259static int 1260hdac_irq_alloc(struct hdac_softc *sc) 1261{ 1262 struct hdac_irq *irq; 1263 int result; 1264 1265 irq = &sc->irq; 1266 irq->irq_rid = 0x0; 1267 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1268 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1269 if (irq->irq_res == NULL) { 1270 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1271 __func__); 1272 goto fail; 1273 } 1274 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1275 hdac_intr_handler, sc, &irq->irq_handle); 1276 if (result != 0) { 1277 device_printf(sc->dev, 1278 "%s: Unable to setup interrupt handler (%x)\n", 1279 __func__, result); 1280 goto fail; 1281 } 1282 1283 return (0); 1284 1285fail: 1286 hdac_irq_free(sc); 1287 1288 return (ENXIO); 1289} 1290 1291/**************************************************************************** 1292 * void hdac_irq_free(struct hdac_softc *) 1293 * 1294 * Free up resources previously allocated by hdac_irq_alloc. 1295 ****************************************************************************/ 1296static void 1297hdac_irq_free(struct hdac_softc *sc) 1298{ 1299 struct hdac_irq *irq; 1300 1301 irq = &sc->irq; 1302 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1303 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1304 if (irq->irq_res != NULL) 1305 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1306 irq->irq_res); 1307 irq->irq_handle = NULL; 1308 irq->irq_res = NULL; 1309} 1310 1311/**************************************************************************** 1312 * void hdac_corb_init(struct hdac_softc *) 1313 * 1314 * Initialize the corb registers for operations but do not start it up yet. 1315 * The CORB engine must not be running when this function is called. 1316 ****************************************************************************/ 1317static void 1318hdac_corb_init(struct hdac_softc *sc) 1319{ 1320 uint8_t corbsize; 1321 uint64_t corbpaddr; 1322 1323 /* Setup the CORB size. */ 1324 switch (sc->corb_size) { 1325 case 256: 1326 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1327 break; 1328 case 16: 1329 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1330 break; 1331 case 2: 1332 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1333 break; 1334 default: 1335 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1336 } 1337 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1338 1339 /* Setup the CORB Address in the hdac */ 1340 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1341 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1342 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1343 1344 /* Set the WP and RP */ 1345 sc->corb_wp = 0; 1346 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1347 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1348 /* 1349 * The HDA specification indicates that the CORBRPRST bit will always 1350 * read as zero. Unfortunately, it seems that at least the 82801G 1351 * doesn't reset the bit to zero, which stalls the corb engine. 1352 * manually reset the bit to zero before continuing. 1353 */ 1354 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1355 1356 /* Enable CORB error reporting */ 1357#if 0 1358 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1359#endif 1360} 1361 1362/**************************************************************************** 1363 * void hdac_rirb_init(struct hdac_softc *) 1364 * 1365 * Initialize the rirb registers for operations but do not start it up yet. 1366 * The RIRB engine must not be running when this function is called. 1367 ****************************************************************************/ 1368static void 1369hdac_rirb_init(struct hdac_softc *sc) 1370{ 1371 uint8_t rirbsize; 1372 uint64_t rirbpaddr; 1373 1374 /* Setup the RIRB size. */ 1375 switch (sc->rirb_size) { 1376 case 256: 1377 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1378 break; 1379 case 16: 1380 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1381 break; 1382 case 2: 1383 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1384 break; 1385 default: 1386 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1387 } 1388 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1389 1390 /* Setup the RIRB Address in the hdac */ 1391 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1392 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1393 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1394 1395 /* Setup the WP and RP */ 1396 sc->rirb_rp = 0; 1397 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1398 1399 if (sc->polling == 0) { 1400 /* Setup the interrupt threshold */ 1401 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1402 1403 /* Enable Overrun and response received reporting */ 1404#if 0 1405 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1406 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1407#else 1408 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1409#endif 1410 } 1411 1412 /* 1413 * Make sure that the Host CPU cache doesn't contain any dirty 1414 * cache lines that falls in the rirb. If I understood correctly, it 1415 * should be sufficient to do this only once as the rirb is purely 1416 * read-only from now on. 1417 */ 1418 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1419 BUS_DMASYNC_PREREAD); 1420} 1421 1422/**************************************************************************** 1423 * void hdac_corb_start(hdac_softc *) 1424 * 1425 * Startup the corb DMA engine 1426 ****************************************************************************/ 1427static void 1428hdac_corb_start(struct hdac_softc *sc) 1429{ 1430 uint32_t corbctl; 1431 1432 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1433 corbctl |= HDAC_CORBCTL_CORBRUN; 1434 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1435} 1436 1437/**************************************************************************** 1438 * void hdac_rirb_start(hdac_softc *) 1439 * 1440 * Startup the rirb DMA engine 1441 ****************************************************************************/ 1442static void 1443hdac_rirb_start(struct hdac_softc *sc) 1444{ 1445 uint32_t rirbctl; 1446 1447 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1448 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1449 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1450} 1451 1452 1453/**************************************************************************** 1454 * void hdac_scan_codecs(struct hdac_softc *) 1455 * 1456 * Scan the bus for available codecs. 1457 ****************************************************************************/ 1458static void 1459hdac_scan_codecs(struct hdac_softc *sc) 1460{ 1461 struct hdac_codec *codec; 1462 int i; 1463 uint16_t statests; 1464 1465 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1466 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1467 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1468 /* We have found a codec. */ 1469 hdac_unlock(sc); 1470 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1471 M_HDAC, M_ZERO | M_NOWAIT); 1472 hdac_lock(sc); 1473 if (codec == NULL) { 1474 device_printf(sc->dev, 1475 "Unable to allocate memory for codec\n"); 1476 continue; 1477 } 1478 codec->commands = NULL; 1479 codec->responses_received = 0; 1480 codec->verbs_sent = 0; 1481 codec->sc = sc; 1482 codec->cad = i; 1483 sc->codecs[i] = codec; 1484 if (hdac_probe_codec(codec) != 0) 1485 break; 1486 } 1487 } 1488 /* All codecs have been probed, now try to attach drivers to them */ 1489 /* bus_generic_attach(sc->dev); */ 1490} 1491 1492/**************************************************************************** 1493 * void hdac_probe_codec(struct hdac_softc *, int) 1494 * 1495 * Probe a the given codec_id for available function groups. 1496 ****************************************************************************/ 1497static int 1498hdac_probe_codec(struct hdac_codec *codec) 1499{ 1500 struct hdac_softc *sc = codec->sc; 1501 struct hdac_devinfo *devinfo; 1502 uint32_t vendorid, revisionid, subnode; 1503 int startnode; 1504 int endnode; 1505 int i; 1506 nid_t cad = codec->cad; 1507 1508 HDA_BOOTVERBOSE( 1509 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1510 ); 1511 vendorid = hdac_command(sc, 1512 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1513 cad); 1514 revisionid = hdac_command(sc, 1515 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1516 cad); 1517 subnode = hdac_command(sc, 1518 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1519 cad); 1520 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1521 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1522 1523 HDA_BOOTVERBOSE( 1524 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1525 startnode, endnode); 1526 ); 1527 for (i = startnode; i < endnode; i++) { 1528 devinfo = hdac_probe_function(codec, i); 1529 if (devinfo != NULL) { 1530 /* XXX Ignore other FG. */ 1531 devinfo->vendor_id = 1532 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1533 devinfo->device_id = 1534 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1535 devinfo->revision_id = 1536 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1537 devinfo->stepping_id = 1538 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1539 HDA_BOOTVERBOSE( 1540 device_printf(sc->dev, 1541 "HDA_DEBUG: \tFound AFG nid=%d " 1542 "[startnode=%d endnode=%d]\n", 1543 devinfo->nid, startnode, endnode); 1544 ); 1545 return (1); 1546 } 1547 } 1548 1549 HDA_BOOTVERBOSE( 1550 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1551 ); 1552 return (0); 1553} 1554 1555static struct hdac_devinfo * 1556hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1557{ 1558 struct hdac_softc *sc = codec->sc; 1559 struct hdac_devinfo *devinfo; 1560 uint32_t fctgrptype; 1561 nid_t cad = codec->cad; 1562 1563 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1564 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1565 1566 /* XXX For now, ignore other FG. */ 1567 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1568 return (NULL); 1569 1570 hdac_unlock(sc); 1571 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1572 M_NOWAIT | M_ZERO); 1573 hdac_lock(sc); 1574 if (devinfo == NULL) { 1575 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1576 __func__); 1577 return (NULL); 1578 } 1579 1580 devinfo->nid = nid; 1581 devinfo->node_type = fctgrptype; 1582 devinfo->codec = codec; 1583 1584 hdac_add_child(sc, devinfo); 1585 1586 return (devinfo); 1587} 1588 1589static void 1590hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1591{ 1592 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1593 device_set_ivars(devinfo->dev, (void *)devinfo); 1594 /* XXX - Print more information when booting verbose??? */ 1595} 1596 1597static void 1598hdac_widget_connection_parse(struct hdac_widget *w) 1599{ 1600 struct hdac_softc *sc = w->devinfo->codec->sc; 1601 uint32_t res; 1602 int i, j, max, found, entnum, cnid; 1603 nid_t cad = w->devinfo->codec->cad; 1604 nid_t nid = w->nid; 1605 1606 res = hdac_command(sc, 1607 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1608 1609 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1610 1611 if (w->nconns < 1) 1612 return; 1613 1614 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1615 res = 0; 1616 i = 0; 1617 found = 0; 1618 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1619 1620 while (i < w->nconns) { 1621 res = hdac_command(sc, 1622 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1623 for (j = 0; j < entnum; j++) { 1624 cnid = res; 1625 cnid >>= (32 / entnum) * j; 1626 cnid &= (1 << (32 / entnum)) - 1; 1627 if (cnid == 0) 1628 continue; 1629 if (found > max) { 1630 device_printf(sc->dev, 1631 "node %d: Adding %d: " 1632 "Max connection reached!\n", 1633 nid, cnid); 1634 continue; 1635 } 1636 w->conns[found++] = cnid; 1637 } 1638 i += entnum; 1639 } 1640 1641 HDA_BOOTVERBOSE( 1642 if (w->nconns != found) { 1643 device_printf(sc->dev, 1644 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1645 "length=%d != found=%d\n", 1646 nid, w->nconns, found); 1647 } 1648 ); 1649} 1650 1651static uint32_t 1652hdac_widget_pin_getconfig(struct hdac_widget *w) 1653{ 1654 struct hdac_softc *sc; 1655 uint32_t config, id; 1656 nid_t cad, nid; 1657 1658 sc = w->devinfo->codec->sc; 1659 cad = w->devinfo->codec->cad; 1660 nid = w->nid; 1661 id = hdac_codec_id(w->devinfo); 1662 1663 config = hdac_command(sc, 1664 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1665 cad); 1666 /* 1667 * XXX REWRITE!!!! Don't argue! 1668 */ 1669 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1670 switch (nid) { 1671 case 26: 1672 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1673 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1674 break; 1675 case 27: 1676 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1677 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1678 break; 1679 } 1680 } else if (id == HDA_CODEC_ALC880 && 1681 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1682 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1683 /* 1684 * Super broken BIOS 1685 */ 1686 switch (nid) { 1687 case 20: 1688 break; 1689 case 21: 1690 break; 1691 case 22: 1692 break; 1693 case 23: 1694 break; 1695 case 24: /* MIC1 */ 1696 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1697 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1698 break; 1699 case 25: /* XXX MIC2 */ 1700 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1701 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1702 break; 1703 case 26: /* LINE1 */ 1704 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1705 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1706 break; 1707 case 27: /* XXX LINE2 */ 1708 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1709 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1710 break; 1711 case 28: /* CD */ 1712 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1713 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1714 break; 1715 case 30: 1716 break; 1717 case 31: 1718 break; 1719 default: 1720 break; 1721 } 1722 } 1723 1724 return (config); 1725} 1726 1727static void 1728hdac_widget_pin_parse(struct hdac_widget *w) 1729{ 1730 struct hdac_softc *sc = w->devinfo->codec->sc; 1731 uint32_t config, pincap; 1732 char *devstr, *connstr; 1733 nid_t cad = w->devinfo->codec->cad; 1734 nid_t nid = w->nid; 1735 1736 config = hdac_widget_pin_getconfig(w); 1737 w->wclass.pin.config = config; 1738 1739 pincap = hdac_command(sc, 1740 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1741 w->wclass.pin.cap = pincap; 1742 1743 w->wclass.pin.ctrl = hdac_command(sc, 1744 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1745 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1746 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1747 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1748 1749 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1750 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1751 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1752 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1753 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1754 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1755 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1756 w->param.eapdbtl = hdac_command(sc, 1757 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1758 w->param.eapdbtl &= 0x7; 1759 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1760 } else 1761 w->param.eapdbtl = HDAC_INVALID; 1762 1763 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1764 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1765 devstr = "line out"; 1766 break; 1767 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1768 devstr = "speaker"; 1769 break; 1770 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1771 devstr = "headphones out"; 1772 break; 1773 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1774 devstr = "CD"; 1775 break; 1776 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1777 devstr = "SPDIF out"; 1778 break; 1779 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1780 devstr = "digital (other) out"; 1781 break; 1782 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1783 devstr = "modem, line side"; 1784 break; 1785 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1786 devstr = "modem, handset side"; 1787 break; 1788 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1789 devstr = "line in"; 1790 break; 1791 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1792 devstr = "AUX"; 1793 break; 1794 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1795 devstr = "Mic in"; 1796 break; 1797 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1798 devstr = "telephony"; 1799 break; 1800 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1801 devstr = "SPDIF in"; 1802 break; 1803 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1804 devstr = "digital (other) in"; 1805 break; 1806 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1807 devstr = "other"; 1808 break; 1809 default: 1810 devstr = "unknown"; 1811 break; 1812 } 1813 1814 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1815 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1816 connstr = "jack"; 1817 break; 1818 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1819 connstr = "none"; 1820 break; 1821 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1822 connstr = "fixed"; 1823 break; 1824 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1825 connstr = "jack / fixed"; 1826 break; 1827 default: 1828 connstr = "unknown"; 1829 break; 1830 } 1831 1832 strlcat(w->name, ": ", sizeof(w->name)); 1833 strlcat(w->name, devstr, sizeof(w->name)); 1834 strlcat(w->name, " (", sizeof(w->name)); 1835 strlcat(w->name, connstr, sizeof(w->name)); 1836 strlcat(w->name, ")", sizeof(w->name)); 1837} 1838 1839static void 1840hdac_widget_parse(struct hdac_widget *w) 1841{ 1842 struct hdac_softc *sc = w->devinfo->codec->sc; 1843 uint32_t wcap, cap; 1844 char *typestr; 1845 nid_t cad = w->devinfo->codec->cad; 1846 nid_t nid = w->nid; 1847 1848 wcap = hdac_command(sc, 1849 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1850 cad); 1851 w->param.widget_cap = wcap; 1852 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1853 1854 switch (w->type) { 1855 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1856 typestr = "audio output"; 1857 break; 1858 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1859 typestr = "audio input"; 1860 break; 1861 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1862 typestr = "audio mixer"; 1863 break; 1864 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1865 typestr = "audio selector"; 1866 break; 1867 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1868 typestr = "pin"; 1869 break; 1870 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1871 typestr = "power widget"; 1872 break; 1873 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1874 typestr = "volume widget"; 1875 break; 1876 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1877 typestr = "beep widget"; 1878 break; 1879 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1880 typestr = "vendor widget"; 1881 break; 1882 default: 1883 typestr = "unknown type"; 1884 break; 1885 } 1886 1887 strlcpy(w->name, typestr, sizeof(w->name)); 1888 1889 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1890 hdac_command(sc, 1891 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1892 cad); 1893 DELAY(1000); 1894 } 1895 1896 hdac_widget_connection_parse(w); 1897 1898 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1899 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1900 w->param.outamp_cap = 1901 hdac_command(sc, 1902 HDA_CMD_GET_PARAMETER(cad, nid, 1903 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1904 else 1905 w->param.outamp_cap = 1906 w->devinfo->function.audio.outamp_cap; 1907 } else 1908 w->param.outamp_cap = 0; 1909 1910 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1911 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1912 w->param.inamp_cap = 1913 hdac_command(sc, 1914 HDA_CMD_GET_PARAMETER(cad, nid, 1915 HDA_PARAM_INPUT_AMP_CAP), cad); 1916 else 1917 w->param.inamp_cap = 1918 w->devinfo->function.audio.inamp_cap; 1919 } else 1920 w->param.inamp_cap = 0; 1921 1922 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1923 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1924 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1925 cap = hdac_command(sc, 1926 HDA_CMD_GET_PARAMETER(cad, nid, 1927 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1928 w->param.supp_stream_formats = (cap != 0) ? cap : 1929 w->devinfo->function.audio.supp_stream_formats; 1930 cap = hdac_command(sc, 1931 HDA_CMD_GET_PARAMETER(cad, nid, 1932 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1933 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1934 w->devinfo->function.audio.supp_pcm_size_rate; 1935 } else { 1936 w->param.supp_stream_formats = 1937 w->devinfo->function.audio.supp_stream_formats; 1938 w->param.supp_pcm_size_rate = 1939 w->devinfo->function.audio.supp_pcm_size_rate; 1940 } 1941 } else { 1942 w->param.supp_stream_formats = 0; 1943 w->param.supp_pcm_size_rate = 0; 1944 } 1945 1946 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1947 hdac_widget_pin_parse(w); 1948} 1949 1950static struct hdac_widget * 1951hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1952{ 1953 if (devinfo == NULL || devinfo->widget == NULL || 1954 nid < devinfo->startnode || nid >= devinfo->endnode) 1955 return (NULL); 1956 return (&devinfo->widget[nid - devinfo->startnode]); 1957} 1958 1959static __inline int 1960hda_poll_channel(struct hdac_chan *ch) 1961{ 1962 uint32_t sz, delta; 1963 volatile uint32_t ptr; 1964 1965 if (ch->active == 0) 1966 return (0); 1967 1968 sz = ch->blksz * ch->blkcnt; 1969 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1970 ch->ptr = ptr; 1971 ptr %= sz; 1972 ptr &= ~(ch->blksz - 1); 1973 delta = (sz + ptr - ch->prevptr) % sz; 1974 1975 if (delta < ch->blksz) 1976 return (0); 1977 1978 ch->prevptr = ptr; 1979 1980 return (1); 1981} 1982 1983#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1984 1985static void 1986hda_poll_callback(void *arg) 1987{ 1988 struct hdac_softc *sc = arg; 1989 uint32_t trigger = 0; 1990 1991 if (sc == NULL) 1992 return; 1993 1994 hdac_lock(sc); 1995 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 1996 hdac_unlock(sc); 1997 return; 1998 } 1999 2000 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2001 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2002 2003 /* XXX */ 2004 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2005 hda_poll_callback, sc); 2006 2007 hdac_unlock(sc); 2008 2009 if (trigger & 1) 2010 chn_intr(sc->play.c); 2011 if (trigger & 2) 2012 chn_intr(sc->rec.c); 2013} 2014 2015static int 2016hdac_rirb_flush(struct hdac_softc *sc) 2017{ 2018 struct hdac_rirb *rirb_base, *rirb; 2019 struct hdac_codec *codec; 2020 struct hdac_command_list *commands; 2021 nid_t cad; 2022 uint32_t resp; 2023 uint8_t rirbwp; 2024 int ret = 0; 2025 2026 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2027 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2028 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2029 BUS_DMASYNC_POSTREAD); 2030 2031 while (sc->rirb_rp != rirbwp) { 2032 sc->rirb_rp++; 2033 sc->rirb_rp %= sc->rirb_size; 2034 rirb = &rirb_base[sc->rirb_rp]; 2035 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2036 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2037 sc->codecs[cad] == NULL) 2038 continue; 2039 resp = rirb->response; 2040 codec = sc->codecs[cad]; 2041 commands = codec->commands; 2042 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2043 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2044 ((resp >> 26) & 0xffff); 2045 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2046 } else if (commands != NULL && commands->num_commands > 0 && 2047 codec->responses_received < commands->num_commands) 2048 commands->responses[codec->responses_received++] = 2049 resp; 2050 ret++; 2051 } 2052 2053 return (ret); 2054} 2055 2056static int 2057hdac_unsolq_flush(struct hdac_softc *sc) 2058{ 2059 nid_t cad; 2060 uint32_t tag; 2061 int ret = 0; 2062 2063 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2064 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2065 while (sc->unsolq_rp != sc->unsolq_wp) { 2066 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2067 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2068 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2069 hdac_unsolicited_handler(sc->codecs[cad], tag); 2070 ret++; 2071 } 2072 sc->unsolq_st = HDAC_UNSOLQ_READY; 2073 } 2074 2075 return (ret); 2076} 2077 2078static void 2079hdac_poll_callback(void *arg) 2080{ 2081 struct hdac_softc *sc = arg; 2082 if (sc == NULL) 2083 return; 2084 2085 hdac_lock(sc); 2086 if (sc->polling == 0) { 2087 hdac_unlock(sc); 2088 return; 2089 } 2090 hdac_rirb_flush(sc); 2091 hdac_unsolq_flush(sc); 2092 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2093 hdac_poll_callback, sc); 2094 hdac_unlock(sc); 2095} 2096 2097static void 2098hdac_stream_stop(struct hdac_chan *ch) 2099{ 2100 struct hdac_softc *sc = ch->devinfo->codec->sc; 2101 uint32_t ctl; 2102 2103 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2104 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2105 HDAC_SDCTL_RUN); 2106 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2107 2108 ch->active = 0; 2109 2110 if (sc->polling != 0) { 2111 int pollticks; 2112 2113 if (hda_chan_active(sc) == 0) { 2114 callout_stop(&sc->poll_hda); 2115 sc->poll_ticks = 1; 2116 } else { 2117 if (sc->play.active != 0) 2118 ch = &sc->play; 2119 else 2120 ch = &sc->rec; 2121 pollticks = ((uint64_t)hz * ch->blksz) / 2122 ((uint64_t)sndbuf_getbps(ch->b) * 2123 sndbuf_getspd(ch->b)); 2124 pollticks >>= 2; 2125 if (pollticks > hz) 2126 pollticks = hz; 2127 if (pollticks < 1) { 2128 HDA_BOOTVERBOSE( 2129 device_printf(sc->dev, 2130 "%s: pollticks=%d < 1 !\n", 2131 __func__, pollticks); 2132 ); 2133 pollticks = 1; 2134 } 2135 if (pollticks > sc->poll_ticks) { 2136 HDA_BOOTVERBOSE( 2137 device_printf(sc->dev, 2138 "%s: pollticks %d -> %d\n", 2139 __func__, sc->poll_ticks, 2140 pollticks); 2141 ); 2142 sc->poll_ticks = pollticks; 2143 callout_reset(&sc->poll_hda, 1, 2144 hda_poll_callback, sc); 2145 } 2146 } 2147 } else { 2148 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2149 ctl &= ~(1 << (ch->off >> 5)); 2150 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2151 } 2152} 2153 2154static void 2155hdac_stream_start(struct hdac_chan *ch) 2156{ 2157 struct hdac_softc *sc = ch->devinfo->codec->sc; 2158 uint32_t ctl; 2159 2160 if (sc->polling != 0) { 2161 int pollticks; 2162 2163 pollticks = ((uint64_t)hz * ch->blksz) / 2164 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2165 pollticks >>= 2; 2166 if (pollticks > hz) 2167 pollticks = hz; 2168 if (pollticks < 1) { 2169 HDA_BOOTVERBOSE( 2170 device_printf(sc->dev, 2171 "%s: pollticks=%d < 1 !\n", 2172 __func__, pollticks); 2173 ); 2174 pollticks = 1; 2175 } 2176 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2177 HDA_BOOTVERBOSE( 2178 if (hda_chan_active(sc) == 0) { 2179 device_printf(sc->dev, 2180 "%s: pollticks=%d\n", 2181 __func__, pollticks); 2182 } else { 2183 device_printf(sc->dev, 2184 "%s: pollticks %d -> %d\n", 2185 __func__, sc->poll_ticks, 2186 pollticks); 2187 } 2188 ); 2189 sc->poll_ticks = pollticks; 2190 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2191 sc); 2192 } 2193 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2194 ctl |= HDAC_SDCTL_RUN; 2195 } else { 2196 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2197 ctl |= 1 << (ch->off >> 5); 2198 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2199 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2200 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2201 HDAC_SDCTL_RUN; 2202 } 2203 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2204 2205 ch->active = 1; 2206} 2207 2208static void 2209hdac_stream_reset(struct hdac_chan *ch) 2210{ 2211 struct hdac_softc *sc = ch->devinfo->codec->sc; 2212 int timeout = 1000; 2213 int to = timeout; 2214 uint32_t ctl; 2215 2216 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2217 ctl |= HDAC_SDCTL_SRST; 2218 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2219 do { 2220 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2221 if (ctl & HDAC_SDCTL_SRST) 2222 break; 2223 DELAY(10); 2224 } while (--to); 2225 if (!(ctl & HDAC_SDCTL_SRST)) { 2226 device_printf(sc->dev, "timeout in reset\n"); 2227 } 2228 ctl &= ~HDAC_SDCTL_SRST; 2229 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2230 to = timeout; 2231 do { 2232 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2233 if (!(ctl & HDAC_SDCTL_SRST)) 2234 break; 2235 DELAY(10); 2236 } while (--to); 2237 if (ctl & HDAC_SDCTL_SRST) 2238 device_printf(sc->dev, "can't reset!\n"); 2239} 2240 2241static void 2242hdac_stream_setid(struct hdac_chan *ch) 2243{ 2244 struct hdac_softc *sc = ch->devinfo->codec->sc; 2245 uint32_t ctl; 2246 2247 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2248 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2249 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2250 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2251} 2252 2253static void 2254hdac_bdl_setup(struct hdac_chan *ch) 2255{ 2256 struct hdac_softc *sc = ch->devinfo->codec->sc; 2257 struct hdac_bdle *bdle; 2258 uint64_t addr; 2259 uint32_t blksz, blkcnt; 2260 int i; 2261 2262 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2263 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2264 2265 if (sc->polling != 0) { 2266 blksz = ch->blksz * ch->blkcnt; 2267 blkcnt = 1; 2268 } else { 2269 blksz = ch->blksz; 2270 blkcnt = ch->blkcnt; 2271 } 2272 2273 for (i = 0; i < blkcnt; i++, bdle++) { 2274 bdle->addrl = (uint32_t)addr; 2275 bdle->addrh = (uint32_t)(addr >> 32); 2276 bdle->len = blksz; 2277 bdle->ioc = 1 ^ sc->polling; 2278 addr += blksz; 2279 } 2280 2281 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2282 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2283 addr = ch->bdl_dma.dma_paddr; 2284 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2285 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2286} 2287 2288static int 2289hdac_bdl_alloc(struct hdac_chan *ch) 2290{ 2291 struct hdac_softc *sc = ch->devinfo->codec->sc; 2292 int rc; 2293 2294 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2295 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2296 if (rc) { 2297 device_printf(sc->dev, "can't alloc bdl\n"); 2298 return (rc); 2299 } 2300 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2301 2302 return (0); 2303} 2304 2305static void 2306hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2307 int index, int lmute, int rmute, 2308 int left, int right, int dir) 2309{ 2310 uint16_t v = 0; 2311 2312 if (sc == NULL) 2313 return; 2314 2315 if (left != right || lmute != rmute) { 2316 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2317 (lmute << 7) | left; 2318 hdac_command(sc, 2319 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2320 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2321 (rmute << 7) | right; 2322 } else 2323 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2324 (lmute << 7) | left; 2325 2326 hdac_command(sc, 2327 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2328} 2329 2330static void 2331hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2332 int left, int right) 2333{ 2334 struct hdac_softc *sc; 2335 nid_t nid, cad; 2336 int lmute, rmute; 2337 2338 if (ctl == NULL || ctl->widget == NULL || 2339 ctl->widget->devinfo == NULL || 2340 ctl->widget->devinfo->codec == NULL || 2341 ctl->widget->devinfo->codec->sc == NULL) 2342 return; 2343 2344 sc = ctl->widget->devinfo->codec->sc; 2345 cad = ctl->widget->devinfo->codec->cad; 2346 nid = ctl->widget->nid; 2347 2348 if (mute == HDA_AMP_MUTE_DEFAULT) { 2349 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2350 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2351 } else { 2352 lmute = HDA_AMP_LEFT_MUTED(mute); 2353 rmute = HDA_AMP_RIGHT_MUTED(mute); 2354 } 2355 2356 if (ctl->dir & HDA_CTL_OUT) 2357 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2358 lmute, rmute, left, right, 0); 2359 if (ctl->dir & HDA_CTL_IN) 2360 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2361 lmute, rmute, left, right, 1); 2362 ctl->left = left; 2363 ctl->right = right; 2364} 2365 2366static void 2367hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2368{ 2369 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2370 return; 2371 hdac_command(w->devinfo->codec->sc, 2372 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2373 w->nid, index), w->devinfo->codec->cad); 2374 w->selconn = index; 2375} 2376 2377 2378/**************************************************************************** 2379 * uint32_t hdac_command_sendone_internal 2380 * 2381 * Wrapper function that sends only one command to a given codec 2382 ****************************************************************************/ 2383static uint32_t 2384hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2385{ 2386 struct hdac_command_list cl; 2387 uint32_t response = HDAC_INVALID; 2388 2389 if (!hdac_lockowned(sc)) 2390 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2391 cl.num_commands = 1; 2392 cl.verbs = &verb; 2393 cl.responses = &response; 2394 2395 hdac_command_send_internal(sc, &cl, cad); 2396 2397 return (response); 2398} 2399 2400/**************************************************************************** 2401 * hdac_command_send_internal 2402 * 2403 * Send a command list to the codec via the corb. We queue as much verbs as 2404 * we can and msleep on the codec. When the interrupt get the responses 2405 * back from the rirb, it will wake us up so we can queue the remaining verbs 2406 * if any. 2407 ****************************************************************************/ 2408static void 2409hdac_command_send_internal(struct hdac_softc *sc, 2410 struct hdac_command_list *commands, nid_t cad) 2411{ 2412 struct hdac_codec *codec; 2413 int corbrp; 2414 uint32_t *corb; 2415 int timeout; 2416 int retry = 10; 2417 struct hdac_rirb *rirb_base; 2418 2419 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2420 commands->num_commands < 1) 2421 return; 2422 2423 codec = sc->codecs[cad]; 2424 codec->commands = commands; 2425 codec->responses_received = 0; 2426 codec->verbs_sent = 0; 2427 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2428 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2429 2430 do { 2431 if (codec->verbs_sent != commands->num_commands) { 2432 /* Queue as many verbs as possible */ 2433 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2434 bus_dmamap_sync(sc->corb_dma.dma_tag, 2435 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2436 while (codec->verbs_sent != commands->num_commands && 2437 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2438 sc->corb_wp++; 2439 sc->corb_wp %= sc->corb_size; 2440 corb[sc->corb_wp] = 2441 commands->verbs[codec->verbs_sent++]; 2442 } 2443 2444 /* Send the verbs to the codecs */ 2445 bus_dmamap_sync(sc->corb_dma.dma_tag, 2446 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2447 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2448 } 2449 2450 timeout = 1000; 2451 while (hdac_rirb_flush(sc) == 0 && --timeout) 2452 DELAY(10); 2453 } while ((codec->verbs_sent != commands->num_commands || 2454 codec->responses_received != commands->num_commands) && --retry); 2455 2456 if (retry == 0) 2457 device_printf(sc->dev, 2458 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2459 __func__, commands->num_commands, codec->verbs_sent, 2460 codec->responses_received); 2461 2462 codec->commands = NULL; 2463 codec->responses_received = 0; 2464 codec->verbs_sent = 0; 2465 2466 hdac_unsolq_flush(sc); 2467} 2468 2469 2470/**************************************************************************** 2471 * Device Methods 2472 ****************************************************************************/ 2473 2474/**************************************************************************** 2475 * int hdac_probe(device_t) 2476 * 2477 * Probe for the presence of an hdac. If none is found, check for a generic 2478 * match using the subclass of the device. 2479 ****************************************************************************/ 2480static int 2481hdac_probe(device_t dev) 2482{ 2483 int i, result; 2484 uint32_t model; 2485 uint16_t class, subclass; 2486 char desc[64]; 2487 2488 model = (uint32_t)pci_get_device(dev) << 16; 2489 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2490 class = pci_get_class(dev); 2491 subclass = pci_get_subclass(dev); 2492 2493 bzero(desc, sizeof(desc)); 2494 result = ENXIO; 2495 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2496 if (hdac_devices[i].model == model) { 2497 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2498 result = BUS_PROBE_DEFAULT; 2499 break; 2500 } 2501 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2502 class == PCIC_MULTIMEDIA && 2503 subclass == PCIS_MULTIMEDIA_HDA) { 2504 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2505 result = BUS_PROBE_GENERIC; 2506 break; 2507 } 2508 } 2509 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2510 subclass == PCIS_MULTIMEDIA_HDA) { 2511 strlcpy(desc, "Generic", sizeof(desc)); 2512 result = BUS_PROBE_GENERIC; 2513 } 2514 if (result != ENXIO) { 2515 strlcat(desc, " High Definition Audio Controller", 2516 sizeof(desc)); 2517 device_set_desc_copy(dev, desc); 2518 } 2519 2520 return (result); 2521} 2522 2523static void * 2524hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2525 struct pcm_channel *c, int dir) 2526{ 2527 struct hdac_devinfo *devinfo = data; 2528 struct hdac_softc *sc = devinfo->codec->sc; 2529 struct hdac_chan *ch; 2530 2531 hdac_lock(sc); 2532 if (dir == PCMDIR_PLAY) { 2533 ch = &sc->play; 2534 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2535 ch->dir = PCMDIR_PLAY; 2536 ch->sid = ++sc->streamcnt; 2537 devinfo->function.audio.playcnt++; 2538 } else { 2539 ch = &sc->rec; 2540 ch->off = devinfo->function.audio.reccnt << 5; 2541 ch->dir = PCMDIR_REC; 2542 ch->sid = ++sc->streamcnt; 2543 devinfo->function.audio.reccnt++; 2544 } 2545 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2546 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2547 ch->pcmrates[0] = 48000; 2548 ch->pcmrates[1] = 0; 2549 } 2550 ch->b = b; 2551 ch->c = c; 2552 ch->devinfo = devinfo; 2553 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2554 ch->blkcnt = sc->chan_blkcnt; 2555 hdac_unlock(sc); 2556 2557 if (hdac_bdl_alloc(ch) != 0) { 2558 ch->blkcnt = 0; 2559 return (NULL); 2560 } 2561 2562 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2563 return (NULL); 2564 2565 hdac_dma_nocache(ch->b->buf); 2566 2567 return (ch); 2568} 2569 2570static int 2571hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2572{ 2573 struct hdac_chan *ch = data; 2574 int i; 2575 2576 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2577 if (format == ch->caps.fmtlist[i]) { 2578 ch->fmt = format; 2579 return (0); 2580 } 2581 } 2582 2583 return (EINVAL); 2584} 2585 2586static int 2587hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2588{ 2589 struct hdac_chan *ch = data; 2590 uint32_t spd = 0, threshold; 2591 int i; 2592 2593 for (i = 0; ch->pcmrates[i] != 0; i++) { 2594 spd = ch->pcmrates[i]; 2595 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2596 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2597 if (speed < threshold) 2598 break; 2599 } 2600 2601 if (spd == 0) /* impossible */ 2602 ch->spd = 48000; 2603 else 2604 ch->spd = spd; 2605 2606 return (ch->spd); 2607} 2608 2609static void 2610hdac_stream_setup(struct hdac_chan *ch) 2611{ 2612 struct hdac_softc *sc = ch->devinfo->codec->sc; 2613 int i; 2614 nid_t cad = ch->devinfo->codec->cad; 2615 uint16_t fmt; 2616 2617 fmt = 0; 2618 if (ch->fmt & AFMT_S16_LE) 2619 fmt |= ch->bit16 << 4; 2620 else if (ch->fmt & AFMT_S32_LE) 2621 fmt |= ch->bit32 << 4; 2622 else 2623 fmt |= 1 << 4; 2624 2625 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2626 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2627 fmt |= hda_rate_tab[i].base; 2628 fmt |= hda_rate_tab[i].mul; 2629 fmt |= hda_rate_tab[i].div; 2630 break; 2631 } 2632 } 2633 2634 if (ch->fmt & AFMT_STEREO) 2635 fmt |= 1; 2636 2637 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2638 2639 for (i = 0; ch->io[i] != -1; i++) { 2640 HDA_BOOTVERBOSE( 2641 device_printf(sc->dev, 2642 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2643 "fmt=0x%08x\n", 2644 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2645 ch->io[i], fmt); 2646 ); 2647 hdac_command(sc, 2648 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2649 hdac_command(sc, 2650 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2651 ch->sid << 4), cad); 2652 } 2653} 2654 2655static int 2656hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2657{ 2658 struct hdac_chan *ch = data; 2659 struct hdac_softc *sc = ch->devinfo->codec->sc; 2660 2661 blksz &= ~0x7f; 2662 if (blksz < 0x80) 2663 blksz = 0x80; 2664 2665 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2666 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2667 2668 if ((sndbuf_getblksz(ch->b) != blksz || 2669 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2670 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2671 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2672 __func__, blksz, ch->blkcnt); 2673 2674 ch->blksz = sndbuf_getblksz(ch->b); 2675 2676 return (ch->blksz); 2677} 2678 2679static void 2680hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2681{ 2682 struct hdac_devinfo *devinfo = ch->devinfo; 2683 nid_t cad = devinfo->codec->cad; 2684 int i; 2685 2686 hdac_stream_stop(ch); 2687 2688 for (i = 0; ch->io[i] != -1; i++) { 2689 hdac_command(sc, 2690 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2691 0), cad); 2692 } 2693} 2694 2695static void 2696hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2697{ 2698 ch->ptr = 0; 2699 ch->prevptr = 0; 2700 hdac_stream_stop(ch); 2701 hdac_stream_reset(ch); 2702 hdac_bdl_setup(ch); 2703 hdac_stream_setid(ch); 2704 hdac_stream_setup(ch); 2705 hdac_stream_start(ch); 2706} 2707 2708static int 2709hdac_channel_trigger(kobj_t obj, void *data, int go) 2710{ 2711 struct hdac_chan *ch = data; 2712 struct hdac_softc *sc = ch->devinfo->codec->sc; 2713 2714 hdac_lock(sc); 2715 switch (go) { 2716 case PCMTRIG_START: 2717 hdac_channel_start(sc, ch); 2718 break; 2719 case PCMTRIG_STOP: 2720 case PCMTRIG_ABORT: 2721 hdac_channel_stop(sc, ch); 2722 break; 2723 } 2724 hdac_unlock(sc); 2725 2726 return (0); 2727} 2728 2729static int 2730hdac_channel_getptr(kobj_t obj, void *data) 2731{ 2732 struct hdac_chan *ch = data; 2733 struct hdac_softc *sc = ch->devinfo->codec->sc; 2734 uint32_t ptr; 2735 2736 hdac_lock(sc); 2737 if (sc->polling != 0) 2738 ptr = ch->ptr; 2739 else 2740 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2741 hdac_unlock(sc); 2742 2743 /* 2744 * Round to available space and force 128 bytes aligment. 2745 */ 2746 ptr %= ch->blksz * ch->blkcnt; 2747 ptr &= ~0x7f; 2748 2749 return (ptr); 2750} 2751 2752static struct pcmchan_caps * 2753hdac_channel_getcaps(kobj_t obj, void *data) 2754{ 2755 return (&((struct hdac_chan *)data)->caps); 2756} 2757 2758static kobj_method_t hdac_channel_methods[] = { 2759 KOBJMETHOD(channel_init, hdac_channel_init), 2760 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2761 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2762 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2763 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2764 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2765 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2766 { 0, 0 } 2767}; 2768CHANNEL_DECLARE(hdac_channel); 2769 2770static int 2771hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2772{ 2773 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2774 struct hdac_softc *sc = devinfo->codec->sc; 2775 struct hdac_widget *w, *cw; 2776 struct hdac_audio_ctl *ctl; 2777 uint32_t mask, recmask, id; 2778 int i, j, softpcmvol; 2779 nid_t cad; 2780 2781 hdac_lock(sc); 2782 2783 mask = 0; 2784 recmask = 0; 2785 2786 id = hdac_codec_id(devinfo); 2787 cad = devinfo->codec->cad; 2788 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2789 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2790 sc->pci_subvendor) && 2791 hdac_hp_switch[i].id == id)) 2792 continue; 2793 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2794 if (w != NULL && w->enable != 0 2795 && w->type == 2796 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2797 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2798 hdac_command(sc, 2799 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2800 w->nid, 2801 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2802 HDAC_UNSOLTAG_EVENT_HP), cad); 2803 hdac_hp_switch_handler(devinfo); 2804 HDA_BOOTVERBOSE( 2805 device_printf(sc->dev, 2806 "HDA_DEBUG: Enabling headphone/speaker " 2807 "audio routing switching:\n"); 2808 device_printf(sc->dev, 2809 "HDA_DEBUG: \tindex=%d nid=%d " 2810 "pci_subvendor=0x%08x " 2811 "codec=0x%08x\n", 2812 i, w->nid, sc->pci_subvendor, id); 2813 ); 2814 } 2815 break; 2816 } 2817 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2818 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2819 sc->pci_subvendor) && 2820 hdac_eapd_switch[i].id == id)) 2821 continue; 2822 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2823 if (w == NULL || w->enable == 0) 2824 break; 2825 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2826 w->param.eapdbtl == HDAC_INVALID) 2827 break; 2828 mask |= SOUND_MASK_OGAIN; 2829 break; 2830 } 2831 2832 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2833 w = hdac_widget_get(devinfo, i); 2834 if (w == NULL || w->enable == 0) 2835 continue; 2836 mask |= w->ctlflags; 2837 if (!(w->pflags & HDA_ADC_RECSEL)) 2838 continue; 2839 for (j = 0; j < w->nconns; j++) { 2840 cw = hdac_widget_get(devinfo, w->conns[j]); 2841 if (cw == NULL || cw->enable == 0) 2842 continue; 2843 recmask |= cw->ctlflags; 2844 } 2845 } 2846 2847 if (!(mask & SOUND_MASK_PCM)) { 2848 softpcmvol = 1; 2849 mask |= SOUND_MASK_PCM; 2850 } else 2851 softpcmvol = (devinfo->function.audio.quirks & 2852 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2853 2854 i = 0; 2855 ctl = NULL; 2856 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2857 if (ctl->widget == NULL || ctl->enable == 0) 2858 continue; 2859 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2860 continue; 2861 if (ctl->step > 0) 2862 break; 2863 } 2864 2865 if (softpcmvol == 1 || ctl == NULL) { 2866 struct snddev_info *d = NULL; 2867 d = device_get_softc(sc->dev); 2868 if (d != NULL) { 2869 d->flags |= SD_F_SOFTPCMVOL; 2870 HDA_BOOTVERBOSE( 2871 device_printf(sc->dev, 2872 "HDA_DEBUG: %s Soft PCM volume\n", 2873 (softpcmvol == 1) ? 2874 "Forcing" : "Enabling"); 2875 ); 2876 } 2877 i = 0; 2878 /* 2879 * XXX Temporary quirk for STAC9220, until the parser 2880 * become smarter. 2881 */ 2882 if (id == HDA_CODEC_STAC9220) { 2883 mask |= SOUND_MASK_VOLUME; 2884 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2885 NULL) { 2886 if (ctl->widget == NULL || ctl->enable == 0) 2887 continue; 2888 if (ctl->widget->nid == 11 && ctl->index == 0) { 2889 ctl->ossmask = SOUND_MASK_VOLUME; 2890 ctl->ossval = 100 | (100 << 8); 2891 } else 2892 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2893 } 2894 } else { 2895 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2896 SOUND_MASK_PCM); 2897 if (!(mask & SOUND_MASK_VOLUME)) 2898 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2899 SOUND_MIXER_NONE); 2900 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2901 NULL) { 2902 if (ctl->widget == NULL || ctl->enable == 0) 2903 continue; 2904 if (!HDA_FLAG_MATCH(ctl->ossmask, 2905 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2906 continue; 2907 if (!(ctl->mute == 1 && ctl->step == 0)) 2908 ctl->enable = 0; 2909 } 2910 } 2911 } 2912 2913 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2914 2915 mix_setrecdevs(m, recmask); 2916 mix_setdevs(m, mask); 2917 2918 hdac_unlock(sc); 2919 2920 return (0); 2921} 2922 2923static int 2924hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2925 unsigned left, unsigned right) 2926{ 2927 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2928 struct hdac_softc *sc = devinfo->codec->sc; 2929 struct hdac_widget *w; 2930 struct hdac_audio_ctl *ctl; 2931 uint32_t id, mute; 2932 int lvol, rvol, mlvol, mrvol; 2933 int i = 0; 2934 2935 hdac_lock(sc); 2936 if (dev == SOUND_MIXER_OGAIN) { 2937 uint32_t orig; 2938 /*if (left != right || !(left == 0 || left == 1)) { 2939 hdac_unlock(sc); 2940 return (-1); 2941 }*/ 2942 id = hdac_codec_id(devinfo); 2943 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2944 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2945 sc->pci_subvendor) && 2946 hdac_eapd_switch[i].id == id) 2947 break; 2948 } 2949 if (i >= HDAC_EAPD_SWITCH_LEN) { 2950 hdac_unlock(sc); 2951 return (-1); 2952 } 2953 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2954 if (w == NULL || 2955 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2956 w->param.eapdbtl == HDAC_INVALID) { 2957 hdac_unlock(sc); 2958 return (-1); 2959 } 2960 orig = w->param.eapdbtl; 2961 if (left == 0) 2962 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2963 else 2964 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2965 if (orig != w->param.eapdbtl) { 2966 uint32_t val; 2967 2968 if (hdac_eapd_switch[i].hp_switch != 0) 2969 hdac_hp_switch_handler(devinfo); 2970 val = w->param.eapdbtl; 2971 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2972 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2973 hdac_command(sc, 2974 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2975 w->nid, val), devinfo->codec->cad); 2976 } 2977 hdac_unlock(sc); 2978 return (left | (left << 8)); 2979 } 2980 if (dev == SOUND_MIXER_VOLUME) 2981 devinfo->function.audio.mvol = left | (right << 8); 2982 2983 mlvol = devinfo->function.audio.mvol & 0x7f; 2984 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2985 lvol = 0; 2986 rvol = 0; 2987 2988 i = 0; 2989 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2990 if (ctl->widget == NULL || ctl->enable == 0 || 2991 !(ctl->ossmask & (1 << dev))) 2992 continue; 2993 switch (dev) { 2994 case SOUND_MIXER_VOLUME: 2995 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2996 lvol = (lvol * ctl->step) / 100; 2997 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2998 rvol = (rvol * ctl->step) / 100; 2999 break; 3000 default: 3001 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3002 lvol = (left * mlvol) / 100; 3003 lvol = (lvol * ctl->step) / 100; 3004 rvol = (right * mrvol) / 100; 3005 rvol = (rvol * ctl->step) / 100; 3006 } else { 3007 lvol = (left * ctl->step) / 100; 3008 rvol = (right * ctl->step) / 100; 3009 } 3010 ctl->ossval = left | (right << 8); 3011 break; 3012 } 3013 mute = 0; 3014 if (ctl->step < 1) { 3015 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3016 (ctl->muted & HDA_AMP_MUTE_LEFT); 3017 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3018 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3019 } else { 3020 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3021 (ctl->muted & HDA_AMP_MUTE_LEFT); 3022 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3023 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3024 } 3025 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3026 } 3027 hdac_unlock(sc); 3028 3029 return (left | (right << 8)); 3030} 3031 3032static int 3033hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3034{ 3035 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3036 struct hdac_widget *w, *cw; 3037 struct hdac_softc *sc = devinfo->codec->sc; 3038 uint32_t ret = src, target; 3039 int i, j; 3040 3041 target = 0; 3042 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3043 if (src & (1 << i)) { 3044 target = 1 << i; 3045 break; 3046 } 3047 } 3048 3049 hdac_lock(sc); 3050 3051 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3052 w = hdac_widget_get(devinfo, i); 3053 if (w == NULL || w->enable == 0) 3054 continue; 3055 if (!(w->pflags & HDA_ADC_RECSEL)) 3056 continue; 3057 for (j = 0; j < w->nconns; j++) { 3058 cw = hdac_widget_get(devinfo, w->conns[j]); 3059 if (cw == NULL || cw->enable == 0) 3060 continue; 3061 if ((target == SOUND_MASK_VOLUME && 3062 cw->type != 3063 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3064 (target != SOUND_MASK_VOLUME && 3065 cw->type == 3066 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3067 continue; 3068 if (cw->ctlflags & target) { 3069 hdac_widget_connection_select(w, j); 3070 ret = target; 3071 j += w->nconns; 3072 } 3073 } 3074 } 3075 3076 hdac_unlock(sc); 3077 3078 return (ret); 3079} 3080 3081static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3082 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3083 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3084 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3085 { 0, 0 } 3086}; 3087MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3088 3089/**************************************************************************** 3090 * int hdac_attach(device_t) 3091 * 3092 * Attach the device into the kernel. Interrupts usually won't be enabled 3093 * when this function is called. Setup everything that doesn't require 3094 * interrupts and defer probing of codecs until interrupts are enabled. 3095 ****************************************************************************/ 3096static int 3097hdac_attach(device_t dev) 3098{ 3099 struct hdac_softc *sc; 3100 int result; 3101 int i = 0; 3102 3103 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3104 if (sc == NULL) { 3105 device_printf(dev, "cannot allocate softc\n"); 3106 return (ENOMEM); 3107 } 3108 3109 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3110 if (sc->lock == NULL) { 3111 device_printf(dev, "mutex creation failed\n"); 3112 free(sc, M_DEVBUF); 3113 return (ENOMEM); 3114 } 3115 3116 sc->dev = dev; 3117 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3118 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3119 3120 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3121 /* Screw nx6325 - subdevice/subvendor swapped */ 3122 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3123 } 3124 3125 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3126 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3127 3128 sc->poll_ticks = 1; 3129 if (resource_int_value(device_get_name(sc->dev), 3130 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3131 sc->polling = 1; 3132 else 3133 sc->polling = 0; 3134 3135 sc->chan_size = pcm_getbuffersize(dev, 3136 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3137 3138 if (resource_int_value(device_get_name(sc->dev), 3139 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3140 i &= ~0x7f; 3141 if (i < 0x80) 3142 i = 0x80; 3143 sc->chan_blkcnt = sc->chan_size / i; 3144 i = 0; 3145 while (sc->chan_blkcnt >> i) 3146 i++; 3147 sc->chan_blkcnt = 1 << (i - 1); 3148 if (sc->chan_blkcnt < HDA_BDL_MIN) 3149 sc->chan_blkcnt = HDA_BDL_MIN; 3150 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3151 sc->chan_blkcnt = HDA_BDL_MAX; 3152 } else 3153 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3154 3155 result = bus_dma_tag_create(NULL, /* parent */ 3156 HDAC_DMA_ALIGNMENT, /* alignment */ 3157 0, /* boundary */ 3158 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3159 BUS_SPACE_MAXADDR, /* highaddr */ 3160 NULL, /* filtfunc */ 3161 NULL, /* fistfuncarg */ 3162 sc->chan_size, /* maxsize */ 3163 1, /* nsegments */ 3164 sc->chan_size, /* maxsegsz */ 3165 0, /* flags */ 3166 NULL, /* lockfunc */ 3167 NULL, /* lockfuncarg */ 3168 &sc->chan_dmat); /* dmat */ 3169 if (result != 0) { 3170 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3171 __func__, result); 3172 snd_mtxfree(sc->lock); 3173 free(sc, M_DEVBUF); 3174 return (ENXIO); 3175 } 3176 3177 3178 sc->hdabus = NULL; 3179 for (i = 0; i < HDAC_CODEC_MAX; i++) 3180 sc->codecs[i] = NULL; 3181 3182 pci_enable_busmaster(dev); 3183 3184 /* Allocate resources */ 3185 result = hdac_mem_alloc(sc); 3186 if (result != 0) 3187 goto hdac_attach_fail; 3188 result = hdac_irq_alloc(sc); 3189 if (result != 0) 3190 goto hdac_attach_fail; 3191 3192 /* Get Capabilities */ 3193 result = hdac_get_capabilities(sc); 3194 if (result != 0) 3195 goto hdac_attach_fail; 3196 3197 /* Allocate CORB and RIRB dma memory */ 3198 result = hdac_dma_alloc(sc, &sc->corb_dma, 3199 sc->corb_size * sizeof(uint32_t)); 3200 if (result != 0) 3201 goto hdac_attach_fail; 3202 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3203 sc->rirb_size * sizeof(struct hdac_rirb)); 3204 if (result != 0) 3205 goto hdac_attach_fail; 3206 3207 /* Quiesce everything */ 3208 hdac_reset(sc); 3209 3210 /* Disable PCI-Express QOS */ 3211 pci_write_config(sc->dev, 0x44, 3212 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3213 3214 /* Initialize the CORB and RIRB */ 3215 hdac_corb_init(sc); 3216 hdac_rirb_init(sc); 3217 3218 /* Defer remaining of initialization until interrupts are enabled */ 3219 sc->intrhook.ich_func = hdac_attach2; 3220 sc->intrhook.ich_arg = (void *)sc; 3221 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3222 sc->intrhook.ich_func = NULL; 3223 hdac_attach2((void *)sc); 3224 } 3225 3226 return (0); 3227 3228hdac_attach_fail: 3229 hdac_dma_free(&sc->rirb_dma); 3230 hdac_dma_free(&sc->corb_dma); 3231 hdac_irq_free(sc); 3232 hdac_mem_free(sc); 3233 snd_mtxfree(sc->lock); 3234 free(sc, M_DEVBUF); 3235 3236 return (ENXIO); 3237} 3238 3239static void 3240hdac_audio_parse(struct hdac_devinfo *devinfo) 3241{ 3242 struct hdac_softc *sc = devinfo->codec->sc; 3243 struct hdac_widget *w; 3244 uint32_t res; 3245 int i; 3246 nid_t cad, nid; 3247 3248 cad = devinfo->codec->cad; 3249 nid = devinfo->nid; 3250 3251 hdac_command(sc, 3252 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3253 3254 DELAY(100); 3255 3256 res = hdac_command(sc, 3257 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3258 3259 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3260 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3261 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3262 3263 HDA_BOOTVERBOSE( 3264 device_printf(sc->dev, " Vendor: 0x%08x\n", 3265 devinfo->vendor_id); 3266 device_printf(sc->dev, " Device: 0x%08x\n", 3267 devinfo->device_id); 3268 device_printf(sc->dev, " Revision: 0x%08x\n", 3269 devinfo->revision_id); 3270 device_printf(sc->dev, " Stepping: 0x%08x\n", 3271 devinfo->stepping_id); 3272 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3273 sc->pci_subvendor); 3274 device_printf(sc->dev, " Nodes: start=%d " 3275 "endnode=%d total=%d\n", 3276 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3277 ); 3278 3279 res = hdac_command(sc, 3280 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3281 cad); 3282 devinfo->function.audio.supp_stream_formats = res; 3283 3284 res = hdac_command(sc, 3285 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3286 cad); 3287 devinfo->function.audio.supp_pcm_size_rate = res; 3288 3289 res = hdac_command(sc, 3290 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3291 cad); 3292 devinfo->function.audio.outamp_cap = res; 3293 3294 res = hdac_command(sc, 3295 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3296 cad); 3297 devinfo->function.audio.inamp_cap = res; 3298 3299 if (devinfo->nodecnt > 0) { 3300 hdac_unlock(sc); 3301 devinfo->widget = (struct hdac_widget *)malloc( 3302 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3303 M_NOWAIT | M_ZERO); 3304 hdac_lock(sc); 3305 } else 3306 devinfo->widget = NULL; 3307 3308 if (devinfo->widget == NULL) { 3309 device_printf(sc->dev, "unable to allocate widgets!\n"); 3310 devinfo->endnode = devinfo->startnode; 3311 devinfo->nodecnt = 0; 3312 return; 3313 } 3314 3315 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3316 w = hdac_widget_get(devinfo, i); 3317 if (w == NULL) 3318 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3319 else { 3320 w->devinfo = devinfo; 3321 w->nid = i; 3322 w->enable = 1; 3323 w->selconn = -1; 3324 w->pflags = 0; 3325 w->ctlflags = 0; 3326 w->param.eapdbtl = HDAC_INVALID; 3327 hdac_widget_parse(w); 3328 } 3329 } 3330} 3331 3332static void 3333hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3334{ 3335 struct hdac_softc *sc = devinfo->codec->sc; 3336 struct hdac_audio_ctl *ctls; 3337 struct hdac_widget *w, *cw; 3338 int i, j, cnt, max, ocap, icap; 3339 int mute, offset, step, size; 3340 3341 /* XXX This is redundant */ 3342 max = 0; 3343 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3344 w = hdac_widget_get(devinfo, i); 3345 if (w == NULL || w->enable == 0) 3346 continue; 3347 if (w->param.outamp_cap != 0) 3348 max++; 3349 if (w->param.inamp_cap != 0) { 3350 switch (w->type) { 3351 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3352 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3353 for (j = 0; j < w->nconns; j++) { 3354 cw = hdac_widget_get(devinfo, 3355 w->conns[j]); 3356 if (cw == NULL || cw->enable == 0) 3357 continue; 3358 max++; 3359 } 3360 break; 3361 default: 3362 max++; 3363 break; 3364 } 3365 } 3366 } 3367 3368 devinfo->function.audio.ctlcnt = max; 3369 3370 if (max < 1) 3371 return; 3372 3373 hdac_unlock(sc); 3374 ctls = (struct hdac_audio_ctl *)malloc( 3375 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3376 hdac_lock(sc); 3377 3378 if (ctls == NULL) { 3379 /* Blekh! */ 3380 device_printf(sc->dev, "unable to allocate ctls!\n"); 3381 devinfo->function.audio.ctlcnt = 0; 3382 return; 3383 } 3384 3385 cnt = 0; 3386 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3387 if (cnt >= max) { 3388 device_printf(sc->dev, "%s: Ctl overflow!\n", 3389 __func__); 3390 break; 3391 } 3392 w = hdac_widget_get(devinfo, i); 3393 if (w == NULL || w->enable == 0) 3394 continue; 3395 ocap = w->param.outamp_cap; 3396 icap = w->param.inamp_cap; 3397 if (ocap != 0) { 3398 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3399 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3400 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3401 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3402 /*if (offset > step) { 3403 HDA_BOOTVERBOSE( 3404 device_printf(sc->dev, 3405 "HDA_DEBUG: BUGGY outamp: nid=%d " 3406 "[offset=%d > step=%d]\n", 3407 w->nid, offset, step); 3408 ); 3409 offset = step; 3410 }*/ 3411 ctls[cnt].enable = 1; 3412 ctls[cnt].widget = w; 3413 ctls[cnt].mute = mute; 3414 ctls[cnt].step = step; 3415 ctls[cnt].size = size; 3416 ctls[cnt].offset = offset; 3417 ctls[cnt].left = offset; 3418 ctls[cnt].right = offset; 3419 ctls[cnt++].dir = HDA_CTL_OUT; 3420 } 3421 3422 if (icap != 0) { 3423 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3424 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3425 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3426 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3427 /*if (offset > step) { 3428 HDA_BOOTVERBOSE( 3429 device_printf(sc->dev, 3430 "HDA_DEBUG: BUGGY inamp: nid=%d " 3431 "[offset=%d > step=%d]\n", 3432 w->nid, offset, step); 3433 ); 3434 offset = step; 3435 }*/ 3436 switch (w->type) { 3437 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3438 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3439 for (j = 0; j < w->nconns; j++) { 3440 if (cnt >= max) { 3441 device_printf(sc->dev, 3442 "%s: Ctl overflow!\n", 3443 __func__); 3444 break; 3445 } 3446 cw = hdac_widget_get(devinfo, 3447 w->conns[j]); 3448 if (cw == NULL || cw->enable == 0) 3449 continue; 3450 ctls[cnt].enable = 1; 3451 ctls[cnt].widget = w; 3452 ctls[cnt].childwidget = cw; 3453 ctls[cnt].index = j; 3454 ctls[cnt].mute = mute; 3455 ctls[cnt].step = step; 3456 ctls[cnt].size = size; 3457 ctls[cnt].offset = offset; 3458 ctls[cnt].left = offset; 3459 ctls[cnt].right = offset; 3460 ctls[cnt++].dir = HDA_CTL_IN; 3461 } 3462 break; 3463 default: 3464 if (cnt >= max) { 3465 device_printf(sc->dev, 3466 "%s: Ctl overflow!\n", 3467 __func__); 3468 break; 3469 } 3470 ctls[cnt].enable = 1; 3471 ctls[cnt].widget = w; 3472 ctls[cnt].mute = mute; 3473 ctls[cnt].step = step; 3474 ctls[cnt].size = size; 3475 ctls[cnt].offset = offset; 3476 ctls[cnt].left = offset; 3477 ctls[cnt].right = offset; 3478 ctls[cnt++].dir = HDA_CTL_IN; 3479 break; 3480 } 3481 } 3482 } 3483 3484 devinfo->function.audio.ctl = ctls; 3485} 3486 3487static const struct { 3488 uint32_t model; 3489 uint32_t id; 3490 uint32_t set, unset; 3491} hdac_quirks[] = { 3492 /* 3493 * XXX Force stereo quirk. Monoural recording / playback 3494 * on few codecs (especially ALC880) seems broken or 3495 * perhaps unsupported. 3496 */ 3497 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3498 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3499 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3500 HDA_QUIRK_GPIO0, 0 }, 3501 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3502 HDA_QUIRK_GPIO0, 0 }, 3503 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3504 HDA_QUIRK_GPIO0, 0 }, 3505 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3506 HDA_QUIRK_EAPDINV, 0 }, 3507 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3508 HDA_QUIRK_EAPDINV, 0 }, 3509 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3510 HDA_QUIRK_GPIO1, 0 }, 3511 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3512 HDA_QUIRK_EAPDINV, 0 }, 3513 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3514 HDA_QUIRK_EAPDINV, 0 }, 3515 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3516 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3517 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3518 0, HDA_QUIRK_FORCESTEREO }, 3519 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3520 HDA_QUIRK_SOFTPCMVOL, 0 } 3521}; 3522#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3523 3524static void 3525hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3526{ 3527 struct hdac_widget *w; 3528 uint32_t id, subvendor; 3529 int i; 3530 3531 id = hdac_codec_id(devinfo); 3532 subvendor = devinfo->codec->sc->pci_subvendor; 3533 3534 /* 3535 * Quirks 3536 */ 3537 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3538 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3539 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3540 continue; 3541 if (hdac_quirks[i].set != 0) 3542 devinfo->function.audio.quirks |= 3543 hdac_quirks[i].set; 3544 if (hdac_quirks[i].unset != 0) 3545 devinfo->function.audio.quirks &= 3546 ~(hdac_quirks[i].unset); 3547 } 3548 3549 switch (id) { 3550 case HDA_CODEC_ALC260: 3551 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3552 w = hdac_widget_get(devinfo, i); 3553 if (w == NULL || w->enable == 0) 3554 continue; 3555 if (w->type != 3556 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3557 continue; 3558 if (w->nid != 5) 3559 w->enable = 0; 3560 } 3561 break; 3562 case HDA_CODEC_ALC861: 3563 if (subvendor == ASUS_P1AH2_SUBVENDOR) { 3564 struct hdac_audio_ctl *ctl; 3565 3566 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3567 if (ctl != NULL) 3568 ctl->muted = HDA_AMP_MUTE_ALL; 3569 } 3570 break; 3571 case HDA_CODEC_ALC880: 3572 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3573 w = hdac_widget_get(devinfo, i); 3574 if (w == NULL || w->enable == 0) 3575 continue; 3576 if (w->type == 3577 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3578 w->nid != 9 && w->nid != 29) { 3579 w->enable = 0; 3580 } else if (w->type != 3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3582 w->nid == 29) { 3583 w->type = 3584 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3585 w->param.widget_cap &= 3586 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3587 w->param.widget_cap |= 3588 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3589 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3590 strlcpy(w->name, "beep widget", sizeof(w->name)); 3591 } 3592 } 3593 break; 3594 case HDA_CODEC_AD1981HD: 3595 w = hdac_widget_get(devinfo, 11); 3596 if (w != NULL && w->enable != 0 && w->nconns > 3) 3597 w->selconn = 3; 3598 if (subvendor == IBM_M52_SUBVENDOR) { 3599 struct hdac_audio_ctl *ctl; 3600 3601 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3602 if (ctl != NULL) 3603 ctl->ossmask = SOUND_MASK_SPEAKER; 3604 } 3605 break; 3606 case HDA_CODEC_AD1986A: 3607 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3608 w = hdac_widget_get(devinfo, i); 3609 if (w == NULL || w->enable == 0) 3610 continue; 3611 if (w->type != 3612 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3613 continue; 3614 if (w->nid != 3) 3615 w->enable = 0; 3616 } 3617 break; 3618 case HDA_CODEC_STAC9221: 3619 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3620 w = hdac_widget_get(devinfo, i); 3621 if (w == NULL || w->enable == 0) 3622 continue; 3623 if (w->type != 3624 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3625 continue; 3626 if (w->nid != 2) 3627 w->enable = 0; 3628 } 3629 break; 3630 case HDA_CODEC_STAC9221D: 3631 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3632 w = hdac_widget_get(devinfo, i); 3633 if (w == NULL || w->enable == 0) 3634 continue; 3635 if (w->type == 3636 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3637 w->nid != 6) 3638 w->enable = 0; 3639 3640 } 3641 break; 3642 default: 3643 break; 3644 } 3645} 3646 3647static int 3648hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3649{ 3650 int *dev = &devinfo->function.audio.ossidx; 3651 3652 while (*dev < SOUND_MIXER_NRDEVICES) { 3653 switch (*dev) { 3654 case SOUND_MIXER_VOLUME: 3655 case SOUND_MIXER_BASS: 3656 case SOUND_MIXER_TREBLE: 3657 case SOUND_MIXER_PCM: 3658 case SOUND_MIXER_SPEAKER: 3659 case SOUND_MIXER_LINE: 3660 case SOUND_MIXER_MIC: 3661 case SOUND_MIXER_CD: 3662 case SOUND_MIXER_RECLEV: 3663 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3664 (*dev)++; 3665 break; 3666 default: 3667 return (*dev)++; 3668 break; 3669 } 3670 } 3671 3672 return (-1); 3673} 3674 3675static int 3676hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3677{ 3678 struct hdac_widget *w; 3679 int i, ret = 0; 3680 3681 if (depth > HDA_PARSE_MAXDEPTH) 3682 return (0); 3683 w = hdac_widget_get(devinfo, nid); 3684 if (w == NULL || w->enable == 0) 3685 return (0); 3686 switch (w->type) { 3687 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3688 w->pflags |= HDA_DAC_PATH; 3689 ret = 1; 3690 break; 3691 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3692 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3693 for (i = 0; i < w->nconns; i++) { 3694 if (hdac_widget_find_dac_path(devinfo, 3695 w->conns[i], depth + 1) != 0) { 3696 if (w->selconn == -1) 3697 w->selconn = i; 3698 ret = 1; 3699 w->pflags |= HDA_DAC_PATH; 3700 } 3701 } 3702 break; 3703 default: 3704 break; 3705 } 3706 return (ret); 3707} 3708 3709static int 3710hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3711{ 3712 struct hdac_widget *w; 3713 int i, conndev, ret = 0; 3714 3715 if (depth > HDA_PARSE_MAXDEPTH) 3716 return (0); 3717 w = hdac_widget_get(devinfo, nid); 3718 if (w == NULL || w->enable == 0) 3719 return (0); 3720 switch (w->type) { 3721 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3722 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3723 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3724 for (i = 0; i < w->nconns; i++) { 3725 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3726 depth + 1) != 0) { 3727 if (w->selconn == -1) 3728 w->selconn = i; 3729 w->pflags |= HDA_ADC_PATH; 3730 ret = 1; 3731 } 3732 } 3733 break; 3734 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3735 conndev = w->wclass.pin.config & 3736 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3737 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3738 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3739 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3740 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3741 w->pflags |= HDA_ADC_PATH; 3742 ret = 1; 3743 } 3744 break; 3745 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3746 if (w->pflags & HDA_DAC_PATH) { 3747 w->pflags |= HDA_ADC_PATH; 3748 ret = 1; 3749 } 3750 break;*/ 3751 default: 3752 break; 3753 } 3754 return (ret); 3755} 3756 3757static uint32_t 3758hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3759 nid_t nid, nid_t pnid, int index, int depth) 3760{ 3761 struct hdac_widget *w, *pw; 3762 struct hdac_audio_ctl *ctl; 3763 uint32_t fl = 0; 3764 int i, ossdev, conndev, strategy; 3765 3766 if (depth > HDA_PARSE_MAXDEPTH) 3767 return (0); 3768 3769 w = hdac_widget_get(devinfo, nid); 3770 if (w == NULL || w->enable == 0) 3771 return (0); 3772 3773 pw = hdac_widget_get(devinfo, pnid); 3774 strategy = devinfo->function.audio.parsing_strategy; 3775 3776 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3777 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3778 for (i = 0; i < w->nconns; i++) { 3779 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3780 w->nid, i, depth + 1); 3781 } 3782 w->ctlflags |= fl; 3783 return (fl); 3784 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3785 (w->pflags & HDA_DAC_PATH)) { 3786 i = 0; 3787 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3788 if (ctl->enable == 0 || ctl->widget == NULL) 3789 continue; 3790 /* XXX This should be compressed! */ 3791 if ((ctl->widget->nid == w->nid) || 3792 (ctl->widget->nid == pnid && ctl->index == index && 3793 (ctl->dir & HDA_CTL_IN)) || 3794 (ctl->widget->nid == pnid && pw != NULL && 3795 pw->type == 3796 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3797 (pw->nconns < 2 || pw->selconn == index || 3798 pw->selconn == -1) && 3799 (ctl->dir & HDA_CTL_OUT)) || 3800 (strategy == HDA_PARSE_DIRECT && 3801 ctl->widget->nid == w->nid)) { 3802 /*if (pw != NULL && pw->selconn == -1) 3803 pw->selconn = index; 3804 fl |= SOUND_MASK_VOLUME; 3805 fl |= SOUND_MASK_PCM; 3806 ctl->ossmask |= SOUND_MASK_VOLUME; 3807 ctl->ossmask |= SOUND_MASK_PCM; 3808 ctl->ossdev = SOUND_MIXER_PCM;*/ 3809 if (!(w->ctlflags & SOUND_MASK_PCM) || 3810 (pw != NULL && 3811 !(pw->ctlflags & SOUND_MASK_PCM))) { 3812 fl |= SOUND_MASK_VOLUME; 3813 fl |= SOUND_MASK_PCM; 3814 ctl->ossmask |= SOUND_MASK_VOLUME; 3815 ctl->ossmask |= SOUND_MASK_PCM; 3816 ctl->ossdev = SOUND_MIXER_PCM; 3817 w->ctlflags |= SOUND_MASK_VOLUME; 3818 w->ctlflags |= SOUND_MASK_PCM; 3819 if (pw != NULL) { 3820 if (pw->selconn == -1) 3821 pw->selconn = index; 3822 pw->ctlflags |= 3823 SOUND_MASK_VOLUME; 3824 pw->ctlflags |= 3825 SOUND_MASK_PCM; 3826 } 3827 } 3828 } 3829 } 3830 w->ctlflags |= fl; 3831 return (fl); 3832 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3833 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3834 (w->pflags & HDA_ADC_PATH)) { 3835 conndev = w->wclass.pin.config & 3836 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3837 i = 0; 3838 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3839 if (ctl->enable == 0 || ctl->widget == NULL) 3840 continue; 3841 /* XXX This should be compressed! */ 3842 if (((ctl->widget->nid == pnid && ctl->index == index && 3843 (ctl->dir & HDA_CTL_IN)) || 3844 (ctl->widget->nid == pnid && pw != NULL && 3845 pw->type == 3846 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3847 (pw->nconns < 2 || pw->selconn == index || 3848 pw->selconn == -1) && 3849 (ctl->dir & HDA_CTL_OUT)) || 3850 (strategy == HDA_PARSE_DIRECT && 3851 ctl->widget->nid == w->nid)) && 3852 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3853 if (pw != NULL && pw->selconn == -1) 3854 pw->selconn = index; 3855 ossdev = 0; 3856 switch (conndev) { 3857 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3858 ossdev = SOUND_MIXER_MIC; 3859 break; 3860 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3861 ossdev = SOUND_MIXER_LINE; 3862 break; 3863 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3864 ossdev = SOUND_MIXER_CD; 3865 break; 3866 default: 3867 ossdev = 3868 hdac_audio_ctl_ossmixer_getnextdev( 3869 devinfo); 3870 if (ossdev < 0) 3871 ossdev = 0; 3872 break; 3873 } 3874 if (strategy == HDA_PARSE_MIXER) { 3875 fl |= SOUND_MASK_VOLUME; 3876 ctl->ossmask |= SOUND_MASK_VOLUME; 3877 } 3878 fl |= 1 << ossdev; 3879 ctl->ossmask |= 1 << ossdev; 3880 ctl->ossdev = ossdev; 3881 } 3882 } 3883 w->ctlflags |= fl; 3884 return (fl); 3885 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3886 i = 0; 3887 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3888 if (ctl->enable == 0 || ctl->widget == NULL) 3889 continue; 3890 /* XXX This should be compressed! */ 3891 if (((ctl->widget->nid == pnid && ctl->index == index && 3892 (ctl->dir & HDA_CTL_IN)) || 3893 (ctl->widget->nid == pnid && pw != NULL && 3894 pw->type == 3895 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3896 (pw->nconns < 2 || pw->selconn == index || 3897 pw->selconn == -1) && 3898 (ctl->dir & HDA_CTL_OUT)) || 3899 (strategy == HDA_PARSE_DIRECT && 3900 ctl->widget->nid == w->nid)) && 3901 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3902 if (pw != NULL && pw->selconn == -1) 3903 pw->selconn = index; 3904 fl |= SOUND_MASK_VOLUME; 3905 fl |= SOUND_MASK_SPEAKER; 3906 ctl->ossmask |= SOUND_MASK_VOLUME; 3907 ctl->ossmask |= SOUND_MASK_SPEAKER; 3908 ctl->ossdev = SOUND_MIXER_SPEAKER; 3909 } 3910 } 3911 w->ctlflags |= fl; 3912 return (fl); 3913 } 3914 return (0); 3915} 3916 3917static uint32_t 3918hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3919{ 3920 struct hdac_widget *w, *cw; 3921 struct hdac_audio_ctl *ctl; 3922 uint32_t fl; 3923 int i; 3924 3925 if (depth > HDA_PARSE_MAXDEPTH) 3926 return (0); 3927 3928 w = hdac_widget_get(devinfo, nid); 3929 if (w == NULL || w->enable == 0) 3930 return (0); 3931 /*if (!(w->pflags & HDA_ADC_PATH)) 3932 return (0); 3933 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3934 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3935 return (0);*/ 3936 i = 0; 3937 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3938 if (ctl->enable == 0 || ctl->widget == NULL) 3939 continue; 3940 if (ctl->widget->nid == nid) { 3941 ctl->ossmask |= SOUND_MASK_RECLEV; 3942 w->ctlflags |= SOUND_MASK_RECLEV; 3943 return (SOUND_MASK_RECLEV); 3944 } 3945 } 3946 for (i = 0; i < w->nconns; i++) { 3947 cw = hdac_widget_get(devinfo, w->conns[i]); 3948 if (cw == NULL || cw->enable == 0) 3949 continue; 3950 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3951 continue; 3952 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3953 if (fl != 0) { 3954 cw->ctlflags |= fl; 3955 w->ctlflags |= fl; 3956 return (fl); 3957 } 3958 } 3959 return (0); 3960} 3961 3962static int 3963hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3964{ 3965 struct hdac_widget *w, *cw; 3966 int i, child = 0; 3967 3968 if (depth > HDA_PARSE_MAXDEPTH) 3969 return (0); 3970 3971 w = hdac_widget_get(devinfo, nid); 3972 if (w == NULL || w->enable == 0) 3973 return (0); 3974 /*if (!(w->pflags & HDA_ADC_PATH)) 3975 return (0); 3976 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3977 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3978 return (0);*/ 3979 /* XXX weak! */ 3980 for (i = 0; i < w->nconns; i++) { 3981 cw = hdac_widget_get(devinfo, w->conns[i]); 3982 if (cw == NULL) 3983 continue; 3984 if (++child > 1) { 3985 w->pflags |= HDA_ADC_RECSEL; 3986 return (1); 3987 } 3988 } 3989 for (i = 0; i < w->nconns; i++) { 3990 if (hdac_audio_ctl_recsel_build(devinfo, 3991 w->conns[i], depth + 1) != 0) 3992 return (1); 3993 } 3994 return (0); 3995} 3996 3997static int 3998hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3999{ 4000 struct hdac_widget *w, *cw; 4001 int i, j, conndev, found_dac = 0; 4002 int strategy; 4003 4004 strategy = devinfo->function.audio.parsing_strategy; 4005 4006 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4007 w = hdac_widget_get(devinfo, i); 4008 if (w == NULL || w->enable == 0) 4009 continue; 4010 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4011 continue; 4012 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4013 continue; 4014 conndev = w->wclass.pin.config & 4015 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4016 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4017 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4018 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4019 continue; 4020 for (j = 0; j < w->nconns; j++) { 4021 cw = hdac_widget_get(devinfo, w->conns[j]); 4022 if (cw == NULL || cw->enable == 0) 4023 continue; 4024 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4025 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4026 cw->type == 4027 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4028 continue; 4029 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4030 != 0) { 4031 if (w->selconn == -1) 4032 w->selconn = j; 4033 w->pflags |= HDA_DAC_PATH; 4034 found_dac++; 4035 } 4036 } 4037 } 4038 4039 return (found_dac); 4040} 4041 4042static void 4043hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4044{ 4045 struct hdac_widget *w; 4046 struct hdac_audio_ctl *ctl; 4047 int i, j, dacs, strategy; 4048 4049 /* Construct DAC path */ 4050 strategy = HDA_PARSE_MIXER; 4051 devinfo->function.audio.parsing_strategy = strategy; 4052 HDA_BOOTVERBOSE( 4053 device_printf(devinfo->codec->sc->dev, 4054 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4055 HDA_WIDGET_PARSER_REV); 4056 ); 4057 dacs = hdac_audio_build_tree_strategy(devinfo); 4058 if (dacs == 0) { 4059 HDA_BOOTVERBOSE( 4060 device_printf(devinfo->codec->sc->dev, 4061 "HDA_DEBUG: HWiP: 0 DAC path found! " 4062 "Retrying parser " 4063 "using HDA_PARSE_DIRECT strategy.\n"); 4064 ); 4065 strategy = HDA_PARSE_DIRECT; 4066 devinfo->function.audio.parsing_strategy = strategy; 4067 dacs = hdac_audio_build_tree_strategy(devinfo); 4068 } 4069 4070 HDA_BOOTVERBOSE( 4071 device_printf(devinfo->codec->sc->dev, 4072 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4073 "strategy.\n", 4074 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4075 ); 4076 4077 /* Construct ADC path */ 4078 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4079 w = hdac_widget_get(devinfo, i); 4080 if (w == NULL || w->enable == 0) 4081 continue; 4082 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4083 continue; 4084 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4085 } 4086 4087 /* Output mixers */ 4088 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4089 w = hdac_widget_get(devinfo, i); 4090 if (w == NULL || w->enable == 0) 4091 continue; 4092 if ((strategy == HDA_PARSE_MIXER && 4093 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4094 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4095 && (w->pflags & HDA_DAC_PATH)) || 4096 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4097 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4098 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4099 w->nid, devinfo->startnode - 1, 0, 0); 4100 } else if (w->type == 4101 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4102 j = 0; 4103 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4104 NULL) { 4105 if (ctl->enable == 0 || ctl->widget == NULL) 4106 continue; 4107 if (ctl->widget->nid != w->nid) 4108 continue; 4109 ctl->ossmask |= SOUND_MASK_VOLUME; 4110 ctl->ossmask |= SOUND_MASK_SPEAKER; 4111 ctl->ossdev = SOUND_MIXER_SPEAKER; 4112 w->ctlflags |= SOUND_MASK_VOLUME; 4113 w->ctlflags |= SOUND_MASK_SPEAKER; 4114 } 4115 } 4116 } 4117 4118 /* Input mixers (rec) */ 4119 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4120 w = hdac_widget_get(devinfo, i); 4121 if (w == NULL || w->enable == 0) 4122 continue; 4123 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4124 w->pflags & HDA_ADC_PATH)) 4125 continue; 4126 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4127 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4128 } 4129} 4130 4131#define HDA_COMMIT_CONN (1 << 0) 4132#define HDA_COMMIT_CTRL (1 << 1) 4133#define HDA_COMMIT_EAPD (1 << 2) 4134#define HDA_COMMIT_GPIO (1 << 3) 4135#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4136 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4137 4138static void 4139hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4140{ 4141 struct hdac_softc *sc = devinfo->codec->sc; 4142 struct hdac_widget *w; 4143 nid_t cad; 4144 int i; 4145 4146 if (!(cfl & HDA_COMMIT_ALL)) 4147 return; 4148 4149 cad = devinfo->codec->cad; 4150 4151 if (cfl & HDA_COMMIT_GPIO) { 4152 uint32_t gdata, gmask, gdir; 4153 int commitgpio = 0; 4154 4155 gdata = 0; 4156 gmask = 0; 4157 gdir = 0; 4158 4159 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4160 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4161 0x7e7, 0), cad); 4162 4163 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4164 commitgpio = 1; 4165 else { 4166 for (i = 0; i < HDA_GPIO_MAX; i++) { 4167 if (!(devinfo->function.audio.quirks & 4168 (1 << i))) 4169 continue; 4170 if (commitgpio == 0) { 4171 commitgpio = 1; 4172 gdata = hdac_command(sc, 4173 HDA_CMD_GET_GPIO_DATA(cad, 4174 devinfo->nid), cad); 4175 gmask = hdac_command(sc, 4176 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4177 devinfo->nid), cad); 4178 gdir = hdac_command(sc, 4179 HDA_CMD_GET_GPIO_DIRECTION(cad, 4180 devinfo->nid), cad); 4181 HDA_BOOTVERBOSE( 4182 device_printf(sc->dev, 4183 "GPIO init: data=0x%08x " 4184 "mask=0x%08x dir=0x%08x\n", 4185 gdata, gmask, gdir); 4186 ); 4187 } 4188 gdata |= 1 << i; 4189 gmask |= 1 << i; 4190 gdir |= 1 << i; 4191 } 4192 } 4193 4194 if (commitgpio != 0) { 4195 HDA_BOOTVERBOSE( 4196 device_printf(sc->dev, 4197 "GPIO commit: data=0x%08x mask=0x%08x " 4198 "dir=0x%08x\n", 4199 gdata, gmask, gdir); 4200 ); 4201 hdac_command(sc, 4202 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4203 gmask), cad); 4204 hdac_command(sc, 4205 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4206 gdir), cad); 4207 hdac_command(sc, 4208 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4209 gdata), cad); 4210 } 4211 } 4212 4213 for (i = 0; i < devinfo->nodecnt; i++) { 4214 w = &devinfo->widget[i]; 4215 if (w == NULL || w->enable == 0) 4216 continue; 4217 if (cfl & HDA_COMMIT_CONN) { 4218 if (w->selconn == -1) 4219 w->selconn = 0; 4220 if (w->nconns > 0) 4221 hdac_widget_connection_select(w, w->selconn); 4222 } 4223 if ((cfl & HDA_COMMIT_CTRL) && 4224 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4225 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4226 (HDA_DAC_PATH | HDA_ADC_PATH)) 4227 device_printf(sc->dev, "WARNING: node %d " 4228 "participate both for DAC/ADC!\n", w->nid); 4229 if (w->pflags & HDA_DAC_PATH) { 4230 w->wclass.pin.ctrl &= 4231 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4232 if ((w->wclass.pin.config & 4233 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4234 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4235 w->wclass.pin.ctrl &= 4236 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4237 } else if (w->pflags & HDA_ADC_PATH) { 4238 w->wclass.pin.ctrl &= 4239 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4240 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4241 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4242 uint32_t pincap = w->wclass.pin.cap; 4243 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4244 w->wclass.pin.ctrl |= 4245 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4246 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4247 ); 4248 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4249 w->wclass.pin.ctrl |= 4250 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4251 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4252 ); 4253 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4254 w->wclass.pin.ctrl |= 4255 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4256 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4257 ); 4258 } 4259 } else 4260 w->wclass.pin.ctrl &= ~( 4261 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4262 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4263 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4264 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4265 hdac_command(sc, 4266 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4267 w->wclass.pin.ctrl), cad); 4268 } 4269 if ((cfl & HDA_COMMIT_EAPD) && 4270 w->param.eapdbtl != HDAC_INVALID) { 4271 uint32_t val; 4272 4273 val = w->param.eapdbtl; 4274 if (devinfo->function.audio.quirks & 4275 HDA_QUIRK_EAPDINV) 4276 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4277 hdac_command(sc, 4278 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4279 val), cad); 4280 4281 } 4282 DELAY(1000); 4283 } 4284} 4285 4286static void 4287hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4288{ 4289 struct hdac_softc *sc = devinfo->codec->sc; 4290 struct hdac_audio_ctl *ctl; 4291 int i; 4292 4293 devinfo->function.audio.mvol = 100 | (100 << 8); 4294 i = 0; 4295 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4296 if (ctl->enable == 0 || ctl->widget == NULL) { 4297 HDA_BOOTVERBOSE( 4298 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4299 i, (ctl->widget != NULL) ? 4300 ctl->widget->nid : -1); 4301 if (ctl->childwidget != NULL) 4302 printf(" childnid=%d", 4303 ctl->childwidget->nid); 4304 if (ctl->widget == NULL) 4305 printf(" NULL WIDGET!"); 4306 printf(" DISABLED\n"); 4307 ); 4308 continue; 4309 } 4310 HDA_BOOTVERBOSE( 4311 if (ctl->ossmask == 0) { 4312 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4313 i, ctl->widget->nid); 4314 if (ctl->childwidget != NULL) 4315 printf(" childnid=%d", 4316 ctl->childwidget->nid); 4317 printf(" Bind to NONE\n"); 4318 } 4319 ); 4320 if (ctl->step > 0) { 4321 ctl->ossval = (ctl->left * 100) / ctl->step; 4322 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4323 } else 4324 ctl->ossval = 0; 4325 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4326 ctl->left, ctl->right); 4327 } 4328} 4329 4330static int 4331hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4332{ 4333 struct hdac_chan *ch; 4334 struct hdac_widget *w; 4335 uint32_t cap, fmtcap, pcmcap, path; 4336 int i, type, ret, max; 4337 4338 if (dir == PCMDIR_PLAY) { 4339 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4340 ch = &devinfo->codec->sc->play; 4341 path = HDA_DAC_PATH; 4342 } else { 4343 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4344 ch = &devinfo->codec->sc->rec; 4345 path = HDA_ADC_PATH; 4346 } 4347 4348 ch->caps = hdac_caps; 4349 ch->caps.fmtlist = ch->fmtlist; 4350 ch->bit16 = 1; 4351 ch->bit32 = 0; 4352 ch->pcmrates[0] = 48000; 4353 ch->pcmrates[1] = 0; 4354 4355 ret = 0; 4356 fmtcap = devinfo->function.audio.supp_stream_formats; 4357 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4358 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4359 4360 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4361 w = hdac_widget_get(devinfo, i); 4362 if (w == NULL || w->enable == 0 || w->type != type || 4363 !(w->pflags & path)) 4364 continue; 4365 cap = w->param.widget_cap; 4366 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4367 continue;*/ 4368 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4369 continue; 4370 cap = w->param.supp_stream_formats; 4371 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4372 } 4373 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4374 }*/ 4375 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4376 continue; 4377 if (ret == 0) { 4378 fmtcap = w->param.supp_stream_formats; 4379 pcmcap = w->param.supp_pcm_size_rate; 4380 } else { 4381 fmtcap &= w->param.supp_stream_formats; 4382 pcmcap &= w->param.supp_pcm_size_rate; 4383 } 4384 ch->io[ret++] = i; 4385 } 4386 ch->io[ret] = -1; 4387 4388 ch->supp_stream_formats = fmtcap; 4389 ch->supp_pcm_size_rate = pcmcap; 4390 4391 /* 4392 * 8bit = 0 4393 * 16bit = 1 4394 * 20bit = 2 4395 * 24bit = 3 4396 * 32bit = 4 4397 */ 4398 if (ret > 0) { 4399 cap = pcmcap; 4400 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4401 ch->bit16 = 1; 4402 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4403 ch->bit16 = 0; 4404 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4405 ch->bit32 = 4; 4406 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4407 ch->bit32 = 3; 4408 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4409 ch->bit32 = 2; 4410 i = 0; 4411 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4412 ch->fmtlist[i++] = AFMT_S16_LE; 4413 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4414 if (ch->bit32 > 0) { 4415 if (!(devinfo->function.audio.quirks & 4416 HDA_QUIRK_FORCESTEREO)) 4417 ch->fmtlist[i++] = AFMT_S32_LE; 4418 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4419 } 4420 ch->fmtlist[i] = 0; 4421 i = 0; 4422 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4423 ch->pcmrates[i++] = 8000; 4424 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4425 ch->pcmrates[i++] = 11025; 4426 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4427 ch->pcmrates[i++] = 16000; 4428 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4429 ch->pcmrates[i++] = 22050; 4430 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4431 ch->pcmrates[i++] = 32000; 4432 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4433 ch->pcmrates[i++] = 44100; 4434 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4435 ch->pcmrates[i++] = 48000; 4436 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4437 ch->pcmrates[i++] = 88200; 4438 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4439 ch->pcmrates[i++] = 96000; 4440 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4441 ch->pcmrates[i++] = 176400; 4442 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4443 ch->pcmrates[i++] = 192000; 4444 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4445 ch->pcmrates[i] = 0; 4446 if (i > 0) { 4447 ch->caps.minspeed = ch->pcmrates[0]; 4448 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4449 } 4450 } 4451 4452 return (ret); 4453} 4454 4455static void 4456hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4457{ 4458 struct hdac_audio_ctl *ctl; 4459 struct hdac_softc *sc = devinfo->codec->sc; 4460 int i; 4461 uint32_t fl = 0; 4462 4463 4464 if (flag == 0) { 4465 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4466 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4467 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4468 } 4469 4470 i = 0; 4471 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4472 if (ctl->enable == 0 || ctl->widget == NULL || 4473 ctl->widget->enable == 0) 4474 continue; 4475 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4476 (flag != 0 && (ctl->ossmask & flag))) { 4477 if (banner != NULL) { 4478 device_printf(sc->dev, "\n"); 4479 device_printf(sc->dev, "%s\n", banner); 4480 } 4481 goto hdac_ctl_dump_it_all; 4482 } 4483 } 4484 4485 return; 4486 4487hdac_ctl_dump_it_all: 4488 i = 0; 4489 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4490 if (ctl->enable == 0 || ctl->widget == NULL || 4491 ctl->widget->enable == 0) 4492 continue; 4493 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4494 (flag != 0 && (ctl->ossmask & flag)))) 4495 continue; 4496 if (flag == 0) { 4497 device_printf(sc->dev, "\n"); 4498 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4499 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4500 } 4501 device_printf(sc->dev, " |\n"); 4502 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4503 ctl->widget->nid, ctl->index); 4504 if (ctl->childwidget != NULL) 4505 printf("(nid: %2d) ", ctl->childwidget->nid); 4506 else 4507 printf(" "); 4508 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4509 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4510 ctl->ossmask); 4511 } 4512} 4513 4514static void 4515hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4516{ 4517 uint32_t cap; 4518 4519 cap = fcap; 4520 if (cap != 0) { 4521 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4522 device_printf(sc->dev, " Format:"); 4523 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4524 printf(" AC3"); 4525 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4526 printf(" FLOAT32"); 4527 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4528 printf(" PCM"); 4529 printf("\n"); 4530 } 4531 cap = pcmcap; 4532 if (cap != 0) { 4533 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4534 device_printf(sc->dev, " PCM size:"); 4535 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4536 printf(" 8"); 4537 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4538 printf(" 16"); 4539 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4540 printf(" 20"); 4541 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4542 printf(" 24"); 4543 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4544 printf(" 32"); 4545 printf("\n"); 4546 device_printf(sc->dev, " PCM rate:"); 4547 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4548 printf(" 8"); 4549 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4550 printf(" 11"); 4551 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4552 printf(" 16"); 4553 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4554 printf(" 22"); 4555 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4556 printf(" 32"); 4557 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4558 printf(" 44"); 4559 printf(" 48"); 4560 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4561 printf(" 88"); 4562 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4563 printf(" 96"); 4564 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4565 printf(" 176"); 4566 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4567 printf(" 192"); 4568 printf("\n"); 4569 } 4570} 4571 4572static void 4573hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4574{ 4575 uint32_t pincap, wcap; 4576 4577 pincap = w->wclass.pin.cap; 4578 wcap = w->param.widget_cap; 4579 4580 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4581 device_printf(sc->dev, " "); 4582 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4583 printf(" ISC"); 4584 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4585 printf(" TRQD"); 4586 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4587 printf(" PDC"); 4588 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4589 printf(" HP"); 4590 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4591 printf(" OUT"); 4592 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4593 printf(" IN"); 4594 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4595 printf(" BAL"); 4596 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4597 printf(" VREF["); 4598 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4599 printf(" 50"); 4600 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4601 printf(" 80"); 4602 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4603 printf(" 100"); 4604 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4605 printf(" GROUND"); 4606 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4607 printf(" HIZ"); 4608 printf(" ]"); 4609 } 4610 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4611 printf(" EAPD"); 4612 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4613 printf(" : UNSOL"); 4614 printf("\n"); 4615 device_printf(sc->dev, " Pin config: 0x%08x\n", 4616 w->wclass.pin.config); 4617 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4618 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4619 printf(" HP"); 4620 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4621 printf(" IN"); 4622 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4623 printf(" OUT"); 4624 printf("\n"); 4625} 4626 4627static void 4628hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4629{ 4630 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4631 device_printf(sc->dev, " " 4632 "mute=%d step=%d size=%d offset=%d\n", 4633 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4634 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4635 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4636 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4637} 4638 4639static void 4640hdac_dump_nodes(struct hdac_devinfo *devinfo) 4641{ 4642 struct hdac_softc *sc = devinfo->codec->sc; 4643 struct hdac_widget *w, *cw; 4644 int i, j; 4645 4646 device_printf(sc->dev, "\n"); 4647 device_printf(sc->dev, "Default Parameter\n"); 4648 device_printf(sc->dev, "-----------------\n"); 4649 hdac_dump_audio_formats(sc, 4650 devinfo->function.audio.supp_stream_formats, 4651 devinfo->function.audio.supp_pcm_size_rate); 4652 device_printf(sc->dev, " IN amp: 0x%08x\n", 4653 devinfo->function.audio.inamp_cap); 4654 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4655 devinfo->function.audio.outamp_cap); 4656 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4657 w = hdac_widget_get(devinfo, i); 4658 if (w == NULL) { 4659 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4660 continue; 4661 } 4662 device_printf(sc->dev, "\n"); 4663 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4664 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4665 "DIGITAL" : "ANALOG", 4666 (w->enable == 0) ? " [DISABLED]" : ""); 4667 device_printf(sc->dev, " name: %s\n", w->name); 4668 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4669 w->param.widget_cap); 4670 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4671 w->pflags); 4672 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4673 w->ctlflags); 4674 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4675 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4676 hdac_dump_audio_formats(sc, 4677 w->param.supp_stream_formats, 4678 w->param.supp_pcm_size_rate); 4679 } else if (w->type == 4680 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4681 hdac_dump_pin(sc, w); 4682 if (w->param.eapdbtl != HDAC_INVALID) 4683 device_printf(sc->dev, " EAPD: 0x%08x\n", 4684 w->param.eapdbtl); 4685 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4686 w->param.outamp_cap != 0) 4687 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4688 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4689 w->param.inamp_cap != 0) 4690 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4691 device_printf(sc->dev, " connections: %d\n", w->nconns); 4692 for (j = 0; j < w->nconns; j++) { 4693 cw = hdac_widget_get(devinfo, w->conns[j]); 4694 device_printf(sc->dev, " |\n"); 4695 device_printf(sc->dev, " + <- nid=%d [%s]", 4696 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4697 if (cw == NULL) 4698 printf(" [UNKNOWN]"); 4699 else if (cw->enable == 0) 4700 printf(" [DISABLED]"); 4701 if (w->nconns > 1 && w->selconn == j && w->type != 4702 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4703 printf(" (selected)"); 4704 printf("\n"); 4705 } 4706 } 4707 4708} 4709 4710static int 4711hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4712{ 4713 struct hdac_widget *w, *cw; 4714 struct hdac_softc *sc = devinfo->codec->sc; 4715 int i; 4716 4717 if (depth > HDA_PARSE_MAXDEPTH) 4718 return (0); 4719 4720 w = hdac_widget_get(devinfo, nid); 4721 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4722 return (0); 4723 4724 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4725 device_printf(sc->dev, "\n"); 4726 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4727 device_printf(sc->dev, " ^\n"); 4728 device_printf(sc->dev, " |\n"); 4729 device_printf(sc->dev, " +-----<------+\n"); 4730 } else { 4731 device_printf(sc->dev, " ^\n"); 4732 device_printf(sc->dev, " |\n"); 4733 device_printf(sc->dev, " "); 4734 printf(" nid=%d [%s]\n", w->nid, w->name); 4735 } 4736 4737 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4738 return (1); 4739 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4740 for (i = 0; i < w->nconns; i++) { 4741 cw = hdac_widget_get(devinfo, w->conns[i]); 4742 if (cw == NULL || cw->enable == 0 || cw->type == 4743 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4744 continue; 4745 if (hdac_dump_dac_internal(devinfo, cw->nid, 4746 depth + 1) != 0) 4747 return (1); 4748 } 4749 } else if ((w->type == 4750 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4751 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4752 w->selconn > -1 && w->selconn < w->nconns) { 4753 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4754 depth + 1) != 0) 4755 return (1); 4756 } 4757 4758 return (0); 4759} 4760 4761static void 4762hdac_dump_dac(struct hdac_devinfo *devinfo) 4763{ 4764 struct hdac_widget *w; 4765 struct hdac_softc *sc = devinfo->codec->sc; 4766 int i, printed = 0; 4767 4768 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4769 w = hdac_widget_get(devinfo, i); 4770 if (w == NULL || w->enable == 0) 4771 continue; 4772 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4773 !(w->pflags & HDA_DAC_PATH)) 4774 continue; 4775 if (printed == 0) { 4776 printed = 1; 4777 device_printf(sc->dev, "\n"); 4778 device_printf(sc->dev, "Playback path:\n"); 4779 } 4780 hdac_dump_dac_internal(devinfo, w->nid, 0); 4781 } 4782} 4783 4784static void 4785hdac_dump_adc(struct hdac_devinfo *devinfo) 4786{ 4787 struct hdac_widget *w, *cw; 4788 struct hdac_softc *sc = devinfo->codec->sc; 4789 int i, j; 4790 int printed = 0; 4791 char ossdevs[256]; 4792 4793 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4794 w = hdac_widget_get(devinfo, i); 4795 if (w == NULL || w->enable == 0) 4796 continue; 4797 if (!(w->pflags & HDA_ADC_RECSEL)) 4798 continue; 4799 if (printed == 0) { 4800 printed = 1; 4801 device_printf(sc->dev, "\n"); 4802 device_printf(sc->dev, "Recording sources:\n"); 4803 } 4804 device_printf(sc->dev, "\n"); 4805 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4806 for (j = 0; j < w->nconns; j++) { 4807 cw = hdac_widget_get(devinfo, w->conns[j]); 4808 if (cw == NULL || cw->enable == 0) 4809 continue; 4810 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4811 ossdevs, sizeof(ossdevs)); 4812 device_printf(sc->dev, " |\n"); 4813 device_printf(sc->dev, " + <- nid=%d [%s]", 4814 cw->nid, cw->name); 4815 if (strlen(ossdevs) > 0) { 4816 printf(" [recsrc: %s]", ossdevs); 4817 } 4818 printf("\n"); 4819 } 4820 } 4821} 4822 4823static void 4824hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4825{ 4826 nid_t *nids; 4827 4828 if (pcnt > 0) { 4829 device_printf(sc->dev, "\n"); 4830 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4831 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4832 sc->play.supp_pcm_size_rate); 4833 device_printf(sc->dev, " DAC:"); 4834 for (nids = sc->play.io; *nids != -1; nids++) 4835 printf(" %d", *nids); 4836 printf("\n"); 4837 } 4838 4839 if (rcnt > 0) { 4840 device_printf(sc->dev, "\n"); 4841 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4842 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4843 sc->rec.supp_pcm_size_rate); 4844 device_printf(sc->dev, " ADC:"); 4845 for (nids = sc->rec.io; *nids != -1; nids++) 4846 printf(" %d", *nids); 4847 printf("\n"); 4848 } 4849} 4850 4851static void 4852hdac_release_resources(struct hdac_softc *sc) 4853{ 4854 struct hdac_devinfo *devinfo = NULL; 4855 device_t *devlist = NULL; 4856 int i, devcount; 4857 4858 if (sc == NULL) 4859 return; 4860 4861 hdac_lock(sc); 4862 if (sc->polling != 0) 4863 callout_stop(&sc->poll_hdac); 4864 hdac_reset(sc); 4865 hdac_unlock(sc); 4866 snd_mtxfree(sc->lock); 4867 4868 device_get_children(sc->dev, &devlist, &devcount); 4869 for (i = 0; devlist != NULL && i < devcount; i++) { 4870 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4871 if (devinfo == NULL) 4872 continue; 4873 if (devinfo->widget != NULL) 4874 free(devinfo->widget, M_HDAC); 4875 if (devinfo->node_type == 4876 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4877 devinfo->function.audio.ctl != NULL) 4878 free(devinfo->function.audio.ctl, M_HDAC); 4879 free(devinfo, M_HDAC); 4880 device_delete_child(sc->dev, devlist[i]); 4881 } 4882 if (devlist != NULL) 4883 free(devlist, M_TEMP); 4884 4885 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4886 if (sc->codecs[i] != NULL) 4887 free(sc->codecs[i], M_HDAC); 4888 sc->codecs[i] = NULL; 4889 } 4890 4891 hdac_dma_free(&sc->rirb_dma); 4892 hdac_dma_free(&sc->corb_dma); 4893 if (sc->play.blkcnt > 0) 4894 hdac_dma_free(&sc->play.bdl_dma); 4895 if (sc->rec.blkcnt > 0) 4896 hdac_dma_free(&sc->rec.bdl_dma); 4897 hdac_irq_free(sc); 4898 hdac_mem_free(sc); 4899 free(sc, M_DEVBUF); 4900 4901} 4902 4903/* This function surely going to make its way into upper level someday. */ 4904static void 4905hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4906{ 4907 const char *res = NULL; 4908 int i = 0, j, k, len, inv; 4909 4910 if (on != NULL) 4911 *on = 0; 4912 if (off != NULL) 4913 *off = 0; 4914 if (sc == NULL) 4915 return; 4916 if (resource_string_value(device_get_name(sc->dev), 4917 device_get_unit(sc->dev), "config", &res) != 0) 4918 return; 4919 if (!(res != NULL && strlen(res) > 0)) 4920 return; 4921 HDA_BOOTVERBOSE( 4922 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4923 ); 4924 for (;;) { 4925 while (res[i] != '\0' && 4926 (res[i] == ',' || isspace(res[i]) != 0)) 4927 i++; 4928 if (res[i] == '\0') { 4929 HDA_BOOTVERBOSE( 4930 printf("\n"); 4931 ); 4932 return; 4933 } 4934 j = i; 4935 while (res[j] != '\0' && 4936 !(res[j] == ',' || isspace(res[j]) != 0)) 4937 j++; 4938 len = j - i; 4939 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4940 inv = 2; 4941 else 4942 inv = 0; 4943 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4944 if (strncmp(res + i + inv, 4945 hdac_quirks_tab[k].key, len - inv) != 0) 4946 continue; 4947 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4948 break; 4949 HDA_BOOTVERBOSE( 4950 printf(" %s%s", (inv != 0) ? "no" : "", 4951 hdac_quirks_tab[k].key); 4952 ); 4953 if (inv == 0 && on != NULL) 4954 *on |= hdac_quirks_tab[k].value; 4955 else if (inv != 0 && off != NULL) 4956 *off |= hdac_quirks_tab[k].value; 4957 break; 4958 } 4959 i = j; 4960 } 4961} 4962 4963#ifdef SND_DYNSYSCTL 4964static int 4965sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4966{ 4967 struct hdac_softc *sc; 4968 struct hdac_devinfo *devinfo; 4969 device_t dev; 4970 uint32_t ctl; 4971 int err, val; 4972 4973 dev = oidp->oid_arg1; 4974 devinfo = pcm_getdevinfo(dev); 4975 if (devinfo == NULL || devinfo->codec == NULL || 4976 devinfo->codec->sc == NULL) 4977 return (EINVAL); 4978 sc = devinfo->codec->sc; 4979 hdac_lock(sc); 4980 val = sc->polling; 4981 hdac_unlock(sc); 4982 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4983 4984 if (err || req->newptr == NULL) 4985 return (err); 4986 if (val < 0 || val > 1) 4987 return (EINVAL); 4988 4989 hdac_lock(sc); 4990 if (val != sc->polling) { 4991 if (hda_chan_active(sc) != 0) 4992 err = EBUSY; 4993 else if (val == 0) { 4994 callout_stop(&sc->poll_hdac); 4995 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 4996 sc->rirb_size / 2); 4997 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4998 ctl |= HDAC_RIRBCTL_RINTCTL; 4999 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5000 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5001 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5002 sc->polling = 0; 5003 DELAY(1000); 5004 } else { 5005 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5006 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5007 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5008 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5009 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5010 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5011 sc); 5012 sc->polling = 1; 5013 DELAY(1000); 5014 } 5015 } 5016 hdac_unlock(sc); 5017 5018 return (err); 5019} 5020#endif 5021 5022static void 5023hdac_attach2(void *arg) 5024{ 5025 struct hdac_softc *sc; 5026 struct hdac_widget *w; 5027 struct hdac_audio_ctl *ctl; 5028 uint32_t quirks_on, quirks_off; 5029 int pcnt, rcnt; 5030 int i; 5031 char status[SND_STATUSLEN]; 5032 device_t *devlist = NULL; 5033 int devcount; 5034 struct hdac_devinfo *devinfo = NULL; 5035 5036 sc = (struct hdac_softc *)arg; 5037 5038 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5039 5040 HDA_BOOTVERBOSE( 5041 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5042 quirks_on, quirks_off); 5043 ); 5044 5045 hdac_lock(sc); 5046 5047 /* Remove ourselves from the config hooks */ 5048 if (sc->intrhook.ich_func != NULL) { 5049 config_intrhook_disestablish(&sc->intrhook); 5050 sc->intrhook.ich_func = NULL; 5051 } 5052 5053 /* Start the corb and rirb engines */ 5054 HDA_BOOTVERBOSE( 5055 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5056 ); 5057 hdac_corb_start(sc); 5058 HDA_BOOTVERBOSE( 5059 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5060 ); 5061 hdac_rirb_start(sc); 5062 5063 HDA_BOOTVERBOSE( 5064 device_printf(sc->dev, 5065 "HDA_DEBUG: Enabling controller interrupt...\n"); 5066 ); 5067 if (sc->polling == 0) 5068 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5069 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5070 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5071 HDAC_GCTL_UNSOL); 5072 5073 DELAY(1000); 5074 5075 HDA_BOOTVERBOSE( 5076 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5077 ); 5078 hdac_scan_codecs(sc); 5079 5080 device_get_children(sc->dev, &devlist, &devcount); 5081 for (i = 0; devlist != NULL && i < devcount; i++) { 5082 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5083 if (devinfo != NULL && devinfo->node_type == 5084 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5085 break; 5086 } else 5087 devinfo = NULL; 5088 } 5089 if (devlist != NULL) 5090 free(devlist, M_TEMP); 5091 5092 if (devinfo == NULL) { 5093 hdac_unlock(sc); 5094 device_printf(sc->dev, "Audio Function Group not found!\n"); 5095 hdac_release_resources(sc); 5096 return; 5097 } 5098 5099 HDA_BOOTVERBOSE( 5100 device_printf(sc->dev, 5101 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5102 devinfo->nid, devinfo->codec->cad); 5103 ); 5104 hdac_audio_parse(devinfo); 5105 HDA_BOOTVERBOSE( 5106 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5107 ); 5108 hdac_audio_ctl_parse(devinfo); 5109 HDA_BOOTVERBOSE( 5110 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5111 ); 5112 hdac_vendor_patch_parse(devinfo); 5113 if (quirks_on != 0) 5114 devinfo->function.audio.quirks |= quirks_on; 5115 if (quirks_off != 0) 5116 devinfo->function.audio.quirks &= ~quirks_off; 5117 5118 /* XXX Disable all DIGITAL path. */ 5119 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5120 w = hdac_widget_get(devinfo, i); 5121 if (w == NULL) 5122 continue; 5123 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5124 w->enable = 0; 5125 continue; 5126 } 5127 /* XXX Disable useless pin ? */ 5128 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5129 (w->wclass.pin.config & 5130 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5131 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5132 w->enable = 0; 5133 } 5134 i = 0; 5135 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5136 if (ctl->widget == NULL) 5137 continue; 5138 w = ctl->widget; 5139 if (w->enable == 0) 5140 ctl->enable = 0; 5141 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5142 ctl->enable = 0; 5143 w = ctl->childwidget; 5144 if (w == NULL) 5145 continue; 5146 if (w->enable == 0 || 5147 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5148 ctl->enable = 0; 5149 } 5150 5151 HDA_BOOTVERBOSE( 5152 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5153 ); 5154 hdac_audio_build_tree(devinfo); 5155 5156 HDA_BOOTVERBOSE( 5157 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5158 ); 5159 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5160 HDA_BOOTVERBOSE( 5161 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5162 ); 5163 hdac_audio_ctl_commit(devinfo); 5164 5165 HDA_BOOTVERBOSE( 5166 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5167 ); 5168 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5169 HDA_BOOTVERBOSE( 5170 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5171 ); 5172 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5173 5174 hdac_unlock(sc); 5175 HDA_BOOTVERBOSE( 5176 device_printf(sc->dev, 5177 "HDA_DEBUG: OSS mixer initialization...\n"); 5178 ); 5179 5180 /* 5181 * There is no point of return after this. If the driver failed, 5182 * so be it. Let the detach procedure do all the cleanup. 5183 */ 5184 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5185 device_printf(sc->dev, "Can't register mixer\n"); 5186 5187 if (pcnt > 0) 5188 pcnt = 1; 5189 if (rcnt > 0) 5190 rcnt = 1; 5191 5192 HDA_BOOTVERBOSE( 5193 device_printf(sc->dev, 5194 "HDA_DEBUG: Registering PCM channels...\n"); 5195 ); 5196 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5197 device_printf(sc->dev, "Can't register PCM\n"); 5198 5199 sc->registered++; 5200 5201 for (i = 0; i < pcnt; i++) 5202 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5203 for (i = 0; i < rcnt; i++) 5204 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5205 5206#ifdef SND_DYNSYSCTL 5207 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5208 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5209 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5210 sysctl_hdac_polling, "I", "Enable polling mode"); 5211#endif 5212 5213 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5214 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5215 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5216 pcm_setstatus(sc->dev, status); 5217 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5218 HDA_BOOTVERBOSE( 5219 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5220 hdac_codec_id(devinfo)); 5221 ); 5222 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5223 HDA_DRV_TEST_REV); 5224 5225 HDA_BOOTVERBOSE( 5226 if (devinfo->function.audio.quirks != 0) { 5227 device_printf(sc->dev, "\n"); 5228 device_printf(sc->dev, "HDA config/quirks:"); 5229 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5230 if (devinfo->function.audio.quirks & 5231 hdac_quirks_tab[i].value) 5232 printf(" %s", hdac_quirks_tab[i].key); 5233 } 5234 printf("\n"); 5235 } 5236 device_printf(sc->dev, "\n"); 5237 device_printf(sc->dev, "+-------------------+\n"); 5238 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5239 device_printf(sc->dev, "+-------------------+\n"); 5240 hdac_dump_nodes(devinfo); 5241 device_printf(sc->dev, "\n"); 5242 device_printf(sc->dev, "+------------------------+\n"); 5243 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5244 device_printf(sc->dev, "+------------------------+\n"); 5245 device_printf(sc->dev, "\n"); 5246 i = 0; 5247 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5248 device_printf(sc->dev, "%3d: nid=%d", i, 5249 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5250 if (ctl->childwidget != NULL) 5251 printf(" cnid=%d", ctl->childwidget->nid); 5252 printf(" dir=0x%x index=%d " 5253 "ossmask=0x%08x ossdev=%d%s\n", 5254 ctl->dir, ctl->index, 5255 ctl->ossmask, ctl->ossdev, 5256 (ctl->enable == 0) ? " [DISABLED]" : ""); 5257 } 5258 device_printf(sc->dev, "\n"); 5259 device_printf(sc->dev, "+-----------------------------------+\n"); 5260 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5261 device_printf(sc->dev, "+-----------------------------------+\n"); 5262 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5263 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5264 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5265 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5266 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5267 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5268 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5269 hdac_dump_ctls(devinfo, NULL, 0); 5270 hdac_dump_dac(devinfo); 5271 hdac_dump_adc(devinfo); 5272 device_printf(sc->dev, "\n"); 5273 device_printf(sc->dev, "+--------------------------------------+\n"); 5274 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5275 device_printf(sc->dev, "+--------------------------------------+\n"); 5276 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5277 ); 5278 5279 if (sc->polling != 0) { 5280 hdac_lock(sc); 5281 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5282 hdac_unlock(sc); 5283 } 5284} 5285 5286/**************************************************************************** 5287 * int hdac_detach(device_t) 5288 * 5289 * Detach and free up resources utilized by the hdac device. 5290 ****************************************************************************/ 5291static int 5292hdac_detach(device_t dev) 5293{ 5294 struct hdac_softc *sc = NULL; 5295 struct hdac_devinfo *devinfo = NULL; 5296 int err; 5297 5298 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5299 if (devinfo != NULL && devinfo->codec != NULL) 5300 sc = devinfo->codec->sc; 5301 if (sc == NULL) 5302 return (0); 5303 5304 if (sc->registered > 0) { 5305 err = pcm_unregister(dev); 5306 if (err != 0) 5307 return (err); 5308 } 5309 5310 hdac_release_resources(sc); 5311 5312 return (0); 5313} 5314 5315static device_method_t hdac_methods[] = { 5316 /* device interface */ 5317 DEVMETHOD(device_probe, hdac_probe), 5318 DEVMETHOD(device_attach, hdac_attach), 5319 DEVMETHOD(device_detach, hdac_detach), 5320 { 0, 0 } 5321}; 5322 5323static driver_t hdac_driver = { 5324 "pcm", 5325 hdac_methods, 5326 PCM_SOFTC_SIZE, 5327}; 5328 5329DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5330MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5331MODULE_VERSION(snd_hda, 1); 5332