hdac.c revision 165103
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061210_0037" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 165103 2006-12-11 18:45:11Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 193#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 194#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 195 196/* IBM / Lenovo */ 197#define IBM_VENDORID 0x1014 198#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 199#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 200 201/* Lenovo */ 202#define LENOVO_VENDORID 0x17aa 203#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 204#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 205 206/* Samsung */ 207#define SAMSUNG_VENDORID 0x144d 208#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 209#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 210 211/* Medion ? */ 212#define MEDION_VENDORID 0x161f 213#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 214#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 215 216/* 217 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 218 * instead of their own, which is beyond my comprehension 219 * (see HDA_CODEC_STAC9221 below). 220 */ 221#define APPLE_INTEL_MAC 0x76808384 222 223/* Misc constants.. */ 224#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 225#define HDA_AMP_MUTE_NONE (0) 226#define HDA_AMP_MUTE_LEFT (1 << 0) 227#define HDA_AMP_MUTE_RIGHT (1 << 1) 228#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 229 230#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 231#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 232 233#define HDA_DAC_PATH (1 << 0) 234#define HDA_ADC_PATH (1 << 1) 235#define HDA_ADC_RECSEL (1 << 2) 236 237#define HDA_CTL_OUT (1 << 0) 238#define HDA_CTL_IN (1 << 1) 239#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 240 241#define HDA_GPIO_MAX 15 242/* 0 - 14 = GPIO */ 243#define HDA_QUIRK_GPIO0 (1 << 0) 244#define HDA_QUIRK_GPIO1 (1 << 1) 245#define HDA_QUIRK_GPIO2 (1 << 2) 246#define HDA_QUIRK_GPIOFLUSH (1 << 15) 247#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 248#define HDA_QUIRK_FIXEDRATE (1 << 17) 249#define HDA_QUIRK_FORCESTEREO (1 << 18) 250#define HDA_QUIRK_EAPDINV (1 << 19) 251#define HDA_QUIRK_VREF (1 << 20) 252 253static const struct { 254 char *key; 255 uint32_t value; 256} hdac_quirks_tab[] = { 257 { "gpio0", HDA_QUIRK_GPIO0 }, 258 { "gpio1", HDA_QUIRK_GPIO1 }, 259 { "gpio2", HDA_QUIRK_GPIO2 }, 260 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 261 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 262 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 263 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 264 { "eapdinv", HDA_QUIRK_EAPDINV }, 265 { "vref", HDA_QUIRK_VREF }, 266}; 267#define HDAC_QUIRKS_TAB_LEN \ 268 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 269 270#define HDA_BDL_MIN 2 271#define HDA_BDL_MAX 256 272#define HDA_BDL_DEFAULT HDA_BDL_MIN 273 274#define HDA_BUFSZ_MIN 4096 275#define HDA_BUFSZ_MAX 65536 276#define HDA_BUFSZ_DEFAULT 16384 277 278#define HDA_PARSE_MAXDEPTH 10 279 280#define HDAC_UNSOLTAG_EVENT_HP 0x00 281 282static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 283 284enum { 285 HDA_PARSE_MIXER, 286 HDA_PARSE_DIRECT 287}; 288 289/* Default */ 290static uint32_t hdac_fmt[] = { 291 AFMT_STEREO | AFMT_S16_LE, 292 0 293}; 294 295static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 296 297static const struct { 298 uint32_t model; 299 char *desc; 300} hdac_devices[] = { 301 { HDA_INTEL_82801F, "Intel 82801F" }, 302 { HDA_INTEL_82801G, "Intel 82801G" }, 303 { HDA_INTEL_82801H, "Intel 82801H" }, 304 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 305 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 306 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 307 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 308 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 309 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 310 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 311 { HDA_ATI_SB450, "ATI SB450" }, 312 { HDA_ATI_SB600, "ATI SB600" }, 313 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 314 { HDA_SIS_966, "SiS 966" }, 315 /* Unknown */ 316 { HDA_INTEL_ALL, "Intel (Unknown)" }, 317 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 318 { HDA_ATI_ALL, "ATI (Unknown)" }, 319 { HDA_VIA_ALL, "VIA (Unknown)" }, 320 { HDA_SIS_ALL, "SiS (Unknown)" }, 321}; 322#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 323 324static const struct { 325 uint32_t rate; 326 int valid; 327 uint16_t base; 328 uint16_t mul; 329 uint16_t div; 330} hda_rate_tab[] = { 331 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 332 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 333 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 334 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 335 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 336 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 337 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 338 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 339 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 340 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 341 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 342 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 343 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 344 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 345 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 346 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 347 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 348 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 349 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 350 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 351 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 352 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 353 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 354 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 355 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 356 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 357 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 358 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 359 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 360 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 361 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 362 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 363 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 364 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 365 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 366}; 367#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 368 369/* All codecs you can eat... */ 370#define HDA_CODEC_CONSTRUCT(vendor, id) \ 371 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 372 373/* Realtek */ 374#define REALTEK_VENDORID 0x10ec 375#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 376#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 377#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 378#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 379#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 380#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 381 382/* Analog Device */ 383#define ANALOGDEVICE_VENDORID 0x11d4 384#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 385#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 386#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 387#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 388 389/* CMedia */ 390#define CMEDIA_VENDORID 0x434d 391#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 392#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 393 394/* Sigmatel */ 395#define SIGMATEL_VENDORID 0x8384 396#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 397#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 398#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 399#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 400#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 401 402/* 403 * Conexant 404 * 405 * Ok, the truth is, I don't have any idea at all whether 406 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 407 * place that tell me it is "Venice" is from its Windows driver INF. 408 * 409 * Venice - CX????? 410 * Waikiki - CX20551-22 411 */ 412#define CONEXANT_VENDORID 0x14f1 413#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 414#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 415#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 416 417 418/* Codecs */ 419static const struct { 420 uint32_t id; 421 char *name; 422} hdac_codecs[] = { 423 { HDA_CODEC_ALC260, "Realtek ALC260" }, 424 { HDA_CODEC_ALC861, "Realtek ALC861" }, 425 { HDA_CODEC_ALC880, "Realtek ALC880" }, 426 { HDA_CODEC_ALC882, "Realtek ALC882" }, 427 { HDA_CODEC_ALC883, "Realtek ALC883" }, 428 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 429 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 430 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 431 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 432 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 433 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 434 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 435 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 436 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 437 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 438 /* Unknown codec */ 439 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 440 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 441 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 442 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 443 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 444}; 445#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 446 447enum { 448 HDAC_HP_SWITCH_CTL, 449 HDAC_HP_SWITCH_CTRL 450}; 451 452static const struct { 453 uint32_t model; 454 uint32_t id; 455 int type; 456 int inverted; 457 nid_t hpnid; 458 nid_t spkrnid[8]; 459 nid_t eapdnid; 460} hdac_hp_switch[] = { 461 /* Specific OEM models */ 462 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 463 17, { 16, -1 }, 16 }, 464 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 465 6, { 5, -1 }, 5 }, 466 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 467 6, { 5, -1 }, 5 }, 468 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 469 13, { 14, -1 }, -1 }, 470 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 471 13, { 14, -1 }, -1 }, 472 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 473 10, { 13, -1 }, -1 }, 474 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 475 26, { 27, -1 }, -1 }, 476 /* 477 * All models that at least come from the same vendor with 478 * simmilar codec. 479 */ 480 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 481 17, { 16, -1 }, 16 }, 482 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 483 6, { 5, -1 }, 5 }, 484 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 485 13, { 14, -1 }, -1 }, 486 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 487 26, { 27, -1 }, -1 }, 488}; 489#define HDAC_HP_SWITCH_LEN \ 490 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 491 492static const struct { 493 uint32_t model; 494 uint32_t id; 495 nid_t eapdnid; 496 int hp_switch; 497} hdac_eapd_switch[] = { 498 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 499 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 500 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 501}; 502#define HDAC_EAPD_SWITCH_LEN \ 503 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 504 505/**************************************************************************** 506 * Function prototypes 507 ****************************************************************************/ 508static void hdac_intr_handler(void *); 509static int hdac_reset(struct hdac_softc *); 510static int hdac_get_capabilities(struct hdac_softc *); 511static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 512static int hdac_dma_alloc(struct hdac_softc *, 513 struct hdac_dma *, bus_size_t); 514static void hdac_dma_free(struct hdac_dma *); 515static int hdac_mem_alloc(struct hdac_softc *); 516static void hdac_mem_free(struct hdac_softc *); 517static int hdac_irq_alloc(struct hdac_softc *); 518static void hdac_irq_free(struct hdac_softc *); 519static void hdac_corb_init(struct hdac_softc *); 520static void hdac_rirb_init(struct hdac_softc *); 521static void hdac_corb_start(struct hdac_softc *); 522static void hdac_rirb_start(struct hdac_softc *); 523static void hdac_scan_codecs(struct hdac_softc *); 524static int hdac_probe_codec(struct hdac_codec *); 525static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 526static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 527 528static void hdac_attach2(void *); 529 530static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 531 uint32_t, int); 532static void hdac_command_send_internal(struct hdac_softc *, 533 struct hdac_command_list *, int); 534 535static int hdac_probe(device_t); 536static int hdac_attach(device_t); 537static int hdac_detach(device_t); 538static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 539static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 540 uint32_t, int, int); 541static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 542 nid_t, int, int); 543static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 544 nid_t, nid_t, int, int, int, int, int, int); 545static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 546static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 547 548static int hdac_rirb_flush(struct hdac_softc *sc); 549static int hdac_unsolq_flush(struct hdac_softc *sc); 550 551#define hdac_command(a1, a2, a3) \ 552 hdac_command_sendone_internal(a1, a2, a3) 553 554#define hdac_codec_id(d) \ 555 ((uint32_t)((d == NULL) ? 0x00000000 : \ 556 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 557 ((uint32_t)(d)->device_id & 0x0000ffff)))) 558 559static char * 560hdac_codec_name(struct hdac_devinfo *devinfo) 561{ 562 uint32_t id; 563 int i; 564 565 id = hdac_codec_id(devinfo); 566 567 for (i = 0; i < HDAC_CODECS_LEN; i++) { 568 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 569 return (hdac_codecs[i].name); 570 } 571 572 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 573} 574 575static char * 576hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 577{ 578 static char *ossname[] = SOUND_DEVICE_NAMES; 579 static char *unknown = "???"; 580 int i; 581 582 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 583 if (devmask & (1 << i)) 584 return (ossname[i]); 585 } 586 return (unknown); 587} 588 589static void 590hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 591{ 592 static char *ossname[] = SOUND_DEVICE_NAMES; 593 int i, first = 1; 594 595 bzero(buf, len); 596 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 597 if (mask & (1 << i)) { 598 if (first == 0) 599 strlcat(buf, ", ", len); 600 strlcat(buf, ossname[i], len); 601 first = 0; 602 } 603 } 604} 605 606static struct hdac_audio_ctl * 607hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 608{ 609 if (devinfo == NULL || 610 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 611 index == NULL || devinfo->function.audio.ctl == NULL || 612 devinfo->function.audio.ctlcnt < 1 || 613 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 614 return (NULL); 615 return (&devinfo->function.audio.ctl[(*index)++]); 616} 617 618static struct hdac_audio_ctl * 619hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 620 int index, int cnt) 621{ 622 struct hdac_audio_ctl *ctl, *retctl = NULL; 623 int i, at, atindex, found = 0; 624 625 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 626 return (NULL); 627 628 at = cnt; 629 if (at == 0) 630 at = 1; 631 else if (at < 0) 632 at = -1; 633 atindex = index; 634 if (atindex < 0) 635 atindex = -1; 636 637 i = 0; 638 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 639 if (ctl->enable == 0 || ctl->widget == NULL) 640 continue; 641 if (!(ctl->widget->nid == nid && (atindex == -1 || 642 ctl->index == atindex))) 643 continue; 644 found++; 645 if (found == cnt) 646 return (ctl); 647 retctl = ctl; 648 } 649 650 return ((at == -1) ? retctl : NULL); 651} 652 653static void 654hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 655{ 656 struct hdac_softc *sc; 657 struct hdac_widget *w; 658 struct hdac_audio_ctl *ctl; 659 uint32_t id, res; 660 int i = 0, j, forcemute; 661 nid_t cad; 662 663 if (devinfo == NULL || devinfo->codec == NULL || 664 devinfo->codec->sc == NULL) 665 return; 666 667 sc = devinfo->codec->sc; 668 cad = devinfo->codec->cad; 669 id = hdac_codec_id(devinfo); 670 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 671 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 672 sc->pci_subvendor) && 673 hdac_hp_switch[i].id == id) 674 break; 675 } 676 677 if (i >= HDAC_HP_SWITCH_LEN) 678 return; 679 680 forcemute = 0; 681 if (hdac_hp_switch[i].eapdnid != -1) { 682 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 683 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 684 forcemute = (w->param.eapdbtl & 685 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 686 } 687 688 res = hdac_command(sc, 689 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 690 HDA_BOOTVERBOSE( 691 device_printf(sc->dev, 692 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 693 hdac_hp_switch[i].hpnid, res); 694 ); 695 res >>= 31; 696 res ^= hdac_hp_switch[i].inverted; 697 698 switch (hdac_hp_switch[i].type) { 699 case HDAC_HP_SWITCH_CTL: 700 ctl = hdac_audio_ctl_amp_get(devinfo, 701 hdac_hp_switch[i].hpnid, 0, 1); 702 if (ctl != NULL) { 703 ctl->muted = (res != 0 && forcemute == 0) ? 704 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 705 hdac_audio_ctl_amp_set(ctl, 706 HDA_AMP_MUTE_DEFAULT, ctl->left, 707 ctl->right); 708 } 709 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 710 ctl = hdac_audio_ctl_amp_get(devinfo, 711 hdac_hp_switch[i].spkrnid[j], 0, 1); 712 if (ctl != NULL) { 713 ctl->muted = (res != 0 || forcemute == 1) ? 714 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 715 hdac_audio_ctl_amp_set(ctl, 716 HDA_AMP_MUTE_DEFAULT, ctl->left, 717 ctl->right); 718 } 719 } 720 break; 721 case HDAC_HP_SWITCH_CTRL: 722 if (res != 0) { 723 /* HP in */ 724 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 725 if (w != NULL && w->type == 726 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 727 if (forcemute == 0) 728 w->wclass.pin.ctrl |= 729 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 730 else 731 w->wclass.pin.ctrl &= 732 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 733 hdac_command(sc, 734 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 735 w->wclass.pin.ctrl), cad); 736 } 737 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 738 w = hdac_widget_get(devinfo, 739 hdac_hp_switch[i].spkrnid[j]); 740 if (w != NULL && w->type == 741 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 742 w->wclass.pin.ctrl &= 743 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 744 hdac_command(sc, 745 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 746 w->nid, 747 w->wclass.pin.ctrl), cad); 748 } 749 } 750 } else { 751 /* HP out */ 752 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 753 if (w != NULL && w->type == 754 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 755 w->wclass.pin.ctrl &= 756 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 757 hdac_command(sc, 758 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 759 w->wclass.pin.ctrl), cad); 760 } 761 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 762 w = hdac_widget_get(devinfo, 763 hdac_hp_switch[i].spkrnid[j]); 764 if (w != NULL && w->type == 765 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 766 if (forcemute == 0) 767 w->wclass.pin.ctrl |= 768 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 769 else 770 w->wclass.pin.ctrl &= 771 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 772 hdac_command(sc, 773 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 774 w->nid, 775 w->wclass.pin.ctrl), cad); 776 } 777 } 778 } 779 break; 780 default: 781 break; 782 } 783} 784 785static void 786hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 787{ 788 struct hdac_softc *sc; 789 struct hdac_devinfo *devinfo = NULL; 790 device_t *devlist = NULL; 791 int devcount, i; 792 793 if (codec == NULL || codec->sc == NULL) 794 return; 795 796 sc = codec->sc; 797 798 HDA_BOOTVERBOSE( 799 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 800 ); 801 802 device_get_children(sc->dev, &devlist, &devcount); 803 for (i = 0; devlist != NULL && i < devcount; i++) { 804 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 805 if (devinfo != NULL && devinfo->node_type == 806 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 807 devinfo->codec != NULL && 808 devinfo->codec->cad == codec->cad) { 809 break; 810 } else 811 devinfo = NULL; 812 } 813 if (devlist != NULL) 814 free(devlist, M_TEMP); 815 816 if (devinfo == NULL) 817 return; 818 819 switch (tag) { 820 case HDAC_UNSOLTAG_EVENT_HP: 821 hdac_hp_switch_handler(devinfo); 822 break; 823 default: 824 break; 825 } 826} 827 828static int 829hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 830{ 831 /* XXX to be removed */ 832#ifdef HDAC_INTR_EXTRA 833 uint32_t res; 834#endif 835 836 if (ch->blkcnt == 0) 837 return (0); 838 839 /* XXX to be removed */ 840#ifdef HDAC_INTR_EXTRA 841 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 842#endif 843 844 /* XXX to be removed */ 845#ifdef HDAC_INTR_EXTRA 846 HDA_BOOTVERBOSE( 847 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 848 device_printf(sc->dev, 849 "PCMDIR_%s intr triggered beyond stream boundary:" 850 "%08x\n", 851 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 852 ); 853#endif 854 855 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 856 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 857 858 /* XXX to be removed */ 859#ifdef HDAC_INTR_EXTRA 860 if (res & HDAC_SDSTS_BCIS) { 861#endif 862 return (1); 863 /* XXX to be removed */ 864#ifdef HDAC_INTR_EXTRA 865 } 866#endif 867 868 return (0); 869} 870 871/**************************************************************************** 872 * void hdac_intr_handler(void *) 873 * 874 * Interrupt handler. Processes interrupts received from the hdac. 875 ****************************************************************************/ 876static void 877hdac_intr_handler(void *context) 878{ 879 struct hdac_softc *sc; 880 uint32_t intsts; 881 uint8_t rirbsts; 882 struct hdac_rirb *rirb_base; 883 uint32_t trigger = 0; 884 885 sc = (struct hdac_softc *)context; 886 887 hdac_lock(sc); 888 if (sc->polling != 0) { 889 hdac_unlock(sc); 890 return; 891 } 892 /* Do we have anything to do? */ 893 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 894 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 895 hdac_unlock(sc); 896 return; 897 } 898 899 /* Was this a controller interrupt? */ 900 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 901 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 902 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 903 /* Get as many responses that we can */ 904 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 905 HDAC_WRITE_1(&sc->mem, 906 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 907 hdac_rirb_flush(sc); 908 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 909 } 910 /* XXX to be removed */ 911 /* Clear interrupt and exit */ 912#ifdef HDAC_INTR_EXTRA 913 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 914#endif 915 } 916 917 hdac_unsolq_flush(sc); 918 919 if (intsts & HDAC_INTSTS_SIS_MASK) { 920 if ((intsts & (1 << sc->num_iss)) && 921 hdac_stream_intr(sc, &sc->play) != 0) 922 trigger |= 1; 923 if ((intsts & (1 << 0)) && 924 hdac_stream_intr(sc, &sc->rec) != 0) 925 trigger |= 2; 926 /* XXX to be removed */ 927#ifdef HDAC_INTR_EXTRA 928 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 929 HDAC_INTSTS_SIS_MASK); 930#endif 931 } 932 933 hdac_unlock(sc); 934 935 if (trigger & 1) 936 chn_intr(sc->play.c); 937 if (trigger & 2) 938 chn_intr(sc->rec.c); 939} 940 941/**************************************************************************** 942 * int hdac_reset(hdac_softc *) 943 * 944 * Reset the hdac to a quiescent and known state. 945 ****************************************************************************/ 946static int 947hdac_reset(struct hdac_softc *sc) 948{ 949 uint32_t gctl; 950 int count, i; 951 952 /* 953 * Stop all Streams DMA engine 954 */ 955 for (i = 0; i < sc->num_iss; i++) 956 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 957 for (i = 0; i < sc->num_oss; i++) 958 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 959 for (i = 0; i < sc->num_bss; i++) 960 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 961 962 /* 963 * Stop Control DMA engines 964 */ 965 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 966 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 967 968 /* 969 * Reset the controller. The reset must remain asserted for 970 * a minimum of 100us. 971 */ 972 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 973 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 974 count = 10000; 975 do { 976 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 977 if (!(gctl & HDAC_GCTL_CRST)) 978 break; 979 DELAY(10); 980 } while (--count); 981 if (gctl & HDAC_GCTL_CRST) { 982 device_printf(sc->dev, "Unable to put hdac in reset\n"); 983 return (ENXIO); 984 } 985 DELAY(100); 986 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 987 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 988 count = 10000; 989 do { 990 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 991 if (gctl & HDAC_GCTL_CRST) 992 break; 993 DELAY(10); 994 } while (--count); 995 if (!(gctl & HDAC_GCTL_CRST)) { 996 device_printf(sc->dev, "Device stuck in reset\n"); 997 return (ENXIO); 998 } 999 1000 /* 1001 * Wait for codecs to finish their own reset sequence. The delay here 1002 * should be of 250us but for some reasons, on it's not enough on my 1003 * computer. Let's use twice as much as necessary to make sure that 1004 * it's reset properly. 1005 */ 1006 DELAY(1000); 1007 1008 return (0); 1009} 1010 1011 1012/**************************************************************************** 1013 * int hdac_get_capabilities(struct hdac_softc *); 1014 * 1015 * Retreive the general capabilities of the hdac; 1016 * Number of Input Streams 1017 * Number of Output Streams 1018 * Number of bidirectional Streams 1019 * 64bit ready 1020 * CORB and RIRB sizes 1021 ****************************************************************************/ 1022static int 1023hdac_get_capabilities(struct hdac_softc *sc) 1024{ 1025 uint16_t gcap; 1026 uint8_t corbsize, rirbsize; 1027 1028 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1029 sc->num_iss = HDAC_GCAP_ISS(gcap); 1030 sc->num_oss = HDAC_GCAP_OSS(gcap); 1031 sc->num_bss = HDAC_GCAP_BSS(gcap); 1032 1033 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1034 1035 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1036 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1037 HDAC_CORBSIZE_CORBSZCAP_256) 1038 sc->corb_size = 256; 1039 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1040 HDAC_CORBSIZE_CORBSZCAP_16) 1041 sc->corb_size = 16; 1042 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1043 HDAC_CORBSIZE_CORBSZCAP_2) 1044 sc->corb_size = 2; 1045 else { 1046 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1047 __func__, corbsize); 1048 return (ENXIO); 1049 } 1050 1051 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1052 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1053 HDAC_RIRBSIZE_RIRBSZCAP_256) 1054 sc->rirb_size = 256; 1055 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1056 HDAC_RIRBSIZE_RIRBSZCAP_16) 1057 sc->rirb_size = 16; 1058 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1059 HDAC_RIRBSIZE_RIRBSZCAP_2) 1060 sc->rirb_size = 2; 1061 else { 1062 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1063 __func__, rirbsize); 1064 return (ENXIO); 1065 } 1066 1067 return (0); 1068} 1069 1070 1071/**************************************************************************** 1072 * void hdac_dma_cb 1073 * 1074 * This function is called by bus_dmamap_load when the mapping has been 1075 * established. We just record the physical address of the mapping into 1076 * the struct hdac_dma passed in. 1077 ****************************************************************************/ 1078static void 1079hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1080{ 1081 struct hdac_dma *dma; 1082 1083 if (error == 0) { 1084 dma = (struct hdac_dma *)callback_arg; 1085 dma->dma_paddr = segs[0].ds_addr; 1086 } 1087} 1088 1089static void 1090hdac_dma_nocache(void *ptr) 1091{ 1092#if defined(__i386__) || defined(__amd64__) 1093 pt_entry_t *pte; 1094 vm_offset_t va; 1095 1096 va = (vm_offset_t)ptr; 1097 pte = vtopte(va); 1098 if (pte) { 1099 *pte |= PG_N; 1100 invltlb(); 1101 } 1102#endif 1103} 1104 1105/**************************************************************************** 1106 * int hdac_dma_alloc 1107 * 1108 * This function allocate and setup a dma region (struct hdac_dma). 1109 * It must be freed by a corresponding hdac_dma_free. 1110 ****************************************************************************/ 1111static int 1112hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1113{ 1114 int result; 1115 int lowaddr; 1116 1117 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1118 BUS_SPACE_MAXADDR_32BIT; 1119 bzero(dma, sizeof(*dma)); 1120 1121 /* 1122 * Create a DMA tag 1123 */ 1124 result = bus_dma_tag_create(NULL, /* parent */ 1125 HDAC_DMA_ALIGNMENT, /* alignment */ 1126 0, /* boundary */ 1127 lowaddr, /* lowaddr */ 1128 BUS_SPACE_MAXADDR, /* highaddr */ 1129 NULL, /* filtfunc */ 1130 NULL, /* fistfuncarg */ 1131 size, /* maxsize */ 1132 1, /* nsegments */ 1133 size, /* maxsegsz */ 1134 0, /* flags */ 1135 NULL, /* lockfunc */ 1136 NULL, /* lockfuncarg */ 1137 &dma->dma_tag); /* dmat */ 1138 if (result != 0) { 1139 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1140 __func__, result); 1141 goto fail; 1142 } 1143 1144 /* 1145 * Allocate DMA memory 1146 */ 1147 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1148 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1149 if (result != 0) { 1150 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1151 __func__, result); 1152 goto fail; 1153 } 1154 1155 /* 1156 * Map the memory 1157 */ 1158 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1159 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1160 BUS_DMA_NOWAIT); 1161 if (result != 0 || dma->dma_paddr == 0) { 1162 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1163 __func__, result); 1164 goto fail; 1165 } 1166 bzero((void *)dma->dma_vaddr, size); 1167 hdac_dma_nocache(dma->dma_vaddr); 1168 1169 return (0); 1170fail: 1171 if (dma->dma_map != NULL) 1172 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1173 if (dma->dma_tag != NULL) 1174 bus_dma_tag_destroy(dma->dma_tag); 1175 return (result); 1176} 1177 1178 1179/**************************************************************************** 1180 * void hdac_dma_free(struct hdac_dma *) 1181 * 1182 * Free a struct dhac_dma that has been previously allocated via the 1183 * hdac_dma_alloc function. 1184 ****************************************************************************/ 1185static void 1186hdac_dma_free(struct hdac_dma *dma) 1187{ 1188 if (dma->dma_tag != NULL) { 1189 /* Flush caches */ 1190 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1191 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1192 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1193 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1194 bus_dma_tag_destroy(dma->dma_tag); 1195 } 1196} 1197 1198/**************************************************************************** 1199 * int hdac_mem_alloc(struct hdac_softc *) 1200 * 1201 * Allocate all the bus resources necessary to speak with the physical 1202 * controller. 1203 ****************************************************************************/ 1204static int 1205hdac_mem_alloc(struct hdac_softc *sc) 1206{ 1207 struct hdac_mem *mem; 1208 1209 mem = &sc->mem; 1210 mem->mem_rid = PCIR_BAR(0); 1211 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1212 &mem->mem_rid, RF_ACTIVE); 1213 if (mem->mem_res == NULL) { 1214 device_printf(sc->dev, 1215 "%s: Unable to allocate memory resource\n", __func__); 1216 return (ENOMEM); 1217 } 1218 mem->mem_tag = rman_get_bustag(mem->mem_res); 1219 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1220 1221 return (0); 1222} 1223 1224/**************************************************************************** 1225 * void hdac_mem_free(struct hdac_softc *) 1226 * 1227 * Free up resources previously allocated by hdac_mem_alloc. 1228 ****************************************************************************/ 1229static void 1230hdac_mem_free(struct hdac_softc *sc) 1231{ 1232 struct hdac_mem *mem; 1233 1234 mem = &sc->mem; 1235 if (mem->mem_res != NULL) 1236 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1237 mem->mem_res); 1238 mem->mem_res = NULL; 1239} 1240 1241/**************************************************************************** 1242 * int hdac_irq_alloc(struct hdac_softc *) 1243 * 1244 * Allocate and setup the resources necessary for interrupt handling. 1245 ****************************************************************************/ 1246static int 1247hdac_irq_alloc(struct hdac_softc *sc) 1248{ 1249 struct hdac_irq *irq; 1250 int result; 1251 1252 irq = &sc->irq; 1253 irq->irq_rid = 0x0; 1254 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1255 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1256 if (irq->irq_res == NULL) { 1257 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1258 __func__); 1259 goto fail; 1260 } 1261 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1262 hdac_intr_handler, sc, &irq->irq_handle); 1263 if (result != 0) { 1264 device_printf(sc->dev, 1265 "%s: Unable to setup interrupt handler (%x)\n", 1266 __func__, result); 1267 goto fail; 1268 } 1269 1270 return (0); 1271 1272fail: 1273 hdac_irq_free(sc); 1274 1275 return (ENXIO); 1276} 1277 1278/**************************************************************************** 1279 * void hdac_irq_free(struct hdac_softc *) 1280 * 1281 * Free up resources previously allocated by hdac_irq_alloc. 1282 ****************************************************************************/ 1283static void 1284hdac_irq_free(struct hdac_softc *sc) 1285{ 1286 struct hdac_irq *irq; 1287 1288 irq = &sc->irq; 1289 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1290 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1291 if (irq->irq_res != NULL) 1292 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1293 irq->irq_res); 1294 irq->irq_handle = NULL; 1295 irq->irq_res = NULL; 1296} 1297 1298/**************************************************************************** 1299 * void hdac_corb_init(struct hdac_softc *) 1300 * 1301 * Initialize the corb registers for operations but do not start it up yet. 1302 * The CORB engine must not be running when this function is called. 1303 ****************************************************************************/ 1304static void 1305hdac_corb_init(struct hdac_softc *sc) 1306{ 1307 uint8_t corbsize; 1308 uint64_t corbpaddr; 1309 1310 /* Setup the CORB size. */ 1311 switch (sc->corb_size) { 1312 case 256: 1313 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1314 break; 1315 case 16: 1316 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1317 break; 1318 case 2: 1319 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1320 break; 1321 default: 1322 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1323 } 1324 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1325 1326 /* Setup the CORB Address in the hdac */ 1327 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1328 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1329 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1330 1331 /* Set the WP and RP */ 1332 sc->corb_wp = 0; 1333 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1334 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1335 /* 1336 * The HDA specification indicates that the CORBRPRST bit will always 1337 * read as zero. Unfortunately, it seems that at least the 82801G 1338 * doesn't reset the bit to zero, which stalls the corb engine. 1339 * manually reset the bit to zero before continuing. 1340 */ 1341 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1342 1343 /* Enable CORB error reporting */ 1344#if 0 1345 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1346#endif 1347} 1348 1349/**************************************************************************** 1350 * void hdac_rirb_init(struct hdac_softc *) 1351 * 1352 * Initialize the rirb registers for operations but do not start it up yet. 1353 * The RIRB engine must not be running when this function is called. 1354 ****************************************************************************/ 1355static void 1356hdac_rirb_init(struct hdac_softc *sc) 1357{ 1358 uint8_t rirbsize; 1359 uint64_t rirbpaddr; 1360 1361 /* Setup the RIRB size. */ 1362 switch (sc->rirb_size) { 1363 case 256: 1364 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1365 break; 1366 case 16: 1367 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1368 break; 1369 case 2: 1370 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1371 break; 1372 default: 1373 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1374 } 1375 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1376 1377 /* Setup the RIRB Address in the hdac */ 1378 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1379 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1380 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1381 1382 /* Setup the WP and RP */ 1383 sc->rirb_rp = 0; 1384 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1385 1386 if (sc->polling == 0) { 1387 /* Setup the interrupt threshold */ 1388 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1389 1390 /* Enable Overrun and response received reporting */ 1391#if 0 1392 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1393 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1394#else 1395 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1396#endif 1397 } 1398 1399 /* 1400 * Make sure that the Host CPU cache doesn't contain any dirty 1401 * cache lines that falls in the rirb. If I understood correctly, it 1402 * should be sufficient to do this only once as the rirb is purely 1403 * read-only from now on. 1404 */ 1405 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1406 BUS_DMASYNC_PREREAD); 1407} 1408 1409/**************************************************************************** 1410 * void hdac_corb_start(hdac_softc *) 1411 * 1412 * Startup the corb DMA engine 1413 ****************************************************************************/ 1414static void 1415hdac_corb_start(struct hdac_softc *sc) 1416{ 1417 uint32_t corbctl; 1418 1419 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1420 corbctl |= HDAC_CORBCTL_CORBRUN; 1421 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1422} 1423 1424/**************************************************************************** 1425 * void hdac_rirb_start(hdac_softc *) 1426 * 1427 * Startup the rirb DMA engine 1428 ****************************************************************************/ 1429static void 1430hdac_rirb_start(struct hdac_softc *sc) 1431{ 1432 uint32_t rirbctl; 1433 1434 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1435 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1436 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1437} 1438 1439 1440/**************************************************************************** 1441 * void hdac_scan_codecs(struct hdac_softc *) 1442 * 1443 * Scan the bus for available codecs. 1444 ****************************************************************************/ 1445static void 1446hdac_scan_codecs(struct hdac_softc *sc) 1447{ 1448 struct hdac_codec *codec; 1449 int i; 1450 uint16_t statests; 1451 1452 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1453 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1454 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1455 /* We have found a codec. */ 1456 hdac_unlock(sc); 1457 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1458 M_HDAC, M_ZERO | M_NOWAIT); 1459 hdac_lock(sc); 1460 if (codec == NULL) { 1461 device_printf(sc->dev, 1462 "Unable to allocate memory for codec\n"); 1463 continue; 1464 } 1465 codec->commands = NULL; 1466 codec->responses_received = 0; 1467 codec->verbs_sent = 0; 1468 codec->sc = sc; 1469 codec->cad = i; 1470 sc->codecs[i] = codec; 1471 if (hdac_probe_codec(codec) != 0) 1472 break; 1473 } 1474 } 1475 /* All codecs have been probed, now try to attach drivers to them */ 1476 /* bus_generic_attach(sc->dev); */ 1477} 1478 1479/**************************************************************************** 1480 * void hdac_probe_codec(struct hdac_softc *, int) 1481 * 1482 * Probe a the given codec_id for available function groups. 1483 ****************************************************************************/ 1484static int 1485hdac_probe_codec(struct hdac_codec *codec) 1486{ 1487 struct hdac_softc *sc = codec->sc; 1488 struct hdac_devinfo *devinfo; 1489 uint32_t vendorid, revisionid, subnode; 1490 int startnode; 1491 int endnode; 1492 int i; 1493 nid_t cad = codec->cad; 1494 1495 HDA_BOOTVERBOSE( 1496 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1497 ); 1498 vendorid = hdac_command(sc, 1499 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1500 cad); 1501 revisionid = hdac_command(sc, 1502 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1503 cad); 1504 subnode = hdac_command(sc, 1505 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1506 cad); 1507 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1508 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1509 1510 HDA_BOOTVERBOSE( 1511 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1512 startnode, endnode); 1513 ); 1514 for (i = startnode; i < endnode; i++) { 1515 devinfo = hdac_probe_function(codec, i); 1516 if (devinfo != NULL) { 1517 /* XXX Ignore other FG. */ 1518 devinfo->vendor_id = 1519 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1520 devinfo->device_id = 1521 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1522 devinfo->revision_id = 1523 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1524 devinfo->stepping_id = 1525 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1526 HDA_BOOTVERBOSE( 1527 device_printf(sc->dev, 1528 "HDA_DEBUG: \tFound AFG nid=%d " 1529 "[startnode=%d endnode=%d]\n", 1530 devinfo->nid, startnode, endnode); 1531 ); 1532 return (1); 1533 } 1534 } 1535 1536 HDA_BOOTVERBOSE( 1537 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1538 ); 1539 return (0); 1540} 1541 1542static struct hdac_devinfo * 1543hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1544{ 1545 struct hdac_softc *sc = codec->sc; 1546 struct hdac_devinfo *devinfo; 1547 uint32_t fctgrptype; 1548 nid_t cad = codec->cad; 1549 1550 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1551 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1552 1553 /* XXX For now, ignore other FG. */ 1554 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1555 return (NULL); 1556 1557 hdac_unlock(sc); 1558 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1559 M_NOWAIT | M_ZERO); 1560 hdac_lock(sc); 1561 if (devinfo == NULL) { 1562 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1563 __func__); 1564 return (NULL); 1565 } 1566 1567 devinfo->nid = nid; 1568 devinfo->node_type = fctgrptype; 1569 devinfo->codec = codec; 1570 1571 hdac_add_child(sc, devinfo); 1572 1573 return (devinfo); 1574} 1575 1576static void 1577hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1578{ 1579 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1580 device_set_ivars(devinfo->dev, (void *)devinfo); 1581 /* XXX - Print more information when booting verbose??? */ 1582} 1583 1584static void 1585hdac_widget_connection_parse(struct hdac_widget *w) 1586{ 1587 struct hdac_softc *sc = w->devinfo->codec->sc; 1588 uint32_t res; 1589 int i, j, max, found, entnum, cnid; 1590 nid_t cad = w->devinfo->codec->cad; 1591 nid_t nid = w->nid; 1592 1593 res = hdac_command(sc, 1594 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1595 1596 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1597 1598 if (w->nconns < 1) 1599 return; 1600 1601 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1602 res = 0; 1603 i = 0; 1604 found = 0; 1605 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1606 1607 while (i < w->nconns) { 1608 res = hdac_command(sc, 1609 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1610 for (j = 0; j < entnum; j++) { 1611 cnid = res; 1612 cnid >>= (32 / entnum) * j; 1613 cnid &= (1 << (32 / entnum)) - 1; 1614 if (cnid == 0) 1615 continue; 1616 if (found > max) { 1617 device_printf(sc->dev, 1618 "node %d: Adding %d: " 1619 "Max connection reached!\n", 1620 nid, cnid); 1621 continue; 1622 } 1623 w->conns[found++] = cnid; 1624 } 1625 i += entnum; 1626 } 1627 1628 HDA_BOOTVERBOSE( 1629 if (w->nconns != found) { 1630 device_printf(sc->dev, 1631 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1632 "length=%d != found=%d\n", 1633 nid, w->nconns, found); 1634 } 1635 ); 1636} 1637 1638static uint32_t 1639hdac_widget_pin_getconfig(struct hdac_widget *w) 1640{ 1641 struct hdac_softc *sc; 1642 uint32_t config, id; 1643 nid_t cad, nid; 1644 1645 sc = w->devinfo->codec->sc; 1646 cad = w->devinfo->codec->cad; 1647 nid = w->nid; 1648 id = hdac_codec_id(w->devinfo); 1649 1650 config = hdac_command(sc, 1651 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1652 cad); 1653 /* 1654 * XXX REWRITE!!!! Don't argue! 1655 */ 1656 if (id == HDA_CODEC_ALC880 && 1657 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1658 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1659 /* 1660 * Super broken BIOS 1661 */ 1662 switch (nid) { 1663 case 20: 1664 break; 1665 case 21: 1666 break; 1667 case 22: 1668 break; 1669 case 23: 1670 break; 1671 case 24: /* MIC1 */ 1672 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1673 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1674 break; 1675 case 25: /* XXX MIC2 */ 1676 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1677 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1678 break; 1679 case 26: /* LINE1 */ 1680 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1681 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1682 break; 1683 case 27: /* XXX LINE2 */ 1684 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1685 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1686 break; 1687 case 28: /* CD */ 1688 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1689 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1690 break; 1691 case 30: 1692 break; 1693 case 31: 1694 break; 1695 default: 1696 break; 1697 } 1698 } 1699 1700 return (config); 1701} 1702 1703static void 1704hdac_widget_pin_parse(struct hdac_widget *w) 1705{ 1706 struct hdac_softc *sc = w->devinfo->codec->sc; 1707 uint32_t config, pincap; 1708 char *devstr, *connstr; 1709 nid_t cad = w->devinfo->codec->cad; 1710 nid_t nid = w->nid; 1711 1712 config = hdac_widget_pin_getconfig(w); 1713 w->wclass.pin.config = config; 1714 1715 pincap = hdac_command(sc, 1716 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1717 w->wclass.pin.cap = pincap; 1718 1719 w->wclass.pin.ctrl = hdac_command(sc, 1720 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1721 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1722 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1723 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1724 1725 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1726 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1727 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1728 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1729 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1730 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1731 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1732 w->param.eapdbtl = hdac_command(sc, 1733 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1734 w->param.eapdbtl &= 0x7; 1735 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1736 } else 1737 w->param.eapdbtl = HDAC_INVALID; 1738 1739 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1740 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1741 devstr = "line out"; 1742 break; 1743 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1744 devstr = "speaker"; 1745 break; 1746 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1747 devstr = "headphones out"; 1748 break; 1749 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1750 devstr = "CD"; 1751 break; 1752 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1753 devstr = "SPDIF out"; 1754 break; 1755 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1756 devstr = "digital (other) out"; 1757 break; 1758 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1759 devstr = "modem, line side"; 1760 break; 1761 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1762 devstr = "modem, handset side"; 1763 break; 1764 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1765 devstr = "line in"; 1766 break; 1767 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1768 devstr = "AUX"; 1769 break; 1770 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1771 devstr = "Mic in"; 1772 break; 1773 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1774 devstr = "telephony"; 1775 break; 1776 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1777 devstr = "SPDIF in"; 1778 break; 1779 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1780 devstr = "digital (other) in"; 1781 break; 1782 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1783 devstr = "other"; 1784 break; 1785 default: 1786 devstr = "unknown"; 1787 break; 1788 } 1789 1790 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1791 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1792 connstr = "jack"; 1793 break; 1794 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1795 connstr = "none"; 1796 break; 1797 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1798 connstr = "fixed"; 1799 break; 1800 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1801 connstr = "jack / fixed"; 1802 break; 1803 default: 1804 connstr = "unknown"; 1805 break; 1806 } 1807 1808 strlcat(w->name, ": ", sizeof(w->name)); 1809 strlcat(w->name, devstr, sizeof(w->name)); 1810 strlcat(w->name, " (", sizeof(w->name)); 1811 strlcat(w->name, connstr, sizeof(w->name)); 1812 strlcat(w->name, ")", sizeof(w->name)); 1813} 1814 1815static void 1816hdac_widget_parse(struct hdac_widget *w) 1817{ 1818 struct hdac_softc *sc = w->devinfo->codec->sc; 1819 uint32_t wcap, cap; 1820 char *typestr; 1821 nid_t cad = w->devinfo->codec->cad; 1822 nid_t nid = w->nid; 1823 1824 wcap = hdac_command(sc, 1825 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1826 cad); 1827 w->param.widget_cap = wcap; 1828 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1829 1830 switch (w->type) { 1831 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1832 typestr = "audio output"; 1833 break; 1834 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1835 typestr = "audio input"; 1836 break; 1837 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1838 typestr = "audio mixer"; 1839 break; 1840 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1841 typestr = "audio selector"; 1842 break; 1843 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1844 typestr = "pin"; 1845 break; 1846 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1847 typestr = "power widget"; 1848 break; 1849 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1850 typestr = "volume widget"; 1851 break; 1852 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1853 typestr = "beep widget"; 1854 break; 1855 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1856 typestr = "vendor widget"; 1857 break; 1858 default: 1859 typestr = "unknown type"; 1860 break; 1861 } 1862 1863 strlcpy(w->name, typestr, sizeof(w->name)); 1864 1865 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1866 hdac_command(sc, 1867 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1868 cad); 1869 DELAY(1000); 1870 } 1871 1872 hdac_widget_connection_parse(w); 1873 1874 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1875 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1876 w->param.outamp_cap = 1877 hdac_command(sc, 1878 HDA_CMD_GET_PARAMETER(cad, nid, 1879 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1880 else 1881 w->param.outamp_cap = 1882 w->devinfo->function.audio.outamp_cap; 1883 } else 1884 w->param.outamp_cap = 0; 1885 1886 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1887 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1888 w->param.inamp_cap = 1889 hdac_command(sc, 1890 HDA_CMD_GET_PARAMETER(cad, nid, 1891 HDA_PARAM_INPUT_AMP_CAP), cad); 1892 else 1893 w->param.inamp_cap = 1894 w->devinfo->function.audio.inamp_cap; 1895 } else 1896 w->param.inamp_cap = 0; 1897 1898 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1899 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1900 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1901 cap = hdac_command(sc, 1902 HDA_CMD_GET_PARAMETER(cad, nid, 1903 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1904 w->param.supp_stream_formats = (cap != 0) ? cap : 1905 w->devinfo->function.audio.supp_stream_formats; 1906 cap = hdac_command(sc, 1907 HDA_CMD_GET_PARAMETER(cad, nid, 1908 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1909 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1910 w->devinfo->function.audio.supp_pcm_size_rate; 1911 } else { 1912 w->param.supp_stream_formats = 1913 w->devinfo->function.audio.supp_stream_formats; 1914 w->param.supp_pcm_size_rate = 1915 w->devinfo->function.audio.supp_pcm_size_rate; 1916 } 1917 } else { 1918 w->param.supp_stream_formats = 0; 1919 w->param.supp_pcm_size_rate = 0; 1920 } 1921 1922 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1923 hdac_widget_pin_parse(w); 1924} 1925 1926static struct hdac_widget * 1927hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1928{ 1929 if (devinfo == NULL || devinfo->widget == NULL || 1930 nid < devinfo->startnode || nid >= devinfo->endnode) 1931 return (NULL); 1932 return (&devinfo->widget[nid - devinfo->startnode]); 1933} 1934 1935static __inline int 1936hda_poll_channel(struct hdac_chan *ch) 1937{ 1938 uint32_t sz, delta; 1939 volatile uint32_t ptr; 1940 1941 if (ch->active == 0) 1942 return (0); 1943 1944 sz = ch->blksz * ch->blkcnt; 1945 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1946 ch->ptr = ptr; 1947 ptr %= sz; 1948 ptr &= ~(ch->blksz - 1); 1949 delta = (sz + ptr - ch->prevptr) % sz; 1950 1951 if (delta < ch->blksz) 1952 return (0); 1953 1954 ch->prevptr = ptr; 1955 1956 return (1); 1957} 1958 1959#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1960 1961static void 1962hda_poll_callback(void *arg) 1963{ 1964 struct hdac_softc *sc = arg; 1965 uint32_t trigger = 0; 1966 1967 if (sc == NULL) 1968 return; 1969 1970 hdac_lock(sc); 1971 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 1972 hdac_unlock(sc); 1973 return; 1974 } 1975 1976 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 1977 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 1978 1979 /* XXX */ 1980 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 1981 hda_poll_callback, sc); 1982 1983 hdac_unlock(sc); 1984 1985 if (trigger & 1) 1986 chn_intr(sc->play.c); 1987 if (trigger & 2) 1988 chn_intr(sc->rec.c); 1989} 1990 1991static int 1992hdac_rirb_flush(struct hdac_softc *sc) 1993{ 1994 struct hdac_rirb *rirb_base, *rirb; 1995 struct hdac_codec *codec; 1996 struct hdac_command_list *commands; 1997 nid_t cad; 1998 uint32_t resp; 1999 uint8_t rirbwp; 2000 int ret = 0; 2001 2002 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2003 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2004 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2005 BUS_DMASYNC_POSTREAD); 2006 2007 while (sc->rirb_rp != rirbwp) { 2008 sc->rirb_rp++; 2009 sc->rirb_rp %= sc->rirb_size; 2010 rirb = &rirb_base[sc->rirb_rp]; 2011 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2012 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2013 sc->codecs[cad] == NULL) 2014 continue; 2015 resp = rirb->response; 2016 codec = sc->codecs[cad]; 2017 commands = codec->commands; 2018 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2019 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2020 ((resp >> 26) & 0xffff); 2021 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2022 } else if (commands != NULL && commands->num_commands > 0 && 2023 codec->responses_received < commands->num_commands) 2024 commands->responses[codec->responses_received++] = 2025 resp; 2026 ret++; 2027 } 2028 2029 return (ret); 2030} 2031 2032static int 2033hdac_unsolq_flush(struct hdac_softc *sc) 2034{ 2035 nid_t cad; 2036 uint32_t tag; 2037 int ret = 0; 2038 2039 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2040 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2041 while (sc->unsolq_rp != sc->unsolq_wp) { 2042 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2043 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2044 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2045 hdac_unsolicited_handler(sc->codecs[cad], tag); 2046 ret++; 2047 } 2048 sc->unsolq_st = HDAC_UNSOLQ_READY; 2049 } 2050 2051 return (ret); 2052} 2053 2054static void 2055hdac_poll_callback(void *arg) 2056{ 2057 struct hdac_softc *sc = arg; 2058 if (sc == NULL) 2059 return; 2060 2061 hdac_lock(sc); 2062 if (sc->polling == 0) { 2063 hdac_unlock(sc); 2064 return; 2065 } 2066 hdac_rirb_flush(sc); 2067 hdac_unsolq_flush(sc); 2068 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2069 hdac_poll_callback, sc); 2070 hdac_unlock(sc); 2071} 2072 2073static void 2074hdac_stream_stop(struct hdac_chan *ch) 2075{ 2076 struct hdac_softc *sc = ch->devinfo->codec->sc; 2077 uint32_t ctl; 2078 2079 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2080 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2081 HDAC_SDCTL_RUN); 2082 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2083 2084 ch->active = 0; 2085 2086 if (sc->polling != 0) { 2087 int pollticks; 2088 2089 if (hda_chan_active(sc) == 0) { 2090 callout_stop(&sc->poll_hda); 2091 sc->poll_ticks = 1; 2092 } else { 2093 if (sc->play.active != 0) 2094 ch = &sc->play; 2095 else 2096 ch = &sc->rec; 2097 pollticks = ((uint64_t)hz * ch->blksz) / 2098 ((uint64_t)sndbuf_getbps(ch->b) * 2099 sndbuf_getspd(ch->b)); 2100 pollticks >>= 2; 2101 if (pollticks > hz) 2102 pollticks = hz; 2103 if (pollticks < 1) { 2104 HDA_BOOTVERBOSE( 2105 device_printf(sc->dev, 2106 "%s: pollticks=%d < 1 !\n", 2107 __func__, pollticks); 2108 ); 2109 pollticks = 1; 2110 } 2111 if (pollticks > sc->poll_ticks) { 2112 HDA_BOOTVERBOSE( 2113 device_printf(sc->dev, 2114 "%s: pollticks %d -> %d\n", 2115 __func__, sc->poll_ticks, 2116 pollticks); 2117 ); 2118 sc->poll_ticks = pollticks; 2119 callout_reset(&sc->poll_hda, 1, 2120 hda_poll_callback, sc); 2121 } 2122 } 2123 } else { 2124 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2125 ctl &= ~(1 << (ch->off >> 5)); 2126 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2127 } 2128} 2129 2130static void 2131hdac_stream_start(struct hdac_chan *ch) 2132{ 2133 struct hdac_softc *sc = ch->devinfo->codec->sc; 2134 uint32_t ctl; 2135 2136 if (sc->polling != 0) { 2137 int pollticks; 2138 2139 pollticks = ((uint64_t)hz * ch->blksz) / 2140 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2141 pollticks >>= 2; 2142 if (pollticks > hz) 2143 pollticks = hz; 2144 if (pollticks < 1) { 2145 HDA_BOOTVERBOSE( 2146 device_printf(sc->dev, 2147 "%s: pollticks=%d < 1 !\n", 2148 __func__, pollticks); 2149 ); 2150 pollticks = 1; 2151 } 2152 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2153 HDA_BOOTVERBOSE( 2154 if (hda_chan_active(sc) == 0) { 2155 device_printf(sc->dev, 2156 "%s: pollticks=%d\n", 2157 __func__, pollticks); 2158 } else { 2159 device_printf(sc->dev, 2160 "%s: pollticks %d -> %d\n", 2161 __func__, sc->poll_ticks, 2162 pollticks); 2163 } 2164 ); 2165 sc->poll_ticks = pollticks; 2166 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2167 sc); 2168 } 2169 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2170 ctl |= HDAC_SDCTL_RUN; 2171 } else { 2172 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2173 ctl |= 1 << (ch->off >> 5); 2174 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2175 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2176 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2177 HDAC_SDCTL_RUN; 2178 } 2179 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2180 2181 ch->active = 1; 2182} 2183 2184static void 2185hdac_stream_reset(struct hdac_chan *ch) 2186{ 2187 struct hdac_softc *sc = ch->devinfo->codec->sc; 2188 int timeout = 1000; 2189 int to = timeout; 2190 uint32_t ctl; 2191 2192 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2193 ctl |= HDAC_SDCTL_SRST; 2194 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2195 do { 2196 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2197 if (ctl & HDAC_SDCTL_SRST) 2198 break; 2199 DELAY(10); 2200 } while (--to); 2201 if (!(ctl & HDAC_SDCTL_SRST)) { 2202 device_printf(sc->dev, "timeout in reset\n"); 2203 } 2204 ctl &= ~HDAC_SDCTL_SRST; 2205 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2206 to = timeout; 2207 do { 2208 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2209 if (!(ctl & HDAC_SDCTL_SRST)) 2210 break; 2211 DELAY(10); 2212 } while (--to); 2213 if (ctl & HDAC_SDCTL_SRST) 2214 device_printf(sc->dev, "can't reset!\n"); 2215} 2216 2217static void 2218hdac_stream_setid(struct hdac_chan *ch) 2219{ 2220 struct hdac_softc *sc = ch->devinfo->codec->sc; 2221 uint32_t ctl; 2222 2223 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2224 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2225 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2226 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2227} 2228 2229static void 2230hdac_bdl_setup(struct hdac_chan *ch) 2231{ 2232 struct hdac_softc *sc = ch->devinfo->codec->sc; 2233 struct hdac_bdle *bdle; 2234 uint64_t addr; 2235 uint32_t blksz, blkcnt; 2236 int i; 2237 2238 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2239 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2240 2241 if (sc->polling != 0) { 2242 blksz = ch->blksz * ch->blkcnt; 2243 blkcnt = 1; 2244 } else { 2245 blksz = ch->blksz; 2246 blkcnt = ch->blkcnt; 2247 } 2248 2249 for (i = 0; i < blkcnt; i++, bdle++) { 2250 bdle->addrl = (uint32_t)addr; 2251 bdle->addrh = (uint32_t)(addr >> 32); 2252 bdle->len = blksz; 2253 bdle->ioc = 1 ^ sc->polling; 2254 addr += blksz; 2255 } 2256 2257 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2258 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2259 addr = ch->bdl_dma.dma_paddr; 2260 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2261 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2262} 2263 2264static int 2265hdac_bdl_alloc(struct hdac_chan *ch) 2266{ 2267 struct hdac_softc *sc = ch->devinfo->codec->sc; 2268 int rc; 2269 2270 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2271 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2272 if (rc) { 2273 device_printf(sc->dev, "can't alloc bdl\n"); 2274 return (rc); 2275 } 2276 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2277 2278 return (0); 2279} 2280 2281static void 2282hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2283 int index, int lmute, int rmute, 2284 int left, int right, int dir) 2285{ 2286 uint16_t v = 0; 2287 2288 if (sc == NULL) 2289 return; 2290 2291 if (left != right || lmute != rmute) { 2292 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2293 (lmute << 7) | left; 2294 hdac_command(sc, 2295 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2296 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2297 (rmute << 7) | right; 2298 } else 2299 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2300 (lmute << 7) | left; 2301 2302 hdac_command(sc, 2303 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2304} 2305 2306static void 2307hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2308 int left, int right) 2309{ 2310 struct hdac_softc *sc; 2311 nid_t nid, cad; 2312 int lmute, rmute; 2313 2314 if (ctl == NULL || ctl->widget == NULL || 2315 ctl->widget->devinfo == NULL || 2316 ctl->widget->devinfo->codec == NULL || 2317 ctl->widget->devinfo->codec->sc == NULL) 2318 return; 2319 2320 sc = ctl->widget->devinfo->codec->sc; 2321 cad = ctl->widget->devinfo->codec->cad; 2322 nid = ctl->widget->nid; 2323 2324 if (mute == HDA_AMP_MUTE_DEFAULT) { 2325 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2326 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2327 } else { 2328 lmute = HDA_AMP_LEFT_MUTED(mute); 2329 rmute = HDA_AMP_RIGHT_MUTED(mute); 2330 } 2331 2332 if (ctl->dir & HDA_CTL_OUT) 2333 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2334 lmute, rmute, left, right, 0); 2335 if (ctl->dir & HDA_CTL_IN) 2336 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2337 lmute, rmute, left, right, 1); 2338 ctl->left = left; 2339 ctl->right = right; 2340} 2341 2342static void 2343hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2344{ 2345 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2346 return; 2347 hdac_command(w->devinfo->codec->sc, 2348 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2349 w->nid, index), w->devinfo->codec->cad); 2350 w->selconn = index; 2351} 2352 2353 2354/**************************************************************************** 2355 * uint32_t hdac_command_sendone_internal 2356 * 2357 * Wrapper function that sends only one command to a given codec 2358 ****************************************************************************/ 2359static uint32_t 2360hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2361{ 2362 struct hdac_command_list cl; 2363 uint32_t response = HDAC_INVALID; 2364 2365 if (!hdac_lockowned(sc)) 2366 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2367 cl.num_commands = 1; 2368 cl.verbs = &verb; 2369 cl.responses = &response; 2370 2371 hdac_command_send_internal(sc, &cl, cad); 2372 2373 return (response); 2374} 2375 2376/**************************************************************************** 2377 * hdac_command_send_internal 2378 * 2379 * Send a command list to the codec via the corb. We queue as much verbs as 2380 * we can and msleep on the codec. When the interrupt get the responses 2381 * back from the rirb, it will wake us up so we can queue the remaining verbs 2382 * if any. 2383 ****************************************************************************/ 2384static void 2385hdac_command_send_internal(struct hdac_softc *sc, 2386 struct hdac_command_list *commands, nid_t cad) 2387{ 2388 struct hdac_codec *codec; 2389 int corbrp; 2390 uint32_t *corb; 2391 int timeout; 2392 int retry = 10; 2393 struct hdac_rirb *rirb_base; 2394 2395 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2396 commands->num_commands < 1) 2397 return; 2398 2399 codec = sc->codecs[cad]; 2400 codec->commands = commands; 2401 codec->responses_received = 0; 2402 codec->verbs_sent = 0; 2403 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2404 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2405 2406 do { 2407 if (codec->verbs_sent != commands->num_commands) { 2408 /* Queue as many verbs as possible */ 2409 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2410 bus_dmamap_sync(sc->corb_dma.dma_tag, 2411 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2412 while (codec->verbs_sent != commands->num_commands && 2413 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2414 sc->corb_wp++; 2415 sc->corb_wp %= sc->corb_size; 2416 corb[sc->corb_wp] = 2417 commands->verbs[codec->verbs_sent++]; 2418 } 2419 2420 /* Send the verbs to the codecs */ 2421 bus_dmamap_sync(sc->corb_dma.dma_tag, 2422 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2423 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2424 } 2425 2426 timeout = 1000; 2427 while (hdac_rirb_flush(sc) == 0 && --timeout) 2428 DELAY(10); 2429 } while ((codec->verbs_sent != commands->num_commands || 2430 codec->responses_received != commands->num_commands) && --retry); 2431 2432 if (retry == 0) 2433 device_printf(sc->dev, 2434 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2435 __func__, commands->num_commands, codec->verbs_sent, 2436 codec->responses_received); 2437 2438 codec->commands = NULL; 2439 codec->responses_received = 0; 2440 codec->verbs_sent = 0; 2441 2442 hdac_unsolq_flush(sc); 2443} 2444 2445 2446/**************************************************************************** 2447 * Device Methods 2448 ****************************************************************************/ 2449 2450/**************************************************************************** 2451 * int hdac_probe(device_t) 2452 * 2453 * Probe for the presence of an hdac. If none is found, check for a generic 2454 * match using the subclass of the device. 2455 ****************************************************************************/ 2456static int 2457hdac_probe(device_t dev) 2458{ 2459 int i, result; 2460 uint32_t model; 2461 uint16_t class, subclass; 2462 char desc[64]; 2463 2464 model = (uint32_t)pci_get_device(dev) << 16; 2465 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2466 class = pci_get_class(dev); 2467 subclass = pci_get_subclass(dev); 2468 2469 bzero(desc, sizeof(desc)); 2470 result = ENXIO; 2471 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2472 if (hdac_devices[i].model == model) { 2473 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2474 result = BUS_PROBE_DEFAULT; 2475 break; 2476 } 2477 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2478 class == PCIC_MULTIMEDIA && 2479 subclass == PCIS_MULTIMEDIA_HDA) { 2480 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2481 result = BUS_PROBE_GENERIC; 2482 break; 2483 } 2484 } 2485 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2486 subclass == PCIS_MULTIMEDIA_HDA) { 2487 strlcpy(desc, "Generic", sizeof(desc)); 2488 result = BUS_PROBE_GENERIC; 2489 } 2490 if (result != ENXIO) { 2491 strlcat(desc, " High Definition Audio Controller", 2492 sizeof(desc)); 2493 device_set_desc_copy(dev, desc); 2494 } 2495 2496 return (result); 2497} 2498 2499static void * 2500hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2501 struct pcm_channel *c, int dir) 2502{ 2503 struct hdac_devinfo *devinfo = data; 2504 struct hdac_softc *sc = devinfo->codec->sc; 2505 struct hdac_chan *ch; 2506 2507 hdac_lock(sc); 2508 if (dir == PCMDIR_PLAY) { 2509 ch = &sc->play; 2510 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2511 ch->dir = PCMDIR_PLAY; 2512 ch->sid = ++sc->streamcnt; 2513 devinfo->function.audio.playcnt++; 2514 } else { 2515 ch = &sc->rec; 2516 ch->off = devinfo->function.audio.reccnt << 5; 2517 ch->dir = PCMDIR_REC; 2518 ch->sid = ++sc->streamcnt; 2519 devinfo->function.audio.reccnt++; 2520 } 2521 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2522 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2523 ch->pcmrates[0] = 48000; 2524 ch->pcmrates[1] = 0; 2525 } 2526 ch->b = b; 2527 ch->c = c; 2528 ch->devinfo = devinfo; 2529 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2530 ch->blkcnt = sc->chan_blkcnt; 2531 hdac_unlock(sc); 2532 2533 if (hdac_bdl_alloc(ch) != 0) { 2534 ch->blkcnt = 0; 2535 return (NULL); 2536 } 2537 2538 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2539 return (NULL); 2540 2541 hdac_dma_nocache(ch->b->buf); 2542 2543 return (ch); 2544} 2545 2546static int 2547hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2548{ 2549 struct hdac_chan *ch = data; 2550 int i; 2551 2552 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2553 if (format == ch->caps.fmtlist[i]) { 2554 ch->fmt = format; 2555 return (0); 2556 } 2557 } 2558 2559 return (EINVAL); 2560} 2561 2562static int 2563hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2564{ 2565 struct hdac_chan *ch = data; 2566 uint32_t spd = 0, threshold; 2567 int i; 2568 2569 for (i = 0; ch->pcmrates[i] != 0; i++) { 2570 spd = ch->pcmrates[i]; 2571 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2572 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2573 if (speed < threshold) 2574 break; 2575 } 2576 2577 if (spd == 0) /* impossible */ 2578 ch->spd = 48000; 2579 else 2580 ch->spd = spd; 2581 2582 return (ch->spd); 2583} 2584 2585static void 2586hdac_stream_setup(struct hdac_chan *ch) 2587{ 2588 struct hdac_softc *sc = ch->devinfo->codec->sc; 2589 int i; 2590 nid_t cad = ch->devinfo->codec->cad; 2591 uint16_t fmt; 2592 2593 fmt = 0; 2594 if (ch->fmt & AFMT_S16_LE) 2595 fmt |= ch->bit16 << 4; 2596 else if (ch->fmt & AFMT_S32_LE) 2597 fmt |= ch->bit32 << 4; 2598 else 2599 fmt |= 1 << 4; 2600 2601 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2602 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2603 fmt |= hda_rate_tab[i].base; 2604 fmt |= hda_rate_tab[i].mul; 2605 fmt |= hda_rate_tab[i].div; 2606 break; 2607 } 2608 } 2609 2610 if (ch->fmt & AFMT_STEREO) 2611 fmt |= 1; 2612 2613 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2614 2615 for (i = 0; ch->io[i] != -1; i++) { 2616 HDA_BOOTVERBOSE( 2617 device_printf(sc->dev, 2618 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2619 "fmt=0x%08x\n", 2620 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2621 ch->io[i], fmt); 2622 ); 2623 hdac_command(sc, 2624 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2625 hdac_command(sc, 2626 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2627 ch->sid << 4), cad); 2628 } 2629} 2630 2631static int 2632hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2633{ 2634 struct hdac_chan *ch = data; 2635 struct hdac_softc *sc = ch->devinfo->codec->sc; 2636 2637 blksz &= ~0x7f; 2638 if (blksz < 0x80) 2639 blksz = 0x80; 2640 2641 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2642 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2643 2644 if ((sndbuf_getblksz(ch->b) != blksz || 2645 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2646 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2647 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2648 __func__, blksz, ch->blkcnt); 2649 2650 ch->blksz = sndbuf_getblksz(ch->b); 2651 2652 return (ch->blksz); 2653} 2654 2655static void 2656hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2657{ 2658 struct hdac_devinfo *devinfo = ch->devinfo; 2659 nid_t cad = devinfo->codec->cad; 2660 int i; 2661 2662 hdac_stream_stop(ch); 2663 2664 for (i = 0; ch->io[i] != -1; i++) { 2665 hdac_command(sc, 2666 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2667 0), cad); 2668 } 2669} 2670 2671static void 2672hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2673{ 2674 ch->ptr = 0; 2675 ch->prevptr = 0; 2676 hdac_stream_stop(ch); 2677 hdac_stream_reset(ch); 2678 hdac_bdl_setup(ch); 2679 hdac_stream_setid(ch); 2680 hdac_stream_setup(ch); 2681 hdac_stream_start(ch); 2682} 2683 2684static int 2685hdac_channel_trigger(kobj_t obj, void *data, int go) 2686{ 2687 struct hdac_chan *ch = data; 2688 struct hdac_softc *sc = ch->devinfo->codec->sc; 2689 2690 hdac_lock(sc); 2691 switch (go) { 2692 case PCMTRIG_START: 2693 hdac_channel_start(sc, ch); 2694 break; 2695 case PCMTRIG_STOP: 2696 case PCMTRIG_ABORT: 2697 hdac_channel_stop(sc, ch); 2698 break; 2699 } 2700 hdac_unlock(sc); 2701 2702 return (0); 2703} 2704 2705static int 2706hdac_channel_getptr(kobj_t obj, void *data) 2707{ 2708 struct hdac_chan *ch = data; 2709 struct hdac_softc *sc = ch->devinfo->codec->sc; 2710 uint32_t ptr; 2711 2712 hdac_lock(sc); 2713 if (sc->polling != 0) 2714 ptr = ch->ptr; 2715 else 2716 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2717 hdac_unlock(sc); 2718 2719 /* 2720 * Round to available space and force 128 bytes aligment. 2721 */ 2722 ptr %= ch->blksz * ch->blkcnt; 2723 ptr &= ~0x7f; 2724 2725 return (ptr); 2726} 2727 2728static struct pcmchan_caps * 2729hdac_channel_getcaps(kobj_t obj, void *data) 2730{ 2731 return (&((struct hdac_chan *)data)->caps); 2732} 2733 2734static kobj_method_t hdac_channel_methods[] = { 2735 KOBJMETHOD(channel_init, hdac_channel_init), 2736 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2737 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2738 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2739 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2740 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2741 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2742 { 0, 0 } 2743}; 2744CHANNEL_DECLARE(hdac_channel); 2745 2746static int 2747hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2748{ 2749 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2750 struct hdac_softc *sc = devinfo->codec->sc; 2751 struct hdac_widget *w, *cw; 2752 struct hdac_audio_ctl *ctl; 2753 uint32_t mask, recmask, id; 2754 int i, j, softpcmvol; 2755 nid_t cad; 2756 2757 hdac_lock(sc); 2758 2759 mask = 0; 2760 recmask = 0; 2761 2762 id = hdac_codec_id(devinfo); 2763 cad = devinfo->codec->cad; 2764 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2765 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2766 sc->pci_subvendor) && 2767 hdac_hp_switch[i].id == id)) 2768 continue; 2769 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2770 if (w != NULL && w->enable != 0 2771 && w->type == 2772 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2773 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2774 hdac_command(sc, 2775 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2776 w->nid, 2777 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2778 HDAC_UNSOLTAG_EVENT_HP), cad); 2779 hdac_hp_switch_handler(devinfo); 2780 HDA_BOOTVERBOSE( 2781 device_printf(sc->dev, 2782 "HDA_DEBUG: Enabling headphone/speaker " 2783 "audio routing switching:\n"); 2784 device_printf(sc->dev, 2785 "HDA_DEBUG: \tindex=%d nid=%d " 2786 "pci_subvendor=0x%08x " 2787 "codec=0x%08x\n", 2788 i, w->nid, sc->pci_subvendor, id); 2789 ); 2790 } 2791 break; 2792 } 2793 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2794 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2795 sc->pci_subvendor) && 2796 hdac_eapd_switch[i].id == id)) 2797 continue; 2798 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2799 if (w == NULL || w->enable == 0) 2800 break; 2801 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2802 w->param.eapdbtl == HDAC_INVALID) 2803 break; 2804 mask |= SOUND_MASK_OGAIN; 2805 break; 2806 } 2807 2808 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2809 w = hdac_widget_get(devinfo, i); 2810 if (w == NULL || w->enable == 0) 2811 continue; 2812 mask |= w->ctlflags; 2813 if (!(w->pflags & HDA_ADC_RECSEL)) 2814 continue; 2815 for (j = 0; j < w->nconns; j++) { 2816 cw = hdac_widget_get(devinfo, w->conns[j]); 2817 if (cw == NULL || cw->enable == 0) 2818 continue; 2819 recmask |= cw->ctlflags; 2820 } 2821 } 2822 2823 if (!(mask & SOUND_MASK_PCM)) { 2824 softpcmvol = 1; 2825 mask |= SOUND_MASK_PCM; 2826 } else 2827 softpcmvol = (devinfo->function.audio.quirks & 2828 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2829 2830 i = 0; 2831 ctl = NULL; 2832 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2833 if (ctl->widget == NULL || ctl->enable == 0) 2834 continue; 2835 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2836 continue; 2837 if (ctl->step > 0) 2838 break; 2839 } 2840 2841 if (softpcmvol == 1 || ctl == NULL) { 2842 struct snddev_info *d = NULL; 2843 d = device_get_softc(sc->dev); 2844 if (d != NULL) { 2845 d->flags |= SD_F_SOFTPCMVOL; 2846 HDA_BOOTVERBOSE( 2847 device_printf(sc->dev, 2848 "HDA_DEBUG: %s Soft PCM volume\n", 2849 (softpcmvol == 1) ? 2850 "Forcing" : "Enabling"); 2851 ); 2852 } 2853 i = 0; 2854 /* 2855 * XXX Temporary quirk for STAC9220, until the parser 2856 * become smarter. 2857 */ 2858 if (id == HDA_CODEC_STAC9220) { 2859 mask |= SOUND_MASK_VOLUME; 2860 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2861 NULL) { 2862 if (ctl->widget == NULL || ctl->enable == 0) 2863 continue; 2864 if (ctl->widget->nid == 11 && ctl->index == 0) { 2865 ctl->ossmask = SOUND_MASK_VOLUME; 2866 ctl->ossval = 100 | (100 << 8); 2867 } else 2868 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2869 } 2870 } else { 2871 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2872 SOUND_MASK_PCM); 2873 if (!(mask & SOUND_MASK_VOLUME)) 2874 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2875 SOUND_MIXER_NONE); 2876 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2877 NULL) { 2878 if (ctl->widget == NULL || ctl->enable == 0) 2879 continue; 2880 if (!HDA_FLAG_MATCH(ctl->ossmask, 2881 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2882 continue; 2883 if (!(ctl->mute == 1 && ctl->step == 0)) 2884 ctl->enable = 0; 2885 } 2886 } 2887 } 2888 2889 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2890 2891 mix_setrecdevs(m, recmask); 2892 mix_setdevs(m, mask); 2893 2894 hdac_unlock(sc); 2895 2896 return (0); 2897} 2898 2899static int 2900hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2901 unsigned left, unsigned right) 2902{ 2903 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2904 struct hdac_softc *sc = devinfo->codec->sc; 2905 struct hdac_widget *w; 2906 struct hdac_audio_ctl *ctl; 2907 uint32_t id, mute; 2908 int lvol, rvol, mlvol, mrvol; 2909 int i = 0; 2910 2911 hdac_lock(sc); 2912 if (dev == SOUND_MIXER_OGAIN) { 2913 uint32_t orig; 2914 /*if (left != right || !(left == 0 || left == 1)) { 2915 hdac_unlock(sc); 2916 return (-1); 2917 }*/ 2918 id = hdac_codec_id(devinfo); 2919 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2920 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2921 sc->pci_subvendor) && 2922 hdac_eapd_switch[i].id == id) 2923 break; 2924 } 2925 if (i >= HDAC_EAPD_SWITCH_LEN) { 2926 hdac_unlock(sc); 2927 return (-1); 2928 } 2929 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2930 if (w == NULL || 2931 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2932 w->param.eapdbtl == HDAC_INVALID) { 2933 hdac_unlock(sc); 2934 return (-1); 2935 } 2936 orig = w->param.eapdbtl; 2937 if (left == 0) 2938 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2939 else 2940 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2941 if (orig != w->param.eapdbtl) { 2942 uint32_t val; 2943 2944 if (hdac_eapd_switch[i].hp_switch != 0) 2945 hdac_hp_switch_handler(devinfo); 2946 val = w->param.eapdbtl; 2947 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2948 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2949 hdac_command(sc, 2950 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2951 w->nid, val), devinfo->codec->cad); 2952 } 2953 hdac_unlock(sc); 2954 return (left | (left << 8)); 2955 } 2956 if (dev == SOUND_MIXER_VOLUME) 2957 devinfo->function.audio.mvol = left | (right << 8); 2958 2959 mlvol = devinfo->function.audio.mvol & 0x7f; 2960 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2961 lvol = 0; 2962 rvol = 0; 2963 2964 i = 0; 2965 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2966 if (ctl->widget == NULL || ctl->enable == 0 || 2967 !(ctl->ossmask & (1 << dev))) 2968 continue; 2969 switch (dev) { 2970 case SOUND_MIXER_VOLUME: 2971 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2972 lvol = (lvol * ctl->step) / 100; 2973 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2974 rvol = (rvol * ctl->step) / 100; 2975 break; 2976 default: 2977 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2978 lvol = (left * mlvol) / 100; 2979 lvol = (lvol * ctl->step) / 100; 2980 rvol = (right * mrvol) / 100; 2981 rvol = (rvol * ctl->step) / 100; 2982 } else { 2983 lvol = (left * ctl->step) / 100; 2984 rvol = (right * ctl->step) / 100; 2985 } 2986 ctl->ossval = left | (right << 8); 2987 break; 2988 } 2989 mute = 0; 2990 if (ctl->step < 1) { 2991 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2992 (ctl->muted & HDA_AMP_MUTE_LEFT); 2993 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2994 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2995 } else { 2996 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2997 (ctl->muted & HDA_AMP_MUTE_LEFT); 2998 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2999 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3000 } 3001 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3002 } 3003 hdac_unlock(sc); 3004 3005 return (left | (right << 8)); 3006} 3007 3008static int 3009hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3010{ 3011 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3012 struct hdac_widget *w, *cw; 3013 struct hdac_softc *sc = devinfo->codec->sc; 3014 uint32_t ret = src, target; 3015 int i, j; 3016 3017 target = 0; 3018 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3019 if (src & (1 << i)) { 3020 target = 1 << i; 3021 break; 3022 } 3023 } 3024 3025 hdac_lock(sc); 3026 3027 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3028 w = hdac_widget_get(devinfo, i); 3029 if (w == NULL || w->enable == 0) 3030 continue; 3031 if (!(w->pflags & HDA_ADC_RECSEL)) 3032 continue; 3033 for (j = 0; j < w->nconns; j++) { 3034 cw = hdac_widget_get(devinfo, w->conns[j]); 3035 if (cw == NULL || cw->enable == 0) 3036 continue; 3037 if ((target == SOUND_MASK_VOLUME && 3038 cw->type != 3039 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3040 (target != SOUND_MASK_VOLUME && 3041 cw->type == 3042 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3043 continue; 3044 if (cw->ctlflags & target) { 3045 hdac_widget_connection_select(w, j); 3046 ret = target; 3047 j += w->nconns; 3048 } 3049 } 3050 } 3051 3052 hdac_unlock(sc); 3053 3054 return (ret); 3055} 3056 3057static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3058 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3059 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3060 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3061 { 0, 0 } 3062}; 3063MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3064 3065/**************************************************************************** 3066 * int hdac_attach(device_t) 3067 * 3068 * Attach the device into the kernel. Interrupts usually won't be enabled 3069 * when this function is called. Setup everything that doesn't require 3070 * interrupts and defer probing of codecs until interrupts are enabled. 3071 ****************************************************************************/ 3072static int 3073hdac_attach(device_t dev) 3074{ 3075 struct hdac_softc *sc; 3076 int result; 3077 int i = 0; 3078 3079 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3080 if (sc == NULL) { 3081 device_printf(dev, "cannot allocate softc\n"); 3082 return (ENOMEM); 3083 } 3084 3085 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3086 if (sc->lock == NULL) { 3087 device_printf(dev, "mutex creation failed\n"); 3088 free(sc, M_DEVBUF); 3089 return (ENOMEM); 3090 } 3091 3092 sc->dev = dev; 3093 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3094 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3095 3096 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3097 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3098 3099 sc->poll_ticks = 1; 3100 if (resource_int_value(device_get_name(sc->dev), 3101 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3102 sc->polling = 1; 3103 else 3104 sc->polling = 0; 3105 3106 sc->chan_size = pcm_getbuffersize(dev, 3107 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3108 3109 if (resource_int_value(device_get_name(sc->dev), 3110 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3111 i &= ~0x7f; 3112 if (i < 0x80) 3113 i = 0x80; 3114 sc->chan_blkcnt = sc->chan_size / i; 3115 i = 0; 3116 while (sc->chan_blkcnt >> i) 3117 i++; 3118 sc->chan_blkcnt = 1 << (i - 1); 3119 if (sc->chan_blkcnt < HDA_BDL_MIN) 3120 sc->chan_blkcnt = HDA_BDL_MIN; 3121 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3122 sc->chan_blkcnt = HDA_BDL_MAX; 3123 } else 3124 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3125 3126 result = bus_dma_tag_create(NULL, /* parent */ 3127 HDAC_DMA_ALIGNMENT, /* alignment */ 3128 0, /* boundary */ 3129 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3130 BUS_SPACE_MAXADDR, /* highaddr */ 3131 NULL, /* filtfunc */ 3132 NULL, /* fistfuncarg */ 3133 sc->chan_size, /* maxsize */ 3134 1, /* nsegments */ 3135 sc->chan_size, /* maxsegsz */ 3136 0, /* flags */ 3137 NULL, /* lockfunc */ 3138 NULL, /* lockfuncarg */ 3139 &sc->chan_dmat); /* dmat */ 3140 if (result != 0) { 3141 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3142 __func__, result); 3143 snd_mtxfree(sc->lock); 3144 free(sc, M_DEVBUF); 3145 return (ENXIO); 3146 } 3147 3148 3149 sc->hdabus = NULL; 3150 for (i = 0; i < HDAC_CODEC_MAX; i++) 3151 sc->codecs[i] = NULL; 3152 3153 pci_enable_busmaster(dev); 3154 3155 /* Allocate resources */ 3156 result = hdac_mem_alloc(sc); 3157 if (result != 0) 3158 goto hdac_attach_fail; 3159 result = hdac_irq_alloc(sc); 3160 if (result != 0) 3161 goto hdac_attach_fail; 3162 3163 /* Get Capabilities */ 3164 result = hdac_get_capabilities(sc); 3165 if (result != 0) 3166 goto hdac_attach_fail; 3167 3168 /* Allocate CORB and RIRB dma memory */ 3169 result = hdac_dma_alloc(sc, &sc->corb_dma, 3170 sc->corb_size * sizeof(uint32_t)); 3171 if (result != 0) 3172 goto hdac_attach_fail; 3173 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3174 sc->rirb_size * sizeof(struct hdac_rirb)); 3175 if (result != 0) 3176 goto hdac_attach_fail; 3177 3178 /* Quiesce everything */ 3179 hdac_reset(sc); 3180 3181 /* Disable PCI-Express QOS */ 3182 pci_write_config(sc->dev, 0x44, 3183 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3184 3185 /* Initialize the CORB and RIRB */ 3186 hdac_corb_init(sc); 3187 hdac_rirb_init(sc); 3188 3189 /* Defer remaining of initialization until interrupts are enabled */ 3190 sc->intrhook.ich_func = hdac_attach2; 3191 sc->intrhook.ich_arg = (void *)sc; 3192 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3193 sc->intrhook.ich_func = NULL; 3194 hdac_attach2((void *)sc); 3195 } 3196 3197 return (0); 3198 3199hdac_attach_fail: 3200 hdac_dma_free(&sc->rirb_dma); 3201 hdac_dma_free(&sc->corb_dma); 3202 hdac_irq_free(sc); 3203 hdac_mem_free(sc); 3204 snd_mtxfree(sc->lock); 3205 free(sc, M_DEVBUF); 3206 3207 return (ENXIO); 3208} 3209 3210static void 3211hdac_audio_parse(struct hdac_devinfo *devinfo) 3212{ 3213 struct hdac_softc *sc = devinfo->codec->sc; 3214 struct hdac_widget *w; 3215 uint32_t res; 3216 int i; 3217 nid_t cad, nid; 3218 3219 cad = devinfo->codec->cad; 3220 nid = devinfo->nid; 3221 3222 hdac_command(sc, 3223 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3224 3225 DELAY(100); 3226 3227 res = hdac_command(sc, 3228 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3229 3230 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3231 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3232 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3233 3234 HDA_BOOTVERBOSE( 3235 device_printf(sc->dev, " Vendor: 0x%08x\n", 3236 devinfo->vendor_id); 3237 device_printf(sc->dev, " Device: 0x%08x\n", 3238 devinfo->device_id); 3239 device_printf(sc->dev, " Revision: 0x%08x\n", 3240 devinfo->revision_id); 3241 device_printf(sc->dev, " Stepping: 0x%08x\n", 3242 devinfo->stepping_id); 3243 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3244 sc->pci_subvendor); 3245 device_printf(sc->dev, " Nodes: start=%d " 3246 "endnode=%d total=%d\n", 3247 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3248 ); 3249 3250 res = hdac_command(sc, 3251 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3252 cad); 3253 devinfo->function.audio.supp_stream_formats = res; 3254 3255 res = hdac_command(sc, 3256 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3257 cad); 3258 devinfo->function.audio.supp_pcm_size_rate = res; 3259 3260 res = hdac_command(sc, 3261 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3262 cad); 3263 devinfo->function.audio.outamp_cap = res; 3264 3265 res = hdac_command(sc, 3266 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3267 cad); 3268 devinfo->function.audio.inamp_cap = res; 3269 3270 if (devinfo->nodecnt > 0) { 3271 hdac_unlock(sc); 3272 devinfo->widget = (struct hdac_widget *)malloc( 3273 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3274 M_NOWAIT | M_ZERO); 3275 hdac_lock(sc); 3276 } else 3277 devinfo->widget = NULL; 3278 3279 if (devinfo->widget == NULL) { 3280 device_printf(sc->dev, "unable to allocate widgets!\n"); 3281 devinfo->endnode = devinfo->startnode; 3282 devinfo->nodecnt = 0; 3283 return; 3284 } 3285 3286 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3287 w = hdac_widget_get(devinfo, i); 3288 if (w == NULL) 3289 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3290 else { 3291 w->devinfo = devinfo; 3292 w->nid = i; 3293 w->enable = 1; 3294 w->selconn = -1; 3295 w->pflags = 0; 3296 w->ctlflags = 0; 3297 w->param.eapdbtl = HDAC_INVALID; 3298 hdac_widget_parse(w); 3299 } 3300 } 3301} 3302 3303static void 3304hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3305{ 3306 struct hdac_softc *sc = devinfo->codec->sc; 3307 struct hdac_audio_ctl *ctls; 3308 struct hdac_widget *w, *cw; 3309 int i, j, cnt, max, ocap, icap; 3310 int mute, offset, step, size; 3311 3312 /* XXX This is redundant */ 3313 max = 0; 3314 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3315 w = hdac_widget_get(devinfo, i); 3316 if (w == NULL || w->enable == 0) 3317 continue; 3318 if (w->param.outamp_cap != 0) 3319 max++; 3320 if (w->param.inamp_cap != 0) { 3321 switch (w->type) { 3322 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3323 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3324 for (j = 0; j < w->nconns; j++) { 3325 cw = hdac_widget_get(devinfo, 3326 w->conns[j]); 3327 if (cw == NULL || cw->enable == 0) 3328 continue; 3329 max++; 3330 } 3331 break; 3332 default: 3333 max++; 3334 break; 3335 } 3336 } 3337 } 3338 3339 devinfo->function.audio.ctlcnt = max; 3340 3341 if (max < 1) 3342 return; 3343 3344 hdac_unlock(sc); 3345 ctls = (struct hdac_audio_ctl *)malloc( 3346 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3347 hdac_lock(sc); 3348 3349 if (ctls == NULL) { 3350 /* Blekh! */ 3351 device_printf(sc->dev, "unable to allocate ctls!\n"); 3352 devinfo->function.audio.ctlcnt = 0; 3353 return; 3354 } 3355 3356 cnt = 0; 3357 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3358 if (cnt >= max) { 3359 device_printf(sc->dev, "%s: Ctl overflow!\n", 3360 __func__); 3361 break; 3362 } 3363 w = hdac_widget_get(devinfo, i); 3364 if (w == NULL || w->enable == 0) 3365 continue; 3366 ocap = w->param.outamp_cap; 3367 icap = w->param.inamp_cap; 3368 if (ocap != 0) { 3369 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3370 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3371 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3372 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3373 /*if (offset > step) { 3374 HDA_BOOTVERBOSE( 3375 device_printf(sc->dev, 3376 "HDA_DEBUG: BUGGY outamp: nid=%d " 3377 "[offset=%d > step=%d]\n", 3378 w->nid, offset, step); 3379 ); 3380 offset = step; 3381 }*/ 3382 ctls[cnt].enable = 1; 3383 ctls[cnt].widget = w; 3384 ctls[cnt].mute = mute; 3385 ctls[cnt].step = step; 3386 ctls[cnt].size = size; 3387 ctls[cnt].offset = offset; 3388 ctls[cnt].left = offset; 3389 ctls[cnt].right = offset; 3390 ctls[cnt++].dir = HDA_CTL_OUT; 3391 } 3392 3393 if (icap != 0) { 3394 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3395 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3396 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3397 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3398 /*if (offset > step) { 3399 HDA_BOOTVERBOSE( 3400 device_printf(sc->dev, 3401 "HDA_DEBUG: BUGGY inamp: nid=%d " 3402 "[offset=%d > step=%d]\n", 3403 w->nid, offset, step); 3404 ); 3405 offset = step; 3406 }*/ 3407 switch (w->type) { 3408 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3409 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3410 for (j = 0; j < w->nconns; j++) { 3411 if (cnt >= max) { 3412 device_printf(sc->dev, 3413 "%s: Ctl overflow!\n", 3414 __func__); 3415 break; 3416 } 3417 cw = hdac_widget_get(devinfo, 3418 w->conns[j]); 3419 if (cw == NULL || cw->enable == 0) 3420 continue; 3421 ctls[cnt].enable = 1; 3422 ctls[cnt].widget = w; 3423 ctls[cnt].childwidget = cw; 3424 ctls[cnt].index = j; 3425 ctls[cnt].mute = mute; 3426 ctls[cnt].step = step; 3427 ctls[cnt].size = size; 3428 ctls[cnt].offset = offset; 3429 ctls[cnt].left = offset; 3430 ctls[cnt].right = offset; 3431 ctls[cnt++].dir = HDA_CTL_IN; 3432 } 3433 break; 3434 default: 3435 if (cnt >= max) { 3436 device_printf(sc->dev, 3437 "%s: Ctl overflow!\n", 3438 __func__); 3439 break; 3440 } 3441 ctls[cnt].enable = 1; 3442 ctls[cnt].widget = w; 3443 ctls[cnt].mute = mute; 3444 ctls[cnt].step = step; 3445 ctls[cnt].size = size; 3446 ctls[cnt].offset = offset; 3447 ctls[cnt].left = offset; 3448 ctls[cnt].right = offset; 3449 ctls[cnt++].dir = HDA_CTL_IN; 3450 break; 3451 } 3452 } 3453 } 3454 3455 devinfo->function.audio.ctl = ctls; 3456} 3457 3458static const struct { 3459 uint32_t model; 3460 uint32_t id; 3461 uint32_t set, unset; 3462} hdac_quirks[] = { 3463 /* 3464 * XXX Force stereo quirk. Monoural recording / playback 3465 * on few codecs (especially ALC880) seems broken or 3466 * perhaps unsupported. 3467 */ 3468 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3469 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3470 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3471 HDA_QUIRK_GPIO0, 0 }, 3472 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3473 HDA_QUIRK_GPIO0, 0 }, 3474 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3475 HDA_QUIRK_GPIO1, 0 }, 3476 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3477 HDA_QUIRK_EAPDINV, 0 }, 3478 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3479 HDA_QUIRK_EAPDINV, 0 }, 3480 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3481 HDA_QUIRK_EAPDINV, 0 }, 3482 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3483 HDA_QUIRK_EAPDINV, 0 }, 3484 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3485 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3486 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3487 0, HDA_QUIRK_FORCESTEREO }, 3488 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3489 HDA_QUIRK_SOFTPCMVOL, 0 } 3490}; 3491#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3492 3493static void 3494hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3495{ 3496 struct hdac_widget *w; 3497 uint32_t id, subvendor; 3498 int i; 3499 3500 id = hdac_codec_id(devinfo); 3501 subvendor = devinfo->codec->sc->pci_subvendor; 3502 3503 /* 3504 * Quirks 3505 */ 3506 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3507 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3508 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3509 continue; 3510 if (hdac_quirks[i].set != 0) 3511 devinfo->function.audio.quirks |= 3512 hdac_quirks[i].set; 3513 if (hdac_quirks[i].unset != 0) 3514 devinfo->function.audio.quirks &= 3515 ~(hdac_quirks[i].unset); 3516 } 3517 3518 switch (id) { 3519 case HDA_CODEC_ALC260: 3520 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3521 w = hdac_widget_get(devinfo, i); 3522 if (w == NULL || w->enable == 0) 3523 continue; 3524 if (w->type != 3525 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3526 continue; 3527 if (w->nid != 5) 3528 w->enable = 0; 3529 } 3530 break; 3531 case HDA_CODEC_ALC861: 3532 if (subvendor == ASUS_P1AH2_SUBVENDOR) { 3533 struct hdac_audio_ctl *ctl; 3534 3535 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3536 if (ctl != NULL) 3537 ctl->muted = HDA_AMP_MUTE_ALL; 3538 } 3539 break; 3540 case HDA_CODEC_ALC880: 3541 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3542 w = hdac_widget_get(devinfo, i); 3543 if (w == NULL || w->enable == 0) 3544 continue; 3545 if (w->type == 3546 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3547 w->nid != 9 && w->nid != 29) { 3548 w->enable = 0; 3549 } else if (w->type != 3550 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3551 w->nid == 29) { 3552 w->type = 3553 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3554 w->param.widget_cap &= 3555 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3556 w->param.widget_cap |= 3557 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3558 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3559 strlcpy(w->name, "beep widget", sizeof(w->name)); 3560 } 3561 } 3562 break; 3563 case HDA_CODEC_AD1981HD: 3564 w = hdac_widget_get(devinfo, 11); 3565 if (w != NULL && w->enable != 0 && w->nconns > 3) 3566 w->selconn = 3; 3567 if (subvendor == IBM_M52_SUBVENDOR) { 3568 struct hdac_audio_ctl *ctl; 3569 3570 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3571 if (ctl != NULL) 3572 ctl->ossmask = SOUND_MASK_SPEAKER; 3573 } 3574 break; 3575 case HDA_CODEC_AD1986A: 3576 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3577 w = hdac_widget_get(devinfo, i); 3578 if (w == NULL || w->enable == 0) 3579 continue; 3580 if (w->type != 3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3582 continue; 3583 if (w->nid != 3) 3584 w->enable = 0; 3585 } 3586 break; 3587 case HDA_CODEC_STAC9221: 3588 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3589 w = hdac_widget_get(devinfo, i); 3590 if (w == NULL || w->enable == 0) 3591 continue; 3592 if (w->type != 3593 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3594 continue; 3595 if (w->nid != 2) 3596 w->enable = 0; 3597 } 3598 break; 3599 case HDA_CODEC_STAC9221D: 3600 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3601 w = hdac_widget_get(devinfo, i); 3602 if (w == NULL || w->enable == 0) 3603 continue; 3604 if (w->type == 3605 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3606 w->nid != 6) 3607 w->enable = 0; 3608 3609 } 3610 break; 3611 default: 3612 break; 3613 } 3614} 3615 3616static int 3617hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3618{ 3619 int *dev = &devinfo->function.audio.ossidx; 3620 3621 while (*dev < SOUND_MIXER_NRDEVICES) { 3622 switch (*dev) { 3623 case SOUND_MIXER_VOLUME: 3624 case SOUND_MIXER_BASS: 3625 case SOUND_MIXER_TREBLE: 3626 case SOUND_MIXER_PCM: 3627 case SOUND_MIXER_SPEAKER: 3628 case SOUND_MIXER_LINE: 3629 case SOUND_MIXER_MIC: 3630 case SOUND_MIXER_CD: 3631 case SOUND_MIXER_RECLEV: 3632 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3633 (*dev)++; 3634 break; 3635 default: 3636 return (*dev)++; 3637 break; 3638 } 3639 } 3640 3641 return (-1); 3642} 3643 3644static int 3645hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3646{ 3647 struct hdac_widget *w; 3648 int i, ret = 0; 3649 3650 if (depth > HDA_PARSE_MAXDEPTH) 3651 return (0); 3652 w = hdac_widget_get(devinfo, nid); 3653 if (w == NULL || w->enable == 0) 3654 return (0); 3655 switch (w->type) { 3656 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3657 w->pflags |= HDA_DAC_PATH; 3658 ret = 1; 3659 break; 3660 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3661 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3662 for (i = 0; i < w->nconns; i++) { 3663 if (hdac_widget_find_dac_path(devinfo, 3664 w->conns[i], depth + 1) != 0) { 3665 if (w->selconn == -1) 3666 w->selconn = i; 3667 ret = 1; 3668 w->pflags |= HDA_DAC_PATH; 3669 } 3670 } 3671 break; 3672 default: 3673 break; 3674 } 3675 return (ret); 3676} 3677 3678static int 3679hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3680{ 3681 struct hdac_widget *w; 3682 int i, conndev, ret = 0; 3683 3684 if (depth > HDA_PARSE_MAXDEPTH) 3685 return (0); 3686 w = hdac_widget_get(devinfo, nid); 3687 if (w == NULL || w->enable == 0) 3688 return (0); 3689 switch (w->type) { 3690 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3691 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3692 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3693 for (i = 0; i < w->nconns; i++) { 3694 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3695 depth + 1) != 0) { 3696 if (w->selconn == -1) 3697 w->selconn = i; 3698 w->pflags |= HDA_ADC_PATH; 3699 ret = 1; 3700 } 3701 } 3702 break; 3703 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3704 conndev = w->wclass.pin.config & 3705 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3706 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3707 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3708 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3709 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3710 w->pflags |= HDA_ADC_PATH; 3711 ret = 1; 3712 } 3713 break; 3714 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3715 if (w->pflags & HDA_DAC_PATH) { 3716 w->pflags |= HDA_ADC_PATH; 3717 ret = 1; 3718 } 3719 break;*/ 3720 default: 3721 break; 3722 } 3723 return (ret); 3724} 3725 3726static uint32_t 3727hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3728 nid_t nid, nid_t pnid, int index, int depth) 3729{ 3730 struct hdac_widget *w, *pw; 3731 struct hdac_audio_ctl *ctl; 3732 uint32_t fl = 0; 3733 int i, ossdev, conndev, strategy; 3734 3735 if (depth > HDA_PARSE_MAXDEPTH) 3736 return (0); 3737 3738 w = hdac_widget_get(devinfo, nid); 3739 if (w == NULL || w->enable == 0) 3740 return (0); 3741 3742 pw = hdac_widget_get(devinfo, pnid); 3743 strategy = devinfo->function.audio.parsing_strategy; 3744 3745 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3746 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3747 for (i = 0; i < w->nconns; i++) { 3748 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3749 w->nid, i, depth + 1); 3750 } 3751 w->ctlflags |= fl; 3752 return (fl); 3753 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3754 (w->pflags & HDA_DAC_PATH)) { 3755 i = 0; 3756 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3757 if (ctl->enable == 0 || ctl->widget == NULL) 3758 continue; 3759 /* XXX This should be compressed! */ 3760 if ((ctl->widget->nid == w->nid) || 3761 (ctl->widget->nid == pnid && ctl->index == index && 3762 (ctl->dir & HDA_CTL_IN)) || 3763 (ctl->widget->nid == pnid && pw != NULL && 3764 pw->type == 3765 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3766 (pw->nconns < 2 || pw->selconn == index || 3767 pw->selconn == -1) && 3768 (ctl->dir & HDA_CTL_OUT)) || 3769 (strategy == HDA_PARSE_DIRECT && 3770 ctl->widget->nid == w->nid)) { 3771 /*if (pw != NULL && pw->selconn == -1) 3772 pw->selconn = index; 3773 fl |= SOUND_MASK_VOLUME; 3774 fl |= SOUND_MASK_PCM; 3775 ctl->ossmask |= SOUND_MASK_VOLUME; 3776 ctl->ossmask |= SOUND_MASK_PCM; 3777 ctl->ossdev = SOUND_MIXER_PCM;*/ 3778 if (!(w->ctlflags & SOUND_MASK_PCM) || 3779 (pw != NULL && 3780 !(pw->ctlflags & SOUND_MASK_PCM))) { 3781 fl |= SOUND_MASK_VOLUME; 3782 fl |= SOUND_MASK_PCM; 3783 ctl->ossmask |= SOUND_MASK_VOLUME; 3784 ctl->ossmask |= SOUND_MASK_PCM; 3785 ctl->ossdev = SOUND_MIXER_PCM; 3786 w->ctlflags |= SOUND_MASK_VOLUME; 3787 w->ctlflags |= SOUND_MASK_PCM; 3788 if (pw != NULL) { 3789 if (pw->selconn == -1) 3790 pw->selconn = index; 3791 pw->ctlflags |= 3792 SOUND_MASK_VOLUME; 3793 pw->ctlflags |= 3794 SOUND_MASK_PCM; 3795 } 3796 } 3797 } 3798 } 3799 w->ctlflags |= fl; 3800 return (fl); 3801 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3802 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3803 (w->pflags & HDA_ADC_PATH)) { 3804 conndev = w->wclass.pin.config & 3805 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3806 i = 0; 3807 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3808 if (ctl->enable == 0 || ctl->widget == NULL) 3809 continue; 3810 /* XXX This should be compressed! */ 3811 if (((ctl->widget->nid == pnid && ctl->index == index && 3812 (ctl->dir & HDA_CTL_IN)) || 3813 (ctl->widget->nid == pnid && pw != NULL && 3814 pw->type == 3815 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3816 (pw->nconns < 2 || pw->selconn == index || 3817 pw->selconn == -1) && 3818 (ctl->dir & HDA_CTL_OUT)) || 3819 (strategy == HDA_PARSE_DIRECT && 3820 ctl->widget->nid == w->nid)) && 3821 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3822 if (pw != NULL && pw->selconn == -1) 3823 pw->selconn = index; 3824 ossdev = 0; 3825 switch (conndev) { 3826 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3827 ossdev = SOUND_MIXER_MIC; 3828 break; 3829 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3830 ossdev = SOUND_MIXER_LINE; 3831 break; 3832 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3833 ossdev = SOUND_MIXER_CD; 3834 break; 3835 default: 3836 ossdev = 3837 hdac_audio_ctl_ossmixer_getnextdev( 3838 devinfo); 3839 if (ossdev < 0) 3840 ossdev = 0; 3841 break; 3842 } 3843 if (strategy == HDA_PARSE_MIXER) { 3844 fl |= SOUND_MASK_VOLUME; 3845 ctl->ossmask |= SOUND_MASK_VOLUME; 3846 } 3847 fl |= 1 << ossdev; 3848 ctl->ossmask |= 1 << ossdev; 3849 ctl->ossdev = ossdev; 3850 } 3851 } 3852 w->ctlflags |= fl; 3853 return (fl); 3854 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3855 i = 0; 3856 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3857 if (ctl->enable == 0 || ctl->widget == NULL) 3858 continue; 3859 /* XXX This should be compressed! */ 3860 if (((ctl->widget->nid == pnid && ctl->index == index && 3861 (ctl->dir & HDA_CTL_IN)) || 3862 (ctl->widget->nid == pnid && pw != NULL && 3863 pw->type == 3864 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3865 (pw->nconns < 2 || pw->selconn == index || 3866 pw->selconn == -1) && 3867 (ctl->dir & HDA_CTL_OUT)) || 3868 (strategy == HDA_PARSE_DIRECT && 3869 ctl->widget->nid == w->nid)) && 3870 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3871 if (pw != NULL && pw->selconn == -1) 3872 pw->selconn = index; 3873 fl |= SOUND_MASK_VOLUME; 3874 fl |= SOUND_MASK_SPEAKER; 3875 ctl->ossmask |= SOUND_MASK_VOLUME; 3876 ctl->ossmask |= SOUND_MASK_SPEAKER; 3877 ctl->ossdev = SOUND_MIXER_SPEAKER; 3878 } 3879 } 3880 w->ctlflags |= fl; 3881 return (fl); 3882 } 3883 return (0); 3884} 3885 3886static uint32_t 3887hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3888{ 3889 struct hdac_widget *w, *cw; 3890 struct hdac_audio_ctl *ctl; 3891 uint32_t fl; 3892 int i; 3893 3894 if (depth > HDA_PARSE_MAXDEPTH) 3895 return (0); 3896 3897 w = hdac_widget_get(devinfo, nid); 3898 if (w == NULL || w->enable == 0) 3899 return (0); 3900 /*if (!(w->pflags & HDA_ADC_PATH)) 3901 return (0); 3902 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3903 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3904 return (0);*/ 3905 i = 0; 3906 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3907 if (ctl->enable == 0 || ctl->widget == NULL) 3908 continue; 3909 if (ctl->widget->nid == nid) { 3910 ctl->ossmask |= SOUND_MASK_RECLEV; 3911 w->ctlflags |= SOUND_MASK_RECLEV; 3912 return (SOUND_MASK_RECLEV); 3913 } 3914 } 3915 for (i = 0; i < w->nconns; i++) { 3916 cw = hdac_widget_get(devinfo, w->conns[i]); 3917 if (cw == NULL || cw->enable == 0) 3918 continue; 3919 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3920 continue; 3921 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3922 if (fl != 0) { 3923 cw->ctlflags |= fl; 3924 w->ctlflags |= fl; 3925 return (fl); 3926 } 3927 } 3928 return (0); 3929} 3930 3931static int 3932hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3933{ 3934 struct hdac_widget *w, *cw; 3935 int i, child = 0; 3936 3937 if (depth > HDA_PARSE_MAXDEPTH) 3938 return (0); 3939 3940 w = hdac_widget_get(devinfo, nid); 3941 if (w == NULL || w->enable == 0) 3942 return (0); 3943 /*if (!(w->pflags & HDA_ADC_PATH)) 3944 return (0); 3945 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3946 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3947 return (0);*/ 3948 /* XXX weak! */ 3949 for (i = 0; i < w->nconns; i++) { 3950 cw = hdac_widget_get(devinfo, w->conns[i]); 3951 if (cw == NULL) 3952 continue; 3953 if (++child > 1) { 3954 w->pflags |= HDA_ADC_RECSEL; 3955 return (1); 3956 } 3957 } 3958 for (i = 0; i < w->nconns; i++) { 3959 if (hdac_audio_ctl_recsel_build(devinfo, 3960 w->conns[i], depth + 1) != 0) 3961 return (1); 3962 } 3963 return (0); 3964} 3965 3966static int 3967hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3968{ 3969 struct hdac_widget *w, *cw; 3970 int i, j, conndev, found_dac = 0; 3971 int strategy; 3972 3973 strategy = devinfo->function.audio.parsing_strategy; 3974 3975 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3976 w = hdac_widget_get(devinfo, i); 3977 if (w == NULL || w->enable == 0) 3978 continue; 3979 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3980 continue; 3981 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3982 continue; 3983 conndev = w->wclass.pin.config & 3984 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3985 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3986 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3987 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3988 continue; 3989 for (j = 0; j < w->nconns; j++) { 3990 cw = hdac_widget_get(devinfo, w->conns[j]); 3991 if (cw == NULL || cw->enable == 0) 3992 continue; 3993 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3994 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3995 cw->type == 3996 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3997 continue; 3998 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3999 != 0) { 4000 if (w->selconn == -1) 4001 w->selconn = j; 4002 w->pflags |= HDA_DAC_PATH; 4003 found_dac++; 4004 } 4005 } 4006 } 4007 4008 return (found_dac); 4009} 4010 4011static void 4012hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4013{ 4014 struct hdac_widget *w; 4015 struct hdac_audio_ctl *ctl; 4016 int i, j, dacs, strategy; 4017 4018 /* Construct DAC path */ 4019 strategy = HDA_PARSE_MIXER; 4020 devinfo->function.audio.parsing_strategy = strategy; 4021 HDA_BOOTVERBOSE( 4022 device_printf(devinfo->codec->sc->dev, 4023 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4024 HDA_WIDGET_PARSER_REV); 4025 ); 4026 dacs = hdac_audio_build_tree_strategy(devinfo); 4027 if (dacs == 0) { 4028 HDA_BOOTVERBOSE( 4029 device_printf(devinfo->codec->sc->dev, 4030 "HDA_DEBUG: HWiP: 0 DAC path found! " 4031 "Retrying parser " 4032 "using HDA_PARSE_DIRECT strategy.\n"); 4033 ); 4034 strategy = HDA_PARSE_DIRECT; 4035 devinfo->function.audio.parsing_strategy = strategy; 4036 dacs = hdac_audio_build_tree_strategy(devinfo); 4037 } 4038 4039 HDA_BOOTVERBOSE( 4040 device_printf(devinfo->codec->sc->dev, 4041 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4042 "strategy.\n", 4043 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4044 ); 4045 4046 /* Construct ADC path */ 4047 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4048 w = hdac_widget_get(devinfo, i); 4049 if (w == NULL || w->enable == 0) 4050 continue; 4051 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4052 continue; 4053 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4054 } 4055 4056 /* Output mixers */ 4057 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4058 w = hdac_widget_get(devinfo, i); 4059 if (w == NULL || w->enable == 0) 4060 continue; 4061 if ((strategy == HDA_PARSE_MIXER && 4062 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4063 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4064 && (w->pflags & HDA_DAC_PATH)) || 4065 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4066 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4067 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4068 w->nid, devinfo->startnode - 1, 0, 0); 4069 } else if (w->type == 4070 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4071 j = 0; 4072 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4073 NULL) { 4074 if (ctl->enable == 0 || ctl->widget == NULL) 4075 continue; 4076 if (ctl->widget->nid != w->nid) 4077 continue; 4078 ctl->ossmask |= SOUND_MASK_VOLUME; 4079 ctl->ossmask |= SOUND_MASK_SPEAKER; 4080 ctl->ossdev = SOUND_MIXER_SPEAKER; 4081 w->ctlflags |= SOUND_MASK_VOLUME; 4082 w->ctlflags |= SOUND_MASK_SPEAKER; 4083 } 4084 } 4085 } 4086 4087 /* Input mixers (rec) */ 4088 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4089 w = hdac_widget_get(devinfo, i); 4090 if (w == NULL || w->enable == 0) 4091 continue; 4092 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4093 w->pflags & HDA_ADC_PATH)) 4094 continue; 4095 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4096 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4097 } 4098} 4099 4100#define HDA_COMMIT_CONN (1 << 0) 4101#define HDA_COMMIT_CTRL (1 << 1) 4102#define HDA_COMMIT_EAPD (1 << 2) 4103#define HDA_COMMIT_GPIO (1 << 3) 4104#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4105 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4106 4107static void 4108hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4109{ 4110 struct hdac_softc *sc = devinfo->codec->sc; 4111 struct hdac_widget *w; 4112 nid_t cad; 4113 int i; 4114 4115 if (!(cfl & HDA_COMMIT_ALL)) 4116 return; 4117 4118 cad = devinfo->codec->cad; 4119 4120 if (cfl & HDA_COMMIT_GPIO) { 4121 uint32_t gdata, gmask, gdir; 4122 int commitgpio = 0; 4123 4124 gdata = 0; 4125 gmask = 0; 4126 gdir = 0; 4127 4128 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4129 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4130 0x7e7, 0), cad); 4131 4132 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4133 commitgpio = 1; 4134 else { 4135 for (i = 0; i < HDA_GPIO_MAX; i++) { 4136 if (!(devinfo->function.audio.quirks & 4137 (1 << i))) 4138 continue; 4139 if (commitgpio == 0) { 4140 commitgpio = 1; 4141 gdata = hdac_command(sc, 4142 HDA_CMD_GET_GPIO_DATA(cad, 4143 devinfo->nid), cad); 4144 gmask = hdac_command(sc, 4145 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4146 devinfo->nid), cad); 4147 gdir = hdac_command(sc, 4148 HDA_CMD_GET_GPIO_DIRECTION(cad, 4149 devinfo->nid), cad); 4150 HDA_BOOTVERBOSE( 4151 device_printf(sc->dev, 4152 "GPIO init: data=0x%08x " 4153 "mask=0x%08x dir=0x%08x\n", 4154 gdata, gmask, gdir); 4155 ); 4156 } 4157 gdata |= 1 << i; 4158 gmask |= 1 << i; 4159 gdir |= 1 << i; 4160 } 4161 } 4162 4163 if (commitgpio != 0) { 4164 HDA_BOOTVERBOSE( 4165 device_printf(sc->dev, 4166 "GPIO commit: data=0x%08x mask=0x%08x " 4167 "dir=0x%08x\n", 4168 gdata, gmask, gdir); 4169 ); 4170 hdac_command(sc, 4171 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4172 gmask), cad); 4173 hdac_command(sc, 4174 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4175 gdir), cad); 4176 hdac_command(sc, 4177 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4178 gdata), cad); 4179 } 4180 } 4181 4182 for (i = 0; i < devinfo->nodecnt; i++) { 4183 w = &devinfo->widget[i]; 4184 if (w == NULL || w->enable == 0) 4185 continue; 4186 if (cfl & HDA_COMMIT_CONN) { 4187 if (w->selconn == -1) 4188 w->selconn = 0; 4189 if (w->nconns > 0) 4190 hdac_widget_connection_select(w, w->selconn); 4191 } 4192 if ((cfl & HDA_COMMIT_CTRL) && 4193 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4194 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4195 (HDA_DAC_PATH | HDA_ADC_PATH)) 4196 device_printf(sc->dev, "WARNING: node %d " 4197 "participate both for DAC/ADC!\n", w->nid); 4198 if (w->pflags & HDA_DAC_PATH) { 4199 w->wclass.pin.ctrl &= 4200 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4201 if ((w->wclass.pin.config & 4202 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4203 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4204 w->wclass.pin.ctrl &= 4205 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4206 } else if (w->pflags & HDA_ADC_PATH) { 4207 w->wclass.pin.ctrl &= 4208 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4209 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4210 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4211 uint32_t pincap = w->wclass.pin.cap; 4212 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4213 w->wclass.pin.ctrl |= 4214 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4215 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4216 ); 4217 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4218 w->wclass.pin.ctrl |= 4219 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4220 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4221 ); 4222 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4223 w->wclass.pin.ctrl |= 4224 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4225 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4226 ); 4227 } 4228 } else 4229 w->wclass.pin.ctrl &= ~( 4230 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4231 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4232 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4233 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4234 hdac_command(sc, 4235 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4236 w->wclass.pin.ctrl), cad); 4237 } 4238 if ((cfl & HDA_COMMIT_EAPD) && 4239 w->param.eapdbtl != HDAC_INVALID) { 4240 uint32_t val; 4241 4242 val = w->param.eapdbtl; 4243 if (devinfo->function.audio.quirks & 4244 HDA_QUIRK_EAPDINV) 4245 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4246 hdac_command(sc, 4247 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4248 val), cad); 4249 4250 } 4251 DELAY(1000); 4252 } 4253} 4254 4255static void 4256hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4257{ 4258 struct hdac_softc *sc = devinfo->codec->sc; 4259 struct hdac_audio_ctl *ctl; 4260 int i; 4261 4262 devinfo->function.audio.mvol = 100 | (100 << 8); 4263 i = 0; 4264 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4265 if (ctl->enable == 0 || ctl->widget == NULL) { 4266 HDA_BOOTVERBOSE( 4267 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4268 i, (ctl->widget != NULL) ? 4269 ctl->widget->nid : -1); 4270 if (ctl->childwidget != NULL) 4271 printf(" childnid=%d", 4272 ctl->childwidget->nid); 4273 if (ctl->widget == NULL) 4274 printf(" NULL WIDGET!"); 4275 printf(" DISABLED\n"); 4276 ); 4277 continue; 4278 } 4279 HDA_BOOTVERBOSE( 4280 if (ctl->ossmask == 0) { 4281 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4282 i, ctl->widget->nid); 4283 if (ctl->childwidget != NULL) 4284 printf(" childnid=%d", 4285 ctl->childwidget->nid); 4286 printf(" Bind to NONE\n"); 4287 } 4288 ); 4289 if (ctl->step > 0) { 4290 ctl->ossval = (ctl->left * 100) / ctl->step; 4291 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4292 } else 4293 ctl->ossval = 0; 4294 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4295 ctl->left, ctl->right); 4296 } 4297} 4298 4299static int 4300hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4301{ 4302 struct hdac_chan *ch; 4303 struct hdac_widget *w; 4304 uint32_t cap, fmtcap, pcmcap, path; 4305 int i, type, ret, max; 4306 4307 if (dir == PCMDIR_PLAY) { 4308 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4309 ch = &devinfo->codec->sc->play; 4310 path = HDA_DAC_PATH; 4311 } else { 4312 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4313 ch = &devinfo->codec->sc->rec; 4314 path = HDA_ADC_PATH; 4315 } 4316 4317 ch->caps = hdac_caps; 4318 ch->caps.fmtlist = ch->fmtlist; 4319 ch->bit16 = 1; 4320 ch->bit32 = 0; 4321 ch->pcmrates[0] = 48000; 4322 ch->pcmrates[1] = 0; 4323 4324 ret = 0; 4325 fmtcap = devinfo->function.audio.supp_stream_formats; 4326 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4327 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4328 4329 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4330 w = hdac_widget_get(devinfo, i); 4331 if (w == NULL || w->enable == 0 || w->type != type || 4332 !(w->pflags & path)) 4333 continue; 4334 cap = w->param.widget_cap; 4335 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4336 continue;*/ 4337 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4338 continue; 4339 cap = w->param.supp_stream_formats; 4340 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4341 } 4342 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4343 }*/ 4344 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4345 continue; 4346 if (ret == 0) { 4347 fmtcap = w->param.supp_stream_formats; 4348 pcmcap = w->param.supp_pcm_size_rate; 4349 } else { 4350 fmtcap &= w->param.supp_stream_formats; 4351 pcmcap &= w->param.supp_pcm_size_rate; 4352 } 4353 ch->io[ret++] = i; 4354 } 4355 ch->io[ret] = -1; 4356 4357 ch->supp_stream_formats = fmtcap; 4358 ch->supp_pcm_size_rate = pcmcap; 4359 4360 /* 4361 * 8bit = 0 4362 * 16bit = 1 4363 * 20bit = 2 4364 * 24bit = 3 4365 * 32bit = 4 4366 */ 4367 if (ret > 0) { 4368 cap = pcmcap; 4369 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4370 ch->bit16 = 1; 4371 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4372 ch->bit16 = 0; 4373 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4374 ch->bit32 = 4; 4375 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4376 ch->bit32 = 3; 4377 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4378 ch->bit32 = 2; 4379 i = 0; 4380 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4381 ch->fmtlist[i++] = AFMT_S16_LE; 4382 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4383 if (ch->bit32 > 0) { 4384 if (!(devinfo->function.audio.quirks & 4385 HDA_QUIRK_FORCESTEREO)) 4386 ch->fmtlist[i++] = AFMT_S32_LE; 4387 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4388 } 4389 ch->fmtlist[i] = 0; 4390 i = 0; 4391 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4392 ch->pcmrates[i++] = 8000; 4393 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4394 ch->pcmrates[i++] = 11025; 4395 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4396 ch->pcmrates[i++] = 16000; 4397 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4398 ch->pcmrates[i++] = 22050; 4399 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4400 ch->pcmrates[i++] = 32000; 4401 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4402 ch->pcmrates[i++] = 44100; 4403 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4404 ch->pcmrates[i++] = 48000; 4405 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4406 ch->pcmrates[i++] = 88200; 4407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4408 ch->pcmrates[i++] = 96000; 4409 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4410 ch->pcmrates[i++] = 176400; 4411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4412 ch->pcmrates[i++] = 192000; 4413 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4414 ch->pcmrates[i] = 0; 4415 if (i > 0) { 4416 ch->caps.minspeed = ch->pcmrates[0]; 4417 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4418 } 4419 } 4420 4421 return (ret); 4422} 4423 4424static void 4425hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4426{ 4427 struct hdac_audio_ctl *ctl; 4428 struct hdac_softc *sc = devinfo->codec->sc; 4429 int i; 4430 uint32_t fl = 0; 4431 4432 4433 if (flag == 0) { 4434 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4435 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4436 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4437 } 4438 4439 i = 0; 4440 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4441 if (ctl->enable == 0 || ctl->widget == NULL || 4442 ctl->widget->enable == 0) 4443 continue; 4444 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4445 (flag != 0 && (ctl->ossmask & flag))) { 4446 if (banner != NULL) { 4447 device_printf(sc->dev, "\n"); 4448 device_printf(sc->dev, "%s\n", banner); 4449 } 4450 goto hdac_ctl_dump_it_all; 4451 } 4452 } 4453 4454 return; 4455 4456hdac_ctl_dump_it_all: 4457 i = 0; 4458 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4459 if (ctl->enable == 0 || ctl->widget == NULL || 4460 ctl->widget->enable == 0) 4461 continue; 4462 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4463 (flag != 0 && (ctl->ossmask & flag)))) 4464 continue; 4465 if (flag == 0) { 4466 device_printf(sc->dev, "\n"); 4467 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4468 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4469 } 4470 device_printf(sc->dev, " |\n"); 4471 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4472 ctl->widget->nid, ctl->index); 4473 if (ctl->childwidget != NULL) 4474 printf("(nid: %2d) ", ctl->childwidget->nid); 4475 else 4476 printf(" "); 4477 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4478 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4479 ctl->ossmask); 4480 } 4481} 4482 4483static void 4484hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4485{ 4486 uint32_t cap; 4487 4488 cap = fcap; 4489 if (cap != 0) { 4490 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4491 device_printf(sc->dev, " Format:"); 4492 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4493 printf(" AC3"); 4494 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4495 printf(" FLOAT32"); 4496 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4497 printf(" PCM"); 4498 printf("\n"); 4499 } 4500 cap = pcmcap; 4501 if (cap != 0) { 4502 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4503 device_printf(sc->dev, " PCM size:"); 4504 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4505 printf(" 8"); 4506 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4507 printf(" 16"); 4508 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4509 printf(" 20"); 4510 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4511 printf(" 24"); 4512 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4513 printf(" 32"); 4514 printf("\n"); 4515 device_printf(sc->dev, " PCM rate:"); 4516 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4517 printf(" 8"); 4518 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4519 printf(" 11"); 4520 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4521 printf(" 16"); 4522 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4523 printf(" 22"); 4524 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4525 printf(" 32"); 4526 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4527 printf(" 44"); 4528 printf(" 48"); 4529 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4530 printf(" 88"); 4531 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4532 printf(" 96"); 4533 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4534 printf(" 176"); 4535 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4536 printf(" 192"); 4537 printf("\n"); 4538 } 4539} 4540 4541static void 4542hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4543{ 4544 uint32_t pincap, wcap; 4545 4546 pincap = w->wclass.pin.cap; 4547 wcap = w->param.widget_cap; 4548 4549 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4550 device_printf(sc->dev, " "); 4551 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4552 printf(" ISC"); 4553 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4554 printf(" TRQD"); 4555 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4556 printf(" PDC"); 4557 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4558 printf(" HP"); 4559 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4560 printf(" OUT"); 4561 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4562 printf(" IN"); 4563 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4564 printf(" BAL"); 4565 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4566 printf(" VREF["); 4567 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4568 printf(" 50"); 4569 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4570 printf(" 80"); 4571 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4572 printf(" 100"); 4573 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4574 printf(" GROUND"); 4575 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4576 printf(" HIZ"); 4577 printf(" ]"); 4578 } 4579 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4580 printf(" EAPD"); 4581 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4582 printf(" : UNSOL"); 4583 printf("\n"); 4584 device_printf(sc->dev, " Pin config: 0x%08x\n", 4585 w->wclass.pin.config); 4586 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4587 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4588 printf(" HP"); 4589 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4590 printf(" IN"); 4591 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4592 printf(" OUT"); 4593 printf("\n"); 4594} 4595 4596static void 4597hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4598{ 4599 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4600 device_printf(sc->dev, " " 4601 "mute=%d step=%d size=%d offset=%d\n", 4602 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4603 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4604 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4605 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4606} 4607 4608static void 4609hdac_dump_nodes(struct hdac_devinfo *devinfo) 4610{ 4611 struct hdac_softc *sc = devinfo->codec->sc; 4612 struct hdac_widget *w, *cw; 4613 int i, j; 4614 4615 device_printf(sc->dev, "\n"); 4616 device_printf(sc->dev, "Default Parameter\n"); 4617 device_printf(sc->dev, "-----------------\n"); 4618 hdac_dump_audio_formats(sc, 4619 devinfo->function.audio.supp_stream_formats, 4620 devinfo->function.audio.supp_pcm_size_rate); 4621 device_printf(sc->dev, " IN amp: 0x%08x\n", 4622 devinfo->function.audio.inamp_cap); 4623 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4624 devinfo->function.audio.outamp_cap); 4625 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4626 w = hdac_widget_get(devinfo, i); 4627 if (w == NULL) { 4628 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4629 continue; 4630 } 4631 device_printf(sc->dev, "\n"); 4632 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4633 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4634 "DIGITAL" : "ANALOG", 4635 (w->enable == 0) ? " [DISABLED]" : ""); 4636 device_printf(sc->dev, " name: %s\n", w->name); 4637 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4638 w->param.widget_cap); 4639 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4640 w->pflags); 4641 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4642 w->ctlflags); 4643 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4644 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4645 hdac_dump_audio_formats(sc, 4646 w->param.supp_stream_formats, 4647 w->param.supp_pcm_size_rate); 4648 } else if (w->type == 4649 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4650 hdac_dump_pin(sc, w); 4651 if (w->param.eapdbtl != HDAC_INVALID) 4652 device_printf(sc->dev, " EAPD: 0x%08x\n", 4653 w->param.eapdbtl); 4654 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4655 w->param.outamp_cap != 0) 4656 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4657 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4658 w->param.inamp_cap != 0) 4659 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4660 device_printf(sc->dev, " connections: %d\n", w->nconns); 4661 for (j = 0; j < w->nconns; j++) { 4662 cw = hdac_widget_get(devinfo, w->conns[j]); 4663 device_printf(sc->dev, " |\n"); 4664 device_printf(sc->dev, " + <- nid=%d [%s]", 4665 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4666 if (cw == NULL) 4667 printf(" [UNKNOWN]"); 4668 else if (cw->enable == 0) 4669 printf(" [DISABLED]"); 4670 if (w->nconns > 1 && w->selconn == j && w->type != 4671 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4672 printf(" (selected)"); 4673 printf("\n"); 4674 } 4675 } 4676 4677} 4678 4679static int 4680hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4681{ 4682 struct hdac_widget *w, *cw; 4683 struct hdac_softc *sc = devinfo->codec->sc; 4684 int i; 4685 4686 if (depth > HDA_PARSE_MAXDEPTH) 4687 return (0); 4688 4689 w = hdac_widget_get(devinfo, nid); 4690 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4691 return (0); 4692 4693 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4694 device_printf(sc->dev, "\n"); 4695 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4696 device_printf(sc->dev, " ^\n"); 4697 device_printf(sc->dev, " |\n"); 4698 device_printf(sc->dev, " +-----<------+\n"); 4699 } else { 4700 device_printf(sc->dev, " ^\n"); 4701 device_printf(sc->dev, " |\n"); 4702 device_printf(sc->dev, " "); 4703 printf(" nid=%d [%s]\n", w->nid, w->name); 4704 } 4705 4706 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4707 return (1); 4708 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4709 for (i = 0; i < w->nconns; i++) { 4710 cw = hdac_widget_get(devinfo, w->conns[i]); 4711 if (cw == NULL || cw->enable == 0 || cw->type == 4712 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4713 continue; 4714 if (hdac_dump_dac_internal(devinfo, cw->nid, 4715 depth + 1) != 0) 4716 return (1); 4717 } 4718 } else if ((w->type == 4719 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4720 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4721 w->selconn > -1 && w->selconn < w->nconns) { 4722 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4723 depth + 1) != 0) 4724 return (1); 4725 } 4726 4727 return (0); 4728} 4729 4730static void 4731hdac_dump_dac(struct hdac_devinfo *devinfo) 4732{ 4733 struct hdac_widget *w; 4734 struct hdac_softc *sc = devinfo->codec->sc; 4735 int i, printed = 0; 4736 4737 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4738 w = hdac_widget_get(devinfo, i); 4739 if (w == NULL || w->enable == 0) 4740 continue; 4741 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4742 !(w->pflags & HDA_DAC_PATH)) 4743 continue; 4744 if (printed == 0) { 4745 printed = 1; 4746 device_printf(sc->dev, "\n"); 4747 device_printf(sc->dev, "Playback path:\n"); 4748 } 4749 hdac_dump_dac_internal(devinfo, w->nid, 0); 4750 } 4751} 4752 4753static void 4754hdac_dump_adc(struct hdac_devinfo *devinfo) 4755{ 4756 struct hdac_widget *w, *cw; 4757 struct hdac_softc *sc = devinfo->codec->sc; 4758 int i, j; 4759 int printed = 0; 4760 char ossdevs[256]; 4761 4762 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4763 w = hdac_widget_get(devinfo, i); 4764 if (w == NULL || w->enable == 0) 4765 continue; 4766 if (!(w->pflags & HDA_ADC_RECSEL)) 4767 continue; 4768 if (printed == 0) { 4769 printed = 1; 4770 device_printf(sc->dev, "\n"); 4771 device_printf(sc->dev, "Recording sources:\n"); 4772 } 4773 device_printf(sc->dev, "\n"); 4774 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4775 for (j = 0; j < w->nconns; j++) { 4776 cw = hdac_widget_get(devinfo, w->conns[j]); 4777 if (cw == NULL || cw->enable == 0) 4778 continue; 4779 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4780 ossdevs, sizeof(ossdevs)); 4781 device_printf(sc->dev, " |\n"); 4782 device_printf(sc->dev, " + <- nid=%d [%s]", 4783 cw->nid, cw->name); 4784 if (strlen(ossdevs) > 0) { 4785 printf(" [recsrc: %s]", ossdevs); 4786 } 4787 printf("\n"); 4788 } 4789 } 4790} 4791 4792static void 4793hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4794{ 4795 nid_t *nids; 4796 4797 if (pcnt > 0) { 4798 device_printf(sc->dev, "\n"); 4799 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4800 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4801 sc->play.supp_pcm_size_rate); 4802 device_printf(sc->dev, " DAC:"); 4803 for (nids = sc->play.io; *nids != -1; nids++) 4804 printf(" %d", *nids); 4805 printf("\n"); 4806 } 4807 4808 if (rcnt > 0) { 4809 device_printf(sc->dev, "\n"); 4810 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4811 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4812 sc->rec.supp_pcm_size_rate); 4813 device_printf(sc->dev, " ADC:"); 4814 for (nids = sc->rec.io; *nids != -1; nids++) 4815 printf(" %d", *nids); 4816 printf("\n"); 4817 } 4818} 4819 4820static void 4821hdac_release_resources(struct hdac_softc *sc) 4822{ 4823 struct hdac_devinfo *devinfo = NULL; 4824 device_t *devlist = NULL; 4825 int i, devcount; 4826 4827 if (sc == NULL) 4828 return; 4829 4830 hdac_lock(sc); 4831 if (sc->polling != 0) 4832 callout_stop(&sc->poll_hdac); 4833 hdac_reset(sc); 4834 hdac_unlock(sc); 4835 snd_mtxfree(sc->lock); 4836 4837 device_get_children(sc->dev, &devlist, &devcount); 4838 for (i = 0; devlist != NULL && i < devcount; i++) { 4839 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4840 if (devinfo == NULL) 4841 continue; 4842 if (devinfo->widget != NULL) 4843 free(devinfo->widget, M_HDAC); 4844 if (devinfo->node_type == 4845 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4846 devinfo->function.audio.ctl != NULL) 4847 free(devinfo->function.audio.ctl, M_HDAC); 4848 free(devinfo, M_HDAC); 4849 device_delete_child(sc->dev, devlist[i]); 4850 } 4851 if (devlist != NULL) 4852 free(devlist, M_TEMP); 4853 4854 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4855 if (sc->codecs[i] != NULL) 4856 free(sc->codecs[i], M_HDAC); 4857 sc->codecs[i] = NULL; 4858 } 4859 4860 hdac_dma_free(&sc->rirb_dma); 4861 hdac_dma_free(&sc->corb_dma); 4862 if (sc->play.blkcnt > 0) 4863 hdac_dma_free(&sc->play.bdl_dma); 4864 if (sc->rec.blkcnt > 0) 4865 hdac_dma_free(&sc->rec.bdl_dma); 4866 hdac_irq_free(sc); 4867 hdac_mem_free(sc); 4868 free(sc, M_DEVBUF); 4869 4870} 4871 4872/* This function surely going to make its way into upper level someday. */ 4873static void 4874hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4875{ 4876 const char *res = NULL; 4877 int i = 0, j, k, len, inv; 4878 4879 if (on != NULL) 4880 *on = 0; 4881 if (off != NULL) 4882 *off = 0; 4883 if (sc == NULL) 4884 return; 4885 if (resource_string_value(device_get_name(sc->dev), 4886 device_get_unit(sc->dev), "config", &res) != 0) 4887 return; 4888 if (!(res != NULL && strlen(res) > 0)) 4889 return; 4890 HDA_BOOTVERBOSE( 4891 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4892 ); 4893 for (;;) { 4894 while (res[i] != '\0' && 4895 (res[i] == ',' || isspace(res[i]) != 0)) 4896 i++; 4897 if (res[i] == '\0') { 4898 HDA_BOOTVERBOSE( 4899 printf("\n"); 4900 ); 4901 return; 4902 } 4903 j = i; 4904 while (res[j] != '\0' && 4905 !(res[j] == ',' || isspace(res[j]) != 0)) 4906 j++; 4907 len = j - i; 4908 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4909 inv = 2; 4910 else 4911 inv = 0; 4912 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4913 if (strncmp(res + i + inv, 4914 hdac_quirks_tab[k].key, len - inv) != 0) 4915 continue; 4916 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4917 break; 4918 HDA_BOOTVERBOSE( 4919 printf(" %s%s", (inv != 0) ? "no" : "", 4920 hdac_quirks_tab[k].key); 4921 ); 4922 if (inv == 0 && on != NULL) 4923 *on |= hdac_quirks_tab[k].value; 4924 else if (inv != 0 && off != NULL) 4925 *off |= hdac_quirks_tab[k].value; 4926 break; 4927 } 4928 i = j; 4929 } 4930} 4931 4932#ifdef SND_DYNSYSCTL 4933static int 4934sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4935{ 4936 struct hdac_softc *sc; 4937 struct hdac_devinfo *devinfo; 4938 device_t dev; 4939 uint32_t ctl; 4940 int err, val; 4941 4942 dev = oidp->oid_arg1; 4943 devinfo = pcm_getdevinfo(dev); 4944 if (devinfo == NULL || devinfo->codec == NULL || 4945 devinfo->codec->sc == NULL) 4946 return (EINVAL); 4947 sc = devinfo->codec->sc; 4948 hdac_lock(sc); 4949 val = sc->polling; 4950 hdac_unlock(sc); 4951 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4952 4953 if (err || req->newptr == NULL) 4954 return (err); 4955 if (val < 0 || val > 1) 4956 return (EINVAL); 4957 4958 hdac_lock(sc); 4959 if (val != sc->polling) { 4960 if (hda_chan_active(sc) != 0) 4961 err = EBUSY; 4962 else if (val == 0) { 4963 callout_stop(&sc->poll_hdac); 4964 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 4965 sc->rirb_size / 2); 4966 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4967 ctl |= HDAC_RIRBCTL_RINTCTL; 4968 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4969 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4970 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4971 sc->polling = 0; 4972 DELAY(1000); 4973 } else { 4974 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 4975 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 4976 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4977 ctl &= ~HDAC_RIRBCTL_RINTCTL; 4978 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4979 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 4980 sc); 4981 sc->polling = 1; 4982 DELAY(1000); 4983 } 4984 } 4985 hdac_unlock(sc); 4986 4987 return (err); 4988} 4989#endif 4990 4991static void 4992hdac_attach2(void *arg) 4993{ 4994 struct hdac_softc *sc; 4995 struct hdac_widget *w; 4996 struct hdac_audio_ctl *ctl; 4997 uint32_t quirks_on, quirks_off; 4998 int pcnt, rcnt; 4999 int i; 5000 char status[SND_STATUSLEN]; 5001 device_t *devlist = NULL; 5002 int devcount; 5003 struct hdac_devinfo *devinfo = NULL; 5004 5005 sc = (struct hdac_softc *)arg; 5006 5007 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5008 5009 HDA_BOOTVERBOSE( 5010 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5011 quirks_on, quirks_off); 5012 ); 5013 5014 hdac_lock(sc); 5015 5016 /* Remove ourselves from the config hooks */ 5017 if (sc->intrhook.ich_func != NULL) { 5018 config_intrhook_disestablish(&sc->intrhook); 5019 sc->intrhook.ich_func = NULL; 5020 } 5021 5022 /* Start the corb and rirb engines */ 5023 HDA_BOOTVERBOSE( 5024 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5025 ); 5026 hdac_corb_start(sc); 5027 HDA_BOOTVERBOSE( 5028 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5029 ); 5030 hdac_rirb_start(sc); 5031 5032 HDA_BOOTVERBOSE( 5033 device_printf(sc->dev, 5034 "HDA_DEBUG: Enabling controller interrupt...\n"); 5035 ); 5036 if (sc->polling == 0) 5037 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5038 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5039 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5040 HDAC_GCTL_UNSOL); 5041 5042 DELAY(1000); 5043 5044 HDA_BOOTVERBOSE( 5045 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5046 ); 5047 hdac_scan_codecs(sc); 5048 5049 device_get_children(sc->dev, &devlist, &devcount); 5050 for (i = 0; devlist != NULL && i < devcount; i++) { 5051 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5052 if (devinfo != NULL && devinfo->node_type == 5053 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5054 break; 5055 } else 5056 devinfo = NULL; 5057 } 5058 if (devlist != NULL) 5059 free(devlist, M_TEMP); 5060 5061 if (devinfo == NULL) { 5062 hdac_unlock(sc); 5063 device_printf(sc->dev, "Audio Function Group not found!\n"); 5064 hdac_release_resources(sc); 5065 return; 5066 } 5067 5068 HDA_BOOTVERBOSE( 5069 device_printf(sc->dev, 5070 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5071 devinfo->nid, devinfo->codec->cad); 5072 ); 5073 hdac_audio_parse(devinfo); 5074 HDA_BOOTVERBOSE( 5075 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5076 ); 5077 hdac_audio_ctl_parse(devinfo); 5078 HDA_BOOTVERBOSE( 5079 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5080 ); 5081 hdac_vendor_patch_parse(devinfo); 5082 if (quirks_on != 0) 5083 devinfo->function.audio.quirks |= quirks_on; 5084 if (quirks_off != 0) 5085 devinfo->function.audio.quirks &= ~quirks_off; 5086 5087 /* XXX Disable all DIGITAL path. */ 5088 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5089 w = hdac_widget_get(devinfo, i); 5090 if (w == NULL) 5091 continue; 5092 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5093 w->enable = 0; 5094 continue; 5095 } 5096 /* XXX Disable useless pin ? */ 5097 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5098 (w->wclass.pin.config & 5099 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5100 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5101 w->enable = 0; 5102 } 5103 i = 0; 5104 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5105 if (ctl->widget == NULL) 5106 continue; 5107 w = ctl->widget; 5108 if (w->enable == 0) 5109 ctl->enable = 0; 5110 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5111 ctl->enable = 0; 5112 w = ctl->childwidget; 5113 if (w == NULL) 5114 continue; 5115 if (w->enable == 0 || 5116 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5117 ctl->enable = 0; 5118 } 5119 5120 HDA_BOOTVERBOSE( 5121 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5122 ); 5123 hdac_audio_build_tree(devinfo); 5124 5125 HDA_BOOTVERBOSE( 5126 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5127 ); 5128 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5129 HDA_BOOTVERBOSE( 5130 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5131 ); 5132 hdac_audio_ctl_commit(devinfo); 5133 5134 HDA_BOOTVERBOSE( 5135 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5136 ); 5137 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5138 HDA_BOOTVERBOSE( 5139 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5140 ); 5141 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5142 5143 hdac_unlock(sc); 5144 HDA_BOOTVERBOSE( 5145 device_printf(sc->dev, 5146 "HDA_DEBUG: OSS mixer initialization...\n"); 5147 ); 5148 5149 /* 5150 * There is no point of return after this. If the driver failed, 5151 * so be it. Let the detach procedure do all the cleanup. 5152 */ 5153 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5154 device_printf(sc->dev, "Can't register mixer\n"); 5155 5156 if (pcnt > 0) 5157 pcnt = 1; 5158 if (rcnt > 0) 5159 rcnt = 1; 5160 5161 HDA_BOOTVERBOSE( 5162 device_printf(sc->dev, 5163 "HDA_DEBUG: Registering PCM channels...\n"); 5164 ); 5165 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5166 device_printf(sc->dev, "Can't register PCM\n"); 5167 5168 sc->registered++; 5169 5170 for (i = 0; i < pcnt; i++) 5171 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5172 for (i = 0; i < rcnt; i++) 5173 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5174 5175#ifdef SND_DYNSYSCTL 5176 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5177 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5178 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5179 sysctl_hdac_polling, "I", "Enable polling mode"); 5180#endif 5181 5182 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5183 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5184 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5185 pcm_setstatus(sc->dev, status); 5186 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5187 HDA_BOOTVERBOSE( 5188 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5189 hdac_codec_id(devinfo)); 5190 ); 5191 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5192 HDA_DRV_TEST_REV); 5193 5194 HDA_BOOTVERBOSE( 5195 if (devinfo->function.audio.quirks != 0) { 5196 device_printf(sc->dev, "\n"); 5197 device_printf(sc->dev, "HDA config/quirks:"); 5198 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5199 if (devinfo->function.audio.quirks & 5200 hdac_quirks_tab[i].value) 5201 printf(" %s", hdac_quirks_tab[i].key); 5202 } 5203 printf("\n"); 5204 } 5205 device_printf(sc->dev, "\n"); 5206 device_printf(sc->dev, "+-------------------+\n"); 5207 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5208 device_printf(sc->dev, "+-------------------+\n"); 5209 hdac_dump_nodes(devinfo); 5210 device_printf(sc->dev, "\n"); 5211 device_printf(sc->dev, "+------------------------+\n"); 5212 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5213 device_printf(sc->dev, "+------------------------+\n"); 5214 device_printf(sc->dev, "\n"); 5215 i = 0; 5216 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5217 device_printf(sc->dev, "%3d: nid=%d", i, 5218 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5219 if (ctl->childwidget != NULL) 5220 printf(" cnid=%d", ctl->childwidget->nid); 5221 printf(" dir=0x%x index=%d " 5222 "ossmask=0x%08x ossdev=%d%s\n", 5223 ctl->dir, ctl->index, 5224 ctl->ossmask, ctl->ossdev, 5225 (ctl->enable == 0) ? " [DISABLED]" : ""); 5226 } 5227 device_printf(sc->dev, "\n"); 5228 device_printf(sc->dev, "+-----------------------------------+\n"); 5229 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5230 device_printf(sc->dev, "+-----------------------------------+\n"); 5231 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5232 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5233 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5234 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5235 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5236 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5237 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5238 hdac_dump_ctls(devinfo, NULL, 0); 5239 hdac_dump_dac(devinfo); 5240 hdac_dump_adc(devinfo); 5241 device_printf(sc->dev, "\n"); 5242 device_printf(sc->dev, "+--------------------------------------+\n"); 5243 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5244 device_printf(sc->dev, "+--------------------------------------+\n"); 5245 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5246 ); 5247 5248 if (sc->polling != 0) { 5249 hdac_lock(sc); 5250 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5251 hdac_unlock(sc); 5252 } 5253} 5254 5255/**************************************************************************** 5256 * int hdac_detach(device_t) 5257 * 5258 * Detach and free up resources utilized by the hdac device. 5259 ****************************************************************************/ 5260static int 5261hdac_detach(device_t dev) 5262{ 5263 struct hdac_softc *sc = NULL; 5264 struct hdac_devinfo *devinfo = NULL; 5265 int err; 5266 5267 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5268 if (devinfo != NULL && devinfo->codec != NULL) 5269 sc = devinfo->codec->sc; 5270 if (sc == NULL) 5271 return (0); 5272 5273 if (sc->registered > 0) { 5274 err = pcm_unregister(dev); 5275 if (err != 0) 5276 return (err); 5277 } 5278 5279 hdac_release_resources(sc); 5280 5281 return (0); 5282} 5283 5284static device_method_t hdac_methods[] = { 5285 /* device interface */ 5286 DEVMETHOD(device_probe, hdac_probe), 5287 DEVMETHOD(device_attach, hdac_attach), 5288 DEVMETHOD(device_detach, hdac_detach), 5289 { 0, 0 } 5290}; 5291 5292static driver_t hdac_driver = { 5293 "pcm", 5294 hdac_methods, 5295 PCM_SOFTC_SIZE, 5296}; 5297 5298DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5299MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5300MODULE_VERSION(snd_hda, 1); 5301