hdac.c revision 165039
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061210_0036" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 165039 2006-12-09 17:52:54Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 193#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 194 195/* IBM / Lenovo */ 196#define IBM_VENDORID 0x1014 197#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 198#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 199 200/* Lenovo */ 201#define LENOVO_VENDORID 0x17aa 202#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 203#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 204 205/* Samsung */ 206#define SAMSUNG_VENDORID 0x144d 207#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 208#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 209 210/* Medion ? */ 211#define MEDION_VENDORID 0x161f 212#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 213#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 214 215/* 216 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 217 * instead of their own, which is beyond my comprehension 218 * (see HDA_CODEC_STAC9221 below). 219 */ 220#define APPLE_INTEL_MAC 0x76808384 221 222/* Misc constants.. */ 223#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 224#define HDA_AMP_MUTE_NONE (0) 225#define HDA_AMP_MUTE_LEFT (1 << 0) 226#define HDA_AMP_MUTE_RIGHT (1 << 1) 227#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 228 229#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 230#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 231 232#define HDA_DAC_PATH (1 << 0) 233#define HDA_ADC_PATH (1 << 1) 234#define HDA_ADC_RECSEL (1 << 2) 235 236#define HDA_CTL_OUT (1 << 0) 237#define HDA_CTL_IN (1 << 1) 238#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 239 240#define HDA_GPIO_MAX 15 241/* 0 - 14 = GPIO */ 242#define HDA_QUIRK_GPIO0 (1 << 0) 243#define HDA_QUIRK_GPIO1 (1 << 1) 244#define HDA_QUIRK_GPIO2 (1 << 2) 245#define HDA_QUIRK_GPIOFLUSH (1 << 15) 246#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 247#define HDA_QUIRK_FIXEDRATE (1 << 17) 248#define HDA_QUIRK_FORCESTEREO (1 << 18) 249#define HDA_QUIRK_EAPDINV (1 << 19) 250 251static const struct { 252 char *key; 253 uint32_t value; 254} hdac_quirks_tab[] = { 255 { "gpio0", HDA_QUIRK_GPIO0 }, 256 { "gpio1", HDA_QUIRK_GPIO1 }, 257 { "gpio2", HDA_QUIRK_GPIO2 }, 258 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 259 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 260 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 261 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 262 { "eapdinv", HDA_QUIRK_EAPDINV }, 263}; 264#define HDAC_QUIRKS_TAB_LEN \ 265 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 266 267#define HDA_BDL_MIN 2 268#define HDA_BDL_MAX 256 269#define HDA_BDL_DEFAULT HDA_BDL_MIN 270 271#define HDA_BUFSZ_MIN 4096 272#define HDA_BUFSZ_MAX 65536 273#define HDA_BUFSZ_DEFAULT 16384 274 275#define HDA_PARSE_MAXDEPTH 10 276 277#define HDAC_UNSOLTAG_EVENT_HP 0x00 278 279static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 280 281enum { 282 HDA_PARSE_MIXER, 283 HDA_PARSE_DIRECT 284}; 285 286/* Default */ 287static uint32_t hdac_fmt[] = { 288 AFMT_STEREO | AFMT_S16_LE, 289 0 290}; 291 292static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 293 294static const struct { 295 uint32_t model; 296 char *desc; 297} hdac_devices[] = { 298 { HDA_INTEL_82801F, "Intel 82801F" }, 299 { HDA_INTEL_82801G, "Intel 82801G" }, 300 { HDA_INTEL_82801H, "Intel 82801H" }, 301 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 302 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 303 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 304 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 305 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 306 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 307 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 308 { HDA_ATI_SB450, "ATI SB450" }, 309 { HDA_ATI_SB600, "ATI SB600" }, 310 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 311 { HDA_SIS_966, "SiS 966" }, 312 /* Unknown */ 313 { HDA_INTEL_ALL, "Intel (Unknown)" }, 314 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 315 { HDA_ATI_ALL, "ATI (Unknown)" }, 316 { HDA_VIA_ALL, "VIA (Unknown)" }, 317 { HDA_SIS_ALL, "SiS (Unknown)" }, 318}; 319#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 320 321static const struct { 322 uint32_t rate; 323 int valid; 324 uint16_t base; 325 uint16_t mul; 326 uint16_t div; 327} hda_rate_tab[] = { 328 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 329 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 330 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 331 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 332 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 333 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 334 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 335 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 336 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 337 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 338 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 339 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 340 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 341 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 342 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 343 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 344 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 345 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 346 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 347 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 348 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 349 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 350 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 351 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 352 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 353 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 354 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 355 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 356 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 357 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 358 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 359 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 360 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 361 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 362 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 363}; 364#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 365 366/* All codecs you can eat... */ 367#define HDA_CODEC_CONSTRUCT(vendor, id) \ 368 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 369 370/* Realtek */ 371#define REALTEK_VENDORID 0x10ec 372#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 373#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 374#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 375#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 376#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 377#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 378 379/* Analog Device */ 380#define ANALOGDEVICE_VENDORID 0x11d4 381#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 382#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 383#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 384#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 385 386/* CMedia */ 387#define CMEDIA_VENDORID 0x434d 388#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 389#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 390 391/* Sigmatel */ 392#define SIGMATEL_VENDORID 0x8384 393#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 394#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 395#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 396#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 397#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 398 399/* 400 * Conexant 401 * 402 * Ok, the truth is, I don't have any idea at all whether 403 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 404 * place that tell me it is "Venice" is from its Windows driver INF. 405 * 406 * Venice - CX????? 407 * Waikiki - CX20551-22 408 */ 409#define CONEXANT_VENDORID 0x14f1 410#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 411#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 412#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 413 414 415/* Codecs */ 416static const struct { 417 uint32_t id; 418 char *name; 419} hdac_codecs[] = { 420 { HDA_CODEC_ALC260, "Realtek ALC260" }, 421 { HDA_CODEC_ALC861, "Realtek ALC861" }, 422 { HDA_CODEC_ALC880, "Realtek ALC880" }, 423 { HDA_CODEC_ALC882, "Realtek ALC882" }, 424 { HDA_CODEC_ALC883, "Realtek ALC883" }, 425 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 426 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 427 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 428 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 429 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 430 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 431 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 432 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 433 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 434 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 435 /* Unknown codec */ 436 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 437 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 438 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 439 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 440 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 441}; 442#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 443 444enum { 445 HDAC_HP_SWITCH_CTL, 446 HDAC_HP_SWITCH_CTRL 447}; 448 449static const struct { 450 uint32_t model; 451 uint32_t id; 452 int type; 453 int inverted; 454 nid_t hpnid; 455 nid_t spkrnid[8]; 456 nid_t eapdnid; 457} hdac_hp_switch[] = { 458 /* Specific OEM models */ 459 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 460 17, { 16, -1 }, 16 }, 461 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 462 6, { 5, -1 }, 5 }, 463 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 464 6, { 5, -1 }, 5 }, 465 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 466 13, { 14, -1 }, -1 }, 467 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 468 13, { 14, -1 }, -1 }, 469 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 470 10, { 13, -1 }, -1 }, 471 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 472 26, { 27, -1 }, -1 }, 473 /* 474 * All models that at least come from the same vendor with 475 * simmilar codec. 476 */ 477 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 478 17, { 16, -1 }, 16 }, 479 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 480 6, { 5, -1 }, 5 }, 481 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 482 13, { 14, -1 }, -1 }, 483 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 484 26, { 27, -1 }, -1 }, 485}; 486#define HDAC_HP_SWITCH_LEN \ 487 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 488 489static const struct { 490 uint32_t model; 491 uint32_t id; 492 nid_t eapdnid; 493 int hp_switch; 494} hdac_eapd_switch[] = { 495 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 496 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 497 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 498}; 499#define HDAC_EAPD_SWITCH_LEN \ 500 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 501 502/**************************************************************************** 503 * Function prototypes 504 ****************************************************************************/ 505static void hdac_intr_handler(void *); 506static int hdac_reset(struct hdac_softc *); 507static int hdac_get_capabilities(struct hdac_softc *); 508static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 509static int hdac_dma_alloc(struct hdac_softc *, 510 struct hdac_dma *, bus_size_t); 511static void hdac_dma_free(struct hdac_dma *); 512static int hdac_mem_alloc(struct hdac_softc *); 513static void hdac_mem_free(struct hdac_softc *); 514static int hdac_irq_alloc(struct hdac_softc *); 515static void hdac_irq_free(struct hdac_softc *); 516static void hdac_corb_init(struct hdac_softc *); 517static void hdac_rirb_init(struct hdac_softc *); 518static void hdac_corb_start(struct hdac_softc *); 519static void hdac_rirb_start(struct hdac_softc *); 520static void hdac_scan_codecs(struct hdac_softc *); 521static int hdac_probe_codec(struct hdac_codec *); 522static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 523static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 524 525static void hdac_attach2(void *); 526 527static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 528 uint32_t, int); 529static void hdac_command_send_internal(struct hdac_softc *, 530 struct hdac_command_list *, int); 531 532static int hdac_probe(device_t); 533static int hdac_attach(device_t); 534static int hdac_detach(device_t); 535static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 536static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 537 uint32_t, int, int); 538static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 539 nid_t, int, int); 540static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 541 nid_t, nid_t, int, int, int, int, int, int); 542static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 543static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 544 545static int hdac_rirb_flush(struct hdac_softc *sc); 546static int hdac_unsolq_flush(struct hdac_softc *sc); 547 548#define hdac_command(a1, a2, a3) \ 549 hdac_command_sendone_internal(a1, a2, a3) 550 551#define hdac_codec_id(d) \ 552 ((uint32_t)((d == NULL) ? 0x00000000 : \ 553 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 554 ((uint32_t)(d)->device_id & 0x0000ffff)))) 555 556static char * 557hdac_codec_name(struct hdac_devinfo *devinfo) 558{ 559 uint32_t id; 560 int i; 561 562 id = hdac_codec_id(devinfo); 563 564 for (i = 0; i < HDAC_CODECS_LEN; i++) { 565 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 566 return (hdac_codecs[i].name); 567 } 568 569 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 570} 571 572static char * 573hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 574{ 575 static char *ossname[] = SOUND_DEVICE_NAMES; 576 static char *unknown = "???"; 577 int i; 578 579 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 580 if (devmask & (1 << i)) 581 return (ossname[i]); 582 } 583 return (unknown); 584} 585 586static void 587hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 588{ 589 static char *ossname[] = SOUND_DEVICE_NAMES; 590 int i, first = 1; 591 592 bzero(buf, len); 593 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 594 if (mask & (1 << i)) { 595 if (first == 0) 596 strlcat(buf, ", ", len); 597 strlcat(buf, ossname[i], len); 598 first = 0; 599 } 600 } 601} 602 603static struct hdac_audio_ctl * 604hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 605{ 606 if (devinfo == NULL || 607 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 608 index == NULL || devinfo->function.audio.ctl == NULL || 609 devinfo->function.audio.ctlcnt < 1 || 610 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 611 return (NULL); 612 return (&devinfo->function.audio.ctl[(*index)++]); 613} 614 615static struct hdac_audio_ctl * 616hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 617 int index, int cnt) 618{ 619 struct hdac_audio_ctl *ctl, *retctl = NULL; 620 int i, at, atindex, found = 0; 621 622 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 623 return (NULL); 624 625 at = cnt; 626 if (at == 0) 627 at = 1; 628 else if (at < 0) 629 at = -1; 630 atindex = index; 631 if (atindex < 0) 632 atindex = -1; 633 634 i = 0; 635 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 636 if (ctl->enable == 0 || ctl->widget == NULL) 637 continue; 638 if (!(ctl->widget->nid == nid && (atindex == -1 || 639 ctl->index == atindex))) 640 continue; 641 found++; 642 if (found == cnt) 643 return (ctl); 644 retctl = ctl; 645 } 646 647 return ((at == -1) ? retctl : NULL); 648} 649 650static void 651hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 652{ 653 struct hdac_softc *sc; 654 struct hdac_widget *w; 655 struct hdac_audio_ctl *ctl; 656 uint32_t id, res; 657 int i = 0, j, forcemute; 658 nid_t cad; 659 660 if (devinfo == NULL || devinfo->codec == NULL || 661 devinfo->codec->sc == NULL) 662 return; 663 664 sc = devinfo->codec->sc; 665 cad = devinfo->codec->cad; 666 id = hdac_codec_id(devinfo); 667 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 668 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 669 sc->pci_subvendor) && 670 hdac_hp_switch[i].id == id) 671 break; 672 } 673 674 if (i >= HDAC_HP_SWITCH_LEN) 675 return; 676 677 forcemute = 0; 678 if (hdac_hp_switch[i].eapdnid != -1) { 679 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 680 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 681 forcemute = (w->param.eapdbtl & 682 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 683 } 684 685 res = hdac_command(sc, 686 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 687 HDA_BOOTVERBOSE( 688 device_printf(sc->dev, 689 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 690 hdac_hp_switch[i].hpnid, res); 691 ); 692 res >>= 31; 693 res ^= hdac_hp_switch[i].inverted; 694 695 switch (hdac_hp_switch[i].type) { 696 case HDAC_HP_SWITCH_CTL: 697 ctl = hdac_audio_ctl_amp_get(devinfo, 698 hdac_hp_switch[i].hpnid, 0, 1); 699 if (ctl != NULL) { 700 ctl->muted = (res != 0 && forcemute == 0) ? 701 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 702 hdac_audio_ctl_amp_set(ctl, 703 HDA_AMP_MUTE_DEFAULT, ctl->left, 704 ctl->right); 705 } 706 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 707 ctl = hdac_audio_ctl_amp_get(devinfo, 708 hdac_hp_switch[i].spkrnid[j], 0, 1); 709 if (ctl != NULL) { 710 ctl->muted = (res != 0 || forcemute == 1) ? 711 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 712 hdac_audio_ctl_amp_set(ctl, 713 HDA_AMP_MUTE_DEFAULT, ctl->left, 714 ctl->right); 715 } 716 } 717 break; 718 case HDAC_HP_SWITCH_CTRL: 719 if (res != 0) { 720 /* HP in */ 721 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 722 if (w != NULL && w->type == 723 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 724 if (forcemute == 0) 725 w->wclass.pin.ctrl |= 726 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 727 else 728 w->wclass.pin.ctrl &= 729 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 730 hdac_command(sc, 731 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 732 w->wclass.pin.ctrl), cad); 733 } 734 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 735 w = hdac_widget_get(devinfo, 736 hdac_hp_switch[i].spkrnid[j]); 737 if (w != NULL && w->type == 738 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 739 w->wclass.pin.ctrl &= 740 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 741 hdac_command(sc, 742 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 743 w->nid, 744 w->wclass.pin.ctrl), cad); 745 } 746 } 747 } else { 748 /* HP out */ 749 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 750 if (w != NULL && w->type == 751 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 752 w->wclass.pin.ctrl &= 753 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 754 hdac_command(sc, 755 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 756 w->wclass.pin.ctrl), cad); 757 } 758 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 759 w = hdac_widget_get(devinfo, 760 hdac_hp_switch[i].spkrnid[j]); 761 if (w != NULL && w->type == 762 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 763 if (forcemute == 0) 764 w->wclass.pin.ctrl |= 765 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 766 else 767 w->wclass.pin.ctrl &= 768 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 769 hdac_command(sc, 770 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 771 w->nid, 772 w->wclass.pin.ctrl), cad); 773 } 774 } 775 } 776 break; 777 default: 778 break; 779 } 780} 781 782static void 783hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 784{ 785 struct hdac_softc *sc; 786 struct hdac_devinfo *devinfo = NULL; 787 device_t *devlist = NULL; 788 int devcount, i; 789 790 if (codec == NULL || codec->sc == NULL) 791 return; 792 793 sc = codec->sc; 794 795 HDA_BOOTVERBOSE( 796 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 797 ); 798 799 device_get_children(sc->dev, &devlist, &devcount); 800 for (i = 0; devlist != NULL && i < devcount; i++) { 801 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 802 if (devinfo != NULL && devinfo->node_type == 803 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 804 devinfo->codec != NULL && 805 devinfo->codec->cad == codec->cad) { 806 break; 807 } else 808 devinfo = NULL; 809 } 810 if (devlist != NULL) 811 free(devlist, M_TEMP); 812 813 if (devinfo == NULL) 814 return; 815 816 switch (tag) { 817 case HDAC_UNSOLTAG_EVENT_HP: 818 hdac_hp_switch_handler(devinfo); 819 break; 820 default: 821 break; 822 } 823} 824 825static int 826hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 827{ 828 /* XXX to be removed */ 829#ifdef HDAC_INTR_EXTRA 830 uint32_t res; 831#endif 832 833 if (ch->blkcnt == 0) 834 return (0); 835 836 /* XXX to be removed */ 837#ifdef HDAC_INTR_EXTRA 838 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 839#endif 840 841 /* XXX to be removed */ 842#ifdef HDAC_INTR_EXTRA 843 HDA_BOOTVERBOSE( 844 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 845 device_printf(sc->dev, 846 "PCMDIR_%s intr triggered beyond stream boundary:" 847 "%08x\n", 848 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 849 ); 850#endif 851 852 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 853 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 854 855 /* XXX to be removed */ 856#ifdef HDAC_INTR_EXTRA 857 if (res & HDAC_SDSTS_BCIS) { 858#endif 859 return (1); 860 /* XXX to be removed */ 861#ifdef HDAC_INTR_EXTRA 862 } 863#endif 864 865 return (0); 866} 867 868/**************************************************************************** 869 * void hdac_intr_handler(void *) 870 * 871 * Interrupt handler. Processes interrupts received from the hdac. 872 ****************************************************************************/ 873static void 874hdac_intr_handler(void *context) 875{ 876 struct hdac_softc *sc; 877 uint32_t intsts; 878 uint8_t rirbsts; 879 struct hdac_rirb *rirb_base; 880 uint32_t trigger = 0; 881 882 sc = (struct hdac_softc *)context; 883 884 hdac_lock(sc); 885 if (sc->polling != 0) { 886 hdac_unlock(sc); 887 return; 888 } 889 /* Do we have anything to do? */ 890 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 891 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 892 hdac_unlock(sc); 893 return; 894 } 895 896 /* Was this a controller interrupt? */ 897 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 898 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 899 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 900 /* Get as many responses that we can */ 901 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 902 HDAC_WRITE_1(&sc->mem, 903 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 904 hdac_rirb_flush(sc); 905 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 906 } 907 /* XXX to be removed */ 908 /* Clear interrupt and exit */ 909#ifdef HDAC_INTR_EXTRA 910 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 911#endif 912 } 913 914 hdac_unsolq_flush(sc); 915 916 if (intsts & HDAC_INTSTS_SIS_MASK) { 917 if ((intsts & (1 << sc->num_iss)) && 918 hdac_stream_intr(sc, &sc->play) != 0) 919 trigger |= 1; 920 if ((intsts & (1 << 0)) && 921 hdac_stream_intr(sc, &sc->rec) != 0) 922 trigger |= 2; 923 /* XXX to be removed */ 924#ifdef HDAC_INTR_EXTRA 925 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 926 HDAC_INTSTS_SIS_MASK); 927#endif 928 } 929 930 hdac_unlock(sc); 931 932 if (trigger & 1) 933 chn_intr(sc->play.c); 934 if (trigger & 2) 935 chn_intr(sc->rec.c); 936} 937 938/**************************************************************************** 939 * int hdac_reset(hdac_softc *) 940 * 941 * Reset the hdac to a quiescent and known state. 942 ****************************************************************************/ 943static int 944hdac_reset(struct hdac_softc *sc) 945{ 946 uint32_t gctl; 947 int count, i; 948 949 /* 950 * Stop all Streams DMA engine 951 */ 952 for (i = 0; i < sc->num_iss; i++) 953 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 954 for (i = 0; i < sc->num_oss; i++) 955 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 956 for (i = 0; i < sc->num_bss; i++) 957 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 958 959 /* 960 * Stop Control DMA engines 961 */ 962 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 963 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 964 965 /* 966 * Reset the controller. The reset must remain asserted for 967 * a minimum of 100us. 968 */ 969 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 970 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 971 count = 10000; 972 do { 973 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 974 if (!(gctl & HDAC_GCTL_CRST)) 975 break; 976 DELAY(10); 977 } while (--count); 978 if (gctl & HDAC_GCTL_CRST) { 979 device_printf(sc->dev, "Unable to put hdac in reset\n"); 980 return (ENXIO); 981 } 982 DELAY(100); 983 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 984 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 985 count = 10000; 986 do { 987 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 988 if (gctl & HDAC_GCTL_CRST) 989 break; 990 DELAY(10); 991 } while (--count); 992 if (!(gctl & HDAC_GCTL_CRST)) { 993 device_printf(sc->dev, "Device stuck in reset\n"); 994 return (ENXIO); 995 } 996 997 /* 998 * Wait for codecs to finish their own reset sequence. The delay here 999 * should be of 250us but for some reasons, on it's not enough on my 1000 * computer. Let's use twice as much as necessary to make sure that 1001 * it's reset properly. 1002 */ 1003 DELAY(1000); 1004 1005 return (0); 1006} 1007 1008 1009/**************************************************************************** 1010 * int hdac_get_capabilities(struct hdac_softc *); 1011 * 1012 * Retreive the general capabilities of the hdac; 1013 * Number of Input Streams 1014 * Number of Output Streams 1015 * Number of bidirectional Streams 1016 * 64bit ready 1017 * CORB and RIRB sizes 1018 ****************************************************************************/ 1019static int 1020hdac_get_capabilities(struct hdac_softc *sc) 1021{ 1022 uint16_t gcap; 1023 uint8_t corbsize, rirbsize; 1024 1025 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1026 sc->num_iss = HDAC_GCAP_ISS(gcap); 1027 sc->num_oss = HDAC_GCAP_OSS(gcap); 1028 sc->num_bss = HDAC_GCAP_BSS(gcap); 1029 1030 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1031 1032 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1033 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1034 HDAC_CORBSIZE_CORBSZCAP_256) 1035 sc->corb_size = 256; 1036 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1037 HDAC_CORBSIZE_CORBSZCAP_16) 1038 sc->corb_size = 16; 1039 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1040 HDAC_CORBSIZE_CORBSZCAP_2) 1041 sc->corb_size = 2; 1042 else { 1043 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1044 __func__, corbsize); 1045 return (ENXIO); 1046 } 1047 1048 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1049 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1050 HDAC_RIRBSIZE_RIRBSZCAP_256) 1051 sc->rirb_size = 256; 1052 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1053 HDAC_RIRBSIZE_RIRBSZCAP_16) 1054 sc->rirb_size = 16; 1055 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1056 HDAC_RIRBSIZE_RIRBSZCAP_2) 1057 sc->rirb_size = 2; 1058 else { 1059 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1060 __func__, rirbsize); 1061 return (ENXIO); 1062 } 1063 1064 return (0); 1065} 1066 1067 1068/**************************************************************************** 1069 * void hdac_dma_cb 1070 * 1071 * This function is called by bus_dmamap_load when the mapping has been 1072 * established. We just record the physical address of the mapping into 1073 * the struct hdac_dma passed in. 1074 ****************************************************************************/ 1075static void 1076hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1077{ 1078 struct hdac_dma *dma; 1079 1080 if (error == 0) { 1081 dma = (struct hdac_dma *)callback_arg; 1082 dma->dma_paddr = segs[0].ds_addr; 1083 } 1084} 1085 1086static void 1087hdac_dma_nocache(void *ptr) 1088{ 1089#if defined(__i386__) || defined(__amd64__) 1090 pt_entry_t *pte; 1091 vm_offset_t va; 1092 1093 va = (vm_offset_t)ptr; 1094 pte = vtopte(va); 1095 if (pte) { 1096 *pte |= PG_N; 1097 invltlb(); 1098 } 1099#endif 1100} 1101 1102/**************************************************************************** 1103 * int hdac_dma_alloc 1104 * 1105 * This function allocate and setup a dma region (struct hdac_dma). 1106 * It must be freed by a corresponding hdac_dma_free. 1107 ****************************************************************************/ 1108static int 1109hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1110{ 1111 int result; 1112 int lowaddr; 1113 1114 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1115 BUS_SPACE_MAXADDR_32BIT; 1116 bzero(dma, sizeof(*dma)); 1117 1118 /* 1119 * Create a DMA tag 1120 */ 1121 result = bus_dma_tag_create(NULL, /* parent */ 1122 HDAC_DMA_ALIGNMENT, /* alignment */ 1123 0, /* boundary */ 1124 lowaddr, /* lowaddr */ 1125 BUS_SPACE_MAXADDR, /* highaddr */ 1126 NULL, /* filtfunc */ 1127 NULL, /* fistfuncarg */ 1128 size, /* maxsize */ 1129 1, /* nsegments */ 1130 size, /* maxsegsz */ 1131 0, /* flags */ 1132 NULL, /* lockfunc */ 1133 NULL, /* lockfuncarg */ 1134 &dma->dma_tag); /* dmat */ 1135 if (result != 0) { 1136 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1137 __func__, result); 1138 goto fail; 1139 } 1140 1141 /* 1142 * Allocate DMA memory 1143 */ 1144 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1145 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1146 if (result != 0) { 1147 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1148 __func__, result); 1149 goto fail; 1150 } 1151 1152 /* 1153 * Map the memory 1154 */ 1155 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1156 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1157 BUS_DMA_NOWAIT); 1158 if (result != 0 || dma->dma_paddr == 0) { 1159 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1160 __func__, result); 1161 goto fail; 1162 } 1163 bzero((void *)dma->dma_vaddr, size); 1164 hdac_dma_nocache(dma->dma_vaddr); 1165 1166 return (0); 1167fail: 1168 if (dma->dma_map != NULL) 1169 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1170 if (dma->dma_tag != NULL) 1171 bus_dma_tag_destroy(dma->dma_tag); 1172 return (result); 1173} 1174 1175 1176/**************************************************************************** 1177 * void hdac_dma_free(struct hdac_dma *) 1178 * 1179 * Free a struct dhac_dma that has been previously allocated via the 1180 * hdac_dma_alloc function. 1181 ****************************************************************************/ 1182static void 1183hdac_dma_free(struct hdac_dma *dma) 1184{ 1185 if (dma->dma_tag != NULL) { 1186 /* Flush caches */ 1187 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1188 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1189 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1190 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1191 bus_dma_tag_destroy(dma->dma_tag); 1192 } 1193} 1194 1195/**************************************************************************** 1196 * int hdac_mem_alloc(struct hdac_softc *) 1197 * 1198 * Allocate all the bus resources necessary to speak with the physical 1199 * controller. 1200 ****************************************************************************/ 1201static int 1202hdac_mem_alloc(struct hdac_softc *sc) 1203{ 1204 struct hdac_mem *mem; 1205 1206 mem = &sc->mem; 1207 mem->mem_rid = PCIR_BAR(0); 1208 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1209 &mem->mem_rid, RF_ACTIVE); 1210 if (mem->mem_res == NULL) { 1211 device_printf(sc->dev, 1212 "%s: Unable to allocate memory resource\n", __func__); 1213 return (ENOMEM); 1214 } 1215 mem->mem_tag = rman_get_bustag(mem->mem_res); 1216 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1217 1218 return (0); 1219} 1220 1221/**************************************************************************** 1222 * void hdac_mem_free(struct hdac_softc *) 1223 * 1224 * Free up resources previously allocated by hdac_mem_alloc. 1225 ****************************************************************************/ 1226static void 1227hdac_mem_free(struct hdac_softc *sc) 1228{ 1229 struct hdac_mem *mem; 1230 1231 mem = &sc->mem; 1232 if (mem->mem_res != NULL) 1233 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1234 mem->mem_res); 1235 mem->mem_res = NULL; 1236} 1237 1238/**************************************************************************** 1239 * int hdac_irq_alloc(struct hdac_softc *) 1240 * 1241 * Allocate and setup the resources necessary for interrupt handling. 1242 ****************************************************************************/ 1243static int 1244hdac_irq_alloc(struct hdac_softc *sc) 1245{ 1246 struct hdac_irq *irq; 1247 int result; 1248 1249 irq = &sc->irq; 1250 irq->irq_rid = 0x0; 1251 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1252 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1253 if (irq->irq_res == NULL) { 1254 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1255 __func__); 1256 goto fail; 1257 } 1258 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1259 hdac_intr_handler, sc, &irq->irq_handle); 1260 if (result != 0) { 1261 device_printf(sc->dev, 1262 "%s: Unable to setup interrupt handler (%x)\n", 1263 __func__, result); 1264 goto fail; 1265 } 1266 1267 return (0); 1268 1269fail: 1270 hdac_irq_free(sc); 1271 1272 return (ENXIO); 1273} 1274 1275/**************************************************************************** 1276 * void hdac_irq_free(struct hdac_softc *) 1277 * 1278 * Free up resources previously allocated by hdac_irq_alloc. 1279 ****************************************************************************/ 1280static void 1281hdac_irq_free(struct hdac_softc *sc) 1282{ 1283 struct hdac_irq *irq; 1284 1285 irq = &sc->irq; 1286 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1287 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1288 if (irq->irq_res != NULL) 1289 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1290 irq->irq_res); 1291 irq->irq_handle = NULL; 1292 irq->irq_res = NULL; 1293} 1294 1295/**************************************************************************** 1296 * void hdac_corb_init(struct hdac_softc *) 1297 * 1298 * Initialize the corb registers for operations but do not start it up yet. 1299 * The CORB engine must not be running when this function is called. 1300 ****************************************************************************/ 1301static void 1302hdac_corb_init(struct hdac_softc *sc) 1303{ 1304 uint8_t corbsize; 1305 uint64_t corbpaddr; 1306 1307 /* Setup the CORB size. */ 1308 switch (sc->corb_size) { 1309 case 256: 1310 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1311 break; 1312 case 16: 1313 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1314 break; 1315 case 2: 1316 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1317 break; 1318 default: 1319 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1320 } 1321 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1322 1323 /* Setup the CORB Address in the hdac */ 1324 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1325 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1326 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1327 1328 /* Set the WP and RP */ 1329 sc->corb_wp = 0; 1330 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1331 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1332 /* 1333 * The HDA specification indicates that the CORBRPRST bit will always 1334 * read as zero. Unfortunately, it seems that at least the 82801G 1335 * doesn't reset the bit to zero, which stalls the corb engine. 1336 * manually reset the bit to zero before continuing. 1337 */ 1338 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1339 1340 /* Enable CORB error reporting */ 1341#if 0 1342 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1343#endif 1344} 1345 1346/**************************************************************************** 1347 * void hdac_rirb_init(struct hdac_softc *) 1348 * 1349 * Initialize the rirb registers for operations but do not start it up yet. 1350 * The RIRB engine must not be running when this function is called. 1351 ****************************************************************************/ 1352static void 1353hdac_rirb_init(struct hdac_softc *sc) 1354{ 1355 uint8_t rirbsize; 1356 uint64_t rirbpaddr; 1357 1358 /* Setup the RIRB size. */ 1359 switch (sc->rirb_size) { 1360 case 256: 1361 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1362 break; 1363 case 16: 1364 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1365 break; 1366 case 2: 1367 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1368 break; 1369 default: 1370 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1371 } 1372 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1373 1374 /* Setup the RIRB Address in the hdac */ 1375 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1376 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1377 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1378 1379 /* Setup the WP and RP */ 1380 sc->rirb_rp = 0; 1381 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1382 1383 if (sc->polling == 0) { 1384 /* Setup the interrupt threshold */ 1385 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1386 1387 /* Enable Overrun and response received reporting */ 1388#if 0 1389 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1390 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1391#else 1392 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1393#endif 1394 } 1395 1396 /* 1397 * Make sure that the Host CPU cache doesn't contain any dirty 1398 * cache lines that falls in the rirb. If I understood correctly, it 1399 * should be sufficient to do this only once as the rirb is purely 1400 * read-only from now on. 1401 */ 1402 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1403 BUS_DMASYNC_PREREAD); 1404} 1405 1406/**************************************************************************** 1407 * void hdac_corb_start(hdac_softc *) 1408 * 1409 * Startup the corb DMA engine 1410 ****************************************************************************/ 1411static void 1412hdac_corb_start(struct hdac_softc *sc) 1413{ 1414 uint32_t corbctl; 1415 1416 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1417 corbctl |= HDAC_CORBCTL_CORBRUN; 1418 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1419} 1420 1421/**************************************************************************** 1422 * void hdac_rirb_start(hdac_softc *) 1423 * 1424 * Startup the rirb DMA engine 1425 ****************************************************************************/ 1426static void 1427hdac_rirb_start(struct hdac_softc *sc) 1428{ 1429 uint32_t rirbctl; 1430 1431 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1432 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1433 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1434} 1435 1436 1437/**************************************************************************** 1438 * void hdac_scan_codecs(struct hdac_softc *) 1439 * 1440 * Scan the bus for available codecs. 1441 ****************************************************************************/ 1442static void 1443hdac_scan_codecs(struct hdac_softc *sc) 1444{ 1445 struct hdac_codec *codec; 1446 int i; 1447 uint16_t statests; 1448 1449 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1450 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1451 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1452 /* We have found a codec. */ 1453 hdac_unlock(sc); 1454 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1455 M_HDAC, M_ZERO | M_NOWAIT); 1456 hdac_lock(sc); 1457 if (codec == NULL) { 1458 device_printf(sc->dev, 1459 "Unable to allocate memory for codec\n"); 1460 continue; 1461 } 1462 codec->commands = NULL; 1463 codec->responses_received = 0; 1464 codec->verbs_sent = 0; 1465 codec->sc = sc; 1466 codec->cad = i; 1467 sc->codecs[i] = codec; 1468 if (hdac_probe_codec(codec) != 0) 1469 break; 1470 } 1471 } 1472 /* All codecs have been probed, now try to attach drivers to them */ 1473 /* bus_generic_attach(sc->dev); */ 1474} 1475 1476/**************************************************************************** 1477 * void hdac_probe_codec(struct hdac_softc *, int) 1478 * 1479 * Probe a the given codec_id for available function groups. 1480 ****************************************************************************/ 1481static int 1482hdac_probe_codec(struct hdac_codec *codec) 1483{ 1484 struct hdac_softc *sc = codec->sc; 1485 struct hdac_devinfo *devinfo; 1486 uint32_t vendorid, revisionid, subnode; 1487 int startnode; 1488 int endnode; 1489 int i; 1490 nid_t cad = codec->cad; 1491 1492 HDA_BOOTVERBOSE( 1493 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1494 ); 1495 vendorid = hdac_command(sc, 1496 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1497 cad); 1498 revisionid = hdac_command(sc, 1499 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1500 cad); 1501 subnode = hdac_command(sc, 1502 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1503 cad); 1504 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1505 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1506 1507 HDA_BOOTVERBOSE( 1508 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1509 startnode, endnode); 1510 ); 1511 for (i = startnode; i < endnode; i++) { 1512 devinfo = hdac_probe_function(codec, i); 1513 if (devinfo != NULL) { 1514 /* XXX Ignore other FG. */ 1515 devinfo->vendor_id = 1516 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1517 devinfo->device_id = 1518 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1519 devinfo->revision_id = 1520 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1521 devinfo->stepping_id = 1522 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1523 HDA_BOOTVERBOSE( 1524 device_printf(sc->dev, 1525 "HDA_DEBUG: \tFound AFG nid=%d " 1526 "[startnode=%d endnode=%d]\n", 1527 devinfo->nid, startnode, endnode); 1528 ); 1529 return (1); 1530 } 1531 } 1532 1533 HDA_BOOTVERBOSE( 1534 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1535 ); 1536 return (0); 1537} 1538 1539static struct hdac_devinfo * 1540hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1541{ 1542 struct hdac_softc *sc = codec->sc; 1543 struct hdac_devinfo *devinfo; 1544 uint32_t fctgrptype; 1545 nid_t cad = codec->cad; 1546 1547 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1548 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1549 1550 /* XXX For now, ignore other FG. */ 1551 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1552 return (NULL); 1553 1554 hdac_unlock(sc); 1555 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1556 M_NOWAIT | M_ZERO); 1557 hdac_lock(sc); 1558 if (devinfo == NULL) { 1559 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1560 __func__); 1561 return (NULL); 1562 } 1563 1564 devinfo->nid = nid; 1565 devinfo->node_type = fctgrptype; 1566 devinfo->codec = codec; 1567 1568 hdac_add_child(sc, devinfo); 1569 1570 return (devinfo); 1571} 1572 1573static void 1574hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1575{ 1576 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1577 device_set_ivars(devinfo->dev, (void *)devinfo); 1578 /* XXX - Print more information when booting verbose??? */ 1579} 1580 1581static void 1582hdac_widget_connection_parse(struct hdac_widget *w) 1583{ 1584 struct hdac_softc *sc = w->devinfo->codec->sc; 1585 uint32_t res; 1586 int i, j, max, found, entnum, cnid; 1587 nid_t cad = w->devinfo->codec->cad; 1588 nid_t nid = w->nid; 1589 1590 res = hdac_command(sc, 1591 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1592 1593 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1594 1595 if (w->nconns < 1) 1596 return; 1597 1598 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1599 res = 0; 1600 i = 0; 1601 found = 0; 1602 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1603 1604 while (i < w->nconns) { 1605 res = hdac_command(sc, 1606 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1607 for (j = 0; j < entnum; j++) { 1608 cnid = res; 1609 cnid >>= (32 / entnum) * j; 1610 cnid &= (1 << (32 / entnum)) - 1; 1611 if (cnid == 0) 1612 continue; 1613 if (found > max) { 1614 device_printf(sc->dev, 1615 "node %d: Adding %d: " 1616 "Max connection reached!\n", 1617 nid, cnid); 1618 continue; 1619 } 1620 w->conns[found++] = cnid; 1621 } 1622 i += entnum; 1623 } 1624 1625 HDA_BOOTVERBOSE( 1626 if (w->nconns != found) { 1627 device_printf(sc->dev, 1628 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1629 "length=%d != found=%d\n", 1630 nid, w->nconns, found); 1631 } 1632 ); 1633} 1634 1635static uint32_t 1636hdac_widget_pin_getconfig(struct hdac_widget *w) 1637{ 1638 struct hdac_softc *sc; 1639 uint32_t config, id; 1640 nid_t cad, nid; 1641 1642 sc = w->devinfo->codec->sc; 1643 cad = w->devinfo->codec->cad; 1644 nid = w->nid; 1645 id = hdac_codec_id(w->devinfo); 1646 1647 config = hdac_command(sc, 1648 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1649 cad); 1650 /* 1651 * XXX REWRITE!!!! Don't argue! 1652 */ 1653 if (id == HDA_CODEC_ALC880 && 1654 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1655 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1656 /* 1657 * Super broken BIOS 1658 */ 1659 switch (nid) { 1660 case 20: 1661 break; 1662 case 21: 1663 break; 1664 case 22: 1665 break; 1666 case 23: 1667 break; 1668 case 24: /* MIC1 */ 1669 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1670 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1671 break; 1672 case 25: /* XXX MIC2 */ 1673 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1674 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1675 break; 1676 case 26: /* LINE1 */ 1677 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1678 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1679 break; 1680 case 27: /* XXX LINE2 */ 1681 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1682 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1683 break; 1684 case 28: /* CD */ 1685 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1686 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1687 break; 1688 case 30: 1689 break; 1690 case 31: 1691 break; 1692 default: 1693 break; 1694 } 1695 } 1696 1697 return (config); 1698} 1699 1700static void 1701hdac_widget_pin_parse(struct hdac_widget *w) 1702{ 1703 struct hdac_softc *sc = w->devinfo->codec->sc; 1704 uint32_t config, pincap; 1705 char *devstr, *connstr; 1706 nid_t cad = w->devinfo->codec->cad; 1707 nid_t nid = w->nid; 1708 1709 config = hdac_widget_pin_getconfig(w); 1710 w->wclass.pin.config = config; 1711 1712 pincap = hdac_command(sc, 1713 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1714 w->wclass.pin.cap = pincap; 1715 1716 w->wclass.pin.ctrl = hdac_command(sc, 1717 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1718 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1719 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1720 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1721 1722 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1723 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1724 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1725 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1726 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1727 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1728 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1729 w->param.eapdbtl = hdac_command(sc, 1730 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1731 w->param.eapdbtl &= 0x7; 1732 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1733 } else 1734 w->param.eapdbtl = HDAC_INVALID; 1735 1736 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1737 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1738 devstr = "line out"; 1739 break; 1740 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1741 devstr = "speaker"; 1742 break; 1743 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1744 devstr = "headphones out"; 1745 break; 1746 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1747 devstr = "CD"; 1748 break; 1749 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1750 devstr = "SPDIF out"; 1751 break; 1752 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1753 devstr = "digital (other) out"; 1754 break; 1755 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1756 devstr = "modem, line side"; 1757 break; 1758 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1759 devstr = "modem, handset side"; 1760 break; 1761 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1762 devstr = "line in"; 1763 break; 1764 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1765 devstr = "AUX"; 1766 break; 1767 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1768 devstr = "Mic in"; 1769 break; 1770 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1771 devstr = "telephony"; 1772 break; 1773 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1774 devstr = "SPDIF in"; 1775 break; 1776 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1777 devstr = "digital (other) in"; 1778 break; 1779 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1780 devstr = "other"; 1781 break; 1782 default: 1783 devstr = "unknown"; 1784 break; 1785 } 1786 1787 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1788 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1789 connstr = "jack"; 1790 break; 1791 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1792 connstr = "none"; 1793 break; 1794 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1795 connstr = "fixed"; 1796 break; 1797 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1798 connstr = "jack / fixed"; 1799 break; 1800 default: 1801 connstr = "unknown"; 1802 break; 1803 } 1804 1805 strlcat(w->name, ": ", sizeof(w->name)); 1806 strlcat(w->name, devstr, sizeof(w->name)); 1807 strlcat(w->name, " (", sizeof(w->name)); 1808 strlcat(w->name, connstr, sizeof(w->name)); 1809 strlcat(w->name, ")", sizeof(w->name)); 1810} 1811 1812static void 1813hdac_widget_parse(struct hdac_widget *w) 1814{ 1815 struct hdac_softc *sc = w->devinfo->codec->sc; 1816 uint32_t wcap, cap; 1817 char *typestr; 1818 nid_t cad = w->devinfo->codec->cad; 1819 nid_t nid = w->nid; 1820 1821 wcap = hdac_command(sc, 1822 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1823 cad); 1824 w->param.widget_cap = wcap; 1825 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1826 1827 switch (w->type) { 1828 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1829 typestr = "audio output"; 1830 break; 1831 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1832 typestr = "audio input"; 1833 break; 1834 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1835 typestr = "audio mixer"; 1836 break; 1837 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1838 typestr = "audio selector"; 1839 break; 1840 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1841 typestr = "pin"; 1842 break; 1843 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1844 typestr = "power widget"; 1845 break; 1846 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1847 typestr = "volume widget"; 1848 break; 1849 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1850 typestr = "beep widget"; 1851 break; 1852 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1853 typestr = "vendor widget"; 1854 break; 1855 default: 1856 typestr = "unknown type"; 1857 break; 1858 } 1859 1860 strlcpy(w->name, typestr, sizeof(w->name)); 1861 1862 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1863 hdac_command(sc, 1864 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1865 cad); 1866 DELAY(1000); 1867 } 1868 1869 hdac_widget_connection_parse(w); 1870 1871 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1872 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1873 w->param.outamp_cap = 1874 hdac_command(sc, 1875 HDA_CMD_GET_PARAMETER(cad, nid, 1876 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1877 else 1878 w->param.outamp_cap = 1879 w->devinfo->function.audio.outamp_cap; 1880 } else 1881 w->param.outamp_cap = 0; 1882 1883 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1884 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1885 w->param.inamp_cap = 1886 hdac_command(sc, 1887 HDA_CMD_GET_PARAMETER(cad, nid, 1888 HDA_PARAM_INPUT_AMP_CAP), cad); 1889 else 1890 w->param.inamp_cap = 1891 w->devinfo->function.audio.inamp_cap; 1892 } else 1893 w->param.inamp_cap = 0; 1894 1895 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1896 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1897 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1898 cap = hdac_command(sc, 1899 HDA_CMD_GET_PARAMETER(cad, nid, 1900 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1901 w->param.supp_stream_formats = (cap != 0) ? cap : 1902 w->devinfo->function.audio.supp_stream_formats; 1903 cap = hdac_command(sc, 1904 HDA_CMD_GET_PARAMETER(cad, nid, 1905 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1906 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1907 w->devinfo->function.audio.supp_pcm_size_rate; 1908 } else { 1909 w->param.supp_stream_formats = 1910 w->devinfo->function.audio.supp_stream_formats; 1911 w->param.supp_pcm_size_rate = 1912 w->devinfo->function.audio.supp_pcm_size_rate; 1913 } 1914 } else { 1915 w->param.supp_stream_formats = 0; 1916 w->param.supp_pcm_size_rate = 0; 1917 } 1918 1919 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1920 hdac_widget_pin_parse(w); 1921} 1922 1923static struct hdac_widget * 1924hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1925{ 1926 if (devinfo == NULL || devinfo->widget == NULL || 1927 nid < devinfo->startnode || nid >= devinfo->endnode) 1928 return (NULL); 1929 return (&devinfo->widget[nid - devinfo->startnode]); 1930} 1931 1932static __inline int 1933hda_poll_channel(struct hdac_chan *ch) 1934{ 1935 uint32_t sz, delta; 1936 volatile uint32_t ptr; 1937 1938 if (ch->active == 0) 1939 return (0); 1940 1941 sz = ch->blksz * ch->blkcnt; 1942 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1943 ch->ptr = ptr; 1944 ptr %= sz; 1945 ptr &= ~(ch->blksz - 1); 1946 delta = (sz + ptr - ch->prevptr) % sz; 1947 1948 if (delta < ch->blksz) 1949 return (0); 1950 1951 ch->prevptr = ptr; 1952 1953 return (1); 1954} 1955 1956#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1957 1958static void 1959hda_poll_callback(void *arg) 1960{ 1961 struct hdac_softc *sc = arg; 1962 uint32_t trigger = 0; 1963 1964 if (sc == NULL) 1965 return; 1966 1967 hdac_lock(sc); 1968 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 1969 hdac_unlock(sc); 1970 return; 1971 } 1972 1973 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 1974 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 1975 1976 /* XXX */ 1977 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 1978 hda_poll_callback, sc); 1979 1980 hdac_unlock(sc); 1981 1982 if (trigger & 1) 1983 chn_intr(sc->play.c); 1984 if (trigger & 2) 1985 chn_intr(sc->rec.c); 1986} 1987 1988static int 1989hdac_rirb_flush(struct hdac_softc *sc) 1990{ 1991 struct hdac_rirb *rirb_base, *rirb; 1992 struct hdac_codec *codec; 1993 struct hdac_command_list *commands; 1994 nid_t cad; 1995 uint32_t resp; 1996 uint8_t rirbwp; 1997 int ret = 0; 1998 1999 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2000 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2001 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2002 BUS_DMASYNC_POSTREAD); 2003 2004 while (sc->rirb_rp != rirbwp) { 2005 sc->rirb_rp++; 2006 sc->rirb_rp %= sc->rirb_size; 2007 rirb = &rirb_base[sc->rirb_rp]; 2008 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2009 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2010 sc->codecs[cad] == NULL) 2011 continue; 2012 resp = rirb->response; 2013 codec = sc->codecs[cad]; 2014 commands = codec->commands; 2015 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2016 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2017 ((resp >> 26) & 0xffff); 2018 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2019 } else if (commands != NULL && commands->num_commands > 0 && 2020 codec->responses_received < commands->num_commands) 2021 commands->responses[codec->responses_received++] = 2022 resp; 2023 ret++; 2024 } 2025 2026 return (ret); 2027} 2028 2029static int 2030hdac_unsolq_flush(struct hdac_softc *sc) 2031{ 2032 nid_t cad; 2033 uint32_t tag; 2034 int ret = 0; 2035 2036 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2037 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2038 while (sc->unsolq_rp != sc->unsolq_wp) { 2039 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2040 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2041 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2042 hdac_unsolicited_handler(sc->codecs[cad], tag); 2043 ret++; 2044 } 2045 sc->unsolq_st = HDAC_UNSOLQ_READY; 2046 } 2047 2048 return (ret); 2049} 2050 2051static void 2052hdac_poll_callback(void *arg) 2053{ 2054 struct hdac_softc *sc = arg; 2055 if (sc == NULL) 2056 return; 2057 2058 hdac_lock(sc); 2059 if (sc->polling == 0) { 2060 hdac_unlock(sc); 2061 return; 2062 } 2063 hdac_rirb_flush(sc); 2064 hdac_unsolq_flush(sc); 2065 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2066 hdac_poll_callback, sc); 2067 hdac_unlock(sc); 2068} 2069 2070static void 2071hdac_stream_stop(struct hdac_chan *ch) 2072{ 2073 struct hdac_softc *sc = ch->devinfo->codec->sc; 2074 uint32_t ctl; 2075 2076 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2077 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2078 HDAC_SDCTL_RUN); 2079 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2080 2081 ch->active = 0; 2082 2083 if (sc->polling != 0) { 2084 int pollticks; 2085 2086 if (hda_chan_active(sc) == 0) { 2087 callout_stop(&sc->poll_hda); 2088 sc->poll_ticks = 1; 2089 } else { 2090 if (sc->play.active != 0) 2091 ch = &sc->play; 2092 else 2093 ch = &sc->rec; 2094 pollticks = ((uint64_t)hz * ch->blksz) / 2095 ((uint64_t)sndbuf_getbps(ch->b) * 2096 sndbuf_getspd(ch->b)); 2097 pollticks >>= 2; 2098 if (pollticks > hz) 2099 pollticks = hz; 2100 if (pollticks < 1) { 2101 HDA_BOOTVERBOSE( 2102 device_printf(sc->dev, 2103 "%s: pollticks=%d < 1 !\n", 2104 __func__, pollticks); 2105 ); 2106 pollticks = 1; 2107 } 2108 if (pollticks > sc->poll_ticks) { 2109 HDA_BOOTVERBOSE( 2110 device_printf(sc->dev, 2111 "%s: pollticks %d -> %d\n", 2112 __func__, sc->poll_ticks, 2113 pollticks); 2114 ); 2115 sc->poll_ticks = pollticks; 2116 callout_reset(&sc->poll_hda, 1, 2117 hda_poll_callback, sc); 2118 } 2119 } 2120 } else { 2121 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2122 ctl &= ~(1 << (ch->off >> 5)); 2123 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2124 } 2125} 2126 2127static void 2128hdac_stream_start(struct hdac_chan *ch) 2129{ 2130 struct hdac_softc *sc = ch->devinfo->codec->sc; 2131 uint32_t ctl; 2132 2133 if (sc->polling != 0) { 2134 int pollticks; 2135 2136 pollticks = ((uint64_t)hz * ch->blksz) / 2137 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2138 pollticks >>= 2; 2139 if (pollticks > hz) 2140 pollticks = hz; 2141 if (pollticks < 1) { 2142 HDA_BOOTVERBOSE( 2143 device_printf(sc->dev, 2144 "%s: pollticks=%d < 1 !\n", 2145 __func__, pollticks); 2146 ); 2147 pollticks = 1; 2148 } 2149 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2150 HDA_BOOTVERBOSE( 2151 if (hda_chan_active(sc) == 0) { 2152 device_printf(sc->dev, 2153 "%s: pollticks=%d\n", 2154 __func__, pollticks); 2155 } else { 2156 device_printf(sc->dev, 2157 "%s: pollticks %d -> %d\n", 2158 __func__, sc->poll_ticks, 2159 pollticks); 2160 } 2161 ); 2162 sc->poll_ticks = pollticks; 2163 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2164 sc); 2165 } 2166 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2167 ctl |= HDAC_SDCTL_RUN; 2168 } else { 2169 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2170 ctl |= 1 << (ch->off >> 5); 2171 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2172 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2173 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2174 HDAC_SDCTL_RUN; 2175 } 2176 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2177 2178 ch->active = 1; 2179} 2180 2181static void 2182hdac_stream_reset(struct hdac_chan *ch) 2183{ 2184 struct hdac_softc *sc = ch->devinfo->codec->sc; 2185 int timeout = 1000; 2186 int to = timeout; 2187 uint32_t ctl; 2188 2189 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2190 ctl |= HDAC_SDCTL_SRST; 2191 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2192 do { 2193 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2194 if (ctl & HDAC_SDCTL_SRST) 2195 break; 2196 DELAY(10); 2197 } while (--to); 2198 if (!(ctl & HDAC_SDCTL_SRST)) { 2199 device_printf(sc->dev, "timeout in reset\n"); 2200 } 2201 ctl &= ~HDAC_SDCTL_SRST; 2202 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2203 to = timeout; 2204 do { 2205 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2206 if (!(ctl & HDAC_SDCTL_SRST)) 2207 break; 2208 DELAY(10); 2209 } while (--to); 2210 if (ctl & HDAC_SDCTL_SRST) 2211 device_printf(sc->dev, "can't reset!\n"); 2212} 2213 2214static void 2215hdac_stream_setid(struct hdac_chan *ch) 2216{ 2217 struct hdac_softc *sc = ch->devinfo->codec->sc; 2218 uint32_t ctl; 2219 2220 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2221 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2222 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2223 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2224} 2225 2226static void 2227hdac_bdl_setup(struct hdac_chan *ch) 2228{ 2229 struct hdac_softc *sc = ch->devinfo->codec->sc; 2230 struct hdac_bdle *bdle; 2231 uint64_t addr; 2232 uint32_t blksz, blkcnt; 2233 int i; 2234 2235 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2236 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2237 2238 if (sc->polling != 0) { 2239 blksz = ch->blksz * ch->blkcnt; 2240 blkcnt = 1; 2241 } else { 2242 blksz = ch->blksz; 2243 blkcnt = ch->blkcnt; 2244 } 2245 2246 for (i = 0; i < blkcnt; i++, bdle++) { 2247 bdle->addrl = (uint32_t)addr; 2248 bdle->addrh = (uint32_t)(addr >> 32); 2249 bdle->len = blksz; 2250 bdle->ioc = 1 ^ sc->polling; 2251 addr += blksz; 2252 } 2253 2254 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2255 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2256 addr = ch->bdl_dma.dma_paddr; 2257 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2258 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2259} 2260 2261static int 2262hdac_bdl_alloc(struct hdac_chan *ch) 2263{ 2264 struct hdac_softc *sc = ch->devinfo->codec->sc; 2265 int rc; 2266 2267 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2268 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2269 if (rc) { 2270 device_printf(sc->dev, "can't alloc bdl\n"); 2271 return (rc); 2272 } 2273 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2274 2275 return (0); 2276} 2277 2278static void 2279hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2280 int index, int lmute, int rmute, 2281 int left, int right, int dir) 2282{ 2283 uint16_t v = 0; 2284 2285 if (sc == NULL) 2286 return; 2287 2288 if (left != right || lmute != rmute) { 2289 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2290 (lmute << 7) | left; 2291 hdac_command(sc, 2292 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2293 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2294 (rmute << 7) | right; 2295 } else 2296 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2297 (lmute << 7) | left; 2298 2299 hdac_command(sc, 2300 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2301} 2302 2303static void 2304hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2305 int left, int right) 2306{ 2307 struct hdac_softc *sc; 2308 nid_t nid, cad; 2309 int lmute, rmute; 2310 2311 if (ctl == NULL || ctl->widget == NULL || 2312 ctl->widget->devinfo == NULL || 2313 ctl->widget->devinfo->codec == NULL || 2314 ctl->widget->devinfo->codec->sc == NULL) 2315 return; 2316 2317 sc = ctl->widget->devinfo->codec->sc; 2318 cad = ctl->widget->devinfo->codec->cad; 2319 nid = ctl->widget->nid; 2320 2321 if (mute == HDA_AMP_MUTE_DEFAULT) { 2322 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2323 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2324 } else { 2325 lmute = HDA_AMP_LEFT_MUTED(mute); 2326 rmute = HDA_AMP_RIGHT_MUTED(mute); 2327 } 2328 2329 if (ctl->dir & HDA_CTL_OUT) 2330 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2331 lmute, rmute, left, right, 0); 2332 if (ctl->dir & HDA_CTL_IN) 2333 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2334 lmute, rmute, left, right, 1); 2335 ctl->left = left; 2336 ctl->right = right; 2337} 2338 2339static void 2340hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2341{ 2342 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2343 return; 2344 hdac_command(w->devinfo->codec->sc, 2345 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2346 w->nid, index), w->devinfo->codec->cad); 2347 w->selconn = index; 2348} 2349 2350 2351/**************************************************************************** 2352 * uint32_t hdac_command_sendone_internal 2353 * 2354 * Wrapper function that sends only one command to a given codec 2355 ****************************************************************************/ 2356static uint32_t 2357hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2358{ 2359 struct hdac_command_list cl; 2360 uint32_t response = HDAC_INVALID; 2361 2362 if (!hdac_lockowned(sc)) 2363 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2364 cl.num_commands = 1; 2365 cl.verbs = &verb; 2366 cl.responses = &response; 2367 2368 hdac_command_send_internal(sc, &cl, cad); 2369 2370 return (response); 2371} 2372 2373/**************************************************************************** 2374 * hdac_command_send_internal 2375 * 2376 * Send a command list to the codec via the corb. We queue as much verbs as 2377 * we can and msleep on the codec. When the interrupt get the responses 2378 * back from the rirb, it will wake us up so we can queue the remaining verbs 2379 * if any. 2380 ****************************************************************************/ 2381static void 2382hdac_command_send_internal(struct hdac_softc *sc, 2383 struct hdac_command_list *commands, nid_t cad) 2384{ 2385 struct hdac_codec *codec; 2386 int corbrp; 2387 uint32_t *corb; 2388 int timeout; 2389 int retry = 10; 2390 struct hdac_rirb *rirb_base; 2391 2392 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2393 commands->num_commands < 1) 2394 return; 2395 2396 codec = sc->codecs[cad]; 2397 codec->commands = commands; 2398 codec->responses_received = 0; 2399 codec->verbs_sent = 0; 2400 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2401 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2402 2403 do { 2404 if (codec->verbs_sent != commands->num_commands) { 2405 /* Queue as many verbs as possible */ 2406 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2407 bus_dmamap_sync(sc->corb_dma.dma_tag, 2408 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2409 while (codec->verbs_sent != commands->num_commands && 2410 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2411 sc->corb_wp++; 2412 sc->corb_wp %= sc->corb_size; 2413 corb[sc->corb_wp] = 2414 commands->verbs[codec->verbs_sent++]; 2415 } 2416 2417 /* Send the verbs to the codecs */ 2418 bus_dmamap_sync(sc->corb_dma.dma_tag, 2419 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2420 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2421 } 2422 2423 timeout = 1000; 2424 while (hdac_rirb_flush(sc) == 0 && --timeout) 2425 DELAY(10); 2426 } while ((codec->verbs_sent != commands->num_commands || 2427 codec->responses_received != commands->num_commands) && --retry); 2428 2429 if (retry == 0) 2430 device_printf(sc->dev, 2431 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2432 __func__, commands->num_commands, codec->verbs_sent, 2433 codec->responses_received); 2434 2435 codec->commands = NULL; 2436 codec->responses_received = 0; 2437 codec->verbs_sent = 0; 2438 2439 hdac_unsolq_flush(sc); 2440} 2441 2442 2443/**************************************************************************** 2444 * Device Methods 2445 ****************************************************************************/ 2446 2447/**************************************************************************** 2448 * int hdac_probe(device_t) 2449 * 2450 * Probe for the presence of an hdac. If none is found, check for a generic 2451 * match using the subclass of the device. 2452 ****************************************************************************/ 2453static int 2454hdac_probe(device_t dev) 2455{ 2456 int i, result; 2457 uint32_t model; 2458 uint16_t class, subclass; 2459 char desc[64]; 2460 2461 model = (uint32_t)pci_get_device(dev) << 16; 2462 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2463 class = pci_get_class(dev); 2464 subclass = pci_get_subclass(dev); 2465 2466 bzero(desc, sizeof(desc)); 2467 result = ENXIO; 2468 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2469 if (hdac_devices[i].model == model) { 2470 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2471 result = BUS_PROBE_DEFAULT; 2472 break; 2473 } 2474 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2475 class == PCIC_MULTIMEDIA && 2476 subclass == PCIS_MULTIMEDIA_HDA) { 2477 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2478 result = BUS_PROBE_GENERIC; 2479 break; 2480 } 2481 } 2482 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2483 subclass == PCIS_MULTIMEDIA_HDA) { 2484 strlcpy(desc, "Generic", sizeof(desc)); 2485 result = BUS_PROBE_GENERIC; 2486 } 2487 if (result != ENXIO) { 2488 strlcat(desc, " High Definition Audio Controller", 2489 sizeof(desc)); 2490 device_set_desc_copy(dev, desc); 2491 } 2492 2493 return (result); 2494} 2495 2496static void * 2497hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2498 struct pcm_channel *c, int dir) 2499{ 2500 struct hdac_devinfo *devinfo = data; 2501 struct hdac_softc *sc = devinfo->codec->sc; 2502 struct hdac_chan *ch; 2503 2504 hdac_lock(sc); 2505 if (dir == PCMDIR_PLAY) { 2506 ch = &sc->play; 2507 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2508 ch->dir = PCMDIR_PLAY; 2509 ch->sid = ++sc->streamcnt; 2510 devinfo->function.audio.playcnt++; 2511 } else { 2512 ch = &sc->rec; 2513 ch->off = devinfo->function.audio.reccnt << 5; 2514 ch->dir = PCMDIR_REC; 2515 ch->sid = ++sc->streamcnt; 2516 devinfo->function.audio.reccnt++; 2517 } 2518 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2519 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2520 ch->pcmrates[0] = 48000; 2521 ch->pcmrates[1] = 0; 2522 } 2523 ch->b = b; 2524 ch->c = c; 2525 ch->devinfo = devinfo; 2526 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2527 ch->blkcnt = sc->chan_blkcnt; 2528 hdac_unlock(sc); 2529 2530 if (hdac_bdl_alloc(ch) != 0) { 2531 ch->blkcnt = 0; 2532 return (NULL); 2533 } 2534 2535 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2536 return (NULL); 2537 2538 hdac_dma_nocache(ch->b->buf); 2539 2540 return (ch); 2541} 2542 2543static int 2544hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2545{ 2546 struct hdac_chan *ch = data; 2547 int i; 2548 2549 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2550 if (format == ch->caps.fmtlist[i]) { 2551 ch->fmt = format; 2552 return (0); 2553 } 2554 } 2555 2556 return (EINVAL); 2557} 2558 2559static int 2560hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2561{ 2562 struct hdac_chan *ch = data; 2563 uint32_t spd = 0, threshold; 2564 int i; 2565 2566 for (i = 0; ch->pcmrates[i] != 0; i++) { 2567 spd = ch->pcmrates[i]; 2568 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2569 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2570 if (speed < threshold) 2571 break; 2572 } 2573 2574 if (spd == 0) /* impossible */ 2575 ch->spd = 48000; 2576 else 2577 ch->spd = spd; 2578 2579 return (ch->spd); 2580} 2581 2582static void 2583hdac_stream_setup(struct hdac_chan *ch) 2584{ 2585 struct hdac_softc *sc = ch->devinfo->codec->sc; 2586 int i; 2587 nid_t cad = ch->devinfo->codec->cad; 2588 uint16_t fmt; 2589 2590 fmt = 0; 2591 if (ch->fmt & AFMT_S16_LE) 2592 fmt |= ch->bit16 << 4; 2593 else if (ch->fmt & AFMT_S32_LE) 2594 fmt |= ch->bit32 << 4; 2595 else 2596 fmt |= 1 << 4; 2597 2598 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2599 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2600 fmt |= hda_rate_tab[i].base; 2601 fmt |= hda_rate_tab[i].mul; 2602 fmt |= hda_rate_tab[i].div; 2603 break; 2604 } 2605 } 2606 2607 if (ch->fmt & AFMT_STEREO) 2608 fmt |= 1; 2609 2610 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2611 2612 for (i = 0; ch->io[i] != -1; i++) { 2613 HDA_BOOTVERBOSE( 2614 device_printf(sc->dev, 2615 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2616 "fmt=0x%08x\n", 2617 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2618 ch->io[i], fmt); 2619 ); 2620 hdac_command(sc, 2621 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2622 hdac_command(sc, 2623 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2624 ch->sid << 4), cad); 2625 } 2626} 2627 2628static int 2629hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2630{ 2631 struct hdac_chan *ch = data; 2632 struct hdac_softc *sc = ch->devinfo->codec->sc; 2633 2634 blksz &= ~0x7f; 2635 if (blksz < 0x80) 2636 blksz = 0x80; 2637 2638 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2639 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2640 2641 if ((sndbuf_getblksz(ch->b) != blksz || 2642 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2643 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2644 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2645 __func__, blksz, ch->blkcnt); 2646 2647 ch->blksz = sndbuf_getblksz(ch->b); 2648 2649 return (ch->blksz); 2650} 2651 2652static void 2653hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2654{ 2655 struct hdac_devinfo *devinfo = ch->devinfo; 2656 nid_t cad = devinfo->codec->cad; 2657 int i; 2658 2659 hdac_stream_stop(ch); 2660 2661 for (i = 0; ch->io[i] != -1; i++) { 2662 hdac_command(sc, 2663 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2664 0), cad); 2665 } 2666} 2667 2668static void 2669hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2670{ 2671 ch->ptr = 0; 2672 ch->prevptr = 0; 2673 hdac_stream_stop(ch); 2674 hdac_stream_reset(ch); 2675 hdac_bdl_setup(ch); 2676 hdac_stream_setid(ch); 2677 hdac_stream_setup(ch); 2678 hdac_stream_start(ch); 2679} 2680 2681static int 2682hdac_channel_trigger(kobj_t obj, void *data, int go) 2683{ 2684 struct hdac_chan *ch = data; 2685 struct hdac_softc *sc = ch->devinfo->codec->sc; 2686 2687 hdac_lock(sc); 2688 switch (go) { 2689 case PCMTRIG_START: 2690 hdac_channel_start(sc, ch); 2691 break; 2692 case PCMTRIG_STOP: 2693 case PCMTRIG_ABORT: 2694 hdac_channel_stop(sc, ch); 2695 break; 2696 } 2697 hdac_unlock(sc); 2698 2699 return (0); 2700} 2701 2702static int 2703hdac_channel_getptr(kobj_t obj, void *data) 2704{ 2705 struct hdac_chan *ch = data; 2706 struct hdac_softc *sc = ch->devinfo->codec->sc; 2707 uint32_t ptr; 2708 2709 hdac_lock(sc); 2710 if (sc->polling != 0) 2711 ptr = ch->ptr; 2712 else 2713 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2714 hdac_unlock(sc); 2715 2716 /* 2717 * Round to available space and force 128 bytes aligment. 2718 */ 2719 ptr %= ch->blksz * ch->blkcnt; 2720 ptr &= ~0x7f; 2721 2722 return (ptr); 2723} 2724 2725static struct pcmchan_caps * 2726hdac_channel_getcaps(kobj_t obj, void *data) 2727{ 2728 return (&((struct hdac_chan *)data)->caps); 2729} 2730 2731static kobj_method_t hdac_channel_methods[] = { 2732 KOBJMETHOD(channel_init, hdac_channel_init), 2733 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2734 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2735 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2736 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2737 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2738 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2739 { 0, 0 } 2740}; 2741CHANNEL_DECLARE(hdac_channel); 2742 2743static int 2744hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2745{ 2746 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2747 struct hdac_softc *sc = devinfo->codec->sc; 2748 struct hdac_widget *w, *cw; 2749 struct hdac_audio_ctl *ctl; 2750 uint32_t mask, recmask, id; 2751 int i, j, softpcmvol; 2752 nid_t cad; 2753 2754 hdac_lock(sc); 2755 2756 mask = 0; 2757 recmask = 0; 2758 2759 id = hdac_codec_id(devinfo); 2760 cad = devinfo->codec->cad; 2761 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2762 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2763 sc->pci_subvendor) && 2764 hdac_hp_switch[i].id == id)) 2765 continue; 2766 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2767 if (w != NULL && w->enable != 0 2768 && w->type == 2769 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2770 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2771 hdac_command(sc, 2772 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2773 w->nid, 2774 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2775 HDAC_UNSOLTAG_EVENT_HP), cad); 2776 hdac_hp_switch_handler(devinfo); 2777 HDA_BOOTVERBOSE( 2778 device_printf(sc->dev, 2779 "HDA_DEBUG: Enabling headphone/speaker " 2780 "audio routing switching:\n"); 2781 device_printf(sc->dev, 2782 "HDA_DEBUG: \tindex=%d nid=%d " 2783 "pci_subvendor=0x%08x " 2784 "codec=0x%08x\n", 2785 i, w->nid, sc->pci_subvendor, id); 2786 ); 2787 } 2788 break; 2789 } 2790 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2791 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2792 sc->pci_subvendor) && 2793 hdac_eapd_switch[i].id == id)) 2794 continue; 2795 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2796 if (w == NULL || w->enable == 0) 2797 break; 2798 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2799 w->param.eapdbtl == HDAC_INVALID) 2800 break; 2801 mask |= SOUND_MASK_OGAIN; 2802 break; 2803 } 2804 2805 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2806 w = hdac_widget_get(devinfo, i); 2807 if (w == NULL || w->enable == 0) 2808 continue; 2809 mask |= w->ctlflags; 2810 if (!(w->pflags & HDA_ADC_RECSEL)) 2811 continue; 2812 for (j = 0; j < w->nconns; j++) { 2813 cw = hdac_widget_get(devinfo, w->conns[j]); 2814 if (cw == NULL || cw->enable == 0) 2815 continue; 2816 recmask |= cw->ctlflags; 2817 } 2818 } 2819 2820 if (!(mask & SOUND_MASK_PCM)) { 2821 softpcmvol = 1; 2822 mask |= SOUND_MASK_PCM; 2823 } else 2824 softpcmvol = (devinfo->function.audio.quirks & 2825 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2826 2827 i = 0; 2828 ctl = NULL; 2829 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2830 if (ctl->widget == NULL || ctl->enable == 0) 2831 continue; 2832 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2833 continue; 2834 if (ctl->step > 0) 2835 break; 2836 } 2837 2838 if (softpcmvol == 1 || ctl == NULL) { 2839 struct snddev_info *d = NULL; 2840 d = device_get_softc(sc->dev); 2841 if (d != NULL) { 2842 d->flags |= SD_F_SOFTPCMVOL; 2843 HDA_BOOTVERBOSE( 2844 device_printf(sc->dev, 2845 "HDA_DEBUG: %s Soft PCM volume\n", 2846 (softpcmvol == 1) ? 2847 "Forcing" : "Enabling"); 2848 ); 2849 } 2850 i = 0; 2851 /* 2852 * XXX Temporary quirk for STAC9220, until the parser 2853 * become smarter. 2854 */ 2855 if (id == HDA_CODEC_STAC9220) { 2856 mask |= SOUND_MASK_VOLUME; 2857 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2858 NULL) { 2859 if (ctl->widget == NULL || ctl->enable == 0) 2860 continue; 2861 if (ctl->widget->nid == 11 && ctl->index == 0) { 2862 ctl->ossmask = SOUND_MASK_VOLUME; 2863 ctl->ossval = 100 | (100 << 8); 2864 } else 2865 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2866 } 2867 } else { 2868 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2869 SOUND_MASK_PCM); 2870 if (!(mask & SOUND_MASK_VOLUME)) 2871 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2872 SOUND_MIXER_NONE); 2873 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2874 NULL) { 2875 if (ctl->widget == NULL || ctl->enable == 0) 2876 continue; 2877 if (!HDA_FLAG_MATCH(ctl->ossmask, 2878 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2879 continue; 2880 if (!(ctl->mute == 1 && ctl->step == 0)) 2881 ctl->enable = 0; 2882 } 2883 } 2884 } 2885 2886 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2887 2888 mix_setrecdevs(m, recmask); 2889 mix_setdevs(m, mask); 2890 2891 hdac_unlock(sc); 2892 2893 return (0); 2894} 2895 2896static int 2897hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2898 unsigned left, unsigned right) 2899{ 2900 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2901 struct hdac_softc *sc = devinfo->codec->sc; 2902 struct hdac_widget *w; 2903 struct hdac_audio_ctl *ctl; 2904 uint32_t id, mute; 2905 int lvol, rvol, mlvol, mrvol; 2906 int i = 0; 2907 2908 hdac_lock(sc); 2909 if (dev == SOUND_MIXER_OGAIN) { 2910 uint32_t orig; 2911 /*if (left != right || !(left == 0 || left == 1)) { 2912 hdac_unlock(sc); 2913 return (-1); 2914 }*/ 2915 id = hdac_codec_id(devinfo); 2916 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2917 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2918 sc->pci_subvendor) && 2919 hdac_eapd_switch[i].id == id) 2920 break; 2921 } 2922 if (i >= HDAC_EAPD_SWITCH_LEN) { 2923 hdac_unlock(sc); 2924 return (-1); 2925 } 2926 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2927 if (w == NULL || 2928 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2929 w->param.eapdbtl == HDAC_INVALID) { 2930 hdac_unlock(sc); 2931 return (-1); 2932 } 2933 orig = w->param.eapdbtl; 2934 if (left == 0) 2935 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2936 else 2937 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2938 if (orig != w->param.eapdbtl) { 2939 uint32_t val; 2940 2941 if (hdac_eapd_switch[i].hp_switch != 0) 2942 hdac_hp_switch_handler(devinfo); 2943 val = w->param.eapdbtl; 2944 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2945 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2946 hdac_command(sc, 2947 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2948 w->nid, val), devinfo->codec->cad); 2949 } 2950 hdac_unlock(sc); 2951 return (left | (left << 8)); 2952 } 2953 if (dev == SOUND_MIXER_VOLUME) 2954 devinfo->function.audio.mvol = left | (right << 8); 2955 2956 mlvol = devinfo->function.audio.mvol & 0x7f; 2957 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2958 lvol = 0; 2959 rvol = 0; 2960 2961 i = 0; 2962 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2963 if (ctl->widget == NULL || ctl->enable == 0 || 2964 !(ctl->ossmask & (1 << dev))) 2965 continue; 2966 switch (dev) { 2967 case SOUND_MIXER_VOLUME: 2968 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2969 lvol = (lvol * ctl->step) / 100; 2970 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2971 rvol = (rvol * ctl->step) / 100; 2972 break; 2973 default: 2974 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2975 lvol = (left * mlvol) / 100; 2976 lvol = (lvol * ctl->step) / 100; 2977 rvol = (right * mrvol) / 100; 2978 rvol = (rvol * ctl->step) / 100; 2979 } else { 2980 lvol = (left * ctl->step) / 100; 2981 rvol = (right * ctl->step) / 100; 2982 } 2983 ctl->ossval = left | (right << 8); 2984 break; 2985 } 2986 mute = 0; 2987 if (ctl->step < 1) { 2988 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2989 (ctl->muted & HDA_AMP_MUTE_LEFT); 2990 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2991 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2992 } else { 2993 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2994 (ctl->muted & HDA_AMP_MUTE_LEFT); 2995 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2996 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2997 } 2998 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2999 } 3000 hdac_unlock(sc); 3001 3002 return (left | (right << 8)); 3003} 3004 3005static int 3006hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3007{ 3008 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3009 struct hdac_widget *w, *cw; 3010 struct hdac_softc *sc = devinfo->codec->sc; 3011 uint32_t ret = src, target; 3012 int i, j; 3013 3014 target = 0; 3015 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3016 if (src & (1 << i)) { 3017 target = 1 << i; 3018 break; 3019 } 3020 } 3021 3022 hdac_lock(sc); 3023 3024 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3025 w = hdac_widget_get(devinfo, i); 3026 if (w == NULL || w->enable == 0) 3027 continue; 3028 if (!(w->pflags & HDA_ADC_RECSEL)) 3029 continue; 3030 for (j = 0; j < w->nconns; j++) { 3031 cw = hdac_widget_get(devinfo, w->conns[j]); 3032 if (cw == NULL || cw->enable == 0) 3033 continue; 3034 if ((target == SOUND_MASK_VOLUME && 3035 cw->type != 3036 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3037 (target != SOUND_MASK_VOLUME && 3038 cw->type == 3039 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3040 continue; 3041 if (cw->ctlflags & target) { 3042 hdac_widget_connection_select(w, j); 3043 ret = target; 3044 j += w->nconns; 3045 } 3046 } 3047 } 3048 3049 hdac_unlock(sc); 3050 3051 return (ret); 3052} 3053 3054static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3055 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3056 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3057 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3058 { 0, 0 } 3059}; 3060MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3061 3062/**************************************************************************** 3063 * int hdac_attach(device_t) 3064 * 3065 * Attach the device into the kernel. Interrupts usually won't be enabled 3066 * when this function is called. Setup everything that doesn't require 3067 * interrupts and defer probing of codecs until interrupts are enabled. 3068 ****************************************************************************/ 3069static int 3070hdac_attach(device_t dev) 3071{ 3072 struct hdac_softc *sc; 3073 int result; 3074 int i = 0; 3075 3076 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3077 if (sc == NULL) { 3078 device_printf(dev, "cannot allocate softc\n"); 3079 return (ENOMEM); 3080 } 3081 3082 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3083 if (sc->lock == NULL) { 3084 device_printf(dev, "mutex creation failed\n"); 3085 free(sc, M_DEVBUF); 3086 return (ENOMEM); 3087 } 3088 3089 sc->dev = dev; 3090 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3091 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3092 3093 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3094 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3095 3096 sc->poll_ticks = 1; 3097 if (resource_int_value(device_get_name(sc->dev), 3098 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3099 sc->polling = 1; 3100 else 3101 sc->polling = 0; 3102 3103 sc->chan_size = pcm_getbuffersize(dev, 3104 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3105 3106 if (resource_int_value(device_get_name(sc->dev), 3107 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3108 i &= ~0x7f; 3109 if (i < 0x80) 3110 i = 0x80; 3111 sc->chan_blkcnt = sc->chan_size / i; 3112 i = 0; 3113 while (sc->chan_blkcnt >> i) 3114 i++; 3115 sc->chan_blkcnt = 1 << (i - 1); 3116 if (sc->chan_blkcnt < HDA_BDL_MIN) 3117 sc->chan_blkcnt = HDA_BDL_MIN; 3118 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3119 sc->chan_blkcnt = HDA_BDL_MAX; 3120 } else 3121 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3122 3123 result = bus_dma_tag_create(NULL, /* parent */ 3124 HDAC_DMA_ALIGNMENT, /* alignment */ 3125 0, /* boundary */ 3126 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3127 BUS_SPACE_MAXADDR, /* highaddr */ 3128 NULL, /* filtfunc */ 3129 NULL, /* fistfuncarg */ 3130 sc->chan_size, /* maxsize */ 3131 1, /* nsegments */ 3132 sc->chan_size, /* maxsegsz */ 3133 0, /* flags */ 3134 NULL, /* lockfunc */ 3135 NULL, /* lockfuncarg */ 3136 &sc->chan_dmat); /* dmat */ 3137 if (result != 0) { 3138 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3139 __func__, result); 3140 snd_mtxfree(sc->lock); 3141 free(sc, M_DEVBUF); 3142 return (ENXIO); 3143 } 3144 3145 3146 sc->hdabus = NULL; 3147 for (i = 0; i < HDAC_CODEC_MAX; i++) 3148 sc->codecs[i] = NULL; 3149 3150 pci_enable_busmaster(dev); 3151 3152 /* Allocate resources */ 3153 result = hdac_mem_alloc(sc); 3154 if (result != 0) 3155 goto hdac_attach_fail; 3156 result = hdac_irq_alloc(sc); 3157 if (result != 0) 3158 goto hdac_attach_fail; 3159 3160 /* Get Capabilities */ 3161 result = hdac_get_capabilities(sc); 3162 if (result != 0) 3163 goto hdac_attach_fail; 3164 3165 /* Allocate CORB and RIRB dma memory */ 3166 result = hdac_dma_alloc(sc, &sc->corb_dma, 3167 sc->corb_size * sizeof(uint32_t)); 3168 if (result != 0) 3169 goto hdac_attach_fail; 3170 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3171 sc->rirb_size * sizeof(struct hdac_rirb)); 3172 if (result != 0) 3173 goto hdac_attach_fail; 3174 3175 /* Quiesce everything */ 3176 hdac_reset(sc); 3177 3178 /* Disable PCI-Express QOS */ 3179 pci_write_config(sc->dev, 0x44, 3180 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3181 3182 /* Initialize the CORB and RIRB */ 3183 hdac_corb_init(sc); 3184 hdac_rirb_init(sc); 3185 3186 /* Defer remaining of initialization until interrupts are enabled */ 3187 sc->intrhook.ich_func = hdac_attach2; 3188 sc->intrhook.ich_arg = (void *)sc; 3189 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3190 sc->intrhook.ich_func = NULL; 3191 hdac_attach2((void *)sc); 3192 } 3193 3194 return (0); 3195 3196hdac_attach_fail: 3197 hdac_dma_free(&sc->rirb_dma); 3198 hdac_dma_free(&sc->corb_dma); 3199 hdac_irq_free(sc); 3200 hdac_mem_free(sc); 3201 snd_mtxfree(sc->lock); 3202 free(sc, M_DEVBUF); 3203 3204 return (ENXIO); 3205} 3206 3207static void 3208hdac_audio_parse(struct hdac_devinfo *devinfo) 3209{ 3210 struct hdac_softc *sc = devinfo->codec->sc; 3211 struct hdac_widget *w; 3212 uint32_t res; 3213 int i; 3214 nid_t cad, nid; 3215 3216 cad = devinfo->codec->cad; 3217 nid = devinfo->nid; 3218 3219 hdac_command(sc, 3220 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3221 3222 DELAY(100); 3223 3224 res = hdac_command(sc, 3225 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3226 3227 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3228 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3229 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3230 3231 HDA_BOOTVERBOSE( 3232 device_printf(sc->dev, " Vendor: 0x%08x\n", 3233 devinfo->vendor_id); 3234 device_printf(sc->dev, " Device: 0x%08x\n", 3235 devinfo->device_id); 3236 device_printf(sc->dev, " Revision: 0x%08x\n", 3237 devinfo->revision_id); 3238 device_printf(sc->dev, " Stepping: 0x%08x\n", 3239 devinfo->stepping_id); 3240 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3241 sc->pci_subvendor); 3242 device_printf(sc->dev, " Nodes: start=%d " 3243 "endnode=%d total=%d\n", 3244 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3245 ); 3246 3247 res = hdac_command(sc, 3248 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3249 cad); 3250 devinfo->function.audio.supp_stream_formats = res; 3251 3252 res = hdac_command(sc, 3253 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3254 cad); 3255 devinfo->function.audio.supp_pcm_size_rate = res; 3256 3257 res = hdac_command(sc, 3258 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3259 cad); 3260 devinfo->function.audio.outamp_cap = res; 3261 3262 res = hdac_command(sc, 3263 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3264 cad); 3265 devinfo->function.audio.inamp_cap = res; 3266 3267 if (devinfo->nodecnt > 0) { 3268 hdac_unlock(sc); 3269 devinfo->widget = (struct hdac_widget *)malloc( 3270 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3271 M_NOWAIT | M_ZERO); 3272 hdac_lock(sc); 3273 } else 3274 devinfo->widget = NULL; 3275 3276 if (devinfo->widget == NULL) { 3277 device_printf(sc->dev, "unable to allocate widgets!\n"); 3278 devinfo->endnode = devinfo->startnode; 3279 devinfo->nodecnt = 0; 3280 return; 3281 } 3282 3283 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3284 w = hdac_widget_get(devinfo, i); 3285 if (w == NULL) 3286 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3287 else { 3288 w->devinfo = devinfo; 3289 w->nid = i; 3290 w->enable = 1; 3291 w->selconn = -1; 3292 w->pflags = 0; 3293 w->ctlflags = 0; 3294 w->param.eapdbtl = HDAC_INVALID; 3295 hdac_widget_parse(w); 3296 } 3297 } 3298} 3299 3300static void 3301hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3302{ 3303 struct hdac_softc *sc = devinfo->codec->sc; 3304 struct hdac_audio_ctl *ctls; 3305 struct hdac_widget *w, *cw; 3306 int i, j, cnt, max, ocap, icap; 3307 int mute, offset, step, size; 3308 3309 /* XXX This is redundant */ 3310 max = 0; 3311 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3312 w = hdac_widget_get(devinfo, i); 3313 if (w == NULL || w->enable == 0) 3314 continue; 3315 if (w->param.outamp_cap != 0) 3316 max++; 3317 if (w->param.inamp_cap != 0) { 3318 switch (w->type) { 3319 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3320 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3321 for (j = 0; j < w->nconns; j++) { 3322 cw = hdac_widget_get(devinfo, 3323 w->conns[j]); 3324 if (cw == NULL || cw->enable == 0) 3325 continue; 3326 max++; 3327 } 3328 break; 3329 default: 3330 max++; 3331 break; 3332 } 3333 } 3334 } 3335 3336 devinfo->function.audio.ctlcnt = max; 3337 3338 if (max < 1) 3339 return; 3340 3341 hdac_unlock(sc); 3342 ctls = (struct hdac_audio_ctl *)malloc( 3343 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3344 hdac_lock(sc); 3345 3346 if (ctls == NULL) { 3347 /* Blekh! */ 3348 device_printf(sc->dev, "unable to allocate ctls!\n"); 3349 devinfo->function.audio.ctlcnt = 0; 3350 return; 3351 } 3352 3353 cnt = 0; 3354 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3355 if (cnt >= max) { 3356 device_printf(sc->dev, "%s: Ctl overflow!\n", 3357 __func__); 3358 break; 3359 } 3360 w = hdac_widget_get(devinfo, i); 3361 if (w == NULL || w->enable == 0) 3362 continue; 3363 ocap = w->param.outamp_cap; 3364 icap = w->param.inamp_cap; 3365 if (ocap != 0) { 3366 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3367 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3368 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3369 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3370 /*if (offset > step) { 3371 HDA_BOOTVERBOSE( 3372 device_printf(sc->dev, 3373 "HDA_DEBUG: BUGGY outamp: nid=%d " 3374 "[offset=%d > step=%d]\n", 3375 w->nid, offset, step); 3376 ); 3377 offset = step; 3378 }*/ 3379 ctls[cnt].enable = 1; 3380 ctls[cnt].widget = w; 3381 ctls[cnt].mute = mute; 3382 ctls[cnt].step = step; 3383 ctls[cnt].size = size; 3384 ctls[cnt].offset = offset; 3385 ctls[cnt].left = offset; 3386 ctls[cnt].right = offset; 3387 ctls[cnt++].dir = HDA_CTL_OUT; 3388 } 3389 3390 if (icap != 0) { 3391 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3392 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3393 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3394 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3395 /*if (offset > step) { 3396 HDA_BOOTVERBOSE( 3397 device_printf(sc->dev, 3398 "HDA_DEBUG: BUGGY inamp: nid=%d " 3399 "[offset=%d > step=%d]\n", 3400 w->nid, offset, step); 3401 ); 3402 offset = step; 3403 }*/ 3404 switch (w->type) { 3405 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3406 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3407 for (j = 0; j < w->nconns; j++) { 3408 if (cnt >= max) { 3409 device_printf(sc->dev, 3410 "%s: Ctl overflow!\n", 3411 __func__); 3412 break; 3413 } 3414 cw = hdac_widget_get(devinfo, 3415 w->conns[j]); 3416 if (cw == NULL || cw->enable == 0) 3417 continue; 3418 ctls[cnt].enable = 1; 3419 ctls[cnt].widget = w; 3420 ctls[cnt].childwidget = cw; 3421 ctls[cnt].index = j; 3422 ctls[cnt].mute = mute; 3423 ctls[cnt].step = step; 3424 ctls[cnt].size = size; 3425 ctls[cnt].offset = offset; 3426 ctls[cnt].left = offset; 3427 ctls[cnt].right = offset; 3428 ctls[cnt++].dir = HDA_CTL_IN; 3429 } 3430 break; 3431 default: 3432 if (cnt >= max) { 3433 device_printf(sc->dev, 3434 "%s: Ctl overflow!\n", 3435 __func__); 3436 break; 3437 } 3438 ctls[cnt].enable = 1; 3439 ctls[cnt].widget = w; 3440 ctls[cnt].mute = mute; 3441 ctls[cnt].step = step; 3442 ctls[cnt].size = size; 3443 ctls[cnt].offset = offset; 3444 ctls[cnt].left = offset; 3445 ctls[cnt].right = offset; 3446 ctls[cnt++].dir = HDA_CTL_IN; 3447 break; 3448 } 3449 } 3450 } 3451 3452 devinfo->function.audio.ctl = ctls; 3453} 3454 3455static const struct { 3456 uint32_t model; 3457 uint32_t id; 3458 uint32_t set, unset; 3459} hdac_quirks[] = { 3460 /* 3461 * XXX Force stereo quirk. Monoural recording / playback 3462 * on few codecs (especially ALC880) seems broken or 3463 * perhaps unsupported. 3464 */ 3465 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3466 HDA_QUIRK_FORCESTEREO, 0 }, 3467 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3468 HDA_QUIRK_GPIO0, 0 }, 3469 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3470 HDA_QUIRK_GPIO0, 0 }, 3471 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3472 HDA_QUIRK_GPIO1, 0 }, 3473 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3474 HDA_QUIRK_EAPDINV, 0 }, 3475 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3476 HDA_QUIRK_EAPDINV, 0 }, 3477 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3478 HDA_QUIRK_EAPDINV, 0 }, 3479 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3480 HDA_QUIRK_EAPDINV, 0 }, 3481 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3482 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3483 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3484 0, HDA_QUIRK_FORCESTEREO }, 3485 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3486 HDA_QUIRK_SOFTPCMVOL, 0 } 3487}; 3488#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3489 3490static void 3491hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3492{ 3493 struct hdac_widget *w; 3494 uint32_t id, subvendor; 3495 int i; 3496 3497 id = hdac_codec_id(devinfo); 3498 subvendor = devinfo->codec->sc->pci_subvendor; 3499 3500 /* 3501 * Quirks 3502 */ 3503 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3504 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3505 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3506 continue; 3507 if (hdac_quirks[i].set != 0) 3508 devinfo->function.audio.quirks |= 3509 hdac_quirks[i].set; 3510 if (hdac_quirks[i].unset != 0) 3511 devinfo->function.audio.quirks &= 3512 ~(hdac_quirks[i].unset); 3513 } 3514 3515 switch (id) { 3516 case HDA_CODEC_ALC260: 3517 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3518 w = hdac_widget_get(devinfo, i); 3519 if (w == NULL || w->enable == 0) 3520 continue; 3521 if (w->type != 3522 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3523 continue; 3524 if (w->nid != 5) 3525 w->enable = 0; 3526 } 3527 break; 3528 case HDA_CODEC_ALC880: 3529 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3530 w = hdac_widget_get(devinfo, i); 3531 if (w == NULL || w->enable == 0) 3532 continue; 3533 if (w->type == 3534 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3535 w->nid != 9 && w->nid != 29) { 3536 w->enable = 0; 3537 } else if (w->type != 3538 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3539 w->nid == 29) { 3540 w->type = 3541 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3542 w->param.widget_cap &= 3543 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3544 w->param.widget_cap |= 3545 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3546 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3547 strlcpy(w->name, "beep widget", sizeof(w->name)); 3548 } 3549 } 3550 break; 3551 case HDA_CODEC_AD1981HD: 3552 w = hdac_widget_get(devinfo, 11); 3553 if (w != NULL && w->enable != 0 && w->nconns > 3) 3554 w->selconn = 3; 3555 if (subvendor == IBM_M52_SUBVENDOR) { 3556 struct hdac_audio_ctl *ctl; 3557 3558 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3559 if (ctl != NULL) 3560 ctl->ossmask = SOUND_MASK_SPEAKER; 3561 } 3562 break; 3563 case HDA_CODEC_AD1986A: 3564 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3565 w = hdac_widget_get(devinfo, i); 3566 if (w == NULL || w->enable == 0) 3567 continue; 3568 if (w->type != 3569 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3570 continue; 3571 if (w->nid != 3) 3572 w->enable = 0; 3573 } 3574 break; 3575 case HDA_CODEC_STAC9221: 3576 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3577 w = hdac_widget_get(devinfo, i); 3578 if (w == NULL || w->enable == 0) 3579 continue; 3580 if (w->type != 3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3582 continue; 3583 if (w->nid != 2) 3584 w->enable = 0; 3585 } 3586 break; 3587 case HDA_CODEC_STAC9221D: 3588 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3589 w = hdac_widget_get(devinfo, i); 3590 if (w == NULL || w->enable == 0) 3591 continue; 3592 if (w->type == 3593 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3594 w->nid != 6) 3595 w->enable = 0; 3596 3597 } 3598 break; 3599 default: 3600 break; 3601 } 3602} 3603 3604static int 3605hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3606{ 3607 int *dev = &devinfo->function.audio.ossidx; 3608 3609 while (*dev < SOUND_MIXER_NRDEVICES) { 3610 switch (*dev) { 3611 case SOUND_MIXER_VOLUME: 3612 case SOUND_MIXER_BASS: 3613 case SOUND_MIXER_TREBLE: 3614 case SOUND_MIXER_PCM: 3615 case SOUND_MIXER_SPEAKER: 3616 case SOUND_MIXER_LINE: 3617 case SOUND_MIXER_MIC: 3618 case SOUND_MIXER_CD: 3619 case SOUND_MIXER_RECLEV: 3620 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3621 (*dev)++; 3622 break; 3623 default: 3624 return (*dev)++; 3625 break; 3626 } 3627 } 3628 3629 return (-1); 3630} 3631 3632static int 3633hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3634{ 3635 struct hdac_widget *w; 3636 int i, ret = 0; 3637 3638 if (depth > HDA_PARSE_MAXDEPTH) 3639 return (0); 3640 w = hdac_widget_get(devinfo, nid); 3641 if (w == NULL || w->enable == 0) 3642 return (0); 3643 switch (w->type) { 3644 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3645 w->pflags |= HDA_DAC_PATH; 3646 ret = 1; 3647 break; 3648 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3649 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3650 for (i = 0; i < w->nconns; i++) { 3651 if (hdac_widget_find_dac_path(devinfo, 3652 w->conns[i], depth + 1) != 0) { 3653 if (w->selconn == -1) 3654 w->selconn = i; 3655 ret = 1; 3656 w->pflags |= HDA_DAC_PATH; 3657 } 3658 } 3659 break; 3660 default: 3661 break; 3662 } 3663 return (ret); 3664} 3665 3666static int 3667hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3668{ 3669 struct hdac_widget *w; 3670 int i, conndev, ret = 0; 3671 3672 if (depth > HDA_PARSE_MAXDEPTH) 3673 return (0); 3674 w = hdac_widget_get(devinfo, nid); 3675 if (w == NULL || w->enable == 0) 3676 return (0); 3677 switch (w->type) { 3678 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3679 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3680 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3681 for (i = 0; i < w->nconns; i++) { 3682 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3683 depth + 1) != 0) { 3684 if (w->selconn == -1) 3685 w->selconn = i; 3686 w->pflags |= HDA_ADC_PATH; 3687 ret = 1; 3688 } 3689 } 3690 break; 3691 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3692 conndev = w->wclass.pin.config & 3693 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3694 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3695 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3696 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3697 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3698 w->pflags |= HDA_ADC_PATH; 3699 ret = 1; 3700 } 3701 break; 3702 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3703 if (w->pflags & HDA_DAC_PATH) { 3704 w->pflags |= HDA_ADC_PATH; 3705 ret = 1; 3706 } 3707 break;*/ 3708 default: 3709 break; 3710 } 3711 return (ret); 3712} 3713 3714static uint32_t 3715hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3716 nid_t nid, nid_t pnid, int index, int depth) 3717{ 3718 struct hdac_widget *w, *pw; 3719 struct hdac_audio_ctl *ctl; 3720 uint32_t fl = 0; 3721 int i, ossdev, conndev, strategy; 3722 3723 if (depth > HDA_PARSE_MAXDEPTH) 3724 return (0); 3725 3726 w = hdac_widget_get(devinfo, nid); 3727 if (w == NULL || w->enable == 0) 3728 return (0); 3729 3730 pw = hdac_widget_get(devinfo, pnid); 3731 strategy = devinfo->function.audio.parsing_strategy; 3732 3733 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3734 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3735 for (i = 0; i < w->nconns; i++) { 3736 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3737 w->nid, i, depth + 1); 3738 } 3739 w->ctlflags |= fl; 3740 return (fl); 3741 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3742 (w->pflags & HDA_DAC_PATH)) { 3743 i = 0; 3744 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3745 if (ctl->enable == 0 || ctl->widget == NULL) 3746 continue; 3747 /* XXX This should be compressed! */ 3748 if ((ctl->widget->nid == w->nid) || 3749 (ctl->widget->nid == pnid && ctl->index == index && 3750 (ctl->dir & HDA_CTL_IN)) || 3751 (ctl->widget->nid == pnid && pw != NULL && 3752 pw->type == 3753 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3754 (pw->nconns < 2 || pw->selconn == index || 3755 pw->selconn == -1) && 3756 (ctl->dir & HDA_CTL_OUT)) || 3757 (strategy == HDA_PARSE_DIRECT && 3758 ctl->widget->nid == w->nid)) { 3759 /*if (pw != NULL && pw->selconn == -1) 3760 pw->selconn = index; 3761 fl |= SOUND_MASK_VOLUME; 3762 fl |= SOUND_MASK_PCM; 3763 ctl->ossmask |= SOUND_MASK_VOLUME; 3764 ctl->ossmask |= SOUND_MASK_PCM; 3765 ctl->ossdev = SOUND_MIXER_PCM;*/ 3766 if (!(w->ctlflags & SOUND_MASK_PCM) || 3767 (pw != NULL && 3768 !(pw->ctlflags & SOUND_MASK_PCM))) { 3769 fl |= SOUND_MASK_VOLUME; 3770 fl |= SOUND_MASK_PCM; 3771 ctl->ossmask |= SOUND_MASK_VOLUME; 3772 ctl->ossmask |= SOUND_MASK_PCM; 3773 ctl->ossdev = SOUND_MIXER_PCM; 3774 w->ctlflags |= SOUND_MASK_VOLUME; 3775 w->ctlflags |= SOUND_MASK_PCM; 3776 if (pw != NULL) { 3777 if (pw->selconn == -1) 3778 pw->selconn = index; 3779 pw->ctlflags |= 3780 SOUND_MASK_VOLUME; 3781 pw->ctlflags |= 3782 SOUND_MASK_PCM; 3783 } 3784 } 3785 } 3786 } 3787 w->ctlflags |= fl; 3788 return (fl); 3789 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3790 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3791 (w->pflags & HDA_ADC_PATH)) { 3792 conndev = w->wclass.pin.config & 3793 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3794 i = 0; 3795 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3796 if (ctl->enable == 0 || ctl->widget == NULL) 3797 continue; 3798 /* XXX This should be compressed! */ 3799 if (((ctl->widget->nid == pnid && ctl->index == index && 3800 (ctl->dir & HDA_CTL_IN)) || 3801 (ctl->widget->nid == pnid && pw != NULL && 3802 pw->type == 3803 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3804 (pw->nconns < 2 || pw->selconn == index || 3805 pw->selconn == -1) && 3806 (ctl->dir & HDA_CTL_OUT)) || 3807 (strategy == HDA_PARSE_DIRECT && 3808 ctl->widget->nid == w->nid)) && 3809 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3810 if (pw != NULL && pw->selconn == -1) 3811 pw->selconn = index; 3812 ossdev = 0; 3813 switch (conndev) { 3814 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3815 ossdev = SOUND_MIXER_MIC; 3816 break; 3817 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3818 ossdev = SOUND_MIXER_LINE; 3819 break; 3820 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3821 ossdev = SOUND_MIXER_CD; 3822 break; 3823 default: 3824 ossdev = 3825 hdac_audio_ctl_ossmixer_getnextdev( 3826 devinfo); 3827 if (ossdev < 0) 3828 ossdev = 0; 3829 break; 3830 } 3831 if (strategy == HDA_PARSE_MIXER) { 3832 fl |= SOUND_MASK_VOLUME; 3833 ctl->ossmask |= SOUND_MASK_VOLUME; 3834 } 3835 fl |= 1 << ossdev; 3836 ctl->ossmask |= 1 << ossdev; 3837 ctl->ossdev = ossdev; 3838 } 3839 } 3840 w->ctlflags |= fl; 3841 return (fl); 3842 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3843 i = 0; 3844 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3845 if (ctl->enable == 0 || ctl->widget == NULL) 3846 continue; 3847 /* XXX This should be compressed! */ 3848 if (((ctl->widget->nid == pnid && ctl->index == index && 3849 (ctl->dir & HDA_CTL_IN)) || 3850 (ctl->widget->nid == pnid && pw != NULL && 3851 pw->type == 3852 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3853 (pw->nconns < 2 || pw->selconn == index || 3854 pw->selconn == -1) && 3855 (ctl->dir & HDA_CTL_OUT)) || 3856 (strategy == HDA_PARSE_DIRECT && 3857 ctl->widget->nid == w->nid)) && 3858 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3859 if (pw != NULL && pw->selconn == -1) 3860 pw->selconn = index; 3861 fl |= SOUND_MASK_VOLUME; 3862 fl |= SOUND_MASK_SPEAKER; 3863 ctl->ossmask |= SOUND_MASK_VOLUME; 3864 ctl->ossmask |= SOUND_MASK_SPEAKER; 3865 ctl->ossdev = SOUND_MIXER_SPEAKER; 3866 } 3867 } 3868 w->ctlflags |= fl; 3869 return (fl); 3870 } 3871 return (0); 3872} 3873 3874static uint32_t 3875hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3876{ 3877 struct hdac_widget *w, *cw; 3878 struct hdac_audio_ctl *ctl; 3879 uint32_t fl; 3880 int i; 3881 3882 if (depth > HDA_PARSE_MAXDEPTH) 3883 return (0); 3884 3885 w = hdac_widget_get(devinfo, nid); 3886 if (w == NULL || w->enable == 0) 3887 return (0); 3888 /*if (!(w->pflags & HDA_ADC_PATH)) 3889 return (0); 3890 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3891 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3892 return (0);*/ 3893 i = 0; 3894 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3895 if (ctl->enable == 0 || ctl->widget == NULL) 3896 continue; 3897 if (ctl->widget->nid == nid) { 3898 ctl->ossmask |= SOUND_MASK_RECLEV; 3899 w->ctlflags |= SOUND_MASK_RECLEV; 3900 return (SOUND_MASK_RECLEV); 3901 } 3902 } 3903 for (i = 0; i < w->nconns; i++) { 3904 cw = hdac_widget_get(devinfo, w->conns[i]); 3905 if (cw == NULL || cw->enable == 0) 3906 continue; 3907 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3908 continue; 3909 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3910 if (fl != 0) { 3911 cw->ctlflags |= fl; 3912 w->ctlflags |= fl; 3913 return (fl); 3914 } 3915 } 3916 return (0); 3917} 3918 3919static int 3920hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3921{ 3922 struct hdac_widget *w, *cw; 3923 int i, child = 0; 3924 3925 if (depth > HDA_PARSE_MAXDEPTH) 3926 return (0); 3927 3928 w = hdac_widget_get(devinfo, nid); 3929 if (w == NULL || w->enable == 0) 3930 return (0); 3931 /*if (!(w->pflags & HDA_ADC_PATH)) 3932 return (0); 3933 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3934 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3935 return (0);*/ 3936 /* XXX weak! */ 3937 for (i = 0; i < w->nconns; i++) { 3938 cw = hdac_widget_get(devinfo, w->conns[i]); 3939 if (cw == NULL) 3940 continue; 3941 if (++child > 1) { 3942 w->pflags |= HDA_ADC_RECSEL; 3943 return (1); 3944 } 3945 } 3946 for (i = 0; i < w->nconns; i++) { 3947 if (hdac_audio_ctl_recsel_build(devinfo, 3948 w->conns[i], depth + 1) != 0) 3949 return (1); 3950 } 3951 return (0); 3952} 3953 3954static int 3955hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3956{ 3957 struct hdac_widget *w, *cw; 3958 int i, j, conndev, found_dac = 0; 3959 int strategy; 3960 3961 strategy = devinfo->function.audio.parsing_strategy; 3962 3963 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3964 w = hdac_widget_get(devinfo, i); 3965 if (w == NULL || w->enable == 0) 3966 continue; 3967 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3968 continue; 3969 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3970 continue; 3971 conndev = w->wclass.pin.config & 3972 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3973 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3974 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3975 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3976 continue; 3977 for (j = 0; j < w->nconns; j++) { 3978 cw = hdac_widget_get(devinfo, w->conns[j]); 3979 if (cw == NULL || cw->enable == 0) 3980 continue; 3981 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3982 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3983 cw->type == 3984 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3985 continue; 3986 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3987 != 0) { 3988 if (w->selconn == -1) 3989 w->selconn = j; 3990 w->pflags |= HDA_DAC_PATH; 3991 found_dac++; 3992 } 3993 } 3994 } 3995 3996 return (found_dac); 3997} 3998 3999static void 4000hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4001{ 4002 struct hdac_widget *w; 4003 struct hdac_audio_ctl *ctl; 4004 int i, j, dacs, strategy; 4005 4006 /* Construct DAC path */ 4007 strategy = HDA_PARSE_MIXER; 4008 devinfo->function.audio.parsing_strategy = strategy; 4009 HDA_BOOTVERBOSE( 4010 device_printf(devinfo->codec->sc->dev, 4011 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4012 HDA_WIDGET_PARSER_REV); 4013 ); 4014 dacs = hdac_audio_build_tree_strategy(devinfo); 4015 if (dacs == 0) { 4016 HDA_BOOTVERBOSE( 4017 device_printf(devinfo->codec->sc->dev, 4018 "HDA_DEBUG: HWiP: 0 DAC path found! " 4019 "Retrying parser " 4020 "using HDA_PARSE_DIRECT strategy.\n"); 4021 ); 4022 strategy = HDA_PARSE_DIRECT; 4023 devinfo->function.audio.parsing_strategy = strategy; 4024 dacs = hdac_audio_build_tree_strategy(devinfo); 4025 } 4026 4027 HDA_BOOTVERBOSE( 4028 device_printf(devinfo->codec->sc->dev, 4029 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4030 "strategy.\n", 4031 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4032 ); 4033 4034 /* Construct ADC path */ 4035 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4036 w = hdac_widget_get(devinfo, i); 4037 if (w == NULL || w->enable == 0) 4038 continue; 4039 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4040 continue; 4041 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4042 } 4043 4044 /* Output mixers */ 4045 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4046 w = hdac_widget_get(devinfo, i); 4047 if (w == NULL || w->enable == 0) 4048 continue; 4049 if ((strategy == HDA_PARSE_MIXER && 4050 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4051 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4052 && (w->pflags & HDA_DAC_PATH)) || 4053 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4054 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4055 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4056 w->nid, devinfo->startnode - 1, 0, 0); 4057 } else if (w->type == 4058 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4059 j = 0; 4060 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4061 NULL) { 4062 if (ctl->enable == 0 || ctl->widget == NULL) 4063 continue; 4064 if (ctl->widget->nid != w->nid) 4065 continue; 4066 ctl->ossmask |= SOUND_MASK_VOLUME; 4067 ctl->ossmask |= SOUND_MASK_SPEAKER; 4068 ctl->ossdev = SOUND_MIXER_SPEAKER; 4069 w->ctlflags |= SOUND_MASK_VOLUME; 4070 w->ctlflags |= SOUND_MASK_SPEAKER; 4071 } 4072 } 4073 } 4074 4075 /* Input mixers (rec) */ 4076 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4077 w = hdac_widget_get(devinfo, i); 4078 if (w == NULL || w->enable == 0) 4079 continue; 4080 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4081 w->pflags & HDA_ADC_PATH)) 4082 continue; 4083 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4084 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4085 } 4086} 4087 4088#define HDA_COMMIT_CONN (1 << 0) 4089#define HDA_COMMIT_CTRL (1 << 1) 4090#define HDA_COMMIT_EAPD (1 << 2) 4091#define HDA_COMMIT_GPIO (1 << 3) 4092#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4093 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4094 4095static void 4096hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4097{ 4098 struct hdac_softc *sc = devinfo->codec->sc; 4099 struct hdac_widget *w; 4100 nid_t cad; 4101 int i; 4102 4103 if (!(cfl & HDA_COMMIT_ALL)) 4104 return; 4105 4106 cad = devinfo->codec->cad; 4107 4108 if (cfl & HDA_COMMIT_GPIO) { 4109 uint32_t gdata, gmask, gdir; 4110 int commitgpio = 0; 4111 4112 gdata = 0; 4113 gmask = 0; 4114 gdir = 0; 4115 4116 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4117 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4118 0x7e7, 0), cad); 4119 4120 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4121 commitgpio = 1; 4122 else { 4123 for (i = 0; i < HDA_GPIO_MAX; i++) { 4124 if (!(devinfo->function.audio.quirks & 4125 (1 << i))) 4126 continue; 4127 if (commitgpio == 0) { 4128 commitgpio = 1; 4129 gdata = hdac_command(sc, 4130 HDA_CMD_GET_GPIO_DATA(cad, 4131 devinfo->nid), cad); 4132 gmask = hdac_command(sc, 4133 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4134 devinfo->nid), cad); 4135 gdir = hdac_command(sc, 4136 HDA_CMD_GET_GPIO_DIRECTION(cad, 4137 devinfo->nid), cad); 4138 HDA_BOOTVERBOSE( 4139 device_printf(sc->dev, 4140 "GPIO init: data=0x%08x " 4141 "mask=0x%08x dir=0x%08x\n", 4142 gdata, gmask, gdir); 4143 ); 4144 } 4145 gdata |= 1 << i; 4146 gmask |= 1 << i; 4147 gdir |= 1 << i; 4148 } 4149 } 4150 4151 if (commitgpio != 0) { 4152 HDA_BOOTVERBOSE( 4153 device_printf(sc->dev, 4154 "GPIO commit: data=0x%08x mask=0x%08x " 4155 "dir=0x%08x\n", 4156 gdata, gmask, gdir); 4157 ); 4158 hdac_command(sc, 4159 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4160 gmask), cad); 4161 hdac_command(sc, 4162 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4163 gdir), cad); 4164 hdac_command(sc, 4165 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4166 gdata), cad); 4167 } 4168 } 4169 4170 for (i = 0; i < devinfo->nodecnt; i++) { 4171 w = &devinfo->widget[i]; 4172 if (w == NULL || w->enable == 0) 4173 continue; 4174 if (cfl & HDA_COMMIT_CONN) { 4175 if (w->selconn == -1) 4176 w->selconn = 0; 4177 if (w->nconns > 0) 4178 hdac_widget_connection_select(w, w->selconn); 4179 } 4180 if ((cfl & HDA_COMMIT_CTRL) && 4181 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4182 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4183 (HDA_DAC_PATH | HDA_ADC_PATH)) 4184 device_printf(sc->dev, "WARNING: node %d " 4185 "participate both for DAC/ADC!\n", w->nid); 4186 if (w->pflags & HDA_DAC_PATH) { 4187 w->wclass.pin.ctrl &= 4188 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4189 if ((w->wclass.pin.config & 4190 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4191 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4192 w->wclass.pin.ctrl &= 4193 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4194 } else if (w->pflags & HDA_ADC_PATH) { 4195 w->wclass.pin.ctrl &= 4196 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4197 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4198 } else 4199 w->wclass.pin.ctrl &= ~( 4200 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4201 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4202 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 4203 hdac_command(sc, 4204 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4205 w->wclass.pin.ctrl), cad); 4206 } 4207 if ((cfl & HDA_COMMIT_EAPD) && 4208 w->param.eapdbtl != HDAC_INVALID) { 4209 uint32_t val; 4210 4211 val = w->param.eapdbtl; 4212 if (devinfo->function.audio.quirks & 4213 HDA_QUIRK_EAPDINV) 4214 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4215 hdac_command(sc, 4216 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4217 val), cad); 4218 4219 } 4220 DELAY(1000); 4221 } 4222} 4223 4224static void 4225hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4226{ 4227 struct hdac_softc *sc = devinfo->codec->sc; 4228 struct hdac_audio_ctl *ctl; 4229 int i; 4230 4231 devinfo->function.audio.mvol = 100 | (100 << 8); 4232 i = 0; 4233 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4234 if (ctl->enable == 0 || ctl->widget == NULL) { 4235 HDA_BOOTVERBOSE( 4236 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4237 i, (ctl->widget != NULL) ? 4238 ctl->widget->nid : -1); 4239 if (ctl->childwidget != NULL) 4240 printf(" childnid=%d", 4241 ctl->childwidget->nid); 4242 if (ctl->widget == NULL) 4243 printf(" NULL WIDGET!"); 4244 printf(" DISABLED\n"); 4245 ); 4246 continue; 4247 } 4248 HDA_BOOTVERBOSE( 4249 if (ctl->ossmask == 0) { 4250 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4251 i, ctl->widget->nid); 4252 if (ctl->childwidget != NULL) 4253 printf(" childnid=%d", 4254 ctl->childwidget->nid); 4255 printf(" Bind to NONE\n"); 4256 } 4257 ); 4258 if (ctl->step > 0) { 4259 ctl->ossval = (ctl->left * 100) / ctl->step; 4260 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4261 } else 4262 ctl->ossval = 0; 4263 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4264 ctl->left, ctl->right); 4265 } 4266} 4267 4268static int 4269hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4270{ 4271 struct hdac_chan *ch; 4272 struct hdac_widget *w; 4273 uint32_t cap, fmtcap, pcmcap, path; 4274 int i, type, ret, max; 4275 4276 if (dir == PCMDIR_PLAY) { 4277 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4278 ch = &devinfo->codec->sc->play; 4279 path = HDA_DAC_PATH; 4280 } else { 4281 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4282 ch = &devinfo->codec->sc->rec; 4283 path = HDA_ADC_PATH; 4284 } 4285 4286 ch->caps = hdac_caps; 4287 ch->caps.fmtlist = ch->fmtlist; 4288 ch->bit16 = 1; 4289 ch->bit32 = 0; 4290 ch->pcmrates[0] = 48000; 4291 ch->pcmrates[1] = 0; 4292 4293 ret = 0; 4294 fmtcap = devinfo->function.audio.supp_stream_formats; 4295 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4296 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4297 4298 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4299 w = hdac_widget_get(devinfo, i); 4300 if (w == NULL || w->enable == 0 || w->type != type || 4301 !(w->pflags & path)) 4302 continue; 4303 cap = w->param.widget_cap; 4304 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4305 continue;*/ 4306 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4307 continue; 4308 cap = w->param.supp_stream_formats; 4309 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4310 } 4311 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4312 }*/ 4313 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4314 continue; 4315 if (ret == 0) { 4316 fmtcap = w->param.supp_stream_formats; 4317 pcmcap = w->param.supp_pcm_size_rate; 4318 } else { 4319 fmtcap &= w->param.supp_stream_formats; 4320 pcmcap &= w->param.supp_pcm_size_rate; 4321 } 4322 ch->io[ret++] = i; 4323 } 4324 ch->io[ret] = -1; 4325 4326 ch->supp_stream_formats = fmtcap; 4327 ch->supp_pcm_size_rate = pcmcap; 4328 4329 /* 4330 * 8bit = 0 4331 * 16bit = 1 4332 * 20bit = 2 4333 * 24bit = 3 4334 * 32bit = 4 4335 */ 4336 if (ret > 0) { 4337 cap = pcmcap; 4338 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4339 ch->bit16 = 1; 4340 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4341 ch->bit16 = 0; 4342 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4343 ch->bit32 = 4; 4344 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4345 ch->bit32 = 3; 4346 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4347 ch->bit32 = 2; 4348 i = 0; 4349 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4350 ch->fmtlist[i++] = AFMT_S16_LE; 4351 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4352 if (ch->bit32 > 0) { 4353 if (!(devinfo->function.audio.quirks & 4354 HDA_QUIRK_FORCESTEREO)) 4355 ch->fmtlist[i++] = AFMT_S32_LE; 4356 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4357 } 4358 ch->fmtlist[i] = 0; 4359 i = 0; 4360 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4361 ch->pcmrates[i++] = 8000; 4362 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4363 ch->pcmrates[i++] = 11025; 4364 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4365 ch->pcmrates[i++] = 16000; 4366 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4367 ch->pcmrates[i++] = 22050; 4368 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4369 ch->pcmrates[i++] = 32000; 4370 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4371 ch->pcmrates[i++] = 44100; 4372 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4373 ch->pcmrates[i++] = 48000; 4374 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4375 ch->pcmrates[i++] = 88200; 4376 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4377 ch->pcmrates[i++] = 96000; 4378 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4379 ch->pcmrates[i++] = 176400; 4380 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4381 ch->pcmrates[i++] = 192000; 4382 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4383 ch->pcmrates[i] = 0; 4384 if (i > 0) { 4385 ch->caps.minspeed = ch->pcmrates[0]; 4386 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4387 } 4388 } 4389 4390 return (ret); 4391} 4392 4393static void 4394hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4395{ 4396 struct hdac_audio_ctl *ctl; 4397 struct hdac_softc *sc = devinfo->codec->sc; 4398 int i; 4399 uint32_t fl = 0; 4400 4401 4402 if (flag == 0) { 4403 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4404 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4405 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4406 } 4407 4408 i = 0; 4409 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4410 if (ctl->enable == 0 || ctl->widget == NULL || 4411 ctl->widget->enable == 0) 4412 continue; 4413 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4414 (flag != 0 && (ctl->ossmask & flag))) { 4415 if (banner != NULL) { 4416 device_printf(sc->dev, "\n"); 4417 device_printf(sc->dev, "%s\n", banner); 4418 } 4419 goto hdac_ctl_dump_it_all; 4420 } 4421 } 4422 4423 return; 4424 4425hdac_ctl_dump_it_all: 4426 i = 0; 4427 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4428 if (ctl->enable == 0 || ctl->widget == NULL || 4429 ctl->widget->enable == 0) 4430 continue; 4431 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4432 (flag != 0 && (ctl->ossmask & flag)))) 4433 continue; 4434 if (flag == 0) { 4435 device_printf(sc->dev, "\n"); 4436 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4437 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4438 } 4439 device_printf(sc->dev, " |\n"); 4440 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4441 ctl->widget->nid, ctl->index); 4442 if (ctl->childwidget != NULL) 4443 printf("(nid: %2d) ", ctl->childwidget->nid); 4444 else 4445 printf(" "); 4446 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4447 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4448 ctl->ossmask); 4449 } 4450} 4451 4452static void 4453hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4454{ 4455 uint32_t cap; 4456 4457 cap = fcap; 4458 if (cap != 0) { 4459 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4460 device_printf(sc->dev, " Format:"); 4461 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4462 printf(" AC3"); 4463 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4464 printf(" FLOAT32"); 4465 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4466 printf(" PCM"); 4467 printf("\n"); 4468 } 4469 cap = pcmcap; 4470 if (cap != 0) { 4471 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4472 device_printf(sc->dev, " PCM size:"); 4473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4474 printf(" 8"); 4475 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4476 printf(" 16"); 4477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4478 printf(" 20"); 4479 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4480 printf(" 24"); 4481 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4482 printf(" 32"); 4483 printf("\n"); 4484 device_printf(sc->dev, " PCM rate:"); 4485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4486 printf(" 8"); 4487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4488 printf(" 11"); 4489 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4490 printf(" 16"); 4491 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4492 printf(" 22"); 4493 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4494 printf(" 32"); 4495 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4496 printf(" 44"); 4497 printf(" 48"); 4498 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4499 printf(" 88"); 4500 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4501 printf(" 96"); 4502 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4503 printf(" 176"); 4504 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4505 printf(" 192"); 4506 printf("\n"); 4507 } 4508} 4509 4510static void 4511hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4512{ 4513 uint32_t pincap, wcap; 4514 4515 pincap = w->wclass.pin.cap; 4516 wcap = w->param.widget_cap; 4517 4518 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4519 device_printf(sc->dev, " "); 4520 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4521 printf(" ISC"); 4522 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4523 printf(" TRQD"); 4524 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4525 printf(" PDC"); 4526 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4527 printf(" HP"); 4528 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4529 printf(" OUT"); 4530 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4531 printf(" IN"); 4532 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4533 printf(" BAL"); 4534 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4535 printf(" EAPD"); 4536 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4537 printf(" : UNSOL"); 4538 printf("\n"); 4539 device_printf(sc->dev, " Pin config: 0x%08x\n", 4540 w->wclass.pin.config); 4541 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4542 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4543 printf(" HP"); 4544 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4545 printf(" IN"); 4546 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4547 printf(" OUT"); 4548 printf("\n"); 4549} 4550 4551static void 4552hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4553{ 4554 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4555 device_printf(sc->dev, " " 4556 "mute=%d step=%d size=%d offset=%d\n", 4557 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4558 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4559 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4560 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4561} 4562 4563static void 4564hdac_dump_nodes(struct hdac_devinfo *devinfo) 4565{ 4566 struct hdac_softc *sc = devinfo->codec->sc; 4567 struct hdac_widget *w, *cw; 4568 int i, j; 4569 4570 device_printf(sc->dev, "\n"); 4571 device_printf(sc->dev, "Default Parameter\n"); 4572 device_printf(sc->dev, "-----------------\n"); 4573 hdac_dump_audio_formats(sc, 4574 devinfo->function.audio.supp_stream_formats, 4575 devinfo->function.audio.supp_pcm_size_rate); 4576 device_printf(sc->dev, " IN amp: 0x%08x\n", 4577 devinfo->function.audio.inamp_cap); 4578 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4579 devinfo->function.audio.outamp_cap); 4580 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4581 w = hdac_widget_get(devinfo, i); 4582 if (w == NULL) { 4583 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4584 continue; 4585 } 4586 device_printf(sc->dev, "\n"); 4587 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4588 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4589 "DIGITAL" : "ANALOG", 4590 (w->enable == 0) ? " [DISABLED]" : ""); 4591 device_printf(sc->dev, " name: %s\n", w->name); 4592 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4593 w->param.widget_cap); 4594 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4595 w->pflags); 4596 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4597 w->ctlflags); 4598 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4599 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4600 hdac_dump_audio_formats(sc, 4601 w->param.supp_stream_formats, 4602 w->param.supp_pcm_size_rate); 4603 } else if (w->type == 4604 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4605 hdac_dump_pin(sc, w); 4606 if (w->param.eapdbtl != HDAC_INVALID) 4607 device_printf(sc->dev, " EAPD: 0x%08x\n", 4608 w->param.eapdbtl); 4609 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4610 w->param.outamp_cap != 0) 4611 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4612 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4613 w->param.inamp_cap != 0) 4614 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4615 device_printf(sc->dev, " connections: %d\n", w->nconns); 4616 for (j = 0; j < w->nconns; j++) { 4617 cw = hdac_widget_get(devinfo, w->conns[j]); 4618 device_printf(sc->dev, " |\n"); 4619 device_printf(sc->dev, " + <- nid=%d [%s]", 4620 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4621 if (cw == NULL) 4622 printf(" [UNKNOWN]"); 4623 else if (cw->enable == 0) 4624 printf(" [DISABLED]"); 4625 if (w->nconns > 1 && w->selconn == j && w->type != 4626 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4627 printf(" (selected)"); 4628 printf("\n"); 4629 } 4630 } 4631 4632} 4633 4634static int 4635hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4636{ 4637 struct hdac_widget *w, *cw; 4638 struct hdac_softc *sc = devinfo->codec->sc; 4639 int i; 4640 4641 if (depth > HDA_PARSE_MAXDEPTH) 4642 return (0); 4643 4644 w = hdac_widget_get(devinfo, nid); 4645 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4646 return (0); 4647 4648 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4649 device_printf(sc->dev, "\n"); 4650 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4651 device_printf(sc->dev, " ^\n"); 4652 device_printf(sc->dev, " |\n"); 4653 device_printf(sc->dev, " +-----<------+\n"); 4654 } else { 4655 device_printf(sc->dev, " ^\n"); 4656 device_printf(sc->dev, " |\n"); 4657 device_printf(sc->dev, " "); 4658 printf(" nid=%d [%s]\n", w->nid, w->name); 4659 } 4660 4661 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4662 return (1); 4663 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4664 for (i = 0; i < w->nconns; i++) { 4665 cw = hdac_widget_get(devinfo, w->conns[i]); 4666 if (cw == NULL || cw->enable == 0 || cw->type == 4667 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4668 continue; 4669 if (hdac_dump_dac_internal(devinfo, cw->nid, 4670 depth + 1) != 0) 4671 return (1); 4672 } 4673 } else if ((w->type == 4674 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4675 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4676 w->selconn > -1 && w->selconn < w->nconns) { 4677 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4678 depth + 1) != 0) 4679 return (1); 4680 } 4681 4682 return (0); 4683} 4684 4685static void 4686hdac_dump_dac(struct hdac_devinfo *devinfo) 4687{ 4688 struct hdac_widget *w; 4689 struct hdac_softc *sc = devinfo->codec->sc; 4690 int i, printed = 0; 4691 4692 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4693 w = hdac_widget_get(devinfo, i); 4694 if (w == NULL || w->enable == 0) 4695 continue; 4696 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4697 !(w->pflags & HDA_DAC_PATH)) 4698 continue; 4699 if (printed == 0) { 4700 printed = 1; 4701 device_printf(sc->dev, "\n"); 4702 device_printf(sc->dev, "Playback path:\n"); 4703 } 4704 hdac_dump_dac_internal(devinfo, w->nid, 0); 4705 } 4706} 4707 4708static void 4709hdac_dump_adc(struct hdac_devinfo *devinfo) 4710{ 4711 struct hdac_widget *w, *cw; 4712 struct hdac_softc *sc = devinfo->codec->sc; 4713 int i, j; 4714 int printed = 0; 4715 char ossdevs[256]; 4716 4717 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4718 w = hdac_widget_get(devinfo, i); 4719 if (w == NULL || w->enable == 0) 4720 continue; 4721 if (!(w->pflags & HDA_ADC_RECSEL)) 4722 continue; 4723 if (printed == 0) { 4724 printed = 1; 4725 device_printf(sc->dev, "\n"); 4726 device_printf(sc->dev, "Recording sources:\n"); 4727 } 4728 device_printf(sc->dev, "\n"); 4729 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4730 for (j = 0; j < w->nconns; j++) { 4731 cw = hdac_widget_get(devinfo, w->conns[j]); 4732 if (cw == NULL || cw->enable == 0) 4733 continue; 4734 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4735 ossdevs, sizeof(ossdevs)); 4736 device_printf(sc->dev, " |\n"); 4737 device_printf(sc->dev, " + <- nid=%d [%s]", 4738 cw->nid, cw->name); 4739 if (strlen(ossdevs) > 0) { 4740 printf(" [recsrc: %s]", ossdevs); 4741 } 4742 printf("\n"); 4743 } 4744 } 4745} 4746 4747static void 4748hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4749{ 4750 nid_t *nids; 4751 4752 if (pcnt > 0) { 4753 device_printf(sc->dev, "\n"); 4754 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4755 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4756 sc->play.supp_pcm_size_rate); 4757 device_printf(sc->dev, " DAC:"); 4758 for (nids = sc->play.io; *nids != -1; nids++) 4759 printf(" %d", *nids); 4760 printf("\n"); 4761 } 4762 4763 if (rcnt > 0) { 4764 device_printf(sc->dev, "\n"); 4765 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4766 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4767 sc->rec.supp_pcm_size_rate); 4768 device_printf(sc->dev, " ADC:"); 4769 for (nids = sc->rec.io; *nids != -1; nids++) 4770 printf(" %d", *nids); 4771 printf("\n"); 4772 } 4773} 4774 4775static void 4776hdac_release_resources(struct hdac_softc *sc) 4777{ 4778 struct hdac_devinfo *devinfo = NULL; 4779 device_t *devlist = NULL; 4780 int i, devcount; 4781 4782 if (sc == NULL) 4783 return; 4784 4785 hdac_lock(sc); 4786 if (sc->polling != 0) 4787 callout_stop(&sc->poll_hdac); 4788 hdac_reset(sc); 4789 hdac_unlock(sc); 4790 snd_mtxfree(sc->lock); 4791 4792 device_get_children(sc->dev, &devlist, &devcount); 4793 for (i = 0; devlist != NULL && i < devcount; i++) { 4794 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4795 if (devinfo == NULL) 4796 continue; 4797 if (devinfo->widget != NULL) 4798 free(devinfo->widget, M_HDAC); 4799 if (devinfo->node_type == 4800 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4801 devinfo->function.audio.ctl != NULL) 4802 free(devinfo->function.audio.ctl, M_HDAC); 4803 free(devinfo, M_HDAC); 4804 device_delete_child(sc->dev, devlist[i]); 4805 } 4806 if (devlist != NULL) 4807 free(devlist, M_TEMP); 4808 4809 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4810 if (sc->codecs[i] != NULL) 4811 free(sc->codecs[i], M_HDAC); 4812 sc->codecs[i] = NULL; 4813 } 4814 4815 hdac_dma_free(&sc->rirb_dma); 4816 hdac_dma_free(&sc->corb_dma); 4817 if (sc->play.blkcnt > 0) 4818 hdac_dma_free(&sc->play.bdl_dma); 4819 if (sc->rec.blkcnt > 0) 4820 hdac_dma_free(&sc->rec.bdl_dma); 4821 hdac_irq_free(sc); 4822 hdac_mem_free(sc); 4823 free(sc, M_DEVBUF); 4824 4825} 4826 4827/* This function surely going to make its way into upper level someday. */ 4828static void 4829hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4830{ 4831 const char *res = NULL; 4832 int i = 0, j, k, len, inv; 4833 4834 if (on != NULL) 4835 *on = 0; 4836 if (off != NULL) 4837 *off = 0; 4838 if (sc == NULL) 4839 return; 4840 if (resource_string_value(device_get_name(sc->dev), 4841 device_get_unit(sc->dev), "config", &res) != 0) 4842 return; 4843 if (!(res != NULL && strlen(res) > 0)) 4844 return; 4845 HDA_BOOTVERBOSE( 4846 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4847 ); 4848 for (;;) { 4849 while (res[i] != '\0' && 4850 (res[i] == ',' || isspace(res[i]) != 0)) 4851 i++; 4852 if (res[i] == '\0') { 4853 HDA_BOOTVERBOSE( 4854 printf("\n"); 4855 ); 4856 return; 4857 } 4858 j = i; 4859 while (res[j] != '\0' && 4860 !(res[j] == ',' || isspace(res[j]) != 0)) 4861 j++; 4862 len = j - i; 4863 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4864 inv = 2; 4865 else 4866 inv = 0; 4867 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4868 if (strncmp(res + i + inv, 4869 hdac_quirks_tab[k].key, len - inv) != 0) 4870 continue; 4871 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4872 break; 4873 HDA_BOOTVERBOSE( 4874 printf(" %s%s", (inv != 0) ? "no" : "", 4875 hdac_quirks_tab[k].key); 4876 ); 4877 if (inv == 0 && on != NULL) 4878 *on |= hdac_quirks_tab[k].value; 4879 else if (inv != 0 && off != NULL) 4880 *off |= hdac_quirks_tab[k].value; 4881 break; 4882 } 4883 i = j; 4884 } 4885} 4886 4887#ifdef SND_DYNSYSCTL 4888static int 4889sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4890{ 4891 struct hdac_softc *sc; 4892 struct hdac_devinfo *devinfo; 4893 device_t dev; 4894 uint32_t ctl; 4895 int err, val; 4896 4897 dev = oidp->oid_arg1; 4898 devinfo = pcm_getdevinfo(dev); 4899 if (devinfo == NULL || devinfo->codec == NULL || 4900 devinfo->codec->sc == NULL) 4901 return (EINVAL); 4902 sc = devinfo->codec->sc; 4903 hdac_lock(sc); 4904 val = sc->polling; 4905 hdac_unlock(sc); 4906 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4907 4908 if (err || req->newptr == NULL) 4909 return (err); 4910 if (val < 0 || val > 1) 4911 return (EINVAL); 4912 4913 hdac_lock(sc); 4914 if (val != sc->polling) { 4915 if (hda_chan_active(sc) != 0) 4916 err = EBUSY; 4917 else if (val == 0) { 4918 callout_stop(&sc->poll_hdac); 4919 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 4920 sc->rirb_size / 2); 4921 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4922 ctl |= HDAC_RIRBCTL_RINTCTL; 4923 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4924 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4925 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4926 sc->polling = 0; 4927 DELAY(1000); 4928 } else { 4929 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 4930 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 4931 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4932 ctl &= ~HDAC_RIRBCTL_RINTCTL; 4933 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4934 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 4935 sc); 4936 sc->polling = 1; 4937 DELAY(1000); 4938 } 4939 } 4940 hdac_unlock(sc); 4941 4942 return (err); 4943} 4944#endif 4945 4946static void 4947hdac_attach2(void *arg) 4948{ 4949 struct hdac_softc *sc; 4950 struct hdac_widget *w; 4951 struct hdac_audio_ctl *ctl; 4952 uint32_t quirks_on, quirks_off; 4953 int pcnt, rcnt; 4954 int i; 4955 char status[SND_STATUSLEN]; 4956 device_t *devlist = NULL; 4957 int devcount; 4958 struct hdac_devinfo *devinfo = NULL; 4959 4960 sc = (struct hdac_softc *)arg; 4961 4962 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4963 4964 HDA_BOOTVERBOSE( 4965 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4966 quirks_on, quirks_off); 4967 ); 4968 4969 hdac_lock(sc); 4970 4971 /* Remove ourselves from the config hooks */ 4972 if (sc->intrhook.ich_func != NULL) { 4973 config_intrhook_disestablish(&sc->intrhook); 4974 sc->intrhook.ich_func = NULL; 4975 } 4976 4977 /* Start the corb and rirb engines */ 4978 HDA_BOOTVERBOSE( 4979 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4980 ); 4981 hdac_corb_start(sc); 4982 HDA_BOOTVERBOSE( 4983 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4984 ); 4985 hdac_rirb_start(sc); 4986 4987 HDA_BOOTVERBOSE( 4988 device_printf(sc->dev, 4989 "HDA_DEBUG: Enabling controller interrupt...\n"); 4990 ); 4991 if (sc->polling == 0) 4992 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4993 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4994 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4995 HDAC_GCTL_UNSOL); 4996 4997 DELAY(1000); 4998 4999 HDA_BOOTVERBOSE( 5000 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5001 ); 5002 hdac_scan_codecs(sc); 5003 5004 device_get_children(sc->dev, &devlist, &devcount); 5005 for (i = 0; devlist != NULL && i < devcount; i++) { 5006 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5007 if (devinfo != NULL && devinfo->node_type == 5008 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5009 break; 5010 } else 5011 devinfo = NULL; 5012 } 5013 if (devlist != NULL) 5014 free(devlist, M_TEMP); 5015 5016 if (devinfo == NULL) { 5017 hdac_unlock(sc); 5018 device_printf(sc->dev, "Audio Function Group not found!\n"); 5019 hdac_release_resources(sc); 5020 return; 5021 } 5022 5023 HDA_BOOTVERBOSE( 5024 device_printf(sc->dev, 5025 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5026 devinfo->nid, devinfo->codec->cad); 5027 ); 5028 hdac_audio_parse(devinfo); 5029 HDA_BOOTVERBOSE( 5030 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5031 ); 5032 hdac_audio_ctl_parse(devinfo); 5033 HDA_BOOTVERBOSE( 5034 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5035 ); 5036 hdac_vendor_patch_parse(devinfo); 5037 if (quirks_on != 0) 5038 devinfo->function.audio.quirks |= quirks_on; 5039 if (quirks_off != 0) 5040 devinfo->function.audio.quirks &= ~quirks_off; 5041 5042 /* XXX Disable all DIGITAL path. */ 5043 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5044 w = hdac_widget_get(devinfo, i); 5045 if (w == NULL) 5046 continue; 5047 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5048 w->enable = 0; 5049 continue; 5050 } 5051 /* XXX Disable useless pin ? */ 5052 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5053 (w->wclass.pin.config & 5054 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5055 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5056 w->enable = 0; 5057 } 5058 i = 0; 5059 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5060 if (ctl->widget == NULL) 5061 continue; 5062 w = ctl->widget; 5063 if (w->enable == 0) 5064 ctl->enable = 0; 5065 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5066 ctl->enable = 0; 5067 w = ctl->childwidget; 5068 if (w == NULL) 5069 continue; 5070 if (w->enable == 0 || 5071 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5072 ctl->enable = 0; 5073 } 5074 5075 HDA_BOOTVERBOSE( 5076 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5077 ); 5078 hdac_audio_build_tree(devinfo); 5079 5080 HDA_BOOTVERBOSE( 5081 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5082 ); 5083 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5084 HDA_BOOTVERBOSE( 5085 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5086 ); 5087 hdac_audio_ctl_commit(devinfo); 5088 5089 HDA_BOOTVERBOSE( 5090 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5091 ); 5092 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5093 HDA_BOOTVERBOSE( 5094 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5095 ); 5096 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5097 5098 hdac_unlock(sc); 5099 HDA_BOOTVERBOSE( 5100 device_printf(sc->dev, 5101 "HDA_DEBUG: OSS mixer initialization...\n"); 5102 ); 5103 5104 /* 5105 * There is no point of return after this. If the driver failed, 5106 * so be it. Let the detach procedure do all the cleanup. 5107 */ 5108 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5109 device_printf(sc->dev, "Can't register mixer\n"); 5110 5111 if (pcnt > 0) 5112 pcnt = 1; 5113 if (rcnt > 0) 5114 rcnt = 1; 5115 5116 HDA_BOOTVERBOSE( 5117 device_printf(sc->dev, 5118 "HDA_DEBUG: Registering PCM channels...\n"); 5119 ); 5120 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5121 device_printf(sc->dev, "Can't register PCM\n"); 5122 5123 sc->registered++; 5124 5125 for (i = 0; i < pcnt; i++) 5126 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5127 for (i = 0; i < rcnt; i++) 5128 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5129 5130#ifdef SND_DYNSYSCTL 5131 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5132 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5133 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5134 sysctl_hdac_polling, "I", "Enable polling mode"); 5135#endif 5136 5137 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5138 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5139 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5140 pcm_setstatus(sc->dev, status); 5141 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5142 HDA_BOOTVERBOSE( 5143 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5144 hdac_codec_id(devinfo)); 5145 ); 5146 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5147 HDA_DRV_TEST_REV); 5148 5149 HDA_BOOTVERBOSE( 5150 if (devinfo->function.audio.quirks != 0) { 5151 device_printf(sc->dev, "\n"); 5152 device_printf(sc->dev, "HDA config/quirks:"); 5153 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5154 if (devinfo->function.audio.quirks & 5155 hdac_quirks_tab[i].value) 5156 printf(" %s", hdac_quirks_tab[i].key); 5157 } 5158 printf("\n"); 5159 } 5160 device_printf(sc->dev, "\n"); 5161 device_printf(sc->dev, "+-------------------+\n"); 5162 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5163 device_printf(sc->dev, "+-------------------+\n"); 5164 hdac_dump_nodes(devinfo); 5165 device_printf(sc->dev, "\n"); 5166 device_printf(sc->dev, "+------------------------+\n"); 5167 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5168 device_printf(sc->dev, "+------------------------+\n"); 5169 device_printf(sc->dev, "\n"); 5170 i = 0; 5171 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5172 device_printf(sc->dev, "%3d: nid=%d", i, 5173 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5174 if (ctl->childwidget != NULL) 5175 printf(" cnid=%d", ctl->childwidget->nid); 5176 printf(" dir=0x%x index=%d " 5177 "ossmask=0x%08x ossdev=%d%s\n", 5178 ctl->dir, ctl->index, 5179 ctl->ossmask, ctl->ossdev, 5180 (ctl->enable == 0) ? " [DISABLED]" : ""); 5181 } 5182 device_printf(sc->dev, "\n"); 5183 device_printf(sc->dev, "+-----------------------------------+\n"); 5184 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5185 device_printf(sc->dev, "+-----------------------------------+\n"); 5186 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5187 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5188 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5189 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5190 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5191 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5192 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5193 hdac_dump_ctls(devinfo, NULL, 0); 5194 hdac_dump_dac(devinfo); 5195 hdac_dump_adc(devinfo); 5196 device_printf(sc->dev, "\n"); 5197 device_printf(sc->dev, "+--------------------------------------+\n"); 5198 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5199 device_printf(sc->dev, "+--------------------------------------+\n"); 5200 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5201 ); 5202 5203 if (sc->polling != 0) { 5204 hdac_lock(sc); 5205 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5206 hdac_unlock(sc); 5207 } 5208} 5209 5210/**************************************************************************** 5211 * int hdac_detach(device_t) 5212 * 5213 * Detach and free up resources utilized by the hdac device. 5214 ****************************************************************************/ 5215static int 5216hdac_detach(device_t dev) 5217{ 5218 struct hdac_softc *sc = NULL; 5219 struct hdac_devinfo *devinfo = NULL; 5220 int err; 5221 5222 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5223 if (devinfo != NULL && devinfo->codec != NULL) 5224 sc = devinfo->codec->sc; 5225 if (sc == NULL) 5226 return (0); 5227 5228 if (sc->registered > 0) { 5229 err = pcm_unregister(dev); 5230 if (err != 0) 5231 return (err); 5232 } 5233 5234 hdac_release_resources(sc); 5235 5236 return (0); 5237} 5238 5239static device_method_t hdac_methods[] = { 5240 /* device interface */ 5241 DEVMETHOD(device_probe, hdac_probe), 5242 DEVMETHOD(device_attach, hdac_attach), 5243 DEVMETHOD(device_detach, hdac_detach), 5244 { 0, 0 } 5245}; 5246 5247static driver_t hdac_driver = { 5248 "pcm", 5249 hdac_methods, 5250 PCM_SOFTC_SIZE, 5251}; 5252 5253DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5254MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5255MODULE_VERSION(snd_hda, 1); 5256