hdac.c revision 164828
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061203_0035" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 164828 2006-12-02 17:12:24Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 193#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 194 195/* IBM / Lenovo */ 196#define IBM_VENDORID 0x1014 197#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 198#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 199 200/* Lenovo */ 201#define LENOVO_VENDORID 0x17aa 202#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 203#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 204 205/* Samsung */ 206#define SAMSUNG_VENDORID 0x144d 207#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 208#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 209 210/* Medion ? */ 211#define MEDION_VENDORID 0x161f 212#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 213#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 214 215/* 216 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 217 * instead of their own, which is beyond my comprehension 218 * (see HDA_CODEC_STAC9221 below). 219 */ 220#define APPLE_INTEL_MAC 0x76808384 221 222/* Misc constants.. */ 223#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 224#define HDA_AMP_MUTE_NONE (0) 225#define HDA_AMP_MUTE_LEFT (1 << 0) 226#define HDA_AMP_MUTE_RIGHT (1 << 1) 227#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 228 229#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 230#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 231 232#define HDA_DAC_PATH (1 << 0) 233#define HDA_ADC_PATH (1 << 1) 234#define HDA_ADC_RECSEL (1 << 2) 235 236#define HDA_CTL_OUT (1 << 0) 237#define HDA_CTL_IN (1 << 1) 238#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 239 240#define HDA_GPIO_MAX 15 241/* 0 - 14 = GPIO */ 242#define HDA_QUIRK_GPIO0 (1 << 0) 243#define HDA_QUIRK_GPIO1 (1 << 1) 244#define HDA_QUIRK_GPIO2 (1 << 2) 245#define HDA_QUIRK_SOFTPCMVOL (1 << 15) 246#define HDA_QUIRK_FIXEDRATE (1 << 16) 247#define HDA_QUIRK_FORCESTEREO (1 << 17) 248#define HDA_QUIRK_EAPDINV (1 << 18) 249 250static const struct { 251 char *key; 252 uint32_t value; 253} hdac_quirks_tab[] = { 254 { "gpio0", HDA_QUIRK_GPIO0 }, 255 { "gpio1", HDA_QUIRK_GPIO1 }, 256 { "gpio2", HDA_QUIRK_GPIO2 }, 257 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 258 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 259 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 260 { "eapdinv", HDA_QUIRK_EAPDINV }, 261}; 262#define HDAC_QUIRKS_TAB_LEN \ 263 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 264 265#define HDA_BDL_MIN 2 266#define HDA_BDL_MAX 256 267#define HDA_BDL_DEFAULT HDA_BDL_MIN 268 269#define HDA_BUFSZ_MIN 4096 270#define HDA_BUFSZ_MAX 65536 271#define HDA_BUFSZ_DEFAULT 16384 272 273#define HDA_PARSE_MAXDEPTH 10 274 275#define HDAC_UNSOLTAG_EVENT_HP 0x00 276 277static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 278 279enum { 280 HDA_PARSE_MIXER, 281 HDA_PARSE_DIRECT 282}; 283 284/* Default */ 285static uint32_t hdac_fmt[] = { 286 AFMT_STEREO | AFMT_S16_LE, 287 0 288}; 289 290static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 291 292static const struct { 293 uint32_t model; 294 char *desc; 295} hdac_devices[] = { 296 { HDA_INTEL_82801F, "Intel 82801F" }, 297 { HDA_INTEL_82801G, "Intel 82801G" }, 298 { HDA_INTEL_82801H, "Intel 82801H" }, 299 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 300 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 301 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 302 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 303 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 304 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 305 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 306 { HDA_ATI_SB450, "ATI SB450" }, 307 { HDA_ATI_SB600, "ATI SB600" }, 308 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 309 { HDA_SIS_966, "SiS 966" }, 310 /* Unknown */ 311 { HDA_INTEL_ALL, "Intel (Unknown)" }, 312 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 313 { HDA_ATI_ALL, "ATI (Unknown)" }, 314 { HDA_VIA_ALL, "VIA (Unknown)" }, 315 { HDA_SIS_ALL, "SiS (Unknown)" }, 316}; 317#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 318 319static const struct { 320 uint32_t rate; 321 int valid; 322 uint16_t base; 323 uint16_t mul; 324 uint16_t div; 325} hda_rate_tab[] = { 326 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 327 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 328 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 329 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 330 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 331 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 332 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 333 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 334 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 335 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 336 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 337 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 338 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 339 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 340 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 341 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 342 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 343 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 344 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 345 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 346 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 347 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 348 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 349 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 350 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 351 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 352 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 353 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 354 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 355 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 356 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 357 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 358 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 359 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 360 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 361}; 362#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 363 364/* All codecs you can eat... */ 365#define HDA_CODEC_CONSTRUCT(vendor, id) \ 366 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 367 368/* Realtek */ 369#define REALTEK_VENDORID 0x10ec 370#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 371#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 372#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 373#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 374#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 375#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 376 377/* Analog Device */ 378#define ANALOGDEVICE_VENDORID 0x11d4 379#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 380#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 381#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 382#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 383 384/* CMedia */ 385#define CMEDIA_VENDORID 0x434d 386#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 387#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 388 389/* Sigmatel */ 390#define SIGMATEL_VENDORID 0x8384 391#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 392#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 393#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 394#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 395#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 396 397/* 398 * Conexant 399 * 400 * Ok, the truth is, I don't have any idea at all whether 401 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 402 * place that tell me it is "Venice" is from its Windows driver INF. 403 * 404 * Venice - CX????? 405 * Waikiki - CX20551-22 406 */ 407#define CONEXANT_VENDORID 0x14f1 408#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 409#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 410#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 411 412 413/* Codecs */ 414static const struct { 415 uint32_t id; 416 char *name; 417} hdac_codecs[] = { 418 { HDA_CODEC_ALC260, "Realtek ALC260" }, 419 { HDA_CODEC_ALC861, "Realtek ALC861" }, 420 { HDA_CODEC_ALC880, "Realtek ALC880" }, 421 { HDA_CODEC_ALC882, "Realtek ALC882" }, 422 { HDA_CODEC_ALC883, "Realtek ALC883" }, 423 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 424 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 425 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 426 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 427 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 428 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 429 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 430 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 431 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 432 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 433 /* Unknown codec */ 434 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 435 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 436 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 437 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 438 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 439}; 440#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 441 442enum { 443 HDAC_HP_SWITCH_CTL, 444 HDAC_HP_SWITCH_CTRL 445}; 446 447static const struct { 448 uint32_t model; 449 uint32_t id; 450 int type; 451 nid_t hpnid; 452 nid_t spkrnid[8]; 453 nid_t eapdnid; 454} hdac_hp_switch[] = { 455 /* Specific OEM models */ 456 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 457 17, { 16, -1 }, 16 }, 458 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 459 6, { 5, -1 }, 5 }, 460 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 461 6, { 5, -1 }, 5 }, 462 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 463 13, { 14, -1 }, -1 }, 464 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 465 13, { 14, -1 }, -1 }, 466 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 467 10, { 13, -1 }, -1 }, 468 /* 469 * All models that at least come from the same vendor with 470 * simmilar codec. 471 */ 472 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 473 17, { 16, -1 }, 16 }, 474 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 475 6, { 5, -1 }, 5 }, 476 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 477 13, { 14, -1 }, -1 }, 478}; 479#define HDAC_HP_SWITCH_LEN \ 480 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 481 482static const struct { 483 uint32_t model; 484 uint32_t id; 485 nid_t eapdnid; 486 int hp_switch; 487} hdac_eapd_switch[] = { 488 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 489 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 490 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 491}; 492#define HDAC_EAPD_SWITCH_LEN \ 493 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 494 495/**************************************************************************** 496 * Function prototypes 497 ****************************************************************************/ 498static void hdac_intr_handler(void *); 499static int hdac_reset(struct hdac_softc *); 500static int hdac_get_capabilities(struct hdac_softc *); 501static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 502static int hdac_dma_alloc(struct hdac_softc *, 503 struct hdac_dma *, bus_size_t); 504static void hdac_dma_free(struct hdac_dma *); 505static int hdac_mem_alloc(struct hdac_softc *); 506static void hdac_mem_free(struct hdac_softc *); 507static int hdac_irq_alloc(struct hdac_softc *); 508static void hdac_irq_free(struct hdac_softc *); 509static void hdac_corb_init(struct hdac_softc *); 510static void hdac_rirb_init(struct hdac_softc *); 511static void hdac_corb_start(struct hdac_softc *); 512static void hdac_rirb_start(struct hdac_softc *); 513static void hdac_scan_codecs(struct hdac_softc *); 514static int hdac_probe_codec(struct hdac_codec *); 515static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 516static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 517 518static void hdac_attach2(void *); 519 520static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 521 uint32_t, int); 522static void hdac_command_send_internal(struct hdac_softc *, 523 struct hdac_command_list *, int); 524 525static int hdac_probe(device_t); 526static int hdac_attach(device_t); 527static int hdac_detach(device_t); 528static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 529static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 530 uint32_t, int, int); 531static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 532 nid_t, int, int); 533static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 534 nid_t, nid_t, int, int, int, int, int, int); 535static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 536static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 537 538static int hdac_rirb_flush(struct hdac_softc *sc); 539static int hdac_unsolq_flush(struct hdac_softc *sc); 540 541#define hdac_command(a1, a2, a3) \ 542 hdac_command_sendone_internal(a1, a2, a3) 543 544#define hdac_codec_id(d) \ 545 ((uint32_t)((d == NULL) ? 0x00000000 : \ 546 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 547 ((uint32_t)(d)->device_id & 0x0000ffff)))) 548 549static char * 550hdac_codec_name(struct hdac_devinfo *devinfo) 551{ 552 uint32_t id; 553 int i; 554 555 id = hdac_codec_id(devinfo); 556 557 for (i = 0; i < HDAC_CODECS_LEN; i++) { 558 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 559 return (hdac_codecs[i].name); 560 } 561 562 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 563} 564 565static char * 566hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 567{ 568 static char *ossname[] = SOUND_DEVICE_NAMES; 569 static char *unknown = "???"; 570 int i; 571 572 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 573 if (devmask & (1 << i)) 574 return (ossname[i]); 575 } 576 return (unknown); 577} 578 579static void 580hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 581{ 582 static char *ossname[] = SOUND_DEVICE_NAMES; 583 int i, first = 1; 584 585 bzero(buf, len); 586 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 587 if (mask & (1 << i)) { 588 if (first == 0) 589 strlcat(buf, ", ", len); 590 strlcat(buf, ossname[i], len); 591 first = 0; 592 } 593 } 594} 595 596static struct hdac_audio_ctl * 597hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 598{ 599 if (devinfo == NULL || 600 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 601 index == NULL || devinfo->function.audio.ctl == NULL || 602 devinfo->function.audio.ctlcnt < 1 || 603 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 604 return (NULL); 605 return (&devinfo->function.audio.ctl[(*index)++]); 606} 607 608static struct hdac_audio_ctl * 609hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 610 int index, int cnt) 611{ 612 struct hdac_audio_ctl *ctl, *retctl = NULL; 613 int i, at, atindex, found = 0; 614 615 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 616 return (NULL); 617 618 at = cnt; 619 if (at == 0) 620 at = 1; 621 else if (at < 0) 622 at = -1; 623 atindex = index; 624 if (atindex < 0) 625 atindex = -1; 626 627 i = 0; 628 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 629 if (ctl->enable == 0 || ctl->widget == NULL) 630 continue; 631 if (!(ctl->widget->nid == nid && (atindex == -1 || 632 ctl->index == atindex))) 633 continue; 634 found++; 635 if (found == cnt) 636 return (ctl); 637 retctl = ctl; 638 } 639 640 return ((at == -1) ? retctl : NULL); 641} 642 643static void 644hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 645{ 646 struct hdac_softc *sc; 647 struct hdac_widget *w; 648 struct hdac_audio_ctl *ctl; 649 uint32_t id, res; 650 int i = 0, j, forcemute; 651 nid_t cad; 652 653 if (devinfo == NULL || devinfo->codec == NULL || 654 devinfo->codec->sc == NULL) 655 return; 656 657 sc = devinfo->codec->sc; 658 cad = devinfo->codec->cad; 659 id = hdac_codec_id(devinfo); 660 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 661 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 662 sc->pci_subvendor) && 663 hdac_hp_switch[i].id == id) 664 break; 665 } 666 667 if (i >= HDAC_HP_SWITCH_LEN) 668 return; 669 670 forcemute = 0; 671 if (hdac_hp_switch[i].eapdnid != -1) { 672 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 673 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 674 forcemute = (w->param.eapdbtl & 675 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 676 } 677 678 res = hdac_command(sc, 679 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 680 HDA_BOOTVERBOSE( 681 device_printf(sc->dev, 682 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 683 hdac_hp_switch[i].hpnid, res); 684 ); 685 res >>= 31; 686 687 switch (hdac_hp_switch[i].type) { 688 case HDAC_HP_SWITCH_CTL: 689 ctl = hdac_audio_ctl_amp_get(devinfo, 690 hdac_hp_switch[i].hpnid, 0, 1); 691 if (ctl != NULL) { 692 ctl->muted = (res != 0 && forcemute == 0) ? 693 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 694 hdac_audio_ctl_amp_set(ctl, 695 HDA_AMP_MUTE_DEFAULT, ctl->left, 696 ctl->right); 697 } 698 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 699 ctl = hdac_audio_ctl_amp_get(devinfo, 700 hdac_hp_switch[i].spkrnid[j], 0, 1); 701 if (ctl != NULL) { 702 ctl->muted = (res != 0 || forcemute == 1) ? 703 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 704 hdac_audio_ctl_amp_set(ctl, 705 HDA_AMP_MUTE_DEFAULT, ctl->left, 706 ctl->right); 707 } 708 } 709 break; 710 case HDAC_HP_SWITCH_CTRL: 711 if (res != 0) { 712 /* HP in */ 713 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 714 if (w != NULL && w->type == 715 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 716 if (forcemute == 0) 717 w->wclass.pin.ctrl |= 718 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 719 else 720 w->wclass.pin.ctrl &= 721 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 722 hdac_command(sc, 723 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 724 w->wclass.pin.ctrl), cad); 725 } 726 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 727 w = hdac_widget_get(devinfo, 728 hdac_hp_switch[i].spkrnid[j]); 729 if (w != NULL && w->type == 730 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 731 w->wclass.pin.ctrl &= 732 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 733 hdac_command(sc, 734 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 735 w->nid, 736 w->wclass.pin.ctrl), cad); 737 } 738 } 739 } else { 740 /* HP out */ 741 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 742 if (w != NULL && w->type == 743 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 744 w->wclass.pin.ctrl &= 745 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 746 hdac_command(sc, 747 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 748 w->wclass.pin.ctrl), cad); 749 } 750 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 751 w = hdac_widget_get(devinfo, 752 hdac_hp_switch[i].spkrnid[j]); 753 if (w != NULL && w->type == 754 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 755 if (forcemute == 0) 756 w->wclass.pin.ctrl |= 757 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 758 else 759 w->wclass.pin.ctrl &= 760 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 761 hdac_command(sc, 762 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 763 w->nid, 764 w->wclass.pin.ctrl), cad); 765 } 766 } 767 } 768 break; 769 default: 770 break; 771 } 772} 773 774static void 775hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 776{ 777 struct hdac_softc *sc; 778 struct hdac_devinfo *devinfo = NULL; 779 device_t *devlist = NULL; 780 int devcount, i; 781 782 if (codec == NULL || codec->sc == NULL) 783 return; 784 785 sc = codec->sc; 786 787 HDA_BOOTVERBOSE( 788 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 789 ); 790 791 device_get_children(sc->dev, &devlist, &devcount); 792 for (i = 0; devlist != NULL && i < devcount; i++) { 793 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 794 if (devinfo != NULL && devinfo->node_type == 795 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 796 devinfo->codec != NULL && 797 devinfo->codec->cad == codec->cad) { 798 break; 799 } else 800 devinfo = NULL; 801 } 802 if (devlist != NULL) 803 free(devlist, M_TEMP); 804 805 if (devinfo == NULL) 806 return; 807 808 switch (tag) { 809 case HDAC_UNSOLTAG_EVENT_HP: 810 hdac_hp_switch_handler(devinfo); 811 break; 812 default: 813 break; 814 } 815} 816 817static int 818hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 819{ 820 /* XXX to be removed */ 821#ifdef HDAC_INTR_EXTRA 822 uint32_t res; 823#endif 824 825 if (ch->blkcnt == 0) 826 return (0); 827 828 /* XXX to be removed */ 829#ifdef HDAC_INTR_EXTRA 830 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 831#endif 832 833 /* XXX to be removed */ 834#ifdef HDAC_INTR_EXTRA 835 HDA_BOOTVERBOSE( 836 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 837 device_printf(sc->dev, 838 "PCMDIR_%s intr triggered beyond stream boundary:" 839 "%08x\n", 840 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 841 ); 842#endif 843 844 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 845 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 846 847 /* XXX to be removed */ 848#ifdef HDAC_INTR_EXTRA 849 if (res & HDAC_SDSTS_BCIS) { 850#endif 851 return (1); 852 /* XXX to be removed */ 853#ifdef HDAC_INTR_EXTRA 854 } 855#endif 856 857 return (0); 858} 859 860/**************************************************************************** 861 * void hdac_intr_handler(void *) 862 * 863 * Interrupt handler. Processes interrupts received from the hdac. 864 ****************************************************************************/ 865static void 866hdac_intr_handler(void *context) 867{ 868 struct hdac_softc *sc; 869 uint32_t intsts; 870 uint8_t rirbsts; 871 struct hdac_rirb *rirb_base; 872 uint32_t trigger = 0; 873 874 sc = (struct hdac_softc *)context; 875 876 hdac_lock(sc); 877 if (sc->polling != 0) { 878 hdac_unlock(sc); 879 return; 880 } 881 /* Do we have anything to do? */ 882 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 883 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 884 hdac_unlock(sc); 885 return; 886 } 887 888 /* Was this a controller interrupt? */ 889 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 890 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 891 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 892 /* Get as many responses that we can */ 893 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 894 HDAC_WRITE_1(&sc->mem, 895 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 896 hdac_rirb_flush(sc); 897 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 898 } 899 /* XXX to be removed */ 900 /* Clear interrupt and exit */ 901#ifdef HDAC_INTR_EXTRA 902 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 903#endif 904 } 905 906 hdac_unsolq_flush(sc); 907 908 if (intsts & HDAC_INTSTS_SIS_MASK) { 909 if ((intsts & (1 << sc->num_iss)) && 910 hdac_stream_intr(sc, &sc->play) != 0) 911 trigger |= 1; 912 if ((intsts & (1 << 0)) && 913 hdac_stream_intr(sc, &sc->rec) != 0) 914 trigger |= 2; 915 /* XXX to be removed */ 916#ifdef HDAC_INTR_EXTRA 917 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 918 HDAC_INTSTS_SIS_MASK); 919#endif 920 } 921 922 hdac_unlock(sc); 923 924 if (trigger & 1) 925 chn_intr(sc->play.c); 926 if (trigger & 2) 927 chn_intr(sc->rec.c); 928} 929 930/**************************************************************************** 931 * int hdac_reset(hdac_softc *) 932 * 933 * Reset the hdac to a quiescent and known state. 934 ****************************************************************************/ 935static int 936hdac_reset(struct hdac_softc *sc) 937{ 938 uint32_t gctl; 939 int count, i; 940 941 /* 942 * Stop all Streams DMA engine 943 */ 944 for (i = 0; i < sc->num_iss; i++) 945 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 946 for (i = 0; i < sc->num_oss; i++) 947 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 948 for (i = 0; i < sc->num_bss; i++) 949 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 950 951 /* 952 * Stop Control DMA engines 953 */ 954 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 955 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 956 957 /* 958 * Reset the controller. The reset must remain asserted for 959 * a minimum of 100us. 960 */ 961 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 962 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 963 count = 10000; 964 do { 965 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 966 if (!(gctl & HDAC_GCTL_CRST)) 967 break; 968 DELAY(10); 969 } while (--count); 970 if (gctl & HDAC_GCTL_CRST) { 971 device_printf(sc->dev, "Unable to put hdac in reset\n"); 972 return (ENXIO); 973 } 974 DELAY(100); 975 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 976 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 977 count = 10000; 978 do { 979 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 980 if (gctl & HDAC_GCTL_CRST) 981 break; 982 DELAY(10); 983 } while (--count); 984 if (!(gctl & HDAC_GCTL_CRST)) { 985 device_printf(sc->dev, "Device stuck in reset\n"); 986 return (ENXIO); 987 } 988 989 /* 990 * Wait for codecs to finish their own reset sequence. The delay here 991 * should be of 250us but for some reasons, on it's not enough on my 992 * computer. Let's use twice as much as necessary to make sure that 993 * it's reset properly. 994 */ 995 DELAY(1000); 996 997 return (0); 998} 999 1000 1001/**************************************************************************** 1002 * int hdac_get_capabilities(struct hdac_softc *); 1003 * 1004 * Retreive the general capabilities of the hdac; 1005 * Number of Input Streams 1006 * Number of Output Streams 1007 * Number of bidirectional Streams 1008 * 64bit ready 1009 * CORB and RIRB sizes 1010 ****************************************************************************/ 1011static int 1012hdac_get_capabilities(struct hdac_softc *sc) 1013{ 1014 uint16_t gcap; 1015 uint8_t corbsize, rirbsize; 1016 1017 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1018 sc->num_iss = HDAC_GCAP_ISS(gcap); 1019 sc->num_oss = HDAC_GCAP_OSS(gcap); 1020 sc->num_bss = HDAC_GCAP_BSS(gcap); 1021 1022 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1023 1024 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1025 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1026 HDAC_CORBSIZE_CORBSZCAP_256) 1027 sc->corb_size = 256; 1028 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1029 HDAC_CORBSIZE_CORBSZCAP_16) 1030 sc->corb_size = 16; 1031 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1032 HDAC_CORBSIZE_CORBSZCAP_2) 1033 sc->corb_size = 2; 1034 else { 1035 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1036 __func__, corbsize); 1037 return (ENXIO); 1038 } 1039 1040 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1041 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1042 HDAC_RIRBSIZE_RIRBSZCAP_256) 1043 sc->rirb_size = 256; 1044 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1045 HDAC_RIRBSIZE_RIRBSZCAP_16) 1046 sc->rirb_size = 16; 1047 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1048 HDAC_RIRBSIZE_RIRBSZCAP_2) 1049 sc->rirb_size = 2; 1050 else { 1051 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1052 __func__, rirbsize); 1053 return (ENXIO); 1054 } 1055 1056 return (0); 1057} 1058 1059 1060/**************************************************************************** 1061 * void hdac_dma_cb 1062 * 1063 * This function is called by bus_dmamap_load when the mapping has been 1064 * established. We just record the physical address of the mapping into 1065 * the struct hdac_dma passed in. 1066 ****************************************************************************/ 1067static void 1068hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1069{ 1070 struct hdac_dma *dma; 1071 1072 if (error == 0) { 1073 dma = (struct hdac_dma *)callback_arg; 1074 dma->dma_paddr = segs[0].ds_addr; 1075 } 1076} 1077 1078static void 1079hdac_dma_nocache(void *ptr) 1080{ 1081#if defined(__i386__) || defined(__amd64__) 1082 pt_entry_t *pte; 1083 vm_offset_t va; 1084 1085 va = (vm_offset_t)ptr; 1086 pte = vtopte(va); 1087 if (pte) { 1088 *pte |= PG_N; 1089 invltlb(); 1090 } 1091#endif 1092} 1093 1094/**************************************************************************** 1095 * int hdac_dma_alloc 1096 * 1097 * This function allocate and setup a dma region (struct hdac_dma). 1098 * It must be freed by a corresponding hdac_dma_free. 1099 ****************************************************************************/ 1100static int 1101hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1102{ 1103 int result; 1104 int lowaddr; 1105 1106 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1107 BUS_SPACE_MAXADDR_32BIT; 1108 bzero(dma, sizeof(*dma)); 1109 1110 /* 1111 * Create a DMA tag 1112 */ 1113 result = bus_dma_tag_create(NULL, /* parent */ 1114 HDAC_DMA_ALIGNMENT, /* alignment */ 1115 0, /* boundary */ 1116 lowaddr, /* lowaddr */ 1117 BUS_SPACE_MAXADDR, /* highaddr */ 1118 NULL, /* filtfunc */ 1119 NULL, /* fistfuncarg */ 1120 size, /* maxsize */ 1121 1, /* nsegments */ 1122 size, /* maxsegsz */ 1123 0, /* flags */ 1124 NULL, /* lockfunc */ 1125 NULL, /* lockfuncarg */ 1126 &dma->dma_tag); /* dmat */ 1127 if (result != 0) { 1128 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1129 __func__, result); 1130 goto fail; 1131 } 1132 1133 /* 1134 * Allocate DMA memory 1135 */ 1136 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1137 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1138 if (result != 0) { 1139 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1140 __func__, result); 1141 goto fail; 1142 } 1143 1144 /* 1145 * Map the memory 1146 */ 1147 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1148 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1149 BUS_DMA_NOWAIT); 1150 if (result != 0 || dma->dma_paddr == 0) { 1151 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1152 __func__, result); 1153 goto fail; 1154 } 1155 bzero((void *)dma->dma_vaddr, size); 1156 hdac_dma_nocache(dma->dma_vaddr); 1157 1158 return (0); 1159fail: 1160 if (dma->dma_map != NULL) 1161 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1162 if (dma->dma_tag != NULL) 1163 bus_dma_tag_destroy(dma->dma_tag); 1164 return (result); 1165} 1166 1167 1168/**************************************************************************** 1169 * void hdac_dma_free(struct hdac_dma *) 1170 * 1171 * Free a struct dhac_dma that has been previously allocated via the 1172 * hdac_dma_alloc function. 1173 ****************************************************************************/ 1174static void 1175hdac_dma_free(struct hdac_dma *dma) 1176{ 1177 if (dma->dma_tag != NULL) { 1178 /* Flush caches */ 1179 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1180 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1181 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1182 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1183 bus_dma_tag_destroy(dma->dma_tag); 1184 } 1185} 1186 1187/**************************************************************************** 1188 * int hdac_mem_alloc(struct hdac_softc *) 1189 * 1190 * Allocate all the bus resources necessary to speak with the physical 1191 * controller. 1192 ****************************************************************************/ 1193static int 1194hdac_mem_alloc(struct hdac_softc *sc) 1195{ 1196 struct hdac_mem *mem; 1197 1198 mem = &sc->mem; 1199 mem->mem_rid = PCIR_BAR(0); 1200 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1201 &mem->mem_rid, RF_ACTIVE); 1202 if (mem->mem_res == NULL) { 1203 device_printf(sc->dev, 1204 "%s: Unable to allocate memory resource\n", __func__); 1205 return (ENOMEM); 1206 } 1207 mem->mem_tag = rman_get_bustag(mem->mem_res); 1208 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1209 1210 return (0); 1211} 1212 1213/**************************************************************************** 1214 * void hdac_mem_free(struct hdac_softc *) 1215 * 1216 * Free up resources previously allocated by hdac_mem_alloc. 1217 ****************************************************************************/ 1218static void 1219hdac_mem_free(struct hdac_softc *sc) 1220{ 1221 struct hdac_mem *mem; 1222 1223 mem = &sc->mem; 1224 if (mem->mem_res != NULL) 1225 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1226 mem->mem_res); 1227 mem->mem_res = NULL; 1228} 1229 1230/**************************************************************************** 1231 * int hdac_irq_alloc(struct hdac_softc *) 1232 * 1233 * Allocate and setup the resources necessary for interrupt handling. 1234 ****************************************************************************/ 1235static int 1236hdac_irq_alloc(struct hdac_softc *sc) 1237{ 1238 struct hdac_irq *irq; 1239 int result; 1240 1241 irq = &sc->irq; 1242 irq->irq_rid = 0x0; 1243 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1244 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1245 if (irq->irq_res == NULL) { 1246 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1247 __func__); 1248 goto fail; 1249 } 1250 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1251 hdac_intr_handler, sc, &irq->irq_handle); 1252 if (result != 0) { 1253 device_printf(sc->dev, 1254 "%s: Unable to setup interrupt handler (%x)\n", 1255 __func__, result); 1256 goto fail; 1257 } 1258 1259 return (0); 1260 1261fail: 1262 hdac_irq_free(sc); 1263 1264 return (ENXIO); 1265} 1266 1267/**************************************************************************** 1268 * void hdac_irq_free(struct hdac_softc *) 1269 * 1270 * Free up resources previously allocated by hdac_irq_alloc. 1271 ****************************************************************************/ 1272static void 1273hdac_irq_free(struct hdac_softc *sc) 1274{ 1275 struct hdac_irq *irq; 1276 1277 irq = &sc->irq; 1278 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1279 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1280 if (irq->irq_res != NULL) 1281 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1282 irq->irq_res); 1283 irq->irq_handle = NULL; 1284 irq->irq_res = NULL; 1285} 1286 1287/**************************************************************************** 1288 * void hdac_corb_init(struct hdac_softc *) 1289 * 1290 * Initialize the corb registers for operations but do not start it up yet. 1291 * The CORB engine must not be running when this function is called. 1292 ****************************************************************************/ 1293static void 1294hdac_corb_init(struct hdac_softc *sc) 1295{ 1296 uint8_t corbsize; 1297 uint64_t corbpaddr; 1298 1299 /* Setup the CORB size. */ 1300 switch (sc->corb_size) { 1301 case 256: 1302 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1303 break; 1304 case 16: 1305 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1306 break; 1307 case 2: 1308 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1309 break; 1310 default: 1311 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1312 } 1313 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1314 1315 /* Setup the CORB Address in the hdac */ 1316 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1317 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1318 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1319 1320 /* Set the WP and RP */ 1321 sc->corb_wp = 0; 1322 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1323 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1324 /* 1325 * The HDA specification indicates that the CORBRPRST bit will always 1326 * read as zero. Unfortunately, it seems that at least the 82801G 1327 * doesn't reset the bit to zero, which stalls the corb engine. 1328 * manually reset the bit to zero before continuing. 1329 */ 1330 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1331 1332 /* Enable CORB error reporting */ 1333#if 0 1334 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1335#endif 1336} 1337 1338/**************************************************************************** 1339 * void hdac_rirb_init(struct hdac_softc *) 1340 * 1341 * Initialize the rirb registers for operations but do not start it up yet. 1342 * The RIRB engine must not be running when this function is called. 1343 ****************************************************************************/ 1344static void 1345hdac_rirb_init(struct hdac_softc *sc) 1346{ 1347 uint8_t rirbsize; 1348 uint64_t rirbpaddr; 1349 1350 /* Setup the RIRB size. */ 1351 switch (sc->rirb_size) { 1352 case 256: 1353 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1354 break; 1355 case 16: 1356 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1357 break; 1358 case 2: 1359 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1360 break; 1361 default: 1362 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1363 } 1364 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1365 1366 /* Setup the RIRB Address in the hdac */ 1367 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1368 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1369 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1370 1371 /* Setup the WP and RP */ 1372 sc->rirb_rp = 0; 1373 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1374 1375 if (sc->polling == 0) { 1376 /* Setup the interrupt threshold */ 1377 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1378 1379 /* Enable Overrun and response received reporting */ 1380#if 0 1381 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1382 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1383#else 1384 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1385#endif 1386 } 1387 1388 /* 1389 * Make sure that the Host CPU cache doesn't contain any dirty 1390 * cache lines that falls in the rirb. If I understood correctly, it 1391 * should be sufficient to do this only once as the rirb is purely 1392 * read-only from now on. 1393 */ 1394 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1395 BUS_DMASYNC_PREREAD); 1396} 1397 1398/**************************************************************************** 1399 * void hdac_corb_start(hdac_softc *) 1400 * 1401 * Startup the corb DMA engine 1402 ****************************************************************************/ 1403static void 1404hdac_corb_start(struct hdac_softc *sc) 1405{ 1406 uint32_t corbctl; 1407 1408 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1409 corbctl |= HDAC_CORBCTL_CORBRUN; 1410 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1411} 1412 1413/**************************************************************************** 1414 * void hdac_rirb_start(hdac_softc *) 1415 * 1416 * Startup the rirb DMA engine 1417 ****************************************************************************/ 1418static void 1419hdac_rirb_start(struct hdac_softc *sc) 1420{ 1421 uint32_t rirbctl; 1422 1423 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1424 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1425 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1426} 1427 1428 1429/**************************************************************************** 1430 * void hdac_scan_codecs(struct hdac_softc *) 1431 * 1432 * Scan the bus for available codecs. 1433 ****************************************************************************/ 1434static void 1435hdac_scan_codecs(struct hdac_softc *sc) 1436{ 1437 struct hdac_codec *codec; 1438 int i; 1439 uint16_t statests; 1440 1441 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1442 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1443 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1444 /* We have found a codec. */ 1445 hdac_unlock(sc); 1446 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1447 M_HDAC, M_ZERO | M_NOWAIT); 1448 hdac_lock(sc); 1449 if (codec == NULL) { 1450 device_printf(sc->dev, 1451 "Unable to allocate memory for codec\n"); 1452 continue; 1453 } 1454 codec->commands = NULL; 1455 codec->responses_received = 0; 1456 codec->verbs_sent = 0; 1457 codec->sc = sc; 1458 codec->cad = i; 1459 sc->codecs[i] = codec; 1460 if (hdac_probe_codec(codec) != 0) 1461 break; 1462 } 1463 } 1464 /* All codecs have been probed, now try to attach drivers to them */ 1465 /* bus_generic_attach(sc->dev); */ 1466} 1467 1468/**************************************************************************** 1469 * void hdac_probe_codec(struct hdac_softc *, int) 1470 * 1471 * Probe a the given codec_id for available function groups. 1472 ****************************************************************************/ 1473static int 1474hdac_probe_codec(struct hdac_codec *codec) 1475{ 1476 struct hdac_softc *sc = codec->sc; 1477 struct hdac_devinfo *devinfo; 1478 uint32_t vendorid, revisionid, subnode; 1479 int startnode; 1480 int endnode; 1481 int i; 1482 nid_t cad = codec->cad; 1483 1484 HDA_BOOTVERBOSE( 1485 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1486 ); 1487 vendorid = hdac_command(sc, 1488 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1489 cad); 1490 revisionid = hdac_command(sc, 1491 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1492 cad); 1493 subnode = hdac_command(sc, 1494 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1495 cad); 1496 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1497 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1498 1499 HDA_BOOTVERBOSE( 1500 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1501 startnode, endnode); 1502 ); 1503 for (i = startnode; i < endnode; i++) { 1504 devinfo = hdac_probe_function(codec, i); 1505 if (devinfo != NULL) { 1506 /* XXX Ignore other FG. */ 1507 devinfo->vendor_id = 1508 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1509 devinfo->device_id = 1510 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1511 devinfo->revision_id = 1512 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1513 devinfo->stepping_id = 1514 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1515 HDA_BOOTVERBOSE( 1516 device_printf(sc->dev, 1517 "HDA_DEBUG: \tFound AFG nid=%d " 1518 "[startnode=%d endnode=%d]\n", 1519 devinfo->nid, startnode, endnode); 1520 ); 1521 return (1); 1522 } 1523 } 1524 1525 HDA_BOOTVERBOSE( 1526 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1527 ); 1528 return (0); 1529} 1530 1531static struct hdac_devinfo * 1532hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1533{ 1534 struct hdac_softc *sc = codec->sc; 1535 struct hdac_devinfo *devinfo; 1536 uint32_t fctgrptype; 1537 nid_t cad = codec->cad; 1538 1539 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1540 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1541 1542 /* XXX For now, ignore other FG. */ 1543 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1544 return (NULL); 1545 1546 hdac_unlock(sc); 1547 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1548 M_NOWAIT | M_ZERO); 1549 hdac_lock(sc); 1550 if (devinfo == NULL) { 1551 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1552 __func__); 1553 return (NULL); 1554 } 1555 1556 devinfo->nid = nid; 1557 devinfo->node_type = fctgrptype; 1558 devinfo->codec = codec; 1559 1560 hdac_add_child(sc, devinfo); 1561 1562 return (devinfo); 1563} 1564 1565static void 1566hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1567{ 1568 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1569 device_set_ivars(devinfo->dev, (void *)devinfo); 1570 /* XXX - Print more information when booting verbose??? */ 1571} 1572 1573static void 1574hdac_widget_connection_parse(struct hdac_widget *w) 1575{ 1576 struct hdac_softc *sc = w->devinfo->codec->sc; 1577 uint32_t res; 1578 int i, j, max, found, entnum, cnid; 1579 nid_t cad = w->devinfo->codec->cad; 1580 nid_t nid = w->nid; 1581 1582 res = hdac_command(sc, 1583 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1584 1585 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1586 1587 if (w->nconns < 1) 1588 return; 1589 1590 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1591 res = 0; 1592 i = 0; 1593 found = 0; 1594 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1595 1596 while (i < w->nconns) { 1597 res = hdac_command(sc, 1598 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1599 for (j = 0; j < entnum; j++) { 1600 cnid = res; 1601 cnid >>= (32 / entnum) * j; 1602 cnid &= (1 << (32 / entnum)) - 1; 1603 if (cnid == 0) 1604 continue; 1605 if (found > max) { 1606 device_printf(sc->dev, 1607 "node %d: Adding %d: " 1608 "Max connection reached!\n", 1609 nid, cnid); 1610 continue; 1611 } 1612 w->conns[found++] = cnid; 1613 } 1614 i += entnum; 1615 } 1616 1617 HDA_BOOTVERBOSE( 1618 if (w->nconns != found) { 1619 device_printf(sc->dev, 1620 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1621 "length=%d != found=%d\n", 1622 nid, w->nconns, found); 1623 } 1624 ); 1625} 1626 1627static uint32_t 1628hdac_widget_pin_getconfig(struct hdac_widget *w) 1629{ 1630 struct hdac_softc *sc; 1631 uint32_t config, id; 1632 nid_t cad, nid; 1633 1634 sc = w->devinfo->codec->sc; 1635 cad = w->devinfo->codec->cad; 1636 nid = w->nid; 1637 id = hdac_codec_id(w->devinfo); 1638 1639 config = hdac_command(sc, 1640 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1641 cad); 1642 /* 1643 * XXX REWRITE!!!! Don't argue! 1644 */ 1645 if (id == HDA_CODEC_ALC880 && 1646 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1647 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1648 /* 1649 * Super broken BIOS 1650 */ 1651 switch (nid) { 1652 case 20: 1653 break; 1654 case 21: 1655 break; 1656 case 22: 1657 break; 1658 case 23: 1659 break; 1660 case 24: /* MIC1 */ 1661 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1662 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1663 break; 1664 case 25: /* XXX MIC2 */ 1665 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1666 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1667 break; 1668 case 26: /* LINE1 */ 1669 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1670 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1671 break; 1672 case 27: /* XXX LINE2 */ 1673 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1674 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1675 break; 1676 case 28: /* CD */ 1677 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1678 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1679 break; 1680 case 30: 1681 break; 1682 case 31: 1683 break; 1684 default: 1685 break; 1686 } 1687 } 1688 1689 return (config); 1690} 1691 1692static void 1693hdac_widget_pin_parse(struct hdac_widget *w) 1694{ 1695 struct hdac_softc *sc = w->devinfo->codec->sc; 1696 uint32_t config, pincap; 1697 char *devstr, *connstr; 1698 nid_t cad = w->devinfo->codec->cad; 1699 nid_t nid = w->nid; 1700 1701 config = hdac_widget_pin_getconfig(w); 1702 w->wclass.pin.config = config; 1703 1704 pincap = hdac_command(sc, 1705 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1706 w->wclass.pin.cap = pincap; 1707 1708 w->wclass.pin.ctrl = hdac_command(sc, 1709 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1710 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1711 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1712 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1713 1714 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1715 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1716 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1717 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1718 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1719 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1720 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1721 w->param.eapdbtl = hdac_command(sc, 1722 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1723 w->param.eapdbtl &= 0x7; 1724 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1725 } else 1726 w->param.eapdbtl = HDAC_INVALID; 1727 1728 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1729 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1730 devstr = "line out"; 1731 break; 1732 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1733 devstr = "speaker"; 1734 break; 1735 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1736 devstr = "headphones out"; 1737 break; 1738 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1739 devstr = "CD"; 1740 break; 1741 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1742 devstr = "SPDIF out"; 1743 break; 1744 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1745 devstr = "digital (other) out"; 1746 break; 1747 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1748 devstr = "modem, line side"; 1749 break; 1750 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1751 devstr = "modem, handset side"; 1752 break; 1753 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1754 devstr = "line in"; 1755 break; 1756 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1757 devstr = "AUX"; 1758 break; 1759 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1760 devstr = "Mic in"; 1761 break; 1762 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1763 devstr = "telephony"; 1764 break; 1765 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1766 devstr = "SPDIF in"; 1767 break; 1768 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1769 devstr = "digital (other) in"; 1770 break; 1771 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1772 devstr = "other"; 1773 break; 1774 default: 1775 devstr = "unknown"; 1776 break; 1777 } 1778 1779 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1780 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1781 connstr = "jack"; 1782 break; 1783 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1784 connstr = "none"; 1785 break; 1786 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1787 connstr = "fixed"; 1788 break; 1789 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1790 connstr = "jack / fixed"; 1791 break; 1792 default: 1793 connstr = "unknown"; 1794 break; 1795 } 1796 1797 strlcat(w->name, ": ", sizeof(w->name)); 1798 strlcat(w->name, devstr, sizeof(w->name)); 1799 strlcat(w->name, " (", sizeof(w->name)); 1800 strlcat(w->name, connstr, sizeof(w->name)); 1801 strlcat(w->name, ")", sizeof(w->name)); 1802} 1803 1804static void 1805hdac_widget_parse(struct hdac_widget *w) 1806{ 1807 struct hdac_softc *sc = w->devinfo->codec->sc; 1808 uint32_t wcap, cap; 1809 char *typestr; 1810 nid_t cad = w->devinfo->codec->cad; 1811 nid_t nid = w->nid; 1812 1813 wcap = hdac_command(sc, 1814 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1815 cad); 1816 w->param.widget_cap = wcap; 1817 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1818 1819 switch (w->type) { 1820 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1821 typestr = "audio output"; 1822 break; 1823 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1824 typestr = "audio input"; 1825 break; 1826 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1827 typestr = "audio mixer"; 1828 break; 1829 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1830 typestr = "audio selector"; 1831 break; 1832 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1833 typestr = "pin"; 1834 break; 1835 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1836 typestr = "power widget"; 1837 break; 1838 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1839 typestr = "volume widget"; 1840 break; 1841 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1842 typestr = "beep widget"; 1843 break; 1844 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1845 typestr = "vendor widget"; 1846 break; 1847 default: 1848 typestr = "unknown type"; 1849 break; 1850 } 1851 1852 strlcpy(w->name, typestr, sizeof(w->name)); 1853 1854 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1855 hdac_command(sc, 1856 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1857 cad); 1858 DELAY(1000); 1859 } 1860 1861 hdac_widget_connection_parse(w); 1862 1863 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1864 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1865 w->param.outamp_cap = 1866 hdac_command(sc, 1867 HDA_CMD_GET_PARAMETER(cad, nid, 1868 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1869 else 1870 w->param.outamp_cap = 1871 w->devinfo->function.audio.outamp_cap; 1872 } else 1873 w->param.outamp_cap = 0; 1874 1875 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1876 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1877 w->param.inamp_cap = 1878 hdac_command(sc, 1879 HDA_CMD_GET_PARAMETER(cad, nid, 1880 HDA_PARAM_INPUT_AMP_CAP), cad); 1881 else 1882 w->param.inamp_cap = 1883 w->devinfo->function.audio.inamp_cap; 1884 } else 1885 w->param.inamp_cap = 0; 1886 1887 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1888 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1889 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1890 cap = hdac_command(sc, 1891 HDA_CMD_GET_PARAMETER(cad, nid, 1892 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1893 w->param.supp_stream_formats = (cap != 0) ? cap : 1894 w->devinfo->function.audio.supp_stream_formats; 1895 cap = hdac_command(sc, 1896 HDA_CMD_GET_PARAMETER(cad, nid, 1897 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1898 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1899 w->devinfo->function.audio.supp_pcm_size_rate; 1900 } else { 1901 w->param.supp_stream_formats = 1902 w->devinfo->function.audio.supp_stream_formats; 1903 w->param.supp_pcm_size_rate = 1904 w->devinfo->function.audio.supp_pcm_size_rate; 1905 } 1906 } else { 1907 w->param.supp_stream_formats = 0; 1908 w->param.supp_pcm_size_rate = 0; 1909 } 1910 1911 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1912 hdac_widget_pin_parse(w); 1913} 1914 1915static struct hdac_widget * 1916hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1917{ 1918 if (devinfo == NULL || devinfo->widget == NULL || 1919 nid < devinfo->startnode || nid >= devinfo->endnode) 1920 return (NULL); 1921 return (&devinfo->widget[nid - devinfo->startnode]); 1922} 1923 1924static __inline int 1925hda_poll_channel(struct hdac_chan *ch) 1926{ 1927 uint32_t sz, delta; 1928 volatile uint32_t ptr; 1929 1930 if (ch->active == 0) 1931 return (0); 1932 1933 sz = ch->blksz * ch->blkcnt; 1934 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1935 ch->ptr = ptr; 1936 ptr %= sz; 1937 ptr &= ~(ch->blksz - 1); 1938 delta = (sz + ptr - ch->prevptr) % sz; 1939 1940 if (delta < ch->blksz) 1941 return (0); 1942 1943 ch->prevptr = ptr; 1944 1945 return (1); 1946} 1947 1948#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1949 1950static void 1951hda_poll_callback(void *arg) 1952{ 1953 struct hdac_softc *sc = arg; 1954 uint32_t trigger = 0; 1955 1956 if (sc == NULL) 1957 return; 1958 1959 hdac_lock(sc); 1960 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 1961 hdac_unlock(sc); 1962 return; 1963 } 1964 1965 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 1966 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 1967 1968 /* XXX */ 1969 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 1970 hda_poll_callback, sc); 1971 1972 hdac_unlock(sc); 1973 1974 if (trigger & 1) 1975 chn_intr(sc->play.c); 1976 if (trigger & 2) 1977 chn_intr(sc->rec.c); 1978} 1979 1980static int 1981hdac_rirb_flush(struct hdac_softc *sc) 1982{ 1983 struct hdac_rirb *rirb_base, *rirb; 1984 struct hdac_codec *codec; 1985 struct hdac_command_list *commands; 1986 nid_t cad; 1987 uint32_t resp; 1988 uint8_t rirbwp; 1989 int ret = 0; 1990 1991 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1992 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 1993 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1994 BUS_DMASYNC_POSTREAD); 1995 1996 while (sc->rirb_rp != rirbwp) { 1997 sc->rirb_rp++; 1998 sc->rirb_rp %= sc->rirb_size; 1999 rirb = &rirb_base[sc->rirb_rp]; 2000 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2001 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2002 sc->codecs[cad] == NULL) 2003 continue; 2004 resp = rirb->response; 2005 codec = sc->codecs[cad]; 2006 commands = codec->commands; 2007 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2008 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2009 ((resp >> 26) & 0xffff); 2010 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2011 } else if (commands != NULL && commands->num_commands > 0 && 2012 codec->responses_received < commands->num_commands) 2013 commands->responses[codec->responses_received++] = 2014 resp; 2015 ret++; 2016 } 2017 2018 return (ret); 2019} 2020 2021static int 2022hdac_unsolq_flush(struct hdac_softc *sc) 2023{ 2024 nid_t cad; 2025 uint32_t tag; 2026 int ret = 0; 2027 2028 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2029 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2030 while (sc->unsolq_rp != sc->unsolq_wp) { 2031 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2032 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2033 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2034 hdac_unsolicited_handler(sc->codecs[cad], tag); 2035 ret++; 2036 } 2037 sc->unsolq_st = HDAC_UNSOLQ_READY; 2038 } 2039 2040 return (ret); 2041} 2042 2043static void 2044hdac_poll_callback(void *arg) 2045{ 2046 struct hdac_softc *sc = arg; 2047 if (sc == NULL) 2048 return; 2049 2050 hdac_lock(sc); 2051 if (sc->polling == 0) { 2052 hdac_unlock(sc); 2053 return; 2054 } 2055 hdac_rirb_flush(sc); 2056 hdac_unsolq_flush(sc); 2057 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2058 hdac_poll_callback, sc); 2059 hdac_unlock(sc); 2060} 2061 2062static void 2063hdac_stream_stop(struct hdac_chan *ch) 2064{ 2065 struct hdac_softc *sc = ch->devinfo->codec->sc; 2066 uint32_t ctl; 2067 2068 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2069 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2070 HDAC_SDCTL_RUN); 2071 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2072 2073 ch->active = 0; 2074 2075 if (sc->polling != 0) { 2076 int pollticks; 2077 2078 if (hda_chan_active(sc) == 0) { 2079 callout_stop(&sc->poll_hda); 2080 sc->poll_ticks = 1; 2081 } else { 2082 if (sc->play.active != 0) 2083 ch = &sc->play; 2084 else 2085 ch = &sc->rec; 2086 pollticks = ((uint64_t)hz * ch->blksz) / 2087 ((uint64_t)sndbuf_getbps(ch->b) * 2088 sndbuf_getspd(ch->b)); 2089 pollticks >>= 2; 2090 if (pollticks > hz) 2091 pollticks = hz; 2092 if (pollticks < 1) { 2093 HDA_BOOTVERBOSE( 2094 device_printf(sc->dev, 2095 "%s: pollticks=%d < 1 !\n", 2096 __func__, pollticks); 2097 ); 2098 pollticks = 1; 2099 } 2100 if (pollticks > sc->poll_ticks) { 2101 HDA_BOOTVERBOSE( 2102 device_printf(sc->dev, 2103 "%s: pollticks %d -> %d\n", 2104 __func__, sc->poll_ticks, 2105 pollticks); 2106 ); 2107 sc->poll_ticks = pollticks; 2108 callout_reset(&sc->poll_hda, 1, 2109 hda_poll_callback, sc); 2110 } 2111 } 2112 } else { 2113 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2114 ctl &= ~(1 << (ch->off >> 5)); 2115 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2116 } 2117} 2118 2119static void 2120hdac_stream_start(struct hdac_chan *ch) 2121{ 2122 struct hdac_softc *sc = ch->devinfo->codec->sc; 2123 uint32_t ctl; 2124 2125 if (sc->polling != 0) { 2126 int pollticks; 2127 2128 pollticks = ((uint64_t)hz * ch->blksz) / 2129 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2130 pollticks >>= 2; 2131 if (pollticks > hz) 2132 pollticks = hz; 2133 if (pollticks < 1) { 2134 HDA_BOOTVERBOSE( 2135 device_printf(sc->dev, 2136 "%s: pollticks=%d < 1 !\n", 2137 __func__, pollticks); 2138 ); 2139 pollticks = 1; 2140 } 2141 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2142 HDA_BOOTVERBOSE( 2143 if (hda_chan_active(sc) == 0) { 2144 device_printf(sc->dev, 2145 "%s: pollticks=%d\n", 2146 __func__, pollticks); 2147 } else { 2148 device_printf(sc->dev, 2149 "%s: pollticks %d -> %d\n", 2150 __func__, sc->poll_ticks, 2151 pollticks); 2152 } 2153 ); 2154 sc->poll_ticks = pollticks; 2155 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2156 sc); 2157 } 2158 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2159 ctl |= HDAC_SDCTL_RUN; 2160 } else { 2161 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2162 ctl |= 1 << (ch->off >> 5); 2163 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2164 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2165 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2166 HDAC_SDCTL_RUN; 2167 } 2168 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2169 2170 ch->active = 1; 2171} 2172 2173static void 2174hdac_stream_reset(struct hdac_chan *ch) 2175{ 2176 struct hdac_softc *sc = ch->devinfo->codec->sc; 2177 int timeout = 1000; 2178 int to = timeout; 2179 uint32_t ctl; 2180 2181 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2182 ctl |= HDAC_SDCTL_SRST; 2183 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2184 do { 2185 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2186 if (ctl & HDAC_SDCTL_SRST) 2187 break; 2188 DELAY(10); 2189 } while (--to); 2190 if (!(ctl & HDAC_SDCTL_SRST)) { 2191 device_printf(sc->dev, "timeout in reset\n"); 2192 } 2193 ctl &= ~HDAC_SDCTL_SRST; 2194 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2195 to = timeout; 2196 do { 2197 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2198 if (!(ctl & HDAC_SDCTL_SRST)) 2199 break; 2200 DELAY(10); 2201 } while (--to); 2202 if (ctl & HDAC_SDCTL_SRST) 2203 device_printf(sc->dev, "can't reset!\n"); 2204} 2205 2206static void 2207hdac_stream_setid(struct hdac_chan *ch) 2208{ 2209 struct hdac_softc *sc = ch->devinfo->codec->sc; 2210 uint32_t ctl; 2211 2212 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2213 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2214 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2215 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2216} 2217 2218static void 2219hdac_bdl_setup(struct hdac_chan *ch) 2220{ 2221 struct hdac_softc *sc = ch->devinfo->codec->sc; 2222 struct hdac_bdle *bdle; 2223 uint64_t addr; 2224 uint32_t blksz, blkcnt; 2225 int i; 2226 2227 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2228 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2229 2230 if (sc->polling != 0) { 2231 blksz = ch->blksz * ch->blkcnt; 2232 blkcnt = 1; 2233 } else { 2234 blksz = ch->blksz; 2235 blkcnt = ch->blkcnt; 2236 } 2237 2238 for (i = 0; i < blkcnt; i++, bdle++) { 2239 bdle->addrl = (uint32_t)addr; 2240 bdle->addrh = (uint32_t)(addr >> 32); 2241 bdle->len = blksz; 2242 bdle->ioc = 1 ^ sc->polling; 2243 addr += blksz; 2244 } 2245 2246 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2247 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2248 addr = ch->bdl_dma.dma_paddr; 2249 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2250 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2251} 2252 2253static int 2254hdac_bdl_alloc(struct hdac_chan *ch) 2255{ 2256 struct hdac_softc *sc = ch->devinfo->codec->sc; 2257 int rc; 2258 2259 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2260 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2261 if (rc) { 2262 device_printf(sc->dev, "can't alloc bdl\n"); 2263 return (rc); 2264 } 2265 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2266 2267 return (0); 2268} 2269 2270static void 2271hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2272 int index, int lmute, int rmute, 2273 int left, int right, int dir) 2274{ 2275 uint16_t v = 0; 2276 2277 if (sc == NULL) 2278 return; 2279 2280 if (left != right || lmute != rmute) { 2281 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2282 (lmute << 7) | left; 2283 hdac_command(sc, 2284 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2285 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2286 (rmute << 7) | right; 2287 } else 2288 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2289 (lmute << 7) | left; 2290 2291 hdac_command(sc, 2292 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2293} 2294 2295static void 2296hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2297 int left, int right) 2298{ 2299 struct hdac_softc *sc; 2300 nid_t nid, cad; 2301 int lmute, rmute; 2302 2303 if (ctl == NULL || ctl->widget == NULL || 2304 ctl->widget->devinfo == NULL || 2305 ctl->widget->devinfo->codec == NULL || 2306 ctl->widget->devinfo->codec->sc == NULL) 2307 return; 2308 2309 sc = ctl->widget->devinfo->codec->sc; 2310 cad = ctl->widget->devinfo->codec->cad; 2311 nid = ctl->widget->nid; 2312 2313 if (mute == HDA_AMP_MUTE_DEFAULT) { 2314 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2315 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2316 } else { 2317 lmute = HDA_AMP_LEFT_MUTED(mute); 2318 rmute = HDA_AMP_RIGHT_MUTED(mute); 2319 } 2320 2321 if (ctl->dir & HDA_CTL_OUT) 2322 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2323 lmute, rmute, left, right, 0); 2324 if (ctl->dir & HDA_CTL_IN) 2325 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2326 lmute, rmute, left, right, 1); 2327 ctl->left = left; 2328 ctl->right = right; 2329} 2330 2331static void 2332hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2333{ 2334 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2335 return; 2336 hdac_command(w->devinfo->codec->sc, 2337 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2338 w->nid, index), w->devinfo->codec->cad); 2339 w->selconn = index; 2340} 2341 2342 2343/**************************************************************************** 2344 * uint32_t hdac_command_sendone_internal 2345 * 2346 * Wrapper function that sends only one command to a given codec 2347 ****************************************************************************/ 2348static uint32_t 2349hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2350{ 2351 struct hdac_command_list cl; 2352 uint32_t response = HDAC_INVALID; 2353 2354 if (!hdac_lockowned(sc)) 2355 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2356 cl.num_commands = 1; 2357 cl.verbs = &verb; 2358 cl.responses = &response; 2359 2360 hdac_command_send_internal(sc, &cl, cad); 2361 2362 return (response); 2363} 2364 2365/**************************************************************************** 2366 * hdac_command_send_internal 2367 * 2368 * Send a command list to the codec via the corb. We queue as much verbs as 2369 * we can and msleep on the codec. When the interrupt get the responses 2370 * back from the rirb, it will wake us up so we can queue the remaining verbs 2371 * if any. 2372 ****************************************************************************/ 2373static void 2374hdac_command_send_internal(struct hdac_softc *sc, 2375 struct hdac_command_list *commands, nid_t cad) 2376{ 2377 struct hdac_codec *codec; 2378 int corbrp; 2379 uint32_t *corb; 2380 int timeout; 2381 int retry = 10; 2382 struct hdac_rirb *rirb_base; 2383 2384 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2385 commands->num_commands < 1) 2386 return; 2387 2388 codec = sc->codecs[cad]; 2389 codec->commands = commands; 2390 codec->responses_received = 0; 2391 codec->verbs_sent = 0; 2392 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2393 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2394 2395 do { 2396 if (codec->verbs_sent != commands->num_commands) { 2397 /* Queue as many verbs as possible */ 2398 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2399 bus_dmamap_sync(sc->corb_dma.dma_tag, 2400 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2401 while (codec->verbs_sent != commands->num_commands && 2402 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2403 sc->corb_wp++; 2404 sc->corb_wp %= sc->corb_size; 2405 corb[sc->corb_wp] = 2406 commands->verbs[codec->verbs_sent++]; 2407 } 2408 2409 /* Send the verbs to the codecs */ 2410 bus_dmamap_sync(sc->corb_dma.dma_tag, 2411 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2412 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2413 } 2414 2415 timeout = 1000; 2416 while (hdac_rirb_flush(sc) == 0 && --timeout) 2417 DELAY(10); 2418 } while ((codec->verbs_sent != commands->num_commands || 2419 codec->responses_received != commands->num_commands) && --retry); 2420 2421 if (retry == 0) 2422 device_printf(sc->dev, 2423 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2424 __func__, commands->num_commands, codec->verbs_sent, 2425 codec->responses_received); 2426 2427 codec->commands = NULL; 2428 codec->responses_received = 0; 2429 codec->verbs_sent = 0; 2430 2431 hdac_unsolq_flush(sc); 2432} 2433 2434 2435/**************************************************************************** 2436 * Device Methods 2437 ****************************************************************************/ 2438 2439/**************************************************************************** 2440 * int hdac_probe(device_t) 2441 * 2442 * Probe for the presence of an hdac. If none is found, check for a generic 2443 * match using the subclass of the device. 2444 ****************************************************************************/ 2445static int 2446hdac_probe(device_t dev) 2447{ 2448 int i, result; 2449 uint32_t model; 2450 uint16_t class, subclass; 2451 char desc[64]; 2452 2453 model = (uint32_t)pci_get_device(dev) << 16; 2454 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2455 class = pci_get_class(dev); 2456 subclass = pci_get_subclass(dev); 2457 2458 bzero(desc, sizeof(desc)); 2459 result = ENXIO; 2460 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2461 if (hdac_devices[i].model == model) { 2462 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2463 result = BUS_PROBE_DEFAULT; 2464 break; 2465 } 2466 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2467 class == PCIC_MULTIMEDIA && 2468 subclass == PCIS_MULTIMEDIA_HDA) { 2469 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2470 result = BUS_PROBE_GENERIC; 2471 break; 2472 } 2473 } 2474 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2475 subclass == PCIS_MULTIMEDIA_HDA) { 2476 strlcpy(desc, "Generic", sizeof(desc)); 2477 result = BUS_PROBE_GENERIC; 2478 } 2479 if (result != ENXIO) { 2480 strlcat(desc, " High Definition Audio Controller", 2481 sizeof(desc)); 2482 device_set_desc_copy(dev, desc); 2483 } 2484 2485 return (result); 2486} 2487 2488static void * 2489hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2490 struct pcm_channel *c, int dir) 2491{ 2492 struct hdac_devinfo *devinfo = data; 2493 struct hdac_softc *sc = devinfo->codec->sc; 2494 struct hdac_chan *ch; 2495 2496 hdac_lock(sc); 2497 if (dir == PCMDIR_PLAY) { 2498 ch = &sc->play; 2499 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2500 ch->dir = PCMDIR_PLAY; 2501 ch->sid = ++sc->streamcnt; 2502 devinfo->function.audio.playcnt++; 2503 } else { 2504 ch = &sc->rec; 2505 ch->off = devinfo->function.audio.reccnt << 5; 2506 ch->dir = PCMDIR_REC; 2507 ch->sid = ++sc->streamcnt; 2508 devinfo->function.audio.reccnt++; 2509 } 2510 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2511 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2512 ch->pcmrates[0] = 48000; 2513 ch->pcmrates[1] = 0; 2514 } 2515 ch->b = b; 2516 ch->c = c; 2517 ch->devinfo = devinfo; 2518 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2519 ch->blkcnt = sc->chan_blkcnt; 2520 hdac_unlock(sc); 2521 2522 if (hdac_bdl_alloc(ch) != 0) { 2523 ch->blkcnt = 0; 2524 return (NULL); 2525 } 2526 2527 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2528 return (NULL); 2529 2530 hdac_dma_nocache(ch->b->buf); 2531 2532 return (ch); 2533} 2534 2535static int 2536hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2537{ 2538 struct hdac_chan *ch = data; 2539 int i; 2540 2541 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2542 if (format == ch->caps.fmtlist[i]) { 2543 ch->fmt = format; 2544 return (0); 2545 } 2546 } 2547 2548 return (EINVAL); 2549} 2550 2551static int 2552hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2553{ 2554 struct hdac_chan *ch = data; 2555 uint32_t spd = 0, threshold; 2556 int i; 2557 2558 for (i = 0; ch->pcmrates[i] != 0; i++) { 2559 spd = ch->pcmrates[i]; 2560 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2561 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2562 if (speed < threshold) 2563 break; 2564 } 2565 2566 if (spd == 0) /* impossible */ 2567 ch->spd = 48000; 2568 else 2569 ch->spd = spd; 2570 2571 return (ch->spd); 2572} 2573 2574static void 2575hdac_stream_setup(struct hdac_chan *ch) 2576{ 2577 struct hdac_softc *sc = ch->devinfo->codec->sc; 2578 int i; 2579 nid_t cad = ch->devinfo->codec->cad; 2580 uint16_t fmt; 2581 2582 fmt = 0; 2583 if (ch->fmt & AFMT_S16_LE) 2584 fmt |= ch->bit16 << 4; 2585 else if (ch->fmt & AFMT_S32_LE) 2586 fmt |= ch->bit32 << 4; 2587 else 2588 fmt |= 1 << 4; 2589 2590 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2591 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2592 fmt |= hda_rate_tab[i].base; 2593 fmt |= hda_rate_tab[i].mul; 2594 fmt |= hda_rate_tab[i].div; 2595 break; 2596 } 2597 } 2598 2599 if (ch->fmt & AFMT_STEREO) 2600 fmt |= 1; 2601 2602 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2603 2604 for (i = 0; ch->io[i] != -1; i++) { 2605 HDA_BOOTVERBOSE( 2606 device_printf(sc->dev, 2607 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2608 "fmt=0x%08x\n", 2609 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2610 ch->io[i], fmt); 2611 ); 2612 hdac_command(sc, 2613 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2614 hdac_command(sc, 2615 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2616 ch->sid << 4), cad); 2617 } 2618} 2619 2620static int 2621hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2622{ 2623 struct hdac_chan *ch = data; 2624 struct hdac_softc *sc = ch->devinfo->codec->sc; 2625 2626 blksz &= ~0x7f; 2627 if (blksz < 0x80) 2628 blksz = 0x80; 2629 2630 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2631 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2632 2633 if ((sndbuf_getblksz(ch->b) != blksz || 2634 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2635 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2636 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2637 __func__, blksz, ch->blkcnt); 2638 2639 ch->blksz = sndbuf_getblksz(ch->b); 2640 2641 return (ch->blksz); 2642} 2643 2644static void 2645hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2646{ 2647 struct hdac_devinfo *devinfo = ch->devinfo; 2648 nid_t cad = devinfo->codec->cad; 2649 int i; 2650 2651 hdac_stream_stop(ch); 2652 2653 for (i = 0; ch->io[i] != -1; i++) { 2654 hdac_command(sc, 2655 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2656 0), cad); 2657 } 2658} 2659 2660static void 2661hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2662{ 2663 ch->ptr = 0; 2664 ch->prevptr = 0; 2665 hdac_stream_stop(ch); 2666 hdac_stream_reset(ch); 2667 hdac_bdl_setup(ch); 2668 hdac_stream_setid(ch); 2669 hdac_stream_setup(ch); 2670 hdac_stream_start(ch); 2671} 2672 2673static int 2674hdac_channel_trigger(kobj_t obj, void *data, int go) 2675{ 2676 struct hdac_chan *ch = data; 2677 struct hdac_softc *sc = ch->devinfo->codec->sc; 2678 2679 hdac_lock(sc); 2680 switch (go) { 2681 case PCMTRIG_START: 2682 hdac_channel_start(sc, ch); 2683 break; 2684 case PCMTRIG_STOP: 2685 case PCMTRIG_ABORT: 2686 hdac_channel_stop(sc, ch); 2687 break; 2688 } 2689 hdac_unlock(sc); 2690 2691 return (0); 2692} 2693 2694static int 2695hdac_channel_getptr(kobj_t obj, void *data) 2696{ 2697 struct hdac_chan *ch = data; 2698 struct hdac_softc *sc = ch->devinfo->codec->sc; 2699 uint32_t ptr; 2700 2701 hdac_lock(sc); 2702 if (sc->polling != 0) 2703 ptr = ch->ptr; 2704 else 2705 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2706 hdac_unlock(sc); 2707 2708 /* 2709 * Round to available space and force 128 bytes aligment. 2710 */ 2711 ptr %= ch->blksz * ch->blkcnt; 2712 ptr &= ~0x7f; 2713 2714 return (ptr); 2715} 2716 2717static struct pcmchan_caps * 2718hdac_channel_getcaps(kobj_t obj, void *data) 2719{ 2720 return (&((struct hdac_chan *)data)->caps); 2721} 2722 2723static kobj_method_t hdac_channel_methods[] = { 2724 KOBJMETHOD(channel_init, hdac_channel_init), 2725 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2726 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2727 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2728 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2729 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2730 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2731 { 0, 0 } 2732}; 2733CHANNEL_DECLARE(hdac_channel); 2734 2735static int 2736hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2737{ 2738 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2739 struct hdac_softc *sc = devinfo->codec->sc; 2740 struct hdac_widget *w, *cw; 2741 struct hdac_audio_ctl *ctl; 2742 uint32_t mask, recmask, id; 2743 int i, j, softpcmvol; 2744 nid_t cad; 2745 2746 hdac_lock(sc); 2747 2748 mask = 0; 2749 recmask = 0; 2750 2751 id = hdac_codec_id(devinfo); 2752 cad = devinfo->codec->cad; 2753 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2754 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2755 sc->pci_subvendor) && 2756 hdac_hp_switch[i].id == id)) 2757 continue; 2758 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2759 if (w != NULL && w->enable != 0 2760 && w->type == 2761 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2762 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2763 hdac_command(sc, 2764 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2765 w->nid, 2766 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2767 HDAC_UNSOLTAG_EVENT_HP), cad); 2768 hdac_hp_switch_handler(devinfo); 2769 HDA_BOOTVERBOSE( 2770 device_printf(sc->dev, 2771 "HDA_DEBUG: Enabling headphone/speaker " 2772 "audio routing switching:\n"); 2773 device_printf(sc->dev, 2774 "HDA_DEBUG: \tindex=%d nid=%d " 2775 "pci_subvendor=0x%08x " 2776 "codec=0x%08x\n", 2777 i, w->nid, sc->pci_subvendor, id); 2778 ); 2779 } 2780 break; 2781 } 2782 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2783 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2784 sc->pci_subvendor) && 2785 hdac_eapd_switch[i].id == id)) 2786 continue; 2787 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2788 if (w == NULL || w->enable == 0) 2789 break; 2790 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2791 w->param.eapdbtl == HDAC_INVALID) 2792 break; 2793 mask |= SOUND_MASK_OGAIN; 2794 break; 2795 } 2796 2797 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2798 w = hdac_widget_get(devinfo, i); 2799 if (w == NULL || w->enable == 0) 2800 continue; 2801 mask |= w->ctlflags; 2802 if (!(w->pflags & HDA_ADC_RECSEL)) 2803 continue; 2804 for (j = 0; j < w->nconns; j++) { 2805 cw = hdac_widget_get(devinfo, w->conns[j]); 2806 if (cw == NULL || cw->enable == 0) 2807 continue; 2808 recmask |= cw->ctlflags; 2809 } 2810 } 2811 2812 if (!(mask & SOUND_MASK_PCM)) { 2813 softpcmvol = 1; 2814 mask |= SOUND_MASK_PCM; 2815 } else 2816 softpcmvol = (devinfo->function.audio.quirks & 2817 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2818 2819 i = 0; 2820 ctl = NULL; 2821 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2822 if (ctl->widget == NULL || ctl->enable == 0) 2823 continue; 2824 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2825 continue; 2826 if (ctl->step > 0) 2827 break; 2828 } 2829 2830 if (softpcmvol == 1 || ctl == NULL) { 2831 struct snddev_info *d = NULL; 2832 d = device_get_softc(sc->dev); 2833 if (d != NULL) { 2834 d->flags |= SD_F_SOFTPCMVOL; 2835 HDA_BOOTVERBOSE( 2836 device_printf(sc->dev, 2837 "HDA_DEBUG: %s Soft PCM volume\n", 2838 (softpcmvol == 1) ? 2839 "Forcing" : "Enabling"); 2840 ); 2841 } 2842 i = 0; 2843 /* 2844 * XXX Temporary quirk for STAC9220, until the parser 2845 * become smarter. 2846 */ 2847 if (id == HDA_CODEC_STAC9220) { 2848 mask |= SOUND_MASK_VOLUME; 2849 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2850 NULL) { 2851 if (ctl->widget == NULL || ctl->enable == 0) 2852 continue; 2853 if (ctl->widget->nid == 11 && ctl->index == 0) { 2854 ctl->ossmask = SOUND_MASK_VOLUME; 2855 ctl->ossval = 100 | (100 << 8); 2856 } else 2857 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2858 } 2859 } else { 2860 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2861 SOUND_MASK_PCM); 2862 if (!(mask & SOUND_MASK_VOLUME)) 2863 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2864 SOUND_MIXER_NONE); 2865 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2866 NULL) { 2867 if (ctl->widget == NULL || ctl->enable == 0) 2868 continue; 2869 if (!HDA_FLAG_MATCH(ctl->ossmask, 2870 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2871 continue; 2872 if (!(ctl->mute == 1 && ctl->step == 0)) 2873 ctl->enable = 0; 2874 } 2875 } 2876 } 2877 2878 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2879 2880 mix_setrecdevs(m, recmask); 2881 mix_setdevs(m, mask); 2882 2883 hdac_unlock(sc); 2884 2885 return (0); 2886} 2887 2888static int 2889hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2890 unsigned left, unsigned right) 2891{ 2892 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2893 struct hdac_softc *sc = devinfo->codec->sc; 2894 struct hdac_widget *w; 2895 struct hdac_audio_ctl *ctl; 2896 uint32_t id, mute; 2897 int lvol, rvol, mlvol, mrvol; 2898 int i = 0; 2899 2900 hdac_lock(sc); 2901 if (dev == SOUND_MIXER_OGAIN) { 2902 uint32_t orig; 2903 /*if (left != right || !(left == 0 || left == 1)) { 2904 hdac_unlock(sc); 2905 return (-1); 2906 }*/ 2907 id = hdac_codec_id(devinfo); 2908 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2909 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2910 sc->pci_subvendor) && 2911 hdac_eapd_switch[i].id == id) 2912 break; 2913 } 2914 if (i >= HDAC_EAPD_SWITCH_LEN) { 2915 hdac_unlock(sc); 2916 return (-1); 2917 } 2918 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2919 if (w == NULL || 2920 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2921 w->param.eapdbtl == HDAC_INVALID) { 2922 hdac_unlock(sc); 2923 return (-1); 2924 } 2925 orig = w->param.eapdbtl; 2926 if (left == 0) 2927 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2928 else 2929 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2930 if (orig != w->param.eapdbtl) { 2931 uint32_t val; 2932 2933 if (hdac_eapd_switch[i].hp_switch != 0) 2934 hdac_hp_switch_handler(devinfo); 2935 val = w->param.eapdbtl; 2936 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2937 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2938 hdac_command(sc, 2939 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2940 w->nid, val), devinfo->codec->cad); 2941 } 2942 hdac_unlock(sc); 2943 return (left | (left << 8)); 2944 } 2945 if (dev == SOUND_MIXER_VOLUME) 2946 devinfo->function.audio.mvol = left | (right << 8); 2947 2948 mlvol = devinfo->function.audio.mvol & 0x7f; 2949 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2950 lvol = 0; 2951 rvol = 0; 2952 2953 i = 0; 2954 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2955 if (ctl->widget == NULL || ctl->enable == 0 || 2956 !(ctl->ossmask & (1 << dev))) 2957 continue; 2958 switch (dev) { 2959 case SOUND_MIXER_VOLUME: 2960 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2961 lvol = (lvol * ctl->step) / 100; 2962 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2963 rvol = (rvol * ctl->step) / 100; 2964 break; 2965 default: 2966 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2967 lvol = (left * mlvol) / 100; 2968 lvol = (lvol * ctl->step) / 100; 2969 rvol = (right * mrvol) / 100; 2970 rvol = (rvol * ctl->step) / 100; 2971 } else { 2972 lvol = (left * ctl->step) / 100; 2973 rvol = (right * ctl->step) / 100; 2974 } 2975 ctl->ossval = left | (right << 8); 2976 break; 2977 } 2978 mute = 0; 2979 if (ctl->step < 1) { 2980 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2981 (ctl->muted & HDA_AMP_MUTE_LEFT); 2982 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2983 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2984 } else { 2985 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2986 (ctl->muted & HDA_AMP_MUTE_LEFT); 2987 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2988 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2989 } 2990 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2991 } 2992 hdac_unlock(sc); 2993 2994 return (left | (right << 8)); 2995} 2996 2997static int 2998hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2999{ 3000 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3001 struct hdac_widget *w, *cw; 3002 struct hdac_softc *sc = devinfo->codec->sc; 3003 uint32_t ret = src, target; 3004 int i, j; 3005 3006 target = 0; 3007 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3008 if (src & (1 << i)) { 3009 target = 1 << i; 3010 break; 3011 } 3012 } 3013 3014 hdac_lock(sc); 3015 3016 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3017 w = hdac_widget_get(devinfo, i); 3018 if (w == NULL || w->enable == 0) 3019 continue; 3020 if (!(w->pflags & HDA_ADC_RECSEL)) 3021 continue; 3022 for (j = 0; j < w->nconns; j++) { 3023 cw = hdac_widget_get(devinfo, w->conns[j]); 3024 if (cw == NULL || cw->enable == 0) 3025 continue; 3026 if ((target == SOUND_MASK_VOLUME && 3027 cw->type != 3028 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3029 (target != SOUND_MASK_VOLUME && 3030 cw->type == 3031 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3032 continue; 3033 if (cw->ctlflags & target) { 3034 hdac_widget_connection_select(w, j); 3035 ret = target; 3036 j += w->nconns; 3037 } 3038 } 3039 } 3040 3041 hdac_unlock(sc); 3042 3043 return (ret); 3044} 3045 3046static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3047 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3048 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3049 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3050 { 0, 0 } 3051}; 3052MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3053 3054/**************************************************************************** 3055 * int hdac_attach(device_t) 3056 * 3057 * Attach the device into the kernel. Interrupts usually won't be enabled 3058 * when this function is called. Setup everything that doesn't require 3059 * interrupts and defer probing of codecs until interrupts are enabled. 3060 ****************************************************************************/ 3061static int 3062hdac_attach(device_t dev) 3063{ 3064 struct hdac_softc *sc; 3065 int result; 3066 int i = 0; 3067 3068 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3069 if (sc == NULL) { 3070 device_printf(dev, "cannot allocate softc\n"); 3071 return (ENOMEM); 3072 } 3073 3074 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3075 if (sc->lock == NULL) { 3076 device_printf(dev, "mutex creation failed\n"); 3077 free(sc, M_DEVBUF); 3078 return (ENOMEM); 3079 } 3080 3081 sc->dev = dev; 3082 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3083 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3084 3085 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3086 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3087 3088 sc->poll_ticks = 1; 3089 if (resource_int_value(device_get_name(sc->dev), 3090 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3091 sc->polling = 1; 3092 else 3093 sc->polling = 0; 3094 3095 sc->chan_size = pcm_getbuffersize(dev, 3096 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3097 3098 if (resource_int_value(device_get_name(sc->dev), 3099 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3100 i &= ~0x7f; 3101 if (i < 0x80) 3102 i = 0x80; 3103 sc->chan_blkcnt = sc->chan_size / i; 3104 i = 0; 3105 while (sc->chan_blkcnt >> i) 3106 i++; 3107 sc->chan_blkcnt = 1 << (i - 1); 3108 if (sc->chan_blkcnt < HDA_BDL_MIN) 3109 sc->chan_blkcnt = HDA_BDL_MIN; 3110 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3111 sc->chan_blkcnt = HDA_BDL_MAX; 3112 } else 3113 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3114 3115 result = bus_dma_tag_create(NULL, /* parent */ 3116 HDAC_DMA_ALIGNMENT, /* alignment */ 3117 0, /* boundary */ 3118 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3119 BUS_SPACE_MAXADDR, /* highaddr */ 3120 NULL, /* filtfunc */ 3121 NULL, /* fistfuncarg */ 3122 sc->chan_size, /* maxsize */ 3123 1, /* nsegments */ 3124 sc->chan_size, /* maxsegsz */ 3125 0, /* flags */ 3126 NULL, /* lockfunc */ 3127 NULL, /* lockfuncarg */ 3128 &sc->chan_dmat); /* dmat */ 3129 if (result != 0) { 3130 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3131 __func__, result); 3132 snd_mtxfree(sc->lock); 3133 free(sc, M_DEVBUF); 3134 return (ENXIO); 3135 } 3136 3137 3138 sc->hdabus = NULL; 3139 for (i = 0; i < HDAC_CODEC_MAX; i++) 3140 sc->codecs[i] = NULL; 3141 3142 pci_enable_busmaster(dev); 3143 3144 /* Allocate resources */ 3145 result = hdac_mem_alloc(sc); 3146 if (result != 0) 3147 goto hdac_attach_fail; 3148 result = hdac_irq_alloc(sc); 3149 if (result != 0) 3150 goto hdac_attach_fail; 3151 3152 /* Get Capabilities */ 3153 result = hdac_get_capabilities(sc); 3154 if (result != 0) 3155 goto hdac_attach_fail; 3156 3157 /* Allocate CORB and RIRB dma memory */ 3158 result = hdac_dma_alloc(sc, &sc->corb_dma, 3159 sc->corb_size * sizeof(uint32_t)); 3160 if (result != 0) 3161 goto hdac_attach_fail; 3162 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3163 sc->rirb_size * sizeof(struct hdac_rirb)); 3164 if (result != 0) 3165 goto hdac_attach_fail; 3166 3167 /* Quiesce everything */ 3168 hdac_reset(sc); 3169 3170 /* Disable PCI-Express QOS */ 3171 pci_write_config(sc->dev, 0x44, 3172 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3173 3174 /* Initialize the CORB and RIRB */ 3175 hdac_corb_init(sc); 3176 hdac_rirb_init(sc); 3177 3178 /* Defer remaining of initialization until interrupts are enabled */ 3179 sc->intrhook.ich_func = hdac_attach2; 3180 sc->intrhook.ich_arg = (void *)sc; 3181 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3182 sc->intrhook.ich_func = NULL; 3183 hdac_attach2((void *)sc); 3184 } 3185 3186 return (0); 3187 3188hdac_attach_fail: 3189 hdac_dma_free(&sc->rirb_dma); 3190 hdac_dma_free(&sc->corb_dma); 3191 hdac_irq_free(sc); 3192 hdac_mem_free(sc); 3193 snd_mtxfree(sc->lock); 3194 free(sc, M_DEVBUF); 3195 3196 return (ENXIO); 3197} 3198 3199static void 3200hdac_audio_parse(struct hdac_devinfo *devinfo) 3201{ 3202 struct hdac_softc *sc = devinfo->codec->sc; 3203 struct hdac_widget *w; 3204 uint32_t res; 3205 int i; 3206 nid_t cad, nid; 3207 3208 cad = devinfo->codec->cad; 3209 nid = devinfo->nid; 3210 3211 hdac_command(sc, 3212 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3213 3214 DELAY(100); 3215 3216 res = hdac_command(sc, 3217 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3218 3219 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3220 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3221 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3222 3223 HDA_BOOTVERBOSE( 3224 device_printf(sc->dev, " Vendor: 0x%08x\n", 3225 devinfo->vendor_id); 3226 device_printf(sc->dev, " Device: 0x%08x\n", 3227 devinfo->device_id); 3228 device_printf(sc->dev, " Revision: 0x%08x\n", 3229 devinfo->revision_id); 3230 device_printf(sc->dev, " Stepping: 0x%08x\n", 3231 devinfo->stepping_id); 3232 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3233 sc->pci_subvendor); 3234 device_printf(sc->dev, " Nodes: start=%d " 3235 "endnode=%d total=%d\n", 3236 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3237 ); 3238 3239 res = hdac_command(sc, 3240 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3241 cad); 3242 devinfo->function.audio.supp_stream_formats = res; 3243 3244 res = hdac_command(sc, 3245 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3246 cad); 3247 devinfo->function.audio.supp_pcm_size_rate = res; 3248 3249 res = hdac_command(sc, 3250 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3251 cad); 3252 devinfo->function.audio.outamp_cap = res; 3253 3254 res = hdac_command(sc, 3255 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3256 cad); 3257 devinfo->function.audio.inamp_cap = res; 3258 3259 if (devinfo->nodecnt > 0) { 3260 hdac_unlock(sc); 3261 devinfo->widget = (struct hdac_widget *)malloc( 3262 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3263 M_NOWAIT | M_ZERO); 3264 hdac_lock(sc); 3265 } else 3266 devinfo->widget = NULL; 3267 3268 if (devinfo->widget == NULL) { 3269 device_printf(sc->dev, "unable to allocate widgets!\n"); 3270 devinfo->endnode = devinfo->startnode; 3271 devinfo->nodecnt = 0; 3272 return; 3273 } 3274 3275 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3276 w = hdac_widget_get(devinfo, i); 3277 if (w == NULL) 3278 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3279 else { 3280 w->devinfo = devinfo; 3281 w->nid = i; 3282 w->enable = 1; 3283 w->selconn = -1; 3284 w->pflags = 0; 3285 w->ctlflags = 0; 3286 w->param.eapdbtl = HDAC_INVALID; 3287 hdac_widget_parse(w); 3288 } 3289 } 3290} 3291 3292static void 3293hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3294{ 3295 struct hdac_softc *sc = devinfo->codec->sc; 3296 struct hdac_audio_ctl *ctls; 3297 struct hdac_widget *w, *cw; 3298 int i, j, cnt, max, ocap, icap; 3299 int mute, offset, step, size; 3300 3301 /* XXX This is redundant */ 3302 max = 0; 3303 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3304 w = hdac_widget_get(devinfo, i); 3305 if (w == NULL || w->enable == 0) 3306 continue; 3307 if (w->param.outamp_cap != 0) 3308 max++; 3309 if (w->param.inamp_cap != 0) { 3310 switch (w->type) { 3311 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3312 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3313 for (j = 0; j < w->nconns; j++) { 3314 cw = hdac_widget_get(devinfo, 3315 w->conns[j]); 3316 if (cw == NULL || cw->enable == 0) 3317 continue; 3318 max++; 3319 } 3320 break; 3321 default: 3322 max++; 3323 break; 3324 } 3325 } 3326 } 3327 3328 devinfo->function.audio.ctlcnt = max; 3329 3330 if (max < 1) 3331 return; 3332 3333 hdac_unlock(sc); 3334 ctls = (struct hdac_audio_ctl *)malloc( 3335 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3336 hdac_lock(sc); 3337 3338 if (ctls == NULL) { 3339 /* Blekh! */ 3340 device_printf(sc->dev, "unable to allocate ctls!\n"); 3341 devinfo->function.audio.ctlcnt = 0; 3342 return; 3343 } 3344 3345 cnt = 0; 3346 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3347 if (cnt >= max) { 3348 device_printf(sc->dev, "%s: Ctl overflow!\n", 3349 __func__); 3350 break; 3351 } 3352 w = hdac_widget_get(devinfo, i); 3353 if (w == NULL || w->enable == 0) 3354 continue; 3355 ocap = w->param.outamp_cap; 3356 icap = w->param.inamp_cap; 3357 if (ocap != 0) { 3358 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3359 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3360 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3361 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3362 /*if (offset > step) { 3363 HDA_BOOTVERBOSE( 3364 device_printf(sc->dev, 3365 "HDA_DEBUG: BUGGY outamp: nid=%d " 3366 "[offset=%d > step=%d]\n", 3367 w->nid, offset, step); 3368 ); 3369 offset = step; 3370 }*/ 3371 ctls[cnt].enable = 1; 3372 ctls[cnt].widget = w; 3373 ctls[cnt].mute = mute; 3374 ctls[cnt].step = step; 3375 ctls[cnt].size = size; 3376 ctls[cnt].offset = offset; 3377 ctls[cnt].left = offset; 3378 ctls[cnt].right = offset; 3379 ctls[cnt++].dir = HDA_CTL_OUT; 3380 } 3381 3382 if (icap != 0) { 3383 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3384 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3385 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3386 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3387 /*if (offset > step) { 3388 HDA_BOOTVERBOSE( 3389 device_printf(sc->dev, 3390 "HDA_DEBUG: BUGGY inamp: nid=%d " 3391 "[offset=%d > step=%d]\n", 3392 w->nid, offset, step); 3393 ); 3394 offset = step; 3395 }*/ 3396 switch (w->type) { 3397 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3398 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3399 for (j = 0; j < w->nconns; j++) { 3400 if (cnt >= max) { 3401 device_printf(sc->dev, 3402 "%s: Ctl overflow!\n", 3403 __func__); 3404 break; 3405 } 3406 cw = hdac_widget_get(devinfo, 3407 w->conns[j]); 3408 if (cw == NULL || cw->enable == 0) 3409 continue; 3410 ctls[cnt].enable = 1; 3411 ctls[cnt].widget = w; 3412 ctls[cnt].childwidget = cw; 3413 ctls[cnt].index = j; 3414 ctls[cnt].mute = mute; 3415 ctls[cnt].step = step; 3416 ctls[cnt].size = size; 3417 ctls[cnt].offset = offset; 3418 ctls[cnt].left = offset; 3419 ctls[cnt].right = offset; 3420 ctls[cnt++].dir = HDA_CTL_IN; 3421 } 3422 break; 3423 default: 3424 if (cnt >= max) { 3425 device_printf(sc->dev, 3426 "%s: Ctl overflow!\n", 3427 __func__); 3428 break; 3429 } 3430 ctls[cnt].enable = 1; 3431 ctls[cnt].widget = w; 3432 ctls[cnt].mute = mute; 3433 ctls[cnt].step = step; 3434 ctls[cnt].size = size; 3435 ctls[cnt].offset = offset; 3436 ctls[cnt].left = offset; 3437 ctls[cnt].right = offset; 3438 ctls[cnt++].dir = HDA_CTL_IN; 3439 break; 3440 } 3441 } 3442 } 3443 3444 devinfo->function.audio.ctl = ctls; 3445} 3446 3447static const struct { 3448 uint32_t model; 3449 uint32_t id; 3450 uint32_t set, unset; 3451} hdac_quirks[] = { 3452 /* 3453 * XXX Force stereo quirk. Monoural recording / playback 3454 * on few codecs (especially ALC880) seems broken or 3455 * perhaps unsupported. 3456 */ 3457 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3458 HDA_QUIRK_FORCESTEREO, 0 }, 3459 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3460 HDA_QUIRK_GPIO1, 0 }, 3461 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3462 HDA_QUIRK_GPIO1, 0 }, 3463 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3464 HDA_QUIRK_GPIO2, 0 }, 3465 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3466 HDA_QUIRK_EAPDINV, 0 }, 3467 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3468 HDA_QUIRK_EAPDINV, 0 }, 3469 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3470 HDA_QUIRK_EAPDINV, 0 }, 3471 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3472 HDA_QUIRK_EAPDINV, 0 }, 3473 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3474 0, HDA_QUIRK_FORCESTEREO }, 3475 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3476 HDA_QUIRK_SOFTPCMVOL, 0 } 3477}; 3478#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3479 3480static void 3481hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3482{ 3483 struct hdac_widget *w; 3484 uint32_t id, subvendor; 3485 int i; 3486 3487 id = hdac_codec_id(devinfo); 3488 subvendor = devinfo->codec->sc->pci_subvendor; 3489 3490 /* 3491 * Quirks 3492 */ 3493 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3494 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3495 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3496 continue; 3497 if (hdac_quirks[i].set != 0) 3498 devinfo->function.audio.quirks |= 3499 hdac_quirks[i].set; 3500 if (hdac_quirks[i].unset != 0) 3501 devinfo->function.audio.quirks &= 3502 ~(hdac_quirks[i].unset); 3503 } 3504 3505 switch (id) { 3506 case HDA_CODEC_ALC260: 3507 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3508 w = hdac_widget_get(devinfo, i); 3509 if (w == NULL || w->enable == 0) 3510 continue; 3511 if (w->type != 3512 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3513 continue; 3514 if (w->nid != 5) 3515 w->enable = 0; 3516 } 3517 break; 3518 case HDA_CODEC_ALC880: 3519 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3520 w = hdac_widget_get(devinfo, i); 3521 if (w == NULL || w->enable == 0) 3522 continue; 3523 if (w->type == 3524 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3525 w->nid != 9 && w->nid != 29) { 3526 w->enable = 0; 3527 } else if (w->type != 3528 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3529 w->nid == 29) { 3530 w->type = 3531 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3532 w->param.widget_cap &= 3533 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3534 w->param.widget_cap |= 3535 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3536 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3537 strlcpy(w->name, "beep widget", sizeof(w->name)); 3538 } 3539 } 3540 break; 3541 case HDA_CODEC_AD1981HD: 3542 w = hdac_widget_get(devinfo, 11); 3543 if (w != NULL && w->enable != 0 && w->nconns > 3) 3544 w->selconn = 3; 3545 if (subvendor == IBM_M52_SUBVENDOR) { 3546 struct hdac_audio_ctl *ctl; 3547 3548 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3549 if (ctl != NULL) 3550 ctl->ossmask = SOUND_MASK_SPEAKER; 3551 } 3552 break; 3553 case HDA_CODEC_AD1986A: 3554 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3555 w = hdac_widget_get(devinfo, i); 3556 if (w == NULL || w->enable == 0) 3557 continue; 3558 if (w->type != 3559 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3560 continue; 3561 if (w->nid != 3) 3562 w->enable = 0; 3563 } 3564 break; 3565 case HDA_CODEC_STAC9221: 3566 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3567 w = hdac_widget_get(devinfo, i); 3568 if (w == NULL || w->enable == 0) 3569 continue; 3570 if (w->type != 3571 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3572 continue; 3573 if (w->nid != 2) 3574 w->enable = 0; 3575 } 3576 break; 3577 case HDA_CODEC_STAC9221D: 3578 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3579 w = hdac_widget_get(devinfo, i); 3580 if (w == NULL || w->enable == 0) 3581 continue; 3582 if (w->type == 3583 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3584 w->nid != 6) 3585 w->enable = 0; 3586 3587 } 3588 break; 3589 default: 3590 break; 3591 } 3592} 3593 3594static int 3595hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3596{ 3597 int *dev = &devinfo->function.audio.ossidx; 3598 3599 while (*dev < SOUND_MIXER_NRDEVICES) { 3600 switch (*dev) { 3601 case SOUND_MIXER_VOLUME: 3602 case SOUND_MIXER_BASS: 3603 case SOUND_MIXER_TREBLE: 3604 case SOUND_MIXER_PCM: 3605 case SOUND_MIXER_SPEAKER: 3606 case SOUND_MIXER_LINE: 3607 case SOUND_MIXER_MIC: 3608 case SOUND_MIXER_CD: 3609 case SOUND_MIXER_RECLEV: 3610 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3611 (*dev)++; 3612 break; 3613 default: 3614 return (*dev)++; 3615 break; 3616 } 3617 } 3618 3619 return (-1); 3620} 3621 3622static int 3623hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3624{ 3625 struct hdac_widget *w; 3626 int i, ret = 0; 3627 3628 if (depth > HDA_PARSE_MAXDEPTH) 3629 return (0); 3630 w = hdac_widget_get(devinfo, nid); 3631 if (w == NULL || w->enable == 0) 3632 return (0); 3633 switch (w->type) { 3634 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3635 w->pflags |= HDA_DAC_PATH; 3636 ret = 1; 3637 break; 3638 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3639 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3640 for (i = 0; i < w->nconns; i++) { 3641 if (hdac_widget_find_dac_path(devinfo, 3642 w->conns[i], depth + 1) != 0) { 3643 if (w->selconn == -1) 3644 w->selconn = i; 3645 ret = 1; 3646 w->pflags |= HDA_DAC_PATH; 3647 } 3648 } 3649 break; 3650 default: 3651 break; 3652 } 3653 return (ret); 3654} 3655 3656static int 3657hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3658{ 3659 struct hdac_widget *w; 3660 int i, conndev, ret = 0; 3661 3662 if (depth > HDA_PARSE_MAXDEPTH) 3663 return (0); 3664 w = hdac_widget_get(devinfo, nid); 3665 if (w == NULL || w->enable == 0) 3666 return (0); 3667 switch (w->type) { 3668 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3669 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3670 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3671 for (i = 0; i < w->nconns; i++) { 3672 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3673 depth + 1) != 0) { 3674 if (w->selconn == -1) 3675 w->selconn = i; 3676 w->pflags |= HDA_ADC_PATH; 3677 ret = 1; 3678 } 3679 } 3680 break; 3681 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3682 conndev = w->wclass.pin.config & 3683 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3684 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3685 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3686 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3687 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3688 w->pflags |= HDA_ADC_PATH; 3689 ret = 1; 3690 } 3691 break; 3692 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3693 if (w->pflags & HDA_DAC_PATH) { 3694 w->pflags |= HDA_ADC_PATH; 3695 ret = 1; 3696 } 3697 break;*/ 3698 default: 3699 break; 3700 } 3701 return (ret); 3702} 3703 3704static uint32_t 3705hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3706 nid_t nid, nid_t pnid, int index, int depth) 3707{ 3708 struct hdac_widget *w, *pw; 3709 struct hdac_audio_ctl *ctl; 3710 uint32_t fl = 0; 3711 int i, ossdev, conndev, strategy; 3712 3713 if (depth > HDA_PARSE_MAXDEPTH) 3714 return (0); 3715 3716 w = hdac_widget_get(devinfo, nid); 3717 if (w == NULL || w->enable == 0) 3718 return (0); 3719 3720 pw = hdac_widget_get(devinfo, pnid); 3721 strategy = devinfo->function.audio.parsing_strategy; 3722 3723 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3724 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3725 for (i = 0; i < w->nconns; i++) { 3726 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3727 w->nid, i, depth + 1); 3728 } 3729 w->ctlflags |= fl; 3730 return (fl); 3731 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3732 (w->pflags & HDA_DAC_PATH)) { 3733 i = 0; 3734 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3735 if (ctl->enable == 0 || ctl->widget == NULL) 3736 continue; 3737 /* XXX This should be compressed! */ 3738 if ((ctl->widget->nid == w->nid) || 3739 (ctl->widget->nid == pnid && ctl->index == index && 3740 (ctl->dir & HDA_CTL_IN)) || 3741 (ctl->widget->nid == pnid && pw != NULL && 3742 pw->type == 3743 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3744 (pw->nconns < 2 || pw->selconn == index || 3745 pw->selconn == -1) && 3746 (ctl->dir & HDA_CTL_OUT)) || 3747 (strategy == HDA_PARSE_DIRECT && 3748 ctl->widget->nid == w->nid)) { 3749 /*if (pw != NULL && pw->selconn == -1) 3750 pw->selconn = index; 3751 fl |= SOUND_MASK_VOLUME; 3752 fl |= SOUND_MASK_PCM; 3753 ctl->ossmask |= SOUND_MASK_VOLUME; 3754 ctl->ossmask |= SOUND_MASK_PCM; 3755 ctl->ossdev = SOUND_MIXER_PCM;*/ 3756 if (!(w->ctlflags & SOUND_MASK_PCM) || 3757 (pw != NULL && 3758 !(pw->ctlflags & SOUND_MASK_PCM))) { 3759 fl |= SOUND_MASK_VOLUME; 3760 fl |= SOUND_MASK_PCM; 3761 ctl->ossmask |= SOUND_MASK_VOLUME; 3762 ctl->ossmask |= SOUND_MASK_PCM; 3763 ctl->ossdev = SOUND_MIXER_PCM; 3764 w->ctlflags |= SOUND_MASK_VOLUME; 3765 w->ctlflags |= SOUND_MASK_PCM; 3766 if (pw != NULL) { 3767 if (pw->selconn == -1) 3768 pw->selconn = index; 3769 pw->ctlflags |= 3770 SOUND_MASK_VOLUME; 3771 pw->ctlflags |= 3772 SOUND_MASK_PCM; 3773 } 3774 } 3775 } 3776 } 3777 w->ctlflags |= fl; 3778 return (fl); 3779 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3780 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3781 (w->pflags & HDA_ADC_PATH)) { 3782 conndev = w->wclass.pin.config & 3783 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3784 i = 0; 3785 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3786 if (ctl->enable == 0 || ctl->widget == NULL) 3787 continue; 3788 /* XXX This should be compressed! */ 3789 if (((ctl->widget->nid == pnid && ctl->index == index && 3790 (ctl->dir & HDA_CTL_IN)) || 3791 (ctl->widget->nid == pnid && pw != NULL && 3792 pw->type == 3793 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3794 (pw->nconns < 2 || pw->selconn == index || 3795 pw->selconn == -1) && 3796 (ctl->dir & HDA_CTL_OUT)) || 3797 (strategy == HDA_PARSE_DIRECT && 3798 ctl->widget->nid == w->nid)) && 3799 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3800 if (pw != NULL && pw->selconn == -1) 3801 pw->selconn = index; 3802 ossdev = 0; 3803 switch (conndev) { 3804 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3805 ossdev = SOUND_MIXER_MIC; 3806 break; 3807 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3808 ossdev = SOUND_MIXER_LINE; 3809 break; 3810 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3811 ossdev = SOUND_MIXER_CD; 3812 break; 3813 default: 3814 ossdev = 3815 hdac_audio_ctl_ossmixer_getnextdev( 3816 devinfo); 3817 if (ossdev < 0) 3818 ossdev = 0; 3819 break; 3820 } 3821 if (strategy == HDA_PARSE_MIXER) { 3822 fl |= SOUND_MASK_VOLUME; 3823 ctl->ossmask |= SOUND_MASK_VOLUME; 3824 } 3825 fl |= 1 << ossdev; 3826 ctl->ossmask |= 1 << ossdev; 3827 ctl->ossdev = ossdev; 3828 } 3829 } 3830 w->ctlflags |= fl; 3831 return (fl); 3832 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3833 i = 0; 3834 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3835 if (ctl->enable == 0 || ctl->widget == NULL) 3836 continue; 3837 /* XXX This should be compressed! */ 3838 if (((ctl->widget->nid == pnid && ctl->index == index && 3839 (ctl->dir & HDA_CTL_IN)) || 3840 (ctl->widget->nid == pnid && pw != NULL && 3841 pw->type == 3842 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3843 (pw->nconns < 2 || pw->selconn == index || 3844 pw->selconn == -1) && 3845 (ctl->dir & HDA_CTL_OUT)) || 3846 (strategy == HDA_PARSE_DIRECT && 3847 ctl->widget->nid == w->nid)) && 3848 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3849 if (pw != NULL && pw->selconn == -1) 3850 pw->selconn = index; 3851 fl |= SOUND_MASK_VOLUME; 3852 fl |= SOUND_MASK_SPEAKER; 3853 ctl->ossmask |= SOUND_MASK_VOLUME; 3854 ctl->ossmask |= SOUND_MASK_SPEAKER; 3855 ctl->ossdev = SOUND_MIXER_SPEAKER; 3856 } 3857 } 3858 w->ctlflags |= fl; 3859 return (fl); 3860 } 3861 return (0); 3862} 3863 3864static uint32_t 3865hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3866{ 3867 struct hdac_widget *w, *cw; 3868 struct hdac_audio_ctl *ctl; 3869 uint32_t fl; 3870 int i; 3871 3872 if (depth > HDA_PARSE_MAXDEPTH) 3873 return (0); 3874 3875 w = hdac_widget_get(devinfo, nid); 3876 if (w == NULL || w->enable == 0) 3877 return (0); 3878 /*if (!(w->pflags & HDA_ADC_PATH)) 3879 return (0); 3880 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3881 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3882 return (0);*/ 3883 i = 0; 3884 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3885 if (ctl->enable == 0 || ctl->widget == NULL) 3886 continue; 3887 if (ctl->widget->nid == nid) { 3888 ctl->ossmask |= SOUND_MASK_RECLEV; 3889 w->ctlflags |= SOUND_MASK_RECLEV; 3890 return (SOUND_MASK_RECLEV); 3891 } 3892 } 3893 for (i = 0; i < w->nconns; i++) { 3894 cw = hdac_widget_get(devinfo, w->conns[i]); 3895 if (cw == NULL || cw->enable == 0) 3896 continue; 3897 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3898 continue; 3899 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3900 if (fl != 0) { 3901 cw->ctlflags |= fl; 3902 w->ctlflags |= fl; 3903 return (fl); 3904 } 3905 } 3906 return (0); 3907} 3908 3909static int 3910hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3911{ 3912 struct hdac_widget *w, *cw; 3913 int i, child = 0; 3914 3915 if (depth > HDA_PARSE_MAXDEPTH) 3916 return (0); 3917 3918 w = hdac_widget_get(devinfo, nid); 3919 if (w == NULL || w->enable == 0) 3920 return (0); 3921 /*if (!(w->pflags & HDA_ADC_PATH)) 3922 return (0); 3923 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3924 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3925 return (0);*/ 3926 /* XXX weak! */ 3927 for (i = 0; i < w->nconns; i++) { 3928 cw = hdac_widget_get(devinfo, w->conns[i]); 3929 if (cw == NULL) 3930 continue; 3931 if (++child > 1) { 3932 w->pflags |= HDA_ADC_RECSEL; 3933 return (1); 3934 } 3935 } 3936 for (i = 0; i < w->nconns; i++) { 3937 if (hdac_audio_ctl_recsel_build(devinfo, 3938 w->conns[i], depth + 1) != 0) 3939 return (1); 3940 } 3941 return (0); 3942} 3943 3944static int 3945hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3946{ 3947 struct hdac_widget *w, *cw; 3948 int i, j, conndev, found_dac = 0; 3949 int strategy; 3950 3951 strategy = devinfo->function.audio.parsing_strategy; 3952 3953 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3954 w = hdac_widget_get(devinfo, i); 3955 if (w == NULL || w->enable == 0) 3956 continue; 3957 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3958 continue; 3959 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3960 continue; 3961 conndev = w->wclass.pin.config & 3962 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3963 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3964 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3965 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3966 continue; 3967 for (j = 0; j < w->nconns; j++) { 3968 cw = hdac_widget_get(devinfo, w->conns[j]); 3969 if (cw == NULL || cw->enable == 0) 3970 continue; 3971 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3972 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3973 cw->type == 3974 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3975 continue; 3976 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3977 != 0) { 3978 if (w->selconn == -1) 3979 w->selconn = j; 3980 w->pflags |= HDA_DAC_PATH; 3981 found_dac++; 3982 } 3983 } 3984 } 3985 3986 return (found_dac); 3987} 3988 3989static void 3990hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3991{ 3992 struct hdac_widget *w; 3993 struct hdac_audio_ctl *ctl; 3994 int i, j, dacs, strategy; 3995 3996 /* Construct DAC path */ 3997 strategy = HDA_PARSE_MIXER; 3998 devinfo->function.audio.parsing_strategy = strategy; 3999 HDA_BOOTVERBOSE( 4000 device_printf(devinfo->codec->sc->dev, 4001 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4002 HDA_WIDGET_PARSER_REV); 4003 ); 4004 dacs = hdac_audio_build_tree_strategy(devinfo); 4005 if (dacs == 0) { 4006 HDA_BOOTVERBOSE( 4007 device_printf(devinfo->codec->sc->dev, 4008 "HDA_DEBUG: HWiP: 0 DAC path found! " 4009 "Retrying parser " 4010 "using HDA_PARSE_DIRECT strategy.\n"); 4011 ); 4012 strategy = HDA_PARSE_DIRECT; 4013 devinfo->function.audio.parsing_strategy = strategy; 4014 dacs = hdac_audio_build_tree_strategy(devinfo); 4015 } 4016 4017 HDA_BOOTVERBOSE( 4018 device_printf(devinfo->codec->sc->dev, 4019 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4020 "strategy.\n", 4021 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4022 ); 4023 4024 /* Construct ADC path */ 4025 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4026 w = hdac_widget_get(devinfo, i); 4027 if (w == NULL || w->enable == 0) 4028 continue; 4029 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4030 continue; 4031 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4032 } 4033 4034 /* Output mixers */ 4035 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4036 w = hdac_widget_get(devinfo, i); 4037 if (w == NULL || w->enable == 0) 4038 continue; 4039 if ((strategy == HDA_PARSE_MIXER && 4040 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4041 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4042 && (w->pflags & HDA_DAC_PATH)) || 4043 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4044 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4045 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4046 w->nid, devinfo->startnode - 1, 0, 0); 4047 } else if (w->type == 4048 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4049 j = 0; 4050 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4051 NULL) { 4052 if (ctl->enable == 0 || ctl->widget == NULL) 4053 continue; 4054 if (ctl->widget->nid != w->nid) 4055 continue; 4056 ctl->ossmask |= SOUND_MASK_VOLUME; 4057 ctl->ossmask |= SOUND_MASK_SPEAKER; 4058 ctl->ossdev = SOUND_MIXER_SPEAKER; 4059 w->ctlflags |= SOUND_MASK_VOLUME; 4060 w->ctlflags |= SOUND_MASK_SPEAKER; 4061 } 4062 } 4063 } 4064 4065 /* Input mixers (rec) */ 4066 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4067 w = hdac_widget_get(devinfo, i); 4068 if (w == NULL || w->enable == 0) 4069 continue; 4070 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4071 w->pflags & HDA_ADC_PATH)) 4072 continue; 4073 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4074 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4075 } 4076} 4077 4078#define HDA_COMMIT_CONN (1 << 0) 4079#define HDA_COMMIT_CTRL (1 << 1) 4080#define HDA_COMMIT_EAPD (1 << 2) 4081#define HDA_COMMIT_GPIO (1 << 3) 4082#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4083 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4084 4085static void 4086hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4087{ 4088 struct hdac_softc *sc = devinfo->codec->sc; 4089 struct hdac_widget *w; 4090 nid_t cad; 4091 int i; 4092 4093 if (!(cfl & HDA_COMMIT_ALL)) 4094 return; 4095 4096 cad = devinfo->codec->cad; 4097 4098 if (cfl & HDA_COMMIT_GPIO) { 4099 if (sc->pci_subvendor == APPLE_INTEL_MAC) { 4100 uint32_t gdata, gmask, gdir; 4101 4102 gdata = hdac_command(sc, 4103 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), 4104 cad); 4105 gmask = hdac_command(sc, 4106 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), 4107 cad); 4108 gdir = hdac_command(sc, 4109 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), 4110 cad); 4111 gdata |= 0x03; 4112 gmask |= 0x03; 4113 gdir |= 0x03; 4114 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4115 0x7e7, 0), cad); 4116 hdac_command(sc, 4117 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4118 gmask), cad); 4119 hdac_command(sc, 4120 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4121 gdir), cad); 4122 hdac_command(sc, 4123 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4124 gdata), cad); 4125 } else { 4126 for (i = 0; i < HDA_GPIO_MAX; i++) { 4127 if (!(devinfo->function.audio.quirks & 4128 (1 << i))) 4129 continue; 4130 hdac_command(sc, 4131 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, 4132 devinfo->nid, i), cad); 4133 hdac_command(sc, 4134 HDA_CMD_SET_GPIO_DIRECTION(cad, 4135 devinfo->nid, i), cad); 4136 hdac_command(sc, 4137 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4138 i), cad); 4139 } 4140 } 4141 } 4142 4143 for (i = 0; i < devinfo->nodecnt; i++) { 4144 w = &devinfo->widget[i]; 4145 if (w == NULL || w->enable == 0) 4146 continue; 4147 if (cfl & HDA_COMMIT_CONN) { 4148 if (w->selconn == -1) 4149 w->selconn = 0; 4150 if (w->nconns > 0) 4151 hdac_widget_connection_select(w, w->selconn); 4152 } 4153 if ((cfl & HDA_COMMIT_CTRL) && 4154 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4155 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4156 (HDA_DAC_PATH | HDA_ADC_PATH)) 4157 device_printf(sc->dev, "WARNING: node %d " 4158 "participate both for DAC/ADC!\n", w->nid); 4159 if (w->pflags & HDA_DAC_PATH) { 4160 w->wclass.pin.ctrl &= 4161 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4162 if ((w->wclass.pin.config & 4163 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4164 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4165 w->wclass.pin.ctrl &= 4166 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4167 } else if (w->pflags & HDA_ADC_PATH) { 4168 w->wclass.pin.ctrl &= 4169 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4170 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4171 } else 4172 w->wclass.pin.ctrl &= ~( 4173 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4174 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4175 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 4176 hdac_command(sc, 4177 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4178 w->wclass.pin.ctrl), cad); 4179 } 4180 if ((cfl & HDA_COMMIT_EAPD) && 4181 w->param.eapdbtl != HDAC_INVALID) { 4182 uint32_t val; 4183 4184 val = w->param.eapdbtl; 4185 if (devinfo->function.audio.quirks & 4186 HDA_QUIRK_EAPDINV) 4187 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4188 hdac_command(sc, 4189 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4190 val), cad); 4191 4192 } 4193 DELAY(1000); 4194 } 4195} 4196 4197static void 4198hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4199{ 4200 struct hdac_softc *sc = devinfo->codec->sc; 4201 struct hdac_audio_ctl *ctl; 4202 int i; 4203 4204 devinfo->function.audio.mvol = 100 | (100 << 8); 4205 i = 0; 4206 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4207 if (ctl->enable == 0 || ctl->widget == NULL) { 4208 HDA_BOOTVERBOSE( 4209 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4210 i, (ctl->widget != NULL) ? 4211 ctl->widget->nid : -1); 4212 if (ctl->childwidget != NULL) 4213 printf(" childnid=%d", 4214 ctl->childwidget->nid); 4215 if (ctl->widget == NULL) 4216 printf(" NULL WIDGET!"); 4217 printf(" DISABLED\n"); 4218 ); 4219 continue; 4220 } 4221 HDA_BOOTVERBOSE( 4222 if (ctl->ossmask == 0) { 4223 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4224 i, ctl->widget->nid); 4225 if (ctl->childwidget != NULL) 4226 printf(" childnid=%d", 4227 ctl->childwidget->nid); 4228 printf(" Bind to NONE\n"); 4229 } 4230 ); 4231 if (ctl->step > 0) { 4232 ctl->ossval = (ctl->left * 100) / ctl->step; 4233 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4234 } else 4235 ctl->ossval = 0; 4236 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4237 ctl->left, ctl->right); 4238 } 4239} 4240 4241static int 4242hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4243{ 4244 struct hdac_chan *ch; 4245 struct hdac_widget *w; 4246 uint32_t cap, fmtcap, pcmcap, path; 4247 int i, type, ret, max; 4248 4249 if (dir == PCMDIR_PLAY) { 4250 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4251 ch = &devinfo->codec->sc->play; 4252 path = HDA_DAC_PATH; 4253 } else { 4254 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4255 ch = &devinfo->codec->sc->rec; 4256 path = HDA_ADC_PATH; 4257 } 4258 4259 ch->caps = hdac_caps; 4260 ch->caps.fmtlist = ch->fmtlist; 4261 ch->bit16 = 1; 4262 ch->bit32 = 0; 4263 ch->pcmrates[0] = 48000; 4264 ch->pcmrates[1] = 0; 4265 4266 ret = 0; 4267 fmtcap = devinfo->function.audio.supp_stream_formats; 4268 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4269 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4270 4271 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4272 w = hdac_widget_get(devinfo, i); 4273 if (w == NULL || w->enable == 0 || w->type != type || 4274 !(w->pflags & path)) 4275 continue; 4276 cap = w->param.widget_cap; 4277 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4278 continue;*/ 4279 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4280 continue; 4281 cap = w->param.supp_stream_formats; 4282 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4283 } 4284 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4285 }*/ 4286 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4287 continue; 4288 if (ret == 0) { 4289 fmtcap = w->param.supp_stream_formats; 4290 pcmcap = w->param.supp_pcm_size_rate; 4291 } else { 4292 fmtcap &= w->param.supp_stream_formats; 4293 pcmcap &= w->param.supp_pcm_size_rate; 4294 } 4295 ch->io[ret++] = i; 4296 } 4297 ch->io[ret] = -1; 4298 4299 ch->supp_stream_formats = fmtcap; 4300 ch->supp_pcm_size_rate = pcmcap; 4301 4302 /* 4303 * 8bit = 0 4304 * 16bit = 1 4305 * 20bit = 2 4306 * 24bit = 3 4307 * 32bit = 4 4308 */ 4309 if (ret > 0) { 4310 cap = pcmcap; 4311 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4312 ch->bit16 = 1; 4313 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4314 ch->bit16 = 0; 4315 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4316 ch->bit32 = 4; 4317 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4318 ch->bit32 = 3; 4319 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4320 ch->bit32 = 2; 4321 i = 0; 4322 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4323 ch->fmtlist[i++] = AFMT_S16_LE; 4324 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4325 if (ch->bit32 > 0) { 4326 if (!(devinfo->function.audio.quirks & 4327 HDA_QUIRK_FORCESTEREO)) 4328 ch->fmtlist[i++] = AFMT_S32_LE; 4329 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4330 } 4331 ch->fmtlist[i] = 0; 4332 i = 0; 4333 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4334 ch->pcmrates[i++] = 8000; 4335 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4336 ch->pcmrates[i++] = 11025; 4337 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4338 ch->pcmrates[i++] = 16000; 4339 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4340 ch->pcmrates[i++] = 22050; 4341 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4342 ch->pcmrates[i++] = 32000; 4343 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4344 ch->pcmrates[i++] = 44100; 4345 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4346 ch->pcmrates[i++] = 48000; 4347 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4348 ch->pcmrates[i++] = 88200; 4349 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4350 ch->pcmrates[i++] = 96000; 4351 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4352 ch->pcmrates[i++] = 176400; 4353 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4354 ch->pcmrates[i++] = 192000; 4355 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4356 ch->pcmrates[i] = 0; 4357 if (i > 0) { 4358 ch->caps.minspeed = ch->pcmrates[0]; 4359 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4360 } 4361 } 4362 4363 return (ret); 4364} 4365 4366static void 4367hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4368{ 4369 struct hdac_audio_ctl *ctl; 4370 struct hdac_softc *sc = devinfo->codec->sc; 4371 int i; 4372 uint32_t fl = 0; 4373 4374 4375 if (flag == 0) { 4376 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4377 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4378 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4379 } 4380 4381 i = 0; 4382 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4383 if (ctl->enable == 0 || ctl->widget == NULL || 4384 ctl->widget->enable == 0) 4385 continue; 4386 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4387 (flag != 0 && (ctl->ossmask & flag))) { 4388 if (banner != NULL) { 4389 device_printf(sc->dev, "\n"); 4390 device_printf(sc->dev, "%s\n", banner); 4391 } 4392 goto hdac_ctl_dump_it_all; 4393 } 4394 } 4395 4396 return; 4397 4398hdac_ctl_dump_it_all: 4399 i = 0; 4400 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4401 if (ctl->enable == 0 || ctl->widget == NULL || 4402 ctl->widget->enable == 0) 4403 continue; 4404 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4405 (flag != 0 && (ctl->ossmask & flag)))) 4406 continue; 4407 if (flag == 0) { 4408 device_printf(sc->dev, "\n"); 4409 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4410 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4411 } 4412 device_printf(sc->dev, " |\n"); 4413 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4414 ctl->widget->nid, ctl->index); 4415 if (ctl->childwidget != NULL) 4416 printf("(nid: %2d) ", ctl->childwidget->nid); 4417 else 4418 printf(" "); 4419 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4420 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4421 ctl->ossmask); 4422 } 4423} 4424 4425static void 4426hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4427{ 4428 uint32_t cap; 4429 4430 cap = fcap; 4431 if (cap != 0) { 4432 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4433 device_printf(sc->dev, " Format:"); 4434 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4435 printf(" AC3"); 4436 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4437 printf(" FLOAT32"); 4438 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4439 printf(" PCM"); 4440 printf("\n"); 4441 } 4442 cap = pcmcap; 4443 if (cap != 0) { 4444 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4445 device_printf(sc->dev, " PCM size:"); 4446 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4447 printf(" 8"); 4448 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4449 printf(" 16"); 4450 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4451 printf(" 20"); 4452 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4453 printf(" 24"); 4454 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4455 printf(" 32"); 4456 printf("\n"); 4457 device_printf(sc->dev, " PCM rate:"); 4458 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4459 printf(" 8"); 4460 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4461 printf(" 11"); 4462 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4463 printf(" 16"); 4464 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4465 printf(" 22"); 4466 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4467 printf(" 32"); 4468 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4469 printf(" 44"); 4470 printf(" 48"); 4471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4472 printf(" 88"); 4473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4474 printf(" 96"); 4475 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4476 printf(" 176"); 4477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4478 printf(" 192"); 4479 printf("\n"); 4480 } 4481} 4482 4483static void 4484hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4485{ 4486 uint32_t pincap, wcap; 4487 4488 pincap = w->wclass.pin.cap; 4489 wcap = w->param.widget_cap; 4490 4491 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4492 device_printf(sc->dev, " "); 4493 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4494 printf(" ISC"); 4495 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4496 printf(" TRQD"); 4497 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4498 printf(" PDC"); 4499 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4500 printf(" HP"); 4501 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4502 printf(" OUT"); 4503 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4504 printf(" IN"); 4505 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4506 printf(" BAL"); 4507 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4508 printf(" EAPD"); 4509 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4510 printf(" : UNSOL"); 4511 printf("\n"); 4512 device_printf(sc->dev, " Pin config: 0x%08x\n", 4513 w->wclass.pin.config); 4514 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4515 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4516 printf(" HP"); 4517 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4518 printf(" IN"); 4519 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4520 printf(" OUT"); 4521 printf("\n"); 4522} 4523 4524static void 4525hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4526{ 4527 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4528 device_printf(sc->dev, " " 4529 "mute=%d step=%d size=%d offset=%d\n", 4530 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4531 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4532 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4533 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4534} 4535 4536static void 4537hdac_dump_nodes(struct hdac_devinfo *devinfo) 4538{ 4539 struct hdac_softc *sc = devinfo->codec->sc; 4540 struct hdac_widget *w, *cw; 4541 int i, j; 4542 4543 device_printf(sc->dev, "\n"); 4544 device_printf(sc->dev, "Default Parameter\n"); 4545 device_printf(sc->dev, "-----------------\n"); 4546 hdac_dump_audio_formats(sc, 4547 devinfo->function.audio.supp_stream_formats, 4548 devinfo->function.audio.supp_pcm_size_rate); 4549 device_printf(sc->dev, " IN amp: 0x%08x\n", 4550 devinfo->function.audio.inamp_cap); 4551 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4552 devinfo->function.audio.outamp_cap); 4553 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4554 w = hdac_widget_get(devinfo, i); 4555 if (w == NULL) { 4556 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4557 continue; 4558 } 4559 device_printf(sc->dev, "\n"); 4560 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4561 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4562 "DIGITAL" : "ANALOG", 4563 (w->enable == 0) ? " [DISABLED]" : ""); 4564 device_printf(sc->dev, " name: %s\n", w->name); 4565 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4566 w->param.widget_cap); 4567 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4568 w->pflags); 4569 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4570 w->ctlflags); 4571 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4572 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4573 hdac_dump_audio_formats(sc, 4574 w->param.supp_stream_formats, 4575 w->param.supp_pcm_size_rate); 4576 } else if (w->type == 4577 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4578 hdac_dump_pin(sc, w); 4579 if (w->param.eapdbtl != HDAC_INVALID) 4580 device_printf(sc->dev, " EAPD: 0x%08x\n", 4581 w->param.eapdbtl); 4582 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4583 w->param.outamp_cap != 0) 4584 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4585 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4586 w->param.inamp_cap != 0) 4587 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4588 device_printf(sc->dev, " connections: %d\n", w->nconns); 4589 for (j = 0; j < w->nconns; j++) { 4590 cw = hdac_widget_get(devinfo, w->conns[j]); 4591 device_printf(sc->dev, " |\n"); 4592 device_printf(sc->dev, " + <- nid=%d [%s]", 4593 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4594 if (cw == NULL) 4595 printf(" [UNKNOWN]"); 4596 else if (cw->enable == 0) 4597 printf(" [DISABLED]"); 4598 if (w->nconns > 1 && w->selconn == j && w->type != 4599 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4600 printf(" (selected)"); 4601 printf("\n"); 4602 } 4603 } 4604 4605} 4606 4607static int 4608hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4609{ 4610 struct hdac_widget *w, *cw; 4611 struct hdac_softc *sc = devinfo->codec->sc; 4612 int i; 4613 4614 if (depth > HDA_PARSE_MAXDEPTH) 4615 return (0); 4616 4617 w = hdac_widget_get(devinfo, nid); 4618 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4619 return (0); 4620 4621 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4622 device_printf(sc->dev, "\n"); 4623 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4624 device_printf(sc->dev, " ^\n"); 4625 device_printf(sc->dev, " |\n"); 4626 device_printf(sc->dev, " +-----<------+\n"); 4627 } else { 4628 device_printf(sc->dev, " ^\n"); 4629 device_printf(sc->dev, " |\n"); 4630 device_printf(sc->dev, " "); 4631 printf(" nid=%d [%s]\n", w->nid, w->name); 4632 } 4633 4634 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4635 return (1); 4636 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4637 for (i = 0; i < w->nconns; i++) { 4638 cw = hdac_widget_get(devinfo, w->conns[i]); 4639 if (cw == NULL || cw->enable == 0 || cw->type == 4640 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4641 continue; 4642 if (hdac_dump_dac_internal(devinfo, cw->nid, 4643 depth + 1) != 0) 4644 return (1); 4645 } 4646 } else if ((w->type == 4647 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4648 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4649 w->selconn > -1 && w->selconn < w->nconns) { 4650 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4651 depth + 1) != 0) 4652 return (1); 4653 } 4654 4655 return (0); 4656} 4657 4658static void 4659hdac_dump_dac(struct hdac_devinfo *devinfo) 4660{ 4661 struct hdac_widget *w; 4662 struct hdac_softc *sc = devinfo->codec->sc; 4663 int i, printed = 0; 4664 4665 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4666 w = hdac_widget_get(devinfo, i); 4667 if (w == NULL || w->enable == 0) 4668 continue; 4669 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4670 !(w->pflags & HDA_DAC_PATH)) 4671 continue; 4672 if (printed == 0) { 4673 printed = 1; 4674 device_printf(sc->dev, "\n"); 4675 device_printf(sc->dev, "Playback path:\n"); 4676 } 4677 hdac_dump_dac_internal(devinfo, w->nid, 0); 4678 } 4679} 4680 4681static void 4682hdac_dump_adc(struct hdac_devinfo *devinfo) 4683{ 4684 struct hdac_widget *w, *cw; 4685 struct hdac_softc *sc = devinfo->codec->sc; 4686 int i, j; 4687 int printed = 0; 4688 char ossdevs[256]; 4689 4690 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4691 w = hdac_widget_get(devinfo, i); 4692 if (w == NULL || w->enable == 0) 4693 continue; 4694 if (!(w->pflags & HDA_ADC_RECSEL)) 4695 continue; 4696 if (printed == 0) { 4697 printed = 1; 4698 device_printf(sc->dev, "\n"); 4699 device_printf(sc->dev, "Recording sources:\n"); 4700 } 4701 device_printf(sc->dev, "\n"); 4702 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4703 for (j = 0; j < w->nconns; j++) { 4704 cw = hdac_widget_get(devinfo, w->conns[j]); 4705 if (cw == NULL || cw->enable == 0) 4706 continue; 4707 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4708 ossdevs, sizeof(ossdevs)); 4709 device_printf(sc->dev, " |\n"); 4710 device_printf(sc->dev, " + <- nid=%d [%s]", 4711 cw->nid, cw->name); 4712 if (strlen(ossdevs) > 0) { 4713 printf(" [recsrc: %s]", ossdevs); 4714 } 4715 printf("\n"); 4716 } 4717 } 4718} 4719 4720static void 4721hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4722{ 4723 nid_t *nids; 4724 4725 if (pcnt > 0) { 4726 device_printf(sc->dev, "\n"); 4727 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4728 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4729 sc->play.supp_pcm_size_rate); 4730 device_printf(sc->dev, " DAC:"); 4731 for (nids = sc->play.io; *nids != -1; nids++) 4732 printf(" %d", *nids); 4733 printf("\n"); 4734 } 4735 4736 if (rcnt > 0) { 4737 device_printf(sc->dev, "\n"); 4738 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4739 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4740 sc->rec.supp_pcm_size_rate); 4741 device_printf(sc->dev, " ADC:"); 4742 for (nids = sc->rec.io; *nids != -1; nids++) 4743 printf(" %d", *nids); 4744 printf("\n"); 4745 } 4746} 4747 4748static void 4749hdac_release_resources(struct hdac_softc *sc) 4750{ 4751 struct hdac_devinfo *devinfo = NULL; 4752 device_t *devlist = NULL; 4753 int i, devcount; 4754 4755 if (sc == NULL) 4756 return; 4757 4758 hdac_lock(sc); 4759 if (sc->polling != 0) 4760 callout_stop(&sc->poll_hdac); 4761 hdac_reset(sc); 4762 hdac_unlock(sc); 4763 snd_mtxfree(sc->lock); 4764 4765 device_get_children(sc->dev, &devlist, &devcount); 4766 for (i = 0; devlist != NULL && i < devcount; i++) { 4767 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4768 if (devinfo == NULL) 4769 continue; 4770 if (devinfo->widget != NULL) 4771 free(devinfo->widget, M_HDAC); 4772 if (devinfo->node_type == 4773 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4774 devinfo->function.audio.ctl != NULL) 4775 free(devinfo->function.audio.ctl, M_HDAC); 4776 free(devinfo, M_HDAC); 4777 device_delete_child(sc->dev, devlist[i]); 4778 } 4779 if (devlist != NULL) 4780 free(devlist, M_TEMP); 4781 4782 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4783 if (sc->codecs[i] != NULL) 4784 free(sc->codecs[i], M_HDAC); 4785 sc->codecs[i] = NULL; 4786 } 4787 4788 hdac_dma_free(&sc->rirb_dma); 4789 hdac_dma_free(&sc->corb_dma); 4790 if (sc->play.blkcnt > 0) 4791 hdac_dma_free(&sc->play.bdl_dma); 4792 if (sc->rec.blkcnt > 0) 4793 hdac_dma_free(&sc->rec.bdl_dma); 4794 hdac_irq_free(sc); 4795 hdac_mem_free(sc); 4796 free(sc, M_DEVBUF); 4797 4798} 4799 4800/* This function surely going to make its way into upper level someday. */ 4801static void 4802hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4803{ 4804 const char *res = NULL; 4805 int i = 0, j, k, len, inv; 4806 4807 if (on != NULL) 4808 *on = 0; 4809 if (off != NULL) 4810 *off = 0; 4811 if (sc == NULL) 4812 return; 4813 if (resource_string_value(device_get_name(sc->dev), 4814 device_get_unit(sc->dev), "config", &res) != 0) 4815 return; 4816 if (!(res != NULL && strlen(res) > 0)) 4817 return; 4818 HDA_BOOTVERBOSE( 4819 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4820 ); 4821 for (;;) { 4822 while (res[i] != '\0' && 4823 (res[i] == ',' || isspace(res[i]) != 0)) 4824 i++; 4825 if (res[i] == '\0') { 4826 HDA_BOOTVERBOSE( 4827 printf("\n"); 4828 ); 4829 return; 4830 } 4831 j = i; 4832 while (res[j] != '\0' && 4833 !(res[j] == ',' || isspace(res[j]) != 0)) 4834 j++; 4835 len = j - i; 4836 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4837 inv = 2; 4838 else 4839 inv = 0; 4840 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4841 if (strncmp(res + i + inv, 4842 hdac_quirks_tab[k].key, len - inv) != 0) 4843 continue; 4844 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4845 break; 4846 HDA_BOOTVERBOSE( 4847 printf(" %s%s", (inv != 0) ? "no" : "", 4848 hdac_quirks_tab[k].key); 4849 ); 4850 if (inv == 0 && on != NULL) 4851 *on |= hdac_quirks_tab[k].value; 4852 else if (inv != 0 && off != NULL) 4853 *off |= hdac_quirks_tab[k].value; 4854 break; 4855 } 4856 i = j; 4857 } 4858} 4859 4860#ifdef SND_DYNSYSCTL 4861static int 4862sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4863{ 4864 struct hdac_softc *sc; 4865 struct hdac_devinfo *devinfo; 4866 device_t dev; 4867 uint32_t ctl; 4868 int err, val; 4869 4870 dev = oidp->oid_arg1; 4871 devinfo = pcm_getdevinfo(dev); 4872 if (devinfo == NULL || devinfo->codec == NULL || 4873 devinfo->codec->sc == NULL) 4874 return (EINVAL); 4875 sc = devinfo->codec->sc; 4876 hdac_lock(sc); 4877 val = sc->polling; 4878 hdac_unlock(sc); 4879 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4880 4881 if (err || req->newptr == NULL) 4882 return (err); 4883 if (val < 0 || val > 1) 4884 return (EINVAL); 4885 4886 hdac_lock(sc); 4887 if (val != sc->polling) { 4888 if (hda_chan_active(sc) != 0) 4889 err = EBUSY; 4890 else if (val == 0) { 4891 callout_stop(&sc->poll_hdac); 4892 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 4893 sc->rirb_size / 2); 4894 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4895 ctl |= HDAC_RIRBCTL_RINTCTL; 4896 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4897 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4898 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4899 sc->polling = 0; 4900 DELAY(1000); 4901 } else { 4902 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 4903 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 4904 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4905 ctl &= ~HDAC_RIRBCTL_RINTCTL; 4906 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4907 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 4908 sc); 4909 sc->polling = 1; 4910 DELAY(1000); 4911 } 4912 } 4913 hdac_unlock(sc); 4914 4915 return (err); 4916} 4917#endif 4918 4919static void 4920hdac_attach2(void *arg) 4921{ 4922 struct hdac_softc *sc; 4923 struct hdac_widget *w; 4924 struct hdac_audio_ctl *ctl; 4925 uint32_t quirks_on, quirks_off; 4926 int pcnt, rcnt; 4927 int i; 4928 char status[SND_STATUSLEN]; 4929 device_t *devlist = NULL; 4930 int devcount; 4931 struct hdac_devinfo *devinfo = NULL; 4932 4933 sc = (struct hdac_softc *)arg; 4934 4935 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4936 4937 HDA_BOOTVERBOSE( 4938 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4939 quirks_on, quirks_off); 4940 ); 4941 4942 hdac_lock(sc); 4943 4944 /* Remove ourselves from the config hooks */ 4945 if (sc->intrhook.ich_func != NULL) { 4946 config_intrhook_disestablish(&sc->intrhook); 4947 sc->intrhook.ich_func = NULL; 4948 } 4949 4950 /* Start the corb and rirb engines */ 4951 HDA_BOOTVERBOSE( 4952 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4953 ); 4954 hdac_corb_start(sc); 4955 HDA_BOOTVERBOSE( 4956 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4957 ); 4958 hdac_rirb_start(sc); 4959 4960 HDA_BOOTVERBOSE( 4961 device_printf(sc->dev, 4962 "HDA_DEBUG: Enabling controller interrupt...\n"); 4963 ); 4964 if (sc->polling == 0) 4965 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4966 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4967 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4968 HDAC_GCTL_UNSOL); 4969 4970 DELAY(1000); 4971 4972 HDA_BOOTVERBOSE( 4973 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4974 ); 4975 hdac_scan_codecs(sc); 4976 4977 device_get_children(sc->dev, &devlist, &devcount); 4978 for (i = 0; devlist != NULL && i < devcount; i++) { 4979 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4980 if (devinfo != NULL && devinfo->node_type == 4981 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4982 break; 4983 } else 4984 devinfo = NULL; 4985 } 4986 if (devlist != NULL) 4987 free(devlist, M_TEMP); 4988 4989 if (devinfo == NULL) { 4990 hdac_unlock(sc); 4991 device_printf(sc->dev, "Audio Function Group not found!\n"); 4992 hdac_release_resources(sc); 4993 return; 4994 } 4995 4996 HDA_BOOTVERBOSE( 4997 device_printf(sc->dev, 4998 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4999 devinfo->nid, devinfo->codec->cad); 5000 ); 5001 hdac_audio_parse(devinfo); 5002 HDA_BOOTVERBOSE( 5003 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5004 ); 5005 hdac_audio_ctl_parse(devinfo); 5006 HDA_BOOTVERBOSE( 5007 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5008 ); 5009 hdac_vendor_patch_parse(devinfo); 5010 if (quirks_on != 0) 5011 devinfo->function.audio.quirks |= quirks_on; 5012 if (quirks_off != 0) 5013 devinfo->function.audio.quirks &= ~quirks_off; 5014 5015 /* XXX Disable all DIGITAL path. */ 5016 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5017 w = hdac_widget_get(devinfo, i); 5018 if (w == NULL) 5019 continue; 5020 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5021 w->enable = 0; 5022 continue; 5023 } 5024 /* XXX Disable useless pin ? */ 5025 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5026 (w->wclass.pin.config & 5027 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5028 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5029 w->enable = 0; 5030 } 5031 i = 0; 5032 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5033 if (ctl->widget == NULL) 5034 continue; 5035 w = ctl->widget; 5036 if (w->enable == 0) 5037 ctl->enable = 0; 5038 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5039 ctl->enable = 0; 5040 w = ctl->childwidget; 5041 if (w == NULL) 5042 continue; 5043 if (w->enable == 0 || 5044 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5045 ctl->enable = 0; 5046 } 5047 5048 HDA_BOOTVERBOSE( 5049 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5050 ); 5051 hdac_audio_build_tree(devinfo); 5052 5053 HDA_BOOTVERBOSE( 5054 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5055 ); 5056 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5057 HDA_BOOTVERBOSE( 5058 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5059 ); 5060 hdac_audio_ctl_commit(devinfo); 5061 5062 HDA_BOOTVERBOSE( 5063 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5064 ); 5065 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5066 HDA_BOOTVERBOSE( 5067 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5068 ); 5069 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5070 5071 hdac_unlock(sc); 5072 HDA_BOOTVERBOSE( 5073 device_printf(sc->dev, 5074 "HDA_DEBUG: OSS mixer initialization...\n"); 5075 ); 5076 5077 /* 5078 * There is no point of return after this. If the driver failed, 5079 * so be it. Let the detach procedure do all the cleanup. 5080 */ 5081 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5082 device_printf(sc->dev, "Can't register mixer\n"); 5083 5084 if (pcnt > 0) 5085 pcnt = 1; 5086 if (rcnt > 0) 5087 rcnt = 1; 5088 5089 HDA_BOOTVERBOSE( 5090 device_printf(sc->dev, 5091 "HDA_DEBUG: Registering PCM channels...\n"); 5092 ); 5093 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5094 device_printf(sc->dev, "Can't register PCM\n"); 5095 5096 sc->registered++; 5097 5098 for (i = 0; i < pcnt; i++) 5099 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5100 for (i = 0; i < rcnt; i++) 5101 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5102 5103#ifdef SND_DYNSYSCTL 5104 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5105 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5106 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5107 sysctl_hdac_polling, "I", "Enable polling mode"); 5108#endif 5109 5110 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5111 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5112 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5113 pcm_setstatus(sc->dev, status); 5114 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5115 HDA_BOOTVERBOSE( 5116 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5117 hdac_codec_id(devinfo)); 5118 ); 5119 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5120 HDA_DRV_TEST_REV); 5121 5122 HDA_BOOTVERBOSE( 5123 if (devinfo->function.audio.quirks != 0) { 5124 device_printf(sc->dev, "\n"); 5125 device_printf(sc->dev, "HDA config/quirks:"); 5126 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5127 if (devinfo->function.audio.quirks & 5128 hdac_quirks_tab[i].value) 5129 printf(" %s", hdac_quirks_tab[i].key); 5130 } 5131 printf("\n"); 5132 } 5133 device_printf(sc->dev, "\n"); 5134 device_printf(sc->dev, "+-------------------+\n"); 5135 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5136 device_printf(sc->dev, "+-------------------+\n"); 5137 hdac_dump_nodes(devinfo); 5138 device_printf(sc->dev, "\n"); 5139 device_printf(sc->dev, "+------------------------+\n"); 5140 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5141 device_printf(sc->dev, "+------------------------+\n"); 5142 device_printf(sc->dev, "\n"); 5143 i = 0; 5144 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5145 device_printf(sc->dev, "%3d: nid=%d", i, 5146 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5147 if (ctl->childwidget != NULL) 5148 printf(" cnid=%d", ctl->childwidget->nid); 5149 printf(" dir=0x%x index=%d " 5150 "ossmask=0x%08x ossdev=%d%s\n", 5151 ctl->dir, ctl->index, 5152 ctl->ossmask, ctl->ossdev, 5153 (ctl->enable == 0) ? " [DISABLED]" : ""); 5154 } 5155 device_printf(sc->dev, "\n"); 5156 device_printf(sc->dev, "+-----------------------------------+\n"); 5157 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5158 device_printf(sc->dev, "+-----------------------------------+\n"); 5159 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5160 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5161 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5162 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5163 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5164 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5165 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5166 hdac_dump_ctls(devinfo, NULL, 0); 5167 hdac_dump_dac(devinfo); 5168 hdac_dump_adc(devinfo); 5169 device_printf(sc->dev, "\n"); 5170 device_printf(sc->dev, "+--------------------------------------+\n"); 5171 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5172 device_printf(sc->dev, "+--------------------------------------+\n"); 5173 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5174 ); 5175 5176 if (sc->polling != 0) { 5177 hdac_lock(sc); 5178 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5179 hdac_unlock(sc); 5180 } 5181} 5182 5183/**************************************************************************** 5184 * int hdac_detach(device_t) 5185 * 5186 * Detach and free up resources utilized by the hdac device. 5187 ****************************************************************************/ 5188static int 5189hdac_detach(device_t dev) 5190{ 5191 struct hdac_softc *sc = NULL; 5192 struct hdac_devinfo *devinfo = NULL; 5193 int err; 5194 5195 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5196 if (devinfo != NULL && devinfo->codec != NULL) 5197 sc = devinfo->codec->sc; 5198 if (sc == NULL) 5199 return (0); 5200 5201 if (sc->registered > 0) { 5202 err = pcm_unregister(dev); 5203 if (err != 0) 5204 return (err); 5205 } 5206 5207 hdac_release_resources(sc); 5208 5209 return (0); 5210} 5211 5212static device_method_t hdac_methods[] = { 5213 /* device interface */ 5214 DEVMETHOD(device_probe, hdac_probe), 5215 DEVMETHOD(device_attach, hdac_attach), 5216 DEVMETHOD(device_detach, hdac_detach), 5217 { 0, 0 } 5218}; 5219 5220static driver_t hdac_driver = { 5221 "pcm", 5222 hdac_methods, 5223 PCM_SOFTC_SIZE, 5224}; 5225 5226DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5227MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5228MODULE_VERSION(snd_hda, 1); 5229