hdac.c revision 164750
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061111_0034" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 164750 2006-11-29 15:15:30Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 193#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 194 195/* IBM / Lenovo */ 196#define IBM_VENDORID 0x1014 197#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 198#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 199 200/* Lenovo */ 201#define LENOVO_VENDORID 0x17aa 202#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 203#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 204 205/* Samsung */ 206#define SAMSUNG_VENDORID 0x144d 207#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 208#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 209 210/* Medion ? */ 211#define MEDION_VENDORID 0x161f 212#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 213#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 214 215/* Misc constants.. */ 216#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 217#define HDA_AMP_MUTE_NONE (0) 218#define HDA_AMP_MUTE_LEFT (1 << 0) 219#define HDA_AMP_MUTE_RIGHT (1 << 1) 220#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 221 222#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 223#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 224 225#define HDA_DAC_PATH (1 << 0) 226#define HDA_ADC_PATH (1 << 1) 227#define HDA_ADC_RECSEL (1 << 2) 228 229#define HDA_CTL_OUT (1 << 0) 230#define HDA_CTL_IN (1 << 1) 231#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 232 233#define HDA_GPIO_MAX 15 234/* 0 - 14 = GPIO */ 235#define HDA_QUIRK_GPIO0 (1 << 0) 236#define HDA_QUIRK_GPIO1 (1 << 1) 237#define HDA_QUIRK_GPIO2 (1 << 2) 238#define HDA_QUIRK_SOFTPCMVOL (1 << 15) 239#define HDA_QUIRK_FIXEDRATE (1 << 16) 240#define HDA_QUIRK_FORCESTEREO (1 << 17) 241#define HDA_QUIRK_EAPDINV (1 << 18) 242 243static const struct { 244 char *key; 245 uint32_t value; 246} hdac_quirks_tab[] = { 247 { "gpio0", HDA_QUIRK_GPIO0 }, 248 { "gpio1", HDA_QUIRK_GPIO1 }, 249 { "gpio2", HDA_QUIRK_GPIO2 }, 250 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 251 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 252 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 253 { "eapdinv", HDA_QUIRK_EAPDINV }, 254}; 255#define HDAC_QUIRKS_TAB_LEN \ 256 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 257 258#define HDA_BDL_MIN 2 259#define HDA_BDL_MAX 256 260#define HDA_BDL_DEFAULT HDA_BDL_MIN 261 262#define HDA_BUFSZ_MIN 4096 263#define HDA_BUFSZ_MAX 65536 264#define HDA_BUFSZ_DEFAULT 16384 265 266#define HDA_PARSE_MAXDEPTH 10 267 268#define HDAC_UNSOLTAG_EVENT_HP 0x00 269 270static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 271 272enum { 273 HDA_PARSE_MIXER, 274 HDA_PARSE_DIRECT 275}; 276 277/* Default */ 278static uint32_t hdac_fmt[] = { 279 AFMT_STEREO | AFMT_S16_LE, 280 0 281}; 282 283static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 284 285static const struct { 286 uint32_t model; 287 char *desc; 288} hdac_devices[] = { 289 { HDA_INTEL_82801F, "Intel 82801F" }, 290 { HDA_INTEL_82801G, "Intel 82801G" }, 291 { HDA_INTEL_82801H, "Intel 82801H" }, 292 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 293 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 294 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 295 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 296 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 297 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 298 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 299 { HDA_ATI_SB450, "ATI SB450" }, 300 { HDA_ATI_SB600, "ATI SB600" }, 301 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 302 { HDA_SIS_966, "SiS 966" }, 303 /* Unknown */ 304 { HDA_INTEL_ALL, "Intel (Unknown)" }, 305 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 306 { HDA_ATI_ALL, "ATI (Unknown)" }, 307 { HDA_VIA_ALL, "VIA (Unknown)" }, 308 { HDA_SIS_ALL, "SiS (Unknown)" }, 309}; 310#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 311 312static const struct { 313 uint32_t rate; 314 int valid; 315 uint16_t base; 316 uint16_t mul; 317 uint16_t div; 318} hda_rate_tab[] = { 319 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 320 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 321 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 322 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 323 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 324 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 325 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 326 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 327 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 328 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 329 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 330 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 331 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 332 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 333 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 334 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 335 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 336 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 337 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 338 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 339 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 340 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 341 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 342 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 343 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 344 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 345 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 346 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 347 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 348 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 349 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 350 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 351 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 352 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 353 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 354}; 355#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 356 357/* All codecs you can eat... */ 358#define HDA_CODEC_CONSTRUCT(vendor, id) \ 359 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 360 361/* Realtek */ 362#define REALTEK_VENDORID 0x10ec 363#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 364#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 365#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 366#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 367#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 368#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 369 370/* Analog Device */ 371#define ANALOGDEVICE_VENDORID 0x11d4 372#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 373#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 374#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 375#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 376 377/* CMedia */ 378#define CMEDIA_VENDORID 0x434d 379#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 380#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 381 382/* Sigmatel */ 383#define SIGMATEL_VENDORID 0x8384 384#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 385#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 386#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 387#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 388#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 389 390/* 391 * Conexant 392 * 393 * Ok, the truth is, I don't have any idea at all whether 394 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 395 * place that tell me it is "Venice" is from its Windows driver INF. 396 * 397 * Venice - CX????? 398 * Waikiki - CX20551-22 399 */ 400#define CONEXANT_VENDORID 0x14f1 401#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 402#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 403#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 404 405 406/* Codecs */ 407static const struct { 408 uint32_t id; 409 char *name; 410} hdac_codecs[] = { 411 { HDA_CODEC_ALC260, "Realtek ALC260" }, 412 { HDA_CODEC_ALC861, "Realtek ALC861" }, 413 { HDA_CODEC_ALC880, "Realtek ALC880" }, 414 { HDA_CODEC_ALC882, "Realtek ALC882" }, 415 { HDA_CODEC_ALC883, "Realtek ALC883" }, 416 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 417 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 418 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 419 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 420 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 421 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 422 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 423 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 424 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 425 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 426 /* Unknown codec */ 427 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 428 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 429 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 430 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 431 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 432}; 433#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 434 435enum { 436 HDAC_HP_SWITCH_CTL, 437 HDAC_HP_SWITCH_CTRL 438}; 439 440static const struct { 441 uint32_t model; 442 uint32_t id; 443 int type; 444 nid_t hpnid; 445 nid_t spkrnid[8]; 446 nid_t eapdnid; 447} hdac_hp_switch[] = { 448 /* Specific OEM models */ 449 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 450 17, { 16, -1 }, 16 }, 451 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 452 6, { 5, -1 }, 5 }, 453 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 454 6, { 5, -1 }, 5 }, 455 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 456 13, { 14, -1 }, -1 }, 457 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 458 13, { 14, -1 }, -1 }, 459 /* 460 * All models that at least come from the same vendor with 461 * simmilar codec. 462 */ 463 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 464 17, { 16, -1 }, 16 }, 465 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 466 6, { 5, -1 }, 5 }, 467 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 468 13, { 14, -1 }, -1 }, 469}; 470#define HDAC_HP_SWITCH_LEN \ 471 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 472 473static const struct { 474 uint32_t model; 475 uint32_t id; 476 nid_t eapdnid; 477 int hp_switch; 478} hdac_eapd_switch[] = { 479 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 480 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 481 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 482}; 483#define HDAC_EAPD_SWITCH_LEN \ 484 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 485 486/**************************************************************************** 487 * Function prototypes 488 ****************************************************************************/ 489static void hdac_intr_handler(void *); 490static int hdac_reset(struct hdac_softc *); 491static int hdac_get_capabilities(struct hdac_softc *); 492static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 493static int hdac_dma_alloc(struct hdac_softc *, 494 struct hdac_dma *, bus_size_t); 495static void hdac_dma_free(struct hdac_dma *); 496static int hdac_mem_alloc(struct hdac_softc *); 497static void hdac_mem_free(struct hdac_softc *); 498static int hdac_irq_alloc(struct hdac_softc *); 499static void hdac_irq_free(struct hdac_softc *); 500static void hdac_corb_init(struct hdac_softc *); 501static void hdac_rirb_init(struct hdac_softc *); 502static void hdac_corb_start(struct hdac_softc *); 503static void hdac_rirb_start(struct hdac_softc *); 504static void hdac_scan_codecs(struct hdac_softc *); 505static int hdac_probe_codec(struct hdac_codec *); 506static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 507static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 508 509static void hdac_attach2(void *); 510 511static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 512 uint32_t, int); 513static void hdac_command_send_internal(struct hdac_softc *, 514 struct hdac_command_list *, int); 515 516static int hdac_probe(device_t); 517static int hdac_attach(device_t); 518static int hdac_detach(device_t); 519static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 520static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 521 uint32_t, int, int); 522static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 523 nid_t, int, int); 524static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 525 nid_t, nid_t, int, int, int, int, int, int); 526static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 527static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 528 529static int hdac_rirb_flush(struct hdac_softc *sc); 530static int hdac_unsolq_flush(struct hdac_softc *sc); 531 532#define hdac_command(a1, a2, a3) \ 533 hdac_command_sendone_internal(a1, a2, a3) 534 535#define hdac_codec_id(d) \ 536 ((uint32_t)((d == NULL) ? 0x00000000 : \ 537 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 538 ((uint32_t)(d)->device_id & 0x0000ffff)))) 539 540static char * 541hdac_codec_name(struct hdac_devinfo *devinfo) 542{ 543 uint32_t id; 544 int i; 545 546 id = hdac_codec_id(devinfo); 547 548 for (i = 0; i < HDAC_CODECS_LEN; i++) { 549 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 550 return (hdac_codecs[i].name); 551 } 552 553 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 554} 555 556static char * 557hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 558{ 559 static char *ossname[] = SOUND_DEVICE_NAMES; 560 static char *unknown = "???"; 561 int i; 562 563 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 564 if (devmask & (1 << i)) 565 return (ossname[i]); 566 } 567 return (unknown); 568} 569 570static void 571hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 572{ 573 static char *ossname[] = SOUND_DEVICE_NAMES; 574 int i, first = 1; 575 576 bzero(buf, len); 577 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 578 if (mask & (1 << i)) { 579 if (first == 0) 580 strlcat(buf, ", ", len); 581 strlcat(buf, ossname[i], len); 582 first = 0; 583 } 584 } 585} 586 587static struct hdac_audio_ctl * 588hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 589{ 590 if (devinfo == NULL || 591 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 592 index == NULL || devinfo->function.audio.ctl == NULL || 593 devinfo->function.audio.ctlcnt < 1 || 594 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 595 return (NULL); 596 return (&devinfo->function.audio.ctl[(*index)++]); 597} 598 599static struct hdac_audio_ctl * 600hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 601 int index, int cnt) 602{ 603 struct hdac_audio_ctl *ctl, *retctl = NULL; 604 int i, at, atindex, found = 0; 605 606 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 607 return (NULL); 608 609 at = cnt; 610 if (at == 0) 611 at = 1; 612 else if (at < 0) 613 at = -1; 614 atindex = index; 615 if (atindex < 0) 616 atindex = -1; 617 618 i = 0; 619 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 620 if (ctl->enable == 0 || ctl->widget == NULL) 621 continue; 622 if (!(ctl->widget->nid == nid && (atindex == -1 || 623 ctl->index == atindex))) 624 continue; 625 found++; 626 if (found == cnt) 627 return (ctl); 628 retctl = ctl; 629 } 630 631 return ((at == -1) ? retctl : NULL); 632} 633 634static void 635hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 636{ 637 struct hdac_softc *sc; 638 struct hdac_widget *w; 639 struct hdac_audio_ctl *ctl; 640 uint32_t id, res; 641 int i = 0, j, forcemute; 642 nid_t cad; 643 644 if (devinfo == NULL || devinfo->codec == NULL || 645 devinfo->codec->sc == NULL) 646 return; 647 648 sc = devinfo->codec->sc; 649 cad = devinfo->codec->cad; 650 id = hdac_codec_id(devinfo); 651 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 652 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 653 sc->pci_subvendor) && 654 hdac_hp_switch[i].id == id) 655 break; 656 } 657 658 if (i >= HDAC_HP_SWITCH_LEN) 659 return; 660 661 forcemute = 0; 662 if (hdac_hp_switch[i].eapdnid != -1) { 663 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 664 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 665 forcemute = (w->param.eapdbtl & 666 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 667 } 668 669 res = hdac_command(sc, 670 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 671 HDA_BOOTVERBOSE( 672 device_printf(sc->dev, 673 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 674 hdac_hp_switch[i].hpnid, res); 675 ); 676 res >>= 31; 677 678 switch (hdac_hp_switch[i].type) { 679 case HDAC_HP_SWITCH_CTL: 680 ctl = hdac_audio_ctl_amp_get(devinfo, 681 hdac_hp_switch[i].hpnid, 0, 1); 682 if (ctl != NULL) { 683 ctl->muted = (res != 0 && forcemute == 0) ? 684 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 685 hdac_audio_ctl_amp_set(ctl, 686 HDA_AMP_MUTE_DEFAULT, ctl->left, 687 ctl->right); 688 } 689 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 690 ctl = hdac_audio_ctl_amp_get(devinfo, 691 hdac_hp_switch[i].spkrnid[j], 0, 1); 692 if (ctl != NULL) { 693 ctl->muted = (res != 0 || forcemute == 1) ? 694 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 695 hdac_audio_ctl_amp_set(ctl, 696 HDA_AMP_MUTE_DEFAULT, ctl->left, 697 ctl->right); 698 } 699 } 700 break; 701 case HDAC_HP_SWITCH_CTRL: 702 if (res != 0) { 703 /* HP in */ 704 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 705 if (w != NULL && w->type == 706 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 707 if (forcemute == 0) 708 w->wclass.pin.ctrl |= 709 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 710 else 711 w->wclass.pin.ctrl &= 712 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 713 hdac_command(sc, 714 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 715 w->wclass.pin.ctrl), cad); 716 } 717 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 718 w = hdac_widget_get(devinfo, 719 hdac_hp_switch[i].spkrnid[j]); 720 if (w != NULL && w->type == 721 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 722 w->wclass.pin.ctrl &= 723 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 724 hdac_command(sc, 725 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 726 w->nid, 727 w->wclass.pin.ctrl), cad); 728 } 729 } 730 } else { 731 /* HP out */ 732 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 733 if (w != NULL && w->type == 734 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 735 w->wclass.pin.ctrl &= 736 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 737 hdac_command(sc, 738 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 739 w->wclass.pin.ctrl), cad); 740 } 741 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 742 w = hdac_widget_get(devinfo, 743 hdac_hp_switch[i].spkrnid[j]); 744 if (w != NULL && w->type == 745 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 746 if (forcemute == 0) 747 w->wclass.pin.ctrl |= 748 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 749 else 750 w->wclass.pin.ctrl &= 751 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 752 hdac_command(sc, 753 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 754 w->nid, 755 w->wclass.pin.ctrl), cad); 756 } 757 } 758 } 759 break; 760 default: 761 break; 762 } 763} 764 765static void 766hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 767{ 768 struct hdac_softc *sc; 769 struct hdac_devinfo *devinfo = NULL; 770 device_t *devlist = NULL; 771 int devcount, i; 772 773 if (codec == NULL || codec->sc == NULL) 774 return; 775 776 sc = codec->sc; 777 778 HDA_BOOTVERBOSE( 779 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 780 ); 781 782 device_get_children(sc->dev, &devlist, &devcount); 783 for (i = 0; devlist != NULL && i < devcount; i++) { 784 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 785 if (devinfo != NULL && devinfo->node_type == 786 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 787 devinfo->codec != NULL && 788 devinfo->codec->cad == codec->cad) { 789 break; 790 } else 791 devinfo = NULL; 792 } 793 if (devlist != NULL) 794 free(devlist, M_TEMP); 795 796 if (devinfo == NULL) 797 return; 798 799 switch (tag) { 800 case HDAC_UNSOLTAG_EVENT_HP: 801 hdac_hp_switch_handler(devinfo); 802 break; 803 default: 804 break; 805 } 806} 807 808static int 809hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 810{ 811 /* XXX to be removed */ 812#ifdef HDAC_INTR_EXTRA 813 uint32_t res; 814#endif 815 816 if (ch->blkcnt == 0) 817 return (0); 818 819 /* XXX to be removed */ 820#ifdef HDAC_INTR_EXTRA 821 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 822#endif 823 824 /* XXX to be removed */ 825#ifdef HDAC_INTR_EXTRA 826 HDA_BOOTVERBOSE( 827 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 828 device_printf(sc->dev, 829 "PCMDIR_%s intr triggered beyond stream boundary:" 830 "%08x\n", 831 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 832 ); 833#endif 834 835 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 836 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 837 838 /* XXX to be removed */ 839#ifdef HDAC_INTR_EXTRA 840 if (res & HDAC_SDSTS_BCIS) { 841#endif 842 return (1); 843 /* XXX to be removed */ 844#ifdef HDAC_INTR_EXTRA 845 } 846#endif 847 848 return (0); 849} 850 851/**************************************************************************** 852 * void hdac_intr_handler(void *) 853 * 854 * Interrupt handler. Processes interrupts received from the hdac. 855 ****************************************************************************/ 856static void 857hdac_intr_handler(void *context) 858{ 859 struct hdac_softc *sc; 860 uint32_t intsts; 861 uint8_t rirbsts; 862 struct hdac_rirb *rirb_base; 863 uint32_t trigger = 0; 864 865 sc = (struct hdac_softc *)context; 866 867 hdac_lock(sc); 868 if (sc->polling != 0) { 869 hdac_unlock(sc); 870 return; 871 } 872 /* Do we have anything to do? */ 873 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 874 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 875 hdac_unlock(sc); 876 return; 877 } 878 879 /* Was this a controller interrupt? */ 880 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 881 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 882 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 883 /* Get as many responses that we can */ 884 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 885 HDAC_WRITE_1(&sc->mem, 886 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 887 hdac_rirb_flush(sc); 888 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 889 } 890 /* XXX to be removed */ 891 /* Clear interrupt and exit */ 892#ifdef HDAC_INTR_EXTRA 893 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 894#endif 895 } 896 897 hdac_unsolq_flush(sc); 898 899 if (intsts & HDAC_INTSTS_SIS_MASK) { 900 if ((intsts & (1 << sc->num_iss)) && 901 hdac_stream_intr(sc, &sc->play) != 0) 902 trigger |= 1; 903 if ((intsts & (1 << 0)) && 904 hdac_stream_intr(sc, &sc->rec) != 0) 905 trigger |= 2; 906 /* XXX to be removed */ 907#ifdef HDAC_INTR_EXTRA 908 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 909 HDAC_INTSTS_SIS_MASK); 910#endif 911 } 912 913 hdac_unlock(sc); 914 915 if (trigger & 1) 916 chn_intr(sc->play.c); 917 if (trigger & 2) 918 chn_intr(sc->rec.c); 919} 920 921/**************************************************************************** 922 * int hdac_reset(hdac_softc *) 923 * 924 * Reset the hdac to a quiescent and known state. 925 ****************************************************************************/ 926static int 927hdac_reset(struct hdac_softc *sc) 928{ 929 uint32_t gctl; 930 int count, i; 931 932 /* 933 * Stop all Streams DMA engine 934 */ 935 for (i = 0; i < sc->num_iss; i++) 936 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 937 for (i = 0; i < sc->num_oss; i++) 938 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 939 for (i = 0; i < sc->num_bss; i++) 940 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 941 942 /* 943 * Stop Control DMA engines 944 */ 945 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 946 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 947 948 /* 949 * Reset the controller. The reset must remain asserted for 950 * a minimum of 100us. 951 */ 952 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 953 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 954 count = 10000; 955 do { 956 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 957 if (!(gctl & HDAC_GCTL_CRST)) 958 break; 959 DELAY(10); 960 } while (--count); 961 if (gctl & HDAC_GCTL_CRST) { 962 device_printf(sc->dev, "Unable to put hdac in reset\n"); 963 return (ENXIO); 964 } 965 DELAY(100); 966 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 967 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 968 count = 10000; 969 do { 970 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 971 if (gctl & HDAC_GCTL_CRST) 972 break; 973 DELAY(10); 974 } while (--count); 975 if (!(gctl & HDAC_GCTL_CRST)) { 976 device_printf(sc->dev, "Device stuck in reset\n"); 977 return (ENXIO); 978 } 979 980 /* 981 * Wait for codecs to finish their own reset sequence. The delay here 982 * should be of 250us but for some reasons, on it's not enough on my 983 * computer. Let's use twice as much as necessary to make sure that 984 * it's reset properly. 985 */ 986 DELAY(1000); 987 988 return (0); 989} 990 991 992/**************************************************************************** 993 * int hdac_get_capabilities(struct hdac_softc *); 994 * 995 * Retreive the general capabilities of the hdac; 996 * Number of Input Streams 997 * Number of Output Streams 998 * Number of bidirectional Streams 999 * 64bit ready 1000 * CORB and RIRB sizes 1001 ****************************************************************************/ 1002static int 1003hdac_get_capabilities(struct hdac_softc *sc) 1004{ 1005 uint16_t gcap; 1006 uint8_t corbsize, rirbsize; 1007 1008 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1009 sc->num_iss = HDAC_GCAP_ISS(gcap); 1010 sc->num_oss = HDAC_GCAP_OSS(gcap); 1011 sc->num_bss = HDAC_GCAP_BSS(gcap); 1012 1013 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1014 1015 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1016 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1017 HDAC_CORBSIZE_CORBSZCAP_256) 1018 sc->corb_size = 256; 1019 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1020 HDAC_CORBSIZE_CORBSZCAP_16) 1021 sc->corb_size = 16; 1022 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1023 HDAC_CORBSIZE_CORBSZCAP_2) 1024 sc->corb_size = 2; 1025 else { 1026 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1027 __func__, corbsize); 1028 return (ENXIO); 1029 } 1030 1031 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1032 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1033 HDAC_RIRBSIZE_RIRBSZCAP_256) 1034 sc->rirb_size = 256; 1035 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1036 HDAC_RIRBSIZE_RIRBSZCAP_16) 1037 sc->rirb_size = 16; 1038 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1039 HDAC_RIRBSIZE_RIRBSZCAP_2) 1040 sc->rirb_size = 2; 1041 else { 1042 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1043 __func__, rirbsize); 1044 return (ENXIO); 1045 } 1046 1047 return (0); 1048} 1049 1050 1051/**************************************************************************** 1052 * void hdac_dma_cb 1053 * 1054 * This function is called by bus_dmamap_load when the mapping has been 1055 * established. We just record the physical address of the mapping into 1056 * the struct hdac_dma passed in. 1057 ****************************************************************************/ 1058static void 1059hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1060{ 1061 struct hdac_dma *dma; 1062 1063 if (error == 0) { 1064 dma = (struct hdac_dma *)callback_arg; 1065 dma->dma_paddr = segs[0].ds_addr; 1066 } 1067} 1068 1069static void 1070hdac_dma_nocache(void *ptr) 1071{ 1072#if defined(__i386__) || defined(__amd64__) 1073 pt_entry_t *pte; 1074 vm_offset_t va; 1075 1076 va = (vm_offset_t)ptr; 1077 pte = vtopte(va); 1078 if (pte) { 1079 *pte |= PG_N; 1080 invltlb(); 1081 } 1082#endif 1083} 1084 1085/**************************************************************************** 1086 * int hdac_dma_alloc 1087 * 1088 * This function allocate and setup a dma region (struct hdac_dma). 1089 * It must be freed by a corresponding hdac_dma_free. 1090 ****************************************************************************/ 1091static int 1092hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1093{ 1094 int result; 1095 int lowaddr; 1096 1097 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1098 BUS_SPACE_MAXADDR_32BIT; 1099 bzero(dma, sizeof(*dma)); 1100 1101 /* 1102 * Create a DMA tag 1103 */ 1104 result = bus_dma_tag_create(NULL, /* parent */ 1105 HDAC_DMA_ALIGNMENT, /* alignment */ 1106 0, /* boundary */ 1107 lowaddr, /* lowaddr */ 1108 BUS_SPACE_MAXADDR, /* highaddr */ 1109 NULL, /* filtfunc */ 1110 NULL, /* fistfuncarg */ 1111 size, /* maxsize */ 1112 1, /* nsegments */ 1113 size, /* maxsegsz */ 1114 0, /* flags */ 1115 NULL, /* lockfunc */ 1116 NULL, /* lockfuncarg */ 1117 &dma->dma_tag); /* dmat */ 1118 if (result != 0) { 1119 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1120 __func__, result); 1121 goto fail; 1122 } 1123 1124 /* 1125 * Allocate DMA memory 1126 */ 1127 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1128 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1129 if (result != 0) { 1130 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1131 __func__, result); 1132 goto fail; 1133 } 1134 1135 /* 1136 * Map the memory 1137 */ 1138 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1139 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1140 BUS_DMA_NOWAIT); 1141 if (result != 0 || dma->dma_paddr == 0) { 1142 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1143 __func__, result); 1144 goto fail; 1145 } 1146 bzero((void *)dma->dma_vaddr, size); 1147 hdac_dma_nocache(dma->dma_vaddr); 1148 1149 return (0); 1150fail: 1151 if (dma->dma_map != NULL) 1152 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1153 if (dma->dma_tag != NULL) 1154 bus_dma_tag_destroy(dma->dma_tag); 1155 return (result); 1156} 1157 1158 1159/**************************************************************************** 1160 * void hdac_dma_free(struct hdac_dma *) 1161 * 1162 * Free a struct dhac_dma that has been previously allocated via the 1163 * hdac_dma_alloc function. 1164 ****************************************************************************/ 1165static void 1166hdac_dma_free(struct hdac_dma *dma) 1167{ 1168 if (dma->dma_tag != NULL) { 1169 /* Flush caches */ 1170 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1171 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1172 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1173 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1174 bus_dma_tag_destroy(dma->dma_tag); 1175 } 1176} 1177 1178/**************************************************************************** 1179 * int hdac_mem_alloc(struct hdac_softc *) 1180 * 1181 * Allocate all the bus resources necessary to speak with the physical 1182 * controller. 1183 ****************************************************************************/ 1184static int 1185hdac_mem_alloc(struct hdac_softc *sc) 1186{ 1187 struct hdac_mem *mem; 1188 1189 mem = &sc->mem; 1190 mem->mem_rid = PCIR_BAR(0); 1191 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1192 &mem->mem_rid, RF_ACTIVE); 1193 if (mem->mem_res == NULL) { 1194 device_printf(sc->dev, 1195 "%s: Unable to allocate memory resource\n", __func__); 1196 return (ENOMEM); 1197 } 1198 mem->mem_tag = rman_get_bustag(mem->mem_res); 1199 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1200 1201 return (0); 1202} 1203 1204/**************************************************************************** 1205 * void hdac_mem_free(struct hdac_softc *) 1206 * 1207 * Free up resources previously allocated by hdac_mem_alloc. 1208 ****************************************************************************/ 1209static void 1210hdac_mem_free(struct hdac_softc *sc) 1211{ 1212 struct hdac_mem *mem; 1213 1214 mem = &sc->mem; 1215 if (mem->mem_res != NULL) 1216 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1217 mem->mem_res); 1218 mem->mem_res = NULL; 1219} 1220 1221/**************************************************************************** 1222 * int hdac_irq_alloc(struct hdac_softc *) 1223 * 1224 * Allocate and setup the resources necessary for interrupt handling. 1225 ****************************************************************************/ 1226static int 1227hdac_irq_alloc(struct hdac_softc *sc) 1228{ 1229 struct hdac_irq *irq; 1230 int result; 1231 1232 irq = &sc->irq; 1233 irq->irq_rid = 0x0; 1234 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1235 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1236 if (irq->irq_res == NULL) { 1237 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1238 __func__); 1239 goto fail; 1240 } 1241 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1242 hdac_intr_handler, sc, &irq->irq_handle); 1243 if (result != 0) { 1244 device_printf(sc->dev, 1245 "%s: Unable to setup interrupt handler (%x)\n", 1246 __func__, result); 1247 goto fail; 1248 } 1249 1250 return (0); 1251 1252fail: 1253 hdac_irq_free(sc); 1254 1255 return (ENXIO); 1256} 1257 1258/**************************************************************************** 1259 * void hdac_irq_free(struct hdac_softc *) 1260 * 1261 * Free up resources previously allocated by hdac_irq_alloc. 1262 ****************************************************************************/ 1263static void 1264hdac_irq_free(struct hdac_softc *sc) 1265{ 1266 struct hdac_irq *irq; 1267 1268 irq = &sc->irq; 1269 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1270 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1271 if (irq->irq_res != NULL) 1272 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1273 irq->irq_res); 1274 irq->irq_handle = NULL; 1275 irq->irq_res = NULL; 1276} 1277 1278/**************************************************************************** 1279 * void hdac_corb_init(struct hdac_softc *) 1280 * 1281 * Initialize the corb registers for operations but do not start it up yet. 1282 * The CORB engine must not be running when this function is called. 1283 ****************************************************************************/ 1284static void 1285hdac_corb_init(struct hdac_softc *sc) 1286{ 1287 uint8_t corbsize; 1288 uint64_t corbpaddr; 1289 1290 /* Setup the CORB size. */ 1291 switch (sc->corb_size) { 1292 case 256: 1293 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1294 break; 1295 case 16: 1296 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1297 break; 1298 case 2: 1299 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1300 break; 1301 default: 1302 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1303 } 1304 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1305 1306 /* Setup the CORB Address in the hdac */ 1307 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1308 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1309 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1310 1311 /* Set the WP and RP */ 1312 sc->corb_wp = 0; 1313 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1314 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1315 /* 1316 * The HDA specification indicates that the CORBRPRST bit will always 1317 * read as zero. Unfortunately, it seems that at least the 82801G 1318 * doesn't reset the bit to zero, which stalls the corb engine. 1319 * manually reset the bit to zero before continuing. 1320 */ 1321 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1322 1323 /* Enable CORB error reporting */ 1324#if 0 1325 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1326#endif 1327} 1328 1329/**************************************************************************** 1330 * void hdac_rirb_init(struct hdac_softc *) 1331 * 1332 * Initialize the rirb registers for operations but do not start it up yet. 1333 * The RIRB engine must not be running when this function is called. 1334 ****************************************************************************/ 1335static void 1336hdac_rirb_init(struct hdac_softc *sc) 1337{ 1338 uint8_t rirbsize; 1339 uint64_t rirbpaddr; 1340 1341 /* Setup the RIRB size. */ 1342 switch (sc->rirb_size) { 1343 case 256: 1344 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1345 break; 1346 case 16: 1347 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1348 break; 1349 case 2: 1350 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1351 break; 1352 default: 1353 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1354 } 1355 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1356 1357 /* Setup the RIRB Address in the hdac */ 1358 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1359 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1360 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1361 1362 /* Setup the WP and RP */ 1363 sc->rirb_rp = 0; 1364 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1365 1366 if (sc->polling == 0) { 1367 /* Setup the interrupt threshold */ 1368 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1369 1370 /* Enable Overrun and response received reporting */ 1371#if 0 1372 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1373 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1374#else 1375 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1376#endif 1377 } 1378 1379 /* 1380 * Make sure that the Host CPU cache doesn't contain any dirty 1381 * cache lines that falls in the rirb. If I understood correctly, it 1382 * should be sufficient to do this only once as the rirb is purely 1383 * read-only from now on. 1384 */ 1385 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1386 BUS_DMASYNC_PREREAD); 1387} 1388 1389/**************************************************************************** 1390 * void hdac_corb_start(hdac_softc *) 1391 * 1392 * Startup the corb DMA engine 1393 ****************************************************************************/ 1394static void 1395hdac_corb_start(struct hdac_softc *sc) 1396{ 1397 uint32_t corbctl; 1398 1399 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1400 corbctl |= HDAC_CORBCTL_CORBRUN; 1401 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1402} 1403 1404/**************************************************************************** 1405 * void hdac_rirb_start(hdac_softc *) 1406 * 1407 * Startup the rirb DMA engine 1408 ****************************************************************************/ 1409static void 1410hdac_rirb_start(struct hdac_softc *sc) 1411{ 1412 uint32_t rirbctl; 1413 1414 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1415 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1416 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1417} 1418 1419 1420/**************************************************************************** 1421 * void hdac_scan_codecs(struct hdac_softc *) 1422 * 1423 * Scan the bus for available codecs. 1424 ****************************************************************************/ 1425static void 1426hdac_scan_codecs(struct hdac_softc *sc) 1427{ 1428 struct hdac_codec *codec; 1429 int i; 1430 uint16_t statests; 1431 1432 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1433 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1434 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1435 /* We have found a codec. */ 1436 hdac_unlock(sc); 1437 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1438 M_HDAC, M_ZERO | M_NOWAIT); 1439 hdac_lock(sc); 1440 if (codec == NULL) { 1441 device_printf(sc->dev, 1442 "Unable to allocate memory for codec\n"); 1443 continue; 1444 } 1445 codec->commands = NULL; 1446 codec->responses_received = 0; 1447 codec->verbs_sent = 0; 1448 codec->sc = sc; 1449 codec->cad = i; 1450 sc->codecs[i] = codec; 1451 if (hdac_probe_codec(codec) != 0) 1452 break; 1453 } 1454 } 1455 /* All codecs have been probed, now try to attach drivers to them */ 1456 /* bus_generic_attach(sc->dev); */ 1457} 1458 1459/**************************************************************************** 1460 * void hdac_probe_codec(struct hdac_softc *, int) 1461 * 1462 * Probe a the given codec_id for available function groups. 1463 ****************************************************************************/ 1464static int 1465hdac_probe_codec(struct hdac_codec *codec) 1466{ 1467 struct hdac_softc *sc = codec->sc; 1468 struct hdac_devinfo *devinfo; 1469 uint32_t vendorid, revisionid, subnode; 1470 int startnode; 1471 int endnode; 1472 int i; 1473 nid_t cad = codec->cad; 1474 1475 HDA_BOOTVERBOSE( 1476 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1477 ); 1478 vendorid = hdac_command(sc, 1479 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1480 cad); 1481 revisionid = hdac_command(sc, 1482 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1483 cad); 1484 subnode = hdac_command(sc, 1485 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1486 cad); 1487 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1488 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1489 1490 HDA_BOOTVERBOSE( 1491 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1492 startnode, endnode); 1493 ); 1494 for (i = startnode; i < endnode; i++) { 1495 devinfo = hdac_probe_function(codec, i); 1496 if (devinfo != NULL) { 1497 /* XXX Ignore other FG. */ 1498 devinfo->vendor_id = 1499 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1500 devinfo->device_id = 1501 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1502 devinfo->revision_id = 1503 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1504 devinfo->stepping_id = 1505 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1506 HDA_BOOTVERBOSE( 1507 device_printf(sc->dev, 1508 "HDA_DEBUG: \tFound AFG nid=%d " 1509 "[startnode=%d endnode=%d]\n", 1510 devinfo->nid, startnode, endnode); 1511 ); 1512 return (1); 1513 } 1514 } 1515 1516 HDA_BOOTVERBOSE( 1517 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1518 ); 1519 return (0); 1520} 1521 1522static struct hdac_devinfo * 1523hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1524{ 1525 struct hdac_softc *sc = codec->sc; 1526 struct hdac_devinfo *devinfo; 1527 uint32_t fctgrptype; 1528 nid_t cad = codec->cad; 1529 1530 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1531 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1532 1533 /* XXX For now, ignore other FG. */ 1534 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1535 return (NULL); 1536 1537 hdac_unlock(sc); 1538 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1539 M_NOWAIT | M_ZERO); 1540 hdac_lock(sc); 1541 if (devinfo == NULL) { 1542 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1543 __func__); 1544 return (NULL); 1545 } 1546 1547 devinfo->nid = nid; 1548 devinfo->node_type = fctgrptype; 1549 devinfo->codec = codec; 1550 1551 hdac_add_child(sc, devinfo); 1552 1553 return (devinfo); 1554} 1555 1556static void 1557hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1558{ 1559 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1560 device_set_ivars(devinfo->dev, (void *)devinfo); 1561 /* XXX - Print more information when booting verbose??? */ 1562} 1563 1564static void 1565hdac_widget_connection_parse(struct hdac_widget *w) 1566{ 1567 struct hdac_softc *sc = w->devinfo->codec->sc; 1568 uint32_t res; 1569 int i, j, max, found, entnum, cnid; 1570 nid_t cad = w->devinfo->codec->cad; 1571 nid_t nid = w->nid; 1572 1573 res = hdac_command(sc, 1574 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1575 1576 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1577 1578 if (w->nconns < 1) 1579 return; 1580 1581 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1582 res = 0; 1583 i = 0; 1584 found = 0; 1585 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1586 1587 while (i < w->nconns) { 1588 res = hdac_command(sc, 1589 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1590 for (j = 0; j < entnum; j++) { 1591 cnid = res; 1592 cnid >>= (32 / entnum) * j; 1593 cnid &= (1 << (32 / entnum)) - 1; 1594 if (cnid == 0) 1595 continue; 1596 if (found > max) { 1597 device_printf(sc->dev, 1598 "node %d: Adding %d: " 1599 "Max connection reached!\n", 1600 nid, cnid); 1601 continue; 1602 } 1603 w->conns[found++] = cnid; 1604 } 1605 i += entnum; 1606 } 1607 1608 HDA_BOOTVERBOSE( 1609 if (w->nconns != found) { 1610 device_printf(sc->dev, 1611 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1612 "length=%d != found=%d\n", 1613 nid, w->nconns, found); 1614 } 1615 ); 1616} 1617 1618static uint32_t 1619hdac_widget_pin_getconfig(struct hdac_widget *w) 1620{ 1621 struct hdac_softc *sc; 1622 uint32_t config, id; 1623 nid_t cad, nid; 1624 1625 sc = w->devinfo->codec->sc; 1626 cad = w->devinfo->codec->cad; 1627 nid = w->nid; 1628 id = hdac_codec_id(w->devinfo); 1629 1630 config = hdac_command(sc, 1631 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1632 cad); 1633 /* 1634 * XXX REWRITE!!!! Don't argue! 1635 */ 1636 if (id == HDA_CODEC_ALC880 && 1637 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1638 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1639 /* 1640 * Super broken BIOS 1641 */ 1642 switch (nid) { 1643 case 20: 1644 break; 1645 case 21: 1646 break; 1647 case 22: 1648 break; 1649 case 23: 1650 break; 1651 case 24: /* MIC1 */ 1652 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1653 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1654 break; 1655 case 25: /* XXX MIC2 */ 1656 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1657 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1658 break; 1659 case 26: /* LINE1 */ 1660 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1661 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1662 break; 1663 case 27: /* XXX LINE2 */ 1664 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1665 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1666 break; 1667 case 28: /* CD */ 1668 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1669 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1670 break; 1671 case 30: 1672 break; 1673 case 31: 1674 break; 1675 default: 1676 break; 1677 } 1678 } 1679 1680 return (config); 1681} 1682 1683static void 1684hdac_widget_pin_parse(struct hdac_widget *w) 1685{ 1686 struct hdac_softc *sc = w->devinfo->codec->sc; 1687 uint32_t config, pincap; 1688 char *devstr, *connstr; 1689 nid_t cad = w->devinfo->codec->cad; 1690 nid_t nid = w->nid; 1691 1692 config = hdac_widget_pin_getconfig(w); 1693 w->wclass.pin.config = config; 1694 1695 pincap = hdac_command(sc, 1696 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1697 w->wclass.pin.cap = pincap; 1698 1699 w->wclass.pin.ctrl = hdac_command(sc, 1700 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1701 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1702 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1703 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1704 1705 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1706 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1707 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1708 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1709 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1710 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1711 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1712 w->param.eapdbtl = hdac_command(sc, 1713 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1714 w->param.eapdbtl &= 0x7; 1715 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1716 } else 1717 w->param.eapdbtl = HDAC_INVALID; 1718 1719 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1720 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1721 devstr = "line out"; 1722 break; 1723 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1724 devstr = "speaker"; 1725 break; 1726 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1727 devstr = "headphones out"; 1728 break; 1729 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1730 devstr = "CD"; 1731 break; 1732 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1733 devstr = "SPDIF out"; 1734 break; 1735 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1736 devstr = "digital (other) out"; 1737 break; 1738 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1739 devstr = "modem, line side"; 1740 break; 1741 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1742 devstr = "modem, handset side"; 1743 break; 1744 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1745 devstr = "line in"; 1746 break; 1747 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1748 devstr = "AUX"; 1749 break; 1750 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1751 devstr = "Mic in"; 1752 break; 1753 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1754 devstr = "telephony"; 1755 break; 1756 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1757 devstr = "SPDIF in"; 1758 break; 1759 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1760 devstr = "digital (other) in"; 1761 break; 1762 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1763 devstr = "other"; 1764 break; 1765 default: 1766 devstr = "unknown"; 1767 break; 1768 } 1769 1770 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1771 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1772 connstr = "jack"; 1773 break; 1774 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1775 connstr = "none"; 1776 break; 1777 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1778 connstr = "fixed"; 1779 break; 1780 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1781 connstr = "jack / fixed"; 1782 break; 1783 default: 1784 connstr = "unknown"; 1785 break; 1786 } 1787 1788 strlcat(w->name, ": ", sizeof(w->name)); 1789 strlcat(w->name, devstr, sizeof(w->name)); 1790 strlcat(w->name, " (", sizeof(w->name)); 1791 strlcat(w->name, connstr, sizeof(w->name)); 1792 strlcat(w->name, ")", sizeof(w->name)); 1793} 1794 1795static void 1796hdac_widget_parse(struct hdac_widget *w) 1797{ 1798 struct hdac_softc *sc = w->devinfo->codec->sc; 1799 uint32_t wcap, cap; 1800 char *typestr; 1801 nid_t cad = w->devinfo->codec->cad; 1802 nid_t nid = w->nid; 1803 1804 wcap = hdac_command(sc, 1805 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1806 cad); 1807 w->param.widget_cap = wcap; 1808 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1809 1810 switch (w->type) { 1811 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1812 typestr = "audio output"; 1813 break; 1814 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1815 typestr = "audio input"; 1816 break; 1817 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1818 typestr = "audio mixer"; 1819 break; 1820 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1821 typestr = "audio selector"; 1822 break; 1823 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1824 typestr = "pin"; 1825 break; 1826 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1827 typestr = "power widget"; 1828 break; 1829 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1830 typestr = "volume widget"; 1831 break; 1832 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1833 typestr = "beep widget"; 1834 break; 1835 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1836 typestr = "vendor widget"; 1837 break; 1838 default: 1839 typestr = "unknown type"; 1840 break; 1841 } 1842 1843 strlcpy(w->name, typestr, sizeof(w->name)); 1844 1845 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1846 hdac_command(sc, 1847 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1848 cad); 1849 DELAY(1000); 1850 } 1851 1852 hdac_widget_connection_parse(w); 1853 1854 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1855 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1856 w->param.outamp_cap = 1857 hdac_command(sc, 1858 HDA_CMD_GET_PARAMETER(cad, nid, 1859 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1860 else 1861 w->param.outamp_cap = 1862 w->devinfo->function.audio.outamp_cap; 1863 } else 1864 w->param.outamp_cap = 0; 1865 1866 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1867 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1868 w->param.inamp_cap = 1869 hdac_command(sc, 1870 HDA_CMD_GET_PARAMETER(cad, nid, 1871 HDA_PARAM_INPUT_AMP_CAP), cad); 1872 else 1873 w->param.inamp_cap = 1874 w->devinfo->function.audio.inamp_cap; 1875 } else 1876 w->param.inamp_cap = 0; 1877 1878 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1879 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1880 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1881 cap = hdac_command(sc, 1882 HDA_CMD_GET_PARAMETER(cad, nid, 1883 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1884 w->param.supp_stream_formats = (cap != 0) ? cap : 1885 w->devinfo->function.audio.supp_stream_formats; 1886 cap = hdac_command(sc, 1887 HDA_CMD_GET_PARAMETER(cad, nid, 1888 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1889 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1890 w->devinfo->function.audio.supp_pcm_size_rate; 1891 } else { 1892 w->param.supp_stream_formats = 1893 w->devinfo->function.audio.supp_stream_formats; 1894 w->param.supp_pcm_size_rate = 1895 w->devinfo->function.audio.supp_pcm_size_rate; 1896 } 1897 } else { 1898 w->param.supp_stream_formats = 0; 1899 w->param.supp_pcm_size_rate = 0; 1900 } 1901 1902 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1903 hdac_widget_pin_parse(w); 1904} 1905 1906static struct hdac_widget * 1907hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1908{ 1909 if (devinfo == NULL || devinfo->widget == NULL || 1910 nid < devinfo->startnode || nid >= devinfo->endnode) 1911 return (NULL); 1912 return (&devinfo->widget[nid - devinfo->startnode]); 1913} 1914 1915static __inline int 1916hda_poll_channel(struct hdac_chan *ch) 1917{ 1918 uint32_t sz, delta; 1919 volatile uint32_t ptr; 1920 1921 if (ch->active == 0) 1922 return (0); 1923 1924 sz = ch->blksz * ch->blkcnt; 1925 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1926 ch->ptr = ptr; 1927 ptr %= sz; 1928 ptr &= ~(ch->blksz - 1); 1929 delta = (sz + ptr - ch->prevptr) % sz; 1930 1931 if (delta < ch->blksz) 1932 return (0); 1933 1934 ch->prevptr = ptr; 1935 1936 return (1); 1937} 1938 1939#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1940 1941static void 1942hda_poll_callback(void *arg) 1943{ 1944 struct hdac_softc *sc = arg; 1945 uint32_t trigger = 0; 1946 1947 if (sc == NULL) 1948 return; 1949 1950 hdac_lock(sc); 1951 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 1952 hdac_unlock(sc); 1953 return; 1954 } 1955 1956 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 1957 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 1958 1959 /* XXX */ 1960 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 1961 hda_poll_callback, sc); 1962 1963 hdac_unlock(sc); 1964 1965 if (trigger & 1) 1966 chn_intr(sc->play.c); 1967 if (trigger & 2) 1968 chn_intr(sc->rec.c); 1969} 1970 1971static int 1972hdac_rirb_flush(struct hdac_softc *sc) 1973{ 1974 struct hdac_rirb *rirb_base, *rirb; 1975 struct hdac_codec *codec; 1976 struct hdac_command_list *commands; 1977 nid_t cad; 1978 uint32_t resp; 1979 uint8_t rirbwp; 1980 int ret = 0; 1981 1982 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1983 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 1984 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1985 BUS_DMASYNC_POSTREAD); 1986 1987 while (sc->rirb_rp != rirbwp) { 1988 sc->rirb_rp++; 1989 sc->rirb_rp %= sc->rirb_size; 1990 rirb = &rirb_base[sc->rirb_rp]; 1991 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 1992 if (cad < 0 || cad >= HDAC_CODEC_MAX || 1993 sc->codecs[cad] == NULL) 1994 continue; 1995 resp = rirb->response; 1996 codec = sc->codecs[cad]; 1997 commands = codec->commands; 1998 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 1999 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2000 ((resp >> 26) & 0xffff); 2001 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2002 } else if (commands != NULL && commands->num_commands > 0 && 2003 codec->responses_received < commands->num_commands) 2004 commands->responses[codec->responses_received++] = 2005 resp; 2006 ret++; 2007 } 2008 2009 return (ret); 2010} 2011 2012static int 2013hdac_unsolq_flush(struct hdac_softc *sc) 2014{ 2015 nid_t cad; 2016 uint32_t tag; 2017 int ret = 0; 2018 2019 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2020 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2021 while (sc->unsolq_rp != sc->unsolq_wp) { 2022 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2023 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2024 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2025 hdac_unsolicited_handler(sc->codecs[cad], tag); 2026 ret++; 2027 } 2028 sc->unsolq_st = HDAC_UNSOLQ_READY; 2029 } 2030 2031 return (ret); 2032} 2033 2034static void 2035hdac_poll_callback(void *arg) 2036{ 2037 struct hdac_softc *sc = arg; 2038 if (sc == NULL) 2039 return; 2040 2041 hdac_lock(sc); 2042 if (sc->polling == 0) { 2043 hdac_unlock(sc); 2044 return; 2045 } 2046 hdac_rirb_flush(sc); 2047 hdac_unsolq_flush(sc); 2048 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2049 hdac_poll_callback, sc); 2050 hdac_unlock(sc); 2051} 2052 2053static void 2054hdac_stream_stop(struct hdac_chan *ch) 2055{ 2056 struct hdac_softc *sc = ch->devinfo->codec->sc; 2057 uint32_t ctl; 2058 2059 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2060 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2061 HDAC_SDCTL_RUN); 2062 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2063 2064 ch->active = 0; 2065 2066 if (sc->polling != 0) { 2067 int pollticks; 2068 2069 if (hda_chan_active(sc) == 0) { 2070 callout_stop(&sc->poll_hda); 2071 sc->poll_ticks = 1; 2072 } else { 2073 if (sc->play.active != 0) 2074 ch = &sc->play; 2075 else 2076 ch = &sc->rec; 2077 pollticks = ((uint64_t)hz * ch->blksz) / 2078 ((uint64_t)sndbuf_getbps(ch->b) * 2079 sndbuf_getspd(ch->b)); 2080 pollticks >>= 2; 2081 if (pollticks > hz) 2082 pollticks = hz; 2083 if (pollticks < 1) { 2084 HDA_BOOTVERBOSE( 2085 device_printf(sc->dev, 2086 "%s: pollticks=%d < 1 !\n", 2087 __func__, pollticks); 2088 ); 2089 pollticks = 1; 2090 } 2091 if (pollticks > sc->poll_ticks) { 2092 HDA_BOOTVERBOSE( 2093 device_printf(sc->dev, 2094 "%s: pollticks %d -> %d\n", 2095 __func__, sc->poll_ticks, 2096 pollticks); 2097 ); 2098 sc->poll_ticks = pollticks; 2099 callout_reset(&sc->poll_hda, 1, 2100 hda_poll_callback, sc); 2101 } 2102 } 2103 } else { 2104 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2105 ctl &= ~(1 << (ch->off >> 5)); 2106 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2107 } 2108} 2109 2110static void 2111hdac_stream_start(struct hdac_chan *ch) 2112{ 2113 struct hdac_softc *sc = ch->devinfo->codec->sc; 2114 uint32_t ctl; 2115 2116 if (sc->polling != 0) { 2117 int pollticks; 2118 2119 pollticks = ((uint64_t)hz * ch->blksz) / 2120 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2121 pollticks >>= 2; 2122 if (pollticks > hz) 2123 pollticks = hz; 2124 if (pollticks < 1) { 2125 HDA_BOOTVERBOSE( 2126 device_printf(sc->dev, 2127 "%s: pollticks=%d < 1 !\n", 2128 __func__, pollticks); 2129 ); 2130 pollticks = 1; 2131 } 2132 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2133 HDA_BOOTVERBOSE( 2134 if (hda_chan_active(sc) == 0) { 2135 device_printf(sc->dev, 2136 "%s: pollticks=%d\n", 2137 __func__, pollticks); 2138 } else { 2139 device_printf(sc->dev, 2140 "%s: pollticks %d -> %d\n", 2141 __func__, sc->poll_ticks, 2142 pollticks); 2143 } 2144 ); 2145 sc->poll_ticks = pollticks; 2146 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2147 sc); 2148 } 2149 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2150 ctl |= HDAC_SDCTL_RUN; 2151 } else { 2152 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2153 ctl |= 1 << (ch->off >> 5); 2154 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2155 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2156 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2157 HDAC_SDCTL_RUN; 2158 } 2159 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2160 2161 ch->active = 1; 2162} 2163 2164static void 2165hdac_stream_reset(struct hdac_chan *ch) 2166{ 2167 struct hdac_softc *sc = ch->devinfo->codec->sc; 2168 int timeout = 1000; 2169 int to = timeout; 2170 uint32_t ctl; 2171 2172 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2173 ctl |= HDAC_SDCTL_SRST; 2174 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2175 do { 2176 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2177 if (ctl & HDAC_SDCTL_SRST) 2178 break; 2179 DELAY(10); 2180 } while (--to); 2181 if (!(ctl & HDAC_SDCTL_SRST)) { 2182 device_printf(sc->dev, "timeout in reset\n"); 2183 } 2184 ctl &= ~HDAC_SDCTL_SRST; 2185 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2186 to = timeout; 2187 do { 2188 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2189 if (!(ctl & HDAC_SDCTL_SRST)) 2190 break; 2191 DELAY(10); 2192 } while (--to); 2193 if (ctl & HDAC_SDCTL_SRST) 2194 device_printf(sc->dev, "can't reset!\n"); 2195} 2196 2197static void 2198hdac_stream_setid(struct hdac_chan *ch) 2199{ 2200 struct hdac_softc *sc = ch->devinfo->codec->sc; 2201 uint32_t ctl; 2202 2203 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2204 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2205 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2206 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2207} 2208 2209static void 2210hdac_bdl_setup(struct hdac_chan *ch) 2211{ 2212 struct hdac_softc *sc = ch->devinfo->codec->sc; 2213 struct hdac_bdle *bdle; 2214 uint64_t addr; 2215 uint32_t blksz, blkcnt; 2216 int i; 2217 2218 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2219 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2220 2221 if (sc->polling != 0) { 2222 blksz = ch->blksz * ch->blkcnt; 2223 blkcnt = 1; 2224 } else { 2225 blksz = ch->blksz; 2226 blkcnt = ch->blkcnt; 2227 } 2228 2229 for (i = 0; i < blkcnt; i++, bdle++) { 2230 bdle->addrl = (uint32_t)addr; 2231 bdle->addrh = (uint32_t)(addr >> 32); 2232 bdle->len = blksz; 2233 bdle->ioc = 1 ^ sc->polling; 2234 addr += blksz; 2235 } 2236 2237 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2238 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2239 addr = ch->bdl_dma.dma_paddr; 2240 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2241 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2242} 2243 2244static int 2245hdac_bdl_alloc(struct hdac_chan *ch) 2246{ 2247 struct hdac_softc *sc = ch->devinfo->codec->sc; 2248 int rc; 2249 2250 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2251 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2252 if (rc) { 2253 device_printf(sc->dev, "can't alloc bdl\n"); 2254 return (rc); 2255 } 2256 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2257 2258 return (0); 2259} 2260 2261static void 2262hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2263 int index, int lmute, int rmute, 2264 int left, int right, int dir) 2265{ 2266 uint16_t v = 0; 2267 2268 if (sc == NULL) 2269 return; 2270 2271 if (left != right || lmute != rmute) { 2272 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2273 (lmute << 7) | left; 2274 hdac_command(sc, 2275 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2276 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2277 (rmute << 7) | right; 2278 } else 2279 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2280 (lmute << 7) | left; 2281 2282 hdac_command(sc, 2283 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2284} 2285 2286static void 2287hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2288 int left, int right) 2289{ 2290 struct hdac_softc *sc; 2291 nid_t nid, cad; 2292 int lmute, rmute; 2293 2294 if (ctl == NULL || ctl->widget == NULL || 2295 ctl->widget->devinfo == NULL || 2296 ctl->widget->devinfo->codec == NULL || 2297 ctl->widget->devinfo->codec->sc == NULL) 2298 return; 2299 2300 sc = ctl->widget->devinfo->codec->sc; 2301 cad = ctl->widget->devinfo->codec->cad; 2302 nid = ctl->widget->nid; 2303 2304 if (mute == HDA_AMP_MUTE_DEFAULT) { 2305 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2306 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2307 } else { 2308 lmute = HDA_AMP_LEFT_MUTED(mute); 2309 rmute = HDA_AMP_RIGHT_MUTED(mute); 2310 } 2311 2312 if (ctl->dir & HDA_CTL_OUT) 2313 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2314 lmute, rmute, left, right, 0); 2315 if (ctl->dir & HDA_CTL_IN) 2316 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2317 lmute, rmute, left, right, 1); 2318 ctl->left = left; 2319 ctl->right = right; 2320} 2321 2322static void 2323hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2324{ 2325 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2326 return; 2327 hdac_command(w->devinfo->codec->sc, 2328 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2329 w->nid, index), w->devinfo->codec->cad); 2330 w->selconn = index; 2331} 2332 2333 2334/**************************************************************************** 2335 * uint32_t hdac_command_sendone_internal 2336 * 2337 * Wrapper function that sends only one command to a given codec 2338 ****************************************************************************/ 2339static uint32_t 2340hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2341{ 2342 struct hdac_command_list cl; 2343 uint32_t response = HDAC_INVALID; 2344 2345 if (!hdac_lockowned(sc)) 2346 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2347 cl.num_commands = 1; 2348 cl.verbs = &verb; 2349 cl.responses = &response; 2350 2351 hdac_command_send_internal(sc, &cl, cad); 2352 2353 return (response); 2354} 2355 2356/**************************************************************************** 2357 * hdac_command_send_internal 2358 * 2359 * Send a command list to the codec via the corb. We queue as much verbs as 2360 * we can and msleep on the codec. When the interrupt get the responses 2361 * back from the rirb, it will wake us up so we can queue the remaining verbs 2362 * if any. 2363 ****************************************************************************/ 2364static void 2365hdac_command_send_internal(struct hdac_softc *sc, 2366 struct hdac_command_list *commands, nid_t cad) 2367{ 2368 struct hdac_codec *codec; 2369 int corbrp; 2370 uint32_t *corb; 2371 int timeout; 2372 int retry = 10; 2373 struct hdac_rirb *rirb_base; 2374 2375 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2376 commands->num_commands < 1) 2377 return; 2378 2379 codec = sc->codecs[cad]; 2380 codec->commands = commands; 2381 codec->responses_received = 0; 2382 codec->verbs_sent = 0; 2383 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2384 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2385 2386 do { 2387 if (codec->verbs_sent != commands->num_commands) { 2388 /* Queue as many verbs as possible */ 2389 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2390 bus_dmamap_sync(sc->corb_dma.dma_tag, 2391 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2392 while (codec->verbs_sent != commands->num_commands && 2393 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2394 sc->corb_wp++; 2395 sc->corb_wp %= sc->corb_size; 2396 corb[sc->corb_wp] = 2397 commands->verbs[codec->verbs_sent++]; 2398 } 2399 2400 /* Send the verbs to the codecs */ 2401 bus_dmamap_sync(sc->corb_dma.dma_tag, 2402 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2403 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2404 } 2405 2406 timeout = 1000; 2407 while (hdac_rirb_flush(sc) == 0 && --timeout) 2408 DELAY(10); 2409 } while ((codec->verbs_sent != commands->num_commands || 2410 codec->responses_received != commands->num_commands) && --retry); 2411 2412 if (retry == 0) 2413 device_printf(sc->dev, 2414 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2415 __func__, commands->num_commands, codec->verbs_sent, 2416 codec->responses_received); 2417 2418 codec->commands = NULL; 2419 codec->responses_received = 0; 2420 codec->verbs_sent = 0; 2421 2422 hdac_unsolq_flush(sc); 2423} 2424 2425 2426/**************************************************************************** 2427 * Device Methods 2428 ****************************************************************************/ 2429 2430/**************************************************************************** 2431 * int hdac_probe(device_t) 2432 * 2433 * Probe for the presence of an hdac. If none is found, check for a generic 2434 * match using the subclass of the device. 2435 ****************************************************************************/ 2436static int 2437hdac_probe(device_t dev) 2438{ 2439 int i, result; 2440 uint32_t model; 2441 uint16_t class, subclass; 2442 char desc[64]; 2443 2444 model = (uint32_t)pci_get_device(dev) << 16; 2445 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2446 class = pci_get_class(dev); 2447 subclass = pci_get_subclass(dev); 2448 2449 bzero(desc, sizeof(desc)); 2450 result = ENXIO; 2451 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2452 if (hdac_devices[i].model == model) { 2453 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2454 result = BUS_PROBE_DEFAULT; 2455 break; 2456 } 2457 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2458 class == PCIC_MULTIMEDIA && 2459 subclass == PCIS_MULTIMEDIA_HDA) { 2460 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2461 result = BUS_PROBE_GENERIC; 2462 break; 2463 } 2464 } 2465 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2466 subclass == PCIS_MULTIMEDIA_HDA) { 2467 strlcpy(desc, "Generic", sizeof(desc)); 2468 result = BUS_PROBE_GENERIC; 2469 } 2470 if (result != ENXIO) { 2471 strlcat(desc, " High Definition Audio Controller", 2472 sizeof(desc)); 2473 device_set_desc_copy(dev, desc); 2474 } 2475 2476 return (result); 2477} 2478 2479static void * 2480hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2481 struct pcm_channel *c, int dir) 2482{ 2483 struct hdac_devinfo *devinfo = data; 2484 struct hdac_softc *sc = devinfo->codec->sc; 2485 struct hdac_chan *ch; 2486 2487 hdac_lock(sc); 2488 if (dir == PCMDIR_PLAY) { 2489 ch = &sc->play; 2490 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2491 ch->dir = PCMDIR_PLAY; 2492 ch->sid = ++sc->streamcnt; 2493 devinfo->function.audio.playcnt++; 2494 } else { 2495 ch = &sc->rec; 2496 ch->off = devinfo->function.audio.reccnt << 5; 2497 ch->dir = PCMDIR_REC; 2498 ch->sid = ++sc->streamcnt; 2499 devinfo->function.audio.reccnt++; 2500 } 2501 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2502 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2503 ch->pcmrates[0] = 48000; 2504 ch->pcmrates[1] = 0; 2505 } 2506 ch->b = b; 2507 ch->c = c; 2508 ch->devinfo = devinfo; 2509 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2510 ch->blkcnt = sc->chan_blkcnt; 2511 hdac_unlock(sc); 2512 2513 if (hdac_bdl_alloc(ch) != 0) { 2514 ch->blkcnt = 0; 2515 return (NULL); 2516 } 2517 2518 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2519 return (NULL); 2520 2521 hdac_dma_nocache(ch->b->buf); 2522 2523 return (ch); 2524} 2525 2526static int 2527hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2528{ 2529 struct hdac_chan *ch = data; 2530 int i; 2531 2532 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2533 if (format == ch->caps.fmtlist[i]) { 2534 ch->fmt = format; 2535 return (0); 2536 } 2537 } 2538 2539 return (EINVAL); 2540} 2541 2542static int 2543hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2544{ 2545 struct hdac_chan *ch = data; 2546 uint32_t spd = 0, threshold; 2547 int i; 2548 2549 for (i = 0; ch->pcmrates[i] != 0; i++) { 2550 spd = ch->pcmrates[i]; 2551 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2552 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2553 if (speed < threshold) 2554 break; 2555 } 2556 2557 if (spd == 0) /* impossible */ 2558 ch->spd = 48000; 2559 else 2560 ch->spd = spd; 2561 2562 return (ch->spd); 2563} 2564 2565static void 2566hdac_stream_setup(struct hdac_chan *ch) 2567{ 2568 struct hdac_softc *sc = ch->devinfo->codec->sc; 2569 int i; 2570 nid_t cad = ch->devinfo->codec->cad; 2571 uint16_t fmt; 2572 2573 fmt = 0; 2574 if (ch->fmt & AFMT_S16_LE) 2575 fmt |= ch->bit16 << 4; 2576 else if (ch->fmt & AFMT_S32_LE) 2577 fmt |= ch->bit32 << 4; 2578 else 2579 fmt |= 1 << 4; 2580 2581 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2582 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2583 fmt |= hda_rate_tab[i].base; 2584 fmt |= hda_rate_tab[i].mul; 2585 fmt |= hda_rate_tab[i].div; 2586 break; 2587 } 2588 } 2589 2590 if (ch->fmt & AFMT_STEREO) 2591 fmt |= 1; 2592 2593 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2594 2595 for (i = 0; ch->io[i] != -1; i++) { 2596 HDA_BOOTVERBOSE( 2597 device_printf(sc->dev, 2598 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2599 "fmt=0x%08x\n", 2600 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2601 ch->io[i], fmt); 2602 ); 2603 hdac_command(sc, 2604 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2605 hdac_command(sc, 2606 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2607 ch->sid << 4), cad); 2608 } 2609} 2610 2611static int 2612hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2613{ 2614 struct hdac_chan *ch = data; 2615 struct hdac_softc *sc = ch->devinfo->codec->sc; 2616 2617 blksz &= ~0x7f; 2618 if (blksz < 0x80) 2619 blksz = 0x80; 2620 2621 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2622 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2623 2624 if ((sndbuf_getblksz(ch->b) != blksz || 2625 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2626 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2627 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2628 __func__, blksz, ch->blkcnt); 2629 2630 ch->blksz = sndbuf_getblksz(ch->b); 2631 2632 return (ch->blksz); 2633} 2634 2635static void 2636hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2637{ 2638 struct hdac_devinfo *devinfo = ch->devinfo; 2639 nid_t cad = devinfo->codec->cad; 2640 int i; 2641 2642 hdac_stream_stop(ch); 2643 2644 for (i = 0; ch->io[i] != -1; i++) { 2645 hdac_command(sc, 2646 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2647 0), cad); 2648 } 2649} 2650 2651static void 2652hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2653{ 2654 ch->ptr = 0; 2655 ch->prevptr = 0; 2656 hdac_stream_stop(ch); 2657 hdac_stream_reset(ch); 2658 hdac_bdl_setup(ch); 2659 hdac_stream_setid(ch); 2660 hdac_stream_setup(ch); 2661 hdac_stream_start(ch); 2662} 2663 2664static int 2665hdac_channel_trigger(kobj_t obj, void *data, int go) 2666{ 2667 struct hdac_chan *ch = data; 2668 struct hdac_softc *sc = ch->devinfo->codec->sc; 2669 2670 hdac_lock(sc); 2671 switch (go) { 2672 case PCMTRIG_START: 2673 hdac_channel_start(sc, ch); 2674 break; 2675 case PCMTRIG_STOP: 2676 case PCMTRIG_ABORT: 2677 hdac_channel_stop(sc, ch); 2678 break; 2679 } 2680 hdac_unlock(sc); 2681 2682 return (0); 2683} 2684 2685static int 2686hdac_channel_getptr(kobj_t obj, void *data) 2687{ 2688 struct hdac_chan *ch = data; 2689 struct hdac_softc *sc = ch->devinfo->codec->sc; 2690 uint32_t ptr; 2691 2692 hdac_lock(sc); 2693 if (sc->polling != 0) 2694 ptr = ch->ptr; 2695 else 2696 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2697 hdac_unlock(sc); 2698 2699 /* 2700 * Round to available space and force 128 bytes aligment. 2701 */ 2702 ptr %= ch->blksz * ch->blkcnt; 2703 ptr &= ~0x7f; 2704 2705 return (ptr); 2706} 2707 2708static struct pcmchan_caps * 2709hdac_channel_getcaps(kobj_t obj, void *data) 2710{ 2711 return (&((struct hdac_chan *)data)->caps); 2712} 2713 2714static kobj_method_t hdac_channel_methods[] = { 2715 KOBJMETHOD(channel_init, hdac_channel_init), 2716 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2717 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2718 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2719 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2720 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2721 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2722 { 0, 0 } 2723}; 2724CHANNEL_DECLARE(hdac_channel); 2725 2726static int 2727hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2728{ 2729 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2730 struct hdac_softc *sc = devinfo->codec->sc; 2731 struct hdac_widget *w, *cw; 2732 struct hdac_audio_ctl *ctl; 2733 uint32_t mask, recmask, id; 2734 int i, j, softpcmvol; 2735 nid_t cad; 2736 2737 hdac_lock(sc); 2738 2739 mask = 0; 2740 recmask = 0; 2741 2742 id = hdac_codec_id(devinfo); 2743 cad = devinfo->codec->cad; 2744 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2745 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2746 sc->pci_subvendor) && 2747 hdac_hp_switch[i].id == id)) 2748 continue; 2749 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2750 if (w != NULL && w->enable != 0 2751 && w->type == 2752 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2753 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2754 hdac_command(sc, 2755 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2756 w->nid, 2757 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2758 HDAC_UNSOLTAG_EVENT_HP), cad); 2759 hdac_hp_switch_handler(devinfo); 2760 HDA_BOOTVERBOSE( 2761 device_printf(sc->dev, 2762 "HDA_DEBUG: Enabling headphone/speaker " 2763 "audio routing switching:\n"); 2764 device_printf(sc->dev, 2765 "HDA_DEBUG: \tindex=%d nid=%d " 2766 "pci_subvendor=0x%08x " 2767 "codec=0x%08x\n", 2768 i, w->nid, sc->pci_subvendor, id); 2769 ); 2770 } 2771 break; 2772 } 2773 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2774 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2775 sc->pci_subvendor) && 2776 hdac_eapd_switch[i].id == id)) 2777 continue; 2778 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2779 if (w == NULL || w->enable == 0) 2780 break; 2781 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2782 w->param.eapdbtl == HDAC_INVALID) 2783 break; 2784 mask |= SOUND_MASK_OGAIN; 2785 break; 2786 } 2787 2788 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2789 w = hdac_widget_get(devinfo, i); 2790 if (w == NULL || w->enable == 0) 2791 continue; 2792 mask |= w->ctlflags; 2793 if (!(w->pflags & HDA_ADC_RECSEL)) 2794 continue; 2795 for (j = 0; j < w->nconns; j++) { 2796 cw = hdac_widget_get(devinfo, w->conns[j]); 2797 if (cw == NULL || cw->enable == 0) 2798 continue; 2799 recmask |= cw->ctlflags; 2800 } 2801 } 2802 2803 if (!(mask & SOUND_MASK_PCM)) { 2804 softpcmvol = 1; 2805 mask |= SOUND_MASK_PCM; 2806 } else 2807 softpcmvol = (devinfo->function.audio.quirks & 2808 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2809 2810 i = 0; 2811 ctl = NULL; 2812 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2813 if (ctl->widget == NULL || ctl->enable == 0) 2814 continue; 2815 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2816 continue; 2817 if (ctl->step > 0) 2818 break; 2819 } 2820 2821 if (softpcmvol == 1 || ctl == NULL) { 2822 struct snddev_info *d = NULL; 2823 d = device_get_softc(sc->dev); 2824 if (d != NULL) { 2825 d->flags |= SD_F_SOFTPCMVOL; 2826 HDA_BOOTVERBOSE( 2827 device_printf(sc->dev, 2828 "HDA_DEBUG: %s Soft PCM volume\n", 2829 (softpcmvol == 1) ? 2830 "Forcing" : "Enabling"); 2831 ); 2832 } 2833 i = 0; 2834 /* 2835 * XXX Temporary quirk for STAC9220, until the parser 2836 * become smarter. 2837 */ 2838 if (id == HDA_CODEC_STAC9220) { 2839 mask |= SOUND_MASK_VOLUME; 2840 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2841 NULL) { 2842 if (ctl->widget == NULL || ctl->enable == 0) 2843 continue; 2844 if (ctl->widget->nid == 11 && ctl->index == 0) { 2845 ctl->ossmask = SOUND_MASK_VOLUME; 2846 ctl->ossval = 100 | (100 << 8); 2847 } else 2848 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2849 } 2850 } else { 2851 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2852 SOUND_MASK_PCM); 2853 if (!(mask & SOUND_MASK_VOLUME)) 2854 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2855 SOUND_MIXER_NONE); 2856 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2857 NULL) { 2858 if (ctl->widget == NULL || ctl->enable == 0) 2859 continue; 2860 if (!HDA_FLAG_MATCH(ctl->ossmask, 2861 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2862 continue; 2863 if (!(ctl->mute == 1 && ctl->step == 0)) 2864 ctl->enable = 0; 2865 } 2866 } 2867 } 2868 2869 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2870 2871 mix_setrecdevs(m, recmask); 2872 mix_setdevs(m, mask); 2873 2874 hdac_unlock(sc); 2875 2876 return (0); 2877} 2878 2879static int 2880hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2881 unsigned left, unsigned right) 2882{ 2883 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2884 struct hdac_softc *sc = devinfo->codec->sc; 2885 struct hdac_widget *w; 2886 struct hdac_audio_ctl *ctl; 2887 uint32_t id, mute; 2888 int lvol, rvol, mlvol, mrvol; 2889 int i = 0; 2890 2891 hdac_lock(sc); 2892 if (dev == SOUND_MIXER_OGAIN) { 2893 uint32_t orig; 2894 /*if (left != right || !(left == 0 || left == 1)) { 2895 hdac_unlock(sc); 2896 return (-1); 2897 }*/ 2898 id = hdac_codec_id(devinfo); 2899 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2900 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2901 sc->pci_subvendor) && 2902 hdac_eapd_switch[i].id == id) 2903 break; 2904 } 2905 if (i >= HDAC_EAPD_SWITCH_LEN) { 2906 hdac_unlock(sc); 2907 return (-1); 2908 } 2909 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2910 if (w == NULL || 2911 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2912 w->param.eapdbtl == HDAC_INVALID) { 2913 hdac_unlock(sc); 2914 return (-1); 2915 } 2916 orig = w->param.eapdbtl; 2917 if (left == 0) 2918 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2919 else 2920 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2921 if (orig != w->param.eapdbtl) { 2922 uint32_t val; 2923 2924 if (hdac_eapd_switch[i].hp_switch != 0) 2925 hdac_hp_switch_handler(devinfo); 2926 val = w->param.eapdbtl; 2927 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2928 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2929 hdac_command(sc, 2930 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2931 w->nid, val), devinfo->codec->cad); 2932 } 2933 hdac_unlock(sc); 2934 return (left | (left << 8)); 2935 } 2936 if (dev == SOUND_MIXER_VOLUME) 2937 devinfo->function.audio.mvol = left | (right << 8); 2938 2939 mlvol = devinfo->function.audio.mvol & 0x7f; 2940 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2941 lvol = 0; 2942 rvol = 0; 2943 2944 i = 0; 2945 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2946 if (ctl->widget == NULL || ctl->enable == 0 || 2947 !(ctl->ossmask & (1 << dev))) 2948 continue; 2949 switch (dev) { 2950 case SOUND_MIXER_VOLUME: 2951 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2952 lvol = (lvol * ctl->step) / 100; 2953 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2954 rvol = (rvol * ctl->step) / 100; 2955 break; 2956 default: 2957 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2958 lvol = (left * mlvol) / 100; 2959 lvol = (lvol * ctl->step) / 100; 2960 rvol = (right * mrvol) / 100; 2961 rvol = (rvol * ctl->step) / 100; 2962 } else { 2963 lvol = (left * ctl->step) / 100; 2964 rvol = (right * ctl->step) / 100; 2965 } 2966 ctl->ossval = left | (right << 8); 2967 break; 2968 } 2969 mute = 0; 2970 if (ctl->step < 1) { 2971 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2972 (ctl->muted & HDA_AMP_MUTE_LEFT); 2973 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2974 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2975 } else { 2976 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2977 (ctl->muted & HDA_AMP_MUTE_LEFT); 2978 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2979 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2980 } 2981 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2982 } 2983 hdac_unlock(sc); 2984 2985 return (left | (right << 8)); 2986} 2987 2988static int 2989hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2990{ 2991 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2992 struct hdac_widget *w, *cw; 2993 struct hdac_softc *sc = devinfo->codec->sc; 2994 uint32_t ret = src, target; 2995 int i, j; 2996 2997 target = 0; 2998 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2999 if (src & (1 << i)) { 3000 target = 1 << i; 3001 break; 3002 } 3003 } 3004 3005 hdac_lock(sc); 3006 3007 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3008 w = hdac_widget_get(devinfo, i); 3009 if (w == NULL || w->enable == 0) 3010 continue; 3011 if (!(w->pflags & HDA_ADC_RECSEL)) 3012 continue; 3013 for (j = 0; j < w->nconns; j++) { 3014 cw = hdac_widget_get(devinfo, w->conns[j]); 3015 if (cw == NULL || cw->enable == 0) 3016 continue; 3017 if ((target == SOUND_MASK_VOLUME && 3018 cw->type != 3019 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3020 (target != SOUND_MASK_VOLUME && 3021 cw->type == 3022 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3023 continue; 3024 if (cw->ctlflags & target) { 3025 hdac_widget_connection_select(w, j); 3026 ret = target; 3027 j += w->nconns; 3028 } 3029 } 3030 } 3031 3032 hdac_unlock(sc); 3033 3034 return (ret); 3035} 3036 3037static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3038 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3039 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3040 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3041 { 0, 0 } 3042}; 3043MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3044 3045/**************************************************************************** 3046 * int hdac_attach(device_t) 3047 * 3048 * Attach the device into the kernel. Interrupts usually won't be enabled 3049 * when this function is called. Setup everything that doesn't require 3050 * interrupts and defer probing of codecs until interrupts are enabled. 3051 ****************************************************************************/ 3052static int 3053hdac_attach(device_t dev) 3054{ 3055 struct hdac_softc *sc; 3056 int result; 3057 int i = 0; 3058 3059 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3060 if (sc == NULL) { 3061 device_printf(dev, "cannot allocate softc\n"); 3062 return (ENOMEM); 3063 } 3064 3065 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3066 if (sc->lock == NULL) { 3067 device_printf(dev, "mutex creation failed\n"); 3068 free(sc, M_DEVBUF); 3069 return (ENOMEM); 3070 } 3071 3072 sc->dev = dev; 3073 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3074 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3075 3076 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3077 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3078 3079 sc->poll_ticks = 1; 3080 if (resource_int_value(device_get_name(sc->dev), 3081 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3082 sc->polling = 1; 3083 else 3084 sc->polling = 0; 3085 3086 sc->chan_size = pcm_getbuffersize(dev, 3087 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3088 3089 if (resource_int_value(device_get_name(sc->dev), 3090 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3091 i &= ~0x7f; 3092 if (i < 0x80) 3093 i = 0x80; 3094 sc->chan_blkcnt = sc->chan_size / i; 3095 i = 0; 3096 while (sc->chan_blkcnt >> i) 3097 i++; 3098 sc->chan_blkcnt = 1 << (i - 1); 3099 if (sc->chan_blkcnt < HDA_BDL_MIN) 3100 sc->chan_blkcnt = HDA_BDL_MIN; 3101 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3102 sc->chan_blkcnt = HDA_BDL_MAX; 3103 } else 3104 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3105 3106 result = bus_dma_tag_create(NULL, /* parent */ 3107 HDAC_DMA_ALIGNMENT, /* alignment */ 3108 0, /* boundary */ 3109 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3110 BUS_SPACE_MAXADDR, /* highaddr */ 3111 NULL, /* filtfunc */ 3112 NULL, /* fistfuncarg */ 3113 sc->chan_size, /* maxsize */ 3114 1, /* nsegments */ 3115 sc->chan_size, /* maxsegsz */ 3116 0, /* flags */ 3117 NULL, /* lockfunc */ 3118 NULL, /* lockfuncarg */ 3119 &sc->chan_dmat); /* dmat */ 3120 if (result != 0) { 3121 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3122 __func__, result); 3123 snd_mtxfree(sc->lock); 3124 free(sc, M_DEVBUF); 3125 return (ENXIO); 3126 } 3127 3128 3129 sc->hdabus = NULL; 3130 for (i = 0; i < HDAC_CODEC_MAX; i++) 3131 sc->codecs[i] = NULL; 3132 3133 pci_enable_busmaster(dev); 3134 3135 /* Allocate resources */ 3136 result = hdac_mem_alloc(sc); 3137 if (result != 0) 3138 goto hdac_attach_fail; 3139 result = hdac_irq_alloc(sc); 3140 if (result != 0) 3141 goto hdac_attach_fail; 3142 3143 /* Get Capabilities */ 3144 result = hdac_get_capabilities(sc); 3145 if (result != 0) 3146 goto hdac_attach_fail; 3147 3148 /* Allocate CORB and RIRB dma memory */ 3149 result = hdac_dma_alloc(sc, &sc->corb_dma, 3150 sc->corb_size * sizeof(uint32_t)); 3151 if (result != 0) 3152 goto hdac_attach_fail; 3153 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3154 sc->rirb_size * sizeof(struct hdac_rirb)); 3155 if (result != 0) 3156 goto hdac_attach_fail; 3157 3158 /* Quiesce everything */ 3159 hdac_reset(sc); 3160 3161 /* Disable PCI-Express QOS */ 3162 pci_write_config(sc->dev, 0x44, 3163 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3164 3165 /* Initialize the CORB and RIRB */ 3166 hdac_corb_init(sc); 3167 hdac_rirb_init(sc); 3168 3169 /* Defer remaining of initialization until interrupts are enabled */ 3170 sc->intrhook.ich_func = hdac_attach2; 3171 sc->intrhook.ich_arg = (void *)sc; 3172 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3173 sc->intrhook.ich_func = NULL; 3174 hdac_attach2((void *)sc); 3175 } 3176 3177 return (0); 3178 3179hdac_attach_fail: 3180 hdac_dma_free(&sc->rirb_dma); 3181 hdac_dma_free(&sc->corb_dma); 3182 hdac_irq_free(sc); 3183 hdac_mem_free(sc); 3184 snd_mtxfree(sc->lock); 3185 free(sc, M_DEVBUF); 3186 3187 return (ENXIO); 3188} 3189 3190static void 3191hdac_audio_parse(struct hdac_devinfo *devinfo) 3192{ 3193 struct hdac_softc *sc = devinfo->codec->sc; 3194 struct hdac_widget *w; 3195 uint32_t res; 3196 int i; 3197 nid_t cad, nid; 3198 3199 cad = devinfo->codec->cad; 3200 nid = devinfo->nid; 3201 3202 hdac_command(sc, 3203 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3204 3205 DELAY(100); 3206 3207 res = hdac_command(sc, 3208 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3209 3210 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3211 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3212 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3213 3214 HDA_BOOTVERBOSE( 3215 device_printf(sc->dev, " Vendor: 0x%08x\n", 3216 devinfo->vendor_id); 3217 device_printf(sc->dev, " Device: 0x%08x\n", 3218 devinfo->device_id); 3219 device_printf(sc->dev, " Revision: 0x%08x\n", 3220 devinfo->revision_id); 3221 device_printf(sc->dev, " Stepping: 0x%08x\n", 3222 devinfo->stepping_id); 3223 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3224 sc->pci_subvendor); 3225 device_printf(sc->dev, " Nodes: start=%d " 3226 "endnode=%d total=%d\n", 3227 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3228 ); 3229 3230 res = hdac_command(sc, 3231 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3232 cad); 3233 devinfo->function.audio.supp_stream_formats = res; 3234 3235 res = hdac_command(sc, 3236 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3237 cad); 3238 devinfo->function.audio.supp_pcm_size_rate = res; 3239 3240 res = hdac_command(sc, 3241 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3242 cad); 3243 devinfo->function.audio.outamp_cap = res; 3244 3245 res = hdac_command(sc, 3246 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3247 cad); 3248 devinfo->function.audio.inamp_cap = res; 3249 3250 if (devinfo->nodecnt > 0) { 3251 hdac_unlock(sc); 3252 devinfo->widget = (struct hdac_widget *)malloc( 3253 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3254 M_NOWAIT | M_ZERO); 3255 hdac_lock(sc); 3256 } else 3257 devinfo->widget = NULL; 3258 3259 if (devinfo->widget == NULL) { 3260 device_printf(sc->dev, "unable to allocate widgets!\n"); 3261 devinfo->endnode = devinfo->startnode; 3262 devinfo->nodecnt = 0; 3263 return; 3264 } 3265 3266 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3267 w = hdac_widget_get(devinfo, i); 3268 if (w == NULL) 3269 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3270 else { 3271 w->devinfo = devinfo; 3272 w->nid = i; 3273 w->enable = 1; 3274 w->selconn = -1; 3275 w->pflags = 0; 3276 w->ctlflags = 0; 3277 w->param.eapdbtl = HDAC_INVALID; 3278 hdac_widget_parse(w); 3279 } 3280 } 3281} 3282 3283static void 3284hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3285{ 3286 struct hdac_softc *sc = devinfo->codec->sc; 3287 struct hdac_audio_ctl *ctls; 3288 struct hdac_widget *w, *cw; 3289 int i, j, cnt, max, ocap, icap; 3290 int mute, offset, step, size; 3291 3292 /* XXX This is redundant */ 3293 max = 0; 3294 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3295 w = hdac_widget_get(devinfo, i); 3296 if (w == NULL || w->enable == 0) 3297 continue; 3298 if (w->param.outamp_cap != 0) 3299 max++; 3300 if (w->param.inamp_cap != 0) { 3301 switch (w->type) { 3302 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3303 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3304 for (j = 0; j < w->nconns; j++) { 3305 cw = hdac_widget_get(devinfo, 3306 w->conns[j]); 3307 if (cw == NULL || cw->enable == 0) 3308 continue; 3309 max++; 3310 } 3311 break; 3312 default: 3313 max++; 3314 break; 3315 } 3316 } 3317 } 3318 3319 devinfo->function.audio.ctlcnt = max; 3320 3321 if (max < 1) 3322 return; 3323 3324 hdac_unlock(sc); 3325 ctls = (struct hdac_audio_ctl *)malloc( 3326 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3327 hdac_lock(sc); 3328 3329 if (ctls == NULL) { 3330 /* Blekh! */ 3331 device_printf(sc->dev, "unable to allocate ctls!\n"); 3332 devinfo->function.audio.ctlcnt = 0; 3333 return; 3334 } 3335 3336 cnt = 0; 3337 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3338 if (cnt >= max) { 3339 device_printf(sc->dev, "%s: Ctl overflow!\n", 3340 __func__); 3341 break; 3342 } 3343 w = hdac_widget_get(devinfo, i); 3344 if (w == NULL || w->enable == 0) 3345 continue; 3346 ocap = w->param.outamp_cap; 3347 icap = w->param.inamp_cap; 3348 if (ocap != 0) { 3349 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3350 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3351 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3352 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3353 /*if (offset > step) { 3354 HDA_BOOTVERBOSE( 3355 device_printf(sc->dev, 3356 "HDA_DEBUG: BUGGY outamp: nid=%d " 3357 "[offset=%d > step=%d]\n", 3358 w->nid, offset, step); 3359 ); 3360 offset = step; 3361 }*/ 3362 ctls[cnt].enable = 1; 3363 ctls[cnt].widget = w; 3364 ctls[cnt].mute = mute; 3365 ctls[cnt].step = step; 3366 ctls[cnt].size = size; 3367 ctls[cnt].offset = offset; 3368 ctls[cnt].left = offset; 3369 ctls[cnt].right = offset; 3370 ctls[cnt++].dir = HDA_CTL_OUT; 3371 } 3372 3373 if (icap != 0) { 3374 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3375 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3376 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3377 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3378 /*if (offset > step) { 3379 HDA_BOOTVERBOSE( 3380 device_printf(sc->dev, 3381 "HDA_DEBUG: BUGGY inamp: nid=%d " 3382 "[offset=%d > step=%d]\n", 3383 w->nid, offset, step); 3384 ); 3385 offset = step; 3386 }*/ 3387 switch (w->type) { 3388 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3389 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3390 for (j = 0; j < w->nconns; j++) { 3391 if (cnt >= max) { 3392 device_printf(sc->dev, 3393 "%s: Ctl overflow!\n", 3394 __func__); 3395 break; 3396 } 3397 cw = hdac_widget_get(devinfo, 3398 w->conns[j]); 3399 if (cw == NULL || cw->enable == 0) 3400 continue; 3401 ctls[cnt].enable = 1; 3402 ctls[cnt].widget = w; 3403 ctls[cnt].childwidget = cw; 3404 ctls[cnt].index = j; 3405 ctls[cnt].mute = mute; 3406 ctls[cnt].step = step; 3407 ctls[cnt].size = size; 3408 ctls[cnt].offset = offset; 3409 ctls[cnt].left = offset; 3410 ctls[cnt].right = offset; 3411 ctls[cnt++].dir = HDA_CTL_IN; 3412 } 3413 break; 3414 default: 3415 if (cnt >= max) { 3416 device_printf(sc->dev, 3417 "%s: Ctl overflow!\n", 3418 __func__); 3419 break; 3420 } 3421 ctls[cnt].enable = 1; 3422 ctls[cnt].widget = w; 3423 ctls[cnt].mute = mute; 3424 ctls[cnt].step = step; 3425 ctls[cnt].size = size; 3426 ctls[cnt].offset = offset; 3427 ctls[cnt].left = offset; 3428 ctls[cnt].right = offset; 3429 ctls[cnt++].dir = HDA_CTL_IN; 3430 break; 3431 } 3432 } 3433 } 3434 3435 devinfo->function.audio.ctl = ctls; 3436} 3437 3438static const struct { 3439 uint32_t model; 3440 uint32_t id; 3441 uint32_t set, unset; 3442} hdac_quirks[] = { 3443 /* 3444 * XXX Force stereo quirk. Monoural recording / playback 3445 * on few codecs (especially ALC880) seems broken or 3446 * perhaps unsupported. 3447 */ 3448 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3449 HDA_QUIRK_FORCESTEREO, 0 }, 3450 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3451 HDA_QUIRK_GPIO1, 0 }, 3452 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3453 HDA_QUIRK_GPIO1, 0 }, 3454 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3455 HDA_QUIRK_GPIO2, 0 }, 3456 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3457 HDA_QUIRK_EAPDINV, 0 }, 3458 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3459 HDA_QUIRK_EAPDINV, 0 }, 3460 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3461 HDA_QUIRK_EAPDINV, 0 }, 3462 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3463 HDA_QUIRK_EAPDINV, 0 }, 3464 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3465 0, HDA_QUIRK_FORCESTEREO }, 3466 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3467 HDA_QUIRK_SOFTPCMVOL, 0 } 3468}; 3469#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3470 3471static void 3472hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3473{ 3474 struct hdac_widget *w; 3475 uint32_t id, subvendor; 3476 int i; 3477 3478 id = hdac_codec_id(devinfo); 3479 subvendor = devinfo->codec->sc->pci_subvendor; 3480 3481 /* 3482 * Quirks 3483 */ 3484 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3485 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3486 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3487 continue; 3488 if (hdac_quirks[i].set != 0) 3489 devinfo->function.audio.quirks |= 3490 hdac_quirks[i].set; 3491 if (hdac_quirks[i].unset != 0) 3492 devinfo->function.audio.quirks &= 3493 ~(hdac_quirks[i].unset); 3494 } 3495 3496 switch (id) { 3497 case HDA_CODEC_ALC260: 3498 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3499 w = hdac_widget_get(devinfo, i); 3500 if (w == NULL || w->enable == 0) 3501 continue; 3502 if (w->type != 3503 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3504 continue; 3505 if (w->nid != 5) 3506 w->enable = 0; 3507 } 3508 break; 3509 case HDA_CODEC_ALC880: 3510 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3511 w = hdac_widget_get(devinfo, i); 3512 if (w == NULL || w->enable == 0) 3513 continue; 3514 if (w->type == 3515 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3516 w->nid != 9 && w->nid != 29) { 3517 w->enable = 0; 3518 } else if (w->type != 3519 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3520 w->nid == 29) { 3521 w->type = 3522 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3523 w->param.widget_cap &= 3524 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3525 w->param.widget_cap |= 3526 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3527 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3528 strlcpy(w->name, "beep widget", sizeof(w->name)); 3529 } 3530 } 3531 break; 3532 case HDA_CODEC_AD1981HD: 3533 w = hdac_widget_get(devinfo, 11); 3534 if (w != NULL && w->enable != 0 && w->nconns > 3) 3535 w->selconn = 3; 3536 if (subvendor == IBM_M52_SUBVENDOR) { 3537 struct hdac_audio_ctl *ctl; 3538 3539 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3540 if (ctl != NULL) 3541 ctl->ossmask = SOUND_MASK_SPEAKER; 3542 } 3543 break; 3544 case HDA_CODEC_AD1986A: 3545 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3546 w = hdac_widget_get(devinfo, i); 3547 if (w == NULL || w->enable == 0) 3548 continue; 3549 if (w->type != 3550 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3551 continue; 3552 if (w->nid != 3) 3553 w->enable = 0; 3554 } 3555 break; 3556 case HDA_CODEC_STAC9221: 3557 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3558 w = hdac_widget_get(devinfo, i); 3559 if (w == NULL || w->enable == 0) 3560 continue; 3561 if (w->type != 3562 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3563 continue; 3564 if (w->nid != 2) 3565 w->enable = 0; 3566 } 3567 break; 3568 case HDA_CODEC_STAC9221D: 3569 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3570 w = hdac_widget_get(devinfo, i); 3571 if (w == NULL || w->enable == 0) 3572 continue; 3573 if (w->type == 3574 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3575 w->nid != 6) 3576 w->enable = 0; 3577 3578 } 3579 break; 3580 default: 3581 break; 3582 } 3583} 3584 3585static int 3586hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3587{ 3588 int *dev = &devinfo->function.audio.ossidx; 3589 3590 while (*dev < SOUND_MIXER_NRDEVICES) { 3591 switch (*dev) { 3592 case SOUND_MIXER_VOLUME: 3593 case SOUND_MIXER_BASS: 3594 case SOUND_MIXER_TREBLE: 3595 case SOUND_MIXER_PCM: 3596 case SOUND_MIXER_SPEAKER: 3597 case SOUND_MIXER_LINE: 3598 case SOUND_MIXER_MIC: 3599 case SOUND_MIXER_CD: 3600 case SOUND_MIXER_RECLEV: 3601 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3602 (*dev)++; 3603 break; 3604 default: 3605 return (*dev)++; 3606 break; 3607 } 3608 } 3609 3610 return (-1); 3611} 3612 3613static int 3614hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3615{ 3616 struct hdac_widget *w; 3617 int i, ret = 0; 3618 3619 if (depth > HDA_PARSE_MAXDEPTH) 3620 return (0); 3621 w = hdac_widget_get(devinfo, nid); 3622 if (w == NULL || w->enable == 0) 3623 return (0); 3624 switch (w->type) { 3625 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3626 w->pflags |= HDA_DAC_PATH; 3627 ret = 1; 3628 break; 3629 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3630 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3631 for (i = 0; i < w->nconns; i++) { 3632 if (hdac_widget_find_dac_path(devinfo, 3633 w->conns[i], depth + 1) != 0) { 3634 if (w->selconn == -1) 3635 w->selconn = i; 3636 ret = 1; 3637 w->pflags |= HDA_DAC_PATH; 3638 } 3639 } 3640 break; 3641 default: 3642 break; 3643 } 3644 return (ret); 3645} 3646 3647static int 3648hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3649{ 3650 struct hdac_widget *w; 3651 int i, conndev, ret = 0; 3652 3653 if (depth > HDA_PARSE_MAXDEPTH) 3654 return (0); 3655 w = hdac_widget_get(devinfo, nid); 3656 if (w == NULL || w->enable == 0) 3657 return (0); 3658 switch (w->type) { 3659 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3660 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3661 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3662 for (i = 0; i < w->nconns; i++) { 3663 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3664 depth + 1) != 0) { 3665 if (w->selconn == -1) 3666 w->selconn = i; 3667 w->pflags |= HDA_ADC_PATH; 3668 ret = 1; 3669 } 3670 } 3671 break; 3672 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3673 conndev = w->wclass.pin.config & 3674 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3675 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3676 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3677 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3678 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3679 w->pflags |= HDA_ADC_PATH; 3680 ret = 1; 3681 } 3682 break; 3683 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3684 if (w->pflags & HDA_DAC_PATH) { 3685 w->pflags |= HDA_ADC_PATH; 3686 ret = 1; 3687 } 3688 break;*/ 3689 default: 3690 break; 3691 } 3692 return (ret); 3693} 3694 3695static uint32_t 3696hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3697 nid_t nid, nid_t pnid, int index, int depth) 3698{ 3699 struct hdac_widget *w, *pw; 3700 struct hdac_audio_ctl *ctl; 3701 uint32_t fl = 0; 3702 int i, ossdev, conndev, strategy; 3703 3704 if (depth > HDA_PARSE_MAXDEPTH) 3705 return (0); 3706 3707 w = hdac_widget_get(devinfo, nid); 3708 if (w == NULL || w->enable == 0) 3709 return (0); 3710 3711 pw = hdac_widget_get(devinfo, pnid); 3712 strategy = devinfo->function.audio.parsing_strategy; 3713 3714 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3715 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3716 for (i = 0; i < w->nconns; i++) { 3717 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3718 w->nid, i, depth + 1); 3719 } 3720 w->ctlflags |= fl; 3721 return (fl); 3722 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3723 (w->pflags & HDA_DAC_PATH)) { 3724 i = 0; 3725 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3726 if (ctl->enable == 0 || ctl->widget == NULL) 3727 continue; 3728 /* XXX This should be compressed! */ 3729 if ((ctl->widget->nid == w->nid) || 3730 (ctl->widget->nid == pnid && ctl->index == index && 3731 (ctl->dir & HDA_CTL_IN)) || 3732 (ctl->widget->nid == pnid && pw != NULL && 3733 pw->type == 3734 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3735 (pw->nconns < 2 || pw->selconn == index || 3736 pw->selconn == -1) && 3737 (ctl->dir & HDA_CTL_OUT)) || 3738 (strategy == HDA_PARSE_DIRECT && 3739 ctl->widget->nid == w->nid)) { 3740 /*if (pw != NULL && pw->selconn == -1) 3741 pw->selconn = index; 3742 fl |= SOUND_MASK_VOLUME; 3743 fl |= SOUND_MASK_PCM; 3744 ctl->ossmask |= SOUND_MASK_VOLUME; 3745 ctl->ossmask |= SOUND_MASK_PCM; 3746 ctl->ossdev = SOUND_MIXER_PCM;*/ 3747 if (!(w->ctlflags & SOUND_MASK_PCM) || 3748 (pw != NULL && 3749 !(pw->ctlflags & SOUND_MASK_PCM))) { 3750 fl |= SOUND_MASK_VOLUME; 3751 fl |= SOUND_MASK_PCM; 3752 ctl->ossmask |= SOUND_MASK_VOLUME; 3753 ctl->ossmask |= SOUND_MASK_PCM; 3754 ctl->ossdev = SOUND_MIXER_PCM; 3755 w->ctlflags |= SOUND_MASK_VOLUME; 3756 w->ctlflags |= SOUND_MASK_PCM; 3757 if (pw != NULL) { 3758 if (pw->selconn == -1) 3759 pw->selconn = index; 3760 pw->ctlflags |= 3761 SOUND_MASK_VOLUME; 3762 pw->ctlflags |= 3763 SOUND_MASK_PCM; 3764 } 3765 } 3766 } 3767 } 3768 w->ctlflags |= fl; 3769 return (fl); 3770 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3771 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3772 (w->pflags & HDA_ADC_PATH)) { 3773 conndev = w->wclass.pin.config & 3774 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3775 i = 0; 3776 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3777 if (ctl->enable == 0 || ctl->widget == NULL) 3778 continue; 3779 /* XXX This should be compressed! */ 3780 if (((ctl->widget->nid == pnid && ctl->index == index && 3781 (ctl->dir & HDA_CTL_IN)) || 3782 (ctl->widget->nid == pnid && pw != NULL && 3783 pw->type == 3784 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3785 (pw->nconns < 2 || pw->selconn == index || 3786 pw->selconn == -1) && 3787 (ctl->dir & HDA_CTL_OUT)) || 3788 (strategy == HDA_PARSE_DIRECT && 3789 ctl->widget->nid == w->nid)) && 3790 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3791 if (pw != NULL && pw->selconn == -1) 3792 pw->selconn = index; 3793 ossdev = 0; 3794 switch (conndev) { 3795 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3796 ossdev = SOUND_MIXER_MIC; 3797 break; 3798 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3799 ossdev = SOUND_MIXER_LINE; 3800 break; 3801 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3802 ossdev = SOUND_MIXER_CD; 3803 break; 3804 default: 3805 ossdev = 3806 hdac_audio_ctl_ossmixer_getnextdev( 3807 devinfo); 3808 if (ossdev < 0) 3809 ossdev = 0; 3810 break; 3811 } 3812 if (strategy == HDA_PARSE_MIXER) { 3813 fl |= SOUND_MASK_VOLUME; 3814 ctl->ossmask |= SOUND_MASK_VOLUME; 3815 } 3816 fl |= 1 << ossdev; 3817 ctl->ossmask |= 1 << ossdev; 3818 ctl->ossdev = ossdev; 3819 } 3820 } 3821 w->ctlflags |= fl; 3822 return (fl); 3823 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3824 i = 0; 3825 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3826 if (ctl->enable == 0 || ctl->widget == NULL) 3827 continue; 3828 /* XXX This should be compressed! */ 3829 if (((ctl->widget->nid == pnid && ctl->index == index && 3830 (ctl->dir & HDA_CTL_IN)) || 3831 (ctl->widget->nid == pnid && pw != NULL && 3832 pw->type == 3833 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3834 (pw->nconns < 2 || pw->selconn == index || 3835 pw->selconn == -1) && 3836 (ctl->dir & HDA_CTL_OUT)) || 3837 (strategy == HDA_PARSE_DIRECT && 3838 ctl->widget->nid == w->nid)) && 3839 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3840 if (pw != NULL && pw->selconn == -1) 3841 pw->selconn = index; 3842 fl |= SOUND_MASK_VOLUME; 3843 fl |= SOUND_MASK_SPEAKER; 3844 ctl->ossmask |= SOUND_MASK_VOLUME; 3845 ctl->ossmask |= SOUND_MASK_SPEAKER; 3846 ctl->ossdev = SOUND_MIXER_SPEAKER; 3847 } 3848 } 3849 w->ctlflags |= fl; 3850 return (fl); 3851 } 3852 return (0); 3853} 3854 3855static uint32_t 3856hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3857{ 3858 struct hdac_widget *w, *cw; 3859 struct hdac_audio_ctl *ctl; 3860 uint32_t fl; 3861 int i; 3862 3863 if (depth > HDA_PARSE_MAXDEPTH) 3864 return (0); 3865 3866 w = hdac_widget_get(devinfo, nid); 3867 if (w == NULL || w->enable == 0) 3868 return (0); 3869 /*if (!(w->pflags & HDA_ADC_PATH)) 3870 return (0); 3871 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3872 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3873 return (0);*/ 3874 i = 0; 3875 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3876 if (ctl->enable == 0 || ctl->widget == NULL) 3877 continue; 3878 if (ctl->widget->nid == nid) { 3879 ctl->ossmask |= SOUND_MASK_RECLEV; 3880 w->ctlflags |= SOUND_MASK_RECLEV; 3881 return (SOUND_MASK_RECLEV); 3882 } 3883 } 3884 for (i = 0; i < w->nconns; i++) { 3885 cw = hdac_widget_get(devinfo, w->conns[i]); 3886 if (cw == NULL || cw->enable == 0) 3887 continue; 3888 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3889 continue; 3890 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3891 if (fl != 0) { 3892 cw->ctlflags |= fl; 3893 w->ctlflags |= fl; 3894 return (fl); 3895 } 3896 } 3897 return (0); 3898} 3899 3900static int 3901hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3902{ 3903 struct hdac_widget *w, *cw; 3904 int i, child = 0; 3905 3906 if (depth > HDA_PARSE_MAXDEPTH) 3907 return (0); 3908 3909 w = hdac_widget_get(devinfo, nid); 3910 if (w == NULL || w->enable == 0) 3911 return (0); 3912 /*if (!(w->pflags & HDA_ADC_PATH)) 3913 return (0); 3914 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3915 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3916 return (0);*/ 3917 /* XXX weak! */ 3918 for (i = 0; i < w->nconns; i++) { 3919 cw = hdac_widget_get(devinfo, w->conns[i]); 3920 if (cw == NULL) 3921 continue; 3922 if (++child > 1) { 3923 w->pflags |= HDA_ADC_RECSEL; 3924 return (1); 3925 } 3926 } 3927 for (i = 0; i < w->nconns; i++) { 3928 if (hdac_audio_ctl_recsel_build(devinfo, 3929 w->conns[i], depth + 1) != 0) 3930 return (1); 3931 } 3932 return (0); 3933} 3934 3935static int 3936hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3937{ 3938 struct hdac_widget *w, *cw; 3939 int i, j, conndev, found_dac = 0; 3940 int strategy; 3941 3942 strategy = devinfo->function.audio.parsing_strategy; 3943 3944 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3945 w = hdac_widget_get(devinfo, i); 3946 if (w == NULL || w->enable == 0) 3947 continue; 3948 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3949 continue; 3950 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3951 continue; 3952 conndev = w->wclass.pin.config & 3953 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3954 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3955 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3956 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3957 continue; 3958 for (j = 0; j < w->nconns; j++) { 3959 cw = hdac_widget_get(devinfo, w->conns[j]); 3960 if (cw == NULL || cw->enable == 0) 3961 continue; 3962 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3963 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3964 cw->type == 3965 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3966 continue; 3967 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3968 != 0) { 3969 if (w->selconn == -1) 3970 w->selconn = j; 3971 w->pflags |= HDA_DAC_PATH; 3972 found_dac++; 3973 } 3974 } 3975 } 3976 3977 return (found_dac); 3978} 3979 3980static void 3981hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3982{ 3983 struct hdac_widget *w; 3984 struct hdac_audio_ctl *ctl; 3985 int i, j, dacs, strategy; 3986 3987 /* Construct DAC path */ 3988 strategy = HDA_PARSE_MIXER; 3989 devinfo->function.audio.parsing_strategy = strategy; 3990 HDA_BOOTVERBOSE( 3991 device_printf(devinfo->codec->sc->dev, 3992 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 3993 HDA_WIDGET_PARSER_REV); 3994 ); 3995 dacs = hdac_audio_build_tree_strategy(devinfo); 3996 if (dacs == 0) { 3997 HDA_BOOTVERBOSE( 3998 device_printf(devinfo->codec->sc->dev, 3999 "HDA_DEBUG: HWiP: 0 DAC path found! " 4000 "Retrying parser " 4001 "using HDA_PARSE_DIRECT strategy.\n"); 4002 ); 4003 strategy = HDA_PARSE_DIRECT; 4004 devinfo->function.audio.parsing_strategy = strategy; 4005 dacs = hdac_audio_build_tree_strategy(devinfo); 4006 } 4007 4008 HDA_BOOTVERBOSE( 4009 device_printf(devinfo->codec->sc->dev, 4010 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4011 "strategy.\n", 4012 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4013 ); 4014 4015 /* Construct ADC path */ 4016 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4017 w = hdac_widget_get(devinfo, i); 4018 if (w == NULL || w->enable == 0) 4019 continue; 4020 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4021 continue; 4022 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4023 } 4024 4025 /* Output mixers */ 4026 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4027 w = hdac_widget_get(devinfo, i); 4028 if (w == NULL || w->enable == 0) 4029 continue; 4030 if ((strategy == HDA_PARSE_MIXER && 4031 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4032 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4033 && (w->pflags & HDA_DAC_PATH)) || 4034 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4035 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4036 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4037 w->nid, devinfo->startnode - 1, 0, 0); 4038 } else if (w->type == 4039 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4040 j = 0; 4041 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4042 NULL) { 4043 if (ctl->enable == 0 || ctl->widget == NULL) 4044 continue; 4045 if (ctl->widget->nid != w->nid) 4046 continue; 4047 ctl->ossmask |= SOUND_MASK_VOLUME; 4048 ctl->ossmask |= SOUND_MASK_SPEAKER; 4049 ctl->ossdev = SOUND_MIXER_SPEAKER; 4050 w->ctlflags |= SOUND_MASK_VOLUME; 4051 w->ctlflags |= SOUND_MASK_SPEAKER; 4052 } 4053 } 4054 } 4055 4056 /* Input mixers (rec) */ 4057 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4058 w = hdac_widget_get(devinfo, i); 4059 if (w == NULL || w->enable == 0) 4060 continue; 4061 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4062 w->pflags & HDA_ADC_PATH)) 4063 continue; 4064 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4065 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4066 } 4067} 4068 4069#define HDA_COMMIT_CONN (1 << 0) 4070#define HDA_COMMIT_CTRL (1 << 1) 4071#define HDA_COMMIT_EAPD (1 << 2) 4072#define HDA_COMMIT_GPIO (1 << 3) 4073#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4074 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4075 4076static void 4077hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4078{ 4079 struct hdac_softc *sc = devinfo->codec->sc; 4080 struct hdac_widget *w; 4081 nid_t cad; 4082 int i; 4083 4084 if (!(cfl & HDA_COMMIT_ALL)) 4085 return; 4086 4087 cad = devinfo->codec->cad; 4088 4089 if (cfl & HDA_COMMIT_GPIO) { 4090 for (i = 0; i < HDA_GPIO_MAX; i++) { 4091 if (!(devinfo->function.audio.quirks & (1 << i))) 4092 continue; 4093 hdac_command(sc, 4094 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, i), 4095 cad); 4096 hdac_command(sc, 4097 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, i), 4098 cad); 4099 hdac_command(sc, 4100 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, i), 4101 cad); 4102 } 4103 } 4104 4105 for (i = 0; i < devinfo->nodecnt; i++) { 4106 w = &devinfo->widget[i]; 4107 if (w == NULL || w->enable == 0) 4108 continue; 4109 if (cfl & HDA_COMMIT_CONN) { 4110 if (w->selconn == -1) 4111 w->selconn = 0; 4112 if (w->nconns > 0) 4113 hdac_widget_connection_select(w, w->selconn); 4114 } 4115 if ((cfl & HDA_COMMIT_CTRL) && 4116 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4117 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4118 (HDA_DAC_PATH | HDA_ADC_PATH)) 4119 device_printf(sc->dev, "WARNING: node %d " 4120 "participate both for DAC/ADC!\n", w->nid); 4121 if (w->pflags & HDA_DAC_PATH) { 4122 w->wclass.pin.ctrl &= 4123 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4124 if ((w->wclass.pin.config & 4125 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4126 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4127 w->wclass.pin.ctrl &= 4128 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4129 } else if (w->pflags & HDA_ADC_PATH) { 4130 w->wclass.pin.ctrl &= 4131 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4132 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4133 } else 4134 w->wclass.pin.ctrl &= ~( 4135 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4136 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4137 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 4138 hdac_command(sc, 4139 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4140 w->wclass.pin.ctrl), cad); 4141 } 4142 if ((cfl & HDA_COMMIT_EAPD) && 4143 w->param.eapdbtl != HDAC_INVALID) { 4144 uint32_t val; 4145 4146 val = w->param.eapdbtl; 4147 if (devinfo->function.audio.quirks & 4148 HDA_QUIRK_EAPDINV) 4149 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4150 hdac_command(sc, 4151 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4152 val), cad); 4153 4154 } 4155 DELAY(1000); 4156 } 4157} 4158 4159static void 4160hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4161{ 4162 struct hdac_softc *sc = devinfo->codec->sc; 4163 struct hdac_audio_ctl *ctl; 4164 int i; 4165 4166 devinfo->function.audio.mvol = 100 | (100 << 8); 4167 i = 0; 4168 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4169 if (ctl->enable == 0 || ctl->widget == NULL) { 4170 HDA_BOOTVERBOSE( 4171 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4172 i, (ctl->widget != NULL) ? 4173 ctl->widget->nid : -1); 4174 if (ctl->childwidget != NULL) 4175 printf(" childnid=%d", 4176 ctl->childwidget->nid); 4177 if (ctl->widget == NULL) 4178 printf(" NULL WIDGET!"); 4179 printf(" DISABLED\n"); 4180 ); 4181 continue; 4182 } 4183 HDA_BOOTVERBOSE( 4184 if (ctl->ossmask == 0) { 4185 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4186 i, ctl->widget->nid); 4187 if (ctl->childwidget != NULL) 4188 printf(" childnid=%d", 4189 ctl->childwidget->nid); 4190 printf(" Bind to NONE\n"); 4191 } 4192 ); 4193 if (ctl->step > 0) { 4194 ctl->ossval = (ctl->left * 100) / ctl->step; 4195 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4196 } else 4197 ctl->ossval = 0; 4198 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4199 ctl->left, ctl->right); 4200 } 4201} 4202 4203static int 4204hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4205{ 4206 struct hdac_chan *ch; 4207 struct hdac_widget *w; 4208 uint32_t cap, fmtcap, pcmcap, path; 4209 int i, type, ret, max; 4210 4211 if (dir == PCMDIR_PLAY) { 4212 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4213 ch = &devinfo->codec->sc->play; 4214 path = HDA_DAC_PATH; 4215 } else { 4216 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4217 ch = &devinfo->codec->sc->rec; 4218 path = HDA_ADC_PATH; 4219 } 4220 4221 ch->caps = hdac_caps; 4222 ch->caps.fmtlist = ch->fmtlist; 4223 ch->bit16 = 1; 4224 ch->bit32 = 0; 4225 ch->pcmrates[0] = 48000; 4226 ch->pcmrates[1] = 0; 4227 4228 ret = 0; 4229 fmtcap = devinfo->function.audio.supp_stream_formats; 4230 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4231 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4232 4233 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4234 w = hdac_widget_get(devinfo, i); 4235 if (w == NULL || w->enable == 0 || w->type != type || 4236 !(w->pflags & path)) 4237 continue; 4238 cap = w->param.widget_cap; 4239 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4240 continue;*/ 4241 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4242 continue; 4243 cap = w->param.supp_stream_formats; 4244 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4245 } 4246 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4247 }*/ 4248 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4249 continue; 4250 if (ret == 0) { 4251 fmtcap = w->param.supp_stream_formats; 4252 pcmcap = w->param.supp_pcm_size_rate; 4253 } else { 4254 fmtcap &= w->param.supp_stream_formats; 4255 pcmcap &= w->param.supp_pcm_size_rate; 4256 } 4257 ch->io[ret++] = i; 4258 } 4259 ch->io[ret] = -1; 4260 4261 ch->supp_stream_formats = fmtcap; 4262 ch->supp_pcm_size_rate = pcmcap; 4263 4264 /* 4265 * 8bit = 0 4266 * 16bit = 1 4267 * 20bit = 2 4268 * 24bit = 3 4269 * 32bit = 4 4270 */ 4271 if (ret > 0) { 4272 cap = pcmcap; 4273 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4274 ch->bit16 = 1; 4275 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4276 ch->bit16 = 0; 4277 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4278 ch->bit32 = 4; 4279 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4280 ch->bit32 = 3; 4281 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4282 ch->bit32 = 2; 4283 i = 0; 4284 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4285 ch->fmtlist[i++] = AFMT_S16_LE; 4286 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4287 if (ch->bit32 > 0) { 4288 if (!(devinfo->function.audio.quirks & 4289 HDA_QUIRK_FORCESTEREO)) 4290 ch->fmtlist[i++] = AFMT_S32_LE; 4291 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4292 } 4293 ch->fmtlist[i] = 0; 4294 i = 0; 4295 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4296 ch->pcmrates[i++] = 8000; 4297 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4298 ch->pcmrates[i++] = 11025; 4299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4300 ch->pcmrates[i++] = 16000; 4301 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4302 ch->pcmrates[i++] = 22050; 4303 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4304 ch->pcmrates[i++] = 32000; 4305 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4306 ch->pcmrates[i++] = 44100; 4307 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4308 ch->pcmrates[i++] = 48000; 4309 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4310 ch->pcmrates[i++] = 88200; 4311 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4312 ch->pcmrates[i++] = 96000; 4313 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4314 ch->pcmrates[i++] = 176400; 4315 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4316 ch->pcmrates[i++] = 192000; 4317 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4318 ch->pcmrates[i] = 0; 4319 if (i > 0) { 4320 ch->caps.minspeed = ch->pcmrates[0]; 4321 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4322 } 4323 } 4324 4325 return (ret); 4326} 4327 4328static void 4329hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4330{ 4331 struct hdac_audio_ctl *ctl; 4332 struct hdac_softc *sc = devinfo->codec->sc; 4333 int i; 4334 uint32_t fl = 0; 4335 4336 4337 if (flag == 0) { 4338 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4339 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4340 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4341 } 4342 4343 i = 0; 4344 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4345 if (ctl->enable == 0 || ctl->widget == NULL || 4346 ctl->widget->enable == 0) 4347 continue; 4348 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4349 (flag != 0 && (ctl->ossmask & flag))) { 4350 if (banner != NULL) { 4351 device_printf(sc->dev, "\n"); 4352 device_printf(sc->dev, "%s\n", banner); 4353 } 4354 goto hdac_ctl_dump_it_all; 4355 } 4356 } 4357 4358 return; 4359 4360hdac_ctl_dump_it_all: 4361 i = 0; 4362 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4363 if (ctl->enable == 0 || ctl->widget == NULL || 4364 ctl->widget->enable == 0) 4365 continue; 4366 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4367 (flag != 0 && (ctl->ossmask & flag)))) 4368 continue; 4369 if (flag == 0) { 4370 device_printf(sc->dev, "\n"); 4371 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4372 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4373 } 4374 device_printf(sc->dev, " |\n"); 4375 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4376 ctl->widget->nid, ctl->index); 4377 if (ctl->childwidget != NULL) 4378 printf("(nid: %2d) ", ctl->childwidget->nid); 4379 else 4380 printf(" "); 4381 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4382 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4383 ctl->ossmask); 4384 } 4385} 4386 4387static void 4388hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4389{ 4390 uint32_t cap; 4391 4392 cap = fcap; 4393 if (cap != 0) { 4394 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4395 device_printf(sc->dev, " Format:"); 4396 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4397 printf(" AC3"); 4398 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4399 printf(" FLOAT32"); 4400 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4401 printf(" PCM"); 4402 printf("\n"); 4403 } 4404 cap = pcmcap; 4405 if (cap != 0) { 4406 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4407 device_printf(sc->dev, " PCM size:"); 4408 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4409 printf(" 8"); 4410 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4411 printf(" 16"); 4412 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4413 printf(" 20"); 4414 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4415 printf(" 24"); 4416 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4417 printf(" 32"); 4418 printf("\n"); 4419 device_printf(sc->dev, " PCM rate:"); 4420 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4421 printf(" 8"); 4422 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4423 printf(" 11"); 4424 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4425 printf(" 16"); 4426 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4427 printf(" 22"); 4428 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4429 printf(" 32"); 4430 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4431 printf(" 44"); 4432 printf(" 48"); 4433 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4434 printf(" 88"); 4435 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4436 printf(" 96"); 4437 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4438 printf(" 176"); 4439 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4440 printf(" 192"); 4441 printf("\n"); 4442 } 4443} 4444 4445static void 4446hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4447{ 4448 uint32_t pincap, wcap; 4449 4450 pincap = w->wclass.pin.cap; 4451 wcap = w->param.widget_cap; 4452 4453 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4454 device_printf(sc->dev, " "); 4455 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4456 printf(" ISC"); 4457 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4458 printf(" TRQD"); 4459 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4460 printf(" PDC"); 4461 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4462 printf(" HP"); 4463 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4464 printf(" OUT"); 4465 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4466 printf(" IN"); 4467 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4468 printf(" BAL"); 4469 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4470 printf(" EAPD"); 4471 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4472 printf(" : UNSOL"); 4473 printf("\n"); 4474 device_printf(sc->dev, " Pin config: 0x%08x\n", 4475 w->wclass.pin.config); 4476 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4477 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4478 printf(" HP"); 4479 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4480 printf(" IN"); 4481 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4482 printf(" OUT"); 4483 printf("\n"); 4484} 4485 4486static void 4487hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4488{ 4489 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4490 device_printf(sc->dev, " " 4491 "mute=%d step=%d size=%d offset=%d\n", 4492 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4493 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4494 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4495 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4496} 4497 4498static void 4499hdac_dump_nodes(struct hdac_devinfo *devinfo) 4500{ 4501 struct hdac_softc *sc = devinfo->codec->sc; 4502 struct hdac_widget *w, *cw; 4503 int i, j; 4504 4505 device_printf(sc->dev, "\n"); 4506 device_printf(sc->dev, "Default Parameter\n"); 4507 device_printf(sc->dev, "-----------------\n"); 4508 hdac_dump_audio_formats(sc, 4509 devinfo->function.audio.supp_stream_formats, 4510 devinfo->function.audio.supp_pcm_size_rate); 4511 device_printf(sc->dev, " IN amp: 0x%08x\n", 4512 devinfo->function.audio.inamp_cap); 4513 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4514 devinfo->function.audio.outamp_cap); 4515 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4516 w = hdac_widget_get(devinfo, i); 4517 if (w == NULL) { 4518 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4519 continue; 4520 } 4521 device_printf(sc->dev, "\n"); 4522 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4523 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4524 "DIGITAL" : "ANALOG", 4525 (w->enable == 0) ? " [DISABLED]" : ""); 4526 device_printf(sc->dev, " name: %s\n", w->name); 4527 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4528 w->param.widget_cap); 4529 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4530 w->pflags); 4531 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4532 w->ctlflags); 4533 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4534 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4535 hdac_dump_audio_formats(sc, 4536 w->param.supp_stream_formats, 4537 w->param.supp_pcm_size_rate); 4538 } else if (w->type == 4539 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4540 hdac_dump_pin(sc, w); 4541 if (w->param.eapdbtl != HDAC_INVALID) 4542 device_printf(sc->dev, " EAPD: 0x%08x\n", 4543 w->param.eapdbtl); 4544 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4545 w->param.outamp_cap != 0) 4546 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4547 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4548 w->param.inamp_cap != 0) 4549 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4550 device_printf(sc->dev, " connections: %d\n", w->nconns); 4551 for (j = 0; j < w->nconns; j++) { 4552 cw = hdac_widget_get(devinfo, w->conns[j]); 4553 device_printf(sc->dev, " |\n"); 4554 device_printf(sc->dev, " + <- nid=%d [%s]", 4555 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4556 if (cw == NULL) 4557 printf(" [UNKNOWN]"); 4558 else if (cw->enable == 0) 4559 printf(" [DISABLED]"); 4560 if (w->nconns > 1 && w->selconn == j && w->type != 4561 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4562 printf(" (selected)"); 4563 printf("\n"); 4564 } 4565 } 4566 4567} 4568 4569static int 4570hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4571{ 4572 struct hdac_widget *w, *cw; 4573 struct hdac_softc *sc = devinfo->codec->sc; 4574 int i; 4575 4576 if (depth > HDA_PARSE_MAXDEPTH) 4577 return (0); 4578 4579 w = hdac_widget_get(devinfo, nid); 4580 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4581 return (0); 4582 4583 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4584 device_printf(sc->dev, "\n"); 4585 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4586 device_printf(sc->dev, " ^\n"); 4587 device_printf(sc->dev, " |\n"); 4588 device_printf(sc->dev, " +-----<------+\n"); 4589 } else { 4590 device_printf(sc->dev, " ^\n"); 4591 device_printf(sc->dev, " |\n"); 4592 device_printf(sc->dev, " "); 4593 printf(" nid=%d [%s]\n", w->nid, w->name); 4594 } 4595 4596 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4597 return (1); 4598 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4599 for (i = 0; i < w->nconns; i++) { 4600 cw = hdac_widget_get(devinfo, w->conns[i]); 4601 if (cw == NULL || cw->enable == 0 || cw->type == 4602 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4603 continue; 4604 if (hdac_dump_dac_internal(devinfo, cw->nid, 4605 depth + 1) != 0) 4606 return (1); 4607 } 4608 } else if ((w->type == 4609 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4610 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4611 w->selconn > -1 && w->selconn < w->nconns) { 4612 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4613 depth + 1) != 0) 4614 return (1); 4615 } 4616 4617 return (0); 4618} 4619 4620static void 4621hdac_dump_dac(struct hdac_devinfo *devinfo) 4622{ 4623 struct hdac_widget *w; 4624 struct hdac_softc *sc = devinfo->codec->sc; 4625 int i, printed = 0; 4626 4627 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4628 w = hdac_widget_get(devinfo, i); 4629 if (w == NULL || w->enable == 0) 4630 continue; 4631 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4632 !(w->pflags & HDA_DAC_PATH)) 4633 continue; 4634 if (printed == 0) { 4635 printed = 1; 4636 device_printf(sc->dev, "\n"); 4637 device_printf(sc->dev, "Playback path:\n"); 4638 } 4639 hdac_dump_dac_internal(devinfo, w->nid, 0); 4640 } 4641} 4642 4643static void 4644hdac_dump_adc(struct hdac_devinfo *devinfo) 4645{ 4646 struct hdac_widget *w, *cw; 4647 struct hdac_softc *sc = devinfo->codec->sc; 4648 int i, j; 4649 int printed = 0; 4650 char ossdevs[256]; 4651 4652 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4653 w = hdac_widget_get(devinfo, i); 4654 if (w == NULL || w->enable == 0) 4655 continue; 4656 if (!(w->pflags & HDA_ADC_RECSEL)) 4657 continue; 4658 if (printed == 0) { 4659 printed = 1; 4660 device_printf(sc->dev, "\n"); 4661 device_printf(sc->dev, "Recording sources:\n"); 4662 } 4663 device_printf(sc->dev, "\n"); 4664 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4665 for (j = 0; j < w->nconns; j++) { 4666 cw = hdac_widget_get(devinfo, w->conns[j]); 4667 if (cw == NULL || cw->enable == 0) 4668 continue; 4669 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4670 ossdevs, sizeof(ossdevs)); 4671 device_printf(sc->dev, " |\n"); 4672 device_printf(sc->dev, " + <- nid=%d [%s]", 4673 cw->nid, cw->name); 4674 if (strlen(ossdevs) > 0) { 4675 printf(" [recsrc: %s]", ossdevs); 4676 } 4677 printf("\n"); 4678 } 4679 } 4680} 4681 4682static void 4683hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4684{ 4685 nid_t *nids; 4686 4687 if (pcnt > 0) { 4688 device_printf(sc->dev, "\n"); 4689 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4690 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4691 sc->play.supp_pcm_size_rate); 4692 device_printf(sc->dev, " DAC:"); 4693 for (nids = sc->play.io; *nids != -1; nids++) 4694 printf(" %d", *nids); 4695 printf("\n"); 4696 } 4697 4698 if (rcnt > 0) { 4699 device_printf(sc->dev, "\n"); 4700 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4701 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4702 sc->rec.supp_pcm_size_rate); 4703 device_printf(sc->dev, " ADC:"); 4704 for (nids = sc->rec.io; *nids != -1; nids++) 4705 printf(" %d", *nids); 4706 printf("\n"); 4707 } 4708} 4709 4710static void 4711hdac_release_resources(struct hdac_softc *sc) 4712{ 4713 struct hdac_devinfo *devinfo = NULL; 4714 device_t *devlist = NULL; 4715 int i, devcount; 4716 4717 if (sc == NULL) 4718 return; 4719 4720 hdac_lock(sc); 4721 if (sc->polling != 0) 4722 callout_stop(&sc->poll_hdac); 4723 hdac_reset(sc); 4724 hdac_unlock(sc); 4725 snd_mtxfree(sc->lock); 4726 4727 device_get_children(sc->dev, &devlist, &devcount); 4728 for (i = 0; devlist != NULL && i < devcount; i++) { 4729 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4730 if (devinfo == NULL) 4731 continue; 4732 if (devinfo->widget != NULL) 4733 free(devinfo->widget, M_HDAC); 4734 if (devinfo->node_type == 4735 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4736 devinfo->function.audio.ctl != NULL) 4737 free(devinfo->function.audio.ctl, M_HDAC); 4738 free(devinfo, M_HDAC); 4739 device_delete_child(sc->dev, devlist[i]); 4740 } 4741 if (devlist != NULL) 4742 free(devlist, M_TEMP); 4743 4744 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4745 if (sc->codecs[i] != NULL) 4746 free(sc->codecs[i], M_HDAC); 4747 sc->codecs[i] = NULL; 4748 } 4749 4750 hdac_dma_free(&sc->rirb_dma); 4751 hdac_dma_free(&sc->corb_dma); 4752 if (sc->play.blkcnt > 0) 4753 hdac_dma_free(&sc->play.bdl_dma); 4754 if (sc->rec.blkcnt > 0) 4755 hdac_dma_free(&sc->rec.bdl_dma); 4756 hdac_irq_free(sc); 4757 hdac_mem_free(sc); 4758 free(sc, M_DEVBUF); 4759 4760} 4761 4762/* This function surely going to make its way into upper level someday. */ 4763static void 4764hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4765{ 4766 const char *res = NULL; 4767 int i = 0, j, k, len, inv; 4768 4769 if (on != NULL) 4770 *on = 0; 4771 if (off != NULL) 4772 *off = 0; 4773 if (sc == NULL) 4774 return; 4775 if (resource_string_value(device_get_name(sc->dev), 4776 device_get_unit(sc->dev), "config", &res) != 0) 4777 return; 4778 if (!(res != NULL && strlen(res) > 0)) 4779 return; 4780 HDA_BOOTVERBOSE( 4781 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4782 ); 4783 for (;;) { 4784 while (res[i] != '\0' && 4785 (res[i] == ',' || isspace(res[i]) != 0)) 4786 i++; 4787 if (res[i] == '\0') { 4788 HDA_BOOTVERBOSE( 4789 printf("\n"); 4790 ); 4791 return; 4792 } 4793 j = i; 4794 while (res[j] != '\0' && 4795 !(res[j] == ',' || isspace(res[j]) != 0)) 4796 j++; 4797 len = j - i; 4798 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4799 inv = 2; 4800 else 4801 inv = 0; 4802 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4803 if (strncmp(res + i + inv, 4804 hdac_quirks_tab[k].key, len - inv) != 0) 4805 continue; 4806 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4807 break; 4808 HDA_BOOTVERBOSE( 4809 printf(" %s%s", (inv != 0) ? "no" : "", 4810 hdac_quirks_tab[k].key); 4811 ); 4812 if (inv == 0 && on != NULL) 4813 *on |= hdac_quirks_tab[k].value; 4814 else if (inv != 0 && off != NULL) 4815 *off |= hdac_quirks_tab[k].value; 4816 break; 4817 } 4818 i = j; 4819 } 4820} 4821 4822#ifdef SND_DYNSYSCTL 4823static int 4824sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4825{ 4826 struct hdac_softc *sc; 4827 struct hdac_devinfo *devinfo; 4828 device_t dev; 4829 uint32_t ctl; 4830 int err, val; 4831 4832 dev = oidp->oid_arg1; 4833 devinfo = pcm_getdevinfo(dev); 4834 if (devinfo == NULL || devinfo->codec == NULL || 4835 devinfo->codec->sc == NULL) 4836 return (EINVAL); 4837 sc = devinfo->codec->sc; 4838 hdac_lock(sc); 4839 val = sc->polling; 4840 hdac_unlock(sc); 4841 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4842 4843 if (err || req->newptr == NULL) 4844 return (err); 4845 if (val < 0 || val > 1) 4846 return (EINVAL); 4847 4848 hdac_lock(sc); 4849 if (val != sc->polling) { 4850 if (hda_chan_active(sc) != 0) 4851 err = EBUSY; 4852 else if (val == 0) { 4853 callout_stop(&sc->poll_hdac); 4854 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 4855 sc->rirb_size / 2); 4856 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4857 ctl |= HDAC_RIRBCTL_RINTCTL; 4858 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4859 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4860 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4861 sc->polling = 0; 4862 DELAY(1000); 4863 } else { 4864 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 4865 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 4866 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4867 ctl &= ~HDAC_RIRBCTL_RINTCTL; 4868 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4869 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 4870 sc); 4871 sc->polling = 1; 4872 DELAY(1000); 4873 } 4874 } 4875 hdac_unlock(sc); 4876 4877 return (err); 4878} 4879#endif 4880 4881static void 4882hdac_attach2(void *arg) 4883{ 4884 struct hdac_softc *sc; 4885 struct hdac_widget *w; 4886 struct hdac_audio_ctl *ctl; 4887 uint32_t quirks_on, quirks_off; 4888 int pcnt, rcnt; 4889 int i; 4890 char status[SND_STATUSLEN]; 4891 device_t *devlist = NULL; 4892 int devcount; 4893 struct hdac_devinfo *devinfo = NULL; 4894 4895 sc = (struct hdac_softc *)arg; 4896 4897 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4898 4899 HDA_BOOTVERBOSE( 4900 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4901 quirks_on, quirks_off); 4902 ); 4903 4904 hdac_lock(sc); 4905 4906 /* Remove ourselves from the config hooks */ 4907 if (sc->intrhook.ich_func != NULL) { 4908 config_intrhook_disestablish(&sc->intrhook); 4909 sc->intrhook.ich_func = NULL; 4910 } 4911 4912 /* Start the corb and rirb engines */ 4913 HDA_BOOTVERBOSE( 4914 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4915 ); 4916 hdac_corb_start(sc); 4917 HDA_BOOTVERBOSE( 4918 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4919 ); 4920 hdac_rirb_start(sc); 4921 4922 HDA_BOOTVERBOSE( 4923 device_printf(sc->dev, 4924 "HDA_DEBUG: Enabling controller interrupt...\n"); 4925 ); 4926 if (sc->polling == 0) 4927 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4928 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4929 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4930 HDAC_GCTL_UNSOL); 4931 4932 DELAY(1000); 4933 4934 HDA_BOOTVERBOSE( 4935 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4936 ); 4937 hdac_scan_codecs(sc); 4938 4939 device_get_children(sc->dev, &devlist, &devcount); 4940 for (i = 0; devlist != NULL && i < devcount; i++) { 4941 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4942 if (devinfo != NULL && devinfo->node_type == 4943 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4944 break; 4945 } else 4946 devinfo = NULL; 4947 } 4948 if (devlist != NULL) 4949 free(devlist, M_TEMP); 4950 4951 if (devinfo == NULL) { 4952 hdac_unlock(sc); 4953 device_printf(sc->dev, "Audio Function Group not found!\n"); 4954 hdac_release_resources(sc); 4955 return; 4956 } 4957 4958 HDA_BOOTVERBOSE( 4959 device_printf(sc->dev, 4960 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4961 devinfo->nid, devinfo->codec->cad); 4962 ); 4963 hdac_audio_parse(devinfo); 4964 HDA_BOOTVERBOSE( 4965 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4966 ); 4967 hdac_audio_ctl_parse(devinfo); 4968 HDA_BOOTVERBOSE( 4969 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4970 ); 4971 hdac_vendor_patch_parse(devinfo); 4972 if (quirks_on != 0) 4973 devinfo->function.audio.quirks |= quirks_on; 4974 if (quirks_off != 0) 4975 devinfo->function.audio.quirks &= ~quirks_off; 4976 4977 /* XXX Disable all DIGITAL path. */ 4978 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4979 w = hdac_widget_get(devinfo, i); 4980 if (w == NULL) 4981 continue; 4982 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4983 w->enable = 0; 4984 continue; 4985 } 4986 /* XXX Disable useless pin ? */ 4987 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4988 (w->wclass.pin.config & 4989 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4990 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4991 w->enable = 0; 4992 } 4993 i = 0; 4994 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4995 if (ctl->widget == NULL) 4996 continue; 4997 w = ctl->widget; 4998 if (w->enable == 0) 4999 ctl->enable = 0; 5000 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5001 ctl->enable = 0; 5002 w = ctl->childwidget; 5003 if (w == NULL) 5004 continue; 5005 if (w->enable == 0 || 5006 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5007 ctl->enable = 0; 5008 } 5009 5010 HDA_BOOTVERBOSE( 5011 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5012 ); 5013 hdac_audio_build_tree(devinfo); 5014 5015 HDA_BOOTVERBOSE( 5016 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5017 ); 5018 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5019 HDA_BOOTVERBOSE( 5020 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5021 ); 5022 hdac_audio_ctl_commit(devinfo); 5023 5024 HDA_BOOTVERBOSE( 5025 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5026 ); 5027 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5028 HDA_BOOTVERBOSE( 5029 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5030 ); 5031 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5032 5033 hdac_unlock(sc); 5034 HDA_BOOTVERBOSE( 5035 device_printf(sc->dev, 5036 "HDA_DEBUG: OSS mixer initialization...\n"); 5037 ); 5038 5039 /* 5040 * There is no point of return after this. If the driver failed, 5041 * so be it. Let the detach procedure do all the cleanup. 5042 */ 5043 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5044 device_printf(sc->dev, "Can't register mixer\n"); 5045 5046 if (pcnt > 0) 5047 pcnt = 1; 5048 if (rcnt > 0) 5049 rcnt = 1; 5050 5051 HDA_BOOTVERBOSE( 5052 device_printf(sc->dev, 5053 "HDA_DEBUG: Registering PCM channels...\n"); 5054 ); 5055 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5056 device_printf(sc->dev, "Can't register PCM\n"); 5057 5058 sc->registered++; 5059 5060 for (i = 0; i < pcnt; i++) 5061 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5062 for (i = 0; i < rcnt; i++) 5063 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5064 5065#ifdef SND_DYNSYSCTL 5066 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5067 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5068 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5069 sysctl_hdac_polling, "I", "Enable polling mode"); 5070#endif 5071 5072 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5073 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5074 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5075 pcm_setstatus(sc->dev, status); 5076 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5077 HDA_BOOTVERBOSE( 5078 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5079 hdac_codec_id(devinfo)); 5080 ); 5081 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5082 HDA_DRV_TEST_REV); 5083 5084 HDA_BOOTVERBOSE( 5085 if (devinfo->function.audio.quirks != 0) { 5086 device_printf(sc->dev, "\n"); 5087 device_printf(sc->dev, "HDA config/quirks:"); 5088 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5089 if (devinfo->function.audio.quirks & 5090 hdac_quirks_tab[i].value) 5091 printf(" %s", hdac_quirks_tab[i].key); 5092 } 5093 printf("\n"); 5094 } 5095 device_printf(sc->dev, "\n"); 5096 device_printf(sc->dev, "+-------------------+\n"); 5097 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5098 device_printf(sc->dev, "+-------------------+\n"); 5099 hdac_dump_nodes(devinfo); 5100 device_printf(sc->dev, "\n"); 5101 device_printf(sc->dev, "+------------------------+\n"); 5102 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5103 device_printf(sc->dev, "+------------------------+\n"); 5104 device_printf(sc->dev, "\n"); 5105 i = 0; 5106 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5107 device_printf(sc->dev, "%3d: nid=%d", i, 5108 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5109 if (ctl->childwidget != NULL) 5110 printf(" cnid=%d", ctl->childwidget->nid); 5111 printf(" dir=0x%x index=%d " 5112 "ossmask=0x%08x ossdev=%d%s\n", 5113 ctl->dir, ctl->index, 5114 ctl->ossmask, ctl->ossdev, 5115 (ctl->enable == 0) ? " [DISABLED]" : ""); 5116 } 5117 device_printf(sc->dev, "\n"); 5118 device_printf(sc->dev, "+-----------------------------------+\n"); 5119 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5120 device_printf(sc->dev, "+-----------------------------------+\n"); 5121 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5122 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5123 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5124 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5125 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5126 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5127 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5128 hdac_dump_ctls(devinfo, NULL, 0); 5129 hdac_dump_dac(devinfo); 5130 hdac_dump_adc(devinfo); 5131 device_printf(sc->dev, "\n"); 5132 device_printf(sc->dev, "+--------------------------------------+\n"); 5133 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5134 device_printf(sc->dev, "+--------------------------------------+\n"); 5135 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5136 ); 5137 5138 if (sc->polling != 0) { 5139 hdac_lock(sc); 5140 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5141 hdac_unlock(sc); 5142 } 5143} 5144 5145/**************************************************************************** 5146 * int hdac_detach(device_t) 5147 * 5148 * Detach and free up resources utilized by the hdac device. 5149 ****************************************************************************/ 5150static int 5151hdac_detach(device_t dev) 5152{ 5153 struct hdac_softc *sc = NULL; 5154 struct hdac_devinfo *devinfo = NULL; 5155 int err; 5156 5157 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5158 if (devinfo != NULL && devinfo->codec != NULL) 5159 sc = devinfo->codec->sc; 5160 if (sc == NULL) 5161 return (0); 5162 5163 if (sc->registered > 0) { 5164 err = pcm_unregister(dev); 5165 if (err != 0) 5166 return (err); 5167 } 5168 5169 hdac_release_resources(sc); 5170 5171 return (0); 5172} 5173 5174static device_method_t hdac_methods[] = { 5175 /* device interface */ 5176 DEVMETHOD(device_probe, hdac_probe), 5177 DEVMETHOD(device_attach, hdac_attach), 5178 DEVMETHOD(device_detach, hdac_detach), 5179 { 0, 0 } 5180}; 5181 5182static driver_t hdac_driver = { 5183 "pcm", 5184 hdac_methods, 5185 PCM_SOFTC_SIZE, 5186}; 5187 5188DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5189MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5190MODULE_VERSION(snd_hda, 1); 5191