hdac.c revision 164657
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061111_0034" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 164657 2006-11-27 06:16:36Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 193#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 194 195/* IBM / Lenovo */ 196#define IBM_VENDORID 0x1014 197#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 198#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 199 200/* Lenovo */ 201#define LENOVO_VENDORID 0x17aa 202#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 203#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 204 205/* Samsung */ 206#define SAMSUNG_VENDORID 0x144d 207#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 208#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 209 210/* Misc constants.. */ 211#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 212#define HDA_AMP_MUTE_NONE (0) 213#define HDA_AMP_MUTE_LEFT (1 << 0) 214#define HDA_AMP_MUTE_RIGHT (1 << 1) 215#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 216 217#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 218#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 219 220#define HDA_DAC_PATH (1 << 0) 221#define HDA_ADC_PATH (1 << 1) 222#define HDA_ADC_RECSEL (1 << 2) 223 224#define HDA_CTL_OUT (1 << 0) 225#define HDA_CTL_IN (1 << 1) 226#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 227 228#define HDA_GPIO_MAX 15 229/* 0 - 14 = GPIO */ 230#define HDA_QUIRK_GPIO0 (1 << 0) 231#define HDA_QUIRK_GPIO1 (1 << 1) 232#define HDA_QUIRK_GPIO2 (1 << 2) 233#define HDA_QUIRK_SOFTPCMVOL (1 << 15) 234#define HDA_QUIRK_FIXEDRATE (1 << 16) 235#define HDA_QUIRK_FORCESTEREO (1 << 17) 236#define HDA_QUIRK_EAPDINV (1 << 18) 237 238static const struct { 239 char *key; 240 uint32_t value; 241} hdac_quirks_tab[] = { 242 { "gpio0", HDA_QUIRK_GPIO0 }, 243 { "gpio1", HDA_QUIRK_GPIO1 }, 244 { "gpio2", HDA_QUIRK_GPIO2 }, 245 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 246 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 247 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 248 { "eapdinv", HDA_QUIRK_EAPDINV }, 249}; 250#define HDAC_QUIRKS_TAB_LEN \ 251 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 252 253#define HDA_BDL_MIN 2 254#define HDA_BDL_MAX 256 255#define HDA_BDL_DEFAULT HDA_BDL_MIN 256 257#define HDA_BUFSZ_MIN 4096 258#define HDA_BUFSZ_MAX 65536 259#define HDA_BUFSZ_DEFAULT 16384 260 261#define HDA_PARSE_MAXDEPTH 10 262 263#define HDAC_UNSOLTAG_EVENT_HP 0x00 264 265static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 266 267enum { 268 HDA_PARSE_MIXER, 269 HDA_PARSE_DIRECT 270}; 271 272/* Default */ 273static uint32_t hdac_fmt[] = { 274 AFMT_STEREO | AFMT_S16_LE, 275 0 276}; 277 278static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 279 280static const struct { 281 uint32_t model; 282 char *desc; 283} hdac_devices[] = { 284 { HDA_INTEL_82801F, "Intel 82801F" }, 285 { HDA_INTEL_82801G, "Intel 82801G" }, 286 { HDA_INTEL_82801H, "Intel 82801H" }, 287 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 288 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 289 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 290 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 291 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 292 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 293 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 294 { HDA_ATI_SB450, "ATI SB450" }, 295 { HDA_ATI_SB600, "ATI SB600" }, 296 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 297 { HDA_SIS_966, "SiS 966" }, 298 /* Unknown */ 299 { HDA_INTEL_ALL, "Intel (Unknown)" }, 300 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 301 { HDA_ATI_ALL, "ATI (Unknown)" }, 302 { HDA_VIA_ALL, "VIA (Unknown)" }, 303 { HDA_SIS_ALL, "SiS (Unknown)" }, 304}; 305#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 306 307static const struct { 308 uint32_t rate; 309 int valid; 310 uint16_t base; 311 uint16_t mul; 312 uint16_t div; 313} hda_rate_tab[] = { 314 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 315 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 316 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 317 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 318 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 319 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 320 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 321 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 322 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 323 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 324 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 325 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 326 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 327 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 328 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 329 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 330 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 331 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 332 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 333 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 334 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 335 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 336 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 337 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 338 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 339 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 340 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 341 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 342 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 343 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 344 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 345 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 346 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 347 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 348 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 349}; 350#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 351 352/* All codecs you can eat... */ 353#define HDA_CODEC_CONSTRUCT(vendor, id) \ 354 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 355 356/* Realtek */ 357#define REALTEK_VENDORID 0x10ec 358#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 359#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 360#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 361#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 362#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 363#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 364 365/* Analog Device */ 366#define ANALOGDEVICE_VENDORID 0x11d4 367#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 368#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 369#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 370#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 371 372/* CMedia */ 373#define CMEDIA_VENDORID 0x434d 374#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 375#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 376 377/* Sigmatel */ 378#define SIGMATEL_VENDORID 0x8384 379#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 380#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 381#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 382#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 383#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 384 385/* 386 * Conexant 387 * 388 * Ok, the truth is, I don't have any idea at all whether 389 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 390 * place that tell me it is "Venice" is from its Windows driver INF. 391 * 392 * Venice - CX????? 393 * Waikiki - CX20551-22 394 */ 395#define CONEXANT_VENDORID 0x14f1 396#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 397#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 398#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 399 400 401/* Codecs */ 402static const struct { 403 uint32_t id; 404 char *name; 405} hdac_codecs[] = { 406 { HDA_CODEC_ALC260, "Realtek ALC260" }, 407 { HDA_CODEC_ALC861, "Realtek ALC861" }, 408 { HDA_CODEC_ALC880, "Realtek ALC880" }, 409 { HDA_CODEC_ALC882, "Realtek ALC882" }, 410 { HDA_CODEC_ALC883, "Realtek ALC883" }, 411 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 412 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 413 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 414 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 415 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 416 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 417 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 418 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 419 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 420 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 421 /* Unknown codec */ 422 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 423 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 424 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 425 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 426 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 427}; 428#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 429 430enum { 431 HDAC_HP_SWITCH_CTL, 432 HDAC_HP_SWITCH_CTRL 433}; 434 435static const struct { 436 uint32_t model; 437 uint32_t id; 438 int type; 439 nid_t hpnid; 440 nid_t spkrnid[8]; 441 nid_t eapdnid; 442} hdac_hp_switch[] = { 443 /* Specific OEM models */ 444 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 445 17, { 16, -1 }, 16 }, 446 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 447 6, { 5, -1 }, 5 }, 448 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 449 6, { 5, -1 }, 5 }, 450 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 451 13, { 14, -1 }, -1 }, 452 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 453 13, { 14, -1 }, -1 }, 454 /* 455 * All models that at least come from the same vendor with 456 * simmilar codec. 457 */ 458 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 459 17, { 16, -1 }, 16 }, 460 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 461 6, { 5, -1 }, 5 }, 462 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 463 13, { 14, -1 }, -1 }, 464}; 465#define HDAC_HP_SWITCH_LEN \ 466 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 467 468static const struct { 469 uint32_t model; 470 uint32_t id; 471 nid_t eapdnid; 472 int hp_switch; 473} hdac_eapd_switch[] = { 474 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 475 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 476 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 477}; 478#define HDAC_EAPD_SWITCH_LEN \ 479 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 480 481/**************************************************************************** 482 * Function prototypes 483 ****************************************************************************/ 484static void hdac_intr_handler(void *); 485static int hdac_reset(struct hdac_softc *); 486static int hdac_get_capabilities(struct hdac_softc *); 487static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 488static int hdac_dma_alloc(struct hdac_softc *, 489 struct hdac_dma *, bus_size_t); 490static void hdac_dma_free(struct hdac_dma *); 491static int hdac_mem_alloc(struct hdac_softc *); 492static void hdac_mem_free(struct hdac_softc *); 493static int hdac_irq_alloc(struct hdac_softc *); 494static void hdac_irq_free(struct hdac_softc *); 495static void hdac_corb_init(struct hdac_softc *); 496static void hdac_rirb_init(struct hdac_softc *); 497static void hdac_corb_start(struct hdac_softc *); 498static void hdac_rirb_start(struct hdac_softc *); 499static void hdac_scan_codecs(struct hdac_softc *); 500static int hdac_probe_codec(struct hdac_codec *); 501static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 502static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 503 504static void hdac_attach2(void *); 505 506static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 507 uint32_t, int); 508static void hdac_command_send_internal(struct hdac_softc *, 509 struct hdac_command_list *, int); 510 511static int hdac_probe(device_t); 512static int hdac_attach(device_t); 513static int hdac_detach(device_t); 514static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 515static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 516 uint32_t, int, int); 517static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 518 nid_t, int, int); 519static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 520 nid_t, nid_t, int, int, int, int, int, int); 521static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 522static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 523 524static int hdac_rirb_flush(struct hdac_softc *sc); 525static int hdac_unsolq_flush(struct hdac_softc *sc); 526 527#define hdac_command(a1, a2, a3) \ 528 hdac_command_sendone_internal(a1, a2, a3) 529 530#define hdac_codec_id(d) \ 531 ((uint32_t)((d == NULL) ? 0x00000000 : \ 532 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 533 ((uint32_t)(d)->device_id & 0x0000ffff)))) 534 535static char * 536hdac_codec_name(struct hdac_devinfo *devinfo) 537{ 538 uint32_t id; 539 int i; 540 541 id = hdac_codec_id(devinfo); 542 543 for (i = 0; i < HDAC_CODECS_LEN; i++) { 544 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 545 return (hdac_codecs[i].name); 546 } 547 548 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 549} 550 551static char * 552hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 553{ 554 static char *ossname[] = SOUND_DEVICE_NAMES; 555 static char *unknown = "???"; 556 int i; 557 558 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 559 if (devmask & (1 << i)) 560 return (ossname[i]); 561 } 562 return (unknown); 563} 564 565static void 566hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 567{ 568 static char *ossname[] = SOUND_DEVICE_NAMES; 569 int i, first = 1; 570 571 bzero(buf, len); 572 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 573 if (mask & (1 << i)) { 574 if (first == 0) 575 strlcat(buf, ", ", len); 576 strlcat(buf, ossname[i], len); 577 first = 0; 578 } 579 } 580} 581 582static struct hdac_audio_ctl * 583hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 584{ 585 if (devinfo == NULL || 586 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 587 index == NULL || devinfo->function.audio.ctl == NULL || 588 devinfo->function.audio.ctlcnt < 1 || 589 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 590 return (NULL); 591 return (&devinfo->function.audio.ctl[(*index)++]); 592} 593 594static struct hdac_audio_ctl * 595hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 596 int index, int cnt) 597{ 598 struct hdac_audio_ctl *ctl, *retctl = NULL; 599 int i, at, atindex, found = 0; 600 601 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 602 return (NULL); 603 604 at = cnt; 605 if (at == 0) 606 at = 1; 607 else if (at < 0) 608 at = -1; 609 atindex = index; 610 if (atindex < 0) 611 atindex = -1; 612 613 i = 0; 614 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 615 if (ctl->enable == 0 || ctl->widget == NULL) 616 continue; 617 if (!(ctl->widget->nid == nid && (atindex == -1 || 618 ctl->index == atindex))) 619 continue; 620 found++; 621 if (found == cnt) 622 return (ctl); 623 retctl = ctl; 624 } 625 626 return ((at == -1) ? retctl : NULL); 627} 628 629static void 630hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 631{ 632 struct hdac_softc *sc; 633 struct hdac_widget *w; 634 struct hdac_audio_ctl *ctl; 635 uint32_t id, res; 636 int i = 0, j, forcemute; 637 nid_t cad; 638 639 if (devinfo == NULL || devinfo->codec == NULL || 640 devinfo->codec->sc == NULL) 641 return; 642 643 sc = devinfo->codec->sc; 644 cad = devinfo->codec->cad; 645 id = hdac_codec_id(devinfo); 646 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 647 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 648 sc->pci_subvendor) && 649 hdac_hp_switch[i].id == id) 650 break; 651 } 652 653 if (i >= HDAC_HP_SWITCH_LEN) 654 return; 655 656 forcemute = 0; 657 if (hdac_hp_switch[i].eapdnid != -1) { 658 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 659 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 660 forcemute = (w->param.eapdbtl & 661 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 662 } 663 664 res = hdac_command(sc, 665 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 666 HDA_BOOTVERBOSE( 667 device_printf(sc->dev, 668 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 669 hdac_hp_switch[i].hpnid, res); 670 ); 671 res >>= 31; 672 673 switch (hdac_hp_switch[i].type) { 674 case HDAC_HP_SWITCH_CTL: 675 ctl = hdac_audio_ctl_amp_get(devinfo, 676 hdac_hp_switch[i].hpnid, 0, 1); 677 if (ctl != NULL) { 678 ctl->muted = (res != 0 && forcemute == 0) ? 679 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 680 hdac_audio_ctl_amp_set(ctl, 681 HDA_AMP_MUTE_DEFAULT, ctl->left, 682 ctl->right); 683 } 684 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 685 ctl = hdac_audio_ctl_amp_get(devinfo, 686 hdac_hp_switch[i].spkrnid[j], 0, 1); 687 if (ctl != NULL) { 688 ctl->muted = (res != 0 || forcemute == 1) ? 689 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 690 hdac_audio_ctl_amp_set(ctl, 691 HDA_AMP_MUTE_DEFAULT, ctl->left, 692 ctl->right); 693 } 694 } 695 break; 696 case HDAC_HP_SWITCH_CTRL: 697 if (res != 0) { 698 /* HP in */ 699 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 700 if (w != NULL && w->type == 701 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 702 if (forcemute == 0) 703 w->wclass.pin.ctrl |= 704 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 705 else 706 w->wclass.pin.ctrl &= 707 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 708 hdac_command(sc, 709 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 710 w->wclass.pin.ctrl), cad); 711 } 712 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 713 w = hdac_widget_get(devinfo, 714 hdac_hp_switch[i].spkrnid[j]); 715 if (w != NULL && w->type == 716 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 717 w->wclass.pin.ctrl &= 718 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 719 hdac_command(sc, 720 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 721 w->nid, 722 w->wclass.pin.ctrl), cad); 723 } 724 } 725 } else { 726 /* HP out */ 727 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 728 if (w != NULL && w->type == 729 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 730 w->wclass.pin.ctrl &= 731 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 732 hdac_command(sc, 733 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 734 w->wclass.pin.ctrl), cad); 735 } 736 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 737 w = hdac_widget_get(devinfo, 738 hdac_hp_switch[i].spkrnid[j]); 739 if (w != NULL && w->type == 740 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 741 if (forcemute == 0) 742 w->wclass.pin.ctrl |= 743 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 744 else 745 w->wclass.pin.ctrl &= 746 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 747 hdac_command(sc, 748 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 749 w->nid, 750 w->wclass.pin.ctrl), cad); 751 } 752 } 753 } 754 break; 755 default: 756 break; 757 } 758} 759 760static void 761hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 762{ 763 struct hdac_softc *sc; 764 struct hdac_devinfo *devinfo = NULL; 765 device_t *devlist = NULL; 766 int devcount, i; 767 768 if (codec == NULL || codec->sc == NULL) 769 return; 770 771 sc = codec->sc; 772 773 HDA_BOOTVERBOSE( 774 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 775 ); 776 777 device_get_children(sc->dev, &devlist, &devcount); 778 for (i = 0; devlist != NULL && i < devcount; i++) { 779 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 780 if (devinfo != NULL && devinfo->node_type == 781 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 782 devinfo->codec != NULL && 783 devinfo->codec->cad == codec->cad) { 784 break; 785 } else 786 devinfo = NULL; 787 } 788 if (devlist != NULL) 789 free(devlist, M_TEMP); 790 791 if (devinfo == NULL) 792 return; 793 794 switch (tag) { 795 case HDAC_UNSOLTAG_EVENT_HP: 796 hdac_hp_switch_handler(devinfo); 797 break; 798 default: 799 break; 800 } 801} 802 803static int 804hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 805{ 806 /* XXX to be removed */ 807#ifdef HDAC_INTR_EXTRA 808 uint32_t res; 809#endif 810 811 if (ch->blkcnt == 0) 812 return (0); 813 814 /* XXX to be removed */ 815#ifdef HDAC_INTR_EXTRA 816 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 817#endif 818 819 /* XXX to be removed */ 820#ifdef HDAC_INTR_EXTRA 821 HDA_BOOTVERBOSE( 822 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 823 device_printf(sc->dev, 824 "PCMDIR_%s intr triggered beyond stream boundary:" 825 "%08x\n", 826 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 827 ); 828#endif 829 830 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 831 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 832 833 /* XXX to be removed */ 834#ifdef HDAC_INTR_EXTRA 835 if (res & HDAC_SDSTS_BCIS) { 836#endif 837 return (1); 838 /* XXX to be removed */ 839#ifdef HDAC_INTR_EXTRA 840 } 841#endif 842 843 return (0); 844} 845 846/**************************************************************************** 847 * void hdac_intr_handler(void *) 848 * 849 * Interrupt handler. Processes interrupts received from the hdac. 850 ****************************************************************************/ 851static void 852hdac_intr_handler(void *context) 853{ 854 struct hdac_softc *sc; 855 uint32_t intsts; 856 uint8_t rirbsts; 857 struct hdac_rirb *rirb_base; 858 uint32_t trigger = 0; 859 860 sc = (struct hdac_softc *)context; 861 862 hdac_lock(sc); 863 if (sc->polling != 0) { 864 hdac_unlock(sc); 865 return; 866 } 867 /* Do we have anything to do? */ 868 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 869 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 870 hdac_unlock(sc); 871 return; 872 } 873 874 /* Was this a controller interrupt? */ 875 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 876 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 877 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 878 /* Get as many responses that we can */ 879 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 880 HDAC_WRITE_1(&sc->mem, 881 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 882 hdac_rirb_flush(sc); 883 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 884 } 885 /* XXX to be removed */ 886 /* Clear interrupt and exit */ 887#ifdef HDAC_INTR_EXTRA 888 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 889#endif 890 } 891 892 hdac_unsolq_flush(sc); 893 894 if (intsts & HDAC_INTSTS_SIS_MASK) { 895 if ((intsts & (1 << sc->num_iss)) && 896 hdac_stream_intr(sc, &sc->play) != 0) 897 trigger |= 1; 898 if ((intsts & (1 << 0)) && 899 hdac_stream_intr(sc, &sc->rec) != 0) 900 trigger |= 2; 901 /* XXX to be removed */ 902#ifdef HDAC_INTR_EXTRA 903 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 904 HDAC_INTSTS_SIS_MASK); 905#endif 906 } 907 908 hdac_unlock(sc); 909 910 if (trigger & 1) 911 chn_intr(sc->play.c); 912 if (trigger & 2) 913 chn_intr(sc->rec.c); 914} 915 916/**************************************************************************** 917 * int hdac_reset(hdac_softc *) 918 * 919 * Reset the hdac to a quiescent and known state. 920 ****************************************************************************/ 921static int 922hdac_reset(struct hdac_softc *sc) 923{ 924 uint32_t gctl; 925 int count, i; 926 927 /* 928 * Stop all Streams DMA engine 929 */ 930 for (i = 0; i < sc->num_iss; i++) 931 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 932 for (i = 0; i < sc->num_oss; i++) 933 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 934 for (i = 0; i < sc->num_bss; i++) 935 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 936 937 /* 938 * Stop Control DMA engines 939 */ 940 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 941 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 942 943 /* 944 * Reset the controller. The reset must remain asserted for 945 * a minimum of 100us. 946 */ 947 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 948 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 949 count = 10000; 950 do { 951 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 952 if (!(gctl & HDAC_GCTL_CRST)) 953 break; 954 DELAY(10); 955 } while (--count); 956 if (gctl & HDAC_GCTL_CRST) { 957 device_printf(sc->dev, "Unable to put hdac in reset\n"); 958 return (ENXIO); 959 } 960 DELAY(100); 961 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 962 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 963 count = 10000; 964 do { 965 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 966 if (gctl & HDAC_GCTL_CRST) 967 break; 968 DELAY(10); 969 } while (--count); 970 if (!(gctl & HDAC_GCTL_CRST)) { 971 device_printf(sc->dev, "Device stuck in reset\n"); 972 return (ENXIO); 973 } 974 975 /* 976 * Wait for codecs to finish their own reset sequence. The delay here 977 * should be of 250us but for some reasons, on it's not enough on my 978 * computer. Let's use twice as much as necessary to make sure that 979 * it's reset properly. 980 */ 981 DELAY(1000); 982 983 return (0); 984} 985 986 987/**************************************************************************** 988 * int hdac_get_capabilities(struct hdac_softc *); 989 * 990 * Retreive the general capabilities of the hdac; 991 * Number of Input Streams 992 * Number of Output Streams 993 * Number of bidirectional Streams 994 * 64bit ready 995 * CORB and RIRB sizes 996 ****************************************************************************/ 997static int 998hdac_get_capabilities(struct hdac_softc *sc) 999{ 1000 uint16_t gcap; 1001 uint8_t corbsize, rirbsize; 1002 1003 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1004 sc->num_iss = HDAC_GCAP_ISS(gcap); 1005 sc->num_oss = HDAC_GCAP_OSS(gcap); 1006 sc->num_bss = HDAC_GCAP_BSS(gcap); 1007 1008 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1009 1010 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1011 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1012 HDAC_CORBSIZE_CORBSZCAP_256) 1013 sc->corb_size = 256; 1014 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1015 HDAC_CORBSIZE_CORBSZCAP_16) 1016 sc->corb_size = 16; 1017 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1018 HDAC_CORBSIZE_CORBSZCAP_2) 1019 sc->corb_size = 2; 1020 else { 1021 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1022 __func__, corbsize); 1023 return (ENXIO); 1024 } 1025 1026 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1027 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1028 HDAC_RIRBSIZE_RIRBSZCAP_256) 1029 sc->rirb_size = 256; 1030 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1031 HDAC_RIRBSIZE_RIRBSZCAP_16) 1032 sc->rirb_size = 16; 1033 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1034 HDAC_RIRBSIZE_RIRBSZCAP_2) 1035 sc->rirb_size = 2; 1036 else { 1037 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1038 __func__, rirbsize); 1039 return (ENXIO); 1040 } 1041 1042 return (0); 1043} 1044 1045 1046/**************************************************************************** 1047 * void hdac_dma_cb 1048 * 1049 * This function is called by bus_dmamap_load when the mapping has been 1050 * established. We just record the physical address of the mapping into 1051 * the struct hdac_dma passed in. 1052 ****************************************************************************/ 1053static void 1054hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1055{ 1056 struct hdac_dma *dma; 1057 1058 if (error == 0) { 1059 dma = (struct hdac_dma *)callback_arg; 1060 dma->dma_paddr = segs[0].ds_addr; 1061 } 1062} 1063 1064static void 1065hdac_dma_nocache(void *ptr) 1066{ 1067#if defined(__i386__) || defined(__amd64__) 1068 pt_entry_t *pte; 1069 vm_offset_t va; 1070 1071 va = (vm_offset_t)ptr; 1072 pte = vtopte(va); 1073 if (pte) { 1074 *pte |= PG_N; 1075 invltlb(); 1076 } 1077#endif 1078} 1079 1080/**************************************************************************** 1081 * int hdac_dma_alloc 1082 * 1083 * This function allocate and setup a dma region (struct hdac_dma). 1084 * It must be freed by a corresponding hdac_dma_free. 1085 ****************************************************************************/ 1086static int 1087hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1088{ 1089 int result; 1090 int lowaddr; 1091 1092 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1093 BUS_SPACE_MAXADDR_32BIT; 1094 bzero(dma, sizeof(*dma)); 1095 1096 /* 1097 * Create a DMA tag 1098 */ 1099 result = bus_dma_tag_create(NULL, /* parent */ 1100 HDAC_DMA_ALIGNMENT, /* alignment */ 1101 0, /* boundary */ 1102 lowaddr, /* lowaddr */ 1103 BUS_SPACE_MAXADDR, /* highaddr */ 1104 NULL, /* filtfunc */ 1105 NULL, /* fistfuncarg */ 1106 size, /* maxsize */ 1107 1, /* nsegments */ 1108 size, /* maxsegsz */ 1109 0, /* flags */ 1110 NULL, /* lockfunc */ 1111 NULL, /* lockfuncarg */ 1112 &dma->dma_tag); /* dmat */ 1113 if (result != 0) { 1114 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1115 __func__, result); 1116 goto fail; 1117 } 1118 1119 /* 1120 * Allocate DMA memory 1121 */ 1122 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1123 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1124 if (result != 0) { 1125 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1126 __func__, result); 1127 goto fail; 1128 } 1129 1130 /* 1131 * Map the memory 1132 */ 1133 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1134 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1135 BUS_DMA_NOWAIT); 1136 if (result != 0 || dma->dma_paddr == 0) { 1137 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1138 __func__, result); 1139 goto fail; 1140 } 1141 bzero((void *)dma->dma_vaddr, size); 1142 hdac_dma_nocache(dma->dma_vaddr); 1143 1144 return (0); 1145fail: 1146 if (dma->dma_map != NULL) 1147 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1148 if (dma->dma_tag != NULL) 1149 bus_dma_tag_destroy(dma->dma_tag); 1150 return (result); 1151} 1152 1153 1154/**************************************************************************** 1155 * void hdac_dma_free(struct hdac_dma *) 1156 * 1157 * Free a struct dhac_dma that has been previously allocated via the 1158 * hdac_dma_alloc function. 1159 ****************************************************************************/ 1160static void 1161hdac_dma_free(struct hdac_dma *dma) 1162{ 1163 if (dma->dma_tag != NULL) { 1164 /* Flush caches */ 1165 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1166 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1167 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1168 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1169 bus_dma_tag_destroy(dma->dma_tag); 1170 } 1171} 1172 1173/**************************************************************************** 1174 * int hdac_mem_alloc(struct hdac_softc *) 1175 * 1176 * Allocate all the bus resources necessary to speak with the physical 1177 * controller. 1178 ****************************************************************************/ 1179static int 1180hdac_mem_alloc(struct hdac_softc *sc) 1181{ 1182 struct hdac_mem *mem; 1183 1184 mem = &sc->mem; 1185 mem->mem_rid = PCIR_BAR(0); 1186 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1187 &mem->mem_rid, RF_ACTIVE); 1188 if (mem->mem_res == NULL) { 1189 device_printf(sc->dev, 1190 "%s: Unable to allocate memory resource\n", __func__); 1191 return (ENOMEM); 1192 } 1193 mem->mem_tag = rman_get_bustag(mem->mem_res); 1194 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1195 1196 return (0); 1197} 1198 1199/**************************************************************************** 1200 * void hdac_mem_free(struct hdac_softc *) 1201 * 1202 * Free up resources previously allocated by hdac_mem_alloc. 1203 ****************************************************************************/ 1204static void 1205hdac_mem_free(struct hdac_softc *sc) 1206{ 1207 struct hdac_mem *mem; 1208 1209 mem = &sc->mem; 1210 if (mem->mem_res != NULL) 1211 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1212 mem->mem_res); 1213 mem->mem_res = NULL; 1214} 1215 1216/**************************************************************************** 1217 * int hdac_irq_alloc(struct hdac_softc *) 1218 * 1219 * Allocate and setup the resources necessary for interrupt handling. 1220 ****************************************************************************/ 1221static int 1222hdac_irq_alloc(struct hdac_softc *sc) 1223{ 1224 struct hdac_irq *irq; 1225 int result; 1226 1227 irq = &sc->irq; 1228 irq->irq_rid = 0x0; 1229 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1230 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1231 if (irq->irq_res == NULL) { 1232 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1233 __func__); 1234 goto fail; 1235 } 1236 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1237 hdac_intr_handler, sc, &irq->irq_handle); 1238 if (result != 0) { 1239 device_printf(sc->dev, 1240 "%s: Unable to setup interrupt handler (%x)\n", 1241 __func__, result); 1242 goto fail; 1243 } 1244 1245 return (0); 1246 1247fail: 1248 hdac_irq_free(sc); 1249 1250 return (ENXIO); 1251} 1252 1253/**************************************************************************** 1254 * void hdac_irq_free(struct hdac_softc *) 1255 * 1256 * Free up resources previously allocated by hdac_irq_alloc. 1257 ****************************************************************************/ 1258static void 1259hdac_irq_free(struct hdac_softc *sc) 1260{ 1261 struct hdac_irq *irq; 1262 1263 irq = &sc->irq; 1264 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1265 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1266 if (irq->irq_res != NULL) 1267 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1268 irq->irq_res); 1269 irq->irq_handle = NULL; 1270 irq->irq_res = NULL; 1271} 1272 1273/**************************************************************************** 1274 * void hdac_corb_init(struct hdac_softc *) 1275 * 1276 * Initialize the corb registers for operations but do not start it up yet. 1277 * The CORB engine must not be running when this function is called. 1278 ****************************************************************************/ 1279static void 1280hdac_corb_init(struct hdac_softc *sc) 1281{ 1282 uint8_t corbsize; 1283 uint64_t corbpaddr; 1284 1285 /* Setup the CORB size. */ 1286 switch (sc->corb_size) { 1287 case 256: 1288 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1289 break; 1290 case 16: 1291 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1292 break; 1293 case 2: 1294 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1295 break; 1296 default: 1297 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1298 } 1299 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1300 1301 /* Setup the CORB Address in the hdac */ 1302 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1303 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1304 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1305 1306 /* Set the WP and RP */ 1307 sc->corb_wp = 0; 1308 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1309 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1310 /* 1311 * The HDA specification indicates that the CORBRPRST bit will always 1312 * read as zero. Unfortunately, it seems that at least the 82801G 1313 * doesn't reset the bit to zero, which stalls the corb engine. 1314 * manually reset the bit to zero before continuing. 1315 */ 1316 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1317 1318 /* Enable CORB error reporting */ 1319#if 0 1320 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1321#endif 1322} 1323 1324/**************************************************************************** 1325 * void hdac_rirb_init(struct hdac_softc *) 1326 * 1327 * Initialize the rirb registers for operations but do not start it up yet. 1328 * The RIRB engine must not be running when this function is called. 1329 ****************************************************************************/ 1330static void 1331hdac_rirb_init(struct hdac_softc *sc) 1332{ 1333 uint8_t rirbsize; 1334 uint64_t rirbpaddr; 1335 1336 /* Setup the RIRB size. */ 1337 switch (sc->rirb_size) { 1338 case 256: 1339 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1340 break; 1341 case 16: 1342 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1343 break; 1344 case 2: 1345 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1346 break; 1347 default: 1348 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1349 } 1350 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1351 1352 /* Setup the RIRB Address in the hdac */ 1353 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1354 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1355 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1356 1357 /* Setup the WP and RP */ 1358 sc->rirb_rp = 0; 1359 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1360 1361 if (sc->polling == 0) { 1362 /* Setup the interrupt threshold */ 1363 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1364 1365 /* Enable Overrun and response received reporting */ 1366#if 0 1367 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1368 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1369#else 1370 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1371#endif 1372 } 1373 1374 /* 1375 * Make sure that the Host CPU cache doesn't contain any dirty 1376 * cache lines that falls in the rirb. If I understood correctly, it 1377 * should be sufficient to do this only once as the rirb is purely 1378 * read-only from now on. 1379 */ 1380 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1381 BUS_DMASYNC_PREREAD); 1382} 1383 1384/**************************************************************************** 1385 * void hdac_corb_start(hdac_softc *) 1386 * 1387 * Startup the corb DMA engine 1388 ****************************************************************************/ 1389static void 1390hdac_corb_start(struct hdac_softc *sc) 1391{ 1392 uint32_t corbctl; 1393 1394 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1395 corbctl |= HDAC_CORBCTL_CORBRUN; 1396 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1397} 1398 1399/**************************************************************************** 1400 * void hdac_rirb_start(hdac_softc *) 1401 * 1402 * Startup the rirb DMA engine 1403 ****************************************************************************/ 1404static void 1405hdac_rirb_start(struct hdac_softc *sc) 1406{ 1407 uint32_t rirbctl; 1408 1409 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1410 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1411 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1412} 1413 1414 1415/**************************************************************************** 1416 * void hdac_scan_codecs(struct hdac_softc *) 1417 * 1418 * Scan the bus for available codecs. 1419 ****************************************************************************/ 1420static void 1421hdac_scan_codecs(struct hdac_softc *sc) 1422{ 1423 struct hdac_codec *codec; 1424 int i; 1425 uint16_t statests; 1426 1427 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1428 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1429 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1430 /* We have found a codec. */ 1431 hdac_unlock(sc); 1432 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1433 M_HDAC, M_ZERO | M_NOWAIT); 1434 hdac_lock(sc); 1435 if (codec == NULL) { 1436 device_printf(sc->dev, 1437 "Unable to allocate memory for codec\n"); 1438 continue; 1439 } 1440 codec->commands = NULL; 1441 codec->responses_received = 0; 1442 codec->verbs_sent = 0; 1443 codec->sc = sc; 1444 codec->cad = i; 1445 sc->codecs[i] = codec; 1446 if (hdac_probe_codec(codec) != 0) 1447 break; 1448 } 1449 } 1450 /* All codecs have been probed, now try to attach drivers to them */ 1451 /* bus_generic_attach(sc->dev); */ 1452} 1453 1454/**************************************************************************** 1455 * void hdac_probe_codec(struct hdac_softc *, int) 1456 * 1457 * Probe a the given codec_id for available function groups. 1458 ****************************************************************************/ 1459static int 1460hdac_probe_codec(struct hdac_codec *codec) 1461{ 1462 struct hdac_softc *sc = codec->sc; 1463 struct hdac_devinfo *devinfo; 1464 uint32_t vendorid, revisionid, subnode; 1465 int startnode; 1466 int endnode; 1467 int i; 1468 nid_t cad = codec->cad; 1469 1470 HDA_BOOTVERBOSE( 1471 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1472 ); 1473 vendorid = hdac_command(sc, 1474 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1475 cad); 1476 revisionid = hdac_command(sc, 1477 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1478 cad); 1479 subnode = hdac_command(sc, 1480 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1481 cad); 1482 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1483 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1484 1485 HDA_BOOTVERBOSE( 1486 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1487 startnode, endnode); 1488 ); 1489 for (i = startnode; i < endnode; i++) { 1490 devinfo = hdac_probe_function(codec, i); 1491 if (devinfo != NULL) { 1492 /* XXX Ignore other FG. */ 1493 devinfo->vendor_id = 1494 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1495 devinfo->device_id = 1496 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1497 devinfo->revision_id = 1498 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1499 devinfo->stepping_id = 1500 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1501 HDA_BOOTVERBOSE( 1502 device_printf(sc->dev, 1503 "HDA_DEBUG: \tFound AFG nid=%d " 1504 "[startnode=%d endnode=%d]\n", 1505 devinfo->nid, startnode, endnode); 1506 ); 1507 return (1); 1508 } 1509 } 1510 1511 HDA_BOOTVERBOSE( 1512 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1513 ); 1514 return (0); 1515} 1516 1517static struct hdac_devinfo * 1518hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1519{ 1520 struct hdac_softc *sc = codec->sc; 1521 struct hdac_devinfo *devinfo; 1522 uint32_t fctgrptype; 1523 nid_t cad = codec->cad; 1524 1525 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1526 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1527 1528 /* XXX For now, ignore other FG. */ 1529 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1530 return (NULL); 1531 1532 hdac_unlock(sc); 1533 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1534 M_NOWAIT | M_ZERO); 1535 hdac_lock(sc); 1536 if (devinfo == NULL) { 1537 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1538 __func__); 1539 return (NULL); 1540 } 1541 1542 devinfo->nid = nid; 1543 devinfo->node_type = fctgrptype; 1544 devinfo->codec = codec; 1545 1546 hdac_add_child(sc, devinfo); 1547 1548 return (devinfo); 1549} 1550 1551static void 1552hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1553{ 1554 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1555 device_set_ivars(devinfo->dev, (void *)devinfo); 1556 /* XXX - Print more information when booting verbose??? */ 1557} 1558 1559static void 1560hdac_widget_connection_parse(struct hdac_widget *w) 1561{ 1562 struct hdac_softc *sc = w->devinfo->codec->sc; 1563 uint32_t res; 1564 int i, j, max, found, entnum, cnid; 1565 nid_t cad = w->devinfo->codec->cad; 1566 nid_t nid = w->nid; 1567 1568 res = hdac_command(sc, 1569 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1570 1571 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1572 1573 if (w->nconns < 1) 1574 return; 1575 1576 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1577 res = 0; 1578 i = 0; 1579 found = 0; 1580 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1581 1582 while (i < w->nconns) { 1583 res = hdac_command(sc, 1584 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1585 for (j = 0; j < entnum; j++) { 1586 cnid = res; 1587 cnid >>= (32 / entnum) * j; 1588 cnid &= (1 << (32 / entnum)) - 1; 1589 if (cnid == 0) 1590 continue; 1591 if (found > max) { 1592 device_printf(sc->dev, 1593 "node %d: Adding %d: " 1594 "Max connection reached!\n", 1595 nid, cnid); 1596 continue; 1597 } 1598 w->conns[found++] = cnid; 1599 } 1600 i += entnum; 1601 } 1602 1603 HDA_BOOTVERBOSE( 1604 if (w->nconns != found) { 1605 device_printf(sc->dev, 1606 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1607 "length=%d != found=%d\n", 1608 nid, w->nconns, found); 1609 } 1610 ); 1611} 1612 1613static uint32_t 1614hdac_widget_pin_getconfig(struct hdac_widget *w) 1615{ 1616 struct hdac_softc *sc; 1617 uint32_t config, id; 1618 nid_t cad, nid; 1619 1620 sc = w->devinfo->codec->sc; 1621 cad = w->devinfo->codec->cad; 1622 nid = w->nid; 1623 id = hdac_codec_id(w->devinfo); 1624 1625 config = hdac_command(sc, 1626 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1627 cad); 1628 /* 1629 * XXX REWRITE!!!! Don't argue! 1630 */ 1631 if (id == HDA_CODEC_ALC880 && 1632 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1633 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1634 /* 1635 * Super broken BIOS 1636 */ 1637 switch (nid) { 1638 case 20: 1639 break; 1640 case 21: 1641 break; 1642 case 22: 1643 break; 1644 case 23: 1645 break; 1646 case 24: /* MIC1 */ 1647 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1648 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1649 break; 1650 case 25: /* XXX MIC2 */ 1651 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1652 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1653 break; 1654 case 26: /* LINE1 */ 1655 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1656 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1657 break; 1658 case 27: /* XXX LINE2 */ 1659 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1660 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1661 break; 1662 case 28: /* CD */ 1663 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1664 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1665 break; 1666 case 30: 1667 break; 1668 case 31: 1669 break; 1670 default: 1671 break; 1672 } 1673 } 1674 1675 return (config); 1676} 1677 1678static void 1679hdac_widget_pin_parse(struct hdac_widget *w) 1680{ 1681 struct hdac_softc *sc = w->devinfo->codec->sc; 1682 uint32_t config, pincap; 1683 char *devstr, *connstr; 1684 nid_t cad = w->devinfo->codec->cad; 1685 nid_t nid = w->nid; 1686 1687 config = hdac_widget_pin_getconfig(w); 1688 w->wclass.pin.config = config; 1689 1690 pincap = hdac_command(sc, 1691 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1692 w->wclass.pin.cap = pincap; 1693 1694 w->wclass.pin.ctrl = hdac_command(sc, 1695 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1696 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1697 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1698 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1699 1700 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1701 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1702 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1703 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1704 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1705 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1706 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1707 w->param.eapdbtl = hdac_command(sc, 1708 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1709 w->param.eapdbtl &= 0x7; 1710 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1711 } else 1712 w->param.eapdbtl = HDAC_INVALID; 1713 1714 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1715 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1716 devstr = "line out"; 1717 break; 1718 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1719 devstr = "speaker"; 1720 break; 1721 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1722 devstr = "headphones out"; 1723 break; 1724 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1725 devstr = "CD"; 1726 break; 1727 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1728 devstr = "SPDIF out"; 1729 break; 1730 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1731 devstr = "digital (other) out"; 1732 break; 1733 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1734 devstr = "modem, line side"; 1735 break; 1736 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1737 devstr = "modem, handset side"; 1738 break; 1739 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1740 devstr = "line in"; 1741 break; 1742 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1743 devstr = "AUX"; 1744 break; 1745 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1746 devstr = "Mic in"; 1747 break; 1748 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1749 devstr = "telephony"; 1750 break; 1751 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1752 devstr = "SPDIF in"; 1753 break; 1754 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1755 devstr = "digital (other) in"; 1756 break; 1757 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1758 devstr = "other"; 1759 break; 1760 default: 1761 devstr = "unknown"; 1762 break; 1763 } 1764 1765 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1766 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1767 connstr = "jack"; 1768 break; 1769 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1770 connstr = "none"; 1771 break; 1772 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1773 connstr = "fixed"; 1774 break; 1775 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1776 connstr = "jack / fixed"; 1777 break; 1778 default: 1779 connstr = "unknown"; 1780 break; 1781 } 1782 1783 strlcat(w->name, ": ", sizeof(w->name)); 1784 strlcat(w->name, devstr, sizeof(w->name)); 1785 strlcat(w->name, " (", sizeof(w->name)); 1786 strlcat(w->name, connstr, sizeof(w->name)); 1787 strlcat(w->name, ")", sizeof(w->name)); 1788} 1789 1790static void 1791hdac_widget_parse(struct hdac_widget *w) 1792{ 1793 struct hdac_softc *sc = w->devinfo->codec->sc; 1794 uint32_t wcap, cap; 1795 char *typestr; 1796 nid_t cad = w->devinfo->codec->cad; 1797 nid_t nid = w->nid; 1798 1799 wcap = hdac_command(sc, 1800 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1801 cad); 1802 w->param.widget_cap = wcap; 1803 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1804 1805 switch (w->type) { 1806 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1807 typestr = "audio output"; 1808 break; 1809 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1810 typestr = "audio input"; 1811 break; 1812 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1813 typestr = "audio mixer"; 1814 break; 1815 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1816 typestr = "audio selector"; 1817 break; 1818 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1819 typestr = "pin"; 1820 break; 1821 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1822 typestr = "power widget"; 1823 break; 1824 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1825 typestr = "volume widget"; 1826 break; 1827 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1828 typestr = "beep widget"; 1829 break; 1830 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1831 typestr = "vendor widget"; 1832 break; 1833 default: 1834 typestr = "unknown type"; 1835 break; 1836 } 1837 1838 strlcpy(w->name, typestr, sizeof(w->name)); 1839 1840 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1841 hdac_command(sc, 1842 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1843 cad); 1844 DELAY(1000); 1845 } 1846 1847 hdac_widget_connection_parse(w); 1848 1849 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1850 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1851 w->param.outamp_cap = 1852 hdac_command(sc, 1853 HDA_CMD_GET_PARAMETER(cad, nid, 1854 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1855 else 1856 w->param.outamp_cap = 1857 w->devinfo->function.audio.outamp_cap; 1858 } else 1859 w->param.outamp_cap = 0; 1860 1861 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1862 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1863 w->param.inamp_cap = 1864 hdac_command(sc, 1865 HDA_CMD_GET_PARAMETER(cad, nid, 1866 HDA_PARAM_INPUT_AMP_CAP), cad); 1867 else 1868 w->param.inamp_cap = 1869 w->devinfo->function.audio.inamp_cap; 1870 } else 1871 w->param.inamp_cap = 0; 1872 1873 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1874 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1875 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1876 cap = hdac_command(sc, 1877 HDA_CMD_GET_PARAMETER(cad, nid, 1878 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1879 w->param.supp_stream_formats = (cap != 0) ? cap : 1880 w->devinfo->function.audio.supp_stream_formats; 1881 cap = hdac_command(sc, 1882 HDA_CMD_GET_PARAMETER(cad, nid, 1883 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1884 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1885 w->devinfo->function.audio.supp_pcm_size_rate; 1886 } else { 1887 w->param.supp_stream_formats = 1888 w->devinfo->function.audio.supp_stream_formats; 1889 w->param.supp_pcm_size_rate = 1890 w->devinfo->function.audio.supp_pcm_size_rate; 1891 } 1892 } else { 1893 w->param.supp_stream_formats = 0; 1894 w->param.supp_pcm_size_rate = 0; 1895 } 1896 1897 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1898 hdac_widget_pin_parse(w); 1899} 1900 1901static struct hdac_widget * 1902hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1903{ 1904 if (devinfo == NULL || devinfo->widget == NULL || 1905 nid < devinfo->startnode || nid >= devinfo->endnode) 1906 return (NULL); 1907 return (&devinfo->widget[nid - devinfo->startnode]); 1908} 1909 1910static __inline int 1911hda_poll_channel(struct hdac_chan *ch) 1912{ 1913 uint32_t sz, delta; 1914 volatile uint32_t ptr; 1915 1916 if (ch->active == 0) 1917 return (0); 1918 1919 sz = ch->blksz * ch->blkcnt; 1920 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1921 ch->ptr = ptr; 1922 ptr %= sz; 1923 ptr &= ~(ch->blksz - 1); 1924 delta = (sz + ptr - ch->prevptr) % sz; 1925 1926 if (delta < ch->blksz) 1927 return (0); 1928 1929 ch->prevptr = ptr; 1930 1931 return (1); 1932} 1933 1934#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1935 1936static void 1937hda_poll_callback(void *arg) 1938{ 1939 struct hdac_softc *sc = arg; 1940 uint32_t trigger = 0; 1941 1942 if (sc == NULL) 1943 return; 1944 1945 hdac_lock(sc); 1946 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 1947 hdac_unlock(sc); 1948 return; 1949 } 1950 1951 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 1952 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 1953 1954 /* XXX */ 1955 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 1956 hda_poll_callback, sc); 1957 1958 hdac_unlock(sc); 1959 1960 if (trigger & 1) 1961 chn_intr(sc->play.c); 1962 if (trigger & 2) 1963 chn_intr(sc->rec.c); 1964} 1965 1966static int 1967hdac_rirb_flush(struct hdac_softc *sc) 1968{ 1969 struct hdac_rirb *rirb_base, *rirb; 1970 struct hdac_codec *codec; 1971 struct hdac_command_list *commands; 1972 nid_t cad; 1973 uint32_t resp; 1974 uint8_t rirbwp; 1975 int ret = 0; 1976 1977 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1978 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 1979 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1980 BUS_DMASYNC_POSTREAD); 1981 1982 while (sc->rirb_rp != rirbwp) { 1983 sc->rirb_rp++; 1984 sc->rirb_rp %= sc->rirb_size; 1985 rirb = &rirb_base[sc->rirb_rp]; 1986 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 1987 if (cad < 0 || cad >= HDAC_CODEC_MAX || 1988 sc->codecs[cad] == NULL) 1989 continue; 1990 resp = rirb->response; 1991 codec = sc->codecs[cad]; 1992 commands = codec->commands; 1993 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 1994 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 1995 ((resp >> 26) & 0xffff); 1996 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 1997 } else if (commands != NULL && commands->num_commands > 0 && 1998 codec->responses_received < commands->num_commands) 1999 commands->responses[codec->responses_received++] = 2000 resp; 2001 ret++; 2002 } 2003 2004 return (ret); 2005} 2006 2007static int 2008hdac_unsolq_flush(struct hdac_softc *sc) 2009{ 2010 nid_t cad; 2011 uint32_t tag; 2012 int ret = 0; 2013 2014 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2015 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2016 while (sc->unsolq_rp != sc->unsolq_wp) { 2017 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2018 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2019 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2020 hdac_unsolicited_handler(sc->codecs[cad], tag); 2021 ret++; 2022 } 2023 sc->unsolq_st = HDAC_UNSOLQ_READY; 2024 } 2025 2026 return (ret); 2027} 2028 2029static void 2030hdac_poll_callback(void *arg) 2031{ 2032 struct hdac_softc *sc = arg; 2033 if (sc == NULL) 2034 return; 2035 2036 hdac_lock(sc); 2037 if (sc->polling == 0) { 2038 hdac_unlock(sc); 2039 return; 2040 } 2041 hdac_rirb_flush(sc); 2042 hdac_unsolq_flush(sc); 2043 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2044 hdac_poll_callback, sc); 2045 hdac_unlock(sc); 2046} 2047 2048static void 2049hdac_stream_stop(struct hdac_chan *ch) 2050{ 2051 struct hdac_softc *sc = ch->devinfo->codec->sc; 2052 uint32_t ctl; 2053 2054 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2055 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2056 HDAC_SDCTL_RUN); 2057 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2058 2059 ch->active = 0; 2060 2061 if (sc->polling != 0) { 2062 int pollticks; 2063 2064 if (hda_chan_active(sc) == 0) { 2065 callout_stop(&sc->poll_hda); 2066 sc->poll_ticks = 1; 2067 } else { 2068 if (sc->play.active != 0) 2069 ch = &sc->play; 2070 else 2071 ch = &sc->rec; 2072 pollticks = ((uint64_t)hz * ch->blksz) / 2073 ((uint64_t)sndbuf_getbps(ch->b) * 2074 sndbuf_getspd(ch->b)); 2075 pollticks >>= 2; 2076 if (pollticks > hz) 2077 pollticks = hz; 2078 if (pollticks < 1) { 2079 HDA_BOOTVERBOSE( 2080 device_printf(sc->dev, 2081 "%s: pollticks=%d < 1 !\n", 2082 __func__, pollticks); 2083 ); 2084 pollticks = 1; 2085 } 2086 if (pollticks > sc->poll_ticks) { 2087 HDA_BOOTVERBOSE( 2088 device_printf(sc->dev, 2089 "%s: pollticks %d -> %d\n", 2090 __func__, sc->poll_ticks, 2091 pollticks); 2092 ); 2093 sc->poll_ticks = pollticks; 2094 callout_reset(&sc->poll_hda, 1, 2095 hda_poll_callback, sc); 2096 } 2097 } 2098 } else { 2099 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2100 ctl &= ~(1 << (ch->off >> 5)); 2101 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2102 } 2103} 2104 2105static void 2106hdac_stream_start(struct hdac_chan *ch) 2107{ 2108 struct hdac_softc *sc = ch->devinfo->codec->sc; 2109 uint32_t ctl; 2110 2111 if (sc->polling != 0) { 2112 int pollticks; 2113 2114 pollticks = ((uint64_t)hz * ch->blksz) / 2115 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2116 pollticks >>= 2; 2117 if (pollticks > hz) 2118 pollticks = hz; 2119 if (pollticks < 1) { 2120 HDA_BOOTVERBOSE( 2121 device_printf(sc->dev, 2122 "%s: pollticks=%d < 1 !\n", 2123 __func__, pollticks); 2124 ); 2125 pollticks = 1; 2126 } 2127 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2128 HDA_BOOTVERBOSE( 2129 if (hda_chan_active(sc) == 0) { 2130 device_printf(sc->dev, 2131 "%s: pollticks=%d\n", 2132 __func__, pollticks); 2133 } else { 2134 device_printf(sc->dev, 2135 "%s: pollticks %d -> %d\n", 2136 __func__, sc->poll_ticks, 2137 pollticks); 2138 } 2139 ); 2140 sc->poll_ticks = pollticks; 2141 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2142 sc); 2143 } 2144 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2145 ctl |= HDAC_SDCTL_RUN; 2146 } else { 2147 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2148 ctl |= 1 << (ch->off >> 5); 2149 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2150 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2151 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2152 HDAC_SDCTL_RUN; 2153 } 2154 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2155 2156 ch->active = 1; 2157} 2158 2159static void 2160hdac_stream_reset(struct hdac_chan *ch) 2161{ 2162 struct hdac_softc *sc = ch->devinfo->codec->sc; 2163 int timeout = 1000; 2164 int to = timeout; 2165 uint32_t ctl; 2166 2167 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2168 ctl |= HDAC_SDCTL_SRST; 2169 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2170 do { 2171 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2172 if (ctl & HDAC_SDCTL_SRST) 2173 break; 2174 DELAY(10); 2175 } while (--to); 2176 if (!(ctl & HDAC_SDCTL_SRST)) { 2177 device_printf(sc->dev, "timeout in reset\n"); 2178 } 2179 ctl &= ~HDAC_SDCTL_SRST; 2180 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2181 to = timeout; 2182 do { 2183 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2184 if (!(ctl & HDAC_SDCTL_SRST)) 2185 break; 2186 DELAY(10); 2187 } while (--to); 2188 if (ctl & HDAC_SDCTL_SRST) 2189 device_printf(sc->dev, "can't reset!\n"); 2190} 2191 2192static void 2193hdac_stream_setid(struct hdac_chan *ch) 2194{ 2195 struct hdac_softc *sc = ch->devinfo->codec->sc; 2196 uint32_t ctl; 2197 2198 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2199 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2200 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2201 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2202} 2203 2204static void 2205hdac_bdl_setup(struct hdac_chan *ch) 2206{ 2207 struct hdac_softc *sc = ch->devinfo->codec->sc; 2208 struct hdac_bdle *bdle; 2209 uint64_t addr; 2210 uint32_t blksz, blkcnt; 2211 int i; 2212 2213 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2214 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2215 2216 if (sc->polling != 0) { 2217 blksz = ch->blksz * ch->blkcnt; 2218 blkcnt = 1; 2219 } else { 2220 blksz = ch->blksz; 2221 blkcnt = ch->blkcnt; 2222 } 2223 2224 for (i = 0; i < blkcnt; i++, bdle++) { 2225 bdle->addrl = (uint32_t)addr; 2226 bdle->addrh = (uint32_t)(addr >> 32); 2227 bdle->len = blksz; 2228 bdle->ioc = 1 ^ sc->polling; 2229 addr += blksz; 2230 } 2231 2232 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2233 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2234 addr = ch->bdl_dma.dma_paddr; 2235 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2236 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2237} 2238 2239static int 2240hdac_bdl_alloc(struct hdac_chan *ch) 2241{ 2242 struct hdac_softc *sc = ch->devinfo->codec->sc; 2243 int rc; 2244 2245 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2246 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2247 if (rc) { 2248 device_printf(sc->dev, "can't alloc bdl\n"); 2249 return (rc); 2250 } 2251 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2252 2253 return (0); 2254} 2255 2256static void 2257hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2258 int index, int lmute, int rmute, 2259 int left, int right, int dir) 2260{ 2261 uint16_t v = 0; 2262 2263 if (sc == NULL) 2264 return; 2265 2266 if (left != right || lmute != rmute) { 2267 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2268 (lmute << 7) | left; 2269 hdac_command(sc, 2270 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2271 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2272 (rmute << 7) | right; 2273 } else 2274 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2275 (lmute << 7) | left; 2276 2277 hdac_command(sc, 2278 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2279} 2280 2281static void 2282hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2283 int left, int right) 2284{ 2285 struct hdac_softc *sc; 2286 nid_t nid, cad; 2287 int lmute, rmute; 2288 2289 if (ctl == NULL || ctl->widget == NULL || 2290 ctl->widget->devinfo == NULL || 2291 ctl->widget->devinfo->codec == NULL || 2292 ctl->widget->devinfo->codec->sc == NULL) 2293 return; 2294 2295 sc = ctl->widget->devinfo->codec->sc; 2296 cad = ctl->widget->devinfo->codec->cad; 2297 nid = ctl->widget->nid; 2298 2299 if (mute == HDA_AMP_MUTE_DEFAULT) { 2300 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2301 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2302 } else { 2303 lmute = HDA_AMP_LEFT_MUTED(mute); 2304 rmute = HDA_AMP_RIGHT_MUTED(mute); 2305 } 2306 2307 if (ctl->dir & HDA_CTL_OUT) 2308 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2309 lmute, rmute, left, right, 0); 2310 if (ctl->dir & HDA_CTL_IN) 2311 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2312 lmute, rmute, left, right, 1); 2313 ctl->left = left; 2314 ctl->right = right; 2315} 2316 2317static void 2318hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2319{ 2320 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2321 return; 2322 hdac_command(w->devinfo->codec->sc, 2323 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2324 w->nid, index), w->devinfo->codec->cad); 2325 w->selconn = index; 2326} 2327 2328 2329/**************************************************************************** 2330 * uint32_t hdac_command_sendone_internal 2331 * 2332 * Wrapper function that sends only one command to a given codec 2333 ****************************************************************************/ 2334static uint32_t 2335hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2336{ 2337 struct hdac_command_list cl; 2338 uint32_t response = HDAC_INVALID; 2339 2340 if (!hdac_lockowned(sc)) 2341 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2342 cl.num_commands = 1; 2343 cl.verbs = &verb; 2344 cl.responses = &response; 2345 2346 hdac_command_send_internal(sc, &cl, cad); 2347 2348 return (response); 2349} 2350 2351/**************************************************************************** 2352 * hdac_command_send_internal 2353 * 2354 * Send a command list to the codec via the corb. We queue as much verbs as 2355 * we can and msleep on the codec. When the interrupt get the responses 2356 * back from the rirb, it will wake us up so we can queue the remaining verbs 2357 * if any. 2358 ****************************************************************************/ 2359static void 2360hdac_command_send_internal(struct hdac_softc *sc, 2361 struct hdac_command_list *commands, nid_t cad) 2362{ 2363 struct hdac_codec *codec; 2364 int corbrp; 2365 uint32_t *corb; 2366 int timeout; 2367 int retry = 10; 2368 struct hdac_rirb *rirb_base; 2369 2370 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2371 commands->num_commands < 1) 2372 return; 2373 2374 codec = sc->codecs[cad]; 2375 codec->commands = commands; 2376 codec->responses_received = 0; 2377 codec->verbs_sent = 0; 2378 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2379 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2380 2381 do { 2382 if (codec->verbs_sent != commands->num_commands) { 2383 /* Queue as many verbs as possible */ 2384 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2385 bus_dmamap_sync(sc->corb_dma.dma_tag, 2386 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2387 while (codec->verbs_sent != commands->num_commands && 2388 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2389 sc->corb_wp++; 2390 sc->corb_wp %= sc->corb_size; 2391 corb[sc->corb_wp] = 2392 commands->verbs[codec->verbs_sent++]; 2393 } 2394 2395 /* Send the verbs to the codecs */ 2396 bus_dmamap_sync(sc->corb_dma.dma_tag, 2397 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2398 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2399 } 2400 2401 timeout = 1000; 2402 while (hdac_rirb_flush(sc) == 0 && --timeout) 2403 DELAY(10); 2404 } while ((codec->verbs_sent != commands->num_commands || 2405 codec->responses_received != commands->num_commands) && --retry); 2406 2407 if (retry == 0) 2408 device_printf(sc->dev, 2409 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2410 __func__, commands->num_commands, codec->verbs_sent, 2411 codec->responses_received); 2412 2413 codec->commands = NULL; 2414 codec->responses_received = 0; 2415 codec->verbs_sent = 0; 2416 2417 hdac_unsolq_flush(sc); 2418} 2419 2420 2421/**************************************************************************** 2422 * Device Methods 2423 ****************************************************************************/ 2424 2425/**************************************************************************** 2426 * int hdac_probe(device_t) 2427 * 2428 * Probe for the presence of an hdac. If none is found, check for a generic 2429 * match using the subclass of the device. 2430 ****************************************************************************/ 2431static int 2432hdac_probe(device_t dev) 2433{ 2434 int i, result; 2435 uint32_t model; 2436 uint16_t class, subclass; 2437 char desc[64]; 2438 2439 model = (uint32_t)pci_get_device(dev) << 16; 2440 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2441 class = pci_get_class(dev); 2442 subclass = pci_get_subclass(dev); 2443 2444 bzero(desc, sizeof(desc)); 2445 result = ENXIO; 2446 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2447 if (hdac_devices[i].model == model) { 2448 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2449 result = BUS_PROBE_DEFAULT; 2450 break; 2451 } 2452 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2453 class == PCIC_MULTIMEDIA && 2454 subclass == PCIS_MULTIMEDIA_HDA) { 2455 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2456 result = BUS_PROBE_GENERIC; 2457 break; 2458 } 2459 } 2460 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2461 subclass == PCIS_MULTIMEDIA_HDA) { 2462 strlcpy(desc, "Generic", sizeof(desc)); 2463 result = BUS_PROBE_GENERIC; 2464 } 2465 if (result != ENXIO) { 2466 strlcat(desc, " High Definition Audio Controller", 2467 sizeof(desc)); 2468 device_set_desc_copy(dev, desc); 2469 } 2470 2471 return (result); 2472} 2473 2474static void * 2475hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2476 struct pcm_channel *c, int dir) 2477{ 2478 struct hdac_devinfo *devinfo = data; 2479 struct hdac_softc *sc = devinfo->codec->sc; 2480 struct hdac_chan *ch; 2481 2482 hdac_lock(sc); 2483 if (dir == PCMDIR_PLAY) { 2484 ch = &sc->play; 2485 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2486 ch->dir = PCMDIR_PLAY; 2487 ch->sid = ++sc->streamcnt; 2488 devinfo->function.audio.playcnt++; 2489 } else { 2490 ch = &sc->rec; 2491 ch->off = devinfo->function.audio.reccnt << 5; 2492 ch->dir = PCMDIR_REC; 2493 ch->sid = ++sc->streamcnt; 2494 devinfo->function.audio.reccnt++; 2495 } 2496 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2497 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2498 ch->pcmrates[0] = 48000; 2499 ch->pcmrates[1] = 0; 2500 } 2501 ch->b = b; 2502 ch->c = c; 2503 ch->devinfo = devinfo; 2504 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2505 ch->blkcnt = sc->chan_blkcnt; 2506 hdac_unlock(sc); 2507 2508 if (hdac_bdl_alloc(ch) != 0) { 2509 ch->blkcnt = 0; 2510 return (NULL); 2511 } 2512 2513 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2514 return (NULL); 2515 2516 hdac_dma_nocache(ch->b->buf); 2517 2518 return (ch); 2519} 2520 2521static int 2522hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2523{ 2524 struct hdac_chan *ch = data; 2525 int i; 2526 2527 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2528 if (format == ch->caps.fmtlist[i]) { 2529 ch->fmt = format; 2530 return (0); 2531 } 2532 } 2533 2534 return (EINVAL); 2535} 2536 2537static int 2538hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2539{ 2540 struct hdac_chan *ch = data; 2541 uint32_t spd = 0, threshold; 2542 int i; 2543 2544 for (i = 0; ch->pcmrates[i] != 0; i++) { 2545 spd = ch->pcmrates[i]; 2546 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2547 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2548 if (speed < threshold) 2549 break; 2550 } 2551 2552 if (spd == 0) /* impossible */ 2553 ch->spd = 48000; 2554 else 2555 ch->spd = spd; 2556 2557 return (ch->spd); 2558} 2559 2560static void 2561hdac_stream_setup(struct hdac_chan *ch) 2562{ 2563 struct hdac_softc *sc = ch->devinfo->codec->sc; 2564 int i; 2565 nid_t cad = ch->devinfo->codec->cad; 2566 uint16_t fmt; 2567 2568 fmt = 0; 2569 if (ch->fmt & AFMT_S16_LE) 2570 fmt |= ch->bit16 << 4; 2571 else if (ch->fmt & AFMT_S32_LE) 2572 fmt |= ch->bit32 << 4; 2573 else 2574 fmt |= 1 << 4; 2575 2576 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2577 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2578 fmt |= hda_rate_tab[i].base; 2579 fmt |= hda_rate_tab[i].mul; 2580 fmt |= hda_rate_tab[i].div; 2581 break; 2582 } 2583 } 2584 2585 if (ch->fmt & AFMT_STEREO) 2586 fmt |= 1; 2587 2588 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2589 2590 for (i = 0; ch->io[i] != -1; i++) { 2591 HDA_BOOTVERBOSE( 2592 device_printf(sc->dev, 2593 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2594 "fmt=0x%08x\n", 2595 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2596 ch->io[i], fmt); 2597 ); 2598 hdac_command(sc, 2599 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2600 hdac_command(sc, 2601 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2602 ch->sid << 4), cad); 2603 } 2604} 2605 2606static int 2607hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2608{ 2609 struct hdac_chan *ch = data; 2610 struct hdac_softc *sc = ch->devinfo->codec->sc; 2611 2612 blksz &= ~0x7f; 2613 if (blksz < 0x80) 2614 blksz = 0x80; 2615 2616 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2617 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2618 2619 if ((sndbuf_getblksz(ch->b) != blksz || 2620 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2621 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2622 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2623 __func__, blksz, ch->blkcnt); 2624 2625 ch->blksz = sndbuf_getblksz(ch->b); 2626 2627 return (ch->blksz); 2628} 2629 2630static void 2631hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2632{ 2633 struct hdac_devinfo *devinfo = ch->devinfo; 2634 nid_t cad = devinfo->codec->cad; 2635 int i; 2636 2637 hdac_stream_stop(ch); 2638 2639 for (i = 0; ch->io[i] != -1; i++) { 2640 hdac_command(sc, 2641 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2642 0), cad); 2643 } 2644} 2645 2646static void 2647hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2648{ 2649 ch->ptr = 0; 2650 ch->prevptr = 0; 2651 hdac_stream_stop(ch); 2652 hdac_stream_reset(ch); 2653 hdac_bdl_setup(ch); 2654 hdac_stream_setid(ch); 2655 hdac_stream_setup(ch); 2656 hdac_stream_start(ch); 2657} 2658 2659static int 2660hdac_channel_trigger(kobj_t obj, void *data, int go) 2661{ 2662 struct hdac_chan *ch = data; 2663 struct hdac_softc *sc = ch->devinfo->codec->sc; 2664 2665 hdac_lock(sc); 2666 switch (go) { 2667 case PCMTRIG_START: 2668 hdac_channel_start(sc, ch); 2669 break; 2670 case PCMTRIG_STOP: 2671 case PCMTRIG_ABORT: 2672 hdac_channel_stop(sc, ch); 2673 break; 2674 } 2675 hdac_unlock(sc); 2676 2677 return (0); 2678} 2679 2680static int 2681hdac_channel_getptr(kobj_t obj, void *data) 2682{ 2683 struct hdac_chan *ch = data; 2684 struct hdac_softc *sc = ch->devinfo->codec->sc; 2685 uint32_t ptr; 2686 2687 hdac_lock(sc); 2688 if (sc->polling != 0) 2689 ptr = ch->ptr; 2690 else 2691 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2692 hdac_unlock(sc); 2693 2694 /* 2695 * Round to available space and force 128 bytes aligment. 2696 */ 2697 ptr %= ch->blksz * ch->blkcnt; 2698 ptr &= ~0x7f; 2699 2700 return (ptr); 2701} 2702 2703static struct pcmchan_caps * 2704hdac_channel_getcaps(kobj_t obj, void *data) 2705{ 2706 return (&((struct hdac_chan *)data)->caps); 2707} 2708 2709static kobj_method_t hdac_channel_methods[] = { 2710 KOBJMETHOD(channel_init, hdac_channel_init), 2711 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2712 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2713 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2714 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2715 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2716 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2717 { 0, 0 } 2718}; 2719CHANNEL_DECLARE(hdac_channel); 2720 2721static int 2722hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2723{ 2724 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2725 struct hdac_softc *sc = devinfo->codec->sc; 2726 struct hdac_widget *w, *cw; 2727 struct hdac_audio_ctl *ctl; 2728 uint32_t mask, recmask, id; 2729 int i, j, softpcmvol; 2730 nid_t cad; 2731 2732 hdac_lock(sc); 2733 2734 mask = 0; 2735 recmask = 0; 2736 2737 id = hdac_codec_id(devinfo); 2738 cad = devinfo->codec->cad; 2739 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2740 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2741 sc->pci_subvendor) && 2742 hdac_hp_switch[i].id == id)) 2743 continue; 2744 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2745 if (w != NULL && w->enable != 0 2746 && w->type == 2747 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2748 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2749 hdac_command(sc, 2750 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2751 w->nid, 2752 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2753 HDAC_UNSOLTAG_EVENT_HP), cad); 2754 hdac_hp_switch_handler(devinfo); 2755 HDA_BOOTVERBOSE( 2756 device_printf(sc->dev, 2757 "HDA_DEBUG: Enabling headphone/speaker " 2758 "audio routing switching:\n"); 2759 device_printf(sc->dev, 2760 "HDA_DEBUG: \tindex=%d nid=%d " 2761 "pci_subvendor=0x%08x " 2762 "codec=0x%08x\n", 2763 i, w->nid, sc->pci_subvendor, id); 2764 ); 2765 } 2766 break; 2767 } 2768 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2769 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2770 sc->pci_subvendor) && 2771 hdac_eapd_switch[i].id == id)) 2772 continue; 2773 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2774 if (w == NULL || w->enable == 0) 2775 break; 2776 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2777 w->param.eapdbtl == HDAC_INVALID) 2778 break; 2779 mask |= SOUND_MASK_OGAIN; 2780 break; 2781 } 2782 2783 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2784 w = hdac_widget_get(devinfo, i); 2785 if (w == NULL || w->enable == 0) 2786 continue; 2787 mask |= w->ctlflags; 2788 if (!(w->pflags & HDA_ADC_RECSEL)) 2789 continue; 2790 for (j = 0; j < w->nconns; j++) { 2791 cw = hdac_widget_get(devinfo, w->conns[j]); 2792 if (cw == NULL || cw->enable == 0) 2793 continue; 2794 recmask |= cw->ctlflags; 2795 } 2796 } 2797 2798 if (!(mask & SOUND_MASK_PCM)) { 2799 softpcmvol = 1; 2800 mask |= SOUND_MASK_PCM; 2801 } else 2802 softpcmvol = (devinfo->function.audio.quirks & 2803 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2804 2805 i = 0; 2806 ctl = NULL; 2807 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2808 if (ctl->widget == NULL || ctl->enable == 0) 2809 continue; 2810 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2811 continue; 2812 if (ctl->step > 0) 2813 break; 2814 } 2815 2816 if (softpcmvol == 1 || ctl == NULL) { 2817 struct snddev_info *d = NULL; 2818 d = device_get_softc(sc->dev); 2819 if (d != NULL) { 2820 d->flags |= SD_F_SOFTPCMVOL; 2821 HDA_BOOTVERBOSE( 2822 device_printf(sc->dev, 2823 "HDA_DEBUG: %s Soft PCM volume\n", 2824 (softpcmvol == 1) ? 2825 "Forcing" : "Enabling"); 2826 ); 2827 } 2828 i = 0; 2829 /* 2830 * XXX Temporary quirk for STAC9220, until the parser 2831 * become smarter. 2832 */ 2833 if (id == HDA_CODEC_STAC9220) { 2834 mask |= SOUND_MASK_VOLUME; 2835 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2836 NULL) { 2837 if (ctl->widget == NULL || ctl->enable == 0) 2838 continue; 2839 if (ctl->widget->nid == 11 && ctl->index == 0) { 2840 ctl->ossmask = SOUND_MASK_VOLUME; 2841 ctl->ossval = 100 | (100 << 8); 2842 } else 2843 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2844 } 2845 } else { 2846 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2847 SOUND_MASK_PCM); 2848 if (!(mask & SOUND_MASK_VOLUME)) 2849 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2850 SOUND_MIXER_NONE); 2851 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2852 NULL) { 2853 if (ctl->widget == NULL || ctl->enable == 0) 2854 continue; 2855 if (!HDA_FLAG_MATCH(ctl->ossmask, 2856 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2857 continue; 2858 if (!(ctl->mute == 1 && ctl->step == 0)) 2859 ctl->enable = 0; 2860 } 2861 } 2862 } 2863 2864 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2865 2866 mix_setrecdevs(m, recmask); 2867 mix_setdevs(m, mask); 2868 2869 hdac_unlock(sc); 2870 2871 return (0); 2872} 2873 2874static int 2875hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2876 unsigned left, unsigned right) 2877{ 2878 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2879 struct hdac_softc *sc = devinfo->codec->sc; 2880 struct hdac_widget *w; 2881 struct hdac_audio_ctl *ctl; 2882 uint32_t id, mute; 2883 int lvol, rvol, mlvol, mrvol; 2884 int i = 0; 2885 2886 hdac_lock(sc); 2887 if (dev == SOUND_MIXER_OGAIN) { 2888 uint32_t orig; 2889 /*if (left != right || !(left == 0 || left == 1)) { 2890 hdac_unlock(sc); 2891 return (-1); 2892 }*/ 2893 id = hdac_codec_id(devinfo); 2894 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2895 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2896 sc->pci_subvendor) && 2897 hdac_eapd_switch[i].id == id) 2898 break; 2899 } 2900 if (i >= HDAC_EAPD_SWITCH_LEN) { 2901 hdac_unlock(sc); 2902 return (-1); 2903 } 2904 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2905 if (w == NULL || 2906 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2907 w->param.eapdbtl == HDAC_INVALID) { 2908 hdac_unlock(sc); 2909 return (-1); 2910 } 2911 orig = w->param.eapdbtl; 2912 if (left == 0) 2913 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2914 else 2915 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2916 if (orig != w->param.eapdbtl) { 2917 uint32_t val; 2918 2919 if (hdac_eapd_switch[i].hp_switch != 0) 2920 hdac_hp_switch_handler(devinfo); 2921 val = w->param.eapdbtl; 2922 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2923 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2924 hdac_command(sc, 2925 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2926 w->nid, val), devinfo->codec->cad); 2927 } 2928 hdac_unlock(sc); 2929 return (left | (left << 8)); 2930 } 2931 if (dev == SOUND_MIXER_VOLUME) 2932 devinfo->function.audio.mvol = left | (right << 8); 2933 2934 mlvol = devinfo->function.audio.mvol & 0x7f; 2935 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2936 lvol = 0; 2937 rvol = 0; 2938 2939 i = 0; 2940 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2941 if (ctl->widget == NULL || ctl->enable == 0 || 2942 !(ctl->ossmask & (1 << dev))) 2943 continue; 2944 switch (dev) { 2945 case SOUND_MIXER_VOLUME: 2946 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2947 lvol = (lvol * ctl->step) / 100; 2948 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2949 rvol = (rvol * ctl->step) / 100; 2950 break; 2951 default: 2952 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2953 lvol = (left * mlvol) / 100; 2954 lvol = (lvol * ctl->step) / 100; 2955 rvol = (right * mrvol) / 100; 2956 rvol = (rvol * ctl->step) / 100; 2957 } else { 2958 lvol = (left * ctl->step) / 100; 2959 rvol = (right * ctl->step) / 100; 2960 } 2961 ctl->ossval = left | (right << 8); 2962 break; 2963 } 2964 mute = 0; 2965 if (ctl->step < 1) { 2966 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2967 (ctl->muted & HDA_AMP_MUTE_LEFT); 2968 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2969 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2970 } else { 2971 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2972 (ctl->muted & HDA_AMP_MUTE_LEFT); 2973 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2974 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2975 } 2976 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2977 } 2978 hdac_unlock(sc); 2979 2980 return (left | (right << 8)); 2981} 2982 2983static int 2984hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2985{ 2986 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2987 struct hdac_widget *w, *cw; 2988 struct hdac_softc *sc = devinfo->codec->sc; 2989 uint32_t ret = src, target; 2990 int i, j; 2991 2992 target = 0; 2993 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2994 if (src & (1 << i)) { 2995 target = 1 << i; 2996 break; 2997 } 2998 } 2999 3000 hdac_lock(sc); 3001 3002 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3003 w = hdac_widget_get(devinfo, i); 3004 if (w == NULL || w->enable == 0) 3005 continue; 3006 if (!(w->pflags & HDA_ADC_RECSEL)) 3007 continue; 3008 for (j = 0; j < w->nconns; j++) { 3009 cw = hdac_widget_get(devinfo, w->conns[j]); 3010 if (cw == NULL || cw->enable == 0) 3011 continue; 3012 if ((target == SOUND_MASK_VOLUME && 3013 cw->type != 3014 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3015 (target != SOUND_MASK_VOLUME && 3016 cw->type == 3017 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3018 continue; 3019 if (cw->ctlflags & target) { 3020 hdac_widget_connection_select(w, j); 3021 ret = target; 3022 j += w->nconns; 3023 } 3024 } 3025 } 3026 3027 hdac_unlock(sc); 3028 3029 return (ret); 3030} 3031 3032static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3033 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3034 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3035 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3036 { 0, 0 } 3037}; 3038MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3039 3040/**************************************************************************** 3041 * int hdac_attach(device_t) 3042 * 3043 * Attach the device into the kernel. Interrupts usually won't be enabled 3044 * when this function is called. Setup everything that doesn't require 3045 * interrupts and defer probing of codecs until interrupts are enabled. 3046 ****************************************************************************/ 3047static int 3048hdac_attach(device_t dev) 3049{ 3050 struct hdac_softc *sc; 3051 int result; 3052 int i = 0; 3053 3054 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3055 if (sc == NULL) { 3056 device_printf(dev, "cannot allocate softc\n"); 3057 return (ENOMEM); 3058 } 3059 3060 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3061 if (sc->lock == NULL) { 3062 device_printf(dev, "mutex creation failed\n"); 3063 free(sc, M_DEVBUF); 3064 return (ENOMEM); 3065 } 3066 3067 sc->dev = dev; 3068 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3069 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3070 3071 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3072 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3073 3074 sc->poll_ticks = 1; 3075 if (resource_int_value(device_get_name(sc->dev), 3076 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3077 sc->polling = 1; 3078 else 3079 sc->polling = 0; 3080 3081 sc->chan_size = pcm_getbuffersize(dev, 3082 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3083 3084 if (resource_int_value(device_get_name(sc->dev), 3085 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3086 i &= ~0x7f; 3087 if (i < 0x80) 3088 i = 0x80; 3089 sc->chan_blkcnt = sc->chan_size / i; 3090 i = 0; 3091 while (sc->chan_blkcnt >> i) 3092 i++; 3093 sc->chan_blkcnt = 1 << (i - 1); 3094 if (sc->chan_blkcnt < HDA_BDL_MIN) 3095 sc->chan_blkcnt = HDA_BDL_MIN; 3096 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3097 sc->chan_blkcnt = HDA_BDL_MAX; 3098 } else 3099 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3100 3101 result = bus_dma_tag_create(NULL, /* parent */ 3102 HDAC_DMA_ALIGNMENT, /* alignment */ 3103 0, /* boundary */ 3104 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3105 BUS_SPACE_MAXADDR, /* highaddr */ 3106 NULL, /* filtfunc */ 3107 NULL, /* fistfuncarg */ 3108 sc->chan_size, /* maxsize */ 3109 1, /* nsegments */ 3110 sc->chan_size, /* maxsegsz */ 3111 0, /* flags */ 3112 NULL, /* lockfunc */ 3113 NULL, /* lockfuncarg */ 3114 &sc->chan_dmat); /* dmat */ 3115 if (result != 0) { 3116 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3117 __func__, result); 3118 snd_mtxfree(sc->lock); 3119 free(sc, M_DEVBUF); 3120 return (ENXIO); 3121 } 3122 3123 3124 sc->hdabus = NULL; 3125 for (i = 0; i < HDAC_CODEC_MAX; i++) 3126 sc->codecs[i] = NULL; 3127 3128 pci_enable_busmaster(dev); 3129 3130 /* Allocate resources */ 3131 result = hdac_mem_alloc(sc); 3132 if (result != 0) 3133 goto hdac_attach_fail; 3134 result = hdac_irq_alloc(sc); 3135 if (result != 0) 3136 goto hdac_attach_fail; 3137 3138 /* Get Capabilities */ 3139 result = hdac_get_capabilities(sc); 3140 if (result != 0) 3141 goto hdac_attach_fail; 3142 3143 /* Allocate CORB and RIRB dma memory */ 3144 result = hdac_dma_alloc(sc, &sc->corb_dma, 3145 sc->corb_size * sizeof(uint32_t)); 3146 if (result != 0) 3147 goto hdac_attach_fail; 3148 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3149 sc->rirb_size * sizeof(struct hdac_rirb)); 3150 if (result != 0) 3151 goto hdac_attach_fail; 3152 3153 /* Quiesce everything */ 3154 hdac_reset(sc); 3155 3156 /* Disable PCI-Express QOS */ 3157 pci_write_config(sc->dev, 0x44, 3158 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3159 3160 /* Initialize the CORB and RIRB */ 3161 hdac_corb_init(sc); 3162 hdac_rirb_init(sc); 3163 3164 /* Defer remaining of initialization until interrupts are enabled */ 3165 sc->intrhook.ich_func = hdac_attach2; 3166 sc->intrhook.ich_arg = (void *)sc; 3167 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3168 sc->intrhook.ich_func = NULL; 3169 hdac_attach2((void *)sc); 3170 } 3171 3172 return (0); 3173 3174hdac_attach_fail: 3175 hdac_dma_free(&sc->rirb_dma); 3176 hdac_dma_free(&sc->corb_dma); 3177 hdac_irq_free(sc); 3178 hdac_mem_free(sc); 3179 snd_mtxfree(sc->lock); 3180 free(sc, M_DEVBUF); 3181 3182 return (ENXIO); 3183} 3184 3185static void 3186hdac_audio_parse(struct hdac_devinfo *devinfo) 3187{ 3188 struct hdac_softc *sc = devinfo->codec->sc; 3189 struct hdac_widget *w; 3190 uint32_t res; 3191 int i; 3192 nid_t cad, nid; 3193 3194 cad = devinfo->codec->cad; 3195 nid = devinfo->nid; 3196 3197 hdac_command(sc, 3198 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3199 3200 DELAY(100); 3201 3202 res = hdac_command(sc, 3203 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3204 3205 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3206 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3207 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3208 3209 HDA_BOOTVERBOSE( 3210 device_printf(sc->dev, " Vendor: 0x%08x\n", 3211 devinfo->vendor_id); 3212 device_printf(sc->dev, " Device: 0x%08x\n", 3213 devinfo->device_id); 3214 device_printf(sc->dev, " Revision: 0x%08x\n", 3215 devinfo->revision_id); 3216 device_printf(sc->dev, " Stepping: 0x%08x\n", 3217 devinfo->stepping_id); 3218 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3219 sc->pci_subvendor); 3220 device_printf(sc->dev, " Nodes: start=%d " 3221 "endnode=%d total=%d\n", 3222 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3223 ); 3224 3225 res = hdac_command(sc, 3226 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3227 cad); 3228 devinfo->function.audio.supp_stream_formats = res; 3229 3230 res = hdac_command(sc, 3231 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3232 cad); 3233 devinfo->function.audio.supp_pcm_size_rate = res; 3234 3235 res = hdac_command(sc, 3236 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3237 cad); 3238 devinfo->function.audio.outamp_cap = res; 3239 3240 res = hdac_command(sc, 3241 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3242 cad); 3243 devinfo->function.audio.inamp_cap = res; 3244 3245 if (devinfo->nodecnt > 0) { 3246 hdac_unlock(sc); 3247 devinfo->widget = (struct hdac_widget *)malloc( 3248 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3249 M_NOWAIT | M_ZERO); 3250 hdac_lock(sc); 3251 } else 3252 devinfo->widget = NULL; 3253 3254 if (devinfo->widget == NULL) { 3255 device_printf(sc->dev, "unable to allocate widgets!\n"); 3256 devinfo->endnode = devinfo->startnode; 3257 devinfo->nodecnt = 0; 3258 return; 3259 } 3260 3261 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3262 w = hdac_widget_get(devinfo, i); 3263 if (w == NULL) 3264 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3265 else { 3266 w->devinfo = devinfo; 3267 w->nid = i; 3268 w->enable = 1; 3269 w->selconn = -1; 3270 w->pflags = 0; 3271 w->ctlflags = 0; 3272 w->param.eapdbtl = HDAC_INVALID; 3273 hdac_widget_parse(w); 3274 } 3275 } 3276} 3277 3278static void 3279hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3280{ 3281 struct hdac_softc *sc = devinfo->codec->sc; 3282 struct hdac_audio_ctl *ctls; 3283 struct hdac_widget *w, *cw; 3284 int i, j, cnt, max, ocap, icap; 3285 int mute, offset, step, size; 3286 3287 /* XXX This is redundant */ 3288 max = 0; 3289 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3290 w = hdac_widget_get(devinfo, i); 3291 if (w == NULL || w->enable == 0) 3292 continue; 3293 if (w->param.outamp_cap != 0) 3294 max++; 3295 if (w->param.inamp_cap != 0) { 3296 switch (w->type) { 3297 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3298 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3299 for (j = 0; j < w->nconns; j++) { 3300 cw = hdac_widget_get(devinfo, 3301 w->conns[j]); 3302 if (cw == NULL || cw->enable == 0) 3303 continue; 3304 max++; 3305 } 3306 break; 3307 default: 3308 max++; 3309 break; 3310 } 3311 } 3312 } 3313 3314 devinfo->function.audio.ctlcnt = max; 3315 3316 if (max < 1) 3317 return; 3318 3319 hdac_unlock(sc); 3320 ctls = (struct hdac_audio_ctl *)malloc( 3321 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3322 hdac_lock(sc); 3323 3324 if (ctls == NULL) { 3325 /* Blekh! */ 3326 device_printf(sc->dev, "unable to allocate ctls!\n"); 3327 devinfo->function.audio.ctlcnt = 0; 3328 return; 3329 } 3330 3331 cnt = 0; 3332 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3333 if (cnt >= max) { 3334 device_printf(sc->dev, "%s: Ctl overflow!\n", 3335 __func__); 3336 break; 3337 } 3338 w = hdac_widget_get(devinfo, i); 3339 if (w == NULL || w->enable == 0) 3340 continue; 3341 ocap = w->param.outamp_cap; 3342 icap = w->param.inamp_cap; 3343 if (ocap != 0) { 3344 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3345 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3346 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3347 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3348 /*if (offset > step) { 3349 HDA_BOOTVERBOSE( 3350 device_printf(sc->dev, 3351 "HDA_DEBUG: BUGGY outamp: nid=%d " 3352 "[offset=%d > step=%d]\n", 3353 w->nid, offset, step); 3354 ); 3355 offset = step; 3356 }*/ 3357 ctls[cnt].enable = 1; 3358 ctls[cnt].widget = w; 3359 ctls[cnt].mute = mute; 3360 ctls[cnt].step = step; 3361 ctls[cnt].size = size; 3362 ctls[cnt].offset = offset; 3363 ctls[cnt].left = offset; 3364 ctls[cnt].right = offset; 3365 ctls[cnt++].dir = HDA_CTL_OUT; 3366 } 3367 3368 if (icap != 0) { 3369 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3370 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3371 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3372 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3373 /*if (offset > step) { 3374 HDA_BOOTVERBOSE( 3375 device_printf(sc->dev, 3376 "HDA_DEBUG: BUGGY inamp: nid=%d " 3377 "[offset=%d > step=%d]\n", 3378 w->nid, offset, step); 3379 ); 3380 offset = step; 3381 }*/ 3382 switch (w->type) { 3383 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3384 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3385 for (j = 0; j < w->nconns; j++) { 3386 if (cnt >= max) { 3387 device_printf(sc->dev, 3388 "%s: Ctl overflow!\n", 3389 __func__); 3390 break; 3391 } 3392 cw = hdac_widget_get(devinfo, 3393 w->conns[j]); 3394 if (cw == NULL || cw->enable == 0) 3395 continue; 3396 ctls[cnt].enable = 1; 3397 ctls[cnt].widget = w; 3398 ctls[cnt].childwidget = cw; 3399 ctls[cnt].index = j; 3400 ctls[cnt].mute = mute; 3401 ctls[cnt].step = step; 3402 ctls[cnt].size = size; 3403 ctls[cnt].offset = offset; 3404 ctls[cnt].left = offset; 3405 ctls[cnt].right = offset; 3406 ctls[cnt++].dir = HDA_CTL_IN; 3407 } 3408 break; 3409 default: 3410 if (cnt >= max) { 3411 device_printf(sc->dev, 3412 "%s: Ctl overflow!\n", 3413 __func__); 3414 break; 3415 } 3416 ctls[cnt].enable = 1; 3417 ctls[cnt].widget = w; 3418 ctls[cnt].mute = mute; 3419 ctls[cnt].step = step; 3420 ctls[cnt].size = size; 3421 ctls[cnt].offset = offset; 3422 ctls[cnt].left = offset; 3423 ctls[cnt].right = offset; 3424 ctls[cnt++].dir = HDA_CTL_IN; 3425 break; 3426 } 3427 } 3428 } 3429 3430 devinfo->function.audio.ctl = ctls; 3431} 3432 3433static const struct { 3434 uint32_t model; 3435 uint32_t id; 3436 uint32_t set, unset; 3437} hdac_quirks[] = { 3438 /* 3439 * XXX Force stereo quirk. Monoural recording / playback 3440 * on few codecs (especially ALC880) seems broken or 3441 * perhaps unsupported. 3442 */ 3443 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3444 HDA_QUIRK_FORCESTEREO, 0 }, 3445 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3446 HDA_QUIRK_GPIO1, 0 }, 3447 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3448 HDA_QUIRK_GPIO1, 0 }, 3449 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3450 HDA_QUIRK_EAPDINV, 0 }, 3451 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3452 HDA_QUIRK_EAPDINV, 0 }, 3453 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3454 HDA_QUIRK_EAPDINV, 0 }, 3455 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3456 HDA_QUIRK_EAPDINV, 0 }, 3457 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3458 0, HDA_QUIRK_FORCESTEREO }, 3459 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3460 HDA_QUIRK_SOFTPCMVOL, 0 } 3461}; 3462#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3463 3464static void 3465hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3466{ 3467 struct hdac_widget *w; 3468 uint32_t id, subvendor; 3469 int i; 3470 3471 id = hdac_codec_id(devinfo); 3472 subvendor = devinfo->codec->sc->pci_subvendor; 3473 3474 /* 3475 * Quirks 3476 */ 3477 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3478 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3479 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3480 continue; 3481 if (hdac_quirks[i].set != 0) 3482 devinfo->function.audio.quirks |= 3483 hdac_quirks[i].set; 3484 if (hdac_quirks[i].unset != 0) 3485 devinfo->function.audio.quirks &= 3486 ~(hdac_quirks[i].unset); 3487 } 3488 3489 switch (id) { 3490 case HDA_CODEC_ALC260: 3491 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3492 w = hdac_widget_get(devinfo, i); 3493 if (w == NULL || w->enable == 0) 3494 continue; 3495 if (w->type != 3496 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3497 continue; 3498 if (w->nid != 5) 3499 w->enable = 0; 3500 } 3501 break; 3502 case HDA_CODEC_ALC880: 3503 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3504 w = hdac_widget_get(devinfo, i); 3505 if (w == NULL || w->enable == 0) 3506 continue; 3507 if (w->type == 3508 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3509 w->nid != 9 && w->nid != 29) { 3510 w->enable = 0; 3511 } else if (w->type != 3512 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3513 w->nid == 29) { 3514 w->type = 3515 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3516 w->param.widget_cap &= 3517 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3518 w->param.widget_cap |= 3519 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3520 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3521 strlcpy(w->name, "beep widget", sizeof(w->name)); 3522 } 3523 } 3524 break; 3525 case HDA_CODEC_AD1981HD: 3526 w = hdac_widget_get(devinfo, 11); 3527 if (w != NULL && w->enable != 0 && w->nconns > 3) 3528 w->selconn = 3; 3529 if (subvendor == IBM_M52_SUBVENDOR) { 3530 struct hdac_audio_ctl *ctl; 3531 3532 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3533 if (ctl != NULL) 3534 ctl->ossmask = SOUND_MASK_SPEAKER; 3535 } 3536 break; 3537 case HDA_CODEC_AD1986A: 3538 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3539 w = hdac_widget_get(devinfo, i); 3540 if (w == NULL || w->enable == 0) 3541 continue; 3542 if (w->type != 3543 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3544 continue; 3545 if (w->nid != 3) 3546 w->enable = 0; 3547 } 3548 break; 3549 case HDA_CODEC_STAC9221: 3550 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3551 w = hdac_widget_get(devinfo, i); 3552 if (w == NULL || w->enable == 0) 3553 continue; 3554 if (w->type != 3555 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3556 continue; 3557 if (w->nid != 2) 3558 w->enable = 0; 3559 } 3560 break; 3561 case HDA_CODEC_STAC9221D: 3562 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3563 w = hdac_widget_get(devinfo, i); 3564 if (w == NULL || w->enable == 0) 3565 continue; 3566 if (w->type == 3567 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3568 w->nid != 6) 3569 w->enable = 0; 3570 3571 } 3572 break; 3573 default: 3574 break; 3575 } 3576} 3577 3578static int 3579hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3580{ 3581 int *dev = &devinfo->function.audio.ossidx; 3582 3583 while (*dev < SOUND_MIXER_NRDEVICES) { 3584 switch (*dev) { 3585 case SOUND_MIXER_VOLUME: 3586 case SOUND_MIXER_BASS: 3587 case SOUND_MIXER_TREBLE: 3588 case SOUND_MIXER_PCM: 3589 case SOUND_MIXER_SPEAKER: 3590 case SOUND_MIXER_LINE: 3591 case SOUND_MIXER_MIC: 3592 case SOUND_MIXER_CD: 3593 case SOUND_MIXER_RECLEV: 3594 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3595 (*dev)++; 3596 break; 3597 default: 3598 return (*dev)++; 3599 break; 3600 } 3601 } 3602 3603 return (-1); 3604} 3605 3606static int 3607hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3608{ 3609 struct hdac_widget *w; 3610 int i, ret = 0; 3611 3612 if (depth > HDA_PARSE_MAXDEPTH) 3613 return (0); 3614 w = hdac_widget_get(devinfo, nid); 3615 if (w == NULL || w->enable == 0) 3616 return (0); 3617 switch (w->type) { 3618 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3619 w->pflags |= HDA_DAC_PATH; 3620 ret = 1; 3621 break; 3622 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3623 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3624 for (i = 0; i < w->nconns; i++) { 3625 if (hdac_widget_find_dac_path(devinfo, 3626 w->conns[i], depth + 1) != 0) { 3627 if (w->selconn == -1) 3628 w->selconn = i; 3629 ret = 1; 3630 w->pflags |= HDA_DAC_PATH; 3631 } 3632 } 3633 break; 3634 default: 3635 break; 3636 } 3637 return (ret); 3638} 3639 3640static int 3641hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3642{ 3643 struct hdac_widget *w; 3644 int i, conndev, ret = 0; 3645 3646 if (depth > HDA_PARSE_MAXDEPTH) 3647 return (0); 3648 w = hdac_widget_get(devinfo, nid); 3649 if (w == NULL || w->enable == 0) 3650 return (0); 3651 switch (w->type) { 3652 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3653 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3654 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3655 for (i = 0; i < w->nconns; i++) { 3656 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3657 depth + 1) != 0) { 3658 if (w->selconn == -1) 3659 w->selconn = i; 3660 w->pflags |= HDA_ADC_PATH; 3661 ret = 1; 3662 } 3663 } 3664 break; 3665 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3666 conndev = w->wclass.pin.config & 3667 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3668 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3669 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3670 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3671 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3672 w->pflags |= HDA_ADC_PATH; 3673 ret = 1; 3674 } 3675 break; 3676 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3677 if (w->pflags & HDA_DAC_PATH) { 3678 w->pflags |= HDA_ADC_PATH; 3679 ret = 1; 3680 } 3681 break;*/ 3682 default: 3683 break; 3684 } 3685 return (ret); 3686} 3687 3688static uint32_t 3689hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3690 nid_t nid, nid_t pnid, int index, int depth) 3691{ 3692 struct hdac_widget *w, *pw; 3693 struct hdac_audio_ctl *ctl; 3694 uint32_t fl = 0; 3695 int i, ossdev, conndev, strategy; 3696 3697 if (depth > HDA_PARSE_MAXDEPTH) 3698 return (0); 3699 3700 w = hdac_widget_get(devinfo, nid); 3701 if (w == NULL || w->enable == 0) 3702 return (0); 3703 3704 pw = hdac_widget_get(devinfo, pnid); 3705 strategy = devinfo->function.audio.parsing_strategy; 3706 3707 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3708 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3709 for (i = 0; i < w->nconns; i++) { 3710 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3711 w->nid, i, depth + 1); 3712 } 3713 w->ctlflags |= fl; 3714 return (fl); 3715 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3716 (w->pflags & HDA_DAC_PATH)) { 3717 i = 0; 3718 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3719 if (ctl->enable == 0 || ctl->widget == NULL) 3720 continue; 3721 /* XXX This should be compressed! */ 3722 if ((ctl->widget->nid == w->nid) || 3723 (ctl->widget->nid == pnid && ctl->index == index && 3724 (ctl->dir & HDA_CTL_IN)) || 3725 (ctl->widget->nid == pnid && pw != NULL && 3726 pw->type == 3727 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3728 (pw->nconns < 2 || pw->selconn == index || 3729 pw->selconn == -1) && 3730 (ctl->dir & HDA_CTL_OUT)) || 3731 (strategy == HDA_PARSE_DIRECT && 3732 ctl->widget->nid == w->nid)) { 3733 /*if (pw != NULL && pw->selconn == -1) 3734 pw->selconn = index; 3735 fl |= SOUND_MASK_VOLUME; 3736 fl |= SOUND_MASK_PCM; 3737 ctl->ossmask |= SOUND_MASK_VOLUME; 3738 ctl->ossmask |= SOUND_MASK_PCM; 3739 ctl->ossdev = SOUND_MIXER_PCM;*/ 3740 if (!(w->ctlflags & SOUND_MASK_PCM) || 3741 (pw != NULL && 3742 !(pw->ctlflags & SOUND_MASK_PCM))) { 3743 fl |= SOUND_MASK_VOLUME; 3744 fl |= SOUND_MASK_PCM; 3745 ctl->ossmask |= SOUND_MASK_VOLUME; 3746 ctl->ossmask |= SOUND_MASK_PCM; 3747 ctl->ossdev = SOUND_MIXER_PCM; 3748 w->ctlflags |= SOUND_MASK_VOLUME; 3749 w->ctlflags |= SOUND_MASK_PCM; 3750 if (pw != NULL) { 3751 if (pw->selconn == -1) 3752 pw->selconn = index; 3753 pw->ctlflags |= 3754 SOUND_MASK_VOLUME; 3755 pw->ctlflags |= 3756 SOUND_MASK_PCM; 3757 } 3758 } 3759 } 3760 } 3761 w->ctlflags |= fl; 3762 return (fl); 3763 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3764 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3765 (w->pflags & HDA_ADC_PATH)) { 3766 conndev = w->wclass.pin.config & 3767 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3768 i = 0; 3769 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3770 if (ctl->enable == 0 || ctl->widget == NULL) 3771 continue; 3772 /* XXX This should be compressed! */ 3773 if (((ctl->widget->nid == pnid && ctl->index == index && 3774 (ctl->dir & HDA_CTL_IN)) || 3775 (ctl->widget->nid == pnid && pw != NULL && 3776 pw->type == 3777 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3778 (pw->nconns < 2 || pw->selconn == index || 3779 pw->selconn == -1) && 3780 (ctl->dir & HDA_CTL_OUT)) || 3781 (strategy == HDA_PARSE_DIRECT && 3782 ctl->widget->nid == w->nid)) && 3783 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3784 if (pw != NULL && pw->selconn == -1) 3785 pw->selconn = index; 3786 ossdev = 0; 3787 switch (conndev) { 3788 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3789 ossdev = SOUND_MIXER_MIC; 3790 break; 3791 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3792 ossdev = SOUND_MIXER_LINE; 3793 break; 3794 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3795 ossdev = SOUND_MIXER_CD; 3796 break; 3797 default: 3798 ossdev = 3799 hdac_audio_ctl_ossmixer_getnextdev( 3800 devinfo); 3801 if (ossdev < 0) 3802 ossdev = 0; 3803 break; 3804 } 3805 if (strategy == HDA_PARSE_MIXER) { 3806 fl |= SOUND_MASK_VOLUME; 3807 ctl->ossmask |= SOUND_MASK_VOLUME; 3808 } 3809 fl |= 1 << ossdev; 3810 ctl->ossmask |= 1 << ossdev; 3811 ctl->ossdev = ossdev; 3812 } 3813 } 3814 w->ctlflags |= fl; 3815 return (fl); 3816 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3817 i = 0; 3818 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3819 if (ctl->enable == 0 || ctl->widget == NULL) 3820 continue; 3821 /* XXX This should be compressed! */ 3822 if (((ctl->widget->nid == pnid && ctl->index == index && 3823 (ctl->dir & HDA_CTL_IN)) || 3824 (ctl->widget->nid == pnid && pw != NULL && 3825 pw->type == 3826 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3827 (pw->nconns < 2 || pw->selconn == index || 3828 pw->selconn == -1) && 3829 (ctl->dir & HDA_CTL_OUT)) || 3830 (strategy == HDA_PARSE_DIRECT && 3831 ctl->widget->nid == w->nid)) && 3832 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3833 if (pw != NULL && pw->selconn == -1) 3834 pw->selconn = index; 3835 fl |= SOUND_MASK_VOLUME; 3836 fl |= SOUND_MASK_SPEAKER; 3837 ctl->ossmask |= SOUND_MASK_VOLUME; 3838 ctl->ossmask |= SOUND_MASK_SPEAKER; 3839 ctl->ossdev = SOUND_MIXER_SPEAKER; 3840 } 3841 } 3842 w->ctlflags |= fl; 3843 return (fl); 3844 } 3845 return (0); 3846} 3847 3848static uint32_t 3849hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3850{ 3851 struct hdac_widget *w, *cw; 3852 struct hdac_audio_ctl *ctl; 3853 uint32_t fl; 3854 int i; 3855 3856 if (depth > HDA_PARSE_MAXDEPTH) 3857 return (0); 3858 3859 w = hdac_widget_get(devinfo, nid); 3860 if (w == NULL || w->enable == 0) 3861 return (0); 3862 /*if (!(w->pflags & HDA_ADC_PATH)) 3863 return (0); 3864 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3865 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3866 return (0);*/ 3867 i = 0; 3868 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3869 if (ctl->enable == 0 || ctl->widget == NULL) 3870 continue; 3871 if (ctl->widget->nid == nid) { 3872 ctl->ossmask |= SOUND_MASK_RECLEV; 3873 w->ctlflags |= SOUND_MASK_RECLEV; 3874 return (SOUND_MASK_RECLEV); 3875 } 3876 } 3877 for (i = 0; i < w->nconns; i++) { 3878 cw = hdac_widget_get(devinfo, w->conns[i]); 3879 if (cw == NULL || cw->enable == 0) 3880 continue; 3881 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3882 continue; 3883 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3884 if (fl != 0) { 3885 cw->ctlflags |= fl; 3886 w->ctlflags |= fl; 3887 return (fl); 3888 } 3889 } 3890 return (0); 3891} 3892 3893static int 3894hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3895{ 3896 struct hdac_widget *w, *cw; 3897 int i, child = 0; 3898 3899 if (depth > HDA_PARSE_MAXDEPTH) 3900 return (0); 3901 3902 w = hdac_widget_get(devinfo, nid); 3903 if (w == NULL || w->enable == 0) 3904 return (0); 3905 /*if (!(w->pflags & HDA_ADC_PATH)) 3906 return (0); 3907 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3908 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3909 return (0);*/ 3910 /* XXX weak! */ 3911 for (i = 0; i < w->nconns; i++) { 3912 cw = hdac_widget_get(devinfo, w->conns[i]); 3913 if (cw == NULL) 3914 continue; 3915 if (++child > 1) { 3916 w->pflags |= HDA_ADC_RECSEL; 3917 return (1); 3918 } 3919 } 3920 for (i = 0; i < w->nconns; i++) { 3921 if (hdac_audio_ctl_recsel_build(devinfo, 3922 w->conns[i], depth + 1) != 0) 3923 return (1); 3924 } 3925 return (0); 3926} 3927 3928static int 3929hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3930{ 3931 struct hdac_widget *w, *cw; 3932 int i, j, conndev, found_dac = 0; 3933 int strategy; 3934 3935 strategy = devinfo->function.audio.parsing_strategy; 3936 3937 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3938 w = hdac_widget_get(devinfo, i); 3939 if (w == NULL || w->enable == 0) 3940 continue; 3941 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3942 continue; 3943 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3944 continue; 3945 conndev = w->wclass.pin.config & 3946 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3947 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3948 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3949 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3950 continue; 3951 for (j = 0; j < w->nconns; j++) { 3952 cw = hdac_widget_get(devinfo, w->conns[j]); 3953 if (cw == NULL || cw->enable == 0) 3954 continue; 3955 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3956 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3957 cw->type == 3958 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3959 continue; 3960 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3961 != 0) { 3962 if (w->selconn == -1) 3963 w->selconn = j; 3964 w->pflags |= HDA_DAC_PATH; 3965 found_dac++; 3966 } 3967 } 3968 } 3969 3970 return (found_dac); 3971} 3972 3973static void 3974hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3975{ 3976 struct hdac_widget *w; 3977 struct hdac_audio_ctl *ctl; 3978 int i, j, dacs, strategy; 3979 3980 /* Construct DAC path */ 3981 strategy = HDA_PARSE_MIXER; 3982 devinfo->function.audio.parsing_strategy = strategy; 3983 HDA_BOOTVERBOSE( 3984 device_printf(devinfo->codec->sc->dev, 3985 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 3986 HDA_WIDGET_PARSER_REV); 3987 ); 3988 dacs = hdac_audio_build_tree_strategy(devinfo); 3989 if (dacs == 0) { 3990 HDA_BOOTVERBOSE( 3991 device_printf(devinfo->codec->sc->dev, 3992 "HDA_DEBUG: HWiP: 0 DAC path found! " 3993 "Retrying parser " 3994 "using HDA_PARSE_DIRECT strategy.\n"); 3995 ); 3996 strategy = HDA_PARSE_DIRECT; 3997 devinfo->function.audio.parsing_strategy = strategy; 3998 dacs = hdac_audio_build_tree_strategy(devinfo); 3999 } 4000 4001 HDA_BOOTVERBOSE( 4002 device_printf(devinfo->codec->sc->dev, 4003 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4004 "strategy.\n", 4005 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4006 ); 4007 4008 /* Construct ADC path */ 4009 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4010 w = hdac_widget_get(devinfo, i); 4011 if (w == NULL || w->enable == 0) 4012 continue; 4013 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4014 continue; 4015 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4016 } 4017 4018 /* Output mixers */ 4019 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4020 w = hdac_widget_get(devinfo, i); 4021 if (w == NULL || w->enable == 0) 4022 continue; 4023 if ((strategy == HDA_PARSE_MIXER && 4024 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4025 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4026 && (w->pflags & HDA_DAC_PATH)) || 4027 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4028 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4029 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4030 w->nid, devinfo->startnode - 1, 0, 0); 4031 } else if (w->type == 4032 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4033 j = 0; 4034 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4035 NULL) { 4036 if (ctl->enable == 0 || ctl->widget == NULL) 4037 continue; 4038 if (ctl->widget->nid != w->nid) 4039 continue; 4040 ctl->ossmask |= SOUND_MASK_VOLUME; 4041 ctl->ossmask |= SOUND_MASK_SPEAKER; 4042 ctl->ossdev = SOUND_MIXER_SPEAKER; 4043 w->ctlflags |= SOUND_MASK_VOLUME; 4044 w->ctlflags |= SOUND_MASK_SPEAKER; 4045 } 4046 } 4047 } 4048 4049 /* Input mixers (rec) */ 4050 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4051 w = hdac_widget_get(devinfo, i); 4052 if (w == NULL || w->enable == 0) 4053 continue; 4054 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4055 w->pflags & HDA_ADC_PATH)) 4056 continue; 4057 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4058 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4059 } 4060} 4061 4062#define HDA_COMMIT_CONN (1 << 0) 4063#define HDA_COMMIT_CTRL (1 << 1) 4064#define HDA_COMMIT_EAPD (1 << 2) 4065#define HDA_COMMIT_GPIO (1 << 3) 4066#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4067 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4068 4069static void 4070hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4071{ 4072 struct hdac_softc *sc = devinfo->codec->sc; 4073 struct hdac_widget *w; 4074 nid_t cad, nid; 4075 int i, gpioval; 4076 4077 if (!(cfl & HDA_COMMIT_ALL)) 4078 return; 4079 4080 cad = devinfo->codec->cad; 4081 4082 if (cfl & HDA_COMMIT_GPIO) { 4083 nid = devinfo->nid; 4084 for (i = 0; i < HDA_GPIO_MAX; i++) { 4085 if (!(devinfo->function.audio.quirks & (1 << i))) 4086 continue; 4087 gpioval = (1 << i) - 1; 4088 hdac_command(sc, 4089 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, gpioval), 4090 cad); 4091 hdac_command(sc, 4092 HDA_CMD_SET_GPIO_DIRECTION(cad, nid, gpioval), 4093 cad); 4094 hdac_command(sc, 4095 HDA_CMD_SET_GPIO_DATA(cad, nid, gpioval), 4096 cad); 4097 } 4098 } 4099 4100 for (i = 0; i < devinfo->nodecnt; i++) { 4101 w = &devinfo->widget[i]; 4102 if (w == NULL || w->enable == 0) 4103 continue; 4104 if (cfl & HDA_COMMIT_CONN) { 4105 if (w->selconn == -1) 4106 w->selconn = 0; 4107 if (w->nconns > 0) 4108 hdac_widget_connection_select(w, w->selconn); 4109 } 4110 if ((cfl & HDA_COMMIT_CTRL) && 4111 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4112 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4113 (HDA_DAC_PATH | HDA_ADC_PATH)) 4114 device_printf(sc->dev, "WARNING: node %d " 4115 "participate both for DAC/ADC!\n", w->nid); 4116 if (w->pflags & HDA_DAC_PATH) { 4117 w->wclass.pin.ctrl &= 4118 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4119 if ((w->wclass.pin.config & 4120 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4121 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4122 w->wclass.pin.ctrl &= 4123 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4124 } else if (w->pflags & HDA_ADC_PATH) { 4125 w->wclass.pin.ctrl &= 4126 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4127 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4128 } else 4129 w->wclass.pin.ctrl &= ~( 4130 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4131 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4132 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 4133 hdac_command(sc, 4134 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4135 w->wclass.pin.ctrl), cad); 4136 } 4137 if ((cfl & HDA_COMMIT_EAPD) && 4138 w->param.eapdbtl != HDAC_INVALID) { 4139 uint32_t val; 4140 4141 val = w->param.eapdbtl; 4142 if (devinfo->function.audio.quirks & 4143 HDA_QUIRK_EAPDINV) 4144 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4145 hdac_command(sc, 4146 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4147 val), cad); 4148 4149 } 4150 DELAY(1000); 4151 } 4152} 4153 4154static void 4155hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4156{ 4157 struct hdac_softc *sc = devinfo->codec->sc; 4158 struct hdac_audio_ctl *ctl; 4159 int i; 4160 4161 devinfo->function.audio.mvol = 100 | (100 << 8); 4162 i = 0; 4163 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4164 if (ctl->enable == 0 || ctl->widget == NULL) { 4165 HDA_BOOTVERBOSE( 4166 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4167 i, (ctl->widget != NULL) ? 4168 ctl->widget->nid : -1); 4169 if (ctl->childwidget != NULL) 4170 printf(" childnid=%d", 4171 ctl->childwidget->nid); 4172 if (ctl->widget == NULL) 4173 printf(" NULL WIDGET!"); 4174 printf(" DISABLED\n"); 4175 ); 4176 continue; 4177 } 4178 HDA_BOOTVERBOSE( 4179 if (ctl->ossmask == 0) { 4180 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4181 i, ctl->widget->nid); 4182 if (ctl->childwidget != NULL) 4183 printf(" childnid=%d", 4184 ctl->childwidget->nid); 4185 printf(" Bind to NONE\n"); 4186 } 4187 ); 4188 if (ctl->step > 0) { 4189 ctl->ossval = (ctl->left * 100) / ctl->step; 4190 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4191 } else 4192 ctl->ossval = 0; 4193 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4194 ctl->left, ctl->right); 4195 } 4196} 4197 4198static int 4199hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4200{ 4201 struct hdac_chan *ch; 4202 struct hdac_widget *w; 4203 uint32_t cap, fmtcap, pcmcap, path; 4204 int i, type, ret, max; 4205 4206 if (dir == PCMDIR_PLAY) { 4207 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4208 ch = &devinfo->codec->sc->play; 4209 path = HDA_DAC_PATH; 4210 } else { 4211 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4212 ch = &devinfo->codec->sc->rec; 4213 path = HDA_ADC_PATH; 4214 } 4215 4216 ch->caps = hdac_caps; 4217 ch->caps.fmtlist = ch->fmtlist; 4218 ch->bit16 = 1; 4219 ch->bit32 = 0; 4220 ch->pcmrates[0] = 48000; 4221 ch->pcmrates[1] = 0; 4222 4223 ret = 0; 4224 fmtcap = devinfo->function.audio.supp_stream_formats; 4225 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4226 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4227 4228 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4229 w = hdac_widget_get(devinfo, i); 4230 if (w == NULL || w->enable == 0 || w->type != type || 4231 !(w->pflags & path)) 4232 continue; 4233 cap = w->param.widget_cap; 4234 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4235 continue;*/ 4236 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4237 continue; 4238 cap = w->param.supp_stream_formats; 4239 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4240 } 4241 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4242 }*/ 4243 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4244 continue; 4245 if (ret == 0) { 4246 fmtcap = w->param.supp_stream_formats; 4247 pcmcap = w->param.supp_pcm_size_rate; 4248 } else { 4249 fmtcap &= w->param.supp_stream_formats; 4250 pcmcap &= w->param.supp_pcm_size_rate; 4251 } 4252 ch->io[ret++] = i; 4253 } 4254 ch->io[ret] = -1; 4255 4256 ch->supp_stream_formats = fmtcap; 4257 ch->supp_pcm_size_rate = pcmcap; 4258 4259 /* 4260 * 8bit = 0 4261 * 16bit = 1 4262 * 20bit = 2 4263 * 24bit = 3 4264 * 32bit = 4 4265 */ 4266 if (ret > 0) { 4267 cap = pcmcap; 4268 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4269 ch->bit16 = 1; 4270 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4271 ch->bit16 = 0; 4272 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4273 ch->bit32 = 4; 4274 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4275 ch->bit32 = 3; 4276 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4277 ch->bit32 = 2; 4278 i = 0; 4279 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4280 ch->fmtlist[i++] = AFMT_S16_LE; 4281 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4282 if (ch->bit32 > 0) { 4283 if (!(devinfo->function.audio.quirks & 4284 HDA_QUIRK_FORCESTEREO)) 4285 ch->fmtlist[i++] = AFMT_S32_LE; 4286 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4287 } 4288 ch->fmtlist[i] = 0; 4289 i = 0; 4290 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4291 ch->pcmrates[i++] = 8000; 4292 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4293 ch->pcmrates[i++] = 11025; 4294 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4295 ch->pcmrates[i++] = 16000; 4296 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4297 ch->pcmrates[i++] = 22050; 4298 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4299 ch->pcmrates[i++] = 32000; 4300 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4301 ch->pcmrates[i++] = 44100; 4302 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4303 ch->pcmrates[i++] = 48000; 4304 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4305 ch->pcmrates[i++] = 88200; 4306 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4307 ch->pcmrates[i++] = 96000; 4308 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4309 ch->pcmrates[i++] = 176400; 4310 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4311 ch->pcmrates[i++] = 192000; 4312 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4313 ch->pcmrates[i] = 0; 4314 if (i > 0) { 4315 ch->caps.minspeed = ch->pcmrates[0]; 4316 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4317 } 4318 } 4319 4320 return (ret); 4321} 4322 4323static void 4324hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4325{ 4326 struct hdac_audio_ctl *ctl; 4327 struct hdac_softc *sc = devinfo->codec->sc; 4328 int i; 4329 uint32_t fl = 0; 4330 4331 4332 if (flag == 0) { 4333 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4334 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4335 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4336 } 4337 4338 i = 0; 4339 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4340 if (ctl->enable == 0 || ctl->widget == NULL || 4341 ctl->widget->enable == 0) 4342 continue; 4343 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4344 (flag != 0 && (ctl->ossmask & flag))) { 4345 if (banner != NULL) { 4346 device_printf(sc->dev, "\n"); 4347 device_printf(sc->dev, "%s\n", banner); 4348 } 4349 goto hdac_ctl_dump_it_all; 4350 } 4351 } 4352 4353 return; 4354 4355hdac_ctl_dump_it_all: 4356 i = 0; 4357 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4358 if (ctl->enable == 0 || ctl->widget == NULL || 4359 ctl->widget->enable == 0) 4360 continue; 4361 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4362 (flag != 0 && (ctl->ossmask & flag)))) 4363 continue; 4364 if (flag == 0) { 4365 device_printf(sc->dev, "\n"); 4366 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4367 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4368 } 4369 device_printf(sc->dev, " |\n"); 4370 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4371 ctl->widget->nid, ctl->index); 4372 if (ctl->childwidget != NULL) 4373 printf("(nid: %2d) ", ctl->childwidget->nid); 4374 else 4375 printf(" "); 4376 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4377 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4378 ctl->ossmask); 4379 } 4380} 4381 4382static void 4383hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4384{ 4385 uint32_t cap; 4386 4387 cap = fcap; 4388 if (cap != 0) { 4389 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4390 device_printf(sc->dev, " Format:"); 4391 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4392 printf(" AC3"); 4393 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4394 printf(" FLOAT32"); 4395 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4396 printf(" PCM"); 4397 printf("\n"); 4398 } 4399 cap = pcmcap; 4400 if (cap != 0) { 4401 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4402 device_printf(sc->dev, " PCM size:"); 4403 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4404 printf(" 8"); 4405 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4406 printf(" 16"); 4407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4408 printf(" 20"); 4409 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4410 printf(" 24"); 4411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4412 printf(" 32"); 4413 printf("\n"); 4414 device_printf(sc->dev, " PCM rate:"); 4415 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4416 printf(" 8"); 4417 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4418 printf(" 11"); 4419 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4420 printf(" 16"); 4421 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4422 printf(" 22"); 4423 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4424 printf(" 32"); 4425 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4426 printf(" 44"); 4427 printf(" 48"); 4428 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4429 printf(" 88"); 4430 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4431 printf(" 96"); 4432 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4433 printf(" 176"); 4434 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4435 printf(" 192"); 4436 printf("\n"); 4437 } 4438} 4439 4440static void 4441hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4442{ 4443 uint32_t pincap, wcap; 4444 4445 pincap = w->wclass.pin.cap; 4446 wcap = w->param.widget_cap; 4447 4448 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4449 device_printf(sc->dev, " "); 4450 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4451 printf(" ISC"); 4452 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4453 printf(" TRQD"); 4454 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4455 printf(" PDC"); 4456 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4457 printf(" HP"); 4458 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4459 printf(" OUT"); 4460 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4461 printf(" IN"); 4462 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4463 printf(" BAL"); 4464 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4465 printf(" EAPD"); 4466 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4467 printf(" : UNSOL"); 4468 printf("\n"); 4469 device_printf(sc->dev, " Pin config: 0x%08x\n", 4470 w->wclass.pin.config); 4471 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4472 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4473 printf(" HP"); 4474 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4475 printf(" IN"); 4476 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4477 printf(" OUT"); 4478 printf("\n"); 4479} 4480 4481static void 4482hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4483{ 4484 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4485 device_printf(sc->dev, " " 4486 "mute=%d step=%d size=%d offset=%d\n", 4487 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4488 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4489 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4490 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4491} 4492 4493static void 4494hdac_dump_nodes(struct hdac_devinfo *devinfo) 4495{ 4496 struct hdac_softc *sc = devinfo->codec->sc; 4497 struct hdac_widget *w, *cw; 4498 int i, j; 4499 4500 device_printf(sc->dev, "\n"); 4501 device_printf(sc->dev, "Default Parameter\n"); 4502 device_printf(sc->dev, "-----------------\n"); 4503 hdac_dump_audio_formats(sc, 4504 devinfo->function.audio.supp_stream_formats, 4505 devinfo->function.audio.supp_pcm_size_rate); 4506 device_printf(sc->dev, " IN amp: 0x%08x\n", 4507 devinfo->function.audio.inamp_cap); 4508 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4509 devinfo->function.audio.outamp_cap); 4510 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4511 w = hdac_widget_get(devinfo, i); 4512 if (w == NULL) { 4513 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4514 continue; 4515 } 4516 device_printf(sc->dev, "\n"); 4517 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4518 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4519 "DIGITAL" : "ANALOG", 4520 (w->enable == 0) ? " [DISABLED]" : ""); 4521 device_printf(sc->dev, " name: %s\n", w->name); 4522 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4523 w->param.widget_cap); 4524 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4525 w->pflags); 4526 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4527 w->ctlflags); 4528 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4529 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4530 hdac_dump_audio_formats(sc, 4531 w->param.supp_stream_formats, 4532 w->param.supp_pcm_size_rate); 4533 } else if (w->type == 4534 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4535 hdac_dump_pin(sc, w); 4536 if (w->param.eapdbtl != HDAC_INVALID) 4537 device_printf(sc->dev, " EAPD: 0x%08x\n", 4538 w->param.eapdbtl); 4539 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4540 w->param.outamp_cap != 0) 4541 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4542 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4543 w->param.inamp_cap != 0) 4544 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4545 device_printf(sc->dev, " connections: %d\n", w->nconns); 4546 for (j = 0; j < w->nconns; j++) { 4547 cw = hdac_widget_get(devinfo, w->conns[j]); 4548 device_printf(sc->dev, " |\n"); 4549 device_printf(sc->dev, " + <- nid=%d [%s]", 4550 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4551 if (cw == NULL) 4552 printf(" [UNKNOWN]"); 4553 else if (cw->enable == 0) 4554 printf(" [DISABLED]"); 4555 if (w->nconns > 1 && w->selconn == j && w->type != 4556 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4557 printf(" (selected)"); 4558 printf("\n"); 4559 } 4560 } 4561 4562} 4563 4564static int 4565hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4566{ 4567 struct hdac_widget *w, *cw; 4568 struct hdac_softc *sc = devinfo->codec->sc; 4569 int i; 4570 4571 if (depth > HDA_PARSE_MAXDEPTH) 4572 return (0); 4573 4574 w = hdac_widget_get(devinfo, nid); 4575 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4576 return (0); 4577 4578 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4579 device_printf(sc->dev, "\n"); 4580 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4581 device_printf(sc->dev, " ^\n"); 4582 device_printf(sc->dev, " |\n"); 4583 device_printf(sc->dev, " +-----<------+\n"); 4584 } else { 4585 device_printf(sc->dev, " ^\n"); 4586 device_printf(sc->dev, " |\n"); 4587 device_printf(sc->dev, " "); 4588 printf(" nid=%d [%s]\n", w->nid, w->name); 4589 } 4590 4591 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4592 return (1); 4593 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4594 for (i = 0; i < w->nconns; i++) { 4595 cw = hdac_widget_get(devinfo, w->conns[i]); 4596 if (cw == NULL || cw->enable == 0 || cw->type == 4597 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4598 continue; 4599 if (hdac_dump_dac_internal(devinfo, cw->nid, 4600 depth + 1) != 0) 4601 return (1); 4602 } 4603 } else if ((w->type == 4604 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4605 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4606 w->selconn > -1 && w->selconn < w->nconns) { 4607 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4608 depth + 1) != 0) 4609 return (1); 4610 } 4611 4612 return (0); 4613} 4614 4615static void 4616hdac_dump_dac(struct hdac_devinfo *devinfo) 4617{ 4618 struct hdac_widget *w; 4619 struct hdac_softc *sc = devinfo->codec->sc; 4620 int i, printed = 0; 4621 4622 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4623 w = hdac_widget_get(devinfo, i); 4624 if (w == NULL || w->enable == 0) 4625 continue; 4626 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4627 !(w->pflags & HDA_DAC_PATH)) 4628 continue; 4629 if (printed == 0) { 4630 printed = 1; 4631 device_printf(sc->dev, "\n"); 4632 device_printf(sc->dev, "Playback path:\n"); 4633 } 4634 hdac_dump_dac_internal(devinfo, w->nid, 0); 4635 } 4636} 4637 4638static void 4639hdac_dump_adc(struct hdac_devinfo *devinfo) 4640{ 4641 struct hdac_widget *w, *cw; 4642 struct hdac_softc *sc = devinfo->codec->sc; 4643 int i, j; 4644 int printed = 0; 4645 char ossdevs[256]; 4646 4647 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4648 w = hdac_widget_get(devinfo, i); 4649 if (w == NULL || w->enable == 0) 4650 continue; 4651 if (!(w->pflags & HDA_ADC_RECSEL)) 4652 continue; 4653 if (printed == 0) { 4654 printed = 1; 4655 device_printf(sc->dev, "\n"); 4656 device_printf(sc->dev, "Recording sources:\n"); 4657 } 4658 device_printf(sc->dev, "\n"); 4659 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4660 for (j = 0; j < w->nconns; j++) { 4661 cw = hdac_widget_get(devinfo, w->conns[j]); 4662 if (cw == NULL || cw->enable == 0) 4663 continue; 4664 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4665 ossdevs, sizeof(ossdevs)); 4666 device_printf(sc->dev, " |\n"); 4667 device_printf(sc->dev, " + <- nid=%d [%s]", 4668 cw->nid, cw->name); 4669 if (strlen(ossdevs) > 0) { 4670 printf(" [recsrc: %s]", ossdevs); 4671 } 4672 printf("\n"); 4673 } 4674 } 4675} 4676 4677static void 4678hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4679{ 4680 nid_t *nids; 4681 4682 if (pcnt > 0) { 4683 device_printf(sc->dev, "\n"); 4684 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4685 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4686 sc->play.supp_pcm_size_rate); 4687 device_printf(sc->dev, " DAC:"); 4688 for (nids = sc->play.io; *nids != -1; nids++) 4689 printf(" %d", *nids); 4690 printf("\n"); 4691 } 4692 4693 if (rcnt > 0) { 4694 device_printf(sc->dev, "\n"); 4695 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4696 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4697 sc->rec.supp_pcm_size_rate); 4698 device_printf(sc->dev, " ADC:"); 4699 for (nids = sc->rec.io; *nids != -1; nids++) 4700 printf(" %d", *nids); 4701 printf("\n"); 4702 } 4703} 4704 4705static void 4706hdac_release_resources(struct hdac_softc *sc) 4707{ 4708 struct hdac_devinfo *devinfo = NULL; 4709 device_t *devlist = NULL; 4710 int i, devcount; 4711 4712 if (sc == NULL) 4713 return; 4714 4715 hdac_lock(sc); 4716 if (sc->polling != 0) 4717 callout_stop(&sc->poll_hdac); 4718 hdac_reset(sc); 4719 hdac_unlock(sc); 4720 snd_mtxfree(sc->lock); 4721 4722 device_get_children(sc->dev, &devlist, &devcount); 4723 for (i = 0; devlist != NULL && i < devcount; i++) { 4724 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4725 if (devinfo == NULL) 4726 continue; 4727 if (devinfo->widget != NULL) 4728 free(devinfo->widget, M_HDAC); 4729 if (devinfo->node_type == 4730 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4731 devinfo->function.audio.ctl != NULL) 4732 free(devinfo->function.audio.ctl, M_HDAC); 4733 free(devinfo, M_HDAC); 4734 device_delete_child(sc->dev, devlist[i]); 4735 } 4736 if (devlist != NULL) 4737 free(devlist, M_TEMP); 4738 4739 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4740 if (sc->codecs[i] != NULL) 4741 free(sc->codecs[i], M_HDAC); 4742 sc->codecs[i] = NULL; 4743 } 4744 4745 hdac_dma_free(&sc->rirb_dma); 4746 hdac_dma_free(&sc->corb_dma); 4747 if (sc->play.blkcnt > 0) 4748 hdac_dma_free(&sc->play.bdl_dma); 4749 if (sc->rec.blkcnt > 0) 4750 hdac_dma_free(&sc->rec.bdl_dma); 4751 hdac_irq_free(sc); 4752 hdac_mem_free(sc); 4753 free(sc, M_DEVBUF); 4754 4755} 4756 4757/* This function surely going to make its way into upper level someday. */ 4758static void 4759hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4760{ 4761 const char *res = NULL; 4762 int i = 0, j, k, len, inv; 4763 4764 if (on != NULL) 4765 *on = 0; 4766 if (off != NULL) 4767 *off = 0; 4768 if (sc == NULL) 4769 return; 4770 if (resource_string_value(device_get_name(sc->dev), 4771 device_get_unit(sc->dev), "config", &res) != 0) 4772 return; 4773 if (!(res != NULL && strlen(res) > 0)) 4774 return; 4775 HDA_BOOTVERBOSE( 4776 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4777 ); 4778 for (;;) { 4779 while (res[i] != '\0' && 4780 (res[i] == ',' || isspace(res[i]) != 0)) 4781 i++; 4782 if (res[i] == '\0') { 4783 HDA_BOOTVERBOSE( 4784 printf("\n"); 4785 ); 4786 return; 4787 } 4788 j = i; 4789 while (res[j] != '\0' && 4790 !(res[j] == ',' || isspace(res[j]) != 0)) 4791 j++; 4792 len = j - i; 4793 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4794 inv = 2; 4795 else 4796 inv = 0; 4797 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4798 if (strncmp(res + i + inv, 4799 hdac_quirks_tab[k].key, len - inv) != 0) 4800 continue; 4801 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4802 break; 4803 HDA_BOOTVERBOSE( 4804 printf(" %s%s", (inv != 0) ? "no" : "", 4805 hdac_quirks_tab[k].key); 4806 ); 4807 if (inv == 0 && on != NULL) 4808 *on |= hdac_quirks_tab[k].value; 4809 else if (inv != 0 && off != NULL) 4810 *off |= hdac_quirks_tab[k].value; 4811 break; 4812 } 4813 i = j; 4814 } 4815} 4816 4817#ifdef SND_DYNSYSCTL 4818static int 4819sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4820{ 4821 struct hdac_softc *sc; 4822 struct hdac_devinfo *devinfo; 4823 device_t dev; 4824 uint32_t ctl; 4825 int err, val; 4826 4827 dev = oidp->oid_arg1; 4828 devinfo = pcm_getdevinfo(dev); 4829 if (devinfo == NULL || devinfo->codec == NULL || 4830 devinfo->codec->sc == NULL) 4831 return (EINVAL); 4832 sc = devinfo->codec->sc; 4833 hdac_lock(sc); 4834 val = sc->polling; 4835 hdac_unlock(sc); 4836 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4837 4838 if (err || req->newptr == NULL) 4839 return (err); 4840 if (val < 0 || val > 1) 4841 return (EINVAL); 4842 4843 hdac_lock(sc); 4844 if (val != sc->polling) { 4845 if (hda_chan_active(sc) != 0) 4846 err = EBUSY; 4847 else if (val == 0) { 4848 callout_stop(&sc->poll_hdac); 4849 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 4850 sc->rirb_size / 2); 4851 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4852 ctl |= HDAC_RIRBCTL_RINTCTL; 4853 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4854 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4855 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4856 sc->polling = 0; 4857 DELAY(1000); 4858 } else { 4859 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 4860 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 4861 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4862 ctl &= ~HDAC_RIRBCTL_RINTCTL; 4863 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4864 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 4865 sc); 4866 sc->polling = 1; 4867 DELAY(1000); 4868 } 4869 } 4870 hdac_unlock(sc); 4871 4872 return (err); 4873} 4874#endif 4875 4876static void 4877hdac_attach2(void *arg) 4878{ 4879 struct hdac_softc *sc; 4880 struct hdac_widget *w; 4881 struct hdac_audio_ctl *ctl; 4882 uint32_t quirks_on, quirks_off; 4883 int pcnt, rcnt; 4884 int i; 4885 char status[SND_STATUSLEN]; 4886 device_t *devlist = NULL; 4887 int devcount; 4888 struct hdac_devinfo *devinfo = NULL; 4889 4890 sc = (struct hdac_softc *)arg; 4891 4892 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4893 4894 HDA_BOOTVERBOSE( 4895 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4896 quirks_on, quirks_off); 4897 ); 4898 4899 hdac_lock(sc); 4900 4901 /* Remove ourselves from the config hooks */ 4902 if (sc->intrhook.ich_func != NULL) { 4903 config_intrhook_disestablish(&sc->intrhook); 4904 sc->intrhook.ich_func = NULL; 4905 } 4906 4907 /* Start the corb and rirb engines */ 4908 HDA_BOOTVERBOSE( 4909 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4910 ); 4911 hdac_corb_start(sc); 4912 HDA_BOOTVERBOSE( 4913 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4914 ); 4915 hdac_rirb_start(sc); 4916 4917 HDA_BOOTVERBOSE( 4918 device_printf(sc->dev, 4919 "HDA_DEBUG: Enabling controller interrupt...\n"); 4920 ); 4921 if (sc->polling == 0) 4922 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4923 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4924 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4925 HDAC_GCTL_UNSOL); 4926 4927 DELAY(1000); 4928 4929 HDA_BOOTVERBOSE( 4930 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4931 ); 4932 hdac_scan_codecs(sc); 4933 4934 device_get_children(sc->dev, &devlist, &devcount); 4935 for (i = 0; devlist != NULL && i < devcount; i++) { 4936 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4937 if (devinfo != NULL && devinfo->node_type == 4938 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4939 break; 4940 } else 4941 devinfo = NULL; 4942 } 4943 if (devlist != NULL) 4944 free(devlist, M_TEMP); 4945 4946 if (devinfo == NULL) { 4947 hdac_unlock(sc); 4948 device_printf(sc->dev, "Audio Function Group not found!\n"); 4949 hdac_release_resources(sc); 4950 return; 4951 } 4952 4953 HDA_BOOTVERBOSE( 4954 device_printf(sc->dev, 4955 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4956 devinfo->nid, devinfo->codec->cad); 4957 ); 4958 hdac_audio_parse(devinfo); 4959 HDA_BOOTVERBOSE( 4960 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4961 ); 4962 hdac_audio_ctl_parse(devinfo); 4963 HDA_BOOTVERBOSE( 4964 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4965 ); 4966 hdac_vendor_patch_parse(devinfo); 4967 if (quirks_on != 0) 4968 devinfo->function.audio.quirks |= quirks_on; 4969 if (quirks_off != 0) 4970 devinfo->function.audio.quirks &= ~quirks_off; 4971 4972 /* XXX Disable all DIGITAL path. */ 4973 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4974 w = hdac_widget_get(devinfo, i); 4975 if (w == NULL) 4976 continue; 4977 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4978 w->enable = 0; 4979 continue; 4980 } 4981 /* XXX Disable useless pin ? */ 4982 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4983 (w->wclass.pin.config & 4984 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4985 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4986 w->enable = 0; 4987 } 4988 i = 0; 4989 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4990 if (ctl->widget == NULL) 4991 continue; 4992 w = ctl->widget; 4993 if (w->enable == 0) 4994 ctl->enable = 0; 4995 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4996 ctl->enable = 0; 4997 w = ctl->childwidget; 4998 if (w == NULL) 4999 continue; 5000 if (w->enable == 0 || 5001 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5002 ctl->enable = 0; 5003 } 5004 5005 HDA_BOOTVERBOSE( 5006 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5007 ); 5008 hdac_audio_build_tree(devinfo); 5009 5010 HDA_BOOTVERBOSE( 5011 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5012 ); 5013 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5014 HDA_BOOTVERBOSE( 5015 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5016 ); 5017 hdac_audio_ctl_commit(devinfo); 5018 5019 HDA_BOOTVERBOSE( 5020 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5021 ); 5022 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5023 HDA_BOOTVERBOSE( 5024 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5025 ); 5026 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5027 5028 hdac_unlock(sc); 5029 HDA_BOOTVERBOSE( 5030 device_printf(sc->dev, 5031 "HDA_DEBUG: OSS mixer initialization...\n"); 5032 ); 5033 5034 /* 5035 * There is no point of return after this. If the driver failed, 5036 * so be it. Let the detach procedure do all the cleanup. 5037 */ 5038 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5039 device_printf(sc->dev, "Can't register mixer\n"); 5040 5041 if (pcnt > 0) 5042 pcnt = 1; 5043 if (rcnt > 0) 5044 rcnt = 1; 5045 5046 HDA_BOOTVERBOSE( 5047 device_printf(sc->dev, 5048 "HDA_DEBUG: Registering PCM channels...\n"); 5049 ); 5050 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5051 device_printf(sc->dev, "Can't register PCM\n"); 5052 5053 sc->registered++; 5054 5055 for (i = 0; i < pcnt; i++) 5056 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5057 for (i = 0; i < rcnt; i++) 5058 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5059 5060#ifdef SND_DYNSYSCTL 5061 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5062 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5063 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5064 sysctl_hdac_polling, "I", "Enable polling mode"); 5065#endif 5066 5067 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5068 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5069 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5070 pcm_setstatus(sc->dev, status); 5071 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5072 HDA_BOOTVERBOSE( 5073 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5074 hdac_codec_id(devinfo)); 5075 ); 5076 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5077 HDA_DRV_TEST_REV); 5078 5079 HDA_BOOTVERBOSE( 5080 if (devinfo->function.audio.quirks != 0) { 5081 device_printf(sc->dev, "\n"); 5082 device_printf(sc->dev, "HDA config/quirks:"); 5083 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5084 if (devinfo->function.audio.quirks & 5085 hdac_quirks_tab[i].value) 5086 printf(" %s", hdac_quirks_tab[i].key); 5087 } 5088 printf("\n"); 5089 } 5090 device_printf(sc->dev, "\n"); 5091 device_printf(sc->dev, "+-------------------+\n"); 5092 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5093 device_printf(sc->dev, "+-------------------+\n"); 5094 hdac_dump_nodes(devinfo); 5095 device_printf(sc->dev, "\n"); 5096 device_printf(sc->dev, "+------------------------+\n"); 5097 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5098 device_printf(sc->dev, "+------------------------+\n"); 5099 device_printf(sc->dev, "\n"); 5100 i = 0; 5101 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5102 device_printf(sc->dev, "%3d: nid=%d", i, 5103 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5104 if (ctl->childwidget != NULL) 5105 printf(" cnid=%d", ctl->childwidget->nid); 5106 printf(" dir=0x%x index=%d " 5107 "ossmask=0x%08x ossdev=%d%s\n", 5108 ctl->dir, ctl->index, 5109 ctl->ossmask, ctl->ossdev, 5110 (ctl->enable == 0) ? " [DISABLED]" : ""); 5111 } 5112 device_printf(sc->dev, "\n"); 5113 device_printf(sc->dev, "+-----------------------------------+\n"); 5114 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5115 device_printf(sc->dev, "+-----------------------------------+\n"); 5116 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5117 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5118 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5119 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5120 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5121 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5122 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5123 hdac_dump_ctls(devinfo, NULL, 0); 5124 hdac_dump_dac(devinfo); 5125 hdac_dump_adc(devinfo); 5126 device_printf(sc->dev, "\n"); 5127 device_printf(sc->dev, "+--------------------------------------+\n"); 5128 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5129 device_printf(sc->dev, "+--------------------------------------+\n"); 5130 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5131 ); 5132 5133 if (sc->polling != 0) { 5134 hdac_lock(sc); 5135 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5136 hdac_unlock(sc); 5137 } 5138} 5139 5140/**************************************************************************** 5141 * int hdac_detach(device_t) 5142 * 5143 * Detach and free up resources utilized by the hdac device. 5144 ****************************************************************************/ 5145static int 5146hdac_detach(device_t dev) 5147{ 5148 struct hdac_softc *sc = NULL; 5149 struct hdac_devinfo *devinfo = NULL; 5150 int err; 5151 5152 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5153 if (devinfo != NULL && devinfo->codec != NULL) 5154 sc = devinfo->codec->sc; 5155 if (sc == NULL) 5156 return (0); 5157 5158 if (sc->registered > 0) { 5159 err = pcm_unregister(dev); 5160 if (err != 0) 5161 return (err); 5162 } 5163 5164 hdac_release_resources(sc); 5165 5166 return (0); 5167} 5168 5169static device_method_t hdac_methods[] = { 5170 /* device interface */ 5171 DEVMETHOD(device_probe, hdac_probe), 5172 DEVMETHOD(device_attach, hdac_attach), 5173 DEVMETHOD(device_detach, hdac_detach), 5174 { 0, 0 } 5175}; 5176 5177static driver_t hdac_driver = { 5178 "pcm", 5179 hdac_methods, 5180 PCM_SOFTC_SIZE, 5181}; 5182 5183DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5184MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5185MODULE_VERSION(snd_hda, 1); 5186