hdac.c revision 164614
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061111_0034" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 164614 2006-11-26 12:24:06Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 193#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 194 195/* IBM / Lenovo */ 196#define IBM_VENDORID 0x1014 197#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 198#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 199 200/* Lenovo */ 201#define LNV_VENDORID 0x17aa 202#define LNV_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LNV, 0x2066) 203#define LNV_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LNV, 0xffff) 204 205 206/* Misc constants.. */ 207#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 208#define HDA_AMP_MUTE_NONE (0) 209#define HDA_AMP_MUTE_LEFT (1 << 0) 210#define HDA_AMP_MUTE_RIGHT (1 << 1) 211#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 212 213#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 214#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 215 216#define HDA_DAC_PATH (1 << 0) 217#define HDA_ADC_PATH (1 << 1) 218#define HDA_ADC_RECSEL (1 << 2) 219 220#define HDA_CTL_OUT (1 << 0) 221#define HDA_CTL_IN (1 << 1) 222#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 223 224#define HDA_GPIO_MAX 15 225/* 0 - 14 = GPIO */ 226#define HDA_QUIRK_GPIO0 (1 << 0) 227#define HDA_QUIRK_GPIO1 (1 << 1) 228#define HDA_QUIRK_GPIO2 (1 << 2) 229#define HDA_QUIRK_SOFTPCMVOL (1 << 15) 230#define HDA_QUIRK_FIXEDRATE (1 << 16) 231#define HDA_QUIRK_FORCESTEREO (1 << 17) 232#define HDA_QUIRK_EAPDINV (1 << 18) 233 234static const struct { 235 char *key; 236 uint32_t value; 237} hdac_quirks_tab[] = { 238 { "gpio0", HDA_QUIRK_GPIO0 }, 239 { "gpio1", HDA_QUIRK_GPIO1 }, 240 { "gpio2", HDA_QUIRK_GPIO2 }, 241 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 242 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 243 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 244 { "eapdinv", HDA_QUIRK_EAPDINV }, 245}; 246#define HDAC_QUIRKS_TAB_LEN \ 247 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 248 249#define HDA_BDL_MIN 2 250#define HDA_BDL_MAX 256 251#define HDA_BDL_DEFAULT HDA_BDL_MIN 252 253#define HDA_BUFSZ_MIN 4096 254#define HDA_BUFSZ_MAX 65536 255#define HDA_BUFSZ_DEFAULT 16384 256 257#define HDA_PARSE_MAXDEPTH 10 258 259#define HDAC_UNSOLTAG_EVENT_HP 0x00 260 261static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 262 263enum { 264 HDA_PARSE_MIXER, 265 HDA_PARSE_DIRECT 266}; 267 268/* Default */ 269static uint32_t hdac_fmt[] = { 270 AFMT_STEREO | AFMT_S16_LE, 271 0 272}; 273 274static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 275 276static const struct { 277 uint32_t model; 278 char *desc; 279} hdac_devices[] = { 280 { HDA_INTEL_82801F, "Intel 82801F" }, 281 { HDA_INTEL_82801G, "Intel 82801G" }, 282 { HDA_INTEL_82801H, "Intel 82801H" }, 283 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 284 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 285 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 286 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 287 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 288 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 289 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 290 { HDA_ATI_SB450, "ATI SB450" }, 291 { HDA_ATI_SB600, "ATI SB600" }, 292 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 293 { HDA_SIS_966, "SiS 966" }, 294 /* Unknown */ 295 { HDA_INTEL_ALL, "Intel (Unknown)" }, 296 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 297 { HDA_ATI_ALL, "ATI (Unknown)" }, 298 { HDA_VIA_ALL, "VIA (Unknown)" }, 299 { HDA_SIS_ALL, "SiS (Unknown)" }, 300}; 301#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 302 303static const struct { 304 uint32_t rate; 305 int valid; 306 uint16_t base; 307 uint16_t mul; 308 uint16_t div; 309} hda_rate_tab[] = { 310 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 311 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 312 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 313 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 314 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 315 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 316 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 317 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 318 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 319 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 320 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 321 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 322 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 323 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 324 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 325 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 326 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 327 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 328 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 329 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 330 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 331 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 332 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 333 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 334 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 335 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 336 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 337 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 338 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 339 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 340 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 341 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 342 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 343 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 344 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 345}; 346#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 347 348/* All codecs you can eat... */ 349#define HDA_CODEC_CONSTRUCT(vendor, id) \ 350 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 351 352/* Realtek */ 353#define REALTEK_VENDORID 0x10ec 354#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 355#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 356#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 357#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 358#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 359#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 360 361/* Analog Device */ 362#define ANALOGDEVICE_VENDORID 0x11d4 363#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 364#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 365#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 366#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 367 368/* CMedia */ 369#define CMEDIA_VENDORID 0x434d 370#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 371#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 372 373/* Sigmatel */ 374#define SIGMATEL_VENDORID 0x8384 375#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 376#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 377#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 378#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 379#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 380 381/* 382 * Conexant 383 * 384 * Ok, the truth is, I don't have any idea at all whether 385 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 386 * place that tell me it is "Venice" is from its Windows driver INF. 387 * 388 * Venice - CX????? 389 * Waikiki - CX20551-22 390 */ 391#define CONEXANT_VENDORID 0x14f1 392#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 393#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 394#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 395 396 397/* Codecs */ 398static const struct { 399 uint32_t id; 400 char *name; 401} hdac_codecs[] = { 402 { HDA_CODEC_ALC260, "Realtek ALC260" }, 403 { HDA_CODEC_ALC861, "Realtek ALC861" }, 404 { HDA_CODEC_ALC880, "Realtek ALC880" }, 405 { HDA_CODEC_ALC882, "Realtek ALC882" }, 406 { HDA_CODEC_ALC883, "Realtek ALC883" }, 407 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 408 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 409 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 410 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 411 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 412 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 413 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 414 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 415 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 416 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 417 /* Unknown codec */ 418 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 419 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 420 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 421 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 422 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 423}; 424#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 425 426enum { 427 HDAC_HP_SWITCH_CTL, 428 HDAC_HP_SWITCH_CTRL 429}; 430 431static const struct { 432 uint32_t model; 433 uint32_t id; 434 int type; 435 nid_t hpnid; 436 nid_t spkrnid[8]; 437 nid_t eapdnid; 438} hdac_hp_switch[] = { 439 /* Specific OEM models */ 440 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 441 17, { 16, -1 }, 16 }, 442 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 443 6, { 5, -1 }, 5 }, 444 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 445 6, { 5, -1 }, 5 }, 446 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 447 13, { 14, -1 }, -1 }, 448 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 449 13, { 14, -1 }, -1 }, 450 /* 451 * All models that at least come from the same vendor with 452 * simmilar codec. 453 */ 454 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 455 17, { 16, -1 }, 16 }, 456 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 457 6, { 5, -1 }, 5 }, 458 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 459 13, { 14, -1 }, -1 }, 460}; 461#define HDAC_HP_SWITCH_LEN \ 462 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 463 464static const struct { 465 uint32_t model; 466 uint32_t id; 467 nid_t eapdnid; 468 int hp_switch; 469} hdac_eapd_switch[] = { 470 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 471 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 472 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 473}; 474#define HDAC_EAPD_SWITCH_LEN \ 475 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 476 477/**************************************************************************** 478 * Function prototypes 479 ****************************************************************************/ 480static void hdac_intr_handler(void *); 481static int hdac_reset(struct hdac_softc *); 482static int hdac_get_capabilities(struct hdac_softc *); 483static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 484static int hdac_dma_alloc(struct hdac_softc *, 485 struct hdac_dma *, bus_size_t); 486static void hdac_dma_free(struct hdac_dma *); 487static int hdac_mem_alloc(struct hdac_softc *); 488static void hdac_mem_free(struct hdac_softc *); 489static int hdac_irq_alloc(struct hdac_softc *); 490static void hdac_irq_free(struct hdac_softc *); 491static void hdac_corb_init(struct hdac_softc *); 492static void hdac_rirb_init(struct hdac_softc *); 493static void hdac_corb_start(struct hdac_softc *); 494static void hdac_rirb_start(struct hdac_softc *); 495static void hdac_scan_codecs(struct hdac_softc *); 496static int hdac_probe_codec(struct hdac_codec *); 497static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 498static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 499 500static void hdac_attach2(void *); 501 502static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 503 uint32_t, int); 504static void hdac_command_send_internal(struct hdac_softc *, 505 struct hdac_command_list *, int); 506 507static int hdac_probe(device_t); 508static int hdac_attach(device_t); 509static int hdac_detach(device_t); 510static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 511static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 512 uint32_t, int, int); 513static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 514 nid_t, int, int); 515static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 516 nid_t, nid_t, int, int, int, int, int, int); 517static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 518static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 519 520static int hdac_rirb_flush(struct hdac_softc *sc); 521static int hdac_unsolq_flush(struct hdac_softc *sc); 522 523#define hdac_command(a1, a2, a3) \ 524 hdac_command_sendone_internal(a1, a2, a3) 525 526#define hdac_codec_id(d) \ 527 ((uint32_t)((d == NULL) ? 0x00000000 : \ 528 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 529 ((uint32_t)(d)->device_id & 0x0000ffff)))) 530 531static char * 532hdac_codec_name(struct hdac_devinfo *devinfo) 533{ 534 uint32_t id; 535 int i; 536 537 id = hdac_codec_id(devinfo); 538 539 for (i = 0; i < HDAC_CODECS_LEN; i++) { 540 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 541 return (hdac_codecs[i].name); 542 } 543 544 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 545} 546 547static char * 548hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 549{ 550 static char *ossname[] = SOUND_DEVICE_NAMES; 551 static char *unknown = "???"; 552 int i; 553 554 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 555 if (devmask & (1 << i)) 556 return (ossname[i]); 557 } 558 return (unknown); 559} 560 561static void 562hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 563{ 564 static char *ossname[] = SOUND_DEVICE_NAMES; 565 int i, first = 1; 566 567 bzero(buf, len); 568 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 569 if (mask & (1 << i)) { 570 if (first == 0) 571 strlcat(buf, ", ", len); 572 strlcat(buf, ossname[i], len); 573 first = 0; 574 } 575 } 576} 577 578static struct hdac_audio_ctl * 579hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 580{ 581 if (devinfo == NULL || 582 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 583 index == NULL || devinfo->function.audio.ctl == NULL || 584 devinfo->function.audio.ctlcnt < 1 || 585 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 586 return (NULL); 587 return (&devinfo->function.audio.ctl[(*index)++]); 588} 589 590static struct hdac_audio_ctl * 591hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 592 int index, int cnt) 593{ 594 struct hdac_audio_ctl *ctl, *retctl = NULL; 595 int i, at, atindex, found = 0; 596 597 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 598 return (NULL); 599 600 at = cnt; 601 if (at == 0) 602 at = 1; 603 else if (at < 0) 604 at = -1; 605 atindex = index; 606 if (atindex < 0) 607 atindex = -1; 608 609 i = 0; 610 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 611 if (ctl->enable == 0 || ctl->widget == NULL) 612 continue; 613 if (!(ctl->widget->nid == nid && (atindex == -1 || 614 ctl->index == atindex))) 615 continue; 616 found++; 617 if (found == cnt) 618 return (ctl); 619 retctl = ctl; 620 } 621 622 return ((at == -1) ? retctl : NULL); 623} 624 625static void 626hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 627{ 628 struct hdac_softc *sc; 629 struct hdac_widget *w; 630 struct hdac_audio_ctl *ctl; 631 uint32_t id, res; 632 int i = 0, j, forcemute; 633 nid_t cad; 634 635 if (devinfo == NULL || devinfo->codec == NULL || 636 devinfo->codec->sc == NULL) 637 return; 638 639 sc = devinfo->codec->sc; 640 cad = devinfo->codec->cad; 641 id = hdac_codec_id(devinfo); 642 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 643 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 644 sc->pci_subvendor) && 645 hdac_hp_switch[i].id == id) 646 break; 647 } 648 649 if (i >= HDAC_HP_SWITCH_LEN) 650 return; 651 652 forcemute = 0; 653 if (hdac_hp_switch[i].eapdnid != -1) { 654 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 655 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 656 forcemute = (w->param.eapdbtl & 657 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 658 } 659 660 res = hdac_command(sc, 661 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 662 HDA_BOOTVERBOSE( 663 device_printf(sc->dev, 664 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 665 hdac_hp_switch[i].hpnid, res); 666 ); 667 res >>= 31; 668 669 switch (hdac_hp_switch[i].type) { 670 case HDAC_HP_SWITCH_CTL: 671 ctl = hdac_audio_ctl_amp_get(devinfo, 672 hdac_hp_switch[i].hpnid, 0, 1); 673 if (ctl != NULL) { 674 ctl->muted = (res != 0 && forcemute == 0) ? 675 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 676 hdac_audio_ctl_amp_set(ctl, 677 HDA_AMP_MUTE_DEFAULT, ctl->left, 678 ctl->right); 679 } 680 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 681 ctl = hdac_audio_ctl_amp_get(devinfo, 682 hdac_hp_switch[i].spkrnid[j], 0, 1); 683 if (ctl != NULL) { 684 ctl->muted = (res != 0 || forcemute == 1) ? 685 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 686 hdac_audio_ctl_amp_set(ctl, 687 HDA_AMP_MUTE_DEFAULT, ctl->left, 688 ctl->right); 689 } 690 } 691 break; 692 case HDAC_HP_SWITCH_CTRL: 693 if (res != 0) { 694 /* HP in */ 695 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 696 if (w != NULL && w->type == 697 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 698 if (forcemute == 0) 699 w->wclass.pin.ctrl |= 700 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 701 else 702 w->wclass.pin.ctrl &= 703 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 704 hdac_command(sc, 705 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 706 w->wclass.pin.ctrl), cad); 707 } 708 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 709 w = hdac_widget_get(devinfo, 710 hdac_hp_switch[i].spkrnid[j]); 711 if (w != NULL && w->type == 712 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 713 w->wclass.pin.ctrl &= 714 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 715 hdac_command(sc, 716 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 717 w->nid, 718 w->wclass.pin.ctrl), cad); 719 } 720 } 721 } else { 722 /* HP out */ 723 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 724 if (w != NULL && w->type == 725 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 726 w->wclass.pin.ctrl &= 727 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 728 hdac_command(sc, 729 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 730 w->wclass.pin.ctrl), cad); 731 } 732 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 733 w = hdac_widget_get(devinfo, 734 hdac_hp_switch[i].spkrnid[j]); 735 if (w != NULL && w->type == 736 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 737 if (forcemute == 0) 738 w->wclass.pin.ctrl |= 739 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 740 else 741 w->wclass.pin.ctrl &= 742 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 743 hdac_command(sc, 744 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 745 w->nid, 746 w->wclass.pin.ctrl), cad); 747 } 748 } 749 } 750 break; 751 default: 752 break; 753 } 754} 755 756static void 757hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 758{ 759 struct hdac_softc *sc; 760 struct hdac_devinfo *devinfo = NULL; 761 device_t *devlist = NULL; 762 int devcount, i; 763 764 if (codec == NULL || codec->sc == NULL) 765 return; 766 767 sc = codec->sc; 768 769 HDA_BOOTVERBOSE( 770 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 771 ); 772 773 device_get_children(sc->dev, &devlist, &devcount); 774 for (i = 0; devlist != NULL && i < devcount; i++) { 775 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 776 if (devinfo != NULL && devinfo->node_type == 777 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 778 devinfo->codec != NULL && 779 devinfo->codec->cad == codec->cad) { 780 break; 781 } else 782 devinfo = NULL; 783 } 784 if (devlist != NULL) 785 free(devlist, M_TEMP); 786 787 if (devinfo == NULL) 788 return; 789 790 switch (tag) { 791 case HDAC_UNSOLTAG_EVENT_HP: 792 hdac_hp_switch_handler(devinfo); 793 break; 794 default: 795 break; 796 } 797} 798 799static int 800hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 801{ 802 /* XXX to be removed */ 803#ifdef HDAC_INTR_EXTRA 804 uint32_t res; 805#endif 806 807 if (ch->blkcnt == 0) 808 return (0); 809 810 /* XXX to be removed */ 811#ifdef HDAC_INTR_EXTRA 812 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 813#endif 814 815 /* XXX to be removed */ 816#ifdef HDAC_INTR_EXTRA 817 HDA_BOOTVERBOSE( 818 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 819 device_printf(sc->dev, 820 "PCMDIR_%s intr triggered beyond stream boundary:" 821 "%08x\n", 822 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 823 ); 824#endif 825 826 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 827 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 828 829 /* XXX to be removed */ 830#ifdef HDAC_INTR_EXTRA 831 if (res & HDAC_SDSTS_BCIS) { 832#endif 833 return (1); 834 /* XXX to be removed */ 835#ifdef HDAC_INTR_EXTRA 836 } 837#endif 838 839 return (0); 840} 841 842/**************************************************************************** 843 * void hdac_intr_handler(void *) 844 * 845 * Interrupt handler. Processes interrupts received from the hdac. 846 ****************************************************************************/ 847static void 848hdac_intr_handler(void *context) 849{ 850 struct hdac_softc *sc; 851 uint32_t intsts; 852 uint8_t rirbsts; 853 struct hdac_rirb *rirb_base; 854 uint32_t trigger = 0; 855 856 sc = (struct hdac_softc *)context; 857 858 hdac_lock(sc); 859 if (sc->polling != 0) { 860 hdac_unlock(sc); 861 return; 862 } 863 /* Do we have anything to do? */ 864 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 865 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 866 hdac_unlock(sc); 867 return; 868 } 869 870 /* Was this a controller interrupt? */ 871 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 872 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 873 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 874 /* Get as many responses that we can */ 875 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 876 HDAC_WRITE_1(&sc->mem, 877 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 878 hdac_rirb_flush(sc); 879 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 880 } 881 /* XXX to be removed */ 882 /* Clear interrupt and exit */ 883#ifdef HDAC_INTR_EXTRA 884 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 885#endif 886 } 887 888 hdac_unsolq_flush(sc); 889 890 if (intsts & HDAC_INTSTS_SIS_MASK) { 891 if ((intsts & (1 << sc->num_iss)) && 892 hdac_stream_intr(sc, &sc->play) != 0) 893 trigger |= 1; 894 if ((intsts & (1 << 0)) && 895 hdac_stream_intr(sc, &sc->rec) != 0) 896 trigger |= 2; 897 /* XXX to be removed */ 898#ifdef HDAC_INTR_EXTRA 899 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 900 HDAC_INTSTS_SIS_MASK); 901#endif 902 } 903 904 hdac_unlock(sc); 905 906 if (trigger & 1) 907 chn_intr(sc->play.c); 908 if (trigger & 2) 909 chn_intr(sc->rec.c); 910} 911 912/**************************************************************************** 913 * int hdac_reset(hdac_softc *) 914 * 915 * Reset the hdac to a quiescent and known state. 916 ****************************************************************************/ 917static int 918hdac_reset(struct hdac_softc *sc) 919{ 920 uint32_t gctl; 921 int count, i; 922 923 /* 924 * Stop all Streams DMA engine 925 */ 926 for (i = 0; i < sc->num_iss; i++) 927 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 928 for (i = 0; i < sc->num_oss; i++) 929 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 930 for (i = 0; i < sc->num_bss; i++) 931 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 932 933 /* 934 * Stop Control DMA engines 935 */ 936 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 937 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 938 939 /* 940 * Reset the controller. The reset must remain asserted for 941 * a minimum of 100us. 942 */ 943 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 944 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 945 count = 10000; 946 do { 947 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 948 if (!(gctl & HDAC_GCTL_CRST)) 949 break; 950 DELAY(10); 951 } while (--count); 952 if (gctl & HDAC_GCTL_CRST) { 953 device_printf(sc->dev, "Unable to put hdac in reset\n"); 954 return (ENXIO); 955 } 956 DELAY(100); 957 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 958 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 959 count = 10000; 960 do { 961 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 962 if (gctl & HDAC_GCTL_CRST) 963 break; 964 DELAY(10); 965 } while (--count); 966 if (!(gctl & HDAC_GCTL_CRST)) { 967 device_printf(sc->dev, "Device stuck in reset\n"); 968 return (ENXIO); 969 } 970 971 /* 972 * Wait for codecs to finish their own reset sequence. The delay here 973 * should be of 250us but for some reasons, on it's not enough on my 974 * computer. Let's use twice as much as necessary to make sure that 975 * it's reset properly. 976 */ 977 DELAY(1000); 978 979 return (0); 980} 981 982 983/**************************************************************************** 984 * int hdac_get_capabilities(struct hdac_softc *); 985 * 986 * Retreive the general capabilities of the hdac; 987 * Number of Input Streams 988 * Number of Output Streams 989 * Number of bidirectional Streams 990 * 64bit ready 991 * CORB and RIRB sizes 992 ****************************************************************************/ 993static int 994hdac_get_capabilities(struct hdac_softc *sc) 995{ 996 uint16_t gcap; 997 uint8_t corbsize, rirbsize; 998 999 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1000 sc->num_iss = HDAC_GCAP_ISS(gcap); 1001 sc->num_oss = HDAC_GCAP_OSS(gcap); 1002 sc->num_bss = HDAC_GCAP_BSS(gcap); 1003 1004 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1005 1006 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1007 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1008 HDAC_CORBSIZE_CORBSZCAP_256) 1009 sc->corb_size = 256; 1010 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1011 HDAC_CORBSIZE_CORBSZCAP_16) 1012 sc->corb_size = 16; 1013 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1014 HDAC_CORBSIZE_CORBSZCAP_2) 1015 sc->corb_size = 2; 1016 else { 1017 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1018 __func__, corbsize); 1019 return (ENXIO); 1020 } 1021 1022 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1023 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1024 HDAC_RIRBSIZE_RIRBSZCAP_256) 1025 sc->rirb_size = 256; 1026 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1027 HDAC_RIRBSIZE_RIRBSZCAP_16) 1028 sc->rirb_size = 16; 1029 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1030 HDAC_RIRBSIZE_RIRBSZCAP_2) 1031 sc->rirb_size = 2; 1032 else { 1033 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1034 __func__, rirbsize); 1035 return (ENXIO); 1036 } 1037 1038 return (0); 1039} 1040 1041 1042/**************************************************************************** 1043 * void hdac_dma_cb 1044 * 1045 * This function is called by bus_dmamap_load when the mapping has been 1046 * established. We just record the physical address of the mapping into 1047 * the struct hdac_dma passed in. 1048 ****************************************************************************/ 1049static void 1050hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1051{ 1052 struct hdac_dma *dma; 1053 1054 if (error == 0) { 1055 dma = (struct hdac_dma *)callback_arg; 1056 dma->dma_paddr = segs[0].ds_addr; 1057 } 1058} 1059 1060static void 1061hdac_dma_nocache(void *ptr) 1062{ 1063#if defined(__i386__) || defined(__amd64__) 1064 pt_entry_t *pte; 1065 vm_offset_t va; 1066 1067 va = (vm_offset_t)ptr; 1068 pte = vtopte(va); 1069 if (pte) { 1070 *pte |= PG_N; 1071 invltlb(); 1072 } 1073#endif 1074} 1075 1076/**************************************************************************** 1077 * int hdac_dma_alloc 1078 * 1079 * This function allocate and setup a dma region (struct hdac_dma). 1080 * It must be freed by a corresponding hdac_dma_free. 1081 ****************************************************************************/ 1082static int 1083hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1084{ 1085 int result; 1086 int lowaddr; 1087 1088 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1089 BUS_SPACE_MAXADDR_32BIT; 1090 bzero(dma, sizeof(*dma)); 1091 1092 /* 1093 * Create a DMA tag 1094 */ 1095 result = bus_dma_tag_create(NULL, /* parent */ 1096 HDAC_DMA_ALIGNMENT, /* alignment */ 1097 0, /* boundary */ 1098 lowaddr, /* lowaddr */ 1099 BUS_SPACE_MAXADDR, /* highaddr */ 1100 NULL, /* filtfunc */ 1101 NULL, /* fistfuncarg */ 1102 size, /* maxsize */ 1103 1, /* nsegments */ 1104 size, /* maxsegsz */ 1105 0, /* flags */ 1106 NULL, /* lockfunc */ 1107 NULL, /* lockfuncarg */ 1108 &dma->dma_tag); /* dmat */ 1109 if (result != 0) { 1110 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1111 __func__, result); 1112 goto fail; 1113 } 1114 1115 /* 1116 * Allocate DMA memory 1117 */ 1118 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1119 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1120 if (result != 0) { 1121 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1122 __func__, result); 1123 goto fail; 1124 } 1125 1126 /* 1127 * Map the memory 1128 */ 1129 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1130 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1131 BUS_DMA_NOWAIT); 1132 if (result != 0 || dma->dma_paddr == 0) { 1133 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1134 __func__, result); 1135 goto fail; 1136 } 1137 bzero((void *)dma->dma_vaddr, size); 1138 hdac_dma_nocache(dma->dma_vaddr); 1139 1140 return (0); 1141fail: 1142 if (dma->dma_map != NULL) 1143 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1144 if (dma->dma_tag != NULL) 1145 bus_dma_tag_destroy(dma->dma_tag); 1146 return (result); 1147} 1148 1149 1150/**************************************************************************** 1151 * void hdac_dma_free(struct hdac_dma *) 1152 * 1153 * Free a struct dhac_dma that has been previously allocated via the 1154 * hdac_dma_alloc function. 1155 ****************************************************************************/ 1156static void 1157hdac_dma_free(struct hdac_dma *dma) 1158{ 1159 if (dma->dma_tag != NULL) { 1160 /* Flush caches */ 1161 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1162 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1163 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1164 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1165 bus_dma_tag_destroy(dma->dma_tag); 1166 } 1167} 1168 1169/**************************************************************************** 1170 * int hdac_mem_alloc(struct hdac_softc *) 1171 * 1172 * Allocate all the bus resources necessary to speak with the physical 1173 * controller. 1174 ****************************************************************************/ 1175static int 1176hdac_mem_alloc(struct hdac_softc *sc) 1177{ 1178 struct hdac_mem *mem; 1179 1180 mem = &sc->mem; 1181 mem->mem_rid = PCIR_BAR(0); 1182 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1183 &mem->mem_rid, RF_ACTIVE); 1184 if (mem->mem_res == NULL) { 1185 device_printf(sc->dev, 1186 "%s: Unable to allocate memory resource\n", __func__); 1187 return (ENOMEM); 1188 } 1189 mem->mem_tag = rman_get_bustag(mem->mem_res); 1190 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1191 1192 return (0); 1193} 1194 1195/**************************************************************************** 1196 * void hdac_mem_free(struct hdac_softc *) 1197 * 1198 * Free up resources previously allocated by hdac_mem_alloc. 1199 ****************************************************************************/ 1200static void 1201hdac_mem_free(struct hdac_softc *sc) 1202{ 1203 struct hdac_mem *mem; 1204 1205 mem = &sc->mem; 1206 if (mem->mem_res != NULL) 1207 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1208 mem->mem_res); 1209 mem->mem_res = NULL; 1210} 1211 1212/**************************************************************************** 1213 * int hdac_irq_alloc(struct hdac_softc *) 1214 * 1215 * Allocate and setup the resources necessary for interrupt handling. 1216 ****************************************************************************/ 1217static int 1218hdac_irq_alloc(struct hdac_softc *sc) 1219{ 1220 struct hdac_irq *irq; 1221 int result; 1222 1223 irq = &sc->irq; 1224 irq->irq_rid = 0x0; 1225 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1226 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1227 if (irq->irq_res == NULL) { 1228 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1229 __func__); 1230 goto fail; 1231 } 1232 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1233 hdac_intr_handler, sc, &irq->irq_handle); 1234 if (result != 0) { 1235 device_printf(sc->dev, 1236 "%s: Unable to setup interrupt handler (%x)\n", 1237 __func__, result); 1238 goto fail; 1239 } 1240 1241 return (0); 1242 1243fail: 1244 hdac_irq_free(sc); 1245 1246 return (ENXIO); 1247} 1248 1249/**************************************************************************** 1250 * void hdac_irq_free(struct hdac_softc *) 1251 * 1252 * Free up resources previously allocated by hdac_irq_alloc. 1253 ****************************************************************************/ 1254static void 1255hdac_irq_free(struct hdac_softc *sc) 1256{ 1257 struct hdac_irq *irq; 1258 1259 irq = &sc->irq; 1260 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1261 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1262 if (irq->irq_res != NULL) 1263 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1264 irq->irq_res); 1265 irq->irq_handle = NULL; 1266 irq->irq_res = NULL; 1267} 1268 1269/**************************************************************************** 1270 * void hdac_corb_init(struct hdac_softc *) 1271 * 1272 * Initialize the corb registers for operations but do not start it up yet. 1273 * The CORB engine must not be running when this function is called. 1274 ****************************************************************************/ 1275static void 1276hdac_corb_init(struct hdac_softc *sc) 1277{ 1278 uint8_t corbsize; 1279 uint64_t corbpaddr; 1280 1281 /* Setup the CORB size. */ 1282 switch (sc->corb_size) { 1283 case 256: 1284 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1285 break; 1286 case 16: 1287 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1288 break; 1289 case 2: 1290 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1291 break; 1292 default: 1293 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1294 } 1295 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1296 1297 /* Setup the CORB Address in the hdac */ 1298 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1299 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1300 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1301 1302 /* Set the WP and RP */ 1303 sc->corb_wp = 0; 1304 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1305 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1306 /* 1307 * The HDA specification indicates that the CORBRPRST bit will always 1308 * read as zero. Unfortunately, it seems that at least the 82801G 1309 * doesn't reset the bit to zero, which stalls the corb engine. 1310 * manually reset the bit to zero before continuing. 1311 */ 1312 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1313 1314 /* Enable CORB error reporting */ 1315#if 0 1316 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1317#endif 1318} 1319 1320/**************************************************************************** 1321 * void hdac_rirb_init(struct hdac_softc *) 1322 * 1323 * Initialize the rirb registers for operations but do not start it up yet. 1324 * The RIRB engine must not be running when this function is called. 1325 ****************************************************************************/ 1326static void 1327hdac_rirb_init(struct hdac_softc *sc) 1328{ 1329 uint8_t rirbsize; 1330 uint64_t rirbpaddr; 1331 1332 /* Setup the RIRB size. */ 1333 switch (sc->rirb_size) { 1334 case 256: 1335 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1336 break; 1337 case 16: 1338 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1339 break; 1340 case 2: 1341 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1342 break; 1343 default: 1344 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1345 } 1346 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1347 1348 /* Setup the RIRB Address in the hdac */ 1349 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1350 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1351 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1352 1353 /* Setup the WP and RP */ 1354 sc->rirb_rp = 0; 1355 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1356 1357 if (sc->polling == 0) { 1358 /* Setup the interrupt threshold */ 1359 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1360 1361 /* Enable Overrun and response received reporting */ 1362#if 0 1363 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1364 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1365#else 1366 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1367#endif 1368 } 1369 1370 /* 1371 * Make sure that the Host CPU cache doesn't contain any dirty 1372 * cache lines that falls in the rirb. If I understood correctly, it 1373 * should be sufficient to do this only once as the rirb is purely 1374 * read-only from now on. 1375 */ 1376 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1377 BUS_DMASYNC_PREREAD); 1378} 1379 1380/**************************************************************************** 1381 * void hdac_corb_start(hdac_softc *) 1382 * 1383 * Startup the corb DMA engine 1384 ****************************************************************************/ 1385static void 1386hdac_corb_start(struct hdac_softc *sc) 1387{ 1388 uint32_t corbctl; 1389 1390 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1391 corbctl |= HDAC_CORBCTL_CORBRUN; 1392 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1393} 1394 1395/**************************************************************************** 1396 * void hdac_rirb_start(hdac_softc *) 1397 * 1398 * Startup the rirb DMA engine 1399 ****************************************************************************/ 1400static void 1401hdac_rirb_start(struct hdac_softc *sc) 1402{ 1403 uint32_t rirbctl; 1404 1405 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1406 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1407 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1408} 1409 1410 1411/**************************************************************************** 1412 * void hdac_scan_codecs(struct hdac_softc *) 1413 * 1414 * Scan the bus for available codecs. 1415 ****************************************************************************/ 1416static void 1417hdac_scan_codecs(struct hdac_softc *sc) 1418{ 1419 struct hdac_codec *codec; 1420 int i; 1421 uint16_t statests; 1422 1423 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1424 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1425 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1426 /* We have found a codec. */ 1427 hdac_unlock(sc); 1428 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1429 M_HDAC, M_ZERO | M_NOWAIT); 1430 hdac_lock(sc); 1431 if (codec == NULL) { 1432 device_printf(sc->dev, 1433 "Unable to allocate memory for codec\n"); 1434 continue; 1435 } 1436 codec->commands = NULL; 1437 codec->responses_received = 0; 1438 codec->verbs_sent = 0; 1439 codec->sc = sc; 1440 codec->cad = i; 1441 sc->codecs[i] = codec; 1442 if (hdac_probe_codec(codec) != 0) 1443 break; 1444 } 1445 } 1446 /* All codecs have been probed, now try to attach drivers to them */ 1447 /* bus_generic_attach(sc->dev); */ 1448} 1449 1450/**************************************************************************** 1451 * void hdac_probe_codec(struct hdac_softc *, int) 1452 * 1453 * Probe a the given codec_id for available function groups. 1454 ****************************************************************************/ 1455static int 1456hdac_probe_codec(struct hdac_codec *codec) 1457{ 1458 struct hdac_softc *sc = codec->sc; 1459 struct hdac_devinfo *devinfo; 1460 uint32_t vendorid, revisionid, subnode; 1461 int startnode; 1462 int endnode; 1463 int i; 1464 nid_t cad = codec->cad; 1465 1466 HDA_BOOTVERBOSE( 1467 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1468 ); 1469 vendorid = hdac_command(sc, 1470 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1471 cad); 1472 revisionid = hdac_command(sc, 1473 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1474 cad); 1475 subnode = hdac_command(sc, 1476 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1477 cad); 1478 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1479 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1480 1481 HDA_BOOTVERBOSE( 1482 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1483 startnode, endnode); 1484 ); 1485 for (i = startnode; i < endnode; i++) { 1486 devinfo = hdac_probe_function(codec, i); 1487 if (devinfo != NULL) { 1488 /* XXX Ignore other FG. */ 1489 devinfo->vendor_id = 1490 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1491 devinfo->device_id = 1492 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1493 devinfo->revision_id = 1494 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1495 devinfo->stepping_id = 1496 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1497 HDA_BOOTVERBOSE( 1498 device_printf(sc->dev, 1499 "HDA_DEBUG: \tFound AFG nid=%d " 1500 "[startnode=%d endnode=%d]\n", 1501 devinfo->nid, startnode, endnode); 1502 ); 1503 return (1); 1504 } 1505 } 1506 1507 HDA_BOOTVERBOSE( 1508 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1509 ); 1510 return (0); 1511} 1512 1513static struct hdac_devinfo * 1514hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1515{ 1516 struct hdac_softc *sc = codec->sc; 1517 struct hdac_devinfo *devinfo; 1518 uint32_t fctgrptype; 1519 nid_t cad = codec->cad; 1520 1521 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1522 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1523 1524 /* XXX For now, ignore other FG. */ 1525 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1526 return (NULL); 1527 1528 hdac_unlock(sc); 1529 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1530 M_NOWAIT | M_ZERO); 1531 hdac_lock(sc); 1532 if (devinfo == NULL) { 1533 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1534 __func__); 1535 return (NULL); 1536 } 1537 1538 devinfo->nid = nid; 1539 devinfo->node_type = fctgrptype; 1540 devinfo->codec = codec; 1541 1542 hdac_add_child(sc, devinfo); 1543 1544 return (devinfo); 1545} 1546 1547static void 1548hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1549{ 1550 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1551 device_set_ivars(devinfo->dev, (void *)devinfo); 1552 /* XXX - Print more information when booting verbose??? */ 1553} 1554 1555static void 1556hdac_widget_connection_parse(struct hdac_widget *w) 1557{ 1558 struct hdac_softc *sc = w->devinfo->codec->sc; 1559 uint32_t res; 1560 int i, j, max, found, entnum, cnid; 1561 nid_t cad = w->devinfo->codec->cad; 1562 nid_t nid = w->nid; 1563 1564 res = hdac_command(sc, 1565 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1566 1567 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1568 1569 if (w->nconns < 1) 1570 return; 1571 1572 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1573 res = 0; 1574 i = 0; 1575 found = 0; 1576 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1577 1578 while (i < w->nconns) { 1579 res = hdac_command(sc, 1580 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1581 for (j = 0; j < entnum; j++) { 1582 cnid = res; 1583 cnid >>= (32 / entnum) * j; 1584 cnid &= (1 << (32 / entnum)) - 1; 1585 if (cnid == 0) 1586 continue; 1587 if (found > max) { 1588 device_printf(sc->dev, 1589 "node %d: Adding %d: " 1590 "Max connection reached!\n", 1591 nid, cnid); 1592 continue; 1593 } 1594 w->conns[found++] = cnid; 1595 } 1596 i += entnum; 1597 } 1598 1599 HDA_BOOTVERBOSE( 1600 if (w->nconns != found) { 1601 device_printf(sc->dev, 1602 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1603 "length=%d != found=%d\n", 1604 nid, w->nconns, found); 1605 } 1606 ); 1607} 1608 1609static uint32_t 1610hdac_widget_pin_getconfig(struct hdac_widget *w) 1611{ 1612 struct hdac_softc *sc; 1613 uint32_t config, id; 1614 nid_t cad, nid; 1615 1616 sc = w->devinfo->codec->sc; 1617 cad = w->devinfo->codec->cad; 1618 nid = w->nid; 1619 id = hdac_codec_id(w->devinfo); 1620 1621 config = hdac_command(sc, 1622 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1623 cad); 1624 /* 1625 * XXX REWRITE!!!! Don't argue! 1626 */ 1627 if (id == HDA_CODEC_ALC880 && 1628 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1629 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1630 /* 1631 * Super broken BIOS 1632 */ 1633 switch (nid) { 1634 case 20: 1635 break; 1636 case 21: 1637 break; 1638 case 22: 1639 break; 1640 case 23: 1641 break; 1642 case 24: /* MIC1 */ 1643 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1644 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1645 break; 1646 case 25: /* XXX MIC2 */ 1647 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1648 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1649 break; 1650 case 26: /* LINE1 */ 1651 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1652 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1653 break; 1654 case 27: /* XXX LINE2 */ 1655 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1656 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1657 break; 1658 case 28: /* CD */ 1659 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1660 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1661 break; 1662 case 30: 1663 break; 1664 case 31: 1665 break; 1666 default: 1667 break; 1668 } 1669 } 1670 1671 return (config); 1672} 1673 1674static void 1675hdac_widget_pin_parse(struct hdac_widget *w) 1676{ 1677 struct hdac_softc *sc = w->devinfo->codec->sc; 1678 uint32_t config, pincap; 1679 char *devstr, *connstr; 1680 nid_t cad = w->devinfo->codec->cad; 1681 nid_t nid = w->nid; 1682 1683 config = hdac_widget_pin_getconfig(w); 1684 w->wclass.pin.config = config; 1685 1686 pincap = hdac_command(sc, 1687 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1688 w->wclass.pin.cap = pincap; 1689 1690 w->wclass.pin.ctrl = hdac_command(sc, 1691 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1692 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1693 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1694 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1695 1696 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1697 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1698 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1699 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1700 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1701 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1702 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1703 w->param.eapdbtl = hdac_command(sc, 1704 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1705 w->param.eapdbtl &= 0x7; 1706 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1707 } else 1708 w->param.eapdbtl = HDAC_INVALID; 1709 1710 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1711 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1712 devstr = "line out"; 1713 break; 1714 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1715 devstr = "speaker"; 1716 break; 1717 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1718 devstr = "headphones out"; 1719 break; 1720 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1721 devstr = "CD"; 1722 break; 1723 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1724 devstr = "SPDIF out"; 1725 break; 1726 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1727 devstr = "digital (other) out"; 1728 break; 1729 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1730 devstr = "modem, line side"; 1731 break; 1732 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1733 devstr = "modem, handset side"; 1734 break; 1735 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1736 devstr = "line in"; 1737 break; 1738 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1739 devstr = "AUX"; 1740 break; 1741 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1742 devstr = "Mic in"; 1743 break; 1744 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1745 devstr = "telephony"; 1746 break; 1747 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1748 devstr = "SPDIF in"; 1749 break; 1750 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1751 devstr = "digital (other) in"; 1752 break; 1753 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1754 devstr = "other"; 1755 break; 1756 default: 1757 devstr = "unknown"; 1758 break; 1759 } 1760 1761 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1762 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1763 connstr = "jack"; 1764 break; 1765 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1766 connstr = "none"; 1767 break; 1768 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1769 connstr = "fixed"; 1770 break; 1771 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1772 connstr = "jack / fixed"; 1773 break; 1774 default: 1775 connstr = "unknown"; 1776 break; 1777 } 1778 1779 strlcat(w->name, ": ", sizeof(w->name)); 1780 strlcat(w->name, devstr, sizeof(w->name)); 1781 strlcat(w->name, " (", sizeof(w->name)); 1782 strlcat(w->name, connstr, sizeof(w->name)); 1783 strlcat(w->name, ")", sizeof(w->name)); 1784} 1785 1786static void 1787hdac_widget_parse(struct hdac_widget *w) 1788{ 1789 struct hdac_softc *sc = w->devinfo->codec->sc; 1790 uint32_t wcap, cap; 1791 char *typestr; 1792 nid_t cad = w->devinfo->codec->cad; 1793 nid_t nid = w->nid; 1794 1795 wcap = hdac_command(sc, 1796 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1797 cad); 1798 w->param.widget_cap = wcap; 1799 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1800 1801 switch (w->type) { 1802 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1803 typestr = "audio output"; 1804 break; 1805 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1806 typestr = "audio input"; 1807 break; 1808 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1809 typestr = "audio mixer"; 1810 break; 1811 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1812 typestr = "audio selector"; 1813 break; 1814 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1815 typestr = "pin"; 1816 break; 1817 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1818 typestr = "power widget"; 1819 break; 1820 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1821 typestr = "volume widget"; 1822 break; 1823 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1824 typestr = "beep widget"; 1825 break; 1826 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1827 typestr = "vendor widget"; 1828 break; 1829 default: 1830 typestr = "unknown type"; 1831 break; 1832 } 1833 1834 strlcpy(w->name, typestr, sizeof(w->name)); 1835 1836 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1837 hdac_command(sc, 1838 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1839 cad); 1840 DELAY(1000); 1841 } 1842 1843 hdac_widget_connection_parse(w); 1844 1845 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1846 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1847 w->param.outamp_cap = 1848 hdac_command(sc, 1849 HDA_CMD_GET_PARAMETER(cad, nid, 1850 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1851 else 1852 w->param.outamp_cap = 1853 w->devinfo->function.audio.outamp_cap; 1854 } else 1855 w->param.outamp_cap = 0; 1856 1857 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1858 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1859 w->param.inamp_cap = 1860 hdac_command(sc, 1861 HDA_CMD_GET_PARAMETER(cad, nid, 1862 HDA_PARAM_INPUT_AMP_CAP), cad); 1863 else 1864 w->param.inamp_cap = 1865 w->devinfo->function.audio.inamp_cap; 1866 } else 1867 w->param.inamp_cap = 0; 1868 1869 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1870 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1871 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1872 cap = hdac_command(sc, 1873 HDA_CMD_GET_PARAMETER(cad, nid, 1874 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1875 w->param.supp_stream_formats = (cap != 0) ? cap : 1876 w->devinfo->function.audio.supp_stream_formats; 1877 cap = hdac_command(sc, 1878 HDA_CMD_GET_PARAMETER(cad, nid, 1879 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1880 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1881 w->devinfo->function.audio.supp_pcm_size_rate; 1882 } else { 1883 w->param.supp_stream_formats = 1884 w->devinfo->function.audio.supp_stream_formats; 1885 w->param.supp_pcm_size_rate = 1886 w->devinfo->function.audio.supp_pcm_size_rate; 1887 } 1888 } else { 1889 w->param.supp_stream_formats = 0; 1890 w->param.supp_pcm_size_rate = 0; 1891 } 1892 1893 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1894 hdac_widget_pin_parse(w); 1895} 1896 1897static struct hdac_widget * 1898hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1899{ 1900 if (devinfo == NULL || devinfo->widget == NULL || 1901 nid < devinfo->startnode || nid >= devinfo->endnode) 1902 return (NULL); 1903 return (&devinfo->widget[nid - devinfo->startnode]); 1904} 1905 1906static __inline int 1907hda_poll_channel(struct hdac_chan *ch) 1908{ 1909 uint32_t sz, delta; 1910 volatile uint32_t ptr; 1911 1912 if (ch->active == 0) 1913 return (0); 1914 1915 sz = ch->blksz * ch->blkcnt; 1916 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 1917 ch->ptr = ptr; 1918 ptr %= sz; 1919 ptr &= ~(ch->blksz - 1); 1920 delta = (sz + ptr - ch->prevptr) % sz; 1921 1922 if (delta < ch->blksz) 1923 return (0); 1924 1925 ch->prevptr = ptr; 1926 1927 return (1); 1928} 1929 1930#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 1931 1932static void 1933hda_poll_callback(void *arg) 1934{ 1935 struct hdac_softc *sc = arg; 1936 uint32_t trigger = 0; 1937 1938 if (sc == NULL) 1939 return; 1940 1941 hdac_lock(sc); 1942 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 1943 hdac_unlock(sc); 1944 return; 1945 } 1946 1947 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 1948 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 1949 1950 /* XXX */ 1951 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 1952 hda_poll_callback, sc); 1953 1954 hdac_unlock(sc); 1955 1956 if (trigger & 1) 1957 chn_intr(sc->play.c); 1958 if (trigger & 2) 1959 chn_intr(sc->rec.c); 1960} 1961 1962static int 1963hdac_rirb_flush(struct hdac_softc *sc) 1964{ 1965 struct hdac_rirb *rirb_base, *rirb; 1966 struct hdac_codec *codec; 1967 struct hdac_command_list *commands; 1968 nid_t cad; 1969 uint32_t resp; 1970 uint8_t rirbwp; 1971 int ret = 0; 1972 1973 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1974 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 1975 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1976 BUS_DMASYNC_POSTREAD); 1977 1978 while (sc->rirb_rp != rirbwp) { 1979 sc->rirb_rp++; 1980 sc->rirb_rp %= sc->rirb_size; 1981 rirb = &rirb_base[sc->rirb_rp]; 1982 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 1983 if (cad < 0 || cad >= HDAC_CODEC_MAX || 1984 sc->codecs[cad] == NULL) 1985 continue; 1986 resp = rirb->response; 1987 codec = sc->codecs[cad]; 1988 commands = codec->commands; 1989 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 1990 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 1991 ((resp >> 26) & 0xffff); 1992 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 1993 } else if (commands != NULL && commands->num_commands > 0 && 1994 codec->responses_received < commands->num_commands) 1995 commands->responses[codec->responses_received++] = 1996 resp; 1997 ret++; 1998 } 1999 2000 return (ret); 2001} 2002 2003static int 2004hdac_unsolq_flush(struct hdac_softc *sc) 2005{ 2006 nid_t cad; 2007 uint32_t tag; 2008 int ret = 0; 2009 2010 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2011 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2012 while (sc->unsolq_rp != sc->unsolq_wp) { 2013 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2014 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2015 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2016 hdac_unsolicited_handler(sc->codecs[cad], tag); 2017 ret++; 2018 } 2019 sc->unsolq_st = HDAC_UNSOLQ_READY; 2020 } 2021 2022 return (ret); 2023} 2024 2025static void 2026hdac_poll_callback(void *arg) 2027{ 2028 struct hdac_softc *sc = arg; 2029 if (sc == NULL) 2030 return; 2031 2032 hdac_lock(sc); 2033 if (sc->polling == 0) { 2034 hdac_unlock(sc); 2035 return; 2036 } 2037 hdac_rirb_flush(sc); 2038 hdac_unsolq_flush(sc); 2039 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2040 hdac_poll_callback, sc); 2041 hdac_unlock(sc); 2042} 2043 2044static void 2045hdac_stream_stop(struct hdac_chan *ch) 2046{ 2047 struct hdac_softc *sc = ch->devinfo->codec->sc; 2048 uint32_t ctl; 2049 2050 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2051 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2052 HDAC_SDCTL_RUN); 2053 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2054 2055 ch->active = 0; 2056 2057 if (sc->polling != 0) { 2058 int pollticks; 2059 2060 if (hda_chan_active(sc) == 0) { 2061 callout_stop(&sc->poll_hda); 2062 sc->poll_ticks = 1; 2063 } else { 2064 if (sc->play.active != 0) 2065 ch = &sc->play; 2066 else 2067 ch = &sc->rec; 2068 pollticks = ((uint64_t)hz * ch->blksz) / 2069 ((uint64_t)sndbuf_getbps(ch->b) * 2070 sndbuf_getspd(ch->b)); 2071 pollticks >>= 2; 2072 if (pollticks > hz) 2073 pollticks = hz; 2074 if (pollticks < 1) { 2075 HDA_BOOTVERBOSE( 2076 device_printf(sc->dev, 2077 "%s: pollticks=%d < 1 !\n", 2078 __func__, pollticks); 2079 ); 2080 pollticks = 1; 2081 } 2082 if (pollticks > sc->poll_ticks) { 2083 HDA_BOOTVERBOSE( 2084 device_printf(sc->dev, 2085 "%s: pollticks %d -> %d\n", 2086 __func__, sc->poll_ticks, 2087 pollticks); 2088 ); 2089 sc->poll_ticks = pollticks; 2090 callout_reset(&sc->poll_hda, 1, 2091 hda_poll_callback, sc); 2092 } 2093 } 2094 } else { 2095 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2096 ctl &= ~(1 << (ch->off >> 5)); 2097 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2098 } 2099} 2100 2101static void 2102hdac_stream_start(struct hdac_chan *ch) 2103{ 2104 struct hdac_softc *sc = ch->devinfo->codec->sc; 2105 uint32_t ctl; 2106 2107 if (sc->polling != 0) { 2108 int pollticks; 2109 2110 pollticks = ((uint64_t)hz * ch->blksz) / 2111 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2112 pollticks >>= 2; 2113 if (pollticks > hz) 2114 pollticks = hz; 2115 if (pollticks < 1) { 2116 HDA_BOOTVERBOSE( 2117 device_printf(sc->dev, 2118 "%s: pollticks=%d < 1 !\n", 2119 __func__, pollticks); 2120 ); 2121 pollticks = 1; 2122 } 2123 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2124 HDA_BOOTVERBOSE( 2125 if (hda_chan_active(sc) == 0) { 2126 device_printf(sc->dev, 2127 "%s: pollticks=%d\n", 2128 __func__, pollticks); 2129 } else { 2130 device_printf(sc->dev, 2131 "%s: pollticks %d -> %d\n", 2132 __func__, sc->poll_ticks, 2133 pollticks); 2134 } 2135 ); 2136 sc->poll_ticks = pollticks; 2137 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2138 sc); 2139 } 2140 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2141 ctl |= HDAC_SDCTL_RUN; 2142 } else { 2143 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2144 ctl |= 1 << (ch->off >> 5); 2145 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2146 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2147 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2148 HDAC_SDCTL_RUN; 2149 } 2150 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2151 2152 ch->active = 1; 2153} 2154 2155static void 2156hdac_stream_reset(struct hdac_chan *ch) 2157{ 2158 struct hdac_softc *sc = ch->devinfo->codec->sc; 2159 int timeout = 1000; 2160 int to = timeout; 2161 uint32_t ctl; 2162 2163 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2164 ctl |= HDAC_SDCTL_SRST; 2165 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2166 do { 2167 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2168 if (ctl & HDAC_SDCTL_SRST) 2169 break; 2170 DELAY(10); 2171 } while (--to); 2172 if (!(ctl & HDAC_SDCTL_SRST)) { 2173 device_printf(sc->dev, "timeout in reset\n"); 2174 } 2175 ctl &= ~HDAC_SDCTL_SRST; 2176 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2177 to = timeout; 2178 do { 2179 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2180 if (!(ctl & HDAC_SDCTL_SRST)) 2181 break; 2182 DELAY(10); 2183 } while (--to); 2184 if (ctl & HDAC_SDCTL_SRST) 2185 device_printf(sc->dev, "can't reset!\n"); 2186} 2187 2188static void 2189hdac_stream_setid(struct hdac_chan *ch) 2190{ 2191 struct hdac_softc *sc = ch->devinfo->codec->sc; 2192 uint32_t ctl; 2193 2194 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2195 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2196 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2197 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2198} 2199 2200static void 2201hdac_bdl_setup(struct hdac_chan *ch) 2202{ 2203 struct hdac_softc *sc = ch->devinfo->codec->sc; 2204 struct hdac_bdle *bdle; 2205 uint64_t addr; 2206 uint32_t blksz, blkcnt; 2207 int i; 2208 2209 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2210 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2211 2212 if (sc->polling != 0) { 2213 blksz = ch->blksz * ch->blkcnt; 2214 blkcnt = 1; 2215 } else { 2216 blksz = ch->blksz; 2217 blkcnt = ch->blkcnt; 2218 } 2219 2220 for (i = 0; i < blkcnt; i++, bdle++) { 2221 bdle->addrl = (uint32_t)addr; 2222 bdle->addrh = (uint32_t)(addr >> 32); 2223 bdle->len = blksz; 2224 bdle->ioc = 1 ^ sc->polling; 2225 addr += blksz; 2226 } 2227 2228 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2229 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2230 addr = ch->bdl_dma.dma_paddr; 2231 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2232 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2233} 2234 2235static int 2236hdac_bdl_alloc(struct hdac_chan *ch) 2237{ 2238 struct hdac_softc *sc = ch->devinfo->codec->sc; 2239 int rc; 2240 2241 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2242 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2243 if (rc) { 2244 device_printf(sc->dev, "can't alloc bdl\n"); 2245 return (rc); 2246 } 2247 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2248 2249 return (0); 2250} 2251 2252static void 2253hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2254 int index, int lmute, int rmute, 2255 int left, int right, int dir) 2256{ 2257 uint16_t v = 0; 2258 2259 if (sc == NULL) 2260 return; 2261 2262 if (left != right || lmute != rmute) { 2263 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2264 (lmute << 7) | left; 2265 hdac_command(sc, 2266 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2267 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2268 (rmute << 7) | right; 2269 } else 2270 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2271 (lmute << 7) | left; 2272 2273 hdac_command(sc, 2274 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2275} 2276 2277static void 2278hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2279 int left, int right) 2280{ 2281 struct hdac_softc *sc; 2282 nid_t nid, cad; 2283 int lmute, rmute; 2284 2285 if (ctl == NULL || ctl->widget == NULL || 2286 ctl->widget->devinfo == NULL || 2287 ctl->widget->devinfo->codec == NULL || 2288 ctl->widget->devinfo->codec->sc == NULL) 2289 return; 2290 2291 sc = ctl->widget->devinfo->codec->sc; 2292 cad = ctl->widget->devinfo->codec->cad; 2293 nid = ctl->widget->nid; 2294 2295 if (mute == HDA_AMP_MUTE_DEFAULT) { 2296 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2297 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2298 } else { 2299 lmute = HDA_AMP_LEFT_MUTED(mute); 2300 rmute = HDA_AMP_RIGHT_MUTED(mute); 2301 } 2302 2303 if (ctl->dir & HDA_CTL_OUT) 2304 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2305 lmute, rmute, left, right, 0); 2306 if (ctl->dir & HDA_CTL_IN) 2307 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2308 lmute, rmute, left, right, 1); 2309 ctl->left = left; 2310 ctl->right = right; 2311} 2312 2313static void 2314hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2315{ 2316 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2317 return; 2318 hdac_command(w->devinfo->codec->sc, 2319 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2320 w->nid, index), w->devinfo->codec->cad); 2321 w->selconn = index; 2322} 2323 2324 2325/**************************************************************************** 2326 * uint32_t hdac_command_sendone_internal 2327 * 2328 * Wrapper function that sends only one command to a given codec 2329 ****************************************************************************/ 2330static uint32_t 2331hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2332{ 2333 struct hdac_command_list cl; 2334 uint32_t response = HDAC_INVALID; 2335 2336 if (!hdac_lockowned(sc)) 2337 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2338 cl.num_commands = 1; 2339 cl.verbs = &verb; 2340 cl.responses = &response; 2341 2342 hdac_command_send_internal(sc, &cl, cad); 2343 2344 return (response); 2345} 2346 2347/**************************************************************************** 2348 * hdac_command_send_internal 2349 * 2350 * Send a command list to the codec via the corb. We queue as much verbs as 2351 * we can and msleep on the codec. When the interrupt get the responses 2352 * back from the rirb, it will wake us up so we can queue the remaining verbs 2353 * if any. 2354 ****************************************************************************/ 2355static void 2356hdac_command_send_internal(struct hdac_softc *sc, 2357 struct hdac_command_list *commands, nid_t cad) 2358{ 2359 struct hdac_codec *codec; 2360 int corbrp; 2361 uint32_t *corb; 2362 int timeout; 2363 int retry = 10; 2364 struct hdac_rirb *rirb_base; 2365 2366 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2367 commands->num_commands < 1) 2368 return; 2369 2370 codec = sc->codecs[cad]; 2371 codec->commands = commands; 2372 codec->responses_received = 0; 2373 codec->verbs_sent = 0; 2374 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2375 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2376 2377 do { 2378 if (codec->verbs_sent != commands->num_commands) { 2379 /* Queue as many verbs as possible */ 2380 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2381 bus_dmamap_sync(sc->corb_dma.dma_tag, 2382 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2383 while (codec->verbs_sent != commands->num_commands && 2384 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2385 sc->corb_wp++; 2386 sc->corb_wp %= sc->corb_size; 2387 corb[sc->corb_wp] = 2388 commands->verbs[codec->verbs_sent++]; 2389 } 2390 2391 /* Send the verbs to the codecs */ 2392 bus_dmamap_sync(sc->corb_dma.dma_tag, 2393 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2394 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2395 } 2396 2397 timeout = 1000; 2398 while (hdac_rirb_flush(sc) == 0 && --timeout) 2399 DELAY(10); 2400 } while ((codec->verbs_sent != commands->num_commands || 2401 codec->responses_received != commands->num_commands) && --retry); 2402 2403 if (retry == 0) 2404 device_printf(sc->dev, 2405 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2406 __func__, commands->num_commands, codec->verbs_sent, 2407 codec->responses_received); 2408 2409 codec->commands = NULL; 2410 codec->responses_received = 0; 2411 codec->verbs_sent = 0; 2412 2413 hdac_unsolq_flush(sc); 2414} 2415 2416 2417/**************************************************************************** 2418 * Device Methods 2419 ****************************************************************************/ 2420 2421/**************************************************************************** 2422 * int hdac_probe(device_t) 2423 * 2424 * Probe for the presence of an hdac. If none is found, check for a generic 2425 * match using the subclass of the device. 2426 ****************************************************************************/ 2427static int 2428hdac_probe(device_t dev) 2429{ 2430 int i, result; 2431 uint32_t model; 2432 uint16_t class, subclass; 2433 char desc[64]; 2434 2435 model = (uint32_t)pci_get_device(dev) << 16; 2436 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2437 class = pci_get_class(dev); 2438 subclass = pci_get_subclass(dev); 2439 2440 bzero(desc, sizeof(desc)); 2441 result = ENXIO; 2442 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2443 if (hdac_devices[i].model == model) { 2444 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2445 result = BUS_PROBE_DEFAULT; 2446 break; 2447 } 2448 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2449 class == PCIC_MULTIMEDIA && 2450 subclass == PCIS_MULTIMEDIA_HDA) { 2451 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2452 result = BUS_PROBE_GENERIC; 2453 break; 2454 } 2455 } 2456 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2457 subclass == PCIS_MULTIMEDIA_HDA) { 2458 strlcpy(desc, "Generic", sizeof(desc)); 2459 result = BUS_PROBE_GENERIC; 2460 } 2461 if (result != ENXIO) { 2462 strlcat(desc, " High Definition Audio Controller", 2463 sizeof(desc)); 2464 device_set_desc_copy(dev, desc); 2465 } 2466 2467 return (result); 2468} 2469 2470static void * 2471hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2472 struct pcm_channel *c, int dir) 2473{ 2474 struct hdac_devinfo *devinfo = data; 2475 struct hdac_softc *sc = devinfo->codec->sc; 2476 struct hdac_chan *ch; 2477 2478 hdac_lock(sc); 2479 if (dir == PCMDIR_PLAY) { 2480 ch = &sc->play; 2481 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2482 ch->dir = PCMDIR_PLAY; 2483 ch->sid = ++sc->streamcnt; 2484 devinfo->function.audio.playcnt++; 2485 } else { 2486 ch = &sc->rec; 2487 ch->off = devinfo->function.audio.reccnt << 5; 2488 ch->dir = PCMDIR_REC; 2489 ch->sid = ++sc->streamcnt; 2490 devinfo->function.audio.reccnt++; 2491 } 2492 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2493 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2494 ch->pcmrates[0] = 48000; 2495 ch->pcmrates[1] = 0; 2496 } 2497 ch->b = b; 2498 ch->c = c; 2499 ch->devinfo = devinfo; 2500 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2501 ch->blkcnt = sc->chan_blkcnt; 2502 hdac_unlock(sc); 2503 2504 if (hdac_bdl_alloc(ch) != 0) { 2505 ch->blkcnt = 0; 2506 return (NULL); 2507 } 2508 2509 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2510 return (NULL); 2511 2512 hdac_dma_nocache(ch->b->buf); 2513 2514 return (ch); 2515} 2516 2517static int 2518hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2519{ 2520 struct hdac_chan *ch = data; 2521 int i; 2522 2523 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2524 if (format == ch->caps.fmtlist[i]) { 2525 ch->fmt = format; 2526 return (0); 2527 } 2528 } 2529 2530 return (EINVAL); 2531} 2532 2533static int 2534hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2535{ 2536 struct hdac_chan *ch = data; 2537 uint32_t spd = 0, threshold; 2538 int i; 2539 2540 for (i = 0; ch->pcmrates[i] != 0; i++) { 2541 spd = ch->pcmrates[i]; 2542 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2543 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2544 if (speed < threshold) 2545 break; 2546 } 2547 2548 if (spd == 0) /* impossible */ 2549 ch->spd = 48000; 2550 else 2551 ch->spd = spd; 2552 2553 return (ch->spd); 2554} 2555 2556static void 2557hdac_stream_setup(struct hdac_chan *ch) 2558{ 2559 struct hdac_softc *sc = ch->devinfo->codec->sc; 2560 int i; 2561 nid_t cad = ch->devinfo->codec->cad; 2562 uint16_t fmt; 2563 2564 fmt = 0; 2565 if (ch->fmt & AFMT_S16_LE) 2566 fmt |= ch->bit16 << 4; 2567 else if (ch->fmt & AFMT_S32_LE) 2568 fmt |= ch->bit32 << 4; 2569 else 2570 fmt |= 1 << 4; 2571 2572 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2573 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2574 fmt |= hda_rate_tab[i].base; 2575 fmt |= hda_rate_tab[i].mul; 2576 fmt |= hda_rate_tab[i].div; 2577 break; 2578 } 2579 } 2580 2581 if (ch->fmt & AFMT_STEREO) 2582 fmt |= 1; 2583 2584 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2585 2586 for (i = 0; ch->io[i] != -1; i++) { 2587 HDA_BOOTVERBOSE( 2588 device_printf(sc->dev, 2589 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2590 "fmt=0x%08x\n", 2591 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2592 ch->io[i], fmt); 2593 ); 2594 hdac_command(sc, 2595 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2596 hdac_command(sc, 2597 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2598 ch->sid << 4), cad); 2599 } 2600} 2601 2602static int 2603hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2604{ 2605 struct hdac_chan *ch = data; 2606 struct hdac_softc *sc = ch->devinfo->codec->sc; 2607 2608 blksz &= ~0x7f; 2609 if (blksz < 0x80) 2610 blksz = 0x80; 2611 2612 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2613 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2614 2615 if ((sndbuf_getblksz(ch->b) != blksz || 2616 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2617 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2618 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2619 __func__, blksz, ch->blkcnt); 2620 2621 ch->blksz = sndbuf_getblksz(ch->b); 2622 2623 return (ch->blksz); 2624} 2625 2626static void 2627hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2628{ 2629 struct hdac_devinfo *devinfo = ch->devinfo; 2630 nid_t cad = devinfo->codec->cad; 2631 int i; 2632 2633 hdac_stream_stop(ch); 2634 2635 for (i = 0; ch->io[i] != -1; i++) { 2636 hdac_command(sc, 2637 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2638 0), cad); 2639 } 2640} 2641 2642static void 2643hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2644{ 2645 ch->ptr = 0; 2646 ch->prevptr = 0; 2647 hdac_stream_stop(ch); 2648 hdac_stream_reset(ch); 2649 hdac_bdl_setup(ch); 2650 hdac_stream_setid(ch); 2651 hdac_stream_setup(ch); 2652 hdac_stream_start(ch); 2653} 2654 2655static int 2656hdac_channel_trigger(kobj_t obj, void *data, int go) 2657{ 2658 struct hdac_chan *ch = data; 2659 struct hdac_softc *sc = ch->devinfo->codec->sc; 2660 2661 hdac_lock(sc); 2662 switch (go) { 2663 case PCMTRIG_START: 2664 hdac_channel_start(sc, ch); 2665 break; 2666 case PCMTRIG_STOP: 2667 case PCMTRIG_ABORT: 2668 hdac_channel_stop(sc, ch); 2669 break; 2670 } 2671 hdac_unlock(sc); 2672 2673 return (0); 2674} 2675 2676static int 2677hdac_channel_getptr(kobj_t obj, void *data) 2678{ 2679 struct hdac_chan *ch = data; 2680 struct hdac_softc *sc = ch->devinfo->codec->sc; 2681 uint32_t ptr; 2682 2683 hdac_lock(sc); 2684 if (sc->polling != 0) 2685 ptr = ch->ptr; 2686 else 2687 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2688 hdac_unlock(sc); 2689 2690 /* 2691 * Round to available space and force 128 bytes aligment. 2692 */ 2693 ptr %= ch->blksz * ch->blkcnt; 2694 ptr &= ~0x7f; 2695 2696 return (ptr); 2697} 2698 2699static struct pcmchan_caps * 2700hdac_channel_getcaps(kobj_t obj, void *data) 2701{ 2702 return (&((struct hdac_chan *)data)->caps); 2703} 2704 2705static kobj_method_t hdac_channel_methods[] = { 2706 KOBJMETHOD(channel_init, hdac_channel_init), 2707 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2708 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2709 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2710 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2711 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2712 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2713 { 0, 0 } 2714}; 2715CHANNEL_DECLARE(hdac_channel); 2716 2717static int 2718hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2719{ 2720 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2721 struct hdac_softc *sc = devinfo->codec->sc; 2722 struct hdac_widget *w, *cw; 2723 struct hdac_audio_ctl *ctl; 2724 uint32_t mask, recmask, id; 2725 int i, j, softpcmvol; 2726 nid_t cad; 2727 2728 hdac_lock(sc); 2729 2730 mask = 0; 2731 recmask = 0; 2732 2733 id = hdac_codec_id(devinfo); 2734 cad = devinfo->codec->cad; 2735 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2736 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2737 sc->pci_subvendor) && 2738 hdac_hp_switch[i].id == id)) 2739 continue; 2740 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2741 if (w != NULL && w->enable != 0 2742 && w->type == 2743 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2744 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2745 hdac_command(sc, 2746 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2747 w->nid, 2748 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2749 HDAC_UNSOLTAG_EVENT_HP), cad); 2750 hdac_hp_switch_handler(devinfo); 2751 HDA_BOOTVERBOSE( 2752 device_printf(sc->dev, 2753 "HDA_DEBUG: Enabling headphone/speaker " 2754 "audio routing switching:\n"); 2755 device_printf(sc->dev, 2756 "HDA_DEBUG: \tindex=%d nid=%d " 2757 "pci_subvendor=0x%08x " 2758 "codec=0x%08x\n", 2759 i, w->nid, sc->pci_subvendor, id); 2760 ); 2761 } 2762 break; 2763 } 2764 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2765 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2766 sc->pci_subvendor) && 2767 hdac_eapd_switch[i].id == id)) 2768 continue; 2769 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2770 if (w == NULL || w->enable == 0) 2771 break; 2772 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2773 w->param.eapdbtl == HDAC_INVALID) 2774 break; 2775 mask |= SOUND_MASK_OGAIN; 2776 break; 2777 } 2778 2779 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2780 w = hdac_widget_get(devinfo, i); 2781 if (w == NULL || w->enable == 0) 2782 continue; 2783 mask |= w->ctlflags; 2784 if (!(w->pflags & HDA_ADC_RECSEL)) 2785 continue; 2786 for (j = 0; j < w->nconns; j++) { 2787 cw = hdac_widget_get(devinfo, w->conns[j]); 2788 if (cw == NULL || cw->enable == 0) 2789 continue; 2790 recmask |= cw->ctlflags; 2791 } 2792 } 2793 2794 if (!(mask & SOUND_MASK_PCM)) { 2795 softpcmvol = 1; 2796 mask |= SOUND_MASK_PCM; 2797 } else 2798 softpcmvol = (devinfo->function.audio.quirks & 2799 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2800 2801 i = 0; 2802 ctl = NULL; 2803 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2804 if (ctl->widget == NULL || ctl->enable == 0) 2805 continue; 2806 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2807 continue; 2808 if (ctl->step > 0) 2809 break; 2810 } 2811 2812 if (softpcmvol == 1 || ctl == NULL) { 2813 struct snddev_info *d = NULL; 2814 d = device_get_softc(sc->dev); 2815 if (d != NULL) { 2816 d->flags |= SD_F_SOFTPCMVOL; 2817 HDA_BOOTVERBOSE( 2818 device_printf(sc->dev, 2819 "HDA_DEBUG: %s Soft PCM volume\n", 2820 (softpcmvol == 1) ? 2821 "Forcing" : "Enabling"); 2822 ); 2823 } 2824 i = 0; 2825 /* 2826 * XXX Temporary quirk for STAC9220, until the parser 2827 * become smarter. 2828 */ 2829 if (id == HDA_CODEC_STAC9220) { 2830 mask |= SOUND_MASK_VOLUME; 2831 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2832 NULL) { 2833 if (ctl->widget == NULL || ctl->enable == 0) 2834 continue; 2835 if (ctl->widget->nid == 11 && ctl->index == 0) { 2836 ctl->ossmask = SOUND_MASK_VOLUME; 2837 ctl->ossval = 100 | (100 << 8); 2838 } else 2839 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2840 } 2841 } else { 2842 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2843 SOUND_MASK_PCM); 2844 if (!(mask & SOUND_MASK_VOLUME)) 2845 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2846 SOUND_MIXER_NONE); 2847 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2848 NULL) { 2849 if (ctl->widget == NULL || ctl->enable == 0) 2850 continue; 2851 if (!HDA_FLAG_MATCH(ctl->ossmask, 2852 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2853 continue; 2854 if (!(ctl->mute == 1 && ctl->step == 0)) 2855 ctl->enable = 0; 2856 } 2857 } 2858 } 2859 2860 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2861 2862 mix_setrecdevs(m, recmask); 2863 mix_setdevs(m, mask); 2864 2865 hdac_unlock(sc); 2866 2867 return (0); 2868} 2869 2870static int 2871hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2872 unsigned left, unsigned right) 2873{ 2874 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2875 struct hdac_softc *sc = devinfo->codec->sc; 2876 struct hdac_widget *w; 2877 struct hdac_audio_ctl *ctl; 2878 uint32_t id, mute; 2879 int lvol, rvol, mlvol, mrvol; 2880 int i = 0; 2881 2882 hdac_lock(sc); 2883 if (dev == SOUND_MIXER_OGAIN) { 2884 uint32_t orig; 2885 /*if (left != right || !(left == 0 || left == 1)) { 2886 hdac_unlock(sc); 2887 return (-1); 2888 }*/ 2889 id = hdac_codec_id(devinfo); 2890 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2891 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2892 sc->pci_subvendor) && 2893 hdac_eapd_switch[i].id == id) 2894 break; 2895 } 2896 if (i >= HDAC_EAPD_SWITCH_LEN) { 2897 hdac_unlock(sc); 2898 return (-1); 2899 } 2900 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2901 if (w == NULL || 2902 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2903 w->param.eapdbtl == HDAC_INVALID) { 2904 hdac_unlock(sc); 2905 return (-1); 2906 } 2907 orig = w->param.eapdbtl; 2908 if (left == 0) 2909 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2910 else 2911 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2912 if (orig != w->param.eapdbtl) { 2913 uint32_t val; 2914 2915 if (hdac_eapd_switch[i].hp_switch != 0) 2916 hdac_hp_switch_handler(devinfo); 2917 val = w->param.eapdbtl; 2918 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2919 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2920 hdac_command(sc, 2921 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2922 w->nid, val), devinfo->codec->cad); 2923 } 2924 hdac_unlock(sc); 2925 return (left | (left << 8)); 2926 } 2927 if (dev == SOUND_MIXER_VOLUME) 2928 devinfo->function.audio.mvol = left | (right << 8); 2929 2930 mlvol = devinfo->function.audio.mvol & 0x7f; 2931 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2932 lvol = 0; 2933 rvol = 0; 2934 2935 i = 0; 2936 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2937 if (ctl->widget == NULL || ctl->enable == 0 || 2938 !(ctl->ossmask & (1 << dev))) 2939 continue; 2940 switch (dev) { 2941 case SOUND_MIXER_VOLUME: 2942 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2943 lvol = (lvol * ctl->step) / 100; 2944 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2945 rvol = (rvol * ctl->step) / 100; 2946 break; 2947 default: 2948 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2949 lvol = (left * mlvol) / 100; 2950 lvol = (lvol * ctl->step) / 100; 2951 rvol = (right * mrvol) / 100; 2952 rvol = (rvol * ctl->step) / 100; 2953 } else { 2954 lvol = (left * ctl->step) / 100; 2955 rvol = (right * ctl->step) / 100; 2956 } 2957 ctl->ossval = left | (right << 8); 2958 break; 2959 } 2960 mute = 0; 2961 if (ctl->step < 1) { 2962 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2963 (ctl->muted & HDA_AMP_MUTE_LEFT); 2964 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2965 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2966 } else { 2967 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2968 (ctl->muted & HDA_AMP_MUTE_LEFT); 2969 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2970 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2971 } 2972 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2973 } 2974 hdac_unlock(sc); 2975 2976 return (left | (right << 8)); 2977} 2978 2979static int 2980hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2981{ 2982 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2983 struct hdac_widget *w, *cw; 2984 struct hdac_softc *sc = devinfo->codec->sc; 2985 uint32_t ret = src, target; 2986 int i, j; 2987 2988 target = 0; 2989 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2990 if (src & (1 << i)) { 2991 target = 1 << i; 2992 break; 2993 } 2994 } 2995 2996 hdac_lock(sc); 2997 2998 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2999 w = hdac_widget_get(devinfo, i); 3000 if (w == NULL || w->enable == 0) 3001 continue; 3002 if (!(w->pflags & HDA_ADC_RECSEL)) 3003 continue; 3004 for (j = 0; j < w->nconns; j++) { 3005 cw = hdac_widget_get(devinfo, w->conns[j]); 3006 if (cw == NULL || cw->enable == 0) 3007 continue; 3008 if ((target == SOUND_MASK_VOLUME && 3009 cw->type != 3010 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3011 (target != SOUND_MASK_VOLUME && 3012 cw->type == 3013 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3014 continue; 3015 if (cw->ctlflags & target) { 3016 hdac_widget_connection_select(w, j); 3017 ret = target; 3018 j += w->nconns; 3019 } 3020 } 3021 } 3022 3023 hdac_unlock(sc); 3024 3025 return (ret); 3026} 3027 3028static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3029 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3030 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3031 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3032 { 0, 0 } 3033}; 3034MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3035 3036/**************************************************************************** 3037 * int hdac_attach(device_t) 3038 * 3039 * Attach the device into the kernel. Interrupts usually won't be enabled 3040 * when this function is called. Setup everything that doesn't require 3041 * interrupts and defer probing of codecs until interrupts are enabled. 3042 ****************************************************************************/ 3043static int 3044hdac_attach(device_t dev) 3045{ 3046 struct hdac_softc *sc; 3047 int result; 3048 int i = 0; 3049 3050 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3051 if (sc == NULL) { 3052 device_printf(dev, "cannot allocate softc\n"); 3053 return (ENOMEM); 3054 } 3055 3056 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3057 if (sc->lock == NULL) { 3058 device_printf(dev, "mutex creation failed\n"); 3059 free(sc, M_DEVBUF); 3060 return (ENOMEM); 3061 } 3062 3063 sc->dev = dev; 3064 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3065 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3066 3067 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3068 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3069 3070 sc->poll_ticks = 1; 3071 if (resource_int_value(device_get_name(sc->dev), 3072 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3073 sc->polling = 1; 3074 else 3075 sc->polling = 0; 3076 3077 sc->chan_size = pcm_getbuffersize(dev, 3078 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3079 3080 if (resource_int_value(device_get_name(sc->dev), 3081 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3082 i &= ~0x7f; 3083 if (i < 0x80) 3084 i = 0x80; 3085 sc->chan_blkcnt = sc->chan_size / i; 3086 i = 0; 3087 while (sc->chan_blkcnt >> i) 3088 i++; 3089 sc->chan_blkcnt = 1 << (i - 1); 3090 if (sc->chan_blkcnt < HDA_BDL_MIN) 3091 sc->chan_blkcnt = HDA_BDL_MIN; 3092 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3093 sc->chan_blkcnt = HDA_BDL_MAX; 3094 } else 3095 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3096 3097 result = bus_dma_tag_create(NULL, /* parent */ 3098 HDAC_DMA_ALIGNMENT, /* alignment */ 3099 0, /* boundary */ 3100 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3101 BUS_SPACE_MAXADDR, /* highaddr */ 3102 NULL, /* filtfunc */ 3103 NULL, /* fistfuncarg */ 3104 sc->chan_size, /* maxsize */ 3105 1, /* nsegments */ 3106 sc->chan_size, /* maxsegsz */ 3107 0, /* flags */ 3108 NULL, /* lockfunc */ 3109 NULL, /* lockfuncarg */ 3110 &sc->chan_dmat); /* dmat */ 3111 if (result != 0) { 3112 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3113 __func__, result); 3114 snd_mtxfree(sc->lock); 3115 free(sc, M_DEVBUF); 3116 return (ENXIO); 3117 } 3118 3119 3120 sc->hdabus = NULL; 3121 for (i = 0; i < HDAC_CODEC_MAX; i++) 3122 sc->codecs[i] = NULL; 3123 3124 pci_enable_busmaster(dev); 3125 3126 /* Allocate resources */ 3127 result = hdac_mem_alloc(sc); 3128 if (result != 0) 3129 goto hdac_attach_fail; 3130 result = hdac_irq_alloc(sc); 3131 if (result != 0) 3132 goto hdac_attach_fail; 3133 3134 /* Get Capabilities */ 3135 result = hdac_get_capabilities(sc); 3136 if (result != 0) 3137 goto hdac_attach_fail; 3138 3139 /* Allocate CORB and RIRB dma memory */ 3140 result = hdac_dma_alloc(sc, &sc->corb_dma, 3141 sc->corb_size * sizeof(uint32_t)); 3142 if (result != 0) 3143 goto hdac_attach_fail; 3144 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3145 sc->rirb_size * sizeof(struct hdac_rirb)); 3146 if (result != 0) 3147 goto hdac_attach_fail; 3148 3149 /* Quiesce everything */ 3150 hdac_reset(sc); 3151 3152 /* Disable PCI-Express QOS */ 3153 pci_write_config(sc->dev, 0x44, 3154 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3155 3156 /* Initialize the CORB and RIRB */ 3157 hdac_corb_init(sc); 3158 hdac_rirb_init(sc); 3159 3160 /* Defer remaining of initialization until interrupts are enabled */ 3161 sc->intrhook.ich_func = hdac_attach2; 3162 sc->intrhook.ich_arg = (void *)sc; 3163 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3164 sc->intrhook.ich_func = NULL; 3165 hdac_attach2((void *)sc); 3166 } 3167 3168 return (0); 3169 3170hdac_attach_fail: 3171 hdac_dma_free(&sc->rirb_dma); 3172 hdac_dma_free(&sc->corb_dma); 3173 hdac_irq_free(sc); 3174 hdac_mem_free(sc); 3175 snd_mtxfree(sc->lock); 3176 free(sc, M_DEVBUF); 3177 3178 return (ENXIO); 3179} 3180 3181static void 3182hdac_audio_parse(struct hdac_devinfo *devinfo) 3183{ 3184 struct hdac_softc *sc = devinfo->codec->sc; 3185 struct hdac_widget *w; 3186 uint32_t res; 3187 int i; 3188 nid_t cad, nid; 3189 3190 cad = devinfo->codec->cad; 3191 nid = devinfo->nid; 3192 3193 hdac_command(sc, 3194 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3195 3196 DELAY(100); 3197 3198 res = hdac_command(sc, 3199 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3200 3201 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3202 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3203 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3204 3205 HDA_BOOTVERBOSE( 3206 device_printf(sc->dev, " Vendor: 0x%08x\n", 3207 devinfo->vendor_id); 3208 device_printf(sc->dev, " Device: 0x%08x\n", 3209 devinfo->device_id); 3210 device_printf(sc->dev, " Revision: 0x%08x\n", 3211 devinfo->revision_id); 3212 device_printf(sc->dev, " Stepping: 0x%08x\n", 3213 devinfo->stepping_id); 3214 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3215 sc->pci_subvendor); 3216 device_printf(sc->dev, " Nodes: start=%d " 3217 "endnode=%d total=%d\n", 3218 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3219 ); 3220 3221 res = hdac_command(sc, 3222 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3223 cad); 3224 devinfo->function.audio.supp_stream_formats = res; 3225 3226 res = hdac_command(sc, 3227 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3228 cad); 3229 devinfo->function.audio.supp_pcm_size_rate = res; 3230 3231 res = hdac_command(sc, 3232 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3233 cad); 3234 devinfo->function.audio.outamp_cap = res; 3235 3236 res = hdac_command(sc, 3237 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3238 cad); 3239 devinfo->function.audio.inamp_cap = res; 3240 3241 if (devinfo->nodecnt > 0) { 3242 hdac_unlock(sc); 3243 devinfo->widget = (struct hdac_widget *)malloc( 3244 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3245 M_NOWAIT | M_ZERO); 3246 hdac_lock(sc); 3247 } else 3248 devinfo->widget = NULL; 3249 3250 if (devinfo->widget == NULL) { 3251 device_printf(sc->dev, "unable to allocate widgets!\n"); 3252 devinfo->endnode = devinfo->startnode; 3253 devinfo->nodecnt = 0; 3254 return; 3255 } 3256 3257 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3258 w = hdac_widget_get(devinfo, i); 3259 if (w == NULL) 3260 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3261 else { 3262 w->devinfo = devinfo; 3263 w->nid = i; 3264 w->enable = 1; 3265 w->selconn = -1; 3266 w->pflags = 0; 3267 w->ctlflags = 0; 3268 w->param.eapdbtl = HDAC_INVALID; 3269 hdac_widget_parse(w); 3270 } 3271 } 3272} 3273 3274static void 3275hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3276{ 3277 struct hdac_softc *sc = devinfo->codec->sc; 3278 struct hdac_audio_ctl *ctls; 3279 struct hdac_widget *w, *cw; 3280 int i, j, cnt, max, ocap, icap; 3281 int mute, offset, step, size; 3282 3283 /* XXX This is redundant */ 3284 max = 0; 3285 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3286 w = hdac_widget_get(devinfo, i); 3287 if (w == NULL || w->enable == 0) 3288 continue; 3289 if (w->param.outamp_cap != 0) 3290 max++; 3291 if (w->param.inamp_cap != 0) { 3292 switch (w->type) { 3293 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3294 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3295 for (j = 0; j < w->nconns; j++) { 3296 cw = hdac_widget_get(devinfo, 3297 w->conns[j]); 3298 if (cw == NULL || cw->enable == 0) 3299 continue; 3300 max++; 3301 } 3302 break; 3303 default: 3304 max++; 3305 break; 3306 } 3307 } 3308 } 3309 3310 devinfo->function.audio.ctlcnt = max; 3311 3312 if (max < 1) 3313 return; 3314 3315 hdac_unlock(sc); 3316 ctls = (struct hdac_audio_ctl *)malloc( 3317 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3318 hdac_lock(sc); 3319 3320 if (ctls == NULL) { 3321 /* Blekh! */ 3322 device_printf(sc->dev, "unable to allocate ctls!\n"); 3323 devinfo->function.audio.ctlcnt = 0; 3324 return; 3325 } 3326 3327 cnt = 0; 3328 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3329 if (cnt >= max) { 3330 device_printf(sc->dev, "%s: Ctl overflow!\n", 3331 __func__); 3332 break; 3333 } 3334 w = hdac_widget_get(devinfo, i); 3335 if (w == NULL || w->enable == 0) 3336 continue; 3337 ocap = w->param.outamp_cap; 3338 icap = w->param.inamp_cap; 3339 if (ocap != 0) { 3340 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3341 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3342 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3343 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3344 /*if (offset > step) { 3345 HDA_BOOTVERBOSE( 3346 device_printf(sc->dev, 3347 "HDA_DEBUG: BUGGY outamp: nid=%d " 3348 "[offset=%d > step=%d]\n", 3349 w->nid, offset, step); 3350 ); 3351 offset = step; 3352 }*/ 3353 ctls[cnt].enable = 1; 3354 ctls[cnt].widget = w; 3355 ctls[cnt].mute = mute; 3356 ctls[cnt].step = step; 3357 ctls[cnt].size = size; 3358 ctls[cnt].offset = offset; 3359 ctls[cnt].left = offset; 3360 ctls[cnt].right = offset; 3361 ctls[cnt++].dir = HDA_CTL_OUT; 3362 } 3363 3364 if (icap != 0) { 3365 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3366 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3367 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3368 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3369 /*if (offset > step) { 3370 HDA_BOOTVERBOSE( 3371 device_printf(sc->dev, 3372 "HDA_DEBUG: BUGGY inamp: nid=%d " 3373 "[offset=%d > step=%d]\n", 3374 w->nid, offset, step); 3375 ); 3376 offset = step; 3377 }*/ 3378 switch (w->type) { 3379 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3380 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3381 for (j = 0; j < w->nconns; j++) { 3382 if (cnt >= max) { 3383 device_printf(sc->dev, 3384 "%s: Ctl overflow!\n", 3385 __func__); 3386 break; 3387 } 3388 cw = hdac_widget_get(devinfo, 3389 w->conns[j]); 3390 if (cw == NULL || cw->enable == 0) 3391 continue; 3392 ctls[cnt].enable = 1; 3393 ctls[cnt].widget = w; 3394 ctls[cnt].childwidget = cw; 3395 ctls[cnt].index = j; 3396 ctls[cnt].mute = mute; 3397 ctls[cnt].step = step; 3398 ctls[cnt].size = size; 3399 ctls[cnt].offset = offset; 3400 ctls[cnt].left = offset; 3401 ctls[cnt].right = offset; 3402 ctls[cnt++].dir = HDA_CTL_IN; 3403 } 3404 break; 3405 default: 3406 if (cnt >= max) { 3407 device_printf(sc->dev, 3408 "%s: Ctl overflow!\n", 3409 __func__); 3410 break; 3411 } 3412 ctls[cnt].enable = 1; 3413 ctls[cnt].widget = w; 3414 ctls[cnt].mute = mute; 3415 ctls[cnt].step = step; 3416 ctls[cnt].size = size; 3417 ctls[cnt].offset = offset; 3418 ctls[cnt].left = offset; 3419 ctls[cnt].right = offset; 3420 ctls[cnt++].dir = HDA_CTL_IN; 3421 break; 3422 } 3423 } 3424 } 3425 3426 devinfo->function.audio.ctl = ctls; 3427} 3428 3429static const struct { 3430 uint32_t model; 3431 uint32_t id; 3432 uint32_t set, unset; 3433} hdac_quirks[] = { 3434 /* 3435 * XXX Force stereo quirk. Monoural recording / playback 3436 * on few codecs (especially ALC880) seems broken or 3437 * perhaps unsupported. 3438 */ 3439 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3440 HDA_QUIRK_FORCESTEREO, 0 }, 3441 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3442 HDA_QUIRK_GPIO1, 0 }, 3443 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3444 HDA_QUIRK_GPIO1, 0 }, 3445 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3446 HDA_QUIRK_EAPDINV, 0 }, 3447 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3448 HDA_QUIRK_EAPDINV, 0 }, 3449 { LNV_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3450 HDA_QUIRK_EAPDINV, 0 }, 3451 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3452 0, HDA_QUIRK_FORCESTEREO }, 3453 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3454 HDA_QUIRK_SOFTPCMVOL, 0 } 3455}; 3456#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3457 3458static void 3459hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3460{ 3461 struct hdac_widget *w; 3462 uint32_t id, subvendor; 3463 int i; 3464 3465 id = hdac_codec_id(devinfo); 3466 subvendor = devinfo->codec->sc->pci_subvendor; 3467 3468 /* 3469 * Quirks 3470 */ 3471 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3472 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3473 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3474 continue; 3475 if (hdac_quirks[i].set != 0) 3476 devinfo->function.audio.quirks |= 3477 hdac_quirks[i].set; 3478 if (hdac_quirks[i].unset != 0) 3479 devinfo->function.audio.quirks &= 3480 ~(hdac_quirks[i].unset); 3481 } 3482 3483 switch (id) { 3484 case HDA_CODEC_ALC260: 3485 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3486 w = hdac_widget_get(devinfo, i); 3487 if (w == NULL || w->enable == 0) 3488 continue; 3489 if (w->type != 3490 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3491 continue; 3492 if (w->nid != 5) 3493 w->enable = 0; 3494 } 3495 break; 3496 case HDA_CODEC_ALC880: 3497 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3498 w = hdac_widget_get(devinfo, i); 3499 if (w == NULL || w->enable == 0) 3500 continue; 3501 if (w->type == 3502 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3503 w->nid != 9 && w->nid != 29) { 3504 w->enable = 0; 3505 } else if (w->type != 3506 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3507 w->nid == 29) { 3508 w->type = 3509 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3510 w->param.widget_cap &= 3511 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3512 w->param.widget_cap |= 3513 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3514 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3515 strlcpy(w->name, "beep widget", sizeof(w->name)); 3516 } 3517 } 3518 break; 3519 case HDA_CODEC_AD1981HD: 3520 w = hdac_widget_get(devinfo, 11); 3521 if (w != NULL && w->enable != 0 && w->nconns > 3) 3522 w->selconn = 3; 3523 if (subvendor == IBM_M52_SUBVENDOR) { 3524 struct hdac_audio_ctl *ctl; 3525 3526 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3527 if (ctl != NULL) 3528 ctl->ossmask = SOUND_MASK_SPEAKER; 3529 } 3530 break; 3531 case HDA_CODEC_AD1986A: 3532 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3533 w = hdac_widget_get(devinfo, i); 3534 if (w == NULL || w->enable == 0) 3535 continue; 3536 if (w->type != 3537 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3538 continue; 3539 if (w->nid != 3) 3540 w->enable = 0; 3541 } 3542 break; 3543 case HDA_CODEC_STAC9221: 3544 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3545 w = hdac_widget_get(devinfo, i); 3546 if (w == NULL || w->enable == 0) 3547 continue; 3548 if (w->type != 3549 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3550 continue; 3551 if (w->nid != 2) 3552 w->enable = 0; 3553 } 3554 break; 3555 case HDA_CODEC_STAC9221D: 3556 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3557 w = hdac_widget_get(devinfo, i); 3558 if (w == NULL || w->enable == 0) 3559 continue; 3560 if (w->type == 3561 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3562 w->nid != 6) 3563 w->enable = 0; 3564 3565 } 3566 break; 3567 default: 3568 break; 3569 } 3570} 3571 3572static int 3573hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3574{ 3575 int *dev = &devinfo->function.audio.ossidx; 3576 3577 while (*dev < SOUND_MIXER_NRDEVICES) { 3578 switch (*dev) { 3579 case SOUND_MIXER_VOLUME: 3580 case SOUND_MIXER_BASS: 3581 case SOUND_MIXER_TREBLE: 3582 case SOUND_MIXER_PCM: 3583 case SOUND_MIXER_SPEAKER: 3584 case SOUND_MIXER_LINE: 3585 case SOUND_MIXER_MIC: 3586 case SOUND_MIXER_CD: 3587 case SOUND_MIXER_RECLEV: 3588 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3589 (*dev)++; 3590 break; 3591 default: 3592 return (*dev)++; 3593 break; 3594 } 3595 } 3596 3597 return (-1); 3598} 3599 3600static int 3601hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3602{ 3603 struct hdac_widget *w; 3604 int i, ret = 0; 3605 3606 if (depth > HDA_PARSE_MAXDEPTH) 3607 return (0); 3608 w = hdac_widget_get(devinfo, nid); 3609 if (w == NULL || w->enable == 0) 3610 return (0); 3611 switch (w->type) { 3612 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3613 w->pflags |= HDA_DAC_PATH; 3614 ret = 1; 3615 break; 3616 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3617 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3618 for (i = 0; i < w->nconns; i++) { 3619 if (hdac_widget_find_dac_path(devinfo, 3620 w->conns[i], depth + 1) != 0) { 3621 if (w->selconn == -1) 3622 w->selconn = i; 3623 ret = 1; 3624 w->pflags |= HDA_DAC_PATH; 3625 } 3626 } 3627 break; 3628 default: 3629 break; 3630 } 3631 return (ret); 3632} 3633 3634static int 3635hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3636{ 3637 struct hdac_widget *w; 3638 int i, conndev, ret = 0; 3639 3640 if (depth > HDA_PARSE_MAXDEPTH) 3641 return (0); 3642 w = hdac_widget_get(devinfo, nid); 3643 if (w == NULL || w->enable == 0) 3644 return (0); 3645 switch (w->type) { 3646 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3647 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3648 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3649 for (i = 0; i < w->nconns; i++) { 3650 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3651 depth + 1) != 0) { 3652 if (w->selconn == -1) 3653 w->selconn = i; 3654 w->pflags |= HDA_ADC_PATH; 3655 ret = 1; 3656 } 3657 } 3658 break; 3659 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3660 conndev = w->wclass.pin.config & 3661 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3662 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3663 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3664 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3665 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3666 w->pflags |= HDA_ADC_PATH; 3667 ret = 1; 3668 } 3669 break; 3670 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3671 if (w->pflags & HDA_DAC_PATH) { 3672 w->pflags |= HDA_ADC_PATH; 3673 ret = 1; 3674 } 3675 break;*/ 3676 default: 3677 break; 3678 } 3679 return (ret); 3680} 3681 3682static uint32_t 3683hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3684 nid_t nid, nid_t pnid, int index, int depth) 3685{ 3686 struct hdac_widget *w, *pw; 3687 struct hdac_audio_ctl *ctl; 3688 uint32_t fl = 0; 3689 int i, ossdev, conndev, strategy; 3690 3691 if (depth > HDA_PARSE_MAXDEPTH) 3692 return (0); 3693 3694 w = hdac_widget_get(devinfo, nid); 3695 if (w == NULL || w->enable == 0) 3696 return (0); 3697 3698 pw = hdac_widget_get(devinfo, pnid); 3699 strategy = devinfo->function.audio.parsing_strategy; 3700 3701 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3702 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3703 for (i = 0; i < w->nconns; i++) { 3704 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3705 w->nid, i, depth + 1); 3706 } 3707 w->ctlflags |= fl; 3708 return (fl); 3709 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3710 (w->pflags & HDA_DAC_PATH)) { 3711 i = 0; 3712 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3713 if (ctl->enable == 0 || ctl->widget == NULL) 3714 continue; 3715 /* XXX This should be compressed! */ 3716 if ((ctl->widget->nid == w->nid) || 3717 (ctl->widget->nid == pnid && ctl->index == index && 3718 (ctl->dir & HDA_CTL_IN)) || 3719 (ctl->widget->nid == pnid && pw != NULL && 3720 pw->type == 3721 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3722 (pw->nconns < 2 || pw->selconn == index || 3723 pw->selconn == -1) && 3724 (ctl->dir & HDA_CTL_OUT)) || 3725 (strategy == HDA_PARSE_DIRECT && 3726 ctl->widget->nid == w->nid)) { 3727 /*if (pw != NULL && pw->selconn == -1) 3728 pw->selconn = index; 3729 fl |= SOUND_MASK_VOLUME; 3730 fl |= SOUND_MASK_PCM; 3731 ctl->ossmask |= SOUND_MASK_VOLUME; 3732 ctl->ossmask |= SOUND_MASK_PCM; 3733 ctl->ossdev = SOUND_MIXER_PCM;*/ 3734 if (!(w->ctlflags & SOUND_MASK_PCM) || 3735 (pw != NULL && 3736 !(pw->ctlflags & SOUND_MASK_PCM))) { 3737 fl |= SOUND_MASK_VOLUME; 3738 fl |= SOUND_MASK_PCM; 3739 ctl->ossmask |= SOUND_MASK_VOLUME; 3740 ctl->ossmask |= SOUND_MASK_PCM; 3741 ctl->ossdev = SOUND_MIXER_PCM; 3742 w->ctlflags |= SOUND_MASK_VOLUME; 3743 w->ctlflags |= SOUND_MASK_PCM; 3744 if (pw != NULL) { 3745 if (pw->selconn == -1) 3746 pw->selconn = index; 3747 pw->ctlflags |= 3748 SOUND_MASK_VOLUME; 3749 pw->ctlflags |= 3750 SOUND_MASK_PCM; 3751 } 3752 } 3753 } 3754 } 3755 w->ctlflags |= fl; 3756 return (fl); 3757 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3758 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3759 (w->pflags & HDA_ADC_PATH)) { 3760 conndev = w->wclass.pin.config & 3761 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3762 i = 0; 3763 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3764 if (ctl->enable == 0 || ctl->widget == NULL) 3765 continue; 3766 /* XXX This should be compressed! */ 3767 if (((ctl->widget->nid == pnid && ctl->index == index && 3768 (ctl->dir & HDA_CTL_IN)) || 3769 (ctl->widget->nid == pnid && pw != NULL && 3770 pw->type == 3771 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3772 (pw->nconns < 2 || pw->selconn == index || 3773 pw->selconn == -1) && 3774 (ctl->dir & HDA_CTL_OUT)) || 3775 (strategy == HDA_PARSE_DIRECT && 3776 ctl->widget->nid == w->nid)) && 3777 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3778 if (pw != NULL && pw->selconn == -1) 3779 pw->selconn = index; 3780 ossdev = 0; 3781 switch (conndev) { 3782 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3783 ossdev = SOUND_MIXER_MIC; 3784 break; 3785 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3786 ossdev = SOUND_MIXER_LINE; 3787 break; 3788 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3789 ossdev = SOUND_MIXER_CD; 3790 break; 3791 default: 3792 ossdev = 3793 hdac_audio_ctl_ossmixer_getnextdev( 3794 devinfo); 3795 if (ossdev < 0) 3796 ossdev = 0; 3797 break; 3798 } 3799 if (strategy == HDA_PARSE_MIXER) { 3800 fl |= SOUND_MASK_VOLUME; 3801 ctl->ossmask |= SOUND_MASK_VOLUME; 3802 } 3803 fl |= 1 << ossdev; 3804 ctl->ossmask |= 1 << ossdev; 3805 ctl->ossdev = ossdev; 3806 } 3807 } 3808 w->ctlflags |= fl; 3809 return (fl); 3810 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3811 i = 0; 3812 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3813 if (ctl->enable == 0 || ctl->widget == NULL) 3814 continue; 3815 /* XXX This should be compressed! */ 3816 if (((ctl->widget->nid == pnid && ctl->index == index && 3817 (ctl->dir & HDA_CTL_IN)) || 3818 (ctl->widget->nid == pnid && pw != NULL && 3819 pw->type == 3820 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3821 (pw->nconns < 2 || pw->selconn == index || 3822 pw->selconn == -1) && 3823 (ctl->dir & HDA_CTL_OUT)) || 3824 (strategy == HDA_PARSE_DIRECT && 3825 ctl->widget->nid == w->nid)) && 3826 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3827 if (pw != NULL && pw->selconn == -1) 3828 pw->selconn = index; 3829 fl |= SOUND_MASK_VOLUME; 3830 fl |= SOUND_MASK_SPEAKER; 3831 ctl->ossmask |= SOUND_MASK_VOLUME; 3832 ctl->ossmask |= SOUND_MASK_SPEAKER; 3833 ctl->ossdev = SOUND_MIXER_SPEAKER; 3834 } 3835 } 3836 w->ctlflags |= fl; 3837 return (fl); 3838 } 3839 return (0); 3840} 3841 3842static uint32_t 3843hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3844{ 3845 struct hdac_widget *w, *cw; 3846 struct hdac_audio_ctl *ctl; 3847 uint32_t fl; 3848 int i; 3849 3850 if (depth > HDA_PARSE_MAXDEPTH) 3851 return (0); 3852 3853 w = hdac_widget_get(devinfo, nid); 3854 if (w == NULL || w->enable == 0) 3855 return (0); 3856 /*if (!(w->pflags & HDA_ADC_PATH)) 3857 return (0); 3858 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3859 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3860 return (0);*/ 3861 i = 0; 3862 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3863 if (ctl->enable == 0 || ctl->widget == NULL) 3864 continue; 3865 if (ctl->widget->nid == nid) { 3866 ctl->ossmask |= SOUND_MASK_RECLEV; 3867 w->ctlflags |= SOUND_MASK_RECLEV; 3868 return (SOUND_MASK_RECLEV); 3869 } 3870 } 3871 for (i = 0; i < w->nconns; i++) { 3872 cw = hdac_widget_get(devinfo, w->conns[i]); 3873 if (cw == NULL || cw->enable == 0) 3874 continue; 3875 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3876 continue; 3877 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3878 if (fl != 0) { 3879 cw->ctlflags |= fl; 3880 w->ctlflags |= fl; 3881 return (fl); 3882 } 3883 } 3884 return (0); 3885} 3886 3887static int 3888hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3889{ 3890 struct hdac_widget *w, *cw; 3891 int i, child = 0; 3892 3893 if (depth > HDA_PARSE_MAXDEPTH) 3894 return (0); 3895 3896 w = hdac_widget_get(devinfo, nid); 3897 if (w == NULL || w->enable == 0) 3898 return (0); 3899 /*if (!(w->pflags & HDA_ADC_PATH)) 3900 return (0); 3901 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3902 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3903 return (0);*/ 3904 /* XXX weak! */ 3905 for (i = 0; i < w->nconns; i++) { 3906 cw = hdac_widget_get(devinfo, w->conns[i]); 3907 if (cw == NULL) 3908 continue; 3909 if (++child > 1) { 3910 w->pflags |= HDA_ADC_RECSEL; 3911 return (1); 3912 } 3913 } 3914 for (i = 0; i < w->nconns; i++) { 3915 if (hdac_audio_ctl_recsel_build(devinfo, 3916 w->conns[i], depth + 1) != 0) 3917 return (1); 3918 } 3919 return (0); 3920} 3921 3922static int 3923hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3924{ 3925 struct hdac_widget *w, *cw; 3926 int i, j, conndev, found_dac = 0; 3927 int strategy; 3928 3929 strategy = devinfo->function.audio.parsing_strategy; 3930 3931 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3932 w = hdac_widget_get(devinfo, i); 3933 if (w == NULL || w->enable == 0) 3934 continue; 3935 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3936 continue; 3937 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3938 continue; 3939 conndev = w->wclass.pin.config & 3940 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3941 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3942 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3943 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3944 continue; 3945 for (j = 0; j < w->nconns; j++) { 3946 cw = hdac_widget_get(devinfo, w->conns[j]); 3947 if (cw == NULL || cw->enable == 0) 3948 continue; 3949 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3950 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3951 cw->type == 3952 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3953 continue; 3954 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3955 != 0) { 3956 if (w->selconn == -1) 3957 w->selconn = j; 3958 w->pflags |= HDA_DAC_PATH; 3959 found_dac++; 3960 } 3961 } 3962 } 3963 3964 return (found_dac); 3965} 3966 3967static void 3968hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3969{ 3970 struct hdac_widget *w; 3971 struct hdac_audio_ctl *ctl; 3972 int i, j, dacs, strategy; 3973 3974 /* Construct DAC path */ 3975 strategy = HDA_PARSE_MIXER; 3976 devinfo->function.audio.parsing_strategy = strategy; 3977 HDA_BOOTVERBOSE( 3978 device_printf(devinfo->codec->sc->dev, 3979 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 3980 HDA_WIDGET_PARSER_REV); 3981 ); 3982 dacs = hdac_audio_build_tree_strategy(devinfo); 3983 if (dacs == 0) { 3984 HDA_BOOTVERBOSE( 3985 device_printf(devinfo->codec->sc->dev, 3986 "HDA_DEBUG: HWiP: 0 DAC path found! " 3987 "Retrying parser " 3988 "using HDA_PARSE_DIRECT strategy.\n"); 3989 ); 3990 strategy = HDA_PARSE_DIRECT; 3991 devinfo->function.audio.parsing_strategy = strategy; 3992 dacs = hdac_audio_build_tree_strategy(devinfo); 3993 } 3994 3995 HDA_BOOTVERBOSE( 3996 device_printf(devinfo->codec->sc->dev, 3997 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 3998 "strategy.\n", 3999 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4000 ); 4001 4002 /* Construct ADC path */ 4003 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4004 w = hdac_widget_get(devinfo, i); 4005 if (w == NULL || w->enable == 0) 4006 continue; 4007 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4008 continue; 4009 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4010 } 4011 4012 /* Output mixers */ 4013 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4014 w = hdac_widget_get(devinfo, i); 4015 if (w == NULL || w->enable == 0) 4016 continue; 4017 if ((strategy == HDA_PARSE_MIXER && 4018 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4019 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4020 && (w->pflags & HDA_DAC_PATH)) || 4021 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4022 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4023 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4024 w->nid, devinfo->startnode - 1, 0, 0); 4025 } else if (w->type == 4026 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4027 j = 0; 4028 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4029 NULL) { 4030 if (ctl->enable == 0 || ctl->widget == NULL) 4031 continue; 4032 if (ctl->widget->nid != w->nid) 4033 continue; 4034 ctl->ossmask |= SOUND_MASK_VOLUME; 4035 ctl->ossmask |= SOUND_MASK_SPEAKER; 4036 ctl->ossdev = SOUND_MIXER_SPEAKER; 4037 w->ctlflags |= SOUND_MASK_VOLUME; 4038 w->ctlflags |= SOUND_MASK_SPEAKER; 4039 } 4040 } 4041 } 4042 4043 /* Input mixers (rec) */ 4044 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4045 w = hdac_widget_get(devinfo, i); 4046 if (w == NULL || w->enable == 0) 4047 continue; 4048 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4049 w->pflags & HDA_ADC_PATH)) 4050 continue; 4051 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4052 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4053 } 4054} 4055 4056#define HDA_COMMIT_CONN (1 << 0) 4057#define HDA_COMMIT_CTRL (1 << 1) 4058#define HDA_COMMIT_EAPD (1 << 2) 4059#define HDA_COMMIT_GPIO (1 << 3) 4060#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4061 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4062 4063static void 4064hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4065{ 4066 struct hdac_softc *sc = devinfo->codec->sc; 4067 struct hdac_widget *w; 4068 nid_t cad, nid; 4069 int i, gpioval; 4070 4071 if (!(cfl & HDA_COMMIT_ALL)) 4072 return; 4073 4074 cad = devinfo->codec->cad; 4075 4076 if (cfl & HDA_COMMIT_GPIO) { 4077 nid = devinfo->nid; 4078 for (i = 0; i < HDA_GPIO_MAX; i++) { 4079 if (!(devinfo->function.audio.quirks & (1 << i))) 4080 continue; 4081 gpioval = (1 << i) - 1; 4082 hdac_command(sc, 4083 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, gpioval), 4084 cad); 4085 hdac_command(sc, 4086 HDA_CMD_SET_GPIO_DIRECTION(cad, nid, gpioval), 4087 cad); 4088 hdac_command(sc, 4089 HDA_CMD_SET_GPIO_DATA(cad, nid, gpioval), 4090 cad); 4091 } 4092 } 4093 4094 for (i = 0; i < devinfo->nodecnt; i++) { 4095 w = &devinfo->widget[i]; 4096 if (w == NULL || w->enable == 0) 4097 continue; 4098 if (cfl & HDA_COMMIT_CONN) { 4099 if (w->selconn == -1) 4100 w->selconn = 0; 4101 if (w->nconns > 0) 4102 hdac_widget_connection_select(w, w->selconn); 4103 } 4104 if ((cfl & HDA_COMMIT_CTRL) && 4105 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4106 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4107 (HDA_DAC_PATH | HDA_ADC_PATH)) 4108 device_printf(sc->dev, "WARNING: node %d " 4109 "participate both for DAC/ADC!\n", w->nid); 4110 if (w->pflags & HDA_DAC_PATH) { 4111 w->wclass.pin.ctrl &= 4112 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4113 if ((w->wclass.pin.config & 4114 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4115 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4116 w->wclass.pin.ctrl &= 4117 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4118 } else if (w->pflags & HDA_ADC_PATH) { 4119 w->wclass.pin.ctrl &= 4120 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4121 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4122 } else 4123 w->wclass.pin.ctrl &= ~( 4124 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4125 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4126 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 4127 hdac_command(sc, 4128 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4129 w->wclass.pin.ctrl), cad); 4130 } 4131 if ((cfl & HDA_COMMIT_EAPD) && 4132 w->param.eapdbtl != HDAC_INVALID) { 4133 uint32_t val; 4134 4135 val = w->param.eapdbtl; 4136 if (devinfo->function.audio.quirks & 4137 HDA_QUIRK_EAPDINV) 4138 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4139 hdac_command(sc, 4140 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4141 val), cad); 4142 4143 } 4144 DELAY(1000); 4145 } 4146} 4147 4148static void 4149hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4150{ 4151 struct hdac_softc *sc = devinfo->codec->sc; 4152 struct hdac_audio_ctl *ctl; 4153 int i; 4154 4155 devinfo->function.audio.mvol = 100 | (100 << 8); 4156 i = 0; 4157 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4158 if (ctl->enable == 0 || ctl->widget == NULL) { 4159 HDA_BOOTVERBOSE( 4160 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4161 i, (ctl->widget != NULL) ? 4162 ctl->widget->nid : -1); 4163 if (ctl->childwidget != NULL) 4164 printf(" childnid=%d", 4165 ctl->childwidget->nid); 4166 if (ctl->widget == NULL) 4167 printf(" NULL WIDGET!"); 4168 printf(" DISABLED\n"); 4169 ); 4170 continue; 4171 } 4172 HDA_BOOTVERBOSE( 4173 if (ctl->ossmask == 0) { 4174 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4175 i, ctl->widget->nid); 4176 if (ctl->childwidget != NULL) 4177 printf(" childnid=%d", 4178 ctl->childwidget->nid); 4179 printf(" Bind to NONE\n"); 4180 } 4181 ); 4182 if (ctl->step > 0) { 4183 ctl->ossval = (ctl->left * 100) / ctl->step; 4184 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4185 } else 4186 ctl->ossval = 0; 4187 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4188 ctl->left, ctl->right); 4189 } 4190} 4191 4192static int 4193hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4194{ 4195 struct hdac_chan *ch; 4196 struct hdac_widget *w; 4197 uint32_t cap, fmtcap, pcmcap, path; 4198 int i, type, ret, max; 4199 4200 if (dir == PCMDIR_PLAY) { 4201 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4202 ch = &devinfo->codec->sc->play; 4203 path = HDA_DAC_PATH; 4204 } else { 4205 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4206 ch = &devinfo->codec->sc->rec; 4207 path = HDA_ADC_PATH; 4208 } 4209 4210 ch->caps = hdac_caps; 4211 ch->caps.fmtlist = ch->fmtlist; 4212 ch->bit16 = 1; 4213 ch->bit32 = 0; 4214 ch->pcmrates[0] = 48000; 4215 ch->pcmrates[1] = 0; 4216 4217 ret = 0; 4218 fmtcap = devinfo->function.audio.supp_stream_formats; 4219 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4220 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4221 4222 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4223 w = hdac_widget_get(devinfo, i); 4224 if (w == NULL || w->enable == 0 || w->type != type || 4225 !(w->pflags & path)) 4226 continue; 4227 cap = w->param.widget_cap; 4228 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4229 continue;*/ 4230 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4231 continue; 4232 cap = w->param.supp_stream_formats; 4233 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4234 } 4235 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4236 }*/ 4237 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4238 continue; 4239 if (ret == 0) { 4240 fmtcap = w->param.supp_stream_formats; 4241 pcmcap = w->param.supp_pcm_size_rate; 4242 } else { 4243 fmtcap &= w->param.supp_stream_formats; 4244 pcmcap &= w->param.supp_pcm_size_rate; 4245 } 4246 ch->io[ret++] = i; 4247 } 4248 ch->io[ret] = -1; 4249 4250 ch->supp_stream_formats = fmtcap; 4251 ch->supp_pcm_size_rate = pcmcap; 4252 4253 /* 4254 * 8bit = 0 4255 * 16bit = 1 4256 * 20bit = 2 4257 * 24bit = 3 4258 * 32bit = 4 4259 */ 4260 if (ret > 0) { 4261 cap = pcmcap; 4262 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4263 ch->bit16 = 1; 4264 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4265 ch->bit16 = 0; 4266 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4267 ch->bit32 = 4; 4268 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4269 ch->bit32 = 3; 4270 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4271 ch->bit32 = 2; 4272 i = 0; 4273 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4274 ch->fmtlist[i++] = AFMT_S16_LE; 4275 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4276 if (ch->bit32 > 0) { 4277 if (!(devinfo->function.audio.quirks & 4278 HDA_QUIRK_FORCESTEREO)) 4279 ch->fmtlist[i++] = AFMT_S32_LE; 4280 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4281 } 4282 ch->fmtlist[i] = 0; 4283 i = 0; 4284 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4285 ch->pcmrates[i++] = 8000; 4286 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4287 ch->pcmrates[i++] = 11025; 4288 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4289 ch->pcmrates[i++] = 16000; 4290 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4291 ch->pcmrates[i++] = 22050; 4292 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4293 ch->pcmrates[i++] = 32000; 4294 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4295 ch->pcmrates[i++] = 44100; 4296 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4297 ch->pcmrates[i++] = 48000; 4298 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4299 ch->pcmrates[i++] = 88200; 4300 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4301 ch->pcmrates[i++] = 96000; 4302 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4303 ch->pcmrates[i++] = 176400; 4304 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4305 ch->pcmrates[i++] = 192000; 4306 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4307 ch->pcmrates[i] = 0; 4308 if (i > 0) { 4309 ch->caps.minspeed = ch->pcmrates[0]; 4310 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4311 } 4312 } 4313 4314 return (ret); 4315} 4316 4317static void 4318hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4319{ 4320 struct hdac_audio_ctl *ctl; 4321 struct hdac_softc *sc = devinfo->codec->sc; 4322 int i; 4323 uint32_t fl = 0; 4324 4325 4326 if (flag == 0) { 4327 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4328 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4329 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4330 } 4331 4332 i = 0; 4333 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4334 if (ctl->enable == 0 || ctl->widget == NULL || 4335 ctl->widget->enable == 0) 4336 continue; 4337 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4338 (flag != 0 && (ctl->ossmask & flag))) { 4339 if (banner != NULL) { 4340 device_printf(sc->dev, "\n"); 4341 device_printf(sc->dev, "%s\n", banner); 4342 } 4343 goto hdac_ctl_dump_it_all; 4344 } 4345 } 4346 4347 return; 4348 4349hdac_ctl_dump_it_all: 4350 i = 0; 4351 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4352 if (ctl->enable == 0 || ctl->widget == NULL || 4353 ctl->widget->enable == 0) 4354 continue; 4355 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4356 (flag != 0 && (ctl->ossmask & flag)))) 4357 continue; 4358 if (flag == 0) { 4359 device_printf(sc->dev, "\n"); 4360 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4361 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4362 } 4363 device_printf(sc->dev, " |\n"); 4364 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4365 ctl->widget->nid, ctl->index); 4366 if (ctl->childwidget != NULL) 4367 printf("(nid: %2d) ", ctl->childwidget->nid); 4368 else 4369 printf(" "); 4370 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4371 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4372 ctl->ossmask); 4373 } 4374} 4375 4376static void 4377hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4378{ 4379 uint32_t cap; 4380 4381 cap = fcap; 4382 if (cap != 0) { 4383 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4384 device_printf(sc->dev, " Format:"); 4385 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4386 printf(" AC3"); 4387 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4388 printf(" FLOAT32"); 4389 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4390 printf(" PCM"); 4391 printf("\n"); 4392 } 4393 cap = pcmcap; 4394 if (cap != 0) { 4395 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4396 device_printf(sc->dev, " PCM size:"); 4397 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4398 printf(" 8"); 4399 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4400 printf(" 16"); 4401 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4402 printf(" 20"); 4403 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4404 printf(" 24"); 4405 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4406 printf(" 32"); 4407 printf("\n"); 4408 device_printf(sc->dev, " PCM rate:"); 4409 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4410 printf(" 8"); 4411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4412 printf(" 11"); 4413 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4414 printf(" 16"); 4415 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4416 printf(" 22"); 4417 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4418 printf(" 32"); 4419 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4420 printf(" 44"); 4421 printf(" 48"); 4422 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4423 printf(" 88"); 4424 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4425 printf(" 96"); 4426 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4427 printf(" 176"); 4428 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4429 printf(" 192"); 4430 printf("\n"); 4431 } 4432} 4433 4434static void 4435hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4436{ 4437 uint32_t pincap, wcap; 4438 4439 pincap = w->wclass.pin.cap; 4440 wcap = w->param.widget_cap; 4441 4442 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4443 device_printf(sc->dev, " "); 4444 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4445 printf(" ISC"); 4446 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4447 printf(" TRQD"); 4448 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4449 printf(" PDC"); 4450 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4451 printf(" HP"); 4452 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4453 printf(" OUT"); 4454 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4455 printf(" IN"); 4456 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4457 printf(" BAL"); 4458 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4459 printf(" EAPD"); 4460 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4461 printf(" : UNSOL"); 4462 printf("\n"); 4463 device_printf(sc->dev, " Pin config: 0x%08x\n", 4464 w->wclass.pin.config); 4465 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4466 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4467 printf(" HP"); 4468 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4469 printf(" IN"); 4470 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4471 printf(" OUT"); 4472 printf("\n"); 4473} 4474 4475static void 4476hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4477{ 4478 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4479 device_printf(sc->dev, " " 4480 "mute=%d step=%d size=%d offset=%d\n", 4481 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4482 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4483 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4484 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4485} 4486 4487static void 4488hdac_dump_nodes(struct hdac_devinfo *devinfo) 4489{ 4490 struct hdac_softc *sc = devinfo->codec->sc; 4491 struct hdac_widget *w, *cw; 4492 int i, j; 4493 4494 device_printf(sc->dev, "\n"); 4495 device_printf(sc->dev, "Default Parameter\n"); 4496 device_printf(sc->dev, "-----------------\n"); 4497 hdac_dump_audio_formats(sc, 4498 devinfo->function.audio.supp_stream_formats, 4499 devinfo->function.audio.supp_pcm_size_rate); 4500 device_printf(sc->dev, " IN amp: 0x%08x\n", 4501 devinfo->function.audio.inamp_cap); 4502 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4503 devinfo->function.audio.outamp_cap); 4504 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4505 w = hdac_widget_get(devinfo, i); 4506 if (w == NULL) { 4507 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4508 continue; 4509 } 4510 device_printf(sc->dev, "\n"); 4511 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4512 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4513 "DIGITAL" : "ANALOG", 4514 (w->enable == 0) ? " [DISABLED]" : ""); 4515 device_printf(sc->dev, " name: %s\n", w->name); 4516 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4517 w->param.widget_cap); 4518 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4519 w->pflags); 4520 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4521 w->ctlflags); 4522 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4523 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4524 hdac_dump_audio_formats(sc, 4525 w->param.supp_stream_formats, 4526 w->param.supp_pcm_size_rate); 4527 } else if (w->type == 4528 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4529 hdac_dump_pin(sc, w); 4530 if (w->param.eapdbtl != HDAC_INVALID) 4531 device_printf(sc->dev, " EAPD: 0x%08x\n", 4532 w->param.eapdbtl); 4533 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4534 w->param.outamp_cap != 0) 4535 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4536 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4537 w->param.inamp_cap != 0) 4538 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4539 device_printf(sc->dev, " connections: %d\n", w->nconns); 4540 for (j = 0; j < w->nconns; j++) { 4541 cw = hdac_widget_get(devinfo, w->conns[j]); 4542 device_printf(sc->dev, " |\n"); 4543 device_printf(sc->dev, " + <- nid=%d [%s]", 4544 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4545 if (cw == NULL) 4546 printf(" [UNKNOWN]"); 4547 else if (cw->enable == 0) 4548 printf(" [DISABLED]"); 4549 if (w->nconns > 1 && w->selconn == j && w->type != 4550 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4551 printf(" (selected)"); 4552 printf("\n"); 4553 } 4554 } 4555 4556} 4557 4558static int 4559hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4560{ 4561 struct hdac_widget *w, *cw; 4562 struct hdac_softc *sc = devinfo->codec->sc; 4563 int i; 4564 4565 if (depth > HDA_PARSE_MAXDEPTH) 4566 return (0); 4567 4568 w = hdac_widget_get(devinfo, nid); 4569 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4570 return (0); 4571 4572 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4573 device_printf(sc->dev, "\n"); 4574 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4575 device_printf(sc->dev, " ^\n"); 4576 device_printf(sc->dev, " |\n"); 4577 device_printf(sc->dev, " +-----<------+\n"); 4578 } else { 4579 device_printf(sc->dev, " ^\n"); 4580 device_printf(sc->dev, " |\n"); 4581 device_printf(sc->dev, " "); 4582 printf(" nid=%d [%s]\n", w->nid, w->name); 4583 } 4584 4585 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4586 return (1); 4587 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4588 for (i = 0; i < w->nconns; i++) { 4589 cw = hdac_widget_get(devinfo, w->conns[i]); 4590 if (cw == NULL || cw->enable == 0 || cw->type == 4591 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4592 continue; 4593 if (hdac_dump_dac_internal(devinfo, cw->nid, 4594 depth + 1) != 0) 4595 return (1); 4596 } 4597 } else if ((w->type == 4598 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4599 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4600 w->selconn > -1 && w->selconn < w->nconns) { 4601 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4602 depth + 1) != 0) 4603 return (1); 4604 } 4605 4606 return (0); 4607} 4608 4609static void 4610hdac_dump_dac(struct hdac_devinfo *devinfo) 4611{ 4612 struct hdac_widget *w; 4613 struct hdac_softc *sc = devinfo->codec->sc; 4614 int i, printed = 0; 4615 4616 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4617 w = hdac_widget_get(devinfo, i); 4618 if (w == NULL || w->enable == 0) 4619 continue; 4620 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4621 !(w->pflags & HDA_DAC_PATH)) 4622 continue; 4623 if (printed == 0) { 4624 printed = 1; 4625 device_printf(sc->dev, "\n"); 4626 device_printf(sc->dev, "Playback path:\n"); 4627 } 4628 hdac_dump_dac_internal(devinfo, w->nid, 0); 4629 } 4630} 4631 4632static void 4633hdac_dump_adc(struct hdac_devinfo *devinfo) 4634{ 4635 struct hdac_widget *w, *cw; 4636 struct hdac_softc *sc = devinfo->codec->sc; 4637 int i, j; 4638 int printed = 0; 4639 char ossdevs[256]; 4640 4641 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4642 w = hdac_widget_get(devinfo, i); 4643 if (w == NULL || w->enable == 0) 4644 continue; 4645 if (!(w->pflags & HDA_ADC_RECSEL)) 4646 continue; 4647 if (printed == 0) { 4648 printed = 1; 4649 device_printf(sc->dev, "\n"); 4650 device_printf(sc->dev, "Recording sources:\n"); 4651 } 4652 device_printf(sc->dev, "\n"); 4653 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4654 for (j = 0; j < w->nconns; j++) { 4655 cw = hdac_widget_get(devinfo, w->conns[j]); 4656 if (cw == NULL || cw->enable == 0) 4657 continue; 4658 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4659 ossdevs, sizeof(ossdevs)); 4660 device_printf(sc->dev, " |\n"); 4661 device_printf(sc->dev, " + <- nid=%d [%s]", 4662 cw->nid, cw->name); 4663 if (strlen(ossdevs) > 0) { 4664 printf(" [recsrc: %s]", ossdevs); 4665 } 4666 printf("\n"); 4667 } 4668 } 4669} 4670 4671static void 4672hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4673{ 4674 nid_t *nids; 4675 4676 if (pcnt > 0) { 4677 device_printf(sc->dev, "\n"); 4678 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4679 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4680 sc->play.supp_pcm_size_rate); 4681 device_printf(sc->dev, " DAC:"); 4682 for (nids = sc->play.io; *nids != -1; nids++) 4683 printf(" %d", *nids); 4684 printf("\n"); 4685 } 4686 4687 if (rcnt > 0) { 4688 device_printf(sc->dev, "\n"); 4689 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4690 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4691 sc->rec.supp_pcm_size_rate); 4692 device_printf(sc->dev, " ADC:"); 4693 for (nids = sc->rec.io; *nids != -1; nids++) 4694 printf(" %d", *nids); 4695 printf("\n"); 4696 } 4697} 4698 4699static void 4700hdac_release_resources(struct hdac_softc *sc) 4701{ 4702 struct hdac_devinfo *devinfo = NULL; 4703 device_t *devlist = NULL; 4704 int i, devcount; 4705 4706 if (sc == NULL) 4707 return; 4708 4709 hdac_lock(sc); 4710 if (sc->polling != 0) 4711 callout_stop(&sc->poll_hdac); 4712 hdac_reset(sc); 4713 hdac_unlock(sc); 4714 snd_mtxfree(sc->lock); 4715 4716 device_get_children(sc->dev, &devlist, &devcount); 4717 for (i = 0; devlist != NULL && i < devcount; i++) { 4718 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4719 if (devinfo == NULL) 4720 continue; 4721 if (devinfo->widget != NULL) 4722 free(devinfo->widget, M_HDAC); 4723 if (devinfo->node_type == 4724 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4725 devinfo->function.audio.ctl != NULL) 4726 free(devinfo->function.audio.ctl, M_HDAC); 4727 free(devinfo, M_HDAC); 4728 device_delete_child(sc->dev, devlist[i]); 4729 } 4730 if (devlist != NULL) 4731 free(devlist, M_TEMP); 4732 4733 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4734 if (sc->codecs[i] != NULL) 4735 free(sc->codecs[i], M_HDAC); 4736 sc->codecs[i] = NULL; 4737 } 4738 4739 hdac_dma_free(&sc->rirb_dma); 4740 hdac_dma_free(&sc->corb_dma); 4741 if (sc->play.blkcnt > 0) 4742 hdac_dma_free(&sc->play.bdl_dma); 4743 if (sc->rec.blkcnt > 0) 4744 hdac_dma_free(&sc->rec.bdl_dma); 4745 hdac_irq_free(sc); 4746 hdac_mem_free(sc); 4747 free(sc, M_DEVBUF); 4748 4749} 4750 4751/* This function surely going to make its way into upper level someday. */ 4752static void 4753hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4754{ 4755 const char *res = NULL; 4756 int i = 0, j, k, len, inv; 4757 4758 if (on != NULL) 4759 *on = 0; 4760 if (off != NULL) 4761 *off = 0; 4762 if (sc == NULL) 4763 return; 4764 if (resource_string_value(device_get_name(sc->dev), 4765 device_get_unit(sc->dev), "config", &res) != 0) 4766 return; 4767 if (!(res != NULL && strlen(res) > 0)) 4768 return; 4769 HDA_BOOTVERBOSE( 4770 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4771 ); 4772 for (;;) { 4773 while (res[i] != '\0' && 4774 (res[i] == ',' || isspace(res[i]) != 0)) 4775 i++; 4776 if (res[i] == '\0') { 4777 HDA_BOOTVERBOSE( 4778 printf("\n"); 4779 ); 4780 return; 4781 } 4782 j = i; 4783 while (res[j] != '\0' && 4784 !(res[j] == ',' || isspace(res[j]) != 0)) 4785 j++; 4786 len = j - i; 4787 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4788 inv = 2; 4789 else 4790 inv = 0; 4791 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4792 if (strncmp(res + i + inv, 4793 hdac_quirks_tab[k].key, len - inv) != 0) 4794 continue; 4795 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4796 break; 4797 HDA_BOOTVERBOSE( 4798 printf(" %s%s", (inv != 0) ? "no" : "", 4799 hdac_quirks_tab[k].key); 4800 ); 4801 if (inv == 0 && on != NULL) 4802 *on |= hdac_quirks_tab[k].value; 4803 else if (inv != 0 && off != NULL) 4804 *off |= hdac_quirks_tab[k].value; 4805 break; 4806 } 4807 i = j; 4808 } 4809} 4810 4811#ifdef SND_DYNSYSCTL 4812static int 4813sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 4814{ 4815 struct hdac_softc *sc; 4816 struct hdac_devinfo *devinfo; 4817 device_t dev; 4818 uint32_t ctl; 4819 int err, val; 4820 4821 dev = oidp->oid_arg1; 4822 devinfo = pcm_getdevinfo(dev); 4823 if (devinfo == NULL || devinfo->codec == NULL || 4824 devinfo->codec->sc == NULL) 4825 return (EINVAL); 4826 sc = devinfo->codec->sc; 4827 hdac_lock(sc); 4828 val = sc->polling; 4829 hdac_unlock(sc); 4830 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 4831 4832 if (err || req->newptr == NULL) 4833 return (err); 4834 if (val < 0 || val > 1) 4835 return (EINVAL); 4836 4837 hdac_lock(sc); 4838 if (val != sc->polling) { 4839 if (hda_chan_active(sc) != 0) 4840 err = EBUSY; 4841 else if (val == 0) { 4842 callout_stop(&sc->poll_hdac); 4843 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 4844 sc->rirb_size / 2); 4845 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4846 ctl |= HDAC_RIRBCTL_RINTCTL; 4847 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4848 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4849 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4850 sc->polling = 0; 4851 DELAY(1000); 4852 } else { 4853 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 4854 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 4855 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 4856 ctl &= ~HDAC_RIRBCTL_RINTCTL; 4857 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 4858 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 4859 sc); 4860 sc->polling = 1; 4861 DELAY(1000); 4862 } 4863 } 4864 hdac_unlock(sc); 4865 4866 return (err); 4867} 4868#endif 4869 4870static void 4871hdac_attach2(void *arg) 4872{ 4873 struct hdac_softc *sc; 4874 struct hdac_widget *w; 4875 struct hdac_audio_ctl *ctl; 4876 uint32_t quirks_on, quirks_off; 4877 int pcnt, rcnt; 4878 int i; 4879 char status[SND_STATUSLEN]; 4880 device_t *devlist = NULL; 4881 int devcount; 4882 struct hdac_devinfo *devinfo = NULL; 4883 4884 sc = (struct hdac_softc *)arg; 4885 4886 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4887 4888 HDA_BOOTVERBOSE( 4889 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4890 quirks_on, quirks_off); 4891 ); 4892 4893 hdac_lock(sc); 4894 4895 /* Remove ourselves from the config hooks */ 4896 if (sc->intrhook.ich_func != NULL) { 4897 config_intrhook_disestablish(&sc->intrhook); 4898 sc->intrhook.ich_func = NULL; 4899 } 4900 4901 /* Start the corb and rirb engines */ 4902 HDA_BOOTVERBOSE( 4903 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4904 ); 4905 hdac_corb_start(sc); 4906 HDA_BOOTVERBOSE( 4907 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4908 ); 4909 hdac_rirb_start(sc); 4910 4911 HDA_BOOTVERBOSE( 4912 device_printf(sc->dev, 4913 "HDA_DEBUG: Enabling controller interrupt...\n"); 4914 ); 4915 if (sc->polling == 0) 4916 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 4917 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4918 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4919 HDAC_GCTL_UNSOL); 4920 4921 DELAY(1000); 4922 4923 HDA_BOOTVERBOSE( 4924 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4925 ); 4926 hdac_scan_codecs(sc); 4927 4928 device_get_children(sc->dev, &devlist, &devcount); 4929 for (i = 0; devlist != NULL && i < devcount; i++) { 4930 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4931 if (devinfo != NULL && devinfo->node_type == 4932 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4933 break; 4934 } else 4935 devinfo = NULL; 4936 } 4937 if (devlist != NULL) 4938 free(devlist, M_TEMP); 4939 4940 if (devinfo == NULL) { 4941 hdac_unlock(sc); 4942 device_printf(sc->dev, "Audio Function Group not found!\n"); 4943 hdac_release_resources(sc); 4944 return; 4945 } 4946 4947 HDA_BOOTVERBOSE( 4948 device_printf(sc->dev, 4949 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4950 devinfo->nid, devinfo->codec->cad); 4951 ); 4952 hdac_audio_parse(devinfo); 4953 HDA_BOOTVERBOSE( 4954 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4955 ); 4956 hdac_audio_ctl_parse(devinfo); 4957 HDA_BOOTVERBOSE( 4958 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4959 ); 4960 hdac_vendor_patch_parse(devinfo); 4961 if (quirks_on != 0) 4962 devinfo->function.audio.quirks |= quirks_on; 4963 if (quirks_off != 0) 4964 devinfo->function.audio.quirks &= ~quirks_off; 4965 4966 /* XXX Disable all DIGITAL path. */ 4967 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4968 w = hdac_widget_get(devinfo, i); 4969 if (w == NULL) 4970 continue; 4971 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4972 w->enable = 0; 4973 continue; 4974 } 4975 /* XXX Disable useless pin ? */ 4976 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4977 (w->wclass.pin.config & 4978 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4979 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4980 w->enable = 0; 4981 } 4982 i = 0; 4983 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4984 if (ctl->widget == NULL) 4985 continue; 4986 w = ctl->widget; 4987 if (w->enable == 0) 4988 ctl->enable = 0; 4989 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4990 ctl->enable = 0; 4991 w = ctl->childwidget; 4992 if (w == NULL) 4993 continue; 4994 if (w->enable == 0 || 4995 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4996 ctl->enable = 0; 4997 } 4998 4999 HDA_BOOTVERBOSE( 5000 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5001 ); 5002 hdac_audio_build_tree(devinfo); 5003 5004 HDA_BOOTVERBOSE( 5005 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5006 ); 5007 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5008 HDA_BOOTVERBOSE( 5009 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5010 ); 5011 hdac_audio_ctl_commit(devinfo); 5012 5013 HDA_BOOTVERBOSE( 5014 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5015 ); 5016 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5017 HDA_BOOTVERBOSE( 5018 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5019 ); 5020 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5021 5022 hdac_unlock(sc); 5023 HDA_BOOTVERBOSE( 5024 device_printf(sc->dev, 5025 "HDA_DEBUG: OSS mixer initialization...\n"); 5026 ); 5027 5028 /* 5029 * There is no point of return after this. If the driver failed, 5030 * so be it. Let the detach procedure do all the cleanup. 5031 */ 5032 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5033 device_printf(sc->dev, "Can't register mixer\n"); 5034 5035 if (pcnt > 0) 5036 pcnt = 1; 5037 if (rcnt > 0) 5038 rcnt = 1; 5039 5040 HDA_BOOTVERBOSE( 5041 device_printf(sc->dev, 5042 "HDA_DEBUG: Registering PCM channels...\n"); 5043 ); 5044 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5045 device_printf(sc->dev, "Can't register PCM\n"); 5046 5047 sc->registered++; 5048 5049 for (i = 0; i < pcnt; i++) 5050 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5051 for (i = 0; i < rcnt; i++) 5052 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5053 5054#ifdef SND_DYNSYSCTL 5055 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5056 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5057 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5058 sysctl_hdac_polling, "I", "Enable polling mode"); 5059#endif 5060 5061 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5062 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5063 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5064 pcm_setstatus(sc->dev, status); 5065 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5066 HDA_BOOTVERBOSE( 5067 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5068 hdac_codec_id(devinfo)); 5069 ); 5070 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5071 HDA_DRV_TEST_REV); 5072 5073 HDA_BOOTVERBOSE( 5074 if (devinfo->function.audio.quirks != 0) { 5075 device_printf(sc->dev, "\n"); 5076 device_printf(sc->dev, "HDA config/quirks:"); 5077 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5078 if (devinfo->function.audio.quirks & 5079 hdac_quirks_tab[i].value) 5080 printf(" %s", hdac_quirks_tab[i].key); 5081 } 5082 printf("\n"); 5083 } 5084 device_printf(sc->dev, "\n"); 5085 device_printf(sc->dev, "+-------------------+\n"); 5086 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5087 device_printf(sc->dev, "+-------------------+\n"); 5088 hdac_dump_nodes(devinfo); 5089 device_printf(sc->dev, "\n"); 5090 device_printf(sc->dev, "+------------------------+\n"); 5091 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5092 device_printf(sc->dev, "+------------------------+\n"); 5093 device_printf(sc->dev, "\n"); 5094 i = 0; 5095 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5096 device_printf(sc->dev, "%3d: nid=%d", i, 5097 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5098 if (ctl->childwidget != NULL) 5099 printf(" cnid=%d", ctl->childwidget->nid); 5100 printf(" dir=0x%x index=%d " 5101 "ossmask=0x%08x ossdev=%d%s\n", 5102 ctl->dir, ctl->index, 5103 ctl->ossmask, ctl->ossdev, 5104 (ctl->enable == 0) ? " [DISABLED]" : ""); 5105 } 5106 device_printf(sc->dev, "\n"); 5107 device_printf(sc->dev, "+-----------------------------------+\n"); 5108 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5109 device_printf(sc->dev, "+-----------------------------------+\n"); 5110 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5111 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5112 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5113 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5114 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5115 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5116 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5117 hdac_dump_ctls(devinfo, NULL, 0); 5118 hdac_dump_dac(devinfo); 5119 hdac_dump_adc(devinfo); 5120 device_printf(sc->dev, "\n"); 5121 device_printf(sc->dev, "+--------------------------------------+\n"); 5122 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5123 device_printf(sc->dev, "+--------------------------------------+\n"); 5124 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5125 ); 5126 5127 if (sc->polling != 0) { 5128 hdac_lock(sc); 5129 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5130 hdac_unlock(sc); 5131 } 5132} 5133 5134/**************************************************************************** 5135 * int hdac_detach(device_t) 5136 * 5137 * Detach and free up resources utilized by the hdac device. 5138 ****************************************************************************/ 5139static int 5140hdac_detach(device_t dev) 5141{ 5142 struct hdac_softc *sc = NULL; 5143 struct hdac_devinfo *devinfo = NULL; 5144 int err; 5145 5146 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5147 if (devinfo != NULL && devinfo->codec != NULL) 5148 sc = devinfo->codec->sc; 5149 if (sc == NULL) 5150 return (0); 5151 5152 if (sc->registered > 0) { 5153 err = pcm_unregister(dev); 5154 if (err != 0) 5155 return (err); 5156 } 5157 5158 hdac_release_resources(sc); 5159 5160 return (0); 5161} 5162 5163static device_method_t hdac_methods[] = { 5164 /* device interface */ 5165 DEVMETHOD(device_probe, hdac_probe), 5166 DEVMETHOD(device_attach, hdac_attach), 5167 DEVMETHOD(device_detach, hdac_detach), 5168 { 0, 0 } 5169}; 5170 5171static driver_t hdac_driver = { 5172 "pcm", 5173 hdac_methods, 5174 PCM_SOFTC_SIZE, 5175}; 5176 5177DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5178MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5179MODULE_VERSION(snd_hda, 1); 5180