hdac.c revision 163432
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especiall UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061017_0033" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 163432 2006-10-16 14:43:22Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 193#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 194 195/* IBM / Lenovo */ 196#define IBM_VENDORID 0x1014 197#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 198#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 199 200 201/* Misc constants.. */ 202#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 203#define HDA_AMP_MUTE_NONE (0) 204#define HDA_AMP_MUTE_LEFT (1 << 0) 205#define HDA_AMP_MUTE_RIGHT (1 << 1) 206#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 207 208#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 209#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 210 211#define HDA_DAC_PATH (1 << 0) 212#define HDA_ADC_PATH (1 << 1) 213#define HDA_ADC_RECSEL (1 << 2) 214 215#define HDA_CTL_OUT (1 << 0) 216#define HDA_CTL_IN (1 << 1) 217#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 218 219#define HDA_GPIO_MAX 15 220/* 0 - 14 = GPIO */ 221#define HDA_QUIRK_GPIO0 (1 << 0) 222#define HDA_QUIRK_GPIO1 (1 << 1) 223#define HDA_QUIRK_GPIO2 (1 << 2) 224#define HDA_QUIRK_SOFTPCMVOL (1 << 15) 225#define HDA_QUIRK_FIXEDRATE (1 << 16) 226#define HDA_QUIRK_FORCESTEREO (1 << 17) 227#define HDA_QUIRK_EAPDINV (1 << 18) 228 229static const struct { 230 char *key; 231 uint32_t value; 232} hdac_quirks_tab[] = { 233 { "gpio0", HDA_QUIRK_GPIO0 }, 234 { "gpio1", HDA_QUIRK_GPIO1 }, 235 { "gpio2", HDA_QUIRK_GPIO2 }, 236 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 237 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 238 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 239 { "eapdinv", HDA_QUIRK_EAPDINV }, 240}; 241#define HDAC_QUIRKS_TAB_LEN \ 242 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 243 244#define HDA_BDL_MIN 2 245#define HDA_BDL_MAX 256 246#define HDA_BDL_DEFAULT HDA_BDL_MIN 247 248#define HDA_BUFSZ_MIN 4096 249#define HDA_BUFSZ_MAX 65536 250#define HDA_BUFSZ_DEFAULT 16384 251 252#define HDA_PARSE_MAXDEPTH 10 253 254#define HDAC_UNSOLTAG_EVENT_HP 0x00 255 256static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 257 258enum { 259 HDA_PARSE_MIXER, 260 HDA_PARSE_DIRECT 261}; 262 263/* Default */ 264static uint32_t hdac_fmt[] = { 265 AFMT_STEREO | AFMT_S16_LE, 266 0 267}; 268 269static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 270 271static const struct { 272 uint32_t model; 273 char *desc; 274} hdac_devices[] = { 275 { HDA_INTEL_82801F, "Intel 82801F" }, 276 { HDA_INTEL_82801G, "Intel 82801G" }, 277 { HDA_INTEL_82801H, "Intel 82801H" }, 278 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 279 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 280 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 281 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 282 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 283 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 284 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 285 { HDA_ATI_SB450, "ATI SB450" }, 286 { HDA_ATI_SB600, "ATI SB600" }, 287 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 288 { HDA_SIS_966, "SiS 966" }, 289 /* Unknown */ 290 { HDA_INTEL_ALL, "Intel (Unknown)" }, 291 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 292 { HDA_ATI_ALL, "ATI (Unknown)" }, 293 { HDA_VIA_ALL, "VIA (Unknown)" }, 294 { HDA_SIS_ALL, "SiS (Unknown)" }, 295}; 296#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 297 298static const struct { 299 uint32_t rate; 300 int valid; 301 uint16_t base; 302 uint16_t mul; 303 uint16_t div; 304} hda_rate_tab[] = { 305 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 306 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 307 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 308 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 309 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 310 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 311 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 312 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 313 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 314 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 315 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 316 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 317 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 318 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 319 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 320 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 321 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 322 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 323 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 324 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 325 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 326 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 327 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 328 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 329 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 330 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 331 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 332 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 333 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 334 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 335 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 336 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 337 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 338 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 339 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 340}; 341#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 342 343/* All codecs you can eat... */ 344#define HDA_CODEC_CONSTRUCT(vendor, id) \ 345 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 346 347/* Realtek */ 348#define REALTEK_VENDORID 0x10ec 349#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 350#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 351#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 352#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 353#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 354#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 355 356/* Analog Device */ 357#define ANALOGDEVICE_VENDORID 0x11d4 358#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 359#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 360#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 361#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 362 363/* CMedia */ 364#define CMEDIA_VENDORID 0x434d 365#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 366#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 367 368/* Sigmatel */ 369#define SIGMATEL_VENDORID 0x8384 370#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 371#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 372#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 373#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 374#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 375 376/* 377 * Conexant 378 * 379 * Ok, the truth is, I don't have any idea at all whether 380 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 381 * place that tell me it is "Venice" is from its Windows driver INF. 382 * 383 * Venice - CX????? 384 * Waikiki - CX20551-22 385 */ 386#define CONEXANT_VENDORID 0x14f1 387#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 388#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 389#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 390 391 392/* Codecs */ 393static const struct { 394 uint32_t id; 395 char *name; 396} hdac_codecs[] = { 397 { HDA_CODEC_ALC260, "Realtek ALC260" }, 398 { HDA_CODEC_ALC861, "Realtek ALC861" }, 399 { HDA_CODEC_ALC880, "Realtek ALC880" }, 400 { HDA_CODEC_ALC882, "Realtek ALC882" }, 401 { HDA_CODEC_ALC883, "Realtek ALC883" }, 402 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 403 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 404 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 405 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 406 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 407 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 408 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 409 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 410 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 411 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 412 /* Unknown codec */ 413 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 414 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 415 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 416 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 417 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 418}; 419#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 420 421enum { 422 HDAC_HP_SWITCH_CTL, 423 HDAC_HP_SWITCH_CTRL 424}; 425 426static const struct { 427 uint32_t model; 428 uint32_t id; 429 int type; 430 nid_t hpnid; 431 nid_t spkrnid[8]; 432 nid_t eapdnid; 433} hdac_hp_switch[] = { 434 /* Specific OEM models */ 435 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 436 17, { 16, -1 }, 16 }, 437 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 438 6, { 5, -1 }, 5 }, 439 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 440 6, { 5, -1 }, 5 }, 441 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 442 13, { 14, -1 }, -1 }, 443 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 444 13, { 14, -1 }, -1 }, 445 /* 446 * All models that at least come from the same vendor with 447 * simmilar codec. 448 */ 449 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 450 17, { 16, -1 }, 16 }, 451 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 452 6, { 5, -1 }, 5 }, 453 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 454 13, { 14, -1 }, -1 }, 455}; 456#define HDAC_HP_SWITCH_LEN \ 457 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 458 459static const struct { 460 uint32_t model; 461 uint32_t id; 462 nid_t eapdnid; 463 int hp_switch; 464} hdac_eapd_switch[] = { 465 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 466 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 467 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 468}; 469#define HDAC_EAPD_SWITCH_LEN \ 470 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 471 472/**************************************************************************** 473 * Function prototypes 474 ****************************************************************************/ 475static void hdac_intr_handler(void *); 476static int hdac_reset(struct hdac_softc *); 477static int hdac_get_capabilities(struct hdac_softc *); 478static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 479static int hdac_dma_alloc(struct hdac_softc *, 480 struct hdac_dma *, bus_size_t); 481static void hdac_dma_free(struct hdac_dma *); 482static int hdac_mem_alloc(struct hdac_softc *); 483static void hdac_mem_free(struct hdac_softc *); 484static int hdac_irq_alloc(struct hdac_softc *); 485static void hdac_irq_free(struct hdac_softc *); 486static void hdac_corb_init(struct hdac_softc *); 487static void hdac_rirb_init(struct hdac_softc *); 488static void hdac_corb_start(struct hdac_softc *); 489static void hdac_rirb_start(struct hdac_softc *); 490static void hdac_scan_codecs(struct hdac_softc *); 491static int hdac_probe_codec(struct hdac_codec *); 492static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 493static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 494 495static void hdac_attach2(void *); 496 497static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 498 uint32_t, int); 499static void hdac_command_send_internal(struct hdac_softc *, 500 struct hdac_command_list *, int); 501 502static int hdac_probe(device_t); 503static int hdac_attach(device_t); 504static int hdac_detach(device_t); 505static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 506static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 507 uint32_t, int, int); 508static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 509 nid_t, int, int); 510static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 511 nid_t, nid_t, int, int, int, int, int, int); 512static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 513static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 514 515#define hdac_command(a1, a2, a3) \ 516 hdac_command_sendone_internal(a1, a2, a3) 517 518#define hdac_codec_id(d) \ 519 ((uint32_t)((d == NULL) ? 0x00000000 : \ 520 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 521 ((uint32_t)(d)->device_id & 0x0000ffff)))) 522 523static char * 524hdac_codec_name(struct hdac_devinfo *devinfo) 525{ 526 uint32_t id; 527 int i; 528 529 id = hdac_codec_id(devinfo); 530 531 for (i = 0; i < HDAC_CODECS_LEN; i++) { 532 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 533 return (hdac_codecs[i].name); 534 } 535 536 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 537} 538 539static char * 540hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 541{ 542 static char *ossname[] = SOUND_DEVICE_NAMES; 543 static char *unknown = "???"; 544 int i; 545 546 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 547 if (devmask & (1 << i)) 548 return (ossname[i]); 549 } 550 return (unknown); 551} 552 553static void 554hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 555{ 556 static char *ossname[] = SOUND_DEVICE_NAMES; 557 int i, first = 1; 558 559 bzero(buf, len); 560 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 561 if (mask & (1 << i)) { 562 if (first == 0) 563 strlcat(buf, ", ", len); 564 strlcat(buf, ossname[i], len); 565 first = 0; 566 } 567 } 568} 569 570static struct hdac_audio_ctl * 571hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 572{ 573 if (devinfo == NULL || 574 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 575 index == NULL || devinfo->function.audio.ctl == NULL || 576 devinfo->function.audio.ctlcnt < 1 || 577 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 578 return (NULL); 579 return (&devinfo->function.audio.ctl[(*index)++]); 580} 581 582static struct hdac_audio_ctl * 583hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 584 int index, int cnt) 585{ 586 struct hdac_audio_ctl *ctl, *retctl = NULL; 587 int i, at, atindex, found = 0; 588 589 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 590 return (NULL); 591 592 at = cnt; 593 if (at == 0) 594 at = 1; 595 else if (at < 0) 596 at = -1; 597 atindex = index; 598 if (atindex < 0) 599 atindex = -1; 600 601 i = 0; 602 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 603 if (ctl->enable == 0 || ctl->widget == NULL) 604 continue; 605 if (!(ctl->widget->nid == nid && (atindex == -1 || 606 ctl->index == atindex))) 607 continue; 608 found++; 609 if (found == cnt) 610 return (ctl); 611 retctl = ctl; 612 } 613 614 return ((at == -1) ? retctl : NULL); 615} 616 617static void 618hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 619{ 620 struct hdac_softc *sc; 621 struct hdac_widget *w; 622 struct hdac_audio_ctl *ctl; 623 uint32_t id, res; 624 int i = 0, j, forcemute; 625 nid_t cad; 626 627 if (devinfo == NULL || devinfo->codec == NULL || 628 devinfo->codec->sc == NULL) 629 return; 630 631 sc = devinfo->codec->sc; 632 cad = devinfo->codec->cad; 633 id = hdac_codec_id(devinfo); 634 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 635 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 636 sc->pci_subvendor) && 637 hdac_hp_switch[i].id == id) 638 break; 639 } 640 641 if (i >= HDAC_HP_SWITCH_LEN) 642 return; 643 644 forcemute = 0; 645 if (hdac_hp_switch[i].eapdnid != -1) { 646 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 647 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 648 forcemute = (w->param.eapdbtl & 649 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 650 } 651 652 res = hdac_command(sc, 653 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 654 HDA_BOOTVERBOSE( 655 device_printf(sc->dev, 656 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 657 hdac_hp_switch[i].hpnid, res); 658 ); 659 res >>= 31; 660 661 switch (hdac_hp_switch[i].type) { 662 case HDAC_HP_SWITCH_CTL: 663 ctl = hdac_audio_ctl_amp_get(devinfo, 664 hdac_hp_switch[i].hpnid, 0, 1); 665 if (ctl != NULL) { 666 ctl->muted = (res != 0 && forcemute == 0) ? 667 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 668 hdac_audio_ctl_amp_set(ctl, 669 HDA_AMP_MUTE_DEFAULT, ctl->left, 670 ctl->right); 671 } 672 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 673 ctl = hdac_audio_ctl_amp_get(devinfo, 674 hdac_hp_switch[i].spkrnid[j], 0, 1); 675 if (ctl != NULL) { 676 ctl->muted = (res != 0 || forcemute == 1) ? 677 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 678 hdac_audio_ctl_amp_set(ctl, 679 HDA_AMP_MUTE_DEFAULT, ctl->left, 680 ctl->right); 681 } 682 } 683 break; 684 case HDAC_HP_SWITCH_CTRL: 685 if (res != 0) { 686 /* HP in */ 687 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 688 if (w != NULL && w->type == 689 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 690 if (forcemute == 0) 691 w->wclass.pin.ctrl |= 692 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 693 else 694 w->wclass.pin.ctrl &= 695 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 696 hdac_command(sc, 697 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 698 w->wclass.pin.ctrl), cad); 699 } 700 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 701 w = hdac_widget_get(devinfo, 702 hdac_hp_switch[i].spkrnid[j]); 703 if (w != NULL && w->type == 704 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 705 w->wclass.pin.ctrl &= 706 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 707 hdac_command(sc, 708 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 709 w->nid, 710 w->wclass.pin.ctrl), cad); 711 } 712 } 713 } else { 714 /* HP out */ 715 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 716 if (w != NULL && w->type == 717 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 718 w->wclass.pin.ctrl &= 719 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 720 hdac_command(sc, 721 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 722 w->wclass.pin.ctrl), cad); 723 } 724 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 725 w = hdac_widget_get(devinfo, 726 hdac_hp_switch[i].spkrnid[j]); 727 if (w != NULL && w->type == 728 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 729 if (forcemute == 0) 730 w->wclass.pin.ctrl |= 731 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 732 else 733 w->wclass.pin.ctrl &= 734 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 735 hdac_command(sc, 736 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 737 w->nid, 738 w->wclass.pin.ctrl), cad); 739 } 740 } 741 } 742 break; 743 default: 744 break; 745 } 746} 747 748static void 749hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 750{ 751 struct hdac_softc *sc; 752 struct hdac_devinfo *devinfo = NULL; 753 device_t *devlist = NULL; 754 int devcount, i; 755 756 if (codec == NULL || codec->sc == NULL) 757 return; 758 759 sc = codec->sc; 760 761 HDA_BOOTVERBOSE( 762 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 763 ); 764 765 device_get_children(sc->dev, &devlist, &devcount); 766 for (i = 0; devlist != NULL && i < devcount; i++) { 767 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 768 if (devinfo != NULL && devinfo->node_type == 769 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 770 devinfo->codec != NULL && 771 devinfo->codec->cad == codec->cad) { 772 break; 773 } else 774 devinfo = NULL; 775 } 776 if (devlist != NULL) 777 free(devlist, M_TEMP); 778 779 if (devinfo == NULL) 780 return; 781 782 switch (tag) { 783 case HDAC_UNSOLTAG_EVENT_HP: 784 hdac_hp_switch_handler(devinfo); 785 break; 786 default: 787 break; 788 } 789} 790 791static void 792hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 793{ 794 /* XXX to be removed */ 795#ifdef HDAC_INTR_EXTRA 796 uint32_t res; 797#endif 798 799 if (ch->blkcnt == 0) 800 return; 801 802 /* XXX to be removed */ 803#ifdef HDAC_INTR_EXTRA 804 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 805#endif 806 807 /* XXX to be removed */ 808#ifdef HDAC_INTR_EXTRA 809 HDA_BOOTVERBOSE( 810 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 811 device_printf(sc->dev, 812 "PCMDIR_%s intr triggered beyond stream boundary:" 813 "%08x\n", 814 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 815 ); 816#endif 817 818 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 819 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 820 821 /* XXX to be removed */ 822#ifdef HDAC_INTR_EXTRA 823 if (res & HDAC_SDSTS_BCIS) { 824#endif 825 ch->prevptr = ch->ptr; 826 ch->ptr += sndbuf_getblksz(ch->b); 827 ch->ptr %= sndbuf_getsize(ch->b); 828 hdac_unlock(sc); 829 chn_intr(ch->c); 830 hdac_lock(sc); 831 /* XXX to be removed */ 832#ifdef HDAC_INTR_EXTRA 833 } 834#endif 835} 836 837/**************************************************************************** 838 * void hdac_intr_handler(void *) 839 * 840 * Interrupt handler. Processes interrupts received from the hdac. 841 ****************************************************************************/ 842static void 843hdac_intr_handler(void *context) 844{ 845 struct hdac_softc *sc; 846 uint32_t intsts; 847 uint8_t rirbsts; 848 uint8_t rirbwp; 849 struct hdac_rirb *rirb_base, *rirb; 850 nid_t ucad; 851 uint32_t utag; 852 853 sc = (struct hdac_softc *)context; 854 855 hdac_lock(sc); 856 /* Do we have anything to do? */ 857 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 858 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 859 hdac_unlock(sc); 860 return; 861 } 862 863 /* Was this a controller interrupt? */ 864 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 865 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 866 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 867 /* Get as many responses that we can */ 868 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 869 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 870 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 871 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 872 BUS_DMASYNC_POSTREAD); 873 while (sc->rirb_rp != rirbwp) { 874 sc->rirb_rp++; 875 sc->rirb_rp %= sc->rirb_size; 876 rirb = &rirb_base[sc->rirb_rp]; 877 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 878 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 879 utag = rirb->response >> 26; 880 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 881 sc->codecs[ucad] != NULL) { 882 sc->unsolq[sc->unsolq_wp++] = 883 (ucad << 16) | 884 (utag & 0xffff); 885 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 886 } 887 } 888 } 889 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 890 } 891 /* XXX to be removed */ 892 /* Clear interrupt and exit */ 893#ifdef HDAC_INTR_EXTRA 894 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 895#endif 896 } 897 if (intsts & HDAC_INTSTS_SIS_MASK) { 898 if (intsts & (1 << sc->num_iss)) 899 hdac_stream_intr(sc, &sc->play); 900 if (intsts & (1 << 0)) 901 hdac_stream_intr(sc, &sc->rec); 902 /* XXX to be removed */ 903#ifdef HDAC_INTR_EXTRA 904 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK); 905#endif 906 } 907 908 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 909 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 910 while (sc->unsolq_rp != sc->unsolq_wp) { 911 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 912 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 913 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 914 hdac_unsolicited_handler(sc->codecs[ucad], utag); 915 } 916 sc->unsolq_st = HDAC_UNSOLQ_READY; 917 } 918 919 hdac_unlock(sc); 920} 921 922/**************************************************************************** 923 * int hdac_reset(hdac_softc *) 924 * 925 * Reset the hdac to a quiescent and known state. 926 ****************************************************************************/ 927static int 928hdac_reset(struct hdac_softc *sc) 929{ 930 uint32_t gctl; 931 int count, i; 932 933 /* 934 * Stop all Streams DMA engine 935 */ 936 for (i = 0; i < sc->num_iss; i++) 937 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 938 for (i = 0; i < sc->num_oss; i++) 939 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 940 for (i = 0; i < sc->num_bss; i++) 941 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 942 943 /* 944 * Stop Control DMA engines 945 */ 946 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 947 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 948 949 /* 950 * Reset the controller. The reset must remain asserted for 951 * a minimum of 100us. 952 */ 953 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 954 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 955 count = 10000; 956 do { 957 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 958 if (!(gctl & HDAC_GCTL_CRST)) 959 break; 960 DELAY(10); 961 } while (--count); 962 if (gctl & HDAC_GCTL_CRST) { 963 device_printf(sc->dev, "Unable to put hdac in reset\n"); 964 return (ENXIO); 965 } 966 DELAY(100); 967 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 968 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 969 count = 10000; 970 do { 971 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 972 if (gctl & HDAC_GCTL_CRST) 973 break; 974 DELAY(10); 975 } while (--count); 976 if (!(gctl & HDAC_GCTL_CRST)) { 977 device_printf(sc->dev, "Device stuck in reset\n"); 978 return (ENXIO); 979 } 980 981 /* 982 * Wait for codecs to finish their own reset sequence. The delay here 983 * should be of 250us but for some reasons, on it's not enough on my 984 * computer. Let's use twice as much as necessary to make sure that 985 * it's reset properly. 986 */ 987 DELAY(1000); 988 989 return (0); 990} 991 992 993/**************************************************************************** 994 * int hdac_get_capabilities(struct hdac_softc *); 995 * 996 * Retreive the general capabilities of the hdac; 997 * Number of Input Streams 998 * Number of Output Streams 999 * Number of bidirectional Streams 1000 * 64bit ready 1001 * CORB and RIRB sizes 1002 ****************************************************************************/ 1003static int 1004hdac_get_capabilities(struct hdac_softc *sc) 1005{ 1006 uint16_t gcap; 1007 uint8_t corbsize, rirbsize; 1008 1009 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1010 sc->num_iss = HDAC_GCAP_ISS(gcap); 1011 sc->num_oss = HDAC_GCAP_OSS(gcap); 1012 sc->num_bss = HDAC_GCAP_BSS(gcap); 1013 1014 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1015 1016 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1017 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1018 HDAC_CORBSIZE_CORBSZCAP_256) 1019 sc->corb_size = 256; 1020 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1021 HDAC_CORBSIZE_CORBSZCAP_16) 1022 sc->corb_size = 16; 1023 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1024 HDAC_CORBSIZE_CORBSZCAP_2) 1025 sc->corb_size = 2; 1026 else { 1027 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1028 __func__, corbsize); 1029 return (ENXIO); 1030 } 1031 1032 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1033 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1034 HDAC_RIRBSIZE_RIRBSZCAP_256) 1035 sc->rirb_size = 256; 1036 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1037 HDAC_RIRBSIZE_RIRBSZCAP_16) 1038 sc->rirb_size = 16; 1039 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1040 HDAC_RIRBSIZE_RIRBSZCAP_2) 1041 sc->rirb_size = 2; 1042 else { 1043 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1044 __func__, rirbsize); 1045 return (ENXIO); 1046 } 1047 1048 return (0); 1049} 1050 1051 1052/**************************************************************************** 1053 * void hdac_dma_cb 1054 * 1055 * This function is called by bus_dmamap_load when the mapping has been 1056 * established. We just record the physical address of the mapping into 1057 * the struct hdac_dma passed in. 1058 ****************************************************************************/ 1059static void 1060hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1061{ 1062 struct hdac_dma *dma; 1063 1064 if (error == 0) { 1065 dma = (struct hdac_dma *)callback_arg; 1066 dma->dma_paddr = segs[0].ds_addr; 1067 } 1068} 1069 1070static void 1071hdac_dma_nocache(void *ptr) 1072{ 1073#if defined(__i386__) || defined(__amd64__) 1074 pt_entry_t *pte; 1075 vm_offset_t va; 1076 1077 va = (vm_offset_t)ptr; 1078 pte = vtopte(va); 1079 if (pte) { 1080 *pte |= PG_N; 1081 invltlb(); 1082 } 1083#endif 1084} 1085 1086/**************************************************************************** 1087 * int hdac_dma_alloc 1088 * 1089 * This function allocate and setup a dma region (struct hdac_dma). 1090 * It must be freed by a corresponding hdac_dma_free. 1091 ****************************************************************************/ 1092static int 1093hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1094{ 1095 int result; 1096 int lowaddr; 1097 1098 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1099 BUS_SPACE_MAXADDR_32BIT; 1100 bzero(dma, sizeof(*dma)); 1101 1102 /* 1103 * Create a DMA tag 1104 */ 1105 result = bus_dma_tag_create(NULL, /* parent */ 1106 HDAC_DMA_ALIGNMENT, /* alignment */ 1107 0, /* boundary */ 1108 lowaddr, /* lowaddr */ 1109 BUS_SPACE_MAXADDR, /* highaddr */ 1110 NULL, /* filtfunc */ 1111 NULL, /* fistfuncarg */ 1112 size, /* maxsize */ 1113 1, /* nsegments */ 1114 size, /* maxsegsz */ 1115 0, /* flags */ 1116 NULL, /* lockfunc */ 1117 NULL, /* lockfuncarg */ 1118 &dma->dma_tag); /* dmat */ 1119 if (result != 0) { 1120 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1121 __func__, result); 1122 goto fail; 1123 } 1124 1125 /* 1126 * Allocate DMA memory 1127 */ 1128 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1129 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1130 if (result != 0) { 1131 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1132 __func__, result); 1133 goto fail; 1134 } 1135 1136 /* 1137 * Map the memory 1138 */ 1139 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1140 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1141 BUS_DMA_NOWAIT); 1142 if (result != 0 || dma->dma_paddr == 0) { 1143 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1144 __func__, result); 1145 goto fail; 1146 } 1147 bzero((void *)dma->dma_vaddr, size); 1148 hdac_dma_nocache(dma->dma_vaddr); 1149 1150 return (0); 1151fail: 1152 if (dma->dma_map != NULL) 1153 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1154 if (dma->dma_tag != NULL) 1155 bus_dma_tag_destroy(dma->dma_tag); 1156 return (result); 1157} 1158 1159 1160/**************************************************************************** 1161 * void hdac_dma_free(struct hdac_dma *) 1162 * 1163 * Free a struct dhac_dma that has been previously allocated via the 1164 * hdac_dma_alloc function. 1165 ****************************************************************************/ 1166static void 1167hdac_dma_free(struct hdac_dma *dma) 1168{ 1169 if (dma->dma_tag != NULL) { 1170 /* Flush caches */ 1171 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1172 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1173 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1174 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1175 bus_dma_tag_destroy(dma->dma_tag); 1176 } 1177} 1178 1179/**************************************************************************** 1180 * int hdac_mem_alloc(struct hdac_softc *) 1181 * 1182 * Allocate all the bus resources necessary to speak with the physical 1183 * controller. 1184 ****************************************************************************/ 1185static int 1186hdac_mem_alloc(struct hdac_softc *sc) 1187{ 1188 struct hdac_mem *mem; 1189 1190 mem = &sc->mem; 1191 mem->mem_rid = PCIR_BAR(0); 1192 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1193 &mem->mem_rid, RF_ACTIVE); 1194 if (mem->mem_res == NULL) { 1195 device_printf(sc->dev, 1196 "%s: Unable to allocate memory resource\n", __func__); 1197 return (ENOMEM); 1198 } 1199 mem->mem_tag = rman_get_bustag(mem->mem_res); 1200 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1201 1202 return (0); 1203} 1204 1205/**************************************************************************** 1206 * void hdac_mem_free(struct hdac_softc *) 1207 * 1208 * Free up resources previously allocated by hdac_mem_alloc. 1209 ****************************************************************************/ 1210static void 1211hdac_mem_free(struct hdac_softc *sc) 1212{ 1213 struct hdac_mem *mem; 1214 1215 mem = &sc->mem; 1216 if (mem->mem_res != NULL) 1217 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1218 mem->mem_res); 1219} 1220 1221/**************************************************************************** 1222 * int hdac_irq_alloc(struct hdac_softc *) 1223 * 1224 * Allocate and setup the resources necessary for interrupt handling. 1225 ****************************************************************************/ 1226static int 1227hdac_irq_alloc(struct hdac_softc *sc) 1228{ 1229 struct hdac_irq *irq; 1230 int result; 1231 1232 irq = &sc->irq; 1233 irq->irq_rid = 0x0; 1234 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1235 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1236 if (irq->irq_res == NULL) { 1237 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1238 __func__); 1239 goto fail; 1240 } 1241 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1242 hdac_intr_handler, sc, &irq->irq_handle); 1243 if (result != 0) { 1244 device_printf(sc->dev, 1245 "%s: Unable to setup interrupt handler (%x)\n", 1246 __func__, result); 1247 goto fail; 1248 } 1249 1250 return (0); 1251 1252fail: 1253 if (irq->irq_res != NULL) 1254 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1255 irq->irq_res); 1256 return (ENXIO); 1257} 1258 1259/**************************************************************************** 1260 * void hdac_irq_free(struct hdac_softc *) 1261 * 1262 * Free up resources previously allocated by hdac_irq_alloc. 1263 ****************************************************************************/ 1264static void 1265hdac_irq_free(struct hdac_softc *sc) 1266{ 1267 struct hdac_irq *irq; 1268 1269 irq = &sc->irq; 1270 if (irq->irq_handle != NULL) 1271 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1272 if (irq->irq_res != NULL) 1273 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1274 irq->irq_res); 1275} 1276 1277/**************************************************************************** 1278 * void hdac_corb_init(struct hdac_softc *) 1279 * 1280 * Initialize the corb registers for operations but do not start it up yet. 1281 * The CORB engine must not be running when this function is called. 1282 ****************************************************************************/ 1283static void 1284hdac_corb_init(struct hdac_softc *sc) 1285{ 1286 uint8_t corbsize; 1287 uint64_t corbpaddr; 1288 1289 /* Setup the CORB size. */ 1290 switch (sc->corb_size) { 1291 case 256: 1292 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1293 break; 1294 case 16: 1295 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1296 break; 1297 case 2: 1298 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1299 break; 1300 default: 1301 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1302 } 1303 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1304 1305 /* Setup the CORB Address in the hdac */ 1306 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1307 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1308 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1309 1310 /* Set the WP and RP */ 1311 sc->corb_wp = 0; 1312 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1313 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1314 /* 1315 * The HDA specification indicates that the CORBRPRST bit will always 1316 * read as zero. Unfortunately, it seems that at least the 82801G 1317 * doesn't reset the bit to zero, which stalls the corb engine. 1318 * manually reset the bit to zero before continuing. 1319 */ 1320 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1321 1322 /* Enable CORB error reporting */ 1323#if 0 1324 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1325#endif 1326} 1327 1328/**************************************************************************** 1329 * void hdac_rirb_init(struct hdac_softc *) 1330 * 1331 * Initialize the rirb registers for operations but do not start it up yet. 1332 * The RIRB engine must not be running when this function is called. 1333 ****************************************************************************/ 1334static void 1335hdac_rirb_init(struct hdac_softc *sc) 1336{ 1337 uint8_t rirbsize; 1338 uint64_t rirbpaddr; 1339 1340 /* Setup the RIRB size. */ 1341 switch (sc->rirb_size) { 1342 case 256: 1343 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1344 break; 1345 case 16: 1346 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1347 break; 1348 case 2: 1349 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1350 break; 1351 default: 1352 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1353 } 1354 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1355 1356 /* Setup the RIRB Address in the hdac */ 1357 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1358 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1359 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1360 1361 /* Setup the WP and RP */ 1362 sc->rirb_rp = 0; 1363 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1364 1365 /* Setup the interrupt threshold */ 1366 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1367 1368 /* Enable Overrun and response received reporting */ 1369#if 0 1370 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1371 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1372#else 1373 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1374#endif 1375 1376 /* 1377 * Make sure that the Host CPU cache doesn't contain any dirty 1378 * cache lines that falls in the rirb. If I understood correctly, it 1379 * should be sufficient to do this only once as the rirb is purely 1380 * read-only from now on. 1381 */ 1382 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1383 BUS_DMASYNC_PREREAD); 1384} 1385 1386/**************************************************************************** 1387 * void hdac_corb_start(hdac_softc *) 1388 * 1389 * Startup the corb DMA engine 1390 ****************************************************************************/ 1391static void 1392hdac_corb_start(struct hdac_softc *sc) 1393{ 1394 uint32_t corbctl; 1395 1396 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1397 corbctl |= HDAC_CORBCTL_CORBRUN; 1398 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1399} 1400 1401/**************************************************************************** 1402 * void hdac_rirb_start(hdac_softc *) 1403 * 1404 * Startup the rirb DMA engine 1405 ****************************************************************************/ 1406static void 1407hdac_rirb_start(struct hdac_softc *sc) 1408{ 1409 uint32_t rirbctl; 1410 1411 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1412 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1413 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1414} 1415 1416 1417/**************************************************************************** 1418 * void hdac_scan_codecs(struct hdac_softc *) 1419 * 1420 * Scan the bus for available codecs. 1421 ****************************************************************************/ 1422static void 1423hdac_scan_codecs(struct hdac_softc *sc) 1424{ 1425 struct hdac_codec *codec; 1426 int i; 1427 uint16_t statests; 1428 1429 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1430 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1431 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1432 /* We have found a codec. */ 1433 hdac_unlock(sc); 1434 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1435 M_HDAC, M_ZERO | M_NOWAIT); 1436 hdac_lock(sc); 1437 if (codec == NULL) { 1438 device_printf(sc->dev, 1439 "Unable to allocate memory for codec\n"); 1440 continue; 1441 } 1442 codec->verbs_sent = 0; 1443 codec->sc = sc; 1444 codec->cad = i; 1445 sc->codecs[i] = codec; 1446 if (hdac_probe_codec(codec) != 0) 1447 break; 1448 } 1449 } 1450 /* All codecs have been probed, now try to attach drivers to them */ 1451 /* bus_generic_attach(sc->dev); */ 1452} 1453 1454/**************************************************************************** 1455 * void hdac_probe_codec(struct hdac_softc *, int) 1456 * 1457 * Probe a the given codec_id for available function groups. 1458 ****************************************************************************/ 1459static int 1460hdac_probe_codec(struct hdac_codec *codec) 1461{ 1462 struct hdac_softc *sc = codec->sc; 1463 struct hdac_devinfo *devinfo; 1464 uint32_t vendorid, revisionid, subnode; 1465 int startnode; 1466 int endnode; 1467 int i; 1468 nid_t cad = codec->cad; 1469 1470 HDA_BOOTVERBOSE( 1471 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1472 ); 1473 vendorid = hdac_command(sc, 1474 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1475 cad); 1476 revisionid = hdac_command(sc, 1477 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1478 cad); 1479 subnode = hdac_command(sc, 1480 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1481 cad); 1482 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1483 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1484 1485 HDA_BOOTVERBOSE( 1486 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1487 startnode, endnode); 1488 ); 1489 for (i = startnode; i < endnode; i++) { 1490 devinfo = hdac_probe_function(codec, i); 1491 if (devinfo != NULL) { 1492 /* XXX Ignore other FG. */ 1493 devinfo->vendor_id = 1494 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1495 devinfo->device_id = 1496 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1497 devinfo->revision_id = 1498 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1499 devinfo->stepping_id = 1500 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1501 HDA_BOOTVERBOSE( 1502 device_printf(sc->dev, 1503 "HDA_DEBUG: \tFound AFG nid=%d " 1504 "[startnode=%d endnode=%d]\n", 1505 devinfo->nid, startnode, endnode); 1506 ); 1507 return (1); 1508 } 1509 } 1510 1511 HDA_BOOTVERBOSE( 1512 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1513 ); 1514 return (0); 1515} 1516 1517static struct hdac_devinfo * 1518hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1519{ 1520 struct hdac_softc *sc = codec->sc; 1521 struct hdac_devinfo *devinfo; 1522 uint32_t fctgrptype; 1523 nid_t cad = codec->cad; 1524 1525 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1526 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1527 1528 /* XXX For now, ignore other FG. */ 1529 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1530 return (NULL); 1531 1532 hdac_unlock(sc); 1533 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1534 M_NOWAIT | M_ZERO); 1535 hdac_lock(sc); 1536 if (devinfo == NULL) { 1537 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1538 __func__); 1539 return (NULL); 1540 } 1541 1542 devinfo->nid = nid; 1543 devinfo->node_type = fctgrptype; 1544 devinfo->codec = codec; 1545 1546 hdac_add_child(sc, devinfo); 1547 1548 return (devinfo); 1549} 1550 1551static void 1552hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1553{ 1554 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1555 device_set_ivars(devinfo->dev, (void *)devinfo); 1556 /* XXX - Print more information when booting verbose??? */ 1557} 1558 1559static void 1560hdac_widget_connection_parse(struct hdac_widget *w) 1561{ 1562 struct hdac_softc *sc = w->devinfo->codec->sc; 1563 uint32_t res; 1564 int i, j, max, found, entnum, cnid; 1565 nid_t cad = w->devinfo->codec->cad; 1566 nid_t nid = w->nid; 1567 1568 res = hdac_command(sc, 1569 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1570 1571 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1572 1573 if (w->nconns < 1) 1574 return; 1575 1576 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1577 res = 0; 1578 i = 0; 1579 found = 0; 1580 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1581 1582 while (i < w->nconns) { 1583 res = hdac_command(sc, 1584 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1585 for (j = 0; j < entnum; j++) { 1586 cnid = res; 1587 cnid >>= (32 / entnum) * j; 1588 cnid &= (1 << (32 / entnum)) - 1; 1589 if (cnid == 0) 1590 continue; 1591 if (found > max) { 1592 device_printf(sc->dev, 1593 "node %d: Adding %d: " 1594 "Max connection reached!\n", 1595 nid, cnid); 1596 continue; 1597 } 1598 w->conns[found++] = cnid; 1599 } 1600 i += entnum; 1601 } 1602 1603 HDA_BOOTVERBOSE( 1604 if (w->nconns != found) { 1605 device_printf(sc->dev, 1606 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1607 "length=%d != found=%d\n", 1608 nid, w->nconns, found); 1609 } 1610 ); 1611} 1612 1613static uint32_t 1614hdac_widget_pin_getconfig(struct hdac_widget *w) 1615{ 1616 struct hdac_softc *sc; 1617 uint32_t config, id; 1618 nid_t cad, nid; 1619 1620 sc = w->devinfo->codec->sc; 1621 cad = w->devinfo->codec->cad; 1622 nid = w->nid; 1623 id = hdac_codec_id(w->devinfo); 1624 1625 config = hdac_command(sc, 1626 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1627 cad); 1628 /* 1629 * XXX REWRITE!!!! Don't argue! 1630 */ 1631 if (id == HDA_CODEC_ALC880 && 1632 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1633 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1634 /* 1635 * Super broken BIOS 1636 */ 1637 switch (nid) { 1638 case 20: 1639 break; 1640 case 21: 1641 break; 1642 case 22: 1643 break; 1644 case 23: 1645 break; 1646 case 24: /* MIC1 */ 1647 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1648 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1649 break; 1650 case 25: /* XXX MIC2 */ 1651 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1652 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1653 break; 1654 case 26: /* LINE1 */ 1655 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1656 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1657 break; 1658 case 27: /* XXX LINE2 */ 1659 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1660 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1661 break; 1662 case 28: /* CD */ 1663 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1664 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1665 break; 1666 case 30: 1667 break; 1668 case 31: 1669 break; 1670 default: 1671 break; 1672 } 1673 } 1674 1675 return (config); 1676} 1677 1678static void 1679hdac_widget_pin_parse(struct hdac_widget *w) 1680{ 1681 struct hdac_softc *sc = w->devinfo->codec->sc; 1682 uint32_t config, pincap; 1683 char *devstr, *connstr; 1684 nid_t cad = w->devinfo->codec->cad; 1685 nid_t nid = w->nid; 1686 1687 config = hdac_widget_pin_getconfig(w); 1688 w->wclass.pin.config = config; 1689 1690 pincap = hdac_command(sc, 1691 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1692 w->wclass.pin.cap = pincap; 1693 1694 w->wclass.pin.ctrl = hdac_command(sc, 1695 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1696 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1697 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1698 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1699 1700 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1701 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1702 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1703 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1704 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1705 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1706 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1707 w->param.eapdbtl = hdac_command(sc, 1708 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1709 w->param.eapdbtl &= 0x7; 1710 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1711 } else 1712 w->param.eapdbtl = HDAC_INVALID; 1713 1714 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1715 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1716 devstr = "line out"; 1717 break; 1718 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1719 devstr = "speaker"; 1720 break; 1721 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1722 devstr = "headphones out"; 1723 break; 1724 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1725 devstr = "CD"; 1726 break; 1727 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1728 devstr = "SPDIF out"; 1729 break; 1730 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1731 devstr = "digital (other) out"; 1732 break; 1733 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1734 devstr = "modem, line side"; 1735 break; 1736 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1737 devstr = "modem, handset side"; 1738 break; 1739 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1740 devstr = "line in"; 1741 break; 1742 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1743 devstr = "AUX"; 1744 break; 1745 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1746 devstr = "Mic in"; 1747 break; 1748 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1749 devstr = "telephony"; 1750 break; 1751 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1752 devstr = "SPDIF in"; 1753 break; 1754 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1755 devstr = "digital (other) in"; 1756 break; 1757 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1758 devstr = "other"; 1759 break; 1760 default: 1761 devstr = "unknown"; 1762 break; 1763 } 1764 1765 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1766 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1767 connstr = "jack"; 1768 break; 1769 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1770 connstr = "none"; 1771 break; 1772 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1773 connstr = "fixed"; 1774 break; 1775 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1776 connstr = "jack / fixed"; 1777 break; 1778 default: 1779 connstr = "unknown"; 1780 break; 1781 } 1782 1783 strlcat(w->name, ": ", sizeof(w->name)); 1784 strlcat(w->name, devstr, sizeof(w->name)); 1785 strlcat(w->name, " (", sizeof(w->name)); 1786 strlcat(w->name, connstr, sizeof(w->name)); 1787 strlcat(w->name, ")", sizeof(w->name)); 1788} 1789 1790static void 1791hdac_widget_parse(struct hdac_widget *w) 1792{ 1793 struct hdac_softc *sc = w->devinfo->codec->sc; 1794 uint32_t wcap, cap; 1795 char *typestr; 1796 nid_t cad = w->devinfo->codec->cad; 1797 nid_t nid = w->nid; 1798 1799 wcap = hdac_command(sc, 1800 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1801 cad); 1802 w->param.widget_cap = wcap; 1803 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1804 1805 switch (w->type) { 1806 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1807 typestr = "audio output"; 1808 break; 1809 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1810 typestr = "audio input"; 1811 break; 1812 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1813 typestr = "audio mixer"; 1814 break; 1815 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1816 typestr = "audio selector"; 1817 break; 1818 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1819 typestr = "pin"; 1820 break; 1821 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1822 typestr = "power widget"; 1823 break; 1824 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1825 typestr = "volume widget"; 1826 break; 1827 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1828 typestr = "beep widget"; 1829 break; 1830 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1831 typestr = "vendor widget"; 1832 break; 1833 default: 1834 typestr = "unknown type"; 1835 break; 1836 } 1837 1838 strlcpy(w->name, typestr, sizeof(w->name)); 1839 1840 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1841 hdac_command(sc, 1842 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1843 cad); 1844 DELAY(1000); 1845 } 1846 1847 hdac_widget_connection_parse(w); 1848 1849 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1850 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1851 w->param.outamp_cap = 1852 hdac_command(sc, 1853 HDA_CMD_GET_PARAMETER(cad, nid, 1854 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1855 else 1856 w->param.outamp_cap = 1857 w->devinfo->function.audio.outamp_cap; 1858 } else 1859 w->param.outamp_cap = 0; 1860 1861 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1862 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1863 w->param.inamp_cap = 1864 hdac_command(sc, 1865 HDA_CMD_GET_PARAMETER(cad, nid, 1866 HDA_PARAM_INPUT_AMP_CAP), cad); 1867 else 1868 w->param.inamp_cap = 1869 w->devinfo->function.audio.inamp_cap; 1870 } else 1871 w->param.inamp_cap = 0; 1872 1873 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1874 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1875 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1876 cap = hdac_command(sc, 1877 HDA_CMD_GET_PARAMETER(cad, nid, 1878 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1879 w->param.supp_stream_formats = (cap != 0) ? cap : 1880 w->devinfo->function.audio.supp_stream_formats; 1881 cap = hdac_command(sc, 1882 HDA_CMD_GET_PARAMETER(cad, nid, 1883 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1884 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1885 w->devinfo->function.audio.supp_pcm_size_rate; 1886 } else { 1887 w->param.supp_stream_formats = 1888 w->devinfo->function.audio.supp_stream_formats; 1889 w->param.supp_pcm_size_rate = 1890 w->devinfo->function.audio.supp_pcm_size_rate; 1891 } 1892 } else { 1893 w->param.supp_stream_formats = 0; 1894 w->param.supp_pcm_size_rate = 0; 1895 } 1896 1897 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1898 hdac_widget_pin_parse(w); 1899} 1900 1901static struct hdac_widget * 1902hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1903{ 1904 if (devinfo == NULL || devinfo->widget == NULL || 1905 nid < devinfo->startnode || nid >= devinfo->endnode) 1906 return (NULL); 1907 return (&devinfo->widget[nid - devinfo->startnode]); 1908} 1909 1910static void 1911hdac_stream_stop(struct hdac_chan *ch) 1912{ 1913 struct hdac_softc *sc = ch->devinfo->codec->sc; 1914 uint32_t ctl; 1915 1916 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1917 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1918 HDAC_SDCTL_RUN); 1919 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1920 1921 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1922 ctl &= ~(1 << (ch->off >> 5)); 1923 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1924} 1925 1926static void 1927hdac_stream_start(struct hdac_chan *ch) 1928{ 1929 struct hdac_softc *sc = ch->devinfo->codec->sc; 1930 uint32_t ctl; 1931 1932 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1933 ctl |= 1 << (ch->off >> 5); 1934 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1935 1936 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1937 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1938 HDAC_SDCTL_RUN; 1939 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1940} 1941 1942static void 1943hdac_stream_reset(struct hdac_chan *ch) 1944{ 1945 struct hdac_softc *sc = ch->devinfo->codec->sc; 1946 int timeout = 1000; 1947 int to = timeout; 1948 uint32_t ctl; 1949 1950 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1951 ctl |= HDAC_SDCTL_SRST; 1952 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1953 do { 1954 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1955 if (ctl & HDAC_SDCTL_SRST) 1956 break; 1957 DELAY(10); 1958 } while (--to); 1959 if (!(ctl & HDAC_SDCTL_SRST)) { 1960 device_printf(sc->dev, "timeout in reset\n"); 1961 } 1962 ctl &= ~HDAC_SDCTL_SRST; 1963 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1964 to = timeout; 1965 do { 1966 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1967 if (!(ctl & HDAC_SDCTL_SRST)) 1968 break; 1969 DELAY(10); 1970 } while (--to); 1971 if (ctl & HDAC_SDCTL_SRST) 1972 device_printf(sc->dev, "can't reset!\n"); 1973} 1974 1975static void 1976hdac_stream_setid(struct hdac_chan *ch) 1977{ 1978 struct hdac_softc *sc = ch->devinfo->codec->sc; 1979 uint32_t ctl; 1980 1981 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 1982 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1983 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 1984 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 1985} 1986 1987static void 1988hdac_bdl_setup(struct hdac_chan *ch) 1989{ 1990 struct hdac_softc *sc = ch->devinfo->codec->sc; 1991 uint64_t addr; 1992 int blks, size, blocksize; 1993 struct hdac_bdle *bdle; 1994 int i; 1995 1996 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 1997 size = sndbuf_getsize(ch->b); 1998 blocksize = sndbuf_getblksz(ch->b); 1999 blks = size / blocksize; 2000 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr; 2001 2002 for (i = 0; i < blks; i++, bdle++) { 2003 bdle->addrl = (uint32_t)addr; 2004 bdle->addrh = (uint32_t)(addr >> 32); 2005 bdle->len = blocksize; 2006 bdle->ioc = 1; 2007 2008 addr += blocksize; 2009 } 2010 2011 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size); 2012 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1); 2013 addr = ch->bdl_dma.dma_paddr; 2014 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2015 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2016} 2017 2018static int 2019hdac_bdl_alloc(struct hdac_chan *ch) 2020{ 2021 struct hdac_softc *sc = ch->devinfo->codec->sc; 2022 int rc; 2023 2024 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2025 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2026 if (rc) { 2027 device_printf(sc->dev, "can't alloc bdl\n"); 2028 return (rc); 2029 } 2030 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2031 2032 return (0); 2033} 2034 2035static void 2036hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2037 int index, int lmute, int rmute, 2038 int left, int right, int dir) 2039{ 2040 uint16_t v = 0; 2041 2042 if (sc == NULL) 2043 return; 2044 2045 if (left != right || lmute != rmute) { 2046 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2047 (lmute << 7) | left; 2048 hdac_command(sc, 2049 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2050 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2051 (rmute << 7) | right; 2052 } else 2053 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2054 (lmute << 7) | left; 2055 2056 hdac_command(sc, 2057 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2058} 2059 2060static void 2061hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2062 int left, int right) 2063{ 2064 struct hdac_softc *sc; 2065 nid_t nid, cad; 2066 int lmute, rmute; 2067 2068 if (ctl == NULL || ctl->widget == NULL || 2069 ctl->widget->devinfo == NULL || 2070 ctl->widget->devinfo->codec == NULL || 2071 ctl->widget->devinfo->codec->sc == NULL) 2072 return; 2073 2074 sc = ctl->widget->devinfo->codec->sc; 2075 cad = ctl->widget->devinfo->codec->cad; 2076 nid = ctl->widget->nid; 2077 2078 if (mute == HDA_AMP_MUTE_DEFAULT) { 2079 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2080 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2081 } else { 2082 lmute = HDA_AMP_LEFT_MUTED(mute); 2083 rmute = HDA_AMP_RIGHT_MUTED(mute); 2084 } 2085 2086 if (ctl->dir & HDA_CTL_OUT) 2087 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2088 lmute, rmute, left, right, 0); 2089 if (ctl->dir & HDA_CTL_IN) 2090 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2091 lmute, rmute, left, right, 1); 2092 ctl->left = left; 2093 ctl->right = right; 2094} 2095 2096static void 2097hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2098{ 2099 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2100 return; 2101 hdac_command(w->devinfo->codec->sc, 2102 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2103 w->nid, index), w->devinfo->codec->cad); 2104 w->selconn = index; 2105} 2106 2107 2108/**************************************************************************** 2109 * uint32_t hdac_command_sendone_internal 2110 * 2111 * Wrapper function that sends only one command to a given codec 2112 ****************************************************************************/ 2113static uint32_t 2114hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2115{ 2116 struct hdac_command_list cl; 2117 uint32_t response = HDAC_INVALID; 2118 2119 if (!hdac_lockowned(sc)) 2120 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2121 cl.num_commands = 1; 2122 cl.verbs = &verb; 2123 cl.responses = &response; 2124 2125 hdac_command_send_internal(sc, &cl, cad); 2126 2127 return (response); 2128} 2129 2130/**************************************************************************** 2131 * hdac_command_send_internal 2132 * 2133 * Send a command list to the codec via the corb. We queue as much verbs as 2134 * we can and msleep on the codec. When the interrupt get the responses 2135 * back from the rirb, it will wake us up so we can queue the remaining verbs 2136 * if any. 2137 ****************************************************************************/ 2138static void 2139hdac_command_send_internal(struct hdac_softc *sc, 2140 struct hdac_command_list *commands, nid_t cad) 2141{ 2142 struct hdac_codec *codec; 2143 int corbrp; 2144 uint32_t *corb; 2145 uint8_t rirbwp; 2146 int timeout; 2147 int retry = 10; 2148 struct hdac_rirb *rirb_base, *rirb; 2149 nid_t ucad; 2150 uint32_t utag; 2151 2152 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL) 2153 return; 2154 2155 codec = sc->codecs[cad]; 2156 codec->commands = commands; 2157 codec->responses_received = 0; 2158 codec->verbs_sent = 0; 2159 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2160 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2161 2162 do { 2163 if (codec->verbs_sent != commands->num_commands) { 2164 /* Queue as many verbs as possible */ 2165 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2166 bus_dmamap_sync(sc->corb_dma.dma_tag, 2167 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2168 while (codec->verbs_sent != commands->num_commands && 2169 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2170 sc->corb_wp++; 2171 sc->corb_wp %= sc->corb_size; 2172 corb[sc->corb_wp] = 2173 commands->verbs[codec->verbs_sent++]; 2174 } 2175 2176 /* Send the verbs to the codecs */ 2177 bus_dmamap_sync(sc->corb_dma.dma_tag, 2178 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2179 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2180 } 2181 2182 timeout = 1000; 2183 do { 2184 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2185 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2186 BUS_DMASYNC_POSTREAD); 2187 if (sc->rirb_rp != rirbwp) { 2188 do { 2189 sc->rirb_rp++; 2190 sc->rirb_rp %= sc->rirb_size; 2191 rirb = &rirb_base[sc->rirb_rp]; 2192 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2193 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2194 utag = rirb->response >> 26; 2195 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 2196 sc->codecs[ucad] != NULL) { 2197 sc->unsolq[sc->unsolq_wp++] = 2198 (ucad << 16) | 2199 (utag & 0xffff); 2200 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2201 } 2202 } else if (codec->responses_received < commands->num_commands) 2203 codec->commands->responses[codec->responses_received++] = 2204 rirb->response; 2205 } while (sc->rirb_rp != rirbwp); 2206 break; 2207 } 2208 DELAY(10); 2209 } while (--timeout); 2210 } while ((codec->verbs_sent != commands->num_commands || 2211 codec->responses_received != commands->num_commands) && 2212 --retry); 2213 2214 if (retry == 0) 2215 device_printf(sc->dev, 2216 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2217 __func__, commands->num_commands, 2218 codec->verbs_sent, codec->responses_received); 2219 2220 codec->verbs_sent = 0; 2221 2222 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2223 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2224 while (sc->unsolq_rp != sc->unsolq_wp) { 2225 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 2226 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2227 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2228 hdac_unsolicited_handler(sc->codecs[ucad], utag); 2229 } 2230 sc->unsolq_st = HDAC_UNSOLQ_READY; 2231 } 2232} 2233 2234 2235/**************************************************************************** 2236 * Device Methods 2237 ****************************************************************************/ 2238 2239/**************************************************************************** 2240 * int hdac_probe(device_t) 2241 * 2242 * Probe for the presence of an hdac. If none is found, check for a generic 2243 * match using the subclass of the device. 2244 ****************************************************************************/ 2245static int 2246hdac_probe(device_t dev) 2247{ 2248 int i, result; 2249 uint32_t model; 2250 uint16_t class, subclass; 2251 char desc[64]; 2252 2253 model = (uint32_t)pci_get_device(dev) << 16; 2254 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2255 class = pci_get_class(dev); 2256 subclass = pci_get_subclass(dev); 2257 2258 bzero(desc, sizeof(desc)); 2259 result = ENXIO; 2260 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2261 if (hdac_devices[i].model == model) { 2262 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2263 result = BUS_PROBE_DEFAULT; 2264 break; 2265 } 2266 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2267 class == PCIC_MULTIMEDIA && 2268 subclass == PCIS_MULTIMEDIA_HDA) { 2269 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2270 result = BUS_PROBE_GENERIC; 2271 break; 2272 } 2273 } 2274 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2275 subclass == PCIS_MULTIMEDIA_HDA) { 2276 strlcpy(desc, "Generic", sizeof(desc)); 2277 result = BUS_PROBE_GENERIC; 2278 } 2279 if (result != ENXIO) { 2280 strlcat(desc, " High Definition Audio Controller", 2281 sizeof(desc)); 2282 device_set_desc_copy(dev, desc); 2283 } 2284 2285 return (result); 2286} 2287 2288static void * 2289hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2290 struct pcm_channel *c, int dir) 2291{ 2292 struct hdac_devinfo *devinfo = data; 2293 struct hdac_softc *sc = devinfo->codec->sc; 2294 struct hdac_chan *ch; 2295 2296 hdac_lock(sc); 2297 if (dir == PCMDIR_PLAY) { 2298 ch = &sc->play; 2299 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2300 ch->dir = PCMDIR_PLAY; 2301 ch->sid = ++sc->streamcnt; 2302 devinfo->function.audio.playcnt++; 2303 } else { 2304 ch = &sc->rec; 2305 ch->off = devinfo->function.audio.reccnt << 5; 2306 ch->dir = PCMDIR_REC; 2307 ch->sid = ++sc->streamcnt; 2308 devinfo->function.audio.reccnt++; 2309 } 2310 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2311 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2312 ch->pcmrates[0] = 48000; 2313 ch->pcmrates[1] = 0; 2314 } 2315 ch->b = b; 2316 ch->c = c; 2317 ch->devinfo = devinfo; 2318 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2319 ch->blkcnt = sc->chan_blkcnt; 2320 hdac_unlock(sc); 2321 2322 if (hdac_bdl_alloc(ch) != 0) { 2323 ch->blkcnt = 0; 2324 return (NULL); 2325 } 2326 2327 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2328 return (NULL); 2329 2330 hdac_dma_nocache(ch->b->buf); 2331 2332 return (ch); 2333} 2334 2335static int 2336hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2337{ 2338 struct hdac_chan *ch = data; 2339 int i; 2340 2341 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2342 if (format == ch->caps.fmtlist[i]) { 2343 ch->fmt = format; 2344 return (0); 2345 } 2346 } 2347 2348 return (EINVAL); 2349} 2350 2351static int 2352hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2353{ 2354 struct hdac_chan *ch = data; 2355 uint32_t spd = 0; 2356 int i; 2357 2358 for (i = 0; ch->pcmrates[i] != 0; i++) { 2359 spd = ch->pcmrates[i]; 2360 if (spd >= speed) 2361 break; 2362 } 2363 2364 if (spd == 0) 2365 ch->spd = 48000; 2366 else 2367 ch->spd = spd; 2368 2369 return (ch->spd); 2370} 2371 2372static void 2373hdac_stream_setup(struct hdac_chan *ch) 2374{ 2375 struct hdac_softc *sc = ch->devinfo->codec->sc; 2376 int i; 2377 nid_t cad = ch->devinfo->codec->cad; 2378 uint16_t fmt; 2379 2380 fmt = 0; 2381 if (ch->fmt & AFMT_S16_LE) 2382 fmt |= ch->bit16 << 4; 2383 else if (ch->fmt & AFMT_S32_LE) 2384 fmt |= ch->bit32 << 4; 2385 else 2386 fmt |= 1 << 4; 2387 2388 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2389 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2390 fmt |= hda_rate_tab[i].base; 2391 fmt |= hda_rate_tab[i].mul; 2392 fmt |= hda_rate_tab[i].div; 2393 break; 2394 } 2395 } 2396 2397 if (ch->fmt & AFMT_STEREO) 2398 fmt |= 1; 2399 2400 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2401 2402 for (i = 0; ch->io[i] != -1; i++) { 2403 HDA_BOOTVERBOSE( 2404 device_printf(sc->dev, 2405 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2406 "fmt=0x%08x\n", 2407 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2408 ch->io[i], fmt); 2409 ); 2410 hdac_command(sc, 2411 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2412 hdac_command(sc, 2413 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2414 ch->sid << 4), cad); 2415 } 2416} 2417 2418static int 2419hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 2420{ 2421 struct hdac_chan *ch = data; 2422 2423 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz); 2424 2425 return (ch->blksz); 2426} 2427 2428static void 2429hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2430{ 2431 struct hdac_devinfo *devinfo = ch->devinfo; 2432 nid_t cad = devinfo->codec->cad; 2433 int i; 2434 2435 hdac_stream_stop(ch); 2436 2437 for (i = 0; ch->io[i] != -1; i++) { 2438 hdac_command(sc, 2439 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2440 0), cad); 2441 } 2442} 2443 2444static void 2445hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2446{ 2447 ch->ptr = 0; 2448 ch->prevptr = 0; 2449 hdac_stream_stop(ch); 2450 hdac_stream_reset(ch); 2451 hdac_bdl_setup(ch); 2452 hdac_stream_setid(ch); 2453 hdac_stream_setup(ch); 2454 hdac_stream_start(ch); 2455} 2456 2457static int 2458hdac_channel_trigger(kobj_t obj, void *data, int go) 2459{ 2460 struct hdac_chan *ch = data; 2461 struct hdac_softc *sc = ch->devinfo->codec->sc; 2462 2463 hdac_lock(sc); 2464 switch (go) { 2465 case PCMTRIG_START: 2466 hdac_channel_start(sc, ch); 2467 break; 2468 case PCMTRIG_STOP: 2469 case PCMTRIG_ABORT: 2470 hdac_channel_stop(sc, ch); 2471 break; 2472 } 2473 hdac_unlock(sc); 2474 2475 return (0); 2476} 2477 2478static int 2479hdac_channel_getptr(kobj_t obj, void *data) 2480{ 2481 struct hdac_chan *ch = data; 2482 struct hdac_softc *sc = ch->devinfo->codec->sc; 2483 int sz, delta; 2484 uint32_t ptr; 2485 2486 hdac_lock(sc); 2487 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2488 hdac_unlock(sc); 2489 2490 sz = sndbuf_getsize(ch->b); 2491 ptr %= sz; 2492 2493 if (ch->dir == PCMDIR_REC) { 2494 delta = ptr % sndbuf_getblksz(ch->b); 2495 if (delta != 0) { 2496 ptr -= delta; 2497 if (ptr < delta) 2498 ptr = sz - delta; 2499 else 2500 ptr -= delta; 2501 } 2502 } 2503 2504 return (ptr); 2505} 2506 2507static struct pcmchan_caps * 2508hdac_channel_getcaps(kobj_t obj, void *data) 2509{ 2510 return (&((struct hdac_chan *)data)->caps); 2511} 2512 2513static kobj_method_t hdac_channel_methods[] = { 2514 KOBJMETHOD(channel_init, hdac_channel_init), 2515 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2516 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2517 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2518 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2519 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2520 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2521 { 0, 0 } 2522}; 2523CHANNEL_DECLARE(hdac_channel); 2524 2525static int 2526hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2527{ 2528 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2529 struct hdac_softc *sc = devinfo->codec->sc; 2530 struct hdac_widget *w, *cw; 2531 struct hdac_audio_ctl *ctl; 2532 uint32_t mask, recmask, id; 2533 int i, j, softpcmvol; 2534 nid_t cad; 2535 2536 hdac_lock(sc); 2537 2538 mask = 0; 2539 recmask = 0; 2540 2541 id = hdac_codec_id(devinfo); 2542 cad = devinfo->codec->cad; 2543 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2544 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2545 sc->pci_subvendor) && 2546 hdac_hp_switch[i].id == id)) 2547 continue; 2548 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2549 if (w != NULL && w->enable != 0 2550 && w->type == 2551 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2552 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2553 hdac_command(sc, 2554 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2555 w->nid, 2556 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2557 HDAC_UNSOLTAG_EVENT_HP), cad); 2558 hdac_hp_switch_handler(devinfo); 2559 HDA_BOOTVERBOSE( 2560 device_printf(sc->dev, 2561 "HDA_DEBUG: Enabling headphone/speaker " 2562 "audio routing switching:\n"); 2563 device_printf(sc->dev, 2564 "HDA_DEBUG: \tindex=%d nid=%d " 2565 "pci_subvendor=0x%08x " 2566 "codec=0x%08x\n", 2567 i, w->nid, sc->pci_subvendor, id); 2568 ); 2569 } 2570 break; 2571 } 2572 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2573 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2574 sc->pci_subvendor) && 2575 hdac_eapd_switch[i].id == id)) 2576 continue; 2577 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2578 if (w == NULL || w->enable == 0) 2579 break; 2580 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2581 w->param.eapdbtl == HDAC_INVALID) 2582 break; 2583 mask |= SOUND_MASK_OGAIN; 2584 break; 2585 } 2586 2587 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2588 w = hdac_widget_get(devinfo, i); 2589 if (w == NULL || w->enable == 0) 2590 continue; 2591 mask |= w->ctlflags; 2592 if (!(w->pflags & HDA_ADC_RECSEL)) 2593 continue; 2594 for (j = 0; j < w->nconns; j++) { 2595 cw = hdac_widget_get(devinfo, w->conns[j]); 2596 if (cw == NULL || cw->enable == 0) 2597 continue; 2598 recmask |= cw->ctlflags; 2599 } 2600 } 2601 2602 if (!(mask & SOUND_MASK_PCM)) { 2603 softpcmvol = 1; 2604 mask |= SOUND_MASK_PCM; 2605 } else 2606 softpcmvol = (devinfo->function.audio.quirks & 2607 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2608 2609 i = 0; 2610 ctl = NULL; 2611 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2612 if (ctl->widget == NULL || ctl->enable == 0) 2613 continue; 2614 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2615 continue; 2616 if (ctl->step > 0) 2617 break; 2618 } 2619 2620 if (softpcmvol == 1 || ctl == NULL) { 2621 struct snddev_info *d = NULL; 2622 d = device_get_softc(sc->dev); 2623 if (d != NULL) { 2624 d->flags |= SD_F_SOFTPCMVOL; 2625 HDA_BOOTVERBOSE( 2626 device_printf(sc->dev, 2627 "HDA_DEBUG: %s Soft PCM volume\n", 2628 (softpcmvol == 1) ? 2629 "Forcing" : "Enabling"); 2630 ); 2631 } 2632 i = 0; 2633 /* 2634 * XXX Temporary quirk for STAC9220, until the parser 2635 * become smarter. 2636 */ 2637 if (id == HDA_CODEC_STAC9220) { 2638 mask |= SOUND_MASK_VOLUME; 2639 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2640 NULL) { 2641 if (ctl->widget == NULL || ctl->enable == 0) 2642 continue; 2643 if (ctl->widget->nid == 11 && ctl->index == 0) { 2644 ctl->ossmask = SOUND_MASK_VOLUME; 2645 ctl->ossval = 100 | (100 << 8); 2646 } else 2647 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2648 } 2649 } else { 2650 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2651 SOUND_MASK_PCM); 2652 if (!(mask & SOUND_MASK_VOLUME)) 2653 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2654 SOUND_MIXER_NONE); 2655 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2656 NULL) { 2657 if (ctl->widget == NULL || ctl->enable == 0) 2658 continue; 2659 if (!HDA_FLAG_MATCH(ctl->ossmask, 2660 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2661 continue; 2662 if (!(ctl->mute == 1 && ctl->step == 0)) 2663 ctl->enable = 0; 2664 } 2665 } 2666 } 2667 2668 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2669 2670 mix_setrecdevs(m, recmask); 2671 mix_setdevs(m, mask); 2672 2673 hdac_unlock(sc); 2674 2675 return (0); 2676} 2677 2678static int 2679hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2680 unsigned left, unsigned right) 2681{ 2682 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2683 struct hdac_softc *sc = devinfo->codec->sc; 2684 struct hdac_widget *w; 2685 struct hdac_audio_ctl *ctl; 2686 uint32_t id, mute; 2687 int lvol, rvol, mlvol, mrvol; 2688 int i = 0; 2689 2690 hdac_lock(sc); 2691 if (dev == SOUND_MIXER_OGAIN) { 2692 uint32_t orig; 2693 /*if (left != right || !(left == 0 || left == 1)) { 2694 hdac_unlock(sc); 2695 return (-1); 2696 }*/ 2697 id = hdac_codec_id(devinfo); 2698 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2699 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2700 sc->pci_subvendor) && 2701 hdac_eapd_switch[i].id == id) 2702 break; 2703 } 2704 if (i >= HDAC_EAPD_SWITCH_LEN) { 2705 hdac_unlock(sc); 2706 return (-1); 2707 } 2708 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2709 if (w == NULL || 2710 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2711 w->param.eapdbtl == HDAC_INVALID) { 2712 hdac_unlock(sc); 2713 return (-1); 2714 } 2715 orig = w->param.eapdbtl; 2716 if (left == 0) 2717 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2718 else 2719 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2720 if (orig != w->param.eapdbtl) { 2721 uint32_t val; 2722 2723 if (hdac_eapd_switch[i].hp_switch != 0) 2724 hdac_hp_switch_handler(devinfo); 2725 val = w->param.eapdbtl; 2726 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2727 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2728 hdac_command(sc, 2729 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2730 w->nid, val), devinfo->codec->cad); 2731 } 2732 hdac_unlock(sc); 2733 return (left | (left << 8)); 2734 } 2735 if (dev == SOUND_MIXER_VOLUME) 2736 devinfo->function.audio.mvol = left | (right << 8); 2737 2738 mlvol = devinfo->function.audio.mvol & 0x7f; 2739 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2740 lvol = 0; 2741 rvol = 0; 2742 2743 i = 0; 2744 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2745 if (ctl->widget == NULL || ctl->enable == 0 || 2746 !(ctl->ossmask & (1 << dev))) 2747 continue; 2748 switch (dev) { 2749 case SOUND_MIXER_VOLUME: 2750 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2751 lvol = (lvol * ctl->step) / 100; 2752 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2753 rvol = (rvol * ctl->step) / 100; 2754 break; 2755 default: 2756 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2757 lvol = (left * mlvol) / 100; 2758 lvol = (lvol * ctl->step) / 100; 2759 rvol = (right * mrvol) / 100; 2760 rvol = (rvol * ctl->step) / 100; 2761 } else { 2762 lvol = (left * ctl->step) / 100; 2763 rvol = (right * ctl->step) / 100; 2764 } 2765 ctl->ossval = left | (right << 8); 2766 break; 2767 } 2768 mute = 0; 2769 if (ctl->step < 1) { 2770 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2771 (ctl->muted & HDA_AMP_MUTE_LEFT); 2772 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2773 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2774 } else { 2775 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2776 (ctl->muted & HDA_AMP_MUTE_LEFT); 2777 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2778 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2779 } 2780 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2781 } 2782 hdac_unlock(sc); 2783 2784 return (left | (right << 8)); 2785} 2786 2787static int 2788hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2789{ 2790 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2791 struct hdac_widget *w, *cw; 2792 struct hdac_softc *sc = devinfo->codec->sc; 2793 uint32_t ret = src, target; 2794 int i, j; 2795 2796 target = 0; 2797 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2798 if (src & (1 << i)) { 2799 target = 1 << i; 2800 break; 2801 } 2802 } 2803 2804 hdac_lock(sc); 2805 2806 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2807 w = hdac_widget_get(devinfo, i); 2808 if (w == NULL || w->enable == 0) 2809 continue; 2810 if (!(w->pflags & HDA_ADC_RECSEL)) 2811 continue; 2812 for (j = 0; j < w->nconns; j++) { 2813 cw = hdac_widget_get(devinfo, w->conns[j]); 2814 if (cw == NULL || cw->enable == 0) 2815 continue; 2816 if ((target == SOUND_MASK_VOLUME && 2817 cw->type != 2818 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 2819 (target != SOUND_MASK_VOLUME && 2820 cw->type == 2821 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 2822 continue; 2823 if (cw->ctlflags & target) { 2824 hdac_widget_connection_select(w, j); 2825 ret = target; 2826 j += w->nconns; 2827 } 2828 } 2829 } 2830 2831 hdac_unlock(sc); 2832 2833 return (ret); 2834} 2835 2836static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 2837 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 2838 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 2839 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 2840 { 0, 0 } 2841}; 2842MIXER_DECLARE(hdac_audio_ctl_ossmixer); 2843 2844/**************************************************************************** 2845 * int hdac_attach(device_t) 2846 * 2847 * Attach the device into the kernel. Interrupts usually won't be enabled 2848 * when this function is called. Setup everything that doesn't require 2849 * interrupts and defer probing of codecs until interrupts are enabled. 2850 ****************************************************************************/ 2851static int 2852hdac_attach(device_t dev) 2853{ 2854 struct hdac_softc *sc; 2855 int result; 2856 int i = 0; 2857 2858 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 2859 if (sc == NULL) { 2860 device_printf(dev, "cannot allocate softc\n"); 2861 return (ENOMEM); 2862 } 2863 2864 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 2865 if (sc->lock == NULL) { 2866 device_printf(dev, "mutex creation failed\n"); 2867 free(sc, M_DEVBUF); 2868 return (ENOMEM); 2869 } 2870 2871 sc->dev = dev; 2872 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 2873 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 2874 2875 sc->chan_size = pcm_getbuffersize(dev, 2876 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT); 2877 if (resource_int_value(device_get_name(sc->dev), 2878 device_get_unit(sc->dev), "blocksize", &i) == 0 && 2879 i > 0) { 2880 sc->chan_blkcnt = sc->chan_size / i; 2881 i = 0; 2882 while (sc->chan_blkcnt >> i) 2883 i++; 2884 sc->chan_blkcnt = 1 << (i - 1); 2885 if (sc->chan_blkcnt < HDA_BDL_MIN) 2886 sc->chan_blkcnt = HDA_BDL_MIN; 2887 else if (sc->chan_blkcnt > HDA_BDL_MAX) 2888 sc->chan_blkcnt = HDA_BDL_MAX; 2889 } else 2890 sc->chan_blkcnt = HDA_BDL_DEFAULT; 2891 2892 result = bus_dma_tag_create(NULL, /* parent */ 2893 HDAC_DMA_ALIGNMENT, /* alignment */ 2894 0, /* boundary */ 2895 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2896 BUS_SPACE_MAXADDR, /* highaddr */ 2897 NULL, /* filtfunc */ 2898 NULL, /* fistfuncarg */ 2899 sc->chan_size, /* maxsize */ 2900 1, /* nsegments */ 2901 sc->chan_size, /* maxsegsz */ 2902 0, /* flags */ 2903 NULL, /* lockfunc */ 2904 NULL, /* lockfuncarg */ 2905 &sc->chan_dmat); /* dmat */ 2906 if (result != 0) { 2907 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 2908 __func__, result); 2909 snd_mtxfree(sc->lock); 2910 free(sc, M_DEVBUF); 2911 return (ENXIO); 2912 } 2913 2914 2915 sc->hdabus = NULL; 2916 for (i = 0; i < HDAC_CODEC_MAX; i++) 2917 sc->codecs[i] = NULL; 2918 2919 pci_enable_busmaster(dev); 2920 2921 /* Allocate resources */ 2922 result = hdac_mem_alloc(sc); 2923 if (result != 0) 2924 goto hdac_attach_fail; 2925 result = hdac_irq_alloc(sc); 2926 if (result != 0) 2927 goto hdac_attach_fail; 2928 2929 /* Get Capabilities */ 2930 result = hdac_get_capabilities(sc); 2931 if (result != 0) 2932 goto hdac_attach_fail; 2933 2934 /* Allocate CORB and RIRB dma memory */ 2935 result = hdac_dma_alloc(sc, &sc->corb_dma, 2936 sc->corb_size * sizeof(uint32_t)); 2937 if (result != 0) 2938 goto hdac_attach_fail; 2939 result = hdac_dma_alloc(sc, &sc->rirb_dma, 2940 sc->rirb_size * sizeof(struct hdac_rirb)); 2941 if (result != 0) 2942 goto hdac_attach_fail; 2943 2944 /* Quiesce everything */ 2945 hdac_reset(sc); 2946 2947 /* Disable PCI-Express QOS */ 2948 pci_write_config(sc->dev, 0x44, 2949 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 2950 2951 /* Initialize the CORB and RIRB */ 2952 hdac_corb_init(sc); 2953 hdac_rirb_init(sc); 2954 2955 /* Defer remaining of initialization until interrupts are enabled */ 2956 sc->intrhook.ich_func = hdac_attach2; 2957 sc->intrhook.ich_arg = (void *)sc; 2958 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 2959 sc->intrhook.ich_func = NULL; 2960 hdac_attach2((void *)sc); 2961 } 2962 2963 return (0); 2964 2965hdac_attach_fail: 2966 hdac_dma_free(&sc->rirb_dma); 2967 hdac_dma_free(&sc->corb_dma); 2968 hdac_irq_free(sc); 2969 hdac_mem_free(sc); 2970 snd_mtxfree(sc->lock); 2971 free(sc, M_DEVBUF); 2972 2973 return (ENXIO); 2974} 2975 2976static void 2977hdac_audio_parse(struct hdac_devinfo *devinfo) 2978{ 2979 struct hdac_softc *sc = devinfo->codec->sc; 2980 struct hdac_widget *w; 2981 uint32_t res; 2982 int i; 2983 nid_t cad, nid; 2984 2985 cad = devinfo->codec->cad; 2986 nid = devinfo->nid; 2987 2988 hdac_command(sc, 2989 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 2990 2991 DELAY(100); 2992 2993 res = hdac_command(sc, 2994 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2995 2996 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2997 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2998 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2999 3000 HDA_BOOTVERBOSE( 3001 device_printf(sc->dev, " Vendor: 0x%08x\n", 3002 devinfo->vendor_id); 3003 device_printf(sc->dev, " Device: 0x%08x\n", 3004 devinfo->device_id); 3005 device_printf(sc->dev, " Revision: 0x%08x\n", 3006 devinfo->revision_id); 3007 device_printf(sc->dev, " Stepping: 0x%08x\n", 3008 devinfo->stepping_id); 3009 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3010 sc->pci_subvendor); 3011 device_printf(sc->dev, " Nodes: start=%d " 3012 "endnode=%d total=%d\n", 3013 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3014 ); 3015 3016 res = hdac_command(sc, 3017 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3018 cad); 3019 devinfo->function.audio.supp_stream_formats = res; 3020 3021 res = hdac_command(sc, 3022 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3023 cad); 3024 devinfo->function.audio.supp_pcm_size_rate = res; 3025 3026 res = hdac_command(sc, 3027 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3028 cad); 3029 devinfo->function.audio.outamp_cap = res; 3030 3031 res = hdac_command(sc, 3032 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3033 cad); 3034 devinfo->function.audio.inamp_cap = res; 3035 3036 if (devinfo->nodecnt > 0) { 3037 hdac_unlock(sc); 3038 devinfo->widget = (struct hdac_widget *)malloc( 3039 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3040 M_NOWAIT | M_ZERO); 3041 hdac_lock(sc); 3042 } else 3043 devinfo->widget = NULL; 3044 3045 if (devinfo->widget == NULL) { 3046 device_printf(sc->dev, "unable to allocate widgets!\n"); 3047 devinfo->endnode = devinfo->startnode; 3048 devinfo->nodecnt = 0; 3049 return; 3050 } 3051 3052 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3053 w = hdac_widget_get(devinfo, i); 3054 if (w == NULL) 3055 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3056 else { 3057 w->devinfo = devinfo; 3058 w->nid = i; 3059 w->enable = 1; 3060 w->selconn = -1; 3061 w->pflags = 0; 3062 w->ctlflags = 0; 3063 w->param.eapdbtl = HDAC_INVALID; 3064 hdac_widget_parse(w); 3065 } 3066 } 3067} 3068 3069static void 3070hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3071{ 3072 struct hdac_softc *sc = devinfo->codec->sc; 3073 struct hdac_audio_ctl *ctls; 3074 struct hdac_widget *w, *cw; 3075 int i, j, cnt, max, ocap, icap; 3076 int mute, offset, step, size; 3077 3078 /* XXX This is redundant */ 3079 max = 0; 3080 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3081 w = hdac_widget_get(devinfo, i); 3082 if (w == NULL || w->enable == 0) 3083 continue; 3084 if (w->param.outamp_cap != 0) 3085 max++; 3086 if (w->param.inamp_cap != 0) { 3087 switch (w->type) { 3088 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3089 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3090 for (j = 0; j < w->nconns; j++) { 3091 cw = hdac_widget_get(devinfo, 3092 w->conns[j]); 3093 if (cw == NULL || cw->enable == 0) 3094 continue; 3095 max++; 3096 } 3097 break; 3098 default: 3099 max++; 3100 break; 3101 } 3102 } 3103 } 3104 3105 devinfo->function.audio.ctlcnt = max; 3106 3107 if (max < 1) 3108 return; 3109 3110 hdac_unlock(sc); 3111 ctls = (struct hdac_audio_ctl *)malloc( 3112 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3113 hdac_lock(sc); 3114 3115 if (ctls == NULL) { 3116 /* Blekh! */ 3117 device_printf(sc->dev, "unable to allocate ctls!\n"); 3118 devinfo->function.audio.ctlcnt = 0; 3119 return; 3120 } 3121 3122 cnt = 0; 3123 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3124 if (cnt >= max) { 3125 device_printf(sc->dev, "%s: Ctl overflow!\n", 3126 __func__); 3127 break; 3128 } 3129 w = hdac_widget_get(devinfo, i); 3130 if (w == NULL || w->enable == 0) 3131 continue; 3132 ocap = w->param.outamp_cap; 3133 icap = w->param.inamp_cap; 3134 if (ocap != 0) { 3135 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3136 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3137 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3138 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3139 /*if (offset > step) { 3140 HDA_BOOTVERBOSE( 3141 device_printf(sc->dev, 3142 "HDA_DEBUG: BUGGY outamp: nid=%d " 3143 "[offset=%d > step=%d]\n", 3144 w->nid, offset, step); 3145 ); 3146 offset = step; 3147 }*/ 3148 ctls[cnt].enable = 1; 3149 ctls[cnt].widget = w; 3150 ctls[cnt].mute = mute; 3151 ctls[cnt].step = step; 3152 ctls[cnt].size = size; 3153 ctls[cnt].offset = offset; 3154 ctls[cnt].left = offset; 3155 ctls[cnt].right = offset; 3156 ctls[cnt++].dir = HDA_CTL_OUT; 3157 } 3158 3159 if (icap != 0) { 3160 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3161 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3162 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3163 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3164 /*if (offset > step) { 3165 HDA_BOOTVERBOSE( 3166 device_printf(sc->dev, 3167 "HDA_DEBUG: BUGGY inamp: nid=%d " 3168 "[offset=%d > step=%d]\n", 3169 w->nid, offset, step); 3170 ); 3171 offset = step; 3172 }*/ 3173 switch (w->type) { 3174 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3175 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3176 for (j = 0; j < w->nconns; j++) { 3177 if (cnt >= max) { 3178 device_printf(sc->dev, 3179 "%s: Ctl overflow!\n", 3180 __func__); 3181 break; 3182 } 3183 cw = hdac_widget_get(devinfo, 3184 w->conns[j]); 3185 if (cw == NULL || cw->enable == 0) 3186 continue; 3187 ctls[cnt].enable = 1; 3188 ctls[cnt].widget = w; 3189 ctls[cnt].childwidget = cw; 3190 ctls[cnt].index = j; 3191 ctls[cnt].mute = mute; 3192 ctls[cnt].step = step; 3193 ctls[cnt].size = size; 3194 ctls[cnt].offset = offset; 3195 ctls[cnt].left = offset; 3196 ctls[cnt].right = offset; 3197 ctls[cnt++].dir = HDA_CTL_IN; 3198 } 3199 break; 3200 default: 3201 if (cnt >= max) { 3202 device_printf(sc->dev, 3203 "%s: Ctl overflow!\n", 3204 __func__); 3205 break; 3206 } 3207 ctls[cnt].enable = 1; 3208 ctls[cnt].widget = w; 3209 ctls[cnt].mute = mute; 3210 ctls[cnt].step = step; 3211 ctls[cnt].size = size; 3212 ctls[cnt].offset = offset; 3213 ctls[cnt].left = offset; 3214 ctls[cnt].right = offset; 3215 ctls[cnt++].dir = HDA_CTL_IN; 3216 break; 3217 } 3218 } 3219 } 3220 3221 devinfo->function.audio.ctl = ctls; 3222} 3223 3224static const struct { 3225 uint32_t model; 3226 uint32_t id; 3227 uint32_t set, unset; 3228} hdac_quirks[] = { 3229 /* 3230 * XXX Fixed rate quirk. Other than 48000 3231 * sounds pretty much like train wreck. 3232 * 3233 * XXX Force stereo quirk. Monoural recording / playback 3234 * on few codecs (especially ALC880) seems broken or 3235 * perhaps unsupported. 3236 */ 3237 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3238 HDA_QUIRK_FIXEDRATE | HDA_QUIRK_FORCESTEREO, 0 }, 3239 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3240 HDA_QUIRK_GPIO1, 0 }, 3241 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3242 HDA_QUIRK_GPIO1, 0 }, 3243 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3244 HDA_QUIRK_EAPDINV, 0 }, 3245 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3246 HDA_QUIRK_EAPDINV, 0 }, 3247 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3248 0, HDA_QUIRK_FORCESTEREO }, 3249 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3250 HDA_QUIRK_SOFTPCMVOL, 0 } 3251}; 3252#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3253 3254static void 3255hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3256{ 3257 struct hdac_widget *w; 3258 uint32_t id, subvendor; 3259 int i; 3260 3261 id = hdac_codec_id(devinfo); 3262 subvendor = devinfo->codec->sc->pci_subvendor; 3263 3264 /* 3265 * Quirks 3266 */ 3267 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3268 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3269 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3270 continue; 3271 if (hdac_quirks[i].set != 0) 3272 devinfo->function.audio.quirks |= 3273 hdac_quirks[i].set; 3274 if (hdac_quirks[i].unset != 0) 3275 devinfo->function.audio.quirks &= 3276 ~(hdac_quirks[i].unset); 3277 } 3278 3279 switch (id) { 3280 case HDA_CODEC_ALC260: 3281 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3282 w = hdac_widget_get(devinfo, i); 3283 if (w == NULL || w->enable == 0) 3284 continue; 3285 if (w->type != 3286 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3287 continue; 3288 if (w->nid != 5) 3289 w->enable = 0; 3290 } 3291 break; 3292 case HDA_CODEC_ALC880: 3293 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3294 w = hdac_widget_get(devinfo, i); 3295 if (w == NULL || w->enable == 0) 3296 continue; 3297 if (w->type == 3298 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3299 w->nid != 9 && w->nid != 29) { 3300 w->enable = 0; 3301 } else if (w->type != 3302 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3303 w->nid == 29) { 3304 w->type = 3305 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3306 w->param.widget_cap &= 3307 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3308 w->param.widget_cap |= 3309 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3310 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3311 strlcpy(w->name, "beep widget", sizeof(w->name)); 3312 } 3313 } 3314 break; 3315 case HDA_CODEC_AD1981HD: 3316 w = hdac_widget_get(devinfo, 11); 3317 if (w != NULL && w->enable != 0 && w->nconns > 3) 3318 w->selconn = 3; 3319 if (subvendor == IBM_M52_SUBVENDOR) { 3320 struct hdac_audio_ctl *ctl; 3321 3322 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3323 if (ctl != NULL) 3324 ctl->ossmask = SOUND_MASK_SPEAKER; 3325 } 3326 break; 3327 case HDA_CODEC_AD1986A: 3328 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3329 w = hdac_widget_get(devinfo, i); 3330 if (w == NULL || w->enable == 0) 3331 continue; 3332 if (w->type != 3333 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3334 continue; 3335 if (w->nid != 3) 3336 w->enable = 0; 3337 } 3338 break; 3339 case HDA_CODEC_STAC9221: 3340 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3341 w = hdac_widget_get(devinfo, i); 3342 if (w == NULL || w->enable == 0) 3343 continue; 3344 if (w->type != 3345 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3346 continue; 3347 if (w->nid != 2) 3348 w->enable = 0; 3349 } 3350 break; 3351 case HDA_CODEC_STAC9221D: 3352 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3353 w = hdac_widget_get(devinfo, i); 3354 if (w == NULL || w->enable == 0) 3355 continue; 3356 if (w->type == 3357 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3358 w->nid != 6) 3359 w->enable = 0; 3360 3361 } 3362 break; 3363 default: 3364 break; 3365 } 3366} 3367 3368static int 3369hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3370{ 3371 int *dev = &devinfo->function.audio.ossidx; 3372 3373 while (*dev < SOUND_MIXER_NRDEVICES) { 3374 switch (*dev) { 3375 case SOUND_MIXER_VOLUME: 3376 case SOUND_MIXER_BASS: 3377 case SOUND_MIXER_TREBLE: 3378 case SOUND_MIXER_PCM: 3379 case SOUND_MIXER_SPEAKER: 3380 case SOUND_MIXER_LINE: 3381 case SOUND_MIXER_MIC: 3382 case SOUND_MIXER_CD: 3383 case SOUND_MIXER_RECLEV: 3384 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3385 (*dev)++; 3386 break; 3387 default: 3388 return (*dev)++; 3389 break; 3390 } 3391 } 3392 3393 return (-1); 3394} 3395 3396static int 3397hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3398{ 3399 struct hdac_widget *w; 3400 int i, ret = 0; 3401 3402 if (depth > HDA_PARSE_MAXDEPTH) 3403 return (0); 3404 w = hdac_widget_get(devinfo, nid); 3405 if (w == NULL || w->enable == 0) 3406 return (0); 3407 switch (w->type) { 3408 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3409 w->pflags |= HDA_DAC_PATH; 3410 ret = 1; 3411 break; 3412 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3413 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3414 for (i = 0; i < w->nconns; i++) { 3415 if (hdac_widget_find_dac_path(devinfo, 3416 w->conns[i], depth + 1) != 0) { 3417 if (w->selconn == -1) 3418 w->selconn = i; 3419 ret = 1; 3420 w->pflags |= HDA_DAC_PATH; 3421 } 3422 } 3423 break; 3424 default: 3425 break; 3426 } 3427 return (ret); 3428} 3429 3430static int 3431hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3432{ 3433 struct hdac_widget *w; 3434 int i, conndev, ret = 0; 3435 3436 if (depth > HDA_PARSE_MAXDEPTH) 3437 return (0); 3438 w = hdac_widget_get(devinfo, nid); 3439 if (w == NULL || w->enable == 0) 3440 return (0); 3441 switch (w->type) { 3442 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3443 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3444 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3445 for (i = 0; i < w->nconns; i++) { 3446 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3447 depth + 1) != 0) { 3448 if (w->selconn == -1) 3449 w->selconn = i; 3450 w->pflags |= HDA_ADC_PATH; 3451 ret = 1; 3452 } 3453 } 3454 break; 3455 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3456 conndev = w->wclass.pin.config & 3457 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3458 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3459 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3460 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3461 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3462 w->pflags |= HDA_ADC_PATH; 3463 ret = 1; 3464 } 3465 break; 3466 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3467 if (w->pflags & HDA_DAC_PATH) { 3468 w->pflags |= HDA_ADC_PATH; 3469 ret = 1; 3470 } 3471 break;*/ 3472 default: 3473 break; 3474 } 3475 return (ret); 3476} 3477 3478static uint32_t 3479hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3480 nid_t nid, nid_t pnid, int index, int depth) 3481{ 3482 struct hdac_widget *w, *pw; 3483 struct hdac_audio_ctl *ctl; 3484 uint32_t fl = 0; 3485 int i, ossdev, conndev, strategy; 3486 3487 if (depth > HDA_PARSE_MAXDEPTH) 3488 return (0); 3489 3490 w = hdac_widget_get(devinfo, nid); 3491 if (w == NULL || w->enable == 0) 3492 return (0); 3493 3494 pw = hdac_widget_get(devinfo, pnid); 3495 strategy = devinfo->function.audio.parsing_strategy; 3496 3497 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3498 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3499 for (i = 0; i < w->nconns; i++) { 3500 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3501 w->nid, i, depth + 1); 3502 } 3503 w->ctlflags |= fl; 3504 return (fl); 3505 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3506 (w->pflags & HDA_DAC_PATH)) { 3507 i = 0; 3508 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3509 if (ctl->enable == 0 || ctl->widget == NULL) 3510 continue; 3511 /* XXX This should be compressed! */ 3512 if ((ctl->widget->nid == w->nid) || 3513 (ctl->widget->nid == pnid && ctl->index == index && 3514 (ctl->dir & HDA_CTL_IN)) || 3515 (ctl->widget->nid == pnid && pw != NULL && 3516 pw->type == 3517 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3518 (pw->nconns < 2 || pw->selconn == index || 3519 pw->selconn == -1) && 3520 (ctl->dir & HDA_CTL_OUT)) || 3521 (strategy == HDA_PARSE_DIRECT && 3522 ctl->widget->nid == w->nid)) { 3523 /*if (pw != NULL && pw->selconn == -1) 3524 pw->selconn = index; 3525 fl |= SOUND_MASK_VOLUME; 3526 fl |= SOUND_MASK_PCM; 3527 ctl->ossmask |= SOUND_MASK_VOLUME; 3528 ctl->ossmask |= SOUND_MASK_PCM; 3529 ctl->ossdev = SOUND_MIXER_PCM;*/ 3530 if (!(w->ctlflags & SOUND_MASK_PCM) || 3531 (pw != NULL && 3532 !(pw->ctlflags & SOUND_MASK_PCM))) { 3533 fl |= SOUND_MASK_VOLUME; 3534 fl |= SOUND_MASK_PCM; 3535 ctl->ossmask |= SOUND_MASK_VOLUME; 3536 ctl->ossmask |= SOUND_MASK_PCM; 3537 ctl->ossdev = SOUND_MIXER_PCM; 3538 w->ctlflags |= SOUND_MASK_VOLUME; 3539 w->ctlflags |= SOUND_MASK_PCM; 3540 if (pw != NULL) { 3541 if (pw->selconn == -1) 3542 pw->selconn = index; 3543 pw->ctlflags |= 3544 SOUND_MASK_VOLUME; 3545 pw->ctlflags |= 3546 SOUND_MASK_PCM; 3547 } 3548 } 3549 } 3550 } 3551 w->ctlflags |= fl; 3552 return (fl); 3553 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 3554 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3555 (w->pflags & HDA_ADC_PATH)) { 3556 conndev = w->wclass.pin.config & 3557 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3558 i = 0; 3559 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3560 if (ctl->enable == 0 || ctl->widget == NULL) 3561 continue; 3562 /* XXX This should be compressed! */ 3563 if (((ctl->widget->nid == pnid && ctl->index == index && 3564 (ctl->dir & HDA_CTL_IN)) || 3565 (ctl->widget->nid == pnid && pw != NULL && 3566 pw->type == 3567 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3568 (pw->nconns < 2 || pw->selconn == index || 3569 pw->selconn == -1) && 3570 (ctl->dir & HDA_CTL_OUT)) || 3571 (strategy == HDA_PARSE_DIRECT && 3572 ctl->widget->nid == w->nid)) && 3573 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3574 if (pw != NULL && pw->selconn == -1) 3575 pw->selconn = index; 3576 ossdev = 0; 3577 switch (conndev) { 3578 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3579 ossdev = SOUND_MIXER_MIC; 3580 break; 3581 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3582 ossdev = SOUND_MIXER_LINE; 3583 break; 3584 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3585 ossdev = SOUND_MIXER_CD; 3586 break; 3587 default: 3588 ossdev = 3589 hdac_audio_ctl_ossmixer_getnextdev( 3590 devinfo); 3591 if (ossdev < 0) 3592 ossdev = 0; 3593 break; 3594 } 3595 if (strategy == HDA_PARSE_MIXER) { 3596 fl |= SOUND_MASK_VOLUME; 3597 ctl->ossmask |= SOUND_MASK_VOLUME; 3598 } 3599 fl |= 1 << ossdev; 3600 ctl->ossmask |= 1 << ossdev; 3601 ctl->ossdev = ossdev; 3602 } 3603 } 3604 w->ctlflags |= fl; 3605 return (fl); 3606 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3607 i = 0; 3608 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3609 if (ctl->enable == 0 || ctl->widget == NULL) 3610 continue; 3611 /* XXX This should be compressed! */ 3612 if (((ctl->widget->nid == pnid && ctl->index == index && 3613 (ctl->dir & HDA_CTL_IN)) || 3614 (ctl->widget->nid == pnid && pw != NULL && 3615 pw->type == 3616 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3617 (pw->nconns < 2 || pw->selconn == index || 3618 pw->selconn == -1) && 3619 (ctl->dir & HDA_CTL_OUT)) || 3620 (strategy == HDA_PARSE_DIRECT && 3621 ctl->widget->nid == w->nid)) && 3622 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3623 if (pw != NULL && pw->selconn == -1) 3624 pw->selconn = index; 3625 fl |= SOUND_MASK_VOLUME; 3626 fl |= SOUND_MASK_SPEAKER; 3627 ctl->ossmask |= SOUND_MASK_VOLUME; 3628 ctl->ossmask |= SOUND_MASK_SPEAKER; 3629 ctl->ossdev = SOUND_MIXER_SPEAKER; 3630 } 3631 } 3632 w->ctlflags |= fl; 3633 return (fl); 3634 } 3635 return (0); 3636} 3637 3638static uint32_t 3639hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3640{ 3641 struct hdac_widget *w, *cw; 3642 struct hdac_audio_ctl *ctl; 3643 uint32_t fl; 3644 int i; 3645 3646 if (depth > HDA_PARSE_MAXDEPTH) 3647 return (0); 3648 3649 w = hdac_widget_get(devinfo, nid); 3650 if (w == NULL || w->enable == 0) 3651 return (0); 3652 /*if (!(w->pflags & HDA_ADC_PATH)) 3653 return (0); 3654 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3655 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3656 return (0);*/ 3657 i = 0; 3658 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3659 if (ctl->enable == 0 || ctl->widget == NULL) 3660 continue; 3661 if (ctl->widget->nid == nid) { 3662 ctl->ossmask |= SOUND_MASK_RECLEV; 3663 w->ctlflags |= SOUND_MASK_RECLEV; 3664 return (SOUND_MASK_RECLEV); 3665 } 3666 } 3667 for (i = 0; i < w->nconns; i++) { 3668 cw = hdac_widget_get(devinfo, w->conns[i]); 3669 if (cw == NULL || cw->enable == 0) 3670 continue; 3671 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3672 continue; 3673 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3674 if (fl != 0) { 3675 cw->ctlflags |= fl; 3676 w->ctlflags |= fl; 3677 return (fl); 3678 } 3679 } 3680 return (0); 3681} 3682 3683static int 3684hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3685{ 3686 struct hdac_widget *w, *cw; 3687 int i, child = 0; 3688 3689 if (depth > HDA_PARSE_MAXDEPTH) 3690 return (0); 3691 3692 w = hdac_widget_get(devinfo, nid); 3693 if (w == NULL || w->enable == 0) 3694 return (0); 3695 /*if (!(w->pflags & HDA_ADC_PATH)) 3696 return (0); 3697 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3698 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3699 return (0);*/ 3700 /* XXX weak! */ 3701 for (i = 0; i < w->nconns; i++) { 3702 cw = hdac_widget_get(devinfo, w->conns[i]); 3703 if (cw == NULL) 3704 continue; 3705 if (++child > 1) { 3706 w->pflags |= HDA_ADC_RECSEL; 3707 return (1); 3708 } 3709 } 3710 for (i = 0; i < w->nconns; i++) { 3711 if (hdac_audio_ctl_recsel_build(devinfo, 3712 w->conns[i], depth + 1) != 0) 3713 return (1); 3714 } 3715 return (0); 3716} 3717 3718static int 3719hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3720{ 3721 struct hdac_widget *w, *cw; 3722 int i, j, conndev, found_dac = 0; 3723 int strategy; 3724 3725 strategy = devinfo->function.audio.parsing_strategy; 3726 3727 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3728 w = hdac_widget_get(devinfo, i); 3729 if (w == NULL || w->enable == 0) 3730 continue; 3731 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3732 continue; 3733 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3734 continue; 3735 conndev = w->wclass.pin.config & 3736 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3737 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3738 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3739 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3740 continue; 3741 for (j = 0; j < w->nconns; j++) { 3742 cw = hdac_widget_get(devinfo, w->conns[j]); 3743 if (cw == NULL || cw->enable == 0) 3744 continue; 3745 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3746 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3747 cw->type == 3748 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3749 continue; 3750 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3751 != 0) { 3752 if (w->selconn == -1) 3753 w->selconn = j; 3754 w->pflags |= HDA_DAC_PATH; 3755 found_dac++; 3756 } 3757 } 3758 } 3759 3760 return (found_dac); 3761} 3762 3763static void 3764hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3765{ 3766 struct hdac_widget *w; 3767 struct hdac_audio_ctl *ctl; 3768 int i, j, dacs, strategy; 3769 3770 /* Construct DAC path */ 3771 strategy = HDA_PARSE_MIXER; 3772 devinfo->function.audio.parsing_strategy = strategy; 3773 HDA_BOOTVERBOSE( 3774 device_printf(devinfo->codec->sc->dev, 3775 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 3776 HDA_WIDGET_PARSER_REV); 3777 ); 3778 dacs = hdac_audio_build_tree_strategy(devinfo); 3779 if (dacs == 0) { 3780 HDA_BOOTVERBOSE( 3781 device_printf(devinfo->codec->sc->dev, 3782 "HDA_DEBUG: HWiP: 0 DAC path found! " 3783 "Retrying parser " 3784 "using HDA_PARSE_DIRECT strategy.\n"); 3785 ); 3786 strategy = HDA_PARSE_DIRECT; 3787 devinfo->function.audio.parsing_strategy = strategy; 3788 dacs = hdac_audio_build_tree_strategy(devinfo); 3789 } 3790 3791 HDA_BOOTVERBOSE( 3792 device_printf(devinfo->codec->sc->dev, 3793 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 3794 "strategy.\n", 3795 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 3796 ); 3797 3798 /* Construct ADC path */ 3799 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3800 w = hdac_widget_get(devinfo, i); 3801 if (w == NULL || w->enable == 0) 3802 continue; 3803 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3804 continue; 3805 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 3806 } 3807 3808 /* Output mixers */ 3809 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3810 w = hdac_widget_get(devinfo, i); 3811 if (w == NULL || w->enable == 0) 3812 continue; 3813 if ((strategy == HDA_PARSE_MIXER && 3814 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3815 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3816 && (w->pflags & HDA_DAC_PATH)) || 3817 (strategy == HDA_PARSE_DIRECT && (w->pflags & 3818 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 3819 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 3820 w->nid, devinfo->startnode - 1, 0, 0); 3821 } else if (w->type == 3822 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3823 j = 0; 3824 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 3825 NULL) { 3826 if (ctl->enable == 0 || ctl->widget == NULL) 3827 continue; 3828 if (ctl->widget->nid != w->nid) 3829 continue; 3830 ctl->ossmask |= SOUND_MASK_VOLUME; 3831 ctl->ossmask |= SOUND_MASK_SPEAKER; 3832 ctl->ossdev = SOUND_MIXER_SPEAKER; 3833 w->ctlflags |= SOUND_MASK_VOLUME; 3834 w->ctlflags |= SOUND_MASK_SPEAKER; 3835 } 3836 } 3837 } 3838 3839 /* Input mixers (rec) */ 3840 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3841 w = hdac_widget_get(devinfo, i); 3842 if (w == NULL || w->enable == 0) 3843 continue; 3844 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3845 w->pflags & HDA_ADC_PATH)) 3846 continue; 3847 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 3848 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 3849 } 3850} 3851 3852#define HDA_COMMIT_CONN (1 << 0) 3853#define HDA_COMMIT_CTRL (1 << 1) 3854#define HDA_COMMIT_EAPD (1 << 2) 3855#define HDA_COMMIT_GPIO (1 << 3) 3856#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 3857 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 3858 3859static void 3860hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 3861{ 3862 struct hdac_softc *sc = devinfo->codec->sc; 3863 struct hdac_widget *w; 3864 nid_t cad, nid; 3865 int i, gpioval; 3866 3867 if (!(cfl & HDA_COMMIT_ALL)) 3868 return; 3869 3870 cad = devinfo->codec->cad; 3871 3872 if (cfl & HDA_COMMIT_GPIO) { 3873 nid = devinfo->nid; 3874 for (i = 0; i < HDA_GPIO_MAX; i++) { 3875 if (!(devinfo->function.audio.quirks & (1 << i))) 3876 continue; 3877 gpioval = (1 << i) - 1; 3878 hdac_command(sc, 3879 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, gpioval), 3880 cad); 3881 hdac_command(sc, 3882 HDA_CMD_SET_GPIO_DIRECTION(cad, nid, gpioval), 3883 cad); 3884 hdac_command(sc, 3885 HDA_CMD_SET_GPIO_DATA(cad, nid, gpioval), 3886 cad); 3887 } 3888 } 3889 3890 for (i = 0; i < devinfo->nodecnt; i++) { 3891 w = &devinfo->widget[i]; 3892 if (w == NULL || w->enable == 0) 3893 continue; 3894 if (cfl & HDA_COMMIT_CONN) { 3895 if (w->selconn == -1) 3896 w->selconn = 0; 3897 if (w->nconns > 0) 3898 hdac_widget_connection_select(w, w->selconn); 3899 } 3900 if ((cfl & HDA_COMMIT_CTRL) && 3901 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 3902 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 3903 (HDA_DAC_PATH | HDA_ADC_PATH)) 3904 device_printf(sc->dev, "WARNING: node %d " 3905 "participate both for DAC/ADC!\n", w->nid); 3906 if (w->pflags & HDA_DAC_PATH) { 3907 w->wclass.pin.ctrl &= 3908 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 3909 if ((w->wclass.pin.config & 3910 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 3911 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 3912 w->wclass.pin.ctrl &= 3913 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 3914 } else if (w->pflags & HDA_ADC_PATH) { 3915 w->wclass.pin.ctrl &= 3916 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3917 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 3918 } else 3919 w->wclass.pin.ctrl &= ~( 3920 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 3921 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3922 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 3923 hdac_command(sc, 3924 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 3925 w->wclass.pin.ctrl), cad); 3926 } 3927 if ((cfl & HDA_COMMIT_EAPD) && 3928 w->param.eapdbtl != HDAC_INVALID) { 3929 uint32_t val; 3930 3931 val = w->param.eapdbtl; 3932 if (devinfo->function.audio.quirks & 3933 HDA_QUIRK_EAPDINV) 3934 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3935 hdac_command(sc, 3936 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 3937 val), cad); 3938 3939 } 3940 DELAY(1000); 3941 } 3942} 3943 3944static void 3945hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 3946{ 3947 struct hdac_softc *sc = devinfo->codec->sc; 3948 struct hdac_audio_ctl *ctl; 3949 int i; 3950 3951 devinfo->function.audio.mvol = 100 | (100 << 8); 3952 i = 0; 3953 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3954 if (ctl->enable == 0 || ctl->widget == NULL) { 3955 HDA_BOOTVERBOSE( 3956 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3957 i, (ctl->widget != NULL) ? 3958 ctl->widget->nid : -1); 3959 if (ctl->childwidget != NULL) 3960 printf(" childnid=%d", 3961 ctl->childwidget->nid); 3962 if (ctl->widget == NULL) 3963 printf(" NULL WIDGET!"); 3964 printf(" DISABLED\n"); 3965 ); 3966 continue; 3967 } 3968 HDA_BOOTVERBOSE( 3969 if (ctl->ossmask == 0) { 3970 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3971 i, ctl->widget->nid); 3972 if (ctl->childwidget != NULL) 3973 printf(" childnid=%d", 3974 ctl->childwidget->nid); 3975 printf(" Bind to NONE\n"); 3976 } 3977 ); 3978 if (ctl->step > 0) { 3979 ctl->ossval = (ctl->left * 100) / ctl->step; 3980 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 3981 } else 3982 ctl->ossval = 0; 3983 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 3984 ctl->left, ctl->right); 3985 } 3986} 3987 3988static int 3989hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 3990{ 3991 struct hdac_chan *ch; 3992 struct hdac_widget *w; 3993 uint32_t cap, fmtcap, pcmcap, path; 3994 int i, type, ret, max; 3995 3996 if (dir == PCMDIR_PLAY) { 3997 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 3998 ch = &devinfo->codec->sc->play; 3999 path = HDA_DAC_PATH; 4000 } else { 4001 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4002 ch = &devinfo->codec->sc->rec; 4003 path = HDA_ADC_PATH; 4004 } 4005 4006 ch->caps = hdac_caps; 4007 ch->caps.fmtlist = ch->fmtlist; 4008 ch->bit16 = 1; 4009 ch->bit32 = 0; 4010 ch->pcmrates[0] = 48000; 4011 ch->pcmrates[1] = 0; 4012 4013 ret = 0; 4014 fmtcap = devinfo->function.audio.supp_stream_formats; 4015 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4016 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4017 4018 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4019 w = hdac_widget_get(devinfo, i); 4020 if (w == NULL || w->enable == 0 || w->type != type || 4021 !(w->pflags & path)) 4022 continue; 4023 cap = w->param.widget_cap; 4024 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4025 continue;*/ 4026 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4027 continue; 4028 cap = w->param.supp_stream_formats; 4029 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4030 } 4031 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4032 }*/ 4033 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4034 continue; 4035 ch->io[ret++] = i; 4036 fmtcap &= w->param.supp_stream_formats; 4037 pcmcap &= w->param.supp_pcm_size_rate; 4038 } 4039 ch->io[ret] = -1; 4040 4041 ch->supp_stream_formats = fmtcap; 4042 ch->supp_pcm_size_rate = pcmcap; 4043 4044 /* 4045 * 8bit = 0 4046 * 16bit = 1 4047 * 20bit = 2 4048 * 24bit = 3 4049 * 32bit = 4 4050 */ 4051 if (ret > 0) { 4052 cap = pcmcap; 4053 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4054 ch->bit16 = 1; 4055 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4056 ch->bit16 = 0; 4057 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4058 ch->bit32 = 4; 4059 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4060 ch->bit32 = 3; 4061 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4062 ch->bit32 = 2; 4063 i = 0; 4064 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4065 ch->fmtlist[i++] = AFMT_S16_LE; 4066 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4067 if (ch->bit32 > 0) { 4068 if (!(devinfo->function.audio.quirks & 4069 HDA_QUIRK_FORCESTEREO)) 4070 ch->fmtlist[i++] = AFMT_S32_LE; 4071 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4072 } 4073 ch->fmtlist[i] = 0; 4074 i = 0; 4075 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4076 ch->pcmrates[i++] = 8000; 4077 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4078 ch->pcmrates[i++] = 11025; 4079 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4080 ch->pcmrates[i++] = 16000; 4081 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4082 ch->pcmrates[i++] = 22050; 4083 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4084 ch->pcmrates[i++] = 32000; 4085 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4086 ch->pcmrates[i++] = 44100; 4087 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4088 ch->pcmrates[i++] = 48000; 4089 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4090 ch->pcmrates[i++] = 88200; 4091 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4092 ch->pcmrates[i++] = 96000; 4093 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4094 ch->pcmrates[i++] = 176400; 4095 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4096 ch->pcmrates[i++] = 192000; 4097 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4098 ch->pcmrates[i] = 0; 4099 if (i > 0) { 4100 ch->caps.minspeed = ch->pcmrates[0]; 4101 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4102 } 4103 } 4104 4105 return (ret); 4106} 4107 4108static void 4109hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4110{ 4111 struct hdac_audio_ctl *ctl; 4112 struct hdac_softc *sc = devinfo->codec->sc; 4113 int i; 4114 uint32_t fl = 0; 4115 4116 4117 if (flag == 0) { 4118 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4119 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4120 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4121 } 4122 4123 i = 0; 4124 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4125 if (ctl->enable == 0 || ctl->widget == NULL || 4126 ctl->widget->enable == 0) 4127 continue; 4128 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4129 (flag != 0 && (ctl->ossmask & flag))) { 4130 if (banner != NULL) { 4131 device_printf(sc->dev, "\n"); 4132 device_printf(sc->dev, "%s\n", banner); 4133 } 4134 goto hdac_ctl_dump_it_all; 4135 } 4136 } 4137 4138 return; 4139 4140hdac_ctl_dump_it_all: 4141 i = 0; 4142 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4143 if (ctl->enable == 0 || ctl->widget == NULL || 4144 ctl->widget->enable == 0) 4145 continue; 4146 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4147 (flag != 0 && (ctl->ossmask & flag)))) 4148 continue; 4149 if (flag == 0) { 4150 device_printf(sc->dev, "\n"); 4151 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4152 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4153 } 4154 device_printf(sc->dev, " |\n"); 4155 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4156 ctl->widget->nid, ctl->index); 4157 if (ctl->childwidget != NULL) 4158 printf("(nid: %2d) ", ctl->childwidget->nid); 4159 else 4160 printf(" "); 4161 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4162 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4163 ctl->ossmask); 4164 } 4165} 4166 4167static void 4168hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4169{ 4170 uint32_t cap; 4171 4172 cap = fcap; 4173 if (cap != 0) { 4174 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4175 device_printf(sc->dev, " Format:"); 4176 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4177 printf(" AC3"); 4178 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4179 printf(" FLOAT32"); 4180 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4181 printf(" PCM"); 4182 printf("\n"); 4183 } 4184 cap = pcmcap; 4185 if (cap != 0) { 4186 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4187 device_printf(sc->dev, " PCM size:"); 4188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4189 printf(" 8"); 4190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4191 printf(" 16"); 4192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4193 printf(" 20"); 4194 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4195 printf(" 24"); 4196 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4197 printf(" 32"); 4198 printf("\n"); 4199 device_printf(sc->dev, " PCM rate:"); 4200 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4201 printf(" 8"); 4202 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4203 printf(" 11"); 4204 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4205 printf(" 16"); 4206 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4207 printf(" 22"); 4208 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4209 printf(" 32"); 4210 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4211 printf(" 44"); 4212 printf(" 48"); 4213 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4214 printf(" 88"); 4215 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4216 printf(" 96"); 4217 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4218 printf(" 176"); 4219 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4220 printf(" 192"); 4221 printf("\n"); 4222 } 4223} 4224 4225static void 4226hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4227{ 4228 uint32_t pincap, wcap; 4229 4230 pincap = w->wclass.pin.cap; 4231 wcap = w->param.widget_cap; 4232 4233 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4234 device_printf(sc->dev, " "); 4235 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4236 printf(" ISC"); 4237 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4238 printf(" TRQD"); 4239 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4240 printf(" PDC"); 4241 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4242 printf(" HP"); 4243 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4244 printf(" OUT"); 4245 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4246 printf(" IN"); 4247 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4248 printf(" BAL"); 4249 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4250 printf(" EAPD"); 4251 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4252 printf(" : UNSOL"); 4253 printf("\n"); 4254 device_printf(sc->dev, " Pin config: 0x%08x\n", 4255 w->wclass.pin.config); 4256 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4257 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4258 printf(" HP"); 4259 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4260 printf(" IN"); 4261 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4262 printf(" OUT"); 4263 printf("\n"); 4264} 4265 4266static void 4267hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4268{ 4269 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4270 device_printf(sc->dev, " " 4271 "mute=%d step=%d size=%d offset=%d\n", 4272 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4273 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4274 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4275 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4276} 4277 4278static void 4279hdac_dump_nodes(struct hdac_devinfo *devinfo) 4280{ 4281 struct hdac_softc *sc = devinfo->codec->sc; 4282 struct hdac_widget *w, *cw; 4283 int i, j; 4284 4285 device_printf(sc->dev, "\n"); 4286 device_printf(sc->dev, "Default Parameter\n"); 4287 device_printf(sc->dev, "-----------------\n"); 4288 hdac_dump_audio_formats(sc, 4289 devinfo->function.audio.supp_stream_formats, 4290 devinfo->function.audio.supp_pcm_size_rate); 4291 device_printf(sc->dev, " IN amp: 0x%08x\n", 4292 devinfo->function.audio.inamp_cap); 4293 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4294 devinfo->function.audio.outamp_cap); 4295 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4296 w = hdac_widget_get(devinfo, i); 4297 if (w == NULL) { 4298 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4299 continue; 4300 } 4301 device_printf(sc->dev, "\n"); 4302 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4303 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4304 "DIGITAL" : "ANALOG", 4305 (w->enable == 0) ? " [DISABLED]" : ""); 4306 device_printf(sc->dev, " name: %s\n", w->name); 4307 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4308 w->param.widget_cap); 4309 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4310 w->pflags); 4311 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4312 w->ctlflags); 4313 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4314 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4315 hdac_dump_audio_formats(sc, 4316 w->param.supp_stream_formats, 4317 w->param.supp_pcm_size_rate); 4318 } else if (w->type == 4319 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4320 hdac_dump_pin(sc, w); 4321 if (w->param.eapdbtl != HDAC_INVALID) 4322 device_printf(sc->dev, " EAPD: 0x%08x\n", 4323 w->param.eapdbtl); 4324 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4325 w->param.outamp_cap != 0) 4326 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4327 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4328 w->param.inamp_cap != 0) 4329 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4330 device_printf(sc->dev, " connections: %d\n", w->nconns); 4331 for (j = 0; j < w->nconns; j++) { 4332 cw = hdac_widget_get(devinfo, w->conns[j]); 4333 device_printf(sc->dev, " |\n"); 4334 device_printf(sc->dev, " + <- nid=%d [%s]", 4335 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4336 if (cw == NULL) 4337 printf(" [UNKNOWN]"); 4338 else if (cw->enable == 0) 4339 printf(" [DISABLED]"); 4340 if (w->nconns > 1 && w->selconn == j && w->type != 4341 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4342 printf(" (selected)"); 4343 printf("\n"); 4344 } 4345 } 4346 4347} 4348 4349static int 4350hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4351{ 4352 struct hdac_widget *w, *cw; 4353 struct hdac_softc *sc = devinfo->codec->sc; 4354 int i; 4355 4356 if (depth > HDA_PARSE_MAXDEPTH) 4357 return (0); 4358 4359 w = hdac_widget_get(devinfo, nid); 4360 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4361 return (0); 4362 4363 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4364 device_printf(sc->dev, "\n"); 4365 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4366 device_printf(sc->dev, " ^\n"); 4367 device_printf(sc->dev, " |\n"); 4368 device_printf(sc->dev, " +-----<------+\n"); 4369 } else { 4370 device_printf(sc->dev, " ^\n"); 4371 device_printf(sc->dev, " |\n"); 4372 device_printf(sc->dev, " "); 4373 printf(" nid=%d [%s]\n", w->nid, w->name); 4374 } 4375 4376 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4377 return (1); 4378 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4379 for (i = 0; i < w->nconns; i++) { 4380 cw = hdac_widget_get(devinfo, w->conns[i]); 4381 if (cw == NULL || cw->enable == 0 || cw->type == 4382 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4383 continue; 4384 if (hdac_dump_dac_internal(devinfo, cw->nid, 4385 depth + 1) != 0) 4386 return (1); 4387 } 4388 } else if ((w->type == 4389 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4390 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4391 w->selconn > -1 && w->selconn < w->nconns) { 4392 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4393 depth + 1) != 0) 4394 return (1); 4395 } 4396 4397 return (0); 4398} 4399 4400static void 4401hdac_dump_dac(struct hdac_devinfo *devinfo) 4402{ 4403 struct hdac_widget *w; 4404 struct hdac_softc *sc = devinfo->codec->sc; 4405 int i, printed = 0; 4406 4407 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4408 w = hdac_widget_get(devinfo, i); 4409 if (w == NULL || w->enable == 0) 4410 continue; 4411 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4412 !(w->pflags & HDA_DAC_PATH)) 4413 continue; 4414 if (printed == 0) { 4415 printed = 1; 4416 device_printf(sc->dev, "\n"); 4417 device_printf(sc->dev, "Playback path:\n"); 4418 } 4419 hdac_dump_dac_internal(devinfo, w->nid, 0); 4420 } 4421} 4422 4423static void 4424hdac_dump_adc(struct hdac_devinfo *devinfo) 4425{ 4426 struct hdac_widget *w, *cw; 4427 struct hdac_softc *sc = devinfo->codec->sc; 4428 int i, j; 4429 int printed = 0; 4430 char ossdevs[256]; 4431 4432 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4433 w = hdac_widget_get(devinfo, i); 4434 if (w == NULL || w->enable == 0) 4435 continue; 4436 if (!(w->pflags & HDA_ADC_RECSEL)) 4437 continue; 4438 if (printed == 0) { 4439 printed = 1; 4440 device_printf(sc->dev, "\n"); 4441 device_printf(sc->dev, "Recording sources:\n"); 4442 } 4443 device_printf(sc->dev, "\n"); 4444 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4445 for (j = 0; j < w->nconns; j++) { 4446 cw = hdac_widget_get(devinfo, w->conns[j]); 4447 if (cw == NULL || cw->enable == 0) 4448 continue; 4449 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4450 ossdevs, sizeof(ossdevs)); 4451 device_printf(sc->dev, " |\n"); 4452 device_printf(sc->dev, " + <- nid=%d [%s]", 4453 cw->nid, cw->name); 4454 if (strlen(ossdevs) > 0) { 4455 printf(" [recsrc: %s]", ossdevs); 4456 } 4457 printf("\n"); 4458 } 4459 } 4460} 4461 4462static void 4463hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4464{ 4465 nid_t *nids; 4466 4467 if (pcnt > 0) { 4468 device_printf(sc->dev, "\n"); 4469 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4470 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4471 sc->play.supp_pcm_size_rate); 4472 device_printf(sc->dev, " DAC:"); 4473 for (nids = sc->play.io; *nids != -1; nids++) 4474 printf(" %d", *nids); 4475 printf("\n"); 4476 } 4477 4478 if (rcnt > 0) { 4479 device_printf(sc->dev, "\n"); 4480 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4481 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4482 sc->rec.supp_pcm_size_rate); 4483 device_printf(sc->dev, " ADC:"); 4484 for (nids = sc->rec.io; *nids != -1; nids++) 4485 printf(" %d", *nids); 4486 printf("\n"); 4487 } 4488} 4489 4490static void 4491hdac_release_resources(struct hdac_softc *sc) 4492{ 4493 struct hdac_devinfo *devinfo = NULL; 4494 device_t *devlist = NULL; 4495 int i, devcount; 4496 4497 if (sc == NULL) 4498 return; 4499 4500 hdac_lock(sc); 4501 hdac_reset(sc); 4502 hdac_unlock(sc); 4503 snd_mtxfree(sc->lock); 4504 4505 device_get_children(sc->dev, &devlist, &devcount); 4506 for (i = 0; devlist != NULL && i < devcount; i++) { 4507 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4508 if (devinfo == NULL) 4509 continue; 4510 if (devinfo->widget != NULL) 4511 free(devinfo->widget, M_HDAC); 4512 if (devinfo->node_type == 4513 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4514 devinfo->function.audio.ctl != NULL) 4515 free(devinfo->function.audio.ctl, M_HDAC); 4516 free(devinfo, M_HDAC); 4517 device_delete_child(sc->dev, devlist[i]); 4518 } 4519 if (devlist != NULL) 4520 free(devlist, M_TEMP); 4521 4522 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4523 if (sc->codecs[i] != NULL) 4524 free(sc->codecs[i], M_HDAC); 4525 sc->codecs[i] = NULL; 4526 } 4527 4528 hdac_dma_free(&sc->rirb_dma); 4529 hdac_dma_free(&sc->corb_dma); 4530 if (sc->play.blkcnt > 0) 4531 hdac_dma_free(&sc->play.bdl_dma); 4532 if (sc->rec.blkcnt > 0) 4533 hdac_dma_free(&sc->rec.bdl_dma); 4534 hdac_irq_free(sc); 4535 hdac_mem_free(sc); 4536 free(sc, M_DEVBUF); 4537 4538} 4539 4540/* This function surely going to make its way into upper level someday. */ 4541static void 4542hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4543{ 4544 const char *res = NULL; 4545 int i = 0, j, k, len, inv; 4546 4547 if (on != NULL) 4548 *on = 0; 4549 if (off != NULL) 4550 *off = 0; 4551 if (sc == NULL) 4552 return; 4553 if (resource_string_value(device_get_name(sc->dev), 4554 device_get_unit(sc->dev), "config", &res) != 0) 4555 return; 4556 if (!(res != NULL && strlen(res) > 0)) 4557 return; 4558 HDA_BOOTVERBOSE( 4559 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4560 ); 4561 for (;;) { 4562 while (res[i] != '\0' && 4563 (res[i] == ',' || isspace(res[i]) != 0)) 4564 i++; 4565 if (res[i] == '\0') { 4566 HDA_BOOTVERBOSE( 4567 printf("\n"); 4568 ); 4569 return; 4570 } 4571 j = i; 4572 while (res[j] != '\0' && 4573 !(res[j] == ',' || isspace(res[j]) != 0)) 4574 j++; 4575 len = j - i; 4576 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4577 inv = 2; 4578 else 4579 inv = 0; 4580 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4581 if (strncmp(res + i + inv, 4582 hdac_quirks_tab[k].key, len - inv) != 0) 4583 continue; 4584 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4585 break; 4586 HDA_BOOTVERBOSE( 4587 printf(" %s%s", (inv != 0) ? "no" : "", 4588 hdac_quirks_tab[k].key); 4589 ); 4590 if (inv == 0 && on != NULL) 4591 *on |= hdac_quirks_tab[k].value; 4592 else if (inv != 0 && off != NULL) 4593 *off |= hdac_quirks_tab[k].value; 4594 break; 4595 } 4596 i = j; 4597 } 4598} 4599 4600static void 4601hdac_attach2(void *arg) 4602{ 4603 struct hdac_softc *sc; 4604 struct hdac_widget *w; 4605 struct hdac_audio_ctl *ctl; 4606 uint32_t quirks_on, quirks_off; 4607 int pcnt, rcnt; 4608 int i; 4609 char status[SND_STATUSLEN]; 4610 device_t *devlist = NULL; 4611 int devcount; 4612 struct hdac_devinfo *devinfo = NULL; 4613 4614 sc = (struct hdac_softc *)arg; 4615 4616 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4617 4618 HDA_BOOTVERBOSE( 4619 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4620 quirks_on, quirks_off); 4621 ); 4622 4623 hdac_lock(sc); 4624 4625 /* Remove ourselves from the config hooks */ 4626 if (sc->intrhook.ich_func != NULL) { 4627 config_intrhook_disestablish(&sc->intrhook); 4628 sc->intrhook.ich_func = NULL; 4629 } 4630 4631 /* Start the corb and rirb engines */ 4632 HDA_BOOTVERBOSE( 4633 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4634 ); 4635 hdac_corb_start(sc); 4636 HDA_BOOTVERBOSE( 4637 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4638 ); 4639 hdac_rirb_start(sc); 4640 4641 HDA_BOOTVERBOSE( 4642 device_printf(sc->dev, 4643 "HDA_DEBUG: Enabling controller interrupt...\n"); 4644 ); 4645 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4646 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4647 HDAC_GCTL_UNSOL); 4648 4649 DELAY(1000); 4650 4651 HDA_BOOTVERBOSE( 4652 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4653 ); 4654 hdac_scan_codecs(sc); 4655 4656 device_get_children(sc->dev, &devlist, &devcount); 4657 for (i = 0; devlist != NULL && i < devcount; i++) { 4658 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4659 if (devinfo != NULL && devinfo->node_type == 4660 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4661 break; 4662 } else 4663 devinfo = NULL; 4664 } 4665 if (devlist != NULL) 4666 free(devlist, M_TEMP); 4667 4668 if (devinfo == NULL) { 4669 hdac_unlock(sc); 4670 device_printf(sc->dev, "Audio Function Group not found!\n"); 4671 hdac_release_resources(sc); 4672 return; 4673 } 4674 4675 HDA_BOOTVERBOSE( 4676 device_printf(sc->dev, 4677 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4678 devinfo->nid, devinfo->codec->cad); 4679 ); 4680 hdac_audio_parse(devinfo); 4681 HDA_BOOTVERBOSE( 4682 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4683 ); 4684 hdac_audio_ctl_parse(devinfo); 4685 HDA_BOOTVERBOSE( 4686 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4687 ); 4688 hdac_vendor_patch_parse(devinfo); 4689 if (quirks_on != 0) 4690 devinfo->function.audio.quirks |= quirks_on; 4691 if (quirks_off != 0) 4692 devinfo->function.audio.quirks &= ~quirks_off; 4693 4694 /* XXX Disable all DIGITAL path. */ 4695 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4696 w = hdac_widget_get(devinfo, i); 4697 if (w == NULL) 4698 continue; 4699 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4700 w->enable = 0; 4701 continue; 4702 } 4703 /* XXX Disable useless pin ? */ 4704 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4705 (w->wclass.pin.config & 4706 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4707 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4708 w->enable = 0; 4709 } 4710 i = 0; 4711 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4712 if (ctl->widget == NULL) 4713 continue; 4714 w = ctl->widget; 4715 if (w->enable == 0) 4716 ctl->enable = 0; 4717 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4718 ctl->enable = 0; 4719 w = ctl->childwidget; 4720 if (w == NULL) 4721 continue; 4722 if (w->enable == 0 || 4723 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4724 ctl->enable = 0; 4725 } 4726 4727 HDA_BOOTVERBOSE( 4728 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 4729 ); 4730 hdac_audio_build_tree(devinfo); 4731 4732 HDA_BOOTVERBOSE( 4733 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 4734 ); 4735 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 4736 HDA_BOOTVERBOSE( 4737 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 4738 ); 4739 hdac_audio_ctl_commit(devinfo); 4740 4741 HDA_BOOTVERBOSE( 4742 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 4743 ); 4744 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 4745 HDA_BOOTVERBOSE( 4746 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 4747 ); 4748 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 4749 4750 hdac_unlock(sc); 4751 HDA_BOOTVERBOSE( 4752 device_printf(sc->dev, 4753 "HDA_DEBUG: OSS mixer initialization...\n"); 4754 ); 4755 4756 /* 4757 * There is no point of return after this. If the driver failed, 4758 * so be it. Let the detach procedure do all the cleanup. 4759 */ 4760 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 4761 device_printf(sc->dev, "Can't register mixer\n"); 4762 4763 if (pcnt > 0) 4764 pcnt = 1; 4765 if (rcnt > 0) 4766 rcnt = 1; 4767 4768 HDA_BOOTVERBOSE( 4769 device_printf(sc->dev, 4770 "HDA_DEBUG: Registering PCM channels...\n"); 4771 ); 4772 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 4773 device_printf(sc->dev, "Can't register PCM\n"); 4774 4775 sc->registered++; 4776 4777 for (i = 0; i < pcnt; i++) 4778 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 4779 for (i = 0; i < rcnt; i++) 4780 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 4781 4782 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 4783 rman_get_start(sc->mem.mem_res), 4784 rman_get_start(sc->irq.irq_res), 4785 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 4786 pcm_setstatus(sc->dev, status); 4787 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 4788 HDA_BOOTVERBOSE( 4789 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 4790 hdac_codec_id(devinfo)); 4791 ); 4792 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 4793 4794 HDA_BOOTVERBOSE( 4795 if (devinfo->function.audio.quirks != 0) { 4796 device_printf(sc->dev, "\n"); 4797 device_printf(sc->dev, "HDA config/quirks:"); 4798 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 4799 if (devinfo->function.audio.quirks & 4800 hdac_quirks_tab[i].value) 4801 printf(" %s", hdac_quirks_tab[i].key); 4802 } 4803 printf("\n"); 4804 } 4805 device_printf(sc->dev, "\n"); 4806 device_printf(sc->dev, "+-------------------+\n"); 4807 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 4808 device_printf(sc->dev, "+-------------------+\n"); 4809 hdac_dump_nodes(devinfo); 4810 device_printf(sc->dev, "\n"); 4811 device_printf(sc->dev, "+------------------------+\n"); 4812 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 4813 device_printf(sc->dev, "+------------------------+\n"); 4814 device_printf(sc->dev, "\n"); 4815 i = 0; 4816 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4817 device_printf(sc->dev, "%3d: nid=%d", i, 4818 (ctl->widget != NULL) ? ctl->widget->nid : -1); 4819 if (ctl->childwidget != NULL) 4820 printf(" cnid=%d", ctl->childwidget->nid); 4821 printf(" dir=0x%x index=%d " 4822 "ossmask=0x%08x ossdev=%d%s\n", 4823 ctl->dir, ctl->index, 4824 ctl->ossmask, ctl->ossdev, 4825 (ctl->enable == 0) ? " [DISABLED]" : ""); 4826 } 4827 device_printf(sc->dev, "\n"); 4828 device_printf(sc->dev, "+-----------------------------------+\n"); 4829 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 4830 device_printf(sc->dev, "+-----------------------------------+\n"); 4831 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 4832 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 4833 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 4834 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 4835 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 4836 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 4837 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 4838 hdac_dump_ctls(devinfo, NULL, 0); 4839 hdac_dump_dac(devinfo); 4840 hdac_dump_adc(devinfo); 4841 device_printf(sc->dev, "\n"); 4842 device_printf(sc->dev, "+--------------------------------------+\n"); 4843 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 4844 device_printf(sc->dev, "+--------------------------------------+\n"); 4845 hdac_dump_pcmchannels(sc, pcnt, rcnt); 4846 ); 4847} 4848 4849/**************************************************************************** 4850 * int hdac_detach(device_t) 4851 * 4852 * Detach and free up resources utilized by the hdac device. 4853 ****************************************************************************/ 4854static int 4855hdac_detach(device_t dev) 4856{ 4857 struct hdac_softc *sc = NULL; 4858 struct hdac_devinfo *devinfo = NULL; 4859 int err; 4860 4861 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 4862 if (devinfo != NULL && devinfo->codec != NULL) 4863 sc = devinfo->codec->sc; 4864 if (sc == NULL) 4865 return (0); 4866 4867 if (sc->registered > 0) { 4868 err = pcm_unregister(dev); 4869 if (err != 0) 4870 return (err); 4871 } 4872 4873 hdac_release_resources(sc); 4874 4875 return (0); 4876} 4877 4878static device_method_t hdac_methods[] = { 4879 /* device interface */ 4880 DEVMETHOD(device_probe, hdac_probe), 4881 DEVMETHOD(device_attach, hdac_attach), 4882 DEVMETHOD(device_detach, hdac_detach), 4883 { 0, 0 } 4884}; 4885 4886static driver_t hdac_driver = { 4887 "pcm", 4888 hdac_methods, 4889 PCM_SOFTC_SIZE, 4890}; 4891 4892DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 4893MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 4894MODULE_VERSION(snd_hda, 1); 4895