hdac.c revision 163276
1204431Sraj/*- 2204431Sraj * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3204431Sraj * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4204431Sraj * All rights reserved. 5204431Sraj * 6204431Sraj * Redistribution and use in source and binary forms, with or without 7204431Sraj * modification, are permitted provided that the following conditions 8204431Sraj * are met: 9204431Sraj * 1. Redistributions of source code must retain the above copyright 10204431Sraj * notice, this list of conditions and the following disclaimer. 11204431Sraj * 2. Redistributions in binary form must reproduce the above copyright 12204431Sraj * notice, this list of conditions and the following disclaimer in the 13204431Sraj * documentation and/or other materials provided with the distribution. 14204431Sraj * 15204431Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16204431Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17204431Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18204431Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19204431Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20204431Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21204431Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22204431Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23204431Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24204431Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25204431Sraj * SUCH DAMAGE. 26204431Sraj */ 27204431Sraj 28204431Sraj/* 29204431Sraj * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30204431Sraj * that this driver still in its early stage, and possible of rewrite are 31204431Sraj * pretty much guaranteed. There are supposedly several distinct parent/child 32204431Sraj * busses to make this "perfect", but as for now and for the sake of 33204433Sraj * simplicity, everything is gobble up within single source. 34204431Sraj * 35204431Sraj * List of subsys: 36204431Sraj * 1) HDA Controller support 37204431Sraj * 2) HDA Codecs support, which may include 38204431Sraj * - HDA 39204431Sraj * - Modem 40204431Sraj * - HDMI 41204431Sraj * 3) Widget parser - the real magic of why this driver works on so 42204431Sraj * many hardwares with minimal vendor specific quirk. The original 43204431Sraj * parser was written using Ruby and can be found at 44204431Sraj * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45204431Sraj * ruby parser take the verbose dmesg dump as its input. Refer to 46204431Sraj * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47204431Sraj * interesting documents, especiall UAA (Universal Audio Architecture). 48204431Sraj * 4) Possible vendor specific support. 49204431Sraj * (snd_hda_intel, snd_hda_ati, etc..) 50204431Sraj * 51204431Sraj * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52204431Sraj * Compaq V3000 with Conexant HDA. 53204431Sraj * 54204431Sraj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55204431Sraj * * * 56204431Sraj * * This driver is a collaborative effort made by: * 57204431Sraj * * * 58204431Sraj * * Stephane E. Potvin <sepotvin@videotron.ca> * 59204431Sraj * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60204431Sraj * * Wesley Morgan <morganw@chemikals.org> * 61204431Sraj * * Daniel Eischen <deischen@FreeBSD.org> * 62204431Sraj * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63204431Sraj * * Ariff Abdullah <ariff@FreeBSD.org> * 64204431Sraj * * * 65204431Sraj * * ....and various people from freebsd-multimedia@FreeBSD.org * 66204431Sraj * * * 67204431Sraj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68204431Sraj */ 69204431Sraj 70204431Sraj#include <sys/ctype.h> 71204431Sraj 72204431Sraj#include <dev/sound/pcm/sound.h> 73204431Sraj#include <dev/pci/pcireg.h> 74204431Sraj#include <dev/pci/pcivar.h> 75204431Sraj 76204431Sraj#include <dev/sound/pci/hda/hdac_private.h> 77204431Sraj#include <dev/sound/pci/hda/hdac_reg.h> 78204431Sraj#include <dev/sound/pci/hda/hda_reg.h> 79204431Sraj#include <dev/sound/pci/hda/hdac.h> 80204431Sraj 81204431Sraj#include "mixer_if.h" 82204431Sraj 83204431Sraj#define HDA_DRV_TEST_REV "20061013_0032" 84204431Sraj#define HDA_WIDGET_PARSER_REV 1 85204431Sraj 86204431SrajSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 163276 2006-10-12 15:37:43Z ariff $"); 87204431Sraj 88204431Sraj#undef HDA_DEBUG_ENABLED 89204431Sraj#define HDA_DEBUG_ENABLED 1 90204431Sraj 91204431Sraj#ifdef HDA_DEBUG_ENABLED 92204431Sraj#define HDA_DEBUG(stmt) do { \ 93204431Sraj stmt \ 94204431Sraj} while(0) 95204431Sraj#else 96204431Sraj#define HDA_DEBUG(stmt) 97204431Sraj#endif 98204431Sraj 99204431Sraj#define HDA_BOOTVERBOSE(stmt) do { \ 100204431Sraj if (bootverbose) { \ 101204431Sraj stmt \ 102204431Sraj } \ 103204431Sraj} while(0) 104204431Sraj 105204431Sraj#if 1 106204431Sraj#undef HDAC_INTR_EXTRA 107204431Sraj#define HDAC_INTR_EXTRA 1 108204431Sraj#endif 109204431Sraj 110204433Sraj#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111204433Sraj#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112204433Sraj#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113204433Sraj#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114204433Sraj 115204431Sraj#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116204431Sraj#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117204431Sraj (fl) == 0xffffffff || \ 118204431Sraj (((fl) & 0xffff0000) == 0xffff0000 && \ 119204431Sraj ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120204431Sraj (((fl) & 0x0000ffff) == 0x0000ffff && \ 121204431Sraj ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122204431Sraj#define HDA_MATCH_ALL 0xffffffff 123204431Sraj#define HDAC_INVALID 0xffffffff 124204431Sraj 125204431Sraj#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126204431Sraj (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127204431Sraj 128204431Sraj/* Controller models */ 129204431Sraj 130204431Sraj/* Intel */ 131204431Sraj#define INTEL_VENDORID 0x8086 132204431Sraj#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133204431Sraj#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134204431Sraj#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135204431Sraj#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136204433Sraj#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137204431Sraj 138204431Sraj/* Nvidia */ 139204431Sraj#define NVIDIA_VENDORID 0x10de 140204431Sraj#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141204431Sraj#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142204431Sraj#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143204431Sraj#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144204431Sraj#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145204431Sraj#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146204431Sraj#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147204431Sraj 148204431Sraj/* ATI */ 149204431Sraj#define ATI_VENDORID 0x1002 150204431Sraj#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151204431Sraj#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152204431Sraj#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153204431Sraj 154204431Sraj/* VIA */ 155204431Sraj#define VIA_VENDORID 0x1106 156204431Sraj#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157204431Sraj#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158204431Sraj 159204431Sraj/* SiS */ 160204431Sraj#define SIS_VENDORID 0x1039 161204431Sraj#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162204431Sraj#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163204431Sraj 164204431Sraj/* OEM/subvendors */ 165204431Sraj 166204431Sraj/* HP/Compaq */ 167204431Sraj#define HP_VENDORID 0x103c 168204431Sraj#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169204431Sraj#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170204431Sraj#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171204431Sraj#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172204431Sraj 173204431Sraj/* Dell */ 174204433Sraj#define DELL_VENDORID 0x1028 175204433Sraj#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176204433Sraj#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177204433Sraj#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178204433Sraj 179204433Sraj/* Clevo */ 180204433Sraj#define CLEVO_VENDORID 0x1558 181204433Sraj#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182204433Sraj#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183204433Sraj 184204433Sraj/* Acer */ 185204433Sraj#define ACER_VENDORID 0x1025 186204431Sraj#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187204431Sraj 188204431Sraj/* Asus */ 189204431Sraj#define ASUS_VENDORID 0x1043 190204431Sraj#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191204431Sraj#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 192204431Sraj#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 193204431Sraj 194204431Sraj/* IBM / Lenovo */ 195204431Sraj#define IBM_VENDORID 0x1014 196204431Sraj#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 197204431Sraj#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 198204431Sraj 199204431Sraj 200204431Sraj/* Misc constants.. */ 201204431Sraj#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 202204431Sraj#define HDA_AMP_MUTE_NONE (0) 203204433Sraj#define HDA_AMP_MUTE_LEFT (1 << 0) 204204433Sraj#define HDA_AMP_MUTE_RIGHT (1 << 1) 205204433Sraj#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 206204431Sraj 207204431Sraj#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 208204431Sraj#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 209204431Sraj 210204431Sraj#define HDA_DAC_PATH (1 << 0) 211204431Sraj#define HDA_ADC_PATH (1 << 1) 212204431Sraj#define HDA_ADC_RECSEL (1 << 2) 213204431Sraj 214204431Sraj#define HDA_CTL_OUT (1 << 0) 215204431Sraj#define HDA_CTL_IN (1 << 1) 216204431Sraj#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 217204431Sraj 218204431Sraj#define HDA_GPIO_MAX 15 219204431Sraj/* 0 - 14 = GPIO */ 220204431Sraj#define HDA_QUIRK_GPIO0 (1 << 0) 221204431Sraj#define HDA_QUIRK_GPIO1 (1 << 1) 222204431Sraj#define HDA_QUIRK_GPIO2 (1 << 2) 223204431Sraj#define HDA_QUIRK_SOFTPCMVOL (1 << 15) 224204431Sraj#define HDA_QUIRK_FIXEDRATE (1 << 16) 225204431Sraj#define HDA_QUIRK_FORCESTEREO (1 << 17) 226204431Sraj#define HDA_QUIRK_EAPDINV (1 << 18) 227204431Sraj 228204431Srajstatic const struct { 229204431Sraj char *key; 230204431Sraj uint32_t value; 231204431Sraj} hdac_quirks_tab[] = { 232204431Sraj { "gpio0", HDA_QUIRK_GPIO0 }, 233204431Sraj { "gpio1", HDA_QUIRK_GPIO1 }, 234204431Sraj { "gpio2", HDA_QUIRK_GPIO2 }, 235204431Sraj { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 236204431Sraj { "fixedrate", HDA_QUIRK_FIXEDRATE }, 237204431Sraj { "forcestereo", HDA_QUIRK_FORCESTEREO }, 238204431Sraj { "eapdinv", HDA_QUIRK_EAPDINV }, 239204431Sraj}; 240204431Sraj#define HDAC_QUIRKS_TAB_LEN \ 241204431Sraj (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 242204431Sraj 243204431Sraj#define HDA_BDL_MIN 2 244204431Sraj#define HDA_BDL_MAX 256 245204431Sraj#define HDA_BDL_DEFAULT HDA_BDL_MIN 246204431Sraj 247204431Sraj#define HDA_BUFSZ_MIN 4096 248#define HDA_BUFSZ_MAX 65536 249#define HDA_BUFSZ_DEFAULT 16384 250 251#define HDA_PARSE_MAXDEPTH 10 252 253#define HDAC_UNSOLTAG_EVENT_HP 0x00 254 255static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 256 257enum { 258 HDA_PARSE_MIXER, 259 HDA_PARSE_DIRECT 260}; 261 262/* Default */ 263static uint32_t hdac_fmt[] = { 264 AFMT_STEREO | AFMT_S16_LE, 265 0 266}; 267 268static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 269 270static const struct { 271 uint32_t model; 272 char *desc; 273} hdac_devices[] = { 274 { HDA_INTEL_82801F, "Intel 82801F" }, 275 { HDA_INTEL_82801G, "Intel 82801G" }, 276 { HDA_INTEL_82801H, "Intel 82801H" }, 277 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 278 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 279 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 280 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 281 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 282 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 283 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 284 { HDA_ATI_SB450, "ATI SB450" }, 285 { HDA_ATI_SB600, "ATI SB600" }, 286 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 287 { HDA_SIS_966, "SiS 966" }, 288 /* Unknown */ 289 { HDA_INTEL_ALL, "Intel (Unknown)" }, 290 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 291 { HDA_ATI_ALL, "ATI (Unknown)" }, 292 { HDA_VIA_ALL, "VIA (Unknown)" }, 293 { HDA_SIS_ALL, "SiS (Unknown)" }, 294}; 295#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 296 297static const struct { 298 uint32_t rate; 299 int valid; 300 uint16_t base; 301 uint16_t mul; 302 uint16_t div; 303} hda_rate_tab[] = { 304 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 305 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 306 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 307 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 308 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 309 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 310 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 311 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 312 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 313 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 314 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 315 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 316 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 317 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 318 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 319 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 320 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 321 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 322 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 323 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 324 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 325 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 326 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 327 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 328 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 329 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 330 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 331 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 332 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 333 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 334 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 335 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 336 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 337 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 338 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 339}; 340#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 341 342/* All codecs you can eat... */ 343#define HDA_CODEC_CONSTRUCT(vendor, id) \ 344 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 345 346/* Realtek */ 347#define REALTEK_VENDORID 0x10ec 348#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 349#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 350#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 351#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 352#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 353#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 354 355/* Analog Device */ 356#define ANALOGDEVICE_VENDORID 0x11d4 357#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 358#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 359#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 360#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 361 362/* CMedia */ 363#define CMEDIA_VENDORID 0x434d 364#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 365#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 366 367/* Sigmatel */ 368#define SIGMATEL_VENDORID 0x8384 369#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 370#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 371#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 372#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 373#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 374 375/* 376 * Conexant 377 * 378 * Ok, the truth is, I don't have any idea at all whether 379 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 380 * place that tell me it is "Venice" is from its Windows driver INF. 381 * 382 * Venice - CX????? 383 * Waikiki - CX20551-22 384 */ 385#define CONEXANT_VENDORID 0x14f1 386#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 387#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 388#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 389 390 391/* Codecs */ 392static const struct { 393 uint32_t id; 394 char *name; 395} hdac_codecs[] = { 396 { HDA_CODEC_ALC260, "Realtek ALC260" }, 397 { HDA_CODEC_ALC861, "Realtek ALC861" }, 398 { HDA_CODEC_ALC880, "Realtek ALC880" }, 399 { HDA_CODEC_ALC882, "Realtek ALC882" }, 400 { HDA_CODEC_ALC883, "Realtek ALC883" }, 401 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 402 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 403 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 404 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 405 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 406 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 407 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 408 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 409 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 410 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 411 /* Unknown codec */ 412 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 413 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 414 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 415 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 416 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 417}; 418#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 419 420enum { 421 HDAC_HP_SWITCH_CTL, 422 HDAC_HP_SWITCH_CTRL 423}; 424 425static const struct { 426 uint32_t model; 427 uint32_t id; 428 int type; 429 nid_t hpnid; 430 nid_t spkrnid[8]; 431 nid_t eapdnid; 432} hdac_hp_switch[] = { 433 /* Specific OEM models */ 434 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 435 17, { 16, -1 }, 16 }, 436 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 437 6, { 5, -1 }, 5 }, 438 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 439 6, { 5, -1 }, 5 }, 440 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 441 13, { 14, -1 }, -1 }, 442 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 443 13, { 14, -1 }, -1 }, 444 /* 445 * All models that at least come from the same vendor with 446 * simmilar codec. 447 */ 448 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 449 17, { 16, -1 }, 16 }, 450 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 451 6, { 5, -1 }, 5 }, 452 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 453 13, { 14, -1 }, -1 }, 454}; 455#define HDAC_HP_SWITCH_LEN \ 456 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 457 458static const struct { 459 uint32_t model; 460 uint32_t id; 461 nid_t eapdnid; 462 int hp_switch; 463} hdac_eapd_switch[] = { 464 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 465 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 466 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 467}; 468#define HDAC_EAPD_SWITCH_LEN \ 469 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 470 471/**************************************************************************** 472 * Function prototypes 473 ****************************************************************************/ 474static void hdac_intr_handler(void *); 475static int hdac_reset(struct hdac_softc *); 476static int hdac_get_capabilities(struct hdac_softc *); 477static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 478static int hdac_dma_alloc(struct hdac_softc *, 479 struct hdac_dma *, bus_size_t); 480static void hdac_dma_free(struct hdac_dma *); 481static int hdac_mem_alloc(struct hdac_softc *); 482static void hdac_mem_free(struct hdac_softc *); 483static int hdac_irq_alloc(struct hdac_softc *); 484static void hdac_irq_free(struct hdac_softc *); 485static void hdac_corb_init(struct hdac_softc *); 486static void hdac_rirb_init(struct hdac_softc *); 487static void hdac_corb_start(struct hdac_softc *); 488static void hdac_rirb_start(struct hdac_softc *); 489static void hdac_scan_codecs(struct hdac_softc *); 490static int hdac_probe_codec(struct hdac_codec *); 491static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 492static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 493 494static void hdac_attach2(void *); 495 496static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 497 uint32_t, int); 498static void hdac_command_send_internal(struct hdac_softc *, 499 struct hdac_command_list *, int); 500 501static int hdac_probe(device_t); 502static int hdac_attach(device_t); 503static int hdac_detach(device_t); 504static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 505static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 506 uint32_t, int, int); 507static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 508 nid_t, int, int); 509static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 510 nid_t, nid_t, int, int, int, int, int, int); 511static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 512static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 513 514#define hdac_command(a1, a2, a3) \ 515 hdac_command_sendone_internal(a1, a2, a3) 516 517#define hdac_codec_id(d) \ 518 ((uint32_t)((d == NULL) ? 0x00000000 : \ 519 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 520 ((uint32_t)(d)->device_id & 0x0000ffff)))) 521 522static char * 523hdac_codec_name(struct hdac_devinfo *devinfo) 524{ 525 uint32_t id; 526 int i; 527 528 id = hdac_codec_id(devinfo); 529 530 for (i = 0; i < HDAC_CODECS_LEN; i++) { 531 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 532 return (hdac_codecs[i].name); 533 } 534 535 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 536} 537 538static char * 539hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 540{ 541 static char *ossname[] = SOUND_DEVICE_NAMES; 542 static char *unknown = "???"; 543 int i; 544 545 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 546 if (devmask & (1 << i)) 547 return (ossname[i]); 548 } 549 return (unknown); 550} 551 552static void 553hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 554{ 555 static char *ossname[] = SOUND_DEVICE_NAMES; 556 int i, first = 1; 557 558 bzero(buf, len); 559 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 560 if (mask & (1 << i)) { 561 if (first == 0) 562 strlcat(buf, ", ", len); 563 strlcat(buf, ossname[i], len); 564 first = 0; 565 } 566 } 567} 568 569static struct hdac_audio_ctl * 570hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 571{ 572 if (devinfo == NULL || 573 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 574 index == NULL || devinfo->function.audio.ctl == NULL || 575 devinfo->function.audio.ctlcnt < 1 || 576 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 577 return (NULL); 578 return (&devinfo->function.audio.ctl[(*index)++]); 579} 580 581static struct hdac_audio_ctl * 582hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 583 int index, int cnt) 584{ 585 struct hdac_audio_ctl *ctl, *retctl = NULL; 586 int i, at, atindex, found = 0; 587 588 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 589 return (NULL); 590 591 at = cnt; 592 if (at == 0) 593 at = 1; 594 else if (at < 0) 595 at = -1; 596 atindex = index; 597 if (atindex < 0) 598 atindex = -1; 599 600 i = 0; 601 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 602 if (ctl->enable == 0 || ctl->widget == NULL) 603 continue; 604 if (!(ctl->widget->nid == nid && (atindex == -1 || 605 ctl->index == atindex))) 606 continue; 607 found++; 608 if (found == cnt) 609 return (ctl); 610 retctl = ctl; 611 } 612 613 return ((at == -1) ? retctl : NULL); 614} 615 616static void 617hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 618{ 619 struct hdac_softc *sc; 620 struct hdac_widget *w; 621 struct hdac_audio_ctl *ctl; 622 uint32_t id, res; 623 int i = 0, j, forcemute; 624 nid_t cad; 625 626 if (devinfo == NULL || devinfo->codec == NULL || 627 devinfo->codec->sc == NULL) 628 return; 629 630 sc = devinfo->codec->sc; 631 cad = devinfo->codec->cad; 632 id = hdac_codec_id(devinfo); 633 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 634 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 635 sc->pci_subvendor) && 636 hdac_hp_switch[i].id == id) 637 break; 638 } 639 640 if (i >= HDAC_HP_SWITCH_LEN) 641 return; 642 643 forcemute = 0; 644 if (hdac_hp_switch[i].eapdnid != -1) { 645 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 646 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 647 forcemute = (w->param.eapdbtl & 648 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 649 } 650 651 res = hdac_command(sc, 652 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 653 HDA_BOOTVERBOSE( 654 device_printf(sc->dev, 655 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 656 hdac_hp_switch[i].hpnid, res); 657 ); 658 res >>= 31; 659 660 switch (hdac_hp_switch[i].type) { 661 case HDAC_HP_SWITCH_CTL: 662 ctl = hdac_audio_ctl_amp_get(devinfo, 663 hdac_hp_switch[i].hpnid, 0, 1); 664 if (ctl != NULL) { 665 ctl->muted = (res != 0 && forcemute == 0) ? 666 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 667 hdac_audio_ctl_amp_set(ctl, 668 HDA_AMP_MUTE_DEFAULT, ctl->left, 669 ctl->right); 670 } 671 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 672 ctl = hdac_audio_ctl_amp_get(devinfo, 673 hdac_hp_switch[i].spkrnid[j], 0, 1); 674 if (ctl != NULL) { 675 ctl->muted = (res != 0 || forcemute == 1) ? 676 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 677 hdac_audio_ctl_amp_set(ctl, 678 HDA_AMP_MUTE_DEFAULT, ctl->left, 679 ctl->right); 680 } 681 } 682 break; 683 case HDAC_HP_SWITCH_CTRL: 684 if (res != 0) { 685 /* HP in */ 686 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 687 if (w != NULL && w->type == 688 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 689 if (forcemute == 0) 690 w->wclass.pin.ctrl |= 691 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 692 else 693 w->wclass.pin.ctrl &= 694 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 695 hdac_command(sc, 696 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 697 w->wclass.pin.ctrl), cad); 698 } 699 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 700 w = hdac_widget_get(devinfo, 701 hdac_hp_switch[i].spkrnid[j]); 702 if (w != NULL && w->type == 703 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 704 w->wclass.pin.ctrl &= 705 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 706 hdac_command(sc, 707 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 708 w->nid, 709 w->wclass.pin.ctrl), cad); 710 } 711 } 712 } else { 713 /* HP out */ 714 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 715 if (w != NULL && w->type == 716 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 717 w->wclass.pin.ctrl &= 718 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 719 hdac_command(sc, 720 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 721 w->wclass.pin.ctrl), cad); 722 } 723 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 724 w = hdac_widget_get(devinfo, 725 hdac_hp_switch[i].spkrnid[j]); 726 if (w != NULL && w->type == 727 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 728 if (forcemute == 0) 729 w->wclass.pin.ctrl |= 730 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 731 else 732 w->wclass.pin.ctrl &= 733 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 734 hdac_command(sc, 735 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 736 w->nid, 737 w->wclass.pin.ctrl), cad); 738 } 739 } 740 } 741 break; 742 default: 743 break; 744 } 745} 746 747static void 748hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 749{ 750 struct hdac_softc *sc; 751 struct hdac_devinfo *devinfo = NULL; 752 device_t *devlist = NULL; 753 int devcount, i; 754 755 if (codec == NULL || codec->sc == NULL) 756 return; 757 758 sc = codec->sc; 759 760 HDA_BOOTVERBOSE( 761 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 762 ); 763 764 device_get_children(sc->dev, &devlist, &devcount); 765 for (i = 0; devlist != NULL && i < devcount; i++) { 766 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 767 if (devinfo != NULL && devinfo->node_type == 768 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 769 devinfo->codec != NULL && 770 devinfo->codec->cad == codec->cad) { 771 break; 772 } else 773 devinfo = NULL; 774 } 775 if (devlist != NULL) 776 free(devlist, M_TEMP); 777 778 if (devinfo == NULL) 779 return; 780 781 switch (tag) { 782 case HDAC_UNSOLTAG_EVENT_HP: 783 hdac_hp_switch_handler(devinfo); 784 break; 785 default: 786 break; 787 } 788} 789 790static void 791hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 792{ 793 /* XXX to be removed */ 794#ifdef HDAC_INTR_EXTRA 795 uint32_t res; 796#endif 797 798 if (ch->blkcnt == 0) 799 return; 800 801 /* XXX to be removed */ 802#ifdef HDAC_INTR_EXTRA 803 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 804#endif 805 806 /* XXX to be removed */ 807#ifdef HDAC_INTR_EXTRA 808 HDA_BOOTVERBOSE( 809 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 810 device_printf(sc->dev, 811 "PCMDIR_%s intr triggered beyond stream boundary:" 812 "%08x\n", 813 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 814 ); 815#endif 816 817 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 818 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 819 820 /* XXX to be removed */ 821#ifdef HDAC_INTR_EXTRA 822 if (res & HDAC_SDSTS_BCIS) { 823#endif 824 ch->prevptr = ch->ptr; 825 ch->ptr += sndbuf_getblksz(ch->b); 826 ch->ptr %= sndbuf_getsize(ch->b); 827 hdac_unlock(sc); 828 chn_intr(ch->c); 829 hdac_lock(sc); 830 /* XXX to be removed */ 831#ifdef HDAC_INTR_EXTRA 832 } 833#endif 834} 835 836/**************************************************************************** 837 * void hdac_intr_handler(void *) 838 * 839 * Interrupt handler. Processes interrupts received from the hdac. 840 ****************************************************************************/ 841static void 842hdac_intr_handler(void *context) 843{ 844 struct hdac_softc *sc; 845 uint32_t intsts; 846 uint8_t rirbsts; 847 uint8_t rirbwp; 848 struct hdac_rirb *rirb_base, *rirb; 849 nid_t ucad; 850 uint32_t utag; 851 852 sc = (struct hdac_softc *)context; 853 854 hdac_lock(sc); 855 /* Do we have anything to do? */ 856 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 857 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 858 hdac_unlock(sc); 859 return; 860 } 861 862 /* Was this a controller interrupt? */ 863 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 864 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 865 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 866 /* Get as many responses that we can */ 867 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 868 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 869 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 870 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 871 BUS_DMASYNC_POSTREAD); 872 while (sc->rirb_rp != rirbwp) { 873 sc->rirb_rp++; 874 sc->rirb_rp %= sc->rirb_size; 875 rirb = &rirb_base[sc->rirb_rp]; 876 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 877 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 878 utag = rirb->response >> 26; 879 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 880 sc->codecs[ucad] != NULL) { 881 sc->unsolq[sc->unsolq_wp++] = 882 (ucad << 16) | 883 (utag & 0xffff); 884 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 885 } 886 } 887 } 888 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 889 } 890 /* XXX to be removed */ 891 /* Clear interrupt and exit */ 892#ifdef HDAC_INTR_EXTRA 893 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 894#endif 895 } 896 if (intsts & HDAC_INTSTS_SIS_MASK) { 897 if (intsts & (1 << sc->num_iss)) 898 hdac_stream_intr(sc, &sc->play); 899 if (intsts & (1 << 0)) 900 hdac_stream_intr(sc, &sc->rec); 901 /* XXX to be removed */ 902#ifdef HDAC_INTR_EXTRA 903 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK); 904#endif 905 } 906 907 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 908 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 909 while (sc->unsolq_rp != sc->unsolq_wp) { 910 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 911 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 912 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 913 hdac_unsolicited_handler(sc->codecs[ucad], utag); 914 } 915 sc->unsolq_st = HDAC_UNSOLQ_READY; 916 } 917 918 hdac_unlock(sc); 919} 920 921/**************************************************************************** 922 * int hdac_reset(hdac_softc *) 923 * 924 * Reset the hdac to a quiescent and known state. 925 ****************************************************************************/ 926static int 927hdac_reset(struct hdac_softc *sc) 928{ 929 uint32_t gctl; 930 int count, i; 931 932 /* 933 * Stop all Streams DMA engine 934 */ 935 for (i = 0; i < sc->num_iss; i++) 936 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 937 for (i = 0; i < sc->num_oss; i++) 938 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 939 for (i = 0; i < sc->num_bss; i++) 940 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 941 942 /* 943 * Stop Control DMA engines 944 */ 945 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 946 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 947 948 /* 949 * Reset the controller. The reset must remain asserted for 950 * a minimum of 100us. 951 */ 952 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 953 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 954 count = 10000; 955 do { 956 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 957 if (!(gctl & HDAC_GCTL_CRST)) 958 break; 959 DELAY(10); 960 } while (--count); 961 if (gctl & HDAC_GCTL_CRST) { 962 device_printf(sc->dev, "Unable to put hdac in reset\n"); 963 return (ENXIO); 964 } 965 DELAY(100); 966 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 967 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 968 count = 10000; 969 do { 970 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 971 if (gctl & HDAC_GCTL_CRST) 972 break; 973 DELAY(10); 974 } while (--count); 975 if (!(gctl & HDAC_GCTL_CRST)) { 976 device_printf(sc->dev, "Device stuck in reset\n"); 977 return (ENXIO); 978 } 979 980 /* 981 * Wait for codecs to finish their own reset sequence. The delay here 982 * should be of 250us but for some reasons, on it's not enough on my 983 * computer. Let's use twice as much as necessary to make sure that 984 * it's reset properly. 985 */ 986 DELAY(1000); 987 988 return (0); 989} 990 991 992/**************************************************************************** 993 * int hdac_get_capabilities(struct hdac_softc *); 994 * 995 * Retreive the general capabilities of the hdac; 996 * Number of Input Streams 997 * Number of Output Streams 998 * Number of bidirectional Streams 999 * 64bit ready 1000 * CORB and RIRB sizes 1001 ****************************************************************************/ 1002static int 1003hdac_get_capabilities(struct hdac_softc *sc) 1004{ 1005 uint16_t gcap; 1006 uint8_t corbsize, rirbsize; 1007 1008 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1009 sc->num_iss = HDAC_GCAP_ISS(gcap); 1010 sc->num_oss = HDAC_GCAP_OSS(gcap); 1011 sc->num_bss = HDAC_GCAP_BSS(gcap); 1012 1013 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1014 1015 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1016 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1017 HDAC_CORBSIZE_CORBSZCAP_256) 1018 sc->corb_size = 256; 1019 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1020 HDAC_CORBSIZE_CORBSZCAP_16) 1021 sc->corb_size = 16; 1022 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1023 HDAC_CORBSIZE_CORBSZCAP_2) 1024 sc->corb_size = 2; 1025 else { 1026 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1027 __func__, corbsize); 1028 return (ENXIO); 1029 } 1030 1031 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1032 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1033 HDAC_RIRBSIZE_RIRBSZCAP_256) 1034 sc->rirb_size = 256; 1035 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1036 HDAC_RIRBSIZE_RIRBSZCAP_16) 1037 sc->rirb_size = 16; 1038 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1039 HDAC_RIRBSIZE_RIRBSZCAP_2) 1040 sc->rirb_size = 2; 1041 else { 1042 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1043 __func__, rirbsize); 1044 return (ENXIO); 1045 } 1046 1047 return (0); 1048} 1049 1050 1051/**************************************************************************** 1052 * void hdac_dma_cb 1053 * 1054 * This function is called by bus_dmamap_load when the mapping has been 1055 * established. We just record the physical address of the mapping into 1056 * the struct hdac_dma passed in. 1057 ****************************************************************************/ 1058static void 1059hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1060{ 1061 struct hdac_dma *dma; 1062 1063 if (error == 0) { 1064 dma = (struct hdac_dma *)callback_arg; 1065 dma->dma_paddr = segs[0].ds_addr; 1066 } 1067} 1068 1069static void 1070hdac_dma_nocache(void *ptr) 1071{ 1072#if defined(__i386__) || defined(__amd64__) 1073 pt_entry_t *pte; 1074 vm_offset_t va; 1075 1076 va = (vm_offset_t)ptr; 1077 pte = vtopte(va); 1078 if (pte) { 1079 *pte |= PG_N; 1080 invltlb(); 1081 } 1082#endif 1083} 1084 1085/**************************************************************************** 1086 * int hdac_dma_alloc 1087 * 1088 * This function allocate and setup a dma region (struct hdac_dma). 1089 * It must be freed by a corresponding hdac_dma_free. 1090 ****************************************************************************/ 1091static int 1092hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1093{ 1094 int result; 1095 int lowaddr; 1096 1097 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1098 BUS_SPACE_MAXADDR_32BIT; 1099 bzero(dma, sizeof(*dma)); 1100 1101 /* 1102 * Create a DMA tag 1103 */ 1104 result = bus_dma_tag_create(NULL, /* parent */ 1105 HDAC_DMA_ALIGNMENT, /* alignment */ 1106 0, /* boundary */ 1107 lowaddr, /* lowaddr */ 1108 BUS_SPACE_MAXADDR, /* highaddr */ 1109 NULL, /* filtfunc */ 1110 NULL, /* fistfuncarg */ 1111 size, /* maxsize */ 1112 1, /* nsegments */ 1113 size, /* maxsegsz */ 1114 0, /* flags */ 1115 NULL, /* lockfunc */ 1116 NULL, /* lockfuncarg */ 1117 &dma->dma_tag); /* dmat */ 1118 if (result != 0) { 1119 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1120 __func__, result); 1121 goto fail; 1122 } 1123 1124 /* 1125 * Allocate DMA memory 1126 */ 1127 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1128 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1129 if (result != 0) { 1130 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1131 __func__, result); 1132 goto fail; 1133 } 1134 1135 /* 1136 * Map the memory 1137 */ 1138 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1139 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1140 BUS_DMA_NOWAIT); 1141 if (result != 0 || dma->dma_paddr == 0) { 1142 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1143 __func__, result); 1144 goto fail; 1145 } 1146 bzero((void *)dma->dma_vaddr, size); 1147 hdac_dma_nocache(dma->dma_vaddr); 1148 1149 return (0); 1150fail: 1151 if (dma->dma_map != NULL) 1152 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1153 if (dma->dma_tag != NULL) 1154 bus_dma_tag_destroy(dma->dma_tag); 1155 return (result); 1156} 1157 1158 1159/**************************************************************************** 1160 * void hdac_dma_free(struct hdac_dma *) 1161 * 1162 * Free a struct dhac_dma that has been previously allocated via the 1163 * hdac_dma_alloc function. 1164 ****************************************************************************/ 1165static void 1166hdac_dma_free(struct hdac_dma *dma) 1167{ 1168 if (dma->dma_tag != NULL) { 1169 /* Flush caches */ 1170 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1171 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1172 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1173 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1174 bus_dma_tag_destroy(dma->dma_tag); 1175 } 1176} 1177 1178/**************************************************************************** 1179 * int hdac_mem_alloc(struct hdac_softc *) 1180 * 1181 * Allocate all the bus resources necessary to speak with the physical 1182 * controller. 1183 ****************************************************************************/ 1184static int 1185hdac_mem_alloc(struct hdac_softc *sc) 1186{ 1187 struct hdac_mem *mem; 1188 1189 mem = &sc->mem; 1190 mem->mem_rid = PCIR_BAR(0); 1191 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1192 &mem->mem_rid, RF_ACTIVE); 1193 if (mem->mem_res == NULL) { 1194 device_printf(sc->dev, 1195 "%s: Unable to allocate memory resource\n", __func__); 1196 return (ENOMEM); 1197 } 1198 mem->mem_tag = rman_get_bustag(mem->mem_res); 1199 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1200 1201 return (0); 1202} 1203 1204/**************************************************************************** 1205 * void hdac_mem_free(struct hdac_softc *) 1206 * 1207 * Free up resources previously allocated by hdac_mem_alloc. 1208 ****************************************************************************/ 1209static void 1210hdac_mem_free(struct hdac_softc *sc) 1211{ 1212 struct hdac_mem *mem; 1213 1214 mem = &sc->mem; 1215 if (mem->mem_res != NULL) 1216 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1217 mem->mem_res); 1218} 1219 1220/**************************************************************************** 1221 * int hdac_irq_alloc(struct hdac_softc *) 1222 * 1223 * Allocate and setup the resources necessary for interrupt handling. 1224 ****************************************************************************/ 1225static int 1226hdac_irq_alloc(struct hdac_softc *sc) 1227{ 1228 struct hdac_irq *irq; 1229 int result; 1230 1231 irq = &sc->irq; 1232 irq->irq_rid = 0x0; 1233 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1234 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1235 if (irq->irq_res == NULL) { 1236 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1237 __func__); 1238 goto fail; 1239 } 1240 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1241 hdac_intr_handler, sc, &irq->irq_handle); 1242 if (result != 0) { 1243 device_printf(sc->dev, 1244 "%s: Unable to setup interrupt handler (%x)\n", 1245 __func__, result); 1246 goto fail; 1247 } 1248 1249 return (0); 1250 1251fail: 1252 if (irq->irq_res != NULL) 1253 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1254 irq->irq_res); 1255 return (ENXIO); 1256} 1257 1258/**************************************************************************** 1259 * void hdac_irq_free(struct hdac_softc *) 1260 * 1261 * Free up resources previously allocated by hdac_irq_alloc. 1262 ****************************************************************************/ 1263static void 1264hdac_irq_free(struct hdac_softc *sc) 1265{ 1266 struct hdac_irq *irq; 1267 1268 irq = &sc->irq; 1269 if (irq->irq_handle != NULL) 1270 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1271 if (irq->irq_res != NULL) 1272 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1273 irq->irq_res); 1274} 1275 1276/**************************************************************************** 1277 * void hdac_corb_init(struct hdac_softc *) 1278 * 1279 * Initialize the corb registers for operations but do not start it up yet. 1280 * The CORB engine must not be running when this function is called. 1281 ****************************************************************************/ 1282static void 1283hdac_corb_init(struct hdac_softc *sc) 1284{ 1285 uint8_t corbsize; 1286 uint64_t corbpaddr; 1287 1288 /* Setup the CORB size. */ 1289 switch (sc->corb_size) { 1290 case 256: 1291 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1292 break; 1293 case 16: 1294 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1295 break; 1296 case 2: 1297 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1298 break; 1299 default: 1300 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1301 } 1302 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1303 1304 /* Setup the CORB Address in the hdac */ 1305 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1306 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1307 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1308 1309 /* Set the WP and RP */ 1310 sc->corb_wp = 0; 1311 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1312 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1313 /* 1314 * The HDA specification indicates that the CORBRPRST bit will always 1315 * read as zero. Unfortunately, it seems that at least the 82801G 1316 * doesn't reset the bit to zero, which stalls the corb engine. 1317 * manually reset the bit to zero before continuing. 1318 */ 1319 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1320 1321 /* Enable CORB error reporting */ 1322#if 0 1323 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1324#endif 1325} 1326 1327/**************************************************************************** 1328 * void hdac_rirb_init(struct hdac_softc *) 1329 * 1330 * Initialize the rirb registers for operations but do not start it up yet. 1331 * The RIRB engine must not be running when this function is called. 1332 ****************************************************************************/ 1333static void 1334hdac_rirb_init(struct hdac_softc *sc) 1335{ 1336 uint8_t rirbsize; 1337 uint64_t rirbpaddr; 1338 1339 /* Setup the RIRB size. */ 1340 switch (sc->rirb_size) { 1341 case 256: 1342 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1343 break; 1344 case 16: 1345 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1346 break; 1347 case 2: 1348 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1349 break; 1350 default: 1351 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1352 } 1353 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1354 1355 /* Setup the RIRB Address in the hdac */ 1356 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1357 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1358 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1359 1360 /* Setup the WP and RP */ 1361 sc->rirb_rp = 0; 1362 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1363 1364 /* Setup the interrupt threshold */ 1365 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1366 1367 /* Enable Overrun and response received reporting */ 1368#if 0 1369 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1370 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1371#else 1372 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1373#endif 1374 1375 /* 1376 * Make sure that the Host CPU cache doesn't contain any dirty 1377 * cache lines that falls in the rirb. If I understood correctly, it 1378 * should be sufficient to do this only once as the rirb is purely 1379 * read-only from now on. 1380 */ 1381 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1382 BUS_DMASYNC_PREREAD); 1383} 1384 1385/**************************************************************************** 1386 * void hdac_corb_start(hdac_softc *) 1387 * 1388 * Startup the corb DMA engine 1389 ****************************************************************************/ 1390static void 1391hdac_corb_start(struct hdac_softc *sc) 1392{ 1393 uint32_t corbctl; 1394 1395 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1396 corbctl |= HDAC_CORBCTL_CORBRUN; 1397 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1398} 1399 1400/**************************************************************************** 1401 * void hdac_rirb_start(hdac_softc *) 1402 * 1403 * Startup the rirb DMA engine 1404 ****************************************************************************/ 1405static void 1406hdac_rirb_start(struct hdac_softc *sc) 1407{ 1408 uint32_t rirbctl; 1409 1410 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1411 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1412 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1413} 1414 1415 1416/**************************************************************************** 1417 * void hdac_scan_codecs(struct hdac_softc *) 1418 * 1419 * Scan the bus for available codecs. 1420 ****************************************************************************/ 1421static void 1422hdac_scan_codecs(struct hdac_softc *sc) 1423{ 1424 struct hdac_codec *codec; 1425 int i; 1426 uint16_t statests; 1427 1428 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1429 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1430 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1431 /* We have found a codec. */ 1432 hdac_unlock(sc); 1433 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1434 M_HDAC, M_ZERO | M_NOWAIT); 1435 hdac_lock(sc); 1436 if (codec == NULL) { 1437 device_printf(sc->dev, 1438 "Unable to allocate memory for codec\n"); 1439 continue; 1440 } 1441 codec->verbs_sent = 0; 1442 codec->sc = sc; 1443 codec->cad = i; 1444 sc->codecs[i] = codec; 1445 if (hdac_probe_codec(codec) != 0) 1446 break; 1447 } 1448 } 1449 /* All codecs have been probed, now try to attach drivers to them */ 1450 /* bus_generic_attach(sc->dev); */ 1451} 1452 1453/**************************************************************************** 1454 * void hdac_probe_codec(struct hdac_softc *, int) 1455 * 1456 * Probe a the given codec_id for available function groups. 1457 ****************************************************************************/ 1458static int 1459hdac_probe_codec(struct hdac_codec *codec) 1460{ 1461 struct hdac_softc *sc = codec->sc; 1462 struct hdac_devinfo *devinfo; 1463 uint32_t vendorid, revisionid, subnode; 1464 int startnode; 1465 int endnode; 1466 int i; 1467 nid_t cad = codec->cad; 1468 1469 HDA_BOOTVERBOSE( 1470 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1471 ); 1472 vendorid = hdac_command(sc, 1473 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1474 cad); 1475 revisionid = hdac_command(sc, 1476 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1477 cad); 1478 subnode = hdac_command(sc, 1479 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1480 cad); 1481 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1482 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1483 1484 HDA_BOOTVERBOSE( 1485 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1486 startnode, endnode); 1487 ); 1488 for (i = startnode; i < endnode; i++) { 1489 devinfo = hdac_probe_function(codec, i); 1490 if (devinfo != NULL) { 1491 /* XXX Ignore other FG. */ 1492 devinfo->vendor_id = 1493 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1494 devinfo->device_id = 1495 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1496 devinfo->revision_id = 1497 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1498 devinfo->stepping_id = 1499 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1500 HDA_BOOTVERBOSE( 1501 device_printf(sc->dev, 1502 "HDA_DEBUG: \tFound AFG nid=%d " 1503 "[startnode=%d endnode=%d]\n", 1504 devinfo->nid, startnode, endnode); 1505 ); 1506 return (1); 1507 } 1508 } 1509 1510 HDA_BOOTVERBOSE( 1511 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1512 ); 1513 return (0); 1514} 1515 1516static struct hdac_devinfo * 1517hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1518{ 1519 struct hdac_softc *sc = codec->sc; 1520 struct hdac_devinfo *devinfo; 1521 uint32_t fctgrptype; 1522 nid_t cad = codec->cad; 1523 1524 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1525 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1526 1527 /* XXX For now, ignore other FG. */ 1528 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1529 return (NULL); 1530 1531 hdac_unlock(sc); 1532 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1533 M_NOWAIT | M_ZERO); 1534 hdac_lock(sc); 1535 if (devinfo == NULL) { 1536 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1537 __func__); 1538 return (NULL); 1539 } 1540 1541 devinfo->nid = nid; 1542 devinfo->node_type = fctgrptype; 1543 devinfo->codec = codec; 1544 1545 hdac_add_child(sc, devinfo); 1546 1547 return (devinfo); 1548} 1549 1550static void 1551hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1552{ 1553 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1554 device_set_ivars(devinfo->dev, (void *)devinfo); 1555 /* XXX - Print more information when booting verbose??? */ 1556} 1557 1558static void 1559hdac_widget_connection_parse(struct hdac_widget *w) 1560{ 1561 struct hdac_softc *sc = w->devinfo->codec->sc; 1562 uint32_t res; 1563 int i, j, max, found, entnum, cnid; 1564 nid_t cad = w->devinfo->codec->cad; 1565 nid_t nid = w->nid; 1566 1567 res = hdac_command(sc, 1568 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1569 1570 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1571 1572 if (w->nconns < 1) 1573 return; 1574 1575 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1576 res = 0; 1577 i = 0; 1578 found = 0; 1579 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1580 1581 while (i < w->nconns) { 1582 res = hdac_command(sc, 1583 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1584 for (j = 0; j < entnum; j++) { 1585 cnid = res; 1586 cnid >>= (32 / entnum) * j; 1587 cnid &= (1 << (32 / entnum)) - 1; 1588 if (cnid == 0) 1589 continue; 1590 if (found > max) { 1591 device_printf(sc->dev, 1592 "node %d: Adding %d: " 1593 "Max connection reached!\n", 1594 nid, cnid); 1595 continue; 1596 } 1597 w->conns[found++] = cnid; 1598 } 1599 i += entnum; 1600 } 1601 1602 HDA_BOOTVERBOSE( 1603 if (w->nconns != found) { 1604 device_printf(sc->dev, 1605 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1606 "length=%d != found=%d\n", 1607 nid, w->nconns, found); 1608 } 1609 ); 1610} 1611 1612static uint32_t 1613hdac_widget_pin_getconfig(struct hdac_widget *w) 1614{ 1615 struct hdac_softc *sc; 1616 uint32_t config, id; 1617 nid_t cad, nid; 1618 1619 sc = w->devinfo->codec->sc; 1620 cad = w->devinfo->codec->cad; 1621 nid = w->nid; 1622 id = hdac_codec_id(w->devinfo); 1623 1624 config = hdac_command(sc, 1625 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1626 cad); 1627 /* 1628 * XXX REWRITE!!!! Don't argue! 1629 */ 1630 if (id == HDA_CODEC_ALC880 && 1631 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1632 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1633 /* 1634 * Super broken BIOS 1635 */ 1636 switch (nid) { 1637 case 20: 1638 break; 1639 case 21: 1640 break; 1641 case 22: 1642 break; 1643 case 23: 1644 break; 1645 case 24: /* MIC1 */ 1646 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1647 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1648 break; 1649 case 25: /* XXX MIC2 */ 1650 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1651 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1652 break; 1653 case 26: /* LINE1 */ 1654 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1655 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1656 break; 1657 case 27: /* XXX LINE2 */ 1658 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1659 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1660 break; 1661 case 28: /* CD */ 1662 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1663 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1664 break; 1665 case 30: 1666 break; 1667 case 31: 1668 break; 1669 default: 1670 break; 1671 } 1672 } 1673 1674 return (config); 1675} 1676 1677static void 1678hdac_widget_pin_parse(struct hdac_widget *w) 1679{ 1680 struct hdac_softc *sc = w->devinfo->codec->sc; 1681 uint32_t config, pincap; 1682 char *devstr, *connstr; 1683 nid_t cad = w->devinfo->codec->cad; 1684 nid_t nid = w->nid; 1685 1686 config = hdac_widget_pin_getconfig(w); 1687 w->wclass.pin.config = config; 1688 1689 pincap = hdac_command(sc, 1690 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1691 w->wclass.pin.cap = pincap; 1692 1693 w->wclass.pin.ctrl = hdac_command(sc, 1694 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1695 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1696 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1697 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1698 1699 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1700 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1701 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1702 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1703 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1704 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1705 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1706 w->param.eapdbtl = hdac_command(sc, 1707 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1708 w->param.eapdbtl &= 0x7; 1709 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1710 } else 1711 w->param.eapdbtl = HDAC_INVALID; 1712 1713 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1714 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1715 devstr = "line out"; 1716 break; 1717 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1718 devstr = "speaker"; 1719 break; 1720 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1721 devstr = "headphones out"; 1722 break; 1723 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1724 devstr = "CD"; 1725 break; 1726 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1727 devstr = "SPDIF out"; 1728 break; 1729 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1730 devstr = "digital (other) out"; 1731 break; 1732 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1733 devstr = "modem, line side"; 1734 break; 1735 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1736 devstr = "modem, handset side"; 1737 break; 1738 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1739 devstr = "line in"; 1740 break; 1741 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1742 devstr = "AUX"; 1743 break; 1744 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1745 devstr = "Mic in"; 1746 break; 1747 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1748 devstr = "telephony"; 1749 break; 1750 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1751 devstr = "SPDIF in"; 1752 break; 1753 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1754 devstr = "digital (other) in"; 1755 break; 1756 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1757 devstr = "other"; 1758 break; 1759 default: 1760 devstr = "unknown"; 1761 break; 1762 } 1763 1764 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1765 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1766 connstr = "jack"; 1767 break; 1768 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1769 connstr = "none"; 1770 break; 1771 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1772 connstr = "fixed"; 1773 break; 1774 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1775 connstr = "jack / fixed"; 1776 break; 1777 default: 1778 connstr = "unknown"; 1779 break; 1780 } 1781 1782 strlcat(w->name, ": ", sizeof(w->name)); 1783 strlcat(w->name, devstr, sizeof(w->name)); 1784 strlcat(w->name, " (", sizeof(w->name)); 1785 strlcat(w->name, connstr, sizeof(w->name)); 1786 strlcat(w->name, ")", sizeof(w->name)); 1787} 1788 1789static void 1790hdac_widget_parse(struct hdac_widget *w) 1791{ 1792 struct hdac_softc *sc = w->devinfo->codec->sc; 1793 uint32_t wcap, cap; 1794 char *typestr; 1795 nid_t cad = w->devinfo->codec->cad; 1796 nid_t nid = w->nid; 1797 1798 wcap = hdac_command(sc, 1799 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1800 cad); 1801 w->param.widget_cap = wcap; 1802 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1803 1804 switch (w->type) { 1805 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1806 typestr = "audio output"; 1807 break; 1808 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1809 typestr = "audio input"; 1810 break; 1811 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1812 typestr = "audio mixer"; 1813 break; 1814 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1815 typestr = "audio selector"; 1816 break; 1817 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1818 typestr = "pin"; 1819 break; 1820 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1821 typestr = "power widget"; 1822 break; 1823 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1824 typestr = "volume widget"; 1825 break; 1826 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1827 typestr = "beep widget"; 1828 break; 1829 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1830 typestr = "vendor widget"; 1831 break; 1832 default: 1833 typestr = "unknown type"; 1834 break; 1835 } 1836 1837 strlcpy(w->name, typestr, sizeof(w->name)); 1838 1839 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1840 hdac_command(sc, 1841 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1842 cad); 1843 DELAY(1000); 1844 } 1845 1846 hdac_widget_connection_parse(w); 1847 1848 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1849 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1850 w->param.outamp_cap = 1851 hdac_command(sc, 1852 HDA_CMD_GET_PARAMETER(cad, nid, 1853 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1854 else 1855 w->param.outamp_cap = 1856 w->devinfo->function.audio.outamp_cap; 1857 } else 1858 w->param.outamp_cap = 0; 1859 1860 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1861 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1862 w->param.inamp_cap = 1863 hdac_command(sc, 1864 HDA_CMD_GET_PARAMETER(cad, nid, 1865 HDA_PARAM_INPUT_AMP_CAP), cad); 1866 else 1867 w->param.inamp_cap = 1868 w->devinfo->function.audio.inamp_cap; 1869 } else 1870 w->param.inamp_cap = 0; 1871 1872 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1873 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1874 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1875 cap = hdac_command(sc, 1876 HDA_CMD_GET_PARAMETER(cad, nid, 1877 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1878 w->param.supp_stream_formats = (cap != 0) ? cap : 1879 w->devinfo->function.audio.supp_stream_formats; 1880 cap = hdac_command(sc, 1881 HDA_CMD_GET_PARAMETER(cad, nid, 1882 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1883 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1884 w->devinfo->function.audio.supp_pcm_size_rate; 1885 } else { 1886 w->param.supp_stream_formats = 1887 w->devinfo->function.audio.supp_stream_formats; 1888 w->param.supp_pcm_size_rate = 1889 w->devinfo->function.audio.supp_pcm_size_rate; 1890 } 1891 } else { 1892 w->param.supp_stream_formats = 0; 1893 w->param.supp_pcm_size_rate = 0; 1894 } 1895 1896 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1897 hdac_widget_pin_parse(w); 1898} 1899 1900static struct hdac_widget * 1901hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1902{ 1903 if (devinfo == NULL || devinfo->widget == NULL || 1904 nid < devinfo->startnode || nid >= devinfo->endnode) 1905 return (NULL); 1906 return (&devinfo->widget[nid - devinfo->startnode]); 1907} 1908 1909static void 1910hdac_stream_stop(struct hdac_chan *ch) 1911{ 1912 struct hdac_softc *sc = ch->devinfo->codec->sc; 1913 uint32_t ctl; 1914 1915 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1916 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1917 HDAC_SDCTL_RUN); 1918 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1919 1920 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1921 ctl &= ~(1 << (ch->off >> 5)); 1922 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1923} 1924 1925static void 1926hdac_stream_start(struct hdac_chan *ch) 1927{ 1928 struct hdac_softc *sc = ch->devinfo->codec->sc; 1929 uint32_t ctl; 1930 1931 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1932 ctl |= 1 << (ch->off >> 5); 1933 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1934 1935 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1936 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1937 HDAC_SDCTL_RUN; 1938 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1939} 1940 1941static void 1942hdac_stream_reset(struct hdac_chan *ch) 1943{ 1944 struct hdac_softc *sc = ch->devinfo->codec->sc; 1945 int timeout = 1000; 1946 int to = timeout; 1947 uint32_t ctl; 1948 1949 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1950 ctl |= HDAC_SDCTL_SRST; 1951 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1952 do { 1953 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1954 if (ctl & HDAC_SDCTL_SRST) 1955 break; 1956 DELAY(10); 1957 } while (--to); 1958 if (!(ctl & HDAC_SDCTL_SRST)) { 1959 device_printf(sc->dev, "timeout in reset\n"); 1960 } 1961 ctl &= ~HDAC_SDCTL_SRST; 1962 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1963 to = timeout; 1964 do { 1965 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1966 if (!(ctl & HDAC_SDCTL_SRST)) 1967 break; 1968 DELAY(10); 1969 } while (--to); 1970 if (ctl & HDAC_SDCTL_SRST) 1971 device_printf(sc->dev, "can't reset!\n"); 1972} 1973 1974static void 1975hdac_stream_setid(struct hdac_chan *ch) 1976{ 1977 struct hdac_softc *sc = ch->devinfo->codec->sc; 1978 uint32_t ctl; 1979 1980 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 1981 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1982 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 1983 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 1984} 1985 1986static void 1987hdac_bdl_setup(struct hdac_chan *ch) 1988{ 1989 struct hdac_softc *sc = ch->devinfo->codec->sc; 1990 uint64_t addr; 1991 int blks, size, blocksize; 1992 struct hdac_bdle *bdle; 1993 int i; 1994 1995 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 1996 size = sndbuf_getsize(ch->b); 1997 blocksize = sndbuf_getblksz(ch->b); 1998 blks = size / blocksize; 1999 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr; 2000 2001 for (i = 0; i < blks; i++, bdle++) { 2002 bdle->addrl = (uint32_t)addr; 2003 bdle->addrh = (uint32_t)(addr >> 32); 2004 bdle->len = blocksize; 2005 bdle->ioc = 1; 2006 2007 addr += blocksize; 2008 } 2009 2010 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size); 2011 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1); 2012 addr = ch->bdl_dma.dma_paddr; 2013 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2014 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2015} 2016 2017static int 2018hdac_bdl_alloc(struct hdac_chan *ch) 2019{ 2020 struct hdac_softc *sc = ch->devinfo->codec->sc; 2021 int rc; 2022 2023 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2024 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2025 if (rc) { 2026 device_printf(sc->dev, "can't alloc bdl\n"); 2027 return (rc); 2028 } 2029 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2030 2031 return (0); 2032} 2033 2034static void 2035hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2036 int index, int lmute, int rmute, 2037 int left, int right, int dir) 2038{ 2039 uint16_t v = 0; 2040 2041 if (sc == NULL) 2042 return; 2043 2044 if (left != right || lmute != rmute) { 2045 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2046 (lmute << 7) | left; 2047 hdac_command(sc, 2048 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2049 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2050 (rmute << 7) | right; 2051 } else 2052 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2053 (lmute << 7) | left; 2054 2055 hdac_command(sc, 2056 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2057} 2058 2059static void 2060hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2061 int left, int right) 2062{ 2063 struct hdac_softc *sc; 2064 nid_t nid, cad; 2065 int lmute, rmute; 2066 2067 if (ctl == NULL || ctl->widget == NULL || 2068 ctl->widget->devinfo == NULL || 2069 ctl->widget->devinfo->codec == NULL || 2070 ctl->widget->devinfo->codec->sc == NULL) 2071 return; 2072 2073 sc = ctl->widget->devinfo->codec->sc; 2074 cad = ctl->widget->devinfo->codec->cad; 2075 nid = ctl->widget->nid; 2076 2077 if (mute == HDA_AMP_MUTE_DEFAULT) { 2078 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2079 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2080 } else { 2081 lmute = HDA_AMP_LEFT_MUTED(mute); 2082 rmute = HDA_AMP_RIGHT_MUTED(mute); 2083 } 2084 2085 if (ctl->dir & HDA_CTL_OUT) 2086 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2087 lmute, rmute, left, right, 0); 2088 if (ctl->dir & HDA_CTL_IN) 2089 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2090 lmute, rmute, left, right, 1); 2091 ctl->left = left; 2092 ctl->right = right; 2093} 2094 2095static void 2096hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2097{ 2098 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2099 return; 2100 hdac_command(w->devinfo->codec->sc, 2101 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2102 w->nid, index), w->devinfo->codec->cad); 2103 w->selconn = index; 2104} 2105 2106 2107/**************************************************************************** 2108 * uint32_t hdac_command_sendone_internal 2109 * 2110 * Wrapper function that sends only one command to a given codec 2111 ****************************************************************************/ 2112static uint32_t 2113hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2114{ 2115 struct hdac_command_list cl; 2116 uint32_t response = HDAC_INVALID; 2117 2118 if (!hdac_lockowned(sc)) 2119 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2120 cl.num_commands = 1; 2121 cl.verbs = &verb; 2122 cl.responses = &response; 2123 2124 hdac_command_send_internal(sc, &cl, cad); 2125 2126 return (response); 2127} 2128 2129/**************************************************************************** 2130 * hdac_command_send_internal 2131 * 2132 * Send a command list to the codec via the corb. We queue as much verbs as 2133 * we can and msleep on the codec. When the interrupt get the responses 2134 * back from the rirb, it will wake us up so we can queue the remaining verbs 2135 * if any. 2136 ****************************************************************************/ 2137static void 2138hdac_command_send_internal(struct hdac_softc *sc, 2139 struct hdac_command_list *commands, nid_t cad) 2140{ 2141 struct hdac_codec *codec; 2142 int corbrp; 2143 uint32_t *corb; 2144 uint8_t rirbwp; 2145 int timeout; 2146 int retry = 10; 2147 struct hdac_rirb *rirb_base, *rirb; 2148 nid_t ucad; 2149 uint32_t utag; 2150 2151 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL) 2152 return; 2153 2154 codec = sc->codecs[cad]; 2155 codec->commands = commands; 2156 codec->responses_received = 0; 2157 codec->verbs_sent = 0; 2158 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2159 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2160 2161 do { 2162 if (codec->verbs_sent != commands->num_commands) { 2163 /* Queue as many verbs as possible */ 2164 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2165 bus_dmamap_sync(sc->corb_dma.dma_tag, 2166 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2167 while (codec->verbs_sent != commands->num_commands && 2168 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2169 sc->corb_wp++; 2170 sc->corb_wp %= sc->corb_size; 2171 corb[sc->corb_wp] = 2172 commands->verbs[codec->verbs_sent++]; 2173 } 2174 2175 /* Send the verbs to the codecs */ 2176 bus_dmamap_sync(sc->corb_dma.dma_tag, 2177 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2178 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2179 } 2180 2181 timeout = 1000; 2182 do { 2183 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2184 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2185 BUS_DMASYNC_POSTREAD); 2186 if (sc->rirb_rp != rirbwp) { 2187 do { 2188 sc->rirb_rp++; 2189 sc->rirb_rp %= sc->rirb_size; 2190 rirb = &rirb_base[sc->rirb_rp]; 2191 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2192 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2193 utag = rirb->response >> 26; 2194 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 2195 sc->codecs[ucad] != NULL) { 2196 sc->unsolq[sc->unsolq_wp++] = 2197 (ucad << 16) | 2198 (utag & 0xffff); 2199 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2200 } 2201 } else if (codec->responses_received < commands->num_commands) 2202 codec->commands->responses[codec->responses_received++] = 2203 rirb->response; 2204 } while (sc->rirb_rp != rirbwp); 2205 break; 2206 } 2207 DELAY(10); 2208 } while (--timeout); 2209 } while ((codec->verbs_sent != commands->num_commands || 2210 codec->responses_received != commands->num_commands) && 2211 --retry); 2212 2213 if (retry == 0) 2214 device_printf(sc->dev, 2215 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2216 __func__, commands->num_commands, 2217 codec->verbs_sent, codec->responses_received); 2218 2219 codec->verbs_sent = 0; 2220 2221 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2222 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2223 while (sc->unsolq_rp != sc->unsolq_wp) { 2224 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 2225 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2226 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2227 hdac_unsolicited_handler(sc->codecs[ucad], utag); 2228 } 2229 sc->unsolq_st = HDAC_UNSOLQ_READY; 2230 } 2231} 2232 2233 2234/**************************************************************************** 2235 * Device Methods 2236 ****************************************************************************/ 2237 2238/**************************************************************************** 2239 * int hdac_probe(device_t) 2240 * 2241 * Probe for the presence of an hdac. If none is found, check for a generic 2242 * match using the subclass of the device. 2243 ****************************************************************************/ 2244static int 2245hdac_probe(device_t dev) 2246{ 2247 int i, result; 2248 uint32_t model; 2249 uint16_t class, subclass; 2250 char desc[64]; 2251 2252 model = (uint32_t)pci_get_device(dev) << 16; 2253 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2254 class = pci_get_class(dev); 2255 subclass = pci_get_subclass(dev); 2256 2257 bzero(desc, sizeof(desc)); 2258 result = ENXIO; 2259 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2260 if (hdac_devices[i].model == model) { 2261 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2262 result = BUS_PROBE_DEFAULT; 2263 break; 2264 } 2265 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2266 class == PCIC_MULTIMEDIA && 2267 subclass == PCIS_MULTIMEDIA_HDA) { 2268 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2269 result = BUS_PROBE_GENERIC; 2270 break; 2271 } 2272 } 2273 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2274 subclass == PCIS_MULTIMEDIA_HDA) { 2275 strlcpy(desc, "Generic", sizeof(desc)); 2276 result = BUS_PROBE_GENERIC; 2277 } 2278 if (result != ENXIO) { 2279 strlcat(desc, " High Definition Audio Controller", 2280 sizeof(desc)); 2281 device_set_desc_copy(dev, desc); 2282 } 2283 2284 return (result); 2285} 2286 2287static void * 2288hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2289 struct pcm_channel *c, int dir) 2290{ 2291 struct hdac_devinfo *devinfo = data; 2292 struct hdac_softc *sc = devinfo->codec->sc; 2293 struct hdac_chan *ch; 2294 2295 hdac_lock(sc); 2296 if (dir == PCMDIR_PLAY) { 2297 ch = &sc->play; 2298 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2299 ch->dir = PCMDIR_PLAY; 2300 ch->sid = ++sc->streamcnt; 2301 devinfo->function.audio.playcnt++; 2302 } else { 2303 ch = &sc->rec; 2304 ch->off = devinfo->function.audio.reccnt << 5; 2305 ch->dir = PCMDIR_REC; 2306 ch->sid = ++sc->streamcnt; 2307 devinfo->function.audio.reccnt++; 2308 } 2309 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2310 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2311 ch->pcmrates[0] = 48000; 2312 ch->pcmrates[1] = 0; 2313 } 2314 ch->b = b; 2315 ch->c = c; 2316 ch->devinfo = devinfo; 2317 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2318 ch->blkcnt = sc->chan_blkcnt; 2319 hdac_unlock(sc); 2320 2321 if (hdac_bdl_alloc(ch) != 0) { 2322 ch->blkcnt = 0; 2323 return (NULL); 2324 } 2325 2326 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2327 return (NULL); 2328 2329 hdac_dma_nocache(ch->b->buf); 2330 2331 return (ch); 2332} 2333 2334static int 2335hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2336{ 2337 struct hdac_chan *ch = data; 2338 int i; 2339 2340 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2341 if (format == ch->caps.fmtlist[i]) { 2342 ch->fmt = format; 2343 return (0); 2344 } 2345 } 2346 2347 return (EINVAL); 2348} 2349 2350static int 2351hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2352{ 2353 struct hdac_chan *ch = data; 2354 uint32_t spd = 0; 2355 int i; 2356 2357 for (i = 0; ch->pcmrates[i] != 0; i++) { 2358 spd = ch->pcmrates[i]; 2359 if (spd >= speed) 2360 break; 2361 } 2362 2363 if (spd == 0) 2364 ch->spd = 48000; 2365 else 2366 ch->spd = spd; 2367 2368 return (ch->spd); 2369} 2370 2371static void 2372hdac_stream_setup(struct hdac_chan *ch) 2373{ 2374 struct hdac_softc *sc = ch->devinfo->codec->sc; 2375 int i; 2376 nid_t cad = ch->devinfo->codec->cad; 2377 uint16_t fmt; 2378 2379 fmt = 0; 2380 if (ch->fmt & AFMT_S16_LE) 2381 fmt |= ch->bit16 << 4; 2382 else if (ch->fmt & AFMT_S32_LE) 2383 fmt |= ch->bit32 << 4; 2384 else 2385 fmt |= 1 << 4; 2386 2387 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2388 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2389 fmt |= hda_rate_tab[i].base; 2390 fmt |= hda_rate_tab[i].mul; 2391 fmt |= hda_rate_tab[i].div; 2392 break; 2393 } 2394 } 2395 2396 if (ch->fmt & AFMT_STEREO) 2397 fmt |= 1; 2398 2399 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2400 2401 for (i = 0; ch->io[i] != -1; i++) { 2402 HDA_BOOTVERBOSE( 2403 device_printf(sc->dev, 2404 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2405 "fmt=0x%08x\n", 2406 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2407 ch->io[i], fmt); 2408 ); 2409 hdac_command(sc, 2410 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2411 hdac_command(sc, 2412 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2413 ch->sid << 4), cad); 2414 } 2415} 2416 2417static int 2418hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 2419{ 2420 struct hdac_chan *ch = data; 2421 2422 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz); 2423 2424 return (ch->blksz); 2425} 2426 2427static void 2428hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2429{ 2430 struct hdac_devinfo *devinfo = ch->devinfo; 2431 nid_t cad = devinfo->codec->cad; 2432 int i; 2433 2434 hdac_stream_stop(ch); 2435 2436 for (i = 0; ch->io[i] != -1; i++) { 2437 hdac_command(sc, 2438 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2439 0), cad); 2440 } 2441} 2442 2443static void 2444hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2445{ 2446 ch->ptr = 0; 2447 ch->prevptr = 0; 2448 hdac_stream_stop(ch); 2449 hdac_stream_reset(ch); 2450 hdac_bdl_setup(ch); 2451 hdac_stream_setid(ch); 2452 hdac_stream_setup(ch); 2453 hdac_stream_start(ch); 2454} 2455 2456static int 2457hdac_channel_trigger(kobj_t obj, void *data, int go) 2458{ 2459 struct hdac_chan *ch = data; 2460 struct hdac_softc *sc = ch->devinfo->codec->sc; 2461 2462 hdac_lock(sc); 2463 switch (go) { 2464 case PCMTRIG_START: 2465 hdac_channel_start(sc, ch); 2466 break; 2467 case PCMTRIG_STOP: 2468 case PCMTRIG_ABORT: 2469 hdac_channel_stop(sc, ch); 2470 break; 2471 } 2472 hdac_unlock(sc); 2473 2474 return (0); 2475} 2476 2477static int 2478hdac_channel_getptr(kobj_t obj, void *data) 2479{ 2480 struct hdac_chan *ch = data; 2481 struct hdac_softc *sc = ch->devinfo->codec->sc; 2482 int sz, delta; 2483 uint32_t ptr; 2484 2485 hdac_lock(sc); 2486 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2487 hdac_unlock(sc); 2488 2489 sz = sndbuf_getsize(ch->b); 2490 ptr %= sz; 2491 2492 if (ch->dir == PCMDIR_REC) { 2493 delta = ptr % sndbuf_getblksz(ch->b); 2494 if (delta != 0) { 2495 ptr -= delta; 2496 if (ptr < delta) 2497 ptr = sz - delta; 2498 else 2499 ptr -= delta; 2500 } 2501 } 2502 2503 return (ptr); 2504} 2505 2506static struct pcmchan_caps * 2507hdac_channel_getcaps(kobj_t obj, void *data) 2508{ 2509 return (&((struct hdac_chan *)data)->caps); 2510} 2511 2512static kobj_method_t hdac_channel_methods[] = { 2513 KOBJMETHOD(channel_init, hdac_channel_init), 2514 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2515 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2516 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2517 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2518 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2519 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2520 { 0, 0 } 2521}; 2522CHANNEL_DECLARE(hdac_channel); 2523 2524static int 2525hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2526{ 2527 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2528 struct hdac_softc *sc = devinfo->codec->sc; 2529 struct hdac_widget *w, *cw; 2530 struct hdac_audio_ctl *ctl; 2531 uint32_t mask, recmask, id; 2532 int i, j, softpcmvol; 2533 nid_t cad; 2534 2535 hdac_lock(sc); 2536 2537 mask = 0; 2538 recmask = 0; 2539 2540 id = hdac_codec_id(devinfo); 2541 cad = devinfo->codec->cad; 2542 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2543 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2544 sc->pci_subvendor) && 2545 hdac_hp_switch[i].id == id)) 2546 continue; 2547 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2548 if (w != NULL && w->enable != 0 2549 && w->type == 2550 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2551 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2552 hdac_command(sc, 2553 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2554 w->nid, 2555 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2556 HDAC_UNSOLTAG_EVENT_HP), cad); 2557 hdac_hp_switch_handler(devinfo); 2558 HDA_BOOTVERBOSE( 2559 device_printf(sc->dev, 2560 "HDA_DEBUG: Enabling headphone/speaker " 2561 "audio routing switching:\n"); 2562 device_printf(sc->dev, 2563 "HDA_DEBUG: \tindex=%d nid=%d " 2564 "pci_subvendor=0x%08x " 2565 "codec=0x%08x\n", 2566 i, w->nid, sc->pci_subvendor, id); 2567 ); 2568 } 2569 break; 2570 } 2571 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2572 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2573 sc->pci_subvendor) && 2574 hdac_eapd_switch[i].id == id)) 2575 continue; 2576 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2577 if (w == NULL || w->enable == 0) 2578 break; 2579 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2580 w->param.eapdbtl == HDAC_INVALID) 2581 break; 2582 mask |= SOUND_MASK_OGAIN; 2583 break; 2584 } 2585 2586 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2587 w = hdac_widget_get(devinfo, i); 2588 if (w == NULL || w->enable == 0) 2589 continue; 2590 mask |= w->ctlflags; 2591 if (!(w->pflags & HDA_ADC_RECSEL)) 2592 continue; 2593 for (j = 0; j < w->nconns; j++) { 2594 cw = hdac_widget_get(devinfo, w->conns[j]); 2595 if (cw == NULL || cw->enable == 0) 2596 continue; 2597 recmask |= cw->ctlflags; 2598 } 2599 } 2600 2601 if (!(mask & SOUND_MASK_PCM)) { 2602 softpcmvol = 1; 2603 mask |= SOUND_MASK_PCM; 2604 } else 2605 softpcmvol = (devinfo->function.audio.quirks & 2606 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2607 2608 i = 0; 2609 ctl = NULL; 2610 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2611 if (ctl->widget == NULL || ctl->enable == 0) 2612 continue; 2613 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2614 continue; 2615 if (ctl->step > 0) 2616 break; 2617 } 2618 2619 if (softpcmvol == 1 || ctl == NULL) { 2620 struct snddev_info *d = NULL; 2621 d = device_get_softc(sc->dev); 2622 if (d != NULL) { 2623 d->flags |= SD_F_SOFTPCMVOL; 2624 HDA_BOOTVERBOSE( 2625 device_printf(sc->dev, 2626 "HDA_DEBUG: %s Soft PCM volume\n", 2627 (softpcmvol == 1) ? 2628 "Forcing" : "Enabling"); 2629 ); 2630 } 2631 i = 0; 2632 /* 2633 * XXX Temporary quirk for STAC9220, until the parser 2634 * become smarter. 2635 */ 2636 if (id == HDA_CODEC_STAC9220) { 2637 mask |= SOUND_MASK_VOLUME; 2638 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2639 NULL) { 2640 if (ctl->widget == NULL || ctl->enable == 0) 2641 continue; 2642 if (ctl->widget->nid == 11 && ctl->index == 0) { 2643 ctl->ossmask = SOUND_MASK_VOLUME; 2644 ctl->ossval = 100 | (100 << 8); 2645 } else 2646 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2647 } 2648 } else { 2649 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2650 SOUND_MASK_PCM); 2651 if (!(mask & SOUND_MASK_VOLUME)) 2652 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2653 SOUND_MIXER_NONE); 2654 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2655 NULL) { 2656 if (ctl->widget == NULL || ctl->enable == 0) 2657 continue; 2658 if (!HDA_FLAG_MATCH(ctl->ossmask, 2659 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2660 continue; 2661 if (!(ctl->mute == 1 && ctl->step == 0)) 2662 ctl->enable = 0; 2663 } 2664 } 2665 } 2666 2667 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2668 2669 mix_setrecdevs(m, recmask); 2670 mix_setdevs(m, mask); 2671 2672 hdac_unlock(sc); 2673 2674 return (0); 2675} 2676 2677static int 2678hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2679 unsigned left, unsigned right) 2680{ 2681 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2682 struct hdac_softc *sc = devinfo->codec->sc; 2683 struct hdac_widget *w; 2684 struct hdac_audio_ctl *ctl; 2685 uint32_t id, mute; 2686 int lvol, rvol, mlvol, mrvol; 2687 int i = 0; 2688 2689 hdac_lock(sc); 2690 if (dev == SOUND_MIXER_OGAIN) { 2691 uint32_t orig; 2692 int set; 2693 /*if (left != right || !(left == 0 || left == 1)) { 2694 hdac_unlock(sc); 2695 return (-1); 2696 }*/ 2697 id = hdac_codec_id(devinfo); 2698 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2699 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2700 sc->pci_subvendor) && 2701 hdac_eapd_switch[i].id == id) 2702 break; 2703 } 2704 if (i >= HDAC_EAPD_SWITCH_LEN) { 2705 hdac_unlock(sc); 2706 return (-1); 2707 } 2708 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2709 if (w == NULL || 2710 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2711 w->param.eapdbtl == HDAC_INVALID) { 2712 hdac_unlock(sc); 2713 return (-1); 2714 } 2715 orig = w->param.eapdbtl; 2716 set = (left != 0) ? 1 : 0; 2717 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 2718 set ^= 1; 2719 if (set == 0) 2720 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2721 else 2722 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2723 if (orig != w->param.eapdbtl) { 2724 if (hdac_eapd_switch[i].hp_switch != 0) 2725 hdac_hp_switch_handler(devinfo); 2726 hdac_command(sc, 2727 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2728 w->nid, w->param.eapdbtl), devinfo->codec->cad); 2729 } 2730 hdac_unlock(sc); 2731 return (left | (left << 8)); 2732 } 2733 if (dev == SOUND_MIXER_VOLUME) 2734 devinfo->function.audio.mvol = left | (right << 8); 2735 2736 mlvol = devinfo->function.audio.mvol & 0x7f; 2737 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2738 lvol = 0; 2739 rvol = 0; 2740 2741 i = 0; 2742 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2743 if (ctl->widget == NULL || ctl->enable == 0 || 2744 !(ctl->ossmask & (1 << dev))) 2745 continue; 2746 switch (dev) { 2747 case SOUND_MIXER_VOLUME: 2748 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2749 lvol = (lvol * ctl->step) / 100; 2750 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2751 rvol = (rvol * ctl->step) / 100; 2752 break; 2753 default: 2754 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2755 lvol = (left * mlvol) / 100; 2756 lvol = (lvol * ctl->step) / 100; 2757 rvol = (right * mrvol) / 100; 2758 rvol = (rvol * ctl->step) / 100; 2759 } else { 2760 lvol = (left * ctl->step) / 100; 2761 rvol = (right * ctl->step) / 100; 2762 } 2763 ctl->ossval = left | (right << 8); 2764 break; 2765 } 2766 mute = 0; 2767 if (ctl->step < 1) { 2768 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2769 (ctl->muted & HDA_AMP_MUTE_LEFT); 2770 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2771 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2772 } else { 2773 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2774 (ctl->muted & HDA_AMP_MUTE_LEFT); 2775 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2776 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2777 } 2778 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2779 } 2780 hdac_unlock(sc); 2781 2782 return (left | (right << 8)); 2783} 2784 2785static int 2786hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2787{ 2788 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2789 struct hdac_widget *w, *cw; 2790 struct hdac_softc *sc = devinfo->codec->sc; 2791 uint32_t ret = src, target; 2792 int i, j; 2793 2794 target = 0; 2795 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2796 if (src & (1 << i)) { 2797 target = 1 << i; 2798 break; 2799 } 2800 } 2801 2802 hdac_lock(sc); 2803 2804 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2805 w = hdac_widget_get(devinfo, i); 2806 if (w == NULL || w->enable == 0) 2807 continue; 2808 if (!(w->pflags & HDA_ADC_RECSEL)) 2809 continue; 2810 for (j = 0; j < w->nconns; j++) { 2811 cw = hdac_widget_get(devinfo, w->conns[j]); 2812 if (cw == NULL || cw->enable == 0) 2813 continue; 2814 if ((target == SOUND_MASK_VOLUME && 2815 cw->type != 2816 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 2817 (target != SOUND_MASK_VOLUME && 2818 cw->type == 2819 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 2820 continue; 2821 if (cw->ctlflags & target) { 2822 hdac_widget_connection_select(w, j); 2823 ret = target; 2824 j += w->nconns; 2825 } 2826 } 2827 } 2828 2829 hdac_unlock(sc); 2830 2831 return (ret); 2832} 2833 2834static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 2835 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 2836 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 2837 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 2838 { 0, 0 } 2839}; 2840MIXER_DECLARE(hdac_audio_ctl_ossmixer); 2841 2842/**************************************************************************** 2843 * int hdac_attach(device_t) 2844 * 2845 * Attach the device into the kernel. Interrupts usually won't be enabled 2846 * when this function is called. Setup everything that doesn't require 2847 * interrupts and defer probing of codecs until interrupts are enabled. 2848 ****************************************************************************/ 2849static int 2850hdac_attach(device_t dev) 2851{ 2852 struct hdac_softc *sc; 2853 int result; 2854 int i = 0; 2855 2856 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 2857 if (sc == NULL) { 2858 device_printf(dev, "cannot allocate softc\n"); 2859 return (ENOMEM); 2860 } 2861 2862 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 2863 if (sc->lock == NULL) { 2864 device_printf(dev, "mutex creation failed\n"); 2865 free(sc, M_DEVBUF); 2866 return (ENOMEM); 2867 } 2868 2869 sc->dev = dev; 2870 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 2871 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 2872 2873 sc->chan_size = pcm_getbuffersize(dev, 2874 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT); 2875 if (resource_int_value(device_get_name(sc->dev), 2876 device_get_unit(sc->dev), "blocksize", &i) == 0 && 2877 i > 0) { 2878 sc->chan_blkcnt = sc->chan_size / i; 2879 i = 0; 2880 while (sc->chan_blkcnt >> i) 2881 i++; 2882 sc->chan_blkcnt = 1 << (i - 1); 2883 if (sc->chan_blkcnt < HDA_BDL_MIN) 2884 sc->chan_blkcnt = HDA_BDL_MIN; 2885 else if (sc->chan_blkcnt > HDA_BDL_MAX) 2886 sc->chan_blkcnt = HDA_BDL_MAX; 2887 } else 2888 sc->chan_blkcnt = HDA_BDL_DEFAULT; 2889 2890 result = bus_dma_tag_create(NULL, /* parent */ 2891 HDAC_DMA_ALIGNMENT, /* alignment */ 2892 0, /* boundary */ 2893 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2894 BUS_SPACE_MAXADDR, /* highaddr */ 2895 NULL, /* filtfunc */ 2896 NULL, /* fistfuncarg */ 2897 sc->chan_size, /* maxsize */ 2898 1, /* nsegments */ 2899 sc->chan_size, /* maxsegsz */ 2900 0, /* flags */ 2901 NULL, /* lockfunc */ 2902 NULL, /* lockfuncarg */ 2903 &sc->chan_dmat); /* dmat */ 2904 if (result != 0) { 2905 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 2906 __func__, result); 2907 snd_mtxfree(sc->lock); 2908 free(sc, M_DEVBUF); 2909 return (ENXIO); 2910 } 2911 2912 2913 sc->hdabus = NULL; 2914 for (i = 0; i < HDAC_CODEC_MAX; i++) 2915 sc->codecs[i] = NULL; 2916 2917 pci_enable_busmaster(dev); 2918 2919 /* Allocate resources */ 2920 result = hdac_mem_alloc(sc); 2921 if (result != 0) 2922 goto hdac_attach_fail; 2923 result = hdac_irq_alloc(sc); 2924 if (result != 0) 2925 goto hdac_attach_fail; 2926 2927 /* Get Capabilities */ 2928 result = hdac_get_capabilities(sc); 2929 if (result != 0) 2930 goto hdac_attach_fail; 2931 2932 /* Allocate CORB and RIRB dma memory */ 2933 result = hdac_dma_alloc(sc, &sc->corb_dma, 2934 sc->corb_size * sizeof(uint32_t)); 2935 if (result != 0) 2936 goto hdac_attach_fail; 2937 result = hdac_dma_alloc(sc, &sc->rirb_dma, 2938 sc->rirb_size * sizeof(struct hdac_rirb)); 2939 if (result != 0) 2940 goto hdac_attach_fail; 2941 2942 /* Quiesce everything */ 2943 hdac_reset(sc); 2944 2945 /* Disable PCI-Express QOS */ 2946 pci_write_config(sc->dev, 0x44, 2947 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 2948 2949 /* Initialize the CORB and RIRB */ 2950 hdac_corb_init(sc); 2951 hdac_rirb_init(sc); 2952 2953 /* Defer remaining of initialization until interrupts are enabled */ 2954 sc->intrhook.ich_func = hdac_attach2; 2955 sc->intrhook.ich_arg = (void *)sc; 2956 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 2957 sc->intrhook.ich_func = NULL; 2958 hdac_attach2((void *)sc); 2959 } 2960 2961 return (0); 2962 2963hdac_attach_fail: 2964 hdac_dma_free(&sc->rirb_dma); 2965 hdac_dma_free(&sc->corb_dma); 2966 hdac_irq_free(sc); 2967 hdac_mem_free(sc); 2968 snd_mtxfree(sc->lock); 2969 free(sc, M_DEVBUF); 2970 2971 return (ENXIO); 2972} 2973 2974static void 2975hdac_audio_parse(struct hdac_devinfo *devinfo) 2976{ 2977 struct hdac_softc *sc = devinfo->codec->sc; 2978 struct hdac_widget *w; 2979 uint32_t res; 2980 int i; 2981 nid_t cad, nid; 2982 2983 cad = devinfo->codec->cad; 2984 nid = devinfo->nid; 2985 2986 hdac_command(sc, 2987 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 2988 2989 DELAY(100); 2990 2991 res = hdac_command(sc, 2992 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2993 2994 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2995 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2996 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2997 2998 HDA_BOOTVERBOSE( 2999 device_printf(sc->dev, " Vendor: 0x%08x\n", 3000 devinfo->vendor_id); 3001 device_printf(sc->dev, " Device: 0x%08x\n", 3002 devinfo->device_id); 3003 device_printf(sc->dev, " Revision: 0x%08x\n", 3004 devinfo->revision_id); 3005 device_printf(sc->dev, " Stepping: 0x%08x\n", 3006 devinfo->stepping_id); 3007 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3008 sc->pci_subvendor); 3009 device_printf(sc->dev, " Nodes: start=%d " 3010 "endnode=%d total=%d\n", 3011 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3012 ); 3013 3014 res = hdac_command(sc, 3015 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3016 cad); 3017 devinfo->function.audio.supp_stream_formats = res; 3018 3019 res = hdac_command(sc, 3020 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3021 cad); 3022 devinfo->function.audio.supp_pcm_size_rate = res; 3023 3024 res = hdac_command(sc, 3025 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3026 cad); 3027 devinfo->function.audio.outamp_cap = res; 3028 3029 res = hdac_command(sc, 3030 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3031 cad); 3032 devinfo->function.audio.inamp_cap = res; 3033 3034 if (devinfo->nodecnt > 0) { 3035 hdac_unlock(sc); 3036 devinfo->widget = (struct hdac_widget *)malloc( 3037 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3038 M_NOWAIT | M_ZERO); 3039 hdac_lock(sc); 3040 } else 3041 devinfo->widget = NULL; 3042 3043 if (devinfo->widget == NULL) { 3044 device_printf(sc->dev, "unable to allocate widgets!\n"); 3045 devinfo->endnode = devinfo->startnode; 3046 devinfo->nodecnt = 0; 3047 return; 3048 } 3049 3050 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3051 w = hdac_widget_get(devinfo, i); 3052 if (w == NULL) 3053 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3054 else { 3055 w->devinfo = devinfo; 3056 w->nid = i; 3057 w->enable = 1; 3058 w->selconn = -1; 3059 w->pflags = 0; 3060 w->ctlflags = 0; 3061 w->param.eapdbtl = HDAC_INVALID; 3062 hdac_widget_parse(w); 3063 } 3064 } 3065} 3066 3067static void 3068hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3069{ 3070 struct hdac_softc *sc = devinfo->codec->sc; 3071 struct hdac_audio_ctl *ctls; 3072 struct hdac_widget *w, *cw; 3073 int i, j, cnt, max, ocap, icap; 3074 int mute, offset, step, size; 3075 3076 /* XXX This is redundant */ 3077 max = 0; 3078 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3079 w = hdac_widget_get(devinfo, i); 3080 if (w == NULL || w->enable == 0) 3081 continue; 3082 if (w->param.outamp_cap != 0) 3083 max++; 3084 if (w->param.inamp_cap != 0) { 3085 switch (w->type) { 3086 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3087 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3088 for (j = 0; j < w->nconns; j++) { 3089 cw = hdac_widget_get(devinfo, 3090 w->conns[j]); 3091 if (cw == NULL || cw->enable == 0) 3092 continue; 3093 max++; 3094 } 3095 break; 3096 default: 3097 max++; 3098 break; 3099 } 3100 } 3101 } 3102 3103 devinfo->function.audio.ctlcnt = max; 3104 3105 if (max < 1) 3106 return; 3107 3108 hdac_unlock(sc); 3109 ctls = (struct hdac_audio_ctl *)malloc( 3110 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3111 hdac_lock(sc); 3112 3113 if (ctls == NULL) { 3114 /* Blekh! */ 3115 device_printf(sc->dev, "unable to allocate ctls!\n"); 3116 devinfo->function.audio.ctlcnt = 0; 3117 return; 3118 } 3119 3120 cnt = 0; 3121 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3122 if (cnt >= max) { 3123 device_printf(sc->dev, "%s: Ctl overflow!\n", 3124 __func__); 3125 break; 3126 } 3127 w = hdac_widget_get(devinfo, i); 3128 if (w == NULL || w->enable == 0) 3129 continue; 3130 ocap = w->param.outamp_cap; 3131 icap = w->param.inamp_cap; 3132 if (ocap != 0) { 3133 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3134 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3135 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3136 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3137 /*if (offset > step) { 3138 HDA_BOOTVERBOSE( 3139 device_printf(sc->dev, 3140 "HDA_DEBUG: BUGGY outamp: nid=%d " 3141 "[offset=%d > step=%d]\n", 3142 w->nid, offset, step); 3143 ); 3144 offset = step; 3145 }*/ 3146 ctls[cnt].enable = 1; 3147 ctls[cnt].widget = w; 3148 ctls[cnt].mute = mute; 3149 ctls[cnt].step = step; 3150 ctls[cnt].size = size; 3151 ctls[cnt].offset = offset; 3152 ctls[cnt].left = offset; 3153 ctls[cnt].right = offset; 3154 ctls[cnt++].dir = HDA_CTL_OUT; 3155 } 3156 3157 if (icap != 0) { 3158 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3159 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3160 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3161 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3162 /*if (offset > step) { 3163 HDA_BOOTVERBOSE( 3164 device_printf(sc->dev, 3165 "HDA_DEBUG: BUGGY inamp: nid=%d " 3166 "[offset=%d > step=%d]\n", 3167 w->nid, offset, step); 3168 ); 3169 offset = step; 3170 }*/ 3171 switch (w->type) { 3172 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3173 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3174 for (j = 0; j < w->nconns; j++) { 3175 if (cnt >= max) { 3176 device_printf(sc->dev, 3177 "%s: Ctl overflow!\n", 3178 __func__); 3179 break; 3180 } 3181 cw = hdac_widget_get(devinfo, 3182 w->conns[j]); 3183 if (cw == NULL || cw->enable == 0) 3184 continue; 3185 ctls[cnt].enable = 1; 3186 ctls[cnt].widget = w; 3187 ctls[cnt].childwidget = cw; 3188 ctls[cnt].index = j; 3189 ctls[cnt].mute = mute; 3190 ctls[cnt].step = step; 3191 ctls[cnt].size = size; 3192 ctls[cnt].offset = offset; 3193 ctls[cnt].left = offset; 3194 ctls[cnt].right = offset; 3195 ctls[cnt++].dir = HDA_CTL_IN; 3196 } 3197 break; 3198 default: 3199 if (cnt >= max) { 3200 device_printf(sc->dev, 3201 "%s: Ctl overflow!\n", 3202 __func__); 3203 break; 3204 } 3205 ctls[cnt].enable = 1; 3206 ctls[cnt].widget = w; 3207 ctls[cnt].mute = mute; 3208 ctls[cnt].step = step; 3209 ctls[cnt].size = size; 3210 ctls[cnt].offset = offset; 3211 ctls[cnt].left = offset; 3212 ctls[cnt].right = offset; 3213 ctls[cnt++].dir = HDA_CTL_IN; 3214 break; 3215 } 3216 } 3217 } 3218 3219 devinfo->function.audio.ctl = ctls; 3220} 3221 3222static const struct { 3223 uint32_t model; 3224 uint32_t id; 3225 uint32_t set, unset; 3226} hdac_quirks[] = { 3227 /* 3228 * XXX Fixed rate quirk. Other than 48000 3229 * sounds pretty much like train wreck. 3230 * 3231 * XXX Force stereo quirk. Monoural recording / playback 3232 * on few codecs (especially ALC880) seems broken or 3233 * perhaps unsupported. 3234 */ 3235 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3236 HDA_QUIRK_FIXEDRATE | HDA_QUIRK_FORCESTEREO, 0 }, 3237 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3238 HDA_QUIRK_GPIO1, 0 }, 3239 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3240 HDA_QUIRK_GPIO1, 0 }, 3241 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3242 HDA_QUIRK_EAPDINV, 0 }, 3243 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3244 0, HDA_QUIRK_FORCESTEREO }, 3245 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3246 HDA_QUIRK_SOFTPCMVOL, 0 } 3247}; 3248#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3249 3250static void 3251hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3252{ 3253 struct hdac_widget *w; 3254 uint32_t id, subvendor; 3255 int i; 3256 3257 id = hdac_codec_id(devinfo); 3258 subvendor = devinfo->codec->sc->pci_subvendor; 3259 3260 /* 3261 * Quirks 3262 */ 3263 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3264 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3265 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3266 continue; 3267 if (hdac_quirks[i].set != 0) 3268 devinfo->function.audio.quirks |= 3269 hdac_quirks[i].set; 3270 if (hdac_quirks[i].unset != 0) 3271 devinfo->function.audio.quirks &= 3272 ~(hdac_quirks[i].unset); 3273 } 3274 3275 switch (id) { 3276 case HDA_CODEC_ALC260: 3277 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3278 w = hdac_widget_get(devinfo, i); 3279 if (w == NULL || w->enable == 0) 3280 continue; 3281 if (w->type != 3282 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3283 continue; 3284 if (w->nid != 5) 3285 w->enable = 0; 3286 } 3287 break; 3288 case HDA_CODEC_ALC880: 3289 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3290 w = hdac_widget_get(devinfo, i); 3291 if (w == NULL || w->enable == 0) 3292 continue; 3293 if (w->type == 3294 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3295 w->nid != 9 && w->nid != 29) { 3296 w->enable = 0; 3297 } else if (w->type != 3298 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3299 w->nid == 29) { 3300 w->type = 3301 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3302 w->param.widget_cap &= 3303 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3304 w->param.widget_cap |= 3305 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3306 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3307 strlcpy(w->name, "beep widget", sizeof(w->name)); 3308 } 3309 } 3310 break; 3311 case HDA_CODEC_AD1981HD: 3312 w = hdac_widget_get(devinfo, 11); 3313 if (w != NULL && w->enable != 0 && w->nconns > 3) 3314 w->selconn = 3; 3315 if (subvendor == IBM_M52_SUBVENDOR) { 3316 struct hdac_audio_ctl *ctl; 3317 3318 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3319 if (ctl != NULL) 3320 ctl->ossmask = SOUND_MASK_SPEAKER; 3321 } 3322 break; 3323 case HDA_CODEC_AD1986A: 3324 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3325 w = hdac_widget_get(devinfo, i); 3326 if (w == NULL || w->enable == 0) 3327 continue; 3328 if (w->type != 3329 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3330 continue; 3331 if (w->nid != 3) 3332 w->enable = 0; 3333 } 3334 break; 3335 case HDA_CODEC_STAC9221: 3336 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3337 w = hdac_widget_get(devinfo, i); 3338 if (w == NULL || w->enable == 0) 3339 continue; 3340 if (w->type != 3341 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3342 continue; 3343 if (w->nid != 2) 3344 w->enable = 0; 3345 } 3346 break; 3347 case HDA_CODEC_STAC9221D: 3348 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3349 w = hdac_widget_get(devinfo, i); 3350 if (w == NULL || w->enable == 0) 3351 continue; 3352 if (w->type == 3353 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3354 w->nid != 6) 3355 w->enable = 0; 3356 3357 } 3358 break; 3359 default: 3360 break; 3361 } 3362} 3363 3364static int 3365hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3366{ 3367 int *dev = &devinfo->function.audio.ossidx; 3368 3369 while (*dev < SOUND_MIXER_NRDEVICES) { 3370 switch (*dev) { 3371 case SOUND_MIXER_VOLUME: 3372 case SOUND_MIXER_BASS: 3373 case SOUND_MIXER_TREBLE: 3374 case SOUND_MIXER_PCM: 3375 case SOUND_MIXER_SPEAKER: 3376 case SOUND_MIXER_LINE: 3377 case SOUND_MIXER_MIC: 3378 case SOUND_MIXER_CD: 3379 case SOUND_MIXER_RECLEV: 3380 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3381 (*dev)++; 3382 break; 3383 default: 3384 return (*dev)++; 3385 break; 3386 } 3387 } 3388 3389 return (-1); 3390} 3391 3392static int 3393hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3394{ 3395 struct hdac_widget *w; 3396 int i, ret = 0; 3397 3398 if (depth > HDA_PARSE_MAXDEPTH) 3399 return (0); 3400 w = hdac_widget_get(devinfo, nid); 3401 if (w == NULL || w->enable == 0) 3402 return (0); 3403 switch (w->type) { 3404 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3405 w->pflags |= HDA_DAC_PATH; 3406 ret = 1; 3407 break; 3408 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3409 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3410 for (i = 0; i < w->nconns; i++) { 3411 if (hdac_widget_find_dac_path(devinfo, 3412 w->conns[i], depth + 1) != 0) { 3413 if (w->selconn == -1) 3414 w->selconn = i; 3415 ret = 1; 3416 w->pflags |= HDA_DAC_PATH; 3417 } 3418 } 3419 break; 3420 default: 3421 break; 3422 } 3423 return (ret); 3424} 3425 3426static int 3427hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3428{ 3429 struct hdac_widget *w; 3430 int i, conndev, ret = 0; 3431 3432 if (depth > HDA_PARSE_MAXDEPTH) 3433 return (0); 3434 w = hdac_widget_get(devinfo, nid); 3435 if (w == NULL || w->enable == 0) 3436 return (0); 3437 switch (w->type) { 3438 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3439 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3440 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3441 for (i = 0; i < w->nconns; i++) { 3442 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3443 depth + 1) != 0) { 3444 if (w->selconn == -1) 3445 w->selconn = i; 3446 w->pflags |= HDA_ADC_PATH; 3447 ret = 1; 3448 } 3449 } 3450 break; 3451 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3452 conndev = w->wclass.pin.config & 3453 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3454 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3455 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3456 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3457 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3458 w->pflags |= HDA_ADC_PATH; 3459 ret = 1; 3460 } 3461 break; 3462 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3463 if (w->pflags & HDA_DAC_PATH) { 3464 w->pflags |= HDA_ADC_PATH; 3465 ret = 1; 3466 } 3467 break;*/ 3468 default: 3469 break; 3470 } 3471 return (ret); 3472} 3473 3474static uint32_t 3475hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3476 nid_t nid, nid_t pnid, int index, int depth) 3477{ 3478 struct hdac_widget *w, *pw; 3479 struct hdac_audio_ctl *ctl; 3480 uint32_t fl = 0; 3481 int i, ossdev, conndev, strategy; 3482 3483 if (depth > HDA_PARSE_MAXDEPTH) 3484 return (0); 3485 3486 w = hdac_widget_get(devinfo, nid); 3487 if (w == NULL || w->enable == 0) 3488 return (0); 3489 3490 pw = hdac_widget_get(devinfo, pnid); 3491 strategy = devinfo->function.audio.parsing_strategy; 3492 3493 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3494 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3495 for (i = 0; i < w->nconns; i++) { 3496 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3497 w->nid, i, depth + 1); 3498 } 3499 w->ctlflags |= fl; 3500 return (fl); 3501 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3502 (w->pflags & HDA_DAC_PATH)) { 3503 i = 0; 3504 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3505 if (ctl->enable == 0 || ctl->widget == NULL) 3506 continue; 3507 /* XXX This should be compressed! */ 3508 if ((ctl->widget->nid == w->nid) || 3509 (ctl->widget->nid == pnid && ctl->index == index && 3510 (ctl->dir & HDA_CTL_IN)) || 3511 (ctl->widget->nid == pnid && pw != NULL && 3512 pw->type == 3513 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3514 (pw->nconns < 2 || pw->selconn == index || 3515 pw->selconn == -1) && 3516 (ctl->dir & HDA_CTL_OUT)) || 3517 (strategy == HDA_PARSE_DIRECT && 3518 ctl->widget->nid == w->nid)) { 3519 /*if (pw != NULL && pw->selconn == -1) 3520 pw->selconn = index; 3521 fl |= SOUND_MASK_VOLUME; 3522 fl |= SOUND_MASK_PCM; 3523 ctl->ossmask |= SOUND_MASK_VOLUME; 3524 ctl->ossmask |= SOUND_MASK_PCM; 3525 ctl->ossdev = SOUND_MIXER_PCM;*/ 3526 if (!(w->ctlflags & SOUND_MASK_PCM) || 3527 (pw != NULL && 3528 !(pw->ctlflags & SOUND_MASK_PCM))) { 3529 fl |= SOUND_MASK_VOLUME; 3530 fl |= SOUND_MASK_PCM; 3531 ctl->ossmask |= SOUND_MASK_VOLUME; 3532 ctl->ossmask |= SOUND_MASK_PCM; 3533 ctl->ossdev = SOUND_MIXER_PCM; 3534 w->ctlflags |= SOUND_MASK_VOLUME; 3535 w->ctlflags |= SOUND_MASK_PCM; 3536 if (pw != NULL) { 3537 if (pw->selconn == -1) 3538 pw->selconn = index; 3539 pw->ctlflags |= 3540 SOUND_MASK_VOLUME; 3541 pw->ctlflags |= 3542 SOUND_MASK_PCM; 3543 } 3544 } 3545 } 3546 } 3547 w->ctlflags |= fl; 3548 return (fl); 3549 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 3550 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3551 (w->pflags & HDA_ADC_PATH)) { 3552 conndev = w->wclass.pin.config & 3553 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3554 i = 0; 3555 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3556 if (ctl->enable == 0 || ctl->widget == NULL) 3557 continue; 3558 /* XXX This should be compressed! */ 3559 if (((ctl->widget->nid == pnid && ctl->index == index && 3560 (ctl->dir & HDA_CTL_IN)) || 3561 (ctl->widget->nid == pnid && pw != NULL && 3562 pw->type == 3563 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3564 (pw->nconns < 2 || pw->selconn == index || 3565 pw->selconn == -1) && 3566 (ctl->dir & HDA_CTL_OUT)) || 3567 (strategy == HDA_PARSE_DIRECT && 3568 ctl->widget->nid == w->nid)) && 3569 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3570 if (pw != NULL && pw->selconn == -1) 3571 pw->selconn = index; 3572 ossdev = 0; 3573 switch (conndev) { 3574 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3575 ossdev = SOUND_MIXER_MIC; 3576 break; 3577 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3578 ossdev = SOUND_MIXER_LINE; 3579 break; 3580 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3581 ossdev = SOUND_MIXER_CD; 3582 break; 3583 default: 3584 ossdev = 3585 hdac_audio_ctl_ossmixer_getnextdev( 3586 devinfo); 3587 if (ossdev < 0) 3588 ossdev = 0; 3589 break; 3590 } 3591 if (strategy == HDA_PARSE_MIXER) { 3592 fl |= SOUND_MASK_VOLUME; 3593 ctl->ossmask |= SOUND_MASK_VOLUME; 3594 } 3595 fl |= 1 << ossdev; 3596 ctl->ossmask |= 1 << ossdev; 3597 ctl->ossdev = ossdev; 3598 } 3599 } 3600 w->ctlflags |= fl; 3601 return (fl); 3602 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3603 i = 0; 3604 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3605 if (ctl->enable == 0 || ctl->widget == NULL) 3606 continue; 3607 /* XXX This should be compressed! */ 3608 if (((ctl->widget->nid == pnid && ctl->index == index && 3609 (ctl->dir & HDA_CTL_IN)) || 3610 (ctl->widget->nid == pnid && pw != NULL && 3611 pw->type == 3612 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3613 (pw->nconns < 2 || pw->selconn == index || 3614 pw->selconn == -1) && 3615 (ctl->dir & HDA_CTL_OUT)) || 3616 (strategy == HDA_PARSE_DIRECT && 3617 ctl->widget->nid == w->nid)) && 3618 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3619 if (pw != NULL && pw->selconn == -1) 3620 pw->selconn = index; 3621 fl |= SOUND_MASK_VOLUME; 3622 fl |= SOUND_MASK_SPEAKER; 3623 ctl->ossmask |= SOUND_MASK_VOLUME; 3624 ctl->ossmask |= SOUND_MASK_SPEAKER; 3625 ctl->ossdev = SOUND_MIXER_SPEAKER; 3626 } 3627 } 3628 w->ctlflags |= fl; 3629 return (fl); 3630 } 3631 return (0); 3632} 3633 3634static uint32_t 3635hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3636{ 3637 struct hdac_widget *w, *cw; 3638 struct hdac_audio_ctl *ctl; 3639 uint32_t fl; 3640 int i; 3641 3642 if (depth > HDA_PARSE_MAXDEPTH) 3643 return (0); 3644 3645 w = hdac_widget_get(devinfo, nid); 3646 if (w == NULL || w->enable == 0) 3647 return (0); 3648 /*if (!(w->pflags & HDA_ADC_PATH)) 3649 return (0); 3650 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3651 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3652 return (0);*/ 3653 i = 0; 3654 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3655 if (ctl->enable == 0 || ctl->widget == NULL) 3656 continue; 3657 if (ctl->widget->nid == nid) { 3658 ctl->ossmask |= SOUND_MASK_RECLEV; 3659 w->ctlflags |= SOUND_MASK_RECLEV; 3660 return (SOUND_MASK_RECLEV); 3661 } 3662 } 3663 for (i = 0; i < w->nconns; i++) { 3664 cw = hdac_widget_get(devinfo, w->conns[i]); 3665 if (cw == NULL || cw->enable == 0) 3666 continue; 3667 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3668 continue; 3669 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3670 if (fl != 0) { 3671 cw->ctlflags |= fl; 3672 w->ctlflags |= fl; 3673 return (fl); 3674 } 3675 } 3676 return (0); 3677} 3678 3679static int 3680hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3681{ 3682 struct hdac_widget *w, *cw; 3683 int i, child = 0; 3684 3685 if (depth > HDA_PARSE_MAXDEPTH) 3686 return (0); 3687 3688 w = hdac_widget_get(devinfo, nid); 3689 if (w == NULL || w->enable == 0) 3690 return (0); 3691 /*if (!(w->pflags & HDA_ADC_PATH)) 3692 return (0); 3693 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3694 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3695 return (0);*/ 3696 /* XXX weak! */ 3697 for (i = 0; i < w->nconns; i++) { 3698 cw = hdac_widget_get(devinfo, w->conns[i]); 3699 if (cw == NULL) 3700 continue; 3701 if (++child > 1) { 3702 w->pflags |= HDA_ADC_RECSEL; 3703 return (1); 3704 } 3705 } 3706 for (i = 0; i < w->nconns; i++) { 3707 if (hdac_audio_ctl_recsel_build(devinfo, 3708 w->conns[i], depth + 1) != 0) 3709 return (1); 3710 } 3711 return (0); 3712} 3713 3714static int 3715hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3716{ 3717 struct hdac_widget *w, *cw; 3718 int i, j, conndev, found_dac = 0; 3719 int strategy; 3720 3721 strategy = devinfo->function.audio.parsing_strategy; 3722 3723 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3724 w = hdac_widget_get(devinfo, i); 3725 if (w == NULL || w->enable == 0) 3726 continue; 3727 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3728 continue; 3729 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3730 continue; 3731 conndev = w->wclass.pin.config & 3732 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3733 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3734 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3735 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3736 continue; 3737 for (j = 0; j < w->nconns; j++) { 3738 cw = hdac_widget_get(devinfo, w->conns[j]); 3739 if (cw == NULL || cw->enable == 0) 3740 continue; 3741 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3742 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3743 cw->type == 3744 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3745 continue; 3746 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3747 != 0) { 3748 if (w->selconn == -1) 3749 w->selconn = j; 3750 w->pflags |= HDA_DAC_PATH; 3751 found_dac++; 3752 } 3753 } 3754 } 3755 3756 return (found_dac); 3757} 3758 3759static void 3760hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3761{ 3762 struct hdac_widget *w; 3763 struct hdac_audio_ctl *ctl; 3764 int i, j, dacs, strategy; 3765 3766 /* Construct DAC path */ 3767 strategy = HDA_PARSE_MIXER; 3768 devinfo->function.audio.parsing_strategy = strategy; 3769 HDA_BOOTVERBOSE( 3770 device_printf(devinfo->codec->sc->dev, 3771 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 3772 HDA_WIDGET_PARSER_REV); 3773 ); 3774 dacs = hdac_audio_build_tree_strategy(devinfo); 3775 if (dacs == 0) { 3776 HDA_BOOTVERBOSE( 3777 device_printf(devinfo->codec->sc->dev, 3778 "HDA_DEBUG: HWiP: 0 DAC path found! " 3779 "Retrying parser " 3780 "using HDA_PARSE_DIRECT strategy.\n"); 3781 ); 3782 strategy = HDA_PARSE_DIRECT; 3783 devinfo->function.audio.parsing_strategy = strategy; 3784 dacs = hdac_audio_build_tree_strategy(devinfo); 3785 } 3786 3787 HDA_BOOTVERBOSE( 3788 device_printf(devinfo->codec->sc->dev, 3789 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 3790 "strategy.\n", 3791 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 3792 ); 3793 3794 /* Construct ADC path */ 3795 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3796 w = hdac_widget_get(devinfo, i); 3797 if (w == NULL || w->enable == 0) 3798 continue; 3799 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3800 continue; 3801 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 3802 } 3803 3804 /* Output mixers */ 3805 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3806 w = hdac_widget_get(devinfo, i); 3807 if (w == NULL || w->enable == 0) 3808 continue; 3809 if ((strategy == HDA_PARSE_MIXER && 3810 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3811 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3812 && (w->pflags & HDA_DAC_PATH)) || 3813 (strategy == HDA_PARSE_DIRECT && (w->pflags & 3814 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 3815 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 3816 w->nid, devinfo->startnode - 1, 0, 0); 3817 } else if (w->type == 3818 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3819 j = 0; 3820 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 3821 NULL) { 3822 if (ctl->enable == 0 || ctl->widget == NULL) 3823 continue; 3824 if (ctl->widget->nid != w->nid) 3825 continue; 3826 ctl->ossmask |= SOUND_MASK_VOLUME; 3827 ctl->ossmask |= SOUND_MASK_SPEAKER; 3828 ctl->ossdev = SOUND_MIXER_SPEAKER; 3829 w->ctlflags |= SOUND_MASK_VOLUME; 3830 w->ctlflags |= SOUND_MASK_SPEAKER; 3831 } 3832 } 3833 } 3834 3835 /* Input mixers (rec) */ 3836 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3837 w = hdac_widget_get(devinfo, i); 3838 if (w == NULL || w->enable == 0) 3839 continue; 3840 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3841 w->pflags & HDA_ADC_PATH)) 3842 continue; 3843 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 3844 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 3845 } 3846} 3847 3848#define HDA_COMMIT_CONN (1 << 0) 3849#define HDA_COMMIT_CTRL (1 << 1) 3850#define HDA_COMMIT_EAPD (1 << 2) 3851#define HDA_COMMIT_GPIO (1 << 3) 3852#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 3853 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 3854 3855static void 3856hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 3857{ 3858 struct hdac_softc *sc = devinfo->codec->sc; 3859 struct hdac_widget *w; 3860 nid_t cad, nid; 3861 int i, gpioval; 3862 3863 if (!(cfl & HDA_COMMIT_ALL)) 3864 return; 3865 3866 cad = devinfo->codec->cad; 3867 3868 if (cfl & HDA_COMMIT_GPIO) { 3869 nid = devinfo->nid; 3870 for (i = 0; i < HDA_GPIO_MAX; i++) { 3871 if (!(devinfo->function.audio.quirks & (1 << i))) 3872 continue; 3873 gpioval = (1 << i) - 1; 3874 hdac_command(sc, 3875 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, gpioval), 3876 cad); 3877 hdac_command(sc, 3878 HDA_CMD_SET_GPIO_DIRECTION(cad, nid, gpioval), 3879 cad); 3880 hdac_command(sc, 3881 HDA_CMD_SET_GPIO_DATA(cad, nid, gpioval), 3882 cad); 3883 } 3884 } 3885 3886 for (i = 0; i < devinfo->nodecnt; i++) { 3887 w = &devinfo->widget[i]; 3888 if (w == NULL || w->enable == 0) 3889 continue; 3890 if (cfl & HDA_COMMIT_CONN) { 3891 if (w->selconn == -1) 3892 w->selconn = 0; 3893 if (w->nconns > 0) 3894 hdac_widget_connection_select(w, w->selconn); 3895 } 3896 if ((cfl & HDA_COMMIT_CTRL) && 3897 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 3898 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 3899 (HDA_DAC_PATH | HDA_ADC_PATH)) 3900 device_printf(sc->dev, "WARNING: node %d " 3901 "participate both for DAC/ADC!\n", w->nid); 3902 if (w->pflags & HDA_DAC_PATH) { 3903 w->wclass.pin.ctrl &= 3904 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 3905 if ((w->wclass.pin.config & 3906 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 3907 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 3908 w->wclass.pin.ctrl &= 3909 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 3910 } else if (w->pflags & HDA_ADC_PATH) { 3911 w->wclass.pin.ctrl &= 3912 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3913 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 3914 } else 3915 w->wclass.pin.ctrl &= ~( 3916 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 3917 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3918 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 3919 hdac_command(sc, 3920 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 3921 w->wclass.pin.ctrl), cad); 3922 } 3923 if ((cfl & HDA_COMMIT_EAPD) && 3924 w->param.eapdbtl != HDAC_INVALID) { 3925 if (devinfo->function.audio.quirks & 3926 HDA_QUIRK_EAPDINV) { 3927 if (w->param.eapdbtl & 3928 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) 3929 w->param.eapdbtl &= 3930 ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3931 else 3932 w->param.eapdbtl |= 3933 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3934 } 3935 hdac_command(sc, 3936 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 3937 w->param.eapdbtl), cad); 3938 3939 } 3940 DELAY(1000); 3941 } 3942} 3943 3944static void 3945hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 3946{ 3947 struct hdac_softc *sc = devinfo->codec->sc; 3948 struct hdac_audio_ctl *ctl; 3949 int i; 3950 3951 devinfo->function.audio.mvol = 100 | (100 << 8); 3952 i = 0; 3953 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3954 if (ctl->enable == 0 || ctl->widget == NULL) { 3955 HDA_BOOTVERBOSE( 3956 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3957 i, (ctl->widget != NULL) ? 3958 ctl->widget->nid : -1); 3959 if (ctl->childwidget != NULL) 3960 printf(" childnid=%d", 3961 ctl->childwidget->nid); 3962 if (ctl->widget == NULL) 3963 printf(" NULL WIDGET!"); 3964 printf(" DISABLED\n"); 3965 ); 3966 continue; 3967 } 3968 HDA_BOOTVERBOSE( 3969 if (ctl->ossmask == 0) { 3970 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3971 i, ctl->widget->nid); 3972 if (ctl->childwidget != NULL) 3973 printf(" childnid=%d", 3974 ctl->childwidget->nid); 3975 printf(" Bind to NONE\n"); 3976 } 3977 ); 3978 if (ctl->step > 0) { 3979 ctl->ossval = (ctl->left * 100) / ctl->step; 3980 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 3981 } else 3982 ctl->ossval = 0; 3983 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 3984 ctl->left, ctl->right); 3985 } 3986} 3987 3988static int 3989hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 3990{ 3991 struct hdac_chan *ch; 3992 struct hdac_widget *w; 3993 uint32_t cap, fmtcap, pcmcap, path; 3994 int i, type, ret, max; 3995 3996 if (dir == PCMDIR_PLAY) { 3997 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 3998 ch = &devinfo->codec->sc->play; 3999 path = HDA_DAC_PATH; 4000 } else { 4001 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4002 ch = &devinfo->codec->sc->rec; 4003 path = HDA_ADC_PATH; 4004 } 4005 4006 ch->caps = hdac_caps; 4007 ch->caps.fmtlist = ch->fmtlist; 4008 ch->bit16 = 1; 4009 ch->bit32 = 0; 4010 ch->pcmrates[0] = 48000; 4011 ch->pcmrates[1] = 0; 4012 4013 ret = 0; 4014 fmtcap = devinfo->function.audio.supp_stream_formats; 4015 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4016 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4017 4018 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4019 w = hdac_widget_get(devinfo, i); 4020 if (w == NULL || w->enable == 0 || w->type != type || 4021 !(w->pflags & path)) 4022 continue; 4023 cap = w->param.widget_cap; 4024 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4025 continue;*/ 4026 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4027 continue; 4028 cap = w->param.supp_stream_formats; 4029 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4030 } 4031 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4032 }*/ 4033 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4034 continue; 4035 ch->io[ret++] = i; 4036 fmtcap &= w->param.supp_stream_formats; 4037 pcmcap &= w->param.supp_pcm_size_rate; 4038 } 4039 ch->io[ret] = -1; 4040 4041 ch->supp_stream_formats = fmtcap; 4042 ch->supp_pcm_size_rate = pcmcap; 4043 4044 /* 4045 * 8bit = 0 4046 * 16bit = 1 4047 * 20bit = 2 4048 * 24bit = 3 4049 * 32bit = 4 4050 */ 4051 if (ret > 0) { 4052 cap = pcmcap; 4053 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4054 ch->bit16 = 1; 4055 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4056 ch->bit16 = 0; 4057 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4058 ch->bit32 = 4; 4059 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4060 ch->bit32 = 3; 4061 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4062 ch->bit32 = 2; 4063 i = 0; 4064 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4065 ch->fmtlist[i++] = AFMT_S16_LE; 4066 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4067 if (ch->bit32 > 0) { 4068 if (!(devinfo->function.audio.quirks & 4069 HDA_QUIRK_FORCESTEREO)) 4070 ch->fmtlist[i++] = AFMT_S32_LE; 4071 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4072 } 4073 ch->fmtlist[i] = 0; 4074 i = 0; 4075 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4076 ch->pcmrates[i++] = 8000; 4077 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4078 ch->pcmrates[i++] = 11025; 4079 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4080 ch->pcmrates[i++] = 16000; 4081 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4082 ch->pcmrates[i++] = 22050; 4083 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4084 ch->pcmrates[i++] = 32000; 4085 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4086 ch->pcmrates[i++] = 44100; 4087 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4088 ch->pcmrates[i++] = 48000; 4089 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4090 ch->pcmrates[i++] = 88200; 4091 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4092 ch->pcmrates[i++] = 96000; 4093 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4094 ch->pcmrates[i++] = 176400; 4095 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4096 ch->pcmrates[i++] = 192000; 4097 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4098 ch->pcmrates[i] = 0; 4099 if (i > 0) { 4100 ch->caps.minspeed = ch->pcmrates[0]; 4101 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4102 } 4103 } 4104 4105 return (ret); 4106} 4107 4108static void 4109hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4110{ 4111 struct hdac_audio_ctl *ctl; 4112 struct hdac_softc *sc = devinfo->codec->sc; 4113 int i; 4114 uint32_t fl = 0; 4115 4116 4117 if (flag == 0) { 4118 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4119 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4120 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4121 } 4122 4123 i = 0; 4124 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4125 if (ctl->enable == 0 || ctl->widget == NULL || 4126 ctl->widget->enable == 0) 4127 continue; 4128 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4129 (flag != 0 && (ctl->ossmask & flag))) { 4130 if (banner != NULL) { 4131 device_printf(sc->dev, "\n"); 4132 device_printf(sc->dev, "%s\n", banner); 4133 } 4134 goto hdac_ctl_dump_it_all; 4135 } 4136 } 4137 4138 return; 4139 4140hdac_ctl_dump_it_all: 4141 i = 0; 4142 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4143 if (ctl->enable == 0 || ctl->widget == NULL || 4144 ctl->widget->enable == 0) 4145 continue; 4146 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4147 (flag != 0 && (ctl->ossmask & flag)))) 4148 continue; 4149 if (flag == 0) { 4150 device_printf(sc->dev, "\n"); 4151 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4152 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4153 } 4154 device_printf(sc->dev, " |\n"); 4155 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4156 ctl->widget->nid, ctl->index); 4157 if (ctl->childwidget != NULL) 4158 printf("(nid: %2d) ", ctl->childwidget->nid); 4159 else 4160 printf(" "); 4161 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4162 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4163 ctl->ossmask); 4164 } 4165} 4166 4167static void 4168hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4169{ 4170 uint32_t cap; 4171 4172 cap = fcap; 4173 if (cap != 0) { 4174 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4175 device_printf(sc->dev, " Format:"); 4176 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4177 printf(" AC3"); 4178 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4179 printf(" FLOAT32"); 4180 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4181 printf(" PCM"); 4182 printf("\n"); 4183 } 4184 cap = pcmcap; 4185 if (cap != 0) { 4186 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4187 device_printf(sc->dev, " PCM size:"); 4188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4189 printf(" 8"); 4190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4191 printf(" 16"); 4192 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4193 printf(" 20"); 4194 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4195 printf(" 24"); 4196 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4197 printf(" 32"); 4198 printf("\n"); 4199 device_printf(sc->dev, " PCM rate:"); 4200 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4201 printf(" 8"); 4202 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4203 printf(" 11"); 4204 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4205 printf(" 16"); 4206 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4207 printf(" 22"); 4208 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4209 printf(" 32"); 4210 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4211 printf(" 44"); 4212 printf(" 48"); 4213 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4214 printf(" 88"); 4215 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4216 printf(" 96"); 4217 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4218 printf(" 176"); 4219 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4220 printf(" 192"); 4221 printf("\n"); 4222 } 4223} 4224 4225static void 4226hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4227{ 4228 uint32_t pincap, wcap; 4229 4230 pincap = w->wclass.pin.cap; 4231 wcap = w->param.widget_cap; 4232 4233 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4234 device_printf(sc->dev, " "); 4235 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4236 printf(" ISC"); 4237 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4238 printf(" TRQD"); 4239 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4240 printf(" PDC"); 4241 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4242 printf(" HP"); 4243 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4244 printf(" OUT"); 4245 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4246 printf(" IN"); 4247 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4248 printf(" BAL"); 4249 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4250 printf(" EAPD"); 4251 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4252 printf(" : UNSOL"); 4253 printf("\n"); 4254 device_printf(sc->dev, " Pin config: 0x%08x\n", 4255 w->wclass.pin.config); 4256 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4257 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4258 printf(" HP"); 4259 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4260 printf(" IN"); 4261 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4262 printf(" OUT"); 4263 printf("\n"); 4264} 4265 4266static void 4267hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4268{ 4269 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4270 device_printf(sc->dev, " " 4271 "mute=%d step=%d size=%d offset=%d\n", 4272 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4273 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4274 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4275 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4276} 4277 4278static void 4279hdac_dump_nodes(struct hdac_devinfo *devinfo) 4280{ 4281 struct hdac_softc *sc = devinfo->codec->sc; 4282 struct hdac_widget *w, *cw; 4283 int i, j; 4284 4285 device_printf(sc->dev, "\n"); 4286 device_printf(sc->dev, "Default Parameter\n"); 4287 device_printf(sc->dev, "-----------------\n"); 4288 hdac_dump_audio_formats(sc, 4289 devinfo->function.audio.supp_stream_formats, 4290 devinfo->function.audio.supp_pcm_size_rate); 4291 device_printf(sc->dev, " IN amp: 0x%08x\n", 4292 devinfo->function.audio.inamp_cap); 4293 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4294 devinfo->function.audio.outamp_cap); 4295 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4296 w = hdac_widget_get(devinfo, i); 4297 if (w == NULL) { 4298 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4299 continue; 4300 } 4301 device_printf(sc->dev, "\n"); 4302 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4303 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4304 "DIGITAL" : "ANALOG", 4305 (w->enable == 0) ? " [DISABLED]" : ""); 4306 device_printf(sc->dev, " name: %s\n", w->name); 4307 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4308 w->param.widget_cap); 4309 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4310 w->pflags); 4311 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4312 w->ctlflags); 4313 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4314 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4315 hdac_dump_audio_formats(sc, 4316 w->param.supp_stream_formats, 4317 w->param.supp_pcm_size_rate); 4318 } else if (w->type == 4319 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4320 hdac_dump_pin(sc, w); 4321 if (w->param.eapdbtl != HDAC_INVALID) 4322 device_printf(sc->dev, " EAPD: 0x%08x\n", 4323 w->param.eapdbtl); 4324 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4325 w->param.outamp_cap != 0) 4326 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4327 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4328 w->param.inamp_cap != 0) 4329 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4330 device_printf(sc->dev, " connections: %d\n", w->nconns); 4331 for (j = 0; j < w->nconns; j++) { 4332 cw = hdac_widget_get(devinfo, w->conns[j]); 4333 device_printf(sc->dev, " |\n"); 4334 device_printf(sc->dev, " + <- nid=%d [%s]", 4335 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4336 if (cw == NULL) 4337 printf(" [UNKNOWN]"); 4338 else if (cw->enable == 0) 4339 printf(" [DISABLED]"); 4340 if (w->nconns > 1 && w->selconn == j && w->type != 4341 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4342 printf(" (selected)"); 4343 printf("\n"); 4344 } 4345 } 4346 4347} 4348 4349static int 4350hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4351{ 4352 struct hdac_widget *w, *cw; 4353 struct hdac_softc *sc = devinfo->codec->sc; 4354 int i; 4355 4356 if (depth > HDA_PARSE_MAXDEPTH) 4357 return (0); 4358 4359 w = hdac_widget_get(devinfo, nid); 4360 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4361 return (0); 4362 4363 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4364 device_printf(sc->dev, "\n"); 4365 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4366 device_printf(sc->dev, " ^\n"); 4367 device_printf(sc->dev, " |\n"); 4368 device_printf(sc->dev, " +-----<------+\n"); 4369 } else { 4370 device_printf(sc->dev, " ^\n"); 4371 device_printf(sc->dev, " |\n"); 4372 device_printf(sc->dev, " "); 4373 printf(" nid=%d [%s]\n", w->nid, w->name); 4374 } 4375 4376 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4377 return (1); 4378 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4379 for (i = 0; i < w->nconns; i++) { 4380 cw = hdac_widget_get(devinfo, w->conns[i]); 4381 if (cw == NULL || cw->enable == 0 || cw->type == 4382 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4383 continue; 4384 if (hdac_dump_dac_internal(devinfo, cw->nid, 4385 depth + 1) != 0) 4386 return (1); 4387 } 4388 } else if ((w->type == 4389 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4390 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4391 w->selconn > -1 && w->selconn < w->nconns) { 4392 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4393 depth + 1) != 0) 4394 return (1); 4395 } 4396 4397 return (0); 4398} 4399 4400static void 4401hdac_dump_dac(struct hdac_devinfo *devinfo) 4402{ 4403 struct hdac_widget *w; 4404 struct hdac_softc *sc = devinfo->codec->sc; 4405 int i, printed = 0; 4406 4407 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4408 w = hdac_widget_get(devinfo, i); 4409 if (w == NULL || w->enable == 0) 4410 continue; 4411 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4412 !(w->pflags & HDA_DAC_PATH)) 4413 continue; 4414 if (printed == 0) { 4415 printed = 1; 4416 device_printf(sc->dev, "\n"); 4417 device_printf(sc->dev, "Playback path:\n"); 4418 } 4419 hdac_dump_dac_internal(devinfo, w->nid, 0); 4420 } 4421} 4422 4423static void 4424hdac_dump_adc(struct hdac_devinfo *devinfo) 4425{ 4426 struct hdac_widget *w, *cw; 4427 struct hdac_softc *sc = devinfo->codec->sc; 4428 int i, j; 4429 int printed = 0; 4430 char ossdevs[256]; 4431 4432 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4433 w = hdac_widget_get(devinfo, i); 4434 if (w == NULL || w->enable == 0) 4435 continue; 4436 if (!(w->pflags & HDA_ADC_RECSEL)) 4437 continue; 4438 if (printed == 0) { 4439 printed = 1; 4440 device_printf(sc->dev, "\n"); 4441 device_printf(sc->dev, "Recording sources:\n"); 4442 } 4443 device_printf(sc->dev, "\n"); 4444 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4445 for (j = 0; j < w->nconns; j++) { 4446 cw = hdac_widget_get(devinfo, w->conns[j]); 4447 if (cw == NULL || cw->enable == 0) 4448 continue; 4449 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4450 ossdevs, sizeof(ossdevs)); 4451 device_printf(sc->dev, " |\n"); 4452 device_printf(sc->dev, " + <- nid=%d [%s]", 4453 cw->nid, cw->name); 4454 if (strlen(ossdevs) > 0) { 4455 printf(" [recsrc: %s]", ossdevs); 4456 } 4457 printf("\n"); 4458 } 4459 } 4460} 4461 4462static void 4463hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4464{ 4465 nid_t *nids; 4466 4467 if (pcnt > 0) { 4468 device_printf(sc->dev, "\n"); 4469 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4470 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4471 sc->play.supp_pcm_size_rate); 4472 device_printf(sc->dev, " DAC:"); 4473 for (nids = sc->play.io; *nids != -1; nids++) 4474 printf(" %d", *nids); 4475 printf("\n"); 4476 } 4477 4478 if (rcnt > 0) { 4479 device_printf(sc->dev, "\n"); 4480 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4481 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4482 sc->rec.supp_pcm_size_rate); 4483 device_printf(sc->dev, " ADC:"); 4484 for (nids = sc->rec.io; *nids != -1; nids++) 4485 printf(" %d", *nids); 4486 printf("\n"); 4487 } 4488} 4489 4490static void 4491hdac_release_resources(struct hdac_softc *sc) 4492{ 4493 struct hdac_devinfo *devinfo = NULL; 4494 device_t *devlist = NULL; 4495 int i, devcount; 4496 4497 if (sc == NULL) 4498 return; 4499 4500 hdac_lock(sc); 4501 hdac_reset(sc); 4502 hdac_unlock(sc); 4503 snd_mtxfree(sc->lock); 4504 4505 device_get_children(sc->dev, &devlist, &devcount); 4506 for (i = 0; devlist != NULL && i < devcount; i++) { 4507 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4508 if (devinfo == NULL) 4509 continue; 4510 if (devinfo->widget != NULL) 4511 free(devinfo->widget, M_HDAC); 4512 if (devinfo->node_type == 4513 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4514 devinfo->function.audio.ctl != NULL) 4515 free(devinfo->function.audio.ctl, M_HDAC); 4516 free(devinfo, M_HDAC); 4517 device_delete_child(sc->dev, devlist[i]); 4518 } 4519 if (devlist != NULL) 4520 free(devlist, M_TEMP); 4521 4522 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4523 if (sc->codecs[i] != NULL) 4524 free(sc->codecs[i], M_HDAC); 4525 sc->codecs[i] = NULL; 4526 } 4527 4528 hdac_dma_free(&sc->rirb_dma); 4529 hdac_dma_free(&sc->corb_dma); 4530 if (sc->play.blkcnt > 0) 4531 hdac_dma_free(&sc->play.bdl_dma); 4532 if (sc->rec.blkcnt > 0) 4533 hdac_dma_free(&sc->rec.bdl_dma); 4534 hdac_irq_free(sc); 4535 hdac_mem_free(sc); 4536 free(sc, M_DEVBUF); 4537 4538} 4539 4540/* This function surely going to make its way into upper level someday. */ 4541static void 4542hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4543{ 4544 const char *res = NULL; 4545 int i = 0, j, k, len, inv; 4546 4547 if (on != NULL) 4548 *on = 0; 4549 if (off != NULL) 4550 *off = 0; 4551 if (sc == NULL) 4552 return; 4553 if (resource_string_value(device_get_name(sc->dev), 4554 device_get_unit(sc->dev), "config", &res) != 0) 4555 return; 4556 if (!(res != NULL && strlen(res) > 0)) 4557 return; 4558 HDA_BOOTVERBOSE( 4559 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4560 ); 4561 for (;;) { 4562 while (res[i] != '\0' && 4563 (res[i] == ',' || isspace(res[i]) != 0)) 4564 i++; 4565 if (res[i] == '\0') { 4566 HDA_BOOTVERBOSE( 4567 printf("\n"); 4568 ); 4569 return; 4570 } 4571 j = i; 4572 while (res[j] != '\0' && 4573 !(res[j] == ',' || isspace(res[j]) != 0)) 4574 j++; 4575 len = j - i; 4576 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4577 inv = 2; 4578 else 4579 inv = 0; 4580 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4581 if (strncmp(res + i + inv, 4582 hdac_quirks_tab[k].key, len - inv) != 0) 4583 continue; 4584 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4585 break; 4586 HDA_BOOTVERBOSE( 4587 printf(" %s%s", (inv != 0) ? "no" : "", 4588 hdac_quirks_tab[k].key); 4589 ); 4590 if (inv == 0 && on != NULL) 4591 *on |= hdac_quirks_tab[k].value; 4592 else if (inv != 0 && off != NULL) 4593 *off |= hdac_quirks_tab[k].value; 4594 break; 4595 } 4596 i = j; 4597 } 4598} 4599 4600static void 4601hdac_attach2(void *arg) 4602{ 4603 struct hdac_softc *sc; 4604 struct hdac_widget *w; 4605 struct hdac_audio_ctl *ctl; 4606 uint32_t quirks_on, quirks_off; 4607 int pcnt, rcnt; 4608 int i; 4609 char status[SND_STATUSLEN]; 4610 device_t *devlist = NULL; 4611 int devcount; 4612 struct hdac_devinfo *devinfo = NULL; 4613 4614 sc = (struct hdac_softc *)arg; 4615 4616 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4617 4618 HDA_BOOTVERBOSE( 4619 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4620 quirks_on, quirks_off); 4621 ); 4622 4623 hdac_lock(sc); 4624 4625 /* Remove ourselves from the config hooks */ 4626 if (sc->intrhook.ich_func != NULL) { 4627 config_intrhook_disestablish(&sc->intrhook); 4628 sc->intrhook.ich_func = NULL; 4629 } 4630 4631 /* Start the corb and rirb engines */ 4632 HDA_BOOTVERBOSE( 4633 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4634 ); 4635 hdac_corb_start(sc); 4636 HDA_BOOTVERBOSE( 4637 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4638 ); 4639 hdac_rirb_start(sc); 4640 4641 HDA_BOOTVERBOSE( 4642 device_printf(sc->dev, 4643 "HDA_DEBUG: Enabling controller interrupt...\n"); 4644 ); 4645 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4646 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4647 HDAC_GCTL_UNSOL); 4648 4649 DELAY(1000); 4650 4651 HDA_BOOTVERBOSE( 4652 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4653 ); 4654 hdac_scan_codecs(sc); 4655 4656 device_get_children(sc->dev, &devlist, &devcount); 4657 for (i = 0; devlist != NULL && i < devcount; i++) { 4658 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4659 if (devinfo != NULL && devinfo->node_type == 4660 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4661 break; 4662 } else 4663 devinfo = NULL; 4664 } 4665 if (devlist != NULL) 4666 free(devlist, M_TEMP); 4667 4668 if (devinfo == NULL) { 4669 hdac_unlock(sc); 4670 device_printf(sc->dev, "Audio Function Group not found!\n"); 4671 hdac_release_resources(sc); 4672 return; 4673 } 4674 4675 HDA_BOOTVERBOSE( 4676 device_printf(sc->dev, 4677 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4678 devinfo->nid, devinfo->codec->cad); 4679 ); 4680 hdac_audio_parse(devinfo); 4681 HDA_BOOTVERBOSE( 4682 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4683 ); 4684 hdac_audio_ctl_parse(devinfo); 4685 HDA_BOOTVERBOSE( 4686 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4687 ); 4688 hdac_vendor_patch_parse(devinfo); 4689 if (quirks_on != 0) 4690 devinfo->function.audio.quirks |= quirks_on; 4691 if (quirks_off != 0) 4692 devinfo->function.audio.quirks &= ~quirks_off; 4693 4694 /* XXX Disable all DIGITAL path. */ 4695 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4696 w = hdac_widget_get(devinfo, i); 4697 if (w == NULL) 4698 continue; 4699 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4700 w->enable = 0; 4701 continue; 4702 } 4703 /* XXX Disable useless pin ? */ 4704 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4705 (w->wclass.pin.config & 4706 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4707 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4708 w->enable = 0; 4709 } 4710 i = 0; 4711 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4712 if (ctl->widget == NULL) 4713 continue; 4714 w = ctl->widget; 4715 if (w->enable == 0) 4716 ctl->enable = 0; 4717 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4718 ctl->enable = 0; 4719 w = ctl->childwidget; 4720 if (w == NULL) 4721 continue; 4722 if (w->enable == 0 || 4723 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4724 ctl->enable = 0; 4725 } 4726 4727 HDA_BOOTVERBOSE( 4728 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 4729 ); 4730 hdac_audio_build_tree(devinfo); 4731 4732 HDA_BOOTVERBOSE( 4733 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 4734 ); 4735 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 4736 HDA_BOOTVERBOSE( 4737 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 4738 ); 4739 hdac_audio_ctl_commit(devinfo); 4740 4741 HDA_BOOTVERBOSE( 4742 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 4743 ); 4744 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 4745 HDA_BOOTVERBOSE( 4746 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 4747 ); 4748 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 4749 4750 hdac_unlock(sc); 4751 HDA_BOOTVERBOSE( 4752 device_printf(sc->dev, 4753 "HDA_DEBUG: OSS mixer initialization...\n"); 4754 ); 4755 4756 /* 4757 * There is no point of return after this. If the driver failed, 4758 * so be it. Let the detach procedure do all the cleanup. 4759 */ 4760 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 4761 device_printf(sc->dev, "Can't register mixer\n"); 4762 4763 if (pcnt > 0) 4764 pcnt = 1; 4765 if (rcnt > 0) 4766 rcnt = 1; 4767 4768 HDA_BOOTVERBOSE( 4769 device_printf(sc->dev, 4770 "HDA_DEBUG: Registering PCM channels...\n"); 4771 ); 4772 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 4773 device_printf(sc->dev, "Can't register PCM\n"); 4774 4775 sc->registered++; 4776 4777 for (i = 0; i < pcnt; i++) 4778 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 4779 for (i = 0; i < rcnt; i++) 4780 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 4781 4782 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 4783 rman_get_start(sc->mem.mem_res), 4784 rman_get_start(sc->irq.irq_res), 4785 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 4786 pcm_setstatus(sc->dev, status); 4787 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 4788 HDA_BOOTVERBOSE( 4789 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 4790 hdac_codec_id(devinfo)); 4791 ); 4792 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 4793 4794 HDA_BOOTVERBOSE( 4795 if (devinfo->function.audio.quirks != 0) { 4796 device_printf(sc->dev, "\n"); 4797 device_printf(sc->dev, "HDA config/quirks:"); 4798 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 4799 if (devinfo->function.audio.quirks & 4800 hdac_quirks_tab[i].value) 4801 printf(" %s", hdac_quirks_tab[i].key); 4802 } 4803 printf("\n"); 4804 } 4805 device_printf(sc->dev, "\n"); 4806 device_printf(sc->dev, "+-------------------+\n"); 4807 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 4808 device_printf(sc->dev, "+-------------------+\n"); 4809 hdac_dump_nodes(devinfo); 4810 device_printf(sc->dev, "\n"); 4811 device_printf(sc->dev, "+------------------------+\n"); 4812 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 4813 device_printf(sc->dev, "+------------------------+\n"); 4814 device_printf(sc->dev, "\n"); 4815 i = 0; 4816 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4817 device_printf(sc->dev, "%3d: nid=%d", i, 4818 (ctl->widget != NULL) ? ctl->widget->nid : -1); 4819 if (ctl->childwidget != NULL) 4820 printf(" cnid=%d", ctl->childwidget->nid); 4821 printf(" dir=0x%x index=%d " 4822 "ossmask=0x%08x ossdev=%d%s\n", 4823 ctl->dir, ctl->index, 4824 ctl->ossmask, ctl->ossdev, 4825 (ctl->enable == 0) ? " [DISABLED]" : ""); 4826 } 4827 device_printf(sc->dev, "\n"); 4828 device_printf(sc->dev, "+-----------------------------------+\n"); 4829 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 4830 device_printf(sc->dev, "+-----------------------------------+\n"); 4831 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 4832 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 4833 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 4834 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 4835 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 4836 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 4837 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 4838 hdac_dump_ctls(devinfo, NULL, 0); 4839 hdac_dump_dac(devinfo); 4840 hdac_dump_adc(devinfo); 4841 device_printf(sc->dev, "\n"); 4842 device_printf(sc->dev, "+--------------------------------------+\n"); 4843 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 4844 device_printf(sc->dev, "+--------------------------------------+\n"); 4845 hdac_dump_pcmchannels(sc, pcnt, rcnt); 4846 ); 4847} 4848 4849/**************************************************************************** 4850 * int hdac_detach(device_t) 4851 * 4852 * Detach and free up resources utilized by the hdac device. 4853 ****************************************************************************/ 4854static int 4855hdac_detach(device_t dev) 4856{ 4857 struct hdac_softc *sc = NULL; 4858 struct hdac_devinfo *devinfo = NULL; 4859 int err; 4860 4861 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 4862 if (devinfo != NULL && devinfo->codec != NULL) 4863 sc = devinfo->codec->sc; 4864 if (sc == NULL) 4865 return (0); 4866 4867 if (sc->registered > 0) { 4868 err = pcm_unregister(dev); 4869 if (err != 0) 4870 return (err); 4871 } 4872 4873 hdac_release_resources(sc); 4874 4875 return (0); 4876} 4877 4878static device_method_t hdac_methods[] = { 4879 /* device interface */ 4880 DEVMETHOD(device_probe, hdac_probe), 4881 DEVMETHOD(device_attach, hdac_attach), 4882 DEVMETHOD(device_detach, hdac_detach), 4883 { 0, 0 } 4884}; 4885 4886static driver_t hdac_driver = { 4887 "pcm", 4888 hdac_methods, 4889 PCM_SOFTC_SIZE, 4890}; 4891 4892DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 4893MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 4894MODULE_VERSION(snd_hda, 1); 4895