hdac.c revision 163257
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especiall UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <sys/ctype.h> 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <dev/sound/pci/hda/hdac_private.h> 77#include <dev/sound/pci/hda/hdac_reg.h> 78#include <dev/sound/pci/hda/hda_reg.h> 79#include <dev/sound/pci/hda/hdac.h> 80 81#include "mixer_if.h" 82 83#define HDA_DRV_TEST_REV "20061009_0031" 84#define HDA_WIDGET_PARSER_REV 1 85 86SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 163257 2006-10-12 04:19:37Z ariff $"); 87 88#undef HDA_DEBUG_ENABLED 89#define HDA_DEBUG_ENABLED 1 90 91#ifdef HDA_DEBUG_ENABLED 92#define HDA_DEBUG(stmt) do { \ 93 stmt \ 94} while(0) 95#else 96#define HDA_DEBUG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127 128/* Controller models */ 129 130/* Intel */ 131#define INTEL_VENDORID 0x8086 132#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137 138/* Nvidia */ 139#define NVIDIA_VENDORID 0x10de 140#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147 148/* ATI */ 149#define ATI_VENDORID 0x1002 150#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153 154/* VIA */ 155#define VIA_VENDORID 0x1106 156#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158 159/* SiS */ 160#define SIS_VENDORID 0x1039 161#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163 164/* OEM/subvendors */ 165 166/* HP/Compaq */ 167#define HP_VENDORID 0x103c 168#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 169#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 170#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 171#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 172 173/* Dell */ 174#define DELL_VENDORID 0x1028 175#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 176#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 177#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 178 179/* Clevo */ 180#define CLEVO_VENDORID 0x1558 181#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 182#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 183 184/* Acer */ 185#define ACER_VENDORID 0x1025 186#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 187 188/* Asus */ 189#define ASUS_VENDORID 0x1043 190#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 191#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 192 193/* IBM / Lenovo */ 194#define IBM_VENDORID 0x1014 195#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 196#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 197 198 199/* Misc constants.. */ 200#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 201#define HDA_AMP_MUTE_NONE (0) 202#define HDA_AMP_MUTE_LEFT (1 << 0) 203#define HDA_AMP_MUTE_RIGHT (1 << 1) 204#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 205 206#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 207#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 208 209#define HDA_DAC_PATH (1 << 0) 210#define HDA_ADC_PATH (1 << 1) 211#define HDA_ADC_RECSEL (1 << 2) 212 213#define HDA_CTL_OUT (1 << 0) 214#define HDA_CTL_IN (1 << 1) 215#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 216 217#define HDA_GPIO_MAX 15 218/* 0 - 14 = GPIO */ 219#define HDA_QUIRK_GPIO0 (1 << 0) 220#define HDA_QUIRK_GPIO1 (1 << 1) 221#define HDA_QUIRK_GPIO2 (1 << 2) 222#define HDA_QUIRK_SOFTPCMVOL (1 << 15) 223#define HDA_QUIRK_FIXEDRATE (1 << 16) 224#define HDA_QUIRK_FORCESTEREO (1 << 17) 225 226static const struct { 227 char *key; 228 uint32_t value; 229} hdac_quirks_tab[] = { 230 { "gpio0", HDA_QUIRK_GPIO0 }, 231 { "gpio1", HDA_QUIRK_GPIO1 }, 232 { "gpio2", HDA_QUIRK_GPIO2 }, 233 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 234 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 235 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 236}; 237#define HDAC_QUIRKS_TAB_LEN \ 238 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 239 240#define HDA_BDL_MIN 2 241#define HDA_BDL_MAX 256 242#define HDA_BDL_DEFAULT HDA_BDL_MIN 243 244#define HDA_BUFSZ_MIN 4096 245#define HDA_BUFSZ_MAX 65536 246#define HDA_BUFSZ_DEFAULT 16384 247 248#define HDA_PARSE_MAXDEPTH 10 249 250#define HDAC_UNSOLTAG_EVENT_HP 0x00 251 252static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 253 254enum { 255 HDA_PARSE_MIXER, 256 HDA_PARSE_DIRECT 257}; 258 259/* Default */ 260static uint32_t hdac_fmt[] = { 261 AFMT_STEREO | AFMT_S16_LE, 262 0 263}; 264 265static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 266 267static const struct { 268 uint32_t model; 269 char *desc; 270} hdac_devices[] = { 271 { HDA_INTEL_82801F, "Intel 82801F" }, 272 { HDA_INTEL_82801G, "Intel 82801G" }, 273 { HDA_INTEL_82801H, "Intel 82801H" }, 274 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 275 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 276 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 277 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 278 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 279 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 280 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 281 { HDA_ATI_SB450, "ATI SB450" }, 282 { HDA_ATI_SB600, "ATI SB600" }, 283 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 284 { HDA_SIS_966, "SiS 966" }, 285 /* Unknown */ 286 { HDA_INTEL_ALL, "Intel (Unknown)" }, 287 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 288 { HDA_ATI_ALL, "ATI (Unknown)" }, 289 { HDA_VIA_ALL, "VIA (Unknown)" }, 290 { HDA_SIS_ALL, "SiS (Unknown)" }, 291}; 292#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 293 294static const struct { 295 uint32_t rate; 296 int valid; 297 uint16_t base; 298 uint16_t mul; 299 uint16_t div; 300} hda_rate_tab[] = { 301 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 302 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 303 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 304 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 305 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 306 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 307 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 308 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 309 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 310 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 311 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 312 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 313 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 314 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 315 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 316 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 317 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 318 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 319 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 320 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 321 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 322 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 323 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 324 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 325 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 326 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 327 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 328 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 329 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 330 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 331 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 332 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 333 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 334 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 335 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 336}; 337#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 338 339/* All codecs you can eat... */ 340#define HDA_CODEC_CONSTRUCT(vendor, id) \ 341 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 342 343/* Realtek */ 344#define REALTEK_VENDORID 0x10ec 345#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 346#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 347#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 348#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 349#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 350#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 351 352/* Analog Device */ 353#define ANALOGDEVICE_VENDORID 0x11d4 354#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 355#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 356#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 357#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 358 359/* CMedia */ 360#define CMEDIA_VENDORID 0x434d 361#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 362#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 363 364/* Sigmatel */ 365#define SIGMATEL_VENDORID 0x8384 366#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 367#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 368#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 369#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 370#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 371 372/* 373 * Conexant 374 * 375 * Ok, the truth is, I don't have any idea at all whether 376 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 377 * place that tell me it is "Venice" is from its Windows driver INF. 378 * 379 * Venice - CX????? 380 * Waikiki - CX20551-22 381 */ 382#define CONEXANT_VENDORID 0x14f1 383#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 384#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 385#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 386 387 388/* Codecs */ 389static const struct { 390 uint32_t id; 391 char *name; 392} hdac_codecs[] = { 393 { HDA_CODEC_ALC260, "Realtek ALC260" }, 394 { HDA_CODEC_ALC861, "Realtek ALC861" }, 395 { HDA_CODEC_ALC880, "Realtek ALC880" }, 396 { HDA_CODEC_ALC882, "Realtek ALC882" }, 397 { HDA_CODEC_ALC883, "Realtek ALC883" }, 398 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 399 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 400 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 401 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 402 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 403 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 404 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 405 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 406 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 407 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 408 /* Unknown codec */ 409 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 410 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 411 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 412 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 413 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 414}; 415#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 416 417enum { 418 HDAC_HP_SWITCH_CTL, 419 HDAC_HP_SWITCH_CTRL 420}; 421 422static const struct { 423 uint32_t model; 424 uint32_t id; 425 int type; 426 nid_t hpnid; 427 nid_t spkrnid[8]; 428 nid_t eapdnid; 429} hdac_hp_switch[] = { 430 /* Specific OEM models */ 431 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 432 17, { 16, -1 }, 16 }, 433 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 434 6, { 5, -1 }, 5 }, 435 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 436 6, { 5, -1 }, 5 }, 437 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 438 13, { 14, -1 }, -1 }, 439 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 440 13, { 14, -1 }, -1 }, 441 /* 442 * All models that at least come from the same vendor with 443 * simmilar codec. 444 */ 445 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 446 17, { 16, -1 }, 16 }, 447 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 448 6, { 5, -1 }, 5 }, 449 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 450 13, { 14, -1 }, -1 }, 451}; 452#define HDAC_HP_SWITCH_LEN \ 453 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 454 455static const struct { 456 uint32_t model; 457 uint32_t id; 458 nid_t eapdnid; 459 int hp_switch; 460} hdac_eapd_switch[] = { 461 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 462 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 463 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 464}; 465#define HDAC_EAPD_SWITCH_LEN \ 466 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 467 468/**************************************************************************** 469 * Function prototypes 470 ****************************************************************************/ 471static void hdac_intr_handler(void *); 472static int hdac_reset(struct hdac_softc *); 473static int hdac_get_capabilities(struct hdac_softc *); 474static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 475static int hdac_dma_alloc(struct hdac_softc *, 476 struct hdac_dma *, bus_size_t); 477static void hdac_dma_free(struct hdac_dma *); 478static int hdac_mem_alloc(struct hdac_softc *); 479static void hdac_mem_free(struct hdac_softc *); 480static int hdac_irq_alloc(struct hdac_softc *); 481static void hdac_irq_free(struct hdac_softc *); 482static void hdac_corb_init(struct hdac_softc *); 483static void hdac_rirb_init(struct hdac_softc *); 484static void hdac_corb_start(struct hdac_softc *); 485static void hdac_rirb_start(struct hdac_softc *); 486static void hdac_scan_codecs(struct hdac_softc *); 487static int hdac_probe_codec(struct hdac_codec *); 488static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 489static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 490 491static void hdac_attach2(void *); 492 493static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 494 uint32_t, int); 495static void hdac_command_send_internal(struct hdac_softc *, 496 struct hdac_command_list *, int); 497 498static int hdac_probe(device_t); 499static int hdac_attach(device_t); 500static int hdac_detach(device_t); 501static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 502static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 503 uint32_t, int, int); 504static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 505 nid_t, int, int); 506static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 507 nid_t, nid_t, int, int, int, int, int, int); 508static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 509static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 510 511#define hdac_command(a1, a2, a3) \ 512 hdac_command_sendone_internal(a1, a2, a3) 513 514#define hdac_codec_id(d) \ 515 ((uint32_t)((d == NULL) ? 0x00000000 : \ 516 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 517 ((uint32_t)(d)->device_id & 0x0000ffff)))) 518 519static char * 520hdac_codec_name(struct hdac_devinfo *devinfo) 521{ 522 uint32_t id; 523 int i; 524 525 id = hdac_codec_id(devinfo); 526 527 for (i = 0; i < HDAC_CODECS_LEN; i++) { 528 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 529 return (hdac_codecs[i].name); 530 } 531 532 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 533} 534 535static char * 536hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 537{ 538 static char *ossname[] = SOUND_DEVICE_NAMES; 539 static char *unknown = "???"; 540 int i; 541 542 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 543 if (devmask & (1 << i)) 544 return (ossname[i]); 545 } 546 return (unknown); 547} 548 549static void 550hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 551{ 552 static char *ossname[] = SOUND_DEVICE_NAMES; 553 int i, first = 1; 554 555 bzero(buf, len); 556 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 557 if (mask & (1 << i)) { 558 if (first == 0) 559 strlcat(buf, ", ", len); 560 strlcat(buf, ossname[i], len); 561 first = 0; 562 } 563 } 564} 565 566static struct hdac_audio_ctl * 567hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 568{ 569 if (devinfo == NULL || 570 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 571 index == NULL || devinfo->function.audio.ctl == NULL || 572 devinfo->function.audio.ctlcnt < 1 || 573 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 574 return (NULL); 575 return (&devinfo->function.audio.ctl[(*index)++]); 576} 577 578static struct hdac_audio_ctl * 579hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 580 int index, int cnt) 581{ 582 struct hdac_audio_ctl *ctl, *retctl = NULL; 583 int i, at, atindex, found = 0; 584 585 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 586 return (NULL); 587 588 at = cnt; 589 if (at == 0) 590 at = 1; 591 else if (at < 0) 592 at = -1; 593 atindex = index; 594 if (atindex < 0) 595 atindex = -1; 596 597 i = 0; 598 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 599 if (ctl->enable == 0 || ctl->widget == NULL) 600 continue; 601 if (!(ctl->widget->nid == nid && (atindex == -1 || 602 ctl->index == atindex))) 603 continue; 604 found++; 605 if (found == cnt) 606 return (ctl); 607 retctl = ctl; 608 } 609 610 return ((at == -1) ? retctl : NULL); 611} 612 613static void 614hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 615{ 616 struct hdac_softc *sc; 617 struct hdac_widget *w; 618 struct hdac_audio_ctl *ctl; 619 uint32_t id, res; 620 int i = 0, j, forcemute; 621 nid_t cad; 622 623 if (devinfo == NULL || devinfo->codec == NULL || 624 devinfo->codec->sc == NULL) 625 return; 626 627 sc = devinfo->codec->sc; 628 cad = devinfo->codec->cad; 629 id = hdac_codec_id(devinfo); 630 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 631 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 632 sc->pci_subvendor) && 633 hdac_hp_switch[i].id == id) 634 break; 635 } 636 637 if (i >= HDAC_HP_SWITCH_LEN) 638 return; 639 640 forcemute = 0; 641 if (hdac_hp_switch[i].eapdnid != -1) { 642 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 643 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 644 forcemute = (w->param.eapdbtl & 645 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 646 } 647 648 res = hdac_command(sc, 649 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 650 HDA_BOOTVERBOSE( 651 device_printf(sc->dev, 652 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 653 hdac_hp_switch[i].hpnid, res); 654 ); 655 res >>= 31; 656 657 switch (hdac_hp_switch[i].type) { 658 case HDAC_HP_SWITCH_CTL: 659 ctl = hdac_audio_ctl_amp_get(devinfo, 660 hdac_hp_switch[i].hpnid, 0, 1); 661 if (ctl != NULL) { 662 ctl->muted = (res != 0 && forcemute == 0) ? 663 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 664 hdac_audio_ctl_amp_set(ctl, 665 HDA_AMP_MUTE_DEFAULT, ctl->left, 666 ctl->right); 667 } 668 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 669 ctl = hdac_audio_ctl_amp_get(devinfo, 670 hdac_hp_switch[i].spkrnid[j], 0, 1); 671 if (ctl != NULL) { 672 ctl->muted = (res != 0 || forcemute == 1) ? 673 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 674 hdac_audio_ctl_amp_set(ctl, 675 HDA_AMP_MUTE_DEFAULT, ctl->left, 676 ctl->right); 677 } 678 } 679 break; 680 case HDAC_HP_SWITCH_CTRL: 681 if (res != 0) { 682 /* HP in */ 683 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 684 if (w != NULL && w->type == 685 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 686 if (forcemute == 0) 687 w->wclass.pin.ctrl |= 688 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 689 else 690 w->wclass.pin.ctrl &= 691 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 692 hdac_command(sc, 693 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 694 w->wclass.pin.ctrl), cad); 695 } 696 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 697 w = hdac_widget_get(devinfo, 698 hdac_hp_switch[i].spkrnid[j]); 699 if (w != NULL && w->type == 700 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 701 w->wclass.pin.ctrl &= 702 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 703 hdac_command(sc, 704 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 705 w->nid, 706 w->wclass.pin.ctrl), cad); 707 } 708 } 709 } else { 710 /* HP out */ 711 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 712 if (w != NULL && w->type == 713 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 714 w->wclass.pin.ctrl &= 715 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 716 hdac_command(sc, 717 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 718 w->wclass.pin.ctrl), cad); 719 } 720 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 721 w = hdac_widget_get(devinfo, 722 hdac_hp_switch[i].spkrnid[j]); 723 if (w != NULL && w->type == 724 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 725 if (forcemute == 0) 726 w->wclass.pin.ctrl |= 727 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 728 else 729 w->wclass.pin.ctrl &= 730 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 731 hdac_command(sc, 732 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 733 w->nid, 734 w->wclass.pin.ctrl), cad); 735 } 736 } 737 } 738 break; 739 default: 740 break; 741 } 742} 743 744static void 745hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 746{ 747 struct hdac_softc *sc; 748 struct hdac_devinfo *devinfo = NULL; 749 device_t *devlist = NULL; 750 int devcount, i; 751 752 if (codec == NULL || codec->sc == NULL) 753 return; 754 755 sc = codec->sc; 756 757 HDA_BOOTVERBOSE( 758 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 759 ); 760 761 device_get_children(sc->dev, &devlist, &devcount); 762 for (i = 0; devlist != NULL && i < devcount; i++) { 763 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 764 if (devinfo != NULL && devinfo->node_type == 765 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 766 devinfo->codec != NULL && 767 devinfo->codec->cad == codec->cad) { 768 break; 769 } else 770 devinfo = NULL; 771 } 772 if (devlist != NULL) 773 free(devlist, M_TEMP); 774 775 if (devinfo == NULL) 776 return; 777 778 switch (tag) { 779 case HDAC_UNSOLTAG_EVENT_HP: 780 hdac_hp_switch_handler(devinfo); 781 break; 782 default: 783 break; 784 } 785} 786 787static void 788hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 789{ 790 /* XXX to be removed */ 791#ifdef HDAC_INTR_EXTRA 792 uint32_t res; 793#endif 794 795 if (ch->blkcnt == 0) 796 return; 797 798 /* XXX to be removed */ 799#ifdef HDAC_INTR_EXTRA 800 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 801#endif 802 803 /* XXX to be removed */ 804#ifdef HDAC_INTR_EXTRA 805 HDA_BOOTVERBOSE( 806 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 807 device_printf(sc->dev, 808 "PCMDIR_%s intr triggered beyond stream boundary:" 809 "%08x\n", 810 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 811 ); 812#endif 813 814 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 815 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 816 817 /* XXX to be removed */ 818#ifdef HDAC_INTR_EXTRA 819 if (res & HDAC_SDSTS_BCIS) { 820#endif 821 ch->prevptr = ch->ptr; 822 ch->ptr += sndbuf_getblksz(ch->b); 823 ch->ptr %= sndbuf_getsize(ch->b); 824 hdac_unlock(sc); 825 chn_intr(ch->c); 826 hdac_lock(sc); 827 /* XXX to be removed */ 828#ifdef HDAC_INTR_EXTRA 829 } 830#endif 831} 832 833/**************************************************************************** 834 * void hdac_intr_handler(void *) 835 * 836 * Interrupt handler. Processes interrupts received from the hdac. 837 ****************************************************************************/ 838static void 839hdac_intr_handler(void *context) 840{ 841 struct hdac_softc *sc; 842 uint32_t intsts; 843 uint8_t rirbsts; 844 uint8_t rirbwp; 845 struct hdac_rirb *rirb_base, *rirb; 846 nid_t ucad; 847 uint32_t utag; 848 849 sc = (struct hdac_softc *)context; 850 851 hdac_lock(sc); 852 /* Do we have anything to do? */ 853 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 854 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 855 hdac_unlock(sc); 856 return; 857 } 858 859 /* Was this a controller interrupt? */ 860 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 861 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 862 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 863 /* Get as many responses that we can */ 864 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 865 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 866 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 867 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 868 BUS_DMASYNC_POSTREAD); 869 while (sc->rirb_rp != rirbwp) { 870 sc->rirb_rp++; 871 sc->rirb_rp %= sc->rirb_size; 872 rirb = &rirb_base[sc->rirb_rp]; 873 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 874 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 875 utag = rirb->response >> 26; 876 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 877 sc->codecs[ucad] != NULL) { 878 sc->unsolq[sc->unsolq_wp++] = 879 (ucad << 16) | 880 (utag & 0xffff); 881 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 882 } 883 } 884 } 885 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 886 } 887 /* XXX to be removed */ 888 /* Clear interrupt and exit */ 889#ifdef HDAC_INTR_EXTRA 890 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 891#endif 892 } 893 if (intsts & HDAC_INTSTS_SIS_MASK) { 894 if (intsts & (1 << sc->num_iss)) 895 hdac_stream_intr(sc, &sc->play); 896 if (intsts & (1 << 0)) 897 hdac_stream_intr(sc, &sc->rec); 898 /* XXX to be removed */ 899#ifdef HDAC_INTR_EXTRA 900 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK); 901#endif 902 } 903 904 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 905 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 906 while (sc->unsolq_rp != sc->unsolq_wp) { 907 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 908 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 909 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 910 hdac_unsolicited_handler(sc->codecs[ucad], utag); 911 } 912 sc->unsolq_st = HDAC_UNSOLQ_READY; 913 } 914 915 hdac_unlock(sc); 916} 917 918/**************************************************************************** 919 * int hdac_reset(hdac_softc *) 920 * 921 * Reset the hdac to a quiescent and known state. 922 ****************************************************************************/ 923static int 924hdac_reset(struct hdac_softc *sc) 925{ 926 uint32_t gctl; 927 int count, i; 928 929 /* 930 * Stop all Streams DMA engine 931 */ 932 for (i = 0; i < sc->num_iss; i++) 933 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 934 for (i = 0; i < sc->num_oss; i++) 935 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 936 for (i = 0; i < sc->num_bss; i++) 937 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 938 939 /* 940 * Stop Control DMA engines 941 */ 942 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 943 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 944 945 /* 946 * Reset the controller. The reset must remain asserted for 947 * a minimum of 100us. 948 */ 949 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 950 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 951 count = 10000; 952 do { 953 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 954 if (!(gctl & HDAC_GCTL_CRST)) 955 break; 956 DELAY(10); 957 } while (--count); 958 if (gctl & HDAC_GCTL_CRST) { 959 device_printf(sc->dev, "Unable to put hdac in reset\n"); 960 return (ENXIO); 961 } 962 DELAY(100); 963 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 964 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 965 count = 10000; 966 do { 967 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 968 if (gctl & HDAC_GCTL_CRST) 969 break; 970 DELAY(10); 971 } while (--count); 972 if (!(gctl & HDAC_GCTL_CRST)) { 973 device_printf(sc->dev, "Device stuck in reset\n"); 974 return (ENXIO); 975 } 976 977 /* 978 * Wait for codecs to finish their own reset sequence. The delay here 979 * should be of 250us but for some reasons, on it's not enough on my 980 * computer. Let's use twice as much as necessary to make sure that 981 * it's reset properly. 982 */ 983 DELAY(1000); 984 985 return (0); 986} 987 988 989/**************************************************************************** 990 * int hdac_get_capabilities(struct hdac_softc *); 991 * 992 * Retreive the general capabilities of the hdac; 993 * Number of Input Streams 994 * Number of Output Streams 995 * Number of bidirectional Streams 996 * 64bit ready 997 * CORB and RIRB sizes 998 ****************************************************************************/ 999static int 1000hdac_get_capabilities(struct hdac_softc *sc) 1001{ 1002 uint16_t gcap; 1003 uint8_t corbsize, rirbsize; 1004 1005 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1006 sc->num_iss = HDAC_GCAP_ISS(gcap); 1007 sc->num_oss = HDAC_GCAP_OSS(gcap); 1008 sc->num_bss = HDAC_GCAP_BSS(gcap); 1009 1010 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1011 1012 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1013 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1014 HDAC_CORBSIZE_CORBSZCAP_256) 1015 sc->corb_size = 256; 1016 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1017 HDAC_CORBSIZE_CORBSZCAP_16) 1018 sc->corb_size = 16; 1019 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1020 HDAC_CORBSIZE_CORBSZCAP_2) 1021 sc->corb_size = 2; 1022 else { 1023 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1024 __func__, corbsize); 1025 return (ENXIO); 1026 } 1027 1028 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1029 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1030 HDAC_RIRBSIZE_RIRBSZCAP_256) 1031 sc->rirb_size = 256; 1032 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1033 HDAC_RIRBSIZE_RIRBSZCAP_16) 1034 sc->rirb_size = 16; 1035 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1036 HDAC_RIRBSIZE_RIRBSZCAP_2) 1037 sc->rirb_size = 2; 1038 else { 1039 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1040 __func__, rirbsize); 1041 return (ENXIO); 1042 } 1043 1044 return (0); 1045} 1046 1047 1048/**************************************************************************** 1049 * void hdac_dma_cb 1050 * 1051 * This function is called by bus_dmamap_load when the mapping has been 1052 * established. We just record the physical address of the mapping into 1053 * the struct hdac_dma passed in. 1054 ****************************************************************************/ 1055static void 1056hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1057{ 1058 struct hdac_dma *dma; 1059 1060 if (error == 0) { 1061 dma = (struct hdac_dma *)callback_arg; 1062 dma->dma_paddr = segs[0].ds_addr; 1063 } 1064} 1065 1066static void 1067hdac_dma_nocache(void *ptr) 1068{ 1069#if defined(__i386__) || defined(__amd64__) 1070 pt_entry_t *pte; 1071 vm_offset_t va; 1072 1073 va = (vm_offset_t)ptr; 1074 pte = vtopte(va); 1075 if (pte) { 1076 *pte |= PG_N; 1077 invltlb(); 1078 } 1079#endif 1080} 1081 1082/**************************************************************************** 1083 * int hdac_dma_alloc 1084 * 1085 * This function allocate and setup a dma region (struct hdac_dma). 1086 * It must be freed by a corresponding hdac_dma_free. 1087 ****************************************************************************/ 1088static int 1089hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1090{ 1091 int result; 1092 int lowaddr; 1093 1094 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1095 BUS_SPACE_MAXADDR_32BIT; 1096 bzero(dma, sizeof(*dma)); 1097 1098 /* 1099 * Create a DMA tag 1100 */ 1101 result = bus_dma_tag_create(NULL, /* parent */ 1102 HDAC_DMA_ALIGNMENT, /* alignment */ 1103 0, /* boundary */ 1104 lowaddr, /* lowaddr */ 1105 BUS_SPACE_MAXADDR, /* highaddr */ 1106 NULL, /* filtfunc */ 1107 NULL, /* fistfuncarg */ 1108 size, /* maxsize */ 1109 1, /* nsegments */ 1110 size, /* maxsegsz */ 1111 0, /* flags */ 1112 NULL, /* lockfunc */ 1113 NULL, /* lockfuncarg */ 1114 &dma->dma_tag); /* dmat */ 1115 if (result != 0) { 1116 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1117 __func__, result); 1118 goto fail; 1119 } 1120 1121 /* 1122 * Allocate DMA memory 1123 */ 1124 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1125 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1126 if (result != 0) { 1127 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1128 __func__, result); 1129 goto fail; 1130 } 1131 1132 /* 1133 * Map the memory 1134 */ 1135 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1136 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1137 BUS_DMA_NOWAIT); 1138 if (result != 0 || dma->dma_paddr == 0) { 1139 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1140 __func__, result); 1141 goto fail; 1142 } 1143 bzero((void *)dma->dma_vaddr, size); 1144 hdac_dma_nocache(dma->dma_vaddr); 1145 1146 return (0); 1147fail: 1148 if (dma->dma_map != NULL) 1149 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1150 if (dma->dma_tag != NULL) 1151 bus_dma_tag_destroy(dma->dma_tag); 1152 return (result); 1153} 1154 1155 1156/**************************************************************************** 1157 * void hdac_dma_free(struct hdac_dma *) 1158 * 1159 * Free a struct dhac_dma that has been previously allocated via the 1160 * hdac_dma_alloc function. 1161 ****************************************************************************/ 1162static void 1163hdac_dma_free(struct hdac_dma *dma) 1164{ 1165 if (dma->dma_tag != NULL) { 1166 /* Flush caches */ 1167 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1168 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1169 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1170 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1171 bus_dma_tag_destroy(dma->dma_tag); 1172 } 1173} 1174 1175/**************************************************************************** 1176 * int hdac_mem_alloc(struct hdac_softc *) 1177 * 1178 * Allocate all the bus resources necessary to speak with the physical 1179 * controller. 1180 ****************************************************************************/ 1181static int 1182hdac_mem_alloc(struct hdac_softc *sc) 1183{ 1184 struct hdac_mem *mem; 1185 1186 mem = &sc->mem; 1187 mem->mem_rid = PCIR_BAR(0); 1188 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1189 &mem->mem_rid, RF_ACTIVE); 1190 if (mem->mem_res == NULL) { 1191 device_printf(sc->dev, 1192 "%s: Unable to allocate memory resource\n", __func__); 1193 return (ENOMEM); 1194 } 1195 mem->mem_tag = rman_get_bustag(mem->mem_res); 1196 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1197 1198 return (0); 1199} 1200 1201/**************************************************************************** 1202 * void hdac_mem_free(struct hdac_softc *) 1203 * 1204 * Free up resources previously allocated by hdac_mem_alloc. 1205 ****************************************************************************/ 1206static void 1207hdac_mem_free(struct hdac_softc *sc) 1208{ 1209 struct hdac_mem *mem; 1210 1211 mem = &sc->mem; 1212 if (mem->mem_res != NULL) 1213 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1214 mem->mem_res); 1215} 1216 1217/**************************************************************************** 1218 * int hdac_irq_alloc(struct hdac_softc *) 1219 * 1220 * Allocate and setup the resources necessary for interrupt handling. 1221 ****************************************************************************/ 1222static int 1223hdac_irq_alloc(struct hdac_softc *sc) 1224{ 1225 struct hdac_irq *irq; 1226 int result; 1227 1228 irq = &sc->irq; 1229 irq->irq_rid = 0x0; 1230 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1231 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1232 if (irq->irq_res == NULL) { 1233 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1234 __func__); 1235 goto fail; 1236 } 1237 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1238 hdac_intr_handler, sc, &irq->irq_handle); 1239 if (result != 0) { 1240 device_printf(sc->dev, 1241 "%s: Unable to setup interrupt handler (%x)\n", 1242 __func__, result); 1243 goto fail; 1244 } 1245 1246 return (0); 1247 1248fail: 1249 if (irq->irq_res != NULL) 1250 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1251 irq->irq_res); 1252 return (ENXIO); 1253} 1254 1255/**************************************************************************** 1256 * void hdac_irq_free(struct hdac_softc *) 1257 * 1258 * Free up resources previously allocated by hdac_irq_alloc. 1259 ****************************************************************************/ 1260static void 1261hdac_irq_free(struct hdac_softc *sc) 1262{ 1263 struct hdac_irq *irq; 1264 1265 irq = &sc->irq; 1266 if (irq->irq_handle != NULL) 1267 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1268 if (irq->irq_res != NULL) 1269 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1270 irq->irq_res); 1271} 1272 1273/**************************************************************************** 1274 * void hdac_corb_init(struct hdac_softc *) 1275 * 1276 * Initialize the corb registers for operations but do not start it up yet. 1277 * The CORB engine must not be running when this function is called. 1278 ****************************************************************************/ 1279static void 1280hdac_corb_init(struct hdac_softc *sc) 1281{ 1282 uint8_t corbsize; 1283 uint64_t corbpaddr; 1284 1285 /* Setup the CORB size. */ 1286 switch (sc->corb_size) { 1287 case 256: 1288 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1289 break; 1290 case 16: 1291 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1292 break; 1293 case 2: 1294 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1295 break; 1296 default: 1297 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1298 } 1299 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1300 1301 /* Setup the CORB Address in the hdac */ 1302 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1303 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1304 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1305 1306 /* Set the WP and RP */ 1307 sc->corb_wp = 0; 1308 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1309 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1310 /* 1311 * The HDA specification indicates that the CORBRPRST bit will always 1312 * read as zero. Unfortunately, it seems that at least the 82801G 1313 * doesn't reset the bit to zero, which stalls the corb engine. 1314 * manually reset the bit to zero before continuing. 1315 */ 1316 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1317 1318 /* Enable CORB error reporting */ 1319#if 0 1320 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1321#endif 1322} 1323 1324/**************************************************************************** 1325 * void hdac_rirb_init(struct hdac_softc *) 1326 * 1327 * Initialize the rirb registers for operations but do not start it up yet. 1328 * The RIRB engine must not be running when this function is called. 1329 ****************************************************************************/ 1330static void 1331hdac_rirb_init(struct hdac_softc *sc) 1332{ 1333 uint8_t rirbsize; 1334 uint64_t rirbpaddr; 1335 1336 /* Setup the RIRB size. */ 1337 switch (sc->rirb_size) { 1338 case 256: 1339 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1340 break; 1341 case 16: 1342 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1343 break; 1344 case 2: 1345 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1346 break; 1347 default: 1348 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1349 } 1350 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1351 1352 /* Setup the RIRB Address in the hdac */ 1353 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1354 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1355 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1356 1357 /* Setup the WP and RP */ 1358 sc->rirb_rp = 0; 1359 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1360 1361 /* Setup the interrupt threshold */ 1362 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1363 1364 /* Enable Overrun and response received reporting */ 1365#if 0 1366 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1367 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1368#else 1369 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1370#endif 1371 1372 /* 1373 * Make sure that the Host CPU cache doesn't contain any dirty 1374 * cache lines that falls in the rirb. If I understood correctly, it 1375 * should be sufficient to do this only once as the rirb is purely 1376 * read-only from now on. 1377 */ 1378 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1379 BUS_DMASYNC_PREREAD); 1380} 1381 1382/**************************************************************************** 1383 * void hdac_corb_start(hdac_softc *) 1384 * 1385 * Startup the corb DMA engine 1386 ****************************************************************************/ 1387static void 1388hdac_corb_start(struct hdac_softc *sc) 1389{ 1390 uint32_t corbctl; 1391 1392 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1393 corbctl |= HDAC_CORBCTL_CORBRUN; 1394 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1395} 1396 1397/**************************************************************************** 1398 * void hdac_rirb_start(hdac_softc *) 1399 * 1400 * Startup the rirb DMA engine 1401 ****************************************************************************/ 1402static void 1403hdac_rirb_start(struct hdac_softc *sc) 1404{ 1405 uint32_t rirbctl; 1406 1407 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1408 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1409 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1410} 1411 1412 1413/**************************************************************************** 1414 * void hdac_scan_codecs(struct hdac_softc *) 1415 * 1416 * Scan the bus for available codecs. 1417 ****************************************************************************/ 1418static void 1419hdac_scan_codecs(struct hdac_softc *sc) 1420{ 1421 struct hdac_codec *codec; 1422 int i; 1423 uint16_t statests; 1424 1425 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1426 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1427 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1428 /* We have found a codec. */ 1429 hdac_unlock(sc); 1430 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1431 M_HDAC, M_ZERO | M_NOWAIT); 1432 hdac_lock(sc); 1433 if (codec == NULL) { 1434 device_printf(sc->dev, 1435 "Unable to allocate memory for codec\n"); 1436 continue; 1437 } 1438 codec->verbs_sent = 0; 1439 codec->sc = sc; 1440 codec->cad = i; 1441 sc->codecs[i] = codec; 1442 if (hdac_probe_codec(codec) != 0) 1443 break; 1444 } 1445 } 1446 /* All codecs have been probed, now try to attach drivers to them */ 1447 /* bus_generic_attach(sc->dev); */ 1448} 1449 1450/**************************************************************************** 1451 * void hdac_probe_codec(struct hdac_softc *, int) 1452 * 1453 * Probe a the given codec_id for available function groups. 1454 ****************************************************************************/ 1455static int 1456hdac_probe_codec(struct hdac_codec *codec) 1457{ 1458 struct hdac_softc *sc = codec->sc; 1459 struct hdac_devinfo *devinfo; 1460 uint32_t vendorid, revisionid, subnode; 1461 int startnode; 1462 int endnode; 1463 int i; 1464 nid_t cad = codec->cad; 1465 1466 HDA_BOOTVERBOSE( 1467 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1468 ); 1469 vendorid = hdac_command(sc, 1470 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1471 cad); 1472 revisionid = hdac_command(sc, 1473 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1474 cad); 1475 subnode = hdac_command(sc, 1476 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1477 cad); 1478 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1479 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1480 1481 HDA_BOOTVERBOSE( 1482 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1483 startnode, endnode); 1484 ); 1485 for (i = startnode; i < endnode; i++) { 1486 devinfo = hdac_probe_function(codec, i); 1487 if (devinfo != NULL) { 1488 /* XXX Ignore other FG. */ 1489 devinfo->vendor_id = 1490 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1491 devinfo->device_id = 1492 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1493 devinfo->revision_id = 1494 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1495 devinfo->stepping_id = 1496 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1497 HDA_BOOTVERBOSE( 1498 device_printf(sc->dev, 1499 "HDA_DEBUG: \tFound AFG nid=%d " 1500 "[startnode=%d endnode=%d]\n", 1501 devinfo->nid, startnode, endnode); 1502 ); 1503 return (1); 1504 } 1505 } 1506 1507 HDA_BOOTVERBOSE( 1508 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1509 ); 1510 return (0); 1511} 1512 1513static struct hdac_devinfo * 1514hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1515{ 1516 struct hdac_softc *sc = codec->sc; 1517 struct hdac_devinfo *devinfo; 1518 uint32_t fctgrptype; 1519 nid_t cad = codec->cad; 1520 1521 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1522 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1523 1524 /* XXX For now, ignore other FG. */ 1525 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1526 return (NULL); 1527 1528 hdac_unlock(sc); 1529 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1530 M_NOWAIT | M_ZERO); 1531 hdac_lock(sc); 1532 if (devinfo == NULL) { 1533 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1534 __func__); 1535 return (NULL); 1536 } 1537 1538 devinfo->nid = nid; 1539 devinfo->node_type = fctgrptype; 1540 devinfo->codec = codec; 1541 1542 hdac_add_child(sc, devinfo); 1543 1544 return (devinfo); 1545} 1546 1547static void 1548hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1549{ 1550 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1551 device_set_ivars(devinfo->dev, (void *)devinfo); 1552 /* XXX - Print more information when booting verbose??? */ 1553} 1554 1555static void 1556hdac_widget_connection_parse(struct hdac_widget *w) 1557{ 1558 struct hdac_softc *sc = w->devinfo->codec->sc; 1559 uint32_t res; 1560 int i, j, max, found, entnum, cnid; 1561 nid_t cad = w->devinfo->codec->cad; 1562 nid_t nid = w->nid; 1563 1564 res = hdac_command(sc, 1565 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1566 1567 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1568 1569 if (w->nconns < 1) 1570 return; 1571 1572 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1573 res = 0; 1574 i = 0; 1575 found = 0; 1576 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1577 1578 while (i < w->nconns) { 1579 res = hdac_command(sc, 1580 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1581 for (j = 0; j < entnum; j++) { 1582 cnid = res; 1583 cnid >>= (32 / entnum) * j; 1584 cnid &= (1 << (32 / entnum)) - 1; 1585 if (cnid == 0) 1586 continue; 1587 if (found > max) { 1588 device_printf(sc->dev, 1589 "node %d: Adding %d: " 1590 "Max connection reached!\n", 1591 nid, cnid); 1592 continue; 1593 } 1594 w->conns[found++] = cnid; 1595 } 1596 i += entnum; 1597 } 1598 1599 HDA_BOOTVERBOSE( 1600 if (w->nconns != found) { 1601 device_printf(sc->dev, 1602 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1603 "length=%d != found=%d\n", 1604 nid, w->nconns, found); 1605 } 1606 ); 1607} 1608 1609static uint32_t 1610hdac_widget_pin_getconfig(struct hdac_widget *w) 1611{ 1612 struct hdac_softc *sc; 1613 uint32_t config, id; 1614 nid_t cad, nid; 1615 1616 sc = w->devinfo->codec->sc; 1617 cad = w->devinfo->codec->cad; 1618 nid = w->nid; 1619 id = hdac_codec_id(w->devinfo); 1620 1621 config = hdac_command(sc, 1622 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1623 cad); 1624 /* 1625 * XXX REWRITE!!!! Don't argue! 1626 */ 1627 if (id == HDA_CODEC_ALC880 && 1628 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1629 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1630 /* 1631 * Super broken BIOS 1632 */ 1633 switch (nid) { 1634 case 20: 1635 break; 1636 case 21: 1637 break; 1638 case 22: 1639 break; 1640 case 23: 1641 break; 1642 case 24: /* MIC1 */ 1643 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1644 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1645 break; 1646 case 25: /* XXX MIC2 */ 1647 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1648 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1649 break; 1650 case 26: /* LINE1 */ 1651 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1652 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1653 break; 1654 case 27: /* XXX LINE2 */ 1655 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1656 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1657 break; 1658 case 28: /* CD */ 1659 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1660 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1661 break; 1662 case 30: 1663 break; 1664 case 31: 1665 break; 1666 default: 1667 break; 1668 } 1669 } 1670 1671 return (config); 1672} 1673 1674static void 1675hdac_widget_pin_parse(struct hdac_widget *w) 1676{ 1677 struct hdac_softc *sc = w->devinfo->codec->sc; 1678 uint32_t config, pincap; 1679 char *devstr, *connstr; 1680 nid_t cad = w->devinfo->codec->cad; 1681 nid_t nid = w->nid; 1682 1683 config = hdac_widget_pin_getconfig(w); 1684 w->wclass.pin.config = config; 1685 1686 pincap = hdac_command(sc, 1687 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1688 w->wclass.pin.cap = pincap; 1689 1690 w->wclass.pin.ctrl = hdac_command(sc, 1691 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1692 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1693 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1694 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1695 1696 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1697 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1698 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1699 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1700 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1701 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1702 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1703 w->param.eapdbtl = hdac_command(sc, 1704 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1705 w->param.eapdbtl &= 0x7; 1706 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1707 } else 1708 w->param.eapdbtl = HDAC_INVALID; 1709 1710 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1711 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1712 devstr = "line out"; 1713 break; 1714 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1715 devstr = "speaker"; 1716 break; 1717 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1718 devstr = "headphones out"; 1719 break; 1720 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1721 devstr = "CD"; 1722 break; 1723 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1724 devstr = "SPDIF out"; 1725 break; 1726 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1727 devstr = "digital (other) out"; 1728 break; 1729 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1730 devstr = "modem, line side"; 1731 break; 1732 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1733 devstr = "modem, handset side"; 1734 break; 1735 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1736 devstr = "line in"; 1737 break; 1738 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1739 devstr = "AUX"; 1740 break; 1741 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1742 devstr = "Mic in"; 1743 break; 1744 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1745 devstr = "telephony"; 1746 break; 1747 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1748 devstr = "SPDIF in"; 1749 break; 1750 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1751 devstr = "digital (other) in"; 1752 break; 1753 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1754 devstr = "other"; 1755 break; 1756 default: 1757 devstr = "unknown"; 1758 break; 1759 } 1760 1761 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1762 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1763 connstr = "jack"; 1764 break; 1765 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1766 connstr = "none"; 1767 break; 1768 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1769 connstr = "fixed"; 1770 break; 1771 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1772 connstr = "jack / fixed"; 1773 break; 1774 default: 1775 connstr = "unknown"; 1776 break; 1777 } 1778 1779 strlcat(w->name, ": ", sizeof(w->name)); 1780 strlcat(w->name, devstr, sizeof(w->name)); 1781 strlcat(w->name, " (", sizeof(w->name)); 1782 strlcat(w->name, connstr, sizeof(w->name)); 1783 strlcat(w->name, ")", sizeof(w->name)); 1784} 1785 1786static void 1787hdac_widget_parse(struct hdac_widget *w) 1788{ 1789 struct hdac_softc *sc = w->devinfo->codec->sc; 1790 uint32_t wcap, cap; 1791 char *typestr; 1792 nid_t cad = w->devinfo->codec->cad; 1793 nid_t nid = w->nid; 1794 1795 wcap = hdac_command(sc, 1796 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1797 cad); 1798 w->param.widget_cap = wcap; 1799 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1800 1801 switch (w->type) { 1802 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1803 typestr = "audio output"; 1804 break; 1805 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1806 typestr = "audio input"; 1807 break; 1808 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1809 typestr = "audio mixer"; 1810 break; 1811 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1812 typestr = "audio selector"; 1813 break; 1814 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1815 typestr = "pin"; 1816 break; 1817 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1818 typestr = "power widget"; 1819 break; 1820 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1821 typestr = "volume widget"; 1822 break; 1823 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1824 typestr = "beep widget"; 1825 break; 1826 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1827 typestr = "vendor widget"; 1828 break; 1829 default: 1830 typestr = "unknown type"; 1831 break; 1832 } 1833 1834 strlcpy(w->name, typestr, sizeof(w->name)); 1835 1836 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1837 hdac_command(sc, 1838 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1839 cad); 1840 DELAY(1000); 1841 } 1842 1843 hdac_widget_connection_parse(w); 1844 1845 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1846 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1847 w->param.outamp_cap = 1848 hdac_command(sc, 1849 HDA_CMD_GET_PARAMETER(cad, nid, 1850 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1851 else 1852 w->param.outamp_cap = 1853 w->devinfo->function.audio.outamp_cap; 1854 } else 1855 w->param.outamp_cap = 0; 1856 1857 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1858 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1859 w->param.inamp_cap = 1860 hdac_command(sc, 1861 HDA_CMD_GET_PARAMETER(cad, nid, 1862 HDA_PARAM_INPUT_AMP_CAP), cad); 1863 else 1864 w->param.inamp_cap = 1865 w->devinfo->function.audio.inamp_cap; 1866 } else 1867 w->param.inamp_cap = 0; 1868 1869 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1870 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1871 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1872 cap = hdac_command(sc, 1873 HDA_CMD_GET_PARAMETER(cad, nid, 1874 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1875 w->param.supp_stream_formats = (cap != 0) ? cap : 1876 w->devinfo->function.audio.supp_stream_formats; 1877 cap = hdac_command(sc, 1878 HDA_CMD_GET_PARAMETER(cad, nid, 1879 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1880 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1881 w->devinfo->function.audio.supp_pcm_size_rate; 1882 } else { 1883 w->param.supp_stream_formats = 1884 w->devinfo->function.audio.supp_stream_formats; 1885 w->param.supp_pcm_size_rate = 1886 w->devinfo->function.audio.supp_pcm_size_rate; 1887 } 1888 } else { 1889 w->param.supp_stream_formats = 0; 1890 w->param.supp_pcm_size_rate = 0; 1891 } 1892 1893 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1894 hdac_widget_pin_parse(w); 1895} 1896 1897static struct hdac_widget * 1898hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1899{ 1900 if (devinfo == NULL || devinfo->widget == NULL || 1901 nid < devinfo->startnode || nid >= devinfo->endnode) 1902 return (NULL); 1903 return (&devinfo->widget[nid - devinfo->startnode]); 1904} 1905 1906static void 1907hdac_stream_stop(struct hdac_chan *ch) 1908{ 1909 struct hdac_softc *sc = ch->devinfo->codec->sc; 1910 uint32_t ctl; 1911 1912 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1913 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1914 HDAC_SDCTL_RUN); 1915 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1916 1917 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1918 ctl &= ~(1 << (ch->off >> 5)); 1919 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1920} 1921 1922static void 1923hdac_stream_start(struct hdac_chan *ch) 1924{ 1925 struct hdac_softc *sc = ch->devinfo->codec->sc; 1926 uint32_t ctl; 1927 1928 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1929 ctl |= 1 << (ch->off >> 5); 1930 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1931 1932 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1933 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1934 HDAC_SDCTL_RUN; 1935 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1936} 1937 1938static void 1939hdac_stream_reset(struct hdac_chan *ch) 1940{ 1941 struct hdac_softc *sc = ch->devinfo->codec->sc; 1942 int timeout = 1000; 1943 int to = timeout; 1944 uint32_t ctl; 1945 1946 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1947 ctl |= HDAC_SDCTL_SRST; 1948 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1949 do { 1950 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1951 if (ctl & HDAC_SDCTL_SRST) 1952 break; 1953 DELAY(10); 1954 } while (--to); 1955 if (!(ctl & HDAC_SDCTL_SRST)) { 1956 device_printf(sc->dev, "timeout in reset\n"); 1957 } 1958 ctl &= ~HDAC_SDCTL_SRST; 1959 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1960 to = timeout; 1961 do { 1962 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1963 if (!(ctl & HDAC_SDCTL_SRST)) 1964 break; 1965 DELAY(10); 1966 } while (--to); 1967 if (ctl & HDAC_SDCTL_SRST) 1968 device_printf(sc->dev, "can't reset!\n"); 1969} 1970 1971static void 1972hdac_stream_setid(struct hdac_chan *ch) 1973{ 1974 struct hdac_softc *sc = ch->devinfo->codec->sc; 1975 uint32_t ctl; 1976 1977 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 1978 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1979 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 1980 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 1981} 1982 1983static void 1984hdac_bdl_setup(struct hdac_chan *ch) 1985{ 1986 struct hdac_softc *sc = ch->devinfo->codec->sc; 1987 uint64_t addr; 1988 int blks, size, blocksize; 1989 struct hdac_bdle *bdle; 1990 int i; 1991 1992 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 1993 size = sndbuf_getsize(ch->b); 1994 blocksize = sndbuf_getblksz(ch->b); 1995 blks = size / blocksize; 1996 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr; 1997 1998 for (i = 0; i < blks; i++, bdle++) { 1999 bdle->addrl = (uint32_t)addr; 2000 bdle->addrh = (uint32_t)(addr >> 32); 2001 bdle->len = blocksize; 2002 bdle->ioc = 1; 2003 2004 addr += blocksize; 2005 } 2006 2007 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size); 2008 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1); 2009 addr = ch->bdl_dma.dma_paddr; 2010 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2011 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2012} 2013 2014static int 2015hdac_bdl_alloc(struct hdac_chan *ch) 2016{ 2017 struct hdac_softc *sc = ch->devinfo->codec->sc; 2018 int rc; 2019 2020 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2021 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2022 if (rc) { 2023 device_printf(sc->dev, "can't alloc bdl\n"); 2024 return (rc); 2025 } 2026 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2027 2028 return (0); 2029} 2030 2031static void 2032hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2033 int index, int lmute, int rmute, 2034 int left, int right, int dir) 2035{ 2036 uint16_t v = 0; 2037 2038 if (sc == NULL) 2039 return; 2040 2041 if (left != right || lmute != rmute) { 2042 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2043 (lmute << 7) | left; 2044 hdac_command(sc, 2045 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2046 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2047 (rmute << 7) | right; 2048 } else 2049 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2050 (lmute << 7) | left; 2051 2052 hdac_command(sc, 2053 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2054} 2055 2056static void 2057hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2058 int left, int right) 2059{ 2060 struct hdac_softc *sc; 2061 nid_t nid, cad; 2062 int lmute, rmute; 2063 2064 if (ctl == NULL || ctl->widget == NULL || 2065 ctl->widget->devinfo == NULL || 2066 ctl->widget->devinfo->codec == NULL || 2067 ctl->widget->devinfo->codec->sc == NULL) 2068 return; 2069 2070 sc = ctl->widget->devinfo->codec->sc; 2071 cad = ctl->widget->devinfo->codec->cad; 2072 nid = ctl->widget->nid; 2073 2074 if (mute == HDA_AMP_MUTE_DEFAULT) { 2075 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2076 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2077 } else { 2078 lmute = HDA_AMP_LEFT_MUTED(mute); 2079 rmute = HDA_AMP_RIGHT_MUTED(mute); 2080 } 2081 2082 if (ctl->dir & HDA_CTL_OUT) 2083 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2084 lmute, rmute, left, right, 0); 2085 if (ctl->dir & HDA_CTL_IN) 2086 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2087 lmute, rmute, left, right, 1); 2088 ctl->left = left; 2089 ctl->right = right; 2090} 2091 2092static void 2093hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2094{ 2095 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2096 return; 2097 hdac_command(w->devinfo->codec->sc, 2098 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2099 w->nid, index), w->devinfo->codec->cad); 2100 w->selconn = index; 2101} 2102 2103 2104/**************************************************************************** 2105 * uint32_t hdac_command_sendone_internal 2106 * 2107 * Wrapper function that sends only one command to a given codec 2108 ****************************************************************************/ 2109static uint32_t 2110hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2111{ 2112 struct hdac_command_list cl; 2113 uint32_t response = HDAC_INVALID; 2114 2115 if (!hdac_lockowned(sc)) 2116 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2117 cl.num_commands = 1; 2118 cl.verbs = &verb; 2119 cl.responses = &response; 2120 2121 hdac_command_send_internal(sc, &cl, cad); 2122 2123 return (response); 2124} 2125 2126/**************************************************************************** 2127 * hdac_command_send_internal 2128 * 2129 * Send a command list to the codec via the corb. We queue as much verbs as 2130 * we can and msleep on the codec. When the interrupt get the responses 2131 * back from the rirb, it will wake us up so we can queue the remaining verbs 2132 * if any. 2133 ****************************************************************************/ 2134static void 2135hdac_command_send_internal(struct hdac_softc *sc, 2136 struct hdac_command_list *commands, nid_t cad) 2137{ 2138 struct hdac_codec *codec; 2139 int corbrp; 2140 uint32_t *corb; 2141 uint8_t rirbwp; 2142 int timeout; 2143 int retry = 10; 2144 struct hdac_rirb *rirb_base, *rirb; 2145 nid_t ucad; 2146 uint32_t utag; 2147 2148 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL) 2149 return; 2150 2151 codec = sc->codecs[cad]; 2152 codec->commands = commands; 2153 codec->responses_received = 0; 2154 codec->verbs_sent = 0; 2155 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2156 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2157 2158 do { 2159 if (codec->verbs_sent != commands->num_commands) { 2160 /* Queue as many verbs as possible */ 2161 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2162 bus_dmamap_sync(sc->corb_dma.dma_tag, 2163 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2164 while (codec->verbs_sent != commands->num_commands && 2165 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2166 sc->corb_wp++; 2167 sc->corb_wp %= sc->corb_size; 2168 corb[sc->corb_wp] = 2169 commands->verbs[codec->verbs_sent++]; 2170 } 2171 2172 /* Send the verbs to the codecs */ 2173 bus_dmamap_sync(sc->corb_dma.dma_tag, 2174 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2175 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2176 } 2177 2178 timeout = 1000; 2179 do { 2180 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2181 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2182 BUS_DMASYNC_POSTREAD); 2183 if (sc->rirb_rp != rirbwp) { 2184 do { 2185 sc->rirb_rp++; 2186 sc->rirb_rp %= sc->rirb_size; 2187 rirb = &rirb_base[sc->rirb_rp]; 2188 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2189 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2190 utag = rirb->response >> 26; 2191 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 2192 sc->codecs[ucad] != NULL) { 2193 sc->unsolq[sc->unsolq_wp++] = 2194 (ucad << 16) | 2195 (utag & 0xffff); 2196 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2197 } 2198 } else if (codec->responses_received < commands->num_commands) 2199 codec->commands->responses[codec->responses_received++] = 2200 rirb->response; 2201 } while (sc->rirb_rp != rirbwp); 2202 break; 2203 } 2204 DELAY(10); 2205 } while (--timeout); 2206 } while ((codec->verbs_sent != commands->num_commands || 2207 codec->responses_received != commands->num_commands) && 2208 --retry); 2209 2210 if (retry == 0) 2211 device_printf(sc->dev, 2212 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2213 __func__, commands->num_commands, 2214 codec->verbs_sent, codec->responses_received); 2215 2216 codec->verbs_sent = 0; 2217 2218 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2219 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2220 while (sc->unsolq_rp != sc->unsolq_wp) { 2221 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 2222 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2223 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2224 hdac_unsolicited_handler(sc->codecs[ucad], utag); 2225 } 2226 sc->unsolq_st = HDAC_UNSOLQ_READY; 2227 } 2228} 2229 2230 2231/**************************************************************************** 2232 * Device Methods 2233 ****************************************************************************/ 2234 2235/**************************************************************************** 2236 * int hdac_probe(device_t) 2237 * 2238 * Probe for the presence of an hdac. If none is found, check for a generic 2239 * match using the subclass of the device. 2240 ****************************************************************************/ 2241static int 2242hdac_probe(device_t dev) 2243{ 2244 int i, result; 2245 uint32_t model; 2246 uint16_t class, subclass; 2247 char desc[64]; 2248 2249 model = (uint32_t)pci_get_device(dev) << 16; 2250 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2251 class = pci_get_class(dev); 2252 subclass = pci_get_subclass(dev); 2253 2254 bzero(desc, sizeof(desc)); 2255 result = ENXIO; 2256 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2257 if (hdac_devices[i].model == model) { 2258 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2259 result = BUS_PROBE_DEFAULT; 2260 break; 2261 } 2262 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2263 class == PCIC_MULTIMEDIA && 2264 subclass == PCIS_MULTIMEDIA_HDA) { 2265 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2266 result = BUS_PROBE_GENERIC; 2267 break; 2268 } 2269 } 2270 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2271 subclass == PCIS_MULTIMEDIA_HDA) { 2272 strlcpy(desc, "Generic", sizeof(desc)); 2273 result = BUS_PROBE_GENERIC; 2274 } 2275 if (result != ENXIO) { 2276 strlcat(desc, " High Definition Audio Controller", 2277 sizeof(desc)); 2278 device_set_desc_copy(dev, desc); 2279 } 2280 2281 return (result); 2282} 2283 2284static void * 2285hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2286 struct pcm_channel *c, int dir) 2287{ 2288 struct hdac_devinfo *devinfo = data; 2289 struct hdac_softc *sc = devinfo->codec->sc; 2290 struct hdac_chan *ch; 2291 2292 hdac_lock(sc); 2293 if (dir == PCMDIR_PLAY) { 2294 ch = &sc->play; 2295 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2296 ch->dir = PCMDIR_PLAY; 2297 ch->sid = ++sc->streamcnt; 2298 devinfo->function.audio.playcnt++; 2299 } else { 2300 ch = &sc->rec; 2301 ch->off = devinfo->function.audio.reccnt << 5; 2302 ch->dir = PCMDIR_REC; 2303 ch->sid = ++sc->streamcnt; 2304 devinfo->function.audio.reccnt++; 2305 } 2306 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2307 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2308 ch->pcmrates[0] = 48000; 2309 ch->pcmrates[1] = 0; 2310 } 2311 ch->b = b; 2312 ch->c = c; 2313 ch->devinfo = devinfo; 2314 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2315 ch->blkcnt = sc->chan_blkcnt; 2316 hdac_unlock(sc); 2317 2318 if (hdac_bdl_alloc(ch) != 0) { 2319 ch->blkcnt = 0; 2320 return (NULL); 2321 } 2322 2323 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2324 return (NULL); 2325 2326 hdac_dma_nocache(ch->b->buf); 2327 2328 return (ch); 2329} 2330 2331static int 2332hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2333{ 2334 struct hdac_chan *ch = data; 2335 int i; 2336 2337 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2338 if (format == ch->caps.fmtlist[i]) { 2339 ch->fmt = format; 2340 return (0); 2341 } 2342 } 2343 2344 return (EINVAL); 2345} 2346 2347static int 2348hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2349{ 2350 struct hdac_chan *ch = data; 2351 uint32_t spd = 0; 2352 int i; 2353 2354 for (i = 0; ch->pcmrates[i] != 0; i++) { 2355 spd = ch->pcmrates[i]; 2356 if (spd >= speed) 2357 break; 2358 } 2359 2360 if (spd == 0) 2361 ch->spd = 48000; 2362 else 2363 ch->spd = spd; 2364 2365 return (ch->spd); 2366} 2367 2368static void 2369hdac_stream_setup(struct hdac_chan *ch) 2370{ 2371 struct hdac_softc *sc = ch->devinfo->codec->sc; 2372 int i; 2373 nid_t cad = ch->devinfo->codec->cad; 2374 uint16_t fmt; 2375 2376 fmt = 0; 2377 if (ch->fmt & AFMT_S16_LE) 2378 fmt |= ch->bit16 << 4; 2379 else if (ch->fmt & AFMT_S32_LE) 2380 fmt |= ch->bit32 << 4; 2381 else 2382 fmt |= 1 << 4; 2383 2384 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2385 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2386 fmt |= hda_rate_tab[i].base; 2387 fmt |= hda_rate_tab[i].mul; 2388 fmt |= hda_rate_tab[i].div; 2389 break; 2390 } 2391 } 2392 2393 if (ch->fmt & AFMT_STEREO) 2394 fmt |= 1; 2395 2396 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2397 2398 for (i = 0; ch->io[i] != -1; i++) { 2399 HDA_BOOTVERBOSE( 2400 device_printf(sc->dev, 2401 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2402 "fmt=0x%08x\n", 2403 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2404 ch->io[i], fmt); 2405 ); 2406 hdac_command(sc, 2407 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2408 hdac_command(sc, 2409 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2410 ch->sid << 4), cad); 2411 } 2412} 2413 2414static int 2415hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 2416{ 2417 struct hdac_chan *ch = data; 2418 2419 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz); 2420 2421 return (ch->blksz); 2422} 2423 2424static void 2425hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2426{ 2427 struct hdac_devinfo *devinfo = ch->devinfo; 2428 nid_t cad = devinfo->codec->cad; 2429 int i; 2430 2431 hdac_stream_stop(ch); 2432 2433 for (i = 0; ch->io[i] != -1; i++) { 2434 hdac_command(sc, 2435 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2436 0), cad); 2437 } 2438} 2439 2440static void 2441hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2442{ 2443 ch->ptr = 0; 2444 ch->prevptr = 0; 2445 hdac_stream_stop(ch); 2446 hdac_stream_reset(ch); 2447 hdac_bdl_setup(ch); 2448 hdac_stream_setid(ch); 2449 hdac_stream_setup(ch); 2450 hdac_stream_start(ch); 2451} 2452 2453static int 2454hdac_channel_trigger(kobj_t obj, void *data, int go) 2455{ 2456 struct hdac_chan *ch = data; 2457 struct hdac_softc *sc = ch->devinfo->codec->sc; 2458 2459 hdac_lock(sc); 2460 switch (go) { 2461 case PCMTRIG_START: 2462 hdac_channel_start(sc, ch); 2463 break; 2464 case PCMTRIG_STOP: 2465 case PCMTRIG_ABORT: 2466 hdac_channel_stop(sc, ch); 2467 break; 2468 } 2469 hdac_unlock(sc); 2470 2471 return (0); 2472} 2473 2474static int 2475hdac_channel_getptr(kobj_t obj, void *data) 2476{ 2477 struct hdac_chan *ch = data; 2478 struct hdac_softc *sc = ch->devinfo->codec->sc; 2479 int sz, delta; 2480 uint32_t ptr; 2481 2482 hdac_lock(sc); 2483 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2484 hdac_unlock(sc); 2485 2486 sz = sndbuf_getsize(ch->b); 2487 ptr %= sz; 2488 2489 if (ch->dir == PCMDIR_REC) { 2490 delta = ptr % sndbuf_getblksz(ch->b); 2491 if (delta != 0) { 2492 ptr -= delta; 2493 if (ptr < delta) 2494 ptr = sz - delta; 2495 else 2496 ptr -= delta; 2497 } 2498 } 2499 2500 return (ptr); 2501} 2502 2503static struct pcmchan_caps * 2504hdac_channel_getcaps(kobj_t obj, void *data) 2505{ 2506 return (&((struct hdac_chan *)data)->caps); 2507} 2508 2509static kobj_method_t hdac_channel_methods[] = { 2510 KOBJMETHOD(channel_init, hdac_channel_init), 2511 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2512 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2513 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2514 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2515 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2516 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2517 { 0, 0 } 2518}; 2519CHANNEL_DECLARE(hdac_channel); 2520 2521static int 2522hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2523{ 2524 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2525 struct hdac_softc *sc = devinfo->codec->sc; 2526 struct hdac_widget *w, *cw; 2527 struct hdac_audio_ctl *ctl; 2528 uint32_t mask, recmask, id; 2529 int i, j, softpcmvol; 2530 nid_t cad; 2531 2532 hdac_lock(sc); 2533 2534 mask = 0; 2535 recmask = 0; 2536 2537 id = hdac_codec_id(devinfo); 2538 cad = devinfo->codec->cad; 2539 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2540 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2541 sc->pci_subvendor) && 2542 hdac_hp_switch[i].id == id)) 2543 continue; 2544 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2545 if (w != NULL && w->enable != 0 2546 && w->type == 2547 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2548 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2549 hdac_command(sc, 2550 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2551 w->nid, 2552 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2553 HDAC_UNSOLTAG_EVENT_HP), cad); 2554 hdac_hp_switch_handler(devinfo); 2555 HDA_BOOTVERBOSE( 2556 device_printf(sc->dev, 2557 "HDA_DEBUG: Enabling headphone/speaker " 2558 "audio routing switching:\n"); 2559 device_printf(sc->dev, 2560 "HDA_DEBUG: \tindex=%d nid=%d " 2561 "pci_subvendor=0x%08x " 2562 "codec=0x%08x\n", 2563 i, w->nid, sc->pci_subvendor, id); 2564 ); 2565 } 2566 break; 2567 } 2568 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2569 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2570 sc->pci_subvendor) && 2571 hdac_eapd_switch[i].id == id)) 2572 continue; 2573 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2574 if (w == NULL || w->enable == 0) 2575 break; 2576 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2577 w->param.eapdbtl == HDAC_INVALID) 2578 break; 2579 mask |= SOUND_MASK_OGAIN; 2580 break; 2581 } 2582 2583 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2584 w = hdac_widget_get(devinfo, i); 2585 if (w == NULL || w->enable == 0) 2586 continue; 2587 mask |= w->ctlflags; 2588 if (!(w->pflags & HDA_ADC_RECSEL)) 2589 continue; 2590 for (j = 0; j < w->nconns; j++) { 2591 cw = hdac_widget_get(devinfo, w->conns[j]); 2592 if (cw == NULL || cw->enable == 0) 2593 continue; 2594 recmask |= cw->ctlflags; 2595 } 2596 } 2597 2598 if (!(mask & SOUND_MASK_PCM)) { 2599 softpcmvol = 1; 2600 mask |= SOUND_MASK_PCM; 2601 } else 2602 softpcmvol = (devinfo->function.audio.quirks & 2603 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2604 2605 i = 0; 2606 ctl = NULL; 2607 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2608 if (ctl->widget == NULL || ctl->enable == 0) 2609 continue; 2610 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2611 continue; 2612 if (ctl->step > 0) 2613 break; 2614 } 2615 2616 if (softpcmvol == 1 || ctl == NULL) { 2617 struct snddev_info *d = NULL; 2618 d = device_get_softc(sc->dev); 2619 if (d != NULL) { 2620 d->flags |= SD_F_SOFTPCMVOL; 2621 HDA_BOOTVERBOSE( 2622 device_printf(sc->dev, 2623 "HDA_DEBUG: %s Soft PCM volume\n", 2624 (softpcmvol == 1) ? 2625 "Forcing" : "Enabling"); 2626 ); 2627 } 2628 i = 0; 2629 /* 2630 * XXX Temporary quirk for STAC9220, until the parser 2631 * become smarter. 2632 */ 2633 if (id == HDA_CODEC_STAC9220) { 2634 mask |= SOUND_MASK_VOLUME; 2635 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2636 NULL) { 2637 if (ctl->widget == NULL || ctl->enable == 0) 2638 continue; 2639 if (ctl->widget->nid == 11 && ctl->index == 0) { 2640 ctl->ossmask = SOUND_MASK_VOLUME; 2641 ctl->ossval = 100 | (100 << 8); 2642 } else 2643 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2644 } 2645 } else { 2646 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2647 SOUND_MASK_PCM); 2648 if (!(mask & SOUND_MASK_VOLUME)) 2649 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2650 SOUND_MIXER_NONE); 2651 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2652 NULL) { 2653 if (ctl->widget == NULL || ctl->enable == 0) 2654 continue; 2655 if (!HDA_FLAG_MATCH(ctl->ossmask, 2656 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 2657 continue; 2658 if (!(ctl->mute == 1 && ctl->step == 0)) 2659 ctl->enable = 0; 2660 } 2661 } 2662 } 2663 2664 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2665 2666 mix_setrecdevs(m, recmask); 2667 mix_setdevs(m, mask); 2668 2669 hdac_unlock(sc); 2670 2671 return (0); 2672} 2673 2674static int 2675hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2676 unsigned left, unsigned right) 2677{ 2678 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2679 struct hdac_softc *sc = devinfo->codec->sc; 2680 struct hdac_widget *w; 2681 struct hdac_audio_ctl *ctl; 2682 uint32_t id, mute; 2683 int lvol, rvol, mlvol, mrvol; 2684 int i = 0; 2685 2686 hdac_lock(sc); 2687 if (dev == SOUND_MIXER_OGAIN) { 2688 uint32_t orig; 2689 /*if (left != right || !(left == 0 || left == 1)) { 2690 hdac_unlock(sc); 2691 return (-1); 2692 }*/ 2693 id = hdac_codec_id(devinfo); 2694 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2695 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2696 sc->pci_subvendor) && 2697 hdac_eapd_switch[i].id == id) 2698 break; 2699 } 2700 if (i >= HDAC_EAPD_SWITCH_LEN) { 2701 hdac_unlock(sc); 2702 return (-1); 2703 } 2704 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2705 if (w == NULL || 2706 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2707 w->param.eapdbtl == HDAC_INVALID) { 2708 hdac_unlock(sc); 2709 return (-1); 2710 } 2711 orig = w->param.eapdbtl; 2712 if (left == 0) 2713 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2714 else 2715 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2716 if (orig != w->param.eapdbtl) { 2717 if (hdac_eapd_switch[i].hp_switch != 0) 2718 hdac_hp_switch_handler(devinfo); 2719 hdac_command(sc, 2720 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 2721 w->nid, w->param.eapdbtl), devinfo->codec->cad); 2722 } 2723 hdac_unlock(sc); 2724 return (left | (left << 8)); 2725 } 2726 if (dev == SOUND_MIXER_VOLUME) 2727 devinfo->function.audio.mvol = left | (right << 8); 2728 2729 mlvol = devinfo->function.audio.mvol & 0x7f; 2730 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2731 lvol = 0; 2732 rvol = 0; 2733 2734 i = 0; 2735 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2736 if (ctl->widget == NULL || ctl->enable == 0 || 2737 !(ctl->ossmask & (1 << dev))) 2738 continue; 2739 switch (dev) { 2740 case SOUND_MIXER_VOLUME: 2741 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2742 lvol = (lvol * ctl->step) / 100; 2743 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2744 rvol = (rvol * ctl->step) / 100; 2745 break; 2746 default: 2747 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2748 lvol = (left * mlvol) / 100; 2749 lvol = (lvol * ctl->step) / 100; 2750 rvol = (right * mrvol) / 100; 2751 rvol = (rvol * ctl->step) / 100; 2752 } else { 2753 lvol = (left * ctl->step) / 100; 2754 rvol = (right * ctl->step) / 100; 2755 } 2756 ctl->ossval = left | (right << 8); 2757 break; 2758 } 2759 mute = 0; 2760 if (ctl->step < 1) { 2761 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2762 (ctl->muted & HDA_AMP_MUTE_LEFT); 2763 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2764 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2765 } else { 2766 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2767 (ctl->muted & HDA_AMP_MUTE_LEFT); 2768 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2769 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2770 } 2771 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2772 } 2773 hdac_unlock(sc); 2774 2775 return (left | (right << 8)); 2776} 2777 2778static int 2779hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2780{ 2781 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2782 struct hdac_widget *w, *cw; 2783 struct hdac_softc *sc = devinfo->codec->sc; 2784 uint32_t ret = src, target; 2785 int i, j; 2786 2787 target = 0; 2788 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2789 if (src & (1 << i)) { 2790 target = 1 << i; 2791 break; 2792 } 2793 } 2794 2795 hdac_lock(sc); 2796 2797 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2798 w = hdac_widget_get(devinfo, i); 2799 if (w == NULL || w->enable == 0) 2800 continue; 2801 if (!(w->pflags & HDA_ADC_RECSEL)) 2802 continue; 2803 for (j = 0; j < w->nconns; j++) { 2804 cw = hdac_widget_get(devinfo, w->conns[j]); 2805 if (cw == NULL || cw->enable == 0) 2806 continue; 2807 if ((target == SOUND_MASK_VOLUME && 2808 cw->type != 2809 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 2810 (target != SOUND_MASK_VOLUME && 2811 cw->type == 2812 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 2813 continue; 2814 if (cw->ctlflags & target) { 2815 hdac_widget_connection_select(w, j); 2816 ret = target; 2817 j += w->nconns; 2818 } 2819 } 2820 } 2821 2822 hdac_unlock(sc); 2823 2824 return (ret); 2825} 2826 2827static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 2828 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 2829 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 2830 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 2831 { 0, 0 } 2832}; 2833MIXER_DECLARE(hdac_audio_ctl_ossmixer); 2834 2835/**************************************************************************** 2836 * int hdac_attach(device_t) 2837 * 2838 * Attach the device into the kernel. Interrupts usually won't be enabled 2839 * when this function is called. Setup everything that doesn't require 2840 * interrupts and defer probing of codecs until interrupts are enabled. 2841 ****************************************************************************/ 2842static int 2843hdac_attach(device_t dev) 2844{ 2845 struct hdac_softc *sc; 2846 int result; 2847 int i = 0; 2848 2849 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 2850 if (sc == NULL) { 2851 device_printf(dev, "cannot allocate softc\n"); 2852 return (ENOMEM); 2853 } 2854 2855 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 2856 if (sc->lock == NULL) { 2857 device_printf(dev, "mutex creation failed\n"); 2858 free(sc, M_DEVBUF); 2859 return (ENOMEM); 2860 } 2861 2862 sc->dev = dev; 2863 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 2864 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 2865 2866 sc->chan_size = pcm_getbuffersize(dev, 2867 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT); 2868 if (resource_int_value(device_get_name(sc->dev), 2869 device_get_unit(sc->dev), "blocksize", &i) == 0 && 2870 i > 0) { 2871 sc->chan_blkcnt = sc->chan_size / i; 2872 i = 0; 2873 while (sc->chan_blkcnt >> i) 2874 i++; 2875 sc->chan_blkcnt = 1 << (i - 1); 2876 if (sc->chan_blkcnt < HDA_BDL_MIN) 2877 sc->chan_blkcnt = HDA_BDL_MIN; 2878 else if (sc->chan_blkcnt > HDA_BDL_MAX) 2879 sc->chan_blkcnt = HDA_BDL_MAX; 2880 } else 2881 sc->chan_blkcnt = HDA_BDL_DEFAULT; 2882 2883 result = bus_dma_tag_create(NULL, /* parent */ 2884 HDAC_DMA_ALIGNMENT, /* alignment */ 2885 0, /* boundary */ 2886 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2887 BUS_SPACE_MAXADDR, /* highaddr */ 2888 NULL, /* filtfunc */ 2889 NULL, /* fistfuncarg */ 2890 sc->chan_size, /* maxsize */ 2891 1, /* nsegments */ 2892 sc->chan_size, /* maxsegsz */ 2893 0, /* flags */ 2894 NULL, /* lockfunc */ 2895 NULL, /* lockfuncarg */ 2896 &sc->chan_dmat); /* dmat */ 2897 if (result != 0) { 2898 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 2899 __func__, result); 2900 snd_mtxfree(sc->lock); 2901 free(sc, M_DEVBUF); 2902 return (ENXIO); 2903 } 2904 2905 2906 sc->hdabus = NULL; 2907 for (i = 0; i < HDAC_CODEC_MAX; i++) 2908 sc->codecs[i] = NULL; 2909 2910 pci_enable_busmaster(dev); 2911 2912 /* Allocate resources */ 2913 result = hdac_mem_alloc(sc); 2914 if (result != 0) 2915 goto hdac_attach_fail; 2916 result = hdac_irq_alloc(sc); 2917 if (result != 0) 2918 goto hdac_attach_fail; 2919 2920 /* Get Capabilities */ 2921 result = hdac_get_capabilities(sc); 2922 if (result != 0) 2923 goto hdac_attach_fail; 2924 2925 /* Allocate CORB and RIRB dma memory */ 2926 result = hdac_dma_alloc(sc, &sc->corb_dma, 2927 sc->corb_size * sizeof(uint32_t)); 2928 if (result != 0) 2929 goto hdac_attach_fail; 2930 result = hdac_dma_alloc(sc, &sc->rirb_dma, 2931 sc->rirb_size * sizeof(struct hdac_rirb)); 2932 if (result != 0) 2933 goto hdac_attach_fail; 2934 2935 /* Quiesce everything */ 2936 hdac_reset(sc); 2937 2938 /* Disable PCI-Express QOS */ 2939 pci_write_config(sc->dev, 0x44, 2940 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 2941 2942 /* Initialize the CORB and RIRB */ 2943 hdac_corb_init(sc); 2944 hdac_rirb_init(sc); 2945 2946 /* Defer remaining of initialization until interrupts are enabled */ 2947 sc->intrhook.ich_func = hdac_attach2; 2948 sc->intrhook.ich_arg = (void *)sc; 2949 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 2950 sc->intrhook.ich_func = NULL; 2951 hdac_attach2((void *)sc); 2952 } 2953 2954 return (0); 2955 2956hdac_attach_fail: 2957 hdac_dma_free(&sc->rirb_dma); 2958 hdac_dma_free(&sc->corb_dma); 2959 hdac_irq_free(sc); 2960 hdac_mem_free(sc); 2961 snd_mtxfree(sc->lock); 2962 free(sc, M_DEVBUF); 2963 2964 return (ENXIO); 2965} 2966 2967static void 2968hdac_audio_parse(struct hdac_devinfo *devinfo) 2969{ 2970 struct hdac_softc *sc = devinfo->codec->sc; 2971 struct hdac_widget *w; 2972 uint32_t res; 2973 int i; 2974 nid_t cad, nid; 2975 2976 cad = devinfo->codec->cad; 2977 nid = devinfo->nid; 2978 2979 hdac_command(sc, 2980 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 2981 2982 DELAY(100); 2983 2984 res = hdac_command(sc, 2985 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2986 2987 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2988 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2989 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2990 2991 HDA_BOOTVERBOSE( 2992 device_printf(sc->dev, " Vendor: 0x%08x\n", 2993 devinfo->vendor_id); 2994 device_printf(sc->dev, " Device: 0x%08x\n", 2995 devinfo->device_id); 2996 device_printf(sc->dev, " Revision: 0x%08x\n", 2997 devinfo->revision_id); 2998 device_printf(sc->dev, " Stepping: 0x%08x\n", 2999 devinfo->stepping_id); 3000 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3001 sc->pci_subvendor); 3002 device_printf(sc->dev, " Nodes: start=%d " 3003 "endnode=%d total=%d\n", 3004 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3005 ); 3006 3007 res = hdac_command(sc, 3008 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3009 cad); 3010 devinfo->function.audio.supp_stream_formats = res; 3011 3012 res = hdac_command(sc, 3013 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3014 cad); 3015 devinfo->function.audio.supp_pcm_size_rate = res; 3016 3017 res = hdac_command(sc, 3018 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3019 cad); 3020 devinfo->function.audio.outamp_cap = res; 3021 3022 res = hdac_command(sc, 3023 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3024 cad); 3025 devinfo->function.audio.inamp_cap = res; 3026 3027 if (devinfo->nodecnt > 0) { 3028 hdac_unlock(sc); 3029 devinfo->widget = (struct hdac_widget *)malloc( 3030 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3031 M_NOWAIT | M_ZERO); 3032 hdac_lock(sc); 3033 } else 3034 devinfo->widget = NULL; 3035 3036 if (devinfo->widget == NULL) { 3037 device_printf(sc->dev, "unable to allocate widgets!\n"); 3038 devinfo->endnode = devinfo->startnode; 3039 devinfo->nodecnt = 0; 3040 return; 3041 } 3042 3043 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3044 w = hdac_widget_get(devinfo, i); 3045 if (w == NULL) 3046 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3047 else { 3048 w->devinfo = devinfo; 3049 w->nid = i; 3050 w->enable = 1; 3051 w->selconn = -1; 3052 w->pflags = 0; 3053 w->ctlflags = 0; 3054 w->param.eapdbtl = HDAC_INVALID; 3055 hdac_widget_parse(w); 3056 } 3057 } 3058} 3059 3060static void 3061hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3062{ 3063 struct hdac_softc *sc = devinfo->codec->sc; 3064 struct hdac_audio_ctl *ctls; 3065 struct hdac_widget *w, *cw; 3066 int i, j, cnt, max, ocap, icap; 3067 int mute, offset, step, size; 3068 3069 /* XXX This is redundant */ 3070 max = 0; 3071 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3072 w = hdac_widget_get(devinfo, i); 3073 if (w == NULL || w->enable == 0) 3074 continue; 3075 if (w->param.outamp_cap != 0) 3076 max++; 3077 if (w->param.inamp_cap != 0) { 3078 switch (w->type) { 3079 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3080 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3081 for (j = 0; j < w->nconns; j++) { 3082 cw = hdac_widget_get(devinfo, 3083 w->conns[j]); 3084 if (cw == NULL || cw->enable == 0) 3085 continue; 3086 max++; 3087 } 3088 break; 3089 default: 3090 max++; 3091 break; 3092 } 3093 } 3094 } 3095 3096 devinfo->function.audio.ctlcnt = max; 3097 3098 if (max < 1) 3099 return; 3100 3101 hdac_unlock(sc); 3102 ctls = (struct hdac_audio_ctl *)malloc( 3103 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3104 hdac_lock(sc); 3105 3106 if (ctls == NULL) { 3107 /* Blekh! */ 3108 device_printf(sc->dev, "unable to allocate ctls!\n"); 3109 devinfo->function.audio.ctlcnt = 0; 3110 return; 3111 } 3112 3113 cnt = 0; 3114 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3115 if (cnt >= max) { 3116 device_printf(sc->dev, "%s: Ctl overflow!\n", 3117 __func__); 3118 break; 3119 } 3120 w = hdac_widget_get(devinfo, i); 3121 if (w == NULL || w->enable == 0) 3122 continue; 3123 ocap = w->param.outamp_cap; 3124 icap = w->param.inamp_cap; 3125 if (ocap != 0) { 3126 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3127 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3128 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3129 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3130 /*if (offset > step) { 3131 HDA_BOOTVERBOSE( 3132 device_printf(sc->dev, 3133 "HDA_DEBUG: BUGGY outamp: nid=%d " 3134 "[offset=%d > step=%d]\n", 3135 w->nid, offset, step); 3136 ); 3137 offset = step; 3138 }*/ 3139 ctls[cnt].enable = 1; 3140 ctls[cnt].widget = w; 3141 ctls[cnt].mute = mute; 3142 ctls[cnt].step = step; 3143 ctls[cnt].size = size; 3144 ctls[cnt].offset = offset; 3145 ctls[cnt].left = offset; 3146 ctls[cnt].right = offset; 3147 ctls[cnt++].dir = HDA_CTL_OUT; 3148 } 3149 3150 if (icap != 0) { 3151 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3152 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3153 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3154 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3155 /*if (offset > step) { 3156 HDA_BOOTVERBOSE( 3157 device_printf(sc->dev, 3158 "HDA_DEBUG: BUGGY inamp: nid=%d " 3159 "[offset=%d > step=%d]\n", 3160 w->nid, offset, step); 3161 ); 3162 offset = step; 3163 }*/ 3164 switch (w->type) { 3165 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3166 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3167 for (j = 0; j < w->nconns; j++) { 3168 if (cnt >= max) { 3169 device_printf(sc->dev, 3170 "%s: Ctl overflow!\n", 3171 __func__); 3172 break; 3173 } 3174 cw = hdac_widget_get(devinfo, 3175 w->conns[j]); 3176 if (cw == NULL || cw->enable == 0) 3177 continue; 3178 ctls[cnt].enable = 1; 3179 ctls[cnt].widget = w; 3180 ctls[cnt].childwidget = cw; 3181 ctls[cnt].index = j; 3182 ctls[cnt].mute = mute; 3183 ctls[cnt].step = step; 3184 ctls[cnt].size = size; 3185 ctls[cnt].offset = offset; 3186 ctls[cnt].left = offset; 3187 ctls[cnt].right = offset; 3188 ctls[cnt++].dir = HDA_CTL_IN; 3189 } 3190 break; 3191 default: 3192 if (cnt >= max) { 3193 device_printf(sc->dev, 3194 "%s: Ctl overflow!\n", 3195 __func__); 3196 break; 3197 } 3198 ctls[cnt].enable = 1; 3199 ctls[cnt].widget = w; 3200 ctls[cnt].mute = mute; 3201 ctls[cnt].step = step; 3202 ctls[cnt].size = size; 3203 ctls[cnt].offset = offset; 3204 ctls[cnt].left = offset; 3205 ctls[cnt].right = offset; 3206 ctls[cnt++].dir = HDA_CTL_IN; 3207 break; 3208 } 3209 } 3210 } 3211 3212 devinfo->function.audio.ctl = ctls; 3213} 3214 3215static const struct { 3216 uint32_t model; 3217 uint32_t id; 3218 uint32_t set, unset; 3219} hdac_quirks[] = { 3220 /* 3221 * XXX Fixed rate quirk. Other than 48000 3222 * sounds pretty much like train wreck. 3223 * 3224 * XXX Force stereo quirk. Monoural recording / playback 3225 * on few codecs (especially ALC880) seems broken or 3226 * perhaps unsupported. 3227 */ 3228 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3229 HDA_QUIRK_FIXEDRATE | HDA_QUIRK_FORCESTEREO, 0 }, 3230 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3231 HDA_QUIRK_GPIO1, 0 }, 3232 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3233 HDA_QUIRK_GPIO1, 0 }, 3234 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3235 0, HDA_QUIRK_FORCESTEREO }, 3236 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3237 HDA_QUIRK_SOFTPCMVOL, 0 } 3238}; 3239#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3240 3241static void 3242hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3243{ 3244 struct hdac_widget *w; 3245 uint32_t id, subvendor; 3246 int i; 3247 3248 id = hdac_codec_id(devinfo); 3249 subvendor = devinfo->codec->sc->pci_subvendor; 3250 3251 /* 3252 * Quirks 3253 */ 3254 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3255 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3256 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3257 continue; 3258 if (hdac_quirks[i].set != 0) 3259 devinfo->function.audio.quirks |= 3260 hdac_quirks[i].set; 3261 if (hdac_quirks[i].unset != 0) 3262 devinfo->function.audio.quirks &= 3263 ~(hdac_quirks[i].unset); 3264 } 3265 3266 switch (id) { 3267 case HDA_CODEC_ALC260: 3268 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3269 w = hdac_widget_get(devinfo, i); 3270 if (w == NULL || w->enable == 0) 3271 continue; 3272 if (w->type != 3273 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3274 continue; 3275 if (w->nid != 5) 3276 w->enable = 0; 3277 } 3278 break; 3279 case HDA_CODEC_ALC880: 3280 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3281 w = hdac_widget_get(devinfo, i); 3282 if (w == NULL || w->enable == 0) 3283 continue; 3284 if (w->type == 3285 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3286 w->nid != 9 && w->nid != 29) { 3287 w->enable = 0; 3288 } else if (w->type != 3289 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3290 w->nid == 29) { 3291 w->type = 3292 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3293 w->param.widget_cap &= 3294 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3295 w->param.widget_cap |= 3296 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3297 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3298 strlcpy(w->name, "beep widget", sizeof(w->name)); 3299 } 3300 } 3301 break; 3302 case HDA_CODEC_AD1981HD: 3303 w = hdac_widget_get(devinfo, 11); 3304 if (w != NULL && w->enable != 0 && w->nconns > 3) 3305 w->selconn = 3; 3306 if (subvendor == IBM_M52_SUBVENDOR) { 3307 struct hdac_audio_ctl *ctl; 3308 3309 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3310 if (ctl != NULL) 3311 ctl->ossmask = SOUND_MASK_SPEAKER; 3312 } 3313 break; 3314 case HDA_CODEC_AD1986A: 3315 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3316 w = hdac_widget_get(devinfo, i); 3317 if (w == NULL || w->enable == 0) 3318 continue; 3319 if (w->type != 3320 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3321 continue; 3322 if (w->nid != 3) 3323 w->enable = 0; 3324 } 3325 break; 3326 case HDA_CODEC_STAC9221: 3327 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3328 w = hdac_widget_get(devinfo, i); 3329 if (w == NULL || w->enable == 0) 3330 continue; 3331 if (w->type != 3332 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3333 continue; 3334 if (w->nid != 2) 3335 w->enable = 0; 3336 } 3337 break; 3338 case HDA_CODEC_STAC9221D: 3339 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3340 w = hdac_widget_get(devinfo, i); 3341 if (w == NULL || w->enable == 0) 3342 continue; 3343 if (w->type == 3344 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3345 w->nid != 6) 3346 w->enable = 0; 3347 3348 } 3349 break; 3350 default: 3351 break; 3352 } 3353} 3354 3355static int 3356hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3357{ 3358 int *dev = &devinfo->function.audio.ossidx; 3359 3360 while (*dev < SOUND_MIXER_NRDEVICES) { 3361 switch (*dev) { 3362 case SOUND_MIXER_VOLUME: 3363 case SOUND_MIXER_BASS: 3364 case SOUND_MIXER_TREBLE: 3365 case SOUND_MIXER_PCM: 3366 case SOUND_MIXER_SPEAKER: 3367 case SOUND_MIXER_LINE: 3368 case SOUND_MIXER_MIC: 3369 case SOUND_MIXER_CD: 3370 case SOUND_MIXER_RECLEV: 3371 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3372 (*dev)++; 3373 break; 3374 default: 3375 return (*dev)++; 3376 break; 3377 } 3378 } 3379 3380 return (-1); 3381} 3382 3383static int 3384hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3385{ 3386 struct hdac_widget *w; 3387 int i, ret = 0; 3388 3389 if (depth > HDA_PARSE_MAXDEPTH) 3390 return (0); 3391 w = hdac_widget_get(devinfo, nid); 3392 if (w == NULL || w->enable == 0) 3393 return (0); 3394 switch (w->type) { 3395 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3396 w->pflags |= HDA_DAC_PATH; 3397 ret = 1; 3398 break; 3399 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3400 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3401 for (i = 0; i < w->nconns; i++) { 3402 if (hdac_widget_find_dac_path(devinfo, 3403 w->conns[i], depth + 1) != 0) { 3404 if (w->selconn == -1) 3405 w->selconn = i; 3406 ret = 1; 3407 w->pflags |= HDA_DAC_PATH; 3408 } 3409 } 3410 break; 3411 default: 3412 break; 3413 } 3414 return (ret); 3415} 3416 3417static int 3418hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3419{ 3420 struct hdac_widget *w; 3421 int i, conndev, ret = 0; 3422 3423 if (depth > HDA_PARSE_MAXDEPTH) 3424 return (0); 3425 w = hdac_widget_get(devinfo, nid); 3426 if (w == NULL || w->enable == 0) 3427 return (0); 3428 switch (w->type) { 3429 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3430 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3431 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3432 for (i = 0; i < w->nconns; i++) { 3433 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3434 depth + 1) != 0) { 3435 if (w->selconn == -1) 3436 w->selconn = i; 3437 w->pflags |= HDA_ADC_PATH; 3438 ret = 1; 3439 } 3440 } 3441 break; 3442 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3443 conndev = w->wclass.pin.config & 3444 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3445 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3446 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3447 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3448 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3449 w->pflags |= HDA_ADC_PATH; 3450 ret = 1; 3451 } 3452 break; 3453 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3454 if (w->pflags & HDA_DAC_PATH) { 3455 w->pflags |= HDA_ADC_PATH; 3456 ret = 1; 3457 } 3458 break;*/ 3459 default: 3460 break; 3461 } 3462 return (ret); 3463} 3464 3465static uint32_t 3466hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3467 nid_t nid, nid_t pnid, int index, int depth) 3468{ 3469 struct hdac_widget *w, *pw; 3470 struct hdac_audio_ctl *ctl; 3471 uint32_t fl = 0; 3472 int i, ossdev, conndev, strategy; 3473 3474 if (depth > HDA_PARSE_MAXDEPTH) 3475 return (0); 3476 3477 w = hdac_widget_get(devinfo, nid); 3478 if (w == NULL || w->enable == 0) 3479 return (0); 3480 3481 pw = hdac_widget_get(devinfo, pnid); 3482 strategy = devinfo->function.audio.parsing_strategy; 3483 3484 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3485 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3486 for (i = 0; i < w->nconns; i++) { 3487 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3488 w->nid, i, depth + 1); 3489 } 3490 w->ctlflags |= fl; 3491 return (fl); 3492 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3493 (w->pflags & HDA_DAC_PATH)) { 3494 i = 0; 3495 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3496 if (ctl->enable == 0 || ctl->widget == NULL) 3497 continue; 3498 /* XXX This should be compressed! */ 3499 if ((ctl->widget->nid == w->nid) || 3500 (ctl->widget->nid == pnid && ctl->index == index && 3501 (ctl->dir & HDA_CTL_IN)) || 3502 (ctl->widget->nid == pnid && pw != NULL && 3503 pw->type == 3504 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3505 (pw->nconns < 2 || pw->selconn == index || 3506 pw->selconn == -1) && 3507 (ctl->dir & HDA_CTL_OUT)) || 3508 (strategy == HDA_PARSE_DIRECT && 3509 ctl->widget->nid == w->nid)) { 3510 /*if (pw != NULL && pw->selconn == -1) 3511 pw->selconn = index; 3512 fl |= SOUND_MASK_VOLUME; 3513 fl |= SOUND_MASK_PCM; 3514 ctl->ossmask |= SOUND_MASK_VOLUME; 3515 ctl->ossmask |= SOUND_MASK_PCM; 3516 ctl->ossdev = SOUND_MIXER_PCM;*/ 3517 if (!(w->ctlflags & SOUND_MASK_PCM) || 3518 (pw != NULL && 3519 !(pw->ctlflags & SOUND_MASK_PCM))) { 3520 fl |= SOUND_MASK_VOLUME; 3521 fl |= SOUND_MASK_PCM; 3522 ctl->ossmask |= SOUND_MASK_VOLUME; 3523 ctl->ossmask |= SOUND_MASK_PCM; 3524 ctl->ossdev = SOUND_MIXER_PCM; 3525 w->ctlflags |= SOUND_MASK_VOLUME; 3526 w->ctlflags |= SOUND_MASK_PCM; 3527 if (pw != NULL) { 3528 if (pw->selconn == -1) 3529 pw->selconn = index; 3530 pw->ctlflags |= 3531 SOUND_MASK_VOLUME; 3532 pw->ctlflags |= 3533 SOUND_MASK_PCM; 3534 } 3535 } 3536 } 3537 } 3538 w->ctlflags |= fl; 3539 return (fl); 3540 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 3541 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3542 (w->pflags & HDA_ADC_PATH)) { 3543 conndev = w->wclass.pin.config & 3544 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3545 i = 0; 3546 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3547 if (ctl->enable == 0 || ctl->widget == NULL) 3548 continue; 3549 /* XXX This should be compressed! */ 3550 if (((ctl->widget->nid == pnid && ctl->index == index && 3551 (ctl->dir & HDA_CTL_IN)) || 3552 (ctl->widget->nid == pnid && pw != NULL && 3553 pw->type == 3554 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3555 (pw->nconns < 2 || pw->selconn == index || 3556 pw->selconn == -1) && 3557 (ctl->dir & HDA_CTL_OUT)) || 3558 (strategy == HDA_PARSE_DIRECT && 3559 ctl->widget->nid == w->nid)) && 3560 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3561 if (pw != NULL && pw->selconn == -1) 3562 pw->selconn = index; 3563 ossdev = 0; 3564 switch (conndev) { 3565 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3566 ossdev = SOUND_MIXER_MIC; 3567 break; 3568 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3569 ossdev = SOUND_MIXER_LINE; 3570 break; 3571 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3572 ossdev = SOUND_MIXER_CD; 3573 break; 3574 default: 3575 ossdev = 3576 hdac_audio_ctl_ossmixer_getnextdev( 3577 devinfo); 3578 if (ossdev < 0) 3579 ossdev = 0; 3580 break; 3581 } 3582 if (strategy == HDA_PARSE_MIXER) { 3583 fl |= SOUND_MASK_VOLUME; 3584 ctl->ossmask |= SOUND_MASK_VOLUME; 3585 } 3586 fl |= 1 << ossdev; 3587 ctl->ossmask |= 1 << ossdev; 3588 ctl->ossdev = ossdev; 3589 } 3590 } 3591 w->ctlflags |= fl; 3592 return (fl); 3593 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3594 i = 0; 3595 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3596 if (ctl->enable == 0 || ctl->widget == NULL) 3597 continue; 3598 /* XXX This should be compressed! */ 3599 if (((ctl->widget->nid == pnid && ctl->index == index && 3600 (ctl->dir & HDA_CTL_IN)) || 3601 (ctl->widget->nid == pnid && pw != NULL && 3602 pw->type == 3603 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3604 (pw->nconns < 2 || pw->selconn == index || 3605 pw->selconn == -1) && 3606 (ctl->dir & HDA_CTL_OUT)) || 3607 (strategy == HDA_PARSE_DIRECT && 3608 ctl->widget->nid == w->nid)) && 3609 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 3610 if (pw != NULL && pw->selconn == -1) 3611 pw->selconn = index; 3612 fl |= SOUND_MASK_VOLUME; 3613 fl |= SOUND_MASK_SPEAKER; 3614 ctl->ossmask |= SOUND_MASK_VOLUME; 3615 ctl->ossmask |= SOUND_MASK_SPEAKER; 3616 ctl->ossdev = SOUND_MIXER_SPEAKER; 3617 } 3618 } 3619 w->ctlflags |= fl; 3620 return (fl); 3621 } 3622 return (0); 3623} 3624 3625static uint32_t 3626hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3627{ 3628 struct hdac_widget *w, *cw; 3629 struct hdac_audio_ctl *ctl; 3630 uint32_t fl; 3631 int i; 3632 3633 if (depth > HDA_PARSE_MAXDEPTH) 3634 return (0); 3635 3636 w = hdac_widget_get(devinfo, nid); 3637 if (w == NULL || w->enable == 0) 3638 return (0); 3639 /*if (!(w->pflags & HDA_ADC_PATH)) 3640 return (0); 3641 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3642 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3643 return (0);*/ 3644 i = 0; 3645 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3646 if (ctl->enable == 0 || ctl->widget == NULL) 3647 continue; 3648 if (ctl->widget->nid == nid) { 3649 ctl->ossmask |= SOUND_MASK_RECLEV; 3650 w->ctlflags |= SOUND_MASK_RECLEV; 3651 return (SOUND_MASK_RECLEV); 3652 } 3653 } 3654 for (i = 0; i < w->nconns; i++) { 3655 cw = hdac_widget_get(devinfo, w->conns[i]); 3656 if (cw == NULL || cw->enable == 0) 3657 continue; 3658 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3659 continue; 3660 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3661 if (fl != 0) { 3662 cw->ctlflags |= fl; 3663 w->ctlflags |= fl; 3664 return (fl); 3665 } 3666 } 3667 return (0); 3668} 3669 3670static int 3671hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3672{ 3673 struct hdac_widget *w, *cw; 3674 int i, child = 0; 3675 3676 if (depth > HDA_PARSE_MAXDEPTH) 3677 return (0); 3678 3679 w = hdac_widget_get(devinfo, nid); 3680 if (w == NULL || w->enable == 0) 3681 return (0); 3682 /*if (!(w->pflags & HDA_ADC_PATH)) 3683 return (0); 3684 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3685 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3686 return (0);*/ 3687 /* XXX weak! */ 3688 for (i = 0; i < w->nconns; i++) { 3689 cw = hdac_widget_get(devinfo, w->conns[i]); 3690 if (cw == NULL) 3691 continue; 3692 if (++child > 1) { 3693 w->pflags |= HDA_ADC_RECSEL; 3694 return (1); 3695 } 3696 } 3697 for (i = 0; i < w->nconns; i++) { 3698 if (hdac_audio_ctl_recsel_build(devinfo, 3699 w->conns[i], depth + 1) != 0) 3700 return (1); 3701 } 3702 return (0); 3703} 3704 3705static int 3706hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3707{ 3708 struct hdac_widget *w, *cw; 3709 int i, j, conndev, found_dac = 0; 3710 int strategy; 3711 3712 strategy = devinfo->function.audio.parsing_strategy; 3713 3714 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3715 w = hdac_widget_get(devinfo, i); 3716 if (w == NULL || w->enable == 0) 3717 continue; 3718 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3719 continue; 3720 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3721 continue; 3722 conndev = w->wclass.pin.config & 3723 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3724 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3725 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3726 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3727 continue; 3728 for (j = 0; j < w->nconns; j++) { 3729 cw = hdac_widget_get(devinfo, w->conns[j]); 3730 if (cw == NULL || cw->enable == 0) 3731 continue; 3732 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3733 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3734 cw->type == 3735 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3736 continue; 3737 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3738 != 0) { 3739 if (w->selconn == -1) 3740 w->selconn = j; 3741 w->pflags |= HDA_DAC_PATH; 3742 found_dac++; 3743 } 3744 } 3745 } 3746 3747 return (found_dac); 3748} 3749 3750static void 3751hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3752{ 3753 struct hdac_widget *w; 3754 struct hdac_audio_ctl *ctl; 3755 int i, j, dacs, strategy; 3756 3757 /* Construct DAC path */ 3758 strategy = HDA_PARSE_MIXER; 3759 devinfo->function.audio.parsing_strategy = strategy; 3760 HDA_BOOTVERBOSE( 3761 device_printf(devinfo->codec->sc->dev, 3762 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 3763 HDA_WIDGET_PARSER_REV); 3764 ); 3765 dacs = hdac_audio_build_tree_strategy(devinfo); 3766 if (dacs == 0) { 3767 HDA_BOOTVERBOSE( 3768 device_printf(devinfo->codec->sc->dev, 3769 "HDA_DEBUG: HWiP: 0 DAC path found! " 3770 "Retrying parser " 3771 "using HDA_PARSE_DIRECT strategy.\n"); 3772 ); 3773 strategy = HDA_PARSE_DIRECT; 3774 devinfo->function.audio.parsing_strategy = strategy; 3775 dacs = hdac_audio_build_tree_strategy(devinfo); 3776 } 3777 3778 HDA_BOOTVERBOSE( 3779 device_printf(devinfo->codec->sc->dev, 3780 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 3781 "strategy.\n", 3782 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 3783 ); 3784 3785 /* Construct ADC path */ 3786 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3787 w = hdac_widget_get(devinfo, i); 3788 if (w == NULL || w->enable == 0) 3789 continue; 3790 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3791 continue; 3792 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 3793 } 3794 3795 /* Output mixers */ 3796 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3797 w = hdac_widget_get(devinfo, i); 3798 if (w == NULL || w->enable == 0) 3799 continue; 3800 if ((strategy == HDA_PARSE_MIXER && 3801 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3802 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3803 && (w->pflags & HDA_DAC_PATH)) || 3804 (strategy == HDA_PARSE_DIRECT && (w->pflags & 3805 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 3806 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 3807 w->nid, devinfo->startnode - 1, 0, 0); 3808 } else if (w->type == 3809 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3810 j = 0; 3811 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 3812 NULL) { 3813 if (ctl->enable == 0 || ctl->widget == NULL) 3814 continue; 3815 if (ctl->widget->nid != w->nid) 3816 continue; 3817 ctl->ossmask |= SOUND_MASK_VOLUME; 3818 ctl->ossmask |= SOUND_MASK_SPEAKER; 3819 ctl->ossdev = SOUND_MIXER_SPEAKER; 3820 w->ctlflags |= SOUND_MASK_VOLUME; 3821 w->ctlflags |= SOUND_MASK_SPEAKER; 3822 } 3823 } 3824 } 3825 3826 /* Input mixers (rec) */ 3827 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3828 w = hdac_widget_get(devinfo, i); 3829 if (w == NULL || w->enable == 0) 3830 continue; 3831 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3832 w->pflags & HDA_ADC_PATH)) 3833 continue; 3834 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 3835 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 3836 } 3837} 3838 3839#define HDA_COMMIT_CONN (1 << 0) 3840#define HDA_COMMIT_CTRL (1 << 1) 3841#define HDA_COMMIT_EAPD (1 << 2) 3842#define HDA_COMMIT_GPIO (1 << 3) 3843#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 3844 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 3845 3846static void 3847hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 3848{ 3849 struct hdac_softc *sc = devinfo->codec->sc; 3850 struct hdac_widget *w; 3851 nid_t cad, nid; 3852 int i, gpioval; 3853 3854 if (!(cfl & HDA_COMMIT_ALL)) 3855 return; 3856 3857 cad = devinfo->codec->cad; 3858 3859 if (cfl & HDA_COMMIT_GPIO) { 3860 nid = devinfo->nid; 3861 for (i = 0; i < HDA_GPIO_MAX; i++) { 3862 if (!(devinfo->function.audio.quirks & (1 << i))) 3863 continue; 3864 gpioval = (1 << i) - 1; 3865 hdac_command(sc, 3866 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, gpioval), 3867 cad); 3868 hdac_command(sc, 3869 HDA_CMD_SET_GPIO_DIRECTION(cad, nid, gpioval), 3870 cad); 3871 hdac_command(sc, 3872 HDA_CMD_SET_GPIO_DATA(cad, nid, gpioval), 3873 cad); 3874 } 3875 } 3876 3877 for (i = 0; i < devinfo->nodecnt; i++) { 3878 w = &devinfo->widget[i]; 3879 if (w == NULL || w->enable == 0) 3880 continue; 3881 if (cfl & HDA_COMMIT_CONN) { 3882 if (w->selconn == -1) 3883 w->selconn = 0; 3884 if (w->nconns > 0) 3885 hdac_widget_connection_select(w, w->selconn); 3886 } 3887 if ((cfl & HDA_COMMIT_CTRL) && 3888 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 3889 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 3890 (HDA_DAC_PATH | HDA_ADC_PATH)) 3891 device_printf(sc->dev, "WARNING: node %d " 3892 "participate both for DAC/ADC!\n", w->nid); 3893 if (w->pflags & HDA_DAC_PATH) { 3894 w->wclass.pin.ctrl &= 3895 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 3896 if ((w->wclass.pin.config & 3897 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 3898 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 3899 w->wclass.pin.ctrl &= 3900 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 3901 } else if (w->pflags & HDA_ADC_PATH) { 3902 w->wclass.pin.ctrl &= 3903 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3904 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 3905 } else 3906 w->wclass.pin.ctrl &= ~( 3907 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 3908 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3909 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 3910 hdac_command(sc, 3911 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 3912 w->wclass.pin.ctrl), cad); 3913 } 3914 if ((cfl & HDA_COMMIT_EAPD) && 3915 w->param.eapdbtl != HDAC_INVALID) 3916 hdac_command(sc, 3917 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 3918 w->param.eapdbtl), cad); 3919 3920 DELAY(1000); 3921 } 3922} 3923 3924static void 3925hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 3926{ 3927 struct hdac_softc *sc = devinfo->codec->sc; 3928 struct hdac_audio_ctl *ctl; 3929 int i; 3930 3931 devinfo->function.audio.mvol = 100 | (100 << 8); 3932 i = 0; 3933 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3934 if (ctl->enable == 0 || ctl->widget == NULL) { 3935 HDA_BOOTVERBOSE( 3936 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3937 i, (ctl->widget != NULL) ? 3938 ctl->widget->nid : -1); 3939 if (ctl->childwidget != NULL) 3940 printf(" childnid=%d", 3941 ctl->childwidget->nid); 3942 if (ctl->widget == NULL) 3943 printf(" NULL WIDGET!"); 3944 printf(" DISABLED\n"); 3945 ); 3946 continue; 3947 } 3948 HDA_BOOTVERBOSE( 3949 if (ctl->ossmask == 0) { 3950 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3951 i, ctl->widget->nid); 3952 if (ctl->childwidget != NULL) 3953 printf(" childnid=%d", 3954 ctl->childwidget->nid); 3955 printf(" Bind to NONE\n"); 3956 } 3957 ); 3958 if (ctl->step > 0) { 3959 ctl->ossval = (ctl->left * 100) / ctl->step; 3960 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 3961 } else 3962 ctl->ossval = 0; 3963 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 3964 ctl->left, ctl->right); 3965 } 3966} 3967 3968static int 3969hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 3970{ 3971 struct hdac_chan *ch; 3972 struct hdac_widget *w; 3973 uint32_t cap, fmtcap, pcmcap, path; 3974 int i, type, ret, max; 3975 3976 if (dir == PCMDIR_PLAY) { 3977 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 3978 ch = &devinfo->codec->sc->play; 3979 path = HDA_DAC_PATH; 3980 } else { 3981 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 3982 ch = &devinfo->codec->sc->rec; 3983 path = HDA_ADC_PATH; 3984 } 3985 3986 ch->caps = hdac_caps; 3987 ch->caps.fmtlist = ch->fmtlist; 3988 ch->bit16 = 1; 3989 ch->bit32 = 0; 3990 ch->pcmrates[0] = 48000; 3991 ch->pcmrates[1] = 0; 3992 3993 ret = 0; 3994 fmtcap = devinfo->function.audio.supp_stream_formats; 3995 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 3996 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 3997 3998 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 3999 w = hdac_widget_get(devinfo, i); 4000 if (w == NULL || w->enable == 0 || w->type != type || 4001 !(w->pflags & path)) 4002 continue; 4003 cap = w->param.widget_cap; 4004 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4005 continue;*/ 4006 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4007 continue; 4008 cap = w->param.supp_stream_formats; 4009 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4010 } 4011 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4012 }*/ 4013 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4014 continue; 4015 ch->io[ret++] = i; 4016 fmtcap &= w->param.supp_stream_formats; 4017 pcmcap &= w->param.supp_pcm_size_rate; 4018 } 4019 ch->io[ret] = -1; 4020 4021 ch->supp_stream_formats = fmtcap; 4022 ch->supp_pcm_size_rate = pcmcap; 4023 4024 /* 4025 * 8bit = 0 4026 * 16bit = 1 4027 * 20bit = 2 4028 * 24bit = 3 4029 * 32bit = 4 4030 */ 4031 if (ret > 0) { 4032 cap = pcmcap; 4033 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4034 ch->bit16 = 1; 4035 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4036 ch->bit16 = 0; 4037 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4038 ch->bit32 = 4; 4039 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4040 ch->bit32 = 3; 4041 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4042 ch->bit32 = 2; 4043 i = 0; 4044 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4045 ch->fmtlist[i++] = AFMT_S16_LE; 4046 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4047 if (ch->bit32 > 0) { 4048 if (!(devinfo->function.audio.quirks & 4049 HDA_QUIRK_FORCESTEREO)) 4050 ch->fmtlist[i++] = AFMT_S32_LE; 4051 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4052 } 4053 ch->fmtlist[i] = 0; 4054 i = 0; 4055 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4056 ch->pcmrates[i++] = 8000; 4057 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4058 ch->pcmrates[i++] = 11025; 4059 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4060 ch->pcmrates[i++] = 16000; 4061 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4062 ch->pcmrates[i++] = 22050; 4063 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4064 ch->pcmrates[i++] = 32000; 4065 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4066 ch->pcmrates[i++] = 44100; 4067 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4068 ch->pcmrates[i++] = 48000; 4069 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4070 ch->pcmrates[i++] = 88200; 4071 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4072 ch->pcmrates[i++] = 96000; 4073 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4074 ch->pcmrates[i++] = 176400; 4075 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4076 ch->pcmrates[i++] = 192000; 4077 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4078 ch->pcmrates[i] = 0; 4079 if (i > 0) { 4080 ch->caps.minspeed = ch->pcmrates[0]; 4081 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4082 } 4083 } 4084 4085 return (ret); 4086} 4087 4088static void 4089hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4090{ 4091 struct hdac_audio_ctl *ctl; 4092 struct hdac_softc *sc = devinfo->codec->sc; 4093 int i; 4094 uint32_t fl = 0; 4095 4096 4097 if (flag == 0) { 4098 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4099 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4100 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4101 } 4102 4103 i = 0; 4104 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4105 if (ctl->enable == 0 || ctl->widget == NULL || 4106 ctl->widget->enable == 0) 4107 continue; 4108 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4109 (flag != 0 && (ctl->ossmask & flag))) { 4110 if (banner != NULL) { 4111 device_printf(sc->dev, "\n"); 4112 device_printf(sc->dev, "%s\n", banner); 4113 } 4114 goto hdac_ctl_dump_it_all; 4115 } 4116 } 4117 4118 return; 4119 4120hdac_ctl_dump_it_all: 4121 i = 0; 4122 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4123 if (ctl->enable == 0 || ctl->widget == NULL || 4124 ctl->widget->enable == 0) 4125 continue; 4126 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4127 (flag != 0 && (ctl->ossmask & flag)))) 4128 continue; 4129 if (flag == 0) { 4130 device_printf(sc->dev, "\n"); 4131 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4132 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4133 } 4134 device_printf(sc->dev, " |\n"); 4135 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4136 ctl->widget->nid, ctl->index); 4137 if (ctl->childwidget != NULL) 4138 printf("(nid: %2d) ", ctl->childwidget->nid); 4139 else 4140 printf(" "); 4141 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4142 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4143 ctl->ossmask); 4144 } 4145} 4146 4147static void 4148hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4149{ 4150 uint32_t cap; 4151 4152 cap = fcap; 4153 if (cap != 0) { 4154 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4155 device_printf(sc->dev, " Format:"); 4156 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4157 printf(" AC3"); 4158 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4159 printf(" FLOAT32"); 4160 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4161 printf(" PCM"); 4162 printf("\n"); 4163 } 4164 cap = pcmcap; 4165 if (cap != 0) { 4166 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4167 device_printf(sc->dev, " PCM size:"); 4168 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4169 printf(" 8"); 4170 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4171 printf(" 16"); 4172 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4173 printf(" 20"); 4174 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4175 printf(" 24"); 4176 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4177 printf(" 32"); 4178 printf("\n"); 4179 device_printf(sc->dev, " PCM rate:"); 4180 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4181 printf(" 8"); 4182 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4183 printf(" 11"); 4184 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4185 printf(" 16"); 4186 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4187 printf(" 22"); 4188 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4189 printf(" 32"); 4190 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4191 printf(" 44"); 4192 printf(" 48"); 4193 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4194 printf(" 88"); 4195 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4196 printf(" 96"); 4197 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4198 printf(" 176"); 4199 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4200 printf(" 192"); 4201 printf("\n"); 4202 } 4203} 4204 4205static void 4206hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4207{ 4208 uint32_t pincap, wcap; 4209 4210 pincap = w->wclass.pin.cap; 4211 wcap = w->param.widget_cap; 4212 4213 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4214 device_printf(sc->dev, " "); 4215 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4216 printf(" ISC"); 4217 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4218 printf(" TRQD"); 4219 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4220 printf(" PDC"); 4221 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4222 printf(" HP"); 4223 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4224 printf(" OUT"); 4225 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4226 printf(" IN"); 4227 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4228 printf(" BAL"); 4229 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4230 printf(" EAPD"); 4231 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4232 printf(" : UNSOL"); 4233 printf("\n"); 4234 device_printf(sc->dev, " Pin config: 0x%08x\n", 4235 w->wclass.pin.config); 4236 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4237 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4238 printf(" HP"); 4239 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4240 printf(" IN"); 4241 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4242 printf(" OUT"); 4243 printf("\n"); 4244} 4245 4246static void 4247hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4248{ 4249 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4250 device_printf(sc->dev, " " 4251 "mute=%d step=%d size=%d offset=%d\n", 4252 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4253 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4254 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4255 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4256} 4257 4258static void 4259hdac_dump_nodes(struct hdac_devinfo *devinfo) 4260{ 4261 struct hdac_softc *sc = devinfo->codec->sc; 4262 struct hdac_widget *w, *cw; 4263 int i, j; 4264 4265 device_printf(sc->dev, "\n"); 4266 device_printf(sc->dev, "Default Parameter\n"); 4267 device_printf(sc->dev, "-----------------\n"); 4268 hdac_dump_audio_formats(sc, 4269 devinfo->function.audio.supp_stream_formats, 4270 devinfo->function.audio.supp_pcm_size_rate); 4271 device_printf(sc->dev, " IN amp: 0x%08x\n", 4272 devinfo->function.audio.inamp_cap); 4273 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4274 devinfo->function.audio.outamp_cap); 4275 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4276 w = hdac_widget_get(devinfo, i); 4277 if (w == NULL) { 4278 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4279 continue; 4280 } 4281 device_printf(sc->dev, "\n"); 4282 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4283 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4284 "DIGITAL" : "ANALOG", 4285 (w->enable == 0) ? " [DISABLED]" : ""); 4286 device_printf(sc->dev, " name: %s\n", w->name); 4287 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4288 w->param.widget_cap); 4289 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4290 w->pflags); 4291 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4292 w->ctlflags); 4293 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4294 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4295 hdac_dump_audio_formats(sc, 4296 w->param.supp_stream_formats, 4297 w->param.supp_pcm_size_rate); 4298 } else if (w->type == 4299 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4300 hdac_dump_pin(sc, w); 4301 if (w->param.eapdbtl != HDAC_INVALID) 4302 device_printf(sc->dev, " EAPD: 0x%08x\n", 4303 w->param.eapdbtl); 4304 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4305 w->param.outamp_cap != 0) 4306 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4307 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4308 w->param.inamp_cap != 0) 4309 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4310 device_printf(sc->dev, " connections: %d\n", w->nconns); 4311 for (j = 0; j < w->nconns; j++) { 4312 cw = hdac_widget_get(devinfo, w->conns[j]); 4313 device_printf(sc->dev, " |\n"); 4314 device_printf(sc->dev, " + <- nid=%d [%s]", 4315 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4316 if (cw == NULL) 4317 printf(" [UNKNOWN]"); 4318 else if (cw->enable == 0) 4319 printf(" [DISABLED]"); 4320 if (w->nconns > 1 && w->selconn == j && w->type != 4321 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4322 printf(" (selected)"); 4323 printf("\n"); 4324 } 4325 } 4326 4327} 4328 4329static int 4330hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4331{ 4332 struct hdac_widget *w, *cw; 4333 struct hdac_softc *sc = devinfo->codec->sc; 4334 int i; 4335 4336 if (depth > HDA_PARSE_MAXDEPTH) 4337 return (0); 4338 4339 w = hdac_widget_get(devinfo, nid); 4340 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4341 return (0); 4342 4343 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4344 device_printf(sc->dev, "\n"); 4345 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4346 device_printf(sc->dev, " ^\n"); 4347 device_printf(sc->dev, " |\n"); 4348 device_printf(sc->dev, " +-----<------+\n"); 4349 } else { 4350 device_printf(sc->dev, " ^\n"); 4351 device_printf(sc->dev, " |\n"); 4352 device_printf(sc->dev, " "); 4353 printf(" nid=%d [%s]\n", w->nid, w->name); 4354 } 4355 4356 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4357 return (1); 4358 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4359 for (i = 0; i < w->nconns; i++) { 4360 cw = hdac_widget_get(devinfo, w->conns[i]); 4361 if (cw == NULL || cw->enable == 0 || cw->type == 4362 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4363 continue; 4364 if (hdac_dump_dac_internal(devinfo, cw->nid, 4365 depth + 1) != 0) 4366 return (1); 4367 } 4368 } else if ((w->type == 4369 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4370 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4371 w->selconn > -1 && w->selconn < w->nconns) { 4372 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4373 depth + 1) != 0) 4374 return (1); 4375 } 4376 4377 return (0); 4378} 4379 4380static void 4381hdac_dump_dac(struct hdac_devinfo *devinfo) 4382{ 4383 struct hdac_widget *w; 4384 struct hdac_softc *sc = devinfo->codec->sc; 4385 int i, printed = 0; 4386 4387 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4388 w = hdac_widget_get(devinfo, i); 4389 if (w == NULL || w->enable == 0) 4390 continue; 4391 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4392 !(w->pflags & HDA_DAC_PATH)) 4393 continue; 4394 if (printed == 0) { 4395 printed = 1; 4396 device_printf(sc->dev, "\n"); 4397 device_printf(sc->dev, "Playback path:\n"); 4398 } 4399 hdac_dump_dac_internal(devinfo, w->nid, 0); 4400 } 4401} 4402 4403static void 4404hdac_dump_adc(struct hdac_devinfo *devinfo) 4405{ 4406 struct hdac_widget *w, *cw; 4407 struct hdac_softc *sc = devinfo->codec->sc; 4408 int i, j; 4409 int printed = 0; 4410 char ossdevs[256]; 4411 4412 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4413 w = hdac_widget_get(devinfo, i); 4414 if (w == NULL || w->enable == 0) 4415 continue; 4416 if (!(w->pflags & HDA_ADC_RECSEL)) 4417 continue; 4418 if (printed == 0) { 4419 printed = 1; 4420 device_printf(sc->dev, "\n"); 4421 device_printf(sc->dev, "Recording sources:\n"); 4422 } 4423 device_printf(sc->dev, "\n"); 4424 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4425 for (j = 0; j < w->nconns; j++) { 4426 cw = hdac_widget_get(devinfo, w->conns[j]); 4427 if (cw == NULL || cw->enable == 0) 4428 continue; 4429 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4430 ossdevs, sizeof(ossdevs)); 4431 device_printf(sc->dev, " |\n"); 4432 device_printf(sc->dev, " + <- nid=%d [%s]", 4433 cw->nid, cw->name); 4434 if (strlen(ossdevs) > 0) { 4435 printf(" [recsrc: %s]", ossdevs); 4436 } 4437 printf("\n"); 4438 } 4439 } 4440} 4441 4442static void 4443hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4444{ 4445 nid_t *nids; 4446 4447 if (pcnt > 0) { 4448 device_printf(sc->dev, "\n"); 4449 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4450 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4451 sc->play.supp_pcm_size_rate); 4452 device_printf(sc->dev, " DAC:"); 4453 for (nids = sc->play.io; *nids != -1; nids++) 4454 printf(" %d", *nids); 4455 printf("\n"); 4456 } 4457 4458 if (rcnt > 0) { 4459 device_printf(sc->dev, "\n"); 4460 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4461 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4462 sc->rec.supp_pcm_size_rate); 4463 device_printf(sc->dev, " ADC:"); 4464 for (nids = sc->rec.io; *nids != -1; nids++) 4465 printf(" %d", *nids); 4466 printf("\n"); 4467 } 4468} 4469 4470static void 4471hdac_release_resources(struct hdac_softc *sc) 4472{ 4473 struct hdac_devinfo *devinfo = NULL; 4474 device_t *devlist = NULL; 4475 int i, devcount; 4476 4477 if (sc == NULL) 4478 return; 4479 4480 hdac_lock(sc); 4481 hdac_reset(sc); 4482 hdac_unlock(sc); 4483 snd_mtxfree(sc->lock); 4484 4485 device_get_children(sc->dev, &devlist, &devcount); 4486 for (i = 0; devlist != NULL && i < devcount; i++) { 4487 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4488 if (devinfo == NULL) 4489 continue; 4490 if (devinfo->widget != NULL) 4491 free(devinfo->widget, M_HDAC); 4492 if (devinfo->node_type == 4493 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4494 devinfo->function.audio.ctl != NULL) 4495 free(devinfo->function.audio.ctl, M_HDAC); 4496 free(devinfo, M_HDAC); 4497 device_delete_child(sc->dev, devlist[i]); 4498 } 4499 if (devlist != NULL) 4500 free(devlist, M_TEMP); 4501 4502 for (i = 0; i < HDAC_CODEC_MAX; i++) { 4503 if (sc->codecs[i] != NULL) 4504 free(sc->codecs[i], M_HDAC); 4505 sc->codecs[i] = NULL; 4506 } 4507 4508 hdac_dma_free(&sc->rirb_dma); 4509 hdac_dma_free(&sc->corb_dma); 4510 if (sc->play.blkcnt > 0) 4511 hdac_dma_free(&sc->play.bdl_dma); 4512 if (sc->rec.blkcnt > 0) 4513 hdac_dma_free(&sc->rec.bdl_dma); 4514 hdac_irq_free(sc); 4515 hdac_mem_free(sc); 4516 free(sc, M_DEVBUF); 4517 4518} 4519 4520/* This function surely going to make its way into upper level someday. */ 4521static void 4522hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 4523{ 4524 const char *res = NULL; 4525 int i = 0, j, k, len, inv; 4526 4527 if (on != NULL) 4528 *on = 0; 4529 if (off != NULL) 4530 *off = 0; 4531 if (sc == NULL) 4532 return; 4533 if (resource_string_value(device_get_name(sc->dev), 4534 device_get_unit(sc->dev), "config", &res) != 0) 4535 return; 4536 if (!(res != NULL && strlen(res) > 0)) 4537 return; 4538 HDA_BOOTVERBOSE( 4539 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 4540 ); 4541 for (;;) { 4542 while (res[i] != '\0' && 4543 (res[i] == ',' || isspace(res[i]) != 0)) 4544 i++; 4545 if (res[i] == '\0') { 4546 HDA_BOOTVERBOSE( 4547 printf("\n"); 4548 ); 4549 return; 4550 } 4551 j = i; 4552 while (res[j] != '\0' && 4553 !(res[j] == ',' || isspace(res[j]) != 0)) 4554 j++; 4555 len = j - i; 4556 if (len > 2 && strncmp(res + i, "no", 2) == 0) 4557 inv = 2; 4558 else 4559 inv = 0; 4560 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 4561 if (strncmp(res + i + inv, 4562 hdac_quirks_tab[k].key, len - inv) != 0) 4563 continue; 4564 if (len - inv != strlen(hdac_quirks_tab[k].key)) 4565 break; 4566 HDA_BOOTVERBOSE( 4567 printf(" %s%s", (inv != 0) ? "no" : "", 4568 hdac_quirks_tab[k].key); 4569 ); 4570 if (inv == 0 && on != NULL) 4571 *on |= hdac_quirks_tab[k].value; 4572 else if (inv != 0 && off != NULL) 4573 *off |= hdac_quirks_tab[k].value; 4574 break; 4575 } 4576 i = j; 4577 } 4578} 4579 4580static void 4581hdac_attach2(void *arg) 4582{ 4583 struct hdac_softc *sc; 4584 struct hdac_widget *w; 4585 struct hdac_audio_ctl *ctl; 4586 uint32_t quirks_on, quirks_off; 4587 int pcnt, rcnt; 4588 int i; 4589 char status[SND_STATUSLEN]; 4590 device_t *devlist = NULL; 4591 int devcount; 4592 struct hdac_devinfo *devinfo = NULL; 4593 4594 sc = (struct hdac_softc *)arg; 4595 4596 hdac_config_fetch(sc, &quirks_on, &quirks_off); 4597 4598 HDA_BOOTVERBOSE( 4599 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 4600 quirks_on, quirks_off); 4601 ); 4602 4603 hdac_lock(sc); 4604 4605 /* Remove ourselves from the config hooks */ 4606 if (sc->intrhook.ich_func != NULL) { 4607 config_intrhook_disestablish(&sc->intrhook); 4608 sc->intrhook.ich_func = NULL; 4609 } 4610 4611 /* Start the corb and rirb engines */ 4612 HDA_BOOTVERBOSE( 4613 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4614 ); 4615 hdac_corb_start(sc); 4616 HDA_BOOTVERBOSE( 4617 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4618 ); 4619 hdac_rirb_start(sc); 4620 4621 HDA_BOOTVERBOSE( 4622 device_printf(sc->dev, 4623 "HDA_DEBUG: Enabling controller interrupt...\n"); 4624 ); 4625 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4626 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 4627 HDAC_GCTL_UNSOL); 4628 4629 DELAY(1000); 4630 4631 HDA_BOOTVERBOSE( 4632 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4633 ); 4634 hdac_scan_codecs(sc); 4635 4636 device_get_children(sc->dev, &devlist, &devcount); 4637 for (i = 0; devlist != NULL && i < devcount; i++) { 4638 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4639 if (devinfo != NULL && devinfo->node_type == 4640 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4641 break; 4642 } else 4643 devinfo = NULL; 4644 } 4645 if (devlist != NULL) 4646 free(devlist, M_TEMP); 4647 4648 if (devinfo == NULL) { 4649 hdac_unlock(sc); 4650 device_printf(sc->dev, "Audio Function Group not found!\n"); 4651 hdac_release_resources(sc); 4652 return; 4653 } 4654 4655 HDA_BOOTVERBOSE( 4656 device_printf(sc->dev, 4657 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4658 devinfo->nid, devinfo->codec->cad); 4659 ); 4660 hdac_audio_parse(devinfo); 4661 HDA_BOOTVERBOSE( 4662 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4663 ); 4664 hdac_audio_ctl_parse(devinfo); 4665 HDA_BOOTVERBOSE( 4666 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4667 ); 4668 hdac_vendor_patch_parse(devinfo); 4669 if (quirks_on != 0) 4670 devinfo->function.audio.quirks |= quirks_on; 4671 if (quirks_off != 0) 4672 devinfo->function.audio.quirks &= ~quirks_off; 4673 4674 /* XXX Disable all DIGITAL path. */ 4675 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4676 w = hdac_widget_get(devinfo, i); 4677 if (w == NULL) 4678 continue; 4679 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4680 w->enable = 0; 4681 continue; 4682 } 4683 /* XXX Disable useless pin ? */ 4684 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4685 (w->wclass.pin.config & 4686 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4687 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4688 w->enable = 0; 4689 } 4690 i = 0; 4691 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4692 if (ctl->widget == NULL) 4693 continue; 4694 w = ctl->widget; 4695 if (w->enable == 0) 4696 ctl->enable = 0; 4697 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4698 ctl->enable = 0; 4699 w = ctl->childwidget; 4700 if (w == NULL) 4701 continue; 4702 if (w->enable == 0 || 4703 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4704 ctl->enable = 0; 4705 } 4706 4707 HDA_BOOTVERBOSE( 4708 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 4709 ); 4710 hdac_audio_build_tree(devinfo); 4711 4712 HDA_BOOTVERBOSE( 4713 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 4714 ); 4715 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 4716 HDA_BOOTVERBOSE( 4717 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 4718 ); 4719 hdac_audio_ctl_commit(devinfo); 4720 4721 HDA_BOOTVERBOSE( 4722 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 4723 ); 4724 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 4725 HDA_BOOTVERBOSE( 4726 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 4727 ); 4728 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 4729 4730 hdac_unlock(sc); 4731 HDA_BOOTVERBOSE( 4732 device_printf(sc->dev, 4733 "HDA_DEBUG: OSS mixer initialization...\n"); 4734 ); 4735 4736 /* 4737 * There is no point of return after this. If the driver failed, 4738 * so be it. Let the detach procedure do all the cleanup. 4739 */ 4740 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 4741 device_printf(sc->dev, "Can't register mixer\n"); 4742 4743 if (pcnt > 0) 4744 pcnt = 1; 4745 if (rcnt > 0) 4746 rcnt = 1; 4747 4748 HDA_BOOTVERBOSE( 4749 device_printf(sc->dev, 4750 "HDA_DEBUG: Registering PCM channels...\n"); 4751 ); 4752 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 4753 device_printf(sc->dev, "Can't register PCM\n"); 4754 4755 sc->registered++; 4756 4757 for (i = 0; i < pcnt; i++) 4758 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 4759 for (i = 0; i < rcnt; i++) 4760 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 4761 4762 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 4763 rman_get_start(sc->mem.mem_res), 4764 rman_get_start(sc->irq.irq_res), 4765 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 4766 pcm_setstatus(sc->dev, status); 4767 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 4768 HDA_BOOTVERBOSE( 4769 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 4770 hdac_codec_id(devinfo)); 4771 ); 4772 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 4773 4774 HDA_BOOTVERBOSE( 4775 if (devinfo->function.audio.quirks != 0) { 4776 device_printf(sc->dev, "\n"); 4777 device_printf(sc->dev, "HDA config/quirks:"); 4778 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 4779 if (devinfo->function.audio.quirks & 4780 hdac_quirks_tab[i].value) 4781 printf(" %s", hdac_quirks_tab[i].key); 4782 } 4783 printf("\n"); 4784 } 4785 device_printf(sc->dev, "\n"); 4786 device_printf(sc->dev, "+-------------------+\n"); 4787 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 4788 device_printf(sc->dev, "+-------------------+\n"); 4789 hdac_dump_nodes(devinfo); 4790 device_printf(sc->dev, "\n"); 4791 device_printf(sc->dev, "+------------------------+\n"); 4792 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 4793 device_printf(sc->dev, "+------------------------+\n"); 4794 device_printf(sc->dev, "\n"); 4795 i = 0; 4796 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4797 device_printf(sc->dev, "%3d: nid=%d", i, 4798 (ctl->widget != NULL) ? ctl->widget->nid : -1); 4799 if (ctl->childwidget != NULL) 4800 printf(" cnid=%d", ctl->childwidget->nid); 4801 printf(" dir=0x%x index=%d " 4802 "ossmask=0x%08x ossdev=%d%s\n", 4803 ctl->dir, ctl->index, 4804 ctl->ossmask, ctl->ossdev, 4805 (ctl->enable == 0) ? " [DISABLED]" : ""); 4806 } 4807 device_printf(sc->dev, "\n"); 4808 device_printf(sc->dev, "+-----------------------------------+\n"); 4809 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 4810 device_printf(sc->dev, "+-----------------------------------+\n"); 4811 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 4812 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 4813 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 4814 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 4815 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 4816 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 4817 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 4818 hdac_dump_ctls(devinfo, NULL, 0); 4819 hdac_dump_dac(devinfo); 4820 hdac_dump_adc(devinfo); 4821 device_printf(sc->dev, "\n"); 4822 device_printf(sc->dev, "+--------------------------------------+\n"); 4823 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 4824 device_printf(sc->dev, "+--------------------------------------+\n"); 4825 hdac_dump_pcmchannels(sc, pcnt, rcnt); 4826 ); 4827} 4828 4829/**************************************************************************** 4830 * int hdac_detach(device_t) 4831 * 4832 * Detach and free up resources utilized by the hdac device. 4833 ****************************************************************************/ 4834static int 4835hdac_detach(device_t dev) 4836{ 4837 struct hdac_softc *sc = NULL; 4838 struct hdac_devinfo *devinfo = NULL; 4839 int err; 4840 4841 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 4842 if (devinfo != NULL && devinfo->codec != NULL) 4843 sc = devinfo->codec->sc; 4844 if (sc == NULL) 4845 return (0); 4846 4847 if (sc->registered > 0) { 4848 err = pcm_unregister(dev); 4849 if (err != 0) 4850 return (err); 4851 } 4852 4853 hdac_release_resources(sc); 4854 4855 return (0); 4856} 4857 4858static device_method_t hdac_methods[] = { 4859 /* device interface */ 4860 DEVMETHOD(device_probe, hdac_probe), 4861 DEVMETHOD(device_attach, hdac_attach), 4862 DEVMETHOD(device_detach, hdac_detach), 4863 { 0, 0 } 4864}; 4865 4866static driver_t hdac_driver = { 4867 "pcm", 4868 hdac_methods, 4869 PCM_SOFTC_SIZE, 4870}; 4871 4872DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 4873MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 4874MODULE_VERSION(snd_hda, 1); 4875