hdac.c revision 162965
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especiall UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <dev/sound/pci/hda/hdac_private.h> 75#include <dev/sound/pci/hda/hdac_reg.h> 76#include <dev/sound/pci/hda/hda_reg.h> 77#include <dev/sound/pci/hda/hdac.h> 78 79#include "mixer_if.h" 80 81#define HDA_DRV_TEST_REV "20061003_0029" 82#define HDA_WIDGET_PARSER_REV 1 83 84SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 162965 2006-10-02 16:30:04Z ariff $"); 85 86#undef HDA_DEBUG_ENABLED 87#define HDA_DEBUG_ENABLED 1 88 89#ifdef HDA_DEBUG_ENABLED 90#define HDA_DEBUG_MSG(stmt) do { \ 91 if (bootverbose) { \ 92 stmt \ 93 } \ 94} while(0) 95#else 96#define HDA_DEBUG_MSG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE_MSG(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 113#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 114#define HDA_MATCH_ALL 0xffffffff 115#define HDAC_INVALID 0xffffffff 116 117#define HDA_MODEL_CONSTRUCT(vendor, model) \ 118 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 119 120/* Controller models */ 121 122/* Intel */ 123#define INTEL_VENDORID 0x8086 124#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 125#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 126#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 127 128/* Nvidia */ 129#define NVIDIA_VENDORID 0x10de 130#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 131#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 132#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 133 134/* ATI */ 135#define ATI_VENDORID 0x1002 136#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 137#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 138 139/* OEM/subvendors */ 140 141/* HP/Compaq */ 142#define HP_VENDORID 0x103c 143#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 144#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 145#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 146#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 147 148/* Dell */ 149#define DELL_VENDORID 0x1028 150#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 151#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 152#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 153 154/* Clevo */ 155#define CLEVO_VENDORID 0x1558 156#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 157#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 158 159/* Acer */ 160#define ACER_VENDORID 0x1025 161#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 162 163/* Asus */ 164#define ASUS_VENDORID 0x1043 165#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 166#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 167 168 169/* Misc constants.. */ 170#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 171#define HDA_AMP_MUTE_NONE (0) 172#define HDA_AMP_MUTE_LEFT (1 << 0) 173#define HDA_AMP_MUTE_RIGHT (1 << 1) 174#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 175 176#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 177#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 178 179#define HDA_DAC_PATH (1 << 0) 180#define HDA_ADC_PATH (1 << 1) 181#define HDA_ADC_RECSEL (1 << 2) 182 183#define HDA_CTL_OUT 0x1 184#define HDA_CTL_IN 0x2 185#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 186 187#define HDA_QUIRK_GPIO1 (1 << 0) 188#define HDA_QUIRK_GPIO2 (1 << 1) 189#define HDA_QUIRK_SOFTPCMVOL (1 << 2) 190#define HDA_QUIRK_FIXEDRATE (1 << 3) 191#define HDA_QUIRK_FORCESTEREO (1 << 4) 192 193#define HDA_BDL_MIN 2 194#define HDA_BDL_MAX 256 195#define HDA_BDL_DEFAULT HDA_BDL_MIN 196 197#define HDA_BUFSZ_MIN 4096 198#define HDA_BUFSZ_MAX 65536 199#define HDA_BUFSZ_DEFAULT 16384 200 201#define HDA_PARSE_MAXDEPTH 10 202 203#define HDAC_UNSOLTAG_EVENT_HP 0x00 204 205static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 206 207enum { 208 HDA_PARSE_MIXER, 209 HDA_PARSE_DIRECT 210}; 211 212/* Default */ 213static uint32_t hdac_fmt[] = { 214 AFMT_STEREO | AFMT_S16_LE, 215 0 216}; 217 218static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 219 220static const struct { 221 uint32_t model; 222 char *desc; 223} hdac_devices[] = { 224 { HDA_INTEL_82801F, "Intel 82801F" }, 225 { HDA_INTEL_82801G, "Intel 82801G" }, 226 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 227 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 228 { HDA_ATI_SB450, "ATI SB450" }, 229 /* Unknown */ 230 { HDA_INTEL_ALL, "Intel (Unknown)" }, 231 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 232 { HDA_ATI_ALL, "ATI (Unknown)" }, 233}; 234#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 235 236static const struct { 237 uint32_t rate; 238 int valid; 239 uint16_t base; 240 uint16_t mul; 241 uint16_t div; 242} hda_rate_tab[] = { 243 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 244 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 245 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 246 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 247 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 248 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 249 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 250 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 251 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 252 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 253 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 254 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 255 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 256 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 257 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 258 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 259 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 260 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 261 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 262 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 263 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 264 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 265 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 266 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 267 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 268 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 269 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 270 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 271 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 272 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 273 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 274 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 275 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 276 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 277 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 278}; 279#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 280 281/* All codecs you can eat... */ 282#define HDA_CODEC_CONSTRUCT(vendor, id) \ 283 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 284 285/* Realtek */ 286#define REALTEK_VENDORID 0x10ec 287#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 288#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 289#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 290#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 291#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 292 293/* Analog Device */ 294#define ANALOGDEVICE_VENDORID 0x11d4 295#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 296#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 297#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 298#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 299 300/* CMedia */ 301#define CMEDIA_VENDORID 0x434d 302#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 303#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 304 305/* Sigmatel */ 306#define SIGMATEL_VENDORID 0x8384 307#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 308#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 309#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 310#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 311#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 312 313/* 314 * Conexant 315 * 316 * Ok, the truth is, I don't have any idea at all whether 317 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 318 * place that tell me it is "Venice" is from its Windows driver INF. 319 */ 320#define CONEXANT_VENDORID 0x14f1 321#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 322#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 323 324 325/* Codecs */ 326static const struct { 327 uint32_t id; 328 char *name; 329} hdac_codecs[] = { 330 { HDA_CODEC_ALC260, "Realtek ALC260" }, 331 { HDA_CODEC_ALC861, "Realtek ALC861" }, 332 { HDA_CODEC_ALC880, "Realtek ALC880" }, 333 { HDA_CODEC_ALC882, "Realtek ALC882" }, 334 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 335 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 336 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 337 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 338 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 339 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 340 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 341 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 342 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 343 /* Unknown codec */ 344 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 345 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 346 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 347 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 348 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 349}; 350#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 351 352enum { 353 HDAC_HP_SWITCH_CTL, 354 HDAC_HP_SWITCH_CTRL 355}; 356 357static const struct { 358 uint32_t model; 359 uint32_t id; 360 int type; 361 nid_t hpnid; 362 nid_t spkrnid[8]; 363 nid_t eapdnid; 364} hdac_hp_switch[] = { 365 /* Specific OEM models */ 366 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 367 17, { 16, -1 }, 16 }, 368 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 369 6, { 5, -1 }, 5 }, 370 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 371 6, { 5, -1 }, 5 }, 372 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 373 13, { 14, -1 }, -1 }, 374 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 375 13, { 14, -1 }, -1 }, 376 /* 377 * All models that at least come from the same vendor with 378 * simmilar codec. 379 */ 380 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 381 17, { 16, -1 }, 16 }, 382 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 383 6, { 5, -1 }, 5 }, 384 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 385 13, { 14, -1 }, -1 }, 386}; 387#define HDAC_HP_SWITCH_LEN \ 388 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 389 390static const struct { 391 uint32_t model; 392 uint32_t id; 393 nid_t eapdnid; 394 int hp_switch; 395} hdac_eapd_switch[] = { 396 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 397 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 398 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 399}; 400#define HDAC_EAPD_SWITCH_LEN \ 401 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 402 403/**************************************************************************** 404 * Function prototypes 405 ****************************************************************************/ 406static void hdac_intr_handler(void *); 407static int hdac_reset(struct hdac_softc *); 408static int hdac_get_capabilities(struct hdac_softc *); 409static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 410static int hdac_dma_alloc(struct hdac_softc *, 411 struct hdac_dma *, bus_size_t); 412static void hdac_dma_free(struct hdac_dma *); 413static int hdac_mem_alloc(struct hdac_softc *); 414static void hdac_mem_free(struct hdac_softc *); 415static int hdac_irq_alloc(struct hdac_softc *); 416static void hdac_irq_free(struct hdac_softc *); 417static void hdac_corb_init(struct hdac_softc *); 418static void hdac_rirb_init(struct hdac_softc *); 419static void hdac_corb_start(struct hdac_softc *); 420static void hdac_rirb_start(struct hdac_softc *); 421static void hdac_scan_codecs(struct hdac_softc *); 422static int hdac_probe_codec(struct hdac_codec *); 423static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 424static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 425 426static void hdac_attach2(void *); 427 428static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 429 uint32_t, int); 430static void hdac_command_send_internal(struct hdac_softc *, 431 struct hdac_command_list *, int); 432 433static int hdac_probe(device_t); 434static int hdac_attach(device_t); 435static int hdac_detach(device_t); 436static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 437static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 438 uint32_t, int, int); 439static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 440 nid_t, int, int); 441static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 442 nid_t, nid_t, int, int, int, int, int, int); 443static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 444static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 445 446#define hdac_command(a1, a2, a3) \ 447 hdac_command_sendone_internal(a1, a2, a3) 448 449#define hdac_codec_id(d) \ 450 ((uint32_t)((d == NULL) ? 0x00000000 : \ 451 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 452 ((uint32_t)(d)->device_id & 0x0000ffff)))) 453 454static char * 455hdac_codec_name(struct hdac_devinfo *devinfo) 456{ 457 uint32_t id; 458 int i; 459 460 id = hdac_codec_id(devinfo); 461 462 for (i = 0; i < HDAC_CODECS_LEN; i++) { 463 if (HDA_FLAG_MATCH(hdac_codecs[i].id, id)) 464 return (hdac_codecs[i].name); 465 } 466 467 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 468} 469 470static char * 471hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 472{ 473 static char *ossname[] = SOUND_DEVICE_NAMES; 474 static char *unknown = "???"; 475 int i; 476 477 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 478 if (devmask & (1 << i)) 479 return (ossname[i]); 480 } 481 return (unknown); 482} 483 484static void 485hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 486{ 487 static char *ossname[] = SOUND_DEVICE_NAMES; 488 int i, first = 1; 489 490 bzero(buf, len); 491 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 492 if (mask & (1 << i)) { 493 if (first == 0) 494 strlcat(buf, ", ", len); 495 strlcat(buf, ossname[i], len); 496 first = 0; 497 } 498 } 499} 500 501static struct hdac_audio_ctl * 502hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 503{ 504 if (devinfo == NULL || 505 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 506 index == NULL || devinfo->function.audio.ctl == NULL || 507 devinfo->function.audio.ctlcnt < 1 || 508 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 509 return (NULL); 510 return (&devinfo->function.audio.ctl[(*index)++]); 511} 512 513static struct hdac_audio_ctl * 514hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 515 int index, int cnt) 516{ 517 struct hdac_audio_ctl *ctl, *retctl = NULL; 518 int i, at, atindex, found = 0; 519 520 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 521 return (NULL); 522 523 at = cnt; 524 if (at == 0) 525 at = 1; 526 else if (at < 0) 527 at = -1; 528 atindex = index; 529 if (atindex < 0) 530 atindex = -1; 531 532 i = 0; 533 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 534 if (ctl->enable == 0 || ctl->widget == NULL) 535 continue; 536 if (!(ctl->widget->nid == nid && (atindex == -1 || 537 ctl->index == atindex))) 538 continue; 539 found++; 540 if (found == cnt) 541 return (ctl); 542 retctl = ctl; 543 } 544 545 return ((at == -1) ? retctl : NULL); 546} 547 548static void 549hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 550{ 551 struct hdac_softc *sc; 552 struct hdac_widget *w; 553 struct hdac_audio_ctl *ctl; 554 uint32_t id, res; 555 int i = 0, j, forcemute; 556 nid_t cad; 557 558 if (devinfo == NULL || devinfo->codec == NULL || 559 devinfo->codec->sc == NULL) 560 return; 561 562 sc = devinfo->codec->sc; 563 cad = devinfo->codec->cad; 564 id = hdac_codec_id(devinfo); 565 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 566 if (HDA_FLAG_MATCH(hdac_hp_switch[i].model, 567 sc->pci_subvendor) && 568 hdac_hp_switch[i].id == id) 569 break; 570 } 571 572 if (i >= HDAC_HP_SWITCH_LEN) 573 return; 574 575 forcemute = 0; 576 if (hdac_hp_switch[i].eapdnid != -1) { 577 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 578 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 579 forcemute = (w->param.eapdbtl & 580 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 581 } 582 583 res = hdac_command(sc, 584 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 585 HDA_BOOTVERBOSE_MSG( 586 device_printf(sc->dev, 587 "Pin sense: nid=%d res=0x%08x\n", 588 hdac_hp_switch[i].hpnid, res); 589 ); 590 res >>= 31; 591 592 switch (hdac_hp_switch[i].type) { 593 case HDAC_HP_SWITCH_CTL: 594 ctl = hdac_audio_ctl_amp_get(devinfo, 595 hdac_hp_switch[i].hpnid, 0, 1); 596 if (ctl != NULL) { 597 ctl->muted = (res != 0 && forcemute == 0) ? 598 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 599 hdac_audio_ctl_amp_set(ctl, 600 HDA_AMP_MUTE_DEFAULT, ctl->left, 601 ctl->right); 602 } 603 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 604 ctl = hdac_audio_ctl_amp_get(devinfo, 605 hdac_hp_switch[i].spkrnid[j], 0, 1); 606 if (ctl != NULL) { 607 ctl->muted = (res != 0 || forcemute == 1) ? 608 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 609 hdac_audio_ctl_amp_set(ctl, 610 HDA_AMP_MUTE_DEFAULT, ctl->left, 611 ctl->right); 612 } 613 } 614 break; 615 case HDAC_HP_SWITCH_CTRL: 616 if (res != 0) { 617 /* HP in */ 618 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 619 if (w != NULL) { 620 if (forcemute == 0) 621 w->wclass.pin.ctrl |= 622 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 623 else 624 w->wclass.pin.ctrl &= 625 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 626 hdac_command(sc, 627 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 628 w->wclass.pin.ctrl), cad); 629 } 630 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 631 w = hdac_widget_get(devinfo, 632 hdac_hp_switch[i].spkrnid[j]); 633 if (w != NULL) { 634 w->wclass.pin.ctrl &= 635 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 636 hdac_command(sc, 637 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 638 w->nid, 639 w->wclass.pin.ctrl), cad); 640 } 641 } 642 } else { 643 /* HP out */ 644 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 645 if (w != NULL) { 646 w->wclass.pin.ctrl &= 647 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 648 hdac_command(sc, 649 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 650 w->wclass.pin.ctrl), cad); 651 } 652 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 653 w = hdac_widget_get(devinfo, 654 hdac_hp_switch[i].spkrnid[j]); 655 if (w != NULL) { 656 if (forcemute == 0) 657 w->wclass.pin.ctrl |= 658 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 659 else 660 w->wclass.pin.ctrl &= 661 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 662 hdac_command(sc, 663 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 664 w->nid, 665 w->wclass.pin.ctrl), cad); 666 } 667 } 668 } 669 break; 670 default: 671 break; 672 } 673} 674 675static void 676hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 677{ 678 struct hdac_softc *sc; 679 struct hdac_devinfo *devinfo = NULL; 680 device_t *devlist = NULL; 681 int devcount, i; 682 683 if (codec == NULL || codec->sc == NULL) 684 return; 685 686 sc = codec->sc; 687 688 HDA_BOOTVERBOSE_MSG( 689 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 690 ); 691 692 device_get_children(sc->dev, &devlist, &devcount); 693 for (i = 0; devlist != NULL && i < devcount; i++) { 694 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 695 if (devinfo != NULL && devinfo->node_type == 696 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 697 devinfo->codec != NULL && 698 devinfo->codec->cad == codec->cad) { 699 break; 700 } else 701 devinfo = NULL; 702 } 703 if (devlist != NULL) 704 free(devlist, M_TEMP); 705 706 if (devinfo == NULL) 707 return; 708 709 switch (tag) { 710 case HDAC_UNSOLTAG_EVENT_HP: 711 hdac_hp_switch_handler(devinfo); 712 break; 713 default: 714 break; 715 } 716} 717 718static void 719hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 720{ 721 /* XXX to be removed */ 722#ifdef HDAC_INTR_EXTRA 723 uint32_t res; 724#endif 725 726 if (ch->blkcnt == 0) 727 return; 728 729 /* XXX to be removed */ 730#ifdef HDAC_INTR_EXTRA 731 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 732#endif 733 734 /* XXX to be removed */ 735#ifdef HDAC_INTR_EXTRA 736 if ((res & HDAC_SDSTS_DESE) || (res & HDAC_SDSTS_FIFOE)) 737 device_printf(sc->dev, 738 "PCMDIR_%s intr triggered beyond stream boundary: %08x\n", 739 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 740#endif 741 742 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 743 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 744 745 /* XXX to be removed */ 746#ifdef HDAC_INTR_EXTRA 747 if (res & HDAC_SDSTS_BCIS) { 748#endif 749 ch->prevptr = ch->ptr; 750 ch->ptr += sndbuf_getblksz(ch->b); 751 ch->ptr %= sndbuf_getsize(ch->b); 752 hdac_unlock(sc); 753 chn_intr(ch->c); 754 hdac_lock(sc); 755 /* XXX to be removed */ 756#ifdef HDAC_INTR_EXTRA 757 } 758#endif 759} 760 761/**************************************************************************** 762 * void hdac_intr_handler(void *) 763 * 764 * Interrupt handler. Processes interrupts received from the hdac. 765 ****************************************************************************/ 766static void 767hdac_intr_handler(void *context) 768{ 769 struct hdac_softc *sc; 770 uint32_t intsts; 771 uint8_t rirbsts; 772 uint8_t rirbwp; 773 struct hdac_rirb *rirb_base, *rirb; 774 nid_t ucad; 775 uint32_t utag; 776 777 sc = (struct hdac_softc *)context; 778 779 hdac_lock(sc); 780 /* Do we have anything to do? */ 781 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 782 if ((intsts & HDAC_INTSTS_GIS) != HDAC_INTSTS_GIS) { 783 hdac_unlock(sc); 784 return; 785 } 786 787 /* Was this a controller interrupt? */ 788 if ((intsts & HDAC_INTSTS_CIS) == HDAC_INTSTS_CIS) { 789 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 790 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 791 /* Get as many responses that we can */ 792 while ((rirbsts & HDAC_RIRBSTS_RINTFL) == HDAC_RIRBSTS_RINTFL) { 793 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 794 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 795 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 796 BUS_DMASYNC_POSTREAD); 797 while (sc->rirb_rp != rirbwp) { 798 sc->rirb_rp++; 799 sc->rirb_rp %= sc->rirb_size; 800 rirb = &rirb_base[sc->rirb_rp]; 801 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 802 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 803 utag = rirb->response >> 26; 804 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 805 sc->codecs[ucad] != NULL) { 806 sc->unsolq[sc->unsolq_wp++] = 807 (ucad << 16) | 808 (utag & 0xffff); 809 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 810 } 811 } 812 } 813 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 814 } 815 /* XXX to be removed */ 816 /* Clear interrupt and exit */ 817#ifdef HDAC_INTR_EXTRA 818 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 819#endif 820 } 821 if ((intsts & HDAC_INTSTS_SIS_MASK)) { 822 if (intsts & (1 << sc->num_iss)) 823 hdac_stream_intr(sc, &sc->play); 824 if (intsts & (1 << 0)) 825 hdac_stream_intr(sc, &sc->rec); 826 /* XXX to be removed */ 827#ifdef HDAC_INTR_EXTRA 828 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK); 829#endif 830 } 831 832 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 833 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 834 while (sc->unsolq_rp != sc->unsolq_wp) { 835 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 836 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 837 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 838 hdac_unsolicited_handler(sc->codecs[ucad], utag); 839 } 840 sc->unsolq_st = HDAC_UNSOLQ_READY; 841 } 842 843 hdac_unlock(sc); 844} 845 846/**************************************************************************** 847 * int had_reset(hdac_softc *) 848 * 849 * Reset the hdac to a quiescent and known state. 850 ****************************************************************************/ 851static int 852hdac_reset(struct hdac_softc *sc) 853{ 854 uint32_t gctl; 855 int count, i; 856 857 /* 858 * Stop all Streams DMA engine 859 */ 860 for (i = 0; i < sc->num_iss; i++) 861 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 862 for (i = 0; i < sc->num_oss; i++) 863 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 864 for (i = 0; i < sc->num_bss; i++) 865 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 866 867 /* 868 * Stop Control DMA engines 869 */ 870 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 871 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 872 873 /* 874 * Reset the controller. The reset must remain asserted for 875 * a minimum of 100us. 876 */ 877 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 878 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 879 count = 10000; 880 do { 881 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 882 if (!(gctl & HDAC_GCTL_CRST)) 883 break; 884 DELAY(10); 885 } while (--count); 886 if (gctl & HDAC_GCTL_CRST) { 887 device_printf(sc->dev, "Unable to put hdac in reset\n"); 888 return (ENXIO); 889 } 890 DELAY(100); 891 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 892 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 893 count = 10000; 894 do { 895 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 896 if ((gctl & HDAC_GCTL_CRST)) 897 break; 898 DELAY(10); 899 } while (--count); 900 if (!(gctl & HDAC_GCTL_CRST)) { 901 device_printf(sc->dev, "Device stuck in reset\n"); 902 return (ENXIO); 903 } 904 905 /* 906 * Enable unsolicited interrupt. 907 */ 908 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 909 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_UNSOL); 910 911 /* 912 * Wait for codecs to finish their own reset sequence. The delay here 913 * should be of 250us but for some reasons, on it's not enough on my 914 * computer. Let's use twice as much as necessary to make sure that 915 * it's reset properly. 916 */ 917 DELAY(1000); 918 919 return (0); 920} 921 922 923/**************************************************************************** 924 * int hdac_get_capabilities(struct hdac_softc *); 925 * 926 * Retreive the general capabilities of the hdac; 927 * Number of Input Streams 928 * Number of Output Streams 929 * Number of bidirectional Streams 930 * 64bit ready 931 * CORB and RIRB sizes 932 ****************************************************************************/ 933static int 934hdac_get_capabilities(struct hdac_softc *sc) 935{ 936 uint16_t gcap; 937 uint8_t corbsize, rirbsize; 938 939 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 940 sc->num_iss = HDAC_GCAP_ISS(gcap); 941 sc->num_oss = HDAC_GCAP_OSS(gcap); 942 sc->num_bss = HDAC_GCAP_BSS(gcap); 943 944 sc->support_64bit = (gcap & HDAC_GCAP_64OK) == HDAC_GCAP_64OK; 945 946 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 947 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 948 HDAC_CORBSIZE_CORBSZCAP_256) 949 sc->corb_size = 256; 950 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 951 HDAC_CORBSIZE_CORBSZCAP_16) 952 sc->corb_size = 16; 953 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 954 HDAC_CORBSIZE_CORBSZCAP_2) 955 sc->corb_size = 2; 956 else { 957 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 958 __func__, corbsize); 959 return (ENXIO); 960 } 961 962 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 963 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 964 HDAC_RIRBSIZE_RIRBSZCAP_256) 965 sc->rirb_size = 256; 966 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 967 HDAC_RIRBSIZE_RIRBSZCAP_16) 968 sc->rirb_size = 16; 969 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 970 HDAC_RIRBSIZE_RIRBSZCAP_2) 971 sc->rirb_size = 2; 972 else { 973 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 974 __func__, rirbsize); 975 return (ENXIO); 976 } 977 978 return (0); 979} 980 981 982/**************************************************************************** 983 * void hdac_dma_cb 984 * 985 * This function is called by bus_dmamap_load when the mapping has been 986 * established. We just record the physical address of the mapping into 987 * the struct hdac_dma passed in. 988 ****************************************************************************/ 989static void 990hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 991{ 992 struct hdac_dma *dma; 993 994 if (error == 0) { 995 dma = (struct hdac_dma *)callback_arg; 996 dma->dma_paddr = segs[0].ds_addr; 997 } 998} 999 1000static void 1001hdac_dma_nocache(void *ptr) 1002{ 1003#if defined(__i386__) || defined(__amd64__) 1004 pt_entry_t *pte; 1005 vm_offset_t va; 1006 1007 va = (vm_offset_t)ptr; 1008 pte = vtopte(va); 1009 if (pte) { 1010 *pte |= PG_N; 1011 invltlb(); 1012 } 1013#endif 1014} 1015 1016/**************************************************************************** 1017 * int hdac_dma_alloc 1018 * 1019 * This function allocate and setup a dma region (struct hdac_dma). 1020 * It must be freed by a corresponding hdac_dma_free. 1021 ****************************************************************************/ 1022static int 1023hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1024{ 1025 int result; 1026 int lowaddr; 1027 1028 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1029 BUS_SPACE_MAXADDR_32BIT; 1030 bzero(dma, sizeof(*dma)); 1031 1032 /* 1033 * Create a DMA tag 1034 */ 1035 result = bus_dma_tag_create(NULL, /* parent */ 1036 HDAC_DMA_ALIGNMENT, /* alignment */ 1037 0, /* boundary */ 1038 lowaddr, /* lowaddr */ 1039 BUS_SPACE_MAXADDR, /* highaddr */ 1040 NULL, /* filtfunc */ 1041 NULL, /* fistfuncarg */ 1042 size, /* maxsize */ 1043 1, /* nsegments */ 1044 size, /* maxsegsz */ 1045 0, /* flags */ 1046 NULL, /* lockfunc */ 1047 NULL, /* lockfuncarg */ 1048 &dma->dma_tag); /* dmat */ 1049 if (result != 0) { 1050 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1051 __func__, result); 1052 goto fail; 1053 } 1054 1055 /* 1056 * Allocate DMA memory 1057 */ 1058 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1059 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1060 if (result != 0) { 1061 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1062 __func__, result); 1063 goto fail; 1064 } 1065 1066 /* 1067 * Map the memory 1068 */ 1069 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1070 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1071 BUS_DMA_NOWAIT); 1072 if (result != 0 || dma->dma_paddr == 0) { 1073 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1074 __func__, result); 1075 goto fail; 1076 } 1077 bzero((void *)dma->dma_vaddr, size); 1078 hdac_dma_nocache(dma->dma_vaddr); 1079 1080 return (0); 1081fail: 1082 if (dma->dma_map != NULL) 1083 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1084 if (dma->dma_tag != NULL) 1085 bus_dma_tag_destroy(dma->dma_tag); 1086 return (result); 1087} 1088 1089 1090/**************************************************************************** 1091 * void hdac_dma_free(struct hdac_dma *) 1092 * 1093 * Free a struct dhac_dma that has been previously allocated via the 1094 * hdac_dma_alloc function. 1095 ****************************************************************************/ 1096static void 1097hdac_dma_free(struct hdac_dma *dma) 1098{ 1099 if (dma->dma_tag != NULL) { 1100 /* Flush caches */ 1101 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1102 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1103 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1104 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1105 bus_dma_tag_destroy(dma->dma_tag); 1106 } 1107} 1108 1109/**************************************************************************** 1110 * int hdac_mem_alloc(struct hdac_softc *) 1111 * 1112 * Allocate all the bus resources necessary to speak with the physical 1113 * controller. 1114 ****************************************************************************/ 1115static int 1116hdac_mem_alloc(struct hdac_softc *sc) 1117{ 1118 struct hdac_mem *mem; 1119 1120 mem = &sc->mem; 1121 mem->mem_rid = PCIR_BAR(0); 1122 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1123 &mem->mem_rid, RF_ACTIVE); 1124 if (mem->mem_res == NULL) { 1125 device_printf(sc->dev, 1126 "%s: Unable to allocate memory resource\n", __func__); 1127 return (ENOMEM); 1128 } 1129 mem->mem_tag = rman_get_bustag(mem->mem_res); 1130 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1131 1132 return (0); 1133} 1134 1135/**************************************************************************** 1136 * void hdac_mem_free(struct hdac_softc *) 1137 * 1138 * Free up resources previously allocated by hdac_mem_alloc. 1139 ****************************************************************************/ 1140static void 1141hdac_mem_free(struct hdac_softc *sc) 1142{ 1143 struct hdac_mem *mem; 1144 1145 mem = &sc->mem; 1146 if (mem->mem_res != NULL) 1147 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1148 mem->mem_res); 1149} 1150 1151/**************************************************************************** 1152 * int hdac_irq_alloc(struct hdac_softc *) 1153 * 1154 * Allocate and setup the resources necessary for interrupt handling. 1155 ****************************************************************************/ 1156static int 1157hdac_irq_alloc(struct hdac_softc *sc) 1158{ 1159 struct hdac_irq *irq; 1160 int result; 1161 1162 irq = &sc->irq; 1163 irq->irq_rid = 0x0; 1164 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1165 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1166 if (irq->irq_res == NULL) { 1167 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1168 __func__); 1169 goto fail; 1170 } 1171 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1172 hdac_intr_handler, sc, &irq->irq_handle); 1173 if (result != 0) { 1174 device_printf(sc->dev, 1175 "%s: Unable to setup interrupt handler (%x)\n", 1176 __func__, result); 1177 goto fail; 1178 } 1179 1180 return (0); 1181 1182fail: 1183 if (irq->irq_res != NULL) 1184 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1185 irq->irq_res); 1186 return (ENXIO); 1187} 1188 1189/**************************************************************************** 1190 * void hdac_irq_free(struct hdac_softc *) 1191 * 1192 * Free up resources previously allocated by hdac_irq_alloc. 1193 ****************************************************************************/ 1194static void 1195hdac_irq_free(struct hdac_softc *sc) 1196{ 1197 struct hdac_irq *irq; 1198 1199 irq = &sc->irq; 1200 if (irq->irq_handle != NULL) 1201 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1202 if (irq->irq_res != NULL) 1203 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1204 irq->irq_res); 1205} 1206 1207/**************************************************************************** 1208 * void hdac_corb_init(struct hdac_softc *) 1209 * 1210 * Initialize the corb registers for operations but do not start it up yet. 1211 * The CORB engine must not be running when this function is called. 1212 ****************************************************************************/ 1213static void 1214hdac_corb_init(struct hdac_softc *sc) 1215{ 1216 uint8_t corbsize; 1217 uint64_t corbpaddr; 1218 1219 /* Setup the CORB size. */ 1220 switch (sc->corb_size) { 1221 case 256: 1222 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1223 break; 1224 case 16: 1225 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1226 break; 1227 case 2: 1228 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1229 break; 1230 default: 1231 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1232 } 1233 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1234 1235 /* Setup the CORB Address in the hdac */ 1236 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1237 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1238 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1239 1240 /* Set the WP and RP */ 1241 sc->corb_wp = 0; 1242 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1243 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1244 /* 1245 * The HDA specification indicates that the CORBRPRST bit will always 1246 * read as zero. Unfortunately, it seems that at least the 82801G 1247 * doesn't reset the bit to zero, which stalls the corb engine. 1248 * manually reset the bit to zero before continuing. 1249 */ 1250 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1251 1252 /* Enable CORB error reporting */ 1253#if 0 1254 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1255#endif 1256} 1257 1258/**************************************************************************** 1259 * void hdac_rirb_init(struct hdac_softc *) 1260 * 1261 * Initialize the rirb registers for operations but do not start it up yet. 1262 * The RIRB engine must not be running when this function is called. 1263 ****************************************************************************/ 1264static void 1265hdac_rirb_init(struct hdac_softc *sc) 1266{ 1267 uint8_t rirbsize; 1268 uint64_t rirbpaddr; 1269 1270 /* Setup the RIRB size. */ 1271 switch (sc->rirb_size) { 1272 case 256: 1273 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1274 break; 1275 case 16: 1276 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1277 break; 1278 case 2: 1279 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1280 break; 1281 default: 1282 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1283 } 1284 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1285 1286 /* Setup the RIRB Address in the hdac */ 1287 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1288 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1289 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1290 1291 /* Setup the WP and RP */ 1292 sc->rirb_rp = 0; 1293 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1294 1295 /* Setup the interrupt threshold */ 1296 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1297 1298 /* Enable Overrun and response received reporting */ 1299#if 0 1300 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1301 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1302#else 1303 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1304#endif 1305 1306 /* 1307 * Make sure that the Host CPU cache doesn't contain any dirty 1308 * cache lines that falls in the rirb. If I understood correctly, it 1309 * should be sufficient to do this only once as the rirb is purely 1310 * read-only from now on. 1311 */ 1312 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1313 BUS_DMASYNC_PREREAD); 1314} 1315 1316/**************************************************************************** 1317 * void hdac_corb_start(hdac_softc *) 1318 * 1319 * Startup the corb DMA engine 1320 ****************************************************************************/ 1321static void 1322hdac_corb_start(struct hdac_softc *sc) 1323{ 1324 uint32_t corbctl; 1325 1326 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1327 corbctl |= HDAC_CORBCTL_CORBRUN; 1328 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1329} 1330 1331/**************************************************************************** 1332 * void hdac_rirb_start(hdac_softc *) 1333 * 1334 * Startup the rirb DMA engine 1335 ****************************************************************************/ 1336static void 1337hdac_rirb_start(struct hdac_softc *sc) 1338{ 1339 uint32_t rirbctl; 1340 1341 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1342 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1343 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1344} 1345 1346 1347/**************************************************************************** 1348 * void hdac_scan_codecs(struct hdac_softc *) 1349 * 1350 * Scan the bus for available codecs. 1351 ****************************************************************************/ 1352static void 1353hdac_scan_codecs(struct hdac_softc *sc) 1354{ 1355 struct hdac_codec *codec; 1356 int i; 1357 uint16_t statests; 1358 1359 SLIST_INIT(&sc->codec_list); 1360 1361 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1362 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1363 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1364 /* We have found a codec. */ 1365 hdac_unlock(sc); 1366 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1367 M_HDAC, M_ZERO | M_NOWAIT); 1368 hdac_lock(sc); 1369 if (codec == NULL) { 1370 device_printf(sc->dev, 1371 "Unable to allocate memory for codec\n"); 1372 continue; 1373 } 1374 codec->verbs_sent = 0; 1375 codec->sc = sc; 1376 codec->cad = i; 1377 sc->codecs[i] = codec; 1378 SLIST_INSERT_HEAD(&sc->codec_list, codec, next_codec); 1379 if (hdac_probe_codec(codec) != 0) 1380 break; 1381 } 1382 } 1383 /* All codecs have been probed, now try to attach drivers to them */ 1384 bus_generic_attach(sc->dev); 1385} 1386 1387/**************************************************************************** 1388 * void hdac_probe_codec(struct hdac_softc *, int) 1389 * 1390 * Probe a the given codec_id for available function groups. 1391 ****************************************************************************/ 1392static int 1393hdac_probe_codec(struct hdac_codec *codec) 1394{ 1395 struct hdac_softc *sc = codec->sc; 1396 struct hdac_devinfo *devinfo; 1397 uint32_t vendorid, revisionid, subnode; 1398 int startnode; 1399 int endnode; 1400 int i; 1401 nid_t cad = codec->cad; 1402 1403 HDA_DEBUG_MSG( 1404 device_printf(sc->dev, "%s: Probing codec: %d\n", 1405 __func__, cad); 1406 ); 1407 vendorid = hdac_command(sc, 1408 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1409 cad); 1410 revisionid = hdac_command(sc, 1411 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1412 cad); 1413 subnode = hdac_command(sc, 1414 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1415 cad); 1416 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1417 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1418 1419 HDA_DEBUG_MSG( 1420 device_printf(sc->dev, "%s: \tstartnode=%d endnode=%d\n", 1421 __func__, startnode, endnode); 1422 ); 1423 for (i = startnode; i < endnode; i++) { 1424 devinfo = hdac_probe_function(codec, i); 1425 if (devinfo != NULL) { 1426 /* XXX Ignore other FG. */ 1427 devinfo->vendor_id = 1428 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1429 devinfo->device_id = 1430 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1431 devinfo->revision_id = 1432 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1433 devinfo->stepping_id = 1434 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1435 HDA_DEBUG_MSG( 1436 device_printf(sc->dev, 1437 "%s: \tFound AFG nid=%d " 1438 "[startnode=%d endnode=%d]\n", 1439 __func__, devinfo->nid, 1440 startnode, endnode); 1441 ); 1442 return (1); 1443 } 1444 } 1445 1446 HDA_DEBUG_MSG( 1447 device_printf(sc->dev, "%s: \tAFG not found\n", 1448 __func__); 1449 ); 1450 return (0); 1451} 1452 1453static struct hdac_devinfo * 1454hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1455{ 1456 struct hdac_softc *sc = codec->sc; 1457 struct hdac_devinfo *devinfo; 1458 uint32_t fctgrptype; 1459 nid_t cad = codec->cad; 1460 1461 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1462 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1463 1464 /* XXX For now, ignore other FG. */ 1465 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1466 return (NULL); 1467 1468 hdac_unlock(sc); 1469 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1470 M_NOWAIT | M_ZERO); 1471 hdac_lock(sc); 1472 if (devinfo == NULL) { 1473 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1474 __func__); 1475 return (NULL); 1476 } 1477 1478 devinfo->nid = nid; 1479 devinfo->node_type = fctgrptype; 1480 devinfo->codec = codec; 1481 1482 hdac_add_child(sc, devinfo); 1483 1484 return (devinfo); 1485} 1486 1487static void 1488hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1489{ 1490 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1491 device_set_ivars(devinfo->dev, (void *)devinfo); 1492 /* XXX - Print more information when booting verbose??? */ 1493} 1494 1495static void 1496hdac_widget_connection_parse(struct hdac_widget *w) 1497{ 1498 struct hdac_softc *sc = w->devinfo->codec->sc; 1499 uint32_t res; 1500 int i, j, max, found, entnum, cnid; 1501 nid_t cad = w->devinfo->codec->cad; 1502 nid_t nid = w->nid; 1503 1504 res = hdac_command(sc, 1505 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1506 1507 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1508 1509 if (w->nconns < 1) 1510 return; 1511 1512 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1513 res = 0; 1514 i = 0; 1515 found = 0; 1516 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1517 1518 while (i < w->nconns) { 1519 res = hdac_command(sc, 1520 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1521 for (j = 0; j < entnum; j++) { 1522 cnid = res; 1523 cnid >>= (32 / entnum) * j; 1524 cnid &= (1 << (32 / entnum)) - 1; 1525 if (cnid == 0) 1526 continue; 1527 if (found > max) { 1528 device_printf(sc->dev, 1529 "node %d: Adding %d: " 1530 "Max connection reached!\n", 1531 nid, cnid); 1532 continue; 1533 } 1534 w->conns[found++] = cnid; 1535 } 1536 i += entnum; 1537 } 1538 1539 HDA_BOOTVERBOSE_MSG( 1540 if (w->nconns != found) { 1541 device_printf(sc->dev, 1542 "node %d: WARNING!!! Connection " 1543 "length=%d != found=%d\n", 1544 nid, w->nconns, found); 1545 } 1546 ); 1547} 1548 1549static uint32_t 1550hdac_widget_pin_getconfig(struct hdac_widget *w) 1551{ 1552 struct hdac_softc *sc; 1553 uint32_t config, id; 1554 nid_t cad, nid; 1555 1556 sc = w->devinfo->codec->sc; 1557 cad = w->devinfo->codec->cad; 1558 nid = w->nid; 1559 id = hdac_codec_id(w->devinfo); 1560 1561 config = hdac_command(sc, 1562 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1563 cad); 1564 /* 1565 * XXX REWRITE!!!! Don't argue! 1566 */ 1567 if (id == HDA_CODEC_ALC880 && 1568 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1569 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1570 /* 1571 * Super broken BIOS 1572 */ 1573 switch (nid) { 1574 case 20: 1575 break; 1576 case 21: 1577 break; 1578 case 22: 1579 break; 1580 case 23: 1581 break; 1582 case 24: /* MIC1 */ 1583 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1584 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1585 break; 1586 case 25: /* XXX MIC2 */ 1587 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1588 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1589 break; 1590 case 26: /* LINE1 */ 1591 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1592 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1593 break; 1594 case 27: /* XXX LINE2 */ 1595 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1596 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1597 break; 1598 case 28: /* CD */ 1599 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1600 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1601 break; 1602 case 30: 1603 break; 1604 case 31: 1605 break; 1606 default: 1607 break; 1608 } 1609 } 1610 1611 return (config); 1612} 1613 1614static void 1615hdac_widget_pin_parse(struct hdac_widget *w) 1616{ 1617 struct hdac_softc *sc = w->devinfo->codec->sc; 1618 uint32_t config, pincap; 1619 char *devstr, *connstr; 1620 nid_t cad = w->devinfo->codec->cad; 1621 nid_t nid = w->nid; 1622 1623 config = hdac_widget_pin_getconfig(w); 1624 w->wclass.pin.config = config; 1625 1626 pincap = hdac_command(sc, 1627 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1628 w->wclass.pin.cap = pincap; 1629 1630 w->wclass.pin.ctrl = hdac_command(sc, 1631 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1632 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1633 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1634 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1635 1636 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1637 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1638 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1639 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1640 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1641 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1642 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1643 w->param.eapdbtl = hdac_command(sc, 1644 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1645 w->param.eapdbtl &= 0x7; 1646 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1647 } else 1648 w->param.eapdbtl = HDAC_INVALID; 1649 1650 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1651 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1652 devstr = "line out"; 1653 break; 1654 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1655 devstr = "speaker"; 1656 break; 1657 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1658 devstr = "headphones out"; 1659 break; 1660 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1661 devstr = "CD"; 1662 break; 1663 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1664 devstr = "SPDIF out"; 1665 break; 1666 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1667 devstr = "digital (other) out"; 1668 break; 1669 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1670 devstr = "modem, line side"; 1671 break; 1672 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1673 devstr = "modem, handset side"; 1674 break; 1675 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1676 devstr = "line in"; 1677 break; 1678 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1679 devstr = "AUX"; 1680 break; 1681 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1682 devstr = "Mic in"; 1683 break; 1684 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1685 devstr = "telephony"; 1686 break; 1687 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1688 devstr = "SPDIF in"; 1689 break; 1690 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1691 devstr = "digital (other) in"; 1692 break; 1693 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1694 devstr = "other"; 1695 break; 1696 default: 1697 devstr = "unknown"; 1698 break; 1699 } 1700 1701 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1702 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1703 connstr = "jack"; 1704 break; 1705 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1706 connstr = "none"; 1707 break; 1708 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1709 connstr = "fixed"; 1710 break; 1711 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1712 connstr = "jack / fixed"; 1713 break; 1714 default: 1715 connstr = "unknown"; 1716 break; 1717 } 1718 1719 strlcat(w->name, ": ", sizeof(w->name)); 1720 strlcat(w->name, devstr, sizeof(w->name)); 1721 strlcat(w->name, " (", sizeof(w->name)); 1722 strlcat(w->name, connstr, sizeof(w->name)); 1723 strlcat(w->name, ")", sizeof(w->name)); 1724} 1725 1726static void 1727hdac_widget_parse(struct hdac_widget *w) 1728{ 1729 struct hdac_softc *sc = w->devinfo->codec->sc; 1730 uint32_t wcap, cap; 1731 char *typestr; 1732 nid_t cad = w->devinfo->codec->cad; 1733 nid_t nid = w->nid; 1734 1735 wcap = hdac_command(sc, 1736 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1737 cad); 1738 w->param.widget_cap = wcap; 1739 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1740 1741 switch (w->type) { 1742 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1743 typestr = "audio output"; 1744 break; 1745 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1746 typestr = "audio input"; 1747 break; 1748 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1749 typestr = "audio mixer"; 1750 break; 1751 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1752 typestr = "audio selector"; 1753 break; 1754 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1755 typestr = "pin"; 1756 break; 1757 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1758 typestr = "power widget"; 1759 break; 1760 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1761 typestr = "volume widget"; 1762 break; 1763 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1764 typestr = "beep widget"; 1765 break; 1766 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1767 typestr = "vendor widget"; 1768 break; 1769 default: 1770 typestr = "unknown type"; 1771 break; 1772 } 1773 1774 strlcpy(w->name, typestr, sizeof(w->name)); 1775 1776 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1777 hdac_command(sc, 1778 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1779 cad); 1780 DELAY(1000); 1781 } 1782 1783 hdac_widget_connection_parse(w); 1784 1785 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1786 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1787 w->param.outamp_cap = 1788 hdac_command(sc, 1789 HDA_CMD_GET_PARAMETER(cad, nid, 1790 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1791 else 1792 w->param.outamp_cap = 1793 w->devinfo->function.audio.outamp_cap; 1794 } else 1795 w->param.outamp_cap = 0; 1796 1797 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1798 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1799 w->param.inamp_cap = 1800 hdac_command(sc, 1801 HDA_CMD_GET_PARAMETER(cad, nid, 1802 HDA_PARAM_INPUT_AMP_CAP), cad); 1803 else 1804 w->param.inamp_cap = 1805 w->devinfo->function.audio.inamp_cap; 1806 } else 1807 w->param.inamp_cap = 0; 1808 1809 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1810 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1811 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1812 cap = hdac_command(sc, 1813 HDA_CMD_GET_PARAMETER(cad, nid, 1814 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1815 w->param.supp_stream_formats = (cap != 0) ? cap : 1816 w->devinfo->function.audio.supp_stream_formats; 1817 cap = hdac_command(sc, 1818 HDA_CMD_GET_PARAMETER(cad, nid, 1819 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1820 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1821 w->devinfo->function.audio.supp_pcm_size_rate; 1822 } else { 1823 w->param.supp_stream_formats = 1824 w->devinfo->function.audio.supp_stream_formats; 1825 w->param.supp_pcm_size_rate = 1826 w->devinfo->function.audio.supp_pcm_size_rate; 1827 } 1828 } else { 1829 w->param.supp_stream_formats = 0; 1830 w->param.supp_pcm_size_rate = 0; 1831 } 1832 1833 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1834 hdac_widget_pin_parse(w); 1835} 1836 1837static struct hdac_widget * 1838hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1839{ 1840 if (devinfo == NULL || devinfo->widget == NULL || 1841 nid < devinfo->startnode || nid >= devinfo->endnode) 1842 return (NULL); 1843 return (&devinfo->widget[nid - devinfo->startnode]); 1844} 1845 1846static void 1847hdac_stream_stop(struct hdac_chan *ch) 1848{ 1849 struct hdac_softc *sc = ch->devinfo->codec->sc; 1850 uint32_t ctl; 1851 1852 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1853 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1854 HDAC_SDCTL_RUN); 1855 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1856 1857 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1858 ctl &= ~(1 << (ch->off >> 5)); 1859 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1860} 1861 1862static void 1863hdac_stream_start(struct hdac_chan *ch) 1864{ 1865 struct hdac_softc *sc = ch->devinfo->codec->sc; 1866 uint32_t ctl; 1867 1868 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1869 ctl |= 1 << (ch->off >> 5); 1870 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1871 1872 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1873 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1874 HDAC_SDCTL_RUN; 1875 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1876} 1877 1878static void 1879hdac_stream_reset(struct hdac_chan *ch) 1880{ 1881 struct hdac_softc *sc = ch->devinfo->codec->sc; 1882 int timeout = 1000; 1883 int to = timeout; 1884 uint32_t ctl; 1885 1886 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1887 ctl |= HDAC_SDCTL_SRST; 1888 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1889 do { 1890 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1891 if (ctl & HDAC_SDCTL_SRST) 1892 break; 1893 DELAY(10); 1894 } while (--to); 1895 if (!(ctl & HDAC_SDCTL_SRST)) { 1896 device_printf(sc->dev, "timeout in reset\n"); 1897 } 1898 ctl &= ~HDAC_SDCTL_SRST; 1899 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1900 to = timeout; 1901 do { 1902 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1903 if (!(ctl & HDAC_SDCTL_SRST)) 1904 break; 1905 DELAY(10); 1906 } while (--to); 1907 if ((ctl & HDAC_SDCTL_SRST)) 1908 device_printf(sc->dev, "can't reset!\n"); 1909} 1910 1911static void 1912hdac_stream_setid(struct hdac_chan *ch) 1913{ 1914 struct hdac_softc *sc = ch->devinfo->codec->sc; 1915 uint32_t ctl; 1916 1917 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 1918 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1919 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 1920 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 1921} 1922 1923static void 1924hdac_bdl_setup(struct hdac_chan *ch) 1925{ 1926 struct hdac_softc *sc = ch->devinfo->codec->sc; 1927 uint64_t addr; 1928 int blks, size, blocksize; 1929 struct hdac_bdle *bdle; 1930 int i; 1931 1932 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 1933 size = sndbuf_getsize(ch->b); 1934 blocksize = sndbuf_getblksz(ch->b); 1935 blks = size / blocksize; 1936 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr; 1937 1938 for (i = 0; i < blks; i++, bdle++) { 1939 bdle->addrl = (uint32_t)addr; 1940 bdle->addrh = (uint32_t)(addr >> 32); 1941 bdle->len = blocksize; 1942 bdle->ioc = 1; 1943 1944 addr += blocksize; 1945 } 1946 1947 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size); 1948 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1); 1949 addr = ch->bdl_dma.dma_paddr; 1950 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 1951 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1952} 1953 1954static int 1955hdac_bdl_alloc(struct hdac_chan *ch) 1956{ 1957 struct hdac_softc *sc = ch->devinfo->codec->sc; 1958 int rc; 1959 1960 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 1961 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1962 if (rc) { 1963 device_printf(sc->dev, "can't alloc bdl\n"); 1964 return (rc); 1965 } 1966 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 1967 1968 return (0); 1969} 1970 1971static void 1972hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 1973 int index, int lmute, int rmute, 1974 int left, int right, int dir) 1975{ 1976 uint16_t v = 0; 1977 1978 if (sc == NULL) 1979 return; 1980 1981 if (left != right || lmute != rmute) { 1982 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 1983 (lmute << 7) | left; 1984 hdac_command(sc, 1985 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 1986 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 1987 (rmute << 7) | right; 1988 } else 1989 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 1990 (lmute << 7) | left; 1991 1992 hdac_command(sc, 1993 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 1994} 1995 1996static void 1997hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 1998 int left, int right) 1999{ 2000 struct hdac_softc *sc; 2001 nid_t nid, cad; 2002 int lmute, rmute; 2003 2004 if (ctl == NULL || ctl->widget == NULL || 2005 ctl->widget->devinfo == NULL || 2006 ctl->widget->devinfo->codec == NULL || 2007 ctl->widget->devinfo->codec->sc == NULL) 2008 return; 2009 2010 sc = ctl->widget->devinfo->codec->sc; 2011 cad = ctl->widget->devinfo->codec->cad; 2012 nid = ctl->widget->nid; 2013 2014 if (mute == HDA_AMP_MUTE_DEFAULT) { 2015 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2016 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2017 } else { 2018 lmute = HDA_AMP_LEFT_MUTED(mute); 2019 rmute = HDA_AMP_RIGHT_MUTED(mute); 2020 } 2021 2022 if (ctl->dir & HDA_CTL_OUT) 2023 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2024 lmute, rmute, left, right, 0); 2025 if (ctl->dir & HDA_CTL_IN) 2026 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2027 lmute, rmute, left, right, 1); 2028 ctl->left = left; 2029 ctl->right = right; 2030} 2031 2032static void 2033hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2034{ 2035 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2036 return; 2037 hdac_command(w->devinfo->codec->sc, 2038 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2039 w->nid, index), w->devinfo->codec->cad); 2040 w->selconn = index; 2041} 2042 2043 2044/**************************************************************************** 2045 * uint32_t hdac_command_sendone_internal 2046 * 2047 * Wrapper function that sends only one command to a given codec 2048 ****************************************************************************/ 2049static uint32_t 2050hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2051{ 2052 struct hdac_command_list cl; 2053 uint32_t response = HDAC_INVALID; 2054 2055 if (!mtx_owned(sc->lock)) 2056 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2057 cl.num_commands = 1; 2058 cl.verbs = &verb; 2059 cl.responses = &response; 2060 2061 hdac_command_send_internal(sc, &cl, cad); 2062 2063 return (response); 2064} 2065 2066/**************************************************************************** 2067 * hdac_command_send_internal 2068 * 2069 * Send a command list to the codec via the corb. We queue as much verbs as 2070 * we can and msleep on the codec. When the interrupt get the responses 2071 * back from the rirb, it will wake us up so we can queue the remaining verbs 2072 * if any. 2073 ****************************************************************************/ 2074static void 2075hdac_command_send_internal(struct hdac_softc *sc, 2076 struct hdac_command_list *commands, nid_t cad) 2077{ 2078 struct hdac_codec *codec; 2079 int corbrp; 2080 uint32_t *corb; 2081 uint8_t rirbwp; 2082 int timeout; 2083 int retry = 10; 2084 struct hdac_rirb *rirb_base, *rirb; 2085 nid_t ucad; 2086 uint32_t utag; 2087 2088 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL) 2089 return; 2090 2091 codec = sc->codecs[cad]; 2092 codec->commands = commands; 2093 codec->responses_received = 0; 2094 codec->verbs_sent = 0; 2095 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2096 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2097 2098 do { 2099 if (codec->verbs_sent != commands->num_commands) { 2100 /* Queue as many verbs as possible */ 2101 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2102 bus_dmamap_sync(sc->corb_dma.dma_tag, 2103 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2104 while (codec->verbs_sent != commands->num_commands && 2105 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2106 sc->corb_wp++; 2107 sc->corb_wp %= sc->corb_size; 2108 corb[sc->corb_wp] = 2109 commands->verbs[codec->verbs_sent++]; 2110 } 2111 2112 /* Send the verbs to the codecs */ 2113 bus_dmamap_sync(sc->corb_dma.dma_tag, 2114 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2115 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2116 } 2117 2118 timeout = 1000; 2119 do { 2120 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2121 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2122 BUS_DMASYNC_POSTREAD); 2123 if (sc->rirb_rp != rirbwp) { 2124 do { 2125 sc->rirb_rp++; 2126 sc->rirb_rp %= sc->rirb_size; 2127 rirb = &rirb_base[sc->rirb_rp]; 2128 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2129 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2130 utag = rirb->response >> 26; 2131 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 2132 sc->codecs[ucad] != NULL) { 2133 sc->unsolq[sc->unsolq_wp++] = 2134 (ucad << 16) | 2135 (utag & 0xffff); 2136 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2137 } 2138 } else if (codec->responses_received < commands->num_commands) 2139 codec->commands->responses[codec->responses_received++] = 2140 rirb->response; 2141 } while (sc->rirb_rp != rirbwp); 2142 break; 2143 } 2144 DELAY(10); 2145 } while (--timeout); 2146 } while ((codec->verbs_sent != commands->num_commands || 2147 codec->responses_received != commands->num_commands) && 2148 --retry); 2149 2150 if (retry == 0) 2151 device_printf(sc->dev, 2152 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2153 __func__, commands->num_commands, 2154 codec->verbs_sent, codec->responses_received); 2155 2156 codec->verbs_sent = 0; 2157 2158 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2159 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2160 while (sc->unsolq_rp != sc->unsolq_wp) { 2161 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 2162 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2163 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2164 hdac_unsolicited_handler(sc->codecs[ucad], utag); 2165 } 2166 sc->unsolq_st = HDAC_UNSOLQ_READY; 2167 } 2168} 2169 2170 2171/**************************************************************************** 2172 * Device Methods 2173 ****************************************************************************/ 2174 2175/**************************************************************************** 2176 * int hdac_probe(device_t) 2177 * 2178 * Probe for the presence of an hdac. If none is found, check for a generic 2179 * match using the subclass of the device. 2180 ****************************************************************************/ 2181static int 2182hdac_probe(device_t dev) 2183{ 2184 int i, result; 2185 uint32_t model, class, subclass; 2186 char desc[64]; 2187 2188 model = (uint32_t)pci_get_device(dev) << 16; 2189 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2190 class = pci_get_class(dev); 2191 subclass = pci_get_subclass(dev); 2192 2193 bzero(desc, sizeof(desc)); 2194 result = ENXIO; 2195 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2196 if (hdac_devices[i].model == model) { 2197 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2198 result = BUS_PROBE_DEFAULT; 2199 break; 2200 } 2201 if (HDA_FLAG_MATCH(hdac_devices[i].model, model) && 2202 class == PCIC_MULTIMEDIA && 2203 subclass == PCIS_MULTIMEDIA_HDA) { 2204 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2205 result = BUS_PROBE_GENERIC; 2206 break; 2207 } 2208 } 2209 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2210 subclass == PCIS_MULTIMEDIA_HDA) { 2211 strlcpy(desc, "Generic", sizeof(desc)); 2212 result = BUS_PROBE_GENERIC; 2213 } 2214 if (result != ENXIO) { 2215 strlcat(desc, " High Definition Audio Controller", 2216 sizeof(desc)); 2217 device_set_desc_copy(dev, desc); 2218 } 2219 2220 return (result); 2221} 2222 2223static void * 2224hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2225 struct pcm_channel *c, int dir) 2226{ 2227 struct hdac_devinfo *devinfo = data; 2228 struct hdac_softc *sc = devinfo->codec->sc; 2229 struct hdac_chan *ch; 2230 2231 hdac_lock(sc); 2232 if (dir == PCMDIR_PLAY) { 2233 ch = &sc->play; 2234 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2235 ch->dir = PCMDIR_PLAY; 2236 ch->sid = ++sc->streamcnt; 2237 devinfo->function.audio.playcnt++; 2238 } else { 2239 ch = &sc->rec; 2240 ch->off = devinfo->function.audio.reccnt << 5; 2241 ch->dir = PCMDIR_REC; 2242 ch->sid = ++sc->streamcnt; 2243 devinfo->function.audio.reccnt++; 2244 } 2245 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2246 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2247 ch->pcmrates[0] = 48000; 2248 ch->pcmrates[1] = 0; 2249 } 2250 ch->b = b; 2251 ch->c = c; 2252 ch->devinfo = devinfo; 2253 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2254 ch->blkcnt = sc->chan_blkcnt; 2255 hdac_unlock(sc); 2256 2257 if (hdac_bdl_alloc(ch) != 0) { 2258 ch->blkcnt = 0; 2259 return (NULL); 2260 } 2261 2262 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2263 return (NULL); 2264 2265 hdac_dma_nocache(ch->b->buf); 2266 2267 return (ch); 2268} 2269 2270static int 2271hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2272{ 2273 struct hdac_chan *ch = data; 2274 int i; 2275 2276 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2277 if (format == ch->caps.fmtlist[i]) { 2278 ch->fmt = format; 2279 return (0); 2280 } 2281 } 2282 2283 return (EINVAL); 2284} 2285 2286static int 2287hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2288{ 2289 struct hdac_chan *ch = data; 2290 uint32_t spd = 0; 2291 int i; 2292 2293 for (i = 0; ch->pcmrates[i] != 0; i++) { 2294 spd = ch->pcmrates[i]; 2295 if (spd >= speed) 2296 break; 2297 } 2298 2299 if (spd == 0) 2300 ch->spd = 48000; 2301 else 2302 ch->spd = spd; 2303 2304 return (ch->spd); 2305} 2306 2307static void 2308hdac_stream_setup(struct hdac_chan *ch) 2309{ 2310 struct hdac_softc *sc = ch->devinfo->codec->sc; 2311 int i; 2312 nid_t cad = ch->devinfo->codec->cad; 2313 uint16_t fmt; 2314 2315 /* 2316 * 8bit = 0 2317 * 16bit = 1 2318 * 20bit = 2 2319 * 24bit = 3 2320 * 32bit = 4 2321 */ 2322 fmt = 0; 2323 if (ch->fmt & AFMT_S16_LE) 2324 fmt |= ch->bit16 << 4; 2325 else if (ch->fmt & AFMT_S32_LE) 2326 fmt |= ch->bit32 << 4; 2327 else 2328 fmt |= 1 << 4; 2329 2330 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2331 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2332 fmt |= hda_rate_tab[i].base; 2333 fmt |= hda_rate_tab[i].mul; 2334 fmt |= hda_rate_tab[i].div; 2335 break; 2336 } 2337 } 2338 2339 if (ch->fmt & AFMT_STEREO) 2340 fmt |= 1; 2341 2342 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2343 2344 for (i = 0; ch->io[i] != -1; i++) { 2345 HDA_BOOTVERBOSE_MSG( 2346 device_printf(sc->dev, 2347 "PCMDIR_%s: Stream setup nid=%d fmt=0x%08x\n", 2348 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2349 ch->io[i], fmt); 2350 ); 2351 hdac_command(sc, 2352 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2353 hdac_command(sc, 2354 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2355 ch->sid << 4), cad); 2356 } 2357} 2358 2359static int 2360hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 2361{ 2362 struct hdac_chan *ch = data; 2363 2364 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz); 2365 2366 return (ch->blksz); 2367} 2368 2369static void 2370hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2371{ 2372 struct hdac_devinfo *devinfo = ch->devinfo; 2373 nid_t cad = devinfo->codec->cad; 2374 int i; 2375 2376 hdac_stream_stop(ch); 2377 2378 for (i = 0; ch->io[i] != -1; i++) { 2379 hdac_command(sc, 2380 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2381 0), cad); 2382 } 2383} 2384 2385static void 2386hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2387{ 2388 ch->ptr = 0; 2389 ch->prevptr = 0; 2390 hdac_stream_stop(ch); 2391 hdac_stream_reset(ch); 2392 hdac_bdl_setup(ch); 2393 hdac_stream_setid(ch); 2394 hdac_stream_setup(ch); 2395 hdac_stream_start(ch); 2396} 2397 2398static int 2399hdac_channel_trigger(kobj_t obj, void *data, int go) 2400{ 2401 struct hdac_chan *ch = data; 2402 struct hdac_softc *sc = ch->devinfo->codec->sc; 2403 2404 hdac_lock(sc); 2405 switch (go) { 2406 case PCMTRIG_START: 2407 hdac_channel_start(sc, ch); 2408 break; 2409 case PCMTRIG_STOP: 2410 case PCMTRIG_ABORT: 2411 hdac_channel_stop(sc, ch); 2412 break; 2413 } 2414 hdac_unlock(sc); 2415 2416 return (0); 2417} 2418 2419static int 2420hdac_channel_getptr(kobj_t obj, void *data) 2421{ 2422 struct hdac_chan *ch = data; 2423 struct hdac_softc *sc = ch->devinfo->codec->sc; 2424 int sz, delta; 2425 uint32_t ptr; 2426 2427 hdac_lock(sc); 2428 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2429 hdac_unlock(sc); 2430 2431 sz = sndbuf_getsize(ch->b); 2432 ptr %= sz; 2433 2434 if (ch->dir == PCMDIR_REC) { 2435 delta = ptr % sndbuf_getblksz(ch->b); 2436 if (delta != 0) { 2437 ptr -= delta; 2438 if (ptr < delta) 2439 ptr = sz - delta; 2440 else 2441 ptr -= delta; 2442 } 2443 } 2444 2445 return (ptr); 2446} 2447 2448static struct pcmchan_caps * 2449hdac_channel_getcaps(kobj_t obj, void *data) 2450{ 2451 return (&((struct hdac_chan *)data)->caps); 2452} 2453 2454static kobj_method_t hdac_channel_methods[] = { 2455 KOBJMETHOD(channel_init, hdac_channel_init), 2456 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2457 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2458 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2459 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2460 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2461 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2462 { 0, 0 } 2463}; 2464CHANNEL_DECLARE(hdac_channel); 2465 2466static int 2467hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2468{ 2469 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2470 struct hdac_softc *sc = devinfo->codec->sc; 2471 struct hdac_widget *w, *cw; 2472 struct hdac_audio_ctl *ctl; 2473 uint32_t mask, recmask, id; 2474 int i, j, softpcmvol; 2475 nid_t cad; 2476 2477 if (resource_int_value(device_get_name(sc->dev), 2478 device_get_unit(sc->dev), "softpcmvol", &softpcmvol) == 0) 2479 softpcmvol = (softpcmvol != 0) ? 1 : 0; 2480 else 2481 softpcmvol = (devinfo->function.audio.quirks & 2482 HDA_QUIRK_SOFTPCMVOL) ? 2483 1 : 0; 2484 2485 hdac_lock(sc); 2486 2487 mask = 0; 2488 recmask = 0; 2489 2490 id = hdac_codec_id(devinfo); 2491 cad = devinfo->codec->cad; 2492 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2493 if (!(HDA_FLAG_MATCH(hdac_hp_switch[i].model, 2494 sc->pci_subvendor) && 2495 hdac_hp_switch[i].id == id)) 2496 continue; 2497 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2498 if (w != NULL && w->enable != 0 2499 && w->type == 2500 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2501 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2502 hdac_command(sc, 2503 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2504 w->nid, 2505 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2506 HDAC_UNSOLTAG_EVENT_HP), cad); 2507 hdac_hp_switch_handler(devinfo); 2508 } 2509 break; 2510 } 2511 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2512 if (!(HDA_FLAG_MATCH(hdac_eapd_switch[i].model, 2513 sc->pci_subvendor) && 2514 hdac_eapd_switch[i].id == id)) 2515 continue; 2516 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2517 if (w == NULL || w->enable == 0) 2518 break; 2519 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2520 w->param.eapdbtl == HDAC_INVALID) 2521 break; 2522 mask |= SOUND_MASK_OGAIN; 2523 break; 2524 } 2525 2526 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2527 w = hdac_widget_get(devinfo, i); 2528 if (w == NULL || w->enable == 0) 2529 continue; 2530 mask |= w->ctlflags; 2531 if (!(w->pflags & HDA_ADC_RECSEL)) 2532 continue; 2533 for (j = 0; j < w->nconns; j++) { 2534 cw = hdac_widget_get(devinfo, w->conns[j]); 2535 if (cw == NULL || cw->enable == 0) 2536 continue; 2537 recmask |= cw->ctlflags; 2538 } 2539 } 2540 2541 if (!(mask & SOUND_MASK_PCM)) { 2542 softpcmvol = 1; 2543 mask |= SOUND_MASK_PCM; 2544 } 2545 2546 i = 0; 2547 ctl = NULL; 2548 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2549 if (ctl->widget == NULL || ctl->enable == 0) 2550 continue; 2551 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2552 continue; 2553 if (ctl->step > 0) 2554 break; 2555 } 2556 2557 if (softpcmvol == 1 || ctl == NULL) { 2558 struct snddev_info *d = NULL; 2559 d = device_get_softc(sc->dev); 2560 if (d != NULL) { 2561 d->flags |= SD_F_SOFTPCMVOL; 2562 HDA_BOOTVERBOSE_MSG( 2563 device_printf(sc->dev, 2564 "%s Soft PCM volume\n", 2565 (softpcmvol == 1) ? 2566 "Forcing" : "Enabling"); 2567 ); 2568 } 2569 i = 0; 2570 /* 2571 * XXX Temporary quirk for STAC9220, until the parser 2572 * become smarter. 2573 */ 2574 if (id == HDA_CODEC_STAC9220) { 2575 mask |= SOUND_MASK_VOLUME; 2576 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2577 NULL) { 2578 if (ctl->widget == NULL || ctl->enable == 0) 2579 continue; 2580 if (ctl->widget->nid == 11 && ctl->index == 0) { 2581 ctl->ossmask = SOUND_MASK_VOLUME; 2582 ctl->ossval = 100 | (100 << 8); 2583 } else 2584 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2585 } 2586 } else { 2587 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2588 SOUND_MASK_PCM); 2589 if (!(mask & SOUND_MASK_VOLUME)) 2590 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2591 SOUND_MIXER_NONE); 2592 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2593 NULL) { 2594 if (ctl->widget == NULL || ctl->enable == 0) 2595 continue; 2596 if ((ctl->ossmask & (SOUND_MASK_VOLUME | 2597 SOUND_MASK_PCM)) != (SOUND_MASK_VOLUME | 2598 SOUND_MASK_PCM)) 2599 continue; 2600 if (!(ctl->mute == 1 && ctl->step == 0)) 2601 ctl->enable = 0; 2602 } 2603 } 2604 } 2605 2606 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2607 2608 mix_setrecdevs(m, recmask); 2609 mix_setdevs(m, mask); 2610 2611 hdac_unlock(sc); 2612 2613 return (0); 2614} 2615 2616static int 2617hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2618 unsigned left, unsigned right) 2619{ 2620 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2621 struct hdac_softc *sc = devinfo->codec->sc; 2622 struct hdac_widget *w; 2623 struct hdac_audio_ctl *ctl; 2624 uint32_t id, mute; 2625 int lvol, rvol, mlvol, mrvol; 2626 int i = 0; 2627 2628 hdac_lock(sc); 2629 if (dev == SOUND_MIXER_OGAIN) { 2630 /*if (left != right || !(left == 0 || left == 1)) { 2631 hdac_unlock(sc); 2632 return (-1); 2633 }*/ 2634 id = hdac_codec_id(devinfo); 2635 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2636 if (HDA_FLAG_MATCH(hdac_eapd_switch[i].model, 2637 sc->pci_subvendor) && 2638 hdac_eapd_switch[i].id == id) 2639 break; 2640 } 2641 if (i >= HDAC_EAPD_SWITCH_LEN) { 2642 hdac_unlock(sc); 2643 return (-1); 2644 } 2645 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2646 if (w == NULL || 2647 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2648 w->param.eapdbtl == HDAC_INVALID) { 2649 hdac_unlock(sc); 2650 return (-1); 2651 } 2652 if (left == 0) 2653 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2654 else 2655 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2656 if (hdac_eapd_switch[i].hp_switch != 0) 2657 hdac_hp_switch_handler(devinfo); 2658 hdac_command(sc, 2659 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, w->nid, 2660 w->param.eapdbtl), devinfo->codec->cad); 2661 hdac_unlock(sc); 2662 return (left | (left << 8)); 2663 } 2664 if (dev == SOUND_MIXER_VOLUME) 2665 devinfo->function.audio.mvol = left | (right << 8); 2666 2667 mlvol = devinfo->function.audio.mvol & 0x7f; 2668 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2669 lvol = 0; 2670 rvol = 0; 2671 2672 i = 0; 2673 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2674 if (ctl->widget == NULL || ctl->enable == 0 || 2675 !(ctl->ossmask & (1 << dev))) 2676 continue; 2677 switch (dev) { 2678 case SOUND_MIXER_VOLUME: 2679 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2680 lvol = (lvol * ctl->step) / 100; 2681 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2682 rvol = (rvol * ctl->step) / 100; 2683 break; 2684 default: 2685 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2686 lvol = (left * mlvol) / 100; 2687 lvol = (lvol * ctl->step) / 100; 2688 rvol = (right * mrvol) / 100; 2689 rvol = (rvol * ctl->step) / 100; 2690 } else { 2691 lvol = (left * ctl->step) / 100; 2692 rvol = (right * ctl->step) / 100; 2693 } 2694 ctl->ossval = left | (right << 8); 2695 break; 2696 } 2697 mute = 0; 2698 if (ctl->step < 1) { 2699 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2700 (ctl->muted & HDA_AMP_MUTE_LEFT); 2701 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2702 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2703 } else { 2704 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2705 (ctl->muted & HDA_AMP_MUTE_LEFT); 2706 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2707 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2708 } 2709 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2710 } 2711 hdac_unlock(sc); 2712 2713 return (left | (right << 8)); 2714} 2715 2716static int 2717hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2718{ 2719 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2720 struct hdac_widget *w, *cw; 2721 struct hdac_softc *sc = devinfo->codec->sc; 2722 uint32_t ret = src, target; 2723 int i, j; 2724 2725 target = 0; 2726 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2727 if (src & (1 << i)) { 2728 target = 1 << i; 2729 break; 2730 } 2731 } 2732 2733 hdac_lock(sc); 2734 2735 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2736 w = hdac_widget_get(devinfo, i); 2737 if (w == NULL || w->enable == 0) 2738 continue; 2739 if (!(w->pflags & HDA_ADC_RECSEL)) 2740 continue; 2741 for (j = 0; j < w->nconns; j++) { 2742 cw = hdac_widget_get(devinfo, w->conns[j]); 2743 if (cw == NULL || cw->enable == 0) 2744 continue; 2745 if ((target == SOUND_MASK_VOLUME && 2746 cw->type != 2747 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 2748 (target != SOUND_MASK_VOLUME && 2749 cw->type == 2750 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 2751 continue; 2752 if (cw->ctlflags & target) { 2753 hdac_widget_connection_select(w, j); 2754 ret = target; 2755 j += w->nconns; 2756 } 2757 } 2758 } 2759 2760 hdac_unlock(sc); 2761 2762 return (ret); 2763} 2764 2765static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 2766 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 2767 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 2768 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 2769 { 0, 0 } 2770}; 2771MIXER_DECLARE(hdac_audio_ctl_ossmixer); 2772 2773/**************************************************************************** 2774 * int hdac_attach(device_t) 2775 * 2776 * Attach the device into the kernel. Interrupts usually won't be enabled 2777 * when this function is called. Setup everything that doesn't require 2778 * interrupts and defer probing of codecs until interrupts are enabled. 2779 ****************************************************************************/ 2780static int 2781hdac_attach(device_t dev) 2782{ 2783 struct hdac_softc *sc; 2784 int result; 2785 int i = 0; 2786 2787 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 2788 if (sc == NULL) { 2789 device_printf(dev, "cannot allocate softc\n"); 2790 return (ENOMEM); 2791 } 2792 sc->dev = dev; 2793 sc->pci_subvendor = pci_get_subdevice(sc->dev) << 16; 2794 sc->pci_subvendor |= pci_get_subvendor(sc->dev); 2795 2796 sc->chan_size = pcm_getbuffersize(dev, 2797 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT); 2798 if (resource_int_value(device_get_name(sc->dev), 2799 device_get_unit(sc->dev), "blocksize", &i) == 0 && 2800 i > 0) { 2801 sc->chan_blkcnt = sc->chan_size / i; 2802 i = 0; 2803 while (sc->chan_blkcnt >> i) 2804 i++; 2805 sc->chan_blkcnt = 1 << (i - 1); 2806 if (sc->chan_blkcnt < HDA_BDL_MIN) 2807 sc->chan_blkcnt = HDA_BDL_MIN; 2808 else if (sc->chan_blkcnt > HDA_BDL_MAX) 2809 sc->chan_blkcnt = HDA_BDL_MAX; 2810 } else 2811 sc->chan_blkcnt = HDA_BDL_DEFAULT; 2812 2813 result = bus_dma_tag_create(NULL, /* parent */ 2814 HDAC_DMA_ALIGNMENT, /* alignment */ 2815 0, /* boundary */ 2816 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2817 BUS_SPACE_MAXADDR, /* highaddr */ 2818 NULL, /* filtfunc */ 2819 NULL, /* fistfuncarg */ 2820 sc->chan_size, /* maxsize */ 2821 1, /* nsegments */ 2822 sc->chan_size, /* maxsegsz */ 2823 0, /* flags */ 2824 NULL, /* lockfunc */ 2825 NULL, /* lockfuncarg */ 2826 &sc->chan_dmat); /* dmat */ 2827 if (result != 0) { 2828 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 2829 __func__, result); 2830 free(sc, M_DEVBUF); 2831 return (ENXIO); 2832 } 2833 2834 2835 sc->hdabus = NULL; 2836 for (i = 0; i < HDAC_CODEC_MAX; i++) 2837 sc->codecs[i] = NULL; 2838 2839 pci_enable_busmaster(dev); 2840 2841 /* Initialize driver mutex */ 2842 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 2843 2844 /* Allocate resources */ 2845 result = hdac_mem_alloc(sc); 2846 if (result != 0) 2847 goto fail; 2848 result = hdac_irq_alloc(sc); 2849 if (result != 0) 2850 goto fail; 2851 2852 /* Get Capabilities */ 2853 result = hdac_get_capabilities(sc); 2854 if (result != 0) 2855 goto fail; 2856 2857 /* Allocate CORB and RIRB dma memory */ 2858 result = hdac_dma_alloc(sc, &sc->corb_dma, 2859 sc->corb_size * sizeof(uint32_t)); 2860 if (result != 0) 2861 goto fail; 2862 result = hdac_dma_alloc(sc, &sc->rirb_dma, 2863 sc->rirb_size * sizeof(struct hdac_rirb)); 2864 if (result != 0) 2865 goto fail; 2866 2867 /* Quiesce everything */ 2868 hdac_reset(sc); 2869 2870 /* Disable PCI-Express QOS */ 2871 pci_write_config(sc->dev, 0x44, 2872 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 2873 2874 /* Initialize the CORB and RIRB */ 2875 hdac_corb_init(sc); 2876 hdac_rirb_init(sc); 2877 2878 /* Defer remaining of initialization until interrupts are enabled */ 2879 sc->intrhook.ich_func = hdac_attach2; 2880 sc->intrhook.ich_arg = (void *)sc; 2881 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 2882 sc->intrhook.ich_func = NULL; 2883 hdac_attach2((void *)sc); 2884 } 2885 2886 return(0); 2887 2888fail: 2889 hdac_dma_free(&sc->rirb_dma); 2890 hdac_dma_free(&sc->corb_dma); 2891 hdac_irq_free(sc); 2892 hdac_mem_free(sc); 2893 snd_mtxfree(sc->lock); 2894 2895 return(ENXIO); 2896} 2897 2898static void 2899hdac_audio_parse(struct hdac_devinfo *devinfo) 2900{ 2901 struct hdac_softc *sc = devinfo->codec->sc; 2902 struct hdac_widget *w; 2903 uint32_t res; 2904 int i; 2905 nid_t cad, nid; 2906 2907 cad = devinfo->codec->cad; 2908 nid = devinfo->nid; 2909 2910 hdac_command(sc, 2911 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 2912 2913 DELAY(100); 2914 2915 res = hdac_command(sc, 2916 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2917 2918 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2919 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2920 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2921 2922 HDA_BOOTVERBOSE_MSG( 2923 device_printf(sc->dev, " Vendor: 0x%08x\n", 2924 devinfo->vendor_id); 2925 device_printf(sc->dev, " Device: 0x%08x\n", 2926 devinfo->device_id); 2927 device_printf(sc->dev, " Revision: 0x%08x\n", 2928 devinfo->revision_id); 2929 device_printf(sc->dev, " Stepping: 0x%08x\n", 2930 devinfo->stepping_id); 2931 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2932 sc->pci_subvendor); 2933 device_printf(sc->dev, " Nodes: start=%d " 2934 "endnode=%d total=%d\n", 2935 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 2936 ); 2937 2938 res = hdac_command(sc, 2939 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 2940 cad); 2941 devinfo->function.audio.supp_stream_formats = res; 2942 2943 res = hdac_command(sc, 2944 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 2945 cad); 2946 devinfo->function.audio.supp_pcm_size_rate = res; 2947 2948 res = hdac_command(sc, 2949 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 2950 cad); 2951 devinfo->function.audio.outamp_cap = res; 2952 2953 res = hdac_command(sc, 2954 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 2955 cad); 2956 devinfo->function.audio.inamp_cap = res; 2957 2958 if (devinfo->nodecnt > 0) { 2959 hdac_unlock(sc); 2960 devinfo->widget = (struct hdac_widget *)malloc( 2961 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2962 M_NOWAIT | M_ZERO); 2963 hdac_lock(sc); 2964 } else 2965 devinfo->widget = NULL; 2966 2967 if (devinfo->widget == NULL) { 2968 device_printf(sc->dev, "unable to allocate widgets!\n"); 2969 devinfo->endnode = devinfo->startnode; 2970 devinfo->nodecnt = 0; 2971 return; 2972 } 2973 2974 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2975 w = hdac_widget_get(devinfo, i); 2976 if (w == NULL) 2977 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 2978 else { 2979 w->devinfo = devinfo; 2980 w->nid = i; 2981 w->enable = 1; 2982 w->selconn = -1; 2983 w->pflags = 0; 2984 w->ctlflags = 0; 2985 w->param.eapdbtl = HDAC_INVALID; 2986 hdac_widget_parse(w); 2987 } 2988 } 2989} 2990 2991static void 2992hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 2993{ 2994 struct hdac_softc *sc = devinfo->codec->sc; 2995 struct hdac_audio_ctl *ctls; 2996 struct hdac_widget *w, *cw; 2997 int i, j, cnt, max, ocap, icap; 2998 2999 /* XXX This is redundant */ 3000 max = 0; 3001 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3002 w = hdac_widget_get(devinfo, i); 3003 if (w == NULL || w->enable == 0) 3004 continue; 3005 if (w->param.outamp_cap != 0) 3006 max++; 3007 if (w->param.inamp_cap != 0) { 3008 switch (w->type) { 3009 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3010 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3011 for (j = 0; j < w->nconns; j++) { 3012 cw = hdac_widget_get(devinfo, 3013 w->conns[j]); 3014 if (cw == NULL || cw->enable == 0) 3015 continue; 3016 max++; 3017 } 3018 break; 3019 default: 3020 max++; 3021 break; 3022 } 3023 } 3024 } 3025 3026 devinfo->function.audio.ctlcnt = max; 3027 3028 if (max < 1) 3029 return; 3030 3031 hdac_unlock(sc); 3032 ctls = (struct hdac_audio_ctl *)malloc( 3033 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3034 hdac_lock(sc); 3035 3036 if (ctls == NULL) { 3037 /* Blekh! */ 3038 device_printf(sc->dev, "unable to allocate ctls!\n"); 3039 devinfo->function.audio.ctlcnt = 0; 3040 return; 3041 } 3042 3043 cnt = 0; 3044 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3045 if (cnt >= max) { 3046 device_printf(sc->dev, "%s: Ctl overflow!\n", 3047 __func__); 3048 break; 3049 } 3050 w = hdac_widget_get(devinfo, i); 3051 if (w == NULL || w->enable == 0) 3052 continue; 3053 ocap = w->param.outamp_cap; 3054 icap = w->param.inamp_cap; 3055 if (ocap != 0) { 3056 ctls[cnt].enable = 1; 3057 ctls[cnt].widget = w; 3058 ctls[cnt].mute = 3059 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3060 ctls[cnt].step = 3061 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3062 ctls[cnt].size = 3063 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3064 ctls[cnt].offset = 3065 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3066 ctls[cnt].left = ctls[cnt].offset; 3067 ctls[cnt].right = ctls[cnt].offset; 3068 ctls[cnt++].dir = HDA_CTL_OUT; 3069 } 3070 3071 if (icap != 0) { 3072 switch (w->type) { 3073 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3074 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3075 for (j = 0; j < w->nconns; j++) { 3076 if (cnt >= max) { 3077 device_printf(sc->dev, 3078 "%s: Ctl overflow!\n", 3079 __func__); 3080 break; 3081 } 3082 cw = hdac_widget_get(devinfo, 3083 w->conns[j]); 3084 if (cw == NULL || cw->enable == 0) 3085 continue; 3086 ctls[cnt].enable = 1; 3087 ctls[cnt].widget = w; 3088 ctls[cnt].childwidget = cw; 3089 ctls[cnt].index = j; 3090 ctls[cnt].mute = 3091 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(icap); 3092 ctls[cnt].step = 3093 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(icap); 3094 ctls[cnt].size = 3095 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(icap); 3096 ctls[cnt].offset = 3097 HDA_PARAM_INPUT_AMP_CAP_OFFSET(icap); 3098 ctls[cnt].left = ctls[cnt].offset; 3099 ctls[cnt].right = ctls[cnt].offset; 3100 ctls[cnt++].dir = HDA_CTL_IN; 3101 } 3102 break; 3103 default: 3104 if (cnt >= max) { 3105 device_printf(sc->dev, 3106 "%s: Ctl overflow!\n", 3107 __func__); 3108 break; 3109 } 3110 ctls[cnt].enable = 1; 3111 ctls[cnt].widget = w; 3112 ctls[cnt].mute = 3113 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(icap); 3114 ctls[cnt].step = 3115 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(icap); 3116 ctls[cnt].size = 3117 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(icap); 3118 ctls[cnt].offset = 3119 HDA_PARAM_INPUT_AMP_CAP_OFFSET(icap); 3120 ctls[cnt].left = ctls[cnt].offset; 3121 ctls[cnt].right = ctls[cnt].offset; 3122 ctls[cnt++].dir = HDA_CTL_IN; 3123 break; 3124 } 3125 } 3126 } 3127 3128 devinfo->function.audio.ctl = ctls; 3129} 3130 3131static const struct { 3132 uint32_t model; 3133 uint32_t id; 3134 uint32_t set, unset; 3135} hdac_quirks[] = { 3136 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3137 HDA_QUIRK_GPIO1, 0 }, 3138 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3139 HDA_QUIRK_GPIO1, 0 }, 3140 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3141 0, HDA_QUIRK_FORCESTEREO }, 3142 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3143 HDA_QUIRK_SOFTPCMVOL, 0 } 3144}; 3145#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3146 3147static void 3148hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3149{ 3150 struct hdac_widget *w; 3151 uint32_t id, subvendor; 3152 int i; 3153 3154 /* 3155 * XXX Fixed rate quirk. Other than 48000 3156 * sounds pretty much like train wreck. 3157 */ 3158 devinfo->function.audio.quirks |= HDA_QUIRK_FIXEDRATE; 3159 /* 3160 * XXX Force stereo quirk. Monoural recording / playback 3161 * on few codecs (especially ALC880) seems broken or 3162 * or perhaps unsupported. 3163 */ 3164 devinfo->function.audio.quirks |= HDA_QUIRK_FORCESTEREO; 3165 id = hdac_codec_id(devinfo); 3166 subvendor = devinfo->codec->sc->pci_subvendor; 3167 switch (id) { 3168 case HDA_CODEC_ALC260: 3169 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3170 w = hdac_widget_get(devinfo, i); 3171 if (w == NULL || w->enable == 0) 3172 continue; 3173 if (w->type != 3174 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3175 continue; 3176 if (w->nid != 5) 3177 w->enable = 0; 3178 } 3179 break; 3180 case HDA_CODEC_ALC880: 3181 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3182 w = hdac_widget_get(devinfo, i); 3183 if (w == NULL || w->enable == 0) 3184 continue; 3185 if (w->type == 3186 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3187 w->nid != 9 && w->nid != 29) { 3188 w->enable = 0; 3189 } else if (w->type != 3190 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3191 w->nid == 29) { 3192 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3193 w->param.widget_cap &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3194 w->param.widget_cap |= 3195 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3196 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3197 strlcpy(w->name, "beep widget", sizeof(w->name)); 3198 } 3199 } 3200 break; 3201 case HDA_CODEC_AD1986A: 3202 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3203 w = hdac_widget_get(devinfo, i); 3204 if (w == NULL || w->enable == 0) 3205 continue; 3206 if (w->type != 3207 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3208 continue; 3209 if (w->nid != 3) 3210 w->enable = 0; 3211 } 3212 break; 3213 case HDA_CODEC_STAC9221: 3214 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3215 w = hdac_widget_get(devinfo, i); 3216 if (w == NULL || w->enable == 0) 3217 continue; 3218 if (w->type != 3219 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3220 continue; 3221 if (w->nid != 2) 3222 w->enable = 0; 3223 } 3224 break; 3225 case HDA_CODEC_STAC9221D: 3226 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3227 w = hdac_widget_get(devinfo, i); 3228 if (w == NULL || w->enable == 0) 3229 continue; 3230 if (w->type == 3231 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3232 w->nid != 6) 3233 w->enable = 0; 3234 3235 } 3236 break; 3237 default: 3238 break; 3239 } 3240 3241 /* 3242 * Quirks 3243 */ 3244 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3245 if (!(HDA_FLAG_MATCH(hdac_quirks[i].model, subvendor) && 3246 HDA_FLAG_MATCH(hdac_quirks[i].id, id))) 3247 continue; 3248 if (hdac_quirks[i].set != 0) 3249 devinfo->function.audio.quirks |= 3250 hdac_quirks[i].set; 3251 if (hdac_quirks[i].unset != 0) 3252 devinfo->function.audio.quirks &= 3253 ~(hdac_quirks[i].unset); 3254 break; 3255 } 3256} 3257 3258static int 3259hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3260{ 3261 int *dev = &devinfo->function.audio.ossidx; 3262 3263 while (*dev < SOUND_MIXER_NRDEVICES) { 3264 switch (*dev) { 3265 case SOUND_MIXER_VOLUME: 3266 case SOUND_MIXER_BASS: 3267 case SOUND_MIXER_TREBLE: 3268 case SOUND_MIXER_PCM: 3269 case SOUND_MIXER_SPEAKER: 3270 case SOUND_MIXER_LINE: 3271 case SOUND_MIXER_MIC: 3272 case SOUND_MIXER_CD: 3273 case SOUND_MIXER_RECLEV: 3274 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3275 (*dev)++; 3276 break; 3277 default: 3278 return (*dev)++; 3279 break; 3280 } 3281 } 3282 3283 return (-1); 3284} 3285 3286static int 3287hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3288{ 3289 struct hdac_widget *w; 3290 int i, ret = 0; 3291 3292 if (depth > HDA_PARSE_MAXDEPTH) 3293 return (0); 3294 w = hdac_widget_get(devinfo, nid); 3295 if (w == NULL || w->enable == 0) 3296 return (0); 3297 switch (w->type) { 3298 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3299 w->pflags |= HDA_DAC_PATH; 3300 ret = 1; 3301 break; 3302 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3303 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3304 for (i = 0; i < w->nconns; i++) { 3305 if (hdac_widget_find_dac_path(devinfo, 3306 w->conns[i], depth + 1) != 0) { 3307 if (w->selconn == -1) 3308 w->selconn = i; 3309 ret = 1; 3310 w->pflags |= HDA_DAC_PATH; 3311 } 3312 } 3313 break; 3314 default: 3315 break; 3316 } 3317 return (ret); 3318} 3319 3320static int 3321hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3322{ 3323 struct hdac_widget *w; 3324 int i, conndev, ret = 0; 3325 3326 if (depth > HDA_PARSE_MAXDEPTH) 3327 return (0); 3328 w = hdac_widget_get(devinfo, nid); 3329 if (w == NULL || w->enable == 0) 3330 return (0); 3331 switch (w->type) { 3332 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3333 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3334 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3335 for (i = 0; i < w->nconns; i++) { 3336 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3337 depth + 1) != 0) { 3338 if (w->selconn == -1) 3339 w->selconn = i; 3340 w->pflags |= HDA_ADC_PATH; 3341 ret = 1; 3342 } 3343 } 3344 break; 3345 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3346 conndev = w->wclass.pin.config & 3347 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3348 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3349 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3350 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3351 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3352 w->pflags |= HDA_ADC_PATH; 3353 ret = 1; 3354 } 3355 break; 3356 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3357 if (w->pflags & HDA_DAC_PATH) { 3358 w->pflags |= HDA_ADC_PATH; 3359 ret = 1; 3360 } 3361 break;*/ 3362 default: 3363 break; 3364 } 3365 return (ret); 3366} 3367 3368static uint32_t 3369hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3370 nid_t nid, nid_t pnid, int index, int depth) 3371{ 3372 struct hdac_widget *w, *pw; 3373 struct hdac_audio_ctl *ctl; 3374 uint32_t fl = 0; 3375 int i, ossdev, conndev, strategy; 3376 3377 if (depth > HDA_PARSE_MAXDEPTH) 3378 return (0); 3379 3380 w = hdac_widget_get(devinfo, nid); 3381 if (w == NULL || w->enable == 0) 3382 return (0); 3383 3384 pw = hdac_widget_get(devinfo, pnid); 3385 strategy = devinfo->function.audio.parsing_strategy; 3386 3387 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3388 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3389 for (i = 0; i < w->nconns; i++) { 3390 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3391 w->nid, i, depth + 1); 3392 } 3393 w->ctlflags |= fl; 3394 return (fl); 3395 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3396 (w->pflags & HDA_DAC_PATH)) { 3397 i = 0; 3398 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3399 if (ctl->enable == 0 || ctl->widget == NULL) 3400 continue; 3401 if ((ctl->widget->nid == w->nid) || 3402 (ctl->widget->nid == pnid && ctl->index == index && 3403 (ctl->dir & HDA_CTL_IN)) || 3404 (ctl->widget->nid == pnid && pw != NULL && 3405 pw->type == 3406 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3407 (pw->nconns < 2 || pw->selconn == index || 3408 pw->selconn == -1) && 3409 (ctl->dir & HDA_CTL_OUT)) || 3410 (strategy == HDA_PARSE_DIRECT && 3411 ctl->widget->nid == w->nid)) { 3412 if (pw != NULL && pw->selconn == -1) 3413 pw->selconn = index; 3414 fl |= SOUND_MASK_VOLUME; 3415 fl |= SOUND_MASK_PCM; 3416 ctl->ossmask |= SOUND_MASK_VOLUME; 3417 ctl->ossmask |= SOUND_MASK_PCM; 3418 ctl->ossdev = SOUND_MIXER_PCM; 3419 } 3420 } 3421 w->ctlflags |= fl; 3422 return (fl); 3423 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 3424 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3425 (w->pflags & HDA_ADC_PATH)) { 3426 conndev = w->wclass.pin.config & 3427 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3428 i = 0; 3429 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3430 if (ctl->enable == 0 || ctl->widget == NULL) 3431 continue; 3432 if (((ctl->widget->nid == pnid && ctl->index == index && 3433 (ctl->dir & HDA_CTL_IN)) || 3434 (ctl->widget->nid == pnid && pw != NULL && 3435 pw->type == 3436 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3437 (pw->nconns < 2 || pw->selconn == index || 3438 pw->selconn == -1) && 3439 (ctl->dir & HDA_CTL_OUT)) || 3440 (strategy == HDA_PARSE_DIRECT && 3441 ctl->widget->nid == w->nid)) && 3442 (ctl->ossmask & ~SOUND_MASK_VOLUME) == 0) { 3443 if (pw != NULL && pw->selconn == -1) 3444 pw->selconn = index; 3445 ossdev = 0; 3446 switch (conndev) { 3447 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3448 ossdev = SOUND_MIXER_MIC; 3449 break; 3450 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3451 ossdev = SOUND_MIXER_LINE; 3452 break; 3453 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3454 ossdev = SOUND_MIXER_CD; 3455 break; 3456 default: 3457 ossdev = 3458 hdac_audio_ctl_ossmixer_getnextdev( 3459 devinfo); 3460 if (ossdev < 0) 3461 ossdev = 0; 3462 break; 3463 } 3464 if (strategy == HDA_PARSE_MIXER) { 3465 fl |= SOUND_MASK_VOLUME; 3466 ctl->ossmask |= SOUND_MASK_VOLUME; 3467 } 3468 fl |= 1 << ossdev; 3469 ctl->ossmask |= 1 << ossdev; 3470 ctl->ossdev = ossdev; 3471 } 3472 } 3473 w->ctlflags |= fl; 3474 return (fl); 3475 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3476 i = 0; 3477 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3478 if (ctl->enable == 0 || ctl->widget == NULL) 3479 continue; 3480 if (((ctl->widget->nid == pnid && ctl->index == index && 3481 (ctl->dir & HDA_CTL_IN)) || 3482 (ctl->widget->nid == pnid && pw != NULL && 3483 pw->type == 3484 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3485 (pw->nconns < 2 || pw->selconn == index || 3486 pw->selconn == -1) && 3487 (ctl->dir & HDA_CTL_OUT)) || 3488 (strategy == HDA_PARSE_DIRECT && 3489 ctl->widget->nid == w->nid)) && 3490 (ctl->ossmask & ~SOUND_MASK_VOLUME) == 0) { 3491 if (pw != NULL && pw->selconn == -1) 3492 pw->selconn = index; 3493 fl |= SOUND_MASK_VOLUME; 3494 fl |= SOUND_MASK_SPEAKER; 3495 ctl->ossmask |= SOUND_MASK_VOLUME; 3496 ctl->ossmask |= SOUND_MASK_SPEAKER; 3497 ctl->ossdev = SOUND_MIXER_SPEAKER; 3498 } 3499 } 3500 w->ctlflags |= fl; 3501 return (fl); 3502 } 3503 return (0); 3504} 3505 3506static uint32_t 3507hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3508{ 3509 struct hdac_widget *w, *cw; 3510 struct hdac_audio_ctl *ctl; 3511 uint32_t fl; 3512 int i; 3513 3514 if (depth > HDA_PARSE_MAXDEPTH) 3515 return (0); 3516 3517 w = hdac_widget_get(devinfo, nid); 3518 if (w == NULL || w->enable == 0) 3519 return (0); 3520 /*if (!(w->pflags & HDA_ADC_PATH)) 3521 return (0); 3522 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3523 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3524 return (0);*/ 3525 i = 0; 3526 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3527 if (ctl->enable == 0 || ctl->widget == NULL) 3528 continue; 3529 if (ctl->widget->nid == nid) { 3530 ctl->ossmask |= SOUND_MASK_RECLEV; 3531 w->ctlflags |= SOUND_MASK_RECLEV; 3532 return (SOUND_MASK_RECLEV); 3533 } 3534 } 3535 for (i = 0; i < w->nconns; i++) { 3536 cw = hdac_widget_get(devinfo, w->conns[i]); 3537 if (cw == NULL || cw->enable == 0) 3538 continue; 3539 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3540 continue; 3541 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3542 if (fl != 0) { 3543 cw->ctlflags |= fl; 3544 w->ctlflags |= fl; 3545 return (fl); 3546 } 3547 } 3548 return (0); 3549} 3550 3551static int 3552hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3553{ 3554 struct hdac_widget *w, *cw; 3555 int i, child = 0; 3556 3557 if (depth > HDA_PARSE_MAXDEPTH) 3558 return (0); 3559 3560 w = hdac_widget_get(devinfo, nid); 3561 if (w == NULL || w->enable == 0) 3562 return (0); 3563 /*if (!(w->pflags & HDA_ADC_PATH)) 3564 return (0); 3565 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3566 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3567 return (0);*/ 3568 /* XXX weak! */ 3569 for (i = 0; i < w->nconns; i++) { 3570 cw = hdac_widget_get(devinfo, w->conns[i]); 3571 if (cw == NULL) 3572 continue; 3573 if (++child > 1) { 3574 w->pflags |= HDA_ADC_RECSEL; 3575 return (1); 3576 } 3577 } 3578 for (i = 0; i < w->nconns; i++) { 3579 if (hdac_audio_ctl_recsel_build(devinfo, 3580 w->conns[i], depth + 1) != 0) 3581 return (1); 3582 } 3583 return (0); 3584} 3585 3586static int 3587hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3588{ 3589 struct hdac_widget *w, *cw; 3590 int i, j, conndev, found_dac = 0; 3591 int strategy; 3592 3593 strategy = devinfo->function.audio.parsing_strategy; 3594 3595 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3596 w = hdac_widget_get(devinfo, i); 3597 if (w == NULL || w->enable == 0) 3598 continue; 3599 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3600 continue; 3601 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3602 continue; 3603 conndev = w->wclass.pin.config & 3604 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3605 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3606 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3607 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3608 continue; 3609 for (j = 0; j < w->nconns; j++) { 3610 cw = hdac_widget_get(devinfo, w->conns[j]); 3611 if (cw == NULL || cw->enable == 0) 3612 continue; 3613 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3614 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3615 cw->type == 3616 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3617 continue; 3618 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3619 != 0) { 3620 if (w->selconn == -1) 3621 w->selconn = j; 3622 w->pflags |= HDA_DAC_PATH; 3623 found_dac++; 3624 } 3625 } 3626 } 3627 3628 return (found_dac); 3629} 3630 3631static void 3632hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3633{ 3634 struct hdac_widget *w; 3635 struct hdac_audio_ctl *ctl; 3636 int i, j, dacs, strategy; 3637 3638 /* Construct DAC path */ 3639 strategy = HDA_PARSE_MIXER; 3640 devinfo->function.audio.parsing_strategy = strategy; 3641 HDA_BOOTVERBOSE_MSG( 3642 device_printf(devinfo->codec->sc->dev, 3643 "HWiP: HDA Widget Parser - Revision %d\n", 3644 HDA_WIDGET_PARSER_REV); 3645 ); 3646 dacs = hdac_audio_build_tree_strategy(devinfo); 3647 if (dacs == 0) { 3648 HDA_BOOTVERBOSE_MSG( 3649 device_printf(devinfo->codec->sc->dev, 3650 "HWiP: 0 DAC found! Retrying parser " 3651 "using HDA_PARSE_DIRECT strategy.\n"); 3652 ); 3653 strategy = HDA_PARSE_DIRECT; 3654 devinfo->function.audio.parsing_strategy = strategy; 3655 dacs = hdac_audio_build_tree_strategy(devinfo); 3656 } 3657 3658 HDA_BOOTVERBOSE_MSG( 3659 device_printf(devinfo->codec->sc->dev, 3660 "HWiP: Found %d DAC(s) using HDA_PARSE_%s strategy.\n", 3661 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 3662 ); 3663 3664 /* Construct ADC path */ 3665 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3666 w = hdac_widget_get(devinfo, i); 3667 if (w == NULL || w->enable == 0) 3668 continue; 3669 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3670 continue; 3671 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 3672 } 3673 3674 /* Output mixers */ 3675 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3676 w = hdac_widget_get(devinfo, i); 3677 if (w == NULL || w->enable == 0) 3678 continue; 3679 if ((strategy == HDA_PARSE_MIXER && 3680 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3681 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3682 && (w->pflags & HDA_DAC_PATH)) || 3683 (strategy == HDA_PARSE_DIRECT && (w->pflags & 3684 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 3685 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 3686 w->nid, devinfo->startnode - 1, 0, 0); 3687 } else if (w->type == 3688 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3689 j = 0; 3690 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 3691 NULL) { 3692 if (ctl->enable == 0 || ctl->widget == NULL) 3693 continue; 3694 if (ctl->widget->nid != w->nid) 3695 continue; 3696 ctl->ossmask |= SOUND_MASK_VOLUME; 3697 ctl->ossmask |= SOUND_MASK_SPEAKER; 3698 ctl->ossdev = SOUND_MIXER_SPEAKER; 3699 w->ctlflags |= SOUND_MASK_VOLUME; 3700 w->ctlflags |= SOUND_MASK_SPEAKER; 3701 } 3702 } 3703 } 3704 3705 /* Input mixers (rec) */ 3706 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3707 w = hdac_widget_get(devinfo, i); 3708 if (w == NULL || w->enable == 0) 3709 continue; 3710 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3711 w->pflags & HDA_ADC_PATH)) 3712 continue; 3713 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 3714 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 3715 } 3716} 3717 3718#define HDA_COMMIT_CONN (1 << 0) 3719#define HDA_COMMIT_CTRL (1 << 1) 3720#define HDA_COMMIT_EAPD (1 << 2) 3721#define HDA_COMMIT_GPIO (1 << 3) 3722#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 3723 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 3724 3725static void 3726hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 3727{ 3728 struct hdac_softc *sc = devinfo->codec->sc; 3729 struct hdac_widget *w; 3730 nid_t cad; 3731 int i; 3732 3733 if (!(cfl & HDA_COMMIT_ALL)) 3734 return; 3735 3736 cad = devinfo->codec->cad; 3737 3738 if ((cfl & HDA_COMMIT_GPIO)) { 3739 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIO1) { 3740 hdac_command(sc, 3741 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, 0x01, 3742 0x01), cad); 3743 hdac_command(sc, 3744 HDA_CMD_SET_GPIO_DIRECTION(cad, 0x01, 3745 0x01), cad); 3746 hdac_command(sc, 3747 HDA_CMD_SET_GPIO_DATA(cad, 0x01, 3748 0x01), cad); 3749 } 3750 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIO2) { 3751 hdac_command(sc, 3752 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, 0x01, 3753 0x02), cad); 3754 hdac_command(sc, 3755 HDA_CMD_SET_GPIO_DIRECTION(cad, 0x01, 3756 0x02), cad); 3757 hdac_command(sc, 3758 HDA_CMD_SET_GPIO_DATA(cad, 0x01, 3759 0x02), cad); 3760 } 3761 } 3762 3763 for (i = 0; i < devinfo->nodecnt; i++) { 3764 w = &devinfo->widget[i]; 3765 if (w == NULL || w->enable == 0) 3766 continue; 3767 if (cfl & HDA_COMMIT_CONN) { 3768 if (w->selconn == -1) 3769 w->selconn = 0; 3770 if (w->nconns > 0) 3771 hdac_widget_connection_select(w, w->selconn); 3772 } 3773 if ((cfl & HDA_COMMIT_CTRL) && 3774 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 3775 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 3776 (HDA_DAC_PATH | HDA_ADC_PATH)) 3777 device_printf(sc->dev, "WARNING: node %d " 3778 "participate both for DAC/ADC!\n", w->nid); 3779 if (w->pflags & HDA_DAC_PATH) { 3780 w->wclass.pin.ctrl &= 3781 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 3782 if ((w->wclass.pin.config & 3783 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 3784 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 3785 w->wclass.pin.ctrl &= 3786 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 3787 } else if (w->pflags & HDA_ADC_PATH) { 3788 w->wclass.pin.ctrl &= 3789 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3790 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 3791 } else 3792 w->wclass.pin.ctrl &= ~( 3793 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 3794 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3795 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 3796 hdac_command(sc, 3797 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 3798 w->wclass.pin.ctrl), cad); 3799 } 3800 if ((cfl & HDA_COMMIT_EAPD) && 3801 w->param.eapdbtl != HDAC_INVALID) 3802 hdac_command(sc, 3803 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 3804 w->param.eapdbtl), cad); 3805 3806 DELAY(1000); 3807 } 3808} 3809 3810static void 3811hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 3812{ 3813 struct hdac_softc *sc = devinfo->codec->sc; 3814 struct hdac_audio_ctl *ctl; 3815 int i; 3816 3817 devinfo->function.audio.mvol = 100 | (100 << 8); 3818 i = 0; 3819 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3820 if (ctl->enable == 0 || ctl->widget == NULL) { 3821 HDA_BOOTVERBOSE_MSG( 3822 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3823 i, (ctl->widget != NULL) ? 3824 ctl->widget->nid : -1); 3825 if (ctl->childwidget != NULL) 3826 printf(" childnid=%d", 3827 ctl->childwidget->nid); 3828 if (ctl->widget == NULL) 3829 printf(" NULL WIDGET!"); 3830 printf(" DISABLED\n"); 3831 ); 3832 continue; 3833 } 3834 HDA_BOOTVERBOSE_MSG( 3835 if (ctl->ossmask == 0) { 3836 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3837 i, ctl->widget->nid); 3838 if (ctl->childwidget != NULL) 3839 printf(" childnid=%d", 3840 ctl->childwidget->nid); 3841 printf(" Bind to NONE\n"); 3842 } 3843 ); 3844 if (ctl->step > 0) { 3845 ctl->ossval = (ctl->left * 100) / ctl->step; 3846 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 3847 } else 3848 ctl->ossval = 0; 3849 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 3850 ctl->left, ctl->right); 3851 } 3852} 3853 3854static int 3855hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 3856{ 3857 struct hdac_chan *ch; 3858 struct hdac_widget *w; 3859 uint32_t cap, fmtcap, pcmcap, path; 3860 int i, type, ret, max; 3861 3862 if (dir == PCMDIR_PLAY) { 3863 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 3864 ch = &devinfo->codec->sc->play; 3865 path = HDA_DAC_PATH; 3866 } else { 3867 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 3868 ch = &devinfo->codec->sc->rec; 3869 path = HDA_ADC_PATH; 3870 } 3871 3872 ch->caps = hdac_caps; 3873 ch->caps.fmtlist = ch->fmtlist; 3874 ch->bit16 = 1; 3875 ch->bit32 = 0; 3876 ch->pcmrates[0] = 48000; 3877 ch->pcmrates[1] = 0; 3878 3879 ret = 0; 3880 fmtcap = devinfo->function.audio.supp_stream_formats; 3881 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 3882 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 3883 3884 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 3885 w = hdac_widget_get(devinfo, i); 3886 if (w == NULL || w->enable == 0 || w->type != type || 3887 (w->pflags & path) == 0) 3888 continue; 3889 cap = w->param.widget_cap; 3890 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 3891 continue;*/ 3892 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 3893 continue; 3894 cap = w->param.supp_stream_formats; 3895 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 3896 } 3897 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 3898 }*/ 3899 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 3900 continue; 3901 ch->io[ret++] = i; 3902 fmtcap &= w->param.supp_stream_formats; 3903 pcmcap &= w->param.supp_pcm_size_rate; 3904 } 3905 ch->io[ret] = -1; 3906 3907 ch->supp_stream_formats = fmtcap; 3908 ch->supp_pcm_size_rate = pcmcap; 3909 3910 /* 3911 * 8bit = 0 3912 * 16bit = 1 3913 * 20bit = 2 3914 * 24bit = 3 3915 * 32bit = 4 3916 */ 3917 if (ret > 0) { 3918 cap = pcmcap; 3919 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 3920 ch->bit16 = 1; 3921 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 3922 ch->bit16 = 0; 3923 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 3924 ch->bit32 = 4; 3925 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 3926 ch->bit32 = 3; 3927 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 3928 ch->bit32 = 2; 3929 i = 0; 3930 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 3931 ch->fmtlist[i++] = AFMT_S16_LE; 3932 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 3933 if (ch->bit32 > 0) { 3934 if (!(devinfo->function.audio.quirks & 3935 HDA_QUIRK_FORCESTEREO)) 3936 ch->fmtlist[i++] = AFMT_S32_LE; 3937 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 3938 } 3939 ch->fmtlist[i] = 0; 3940 i = 0; 3941 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 3942 ch->pcmrates[i++] = 8000; 3943 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 3944 ch->pcmrates[i++] = 11025; 3945 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 3946 ch->pcmrates[i++] = 16000; 3947 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 3948 ch->pcmrates[i++] = 22050; 3949 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 3950 ch->pcmrates[i++] = 32000; 3951 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 3952 ch->pcmrates[i++] = 44100; 3953 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 3954 ch->pcmrates[i++] = 48000; 3955 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 3956 ch->pcmrates[i++] = 88200; 3957 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 3958 ch->pcmrates[i++] = 96000; 3959 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 3960 ch->pcmrates[i++] = 176400; 3961 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 3962 ch->pcmrates[i++] = 192000; 3963 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 3964 ch->pcmrates[i] = 0; 3965 if (i > 0) { 3966 ch->caps.minspeed = ch->pcmrates[0]; 3967 ch->caps.maxspeed = ch->pcmrates[i - 1]; 3968 } 3969 } 3970 3971 return (ret); 3972} 3973 3974static void 3975hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 3976{ 3977 struct hdac_audio_ctl *ctl; 3978 struct hdac_softc *sc = devinfo->codec->sc; 3979 int i; 3980 uint32_t fl = 0; 3981 3982 3983 if (flag == 0) { 3984 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 3985 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 3986 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 3987 } 3988 3989 i = 0; 3990 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3991 if (ctl->enable == 0 || ctl->widget == NULL || 3992 ctl->widget->enable == 0) 3993 continue; 3994 if ((flag == 0 && (ctl->ossmask & ~fl)) || 3995 (flag != 0 && (ctl->ossmask & flag))) { 3996 if (banner != NULL) { 3997 device_printf(sc->dev, "\n"); 3998 device_printf(sc->dev, "%s\n", banner); 3999 } 4000 goto hdac_ctl_dump_it_all; 4001 } 4002 } 4003 4004 return; 4005 4006hdac_ctl_dump_it_all: 4007 i = 0; 4008 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4009 if (ctl->enable == 0 || ctl->widget == NULL || 4010 ctl->widget->enable == 0) 4011 continue; 4012 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4013 (flag != 0 && (ctl->ossmask & flag)))) 4014 continue; 4015 if (flag == 0) { 4016 device_printf(sc->dev, "\n"); 4017 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4018 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4019 } 4020 device_printf(sc->dev, " |\n"); 4021 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4022 ctl->widget->nid, ctl->index); 4023 if (ctl->childwidget != NULL) 4024 printf("(nid: %2d) ", ctl->childwidget->nid); 4025 else 4026 printf(" "); 4027 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4028 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4029 ctl->ossmask); 4030 } 4031} 4032 4033static void 4034hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4035{ 4036 uint32_t cap; 4037 4038 cap = fcap; 4039 if (cap != 0) { 4040 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4041 device_printf(sc->dev, " Format:"); 4042 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4043 printf(" AC3"); 4044 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4045 printf(" FLOAT32"); 4046 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4047 printf(" PCM"); 4048 printf("\n"); 4049 } 4050 cap = pcmcap; 4051 if (cap != 0) { 4052 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4053 device_printf(sc->dev, " PCM size:"); 4054 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4055 printf(" 8"); 4056 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4057 printf(" 16"); 4058 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4059 printf(" 20"); 4060 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4061 printf(" 24"); 4062 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4063 printf(" 32"); 4064 printf("\n"); 4065 device_printf(sc->dev, " PCM rate:"); 4066 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4067 printf(" 8"); 4068 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4069 printf(" 11"); 4070 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4071 printf(" 16"); 4072 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4073 printf(" 22"); 4074 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4075 printf(" 32"); 4076 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4077 printf(" 44"); 4078 printf(" 48"); 4079 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4080 printf(" 88"); 4081 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4082 printf(" 96"); 4083 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4084 printf(" 176"); 4085 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4086 printf(" 192"); 4087 printf("\n"); 4088 } 4089} 4090 4091static void 4092hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4093{ 4094 uint32_t pincap, wcap; 4095 4096 pincap = w->wclass.pin.cap; 4097 wcap = w->param.widget_cap; 4098 4099 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4100 device_printf(sc->dev, " "); 4101 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4102 printf(" ISC"); 4103 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4104 printf(" TRQD"); 4105 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4106 printf(" PDC"); 4107 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4108 printf(" HP"); 4109 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4110 printf(" OUT"); 4111 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4112 printf(" IN"); 4113 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4114 printf(" BAL"); 4115 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4116 printf(" EAPD"); 4117 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4118 printf(" : UNSOL"); 4119 printf("\n"); 4120 device_printf(sc->dev, " Pin config: 0x%08x\n", 4121 w->wclass.pin.config); 4122 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4123 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4124 printf(" HP"); 4125 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4126 printf(" IN"); 4127 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4128 printf(" OUT"); 4129 printf("\n"); 4130} 4131 4132static void 4133hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4134{ 4135 device_printf(sc->dev, " %s amp: 0x%0x\n", banner, cap); 4136 device_printf(sc->dev, " " 4137 "mute=%d step=%d size=%d offset=%d\n", 4138 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4139 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4140 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4141 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4142} 4143 4144static void 4145hdac_dump_nodes(struct hdac_devinfo *devinfo) 4146{ 4147 struct hdac_softc *sc = devinfo->codec->sc; 4148 struct hdac_widget *w, *cw; 4149 int i, j; 4150 4151 device_printf(sc->dev, "\n"); 4152 device_printf(sc->dev, "Default Parameter\n"); 4153 device_printf(sc->dev, "-----------------\n"); 4154 hdac_dump_audio_formats(sc, 4155 devinfo->function.audio.supp_stream_formats, 4156 devinfo->function.audio.supp_pcm_size_rate); 4157 device_printf(sc->dev, " IN amp: 0x%08x\n", 4158 devinfo->function.audio.inamp_cap); 4159 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4160 devinfo->function.audio.outamp_cap); 4161 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4162 w = hdac_widget_get(devinfo, i); 4163 if (w == NULL) { 4164 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4165 continue; 4166 } 4167 device_printf(sc->dev, "\n"); 4168 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4169 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4170 "DIGITAL" : "ANALOG", 4171 (w->enable == 0) ? " [DISABLED]" : ""); 4172 device_printf(sc->dev, " name: %s\n", w->name); 4173 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4174 w->param.widget_cap); 4175 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4176 w->pflags); 4177 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4178 w->ctlflags); 4179 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4180 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4181 hdac_dump_audio_formats(sc, 4182 w->param.supp_stream_formats, 4183 w->param.supp_pcm_size_rate); 4184 } else if (w->type == 4185 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4186 hdac_dump_pin(sc, w); 4187 if (w->param.eapdbtl != HDAC_INVALID) 4188 device_printf(sc->dev, " EAPD: 0x%08x\n", 4189 w->param.eapdbtl); 4190 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap)) 4191 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4192 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap)) 4193 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4194 device_printf(sc->dev, " connections: %d\n", w->nconns); 4195 for (j = 0; j < w->nconns; j++) { 4196 cw = hdac_widget_get(devinfo, w->conns[j]); 4197 device_printf(sc->dev, " |\n"); 4198 device_printf(sc->dev, " + <- nid=%d [%s]", 4199 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4200 if (cw == NULL) 4201 printf(" [UNKNOWN]"); 4202 else if (cw->enable == 0) 4203 printf(" [DISABLED]"); 4204 if (w->nconns > 1 && w->selconn == j && w->type != 4205 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4206 printf(" (selected)"); 4207 printf("\n"); 4208 } 4209 } 4210 4211} 4212 4213static void 4214hdac_dump_dac(struct hdac_devinfo *devinfo) 4215{ 4216 /* XXX TODO */ 4217} 4218 4219static void 4220hdac_dump_adc(struct hdac_devinfo *devinfo) 4221{ 4222 struct hdac_widget *w, *cw; 4223 struct hdac_softc *sc = devinfo->codec->sc; 4224 int i, j; 4225 int printed = 0; 4226 char ossdevs[256]; 4227 4228 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4229 w = hdac_widget_get(devinfo, i); 4230 if (w == NULL || w->enable == 0) 4231 continue; 4232 if (!(w->pflags & HDA_ADC_RECSEL)) 4233 continue; 4234 if (printed == 0) { 4235 printed = 1; 4236 device_printf(sc->dev, "\n"); 4237 device_printf(sc->dev, "Recording sources:\n"); 4238 } 4239 device_printf(sc->dev, "\n"); 4240 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4241 for (j = 0; j < w->nconns; j++) { 4242 cw = hdac_widget_get(devinfo, w->conns[j]); 4243 if (cw == NULL || cw->enable == 0) 4244 continue; 4245 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4246 ossdevs, sizeof(ossdevs)); 4247 device_printf(sc->dev, " |\n"); 4248 device_printf(sc->dev, " + <- nid=%d [%s]", 4249 cw->nid, cw->name); 4250 if (strlen(ossdevs) > 0) { 4251 printf(" [recsrc: %s]", ossdevs); 4252 } 4253 printf("\n"); 4254 } 4255 } 4256} 4257 4258static void 4259hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4260{ 4261 nid_t *nids; 4262 4263 if (pcnt > 0) { 4264 device_printf(sc->dev, "\n"); 4265 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4266 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4267 sc->play.supp_pcm_size_rate); 4268 device_printf(sc->dev, " DAC:"); 4269 for (nids = sc->play.io; *nids != -1; nids++) 4270 printf(" %d", *nids); 4271 printf("\n"); 4272 } 4273 4274 if (rcnt > 0) { 4275 device_printf(sc->dev, "\n"); 4276 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4277 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4278 sc->rec.supp_pcm_size_rate); 4279 device_printf(sc->dev, " ADC:"); 4280 for (nids = sc->rec.io; *nids != -1; nids++) 4281 printf(" %d", *nids); 4282 printf("\n"); 4283 } 4284} 4285 4286static void 4287hdac_attach2(void *arg) 4288{ 4289 struct hdac_softc *sc; 4290 struct hdac_widget *w; 4291 struct hdac_audio_ctl *ctl; 4292 int pcnt, rcnt; 4293 int i; 4294 char status[SND_STATUSLEN]; 4295 device_t *devlist = NULL; 4296 int devcount; 4297 struct hdac_devinfo *devinfo = NULL; 4298 4299 sc = (struct hdac_softc *)arg; 4300 4301 4302 hdac_lock(sc); 4303 4304 /* Remove ourselves from the config hooks */ 4305 if (sc->intrhook.ich_func != NULL) { 4306 config_intrhook_disestablish(&sc->intrhook); 4307 sc->intrhook.ich_func = NULL; 4308 } 4309 4310 /* Start the corb and rirb engines */ 4311 HDA_DEBUG_MSG( 4312 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4313 ); 4314 hdac_corb_start(sc); 4315 HDA_DEBUG_MSG( 4316 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4317 ); 4318 hdac_rirb_start(sc); 4319 4320 HDA_DEBUG_MSG( 4321 device_printf(sc->dev, 4322 "HDA_DEBUG: Enabling controller interrupt...\n"); 4323 ); 4324 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4325 4326 DELAY(1000); 4327 4328 HDA_DEBUG_MSG( 4329 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4330 ); 4331 hdac_scan_codecs(sc); 4332 4333 device_get_children(sc->dev, &devlist, &devcount); 4334 for (i = 0; devlist != NULL && i < devcount; i++) { 4335 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4336 if (devinfo != NULL && devinfo->node_type == 4337 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4338 break; 4339 } else 4340 devinfo = NULL; 4341 } 4342 if (devlist != NULL) 4343 free(devlist, M_TEMP); 4344 4345 if (devinfo == NULL) { 4346 hdac_unlock(sc); 4347 device_printf(sc->dev, "Audio Function Group not found!\n"); 4348 return; 4349 } 4350 4351 HDA_DEBUG_MSG( 4352 device_printf(sc->dev, 4353 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4354 devinfo->nid, devinfo->codec->cad); 4355 ); 4356 hdac_audio_parse(devinfo); 4357 HDA_DEBUG_MSG( 4358 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4359 ); 4360 hdac_audio_ctl_parse(devinfo); 4361 HDA_DEBUG_MSG( 4362 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4363 ); 4364 hdac_vendor_patch_parse(devinfo); 4365 4366 /* XXX Disable all DIGITAL path. */ 4367 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4368 w = hdac_widget_get(devinfo, i); 4369 if (w == NULL) 4370 continue; 4371 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4372 w->enable = 0; 4373 continue; 4374 } 4375 /* XXX Disable useless pin ? */ 4376 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4377 (w->wclass.pin.config & 4378 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4379 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4380 w->enable = 0; 4381 } 4382 i = 0; 4383 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4384 if (ctl->widget == NULL) 4385 continue; 4386 w = ctl->widget; 4387 if (w->enable == 0) 4388 ctl->enable = 0; 4389 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4390 ctl->enable = 0; 4391 w = ctl->childwidget; 4392 if (w == NULL) 4393 continue; 4394 if (w->enable == 0 || 4395 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4396 ctl->enable = 0; 4397 } 4398 4399 HDA_DEBUG_MSG( 4400 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 4401 ); 4402 hdac_audio_build_tree(devinfo); 4403 4404 HDA_DEBUG_MSG( 4405 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 4406 ); 4407 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 4408 HDA_DEBUG_MSG( 4409 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 4410 ); 4411 hdac_audio_ctl_commit(devinfo); 4412 4413 HDA_DEBUG_MSG( 4414 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 4415 ); 4416 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 4417 HDA_DEBUG_MSG( 4418 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 4419 ); 4420 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 4421 4422 hdac_unlock(sc); 4423 HDA_DEBUG_MSG( 4424 device_printf(sc->dev, 4425 "HDA_DEBUG: OSS mixer initialization...\n"); 4426 ); 4427 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo)) { 4428 device_printf(sc->dev, "Can't register mixer\n"); 4429 } 4430 4431 if (pcnt > 0) 4432 pcnt = 1; 4433 if (rcnt > 0) 4434 rcnt = 1; 4435 4436 HDA_DEBUG_MSG( 4437 device_printf(sc->dev, 4438 "HDA_DEBUG: Registering PCM channels...\n"); 4439 ); 4440 if (pcm_register(sc->dev, devinfo, pcnt, rcnt)) { 4441 device_printf(sc->dev, "Can't register PCM\n"); 4442 } 4443 4444 sc->registered++; 4445 4446 for (i = 0; i < pcnt; i++) 4447 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 4448 for (i = 0; i < rcnt; i++) 4449 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 4450 4451 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 4452 rman_get_start(sc->mem.mem_res), 4453 rman_get_start(sc->irq.irq_res), 4454 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 4455 pcm_setstatus(sc->dev, status); 4456 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 4457 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 4458 4459 HDA_BOOTVERBOSE_MSG( 4460 if (devinfo->function.audio.quirks != 0) { 4461 device_printf(sc->dev, "\n"); 4462 device_printf(sc->dev, "HDA quirks:"); 4463 if (devinfo->function.audio.quirks & 4464 HDA_QUIRK_GPIO1) 4465 printf(" GPIO1"); 4466 if (devinfo->function.audio.quirks & 4467 HDA_QUIRK_GPIO2) 4468 printf(" GPIO2"); 4469 if (devinfo->function.audio.quirks & 4470 HDA_QUIRK_SOFTPCMVOL) 4471 printf(" SOFTPCMVOL"); 4472 if (devinfo->function.audio.quirks & 4473 HDA_QUIRK_FIXEDRATE) 4474 printf(" FIXEDRATE"); 4475 if (devinfo->function.audio.quirks & 4476 HDA_QUIRK_FORCESTEREO) 4477 printf(" FORCESTEREO"); 4478 printf("\n"); 4479 } 4480 device_printf(sc->dev, "\n"); 4481 device_printf(sc->dev, "+-------------------+\n"); 4482 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 4483 device_printf(sc->dev, "+-------------------+\n"); 4484 hdac_dump_nodes(devinfo); 4485 device_printf(sc->dev, "\n"); 4486 device_printf(sc->dev, "+------------------------+\n"); 4487 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 4488 device_printf(sc->dev, "+------------------------+\n"); 4489 device_printf(sc->dev, "\n"); 4490 i = 0; 4491 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4492 device_printf(sc->dev, "%3d: nid=%d", i, 4493 (ctl->widget != NULL) ? ctl->widget->nid : -1); 4494 if (ctl->childwidget != NULL) 4495 printf(" cnid=%d", ctl->childwidget->nid); 4496 printf(" dir=0x%x index=%d " 4497 "ossmask=0x%08x ossdev=%d%s\n", 4498 ctl->dir, ctl->index, 4499 ctl->ossmask, ctl->ossdev, 4500 (ctl->enable == 0) ? " [DISABLED]" : ""); 4501 } 4502 device_printf(sc->dev, "\n"); 4503 device_printf(sc->dev, "+-----------------------------------+\n"); 4504 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 4505 device_printf(sc->dev, "+-----------------------------------+\n"); 4506 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 4507 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 4508 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 4509 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 4510 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 4511 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 4512 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 4513 hdac_dump_ctls(devinfo, NULL, 0); 4514 hdac_dump_dac(devinfo); 4515 hdac_dump_adc(devinfo); 4516 device_printf(sc->dev, "\n"); 4517 device_printf(sc->dev, "+--------------------------------------+\n"); 4518 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 4519 device_printf(sc->dev, "+--------------------------------------+\n"); 4520 hdac_dump_pcmchannels(sc, pcnt, rcnt); 4521 ); 4522} 4523 4524/**************************************************************************** 4525 * int hdac_detach(device_t) 4526 * 4527 * Detach and free up resources utilized by the hdac device. 4528 ****************************************************************************/ 4529static int 4530hdac_detach(device_t dev) 4531{ 4532 struct hdac_softc *sc = NULL; 4533 device_t *devlist = NULL; 4534 int devcount; 4535 struct hdac_devinfo *devinfo = NULL; 4536 struct hdac_codec *codec; 4537 int i; 4538 4539 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 4540 if (devinfo != NULL && devinfo->codec != NULL) 4541 sc = devinfo->codec->sc; 4542 if (sc == NULL) 4543 return (EINVAL); 4544 4545 if (sc->registered > 0) { 4546 i = pcm_unregister(dev); 4547 if (i) 4548 return (i); 4549 } 4550 4551 sc->registered = 0; 4552 4553 /* Lock the mutex before messing with the dma engines */ 4554 hdac_lock(sc); 4555 hdac_reset(sc); 4556 hdac_unlock(sc); 4557 snd_mtxfree(sc->lock); 4558 sc->lock = NULL; 4559 4560 device_get_children(sc->dev, &devlist, &devcount); 4561 for (i = 0; devlist != NULL && i < devcount; i++) { 4562 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 4563 if (devinfo == NULL) 4564 continue; 4565 if (devinfo->widget != NULL) 4566 free(devinfo->widget, M_HDAC); 4567 if (devinfo->node_type == 4568 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4569 devinfo->function.audio.ctl != NULL) 4570 free(devinfo->function.audio.ctl, M_HDAC); 4571 free(devinfo, M_HDAC); 4572 device_delete_child(sc->dev, devlist[i]); 4573 } 4574 if (devlist != NULL) 4575 free(devlist, M_TEMP); 4576 4577 while (!SLIST_EMPTY(&sc->codec_list)) { 4578 codec = SLIST_FIRST(&sc->codec_list); 4579 SLIST_REMOVE_HEAD(&sc->codec_list, next_codec); 4580 free(codec, M_HDAC); 4581 } 4582 4583 hdac_dma_free(&sc->rirb_dma); 4584 hdac_dma_free(&sc->corb_dma); 4585 if (sc->play.blkcnt) 4586 hdac_dma_free(&sc->play.bdl_dma); 4587 if (sc->rec.blkcnt) 4588 hdac_dma_free(&sc->rec.bdl_dma); 4589 hdac_irq_free(sc); 4590 hdac_mem_free(sc); 4591 free(sc, M_DEVBUF); 4592 4593 return (0); 4594} 4595 4596static device_method_t hdac_methods[] = { 4597 /* device interface */ 4598 DEVMETHOD(device_probe, hdac_probe), 4599 DEVMETHOD(device_attach, hdac_attach), 4600 DEVMETHOD(device_detach, hdac_detach), 4601 { 0, 0 } 4602}; 4603 4604static driver_t hdac_driver = { 4605 "pcm", 4606 hdac_methods, 4607 PCM_SOFTC_SIZE, 4608}; 4609 4610DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 4611MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 4612MODULE_VERSION(snd_hda, 1); 4613