hdac.c revision 162956
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especiall UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <dev/sound/pci/hda/hdac_private.h> 75#include <dev/sound/pci/hda/hdac_reg.h> 76#include <dev/sound/pci/hda/hda_reg.h> 77#include <dev/sound/pci/hda/hdac.h> 78 79#include "mixer_if.h" 80 81#define HDA_DRV_TEST_REV "20061001_0028" 82#define HDA_WIDGET_PARSER_REV 1 83 84SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 162956 2006-10-02 15:26:37Z ariff $"); 85 86#undef HDA_DEBUG_ENABLED 87#define HDA_DEBUG_ENABLED 1 88 89#ifdef HDA_DEBUG_ENABLED 90#define HDA_DEBUG_MSG(stmt) do { \ 91 if (bootverbose) { \ 92 stmt \ 93 } \ 94} while(0) 95#else 96#define HDA_DEBUG_MSG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE_MSG(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 0 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 113#define HDA_MODEL_CONSTRUCT(vendor, model) \ 114 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 115 116/* Controller models */ 117 118/* Intel */ 119#define INTEL_VENDORID 0x8086 120#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 121#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 122#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 123 124/* Nvidia */ 125#define NVIDIA_VENDORID 0x10de 126#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 127#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 128#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 129 130/* ATI */ 131#define ATI_VENDORID 0x1002 132#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 133#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 134 135/* OEM/subvendors */ 136 137/* HP/Compaq */ 138#define HP_VENDORID 0x103c 139#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 140#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 141#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 142#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 143 144/* Dell */ 145#define DELL_VENDORID 0x1028 146#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 147#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 148#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 149 150/* Clevo */ 151#define CLEVO_VENDORID 0x1558 152#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 153#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 154 155/* Acer */ 156#define ACER_VENDORID 0x1025 157#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 158 159 160/* Misc constants.. */ 161#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 162#define HDA_AMP_MUTE_NONE (0) 163#define HDA_AMP_MUTE_LEFT (1 << 0) 164#define HDA_AMP_MUTE_RIGHT (1 << 1) 165#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 166 167#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 168#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 169 170#define HDA_DAC_PATH (1 << 0) 171#define HDA_ADC_PATH (1 << 1) 172#define HDA_ADC_RECSEL (1 << 2) 173 174#define HDA_CTL_OUT 0x1 175#define HDA_CTL_IN 0x2 176#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 177 178#define HDA_QUIRK_GPIO1 (1 << 0) 179#define HDA_QUIRK_GPIO2 (1 << 1) 180#define HDA_QUIRK_SOFTPCMVOL (1 << 2) 181#define HDA_QUIRK_FIXEDRATE (1 << 3) 182#define HDA_QUIRK_FORCESTEREO (1 << 4) 183 184#define HDA_BDL_MIN 2 185#define HDA_BDL_MAX 256 186#define HDA_BDL_DEFAULT HDA_BDL_MIN 187 188#define HDA_BUFSZ_MIN 4096 189#define HDA_BUFSZ_MAX 65536 190#define HDA_BUFSZ_DEFAULT 16384 191 192#define HDA_PARSE_MAXDEPTH 10 193 194#define HDAC_UNSOLTAG_EVENT_HP 0x00 195 196static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 197 198enum { 199 HDA_PARSE_MIXER, 200 HDA_PARSE_DIRECT 201}; 202 203/* Default */ 204static uint32_t hdac_fmt[] = { 205 AFMT_STEREO | AFMT_S16_LE, 206 0 207}; 208 209static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 210 211static const struct { 212 uint32_t model; 213 char *desc; 214} hdac_devices[] = { 215 { HDA_INTEL_82801F, "Intel 82801F" }, 216 { HDA_INTEL_82801G, "Intel 82801G" }, 217 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 218 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 219 { HDA_ATI_SB450, "ATI SB450" }, 220 /* Unknown */ 221 { HDA_INTEL_ALL, "Intel (Unknown)" }, 222 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 223 { HDA_ATI_ALL, "ATI (Unknown)" }, 224}; 225#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 226 227static const struct { 228 uint32_t rate; 229 int valid; 230 uint16_t base; 231 uint16_t mul; 232 uint16_t div; 233} hda_rate_tab[] = { 234 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 235 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 236 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 237 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 238 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 239 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 240 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 241 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 242 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 243 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 244 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 245 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 246 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 247 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 248 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 249 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 250 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 251 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 252 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 253 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 254 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 255 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 256 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 257 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 258 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 259 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 260 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 261 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 262 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 263 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 264 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 265 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 266 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 267 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 268 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 269}; 270#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 271 272/* All codecs you can eat... */ 273#define HDA_CODEC_CONSTRUCT(vendor, id) \ 274 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 275 276/* Realtek */ 277#define REALTEK_VENDORID 0x10ec 278#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 279#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 280#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 281#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 282#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 283 284/* Analog Device */ 285#define ANALOGDEVICE_VENDORID 0x11d4 286#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 287#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 288#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 289#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 290 291/* CMedia */ 292#define CMEDIA_VENDORID 0x434d 293#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 294#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 295 296/* Sigmatel */ 297#define SIGMATEL_VENDORID 0x8384 298#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 299#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 300#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 301#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 302#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 303 304/* 305 * Conexant 306 * 307 * Ok, the truth is, I don't have any idea at all whether 308 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 309 * place that tell me it is "Venice" is from its Windows driver INF. 310 */ 311#define CONEXANT_VENDORID 0x14f1 312#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 313#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 314 315 316/* Codecs */ 317static const struct { 318 uint32_t id; 319 char *name; 320} hdac_codecs[] = { 321 { HDA_CODEC_ALC260, "Realtek ALC260" }, 322 { HDA_CODEC_ALC861, "Realtek ALC861" }, 323 { HDA_CODEC_ALC880, "Realtek ALC880" }, 324 { HDA_CODEC_ALC882, "Realtek ALC882" }, 325 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 326 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 327 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 328 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 329 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 330 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 331 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 332 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 333 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 334 /* Unknown codec */ 335 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 336 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 337 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 338 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 339 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 340}; 341#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 342 343enum { 344 HDAC_HP_SWITCH_CTL, 345 HDAC_HP_SWITCH_CTRL 346}; 347 348static const struct { 349 uint32_t vendormask; 350 uint32_t id; 351 int type; 352 nid_t hpnid; 353 nid_t spkrnid[8]; 354 nid_t eapdnid; 355} hdac_hp_switch[] = { 356 /* Specific OEM models */ 357 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 358 17, { 16, -1 }, 16 }, 359 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 360 6, { 5, -1 }, 5 }, 361 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 362 6, { 5, -1 }, 5 }, 363 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 364 13, { 14, -1 }, -1 }, 365 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 366 13, { 14, -1 }, -1 }, 367 /* 368 * All models that at least come from the same vendor with 369 * simmilar codec. 370 */ 371 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 372 17, { 16, -1 }, 16 }, 373 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 374 6, { 5, -1 }, 5 }, 375 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 376 13, { 14, -1 }, -1 }, 377}; 378#define HDAC_HP_SWITCH_LEN \ 379 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 380 381static const struct { 382 uint32_t vendormask; 383 uint32_t id; 384 nid_t eapdnid; 385 int hp_switch; 386} hdac_eapd_switch[] = { 387 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 388 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 389 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 390}; 391#define HDAC_EAPD_SWITCH_LEN \ 392 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 393 394/**************************************************************************** 395 * Function prototypes 396 ****************************************************************************/ 397static void hdac_intr_handler(void *); 398static int hdac_reset(struct hdac_softc *); 399static int hdac_get_capabilities(struct hdac_softc *); 400static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 401static int hdac_dma_alloc(struct hdac_softc *, 402 struct hdac_dma *, bus_size_t); 403static void hdac_dma_free(struct hdac_dma *); 404static int hdac_mem_alloc(struct hdac_softc *); 405static void hdac_mem_free(struct hdac_softc *); 406static int hdac_irq_alloc(struct hdac_softc *); 407static void hdac_irq_free(struct hdac_softc *); 408static void hdac_corb_init(struct hdac_softc *); 409static void hdac_rirb_init(struct hdac_softc *); 410static void hdac_corb_start(struct hdac_softc *); 411static void hdac_rirb_start(struct hdac_softc *); 412static void hdac_scan_codecs(struct hdac_softc *); 413static int hdac_probe_codec(struct hdac_codec *); 414static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 415static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 416 417static void hdac_attach2(void *); 418 419static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 420 uint32_t, int); 421static void hdac_command_send_internal(struct hdac_softc *, 422 struct hdac_command_list *, int); 423 424static int hdac_probe(device_t); 425static int hdac_attach(device_t); 426static int hdac_detach(device_t); 427static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 428static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 429 uint32_t, int, int); 430static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 431 nid_t, int, int); 432static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 433 nid_t, nid_t, int, int, int, int, int, int); 434static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 435static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 436 437#define hdac_command(a1, a2, a3) \ 438 hdac_command_sendone_internal(a1, a2, a3) 439 440#define hdac_codec_id(d) \ 441 ((uint32_t)((d == NULL) ? 0x00000000 : \ 442 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 443 ((uint32_t)(d)->device_id & 0x0000ffff)))) 444 445static char * 446hdac_codec_name(struct hdac_devinfo *devinfo) 447{ 448 uint32_t id; 449 int i; 450 451 id = hdac_codec_id(devinfo); 452 453 for (i = 0; i < HDAC_CODECS_LEN; i++) { 454 if ((hdac_codecs[i].id & id) == id) 455 return (hdac_codecs[i].name); 456 } 457 458 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 459} 460 461static char * 462hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 463{ 464 static char *ossname[] = SOUND_DEVICE_NAMES; 465 static char *unknown = "???"; 466 int i; 467 468 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 469 if (devmask & (1 << i)) 470 return (ossname[i]); 471 } 472 return (unknown); 473} 474 475static void 476hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 477{ 478 static char *ossname[] = SOUND_DEVICE_NAMES; 479 int i, first = 1; 480 481 bzero(buf, len); 482 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 483 if (mask & (1 << i)) { 484 if (first == 0) 485 strlcat(buf, ", ", len); 486 strlcat(buf, ossname[i], len); 487 first = 0; 488 } 489 } 490} 491 492static struct hdac_audio_ctl * 493hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 494{ 495 if (devinfo == NULL || 496 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 497 index == NULL || devinfo->function.audio.ctl == NULL || 498 devinfo->function.audio.ctlcnt < 1 || 499 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 500 return (NULL); 501 return (&devinfo->function.audio.ctl[(*index)++]); 502} 503 504static struct hdac_audio_ctl * 505hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 506 int index, int cnt) 507{ 508 struct hdac_audio_ctl *ctl, *retctl = NULL; 509 int i, at, atindex, found = 0; 510 511 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 512 return (NULL); 513 514 at = cnt; 515 if (at == 0) 516 at = 1; 517 else if (at < 0) 518 at = -1; 519 atindex = index; 520 if (atindex < 0) 521 atindex = -1; 522 523 i = 0; 524 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 525 if (ctl->enable == 0 || ctl->widget == NULL) 526 continue; 527 if (!(ctl->widget->nid == nid && (atindex == -1 || 528 ctl->index == atindex))) 529 continue; 530 found++; 531 if (found == cnt) 532 return (ctl); 533 retctl = ctl; 534 } 535 536 return ((at == -1) ? retctl : NULL); 537} 538 539static void 540hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 541{ 542 struct hdac_softc *sc; 543 struct hdac_widget *w; 544 struct hdac_audio_ctl *ctl; 545 uint32_t id, res; 546 int i = 0, j, forcemute; 547 nid_t cad; 548 549 if (devinfo == NULL || devinfo->codec == NULL || 550 devinfo->codec->sc == NULL) 551 return; 552 553 sc = devinfo->codec->sc; 554 cad = devinfo->codec->cad; 555 id = hdac_codec_id(devinfo); 556 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 557 if ((hdac_hp_switch[i].vendormask & sc->pci_subvendor) == 558 sc->pci_subvendor && 559 hdac_hp_switch[i].id == id) 560 break; 561 } 562 563 if (i >= HDAC_HP_SWITCH_LEN) 564 return; 565 566 forcemute = 0; 567 if (hdac_hp_switch[i].eapdnid != -1) { 568 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 569 if (w != NULL && w->param.eapdbtl != 0xffffffff) 570 forcemute = (w->param.eapdbtl & 571 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 572 } 573 574 res = hdac_command(sc, 575 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 576 HDA_BOOTVERBOSE_MSG( 577 device_printf(sc->dev, 578 "Pin sense: nid=%d res=0x%08x\n", 579 hdac_hp_switch[i].hpnid, res); 580 ); 581 res >>= 31; 582 583 switch (hdac_hp_switch[i].type) { 584 case HDAC_HP_SWITCH_CTL: 585 ctl = hdac_audio_ctl_amp_get(devinfo, 586 hdac_hp_switch[i].hpnid, 0, 1); 587 if (ctl != NULL) { 588 ctl->muted = (res != 0 && forcemute == 0) ? 589 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 590 hdac_audio_ctl_amp_set(ctl, 591 HDA_AMP_MUTE_DEFAULT, ctl->left, 592 ctl->right); 593 } 594 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 595 ctl = hdac_audio_ctl_amp_get(devinfo, 596 hdac_hp_switch[i].spkrnid[j], 0, 1); 597 if (ctl != NULL) { 598 ctl->muted = (res != 0 || forcemute == 1) ? 599 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 600 hdac_audio_ctl_amp_set(ctl, 601 HDA_AMP_MUTE_DEFAULT, ctl->left, 602 ctl->right); 603 } 604 } 605 break; 606 case HDAC_HP_SWITCH_CTRL: 607 if (res != 0) { 608 /* HP in */ 609 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 610 if (w != NULL) { 611 if (forcemute == 0) 612 w->wclass.pin.ctrl |= 613 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 614 else 615 w->wclass.pin.ctrl &= 616 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 617 hdac_command(sc, 618 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 619 w->wclass.pin.ctrl), cad); 620 } 621 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 622 w = hdac_widget_get(devinfo, 623 hdac_hp_switch[i].spkrnid[j]); 624 if (w != NULL) { 625 w->wclass.pin.ctrl &= 626 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 627 hdac_command(sc, 628 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 629 w->nid, 630 w->wclass.pin.ctrl), cad); 631 } 632 } 633 } else { 634 /* HP out */ 635 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 636 if (w != NULL) { 637 w->wclass.pin.ctrl &= 638 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 639 hdac_command(sc, 640 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 641 w->wclass.pin.ctrl), cad); 642 } 643 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 644 w = hdac_widget_get(devinfo, 645 hdac_hp_switch[i].spkrnid[j]); 646 if (w != NULL) { 647 if (forcemute == 0) 648 w->wclass.pin.ctrl |= 649 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 650 else 651 w->wclass.pin.ctrl &= 652 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 653 hdac_command(sc, 654 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 655 w->nid, 656 w->wclass.pin.ctrl), cad); 657 } 658 } 659 } 660 break; 661 default: 662 break; 663 } 664} 665 666static void 667hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 668{ 669 struct hdac_softc *sc; 670 struct hdac_devinfo *devinfo = NULL; 671 device_t *devlist; 672 int devcount, i; 673 674 if (codec == NULL || codec->sc == NULL) 675 return; 676 677 sc = codec->sc; 678 679 HDA_BOOTVERBOSE_MSG( 680 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 681 ); 682 683 device_get_children(sc->dev, &devlist, &devcount); 684 if (devcount != 0 && devlist != NULL) { 685 for (i = 0; i < devcount; i++) { 686 devinfo = (struct hdac_devinfo *) 687 device_get_ivars(devlist[i]); 688 if (devinfo != NULL && 689 devinfo->node_type == 690 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 691 devinfo->codec != NULL && 692 devinfo->codec->cad == codec->cad) { 693 break; 694 } else 695 devinfo = NULL; 696 } 697 } 698 if (devinfo == NULL) 699 return; 700 701 switch (tag) { 702 case HDAC_UNSOLTAG_EVENT_HP: 703 hdac_hp_switch_handler(devinfo); 704 break; 705 default: 706 break; 707 } 708} 709 710static void 711hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 712{ 713 /* XXX to be removed */ 714#ifdef HDAC_INTR_EXTRA 715 uint32_t res; 716#endif 717 718 if (ch->blkcnt == 0) 719 return; 720 721 /* XXX to be removed */ 722#ifdef HDAC_INTR_EXTRA 723 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 724#endif 725 726 /* XXX to be removed */ 727#ifdef HDAC_INTR_EXTRA 728 if ((res & HDAC_SDSTS_DESE) || (res & HDAC_SDSTS_FIFOE)) 729 device_printf(sc->dev, 730 "PCMDIR_%s intr triggered beyond stream boundary: %08x\n", 731 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 732#endif 733 734 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 735 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 736 737 /* XXX to be removed */ 738#ifdef HDAC_INTR_EXTRA 739 if (res & HDAC_SDSTS_BCIS) { 740#endif 741 ch->prevptr = ch->ptr; 742 ch->ptr += sndbuf_getblksz(ch->b); 743 ch->ptr %= sndbuf_getsize(ch->b); 744 hdac_unlock(sc); 745 chn_intr(ch->c); 746 hdac_lock(sc); 747 /* XXX to be removed */ 748#ifdef HDAC_INTR_EXTRA 749 } 750#endif 751} 752 753/**************************************************************************** 754 * void hdac_intr_handler(void *) 755 * 756 * Interrupt handler. Processes interrupts received from the hdac. 757 ****************************************************************************/ 758static void 759hdac_intr_handler(void *context) 760{ 761 struct hdac_softc *sc; 762 uint32_t intsts; 763 uint8_t rirbsts; 764 uint8_t rirbwp; 765 struct hdac_rirb *rirb_base, *rirb; 766 nid_t ucad; 767 uint32_t utag; 768 769 sc = (struct hdac_softc *)context; 770 771 hdac_lock(sc); 772 /* Do we have anything to do? */ 773 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 774 if ((intsts & HDAC_INTSTS_GIS) != HDAC_INTSTS_GIS) { 775 hdac_unlock(sc); 776 return; 777 } 778 779 /* Was this a controller interrupt? */ 780 if ((intsts & HDAC_INTSTS_CIS) == HDAC_INTSTS_CIS) { 781 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 782 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 783 /* Get as many responses that we can */ 784 while ((rirbsts & HDAC_RIRBSTS_RINTFL) == HDAC_RIRBSTS_RINTFL) { 785 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 786 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 787 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 788 BUS_DMASYNC_POSTREAD); 789 while (sc->rirb_rp != rirbwp) { 790 sc->rirb_rp++; 791 sc->rirb_rp %= sc->rirb_size; 792 rirb = &rirb_base[sc->rirb_rp]; 793 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 794 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 795 utag = rirb->response >> 26; 796 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 797 sc->codecs[ucad] != NULL) { 798 sc->unsolq[sc->unsolq_wp++] = 799 (ucad << 16) | 800 (utag & 0xffff); 801 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 802 } 803 } 804 } 805 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 806 } 807 /* XXX to be removed */ 808 /* Clear interrupt and exit */ 809#ifdef HDAC_INTR_EXTRA 810 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 811#endif 812 } 813 if ((intsts & HDAC_INTSTS_SIS_MASK)) { 814 if (intsts & (1 << sc->num_iss)) 815 hdac_stream_intr(sc, &sc->play); 816 if (intsts & (1 << 0)) 817 hdac_stream_intr(sc, &sc->rec); 818 /* XXX to be removed */ 819#ifdef HDAC_INTR_EXTRA 820 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK); 821#endif 822 } 823 824 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 825 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 826 while (sc->unsolq_rp != sc->unsolq_wp) { 827 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 828 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 829 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 830 hdac_unsolicited_handler(sc->codecs[ucad], utag); 831 } 832 sc->unsolq_st = HDAC_UNSOLQ_READY; 833 } 834 835 hdac_unlock(sc); 836} 837 838/**************************************************************************** 839 * int had_reset(hdac_softc *) 840 * 841 * Reset the hdac to a quiescent and known state. 842 ****************************************************************************/ 843static int 844hdac_reset(struct hdac_softc *sc) 845{ 846 uint32_t gctl; 847 int count, i; 848 849 /* 850 * Stop all Streams DMA engine 851 */ 852 for (i = 0; i < sc->num_iss; i++) 853 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 854 for (i = 0; i < sc->num_oss; i++) 855 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 856 for (i = 0; i < sc->num_bss; i++) 857 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 858 859 /* 860 * Stop Control DMA engines 861 */ 862 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 863 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 864 865 /* 866 * Reset the controller. The reset must remain asserted for 867 * a minimum of 100us. 868 */ 869 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 870 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 871 count = 10000; 872 do { 873 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 874 if (!(gctl & HDAC_GCTL_CRST)) 875 break; 876 DELAY(10); 877 } while (--count); 878 if (gctl & HDAC_GCTL_CRST) { 879 device_printf(sc->dev, "Unable to put hdac in reset\n"); 880 return (ENXIO); 881 } 882 DELAY(100); 883 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 884 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 885 count = 10000; 886 do { 887 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 888 if ((gctl & HDAC_GCTL_CRST)) 889 break; 890 DELAY(10); 891 } while (--count); 892 if (!(gctl & HDAC_GCTL_CRST)) { 893 device_printf(sc->dev, "Device stuck in reset\n"); 894 return (ENXIO); 895 } 896 897 /* 898 * Enable unsolicited interrupt. 899 */ 900 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 901 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_UNSOL); 902 903 /* 904 * Wait for codecs to finish their own reset sequence. The delay here 905 * should be of 250us but for some reasons, on it's not enough on my 906 * computer. Let's use twice as much as necessary to make sure that 907 * it's reset properly. 908 */ 909 DELAY(1000); 910 911 return (0); 912} 913 914 915/**************************************************************************** 916 * int hdac_get_capabilities(struct hdac_softc *); 917 * 918 * Retreive the general capabilities of the hdac; 919 * Number of Input Streams 920 * Number of Output Streams 921 * Number of bidirectional Streams 922 * 64bit ready 923 * CORB and RIRB sizes 924 ****************************************************************************/ 925static int 926hdac_get_capabilities(struct hdac_softc *sc) 927{ 928 uint16_t gcap; 929 uint8_t corbsize, rirbsize; 930 931 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 932 sc->num_iss = HDAC_GCAP_ISS(gcap); 933 sc->num_oss = HDAC_GCAP_OSS(gcap); 934 sc->num_bss = HDAC_GCAP_BSS(gcap); 935 936 sc->support_64bit = (gcap & HDAC_GCAP_64OK) == HDAC_GCAP_64OK; 937 938 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 939 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 940 HDAC_CORBSIZE_CORBSZCAP_256) 941 sc->corb_size = 256; 942 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 943 HDAC_CORBSIZE_CORBSZCAP_16) 944 sc->corb_size = 16; 945 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 946 HDAC_CORBSIZE_CORBSZCAP_2) 947 sc->corb_size = 2; 948 else { 949 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 950 __func__, corbsize); 951 return (ENXIO); 952 } 953 954 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 955 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 956 HDAC_RIRBSIZE_RIRBSZCAP_256) 957 sc->rirb_size = 256; 958 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 959 HDAC_RIRBSIZE_RIRBSZCAP_16) 960 sc->rirb_size = 16; 961 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 962 HDAC_RIRBSIZE_RIRBSZCAP_2) 963 sc->rirb_size = 2; 964 else { 965 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 966 __func__, rirbsize); 967 return (ENXIO); 968 } 969 970 return (0); 971} 972 973 974/**************************************************************************** 975 * void hdac_dma_cb 976 * 977 * This function is called by bus_dmamap_load when the mapping has been 978 * established. We just record the physical address of the mapping into 979 * the struct hdac_dma passed in. 980 ****************************************************************************/ 981static void 982hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 983{ 984 struct hdac_dma *dma; 985 986 if (error == 0) { 987 dma = (struct hdac_dma *)callback_arg; 988 dma->dma_paddr = segs[0].ds_addr; 989 } 990} 991 992static void 993hdac_dma_nocache(void *ptr) 994{ 995#if defined(__i386__) || defined(__amd64__) 996 pt_entry_t *pte; 997 vm_offset_t va; 998 999 va = (vm_offset_t)ptr; 1000 pte = vtopte(va); 1001 if (pte) { 1002 *pte |= PG_N; 1003 invltlb(); 1004 } 1005#endif 1006} 1007 1008/**************************************************************************** 1009 * int hdac_dma_alloc 1010 * 1011 * This function allocate and setup a dma region (struct hdac_dma). 1012 * It must be freed by a corresponding hdac_dma_free. 1013 ****************************************************************************/ 1014static int 1015hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1016{ 1017 int result; 1018 int lowaddr; 1019 1020 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1021 BUS_SPACE_MAXADDR_32BIT; 1022 bzero(dma, sizeof(*dma)); 1023 1024 /* 1025 * Create a DMA tag 1026 */ 1027 result = bus_dma_tag_create(NULL, /* parent */ 1028 HDAC_DMA_ALIGNMENT, /* alignment */ 1029 0, /* boundary */ 1030 lowaddr, /* lowaddr */ 1031 BUS_SPACE_MAXADDR, /* highaddr */ 1032 NULL, /* filtfunc */ 1033 NULL, /* fistfuncarg */ 1034 size, /* maxsize */ 1035 1, /* nsegments */ 1036 size, /* maxsegsz */ 1037 0, /* flags */ 1038 NULL, /* lockfunc */ 1039 NULL, /* lockfuncarg */ 1040 &dma->dma_tag); /* dmat */ 1041 if (result != 0) { 1042 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1043 __func__, result); 1044 goto fail; 1045 } 1046 1047 /* 1048 * Allocate DMA memory 1049 */ 1050 result = bus_dmamem_alloc(dma->dma_tag, (void **) &dma->dma_vaddr, 1051 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1052 if (result != 0) { 1053 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1054 __func__, result); 1055 goto fail; 1056 } 1057 1058 /* 1059 * Map the memory 1060 */ 1061 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1062 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1063 BUS_DMA_NOWAIT); 1064 if (result != 0 || dma->dma_paddr == 0) { 1065 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1066 __func__, result); 1067 goto fail; 1068 } 1069 bzero((void *)dma->dma_vaddr, size); 1070 hdac_dma_nocache(dma->dma_vaddr); 1071 1072 return (0); 1073fail: 1074 if (dma->dma_map != NULL) 1075 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1076 if (dma->dma_tag != NULL) 1077 bus_dma_tag_destroy(dma->dma_tag); 1078 return (result); 1079} 1080 1081 1082/**************************************************************************** 1083 * void hdac_dma_free(struct hdac_dma *) 1084 * 1085 * Free a struct dhac_dma that has been previously allocated via the 1086 * hdac_dma_alloc function. 1087 ****************************************************************************/ 1088static void 1089hdac_dma_free(struct hdac_dma *dma) 1090{ 1091 if (dma->dma_tag != NULL) { 1092 /* Flush caches */ 1093 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1094 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1095 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1096 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1097 bus_dma_tag_destroy(dma->dma_tag); 1098 } 1099} 1100 1101/**************************************************************************** 1102 * int hdac_mem_alloc(struct hdac_softc *) 1103 * 1104 * Allocate all the bus resources necessary to speak with the physical 1105 * controller. 1106 ****************************************************************************/ 1107static int 1108hdac_mem_alloc(struct hdac_softc *sc) 1109{ 1110 struct hdac_mem *mem; 1111 1112 mem = &sc->mem; 1113 mem->mem_rid = PCIR_BAR(0); 1114 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1115 &mem->mem_rid, RF_ACTIVE); 1116 if (mem->mem_res == NULL) { 1117 device_printf(sc->dev, 1118 "%s: Unable to allocate memory resource\n", __func__); 1119 return (ENOMEM); 1120 } 1121 mem->mem_tag = rman_get_bustag(mem->mem_res); 1122 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1123 1124 return (0); 1125} 1126 1127/**************************************************************************** 1128 * void hdac_mem_free(struct hdac_softc *) 1129 * 1130 * Free up resources previously allocated by hdac_mem_alloc. 1131 ****************************************************************************/ 1132static void 1133hdac_mem_free(struct hdac_softc *sc) 1134{ 1135 struct hdac_mem *mem; 1136 1137 mem = &sc->mem; 1138 if (mem->mem_res != NULL) 1139 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1140 mem->mem_res); 1141} 1142 1143/**************************************************************************** 1144 * int hdac_irq_alloc(struct hdac_softc *) 1145 * 1146 * Allocate and setup the resources necessary for interrupt handling. 1147 ****************************************************************************/ 1148static int 1149hdac_irq_alloc(struct hdac_softc *sc) 1150{ 1151 struct hdac_irq *irq; 1152 int result; 1153 1154 irq = &sc->irq; 1155 irq->irq_rid = 0x0; 1156 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1157 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1158 if (irq->irq_res == NULL) { 1159 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1160 __func__); 1161 goto fail; 1162 } 1163 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1164 hdac_intr_handler, sc, &irq->irq_handle); 1165 if (result != 0) { 1166 device_printf(sc->dev, 1167 "%s: Unable to setup interrupt handler (%x)\n", 1168 __func__, result); 1169 goto fail; 1170 } 1171 1172 return (0); 1173 1174fail: 1175 if (irq->irq_res != NULL) 1176 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1177 irq->irq_res); 1178 return (ENXIO); 1179} 1180 1181/**************************************************************************** 1182 * void hdac_irq_free(struct hdac_softc *) 1183 * 1184 * Free up resources previously allocated by hdac_irq_alloc. 1185 ****************************************************************************/ 1186static void 1187hdac_irq_free(struct hdac_softc *sc) 1188{ 1189 struct hdac_irq *irq; 1190 1191 irq = &sc->irq; 1192 if (irq->irq_handle != NULL) 1193 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1194 if (irq->irq_res != NULL) 1195 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1196 irq->irq_res); 1197} 1198 1199/**************************************************************************** 1200 * void hdac_corb_init(struct hdac_softc *) 1201 * 1202 * Initialize the corb registers for operations but do not start it up yet. 1203 * The CORB engine must not be running when this function is called. 1204 ****************************************************************************/ 1205static void 1206hdac_corb_init(struct hdac_softc *sc) 1207{ 1208 uint8_t corbsize; 1209 uint64_t corbpaddr; 1210 1211 /* Setup the CORB size. */ 1212 switch (sc->corb_size) { 1213 case 256: 1214 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1215 break; 1216 case 16: 1217 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1218 break; 1219 case 2: 1220 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1221 break; 1222 default: 1223 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1224 } 1225 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1226 1227 /* Setup the CORB Address in the hdac */ 1228 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1229 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1230 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1231 1232 /* Set the WP and RP */ 1233 sc->corb_wp = 0; 1234 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1235 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1236 /* 1237 * The HDA specification indicates that the CORBRPRST bit will always 1238 * read as zero. Unfortunately, it seems that at least the 82801G 1239 * doesn't reset the bit to zero, which stalls the corb engine. 1240 * manually reset the bit to zero before continuing. 1241 */ 1242 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1243 1244 /* Enable CORB error reporting */ 1245#if 0 1246 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1247#endif 1248} 1249 1250/**************************************************************************** 1251 * void hdac_rirb_init(struct hdac_softc *) 1252 * 1253 * Initialize the rirb registers for operations but do not start it up yet. 1254 * The RIRB engine must not be running when this function is called. 1255 ****************************************************************************/ 1256static void 1257hdac_rirb_init(struct hdac_softc *sc) 1258{ 1259 uint8_t rirbsize; 1260 uint64_t rirbpaddr; 1261 1262 /* Setup the RIRB size. */ 1263 switch (sc->rirb_size) { 1264 case 256: 1265 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1266 break; 1267 case 16: 1268 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1269 break; 1270 case 2: 1271 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1272 break; 1273 default: 1274 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1275 } 1276 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1277 1278 /* Setup the RIRB Address in the hdac */ 1279 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1280 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1281 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1282 1283 /* Setup the WP and RP */ 1284 sc->rirb_rp = 0; 1285 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1286 1287 /* Setup the interrupt threshold */ 1288 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1289 1290 /* Enable Overrun and response received reporting */ 1291#if 0 1292 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1293 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1294#else 1295 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1296#endif 1297 1298 /* 1299 * Make sure that the Host CPU cache doesn't contain any dirty 1300 * cache lines that falls in the rirb. If I understood correctly, it 1301 * should be sufficient to do this only once as the rirb is purely 1302 * read-only from now on. 1303 */ 1304 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1305 BUS_DMASYNC_PREREAD); 1306} 1307 1308/**************************************************************************** 1309 * void hdac_corb_start(hdac_softc *) 1310 * 1311 * Startup the corb DMA engine 1312 ****************************************************************************/ 1313static void 1314hdac_corb_start(struct hdac_softc *sc) 1315{ 1316 uint32_t corbctl; 1317 1318 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1319 corbctl |= HDAC_CORBCTL_CORBRUN; 1320 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1321} 1322 1323/**************************************************************************** 1324 * void hdac_rirb_start(hdac_softc *) 1325 * 1326 * Startup the rirb DMA engine 1327 ****************************************************************************/ 1328static void 1329hdac_rirb_start(struct hdac_softc *sc) 1330{ 1331 uint32_t rirbctl; 1332 1333 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1334 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1335 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1336} 1337 1338 1339/**************************************************************************** 1340 * void hdac_scan_codecs(struct hdac_softc *) 1341 * 1342 * Scan the bus for available codecs. 1343 ****************************************************************************/ 1344static void 1345hdac_scan_codecs(struct hdac_softc *sc) 1346{ 1347 struct hdac_codec *codec; 1348 int i; 1349 uint16_t statests; 1350 1351 SLIST_INIT(&sc->codec_list); 1352 1353 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1354 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1355 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1356 /* We have found a codec. */ 1357 hdac_unlock(sc); 1358 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1359 M_HDAC, M_ZERO | M_NOWAIT); 1360 hdac_lock(sc); 1361 if (codec == NULL) { 1362 device_printf(sc->dev, 1363 "Unable to allocate memory for codec\n"); 1364 continue; 1365 } 1366 codec->verbs_sent = 0; 1367 codec->sc = sc; 1368 codec->cad = i; 1369 sc->codecs[i] = codec; 1370 SLIST_INSERT_HEAD(&sc->codec_list, codec, next_codec); 1371 if (hdac_probe_codec(codec) != 0) 1372 break; 1373 } 1374 } 1375 /* All codecs have been probed, now try to attach drivers to them */ 1376 bus_generic_attach(sc->dev); 1377} 1378 1379/**************************************************************************** 1380 * void hdac_probe_codec(struct hdac_softc *, int) 1381 * 1382 * Probe a the given codec_id for available function groups. 1383 ****************************************************************************/ 1384static int 1385hdac_probe_codec(struct hdac_codec *codec) 1386{ 1387 struct hdac_softc *sc = codec->sc; 1388 struct hdac_devinfo *devinfo; 1389 uint32_t vendorid, revisionid, subnode; 1390 int startnode; 1391 int endnode; 1392 int i; 1393 nid_t cad = codec->cad; 1394 1395 HDA_DEBUG_MSG( 1396 device_printf(sc->dev, "%s: Probing codec: %d\n", 1397 __func__, cad); 1398 ); 1399 vendorid = hdac_command(sc, 1400 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1401 cad); 1402 revisionid = hdac_command(sc, 1403 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1404 cad); 1405 subnode = hdac_command(sc, 1406 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1407 cad); 1408 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1409 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1410 1411 HDA_DEBUG_MSG( 1412 device_printf(sc->dev, "%s: \tstartnode=%d endnode=%d\n", 1413 __func__, startnode, endnode); 1414 ); 1415 for (i = startnode; i < endnode; i++) { 1416 devinfo = hdac_probe_function(codec, i); 1417 if (devinfo != NULL) { 1418 /* XXX Ignore other FG. */ 1419 devinfo->vendor_id = 1420 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1421 devinfo->device_id = 1422 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1423 devinfo->revision_id = 1424 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1425 devinfo->stepping_id = 1426 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1427 HDA_DEBUG_MSG( 1428 device_printf(sc->dev, 1429 "%s: \tFound AFG nid=%d " 1430 "[startnode=%d endnode=%d]\n", 1431 __func__, devinfo->nid, 1432 startnode, endnode); 1433 ); 1434 return (1); 1435 } 1436 } 1437 1438 HDA_DEBUG_MSG( 1439 device_printf(sc->dev, "%s: \tAFG not found\n", 1440 __func__); 1441 ); 1442 return (0); 1443} 1444 1445static struct hdac_devinfo * 1446hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1447{ 1448 struct hdac_softc *sc = codec->sc; 1449 struct hdac_devinfo *devinfo; 1450 uint32_t fctgrptype; 1451 nid_t cad = codec->cad; 1452 1453 fctgrptype = hdac_command(sc, 1454 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad); 1455 1456 /* XXX For now, ignore other FG. */ 1457 if (HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(fctgrptype) != 1458 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1459 return (NULL); 1460 1461 hdac_unlock(sc); 1462 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1463 M_NOWAIT | M_ZERO); 1464 hdac_lock(sc); 1465 if (devinfo == NULL) { 1466 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1467 __func__); 1468 return (NULL); 1469 } 1470 1471 devinfo->nid = nid; 1472 devinfo->node_type = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(fctgrptype); 1473 devinfo->codec = codec; 1474 1475 hdac_add_child(sc, devinfo); 1476 1477 return (devinfo); 1478} 1479 1480static void 1481hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1482{ 1483 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1484 device_set_ivars(devinfo->dev, (void *)devinfo); 1485 /* XXX - Print more information when booting verbose??? */ 1486} 1487 1488static void 1489hdac_widget_connection_parse(struct hdac_widget *w) 1490{ 1491 struct hdac_softc *sc = w->devinfo->codec->sc; 1492 uint32_t res; 1493 int i, j, max, found, entnum, cnid; 1494 nid_t cad = w->devinfo->codec->cad; 1495 nid_t nid = w->nid; 1496 1497 res = hdac_command(sc, 1498 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1499 1500 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1501 1502 if (w->nconns < 1) 1503 return; 1504 1505 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1506 res = 0; 1507 i = 0; 1508 found = 0; 1509 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1510 1511 while (i < w->nconns) { 1512 res = hdac_command(sc, 1513 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1514 for (j = 0; j < entnum; j++) { 1515 cnid = res; 1516 cnid >>= (32 / entnum) * j; 1517 cnid &= (1 << (32 / entnum)) - 1; 1518 if (cnid == 0) 1519 continue; 1520 if (found > max) { 1521 device_printf(sc->dev, 1522 "node %d: Adding %d: " 1523 "Max connection reached!\n", 1524 nid, cnid); 1525 continue; 1526 } 1527 w->conns[found++] = cnid; 1528 } 1529 i += entnum; 1530 } 1531 1532 HDA_BOOTVERBOSE_MSG( 1533 if (w->nconns != found) { 1534 device_printf(sc->dev, 1535 "node %d: WARNING!!! Connection " 1536 "length=%d != found=%d\n", 1537 nid, w->nconns, found); 1538 } 1539 ); 1540} 1541 1542static uint32_t 1543hdac_widget_pin_getconfig(struct hdac_widget *w) 1544{ 1545 struct hdac_softc *sc; 1546 uint32_t config, id; 1547 nid_t cad, nid; 1548 1549 sc = w->devinfo->codec->sc; 1550 cad = w->devinfo->codec->cad; 1551 nid = w->nid; 1552 id = hdac_codec_id(w->devinfo); 1553 1554 config = hdac_command(sc, 1555 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1556 cad); 1557 if (id == HDA_CODEC_ALC880 && 1558 sc->pci_subvendor == CLEVO_D900T_SUBVENDOR) { 1559 /* 1560 * Super broken BIOS: Clevo D900T 1561 */ 1562 switch (nid) { 1563 case 20: 1564 break; 1565 case 21: 1566 break; 1567 case 22: 1568 break; 1569 case 23: 1570 break; 1571 case 24: /* MIC1 */ 1572 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1573 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1574 break; 1575 case 25: /* XXX MIC2 */ 1576 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1577 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1578 break; 1579 case 26: /* LINE1 */ 1580 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1581 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1582 break; 1583 case 27: /* XXX LINE2 */ 1584 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1585 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1586 break; 1587 case 28: /* CD */ 1588 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1589 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1590 break; 1591 case 30: 1592 break; 1593 case 31: 1594 break; 1595 default: 1596 break; 1597 } 1598 } 1599 1600 return (config); 1601} 1602 1603static void 1604hdac_widget_pin_parse(struct hdac_widget *w) 1605{ 1606 struct hdac_softc *sc = w->devinfo->codec->sc; 1607 uint32_t config, pincap; 1608 char *devstr, *connstr; 1609 nid_t cad = w->devinfo->codec->cad; 1610 nid_t nid = w->nid; 1611 1612 config = hdac_widget_pin_getconfig(w); 1613 w->wclass.pin.config = config; 1614 1615 pincap = hdac_command(sc, 1616 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1617 w->wclass.pin.cap = pincap; 1618 1619 w->wclass.pin.ctrl = hdac_command(sc, 1620 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1621 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1622 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1623 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1624 1625 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1626 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1627 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1628 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1629 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1630 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1631 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1632 w->param.eapdbtl = hdac_command(sc, 1633 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1634 w->param.eapdbtl &= 0x7; 1635 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1636 } else 1637 w->param.eapdbtl = 0xffffffff; 1638 1639 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1640 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1641 devstr = "line out"; 1642 break; 1643 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1644 devstr = "speaker"; 1645 break; 1646 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1647 devstr = "headphones out"; 1648 break; 1649 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1650 devstr = "CD"; 1651 break; 1652 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1653 devstr = "SPDIF out"; 1654 break; 1655 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1656 devstr = "digital (other) out"; 1657 break; 1658 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1659 devstr = "modem, line side"; 1660 break; 1661 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1662 devstr = "modem, handset side"; 1663 break; 1664 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1665 devstr = "line in"; 1666 break; 1667 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1668 devstr = "AUX"; 1669 break; 1670 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1671 devstr = "Mic in"; 1672 break; 1673 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1674 devstr = "telephony"; 1675 break; 1676 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1677 devstr = "SPDIF in"; 1678 break; 1679 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1680 devstr = "digital (other) in"; 1681 break; 1682 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1683 devstr = "other"; 1684 break; 1685 default: 1686 devstr = "unknown"; 1687 break; 1688 } 1689 1690 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1691 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1692 connstr = "jack"; 1693 break; 1694 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1695 connstr = "none"; 1696 break; 1697 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1698 connstr = "fixed"; 1699 break; 1700 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1701 connstr = "jack / fixed"; 1702 break; 1703 default: 1704 connstr = "unknown"; 1705 break; 1706 } 1707 1708 strlcat(w->name, ": ", sizeof(w->name)); 1709 strlcat(w->name, devstr, sizeof(w->name)); 1710 strlcat(w->name, " (", sizeof(w->name)); 1711 strlcat(w->name, connstr, sizeof(w->name)); 1712 strlcat(w->name, ")", sizeof(w->name)); 1713} 1714 1715static void 1716hdac_widget_parse(struct hdac_widget *w) 1717{ 1718 struct hdac_softc *sc = w->devinfo->codec->sc; 1719 uint32_t wcap, cap; 1720 char *typestr; 1721 nid_t cad = w->devinfo->codec->cad; 1722 nid_t nid = w->nid; 1723 1724 wcap = hdac_command(sc, 1725 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1726 cad); 1727 w->param.widget_cap = wcap; 1728 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1729 1730 switch (w->type) { 1731 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1732 typestr = "audio output"; 1733 break; 1734 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1735 typestr = "audio input"; 1736 break; 1737 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1738 typestr = "audio mixer"; 1739 break; 1740 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1741 typestr = "audio selector"; 1742 break; 1743 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1744 typestr = "pin"; 1745 break; 1746 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1747 typestr = "power widget"; 1748 break; 1749 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1750 typestr = "volume widget"; 1751 break; 1752 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1753 typestr = "beep widget"; 1754 break; 1755 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1756 typestr = "vendor widget"; 1757 break; 1758 default: 1759 typestr = "unknown type"; 1760 break; 1761 } 1762 1763 strlcpy(w->name, typestr, sizeof(w->name)); 1764 1765 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1766 hdac_command(sc, 1767 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1768 cad); 1769 DELAY(1000); 1770 } 1771 1772 hdac_widget_connection_parse(w); 1773 1774 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1775 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1776 w->param.outamp_cap = 1777 hdac_command(sc, 1778 HDA_CMD_GET_PARAMETER(cad, nid, 1779 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1780 else 1781 w->param.outamp_cap = 1782 w->devinfo->function.audio.outamp_cap; 1783 } else 1784 w->param.outamp_cap = 0; 1785 1786 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1787 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1788 w->param.inamp_cap = 1789 hdac_command(sc, 1790 HDA_CMD_GET_PARAMETER(cad, nid, 1791 HDA_PARAM_INPUT_AMP_CAP), cad); 1792 else 1793 w->param.inamp_cap = 1794 w->devinfo->function.audio.inamp_cap; 1795 } else 1796 w->param.inamp_cap = 0; 1797 1798 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1799 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1800 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1801 cap = hdac_command(sc, 1802 HDA_CMD_GET_PARAMETER(cad, nid, 1803 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1804 w->param.supp_stream_formats = (cap != 0) ? cap : 1805 w->devinfo->function.audio.supp_stream_formats; 1806 cap = hdac_command(sc, 1807 HDA_CMD_GET_PARAMETER(cad, nid, 1808 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1809 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1810 w->devinfo->function.audio.supp_pcm_size_rate; 1811 } else { 1812 w->param.supp_stream_formats = 1813 w->devinfo->function.audio.supp_stream_formats; 1814 w->param.supp_pcm_size_rate = 1815 w->devinfo->function.audio.supp_pcm_size_rate; 1816 } 1817 } else { 1818 w->param.supp_stream_formats = 0; 1819 w->param.supp_pcm_size_rate = 0; 1820 } 1821 1822 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1823 hdac_widget_pin_parse(w); 1824} 1825 1826static struct hdac_widget * 1827hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1828{ 1829 if (devinfo == NULL || devinfo->widget == NULL || 1830 nid < devinfo->startnode || nid >= devinfo->endnode) 1831 return (NULL); 1832 return (&devinfo->widget[nid - devinfo->startnode]); 1833} 1834 1835static void 1836hdac_stream_stop(struct hdac_chan *ch) 1837{ 1838 struct hdac_softc *sc = ch->devinfo->codec->sc; 1839 uint32_t ctl; 1840 1841 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1842 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1843 HDAC_SDCTL_RUN); 1844 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1845 1846 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1847 ctl &= ~(1 << (ch->off >> 5)); 1848 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1849} 1850 1851static void 1852hdac_stream_start(struct hdac_chan *ch) 1853{ 1854 struct hdac_softc *sc = ch->devinfo->codec->sc; 1855 uint32_t ctl; 1856 1857 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1858 ctl |= 1 << (ch->off >> 5); 1859 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1860 1861 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1862 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1863 HDAC_SDCTL_RUN; 1864 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1865} 1866 1867static void 1868hdac_stream_reset(struct hdac_chan *ch) 1869{ 1870 struct hdac_softc *sc = ch->devinfo->codec->sc; 1871 int timeout = 1000; 1872 int to = timeout; 1873 uint32_t ctl; 1874 1875 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1876 ctl |= HDAC_SDCTL_SRST; 1877 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1878 do { 1879 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1880 if (ctl & HDAC_SDCTL_SRST) 1881 break; 1882 DELAY(10); 1883 } while (--to); 1884 if (!(ctl & HDAC_SDCTL_SRST)) { 1885 device_printf(sc->dev, "timeout in reset\n"); 1886 } 1887 ctl &= ~HDAC_SDCTL_SRST; 1888 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1889 to = timeout; 1890 do { 1891 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1892 if (!(ctl & HDAC_SDCTL_SRST)) 1893 break; 1894 DELAY(10); 1895 } while (--to); 1896 if ((ctl & HDAC_SDCTL_SRST)) 1897 device_printf(sc->dev, "can't reset!\n"); 1898} 1899 1900static void 1901hdac_stream_setid(struct hdac_chan *ch) 1902{ 1903 struct hdac_softc *sc = ch->devinfo->codec->sc; 1904 uint32_t ctl; 1905 1906 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 1907 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1908 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 1909 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 1910} 1911 1912static void 1913hdac_bdl_setup(struct hdac_chan *ch) 1914{ 1915 struct hdac_softc *sc = ch->devinfo->codec->sc; 1916 uint64_t addr; 1917 int blks, size, blocksize; 1918 struct hdac_bdle *bdle; 1919 int i; 1920 1921 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 1922 size = sndbuf_getsize(ch->b); 1923 blocksize = sndbuf_getblksz(ch->b); 1924 blks = size / blocksize; 1925 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr; 1926 1927 for (i = 0; i < blks; i++, bdle++) { 1928 bdle->addrl = (uint32_t)addr; 1929 bdle->addrh = (uint32_t)(addr >> 32); 1930 bdle->len = blocksize; 1931 bdle->ioc = 1; 1932 1933 addr += blocksize; 1934 } 1935 1936 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size); 1937 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1); 1938 addr = ch->bdl_dma.dma_paddr; 1939 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 1940 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1941} 1942 1943static int 1944hdac_bdl_alloc(struct hdac_chan *ch) 1945{ 1946 struct hdac_softc *sc = ch->devinfo->codec->sc; 1947 int rc; 1948 1949 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 1950 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1951 if (rc) { 1952 device_printf(sc->dev, "can't alloc bdl\n"); 1953 return (rc); 1954 } 1955 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 1956 1957 return (0); 1958} 1959 1960static void 1961hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 1962 int index, int lmute, int rmute, 1963 int left, int right, int dir) 1964{ 1965 uint16_t v = 0; 1966 1967 if (sc == NULL) 1968 return; 1969 1970 if (left != right || lmute != rmute) { 1971 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 1972 (lmute << 7) | left; 1973 hdac_command(sc, 1974 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 1975 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 1976 (rmute << 7) | right; 1977 } else 1978 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 1979 (lmute << 7) | left; 1980 1981 hdac_command(sc, 1982 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 1983} 1984 1985static void 1986hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 1987 int left, int right) 1988{ 1989 struct hdac_softc *sc; 1990 nid_t nid, cad; 1991 int lmute, rmute; 1992 1993 if (ctl == NULL || ctl->widget == NULL || 1994 ctl->widget->devinfo == NULL || 1995 ctl->widget->devinfo->codec == NULL || 1996 ctl->widget->devinfo->codec->sc == NULL) 1997 return; 1998 1999 sc = ctl->widget->devinfo->codec->sc; 2000 cad = ctl->widget->devinfo->codec->cad; 2001 nid = ctl->widget->nid; 2002 2003 if (mute == HDA_AMP_MUTE_DEFAULT) { 2004 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2005 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2006 } else { 2007 lmute = HDA_AMP_LEFT_MUTED(mute); 2008 rmute = HDA_AMP_RIGHT_MUTED(mute); 2009 } 2010 2011 if (ctl->dir & HDA_CTL_OUT) 2012 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2013 lmute, rmute, left, right, 0); 2014 if (ctl->dir & HDA_CTL_IN) 2015 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2016 lmute, rmute, left, right, 1); 2017 ctl->left = left; 2018 ctl->right = right; 2019} 2020 2021static void 2022hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2023{ 2024 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2025 return; 2026 hdac_command(w->devinfo->codec->sc, 2027 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2028 w->nid, index), w->devinfo->codec->cad); 2029 w->selconn = index; 2030} 2031 2032 2033/**************************************************************************** 2034 * uint32_t hdac_command_sendone_internal 2035 * 2036 * Wrapper function that sends only one command to a given codec 2037 ****************************************************************************/ 2038static uint32_t 2039hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2040{ 2041 struct hdac_command_list cl; 2042 uint32_t response = 0xffffffff; 2043 2044 if (!mtx_owned(sc->lock)) 2045 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2046 cl.num_commands = 1; 2047 cl.verbs = &verb; 2048 cl.responses = &response; 2049 2050 hdac_command_send_internal(sc, &cl, cad); 2051 2052 return (response); 2053} 2054 2055/**************************************************************************** 2056 * hdac_command_send_internal 2057 * 2058 * Send a command list to the codec via the corb. We queue as much verbs as 2059 * we can and msleep on the codec. When the interrupt get the responses 2060 * back from the rirb, it will wake us up so we can queue the remaining verbs 2061 * if any. 2062 ****************************************************************************/ 2063static void 2064hdac_command_send_internal(struct hdac_softc *sc, 2065 struct hdac_command_list *commands, nid_t cad) 2066{ 2067 struct hdac_codec *codec; 2068 int corbrp; 2069 uint32_t *corb; 2070 uint8_t rirbwp; 2071 int timeout; 2072 int retry = 10; 2073 struct hdac_rirb *rirb_base, *rirb; 2074 nid_t ucad; 2075 uint32_t utag; 2076 2077 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL) 2078 return; 2079 2080 codec = sc->codecs[cad]; 2081 codec->commands = commands; 2082 codec->responses_received = 0; 2083 codec->verbs_sent = 0; 2084 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2085 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2086 2087 do { 2088 if (codec->verbs_sent != commands->num_commands) { 2089 /* Queue as many verbs as possible */ 2090 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2091 bus_dmamap_sync(sc->corb_dma.dma_tag, 2092 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2093 while (codec->verbs_sent != commands->num_commands && 2094 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2095 sc->corb_wp++; 2096 sc->corb_wp %= sc->corb_size; 2097 corb[sc->corb_wp] = 2098 commands->verbs[codec->verbs_sent++]; 2099 } 2100 2101 /* Send the verbs to the codecs */ 2102 bus_dmamap_sync(sc->corb_dma.dma_tag, 2103 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2104 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2105 } 2106 2107 timeout = 1000; 2108 do { 2109 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2110 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2111 BUS_DMASYNC_POSTREAD); 2112 if (sc->rirb_rp != rirbwp) { 2113 do { 2114 sc->rirb_rp++; 2115 sc->rirb_rp %= sc->rirb_size; 2116 rirb = &rirb_base[sc->rirb_rp]; 2117 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2118 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2119 utag = rirb->response >> 26; 2120 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 2121 sc->codecs[ucad] != NULL) { 2122 sc->unsolq[sc->unsolq_wp++] = 2123 (ucad << 16) | 2124 (utag & 0xffff); 2125 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2126 } 2127 } else if (codec->responses_received < commands->num_commands) 2128 codec->commands->responses[codec->responses_received++] = 2129 rirb->response; 2130 } while (sc->rirb_rp != rirbwp); 2131 break; 2132 } 2133 DELAY(10); 2134 } while (--timeout); 2135 } while ((codec->verbs_sent != commands->num_commands || 2136 codec->responses_received != commands->num_commands) && 2137 --retry); 2138 2139 if (retry == 0) 2140 device_printf(sc->dev, 2141 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2142 __func__, commands->num_commands, 2143 codec->verbs_sent, codec->responses_received); 2144 2145 codec->verbs_sent = 0; 2146 2147 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2148 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2149 while (sc->unsolq_rp != sc->unsolq_wp) { 2150 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 2151 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2152 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2153 hdac_unsolicited_handler(sc->codecs[ucad], utag); 2154 } 2155 sc->unsolq_st = HDAC_UNSOLQ_READY; 2156 } 2157} 2158 2159 2160/**************************************************************************** 2161 * Device Methods 2162 ****************************************************************************/ 2163 2164/**************************************************************************** 2165 * int hdac_probe(device_t) 2166 * 2167 * Probe for the presence of an hdac. If none is found, check for a generic 2168 * match using the subclass of the device. 2169 ****************************************************************************/ 2170static int 2171hdac_probe(device_t dev) 2172{ 2173 int i, result; 2174 uint32_t model, class, subclass; 2175 char desc[64]; 2176 2177 model = (uint32_t)pci_get_device(dev) << 16; 2178 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2179 class = pci_get_class(dev); 2180 subclass = pci_get_subclass(dev); 2181 2182 bzero(desc, sizeof(desc)); 2183 result = ENXIO; 2184 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2185 if (hdac_devices[i].model == model) { 2186 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2187 result = BUS_PROBE_DEFAULT; 2188 break; 2189 } 2190 if ((hdac_devices[i].model & model) == model && 2191 class == PCIC_MULTIMEDIA && 2192 subclass == PCIS_MULTIMEDIA_HDA) { 2193 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2194 result = BUS_PROBE_GENERIC; 2195 break; 2196 } 2197 } 2198 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2199 subclass == PCIS_MULTIMEDIA_HDA) { 2200 strlcpy(desc, "Generic", sizeof(desc)); 2201 result = BUS_PROBE_GENERIC; 2202 } 2203 if (result != ENXIO) { 2204 strlcat(desc, " High Definition Audio Controller", 2205 sizeof(desc)); 2206 device_set_desc_copy(dev, desc); 2207 } 2208 2209 return (result); 2210} 2211 2212static void * 2213hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2214 struct pcm_channel *c, int dir) 2215{ 2216 struct hdac_devinfo *devinfo = data; 2217 struct hdac_softc *sc = devinfo->codec->sc; 2218 struct hdac_chan *ch; 2219 2220 hdac_lock(sc); 2221 if (dir == PCMDIR_PLAY) { 2222 ch = &sc->play; 2223 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2224 ch->dir = PCMDIR_PLAY; 2225 ch->sid = ++sc->streamcnt; 2226 devinfo->function.audio.playcnt++; 2227 } else { 2228 ch = &sc->rec; 2229 ch->off = devinfo->function.audio.reccnt << 5; 2230 ch->dir = PCMDIR_REC; 2231 ch->sid = ++sc->streamcnt; 2232 devinfo->function.audio.reccnt++; 2233 } 2234 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2235 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2236 ch->pcmrates[0] = 48000; 2237 ch->pcmrates[1] = 0; 2238 } 2239 ch->b = b; 2240 ch->c = c; 2241 ch->devinfo = devinfo; 2242 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2243 ch->blkcnt = sc->chan_blkcnt; 2244 hdac_unlock(sc); 2245 2246 if (hdac_bdl_alloc(ch) != 0) { 2247 ch->blkcnt = 0; 2248 return (NULL); 2249 } 2250 2251 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2252 return (NULL); 2253 2254 hdac_dma_nocache(ch->b->buf); 2255 2256 return (ch); 2257} 2258 2259static int 2260hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2261{ 2262 struct hdac_chan *ch = data; 2263 int i; 2264 2265 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2266 if (format == ch->caps.fmtlist[i]) { 2267 ch->fmt = format; 2268 return (0); 2269 } 2270 } 2271 2272 return (EINVAL); 2273} 2274 2275static int 2276hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2277{ 2278 struct hdac_chan *ch = data; 2279 uint32_t spd = 0; 2280 int i; 2281 2282 for (i = 0; ch->pcmrates[i] != 0; i++) { 2283 spd = ch->pcmrates[i]; 2284 if (spd >= speed) 2285 break; 2286 } 2287 2288 if (spd == 0) 2289 ch->spd = 48000; 2290 else 2291 ch->spd = spd; 2292 2293 return (ch->spd); 2294} 2295 2296static void 2297hdac_stream_setup(struct hdac_chan *ch) 2298{ 2299 struct hdac_softc *sc = ch->devinfo->codec->sc; 2300 int i; 2301 nid_t cad = ch->devinfo->codec->cad; 2302 uint16_t fmt; 2303 2304 /* 2305 * 8bit = 0 2306 * 16bit = 1 2307 * 20bit = 2 2308 * 24bit = 3 2309 * 32bit = 4 2310 */ 2311 fmt = 0; 2312 if (ch->fmt & AFMT_S16_LE) 2313 fmt |= ch->bit16 << 4; 2314 else if (ch->fmt & AFMT_S32_LE) 2315 fmt |= ch->bit32 << 4; 2316 else 2317 fmt |= 1 << 4; 2318 2319 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2320 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2321 fmt |= hda_rate_tab[i].base; 2322 fmt |= hda_rate_tab[i].mul; 2323 fmt |= hda_rate_tab[i].div; 2324 break; 2325 } 2326 } 2327 2328 if (ch->fmt & AFMT_STEREO) 2329 fmt |= 1; 2330 2331 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2332 2333 for (i = 0; ch->io[i] != -1; i++) { 2334 HDA_BOOTVERBOSE_MSG( 2335 device_printf(sc->dev, 2336 "PCMDIR_%s: Stream setup nid=%d fmt=0x%08x\n", 2337 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2338 ch->io[i], fmt); 2339 ); 2340 hdac_command(sc, 2341 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2342 hdac_command(sc, 2343 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2344 ch->sid << 4), cad); 2345 } 2346} 2347 2348static int 2349hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 2350{ 2351 struct hdac_chan *ch = data; 2352 2353 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz); 2354 2355 return (ch->blksz); 2356} 2357 2358static void 2359hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2360{ 2361 struct hdac_devinfo *devinfo = ch->devinfo; 2362 nid_t cad = devinfo->codec->cad; 2363 int i; 2364 2365 hdac_stream_stop(ch); 2366 2367 for (i = 0; ch->io[i] != -1; i++) { 2368 hdac_command(sc, 2369 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2370 0), cad); 2371 } 2372} 2373 2374static void 2375hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2376{ 2377 ch->ptr = 0; 2378 ch->prevptr = 0; 2379 hdac_stream_stop(ch); 2380 hdac_stream_reset(ch); 2381 hdac_bdl_setup(ch); 2382 hdac_stream_setid(ch); 2383 hdac_stream_setup(ch); 2384 hdac_stream_start(ch); 2385} 2386 2387static int 2388hdac_channel_trigger(kobj_t obj, void *data, int go) 2389{ 2390 struct hdac_chan *ch = data; 2391 struct hdac_softc *sc = ch->devinfo->codec->sc; 2392 2393 hdac_lock(sc); 2394 switch (go) { 2395 case PCMTRIG_START: 2396 hdac_channel_start(sc, ch); 2397 break; 2398 case PCMTRIG_STOP: 2399 case PCMTRIG_ABORT: 2400 hdac_channel_stop(sc, ch); 2401 break; 2402 } 2403 hdac_unlock(sc); 2404 2405 return (0); 2406} 2407 2408static int 2409hdac_channel_getptr(kobj_t obj, void *data) 2410{ 2411 struct hdac_chan *ch = data; 2412 struct hdac_softc *sc = ch->devinfo->codec->sc; 2413 int sz, delta; 2414 uint32_t ptr; 2415 2416 hdac_lock(sc); 2417 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2418 hdac_unlock(sc); 2419 2420 sz = sndbuf_getsize(ch->b); 2421 ptr %= sz; 2422 2423 if (ch->dir == PCMDIR_REC) { 2424 delta = ptr % sndbuf_getblksz(ch->b); 2425 if (delta != 0) { 2426 ptr -= delta; 2427 if (ptr < delta) 2428 ptr = sz - delta; 2429 else 2430 ptr -= delta; 2431 } 2432 } 2433 2434 return (ptr); 2435} 2436 2437static struct pcmchan_caps * 2438hdac_channel_getcaps(kobj_t obj, void *data) 2439{ 2440 return (&((struct hdac_chan *)data)->caps); 2441} 2442 2443static kobj_method_t hdac_channel_methods[] = { 2444 KOBJMETHOD(channel_init, hdac_channel_init), 2445 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2446 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2447 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2448 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2449 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2450 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2451 { 0, 0 } 2452}; 2453CHANNEL_DECLARE(hdac_channel); 2454 2455static int 2456hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2457{ 2458 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2459 struct hdac_softc *sc = devinfo->codec->sc; 2460 struct hdac_widget *w, *cw; 2461 struct hdac_audio_ctl *ctl; 2462 uint32_t mask, recmask, id; 2463 int i, j, softpcmvol; 2464 nid_t cad; 2465 2466 if (resource_int_value(device_get_name(sc->dev), 2467 device_get_unit(sc->dev), "softpcmvol", &softpcmvol) == 0) 2468 softpcmvol = (softpcmvol != 0) ? 1 : 0; 2469 else 2470 softpcmvol = (devinfo->function.audio.quirks & 2471 HDA_QUIRK_SOFTPCMVOL) ? 2472 1 : 0; 2473 2474 hdac_lock(sc); 2475 2476 mask = 0; 2477 recmask = 0; 2478 2479 id = hdac_codec_id(devinfo); 2480 cad = devinfo->codec->cad; 2481 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2482 if (!((hdac_hp_switch[i].vendormask & sc->pci_subvendor) == 2483 sc->pci_subvendor && 2484 hdac_hp_switch[i].id == id)) 2485 continue; 2486 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2487 if (w != NULL && w->enable != 0 2488 && w->type == 2489 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2490 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2491 hdac_command(sc, 2492 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2493 w->nid, 2494 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2495 HDAC_UNSOLTAG_EVENT_HP), cad); 2496 hdac_hp_switch_handler(devinfo); 2497 } 2498 break; 2499 } 2500 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2501 if (!((hdac_eapd_switch[i].vendormask & sc->pci_subvendor) == 2502 sc->pci_subvendor && hdac_eapd_switch[i].id == id)) 2503 continue; 2504 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2505 if (w == NULL || w->enable == 0) 2506 break; 2507 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2508 w->param.eapdbtl == 0xffffffff) 2509 break; 2510 mask |= SOUND_MASK_OGAIN; 2511 break; 2512 } 2513 2514 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2515 w = hdac_widget_get(devinfo, i); 2516 if (w == NULL || w->enable == 0) 2517 continue; 2518 mask |= w->ctlflags; 2519 if (!(w->pflags & HDA_ADC_RECSEL)) 2520 continue; 2521 for (j = 0; j < w->nconns; j++) { 2522 cw = hdac_widget_get(devinfo, w->conns[j]); 2523 if (cw == NULL || cw->enable == 0) 2524 continue; 2525 recmask |= cw->ctlflags; 2526 } 2527 } 2528 2529 if (!(mask & SOUND_MASK_PCM)) { 2530 softpcmvol = 1; 2531 mask |= SOUND_MASK_PCM; 2532 } 2533 2534 i = 0; 2535 ctl = NULL; 2536 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2537 if (ctl->widget == NULL || ctl->enable == 0) 2538 continue; 2539 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2540 continue; 2541 if (ctl->step > 0) 2542 break; 2543 } 2544 2545 if (softpcmvol == 1 || ctl == NULL) { 2546 struct snddev_info *d = NULL; 2547 d = device_get_softc(sc->dev); 2548 if (d != NULL) { 2549 d->flags |= SD_F_SOFTPCMVOL; 2550 HDA_BOOTVERBOSE_MSG( 2551 device_printf(sc->dev, 2552 "%s Soft PCM volume\n", 2553 (softpcmvol == 1) ? 2554 "Forcing" : "Enabling"); 2555 ); 2556 } 2557 i = 0; 2558 /* 2559 * XXX Temporary quirk for STAC9220, until the parser 2560 * become smarter. 2561 */ 2562 if (id == HDA_CODEC_STAC9220) { 2563 mask |= SOUND_MASK_VOLUME; 2564 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2565 NULL) { 2566 if (ctl->widget == NULL || ctl->enable == 0) 2567 continue; 2568 if (ctl->widget->nid == 11 && ctl->index == 0) { 2569 ctl->ossmask = SOUND_MASK_VOLUME; 2570 ctl->ossval = 100 | (100 << 8); 2571 } else 2572 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2573 } 2574 } else { 2575 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2576 SOUND_MASK_PCM); 2577 if (!(mask & SOUND_MASK_VOLUME)) 2578 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2579 SOUND_MIXER_NONE); 2580 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2581 NULL) { 2582 if (ctl->widget == NULL || ctl->enable == 0) 2583 continue; 2584 if ((ctl->ossmask & (SOUND_MASK_VOLUME | 2585 SOUND_MASK_PCM)) != (SOUND_MASK_VOLUME | 2586 SOUND_MASK_PCM)) 2587 continue; 2588 if (!(ctl->mute == 1 && ctl->step == 0)) 2589 ctl->enable = 0; 2590 } 2591 } 2592 } 2593 2594 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2595 2596 mix_setrecdevs(m, recmask); 2597 mix_setdevs(m, mask); 2598 2599 hdac_unlock(sc); 2600 2601 return (0); 2602} 2603 2604static int 2605hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2606 unsigned left, unsigned right) 2607{ 2608 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2609 struct hdac_softc *sc = devinfo->codec->sc; 2610 struct hdac_widget *w; 2611 struct hdac_audio_ctl *ctl; 2612 uint32_t id, mute; 2613 int lvol, rvol, mlvol, mrvol; 2614 int i = 0; 2615 2616 hdac_lock(sc); 2617 if (dev == SOUND_MIXER_OGAIN) { 2618 /*if (left != right || !(left == 0 || left == 1)) { 2619 hdac_unlock(sc); 2620 return (-1); 2621 }*/ 2622 id = hdac_codec_id(devinfo); 2623 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2624 if ((hdac_eapd_switch[i].vendormask & 2625 sc->pci_subvendor) == sc->pci_subvendor && 2626 hdac_eapd_switch[i].id == id) 2627 break; 2628 } 2629 if (i >= HDAC_EAPD_SWITCH_LEN) { 2630 hdac_unlock(sc); 2631 return (-1); 2632 } 2633 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2634 if (w == NULL || 2635 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2636 w->param.eapdbtl == 0xffffffff) { 2637 hdac_unlock(sc); 2638 return (-1); 2639 } 2640 if (left == 0) 2641 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2642 else 2643 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2644 if (hdac_eapd_switch[i].hp_switch != 0) 2645 hdac_hp_switch_handler(devinfo); 2646 hdac_command(sc, 2647 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, w->nid, 2648 w->param.eapdbtl), devinfo->codec->cad); 2649 hdac_unlock(sc); 2650 return (left | (left << 8)); 2651 } 2652 if (dev == SOUND_MIXER_VOLUME) 2653 devinfo->function.audio.mvol = left | (right << 8); 2654 2655 mlvol = devinfo->function.audio.mvol & 0x7f; 2656 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2657 lvol = 0; 2658 rvol = 0; 2659 2660 i = 0; 2661 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2662 if (ctl->widget == NULL || ctl->enable == 0 || 2663 !(ctl->ossmask & (1 << dev))) 2664 continue; 2665 switch (dev) { 2666 case SOUND_MIXER_VOLUME: 2667 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2668 lvol = (lvol * ctl->step) / 100; 2669 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2670 rvol = (rvol * ctl->step) / 100; 2671 break; 2672 default: 2673 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2674 lvol = (left * mlvol) / 100; 2675 lvol = (lvol * ctl->step) / 100; 2676 rvol = (right * mrvol) / 100; 2677 rvol = (rvol * ctl->step) / 100; 2678 } else { 2679 lvol = (left * ctl->step) / 100; 2680 rvol = (right * ctl->step) / 100; 2681 } 2682 ctl->ossval = left | (right << 8); 2683 break; 2684 } 2685 mute = 0; 2686 if (ctl->step < 1) { 2687 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2688 (ctl->muted & HDA_AMP_MUTE_LEFT); 2689 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2690 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2691 } else { 2692 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2693 (ctl->muted & HDA_AMP_MUTE_LEFT); 2694 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2695 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2696 } 2697 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2698 } 2699 hdac_unlock(sc); 2700 2701 return (left | (right << 8)); 2702} 2703 2704static int 2705hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2706{ 2707 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2708 struct hdac_widget *w, *cw; 2709 struct hdac_softc *sc = devinfo->codec->sc; 2710 uint32_t ret = src, target; 2711 int i, j; 2712 2713 target = 0; 2714 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2715 if (src & (1 << i)) { 2716 target = 1 << i; 2717 break; 2718 } 2719 } 2720 2721 hdac_lock(sc); 2722 2723 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2724 w = hdac_widget_get(devinfo, i); 2725 if (w == NULL && w->enable == 0) 2726 continue; 2727 if (!(w->pflags & HDA_ADC_RECSEL)) 2728 continue; 2729 for (j = 0; j < w->nconns; j++) { 2730 cw = hdac_widget_get(devinfo, w->conns[j]); 2731 if (cw == NULL || cw->enable == 0) 2732 continue; 2733 if ((target == SOUND_MASK_VOLUME && 2734 cw->type != 2735 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 2736 (target != SOUND_MASK_VOLUME && 2737 cw->type == 2738 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 2739 continue; 2740 if (cw->ctlflags & target) { 2741 hdac_widget_connection_select(w, j); 2742 ret = target; 2743 j += w->nconns; 2744 } 2745 } 2746 } 2747 2748 hdac_unlock(sc); 2749 2750 return (ret); 2751} 2752 2753static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 2754 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 2755 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 2756 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 2757 { 0, 0 } 2758}; 2759MIXER_DECLARE(hdac_audio_ctl_ossmixer); 2760 2761/**************************************************************************** 2762 * int hdac_attach(device_t) 2763 * 2764 * Attach the device into the kernel. Interrupts usually won't be enabled 2765 * when this function is called. Setup everything that doesn't require 2766 * interrupts and defer probing of codecs until interrupts are enabled. 2767 ****************************************************************************/ 2768static int 2769hdac_attach(device_t dev) 2770{ 2771 struct hdac_softc *sc; 2772 int result; 2773 int i = 0; 2774 2775 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 2776 if (sc == NULL) { 2777 device_printf(dev, "cannot allocate softc\n"); 2778 return (ENOMEM); 2779 } 2780 sc->dev = dev; 2781 sc->pci_subvendor = pci_get_subdevice(sc->dev) << 16; 2782 sc->pci_subvendor |= pci_get_subvendor(sc->dev); 2783 2784 sc->chan_size = pcm_getbuffersize(dev, 2785 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT); 2786 if (resource_int_value(device_get_name(sc->dev), 2787 device_get_unit(sc->dev), "blocksize", &i) == 0 && 2788 i > 0) { 2789 sc->chan_blkcnt = sc->chan_size / i; 2790 i = 0; 2791 while (sc->chan_blkcnt >> i) 2792 i++; 2793 sc->chan_blkcnt = 1 << (i - 1); 2794 if (sc->chan_blkcnt < HDA_BDL_MIN) 2795 sc->chan_blkcnt = HDA_BDL_MIN; 2796 else if (sc->chan_blkcnt > HDA_BDL_MAX) 2797 sc->chan_blkcnt = HDA_BDL_MAX; 2798 } else 2799 sc->chan_blkcnt = HDA_BDL_DEFAULT; 2800 2801 result = bus_dma_tag_create(NULL, /* parent */ 2802 HDAC_DMA_ALIGNMENT, /* alignment */ 2803 0, /* boundary */ 2804 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2805 BUS_SPACE_MAXADDR, /* highaddr */ 2806 NULL, /* filtfunc */ 2807 NULL, /* fistfuncarg */ 2808 sc->chan_size, /* maxsize */ 2809 1, /* nsegments */ 2810 sc->chan_size, /* maxsegsz */ 2811 0, /* flags */ 2812 NULL, /* lockfunc */ 2813 NULL, /* lockfuncarg */ 2814 &sc->chan_dmat); /* dmat */ 2815 if (result != 0) { 2816 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 2817 __func__, result); 2818 free(sc, M_DEVBUF); 2819 return (ENXIO); 2820 } 2821 2822 2823 sc->hdabus = NULL; 2824 for (i = 0; i < HDAC_CODEC_MAX; i++) 2825 sc->codecs[i] = NULL; 2826 2827 pci_enable_busmaster(dev); 2828 2829 /* Initialize driver mutex */ 2830 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 2831 2832 /* Allocate resources */ 2833 result = hdac_mem_alloc(sc); 2834 if (result != 0) 2835 goto fail; 2836 result = hdac_irq_alloc(sc); 2837 if (result != 0) 2838 goto fail; 2839 2840 /* Get Capabilities */ 2841 result = hdac_get_capabilities(sc); 2842 if (result != 0) 2843 goto fail; 2844 2845 /* Allocate CORB and RIRB dma memory */ 2846 result = hdac_dma_alloc(sc, &sc->corb_dma, 2847 sc->corb_size * sizeof(uint32_t)); 2848 if (result != 0) 2849 goto fail; 2850 result = hdac_dma_alloc(sc, &sc->rirb_dma, 2851 sc->rirb_size * sizeof(struct hdac_rirb)); 2852 if (result != 0) 2853 goto fail; 2854 2855 /* Quiesce everything */ 2856 hdac_reset(sc); 2857 2858 /* Disable PCI-Express QOS */ 2859 pci_write_config(sc->dev, 0x44, 2860 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 2861 2862 /* Initialize the CORB and RIRB */ 2863 hdac_corb_init(sc); 2864 hdac_rirb_init(sc); 2865 2866 /* Defer remaining of initialization until interrupts are enabled */ 2867 sc->intrhook.ich_func = hdac_attach2; 2868 sc->intrhook.ich_arg = (void *)sc; 2869 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 2870 sc->intrhook.ich_func = NULL; 2871 hdac_attach2((void *)sc); 2872 } 2873 2874 return(0); 2875 2876fail: 2877 hdac_dma_free(&sc->rirb_dma); 2878 hdac_dma_free(&sc->corb_dma); 2879 hdac_irq_free(sc); 2880 hdac_mem_free(sc); 2881 snd_mtxfree(sc->lock); 2882 2883 return(ENXIO); 2884} 2885 2886static void 2887hdac_audio_parse(struct hdac_devinfo *devinfo) 2888{ 2889 struct hdac_softc *sc = devinfo->codec->sc; 2890 struct hdac_widget *w; 2891 uint32_t res; 2892 int i; 2893 nid_t cad, nid; 2894 2895 cad = devinfo->codec->cad; 2896 nid = devinfo->nid; 2897 2898 hdac_command(sc, 2899 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 2900 2901 DELAY(100); 2902 2903 res = hdac_command(sc, 2904 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2905 2906 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2907 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2908 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2909 2910 HDA_BOOTVERBOSE_MSG( 2911 device_printf(sc->dev, " Vendor: 0x%08x\n", 2912 devinfo->vendor_id); 2913 device_printf(sc->dev, " Device: 0x%08x\n", 2914 devinfo->device_id); 2915 device_printf(sc->dev, " Revision: 0x%08x\n", 2916 devinfo->revision_id); 2917 device_printf(sc->dev, " Stepping: 0x%08x\n", 2918 devinfo->stepping_id); 2919 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2920 sc->pci_subvendor); 2921 device_printf(sc->dev, " Nodes: start=%d " 2922 "endnode=%d total=%d\n", 2923 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 2924 ); 2925 2926 res = hdac_command(sc, 2927 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 2928 cad); 2929 devinfo->function.audio.supp_stream_formats = res; 2930 2931 res = hdac_command(sc, 2932 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 2933 cad); 2934 devinfo->function.audio.supp_pcm_size_rate = res; 2935 2936 res = hdac_command(sc, 2937 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 2938 cad); 2939 devinfo->function.audio.outamp_cap = res; 2940 2941 res = hdac_command(sc, 2942 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 2943 cad); 2944 devinfo->function.audio.inamp_cap = res; 2945 2946 if (devinfo->nodecnt > 0) { 2947 hdac_unlock(sc); 2948 devinfo->widget = (struct hdac_widget *)malloc( 2949 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2950 M_NOWAIT | M_ZERO); 2951 hdac_lock(sc); 2952 } else 2953 devinfo->widget = NULL; 2954 2955 if (devinfo->widget == NULL) { 2956 device_printf(sc->dev, "unable to allocate widgets!\n"); 2957 devinfo->endnode = devinfo->startnode; 2958 devinfo->nodecnt = 0; 2959 return; 2960 } 2961 2962 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2963 w = hdac_widget_get(devinfo, i); 2964 if (w == NULL) 2965 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 2966 else { 2967 w->devinfo = devinfo; 2968 w->nid = i; 2969 w->enable = 1; 2970 w->selconn = -1; 2971 w->pflags = 0; 2972 w->ctlflags = 0; 2973 w->param.eapdbtl = 0xffffffff; 2974 hdac_widget_parse(w); 2975 } 2976 } 2977} 2978 2979static void 2980hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 2981{ 2982 struct hdac_softc *sc = devinfo->codec->sc; 2983 struct hdac_audio_ctl *ctls; 2984 struct hdac_widget *w, *cw; 2985 int i, j, cnt, max, ocap, icap; 2986 2987 /* XXX This is redundant */ 2988 max = 0; 2989 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2990 w = hdac_widget_get(devinfo, i); 2991 if (w == NULL || w->enable == 0) 2992 continue; 2993 if (w->param.outamp_cap != 0) 2994 max++; 2995 if (w->param.inamp_cap != 0) { 2996 switch (w->type) { 2997 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2998 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2999 for (j = 0; j < w->nconns; j++) { 3000 cw = hdac_widget_get(devinfo, 3001 w->conns[j]); 3002 if (cw == NULL || cw->enable == 0) 3003 continue; 3004 max++; 3005 } 3006 break; 3007 default: 3008 max++; 3009 break; 3010 } 3011 } 3012 } 3013 3014 devinfo->function.audio.ctlcnt = max; 3015 3016 if (max < 1) 3017 return; 3018 3019 hdac_unlock(sc); 3020 ctls = (struct hdac_audio_ctl *)malloc( 3021 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3022 hdac_lock(sc); 3023 3024 if (ctls == NULL) { 3025 /* Blekh! */ 3026 device_printf(sc->dev, "unable to allocate ctls!\n"); 3027 devinfo->function.audio.ctlcnt = 0; 3028 return; 3029 } 3030 3031 cnt = 0; 3032 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3033 if (cnt >= max) { 3034 device_printf(sc->dev, "%s: Ctl overflow!\n", 3035 __func__); 3036 break; 3037 } 3038 w = hdac_widget_get(devinfo, i); 3039 if (w == NULL || w->enable == 0) 3040 continue; 3041 ocap = w->param.outamp_cap; 3042 icap = w->param.inamp_cap; 3043 if (ocap != 0) { 3044 ctls[cnt].enable = 1; 3045 ctls[cnt].widget = w; 3046 ctls[cnt].mute = 3047 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3048 ctls[cnt].step = 3049 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3050 ctls[cnt].size = 3051 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3052 ctls[cnt].offset = 3053 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3054 ctls[cnt].left = ctls[cnt].offset; 3055 ctls[cnt].right = ctls[cnt].offset; 3056 ctls[cnt++].dir = HDA_CTL_OUT; 3057 } 3058 3059 if (icap != 0) { 3060 switch (w->type) { 3061 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3062 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3063 for (j = 0; j < w->nconns; j++) { 3064 if (cnt >= max) { 3065 device_printf(sc->dev, 3066 "%s: Ctl overflow!\n", 3067 __func__); 3068 break; 3069 } 3070 cw = hdac_widget_get(devinfo, 3071 w->conns[j]); 3072 if (cw == NULL || cw->enable == 0) 3073 continue; 3074 ctls[cnt].enable = 1; 3075 ctls[cnt].widget = w; 3076 ctls[cnt].childwidget = cw; 3077 ctls[cnt].index = j; 3078 ctls[cnt].mute = 3079 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(icap); 3080 ctls[cnt].step = 3081 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(icap); 3082 ctls[cnt].size = 3083 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(icap); 3084 ctls[cnt].offset = 3085 HDA_PARAM_INPUT_AMP_CAP_OFFSET(icap); 3086 ctls[cnt].left = ctls[cnt].offset; 3087 ctls[cnt].right = ctls[cnt].offset; 3088 ctls[cnt++].dir = HDA_CTL_IN; 3089 } 3090 break; 3091 default: 3092 if (cnt >= max) { 3093 device_printf(sc->dev, 3094 "%s: Ctl overflow!\n", 3095 __func__); 3096 break; 3097 } 3098 ctls[cnt].enable = 1; 3099 ctls[cnt].widget = w; 3100 ctls[cnt].mute = 3101 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(icap); 3102 ctls[cnt].step = 3103 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(icap); 3104 ctls[cnt].size = 3105 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(icap); 3106 ctls[cnt].offset = 3107 HDA_PARAM_INPUT_AMP_CAP_OFFSET(icap); 3108 ctls[cnt].left = ctls[cnt].offset; 3109 ctls[cnt].right = ctls[cnt].offset; 3110 ctls[cnt++].dir = HDA_CTL_IN; 3111 break; 3112 } 3113 } 3114 } 3115 3116 devinfo->function.audio.ctl = ctls; 3117} 3118 3119static void 3120hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3121{ 3122 struct hdac_widget *w; 3123 uint32_t id; 3124 int i; 3125 3126 /* 3127 * XXX Fixed rate quirk. Other than 48000 3128 * sounds pretty much like train wreck. 3129 */ 3130 devinfo->function.audio.quirks |= HDA_QUIRK_FIXEDRATE; 3131 /* 3132 * XXX Force stereo quirk. Monoural recording / playback 3133 * on few codecs (especially ALC880) seems broken or 3134 * or perhaps unsupported. 3135 */ 3136 devinfo->function.audio.quirks |= HDA_QUIRK_FORCESTEREO; 3137 id = hdac_codec_id(devinfo); 3138 switch (id) { 3139 case HDA_CODEC_ALC260: 3140 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3141 w = hdac_widget_get(devinfo, i); 3142 if (w == NULL || w->enable == 0) 3143 continue; 3144 if (w->type != 3145 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3146 continue; 3147 if (w->nid != 5) 3148 w->enable = 0; 3149 } 3150 break; 3151 case HDA_CODEC_ALC880: 3152 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3153 w = hdac_widget_get(devinfo, i); 3154 if (w == NULL || w->enable == 0) 3155 continue; 3156 if (w->type == 3157 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3158 w->nid != 9 && w->nid != 29) { 3159 w->enable = 0; 3160 } else if (w->type != 3161 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3162 w->nid == 29) { 3163 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3164 w->param.widget_cap &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3165 w->param.widget_cap |= 3166 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3167 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3168 strlcpy(w->name, "beep widget", sizeof(w->name)); 3169 } 3170 } 3171 break; 3172 case HDA_CODEC_AD1986A: 3173 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3174 w = hdac_widget_get(devinfo, i); 3175 if (w == NULL || w->enable == 0) 3176 continue; 3177 if (w->type != 3178 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3179 continue; 3180 if (w->nid != 3) 3181 w->enable = 0; 3182 } 3183 break; 3184 case HDA_CODEC_STAC9221: 3185 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3186 w = hdac_widget_get(devinfo, i); 3187 if (w == NULL || w->enable == 0) 3188 continue; 3189 if (w->type != 3190 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3191 continue; 3192 if (w->nid != 2) 3193 w->enable = 0; 3194 } 3195 break; 3196 case HDA_CODEC_STAC9221D: 3197 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3198 w = hdac_widget_get(devinfo, i); 3199 if (w == NULL || w->enable == 0) 3200 continue; 3201 if (w->type == 3202 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3203 w->nid != 6) 3204 w->enable = 0; 3205 3206 } 3207 break; 3208 case HDA_CODEC_CXVENICE: 3209 devinfo->function.audio.quirks &= ~HDA_QUIRK_FORCESTEREO; 3210 break; 3211 default: 3212 break; 3213 } 3214 if ((HDA_CODEC_STACXXXX & id) == id) { 3215 /* Sigmatel codecs need soft PCM volume emulation */ 3216 devinfo->function.audio.quirks |= HDA_QUIRK_SOFTPCMVOL; 3217 } 3218 if ((ACER_ALL_SUBVENDOR & devinfo->codec->sc->pci_subvendor) == 3219 devinfo->codec->sc->pci_subvendor) { 3220 /* Acer */ 3221 devinfo->function.audio.quirks |= HDA_QUIRK_GPIO1; 3222 } 3223} 3224 3225static int 3226hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3227{ 3228 int *dev = &devinfo->function.audio.ossidx; 3229 3230 while (*dev < SOUND_MIXER_NRDEVICES) { 3231 switch (*dev) { 3232 case SOUND_MIXER_VOLUME: 3233 case SOUND_MIXER_BASS: 3234 case SOUND_MIXER_TREBLE: 3235 case SOUND_MIXER_PCM: 3236 case SOUND_MIXER_SPEAKER: 3237 case SOUND_MIXER_LINE: 3238 case SOUND_MIXER_MIC: 3239 case SOUND_MIXER_CD: 3240 case SOUND_MIXER_RECLEV: 3241 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3242 (*dev)++; 3243 break; 3244 default: 3245 return (*dev)++; 3246 break; 3247 } 3248 } 3249 3250 return (-1); 3251} 3252 3253static int 3254hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3255{ 3256 struct hdac_widget *w; 3257 int i, ret = 0; 3258 3259 if (depth > HDA_PARSE_MAXDEPTH) 3260 return (0); 3261 w = hdac_widget_get(devinfo, nid); 3262 if (w == NULL || w->enable == 0) 3263 return (0); 3264 switch (w->type) { 3265 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3266 w->pflags |= HDA_DAC_PATH; 3267 ret = 1; 3268 break; 3269 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3270 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3271 for (i = 0; i < w->nconns; i++) { 3272 if (hdac_widget_find_dac_path(devinfo, 3273 w->conns[i], depth + 1) != 0) { 3274 if (w->selconn == -1) 3275 w->selconn = i; 3276 ret = 1; 3277 w->pflags |= HDA_DAC_PATH; 3278 } 3279 } 3280 break; 3281 default: 3282 break; 3283 } 3284 return (ret); 3285} 3286 3287static int 3288hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3289{ 3290 struct hdac_widget *w; 3291 int i, conndev, ret = 0; 3292 3293 if (depth > HDA_PARSE_MAXDEPTH) 3294 return (0); 3295 w = hdac_widget_get(devinfo, nid); 3296 if (w == NULL || w->enable == 0) 3297 return (0); 3298 switch (w->type) { 3299 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3300 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3301 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3302 for (i = 0; i < w->nconns; i++) { 3303 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3304 depth + 1) != 0) { 3305 if (w->selconn == -1) 3306 w->selconn = i; 3307 w->pflags |= HDA_ADC_PATH; 3308 ret = 1; 3309 } 3310 } 3311 break; 3312 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3313 conndev = w->wclass.pin.config & 3314 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3315 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3316 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3317 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3318 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3319 w->pflags |= HDA_ADC_PATH; 3320 ret = 1; 3321 } 3322 break; 3323 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3324 if (w->pflags & HDA_DAC_PATH) { 3325 w->pflags |= HDA_ADC_PATH; 3326 ret = 1; 3327 } 3328 break;*/ 3329 default: 3330 break; 3331 } 3332 return (ret); 3333} 3334 3335static uint32_t 3336hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3337 nid_t nid, nid_t pnid, int index, int depth) 3338{ 3339 struct hdac_widget *w, *pw; 3340 struct hdac_audio_ctl *ctl; 3341 uint32_t fl = 0; 3342 int i, ossdev, conndev, strategy; 3343 3344 if (depth > HDA_PARSE_MAXDEPTH) 3345 return (0); 3346 3347 w = hdac_widget_get(devinfo, nid); 3348 if (w == NULL || w->enable == 0) 3349 return (0); 3350 3351 pw = hdac_widget_get(devinfo, pnid); 3352 strategy = devinfo->function.audio.parsing_strategy; 3353 3354 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3355 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3356 for (i = 0; i < w->nconns; i++) { 3357 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3358 w->nid, i, depth + 1); 3359 } 3360 w->ctlflags |= fl; 3361 return (fl); 3362 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3363 (w->pflags & HDA_DAC_PATH)) { 3364 i = 0; 3365 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3366 if (ctl->enable == 0 || ctl->widget == NULL) 3367 continue; 3368 if ((ctl->widget->nid == w->nid) || 3369 (ctl->widget->nid == pnid && ctl->index == index && 3370 (ctl->dir & HDA_CTL_IN)) || 3371 (ctl->widget->nid == pnid && pw != NULL && 3372 pw->type == 3373 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3374 (pw->nconns < 2 || pw->selconn == index || 3375 pw->selconn == -1) && 3376 (ctl->dir & HDA_CTL_OUT)) || 3377 (strategy == HDA_PARSE_DIRECT && 3378 ctl->widget->nid == w->nid)) { 3379 if (pw != NULL && pw->selconn == -1) 3380 pw->selconn = index; 3381 fl |= SOUND_MASK_VOLUME; 3382 fl |= SOUND_MASK_PCM; 3383 ctl->ossmask |= SOUND_MASK_VOLUME; 3384 ctl->ossmask |= SOUND_MASK_PCM; 3385 ctl->ossdev = SOUND_MIXER_PCM; 3386 } 3387 } 3388 w->ctlflags |= fl; 3389 return (fl); 3390 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 3391 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3392 (w->pflags & HDA_ADC_PATH)) { 3393 conndev = w->wclass.pin.config & 3394 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3395 i = 0; 3396 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3397 if (ctl->enable == 0 || ctl->widget == NULL) 3398 continue; 3399 if (((ctl->widget->nid == pnid && ctl->index == index && 3400 (ctl->dir & HDA_CTL_IN)) || 3401 (ctl->widget->nid == pnid && pw != NULL && 3402 pw->type == 3403 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3404 (pw->nconns < 2 || pw->selconn == index || 3405 pw->selconn == -1) && 3406 (ctl->dir & HDA_CTL_OUT)) || 3407 (strategy == HDA_PARSE_DIRECT && 3408 ctl->widget->nid == w->nid)) && 3409 (ctl->ossmask & ~SOUND_MASK_VOLUME) == 0) { 3410 if (pw != NULL && pw->selconn == -1) 3411 pw->selconn = index; 3412 ossdev = 0; 3413 switch (conndev) { 3414 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3415 ossdev = SOUND_MIXER_MIC; 3416 break; 3417 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3418 ossdev = SOUND_MIXER_LINE; 3419 break; 3420 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3421 ossdev = SOUND_MIXER_CD; 3422 break; 3423 default: 3424 ossdev = 3425 hdac_audio_ctl_ossmixer_getnextdev( 3426 devinfo); 3427 if (ossdev < 0) 3428 ossdev = 0; 3429 break; 3430 } 3431 if (strategy == HDA_PARSE_MIXER) { 3432 fl |= SOUND_MASK_VOLUME; 3433 ctl->ossmask |= SOUND_MASK_VOLUME; 3434 } 3435 fl |= 1 << ossdev; 3436 ctl->ossmask |= 1 << ossdev; 3437 ctl->ossdev = ossdev; 3438 } 3439 } 3440 w->ctlflags |= fl; 3441 return (fl); 3442 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3443 i = 0; 3444 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3445 if (ctl->enable == 0 || ctl->widget == NULL) 3446 continue; 3447 if (((ctl->widget->nid == pnid && ctl->index == index && 3448 (ctl->dir & HDA_CTL_IN)) || 3449 (ctl->widget->nid == pnid && pw != NULL && 3450 pw->type == 3451 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3452 (pw->nconns < 2 || pw->selconn == index || 3453 pw->selconn == -1) && 3454 (ctl->dir & HDA_CTL_OUT)) || 3455 (strategy == HDA_PARSE_DIRECT && 3456 ctl->widget->nid == w->nid)) && 3457 (ctl->ossmask & ~SOUND_MASK_VOLUME) == 0) { 3458 if (pw != NULL && pw->selconn == -1) 3459 pw->selconn = index; 3460 fl |= SOUND_MASK_VOLUME; 3461 fl |= SOUND_MASK_SPEAKER; 3462 ctl->ossmask |= SOUND_MASK_VOLUME; 3463 ctl->ossmask |= SOUND_MASK_SPEAKER; 3464 ctl->ossdev = SOUND_MIXER_SPEAKER; 3465 } 3466 } 3467 w->ctlflags |= fl; 3468 return (fl); 3469 } 3470 return (0); 3471} 3472 3473static uint32_t 3474hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3475{ 3476 struct hdac_widget *w, *cw; 3477 struct hdac_audio_ctl *ctl; 3478 uint32_t fl; 3479 int i; 3480 3481 if (depth > HDA_PARSE_MAXDEPTH) 3482 return (0); 3483 3484 w = hdac_widget_get(devinfo, nid); 3485 if (w == NULL || w->enable == 0) 3486 return (0); 3487 /*if (!(w->pflags & HDA_ADC_PATH)) 3488 return (0); 3489 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3490 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3491 return (0);*/ 3492 i = 0; 3493 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3494 if (ctl->enable == 0 || ctl->widget == NULL) 3495 continue; 3496 if (ctl->widget->nid == nid) { 3497 ctl->ossmask |= SOUND_MASK_RECLEV; 3498 w->ctlflags |= SOUND_MASK_RECLEV; 3499 return (SOUND_MASK_RECLEV); 3500 } 3501 } 3502 for (i = 0; i < w->nconns; i++) { 3503 cw = hdac_widget_get(devinfo, w->conns[i]); 3504 if (cw == NULL || cw->enable == 0) 3505 continue; 3506 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3507 continue; 3508 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3509 if (fl != 0) { 3510 cw->ctlflags |= fl; 3511 w->ctlflags |= fl; 3512 return (fl); 3513 } 3514 } 3515 return (0); 3516} 3517 3518static int 3519hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3520{ 3521 struct hdac_widget *w, *cw; 3522 int i, child = 0; 3523 3524 if (depth > HDA_PARSE_MAXDEPTH) 3525 return (0); 3526 3527 w = hdac_widget_get(devinfo, nid); 3528 if (w == NULL || w->enable == 0) 3529 return (0); 3530 /*if (!(w->pflags & HDA_ADC_PATH)) 3531 return (0); 3532 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3533 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3534 return (0);*/ 3535 /* XXX weak! */ 3536 for (i = 0; i < w->nconns; i++) { 3537 cw = hdac_widget_get(devinfo, w->conns[i]); 3538 if (cw == NULL) 3539 continue; 3540 if (++child > 1) { 3541 w->pflags |= HDA_ADC_RECSEL; 3542 return (1); 3543 } 3544 } 3545 for (i = 0; i < w->nconns; i++) { 3546 if (hdac_audio_ctl_recsel_build(devinfo, 3547 w->conns[i], depth + 1) != 0) 3548 return (1); 3549 } 3550 return (0); 3551} 3552 3553static int 3554hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3555{ 3556 struct hdac_widget *w, *cw; 3557 int i, j, conndev, found_dac = 0; 3558 int strategy; 3559 3560 strategy = devinfo->function.audio.parsing_strategy; 3561 3562 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3563 w = hdac_widget_get(devinfo, i); 3564 if (w == NULL || w->enable == 0) 3565 continue; 3566 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3567 continue; 3568 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3569 continue; 3570 conndev = w->wclass.pin.config & 3571 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3572 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3573 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3574 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3575 continue; 3576 for (j = 0; j < w->nconns; j++) { 3577 cw = hdac_widget_get(devinfo, w->conns[j]); 3578 if (cw == NULL || cw->enable == 0) 3579 continue; 3580 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3582 cw->type == 3583 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3584 continue; 3585 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3586 != 0) { 3587 if (w->selconn == -1) 3588 w->selconn = j; 3589 w->pflags |= HDA_DAC_PATH; 3590 found_dac++; 3591 } 3592 } 3593 } 3594 3595 return (found_dac); 3596} 3597 3598static void 3599hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3600{ 3601 struct hdac_widget *w; 3602 struct hdac_audio_ctl *ctl; 3603 int i, j, dacs, strategy; 3604 3605 /* Construct DAC path */ 3606 strategy = HDA_PARSE_MIXER; 3607 devinfo->function.audio.parsing_strategy = strategy; 3608 HDA_BOOTVERBOSE_MSG( 3609 device_printf(devinfo->codec->sc->dev, 3610 "HWiP: HDA Widget Parser - Revision %d\n", 3611 HDA_WIDGET_PARSER_REV); 3612 ); 3613 dacs = hdac_audio_build_tree_strategy(devinfo); 3614 if (dacs == 0) { 3615 HDA_BOOTVERBOSE_MSG( 3616 device_printf(devinfo->codec->sc->dev, 3617 "HWiP: 0 DAC found! Retrying parser " 3618 "using HDA_PARSE_DIRECT strategy.\n"); 3619 ); 3620 strategy = HDA_PARSE_DIRECT; 3621 devinfo->function.audio.parsing_strategy = strategy; 3622 dacs = hdac_audio_build_tree_strategy(devinfo); 3623 } 3624 3625 HDA_BOOTVERBOSE_MSG( 3626 device_printf(devinfo->codec->sc->dev, 3627 "HWiP: Found %d DAC(s) using HDA_PARSE_%s strategy.\n", 3628 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 3629 ); 3630 3631 /* Construct ADC path */ 3632 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3633 w = hdac_widget_get(devinfo, i); 3634 if (w == NULL || w->enable == 0) 3635 continue; 3636 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3637 continue; 3638 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 3639 } 3640 3641 /* Output mixers */ 3642 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3643 w = hdac_widget_get(devinfo, i); 3644 if (w == NULL || w->enable == 0) 3645 continue; 3646 if ((strategy == HDA_PARSE_MIXER && 3647 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3648 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3649 && (w->pflags & HDA_DAC_PATH)) || 3650 (strategy == HDA_PARSE_DIRECT && (w->pflags & 3651 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 3652 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 3653 w->nid, devinfo->startnode - 1, 0, 0); 3654 } else if (w->type == 3655 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3656 j = 0; 3657 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 3658 NULL) { 3659 if (ctl->enable == 0 || ctl->widget == NULL) 3660 continue; 3661 if (ctl->widget->nid != w->nid) 3662 continue; 3663 ctl->ossmask |= SOUND_MASK_VOLUME; 3664 ctl->ossmask |= SOUND_MASK_SPEAKER; 3665 ctl->ossdev = SOUND_MIXER_SPEAKER; 3666 w->ctlflags |= SOUND_MASK_VOLUME; 3667 w->ctlflags |= SOUND_MASK_SPEAKER; 3668 } 3669 } 3670 } 3671 3672 /* Input mixers (rec) */ 3673 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3674 w = hdac_widget_get(devinfo, i); 3675 if (w == NULL || w->enable == 0) 3676 continue; 3677 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3678 w->pflags & HDA_ADC_PATH)) 3679 continue; 3680 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 3681 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 3682 } 3683} 3684 3685#define HDA_COMMIT_CONN (1 << 0) 3686#define HDA_COMMIT_CTRL (1 << 1) 3687#define HDA_COMMIT_EAPD (1 << 2) 3688#define HDA_COMMIT_GPIO (1 << 3) 3689#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 3690 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 3691 3692static void 3693hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 3694{ 3695 struct hdac_softc *sc = devinfo->codec->sc; 3696 struct hdac_widget *w; 3697 nid_t cad; 3698 int i; 3699 3700 if (!(cfl & HDA_COMMIT_ALL)) 3701 return; 3702 3703 cad = devinfo->codec->cad; 3704 3705 if ((cfl & HDA_COMMIT_GPIO)) { 3706 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIO1) { 3707 hdac_command(sc, 3708 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, 0x01, 3709 0x01), cad); 3710 hdac_command(sc, 3711 HDA_CMD_SET_GPIO_DIRECTION(cad, 0x01, 3712 0x01), cad); 3713 hdac_command(sc, 3714 HDA_CMD_SET_GPIO_DATA(cad, 0x01, 3715 0x01), cad); 3716 } 3717 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIO2) { 3718 hdac_command(sc, 3719 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, 0x01, 3720 0x02), cad); 3721 hdac_command(sc, 3722 HDA_CMD_SET_GPIO_DIRECTION(cad, 0x01, 3723 0x02), cad); 3724 hdac_command(sc, 3725 HDA_CMD_SET_GPIO_DATA(cad, 0x01, 3726 0x02), cad); 3727 } 3728 } 3729 3730 for (i = 0; i < devinfo->nodecnt; i++) { 3731 w = &devinfo->widget[i]; 3732 if (w == NULL || w->enable == 0) 3733 continue; 3734 if (cfl & HDA_COMMIT_CONN) { 3735 if (w->selconn == -1) 3736 w->selconn = 0; 3737 if (w->nconns > 0) 3738 hdac_widget_connection_select(w, w->selconn); 3739 } 3740 if ((cfl & HDA_COMMIT_CTRL) && 3741 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 3742 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 3743 (HDA_DAC_PATH | HDA_ADC_PATH)) 3744 device_printf(sc->dev, "WARNING: node %d " 3745 "participate both for DAC/ADC!\n", w->nid); 3746 if (w->pflags & HDA_DAC_PATH) { 3747 w->wclass.pin.ctrl &= 3748 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 3749 if ((w->wclass.pin.config & 3750 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 3751 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 3752 w->wclass.pin.ctrl &= 3753 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 3754 } else if (w->pflags & HDA_ADC_PATH) { 3755 w->wclass.pin.ctrl &= 3756 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3757 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 3758 } else 3759 w->wclass.pin.ctrl &= ~( 3760 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 3761 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3762 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 3763 hdac_command(sc, 3764 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 3765 w->wclass.pin.ctrl), cad); 3766 } 3767 if ((cfl & HDA_COMMIT_EAPD) && 3768 w->param.eapdbtl != 0xffffffff) 3769 hdac_command(sc, 3770 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 3771 w->param.eapdbtl), cad); 3772 3773 DELAY(1000); 3774 } 3775} 3776 3777static void 3778hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 3779{ 3780 struct hdac_softc *sc = devinfo->codec->sc; 3781 struct hdac_audio_ctl *ctl; 3782 int i; 3783 3784 devinfo->function.audio.mvol = 100 | (100 << 8); 3785 i = 0; 3786 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3787 if (ctl->enable == 0 || ctl->widget == NULL) { 3788 HDA_BOOTVERBOSE_MSG( 3789 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3790 i, (ctl->widget != NULL) ? 3791 ctl->widget->nid : -1); 3792 if (ctl->childwidget != NULL) 3793 printf(" childnid=%d", 3794 ctl->childwidget->nid); 3795 if (ctl->widget == NULL) 3796 printf(" NULL WIDGET!"); 3797 printf(" DISABLED\n"); 3798 ); 3799 continue; 3800 } 3801 HDA_BOOTVERBOSE_MSG( 3802 if (ctl->ossmask == 0) { 3803 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3804 i, ctl->widget->nid); 3805 if (ctl->childwidget != NULL) 3806 printf(" childnid=%d", 3807 ctl->childwidget->nid); 3808 printf(" Bind to NONE\n"); 3809 } 3810 ); 3811 if (ctl->step > 0) { 3812 ctl->ossval = (ctl->left * 100) / ctl->step; 3813 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 3814 } else 3815 ctl->ossval = 0; 3816 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 3817 ctl->left, ctl->right); 3818 } 3819} 3820 3821static int 3822hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 3823{ 3824 struct hdac_chan *ch; 3825 struct hdac_widget *w; 3826 uint32_t cap, fmtcap, pcmcap, path; 3827 int i, type, ret, max; 3828 3829 if (dir == PCMDIR_PLAY) { 3830 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 3831 ch = &devinfo->codec->sc->play; 3832 path = HDA_DAC_PATH; 3833 } else { 3834 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 3835 ch = &devinfo->codec->sc->rec; 3836 path = HDA_ADC_PATH; 3837 } 3838 3839 ch->caps = hdac_caps; 3840 ch->caps.fmtlist = ch->fmtlist; 3841 ch->bit16 = 1; 3842 ch->bit32 = 0; 3843 ch->pcmrates[0] = 48000; 3844 ch->pcmrates[1] = 0; 3845 3846 ret = 0; 3847 fmtcap = devinfo->function.audio.supp_stream_formats; 3848 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 3849 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 3850 3851 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 3852 w = hdac_widget_get(devinfo, i); 3853 if (w == NULL || w->enable == 0 || w->type != type || 3854 (w->pflags & path) == 0) 3855 continue; 3856 cap = w->param.widget_cap; 3857 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 3858 continue;*/ 3859 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 3860 continue; 3861 cap = w->param.supp_stream_formats; 3862 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 3863 } 3864 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 3865 }*/ 3866 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 3867 continue; 3868 ch->io[ret++] = i; 3869 fmtcap &= w->param.supp_stream_formats; 3870 pcmcap &= w->param.supp_pcm_size_rate; 3871 } 3872 ch->io[ret] = -1; 3873 3874 ch->supp_stream_formats = fmtcap; 3875 ch->supp_pcm_size_rate = pcmcap; 3876 3877 /* 3878 * 8bit = 0 3879 * 16bit = 1 3880 * 20bit = 2 3881 * 24bit = 3 3882 * 32bit = 4 3883 */ 3884 if (ret > 0) { 3885 cap = pcmcap; 3886 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 3887 ch->bit16 = 1; 3888 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 3889 ch->bit16 = 0; 3890 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 3891 ch->bit32 = 4; 3892 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 3893 ch->bit32 = 3; 3894 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 3895 ch->bit32 = 2; 3896 i = 0; 3897 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 3898 ch->fmtlist[i++] = AFMT_S16_LE; 3899 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 3900 if (ch->bit32 > 0) { 3901 if (!(devinfo->function.audio.quirks & 3902 HDA_QUIRK_FORCESTEREO)) 3903 ch->fmtlist[i++] = AFMT_S32_LE; 3904 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 3905 } 3906 ch->fmtlist[i] = 0; 3907 i = 0; 3908 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 3909 ch->pcmrates[i++] = 8000; 3910 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 3911 ch->pcmrates[i++] = 11025; 3912 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 3913 ch->pcmrates[i++] = 16000; 3914 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 3915 ch->pcmrates[i++] = 22050; 3916 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 3917 ch->pcmrates[i++] = 32000; 3918 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 3919 ch->pcmrates[i++] = 44100; 3920 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 3921 ch->pcmrates[i++] = 48000; 3922 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 3923 ch->pcmrates[i++] = 88200; 3924 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 3925 ch->pcmrates[i++] = 96000; 3926 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 3927 ch->pcmrates[i++] = 176400; 3928 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 3929 ch->pcmrates[i++] = 192000; 3930 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 3931 ch->pcmrates[i] = 0; 3932 if (i > 0) { 3933 ch->caps.minspeed = ch->pcmrates[0]; 3934 ch->caps.maxspeed = ch->pcmrates[i - 1]; 3935 } 3936 } 3937 3938 return (ret); 3939} 3940 3941static void 3942hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 3943{ 3944 struct hdac_audio_ctl *ctl; 3945 struct hdac_softc *sc = devinfo->codec->sc; 3946 int i; 3947 uint32_t fl = 0; 3948 3949 3950 if (flag == 0) { 3951 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 3952 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 3953 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 3954 } 3955 3956 i = 0; 3957 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3958 if (ctl->enable == 0 || ctl->widget == NULL || 3959 ctl->widget->enable == 0) 3960 continue; 3961 if ((flag == 0 && (ctl->ossmask & ~fl)) || 3962 (flag != 0 && (ctl->ossmask & flag))) { 3963 if (banner != NULL) { 3964 device_printf(sc->dev, "\n"); 3965 device_printf(sc->dev, "%s\n", banner); 3966 } 3967 goto hdac_ctl_dump_it_all; 3968 } 3969 } 3970 3971 return; 3972 3973hdac_ctl_dump_it_all: 3974 i = 0; 3975 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3976 if (ctl->enable == 0 || ctl->widget == NULL || 3977 ctl->widget->enable == 0) 3978 continue; 3979 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 3980 (flag != 0 && (ctl->ossmask & flag)))) 3981 continue; 3982 if (flag == 0) { 3983 device_printf(sc->dev, "\n"); 3984 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 3985 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 3986 } 3987 device_printf(sc->dev, " |\n"); 3988 device_printf(sc->dev, " +- nid: %2d index: %2d ", 3989 ctl->widget->nid, ctl->index); 3990 if (ctl->childwidget != NULL) 3991 printf("(nid: %2d) ", ctl->childwidget->nid); 3992 else 3993 printf(" "); 3994 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 3995 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 3996 ctl->ossmask); 3997 } 3998} 3999 4000static void 4001hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4002{ 4003 uint32_t cap; 4004 4005 cap = fcap; 4006 if (cap != 0) { 4007 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4008 device_printf(sc->dev, " Format:"); 4009 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4010 printf(" AC3"); 4011 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4012 printf(" FLOAT32"); 4013 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4014 printf(" PCM"); 4015 printf("\n"); 4016 } 4017 cap = pcmcap; 4018 if (cap != 0) { 4019 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4020 device_printf(sc->dev, " PCM size:"); 4021 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4022 printf(" 8"); 4023 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4024 printf(" 16"); 4025 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4026 printf(" 20"); 4027 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4028 printf(" 24"); 4029 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4030 printf(" 32"); 4031 printf("\n"); 4032 device_printf(sc->dev, " PCM rate:"); 4033 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4034 printf(" 8"); 4035 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4036 printf(" 11"); 4037 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4038 printf(" 16"); 4039 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4040 printf(" 22"); 4041 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4042 printf(" 32"); 4043 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4044 printf(" 44"); 4045 printf(" 48"); 4046 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4047 printf(" 88"); 4048 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4049 printf(" 96"); 4050 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4051 printf(" 176"); 4052 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4053 printf(" 192"); 4054 printf("\n"); 4055 } 4056} 4057 4058static void 4059hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4060{ 4061 uint32_t pincap, wcap; 4062 4063 pincap = w->wclass.pin.cap; 4064 wcap = w->param.widget_cap; 4065 4066 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4067 device_printf(sc->dev, " "); 4068 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4069 printf(" ISC"); 4070 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4071 printf(" TRQD"); 4072 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4073 printf(" PDC"); 4074 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4075 printf(" HP"); 4076 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4077 printf(" OUT"); 4078 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4079 printf(" IN"); 4080 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4081 printf(" BAL"); 4082 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4083 printf(" EAPD"); 4084 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4085 printf(" : UNSOL"); 4086 printf("\n"); 4087 device_printf(sc->dev, " Pin config: 0x%08x\n", 4088 w->wclass.pin.config); 4089 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4090 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4091 printf(" HP"); 4092 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4093 printf(" IN"); 4094 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4095 printf(" OUT"); 4096 printf("\n"); 4097} 4098 4099static void 4100hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4101{ 4102 device_printf(sc->dev, " %s amp: 0x%0x\n", banner, cap); 4103 device_printf(sc->dev, " " 4104 "mute=%d step=%d size=%d offset=%d\n", 4105 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4106 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4107 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4108 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4109} 4110 4111static void 4112hdac_dump_nodes(struct hdac_devinfo *devinfo) 4113{ 4114 struct hdac_softc *sc = devinfo->codec->sc; 4115 struct hdac_widget *w, *cw; 4116 int i, j; 4117 4118 device_printf(sc->dev, "\n"); 4119 device_printf(sc->dev, "Default Parameter\n"); 4120 device_printf(sc->dev, "-----------------\n"); 4121 hdac_dump_audio_formats(sc, 4122 devinfo->function.audio.supp_stream_formats, 4123 devinfo->function.audio.supp_pcm_size_rate); 4124 device_printf(sc->dev, " IN amp: 0x%08x\n", 4125 devinfo->function.audio.inamp_cap); 4126 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4127 devinfo->function.audio.outamp_cap); 4128 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4129 w = hdac_widget_get(devinfo, i); 4130 if (w == NULL) { 4131 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4132 continue; 4133 } 4134 device_printf(sc->dev, "\n"); 4135 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4136 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4137 "DIGITAL" : "ANALOG", 4138 (w->enable == 0) ? " [DISABLED]" : ""); 4139 device_printf(sc->dev, " name: %s\n", w->name); 4140 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4141 w->param.widget_cap); 4142 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4143 w->pflags); 4144 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4145 w->ctlflags); 4146 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4147 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4148 hdac_dump_audio_formats(sc, 4149 w->param.supp_stream_formats, 4150 w->param.supp_pcm_size_rate); 4151 } else if (w->type == 4152 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4153 hdac_dump_pin(sc, w); 4154 if (w->param.eapdbtl != 0xffffffff) 4155 device_printf(sc->dev, " EAPD: 0x%08x\n", 4156 w->param.eapdbtl); 4157 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap)) 4158 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4159 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap)) 4160 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4161 device_printf(sc->dev, " connections: %d\n", w->nconns); 4162 for (j = 0; j < w->nconns; j++) { 4163 cw = hdac_widget_get(devinfo, w->conns[j]); 4164 device_printf(sc->dev, " |\n"); 4165 device_printf(sc->dev, " + <- nid=%d [%s]", 4166 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4167 if (cw == NULL) 4168 printf(" [UNKNOWN]"); 4169 else if (cw->enable == 0) 4170 printf(" [DISABLED]"); 4171 if (w->nconns > 1 && w->selconn == j && w->type != 4172 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4173 printf(" (selected)"); 4174 printf("\n"); 4175 } 4176 } 4177 4178} 4179 4180static void 4181hdac_dump_dac(struct hdac_devinfo *devinfo) 4182{ 4183 /* XXX TODO */ 4184} 4185 4186static void 4187hdac_dump_adc(struct hdac_devinfo *devinfo) 4188{ 4189 struct hdac_widget *w, *cw; 4190 struct hdac_softc *sc = devinfo->codec->sc; 4191 int i, j; 4192 int printed = 0; 4193 char ossdevs[256]; 4194 4195 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4196 w = hdac_widget_get(devinfo, i); 4197 if (w == NULL || w->enable == 0) 4198 continue; 4199 if (!(w->pflags & HDA_ADC_RECSEL)) 4200 continue; 4201 if (printed == 0) { 4202 printed = 1; 4203 device_printf(sc->dev, "\n"); 4204 device_printf(sc->dev, "Recording sources:\n"); 4205 } 4206 device_printf(sc->dev, "\n"); 4207 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4208 for (j = 0; j < w->nconns; j++) { 4209 cw = hdac_widget_get(devinfo, w->conns[j]); 4210 if (cw == NULL || cw->enable == 0) 4211 continue; 4212 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4213 ossdevs, sizeof(ossdevs)); 4214 device_printf(sc->dev, " |\n"); 4215 device_printf(sc->dev, " + <- nid=%d [%s]", 4216 cw->nid, cw->name); 4217 if (strlen(ossdevs) > 0) { 4218 printf(" [recsrc: %s]", ossdevs); 4219 } 4220 printf("\n"); 4221 } 4222 } 4223} 4224 4225static void 4226hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4227{ 4228 nid_t *nids; 4229 4230 if (pcnt > 0) { 4231 device_printf(sc->dev, "\n"); 4232 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4233 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4234 sc->play.supp_pcm_size_rate); 4235 device_printf(sc->dev, " DAC:"); 4236 for (nids = sc->play.io; *nids != -1; nids++) 4237 printf(" %d", *nids); 4238 printf("\n"); 4239 } 4240 4241 if (rcnt > 0) { 4242 device_printf(sc->dev, "\n"); 4243 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4244 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4245 sc->rec.supp_pcm_size_rate); 4246 device_printf(sc->dev, " ADC:"); 4247 for (nids = sc->rec.io; *nids != -1; nids++) 4248 printf(" %d", *nids); 4249 printf("\n"); 4250 } 4251} 4252 4253static void 4254hdac_attach2(void *arg) 4255{ 4256 struct hdac_softc *sc; 4257 struct hdac_widget *w; 4258 struct hdac_audio_ctl *ctl; 4259 int pcnt, rcnt; 4260 int i; 4261 char status[SND_STATUSLEN]; 4262 device_t *devlist; 4263 int devcount; 4264 struct hdac_devinfo *devinfo = NULL; 4265 4266 sc = (struct hdac_softc *)arg; 4267 4268 4269 hdac_lock(sc); 4270 4271 /* Remove ourselves from the config hooks */ 4272 if (sc->intrhook.ich_func != NULL) { 4273 config_intrhook_disestablish(&sc->intrhook); 4274 sc->intrhook.ich_func = NULL; 4275 } 4276 4277 /* Start the corb and rirb engines */ 4278 HDA_DEBUG_MSG( 4279 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4280 ); 4281 hdac_corb_start(sc); 4282 HDA_DEBUG_MSG( 4283 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4284 ); 4285 hdac_rirb_start(sc); 4286 4287 HDA_DEBUG_MSG( 4288 device_printf(sc->dev, 4289 "HDA_DEBUG: Enabling controller interrupt...\n"); 4290 ); 4291 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4292 4293 DELAY(1000); 4294 4295 HDA_DEBUG_MSG( 4296 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4297 ); 4298 hdac_scan_codecs(sc); 4299 4300 device_get_children(sc->dev, &devlist, &devcount); 4301 if (devcount != 0 && devlist != NULL) { 4302 for (i = 0; i < devcount; i++) { 4303 devinfo = (struct hdac_devinfo *) 4304 device_get_ivars(devlist[i]); 4305 if (devinfo != NULL && 4306 devinfo->node_type == 4307 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4308 break; 4309 } else 4310 devinfo = NULL; 4311 } 4312 } 4313 4314 if (devinfo == NULL) { 4315 hdac_unlock(sc); 4316 device_printf(sc->dev, "Audio Function Group not found!\n"); 4317 return; 4318 } 4319 4320 HDA_DEBUG_MSG( 4321 device_printf(sc->dev, 4322 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4323 devinfo->nid, devinfo->codec->cad); 4324 ); 4325 hdac_audio_parse(devinfo); 4326 HDA_DEBUG_MSG( 4327 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4328 ); 4329 hdac_audio_ctl_parse(devinfo); 4330 HDA_DEBUG_MSG( 4331 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4332 ); 4333 hdac_vendor_patch_parse(devinfo); 4334 4335 /* XXX Disable all DIGITAL path. */ 4336 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4337 w = hdac_widget_get(devinfo, i); 4338 if (w == NULL) 4339 continue; 4340 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4341 w->enable = 0; 4342 continue; 4343 } 4344 /* XXX Disable useless pin ? */ 4345 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4346 (w->wclass.pin.config & 4347 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4348 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4349 w->enable = 0; 4350 } 4351 i = 0; 4352 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4353 if (ctl->widget == NULL) 4354 continue; 4355 w = ctl->widget; 4356 if (w->enable == 0) 4357 ctl->enable = 0; 4358 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4359 ctl->enable = 0; 4360 w = ctl->childwidget; 4361 if (w == NULL) 4362 continue; 4363 if (w->enable == 0 || 4364 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4365 ctl->enable = 0; 4366 } 4367 4368 HDA_DEBUG_MSG( 4369 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 4370 ); 4371 hdac_audio_build_tree(devinfo); 4372 4373 HDA_DEBUG_MSG( 4374 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 4375 ); 4376 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 4377 HDA_DEBUG_MSG( 4378 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 4379 ); 4380 hdac_audio_ctl_commit(devinfo); 4381 4382 HDA_DEBUG_MSG( 4383 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 4384 ); 4385 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 4386 HDA_DEBUG_MSG( 4387 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 4388 ); 4389 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 4390 4391 hdac_unlock(sc); 4392 HDA_DEBUG_MSG( 4393 device_printf(sc->dev, 4394 "HDA_DEBUG: OSS mixer initialization...\n"); 4395 ); 4396 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo)) { 4397 device_printf(sc->dev, "Can't register mixer\n"); 4398 } 4399 4400 if (pcnt > 0) 4401 pcnt = 1; 4402 if (rcnt > 0) 4403 rcnt = 1; 4404 4405 HDA_DEBUG_MSG( 4406 device_printf(sc->dev, 4407 "HDA_DEBUG: Registering PCM channels...\n"); 4408 ); 4409 if (pcm_register(sc->dev, devinfo, pcnt, rcnt)) { 4410 device_printf(sc->dev, "Can't register PCM\n"); 4411 } 4412 4413 sc->registered++; 4414 4415 for (i = 0; i < pcnt; i++) 4416 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 4417 for (i = 0; i < rcnt; i++) 4418 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 4419 4420 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 4421 rman_get_start(sc->mem.mem_res), 4422 rman_get_start(sc->irq.irq_res), 4423 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 4424 pcm_setstatus(sc->dev, status); 4425 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 4426 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 4427 4428 HDA_BOOTVERBOSE_MSG( 4429 if (devinfo->function.audio.quirks != 0) { 4430 device_printf(sc->dev, "\n"); 4431 device_printf(sc->dev, "HDA quirks:"); 4432 if (devinfo->function.audio.quirks & 4433 HDA_QUIRK_GPIO1) 4434 printf(" GPIO1"); 4435 if (devinfo->function.audio.quirks & 4436 HDA_QUIRK_GPIO2) 4437 printf(" GPIO2"); 4438 if (devinfo->function.audio.quirks & 4439 HDA_QUIRK_SOFTPCMVOL) 4440 printf(" SOFTPCMVOL"); 4441 if (devinfo->function.audio.quirks & 4442 HDA_QUIRK_FIXEDRATE) 4443 printf(" FIXEDRATE"); 4444 if (devinfo->function.audio.quirks & 4445 HDA_QUIRK_FORCESTEREO) 4446 printf(" FORCESTEREO"); 4447 printf("\n"); 4448 } 4449 device_printf(sc->dev, "\n"); 4450 device_printf(sc->dev, "+-------------------+\n"); 4451 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 4452 device_printf(sc->dev, "+-------------------+\n"); 4453 hdac_dump_nodes(devinfo); 4454 device_printf(sc->dev, "\n"); 4455 device_printf(sc->dev, "+------------------------+\n"); 4456 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 4457 device_printf(sc->dev, "+------------------------+\n"); 4458 device_printf(sc->dev, "\n"); 4459 i = 0; 4460 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4461 device_printf(sc->dev, "%3d: nid=%d", i, 4462 (ctl->widget != NULL) ? ctl->widget->nid : -1); 4463 if (ctl->childwidget != NULL) 4464 printf(" cnid=%d", ctl->childwidget->nid); 4465 printf(" dir=0x%x index=%d " 4466 "ossmask=0x%08x ossdev=%d%s\n", 4467 ctl->dir, ctl->index, 4468 ctl->ossmask, ctl->ossdev, 4469 (ctl->enable == 0) ? " [DISABLED]" : ""); 4470 } 4471 device_printf(sc->dev, "\n"); 4472 device_printf(sc->dev, "+-----------------------------------+\n"); 4473 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 4474 device_printf(sc->dev, "+-----------------------------------+\n"); 4475 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 4476 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 4477 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 4478 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 4479 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 4480 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 4481 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 4482 hdac_dump_ctls(devinfo, NULL, 0); 4483 hdac_dump_dac(devinfo); 4484 hdac_dump_adc(devinfo); 4485 device_printf(sc->dev, "\n"); 4486 device_printf(sc->dev, "+--------------------------------------+\n"); 4487 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 4488 device_printf(sc->dev, "+--------------------------------------+\n"); 4489 hdac_dump_pcmchannels(sc, pcnt, rcnt); 4490 ); 4491} 4492 4493/**************************************************************************** 4494 * int hdac_detach(device_t) 4495 * 4496 * Detach and free up resources utilized by the hdac device. 4497 ****************************************************************************/ 4498static int 4499hdac_detach(device_t dev) 4500{ 4501 struct hdac_softc *sc = NULL; 4502 device_t *devlist; 4503 int devcount; 4504 struct hdac_devinfo *devinfo = NULL; 4505 struct hdac_codec *codec, *codec_tmp; 4506 int i; 4507 4508 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 4509 if (devinfo != NULL && devinfo->codec != NULL) 4510 sc = devinfo->codec->sc; 4511 if (sc == NULL) 4512 return (EINVAL); 4513 4514 if (sc->registered > 0) { 4515 i = pcm_unregister(dev); 4516 if (i) 4517 return (i); 4518 } 4519 4520 sc->registered = 0; 4521 4522 /* Lock the mutex before messing with the dma engines */ 4523 hdac_lock(sc); 4524 hdac_reset(sc); 4525 hdac_unlock(sc); 4526 snd_mtxfree(sc->lock); 4527 sc->lock = NULL; 4528 4529 device_get_children(sc->dev, &devlist, &devcount); 4530 if (devcount != 0 && devlist != NULL) { 4531 for (i = 0; i < devcount; i++) { 4532 devinfo = (struct hdac_devinfo *) 4533 device_get_ivars(devlist[i]); 4534 if (devinfo == NULL) 4535 continue; 4536 if (devinfo->widget != NULL) { 4537 free(devinfo->widget, M_HDAC); 4538 } 4539 if (devinfo->node_type == 4540 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4541 devinfo->function.audio.ctl != NULL) { 4542 free(devinfo->function.audio.ctl, M_HDAC); 4543 } 4544 4545 free(devinfo, M_HDAC); 4546 device_delete_child(sc->dev, devlist[i]); 4547 } 4548 free(devlist, M_TEMP); 4549 } 4550 4551 SLIST_FOREACH_SAFE(codec, &sc->codec_list, next_codec, codec_tmp) { 4552 SLIST_REMOVE(&sc->codec_list, codec, hdac_codec, 4553 next_codec); 4554 free((void *)codec, M_HDAC); 4555 } 4556 4557 hdac_dma_free(&sc->rirb_dma); 4558 hdac_dma_free(&sc->corb_dma); 4559 if (sc->play.blkcnt) 4560 hdac_dma_free(&sc->play.bdl_dma); 4561 if (sc->rec.blkcnt) 4562 hdac_dma_free(&sc->rec.bdl_dma); 4563 hdac_irq_free(sc); 4564 hdac_mem_free(sc); 4565 free(sc, M_DEVBUF); 4566 4567 return (0); 4568} 4569 4570static device_method_t hdac_methods[] = { 4571 /* device interface */ 4572 DEVMETHOD(device_probe, hdac_probe), 4573 DEVMETHOD(device_attach, hdac_attach), 4574 DEVMETHOD(device_detach, hdac_detach), 4575 { 0, 0 } 4576}; 4577 4578static driver_t hdac_driver = { 4579 "pcm", 4580 hdac_methods, 4581 PCM_SOFTC_SIZE, 4582}; 4583 4584DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 4585MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 4586MODULE_VERSION(snd_hda, 1); 4587