hdac.c revision 162922
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30 * that this driver still in its early stage, and possible of rewrite are 31 * pretty much guaranteed. There are supposedly several distinct parent/child 32 * busses to make this "perfect", but as for now and for the sake of 33 * simplicity, everything is gobble up within single source. 34 * 35 * List of subsys: 36 * 1) HDA Controller support 37 * 2) HDA Codecs support, which may include 38 * - HDA 39 * - Modem 40 * - HDMI 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especiall UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * * 65 * * ....and various people from freebsd-multimedia@FreeBSD.org * 66 * * * 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68 */ 69 70#include <dev/sound/pcm/sound.h> 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <dev/sound/pci/hda/hdac_private.h> 75#include <dev/sound/pci/hda/hdac_reg.h> 76#include <dev/sound/pci/hda/hda_reg.h> 77#include <dev/sound/pci/hda/hdac.h> 78 79#include "mixer_if.h" 80 81#define HDA_DRV_TEST_REV "20061001_0028" 82#define HDA_WIDGET_PARSER_REV 1 83 84SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 162922 2006-10-01 11:13:00Z ariff $"); 85 86#undef HDA_DEBUG_ENABLED 87#define HDA_DEBUG_ENABLED 1 88 89#ifdef HDA_DEBUG_ENABLED 90#define HDA_DEBUG_MSG(stmt) do { \ 91 if (bootverbose) { \ 92 stmt \ 93 } \ 94} while(0) 95#else 96#define HDA_DEBUG_MSG(stmt) 97#endif 98 99#define HDA_BOOTVERBOSE_MSG(stmt) do { \ 100 if (bootverbose) { \ 101 stmt \ 102 } \ 103} while(0) 104 105#if 0 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112 113#define HDA_MODEL_CONSTRUCT(vendor, model) \ 114 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 115 116/* Controller models */ 117 118/* Intel */ 119#define INTEL_VENDORID 0x8086 120#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 121#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 122#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 123 124/* Nvidia */ 125#define NVIDIA_VENDORID 0x10de 126#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 127#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 128#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 129 130/* ATI */ 131#define ATI_VENDORID 0x1002 132#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 133#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 134 135/* OEM/subvendors */ 136 137/* HP/Compaq */ 138#define HP_VENDORID 0x103c 139#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 140#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 141#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 142#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 143 144/* Dell */ 145#define DELL_VENDORID 0x1028 146#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 147#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 148#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 149 150/* Clevo */ 151#define CLEVO_VENDORID 0x1558 152#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 153#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 154 155/* Acer */ 156#define ACER_VENDORID 0x1025 157#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 158 159 160/* Misc constants.. */ 161#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 162#define HDA_AMP_MUTE_NONE (0) 163#define HDA_AMP_MUTE_LEFT (1 << 0) 164#define HDA_AMP_MUTE_RIGHT (1 << 1) 165#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 166 167#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 168#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 169 170#define HDA_DAC_PATH (1 << 0) 171#define HDA_ADC_PATH (1 << 1) 172#define HDA_ADC_RECSEL (1 << 2) 173 174#define HDA_CTL_OUT 0x1 175#define HDA_CTL_IN 0x2 176#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 177 178#define HDA_QUIRK_GPIO1 (1 << 0) 179#define HDA_QUIRK_GPIO2 (1 << 1) 180#define HDA_QUIRK_SOFTPCMVOL (1 << 2) 181#define HDA_QUIRK_FIXEDRATE (1 << 3) 182#define HDA_QUIRK_FORCESTEREO (1 << 4) 183 184#define HDA_BDL_MIN 2 185#define HDA_BDL_MAX 256 186#define HDA_BDL_DEFAULT HDA_BDL_MIN 187 188#define HDA_BUFSZ_MIN 4096 189#define HDA_BUFSZ_MAX 65536 190#define HDA_BUFSZ_DEFAULT 16384 191 192#define HDA_PARSE_MAXDEPTH 10 193 194#define HDAC_UNSOLTAG_EVENT_HP 0x00 195 196static MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 197 198enum { 199 HDA_PARSE_MIXER, 200 HDA_PARSE_DIRECT 201}; 202 203/* Default */ 204static uint32_t hdac_fmt[] = { 205 AFMT_STEREO | AFMT_S16_LE, 206 0 207}; 208 209static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 210 211static const struct { 212 uint32_t model; 213 char *desc; 214} hdac_devices[] = { 215 { HDA_INTEL_82801F, "Intel 82801F" }, 216 { HDA_INTEL_82801G, "Intel 82801G" }, 217 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 218 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 219 { HDA_ATI_SB450, "ATI SB450" }, 220 /* Unknown */ 221 { HDA_INTEL_ALL, "Intel (Unknown)" }, 222 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 223 { HDA_ATI_ALL, "ATI (Unknown)" }, 224}; 225#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 226 227static const struct { 228 uint32_t rate; 229 int valid; 230 uint16_t base; 231 uint16_t mul; 232 uint16_t div; 233} hda_rate_tab[] = { 234 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 235 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 236 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 237 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 238 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 239 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 240 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 241 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 242 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 243 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 244 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 245 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 246 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 247 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 248 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 249 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 250 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 251 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 252 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 253 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 254 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 255 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 256 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 257 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 258 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 259 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 260 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 261 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 262 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 263 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 264 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 265 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 266 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 267 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 268 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 269}; 270#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 271 272/* All codecs you can eat... */ 273#define HDA_CODEC_CONSTRUCT(vendor, id) \ 274 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 275 276/* Realtek */ 277#define REALTEK_VENDORID 0x10ec 278#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 279#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 280#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 281#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 282#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 283 284/* Analog Device */ 285#define ANALOGDEVICE_VENDORID 0x11d4 286#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 287#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 288#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 289#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 290 291/* CMedia */ 292#define CMEDIA_VENDORID 0x434d 293#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 294#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 295 296/* Sigmatel */ 297#define SIGMATEL_VENDORID 0x8384 298#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 299#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 300#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 301#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 302#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 303 304/* 305 * Conexant 306 * 307 * Ok, the truth is, I don't have any idea at all whether 308 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 309 * place that tell me it is "Venice" is from its Windows driver INF. 310 */ 311#define CONEXANT_VENDORID 0x14f1 312#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 313#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 314 315 316/* Codecs */ 317static const struct { 318 uint32_t id; 319 char *name; 320} hdac_codecs[] = { 321 { HDA_CODEC_ALC260, "Realtek ALC260" }, 322 { HDA_CODEC_ALC861, "Realtek ALC861" }, 323 { HDA_CODEC_ALC880, "Realtek ALC880" }, 324 { HDA_CODEC_ALC882, "Realtek ALC882" }, 325 { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 326 { HDA_CODEC_AD1983, "Analog Device AD1983" }, 327 { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 328 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 329 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 330 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 331 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 332 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 333 { HDA_CODEC_CXVENICE, "Conexant Venice" }, 334 /* Unknown codec */ 335 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 336 { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 337 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 338 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 339 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 340}; 341#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 342 343enum { 344 HDAC_HP_SWITCH_CTL, 345 HDAC_HP_SWITCH_CTRL 346}; 347 348static const struct { 349 uint32_t vendormask; 350 uint32_t id; 351 int type; 352 nid_t hpnid; 353 nid_t spkrnid[8]; 354 nid_t eapdnid; 355} hdac_hp_switch[] = { 356 /* Specific OEM models */ 357 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 358 17, { 16, -1 }, 16 }, 359 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 360 6, { 5, -1 }, 5 }, 361 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 362 6, { 5, -1 }, 5 }, 363 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 364 13, { 14, -1 }, -1 }, 365 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 366 13, { 14, -1 }, -1 }, 367 /* 368 * All models that at least come from the same vendor with 369 * simmilar codec. 370 */ 371 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 372 17, { 16, -1 }, 16 }, 373 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 374 6, { 5, -1 }, 5 }, 375 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 376 13, { 14, -1 }, -1 }, 377}; 378#define HDAC_HP_SWITCH_LEN \ 379 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 380 381static const struct { 382 uint32_t vendormask; 383 uint32_t id; 384 nid_t eapdnid; 385 int hp_switch; 386} hdac_eapd_switch[] = { 387 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 388 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 389 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 390}; 391#define HDAC_EAPD_SWITCH_LEN \ 392 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 393 394/**************************************************************************** 395 * Function prototypes 396 ****************************************************************************/ 397static void hdac_intr_handler(void *); 398static int hdac_reset(struct hdac_softc *); 399static int hdac_get_capabilities(struct hdac_softc *); 400static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 401static int hdac_dma_alloc(struct hdac_softc *, 402 struct hdac_dma *, bus_size_t); 403static void hdac_dma_free(struct hdac_dma *); 404static int hdac_mem_alloc(struct hdac_softc *); 405static void hdac_mem_free(struct hdac_softc *); 406static int hdac_irq_alloc(struct hdac_softc *); 407static void hdac_irq_free(struct hdac_softc *); 408static void hdac_corb_init(struct hdac_softc *); 409static void hdac_rirb_init(struct hdac_softc *); 410static void hdac_corb_start(struct hdac_softc *); 411static void hdac_rirb_start(struct hdac_softc *); 412static void hdac_scan_codecs(struct hdac_softc *); 413static int hdac_probe_codec(struct hdac_codec *); 414static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 415static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 416 417static void hdac_attach2(void *); 418 419static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 420 uint32_t, int); 421static void hdac_command_send_internal(struct hdac_softc *, 422 struct hdac_command_list *, int); 423 424static int hdac_probe(device_t); 425static int hdac_attach(device_t); 426static int hdac_detach(device_t); 427static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 428static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 429 uint32_t, int, int); 430static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 431 nid_t, int, int); 432static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 433 nid_t, nid_t, int, int, int, int, int, int); 434static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 435static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 436 437#define hdac_command(a1, a2, a3) \ 438 hdac_command_sendone_internal(a1, a2, a3) 439 440#define hdac_codec_id(d) \ 441 ((uint32_t)((d == NULL) ? 0x00000000 : \ 442 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 443 ((uint32_t)(d)->device_id & 0x0000ffff)))) 444 445static char * 446hdac_codec_name(struct hdac_devinfo *devinfo) 447{ 448 uint32_t id; 449 int i; 450 451 id = hdac_codec_id(devinfo); 452 453 for (i = 0; i < HDAC_CODECS_LEN; i++) { 454 if ((hdac_codecs[i].id & id) == id) 455 return (hdac_codecs[i].name); 456 } 457 458 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 459} 460 461static char * 462hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 463{ 464 static char *ossname[] = SOUND_DEVICE_NAMES; 465 static char *unknown = "???"; 466 int i; 467 468 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 469 if (devmask & (1 << i)) 470 return (ossname[i]); 471 } 472 return (unknown); 473} 474 475static void 476hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 477{ 478 static char *ossname[] = SOUND_DEVICE_NAMES; 479 int i, first = 1; 480 481 bzero(buf, len); 482 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 483 if (mask & (1 << i)) { 484 if (first == 0) 485 strlcat(buf, ", ", len); 486 strlcat(buf, ossname[i], len); 487 first = 0; 488 } 489 } 490} 491 492static struct hdac_audio_ctl * 493hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 494{ 495 if (devinfo == NULL || 496 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 497 index == NULL || devinfo->function.audio.ctl == NULL || 498 devinfo->function.audio.ctlcnt < 1 || 499 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 500 return (NULL); 501 return (&devinfo->function.audio.ctl[(*index)++]); 502} 503 504static struct hdac_audio_ctl * 505hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 506 int index, int cnt) 507{ 508 struct hdac_audio_ctl *ctl, *retctl = NULL; 509 int i, at, atindex, found = 0; 510 511 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 512 return (NULL); 513 514 at = cnt; 515 if (at == 0) 516 at = 1; 517 else if (at < 0) 518 at = -1; 519 atindex = index; 520 if (atindex < 0) 521 atindex = -1; 522 523 i = 0; 524 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 525 if (ctl->enable == 0 || ctl->widget == NULL) 526 continue; 527 if (!(ctl->widget->nid == nid && (atindex == -1 || 528 ctl->index == atindex))) 529 continue; 530 found++; 531 if (found == cnt) 532 return (ctl); 533 retctl = ctl; 534 } 535 536 return ((at == -1) ? retctl : NULL); 537} 538 539static void 540hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 541{ 542 struct hdac_softc *sc; 543 struct hdac_widget *w; 544 struct hdac_audio_ctl *ctl; 545 uint32_t id, res; 546 int i = 0, j, forcemute; 547 nid_t cad; 548 549 if (devinfo == NULL || devinfo->codec == NULL || 550 devinfo->codec->sc == NULL) 551 return; 552 553 sc = devinfo->codec->sc; 554 cad = devinfo->codec->cad; 555 id = hdac_codec_id(devinfo); 556 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 557 if ((hdac_hp_switch[i].vendormask & sc->pci_subvendor) == 558 sc->pci_subvendor && 559 hdac_hp_switch[i].id == id) 560 break; 561 } 562 563 if (i >= HDAC_HP_SWITCH_LEN) 564 return; 565 566 forcemute = 0; 567 if (hdac_hp_switch[i].eapdnid != -1) { 568 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 569 if (w != NULL && w->param.eapdbtl != 0xffffffff) 570 forcemute = (w->param.eapdbtl & 571 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 572 } 573 574 res = hdac_command(sc, 575 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 576 HDA_BOOTVERBOSE_MSG( 577 device_printf(sc->dev, 578 "Pin sense: nid=%d res=0x%08x\n", 579 hdac_hp_switch[i].hpnid, res); 580 ); 581 res >>= 31; 582 583 switch (hdac_hp_switch[i].type) { 584 case HDAC_HP_SWITCH_CTL: 585 ctl = hdac_audio_ctl_amp_get(devinfo, 586 hdac_hp_switch[i].hpnid, 0, 1); 587 if (ctl != NULL) { 588 ctl->muted = (res != 0 && forcemute == 0) ? 589 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 590 hdac_audio_ctl_amp_set(ctl, 591 HDA_AMP_MUTE_DEFAULT, ctl->left, 592 ctl->right); 593 } 594 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 595 ctl = hdac_audio_ctl_amp_get(devinfo, 596 hdac_hp_switch[i].spkrnid[j], 0, 1); 597 if (ctl != NULL) { 598 ctl->muted = (res != 0 || forcemute == 1) ? 599 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 600 hdac_audio_ctl_amp_set(ctl, 601 HDA_AMP_MUTE_DEFAULT, ctl->left, 602 ctl->right); 603 } 604 } 605 break; 606 case HDAC_HP_SWITCH_CTRL: 607 if (res != 0) { 608 /* HP in */ 609 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 610 if (w != NULL) { 611 if (forcemute == 0) 612 w->wclass.pin.ctrl |= 613 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 614 else 615 w->wclass.pin.ctrl &= 616 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 617 hdac_command(sc, 618 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 619 w->wclass.pin.ctrl), cad); 620 } 621 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 622 w = hdac_widget_get(devinfo, 623 hdac_hp_switch[i].spkrnid[j]); 624 if (w != NULL) { 625 w->wclass.pin.ctrl &= 626 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 627 hdac_command(sc, 628 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 629 w->nid, 630 w->wclass.pin.ctrl), cad); 631 } 632 } 633 } else { 634 /* HP out */ 635 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 636 if (w != NULL) { 637 w->wclass.pin.ctrl &= 638 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 639 hdac_command(sc, 640 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 641 w->wclass.pin.ctrl), cad); 642 } 643 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 644 w = hdac_widget_get(devinfo, 645 hdac_hp_switch[i].spkrnid[j]); 646 if (w != NULL) { 647 if (forcemute == 0) 648 w->wclass.pin.ctrl |= 649 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 650 else 651 w->wclass.pin.ctrl &= 652 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 653 hdac_command(sc, 654 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 655 w->nid, 656 w->wclass.pin.ctrl), cad); 657 } 658 } 659 } 660 break; 661 default: 662 break; 663 } 664} 665 666static void 667hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 668{ 669 struct hdac_softc *sc; 670 struct hdac_devinfo *devinfo = NULL; 671 device_t *devlist; 672 int devcount, i; 673 674 if (codec == NULL || codec->sc == NULL) 675 return; 676 677 sc = codec->sc; 678 679 HDA_BOOTVERBOSE_MSG( 680 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 681 ); 682 683 device_get_children(sc->dev, &devlist, &devcount); 684 if (devcount != 0 && devlist != NULL) { 685 for (i = 0; i < devcount; i++) { 686 devinfo = (struct hdac_devinfo *) 687 device_get_ivars(devlist[i]); 688 if (devinfo != NULL && 689 devinfo->node_type == 690 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 691 devinfo->codec != NULL && 692 devinfo->codec->cad == codec->cad) { 693 break; 694 } else 695 devinfo = NULL; 696 } 697 } 698 if (devinfo == NULL) 699 return; 700 701 switch (tag) { 702 case HDAC_UNSOLTAG_EVENT_HP: 703 hdac_hp_switch_handler(devinfo); 704 break; 705 default: 706 break; 707 } 708} 709 710static void 711hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 712{ 713 /* XXX to be removed */ 714#ifdef HDAC_INTR_EXTRA 715 uint32_t res; 716#endif 717 718 if (ch->blkcnt == 0) 719 return; 720 721 /* XXX to be removed */ 722#ifdef HDAC_INTR_EXTRA 723 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 724#endif 725 726 /* XXX to be removed */ 727#ifdef HDAC_INTR_EXTRA 728 if ((res & HDAC_SDSTS_DESE) || (res & HDAC_SDSTS_FIFOE)) 729 device_printf(sc->dev, 730 "PCMDIR_%s intr triggered beyond stream boundary: %08x\n", 731 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 732#endif 733 734 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 735 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 736 737 /* XXX to be removed */ 738#ifdef HDAC_INTR_EXTRA 739 if (res & HDAC_SDSTS_BCIS) { 740#endif 741 ch->prevptr = ch->ptr; 742 ch->ptr += sndbuf_getblksz(ch->b); 743 ch->ptr %= sndbuf_getsize(ch->b); 744 hdac_unlock(sc); 745 chn_intr(ch->c); 746 hdac_lock(sc); 747 /* XXX to be removed */ 748#ifdef HDAC_INTR_EXTRA 749 } 750#endif 751} 752 753/**************************************************************************** 754 * void hdac_intr_handler(void *) 755 * 756 * Interrupt handler. Processes interrupts received from the hdac. 757 ****************************************************************************/ 758static void 759hdac_intr_handler(void *context) 760{ 761 struct hdac_softc *sc; 762 uint32_t intsts; 763 uint8_t rirbsts; 764 uint8_t rirbwp; 765 struct hdac_rirb *rirb_base, *rirb; 766 nid_t ucad; 767 uint32_t utag; 768 769 sc = (struct hdac_softc *)context; 770 771 hdac_lock(sc); 772 /* Do we have anything to do? */ 773 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 774 if ((intsts & HDAC_INTSTS_GIS) != HDAC_INTSTS_GIS) { 775 hdac_unlock(sc); 776 return; 777 } 778 779 /* Was this a controller interrupt? */ 780 if ((intsts & HDAC_INTSTS_CIS) == HDAC_INTSTS_CIS) { 781 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 782 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 783 /* Get as many responses that we can */ 784 while ((rirbsts & HDAC_RIRBSTS_RINTFL) == HDAC_RIRBSTS_RINTFL) { 785 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 786 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 787 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 788 BUS_DMASYNC_POSTREAD); 789 while (sc->rirb_rp != rirbwp) { 790 sc->rirb_rp++; 791 sc->rirb_rp %= sc->rirb_size; 792 rirb = &rirb_base[sc->rirb_rp]; 793 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 794 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 795 utag = rirb->response >> 26; 796 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 797 sc->codecs[ucad] != NULL) { 798 sc->unsolq[sc->unsolq_wp++] = 799 (ucad << 16) | 800 (utag & 0xffff); 801 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 802 } 803 } 804 } 805 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 806 } 807 /* XXX to be removed */ 808 /* Clear interrupt and exit */ 809#ifdef HDAC_INTR_EXTRA 810 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 811#endif 812 } 813 if ((intsts & HDAC_INTSTS_SIS_MASK)) { 814 if (intsts & (1 << sc->num_iss)) 815 hdac_stream_intr(sc, &sc->play); 816 if (intsts & (1 << 0)) 817 hdac_stream_intr(sc, &sc->rec); 818 /* XXX to be removed */ 819#ifdef HDAC_INTR_EXTRA 820 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & HDAC_INTSTS_SIS_MASK); 821#endif 822 } 823 824 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 825 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 826 while (sc->unsolq_rp != sc->unsolq_wp) { 827 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 828 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 829 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 830 hdac_unsolicited_handler(sc->codecs[ucad], utag); 831 } 832 sc->unsolq_st = HDAC_UNSOLQ_READY; 833 } 834 835 hdac_unlock(sc); 836} 837 838/**************************************************************************** 839 * int had_reset(hdac_softc *) 840 * 841 * Reset the hdac to a quiescent and known state. 842 ****************************************************************************/ 843static int 844hdac_reset(struct hdac_softc *sc) 845{ 846 uint32_t gctl; 847 int count, i; 848 849 /* 850 * Stop all Streams DMA engine 851 */ 852 for (i = 0; i < sc->num_iss; i++) 853 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 854 for (i = 0; i < sc->num_oss; i++) 855 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 856 for (i = 0; i < sc->num_bss; i++) 857 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 858 859 /* 860 * Stop Control DMA engines 861 */ 862 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 863 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 864 865 /* 866 * Reset the controller. The reset must remain asserted for 867 * a minimum of 100us. 868 */ 869 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 870 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 871 count = 10000; 872 do { 873 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 874 if (!(gctl & HDAC_GCTL_CRST)) 875 break; 876 DELAY(10); 877 } while (--count); 878 if (gctl & HDAC_GCTL_CRST) { 879 device_printf(sc->dev, "Unable to put hdac in reset\n"); 880 return (ENXIO); 881 } 882 DELAY(100); 883 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 884 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 885 count = 10000; 886 do { 887 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 888 if ((gctl & HDAC_GCTL_CRST)) 889 break; 890 DELAY(10); 891 } while (--count); 892 if (!(gctl & HDAC_GCTL_CRST)) { 893 device_printf(sc->dev, "Device stuck in reset\n"); 894 return (ENXIO); 895 } 896 897 /* 898 * Enable unsolicited interrupt. 899 */ 900 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 901 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_UNSOL); 902 903 /* 904 * Wait for codecs to finish their own reset sequence. The delay here 905 * should be of 250us but for some reasons, on it's not enough on my 906 * computer. Let's use twice as much as necessary to make sure that 907 * it's reset properly. 908 */ 909 DELAY(1000); 910 911 return (0); 912} 913 914 915/**************************************************************************** 916 * int hdac_get_capabilities(struct hdac_softc *); 917 * 918 * Retreive the general capabilities of the hdac; 919 * Number of Input Streams 920 * Number of Output Streams 921 * Number of bidirectional Streams 922 * 64bit ready 923 * CORB and RIRB sizes 924 ****************************************************************************/ 925static int 926hdac_get_capabilities(struct hdac_softc *sc) 927{ 928 uint16_t gcap; 929 uint8_t corbsize, rirbsize; 930 931 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 932 sc->num_iss = HDAC_GCAP_ISS(gcap); 933 sc->num_oss = HDAC_GCAP_OSS(gcap); 934 sc->num_bss = HDAC_GCAP_BSS(gcap); 935 936 sc->support_64bit = (gcap & HDAC_GCAP_64OK) == HDAC_GCAP_64OK; 937 938 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 939 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 940 HDAC_CORBSIZE_CORBSZCAP_256) 941 sc->corb_size = 256; 942 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 943 HDAC_CORBSIZE_CORBSZCAP_16) 944 sc->corb_size = 16; 945 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 946 HDAC_CORBSIZE_CORBSZCAP_2) 947 sc->corb_size = 2; 948 else { 949 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 950 __func__, corbsize); 951 return (ENXIO); 952 } 953 954 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 955 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 956 HDAC_RIRBSIZE_RIRBSZCAP_256) 957 sc->rirb_size = 256; 958 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 959 HDAC_RIRBSIZE_RIRBSZCAP_16) 960 sc->rirb_size = 16; 961 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 962 HDAC_RIRBSIZE_RIRBSZCAP_2) 963 sc->rirb_size = 2; 964 else { 965 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 966 __func__, rirbsize); 967 return (ENXIO); 968 } 969 970 return (0); 971} 972 973 974/**************************************************************************** 975 * void hdac_dma_cb 976 * 977 * This function is called by bus_dmamap_load when the mapping has been 978 * established. We just record the physical address of the mapping into 979 * the struct hdac_dma passed in. 980 ****************************************************************************/ 981static void 982hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 983{ 984 struct hdac_dma *dma; 985 986 if (error == 0) { 987 dma = (struct hdac_dma *)callback_arg; 988 dma->dma_paddr = segs[0].ds_addr; 989 } 990} 991 992static void 993hdac_dma_nocache(void *ptr) 994{ 995 pt_entry_t *pte; 996 vm_offset_t va; 997 998 va = (vm_offset_t)ptr; 999 pte = vtopte(va); 1000 if (pte) { 1001 *pte |= PG_N; 1002 invltlb(); 1003 } 1004} 1005 1006/**************************************************************************** 1007 * int hdac_dma_alloc 1008 * 1009 * This function allocate and setup a dma region (struct hdac_dma). 1010 * It must be freed by a corresponding hdac_dma_free. 1011 ****************************************************************************/ 1012static int 1013hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1014{ 1015 int result; 1016 int lowaddr; 1017 1018 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1019 BUS_SPACE_MAXADDR_32BIT; 1020 bzero(dma, sizeof(*dma)); 1021 1022 /* 1023 * Create a DMA tag 1024 */ 1025 result = bus_dma_tag_create(NULL, /* parent */ 1026 HDAC_DMA_ALIGNMENT, /* alignment */ 1027 0, /* boundary */ 1028 lowaddr, /* lowaddr */ 1029 BUS_SPACE_MAXADDR, /* highaddr */ 1030 NULL, /* filtfunc */ 1031 NULL, /* fistfuncarg */ 1032 size, /* maxsize */ 1033 1, /* nsegments */ 1034 size, /* maxsegsz */ 1035 0, /* flags */ 1036 NULL, /* lockfunc */ 1037 NULL, /* lockfuncarg */ 1038 &dma->dma_tag); /* dmat */ 1039 if (result != 0) { 1040 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1041 __func__, result); 1042 goto fail; 1043 } 1044 1045 /* 1046 * Allocate DMA memory 1047 */ 1048 result = bus_dmamem_alloc(dma->dma_tag, (void **) &dma->dma_vaddr, 1049 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1050 if (result != 0) { 1051 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1052 __func__, result); 1053 goto fail; 1054 } 1055 1056 /* 1057 * Map the memory 1058 */ 1059 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1060 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1061 BUS_DMA_NOWAIT); 1062 if (result != 0 || dma->dma_paddr == 0) { 1063 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1064 __func__, result); 1065 goto fail; 1066 } 1067 bzero((void *)dma->dma_vaddr, size); 1068 hdac_dma_nocache(dma->dma_vaddr); 1069 1070 return (0); 1071fail: 1072 if (dma->dma_map != NULL) 1073 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1074 if (dma->dma_tag != NULL) 1075 bus_dma_tag_destroy(dma->dma_tag); 1076 return (result); 1077} 1078 1079 1080/**************************************************************************** 1081 * void hdac_dma_free(struct hdac_dma *) 1082 * 1083 * Free a struct dhac_dma that has been previously allocated via the 1084 * hdac_dma_alloc function. 1085 ****************************************************************************/ 1086static void 1087hdac_dma_free(struct hdac_dma *dma) 1088{ 1089 if (dma->dma_tag != NULL) { 1090 /* Flush caches */ 1091 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1092 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1093 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1094 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1095 bus_dma_tag_destroy(dma->dma_tag); 1096 } 1097} 1098 1099/**************************************************************************** 1100 * int hdac_mem_alloc(struct hdac_softc *) 1101 * 1102 * Allocate all the bus resources necessary to speak with the physical 1103 * controller. 1104 ****************************************************************************/ 1105static int 1106hdac_mem_alloc(struct hdac_softc *sc) 1107{ 1108 struct hdac_mem *mem; 1109 1110 mem = &sc->mem; 1111 mem->mem_rid = PCIR_BAR(0); 1112 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1113 &mem->mem_rid, RF_ACTIVE); 1114 if (mem->mem_res == NULL) { 1115 device_printf(sc->dev, 1116 "%s: Unable to allocate memory resource\n", __func__); 1117 return (ENOMEM); 1118 } 1119 mem->mem_tag = rman_get_bustag(mem->mem_res); 1120 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1121 1122 return (0); 1123} 1124 1125/**************************************************************************** 1126 * void hdac_mem_free(struct hdac_softc *) 1127 * 1128 * Free up resources previously allocated by hdac_mem_alloc. 1129 ****************************************************************************/ 1130static void 1131hdac_mem_free(struct hdac_softc *sc) 1132{ 1133 struct hdac_mem *mem; 1134 1135 mem = &sc->mem; 1136 if (mem->mem_res != NULL) 1137 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1138 mem->mem_res); 1139} 1140 1141/**************************************************************************** 1142 * int hdac_irq_alloc(struct hdac_softc *) 1143 * 1144 * Allocate and setup the resources necessary for interrupt handling. 1145 ****************************************************************************/ 1146static int 1147hdac_irq_alloc(struct hdac_softc *sc) 1148{ 1149 struct hdac_irq *irq; 1150 int result; 1151 1152 irq = &sc->irq; 1153 irq->irq_rid = 0x0; 1154 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1155 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1156 if (irq->irq_res == NULL) { 1157 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1158 __func__); 1159 goto fail; 1160 } 1161 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1162 hdac_intr_handler, sc, &irq->irq_handle); 1163 if (result != 0) { 1164 device_printf(sc->dev, 1165 "%s: Unable to setup interrupt handler (%x)\n", 1166 __func__, result); 1167 goto fail; 1168 } 1169 1170 return (0); 1171 1172fail: 1173 if (irq->irq_res != NULL) 1174 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1175 irq->irq_res); 1176 return (ENXIO); 1177} 1178 1179/**************************************************************************** 1180 * void hdac_irq_free(struct hdac_softc *) 1181 * 1182 * Free up resources previously allocated by hdac_irq_alloc. 1183 ****************************************************************************/ 1184static void 1185hdac_irq_free(struct hdac_softc *sc) 1186{ 1187 struct hdac_irq *irq; 1188 1189 irq = &sc->irq; 1190 if (irq->irq_handle != NULL) 1191 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1192 if (irq->irq_res != NULL) 1193 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1194 irq->irq_res); 1195} 1196 1197/**************************************************************************** 1198 * void hdac_corb_init(struct hdac_softc *) 1199 * 1200 * Initialize the corb registers for operations but do not start it up yet. 1201 * The CORB engine must not be running when this function is called. 1202 ****************************************************************************/ 1203static void 1204hdac_corb_init(struct hdac_softc *sc) 1205{ 1206 uint8_t corbsize; 1207 uint64_t corbpaddr; 1208 1209 /* Setup the CORB size. */ 1210 switch (sc->corb_size) { 1211 case 256: 1212 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1213 break; 1214 case 16: 1215 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1216 break; 1217 case 2: 1218 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1219 break; 1220 default: 1221 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1222 } 1223 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1224 1225 /* Setup the CORB Address in the hdac */ 1226 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1227 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1228 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1229 1230 /* Set the WP and RP */ 1231 sc->corb_wp = 0; 1232 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1233 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1234 /* 1235 * The HDA specification indicates that the CORBRPRST bit will always 1236 * read as zero. Unfortunately, it seems that at least the 82801G 1237 * doesn't reset the bit to zero, which stalls the corb engine. 1238 * manually reset the bit to zero before continuing. 1239 */ 1240 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1241 1242 /* Enable CORB error reporting */ 1243#if 0 1244 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1245#endif 1246} 1247 1248/**************************************************************************** 1249 * void hdac_rirb_init(struct hdac_softc *) 1250 * 1251 * Initialize the rirb registers for operations but do not start it up yet. 1252 * The RIRB engine must not be running when this function is called. 1253 ****************************************************************************/ 1254static void 1255hdac_rirb_init(struct hdac_softc *sc) 1256{ 1257 uint8_t rirbsize; 1258 uint64_t rirbpaddr; 1259 1260 /* Setup the RIRB size. */ 1261 switch (sc->rirb_size) { 1262 case 256: 1263 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1264 break; 1265 case 16: 1266 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1267 break; 1268 case 2: 1269 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1270 break; 1271 default: 1272 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1273 } 1274 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1275 1276 /* Setup the RIRB Address in the hdac */ 1277 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1278 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1279 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1280 1281 /* Setup the WP and RP */ 1282 sc->rirb_rp = 0; 1283 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1284 1285 /* Setup the interrupt threshold */ 1286 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1287 1288 /* Enable Overrun and response received reporting */ 1289#if 0 1290 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1291 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1292#else 1293 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1294#endif 1295 1296 /* 1297 * Make sure that the Host CPU cache doesn't contain any dirty 1298 * cache lines that falls in the rirb. If I understood correctly, it 1299 * should be sufficient to do this only once as the rirb is purely 1300 * read-only from now on. 1301 */ 1302 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1303 BUS_DMASYNC_PREREAD); 1304} 1305 1306/**************************************************************************** 1307 * void hdac_corb_start(hdac_softc *) 1308 * 1309 * Startup the corb DMA engine 1310 ****************************************************************************/ 1311static void 1312hdac_corb_start(struct hdac_softc *sc) 1313{ 1314 uint32_t corbctl; 1315 1316 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1317 corbctl |= HDAC_CORBCTL_CORBRUN; 1318 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1319} 1320 1321/**************************************************************************** 1322 * void hdac_rirb_start(hdac_softc *) 1323 * 1324 * Startup the rirb DMA engine 1325 ****************************************************************************/ 1326static void 1327hdac_rirb_start(struct hdac_softc *sc) 1328{ 1329 uint32_t rirbctl; 1330 1331 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1332 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1333 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1334} 1335 1336 1337/**************************************************************************** 1338 * void hdac_scan_codecs(struct hdac_softc *) 1339 * 1340 * Scan the bus for available codecs. 1341 ****************************************************************************/ 1342static void 1343hdac_scan_codecs(struct hdac_softc *sc) 1344{ 1345 struct hdac_codec *codec; 1346 int i; 1347 uint16_t statests; 1348 1349 SLIST_INIT(&sc->codec_list); 1350 1351 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1352 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1353 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1354 /* We have found a codec. */ 1355 hdac_unlock(sc); 1356 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1357 M_HDAC, M_ZERO | M_NOWAIT); 1358 hdac_lock(sc); 1359 if (codec == NULL) { 1360 device_printf(sc->dev, 1361 "Unable to allocate memory for codec\n"); 1362 continue; 1363 } 1364 codec->verbs_sent = 0; 1365 codec->sc = sc; 1366 codec->cad = i; 1367 sc->codecs[i] = codec; 1368 SLIST_INSERT_HEAD(&sc->codec_list, codec, next_codec); 1369 if (hdac_probe_codec(codec) != 0) 1370 break; 1371 } 1372 } 1373 /* All codecs have been probed, now try to attach drivers to them */ 1374 bus_generic_attach(sc->dev); 1375} 1376 1377/**************************************************************************** 1378 * void hdac_probe_codec(struct hdac_softc *, int) 1379 * 1380 * Probe a the given codec_id for available function groups. 1381 ****************************************************************************/ 1382static int 1383hdac_probe_codec(struct hdac_codec *codec) 1384{ 1385 struct hdac_softc *sc = codec->sc; 1386 struct hdac_devinfo *devinfo; 1387 uint32_t vendorid, revisionid, subnode; 1388 int startnode; 1389 int endnode; 1390 int i; 1391 nid_t cad = codec->cad; 1392 1393 HDA_DEBUG_MSG( 1394 device_printf(sc->dev, "%s: Probing codec: %d\n", 1395 __func__, cad); 1396 ); 1397 vendorid = hdac_command(sc, 1398 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1399 cad); 1400 revisionid = hdac_command(sc, 1401 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1402 cad); 1403 subnode = hdac_command(sc, 1404 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1405 cad); 1406 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1407 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1408 1409 HDA_DEBUG_MSG( 1410 device_printf(sc->dev, "%s: \tstartnode=%d endnode=%d\n", 1411 __func__, startnode, endnode); 1412 ); 1413 for (i = startnode; i < endnode; i++) { 1414 devinfo = hdac_probe_function(codec, i); 1415 if (devinfo != NULL) { 1416 /* XXX Ignore other FG. */ 1417 devinfo->vendor_id = 1418 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1419 devinfo->device_id = 1420 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1421 devinfo->revision_id = 1422 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1423 devinfo->stepping_id = 1424 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1425 HDA_DEBUG_MSG( 1426 device_printf(sc->dev, 1427 "%s: \tFound AFG nid=%d " 1428 "[startnode=%d endnode=%d]\n", 1429 __func__, devinfo->nid, 1430 startnode, endnode); 1431 ); 1432 return (1); 1433 } 1434 } 1435 1436 HDA_DEBUG_MSG( 1437 device_printf(sc->dev, "%s: \tAFG not found\n", 1438 __func__); 1439 ); 1440 return (0); 1441} 1442 1443static struct hdac_devinfo * 1444hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1445{ 1446 struct hdac_softc *sc = codec->sc; 1447 struct hdac_devinfo *devinfo; 1448 uint32_t fctgrptype; 1449 nid_t cad = codec->cad; 1450 1451 fctgrptype = hdac_command(sc, 1452 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad); 1453 1454 /* XXX For now, ignore other FG. */ 1455 if (HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(fctgrptype) != 1456 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1457 return (NULL); 1458 1459 hdac_unlock(sc); 1460 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1461 M_NOWAIT | M_ZERO); 1462 hdac_lock(sc); 1463 if (devinfo == NULL) { 1464 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1465 __func__); 1466 return (NULL); 1467 } 1468 1469 devinfo->nid = nid; 1470 devinfo->node_type = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(fctgrptype); 1471 devinfo->codec = codec; 1472 1473 hdac_add_child(sc, devinfo); 1474 1475 return (devinfo); 1476} 1477 1478static void 1479hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1480{ 1481 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1482 device_set_ivars(devinfo->dev, (void *)devinfo); 1483 /* XXX - Print more information when booting verbose??? */ 1484} 1485 1486static void 1487hdac_widget_connection_parse(struct hdac_widget *w) 1488{ 1489 struct hdac_softc *sc = w->devinfo->codec->sc; 1490 uint32_t res; 1491 int i, j, max, found, entnum, cnid; 1492 nid_t cad = w->devinfo->codec->cad; 1493 nid_t nid = w->nid; 1494 1495 res = hdac_command(sc, 1496 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1497 1498 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1499 1500 if (w->nconns < 1) 1501 return; 1502 1503 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1504 res = 0; 1505 i = 0; 1506 found = 0; 1507 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1508 1509 while (i < w->nconns) { 1510 res = hdac_command(sc, 1511 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1512 for (j = 0; j < entnum; j++) { 1513 cnid = res; 1514 cnid >>= (32 / entnum) * j; 1515 cnid &= (1 << (32 / entnum)) - 1; 1516 if (cnid == 0) 1517 continue; 1518 if (found > max) { 1519 device_printf(sc->dev, 1520 "node %d: Adding %d: " 1521 "Max connection reached!\n", 1522 nid, cnid); 1523 continue; 1524 } 1525 w->conns[found++] = cnid; 1526 } 1527 i += entnum; 1528 } 1529 1530 HDA_BOOTVERBOSE_MSG( 1531 if (w->nconns != found) { 1532 device_printf(sc->dev, 1533 "node %d: WARNING!!! Connection " 1534 "length=%d != found=%d\n", 1535 nid, w->nconns, found); 1536 } 1537 ); 1538} 1539 1540static uint32_t 1541hdac_widget_pin_getconfig(struct hdac_widget *w) 1542{ 1543 struct hdac_softc *sc; 1544 uint32_t config, id; 1545 nid_t cad, nid; 1546 1547 sc = w->devinfo->codec->sc; 1548 cad = w->devinfo->codec->cad; 1549 nid = w->nid; 1550 id = hdac_codec_id(w->devinfo); 1551 1552 config = hdac_command(sc, 1553 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1554 cad); 1555 if (id == HDA_CODEC_ALC880 && 1556 sc->pci_subvendor == CLEVO_D900T_SUBVENDOR) { 1557 /* 1558 * Super broken BIOS: Clevo D900T 1559 */ 1560 switch (nid) { 1561 case 20: 1562 break; 1563 case 21: 1564 break; 1565 case 22: 1566 break; 1567 case 23: 1568 break; 1569 case 24: /* MIC1 */ 1570 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1571 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1572 break; 1573 case 25: /* XXX MIC2 */ 1574 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1575 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1576 break; 1577 case 26: /* LINE1 */ 1578 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1579 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1580 break; 1581 case 27: /* XXX LINE2 */ 1582 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1583 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1584 break; 1585 case 28: /* CD */ 1586 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1587 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1588 break; 1589 case 30: 1590 break; 1591 case 31: 1592 break; 1593 default: 1594 break; 1595 } 1596 } 1597 1598 return (config); 1599} 1600 1601static void 1602hdac_widget_pin_parse(struct hdac_widget *w) 1603{ 1604 struct hdac_softc *sc = w->devinfo->codec->sc; 1605 uint32_t config, pincap; 1606 char *devstr, *connstr; 1607 nid_t cad = w->devinfo->codec->cad; 1608 nid_t nid = w->nid; 1609 1610 config = hdac_widget_pin_getconfig(w); 1611 w->wclass.pin.config = config; 1612 1613 pincap = hdac_command(sc, 1614 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1615 w->wclass.pin.cap = pincap; 1616 1617 w->wclass.pin.ctrl = hdac_command(sc, 1618 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1619 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1620 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1621 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1622 1623 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1624 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1625 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1626 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1627 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1628 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1629 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1630 w->param.eapdbtl = hdac_command(sc, 1631 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1632 w->param.eapdbtl &= 0x7; 1633 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1634 } else 1635 w->param.eapdbtl = 0xffffffff; 1636 1637 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1638 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1639 devstr = "line out"; 1640 break; 1641 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1642 devstr = "speaker"; 1643 break; 1644 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1645 devstr = "headphones out"; 1646 break; 1647 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1648 devstr = "CD"; 1649 break; 1650 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1651 devstr = "SPDIF out"; 1652 break; 1653 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1654 devstr = "digital (other) out"; 1655 break; 1656 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1657 devstr = "modem, line side"; 1658 break; 1659 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1660 devstr = "modem, handset side"; 1661 break; 1662 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1663 devstr = "line in"; 1664 break; 1665 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1666 devstr = "AUX"; 1667 break; 1668 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1669 devstr = "Mic in"; 1670 break; 1671 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1672 devstr = "telephony"; 1673 break; 1674 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1675 devstr = "SPDIF in"; 1676 break; 1677 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1678 devstr = "digital (other) in"; 1679 break; 1680 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1681 devstr = "other"; 1682 break; 1683 default: 1684 devstr = "unknown"; 1685 break; 1686 } 1687 1688 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1689 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1690 connstr = "jack"; 1691 break; 1692 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1693 connstr = "none"; 1694 break; 1695 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1696 connstr = "fixed"; 1697 break; 1698 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1699 connstr = "jack / fixed"; 1700 break; 1701 default: 1702 connstr = "unknown"; 1703 break; 1704 } 1705 1706 strlcat(w->name, ": ", sizeof(w->name)); 1707 strlcat(w->name, devstr, sizeof(w->name)); 1708 strlcat(w->name, " (", sizeof(w->name)); 1709 strlcat(w->name, connstr, sizeof(w->name)); 1710 strlcat(w->name, ")", sizeof(w->name)); 1711} 1712 1713static void 1714hdac_widget_parse(struct hdac_widget *w) 1715{ 1716 struct hdac_softc *sc = w->devinfo->codec->sc; 1717 uint32_t wcap, cap; 1718 char *typestr; 1719 nid_t cad = w->devinfo->codec->cad; 1720 nid_t nid = w->nid; 1721 1722 wcap = hdac_command(sc, 1723 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1724 cad); 1725 w->param.widget_cap = wcap; 1726 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1727 1728 switch (w->type) { 1729 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1730 typestr = "audio output"; 1731 break; 1732 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1733 typestr = "audio input"; 1734 break; 1735 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1736 typestr = "audio mixer"; 1737 break; 1738 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1739 typestr = "audio selector"; 1740 break; 1741 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1742 typestr = "pin"; 1743 break; 1744 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1745 typestr = "power widget"; 1746 break; 1747 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1748 typestr = "volume widget"; 1749 break; 1750 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1751 typestr = "beep widget"; 1752 break; 1753 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1754 typestr = "vendor widget"; 1755 break; 1756 default: 1757 typestr = "unknown type"; 1758 break; 1759 } 1760 1761 strlcpy(w->name, typestr, sizeof(w->name)); 1762 1763 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1764 hdac_command(sc, 1765 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 1766 cad); 1767 DELAY(1000); 1768 } 1769 1770 hdac_widget_connection_parse(w); 1771 1772 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 1773 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1774 w->param.outamp_cap = 1775 hdac_command(sc, 1776 HDA_CMD_GET_PARAMETER(cad, nid, 1777 HDA_PARAM_OUTPUT_AMP_CAP), cad); 1778 else 1779 w->param.outamp_cap = 1780 w->devinfo->function.audio.outamp_cap; 1781 } else 1782 w->param.outamp_cap = 0; 1783 1784 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 1785 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 1786 w->param.inamp_cap = 1787 hdac_command(sc, 1788 HDA_CMD_GET_PARAMETER(cad, nid, 1789 HDA_PARAM_INPUT_AMP_CAP), cad); 1790 else 1791 w->param.inamp_cap = 1792 w->devinfo->function.audio.inamp_cap; 1793 } else 1794 w->param.inamp_cap = 0; 1795 1796 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 1797 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 1798 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 1799 cap = hdac_command(sc, 1800 HDA_CMD_GET_PARAMETER(cad, nid, 1801 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 1802 w->param.supp_stream_formats = (cap != 0) ? cap : 1803 w->devinfo->function.audio.supp_stream_formats; 1804 cap = hdac_command(sc, 1805 HDA_CMD_GET_PARAMETER(cad, nid, 1806 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 1807 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 1808 w->devinfo->function.audio.supp_pcm_size_rate; 1809 } else { 1810 w->param.supp_stream_formats = 1811 w->devinfo->function.audio.supp_stream_formats; 1812 w->param.supp_pcm_size_rate = 1813 w->devinfo->function.audio.supp_pcm_size_rate; 1814 } 1815 } else { 1816 w->param.supp_stream_formats = 0; 1817 w->param.supp_pcm_size_rate = 0; 1818 } 1819 1820 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1821 hdac_widget_pin_parse(w); 1822} 1823 1824static struct hdac_widget * 1825hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 1826{ 1827 if (devinfo == NULL || devinfo->widget == NULL || 1828 nid < devinfo->startnode || nid >= devinfo->endnode) 1829 return (NULL); 1830 return (&devinfo->widget[nid - devinfo->startnode]); 1831} 1832 1833static void 1834hdac_stream_stop(struct hdac_chan *ch) 1835{ 1836 struct hdac_softc *sc = ch->devinfo->codec->sc; 1837 uint32_t ctl; 1838 1839 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1840 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1841 HDAC_SDCTL_RUN); 1842 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1843 1844 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1845 ctl &= ~(1 << (ch->off >> 5)); 1846 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1847} 1848 1849static void 1850hdac_stream_start(struct hdac_chan *ch) 1851{ 1852 struct hdac_softc *sc = ch->devinfo->codec->sc; 1853 uint32_t ctl; 1854 1855 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1856 ctl |= 1 << (ch->off >> 5); 1857 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1858 1859 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1860 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1861 HDAC_SDCTL_RUN; 1862 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1863} 1864 1865static void 1866hdac_stream_reset(struct hdac_chan *ch) 1867{ 1868 struct hdac_softc *sc = ch->devinfo->codec->sc; 1869 int timeout = 1000; 1870 int to = timeout; 1871 uint32_t ctl; 1872 1873 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1874 ctl |= HDAC_SDCTL_SRST; 1875 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1876 do { 1877 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1878 if (ctl & HDAC_SDCTL_SRST) 1879 break; 1880 DELAY(10); 1881 } while (--to); 1882 if (!(ctl & HDAC_SDCTL_SRST)) { 1883 device_printf(sc->dev, "timeout in reset\n"); 1884 } 1885 ctl &= ~HDAC_SDCTL_SRST; 1886 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 1887 to = timeout; 1888 do { 1889 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 1890 if (!(ctl & HDAC_SDCTL_SRST)) 1891 break; 1892 DELAY(10); 1893 } while (--to); 1894 if ((ctl & HDAC_SDCTL_SRST)) 1895 device_printf(sc->dev, "can't reset!\n"); 1896} 1897 1898static void 1899hdac_stream_setid(struct hdac_chan *ch) 1900{ 1901 struct hdac_softc *sc = ch->devinfo->codec->sc; 1902 uint32_t ctl; 1903 1904 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 1905 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1906 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 1907 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 1908} 1909 1910static void 1911hdac_bdl_setup(struct hdac_chan *ch) 1912{ 1913 struct hdac_softc *sc = ch->devinfo->codec->sc; 1914 uint64_t addr; 1915 int blks, size, blocksize; 1916 struct hdac_bdle *bdle; 1917 int i; 1918 1919 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 1920 size = sndbuf_getsize(ch->b); 1921 blocksize = sndbuf_getblksz(ch->b); 1922 blks = size / blocksize; 1923 bdle = (struct hdac_bdle*)ch->bdl_dma.dma_vaddr; 1924 1925 for (i = 0; i < blks; i++, bdle++) { 1926 bdle->addrl = (uint32_t)addr; 1927 bdle->addrh = (uint32_t)(addr >> 32); 1928 bdle->len = blocksize; 1929 bdle->ioc = 1; 1930 1931 addr += blocksize; 1932 } 1933 1934 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, size); 1935 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blks - 1); 1936 addr = ch->bdl_dma.dma_paddr; 1937 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 1938 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1939} 1940 1941static int 1942hdac_bdl_alloc(struct hdac_chan *ch) 1943{ 1944 struct hdac_softc *sc = ch->devinfo->codec->sc; 1945 int rc; 1946 1947 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 1948 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1949 if (rc) { 1950 device_printf(sc->dev, "can't alloc bdl\n"); 1951 return (rc); 1952 } 1953 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 1954 1955 return (0); 1956} 1957 1958static void 1959hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 1960 int index, int lmute, int rmute, 1961 int left, int right, int dir) 1962{ 1963 uint16_t v = 0; 1964 1965 if (sc == NULL) 1966 return; 1967 1968 if (left != right || lmute != rmute) { 1969 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 1970 (lmute << 7) | left; 1971 hdac_command(sc, 1972 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 1973 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 1974 (rmute << 7) | right; 1975 } else 1976 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 1977 (lmute << 7) | left; 1978 1979 hdac_command(sc, 1980 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 1981} 1982 1983static void 1984hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 1985 int left, int right) 1986{ 1987 struct hdac_softc *sc; 1988 nid_t nid, cad; 1989 int lmute, rmute; 1990 1991 if (ctl == NULL || ctl->widget == NULL || 1992 ctl->widget->devinfo == NULL || 1993 ctl->widget->devinfo->codec == NULL || 1994 ctl->widget->devinfo->codec->sc == NULL) 1995 return; 1996 1997 sc = ctl->widget->devinfo->codec->sc; 1998 cad = ctl->widget->devinfo->codec->cad; 1999 nid = ctl->widget->nid; 2000 2001 if (mute == HDA_AMP_MUTE_DEFAULT) { 2002 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2003 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2004 } else { 2005 lmute = HDA_AMP_LEFT_MUTED(mute); 2006 rmute = HDA_AMP_RIGHT_MUTED(mute); 2007 } 2008 2009 if (ctl->dir & HDA_CTL_OUT) 2010 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2011 lmute, rmute, left, right, 0); 2012 if (ctl->dir & HDA_CTL_IN) 2013 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2014 lmute, rmute, left, right, 1); 2015 ctl->left = left; 2016 ctl->right = right; 2017} 2018 2019static void 2020hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2021{ 2022 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2023 return; 2024 hdac_command(w->devinfo->codec->sc, 2025 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2026 w->nid, index), w->devinfo->codec->cad); 2027 w->selconn = index; 2028} 2029 2030 2031/**************************************************************************** 2032 * uint32_t hdac_command_sendone_internal 2033 * 2034 * Wrapper function that sends only one command to a given codec 2035 ****************************************************************************/ 2036static uint32_t 2037hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2038{ 2039 struct hdac_command_list cl; 2040 uint32_t response = 0xffffffff; 2041 2042 if (!mtx_owned(sc->lock)) 2043 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2044 cl.num_commands = 1; 2045 cl.verbs = &verb; 2046 cl.responses = &response; 2047 2048 hdac_command_send_internal(sc, &cl, cad); 2049 2050 return (response); 2051} 2052 2053/**************************************************************************** 2054 * hdac_command_send_internal 2055 * 2056 * Send a command list to the codec via the corb. We queue as much verbs as 2057 * we can and msleep on the codec. When the interrupt get the responses 2058 * back from the rirb, it will wake us up so we can queue the remaining verbs 2059 * if any. 2060 ****************************************************************************/ 2061static void 2062hdac_command_send_internal(struct hdac_softc *sc, 2063 struct hdac_command_list *commands, nid_t cad) 2064{ 2065 struct hdac_codec *codec; 2066 int corbrp; 2067 uint32_t *corb; 2068 uint8_t rirbwp; 2069 int timeout; 2070 int retry = 10; 2071 struct hdac_rirb *rirb_base, *rirb; 2072 nid_t ucad; 2073 uint32_t utag; 2074 2075 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL) 2076 return; 2077 2078 codec = sc->codecs[cad]; 2079 codec->commands = commands; 2080 codec->responses_received = 0; 2081 codec->verbs_sent = 0; 2082 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2083 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2084 2085 do { 2086 if (codec->verbs_sent != commands->num_commands) { 2087 /* Queue as many verbs as possible */ 2088 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2089 bus_dmamap_sync(sc->corb_dma.dma_tag, 2090 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2091 while (codec->verbs_sent != commands->num_commands && 2092 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2093 sc->corb_wp++; 2094 sc->corb_wp %= sc->corb_size; 2095 corb[sc->corb_wp] = 2096 commands->verbs[codec->verbs_sent++]; 2097 } 2098 2099 /* Send the verbs to the codecs */ 2100 bus_dmamap_sync(sc->corb_dma.dma_tag, 2101 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2102 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2103 } 2104 2105 timeout = 1000; 2106 do { 2107 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2108 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2109 BUS_DMASYNC_POSTREAD); 2110 if (sc->rirb_rp != rirbwp) { 2111 do { 2112 sc->rirb_rp++; 2113 sc->rirb_rp %= sc->rirb_size; 2114 rirb = &rirb_base[sc->rirb_rp]; 2115 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2116 ucad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2117 utag = rirb->response >> 26; 2118 if (ucad > -1 && ucad < HDAC_CODEC_MAX && 2119 sc->codecs[ucad] != NULL) { 2120 sc->unsolq[sc->unsolq_wp++] = 2121 (ucad << 16) | 2122 (utag & 0xffff); 2123 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2124 } 2125 } else if (codec->responses_received < commands->num_commands) 2126 codec->commands->responses[codec->responses_received++] = 2127 rirb->response; 2128 } while (sc->rirb_rp != rirbwp); 2129 break; 2130 } 2131 DELAY(10); 2132 } while (--timeout); 2133 } while ((codec->verbs_sent != commands->num_commands || 2134 codec->responses_received != commands->num_commands) && 2135 --retry); 2136 2137 if (retry == 0) 2138 device_printf(sc->dev, 2139 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2140 __func__, commands->num_commands, 2141 codec->verbs_sent, codec->responses_received); 2142 2143 codec->verbs_sent = 0; 2144 2145 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2146 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2147 while (sc->unsolq_rp != sc->unsolq_wp) { 2148 ucad = sc->unsolq[sc->unsolq_rp] >> 16; 2149 utag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2150 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2151 hdac_unsolicited_handler(sc->codecs[ucad], utag); 2152 } 2153 sc->unsolq_st = HDAC_UNSOLQ_READY; 2154 } 2155} 2156 2157 2158/**************************************************************************** 2159 * Device Methods 2160 ****************************************************************************/ 2161 2162/**************************************************************************** 2163 * int hdac_probe(device_t) 2164 * 2165 * Probe for the presence of an hdac. If none is found, check for a generic 2166 * match using the subclass of the device. 2167 ****************************************************************************/ 2168static int 2169hdac_probe(device_t dev) 2170{ 2171 int i, result; 2172 uint32_t model, class, subclass; 2173 char desc[64]; 2174 2175 model = (uint32_t)pci_get_device(dev) << 16; 2176 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2177 class = pci_get_class(dev); 2178 subclass = pci_get_subclass(dev); 2179 2180 bzero(desc, sizeof(desc)); 2181 result = ENXIO; 2182 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2183 if (hdac_devices[i].model == model) { 2184 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2185 result = BUS_PROBE_DEFAULT; 2186 break; 2187 } 2188 if ((hdac_devices[i].model & model) == model && 2189 class == PCIC_MULTIMEDIA && 2190 subclass == PCIS_MULTIMEDIA_HDA) { 2191 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2192 result = BUS_PROBE_GENERIC; 2193 break; 2194 } 2195 } 2196 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2197 subclass == PCIS_MULTIMEDIA_HDA) { 2198 strlcpy(desc, "Generic", sizeof(desc)); 2199 result = BUS_PROBE_GENERIC; 2200 } 2201 if (result != ENXIO) { 2202 strlcat(desc, " High Definition Audio Controller", 2203 sizeof(desc)); 2204 device_set_desc_copy(dev, desc); 2205 } 2206 2207 return (result); 2208} 2209 2210static void * 2211hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2212 struct pcm_channel *c, int dir) 2213{ 2214 struct hdac_devinfo *devinfo = data; 2215 struct hdac_softc *sc = devinfo->codec->sc; 2216 struct hdac_chan *ch; 2217 2218 hdac_lock(sc); 2219 if (dir == PCMDIR_PLAY) { 2220 ch = &sc->play; 2221 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2222 ch->dir = PCMDIR_PLAY; 2223 ch->sid = ++sc->streamcnt; 2224 devinfo->function.audio.playcnt++; 2225 } else { 2226 ch = &sc->rec; 2227 ch->off = devinfo->function.audio.reccnt << 5; 2228 ch->dir = PCMDIR_REC; 2229 ch->sid = ++sc->streamcnt; 2230 devinfo->function.audio.reccnt++; 2231 } 2232 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2233 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2234 ch->pcmrates[0] = 48000; 2235 ch->pcmrates[1] = 0; 2236 } 2237 ch->b = b; 2238 ch->c = c; 2239 ch->devinfo = devinfo; 2240 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2241 ch->blkcnt = sc->chan_blkcnt; 2242 hdac_unlock(sc); 2243 2244 if (hdac_bdl_alloc(ch) != 0) { 2245 ch->blkcnt = 0; 2246 return (NULL); 2247 } 2248 2249 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2250 return (NULL); 2251 2252 hdac_dma_nocache(ch->b->buf); 2253 2254 return (ch); 2255} 2256 2257static int 2258hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2259{ 2260 struct hdac_chan *ch = data; 2261 int i; 2262 2263 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2264 if (format == ch->caps.fmtlist[i]) { 2265 ch->fmt = format; 2266 return (0); 2267 } 2268 } 2269 2270 return (EINVAL); 2271} 2272 2273static int 2274hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2275{ 2276 struct hdac_chan *ch = data; 2277 uint32_t spd = 0; 2278 int i; 2279 2280 for (i = 0; ch->pcmrates[i] != 0; i++) { 2281 spd = ch->pcmrates[i]; 2282 if (spd >= speed) 2283 break; 2284 } 2285 2286 if (spd == 0) 2287 ch->spd = 48000; 2288 else 2289 ch->spd = spd; 2290 2291 return (ch->spd); 2292} 2293 2294static void 2295hdac_stream_setup(struct hdac_chan *ch) 2296{ 2297 struct hdac_softc *sc = ch->devinfo->codec->sc; 2298 int i; 2299 nid_t cad = ch->devinfo->codec->cad; 2300 uint16_t fmt; 2301 2302 /* 2303 * 8bit = 0 2304 * 16bit = 1 2305 * 20bit = 2 2306 * 24bit = 3 2307 * 32bit = 4 2308 */ 2309 fmt = 0; 2310 if (ch->fmt & AFMT_S16_LE) 2311 fmt |= ch->bit16 << 4; 2312 else if (ch->fmt & AFMT_S32_LE) 2313 fmt |= ch->bit32 << 4; 2314 else 2315 fmt |= 1 << 4; 2316 2317 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2318 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2319 fmt |= hda_rate_tab[i].base; 2320 fmt |= hda_rate_tab[i].mul; 2321 fmt |= hda_rate_tab[i].div; 2322 break; 2323 } 2324 } 2325 2326 if (ch->fmt & AFMT_STEREO) 2327 fmt |= 1; 2328 2329 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2330 2331 for (i = 0; ch->io[i] != -1; i++) { 2332 HDA_BOOTVERBOSE_MSG( 2333 device_printf(sc->dev, 2334 "PCMDIR_%s: Stream setup nid=%d fmt=0x%08x\n", 2335 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2336 ch->io[i], fmt); 2337 ); 2338 hdac_command(sc, 2339 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2340 hdac_command(sc, 2341 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2342 ch->sid << 4), cad); 2343 } 2344} 2345 2346static int 2347hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 2348{ 2349 struct hdac_chan *ch = data; 2350 2351 sndbuf_resize(ch->b, ch->blkcnt, ch->blksz); 2352 2353 return (ch->blksz); 2354} 2355 2356static void 2357hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2358{ 2359 struct hdac_devinfo *devinfo = ch->devinfo; 2360 nid_t cad = devinfo->codec->cad; 2361 int i; 2362 2363 hdac_stream_stop(ch); 2364 2365 for (i = 0; ch->io[i] != -1; i++) { 2366 hdac_command(sc, 2367 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2368 0), cad); 2369 } 2370} 2371 2372static void 2373hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2374{ 2375 ch->ptr = 0; 2376 ch->prevptr = 0; 2377 hdac_stream_stop(ch); 2378 hdac_stream_reset(ch); 2379 hdac_bdl_setup(ch); 2380 hdac_stream_setid(ch); 2381 hdac_stream_setup(ch); 2382 hdac_stream_start(ch); 2383} 2384 2385static int 2386hdac_channel_trigger(kobj_t obj, void *data, int go) 2387{ 2388 struct hdac_chan *ch = data; 2389 struct hdac_softc *sc = ch->devinfo->codec->sc; 2390 2391 hdac_lock(sc); 2392 switch (go) { 2393 case PCMTRIG_START: 2394 hdac_channel_start(sc, ch); 2395 break; 2396 case PCMTRIG_STOP: 2397 case PCMTRIG_ABORT: 2398 hdac_channel_stop(sc, ch); 2399 break; 2400 } 2401 hdac_unlock(sc); 2402 2403 return (0); 2404} 2405 2406static int 2407hdac_channel_getptr(kobj_t obj, void *data) 2408{ 2409 struct hdac_chan *ch = data; 2410 struct hdac_softc *sc = ch->devinfo->codec->sc; 2411 int sz, delta; 2412 uint32_t ptr; 2413 2414 hdac_lock(sc); 2415 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2416 hdac_unlock(sc); 2417 2418 sz = sndbuf_getsize(ch->b); 2419 ptr %= sz; 2420 2421 if (ch->dir == PCMDIR_REC) { 2422 delta = ptr % sndbuf_getblksz(ch->b); 2423 if (delta != 0) { 2424 ptr -= delta; 2425 if (ptr < delta) 2426 ptr = sz - delta; 2427 else 2428 ptr -= delta; 2429 } 2430 } 2431 2432 return (ptr); 2433} 2434 2435static struct pcmchan_caps * 2436hdac_channel_getcaps(kobj_t obj, void *data) 2437{ 2438 return (&((struct hdac_chan *)data)->caps); 2439} 2440 2441static kobj_method_t hdac_channel_methods[] = { 2442 KOBJMETHOD(channel_init, hdac_channel_init), 2443 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2444 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2445 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2446 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2447 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2448 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2449 { 0, 0 } 2450}; 2451CHANNEL_DECLARE(hdac_channel); 2452 2453static int 2454hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2455{ 2456 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2457 struct hdac_softc *sc = devinfo->codec->sc; 2458 struct hdac_widget *w, *cw; 2459 struct hdac_audio_ctl *ctl; 2460 uint32_t mask, recmask, id; 2461 int i, j, softpcmvol; 2462 nid_t cad; 2463 2464 if (resource_int_value(device_get_name(sc->dev), 2465 device_get_unit(sc->dev), "softpcmvol", &softpcmvol) == 0) 2466 softpcmvol = (softpcmvol != 0) ? 1 : 0; 2467 else 2468 softpcmvol = (devinfo->function.audio.quirks & 2469 HDA_QUIRK_SOFTPCMVOL) ? 2470 1 : 0; 2471 2472 hdac_lock(sc); 2473 2474 mask = 0; 2475 recmask = 0; 2476 2477 id = hdac_codec_id(devinfo); 2478 cad = devinfo->codec->cad; 2479 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2480 if (!((hdac_hp_switch[i].vendormask & sc->pci_subvendor) == 2481 sc->pci_subvendor && 2482 hdac_hp_switch[i].id == id)) 2483 continue; 2484 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2485 if (w != NULL && w->enable != 0 2486 && w->type == 2487 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2488 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2489 hdac_command(sc, 2490 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2491 w->nid, 2492 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2493 HDAC_UNSOLTAG_EVENT_HP), cad); 2494 hdac_hp_switch_handler(devinfo); 2495 } 2496 break; 2497 } 2498 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2499 if (!((hdac_eapd_switch[i].vendormask & sc->pci_subvendor) == 2500 sc->pci_subvendor && hdac_eapd_switch[i].id == id)) 2501 continue; 2502 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2503 if (w == NULL || w->enable == 0) 2504 break; 2505 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2506 w->param.eapdbtl == 0xffffffff) 2507 break; 2508 mask |= SOUND_MASK_OGAIN; 2509 break; 2510 } 2511 2512 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2513 w = hdac_widget_get(devinfo, i); 2514 if (w == NULL || w->enable == 0) 2515 continue; 2516 mask |= w->ctlflags; 2517 if (!(w->pflags & HDA_ADC_RECSEL)) 2518 continue; 2519 for (j = 0; j < w->nconns; j++) { 2520 cw = hdac_widget_get(devinfo, w->conns[j]); 2521 if (cw == NULL || cw->enable == 0) 2522 continue; 2523 recmask |= cw->ctlflags; 2524 } 2525 } 2526 2527 if (!(mask & SOUND_MASK_PCM)) { 2528 softpcmvol = 1; 2529 mask |= SOUND_MASK_PCM; 2530 } 2531 2532 i = 0; 2533 ctl = NULL; 2534 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2535 if (ctl->widget == NULL || ctl->enable == 0) 2536 continue; 2537 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2538 continue; 2539 if (ctl->step > 0) 2540 break; 2541 } 2542 2543 if (softpcmvol == 1 || ctl == NULL) { 2544 struct snddev_info *d = NULL; 2545 d = device_get_softc(sc->dev); 2546 if (d != NULL) { 2547 d->flags |= SD_F_SOFTPCMVOL; 2548 HDA_BOOTVERBOSE_MSG( 2549 device_printf(sc->dev, 2550 "%s Soft PCM volume\n", 2551 (softpcmvol == 1) ? 2552 "Forcing" : "Enabling"); 2553 ); 2554 } 2555 i = 0; 2556 /* 2557 * XXX Temporary quirk for STAC9220, until the parser 2558 * become smarter. 2559 */ 2560 if (id == HDA_CODEC_STAC9220) { 2561 mask |= SOUND_MASK_VOLUME; 2562 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2563 NULL) { 2564 if (ctl->widget == NULL || ctl->enable == 0) 2565 continue; 2566 if (ctl->widget->nid == 11 && ctl->index == 0) { 2567 ctl->ossmask = SOUND_MASK_VOLUME; 2568 ctl->ossval = 100 | (100 << 8); 2569 } else 2570 ctl->ossmask &= ~SOUND_MASK_VOLUME; 2571 } 2572 } else { 2573 mix_setparentchild(m, SOUND_MIXER_VOLUME, 2574 SOUND_MASK_PCM); 2575 if (!(mask & SOUND_MASK_VOLUME)) 2576 mix_setrealdev(m, SOUND_MIXER_VOLUME, 2577 SOUND_MIXER_NONE); 2578 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2579 NULL) { 2580 if (ctl->widget == NULL || ctl->enable == 0) 2581 continue; 2582 if ((ctl->ossmask & (SOUND_MASK_VOLUME | 2583 SOUND_MASK_PCM)) != (SOUND_MASK_VOLUME | 2584 SOUND_MASK_PCM)) 2585 continue; 2586 if (!(ctl->mute == 1 && ctl->step == 0)) 2587 ctl->enable = 0; 2588 } 2589 } 2590 } 2591 2592 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 2593 2594 mix_setrecdevs(m, recmask); 2595 mix_setdevs(m, mask); 2596 2597 hdac_unlock(sc); 2598 2599 return (0); 2600} 2601 2602static int 2603hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 2604 unsigned left, unsigned right) 2605{ 2606 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2607 struct hdac_softc *sc = devinfo->codec->sc; 2608 struct hdac_widget *w; 2609 struct hdac_audio_ctl *ctl; 2610 uint32_t id, mute; 2611 int lvol, rvol, mlvol, mrvol; 2612 int i = 0; 2613 2614 hdac_lock(sc); 2615 if (dev == SOUND_MIXER_OGAIN) { 2616 /*if (left != right || !(left == 0 || left == 1)) { 2617 hdac_unlock(sc); 2618 return (-1); 2619 }*/ 2620 id = hdac_codec_id(devinfo); 2621 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2622 if ((hdac_eapd_switch[i].vendormask & 2623 sc->pci_subvendor) == sc->pci_subvendor && 2624 hdac_eapd_switch[i].id == id) 2625 break; 2626 } 2627 if (i >= HDAC_EAPD_SWITCH_LEN) { 2628 hdac_unlock(sc); 2629 return (-1); 2630 } 2631 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2632 if (w == NULL || 2633 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2634 w->param.eapdbtl == 0xffffffff) { 2635 hdac_unlock(sc); 2636 return (-1); 2637 } 2638 if (left == 0) 2639 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2640 else 2641 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2642 if (hdac_eapd_switch[i].hp_switch != 0) 2643 hdac_hp_switch_handler(devinfo); 2644 hdac_command(sc, 2645 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, w->nid, 2646 w->param.eapdbtl), devinfo->codec->cad); 2647 hdac_unlock(sc); 2648 return (left | (left << 8)); 2649 } 2650 if (dev == SOUND_MIXER_VOLUME) 2651 devinfo->function.audio.mvol = left | (right << 8); 2652 2653 mlvol = devinfo->function.audio.mvol & 0x7f; 2654 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 2655 lvol = 0; 2656 rvol = 0; 2657 2658 i = 0; 2659 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2660 if (ctl->widget == NULL || ctl->enable == 0 || 2661 !(ctl->ossmask & (1 << dev))) 2662 continue; 2663 switch (dev) { 2664 case SOUND_MIXER_VOLUME: 2665 lvol = ((ctl->ossval & 0x7f) * left) / 100; 2666 lvol = (lvol * ctl->step) / 100; 2667 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 2668 rvol = (rvol * ctl->step) / 100; 2669 break; 2670 default: 2671 if (ctl->ossmask & SOUND_MASK_VOLUME) { 2672 lvol = (left * mlvol) / 100; 2673 lvol = (lvol * ctl->step) / 100; 2674 rvol = (right * mrvol) / 100; 2675 rvol = (rvol * ctl->step) / 100; 2676 } else { 2677 lvol = (left * ctl->step) / 100; 2678 rvol = (right * ctl->step) / 100; 2679 } 2680 ctl->ossval = left | (right << 8); 2681 break; 2682 } 2683 mute = 0; 2684 if (ctl->step < 1) { 2685 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 2686 (ctl->muted & HDA_AMP_MUTE_LEFT); 2687 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 2688 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2689 } else { 2690 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 2691 (ctl->muted & HDA_AMP_MUTE_LEFT); 2692 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 2693 (ctl->muted & HDA_AMP_MUTE_RIGHT); 2694 } 2695 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 2696 } 2697 hdac_unlock(sc); 2698 2699 return (left | (right << 8)); 2700} 2701 2702static int 2703hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 2704{ 2705 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2706 struct hdac_widget *w, *cw; 2707 struct hdac_softc *sc = devinfo->codec->sc; 2708 uint32_t ret = src, target; 2709 int i, j; 2710 2711 target = 0; 2712 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 2713 if (src & (1 << i)) { 2714 target = 1 << i; 2715 break; 2716 } 2717 } 2718 2719 hdac_lock(sc); 2720 2721 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2722 w = hdac_widget_get(devinfo, i); 2723 if (w == NULL && w->enable == 0) 2724 continue; 2725 if (!(w->pflags & HDA_ADC_RECSEL)) 2726 continue; 2727 for (j = 0; j < w->nconns; j++) { 2728 cw = hdac_widget_get(devinfo, w->conns[j]); 2729 if (cw == NULL || cw->enable == 0) 2730 continue; 2731 if ((target == SOUND_MASK_VOLUME && 2732 cw->type != 2733 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 2734 (target != SOUND_MASK_VOLUME && 2735 cw->type == 2736 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 2737 continue; 2738 if (cw->ctlflags & target) { 2739 hdac_widget_connection_select(w, j); 2740 ret = target; 2741 j += w->nconns; 2742 } 2743 } 2744 } 2745 2746 hdac_unlock(sc); 2747 2748 return (ret); 2749} 2750 2751static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 2752 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 2753 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 2754 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 2755 { 0, 0 } 2756}; 2757MIXER_DECLARE(hdac_audio_ctl_ossmixer); 2758 2759/**************************************************************************** 2760 * int hdac_attach(device_t) 2761 * 2762 * Attach the device into the kernel. Interrupts usually won't be enabled 2763 * when this function is called. Setup everything that doesn't require 2764 * interrupts and defer probing of codecs until interrupts are enabled. 2765 ****************************************************************************/ 2766static int 2767hdac_attach(device_t dev) 2768{ 2769 struct hdac_softc *sc; 2770 int result; 2771 int i = 0; 2772 2773 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 2774 if (sc == NULL) { 2775 device_printf(dev, "cannot allocate softc\n"); 2776 return (ENOMEM); 2777 } 2778 sc->dev = dev; 2779 sc->pci_subvendor = pci_get_subdevice(sc->dev) << 16; 2780 sc->pci_subvendor |= pci_get_subvendor(sc->dev); 2781 2782 sc->chan_size = pcm_getbuffersize(dev, 2783 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_DEFAULT); 2784 if (resource_int_value(device_get_name(sc->dev), 2785 device_get_unit(sc->dev), "blocksize", &i) == 0 && 2786 i > 0) { 2787 sc->chan_blkcnt = sc->chan_size / i; 2788 i = 0; 2789 while (sc->chan_blkcnt >> i) 2790 i++; 2791 sc->chan_blkcnt = 1 << (i - 1); 2792 if (sc->chan_blkcnt < HDA_BDL_MIN) 2793 sc->chan_blkcnt = HDA_BDL_MIN; 2794 else if (sc->chan_blkcnt > HDA_BDL_MAX) 2795 sc->chan_blkcnt = HDA_BDL_MAX; 2796 } else 2797 sc->chan_blkcnt = HDA_BDL_DEFAULT; 2798 2799 result = bus_dma_tag_create(NULL, /* parent */ 2800 HDAC_DMA_ALIGNMENT, /* alignment */ 2801 0, /* boundary */ 2802 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2803 BUS_SPACE_MAXADDR, /* highaddr */ 2804 NULL, /* filtfunc */ 2805 NULL, /* fistfuncarg */ 2806 sc->chan_size, /* maxsize */ 2807 1, /* nsegments */ 2808 sc->chan_size, /* maxsegsz */ 2809 0, /* flags */ 2810 NULL, /* lockfunc */ 2811 NULL, /* lockfuncarg */ 2812 &sc->chan_dmat); /* dmat */ 2813 if (result != 0) { 2814 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 2815 __func__, result); 2816 free(sc, M_DEVBUF); 2817 return (ENXIO); 2818 } 2819 2820 2821 sc->hdabus = NULL; 2822 for (i = 0; i < HDAC_CODEC_MAX; i++) 2823 sc->codecs[i] = NULL; 2824 2825 pci_enable_busmaster(dev); 2826 2827 /* Initialize driver mutex */ 2828 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 2829 2830 /* Allocate resources */ 2831 result = hdac_mem_alloc(sc); 2832 if (result != 0) 2833 goto fail; 2834 result = hdac_irq_alloc(sc); 2835 if (result != 0) 2836 goto fail; 2837 2838 /* Get Capabilities */ 2839 result = hdac_get_capabilities(sc); 2840 if (result != 0) 2841 goto fail; 2842 2843 /* Allocate CORB and RIRB dma memory */ 2844 result = hdac_dma_alloc(sc, &sc->corb_dma, 2845 sc->corb_size * sizeof(uint32_t)); 2846 if (result != 0) 2847 goto fail; 2848 result = hdac_dma_alloc(sc, &sc->rirb_dma, 2849 sc->rirb_size * sizeof(struct hdac_rirb)); 2850 if (result != 0) 2851 goto fail; 2852 2853 /* Quiesce everything */ 2854 hdac_reset(sc); 2855 2856 /* Disable PCI-Express QOS */ 2857 pci_write_config(sc->dev, 0x44, 2858 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 2859 2860 /* Initialize the CORB and RIRB */ 2861 hdac_corb_init(sc); 2862 hdac_rirb_init(sc); 2863 2864 /* Defer remaining of initialization until interrupts are enabled */ 2865 sc->intrhook.ich_func = hdac_attach2; 2866 sc->intrhook.ich_arg = (void *)sc; 2867 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 2868 sc->intrhook.ich_func = NULL; 2869 hdac_attach2((void *)sc); 2870 } 2871 2872 return(0); 2873 2874fail: 2875 hdac_dma_free(&sc->rirb_dma); 2876 hdac_dma_free(&sc->corb_dma); 2877 hdac_irq_free(sc); 2878 hdac_mem_free(sc); 2879 snd_mtxfree(sc->lock); 2880 2881 return(ENXIO); 2882} 2883 2884static void 2885hdac_audio_parse(struct hdac_devinfo *devinfo) 2886{ 2887 struct hdac_softc *sc = devinfo->codec->sc; 2888 struct hdac_widget *w; 2889 uint32_t res; 2890 int i; 2891 nid_t cad, nid; 2892 2893 cad = devinfo->codec->cad; 2894 nid = devinfo->nid; 2895 2896 hdac_command(sc, 2897 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 2898 2899 DELAY(100); 2900 2901 res = hdac_command(sc, 2902 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2903 2904 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2905 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2906 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2907 2908 HDA_BOOTVERBOSE_MSG( 2909 device_printf(sc->dev, " Vendor: 0x%08x\n", 2910 devinfo->vendor_id); 2911 device_printf(sc->dev, " Device: 0x%08x\n", 2912 devinfo->device_id); 2913 device_printf(sc->dev, " Revision: 0x%08x\n", 2914 devinfo->revision_id); 2915 device_printf(sc->dev, " Stepping: 0x%08x\n", 2916 devinfo->stepping_id); 2917 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2918 sc->pci_subvendor); 2919 device_printf(sc->dev, " Nodes: start=%d " 2920 "endnode=%d total=%d\n", 2921 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 2922 ); 2923 2924 res = hdac_command(sc, 2925 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 2926 cad); 2927 devinfo->function.audio.supp_stream_formats = res; 2928 2929 res = hdac_command(sc, 2930 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 2931 cad); 2932 devinfo->function.audio.supp_pcm_size_rate = res; 2933 2934 res = hdac_command(sc, 2935 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 2936 cad); 2937 devinfo->function.audio.outamp_cap = res; 2938 2939 res = hdac_command(sc, 2940 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 2941 cad); 2942 devinfo->function.audio.inamp_cap = res; 2943 2944 if (devinfo->nodecnt > 0) { 2945 hdac_unlock(sc); 2946 devinfo->widget = (struct hdac_widget *)malloc( 2947 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2948 M_NOWAIT | M_ZERO); 2949 hdac_lock(sc); 2950 } else 2951 devinfo->widget = NULL; 2952 2953 if (devinfo->widget == NULL) { 2954 device_printf(sc->dev, "unable to allocate widgets!\n"); 2955 devinfo->endnode = devinfo->startnode; 2956 devinfo->nodecnt = 0; 2957 return; 2958 } 2959 2960 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2961 w = hdac_widget_get(devinfo, i); 2962 if (w == NULL) 2963 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 2964 else { 2965 w->devinfo = devinfo; 2966 w->nid = i; 2967 w->enable = 1; 2968 w->selconn = -1; 2969 w->pflags = 0; 2970 w->ctlflags = 0; 2971 w->param.eapdbtl = 0xffffffff; 2972 hdac_widget_parse(w); 2973 } 2974 } 2975} 2976 2977static void 2978hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 2979{ 2980 struct hdac_softc *sc = devinfo->codec->sc; 2981 struct hdac_audio_ctl *ctls; 2982 struct hdac_widget *w, *cw; 2983 int i, j, cnt, max, ocap, icap; 2984 2985 /* XXX This is redundant */ 2986 max = 0; 2987 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2988 w = hdac_widget_get(devinfo, i); 2989 if (w == NULL || w->enable == 0) 2990 continue; 2991 if (w->param.outamp_cap != 0) 2992 max++; 2993 if (w->param.inamp_cap != 0) { 2994 switch (w->type) { 2995 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2996 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2997 for (j = 0; j < w->nconns; j++) { 2998 cw = hdac_widget_get(devinfo, 2999 w->conns[j]); 3000 if (cw == NULL || cw->enable == 0) 3001 continue; 3002 max++; 3003 } 3004 break; 3005 default: 3006 max++; 3007 break; 3008 } 3009 } 3010 } 3011 3012 devinfo->function.audio.ctlcnt = max; 3013 3014 if (max < 1) 3015 return; 3016 3017 hdac_unlock(sc); 3018 ctls = (struct hdac_audio_ctl *)malloc( 3019 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3020 hdac_lock(sc); 3021 3022 if (ctls == NULL) { 3023 /* Blekh! */ 3024 device_printf(sc->dev, "unable to allocate ctls!\n"); 3025 devinfo->function.audio.ctlcnt = 0; 3026 return; 3027 } 3028 3029 cnt = 0; 3030 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3031 if (cnt >= max) { 3032 device_printf(sc->dev, "%s: Ctl overflow!\n", 3033 __func__); 3034 break; 3035 } 3036 w = hdac_widget_get(devinfo, i); 3037 if (w == NULL || w->enable == 0) 3038 continue; 3039 ocap = w->param.outamp_cap; 3040 icap = w->param.inamp_cap; 3041 if (ocap != 0) { 3042 ctls[cnt].enable = 1; 3043 ctls[cnt].widget = w; 3044 ctls[cnt].mute = 3045 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3046 ctls[cnt].step = 3047 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3048 ctls[cnt].size = 3049 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3050 ctls[cnt].offset = 3051 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3052 ctls[cnt].left = ctls[cnt].offset; 3053 ctls[cnt].right = ctls[cnt].offset; 3054 ctls[cnt++].dir = HDA_CTL_OUT; 3055 } 3056 3057 if (icap != 0) { 3058 switch (w->type) { 3059 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3060 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3061 for (j = 0; j < w->nconns; j++) { 3062 if (cnt >= max) { 3063 device_printf(sc->dev, 3064 "%s: Ctl overflow!\n", 3065 __func__); 3066 break; 3067 } 3068 cw = hdac_widget_get(devinfo, 3069 w->conns[j]); 3070 if (cw == NULL || cw->enable == 0) 3071 continue; 3072 ctls[cnt].enable = 1; 3073 ctls[cnt].widget = w; 3074 ctls[cnt].childwidget = cw; 3075 ctls[cnt].index = j; 3076 ctls[cnt].mute = 3077 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(icap); 3078 ctls[cnt].step = 3079 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(icap); 3080 ctls[cnt].size = 3081 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(icap); 3082 ctls[cnt].offset = 3083 HDA_PARAM_INPUT_AMP_CAP_OFFSET(icap); 3084 ctls[cnt].left = ctls[cnt].offset; 3085 ctls[cnt].right = ctls[cnt].offset; 3086 ctls[cnt++].dir = HDA_CTL_IN; 3087 } 3088 break; 3089 default: 3090 if (cnt >= max) { 3091 device_printf(sc->dev, 3092 "%s: Ctl overflow!\n", 3093 __func__); 3094 break; 3095 } 3096 ctls[cnt].enable = 1; 3097 ctls[cnt].widget = w; 3098 ctls[cnt].mute = 3099 HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(icap); 3100 ctls[cnt].step = 3101 HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(icap); 3102 ctls[cnt].size = 3103 HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(icap); 3104 ctls[cnt].offset = 3105 HDA_PARAM_INPUT_AMP_CAP_OFFSET(icap); 3106 ctls[cnt].left = ctls[cnt].offset; 3107 ctls[cnt].right = ctls[cnt].offset; 3108 ctls[cnt++].dir = HDA_CTL_IN; 3109 break; 3110 } 3111 } 3112 } 3113 3114 devinfo->function.audio.ctl = ctls; 3115} 3116 3117static void 3118hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3119{ 3120 struct hdac_widget *w; 3121 uint32_t id; 3122 int i; 3123 3124 /* 3125 * XXX Fixed rate quirk. Other than 48000 3126 * sounds pretty much like train wreck. 3127 */ 3128 devinfo->function.audio.quirks |= HDA_QUIRK_FIXEDRATE; 3129 /* 3130 * XXX Force stereo quirk. Monoural recording / playback 3131 * on few codecs (especially ALC880) seems broken or 3132 * or perhaps unsupported. 3133 */ 3134 devinfo->function.audio.quirks |= HDA_QUIRK_FORCESTEREO; 3135 id = hdac_codec_id(devinfo); 3136 switch (id) { 3137 case HDA_CODEC_ALC260: 3138 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3139 w = hdac_widget_get(devinfo, i); 3140 if (w == NULL || w->enable == 0) 3141 continue; 3142 if (w->type != 3143 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3144 continue; 3145 if (w->nid != 5) 3146 w->enable = 0; 3147 } 3148 break; 3149 case HDA_CODEC_ALC880: 3150 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3151 w = hdac_widget_get(devinfo, i); 3152 if (w == NULL || w->enable == 0) 3153 continue; 3154 if (w->type == 3155 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3156 w->nid != 9 && w->nid != 29) { 3157 w->enable = 0; 3158 } else if (w->type != 3159 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3160 w->nid == 29) { 3161 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3162 w->param.widget_cap &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3163 w->param.widget_cap |= 3164 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3165 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3166 strlcpy(w->name, "beep widget", sizeof(w->name)); 3167 } 3168 } 3169 break; 3170 case HDA_CODEC_AD1986A: 3171 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3172 w = hdac_widget_get(devinfo, i); 3173 if (w == NULL || w->enable == 0) 3174 continue; 3175 if (w->type != 3176 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3177 continue; 3178 if (w->nid != 3) 3179 w->enable = 0; 3180 } 3181 break; 3182 case HDA_CODEC_STAC9221: 3183 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3184 w = hdac_widget_get(devinfo, i); 3185 if (w == NULL || w->enable == 0) 3186 continue; 3187 if (w->type != 3188 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3189 continue; 3190 if (w->nid != 2) 3191 w->enable = 0; 3192 } 3193 break; 3194 case HDA_CODEC_STAC9221D: 3195 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3196 w = hdac_widget_get(devinfo, i); 3197 if (w == NULL || w->enable == 0) 3198 continue; 3199 if (w->type == 3200 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3201 w->nid != 6) 3202 w->enable = 0; 3203 3204 } 3205 break; 3206 case HDA_CODEC_CXVENICE: 3207 devinfo->function.audio.quirks &= ~HDA_QUIRK_FORCESTEREO; 3208 break; 3209 default: 3210 break; 3211 } 3212 if ((HDA_CODEC_STACXXXX & id) == id) { 3213 /* Sigmatel codecs need soft PCM volume emulation */ 3214 devinfo->function.audio.quirks |= HDA_QUIRK_SOFTPCMVOL; 3215 } 3216 if ((ACER_ALL_SUBVENDOR & devinfo->codec->sc->pci_subvendor) == 3217 devinfo->codec->sc->pci_subvendor) { 3218 /* Acer */ 3219 devinfo->function.audio.quirks |= HDA_QUIRK_GPIO1; 3220 } 3221} 3222 3223static int 3224hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3225{ 3226 int *dev = &devinfo->function.audio.ossidx; 3227 3228 while (*dev < SOUND_MIXER_NRDEVICES) { 3229 switch (*dev) { 3230 case SOUND_MIXER_VOLUME: 3231 case SOUND_MIXER_BASS: 3232 case SOUND_MIXER_TREBLE: 3233 case SOUND_MIXER_PCM: 3234 case SOUND_MIXER_SPEAKER: 3235 case SOUND_MIXER_LINE: 3236 case SOUND_MIXER_MIC: 3237 case SOUND_MIXER_CD: 3238 case SOUND_MIXER_RECLEV: 3239 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3240 (*dev)++; 3241 break; 3242 default: 3243 return (*dev)++; 3244 break; 3245 } 3246 } 3247 3248 return (-1); 3249} 3250 3251static int 3252hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3253{ 3254 struct hdac_widget *w; 3255 int i, ret = 0; 3256 3257 if (depth > HDA_PARSE_MAXDEPTH) 3258 return (0); 3259 w = hdac_widget_get(devinfo, nid); 3260 if (w == NULL || w->enable == 0) 3261 return (0); 3262 switch (w->type) { 3263 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3264 w->pflags |= HDA_DAC_PATH; 3265 ret = 1; 3266 break; 3267 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3268 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3269 for (i = 0; i < w->nconns; i++) { 3270 if (hdac_widget_find_dac_path(devinfo, 3271 w->conns[i], depth + 1) != 0) { 3272 if (w->selconn == -1) 3273 w->selconn = i; 3274 ret = 1; 3275 w->pflags |= HDA_DAC_PATH; 3276 } 3277 } 3278 break; 3279 default: 3280 break; 3281 } 3282 return (ret); 3283} 3284 3285static int 3286hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3287{ 3288 struct hdac_widget *w; 3289 int i, conndev, ret = 0; 3290 3291 if (depth > HDA_PARSE_MAXDEPTH) 3292 return (0); 3293 w = hdac_widget_get(devinfo, nid); 3294 if (w == NULL || w->enable == 0) 3295 return (0); 3296 switch (w->type) { 3297 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3298 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3299 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3300 for (i = 0; i < w->nconns; i++) { 3301 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3302 depth + 1) != 0) { 3303 if (w->selconn == -1) 3304 w->selconn = i; 3305 w->pflags |= HDA_ADC_PATH; 3306 ret = 1; 3307 } 3308 } 3309 break; 3310 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3311 conndev = w->wclass.pin.config & 3312 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3313 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3314 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3315 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3316 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3317 w->pflags |= HDA_ADC_PATH; 3318 ret = 1; 3319 } 3320 break; 3321 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3322 if (w->pflags & HDA_DAC_PATH) { 3323 w->pflags |= HDA_ADC_PATH; 3324 ret = 1; 3325 } 3326 break;*/ 3327 default: 3328 break; 3329 } 3330 return (ret); 3331} 3332 3333static uint32_t 3334hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3335 nid_t nid, nid_t pnid, int index, int depth) 3336{ 3337 struct hdac_widget *w, *pw; 3338 struct hdac_audio_ctl *ctl; 3339 uint32_t fl = 0; 3340 int i, ossdev, conndev, strategy; 3341 3342 if (depth > HDA_PARSE_MAXDEPTH) 3343 return (0); 3344 3345 w = hdac_widget_get(devinfo, nid); 3346 if (w == NULL || w->enable == 0) 3347 return (0); 3348 3349 pw = hdac_widget_get(devinfo, pnid); 3350 strategy = devinfo->function.audio.parsing_strategy; 3351 3352 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3353 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3354 for (i = 0; i < w->nconns; i++) { 3355 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3356 w->nid, i, depth + 1); 3357 } 3358 w->ctlflags |= fl; 3359 return (fl); 3360 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3361 (w->pflags & HDA_DAC_PATH)) { 3362 i = 0; 3363 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3364 if (ctl->enable == 0 || ctl->widget == NULL) 3365 continue; 3366 if ((ctl->widget->nid == w->nid) || 3367 (ctl->widget->nid == pnid && ctl->index == index && 3368 (ctl->dir & HDA_CTL_IN)) || 3369 (ctl->widget->nid == pnid && pw != NULL && 3370 pw->type == 3371 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3372 (pw->nconns < 2 || pw->selconn == index || 3373 pw->selconn == -1) && 3374 (ctl->dir & HDA_CTL_OUT)) || 3375 (strategy == HDA_PARSE_DIRECT && 3376 ctl->widget->nid == w->nid)) { 3377 if (pw != NULL && pw->selconn == -1) 3378 pw->selconn = index; 3379 fl |= SOUND_MASK_VOLUME; 3380 fl |= SOUND_MASK_PCM; 3381 ctl->ossmask |= SOUND_MASK_VOLUME; 3382 ctl->ossmask |= SOUND_MASK_PCM; 3383 ctl->ossdev = SOUND_MIXER_PCM; 3384 } 3385 } 3386 w->ctlflags |= fl; 3387 return (fl); 3388 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 3389 && HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3390 (w->pflags & HDA_ADC_PATH)) { 3391 conndev = w->wclass.pin.config & 3392 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3393 i = 0; 3394 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3395 if (ctl->enable == 0 || ctl->widget == NULL) 3396 continue; 3397 if (((ctl->widget->nid == pnid && ctl->index == index && 3398 (ctl->dir & HDA_CTL_IN)) || 3399 (ctl->widget->nid == pnid && pw != NULL && 3400 pw->type == 3401 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3402 (pw->nconns < 2 || pw->selconn == index || 3403 pw->selconn == -1) && 3404 (ctl->dir & HDA_CTL_OUT)) || 3405 (strategy == HDA_PARSE_DIRECT && 3406 ctl->widget->nid == w->nid)) && 3407 (ctl->ossmask & ~SOUND_MASK_VOLUME) == 0) { 3408 if (pw != NULL && pw->selconn == -1) 3409 pw->selconn = index; 3410 ossdev = 0; 3411 switch (conndev) { 3412 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 3413 ossdev = SOUND_MIXER_MIC; 3414 break; 3415 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 3416 ossdev = SOUND_MIXER_LINE; 3417 break; 3418 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 3419 ossdev = SOUND_MIXER_CD; 3420 break; 3421 default: 3422 ossdev = 3423 hdac_audio_ctl_ossmixer_getnextdev( 3424 devinfo); 3425 if (ossdev < 0) 3426 ossdev = 0; 3427 break; 3428 } 3429 if (strategy == HDA_PARSE_MIXER) { 3430 fl |= SOUND_MASK_VOLUME; 3431 ctl->ossmask |= SOUND_MASK_VOLUME; 3432 } 3433 fl |= 1 << ossdev; 3434 ctl->ossmask |= 1 << ossdev; 3435 ctl->ossdev = ossdev; 3436 } 3437 } 3438 w->ctlflags |= fl; 3439 return (fl); 3440 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3441 i = 0; 3442 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3443 if (ctl->enable == 0 || ctl->widget == NULL) 3444 continue; 3445 if (((ctl->widget->nid == pnid && ctl->index == index && 3446 (ctl->dir & HDA_CTL_IN)) || 3447 (ctl->widget->nid == pnid && pw != NULL && 3448 pw->type == 3449 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3450 (pw->nconns < 2 || pw->selconn == index || 3451 pw->selconn == -1) && 3452 (ctl->dir & HDA_CTL_OUT)) || 3453 (strategy == HDA_PARSE_DIRECT && 3454 ctl->widget->nid == w->nid)) && 3455 (ctl->ossmask & ~SOUND_MASK_VOLUME) == 0) { 3456 if (pw != NULL && pw->selconn == -1) 3457 pw->selconn = index; 3458 fl |= SOUND_MASK_VOLUME; 3459 fl |= SOUND_MASK_SPEAKER; 3460 ctl->ossmask |= SOUND_MASK_VOLUME; 3461 ctl->ossmask |= SOUND_MASK_SPEAKER; 3462 ctl->ossdev = SOUND_MIXER_SPEAKER; 3463 } 3464 } 3465 w->ctlflags |= fl; 3466 return (fl); 3467 } 3468 return (0); 3469} 3470 3471static uint32_t 3472hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3473{ 3474 struct hdac_widget *w, *cw; 3475 struct hdac_audio_ctl *ctl; 3476 uint32_t fl; 3477 int i; 3478 3479 if (depth > HDA_PARSE_MAXDEPTH) 3480 return (0); 3481 3482 w = hdac_widget_get(devinfo, nid); 3483 if (w == NULL || w->enable == 0) 3484 return (0); 3485 /*if (!(w->pflags & HDA_ADC_PATH)) 3486 return (0); 3487 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3488 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3489 return (0);*/ 3490 i = 0; 3491 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3492 if (ctl->enable == 0 || ctl->widget == NULL) 3493 continue; 3494 if (ctl->widget->nid == nid) { 3495 ctl->ossmask |= SOUND_MASK_RECLEV; 3496 w->ctlflags |= SOUND_MASK_RECLEV; 3497 return (SOUND_MASK_RECLEV); 3498 } 3499 } 3500 for (i = 0; i < w->nconns; i++) { 3501 cw = hdac_widget_get(devinfo, w->conns[i]); 3502 if (cw == NULL || cw->enable == 0) 3503 continue; 3504 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3505 continue; 3506 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 3507 if (fl != 0) { 3508 cw->ctlflags |= fl; 3509 w->ctlflags |= fl; 3510 return (fl); 3511 } 3512 } 3513 return (0); 3514} 3515 3516static int 3517hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3518{ 3519 struct hdac_widget *w, *cw; 3520 int i, child = 0; 3521 3522 if (depth > HDA_PARSE_MAXDEPTH) 3523 return (0); 3524 3525 w = hdac_widget_get(devinfo, nid); 3526 if (w == NULL || w->enable == 0) 3527 return (0); 3528 /*if (!(w->pflags & HDA_ADC_PATH)) 3529 return (0); 3530 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 3531 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3532 return (0);*/ 3533 /* XXX weak! */ 3534 for (i = 0; i < w->nconns; i++) { 3535 cw = hdac_widget_get(devinfo, w->conns[i]); 3536 if (cw == NULL) 3537 continue; 3538 if (++child > 1) { 3539 w->pflags |= HDA_ADC_RECSEL; 3540 return (1); 3541 } 3542 } 3543 for (i = 0; i < w->nconns; i++) { 3544 if (hdac_audio_ctl_recsel_build(devinfo, 3545 w->conns[i], depth + 1) != 0) 3546 return (1); 3547 } 3548 return (0); 3549} 3550 3551static int 3552hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 3553{ 3554 struct hdac_widget *w, *cw; 3555 int i, j, conndev, found_dac = 0; 3556 int strategy; 3557 3558 strategy = devinfo->function.audio.parsing_strategy; 3559 3560 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3561 w = hdac_widget_get(devinfo, i); 3562 if (w == NULL || w->enable == 0) 3563 continue; 3564 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 3565 continue; 3566 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 3567 continue; 3568 conndev = w->wclass.pin.config & 3569 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3570 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 3571 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 3572 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 3573 continue; 3574 for (j = 0; j < w->nconns; j++) { 3575 cw = hdac_widget_get(devinfo, w->conns[j]); 3576 if (cw == NULL || cw->enable == 0) 3577 continue; 3578 if (strategy == HDA_PARSE_MIXER && !(cw->type == 3579 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3580 cw->type == 3581 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 3582 continue; 3583 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 3584 != 0) { 3585 if (w->selconn == -1) 3586 w->selconn = j; 3587 w->pflags |= HDA_DAC_PATH; 3588 found_dac++; 3589 } 3590 } 3591 } 3592 3593 return (found_dac); 3594} 3595 3596static void 3597hdac_audio_build_tree(struct hdac_devinfo *devinfo) 3598{ 3599 struct hdac_widget *w; 3600 struct hdac_audio_ctl *ctl; 3601 int i, j, dacs, strategy; 3602 3603 /* Construct DAC path */ 3604 strategy = HDA_PARSE_MIXER; 3605 devinfo->function.audio.parsing_strategy = strategy; 3606 HDA_BOOTVERBOSE_MSG( 3607 device_printf(devinfo->codec->sc->dev, 3608 "HWiP: HDA Widget Parser - Revision %d\n", 3609 HDA_WIDGET_PARSER_REV); 3610 ); 3611 dacs = hdac_audio_build_tree_strategy(devinfo); 3612 if (dacs == 0) { 3613 HDA_BOOTVERBOSE_MSG( 3614 device_printf(devinfo->codec->sc->dev, 3615 "HWiP: 0 DAC found! Retrying parser " 3616 "using HDA_PARSE_DIRECT strategy.\n"); 3617 ); 3618 strategy = HDA_PARSE_DIRECT; 3619 devinfo->function.audio.parsing_strategy = strategy; 3620 dacs = hdac_audio_build_tree_strategy(devinfo); 3621 } 3622 3623 HDA_BOOTVERBOSE_MSG( 3624 device_printf(devinfo->codec->sc->dev, 3625 "HWiP: Found %d DAC(s) using HDA_PARSE_%s strategy.\n", 3626 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 3627 ); 3628 3629 /* Construct ADC path */ 3630 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3631 w = hdac_widget_get(devinfo, i); 3632 if (w == NULL || w->enable == 0) 3633 continue; 3634 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3635 continue; 3636 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 3637 } 3638 3639 /* Output mixers */ 3640 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3641 w = hdac_widget_get(devinfo, i); 3642 if (w == NULL || w->enable == 0) 3643 continue; 3644 if ((strategy == HDA_PARSE_MIXER && 3645 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 3646 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 3647 && (w->pflags & HDA_DAC_PATH)) || 3648 (strategy == HDA_PARSE_DIRECT && (w->pflags & 3649 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 3650 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 3651 w->nid, devinfo->startnode - 1, 0, 0); 3652 } else if (w->type == 3653 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 3654 j = 0; 3655 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 3656 NULL) { 3657 if (ctl->enable == 0 || ctl->widget == NULL) 3658 continue; 3659 if (ctl->widget->nid != w->nid) 3660 continue; 3661 ctl->ossmask |= SOUND_MASK_VOLUME; 3662 ctl->ossmask |= SOUND_MASK_SPEAKER; 3663 ctl->ossdev = SOUND_MIXER_SPEAKER; 3664 w->ctlflags |= SOUND_MASK_VOLUME; 3665 w->ctlflags |= SOUND_MASK_SPEAKER; 3666 } 3667 } 3668 } 3669 3670 /* Input mixers (rec) */ 3671 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3672 w = hdac_widget_get(devinfo, i); 3673 if (w == NULL || w->enable == 0) 3674 continue; 3675 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3676 w->pflags & HDA_ADC_PATH)) 3677 continue; 3678 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 3679 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 3680 } 3681} 3682 3683#define HDA_COMMIT_CONN (1 << 0) 3684#define HDA_COMMIT_CTRL (1 << 1) 3685#define HDA_COMMIT_EAPD (1 << 2) 3686#define HDA_COMMIT_GPIO (1 << 3) 3687#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 3688 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 3689 3690static void 3691hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 3692{ 3693 struct hdac_softc *sc = devinfo->codec->sc; 3694 struct hdac_widget *w; 3695 nid_t cad; 3696 int i; 3697 3698 if (!(cfl & HDA_COMMIT_ALL)) 3699 return; 3700 3701 cad = devinfo->codec->cad; 3702 3703 if ((cfl & HDA_COMMIT_GPIO)) { 3704 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIO1) { 3705 hdac_command(sc, 3706 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, 0x01, 3707 0x01), cad); 3708 hdac_command(sc, 3709 HDA_CMD_SET_GPIO_DIRECTION(cad, 0x01, 3710 0x01), cad); 3711 hdac_command(sc, 3712 HDA_CMD_SET_GPIO_DATA(cad, 0x01, 3713 0x01), cad); 3714 } 3715 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIO2) { 3716 hdac_command(sc, 3717 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, 0x01, 3718 0x02), cad); 3719 hdac_command(sc, 3720 HDA_CMD_SET_GPIO_DIRECTION(cad, 0x01, 3721 0x02), cad); 3722 hdac_command(sc, 3723 HDA_CMD_SET_GPIO_DATA(cad, 0x01, 3724 0x02), cad); 3725 } 3726 } 3727 3728 for (i = 0; i < devinfo->nodecnt; i++) { 3729 w = &devinfo->widget[i]; 3730 if (w == NULL || w->enable == 0) 3731 continue; 3732 if (cfl & HDA_COMMIT_CONN) { 3733 if (w->selconn == -1) 3734 w->selconn = 0; 3735 if (w->nconns > 0) 3736 hdac_widget_connection_select(w, w->selconn); 3737 } 3738 if ((cfl & HDA_COMMIT_CTRL) && 3739 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 3740 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 3741 (HDA_DAC_PATH | HDA_ADC_PATH)) 3742 device_printf(sc->dev, "WARNING: node %d " 3743 "participate both for DAC/ADC!\n", w->nid); 3744 if (w->pflags & HDA_DAC_PATH) { 3745 w->wclass.pin.ctrl &= 3746 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 3747 if ((w->wclass.pin.config & 3748 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 3749 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 3750 w->wclass.pin.ctrl &= 3751 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 3752 } else if (w->pflags & HDA_ADC_PATH) { 3753 w->wclass.pin.ctrl &= 3754 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3755 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 3756 } else 3757 w->wclass.pin.ctrl &= ~( 3758 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 3759 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 3760 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 3761 hdac_command(sc, 3762 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 3763 w->wclass.pin.ctrl), cad); 3764 } 3765 if ((cfl & HDA_COMMIT_EAPD) && 3766 w->param.eapdbtl != 0xffffffff) 3767 hdac_command(sc, 3768 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 3769 w->param.eapdbtl), cad); 3770 3771 DELAY(1000); 3772 } 3773} 3774 3775static void 3776hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 3777{ 3778 struct hdac_softc *sc = devinfo->codec->sc; 3779 struct hdac_audio_ctl *ctl; 3780 int i; 3781 3782 devinfo->function.audio.mvol = 100 | (100 << 8); 3783 i = 0; 3784 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3785 if (ctl->enable == 0 || ctl->widget == NULL) { 3786 HDA_BOOTVERBOSE_MSG( 3787 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3788 i, (ctl->widget != NULL) ? 3789 ctl->widget->nid : -1); 3790 if (ctl->childwidget != NULL) 3791 printf(" childnid=%d", 3792 ctl->childwidget->nid); 3793 if (ctl->widget == NULL) 3794 printf(" NULL WIDGET!"); 3795 printf(" DISABLED\n"); 3796 ); 3797 continue; 3798 } 3799 HDA_BOOTVERBOSE_MSG( 3800 if (ctl->ossmask == 0) { 3801 device_printf(sc->dev, "[%2d] Ctl nid=%d", 3802 i, ctl->widget->nid); 3803 if (ctl->childwidget != NULL) 3804 printf(" childnid=%d", 3805 ctl->childwidget->nid); 3806 printf(" Bind to NONE\n"); 3807 } 3808 ); 3809 if (ctl->step > 0) { 3810 ctl->ossval = (ctl->left * 100) / ctl->step; 3811 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 3812 } else 3813 ctl->ossval = 0; 3814 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 3815 ctl->left, ctl->right); 3816 } 3817} 3818 3819static int 3820hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 3821{ 3822 struct hdac_chan *ch; 3823 struct hdac_widget *w; 3824 uint32_t cap, fmtcap, pcmcap, path; 3825 int i, type, ret, max; 3826 3827 if (dir == PCMDIR_PLAY) { 3828 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 3829 ch = &devinfo->codec->sc->play; 3830 path = HDA_DAC_PATH; 3831 } else { 3832 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 3833 ch = &devinfo->codec->sc->rec; 3834 path = HDA_ADC_PATH; 3835 } 3836 3837 ch->caps = hdac_caps; 3838 ch->caps.fmtlist = ch->fmtlist; 3839 ch->bit16 = 1; 3840 ch->bit32 = 0; 3841 ch->pcmrates[0] = 48000; 3842 ch->pcmrates[1] = 0; 3843 3844 ret = 0; 3845 fmtcap = devinfo->function.audio.supp_stream_formats; 3846 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 3847 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 3848 3849 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 3850 w = hdac_widget_get(devinfo, i); 3851 if (w == NULL || w->enable == 0 || w->type != type || 3852 (w->pflags & path) == 0) 3853 continue; 3854 cap = w->param.widget_cap; 3855 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 3856 continue;*/ 3857 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 3858 continue; 3859 cap = w->param.supp_stream_formats; 3860 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 3861 } 3862 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 3863 }*/ 3864 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 3865 continue; 3866 ch->io[ret++] = i; 3867 fmtcap &= w->param.supp_stream_formats; 3868 pcmcap &= w->param.supp_pcm_size_rate; 3869 } 3870 ch->io[ret] = -1; 3871 3872 ch->supp_stream_formats = fmtcap; 3873 ch->supp_pcm_size_rate = pcmcap; 3874 3875 /* 3876 * 8bit = 0 3877 * 16bit = 1 3878 * 20bit = 2 3879 * 24bit = 3 3880 * 32bit = 4 3881 */ 3882 if (ret > 0) { 3883 cap = pcmcap; 3884 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 3885 ch->bit16 = 1; 3886 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 3887 ch->bit16 = 0; 3888 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 3889 ch->bit32 = 4; 3890 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 3891 ch->bit32 = 3; 3892 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 3893 ch->bit32 = 2; 3894 i = 0; 3895 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 3896 ch->fmtlist[i++] = AFMT_S16_LE; 3897 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 3898 if (ch->bit32 > 0) { 3899 if (!(devinfo->function.audio.quirks & 3900 HDA_QUIRK_FORCESTEREO)) 3901 ch->fmtlist[i++] = AFMT_S32_LE; 3902 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 3903 } 3904 ch->fmtlist[i] = 0; 3905 i = 0; 3906 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 3907 ch->pcmrates[i++] = 8000; 3908 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 3909 ch->pcmrates[i++] = 11025; 3910 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 3911 ch->pcmrates[i++] = 16000; 3912 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 3913 ch->pcmrates[i++] = 22050; 3914 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 3915 ch->pcmrates[i++] = 32000; 3916 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 3917 ch->pcmrates[i++] = 44100; 3918 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 3919 ch->pcmrates[i++] = 48000; 3920 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 3921 ch->pcmrates[i++] = 88200; 3922 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 3923 ch->pcmrates[i++] = 96000; 3924 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 3925 ch->pcmrates[i++] = 176400; 3926 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 3927 ch->pcmrates[i++] = 192000; 3928 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 3929 ch->pcmrates[i] = 0; 3930 if (i > 0) { 3931 ch->caps.minspeed = ch->pcmrates[0]; 3932 ch->caps.maxspeed = ch->pcmrates[i - 1]; 3933 } 3934 } 3935 3936 return (ret); 3937} 3938 3939static void 3940hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 3941{ 3942 struct hdac_audio_ctl *ctl; 3943 struct hdac_softc *sc = devinfo->codec->sc; 3944 int i; 3945 uint32_t fl = 0; 3946 3947 3948 if (flag == 0) { 3949 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 3950 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 3951 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 3952 } 3953 3954 i = 0; 3955 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3956 if (ctl->enable == 0 || ctl->widget == NULL || 3957 ctl->widget->enable == 0) 3958 continue; 3959 if ((flag == 0 && (ctl->ossmask & ~fl)) || 3960 (flag != 0 && (ctl->ossmask & flag))) { 3961 if (banner != NULL) { 3962 device_printf(sc->dev, "\n"); 3963 device_printf(sc->dev, "%s\n", banner); 3964 } 3965 goto hdac_ctl_dump_it_all; 3966 } 3967 } 3968 3969 return; 3970 3971hdac_ctl_dump_it_all: 3972 i = 0; 3973 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3974 if (ctl->enable == 0 || ctl->widget == NULL || 3975 ctl->widget->enable == 0) 3976 continue; 3977 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 3978 (flag != 0 && (ctl->ossmask & flag)))) 3979 continue; 3980 if (flag == 0) { 3981 device_printf(sc->dev, "\n"); 3982 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 3983 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 3984 } 3985 device_printf(sc->dev, " |\n"); 3986 device_printf(sc->dev, " +- nid: %2d index: %2d ", 3987 ctl->widget->nid, ctl->index); 3988 if (ctl->childwidget != NULL) 3989 printf("(nid: %2d) ", ctl->childwidget->nid); 3990 else 3991 printf(" "); 3992 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 3993 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 3994 ctl->ossmask); 3995 } 3996} 3997 3998static void 3999hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4000{ 4001 uint32_t cap; 4002 4003 cap = fcap; 4004 if (cap != 0) { 4005 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4006 device_printf(sc->dev, " Format:"); 4007 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4008 printf(" AC3"); 4009 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4010 printf(" FLOAT32"); 4011 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4012 printf(" PCM"); 4013 printf("\n"); 4014 } 4015 cap = pcmcap; 4016 if (cap != 0) { 4017 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4018 device_printf(sc->dev, " PCM size:"); 4019 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4020 printf(" 8"); 4021 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4022 printf(" 16"); 4023 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4024 printf(" 20"); 4025 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4026 printf(" 24"); 4027 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4028 printf(" 32"); 4029 printf("\n"); 4030 device_printf(sc->dev, " PCM rate:"); 4031 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4032 printf(" 8"); 4033 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4034 printf(" 11"); 4035 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4036 printf(" 16"); 4037 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4038 printf(" 22"); 4039 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4040 printf(" 32"); 4041 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4042 printf(" 44"); 4043 printf(" 48"); 4044 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4045 printf(" 88"); 4046 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4047 printf(" 96"); 4048 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4049 printf(" 176"); 4050 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4051 printf(" 192"); 4052 printf("\n"); 4053 } 4054} 4055 4056static void 4057hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4058{ 4059 uint32_t pincap, wcap; 4060 4061 pincap = w->wclass.pin.cap; 4062 wcap = w->param.widget_cap; 4063 4064 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4065 device_printf(sc->dev, " "); 4066 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4067 printf(" ISC"); 4068 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4069 printf(" TRQD"); 4070 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4071 printf(" PDC"); 4072 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4073 printf(" HP"); 4074 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4075 printf(" OUT"); 4076 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4077 printf(" IN"); 4078 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4079 printf(" BAL"); 4080 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4081 printf(" EAPD"); 4082 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4083 printf(" : UNSOL"); 4084 printf("\n"); 4085 device_printf(sc->dev, " Pin config: 0x%08x\n", 4086 w->wclass.pin.config); 4087 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4088 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4089 printf(" HP"); 4090 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4091 printf(" IN"); 4092 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4093 printf(" OUT"); 4094 printf("\n"); 4095} 4096 4097static void 4098hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4099{ 4100 device_printf(sc->dev, " %s amp: 0x%0x\n", banner, cap); 4101 device_printf(sc->dev, " " 4102 "mute=%d step=%d size=%d offset=%d\n", 4103 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4104 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4105 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4106 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4107} 4108 4109static void 4110hdac_dump_nodes(struct hdac_devinfo *devinfo) 4111{ 4112 struct hdac_softc *sc = devinfo->codec->sc; 4113 struct hdac_widget *w, *cw; 4114 int i, j; 4115 4116 device_printf(sc->dev, "\n"); 4117 device_printf(sc->dev, "Default Parameter\n"); 4118 device_printf(sc->dev, "-----------------\n"); 4119 hdac_dump_audio_formats(sc, 4120 devinfo->function.audio.supp_stream_formats, 4121 devinfo->function.audio.supp_pcm_size_rate); 4122 device_printf(sc->dev, " IN amp: 0x%08x\n", 4123 devinfo->function.audio.inamp_cap); 4124 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4125 devinfo->function.audio.outamp_cap); 4126 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4127 w = hdac_widget_get(devinfo, i); 4128 if (w == NULL) { 4129 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4130 continue; 4131 } 4132 device_printf(sc->dev, "\n"); 4133 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4134 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4135 "DIGITAL" : "ANALOG", 4136 (w->enable == 0) ? " [DISABLED]" : ""); 4137 device_printf(sc->dev, " name: %s\n", w->name); 4138 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4139 w->param.widget_cap); 4140 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4141 w->pflags); 4142 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4143 w->ctlflags); 4144 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4145 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4146 hdac_dump_audio_formats(sc, 4147 w->param.supp_stream_formats, 4148 w->param.supp_pcm_size_rate); 4149 } else if (w->type == 4150 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4151 hdac_dump_pin(sc, w); 4152 if (w->param.eapdbtl != 0xffffffff) 4153 device_printf(sc->dev, " EAPD: 0x%08x\n", 4154 w->param.eapdbtl); 4155 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap)) 4156 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4157 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap)) 4158 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4159 device_printf(sc->dev, " connections: %d\n", w->nconns); 4160 for (j = 0; j < w->nconns; j++) { 4161 cw = hdac_widget_get(devinfo, w->conns[j]); 4162 device_printf(sc->dev, " |\n"); 4163 device_printf(sc->dev, " + <- nid=%d [%s]", 4164 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4165 if (cw == NULL) 4166 printf(" [UNKNOWN]"); 4167 else if (cw->enable == 0) 4168 printf(" [DISABLED]"); 4169 if (w->nconns > 1 && w->selconn == j && w->type != 4170 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4171 printf(" (selected)"); 4172 printf("\n"); 4173 } 4174 } 4175 4176} 4177 4178static void 4179hdac_dump_dac(struct hdac_devinfo *devinfo) 4180{ 4181 /* XXX TODO */ 4182} 4183 4184static void 4185hdac_dump_adc(struct hdac_devinfo *devinfo) 4186{ 4187 struct hdac_widget *w, *cw; 4188 struct hdac_softc *sc = devinfo->codec->sc; 4189 int i, j; 4190 int printed = 0; 4191 char ossdevs[256]; 4192 4193 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4194 w = hdac_widget_get(devinfo, i); 4195 if (w == NULL || w->enable == 0) 4196 continue; 4197 if (!(w->pflags & HDA_ADC_RECSEL)) 4198 continue; 4199 if (printed == 0) { 4200 printed = 1; 4201 device_printf(sc->dev, "\n"); 4202 device_printf(sc->dev, "Recording sources:\n"); 4203 } 4204 device_printf(sc->dev, "\n"); 4205 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4206 for (j = 0; j < w->nconns; j++) { 4207 cw = hdac_widget_get(devinfo, w->conns[j]); 4208 if (cw == NULL || cw->enable == 0) 4209 continue; 4210 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4211 ossdevs, sizeof(ossdevs)); 4212 device_printf(sc->dev, " |\n"); 4213 device_printf(sc->dev, " + <- nid=%d [%s]", 4214 cw->nid, cw->name); 4215 if (strlen(ossdevs) > 0) { 4216 printf(" [recsrc: %s]", ossdevs); 4217 } 4218 printf("\n"); 4219 } 4220 } 4221} 4222 4223static void 4224hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4225{ 4226 nid_t *nids; 4227 4228 if (pcnt > 0) { 4229 device_printf(sc->dev, "\n"); 4230 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4231 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4232 sc->play.supp_pcm_size_rate); 4233 device_printf(sc->dev, " DAC:"); 4234 for (nids = sc->play.io; *nids != -1; nids++) 4235 printf(" %d", *nids); 4236 printf("\n"); 4237 } 4238 4239 if (rcnt > 0) { 4240 device_printf(sc->dev, "\n"); 4241 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 4242 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4243 sc->rec.supp_pcm_size_rate); 4244 device_printf(sc->dev, " ADC:"); 4245 for (nids = sc->rec.io; *nids != -1; nids++) 4246 printf(" %d", *nids); 4247 printf("\n"); 4248 } 4249} 4250 4251static void 4252hdac_attach2(void *arg) 4253{ 4254 struct hdac_softc *sc; 4255 struct hdac_widget *w; 4256 struct hdac_audio_ctl *ctl; 4257 int pcnt, rcnt; 4258 int i; 4259 char status[SND_STATUSLEN]; 4260 device_t *devlist; 4261 int devcount; 4262 struct hdac_devinfo *devinfo = NULL; 4263 4264 sc = (struct hdac_softc *)arg; 4265 4266 4267 hdac_lock(sc); 4268 4269 /* Remove ourselves from the config hooks */ 4270 if (sc->intrhook.ich_func != NULL) { 4271 config_intrhook_disestablish(&sc->intrhook); 4272 sc->intrhook.ich_func = NULL; 4273 } 4274 4275 /* Start the corb and rirb engines */ 4276 HDA_DEBUG_MSG( 4277 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 4278 ); 4279 hdac_corb_start(sc); 4280 HDA_DEBUG_MSG( 4281 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 4282 ); 4283 hdac_rirb_start(sc); 4284 4285 HDA_DEBUG_MSG( 4286 device_printf(sc->dev, 4287 "HDA_DEBUG: Enabling controller interrupt...\n"); 4288 ); 4289 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 4290 4291 DELAY(1000); 4292 4293 HDA_DEBUG_MSG( 4294 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 4295 ); 4296 hdac_scan_codecs(sc); 4297 4298 device_get_children(sc->dev, &devlist, &devcount); 4299 if (devcount != 0 && devlist != NULL) { 4300 for (i = 0; i < devcount; i++) { 4301 devinfo = (struct hdac_devinfo *) 4302 device_get_ivars(devlist[i]); 4303 if (devinfo != NULL && 4304 devinfo->node_type == 4305 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 4306 break; 4307 } else 4308 devinfo = NULL; 4309 } 4310 } 4311 4312 if (devinfo == NULL) { 4313 hdac_unlock(sc); 4314 device_printf(sc->dev, "Audio Function Group not found!\n"); 4315 return; 4316 } 4317 4318 HDA_DEBUG_MSG( 4319 device_printf(sc->dev, 4320 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 4321 devinfo->nid, devinfo->codec->cad); 4322 ); 4323 hdac_audio_parse(devinfo); 4324 HDA_DEBUG_MSG( 4325 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 4326 ); 4327 hdac_audio_ctl_parse(devinfo); 4328 HDA_DEBUG_MSG( 4329 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 4330 ); 4331 hdac_vendor_patch_parse(devinfo); 4332 4333 /* XXX Disable all DIGITAL path. */ 4334 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4335 w = hdac_widget_get(devinfo, i); 4336 if (w == NULL) 4337 continue; 4338 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4339 w->enable = 0; 4340 continue; 4341 } 4342 /* XXX Disable useless pin ? */ 4343 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4344 (w->wclass.pin.config & 4345 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4346 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4347 w->enable = 0; 4348 } 4349 i = 0; 4350 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4351 if (ctl->widget == NULL) 4352 continue; 4353 w = ctl->widget; 4354 if (w->enable == 0) 4355 ctl->enable = 0; 4356 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4357 ctl->enable = 0; 4358 w = ctl->childwidget; 4359 if (w == NULL) 4360 continue; 4361 if (w->enable == 0 || 4362 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4363 ctl->enable = 0; 4364 } 4365 4366 HDA_DEBUG_MSG( 4367 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 4368 ); 4369 hdac_audio_build_tree(devinfo); 4370 4371 HDA_DEBUG_MSG( 4372 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 4373 ); 4374 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 4375 HDA_DEBUG_MSG( 4376 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 4377 ); 4378 hdac_audio_ctl_commit(devinfo); 4379 4380 HDA_DEBUG_MSG( 4381 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 4382 ); 4383 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 4384 HDA_DEBUG_MSG( 4385 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 4386 ); 4387 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 4388 4389 hdac_unlock(sc); 4390 HDA_DEBUG_MSG( 4391 device_printf(sc->dev, 4392 "HDA_DEBUG: OSS mixer initialization...\n"); 4393 ); 4394 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo)) { 4395 device_printf(sc->dev, "Can't register mixer\n"); 4396 } 4397 4398 if (pcnt > 0) 4399 pcnt = 1; 4400 if (rcnt > 0) 4401 rcnt = 1; 4402 4403 HDA_DEBUG_MSG( 4404 device_printf(sc->dev, 4405 "HDA_DEBUG: Registering PCM channels...\n"); 4406 ); 4407 if (pcm_register(sc->dev, devinfo, pcnt, rcnt)) { 4408 device_printf(sc->dev, "Can't register PCM\n"); 4409 } 4410 4411 sc->registered++; 4412 4413 for (i = 0; i < pcnt; i++) 4414 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 4415 for (i = 0; i < rcnt; i++) 4416 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 4417 4418 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 4419 rman_get_start(sc->mem.mem_res), 4420 rman_get_start(sc->irq.irq_res), 4421 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 4422 pcm_setstatus(sc->dev, status); 4423 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 4424 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", HDA_DRV_TEST_REV); 4425 4426 HDA_BOOTVERBOSE_MSG( 4427 if (devinfo->function.audio.quirks != 0) { 4428 device_printf(sc->dev, "\n"); 4429 device_printf(sc->dev, "HDA quirks:"); 4430 if (devinfo->function.audio.quirks & 4431 HDA_QUIRK_GPIO1) 4432 printf(" GPIO1"); 4433 if (devinfo->function.audio.quirks & 4434 HDA_QUIRK_GPIO2) 4435 printf(" GPIO2"); 4436 if (devinfo->function.audio.quirks & 4437 HDA_QUIRK_SOFTPCMVOL) 4438 printf(" SOFTPCMVOL"); 4439 if (devinfo->function.audio.quirks & 4440 HDA_QUIRK_FIXEDRATE) 4441 printf(" FIXEDRATE"); 4442 if (devinfo->function.audio.quirks & 4443 HDA_QUIRK_FORCESTEREO) 4444 printf(" FORCESTEREO"); 4445 printf("\n"); 4446 } 4447 device_printf(sc->dev, "\n"); 4448 device_printf(sc->dev, "+-------------------+\n"); 4449 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 4450 device_printf(sc->dev, "+-------------------+\n"); 4451 hdac_dump_nodes(devinfo); 4452 device_printf(sc->dev, "\n"); 4453 device_printf(sc->dev, "+------------------------+\n"); 4454 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 4455 device_printf(sc->dev, "+------------------------+\n"); 4456 device_printf(sc->dev, "\n"); 4457 i = 0; 4458 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4459 device_printf(sc->dev, "%3d: nid=%d", i, 4460 (ctl->widget != NULL) ? ctl->widget->nid : -1); 4461 if (ctl->childwidget != NULL) 4462 printf(" cnid=%d", ctl->childwidget->nid); 4463 printf(" dir=0x%x index=%d " 4464 "ossmask=0x%08x ossdev=%d%s\n", 4465 ctl->dir, ctl->index, 4466 ctl->ossmask, ctl->ossdev, 4467 (ctl->enable == 0) ? " [DISABLED]" : ""); 4468 } 4469 device_printf(sc->dev, "\n"); 4470 device_printf(sc->dev, "+-----------------------------------+\n"); 4471 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 4472 device_printf(sc->dev, "+-----------------------------------+\n"); 4473 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 4474 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 4475 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 4476 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 4477 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 4478 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 4479 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 4480 hdac_dump_ctls(devinfo, NULL, 0); 4481 hdac_dump_dac(devinfo); 4482 hdac_dump_adc(devinfo); 4483 device_printf(sc->dev, "\n"); 4484 device_printf(sc->dev, "+--------------------------------------+\n"); 4485 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 4486 device_printf(sc->dev, "+--------------------------------------+\n"); 4487 hdac_dump_pcmchannels(sc, pcnt, rcnt); 4488 ); 4489} 4490 4491/**************************************************************************** 4492 * int hdac_detach(device_t) 4493 * 4494 * Detach and free up resources utilized by the hdac device. 4495 ****************************************************************************/ 4496static int 4497hdac_detach(device_t dev) 4498{ 4499 struct hdac_softc *sc = NULL; 4500 device_t *devlist; 4501 int devcount; 4502 struct hdac_devinfo *devinfo = NULL; 4503 struct hdac_codec *codec, *codec_tmp; 4504 int i; 4505 4506 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 4507 if (devinfo != NULL && devinfo->codec != NULL) 4508 sc = devinfo->codec->sc; 4509 if (sc == NULL) 4510 return (EINVAL); 4511 4512 if (sc->registered > 0) { 4513 i = pcm_unregister(dev); 4514 if (i) 4515 return (i); 4516 } 4517 4518 sc->registered = 0; 4519 4520 /* Lock the mutex before messing with the dma engines */ 4521 hdac_lock(sc); 4522 hdac_reset(sc); 4523 hdac_unlock(sc); 4524 snd_mtxfree(sc->lock); 4525 sc->lock = NULL; 4526 4527 device_get_children(sc->dev, &devlist, &devcount); 4528 if (devcount != 0 && devlist != NULL) { 4529 for (i = 0; i < devcount; i++) { 4530 devinfo = (struct hdac_devinfo *) 4531 device_get_ivars(devlist[i]); 4532 if (devinfo == NULL) 4533 continue; 4534 if (devinfo->widget != NULL) { 4535 free(devinfo->widget, M_HDAC); 4536 } 4537 if (devinfo->node_type == 4538 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 4539 devinfo->function.audio.ctl != NULL) { 4540 free(devinfo->function.audio.ctl, M_HDAC); 4541 } 4542 4543 free(devinfo, M_HDAC); 4544 device_delete_child(sc->dev, devlist[i]); 4545 } 4546 free(devlist, M_TEMP); 4547 } 4548 4549 SLIST_FOREACH_SAFE(codec, &sc->codec_list, next_codec, codec_tmp) { 4550 SLIST_REMOVE(&sc->codec_list, codec, hdac_codec, 4551 next_codec); 4552 free((void *)codec, M_HDAC); 4553 } 4554 4555 hdac_dma_free(&sc->rirb_dma); 4556 hdac_dma_free(&sc->corb_dma); 4557 if (sc->play.blkcnt) 4558 hdac_dma_free(&sc->play.bdl_dma); 4559 if (sc->rec.blkcnt) 4560 hdac_dma_free(&sc->rec.bdl_dma); 4561 hdac_irq_free(sc); 4562 hdac_mem_free(sc); 4563 free(sc, M_DEVBUF); 4564 4565 return (0); 4566} 4567 4568static device_method_t hdac_methods[] = { 4569 /* device interface */ 4570 DEVMETHOD(device_probe, hdac_probe), 4571 DEVMETHOD(device_attach, hdac_attach), 4572 DEVMETHOD(device_detach, hdac_detach), 4573 { 0, 0 } 4574}; 4575 4576static driver_t hdac_driver = { 4577 "pcm", 4578 hdac_methods, 4579 PCM_SOFTC_SIZE, 4580}; 4581 4582DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 4583MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 4584MODULE_VERSION(snd_hda, 1); 4585