hdac.c revision 345822
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_snd.h" 35#endif 36 37#include <dev/sound/pcm/sound.h> 38#include <dev/pci/pcireg.h> 39#include <dev/pci/pcivar.h> 40 41#include <sys/ctype.h> 42#include <sys/taskqueue.h> 43 44#include <dev/sound/pci/hda/hdac_private.h> 45#include <dev/sound/pci/hda/hdac_reg.h> 46#include <dev/sound/pci/hda/hda_reg.h> 47#include <dev/sound/pci/hda/hdac.h> 48 49#define HDA_DRV_TEST_REV "20120126_0002" 50 51SND_DECLARE_FILE("$FreeBSD: stable/11/sys/dev/sound/pci/hda/hdac.c 345822 2019-04-03 01:30:59Z mav $"); 52 53#define hdac_lock(sc) snd_mtxlock((sc)->lock) 54#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56#define hdac_lockowned(sc) mtx_owned((sc)->lock) 57 58#define HDAC_QUIRK_64BIT (1 << 0) 59#define HDAC_QUIRK_DMAPOS (1 << 1) 60#define HDAC_QUIRK_MSI (1 << 2) 61 62static const struct { 63 const char *key; 64 uint32_t value; 65} hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69}; 70 71MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 72 73static const struct { 74 uint32_t model; 75 const char *desc; 76 char quirks_on; 77 char quirks_off; 78} hdac_devices[] = { 79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 80 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 81 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 82 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 83 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 85 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 }, 86 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 87 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 88 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 89 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 90 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 91 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 92 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 93 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 94 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 95 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 96 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 97 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 }, 98 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 99 { HDA_INTEL_KBLK, "Intel Kaby Lake", 0, 0 }, 100 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 }, 101 { HDA_INTEL_CFLK, "Intel Coffee Lake", 0, 0 }, 102 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 103 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 104 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 105 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 106 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 107 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 108 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 109 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 }, 110 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 }, 111 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 112 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 113 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 114 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 115 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 116 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 117 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 118 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 119 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 120 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 121 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 122 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 123 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 124 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 125 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 126 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 127 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 128 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 129 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 130 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 131 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 132 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 133 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 134 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 135 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 136 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 137 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 138 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 139 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 140 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 141 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 142 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 143 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 144 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 145 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 146 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 147 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 148 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 149 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 150 { HDA_ATI_R600, "ATI R600", 0, 0 }, 151 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 152 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 153 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 154 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 155 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 156 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 157 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 158 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 159 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 160 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 161 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 162 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 163 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 164 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 165 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 166 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 167 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 168 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 169 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 170 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 171 { HDA_SIS_966, "SiS 966", 0, 0 }, 172 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 173 /* Unknown */ 174 { HDA_INTEL_ALL, "Intel", 0, 0 }, 175 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 176 { HDA_ATI_ALL, "ATI", 0, 0 }, 177 { HDA_AMD_ALL, "AMD", 0, 0 }, 178 { HDA_CREATIVE_ALL, "Creative", 0, 0 }, 179 { HDA_VIA_ALL, "VIA", 0, 0 }, 180 { HDA_SIS_ALL, "SiS", 0, 0 }, 181 { HDA_ULI_ALL, "ULI", 0, 0 }, 182}; 183 184static const struct { 185 uint16_t vendor; 186 uint8_t reg; 187 uint8_t mask; 188 uint8_t enable; 189} hdac_pcie_snoop[] = { 190 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 191 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 192 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 193}; 194 195/**************************************************************************** 196 * Function prototypes 197 ****************************************************************************/ 198static void hdac_intr_handler(void *); 199static int hdac_reset(struct hdac_softc *, int); 200static int hdac_get_capabilities(struct hdac_softc *); 201static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 202static int hdac_dma_alloc(struct hdac_softc *, 203 struct hdac_dma *, bus_size_t); 204static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 205static int hdac_mem_alloc(struct hdac_softc *); 206static void hdac_mem_free(struct hdac_softc *); 207static int hdac_irq_alloc(struct hdac_softc *); 208static void hdac_irq_free(struct hdac_softc *); 209static void hdac_corb_init(struct hdac_softc *); 210static void hdac_rirb_init(struct hdac_softc *); 211static void hdac_corb_start(struct hdac_softc *); 212static void hdac_rirb_start(struct hdac_softc *); 213 214static void hdac_attach2(void *); 215 216static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 217 218static int hdac_probe(device_t); 219static int hdac_attach(device_t); 220static int hdac_detach(device_t); 221static int hdac_suspend(device_t); 222static int hdac_resume(device_t); 223 224static int hdac_rirb_flush(struct hdac_softc *sc); 225static int hdac_unsolq_flush(struct hdac_softc *sc); 226 227#define hdac_command(a1, a2, a3) \ 228 hdac_send_command(a1, a3, a2) 229 230/* This function surely going to make its way into upper level someday. */ 231static void 232hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 233{ 234 const char *res = NULL; 235 int i = 0, j, k, len, inv; 236 237 if (resource_string_value(device_get_name(sc->dev), 238 device_get_unit(sc->dev), "config", &res) != 0) 239 return; 240 if (!(res != NULL && strlen(res) > 0)) 241 return; 242 HDA_BOOTVERBOSE( 243 device_printf(sc->dev, "Config options:"); 244 ); 245 for (;;) { 246 while (res[i] != '\0' && 247 (res[i] == ',' || isspace(res[i]) != 0)) 248 i++; 249 if (res[i] == '\0') { 250 HDA_BOOTVERBOSE( 251 printf("\n"); 252 ); 253 return; 254 } 255 j = i; 256 while (res[j] != '\0' && 257 !(res[j] == ',' || isspace(res[j]) != 0)) 258 j++; 259 len = j - i; 260 if (len > 2 && strncmp(res + i, "no", 2) == 0) 261 inv = 2; 262 else 263 inv = 0; 264 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 265 if (strncmp(res + i + inv, 266 hdac_quirks_tab[k].key, len - inv) != 0) 267 continue; 268 if (len - inv != strlen(hdac_quirks_tab[k].key)) 269 continue; 270 HDA_BOOTVERBOSE( 271 printf(" %s%s", (inv != 0) ? "no" : "", 272 hdac_quirks_tab[k].key); 273 ); 274 if (inv == 0) { 275 *on |= hdac_quirks_tab[k].value; 276 *on &= ~hdac_quirks_tab[k].value; 277 } else if (inv != 0) { 278 *off |= hdac_quirks_tab[k].value; 279 *off &= ~hdac_quirks_tab[k].value; 280 } 281 break; 282 } 283 i = j; 284 } 285} 286 287/**************************************************************************** 288 * void hdac_intr_handler(void *) 289 * 290 * Interrupt handler. Processes interrupts received from the hdac. 291 ****************************************************************************/ 292static void 293hdac_intr_handler(void *context) 294{ 295 struct hdac_softc *sc; 296 device_t dev; 297 uint32_t intsts; 298 uint8_t rirbsts; 299 int i; 300 301 sc = (struct hdac_softc *)context; 302 hdac_lock(sc); 303 304 /* Do we have anything to do? */ 305 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 306 if ((intsts & HDAC_INTSTS_GIS) == 0) { 307 hdac_unlock(sc); 308 return; 309 } 310 311 /* Was this a controller interrupt? */ 312 if (intsts & HDAC_INTSTS_CIS) { 313 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 314 /* Get as many responses that we can */ 315 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 316 HDAC_WRITE_1(&sc->mem, 317 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 318 hdac_rirb_flush(sc); 319 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 320 } 321 if (sc->unsolq_rp != sc->unsolq_wp) 322 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 323 } 324 325 if (intsts & HDAC_INTSTS_SIS_MASK) { 326 for (i = 0; i < sc->num_ss; i++) { 327 if ((intsts & (1 << i)) == 0) 328 continue; 329 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 330 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 331 if ((dev = sc->streams[i].dev) != NULL) { 332 HDAC_STREAM_INTR(dev, 333 sc->streams[i].dir, sc->streams[i].stream); 334 } 335 } 336 } 337 338 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 339 hdac_unlock(sc); 340} 341 342static void 343hdac_poll_callback(void *arg) 344{ 345 struct hdac_softc *sc = arg; 346 347 if (sc == NULL) 348 return; 349 350 hdac_lock(sc); 351 if (sc->polling == 0) { 352 hdac_unlock(sc); 353 return; 354 } 355 callout_reset(&sc->poll_callout, sc->poll_ival, 356 hdac_poll_callback, sc); 357 hdac_unlock(sc); 358 359 hdac_intr_handler(sc); 360} 361 362/**************************************************************************** 363 * int hdac_reset(hdac_softc *, int) 364 * 365 * Reset the hdac to a quiescent and known state. 366 ****************************************************************************/ 367static int 368hdac_reset(struct hdac_softc *sc, int wakeup) 369{ 370 uint32_t gctl; 371 int count, i; 372 373 /* 374 * Stop all Streams DMA engine 375 */ 376 for (i = 0; i < sc->num_iss; i++) 377 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 378 for (i = 0; i < sc->num_oss; i++) 379 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 380 for (i = 0; i < sc->num_bss; i++) 381 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 382 383 /* 384 * Stop Control DMA engines. 385 */ 386 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 387 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 388 389 /* 390 * Reset DMA position buffer. 391 */ 392 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 393 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 394 395 /* 396 * Reset the controller. The reset must remain asserted for 397 * a minimum of 100us. 398 */ 399 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 400 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 401 count = 10000; 402 do { 403 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 404 if (!(gctl & HDAC_GCTL_CRST)) 405 break; 406 DELAY(10); 407 } while (--count); 408 if (gctl & HDAC_GCTL_CRST) { 409 device_printf(sc->dev, "Unable to put hdac in reset\n"); 410 return (ENXIO); 411 } 412 413 /* If wakeup is not requested - leave the controller in reset state. */ 414 if (!wakeup) 415 return (0); 416 417 DELAY(100); 418 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 419 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 420 count = 10000; 421 do { 422 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 423 if (gctl & HDAC_GCTL_CRST) 424 break; 425 DELAY(10); 426 } while (--count); 427 if (!(gctl & HDAC_GCTL_CRST)) { 428 device_printf(sc->dev, "Device stuck in reset\n"); 429 return (ENXIO); 430 } 431 432 /* 433 * Wait for codecs to finish their own reset sequence. The delay here 434 * should be of 250us but for some reasons, on it's not enough on my 435 * computer. Let's use twice as much as necessary to make sure that 436 * it's reset properly. 437 */ 438 DELAY(1000); 439 440 return (0); 441} 442 443 444/**************************************************************************** 445 * int hdac_get_capabilities(struct hdac_softc *); 446 * 447 * Retreive the general capabilities of the hdac; 448 * Number of Input Streams 449 * Number of Output Streams 450 * Number of bidirectional Streams 451 * 64bit ready 452 * CORB and RIRB sizes 453 ****************************************************************************/ 454static int 455hdac_get_capabilities(struct hdac_softc *sc) 456{ 457 uint16_t gcap; 458 uint8_t corbsize, rirbsize; 459 460 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 461 sc->num_iss = HDAC_GCAP_ISS(gcap); 462 sc->num_oss = HDAC_GCAP_OSS(gcap); 463 sc->num_bss = HDAC_GCAP_BSS(gcap); 464 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 465 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 466 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 467 if (sc->quirks_on & HDAC_QUIRK_64BIT) 468 sc->support_64bit = 1; 469 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 470 sc->support_64bit = 0; 471 472 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 473 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 474 HDAC_CORBSIZE_CORBSZCAP_256) 475 sc->corb_size = 256; 476 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 477 HDAC_CORBSIZE_CORBSZCAP_16) 478 sc->corb_size = 16; 479 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 480 HDAC_CORBSIZE_CORBSZCAP_2) 481 sc->corb_size = 2; 482 else { 483 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 484 __func__, corbsize); 485 return (ENXIO); 486 } 487 488 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 489 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 490 HDAC_RIRBSIZE_RIRBSZCAP_256) 491 sc->rirb_size = 256; 492 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 493 HDAC_RIRBSIZE_RIRBSZCAP_16) 494 sc->rirb_size = 16; 495 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 496 HDAC_RIRBSIZE_RIRBSZCAP_2) 497 sc->rirb_size = 2; 498 else { 499 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 500 __func__, rirbsize); 501 return (ENXIO); 502 } 503 504 HDA_BOOTVERBOSE( 505 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 506 "NSDO %d%s, CORB %d, RIRB %d\n", 507 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 508 sc->support_64bit ? ", 64bit" : "", 509 sc->corb_size, sc->rirb_size); 510 ); 511 512 return (0); 513} 514 515 516/**************************************************************************** 517 * void hdac_dma_cb 518 * 519 * This function is called by bus_dmamap_load when the mapping has been 520 * established. We just record the physical address of the mapping into 521 * the struct hdac_dma passed in. 522 ****************************************************************************/ 523static void 524hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 525{ 526 struct hdac_dma *dma; 527 528 if (error == 0) { 529 dma = (struct hdac_dma *)callback_arg; 530 dma->dma_paddr = segs[0].ds_addr; 531 } 532} 533 534 535/**************************************************************************** 536 * int hdac_dma_alloc 537 * 538 * This function allocate and setup a dma region (struct hdac_dma). 539 * It must be freed by a corresponding hdac_dma_free. 540 ****************************************************************************/ 541static int 542hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 543{ 544 bus_size_t roundsz; 545 int result; 546 547 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 548 bzero(dma, sizeof(*dma)); 549 550 /* 551 * Create a DMA tag 552 */ 553 result = bus_dma_tag_create( 554 bus_get_dma_tag(sc->dev), /* parent */ 555 HDA_DMA_ALIGNMENT, /* alignment */ 556 0, /* boundary */ 557 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 558 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 559 BUS_SPACE_MAXADDR, /* highaddr */ 560 NULL, /* filtfunc */ 561 NULL, /* fistfuncarg */ 562 roundsz, /* maxsize */ 563 1, /* nsegments */ 564 roundsz, /* maxsegsz */ 565 0, /* flags */ 566 NULL, /* lockfunc */ 567 NULL, /* lockfuncarg */ 568 &dma->dma_tag); /* dmat */ 569 if (result != 0) { 570 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 571 __func__, result); 572 goto hdac_dma_alloc_fail; 573 } 574 575 /* 576 * Allocate DMA memory 577 */ 578 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 579 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 580 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 581 &dma->dma_map); 582 if (result != 0) { 583 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 584 __func__, result); 585 goto hdac_dma_alloc_fail; 586 } 587 588 dma->dma_size = roundsz; 589 590 /* 591 * Map the memory 592 */ 593 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 594 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 595 if (result != 0 || dma->dma_paddr == 0) { 596 if (result == 0) 597 result = ENOMEM; 598 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 599 __func__, result); 600 goto hdac_dma_alloc_fail; 601 } 602 603 HDA_BOOTHVERBOSE( 604 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 605 __func__, (uintmax_t)size, (uintmax_t)roundsz); 606 ); 607 608 return (0); 609 610hdac_dma_alloc_fail: 611 hdac_dma_free(sc, dma); 612 613 return (result); 614} 615 616 617/**************************************************************************** 618 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 619 * 620 * Free a struct dhac_dma that has been previously allocated via the 621 * hdac_dma_alloc function. 622 ****************************************************************************/ 623static void 624hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 625{ 626 if (dma->dma_paddr != 0) { 627#if 0 628 /* Flush caches */ 629 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 630 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 631#endif 632 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 633 dma->dma_paddr = 0; 634 } 635 if (dma->dma_vaddr != NULL) { 636 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 637 dma->dma_vaddr = NULL; 638 } 639 if (dma->dma_tag != NULL) { 640 bus_dma_tag_destroy(dma->dma_tag); 641 dma->dma_tag = NULL; 642 } 643 dma->dma_size = 0; 644} 645 646/**************************************************************************** 647 * int hdac_mem_alloc(struct hdac_softc *) 648 * 649 * Allocate all the bus resources necessary to speak with the physical 650 * controller. 651 ****************************************************************************/ 652static int 653hdac_mem_alloc(struct hdac_softc *sc) 654{ 655 struct hdac_mem *mem; 656 657 mem = &sc->mem; 658 mem->mem_rid = PCIR_BAR(0); 659 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 660 &mem->mem_rid, RF_ACTIVE); 661 if (mem->mem_res == NULL) { 662 device_printf(sc->dev, 663 "%s: Unable to allocate memory resource\n", __func__); 664 return (ENOMEM); 665 } 666 mem->mem_tag = rman_get_bustag(mem->mem_res); 667 mem->mem_handle = rman_get_bushandle(mem->mem_res); 668 669 return (0); 670} 671 672/**************************************************************************** 673 * void hdac_mem_free(struct hdac_softc *) 674 * 675 * Free up resources previously allocated by hdac_mem_alloc. 676 ****************************************************************************/ 677static void 678hdac_mem_free(struct hdac_softc *sc) 679{ 680 struct hdac_mem *mem; 681 682 mem = &sc->mem; 683 if (mem->mem_res != NULL) 684 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 685 mem->mem_res); 686 mem->mem_res = NULL; 687} 688 689/**************************************************************************** 690 * int hdac_irq_alloc(struct hdac_softc *) 691 * 692 * Allocate and setup the resources necessary for interrupt handling. 693 ****************************************************************************/ 694static int 695hdac_irq_alloc(struct hdac_softc *sc) 696{ 697 struct hdac_irq *irq; 698 int result; 699 700 irq = &sc->irq; 701 irq->irq_rid = 0x0; 702 703 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 704 (result = pci_msi_count(sc->dev)) == 1 && 705 pci_alloc_msi(sc->dev, &result) == 0) 706 irq->irq_rid = 0x1; 707 708 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 709 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 710 if (irq->irq_res == NULL) { 711 device_printf(sc->dev, "%s: Unable to allocate irq\n", 712 __func__); 713 goto hdac_irq_alloc_fail; 714 } 715 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 716 NULL, hdac_intr_handler, sc, &irq->irq_handle); 717 if (result != 0) { 718 device_printf(sc->dev, 719 "%s: Unable to setup interrupt handler (%x)\n", 720 __func__, result); 721 goto hdac_irq_alloc_fail; 722 } 723 724 return (0); 725 726hdac_irq_alloc_fail: 727 hdac_irq_free(sc); 728 729 return (ENXIO); 730} 731 732/**************************************************************************** 733 * void hdac_irq_free(struct hdac_softc *) 734 * 735 * Free up resources previously allocated by hdac_irq_alloc. 736 ****************************************************************************/ 737static void 738hdac_irq_free(struct hdac_softc *sc) 739{ 740 struct hdac_irq *irq; 741 742 irq = &sc->irq; 743 if (irq->irq_res != NULL && irq->irq_handle != NULL) 744 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 745 if (irq->irq_res != NULL) 746 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 747 irq->irq_res); 748 if (irq->irq_rid == 0x1) 749 pci_release_msi(sc->dev); 750 irq->irq_handle = NULL; 751 irq->irq_res = NULL; 752 irq->irq_rid = 0x0; 753} 754 755/**************************************************************************** 756 * void hdac_corb_init(struct hdac_softc *) 757 * 758 * Initialize the corb registers for operations but do not start it up yet. 759 * The CORB engine must not be running when this function is called. 760 ****************************************************************************/ 761static void 762hdac_corb_init(struct hdac_softc *sc) 763{ 764 uint8_t corbsize; 765 uint64_t corbpaddr; 766 767 /* Setup the CORB size. */ 768 switch (sc->corb_size) { 769 case 256: 770 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 771 break; 772 case 16: 773 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 774 break; 775 case 2: 776 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 777 break; 778 default: 779 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 780 } 781 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 782 783 /* Setup the CORB Address in the hdac */ 784 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 785 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 786 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 787 788 /* Set the WP and RP */ 789 sc->corb_wp = 0; 790 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 791 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 792 /* 793 * The HDA specification indicates that the CORBRPRST bit will always 794 * read as zero. Unfortunately, it seems that at least the 82801G 795 * doesn't reset the bit to zero, which stalls the corb engine. 796 * manually reset the bit to zero before continuing. 797 */ 798 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 799 800 /* Enable CORB error reporting */ 801#if 0 802 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 803#endif 804} 805 806/**************************************************************************** 807 * void hdac_rirb_init(struct hdac_softc *) 808 * 809 * Initialize the rirb registers for operations but do not start it up yet. 810 * The RIRB engine must not be running when this function is called. 811 ****************************************************************************/ 812static void 813hdac_rirb_init(struct hdac_softc *sc) 814{ 815 uint8_t rirbsize; 816 uint64_t rirbpaddr; 817 818 /* Setup the RIRB size. */ 819 switch (sc->rirb_size) { 820 case 256: 821 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 822 break; 823 case 16: 824 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 825 break; 826 case 2: 827 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 828 break; 829 default: 830 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 831 } 832 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 833 834 /* Setup the RIRB Address in the hdac */ 835 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 836 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 837 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 838 839 /* Setup the WP and RP */ 840 sc->rirb_rp = 0; 841 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 842 843 /* Setup the interrupt threshold */ 844 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 845 846 /* Enable Overrun and response received reporting */ 847#if 0 848 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 849 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 850#else 851 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 852#endif 853 854#if 0 855 /* 856 * Make sure that the Host CPU cache doesn't contain any dirty 857 * cache lines that falls in the rirb. If I understood correctly, it 858 * should be sufficient to do this only once as the rirb is purely 859 * read-only from now on. 860 */ 861 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 862 BUS_DMASYNC_PREREAD); 863#endif 864} 865 866/**************************************************************************** 867 * void hdac_corb_start(hdac_softc *) 868 * 869 * Startup the corb DMA engine 870 ****************************************************************************/ 871static void 872hdac_corb_start(struct hdac_softc *sc) 873{ 874 uint32_t corbctl; 875 876 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 877 corbctl |= HDAC_CORBCTL_CORBRUN; 878 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 879} 880 881/**************************************************************************** 882 * void hdac_rirb_start(hdac_softc *) 883 * 884 * Startup the rirb DMA engine 885 ****************************************************************************/ 886static void 887hdac_rirb_start(struct hdac_softc *sc) 888{ 889 uint32_t rirbctl; 890 891 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 892 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 893 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 894} 895 896static int 897hdac_rirb_flush(struct hdac_softc *sc) 898{ 899 struct hdac_rirb *rirb_base, *rirb; 900 nid_t cad; 901 uint32_t resp; 902 uint8_t rirbwp; 903 int ret; 904 905 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 906 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 907#if 0 908 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 909 BUS_DMASYNC_POSTREAD); 910#endif 911 912 ret = 0; 913 while (sc->rirb_rp != rirbwp) { 914 sc->rirb_rp++; 915 sc->rirb_rp %= sc->rirb_size; 916 rirb = &rirb_base[sc->rirb_rp]; 917 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 918 resp = rirb->response; 919 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 920 sc->unsolq[sc->unsolq_wp++] = resp; 921 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 922 sc->unsolq[sc->unsolq_wp++] = cad; 923 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 924 } else if (sc->codecs[cad].pending <= 0) { 925 device_printf(sc->dev, "Unexpected unsolicited " 926 "response from address %d: %08x\n", cad, resp); 927 } else { 928 sc->codecs[cad].response = resp; 929 sc->codecs[cad].pending--; 930 } 931 ret++; 932 } 933 return (ret); 934} 935 936static int 937hdac_unsolq_flush(struct hdac_softc *sc) 938{ 939 device_t child; 940 nid_t cad; 941 uint32_t resp; 942 int ret = 0; 943 944 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 945 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 946 while (sc->unsolq_rp != sc->unsolq_wp) { 947 resp = sc->unsolq[sc->unsolq_rp++]; 948 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 949 cad = sc->unsolq[sc->unsolq_rp++]; 950 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 951 if ((child = sc->codecs[cad].dev) != NULL) 952 HDAC_UNSOL_INTR(child, resp); 953 ret++; 954 } 955 sc->unsolq_st = HDAC_UNSOLQ_READY; 956 } 957 958 return (ret); 959} 960 961/**************************************************************************** 962 * uint32_t hdac_command_sendone_internal 963 * 964 * Wrapper function that sends only one command to a given codec 965 ****************************************************************************/ 966static uint32_t 967hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 968{ 969 int timeout; 970 uint32_t *corb; 971 972 if (!hdac_lockowned(sc)) 973 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 974 verb &= ~HDA_CMD_CAD_MASK; 975 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 976 sc->codecs[cad].response = HDA_INVALID; 977 978 sc->codecs[cad].pending++; 979 sc->corb_wp++; 980 sc->corb_wp %= sc->corb_size; 981 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 982#if 0 983 bus_dmamap_sync(sc->corb_dma.dma_tag, 984 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 985#endif 986 corb[sc->corb_wp] = verb; 987#if 0 988 bus_dmamap_sync(sc->corb_dma.dma_tag, 989 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 990#endif 991 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 992 993 timeout = 10000; 994 do { 995 if (hdac_rirb_flush(sc) == 0) 996 DELAY(10); 997 } while (sc->codecs[cad].pending != 0 && --timeout); 998 999 if (sc->codecs[cad].pending != 0) { 1000 device_printf(sc->dev, "Command timeout on address %d\n", cad); 1001 sc->codecs[cad].pending = 0; 1002 } 1003 1004 if (sc->unsolq_rp != sc->unsolq_wp) 1005 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1006 return (sc->codecs[cad].response); 1007} 1008 1009/**************************************************************************** 1010 * Device Methods 1011 ****************************************************************************/ 1012 1013/**************************************************************************** 1014 * int hdac_probe(device_t) 1015 * 1016 * Probe for the presence of an hdac. If none is found, check for a generic 1017 * match using the subclass of the device. 1018 ****************************************************************************/ 1019static int 1020hdac_probe(device_t dev) 1021{ 1022 int i, result; 1023 uint32_t model; 1024 uint16_t class, subclass; 1025 char desc[64]; 1026 1027 model = (uint32_t)pci_get_device(dev) << 16; 1028 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1029 class = pci_get_class(dev); 1030 subclass = pci_get_subclass(dev); 1031 1032 bzero(desc, sizeof(desc)); 1033 result = ENXIO; 1034 for (i = 0; i < nitems(hdac_devices); i++) { 1035 if (hdac_devices[i].model == model) { 1036 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1037 result = BUS_PROBE_DEFAULT; 1038 break; 1039 } 1040 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1041 class == PCIC_MULTIMEDIA && 1042 subclass == PCIS_MULTIMEDIA_HDA) { 1043 snprintf(desc, sizeof(desc), 1044 "%s (0x%04x)", 1045 hdac_devices[i].desc, pci_get_device(dev)); 1046 result = BUS_PROBE_GENERIC; 1047 break; 1048 } 1049 } 1050 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1051 subclass == PCIS_MULTIMEDIA_HDA) { 1052 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1053 result = BUS_PROBE_GENERIC; 1054 } 1055 if (result != ENXIO) { 1056 strlcat(desc, " HDA Controller", sizeof(desc)); 1057 device_set_desc_copy(dev, desc); 1058 } 1059 1060 return (result); 1061} 1062 1063static void 1064hdac_unsolq_task(void *context, int pending) 1065{ 1066 struct hdac_softc *sc; 1067 1068 sc = (struct hdac_softc *)context; 1069 1070 hdac_lock(sc); 1071 hdac_unsolq_flush(sc); 1072 hdac_unlock(sc); 1073} 1074 1075/**************************************************************************** 1076 * int hdac_attach(device_t) 1077 * 1078 * Attach the device into the kernel. Interrupts usually won't be enabled 1079 * when this function is called. Setup everything that doesn't require 1080 * interrupts and defer probing of codecs until interrupts are enabled. 1081 ****************************************************************************/ 1082static int 1083hdac_attach(device_t dev) 1084{ 1085 struct hdac_softc *sc; 1086 int result; 1087 int i, devid = -1; 1088 uint32_t model; 1089 uint16_t class, subclass; 1090 uint16_t vendor; 1091 uint8_t v; 1092 1093 sc = device_get_softc(dev); 1094 HDA_BOOTVERBOSE( 1095 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1096 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1097 device_printf(dev, "HDA Driver Revision: %s\n", 1098 HDA_DRV_TEST_REV); 1099 ); 1100 1101 model = (uint32_t)pci_get_device(dev) << 16; 1102 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1103 class = pci_get_class(dev); 1104 subclass = pci_get_subclass(dev); 1105 1106 for (i = 0; i < nitems(hdac_devices); i++) { 1107 if (hdac_devices[i].model == model) { 1108 devid = i; 1109 break; 1110 } 1111 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1112 class == PCIC_MULTIMEDIA && 1113 subclass == PCIS_MULTIMEDIA_HDA) { 1114 devid = i; 1115 break; 1116 } 1117 } 1118 1119 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1120 sc->dev = dev; 1121 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1122 callout_init(&sc->poll_callout, 1); 1123 for (i = 0; i < HDAC_CODEC_MAX; i++) 1124 sc->codecs[i].dev = NULL; 1125 if (devid >= 0) { 1126 sc->quirks_on = hdac_devices[devid].quirks_on; 1127 sc->quirks_off = hdac_devices[devid].quirks_off; 1128 } else { 1129 sc->quirks_on = 0; 1130 sc->quirks_off = 0; 1131 } 1132 if (resource_int_value(device_get_name(dev), 1133 device_get_unit(dev), "msi", &i) == 0) { 1134 if (i == 0) 1135 sc->quirks_off |= HDAC_QUIRK_MSI; 1136 else { 1137 sc->quirks_on |= HDAC_QUIRK_MSI; 1138 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1139 } 1140 } 1141 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1142 HDA_BOOTVERBOSE( 1143 device_printf(sc->dev, 1144 "Config options: on=0x%08x off=0x%08x\n", 1145 sc->quirks_on, sc->quirks_off); 1146 ); 1147 sc->poll_ival = hz; 1148 if (resource_int_value(device_get_name(dev), 1149 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1150 sc->polling = 1; 1151 else 1152 sc->polling = 0; 1153 1154 pci_enable_busmaster(dev); 1155 1156 vendor = pci_get_vendor(dev); 1157 if (vendor == INTEL_VENDORID) { 1158 /* TCSEL -> TC0 */ 1159 v = pci_read_config(dev, 0x44, 1); 1160 pci_write_config(dev, 0x44, v & 0xf8, 1); 1161 HDA_BOOTHVERBOSE( 1162 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1163 pci_read_config(dev, 0x44, 1)); 1164 ); 1165 } 1166 1167#if defined(__i386__) || defined(__amd64__) 1168 sc->flags |= HDAC_F_DMA_NOCACHE; 1169 1170 if (resource_int_value(device_get_name(dev), 1171 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1172#else 1173 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1174#endif 1175 /* 1176 * Try to enable PCIe snoop to avoid messing around with 1177 * uncacheable DMA attribute. Since PCIe snoop register 1178 * config is pretty much vendor specific, there are no 1179 * general solutions on how to enable it, forcing us (even 1180 * Microsoft) to enable uncacheable or write combined DMA 1181 * by default. 1182 * 1183 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1184 */ 1185 for (i = 0; i < nitems(hdac_pcie_snoop); i++) { 1186 if (hdac_pcie_snoop[i].vendor != vendor) 1187 continue; 1188 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1189 if (hdac_pcie_snoop[i].reg == 0x00) 1190 break; 1191 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1192 if ((v & hdac_pcie_snoop[i].enable) == 1193 hdac_pcie_snoop[i].enable) 1194 break; 1195 v &= hdac_pcie_snoop[i].mask; 1196 v |= hdac_pcie_snoop[i].enable; 1197 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1198 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1199 if ((v & hdac_pcie_snoop[i].enable) != 1200 hdac_pcie_snoop[i].enable) { 1201 HDA_BOOTVERBOSE( 1202 device_printf(dev, 1203 "WARNING: Failed to enable PCIe " 1204 "snoop!\n"); 1205 ); 1206#if defined(__i386__) || defined(__amd64__) 1207 sc->flags |= HDAC_F_DMA_NOCACHE; 1208#endif 1209 } 1210 break; 1211 } 1212#if defined(__i386__) || defined(__amd64__) 1213 } 1214#endif 1215 1216 HDA_BOOTHVERBOSE( 1217 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1218 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1219 "Uncacheable" : "PCIe snoop", vendor); 1220 ); 1221 1222 /* Allocate resources */ 1223 result = hdac_mem_alloc(sc); 1224 if (result != 0) 1225 goto hdac_attach_fail; 1226 result = hdac_irq_alloc(sc); 1227 if (result != 0) 1228 goto hdac_attach_fail; 1229 1230 /* Get Capabilities */ 1231 result = hdac_get_capabilities(sc); 1232 if (result != 0) 1233 goto hdac_attach_fail; 1234 1235 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1236 result = hdac_dma_alloc(sc, &sc->corb_dma, 1237 sc->corb_size * sizeof(uint32_t)); 1238 if (result != 0) 1239 goto hdac_attach_fail; 1240 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1241 sc->rirb_size * sizeof(struct hdac_rirb)); 1242 if (result != 0) 1243 goto hdac_attach_fail; 1244 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1245 M_HDAC, M_ZERO | M_WAITOK); 1246 for (i = 0; i < sc->num_ss; i++) { 1247 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1248 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1249 if (result != 0) 1250 goto hdac_attach_fail; 1251 } 1252 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1253 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1254 HDA_BOOTVERBOSE( 1255 device_printf(dev, "Failed to " 1256 "allocate DMA pos buffer " 1257 "(non-fatal)\n"); 1258 ); 1259 } else { 1260 uint64_t addr = sc->pos_dma.dma_paddr; 1261 1262 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1263 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1264 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1265 HDAC_DPLBASE_DPLBASE_DMAPBE); 1266 } 1267 } 1268 1269 result = bus_dma_tag_create( 1270 bus_get_dma_tag(sc->dev), /* parent */ 1271 HDA_DMA_ALIGNMENT, /* alignment */ 1272 0, /* boundary */ 1273 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1274 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1275 BUS_SPACE_MAXADDR, /* highaddr */ 1276 NULL, /* filtfunc */ 1277 NULL, /* fistfuncarg */ 1278 HDA_BUFSZ_MAX, /* maxsize */ 1279 1, /* nsegments */ 1280 HDA_BUFSZ_MAX, /* maxsegsz */ 1281 0, /* flags */ 1282 NULL, /* lockfunc */ 1283 NULL, /* lockfuncarg */ 1284 &sc->chan_dmat); /* dmat */ 1285 if (result != 0) { 1286 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1287 __func__, result); 1288 goto hdac_attach_fail; 1289 } 1290 1291 /* Quiesce everything */ 1292 HDA_BOOTHVERBOSE( 1293 device_printf(dev, "Reset controller...\n"); 1294 ); 1295 hdac_reset(sc, 1); 1296 1297 /* Initialize the CORB and RIRB */ 1298 hdac_corb_init(sc); 1299 hdac_rirb_init(sc); 1300 1301 /* Defer remaining of initialization until interrupts are enabled */ 1302 sc->intrhook.ich_func = hdac_attach2; 1303 sc->intrhook.ich_arg = (void *)sc; 1304 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1305 sc->intrhook.ich_func = NULL; 1306 hdac_attach2((void *)sc); 1307 } 1308 1309 return (0); 1310 1311hdac_attach_fail: 1312 hdac_irq_free(sc); 1313 for (i = 0; i < sc->num_ss; i++) 1314 hdac_dma_free(sc, &sc->streams[i].bdl); 1315 free(sc->streams, M_HDAC); 1316 hdac_dma_free(sc, &sc->rirb_dma); 1317 hdac_dma_free(sc, &sc->corb_dma); 1318 hdac_mem_free(sc); 1319 snd_mtxfree(sc->lock); 1320 1321 return (ENXIO); 1322} 1323 1324static int 1325sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1326{ 1327 struct hdac_softc *sc; 1328 device_t *devlist; 1329 device_t dev; 1330 int devcount, i, err, val; 1331 1332 dev = oidp->oid_arg1; 1333 sc = device_get_softc(dev); 1334 if (sc == NULL) 1335 return (EINVAL); 1336 val = 0; 1337 err = sysctl_handle_int(oidp, &val, 0, req); 1338 if (err != 0 || req->newptr == NULL || val == 0) 1339 return (err); 1340 1341 /* XXX: Temporary. For debugging. */ 1342 if (val == 100) { 1343 hdac_suspend(dev); 1344 return (0); 1345 } else if (val == 101) { 1346 hdac_resume(dev); 1347 return (0); 1348 } 1349 1350 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1351 return (err); 1352 hdac_lock(sc); 1353 for (i = 0; i < devcount; i++) 1354 HDAC_PINDUMP(devlist[i]); 1355 hdac_unlock(sc); 1356 free(devlist, M_TEMP); 1357 return (0); 1358} 1359 1360static int 1361hdac_mdata_rate(uint16_t fmt) 1362{ 1363 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1364 int rate, bits; 1365 1366 if (fmt & (1 << 14)) 1367 rate = 44100; 1368 else 1369 rate = 48000; 1370 rate *= ((fmt >> 11) & 0x07) + 1; 1371 rate /= ((fmt >> 8) & 0x07) + 1; 1372 bits = mbits[(fmt >> 4) & 0x03]; 1373 bits *= (fmt & 0x0f) + 1; 1374 return (rate * bits); 1375} 1376 1377static int 1378hdac_bdata_rate(uint16_t fmt, int output) 1379{ 1380 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1381 int rate, bits; 1382 1383 rate = 48000; 1384 rate *= ((fmt >> 11) & 0x07) + 1; 1385 bits = bbits[(fmt >> 4) & 0x03]; 1386 bits *= (fmt & 0x0f) + 1; 1387 if (!output) 1388 bits = ((bits + 7) & ~0x07) + 10; 1389 return (rate * bits); 1390} 1391 1392static void 1393hdac_poll_reinit(struct hdac_softc *sc) 1394{ 1395 int i, pollticks, min = 1000000; 1396 struct hdac_stream *s; 1397 1398 if (sc->polling == 0) 1399 return; 1400 if (sc->unsol_registered > 0) 1401 min = hz / 2; 1402 for (i = 0; i < sc->num_ss; i++) { 1403 s = &sc->streams[i]; 1404 if (s->running == 0) 1405 continue; 1406 pollticks = ((uint64_t)hz * s->blksz) / 1407 (hdac_mdata_rate(s->format) / 8); 1408 pollticks >>= 1; 1409 if (pollticks > hz) 1410 pollticks = hz; 1411 if (pollticks < 1) { 1412 HDA_BOOTVERBOSE( 1413 device_printf(sc->dev, 1414 "poll interval < 1 tick !\n"); 1415 ); 1416 pollticks = 1; 1417 } 1418 if (min > pollticks) 1419 min = pollticks; 1420 } 1421 HDA_BOOTVERBOSE( 1422 device_printf(sc->dev, 1423 "poll interval %d -> %d ticks\n", 1424 sc->poll_ival, min); 1425 ); 1426 sc->poll_ival = min; 1427 if (min == 1000000) 1428 callout_stop(&sc->poll_callout); 1429 else 1430 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1431} 1432 1433static int 1434sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1435{ 1436 struct hdac_softc *sc; 1437 device_t dev; 1438 uint32_t ctl; 1439 int err, val; 1440 1441 dev = oidp->oid_arg1; 1442 sc = device_get_softc(dev); 1443 if (sc == NULL) 1444 return (EINVAL); 1445 hdac_lock(sc); 1446 val = sc->polling; 1447 hdac_unlock(sc); 1448 err = sysctl_handle_int(oidp, &val, 0, req); 1449 1450 if (err != 0 || req->newptr == NULL) 1451 return (err); 1452 if (val < 0 || val > 1) 1453 return (EINVAL); 1454 1455 hdac_lock(sc); 1456 if (val != sc->polling) { 1457 if (val == 0) { 1458 callout_stop(&sc->poll_callout); 1459 hdac_unlock(sc); 1460 callout_drain(&sc->poll_callout); 1461 hdac_lock(sc); 1462 sc->polling = 0; 1463 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1464 ctl |= HDAC_INTCTL_GIE; 1465 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1466 } else { 1467 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1468 ctl &= ~HDAC_INTCTL_GIE; 1469 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1470 sc->polling = 1; 1471 hdac_poll_reinit(sc); 1472 } 1473 } 1474 hdac_unlock(sc); 1475 1476 return (err); 1477} 1478 1479static void 1480hdac_attach2(void *arg) 1481{ 1482 struct hdac_softc *sc; 1483 device_t child; 1484 uint32_t vendorid, revisionid; 1485 int i; 1486 uint16_t statests; 1487 1488 sc = (struct hdac_softc *)arg; 1489 1490 hdac_lock(sc); 1491 1492 /* Remove ourselves from the config hooks */ 1493 if (sc->intrhook.ich_func != NULL) { 1494 config_intrhook_disestablish(&sc->intrhook); 1495 sc->intrhook.ich_func = NULL; 1496 } 1497 1498 HDA_BOOTHVERBOSE( 1499 device_printf(sc->dev, "Starting CORB Engine...\n"); 1500 ); 1501 hdac_corb_start(sc); 1502 HDA_BOOTHVERBOSE( 1503 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1504 ); 1505 hdac_rirb_start(sc); 1506 HDA_BOOTHVERBOSE( 1507 device_printf(sc->dev, 1508 "Enabling controller interrupt...\n"); 1509 ); 1510 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1511 HDAC_GCTL_UNSOL); 1512 if (sc->polling == 0) { 1513 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1514 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1515 } 1516 DELAY(1000); 1517 1518 HDA_BOOTHVERBOSE( 1519 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1520 ); 1521 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1522 hdac_unlock(sc); 1523 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1524 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1525 HDA_BOOTHVERBOSE( 1526 device_printf(sc->dev, 1527 "Found CODEC at address %d\n", i); 1528 ); 1529 hdac_lock(sc); 1530 vendorid = hdac_send_command(sc, i, 1531 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1532 revisionid = hdac_send_command(sc, i, 1533 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1534 hdac_unlock(sc); 1535 if (vendorid == HDA_INVALID && 1536 revisionid == HDA_INVALID) { 1537 device_printf(sc->dev, 1538 "CODEC is not responding!\n"); 1539 continue; 1540 } 1541 sc->codecs[i].vendor_id = 1542 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1543 sc->codecs[i].device_id = 1544 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1545 sc->codecs[i].revision_id = 1546 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1547 sc->codecs[i].stepping_id = 1548 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1549 child = device_add_child(sc->dev, "hdacc", -1); 1550 if (child == NULL) { 1551 device_printf(sc->dev, 1552 "Failed to add CODEC device\n"); 1553 continue; 1554 } 1555 device_set_ivars(child, (void *)(intptr_t)i); 1556 sc->codecs[i].dev = child; 1557 } 1558 } 1559 bus_generic_attach(sc->dev); 1560 1561 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1562 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1563 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1564 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1565 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1566 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1567 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1568 sysctl_hdac_polling, "I", "Enable polling mode"); 1569} 1570 1571/**************************************************************************** 1572 * int hdac_suspend(device_t) 1573 * 1574 * Suspend and power down HDA bus and codecs. 1575 ****************************************************************************/ 1576static int 1577hdac_suspend(device_t dev) 1578{ 1579 struct hdac_softc *sc = device_get_softc(dev); 1580 1581 HDA_BOOTHVERBOSE( 1582 device_printf(dev, "Suspend...\n"); 1583 ); 1584 bus_generic_suspend(dev); 1585 1586 hdac_lock(sc); 1587 HDA_BOOTHVERBOSE( 1588 device_printf(dev, "Reset controller...\n"); 1589 ); 1590 callout_stop(&sc->poll_callout); 1591 hdac_reset(sc, 0); 1592 hdac_unlock(sc); 1593 callout_drain(&sc->poll_callout); 1594 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1595 HDA_BOOTHVERBOSE( 1596 device_printf(dev, "Suspend done\n"); 1597 ); 1598 return (0); 1599} 1600 1601/**************************************************************************** 1602 * int hdac_resume(device_t) 1603 * 1604 * Powerup and restore HDA bus and codecs state. 1605 ****************************************************************************/ 1606static int 1607hdac_resume(device_t dev) 1608{ 1609 struct hdac_softc *sc = device_get_softc(dev); 1610 int error; 1611 1612 HDA_BOOTHVERBOSE( 1613 device_printf(dev, "Resume...\n"); 1614 ); 1615 hdac_lock(sc); 1616 1617 /* Quiesce everything */ 1618 HDA_BOOTHVERBOSE( 1619 device_printf(dev, "Reset controller...\n"); 1620 ); 1621 hdac_reset(sc, 1); 1622 1623 /* Initialize the CORB and RIRB */ 1624 hdac_corb_init(sc); 1625 hdac_rirb_init(sc); 1626 1627 HDA_BOOTHVERBOSE( 1628 device_printf(dev, "Starting CORB Engine...\n"); 1629 ); 1630 hdac_corb_start(sc); 1631 HDA_BOOTHVERBOSE( 1632 device_printf(dev, "Starting RIRB Engine...\n"); 1633 ); 1634 hdac_rirb_start(sc); 1635 HDA_BOOTHVERBOSE( 1636 device_printf(dev, "Enabling controller interrupt...\n"); 1637 ); 1638 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1639 HDAC_GCTL_UNSOL); 1640 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1641 DELAY(1000); 1642 hdac_poll_reinit(sc); 1643 hdac_unlock(sc); 1644 1645 error = bus_generic_resume(dev); 1646 HDA_BOOTHVERBOSE( 1647 device_printf(dev, "Resume done\n"); 1648 ); 1649 return (error); 1650} 1651 1652/**************************************************************************** 1653 * int hdac_detach(device_t) 1654 * 1655 * Detach and free up resources utilized by the hdac device. 1656 ****************************************************************************/ 1657static int 1658hdac_detach(device_t dev) 1659{ 1660 struct hdac_softc *sc = device_get_softc(dev); 1661 device_t *devlist; 1662 int cad, i, devcount, error; 1663 1664 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1665 return (error); 1666 for (i = 0; i < devcount; i++) { 1667 cad = (intptr_t)device_get_ivars(devlist[i]); 1668 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1669 free(devlist, M_TEMP); 1670 return (error); 1671 } 1672 sc->codecs[cad].dev = NULL; 1673 } 1674 free(devlist, M_TEMP); 1675 1676 hdac_lock(sc); 1677 hdac_reset(sc, 0); 1678 hdac_unlock(sc); 1679 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1680 hdac_irq_free(sc); 1681 1682 for (i = 0; i < sc->num_ss; i++) 1683 hdac_dma_free(sc, &sc->streams[i].bdl); 1684 free(sc->streams, M_HDAC); 1685 hdac_dma_free(sc, &sc->pos_dma); 1686 hdac_dma_free(sc, &sc->rirb_dma); 1687 hdac_dma_free(sc, &sc->corb_dma); 1688 if (sc->chan_dmat != NULL) { 1689 bus_dma_tag_destroy(sc->chan_dmat); 1690 sc->chan_dmat = NULL; 1691 } 1692 hdac_mem_free(sc); 1693 snd_mtxfree(sc->lock); 1694 return (0); 1695} 1696 1697static bus_dma_tag_t 1698hdac_get_dma_tag(device_t dev, device_t child) 1699{ 1700 struct hdac_softc *sc = device_get_softc(dev); 1701 1702 return (sc->chan_dmat); 1703} 1704 1705static int 1706hdac_print_child(device_t dev, device_t child) 1707{ 1708 int retval; 1709 1710 retval = bus_print_child_header(dev, child); 1711 retval += printf(" at cad %d", 1712 (int)(intptr_t)device_get_ivars(child)); 1713 retval += bus_print_child_footer(dev, child); 1714 1715 return (retval); 1716} 1717 1718static int 1719hdac_child_location_str(device_t dev, device_t child, char *buf, 1720 size_t buflen) 1721{ 1722 1723 snprintf(buf, buflen, "cad=%d", 1724 (int)(intptr_t)device_get_ivars(child)); 1725 return (0); 1726} 1727 1728static int 1729hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1730 size_t buflen) 1731{ 1732 struct hdac_softc *sc = device_get_softc(dev); 1733 nid_t cad = (uintptr_t)device_get_ivars(child); 1734 1735 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1736 "stepping=0x%02x", 1737 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1738 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1739 return (0); 1740} 1741 1742static int 1743hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1744{ 1745 struct hdac_softc *sc = device_get_softc(dev); 1746 nid_t cad = (uintptr_t)device_get_ivars(child); 1747 1748 switch (which) { 1749 case HDA_IVAR_CODEC_ID: 1750 *result = cad; 1751 break; 1752 case HDA_IVAR_VENDOR_ID: 1753 *result = sc->codecs[cad].vendor_id; 1754 break; 1755 case HDA_IVAR_DEVICE_ID: 1756 *result = sc->codecs[cad].device_id; 1757 break; 1758 case HDA_IVAR_REVISION_ID: 1759 *result = sc->codecs[cad].revision_id; 1760 break; 1761 case HDA_IVAR_STEPPING_ID: 1762 *result = sc->codecs[cad].stepping_id; 1763 break; 1764 case HDA_IVAR_SUBVENDOR_ID: 1765 *result = pci_get_subvendor(dev); 1766 break; 1767 case HDA_IVAR_SUBDEVICE_ID: 1768 *result = pci_get_subdevice(dev); 1769 break; 1770 case HDA_IVAR_DMA_NOCACHE: 1771 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1772 break; 1773 case HDA_IVAR_STRIPES_MASK: 1774 *result = (1 << (1 << sc->num_sdo)) - 1; 1775 break; 1776 default: 1777 return (ENOENT); 1778 } 1779 return (0); 1780} 1781 1782static struct mtx * 1783hdac_get_mtx(device_t dev, device_t child) 1784{ 1785 struct hdac_softc *sc = device_get_softc(dev); 1786 1787 return (sc->lock); 1788} 1789 1790static uint32_t 1791hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1792{ 1793 1794 return (hdac_send_command(device_get_softc(dev), 1795 (intptr_t)device_get_ivars(child), verb)); 1796} 1797 1798static int 1799hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1800{ 1801 int i, ss; 1802 1803 ss = -1; 1804 /* Allocate ISS/OSS first. */ 1805 if (dir == 0) { 1806 for (i = 0; i < sc->num_iss; i++) { 1807 if (sc->streams[i].stream == stream) { 1808 ss = i; 1809 break; 1810 } 1811 } 1812 } else { 1813 for (i = 0; i < sc->num_oss; i++) { 1814 if (sc->streams[i + sc->num_iss].stream == stream) { 1815 ss = i + sc->num_iss; 1816 break; 1817 } 1818 } 1819 } 1820 /* Fallback to BSS. */ 1821 if (ss == -1) { 1822 for (i = 0; i < sc->num_bss; i++) { 1823 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1824 == stream) { 1825 ss = i + sc->num_iss + sc->num_oss; 1826 break; 1827 } 1828 } 1829 } 1830 return (ss); 1831} 1832 1833static int 1834hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1835 uint32_t **dmapos) 1836{ 1837 struct hdac_softc *sc = device_get_softc(dev); 1838 nid_t cad = (uintptr_t)device_get_ivars(child); 1839 int stream, ss, bw, maxbw, prevbw; 1840 1841 /* Look for empty stream. */ 1842 ss = hdac_find_stream(sc, dir, 0); 1843 1844 /* Return if found nothing. */ 1845 if (ss < 0) 1846 return (0); 1847 1848 /* Check bus bandwidth. */ 1849 bw = hdac_bdata_rate(format, dir); 1850 if (dir == 1) { 1851 bw *= 1 << (sc->num_sdo - stripe); 1852 prevbw = sc->sdo_bw_used; 1853 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1854 } else { 1855 prevbw = sc->codecs[cad].sdi_bw_used; 1856 maxbw = 48000 * 464; 1857 } 1858 HDA_BOOTHVERBOSE( 1859 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1860 (bw + prevbw) / 1000, maxbw / 1000, 1861 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1862 ); 1863 if (bw + prevbw > maxbw) 1864 return (0); 1865 if (dir == 1) 1866 sc->sdo_bw_used += bw; 1867 else 1868 sc->codecs[cad].sdi_bw_used += bw; 1869 1870 /* Allocate stream number */ 1871 if (ss >= sc->num_iss + sc->num_oss) 1872 stream = 15 - (ss - sc->num_iss - sc->num_oss); 1873 else if (ss >= sc->num_iss) 1874 stream = ss - sc->num_iss + 1; 1875 else 1876 stream = ss + 1; 1877 1878 sc->streams[ss].dev = child; 1879 sc->streams[ss].dir = dir; 1880 sc->streams[ss].stream = stream; 1881 sc->streams[ss].bw = bw; 1882 sc->streams[ss].format = format; 1883 sc->streams[ss].stripe = stripe; 1884 if (dmapos != NULL) { 1885 if (sc->pos_dma.dma_vaddr != NULL) 1886 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1887 else 1888 *dmapos = NULL; 1889 } 1890 return (stream); 1891} 1892 1893static void 1894hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1895{ 1896 struct hdac_softc *sc = device_get_softc(dev); 1897 nid_t cad = (uintptr_t)device_get_ivars(child); 1898 int ss; 1899 1900 ss = hdac_find_stream(sc, dir, stream); 1901 KASSERT(ss >= 0, 1902 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1903 if (dir == 1) 1904 sc->sdo_bw_used -= sc->streams[ss].bw; 1905 else 1906 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1907 sc->streams[ss].stream = 0; 1908 sc->streams[ss].dev = NULL; 1909} 1910 1911static int 1912hdac_stream_start(device_t dev, device_t child, 1913 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1914{ 1915 struct hdac_softc *sc = device_get_softc(dev); 1916 struct hdac_bdle *bdle; 1917 uint64_t addr; 1918 int i, ss, off; 1919 uint32_t ctl; 1920 1921 ss = hdac_find_stream(sc, dir, stream); 1922 KASSERT(ss >= 0, 1923 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1924 1925 addr = (uint64_t)buf; 1926 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1927 for (i = 0; i < blkcnt; i++, bdle++) { 1928 bdle->addrl = (uint32_t)addr; 1929 bdle->addrh = (uint32_t)(addr >> 32); 1930 bdle->len = blksz; 1931 bdle->ioc = 1; 1932 addr += blksz; 1933 } 1934 1935 off = ss << 5; 1936 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1937 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1938 addr = sc->streams[ss].bdl.dma_paddr; 1939 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1940 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1941 1942 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1943 if (dir) 1944 ctl |= HDAC_SDCTL2_DIR; 1945 else 1946 ctl &= ~HDAC_SDCTL2_DIR; 1947 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1948 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1949 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1950 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1951 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1952 1953 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1954 1955 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1956 ctl |= 1 << ss; 1957 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1958 1959 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1960 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1961 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1962 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1963 HDAC_SDCTL_RUN; 1964 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1965 1966 sc->streams[ss].blksz = blksz; 1967 sc->streams[ss].running = 1; 1968 hdac_poll_reinit(sc); 1969 return (0); 1970} 1971 1972static void 1973hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1974{ 1975 struct hdac_softc *sc = device_get_softc(dev); 1976 int ss, off; 1977 uint32_t ctl; 1978 1979 ss = hdac_find_stream(sc, dir, stream); 1980 KASSERT(ss >= 0, 1981 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1982 1983 off = ss << 5; 1984 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1985 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1986 HDAC_SDCTL_RUN); 1987 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1988 1989 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1990 ctl &= ~(1 << ss); 1991 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1992 1993 sc->streams[ss].running = 0; 1994 hdac_poll_reinit(sc); 1995} 1996 1997static void 1998hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1999{ 2000 struct hdac_softc *sc = device_get_softc(dev); 2001 int timeout = 1000; 2002 int to = timeout; 2003 int ss, off; 2004 uint32_t ctl; 2005 2006 ss = hdac_find_stream(sc, dir, stream); 2007 KASSERT(ss >= 0, 2008 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2009 2010 off = ss << 5; 2011 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2012 ctl |= HDAC_SDCTL_SRST; 2013 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2014 do { 2015 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2016 if (ctl & HDAC_SDCTL_SRST) 2017 break; 2018 DELAY(10); 2019 } while (--to); 2020 if (!(ctl & HDAC_SDCTL_SRST)) 2021 device_printf(dev, "Reset setting timeout\n"); 2022 ctl &= ~HDAC_SDCTL_SRST; 2023 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2024 to = timeout; 2025 do { 2026 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2027 if (!(ctl & HDAC_SDCTL_SRST)) 2028 break; 2029 DELAY(10); 2030 } while (--to); 2031 if (ctl & HDAC_SDCTL_SRST) 2032 device_printf(dev, "Reset timeout!\n"); 2033} 2034 2035static uint32_t 2036hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2037{ 2038 struct hdac_softc *sc = device_get_softc(dev); 2039 int ss, off; 2040 2041 ss = hdac_find_stream(sc, dir, stream); 2042 KASSERT(ss >= 0, 2043 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2044 2045 off = ss << 5; 2046 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2047} 2048 2049static int 2050hdac_unsol_alloc(device_t dev, device_t child, int tag) 2051{ 2052 struct hdac_softc *sc = device_get_softc(dev); 2053 2054 sc->unsol_registered++; 2055 hdac_poll_reinit(sc); 2056 return (tag); 2057} 2058 2059static void 2060hdac_unsol_free(device_t dev, device_t child, int tag) 2061{ 2062 struct hdac_softc *sc = device_get_softc(dev); 2063 2064 sc->unsol_registered--; 2065 hdac_poll_reinit(sc); 2066} 2067 2068static device_method_t hdac_methods[] = { 2069 /* device interface */ 2070 DEVMETHOD(device_probe, hdac_probe), 2071 DEVMETHOD(device_attach, hdac_attach), 2072 DEVMETHOD(device_detach, hdac_detach), 2073 DEVMETHOD(device_suspend, hdac_suspend), 2074 DEVMETHOD(device_resume, hdac_resume), 2075 /* Bus interface */ 2076 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2077 DEVMETHOD(bus_print_child, hdac_print_child), 2078 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2079 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2080 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2081 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2082 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2083 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2084 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2085 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2086 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2087 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2088 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2089 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2090 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2091 DEVMETHOD_END 2092}; 2093 2094static driver_t hdac_driver = { 2095 "hdac", 2096 hdac_methods, 2097 sizeof(struct hdac_softc), 2098}; 2099 2100static devclass_t hdac_devclass; 2101 2102DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2103