hdac.c revision 197611
1156230Smux/*- 2156230Smux * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3156230Smux * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4156230Smux * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5156230Smux * All rights reserved. 6156230Smux * 7156230Smux * Redistribution and use in source and binary forms, with or without 8156230Smux * modification, are permitted provided that the following conditions 9156230Smux * are met: 10156230Smux * 1. Redistributions of source code must retain the above copyright 11156230Smux * notice, this list of conditions and the following disclaimer. 12156230Smux * 2. Redistributions in binary form must reproduce the above copyright 13156230Smux * notice, this list of conditions and the following disclaimer in the 14156230Smux * documentation and/or other materials provided with the distribution. 15156230Smux * 16156230Smux * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17156230Smux * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18156230Smux * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19156230Smux * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20156230Smux * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21156230Smux * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22156230Smux * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23156230Smux * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24156230Smux * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25156230Smux * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26156230Smux * SUCH DAMAGE. 27156230Smux */ 28156230Smux 29156230Smux/* 30156230Smux * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31156230Smux * that this driver still in its early stage, and possible of rewrite are 32156230Smux * pretty much guaranteed. There are supposedly several distinct parent/child 33156230Smux * busses to make this "perfect", but as for now and for the sake of 34156230Smux * simplicity, everything is gobble up within single source. 35156230Smux * 36156230Smux * List of subsys: 37156230Smux * 1) HDA Controller support 38156230Smux * 2) HDA Codecs support, which may include 39156230Smux * - HDA 40156230Smux * - Modem 41156230Smux * 3) Widget parser - the real magic of why this driver works on so 42156230Smux * many hardwares with minimal vendor specific quirk. The original 43156230Smux * parser was written using Ruby and can be found at 44156230Smux * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45156230Smux * ruby parser take the verbose dmesg dump as its input. Refer to 46156230Smux * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47156230Smux * interesting documents, especially UAA (Universal Audio Architecture). 48186781Slulf * 4) Possible vendor specific support. 49186781Slulf * (snd_hda_intel, snd_hda_ati, etc..) 50186781Slulf * 51156230Smux * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52156230Smux * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20090929_0137" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 197611 2009-09-29 09:36:38Z mav $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 144#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 145#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 146#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 147#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 148#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 149#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 150#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153 154/* Nvidia */ 155#define NVIDIA_VENDORID 0x10de 156#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 175#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 176#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 177#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 178#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 179 180/* ATI */ 181#define ATI_VENDORID 0x1002 182#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 183#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 184#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 185#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 186#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 187#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 188#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 189#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 190#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 191#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 192#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 193#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 194#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 195#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 196#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 197#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 198 199/* VIA */ 200#define VIA_VENDORID 0x1106 201#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 202#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 203 204/* SiS */ 205#define SIS_VENDORID 0x1039 206#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 207#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 208 209/* ULI */ 210#define ULI_VENDORID 0x10b9 211#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 212#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 213 214/* OEM/subvendors */ 215 216/* Intel */ 217#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 218 219/* HP/Compaq */ 220#define HP_VENDORID 0x103c 221#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 222#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 223#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 224#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 225#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 226#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 227#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 228#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 229#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 230#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 231/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 232#define HP_NX6325_SUBVENDORX 0x103c30b0 233 234/* Dell */ 235#define DELL_VENDORID 0x1028 236#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 237#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 238#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 239#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 240#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 241#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 242#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 243#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 244 245/* Clevo */ 246#define CLEVO_VENDORID 0x1558 247#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 248#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 249 250/* Acer */ 251#define ACER_VENDORID 0x1025 252#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 253#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 254#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 255#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 256#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 257#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 258#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 259#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 260 261/* Asus */ 262#define ASUS_VENDORID 0x1043 263#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 264#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 265#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 267#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 268#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 269#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 270#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 271#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 272#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 273#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 274#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 276#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 277#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 278#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 279#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 280 281/* IBM / Lenovo */ 282#define IBM_VENDORID 0x1014 283#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 284#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 285 286/* Lenovo */ 287#define LENOVO_VENDORID 0x17aa 288#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 289#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 290#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 291#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 292 293/* Samsung */ 294#define SAMSUNG_VENDORID 0x144d 295#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 296#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 297 298/* Medion ? */ 299#define MEDION_VENDORID 0x161f 300#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 301#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 302 303/* Apple Computer Inc. */ 304#define APPLE_VENDORID 0x106b 305#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 306 307/* Sony */ 308#define SONY_VENDORID 0x104d 309#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 310#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 311 312/* 313 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 314 * instead of their own, which is beyond my comprehension 315 * (see HDA_CODEC_STAC9221 below). 316 */ 317#define APPLE_INTEL_MAC 0x76808384 318 319/* LG Electronics */ 320#define LG_VENDORID 0x1854 321#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 322#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 323 324/* Fujitsu Siemens */ 325#define FS_VENDORID 0x1734 326#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 327#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 328#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 329 330/* Fujitsu Limited */ 331#define FL_VENDORID 0x10cf 332#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 333#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 334#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 335 336/* Toshiba */ 337#define TOSHIBA_VENDORID 0x1179 338#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 339#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 340#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 341 342/* Micro-Star International (MSI) */ 343#define MSI_VENDORID 0x1462 344#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 345#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 346#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 347 348/* Giga-Byte Technology */ 349#define GB_VENDORID 0x1458 350#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 351#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 352 353/* Uniwill ? */ 354#define UNIWILL_VENDORID 0x1584 355#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 356#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 357 358 359/* Misc constants.. */ 360#define HDA_AMP_VOL_DEFAULT (-1) 361#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 362#define HDA_AMP_MUTE_NONE (0) 363#define HDA_AMP_MUTE_LEFT (1 << 0) 364#define HDA_AMP_MUTE_RIGHT (1 << 1) 365#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 366 367#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 368#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 369 370#define HDA_ADC_MONITOR (1 << 0) 371 372#define HDA_CTL_OUT 1 373#define HDA_CTL_IN 2 374 375#define HDA_GPIO_MAX 8 376/* 0 - 7 = GPIO , 8 = Flush */ 377#define HDA_QUIRK_GPIO0 (1 << 0) 378#define HDA_QUIRK_GPIO1 (1 << 1) 379#define HDA_QUIRK_GPIO2 (1 << 2) 380#define HDA_QUIRK_GPIO3 (1 << 3) 381#define HDA_QUIRK_GPIO4 (1 << 4) 382#define HDA_QUIRK_GPIO5 (1 << 5) 383#define HDA_QUIRK_GPIO6 (1 << 6) 384#define HDA_QUIRK_GPIO7 (1 << 7) 385#define HDA_QUIRK_GPIOFLUSH (1 << 8) 386 387/* 9 - 25 = anything else */ 388#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 389#define HDA_QUIRK_FIXEDRATE (1 << 10) 390#define HDA_QUIRK_FORCESTEREO (1 << 11) 391#define HDA_QUIRK_EAPDINV (1 << 12) 392#define HDA_QUIRK_DMAPOS (1 << 13) 393#define HDA_QUIRK_SENSEINV (1 << 14) 394 395/* 26 - 31 = vrefs */ 396#define HDA_QUIRK_IVREF50 (1 << 26) 397#define HDA_QUIRK_IVREF80 (1 << 27) 398#define HDA_QUIRK_IVREF100 (1 << 28) 399#define HDA_QUIRK_OVREF50 (1 << 29) 400#define HDA_QUIRK_OVREF80 (1 << 30) 401#define HDA_QUIRK_OVREF100 (1 << 31) 402 403#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 404 HDA_QUIRK_IVREF100) 405#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 406 HDA_QUIRK_OVREF100) 407#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 408 409#if __FreeBSD_version < 600000 410#define taskqueue_drain(...) 411#endif 412 413static const struct { 414 char *key; 415 uint32_t value; 416} hdac_quirks_tab[] = { 417 { "gpio0", HDA_QUIRK_GPIO0 }, 418 { "gpio1", HDA_QUIRK_GPIO1 }, 419 { "gpio2", HDA_QUIRK_GPIO2 }, 420 { "gpio3", HDA_QUIRK_GPIO3 }, 421 { "gpio4", HDA_QUIRK_GPIO4 }, 422 { "gpio5", HDA_QUIRK_GPIO5 }, 423 { "gpio6", HDA_QUIRK_GPIO6 }, 424 { "gpio7", HDA_QUIRK_GPIO7 }, 425 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 426 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 427 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 428 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 429 { "eapdinv", HDA_QUIRK_EAPDINV }, 430 { "dmapos", HDA_QUIRK_DMAPOS }, 431 { "senseinv", HDA_QUIRK_SENSEINV }, 432 { "ivref50", HDA_QUIRK_IVREF50 }, 433 { "ivref80", HDA_QUIRK_IVREF80 }, 434 { "ivref100", HDA_QUIRK_IVREF100 }, 435 { "ovref50", HDA_QUIRK_OVREF50 }, 436 { "ovref80", HDA_QUIRK_OVREF80 }, 437 { "ovref100", HDA_QUIRK_OVREF100 }, 438 { "ivref", HDA_QUIRK_IVREF }, 439 { "ovref", HDA_QUIRK_OVREF }, 440 { "vref", HDA_QUIRK_VREF }, 441}; 442#define HDAC_QUIRKS_TAB_LEN \ 443 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 444 445#define HDA_BDL_MIN 2 446#define HDA_BDL_MAX 256 447#define HDA_BDL_DEFAULT HDA_BDL_MIN 448 449#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 450#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 451 452#define HDA_BUFSZ_MIN 4096 453#define HDA_BUFSZ_MAX 65536 454#define HDA_BUFSZ_DEFAULT 16384 455 456#define HDA_PARSE_MAXDEPTH 10 457 458#define HDAC_UNSOLTAG_EVENT_HP 0x00 459 460MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 461 462const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 463 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 464 "White", "Other"}; 465 466const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 467 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 468 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 469 470const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 471 472/* Default */ 473static uint32_t hdac_fmt[] = { 474 SND_FORMAT(AFMT_S16_LE, 2, 0), 475 0 476}; 477 478static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 479 480#define HDAC_NO_MSI 1 481#define HDAC_NO_64BIT 2 482 483static const struct { 484 uint32_t model; 485 char *desc; 486 char flags; 487} hdac_devices[] = { 488 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 489 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 490 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 491 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 492 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 493 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 494 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 495 { HDA_INTEL_PCH, "Intel PCH", 0 }, 496 { HDA_INTEL_SCH, "Intel SCH", 0 }, 497 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 498 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 500 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 502 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 504 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 506 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 508 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 512 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 516 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 519 { HDA_ATI_SB450, "ATI SB450", 0 }, 520 { HDA_ATI_SB600, "ATI SB600", 0 }, 521 { HDA_ATI_RS600, "ATI RS600", 0 }, 522 { HDA_ATI_RS690, "ATI RS690", 0 }, 523 { HDA_ATI_RS780, "ATI RS780", 0 }, 524 { HDA_ATI_R600, "ATI R600", 0 }, 525 { HDA_ATI_RV610, "ATI RV610", 0 }, 526 { HDA_ATI_RV620, "ATI RV620", 0 }, 527 { HDA_ATI_RV630, "ATI RV630", 0 }, 528 { HDA_ATI_RV635, "ATI RV635", 0 }, 529 { HDA_ATI_RV710, "ATI RV710", 0 }, 530 { HDA_ATI_RV730, "ATI RV730", 0 }, 531 { HDA_ATI_RV740, "ATI RV740", 0 }, 532 { HDA_ATI_RV770, "ATI RV770", 0 }, 533 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 534 { HDA_SIS_966, "SiS 966", 0 }, 535 { HDA_ULI_M5461, "ULI M5461", 0 }, 536 /* Unknown */ 537 { HDA_INTEL_ALL, "Intel (Unknown)" }, 538 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 539 { HDA_ATI_ALL, "ATI (Unknown)" }, 540 { HDA_VIA_ALL, "VIA (Unknown)" }, 541 { HDA_SIS_ALL, "SiS (Unknown)" }, 542 { HDA_ULI_ALL, "ULI (Unknown)" }, 543}; 544#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 545 546static const struct { 547 uint16_t vendor; 548 uint8_t reg; 549 uint8_t mask; 550 uint8_t enable; 551} hdac_pcie_snoop[] = { 552 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 553 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 554 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 555}; 556#define HDAC_PCIESNOOP_LEN \ 557 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 558 559static const struct { 560 uint32_t rate; 561 int valid; 562 uint16_t base; 563 uint16_t mul; 564 uint16_t div; 565} hda_rate_tab[] = { 566 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 567 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 568 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 569 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 570 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 571 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 572 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 573 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 574 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 575 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 576 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 577 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 578 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 579 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 580 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 581 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 582 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 583 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 584 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 585 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 586 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 587 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 588 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 589 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 590 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 591 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 592 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 593 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 594 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 595 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 596 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 597 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 598 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 599 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 600 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 601}; 602#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 603 604/* All codecs you can eat... */ 605#define HDA_CODEC_CONSTRUCT(vendor, id) \ 606 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 607 608/* Realtek */ 609#define REALTEK_VENDORID 0x10ec 610#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 611#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 612#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 613#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 614#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 615#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 616#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 617#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 618#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 619#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 620#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 621#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 622#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 623#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 624#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 625#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 626#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 627#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 628 629/* Analog Devices */ 630#define ANALOGDEVICES_VENDORID 0x11d4 631#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 632#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 633#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 634#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 635#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 636#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 637#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 638#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 639#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 640#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 641#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 642#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 643#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 644#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 645#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 646#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 647 648/* CMedia */ 649#define CMEDIA_VENDORID 0x434d 650#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 651#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 652 653/* Sigmatel */ 654#define SIGMATEL_VENDORID 0x8384 655#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 656#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 657#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 658#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 659#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 660#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 661#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 662#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 663#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 664#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 665#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 666#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 667#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 668#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 669#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 670#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 671#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 672#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 673#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 674#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 675#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 676#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 677#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 678#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 679#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 680#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 681#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 682#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 683#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 684#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 685#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 686#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 687#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 688#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 689#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 690#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 691#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 692#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 693#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 694#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 695 696/* IDT */ 697#define IDT_VENDORID 0x111d 698#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 699#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 700#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 701#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 702#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 703#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 704#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 705#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 706#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 707#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 708#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 709#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 710#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 711 712/* Silicon Image */ 713#define SII_VENDORID 0x1095 714#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 715#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 716#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 717 718/* Lucent/Agere */ 719#define AGERE_VENDORID 0x11c1 720#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 721 722/* Conexant */ 723#define CONEXANT_VENDORID 0x14f1 724#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 725#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 726#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 727#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 728 729/* VIA */ 730#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 731#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 732#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 733#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 734#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 735#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 736#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 737#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 738#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 739#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 740#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 741#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 742#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 743#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 744#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 745#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 746#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 747#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 748#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 749#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 750#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 751#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 752#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 753#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 754#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 755#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 756#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 757#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 758#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 759#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 760#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 761#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 762#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 763#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 764#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 765#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 766#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 767 768/* ATI */ 769#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 770#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 771#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 772#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 773#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 774 775/* NVIDIA */ 776#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 777#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 778#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 779#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 780#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 781#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 782 783/* INTEL */ 784#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 785#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 786#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 787#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 788#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 789 790/* Codecs */ 791static const struct { 792 uint32_t id; 793 char *name; 794} hdac_codecs[] = { 795 { HDA_CODEC_ALC260, "Realtek ALC260" }, 796 { HDA_CODEC_ALC262, "Realtek ALC262" }, 797 { HDA_CODEC_ALC267, "Realtek ALC267" }, 798 { HDA_CODEC_ALC268, "Realtek ALC268" }, 799 { HDA_CODEC_ALC269, "Realtek ALC269" }, 800 { HDA_CODEC_ALC272, "Realtek ALC272" }, 801 { HDA_CODEC_ALC660, "Realtek ALC660" }, 802 { HDA_CODEC_ALC662, "Realtek ALC662" }, 803 { HDA_CODEC_ALC663, "Realtek ALC663" }, 804 { HDA_CODEC_ALC861, "Realtek ALC861" }, 805 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 806 { HDA_CODEC_ALC880, "Realtek ALC880" }, 807 { HDA_CODEC_ALC882, "Realtek ALC882" }, 808 { HDA_CODEC_ALC883, "Realtek ALC883" }, 809 { HDA_CODEC_ALC885, "Realtek ALC885" }, 810 { HDA_CODEC_ALC888, "Realtek ALC888" }, 811 { HDA_CODEC_ALC889, "Realtek ALC889" }, 812 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 813 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 814 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 815 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 816 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 817 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 818 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 819 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 820 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 821 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 822 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 823 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 824 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 825 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 826 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 827 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 828 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 829 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 830 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 831 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 832 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 833 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 834 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 835 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 836 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 837 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 838 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 839 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 840 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 841 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 842 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 843 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 844 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 845 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 846 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 847 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 848 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 849 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 850 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 851 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 852 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 853 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 854 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 855 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 856 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 857 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 858 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 859 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 860 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 861 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 862 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 863 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 864 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 865 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 866 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 867 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 868 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 869 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 870 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 871 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 872 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 873 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 874 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 875 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 876 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 877 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 878 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 879 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 880 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 881 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 882 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 883 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 884 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 885 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 886 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 887 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 888 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 889 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 890 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 891 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 892 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 893 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 894 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 895 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 896 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 897 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 898 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 899 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 900 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 901 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 902 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 903 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 904 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 905 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 906 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 907 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 908 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 909 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 910 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 911 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 912 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 913 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 914 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 915 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 916 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 917 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 918 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 919 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 920 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 921 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 922 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 923 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 924 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 925 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 926 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 927 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 928 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 929 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 930 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 931 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 932 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 933 /* Unknown codec */ 934 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 935 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 936 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 937 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 938 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 939 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 940 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 941 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 942 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 943 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 944 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 945 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 946}; 947#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 948 949 950/**************************************************************************** 951 * Function prototypes 952 ****************************************************************************/ 953static void hdac_intr_handler(void *); 954static int hdac_reset(struct hdac_softc *, int); 955static int hdac_get_capabilities(struct hdac_softc *); 956static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 957static int hdac_dma_alloc(struct hdac_softc *, 958 struct hdac_dma *, bus_size_t); 959static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 960static int hdac_mem_alloc(struct hdac_softc *); 961static void hdac_mem_free(struct hdac_softc *); 962static int hdac_irq_alloc(struct hdac_softc *); 963static void hdac_irq_free(struct hdac_softc *); 964static void hdac_corb_init(struct hdac_softc *); 965static void hdac_rirb_init(struct hdac_softc *); 966static void hdac_corb_start(struct hdac_softc *); 967static void hdac_rirb_start(struct hdac_softc *); 968static void hdac_scan_codecs(struct hdac_softc *); 969static void hdac_probe_codec(struct hdac_codec *); 970static void hdac_probe_function(struct hdac_codec *, nid_t); 971static int hdac_pcmchannel_setup(struct hdac_chan *); 972 973static void hdac_attach2(void *); 974 975static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 976 uint32_t, int); 977static void hdac_command_send_internal(struct hdac_softc *, 978 struct hdac_command_list *, int); 979 980static int hdac_probe(device_t); 981static int hdac_attach(device_t); 982static int hdac_detach(device_t); 983static int hdac_suspend(device_t); 984static int hdac_resume(device_t); 985static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 986static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 987 uint32_t, int, int); 988static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 989 nid_t, int, int, int); 990static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 991 nid_t, nid_t, int, int, int, int, int, int); 992static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 993 994static int hdac_rirb_flush(struct hdac_softc *sc); 995static int hdac_unsolq_flush(struct hdac_softc *sc); 996 997static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 998 999#define hdac_command(a1, a2, a3) \ 1000 hdac_command_sendone_internal(a1, a2, a3) 1001 1002#define hdac_codec_id(c) \ 1003 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1004 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1005 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1006 1007static char * 1008hdac_codec_name(struct hdac_codec *codec) 1009{ 1010 uint32_t id; 1011 int i; 1012 1013 id = hdac_codec_id(codec); 1014 1015 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1016 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1017 return (hdac_codecs[i].name); 1018 } 1019 1020 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1021} 1022 1023static char * 1024hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1025{ 1026 static char *ossname[] = SOUND_DEVICE_NAMES; 1027 int i, first = 1; 1028 1029 bzero(buf, len); 1030 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1031 if (mask & (1 << i)) { 1032 if (first == 0) 1033 strlcat(buf, ", ", len); 1034 strlcat(buf, ossname[i], len); 1035 first = 0; 1036 } 1037 } 1038 return (buf); 1039} 1040 1041static struct hdac_audio_ctl * 1042hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1043{ 1044 if (devinfo == NULL || 1045 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1046 index == NULL || devinfo->function.audio.ctl == NULL || 1047 devinfo->function.audio.ctlcnt < 1 || 1048 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1049 return (NULL); 1050 return (&devinfo->function.audio.ctl[(*index)++]); 1051} 1052 1053static struct hdac_audio_ctl * 1054hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1055 int index, int cnt) 1056{ 1057 struct hdac_audio_ctl *ctl; 1058 int i, found = 0; 1059 1060 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1061 return (NULL); 1062 1063 i = 0; 1064 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1065 if (ctl->enable == 0) 1066 continue; 1067 if (ctl->widget->nid != nid) 1068 continue; 1069 if (dir && ctl->ndir != dir) 1070 continue; 1071 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1072 ctl->dir == ctl->ndir && ctl->index != index) 1073 continue; 1074 found++; 1075 if (found == cnt || cnt <= 0) 1076 return (ctl); 1077 } 1078 1079 return (NULL); 1080} 1081 1082/* 1083 * Jack detection (Speaker/HP redirection) event handler. 1084 */ 1085static void 1086hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1087{ 1088 struct hdac_audio_as *as; 1089 struct hdac_softc *sc; 1090 struct hdac_widget *w; 1091 struct hdac_audio_ctl *ctl; 1092 uint32_t val, res; 1093 int i, j; 1094 nid_t cad; 1095 1096 if (devinfo == NULL || devinfo->codec == NULL || 1097 devinfo->codec->sc == NULL) 1098 return; 1099 1100 sc = devinfo->codec->sc; 1101 cad = devinfo->codec->cad; 1102 as = devinfo->function.audio.as; 1103 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1104 if (as[i].hpredir < 0) 1105 continue; 1106 1107 w = hdac_widget_get(devinfo, as[i].pins[15]); 1108 if (w == NULL || w->enable == 0 || w->type != 1109 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1110 continue; 1111 1112 res = hdac_command(sc, 1113 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1114 1115 HDA_BOOTVERBOSE( 1116 device_printf(sc->dev, 1117 "Pin sense: nid=%d res=0x%08x\n", 1118 as[i].pins[15], res); 1119 ); 1120 1121 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1122 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1123 res ^= 1; 1124 1125 /* (Un)Mute headphone pin. */ 1126 ctl = hdac_audio_ctl_amp_get(devinfo, 1127 as[i].pins[15], HDA_CTL_IN, -1, 1); 1128 if (ctl != NULL && ctl->mute) { 1129 /* If pin has muter - use it. */ 1130 val = (res != 0) ? 0 : 1; 1131 if (val != ctl->forcemute) { 1132 ctl->forcemute = val; 1133 hdac_audio_ctl_amp_set(ctl, 1134 HDA_AMP_MUTE_DEFAULT, 1135 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1136 } 1137 } else { 1138 /* If there is no muter - disable pin output. */ 1139 w = hdac_widget_get(devinfo, as[i].pins[15]); 1140 if (w != NULL && w->type == 1141 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1142 if (res != 0) 1143 val = w->wclass.pin.ctrl | 1144 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1145 else 1146 val = w->wclass.pin.ctrl & 1147 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1148 if (val != w->wclass.pin.ctrl) { 1149 w->wclass.pin.ctrl = val; 1150 hdac_command(sc, 1151 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1152 w->nid, w->wclass.pin.ctrl), cad); 1153 } 1154 } 1155 } 1156 /* (Un)Mute other pins. */ 1157 for (j = 0; j < 15; j++) { 1158 if (as[i].pins[j] <= 0) 1159 continue; 1160 ctl = hdac_audio_ctl_amp_get(devinfo, 1161 as[i].pins[j], HDA_CTL_IN, -1, 1); 1162 if (ctl != NULL && ctl->mute) { 1163 /* If pin has muter - use it. */ 1164 val = (res != 0) ? 1 : 0; 1165 if (val == ctl->forcemute) 1166 continue; 1167 ctl->forcemute = val; 1168 hdac_audio_ctl_amp_set(ctl, 1169 HDA_AMP_MUTE_DEFAULT, 1170 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1171 continue; 1172 } 1173 /* If there is no muter - disable pin output. */ 1174 w = hdac_widget_get(devinfo, as[i].pins[j]); 1175 if (w != NULL && w->type == 1176 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1177 if (res != 0) 1178 val = w->wclass.pin.ctrl & 1179 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1180 else 1181 val = w->wclass.pin.ctrl | 1182 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1183 if (val != w->wclass.pin.ctrl) { 1184 w->wclass.pin.ctrl = val; 1185 hdac_command(sc, 1186 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1187 w->nid, w->wclass.pin.ctrl), cad); 1188 } 1189 } 1190 } 1191 } 1192} 1193 1194/* 1195 * Callback for poll based jack detection. 1196 */ 1197static void 1198hdac_jack_poll_callback(void *arg) 1199{ 1200 struct hdac_devinfo *devinfo = arg; 1201 struct hdac_softc *sc; 1202 1203 if (devinfo == NULL || devinfo->codec == NULL || 1204 devinfo->codec->sc == NULL) 1205 return; 1206 sc = devinfo->codec->sc; 1207 hdac_lock(sc); 1208 if (sc->poll_ival == 0) { 1209 hdac_unlock(sc); 1210 return; 1211 } 1212 hdac_hp_switch_handler(devinfo); 1213 callout_reset(&sc->poll_jack, sc->poll_ival, 1214 hdac_jack_poll_callback, devinfo); 1215 hdac_unlock(sc); 1216} 1217 1218/* 1219 * Jack detection initializer. 1220 */ 1221static void 1222hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1223{ 1224 struct hdac_softc *sc = devinfo->codec->sc; 1225 struct hdac_audio_as *as = devinfo->function.audio.as; 1226 struct hdac_widget *w; 1227 uint32_t id; 1228 int i, enable = 0, poll = 0; 1229 nid_t cad; 1230 1231 id = hdac_codec_id(devinfo->codec); 1232 cad = devinfo->codec->cad; 1233 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1234 if (as[i].hpredir < 0) 1235 continue; 1236 1237 w = hdac_widget_get(devinfo, as[i].pins[15]); 1238 if (w == NULL || w->enable == 0 || w->type != 1239 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1240 continue; 1241 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1242 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1243 device_printf(sc->dev, 1244 "No jack detection support at pin %d\n", 1245 as[i].pins[15]); 1246 continue; 1247 } 1248 enable = 1; 1249 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1250 hdac_command(sc, 1251 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1252 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1253 HDAC_UNSOLTAG_EVENT_HP), cad); 1254 } else 1255 poll = 1; 1256 HDA_BOOTVERBOSE( 1257 device_printf(sc->dev, 1258 "Enabling headphone/speaker " 1259 "audio routing switching:\n"); 1260 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1261 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1262 ); 1263 } 1264 if (enable) { 1265 hdac_hp_switch_handler(devinfo); 1266 if (poll) { 1267 callout_reset(&sc->poll_jack, 1, 1268 hdac_jack_poll_callback, devinfo); 1269 } 1270 } 1271} 1272 1273/* 1274 * Unsolicited messages handler. 1275 */ 1276static void 1277hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1278{ 1279 struct hdac_softc *sc; 1280 struct hdac_devinfo *devinfo = NULL; 1281 int i; 1282 1283 if (codec == NULL || codec->sc == NULL) 1284 return; 1285 1286 sc = codec->sc; 1287 1288 HDA_BOOTVERBOSE( 1289 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1290 ); 1291 1292 for (i = 0; i < codec->num_fgs; i++) { 1293 if (codec->fgs[i].node_type == 1294 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1295 devinfo = &codec->fgs[i]; 1296 break; 1297 } 1298 } 1299 1300 if (devinfo == NULL) 1301 return; 1302 1303 switch (tag) { 1304 case HDAC_UNSOLTAG_EVENT_HP: 1305 hdac_hp_switch_handler(devinfo); 1306 break; 1307 default: 1308 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1309 break; 1310 } 1311} 1312 1313static int 1314hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1315{ 1316 /* XXX to be removed */ 1317#ifdef HDAC_INTR_EXTRA 1318 uint32_t res; 1319#endif 1320 1321 if (!(ch->flags & HDAC_CHN_RUNNING)) 1322 return (0); 1323 1324 /* XXX to be removed */ 1325#ifdef HDAC_INTR_EXTRA 1326 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1327#endif 1328 1329 /* XXX to be removed */ 1330#ifdef HDAC_INTR_EXTRA 1331 HDA_BOOTVERBOSE( 1332 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1333 device_printf(ch->pdevinfo->dev, 1334 "PCMDIR_%s intr triggered beyond stream boundary:" 1335 "%08x\n", 1336 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1337 ); 1338#endif 1339 1340 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1341 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1342 1343 /* XXX to be removed */ 1344#ifdef HDAC_INTR_EXTRA 1345 if (res & HDAC_SDSTS_BCIS) { 1346#endif 1347 return (1); 1348 /* XXX to be removed */ 1349#ifdef HDAC_INTR_EXTRA 1350 } 1351#endif 1352 1353 return (0); 1354} 1355 1356/**************************************************************************** 1357 * void hdac_intr_handler(void *) 1358 * 1359 * Interrupt handler. Processes interrupts received from the hdac. 1360 ****************************************************************************/ 1361static void 1362hdac_intr_handler(void *context) 1363{ 1364 struct hdac_softc *sc; 1365 uint32_t intsts; 1366 uint8_t rirbsts; 1367 struct hdac_rirb *rirb_base; 1368 uint32_t trigger; 1369 int i; 1370 1371 sc = (struct hdac_softc *)context; 1372 1373 hdac_lock(sc); 1374 if (sc->polling != 0) { 1375 hdac_unlock(sc); 1376 return; 1377 } 1378 1379 /* Do we have anything to do? */ 1380 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1381 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1382 hdac_unlock(sc); 1383 return; 1384 } 1385 1386 trigger = 0; 1387 1388 /* Was this a controller interrupt? */ 1389 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1390 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1391 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1392 /* Get as many responses that we can */ 1393 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1394 HDAC_WRITE_1(&sc->mem, 1395 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1396 if (hdac_rirb_flush(sc) != 0) 1397 trigger |= HDAC_TRIGGER_UNSOL; 1398 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1399 } 1400 /* XXX to be removed */ 1401 /* Clear interrupt and exit */ 1402#ifdef HDAC_INTR_EXTRA 1403 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1404#endif 1405 } 1406 1407 if (intsts & HDAC_INTSTS_SIS_MASK) { 1408 for (i = 0; i < sc->num_chans; i++) { 1409 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1410 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1411 trigger |= (1 << i); 1412 } 1413 /* XXX to be removed */ 1414#ifdef HDAC_INTR_EXTRA 1415 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1416 HDAC_INTSTS_SIS_MASK); 1417#endif 1418 } 1419 1420 hdac_unlock(sc); 1421 1422 for (i = 0; i < sc->num_chans; i++) { 1423 if (trigger & (1 << i)) 1424 chn_intr(sc->chans[i].c); 1425 } 1426 if (trigger & HDAC_TRIGGER_UNSOL) 1427 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1428} 1429 1430/**************************************************************************** 1431 * int hdac_reset(hdac_softc *, int) 1432 * 1433 * Reset the hdac to a quiescent and known state. 1434 ****************************************************************************/ 1435static int 1436hdac_reset(struct hdac_softc *sc, int wakeup) 1437{ 1438 uint32_t gctl; 1439 int count, i; 1440 1441 /* 1442 * Stop all Streams DMA engine 1443 */ 1444 for (i = 0; i < sc->num_iss; i++) 1445 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1446 for (i = 0; i < sc->num_oss; i++) 1447 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1448 for (i = 0; i < sc->num_bss; i++) 1449 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1450 1451 /* 1452 * Stop Control DMA engines. 1453 */ 1454 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1455 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1456 1457 /* 1458 * Reset DMA position buffer. 1459 */ 1460 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1461 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1462 1463 /* 1464 * Reset the controller. The reset must remain asserted for 1465 * a minimum of 100us. 1466 */ 1467 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1468 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1469 count = 10000; 1470 do { 1471 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1472 if (!(gctl & HDAC_GCTL_CRST)) 1473 break; 1474 DELAY(10); 1475 } while (--count); 1476 if (gctl & HDAC_GCTL_CRST) { 1477 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1478 return (ENXIO); 1479 } 1480 1481 /* If wakeup is not requested - leave the controller in reset state. */ 1482 if (!wakeup) 1483 return (0); 1484 1485 DELAY(100); 1486 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1487 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1488 count = 10000; 1489 do { 1490 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1491 if (gctl & HDAC_GCTL_CRST) 1492 break; 1493 DELAY(10); 1494 } while (--count); 1495 if (!(gctl & HDAC_GCTL_CRST)) { 1496 device_printf(sc->dev, "Device stuck in reset\n"); 1497 return (ENXIO); 1498 } 1499 1500 /* 1501 * Wait for codecs to finish their own reset sequence. The delay here 1502 * should be of 250us but for some reasons, on it's not enough on my 1503 * computer. Let's use twice as much as necessary to make sure that 1504 * it's reset properly. 1505 */ 1506 DELAY(1000); 1507 1508 return (0); 1509} 1510 1511 1512/**************************************************************************** 1513 * int hdac_get_capabilities(struct hdac_softc *); 1514 * 1515 * Retreive the general capabilities of the hdac; 1516 * Number of Input Streams 1517 * Number of Output Streams 1518 * Number of bidirectional Streams 1519 * 64bit ready 1520 * CORB and RIRB sizes 1521 ****************************************************************************/ 1522static int 1523hdac_get_capabilities(struct hdac_softc *sc) 1524{ 1525 uint16_t gcap; 1526 uint8_t corbsize, rirbsize; 1527 1528 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1529 sc->num_iss = HDAC_GCAP_ISS(gcap); 1530 sc->num_oss = HDAC_GCAP_OSS(gcap); 1531 sc->num_bss = HDAC_GCAP_BSS(gcap); 1532 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1533 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1534 1535 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1536 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1537 HDAC_CORBSIZE_CORBSZCAP_256) 1538 sc->corb_size = 256; 1539 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1540 HDAC_CORBSIZE_CORBSZCAP_16) 1541 sc->corb_size = 16; 1542 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1543 HDAC_CORBSIZE_CORBSZCAP_2) 1544 sc->corb_size = 2; 1545 else { 1546 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1547 __func__, corbsize); 1548 return (ENXIO); 1549 } 1550 1551 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1552 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1553 HDAC_RIRBSIZE_RIRBSZCAP_256) 1554 sc->rirb_size = 256; 1555 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1556 HDAC_RIRBSIZE_RIRBSZCAP_16) 1557 sc->rirb_size = 16; 1558 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1559 HDAC_RIRBSIZE_RIRBSZCAP_2) 1560 sc->rirb_size = 2; 1561 else { 1562 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1563 __func__, rirbsize); 1564 return (ENXIO); 1565 } 1566 1567 HDA_BOOTVERBOSE( 1568 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1569 "NSDO %d%s, CORB %d, RIRB %d\n", 1570 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1571 sc->support_64bit ? ", 64bit" : "", 1572 sc->corb_size, sc->rirb_size); 1573 ); 1574 1575 return (0); 1576} 1577 1578 1579/**************************************************************************** 1580 * void hdac_dma_cb 1581 * 1582 * This function is called by bus_dmamap_load when the mapping has been 1583 * established. We just record the physical address of the mapping into 1584 * the struct hdac_dma passed in. 1585 ****************************************************************************/ 1586static void 1587hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1588{ 1589 struct hdac_dma *dma; 1590 1591 if (error == 0) { 1592 dma = (struct hdac_dma *)callback_arg; 1593 dma->dma_paddr = segs[0].ds_addr; 1594 } 1595} 1596 1597 1598/**************************************************************************** 1599 * int hdac_dma_alloc 1600 * 1601 * This function allocate and setup a dma region (struct hdac_dma). 1602 * It must be freed by a corresponding hdac_dma_free. 1603 ****************************************************************************/ 1604static int 1605hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1606{ 1607 bus_size_t roundsz; 1608 int result; 1609 1610 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1611 bzero(dma, sizeof(*dma)); 1612 1613 /* 1614 * Create a DMA tag 1615 */ 1616 result = bus_dma_tag_create( 1617 bus_get_dma_tag(sc->dev), /* parent */ 1618 HDAC_DMA_ALIGNMENT, /* alignment */ 1619 0, /* boundary */ 1620 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1621 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1622 BUS_SPACE_MAXADDR, /* highaddr */ 1623 NULL, /* filtfunc */ 1624 NULL, /* fistfuncarg */ 1625 roundsz, /* maxsize */ 1626 1, /* nsegments */ 1627 roundsz, /* maxsegsz */ 1628 0, /* flags */ 1629 NULL, /* lockfunc */ 1630 NULL, /* lockfuncarg */ 1631 &dma->dma_tag); /* dmat */ 1632 if (result != 0) { 1633 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1634 __func__, result); 1635 goto hdac_dma_alloc_fail; 1636 } 1637 1638 /* 1639 * Allocate DMA memory 1640 */ 1641 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1642 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1643 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1644 &dma->dma_map); 1645 if (result != 0) { 1646 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1647 __func__, result); 1648 goto hdac_dma_alloc_fail; 1649 } 1650 1651 dma->dma_size = roundsz; 1652 1653 /* 1654 * Map the memory 1655 */ 1656 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1657 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1658 if (result != 0 || dma->dma_paddr == 0) { 1659 if (result == 0) 1660 result = ENOMEM; 1661 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1662 __func__, result); 1663 goto hdac_dma_alloc_fail; 1664 } 1665 1666 HDA_BOOTHVERBOSE( 1667 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1668 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1669 ); 1670 1671 return (0); 1672 1673hdac_dma_alloc_fail: 1674 hdac_dma_free(sc, dma); 1675 1676 return (result); 1677} 1678 1679 1680/**************************************************************************** 1681 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1682 * 1683 * Free a struct dhac_dma that has been previously allocated via the 1684 * hdac_dma_alloc function. 1685 ****************************************************************************/ 1686static void 1687hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1688{ 1689 if (dma->dma_map != NULL) { 1690#if 0 1691 /* Flush caches */ 1692 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1693 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1694#endif 1695 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1696 } 1697 if (dma->dma_vaddr != NULL) { 1698 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1699 dma->dma_vaddr = NULL; 1700 } 1701 dma->dma_map = NULL; 1702 if (dma->dma_tag != NULL) { 1703 bus_dma_tag_destroy(dma->dma_tag); 1704 dma->dma_tag = NULL; 1705 } 1706 dma->dma_size = 0; 1707} 1708 1709/**************************************************************************** 1710 * int hdac_mem_alloc(struct hdac_softc *) 1711 * 1712 * Allocate all the bus resources necessary to speak with the physical 1713 * controller. 1714 ****************************************************************************/ 1715static int 1716hdac_mem_alloc(struct hdac_softc *sc) 1717{ 1718 struct hdac_mem *mem; 1719 1720 mem = &sc->mem; 1721 mem->mem_rid = PCIR_BAR(0); 1722 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1723 &mem->mem_rid, RF_ACTIVE); 1724 if (mem->mem_res == NULL) { 1725 device_printf(sc->dev, 1726 "%s: Unable to allocate memory resource\n", __func__); 1727 return (ENOMEM); 1728 } 1729 mem->mem_tag = rman_get_bustag(mem->mem_res); 1730 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1731 1732 return (0); 1733} 1734 1735/**************************************************************************** 1736 * void hdac_mem_free(struct hdac_softc *) 1737 * 1738 * Free up resources previously allocated by hdac_mem_alloc. 1739 ****************************************************************************/ 1740static void 1741hdac_mem_free(struct hdac_softc *sc) 1742{ 1743 struct hdac_mem *mem; 1744 1745 mem = &sc->mem; 1746 if (mem->mem_res != NULL) 1747 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1748 mem->mem_res); 1749 mem->mem_res = NULL; 1750} 1751 1752/**************************************************************************** 1753 * int hdac_irq_alloc(struct hdac_softc *) 1754 * 1755 * Allocate and setup the resources necessary for interrupt handling. 1756 ****************************************************************************/ 1757static int 1758hdac_irq_alloc(struct hdac_softc *sc) 1759{ 1760 struct hdac_irq *irq; 1761 int result; 1762 1763 irq = &sc->irq; 1764 irq->irq_rid = 0x0; 1765 1766 if ((sc->flags & HDAC_F_MSI) && 1767 (result = pci_msi_count(sc->dev)) == 1 && 1768 pci_alloc_msi(sc->dev, &result) == 0) 1769 irq->irq_rid = 0x1; 1770 else 1771 sc->flags &= ~HDAC_F_MSI; 1772 1773 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1774 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1775 if (irq->irq_res == NULL) { 1776 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1777 __func__); 1778 goto hdac_irq_alloc_fail; 1779 } 1780 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1781 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1782 if (result != 0) { 1783 device_printf(sc->dev, 1784 "%s: Unable to setup interrupt handler (%x)\n", 1785 __func__, result); 1786 goto hdac_irq_alloc_fail; 1787 } 1788 1789 return (0); 1790 1791hdac_irq_alloc_fail: 1792 hdac_irq_free(sc); 1793 1794 return (ENXIO); 1795} 1796 1797/**************************************************************************** 1798 * void hdac_irq_free(struct hdac_softc *) 1799 * 1800 * Free up resources previously allocated by hdac_irq_alloc. 1801 ****************************************************************************/ 1802static void 1803hdac_irq_free(struct hdac_softc *sc) 1804{ 1805 struct hdac_irq *irq; 1806 1807 irq = &sc->irq; 1808 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1809 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1810 if (irq->irq_res != NULL) 1811 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1812 irq->irq_res); 1813 if (irq->irq_rid == 0x1) 1814 pci_release_msi(sc->dev); 1815 irq->irq_handle = NULL; 1816 irq->irq_res = NULL; 1817 irq->irq_rid = 0x0; 1818} 1819 1820/**************************************************************************** 1821 * void hdac_corb_init(struct hdac_softc *) 1822 * 1823 * Initialize the corb registers for operations but do not start it up yet. 1824 * The CORB engine must not be running when this function is called. 1825 ****************************************************************************/ 1826static void 1827hdac_corb_init(struct hdac_softc *sc) 1828{ 1829 uint8_t corbsize; 1830 uint64_t corbpaddr; 1831 1832 /* Setup the CORB size. */ 1833 switch (sc->corb_size) { 1834 case 256: 1835 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1836 break; 1837 case 16: 1838 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1839 break; 1840 case 2: 1841 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1842 break; 1843 default: 1844 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1845 } 1846 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1847 1848 /* Setup the CORB Address in the hdac */ 1849 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1850 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1851 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1852 1853 /* Set the WP and RP */ 1854 sc->corb_wp = 0; 1855 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1856 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1857 /* 1858 * The HDA specification indicates that the CORBRPRST bit will always 1859 * read as zero. Unfortunately, it seems that at least the 82801G 1860 * doesn't reset the bit to zero, which stalls the corb engine. 1861 * manually reset the bit to zero before continuing. 1862 */ 1863 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1864 1865 /* Enable CORB error reporting */ 1866#if 0 1867 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1868#endif 1869} 1870 1871/**************************************************************************** 1872 * void hdac_rirb_init(struct hdac_softc *) 1873 * 1874 * Initialize the rirb registers for operations but do not start it up yet. 1875 * The RIRB engine must not be running when this function is called. 1876 ****************************************************************************/ 1877static void 1878hdac_rirb_init(struct hdac_softc *sc) 1879{ 1880 uint8_t rirbsize; 1881 uint64_t rirbpaddr; 1882 1883 /* Setup the RIRB size. */ 1884 switch (sc->rirb_size) { 1885 case 256: 1886 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1887 break; 1888 case 16: 1889 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1890 break; 1891 case 2: 1892 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1893 break; 1894 default: 1895 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1896 } 1897 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1898 1899 /* Setup the RIRB Address in the hdac */ 1900 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1901 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1902 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1903 1904 /* Setup the WP and RP */ 1905 sc->rirb_rp = 0; 1906 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1907 1908 /* Setup the interrupt threshold */ 1909 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1910 1911 /* Enable Overrun and response received reporting */ 1912#if 0 1913 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1914 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1915#else 1916 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1917#endif 1918 1919#if 0 1920 /* 1921 * Make sure that the Host CPU cache doesn't contain any dirty 1922 * cache lines that falls in the rirb. If I understood correctly, it 1923 * should be sufficient to do this only once as the rirb is purely 1924 * read-only from now on. 1925 */ 1926 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1927 BUS_DMASYNC_PREREAD); 1928#endif 1929} 1930 1931/**************************************************************************** 1932 * void hdac_corb_start(hdac_softc *) 1933 * 1934 * Startup the corb DMA engine 1935 ****************************************************************************/ 1936static void 1937hdac_corb_start(struct hdac_softc *sc) 1938{ 1939 uint32_t corbctl; 1940 1941 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1942 corbctl |= HDAC_CORBCTL_CORBRUN; 1943 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1944} 1945 1946/**************************************************************************** 1947 * void hdac_rirb_start(hdac_softc *) 1948 * 1949 * Startup the rirb DMA engine 1950 ****************************************************************************/ 1951static void 1952hdac_rirb_start(struct hdac_softc *sc) 1953{ 1954 uint32_t rirbctl; 1955 1956 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1957 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1958 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1959} 1960 1961 1962/**************************************************************************** 1963 * void hdac_scan_codecs(struct hdac_softc *, int) 1964 * 1965 * Scan the bus for available codecs, starting with num. 1966 ****************************************************************************/ 1967static void 1968hdac_scan_codecs(struct hdac_softc *sc) 1969{ 1970 struct hdac_codec *codec; 1971 int i; 1972 uint16_t statests; 1973 1974 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1975 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1976 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1977 /* We have found a codec. */ 1978 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1979 M_HDAC, M_ZERO | M_NOWAIT); 1980 if (codec == NULL) { 1981 device_printf(sc->dev, 1982 "Unable to allocate memory for codec\n"); 1983 continue; 1984 } 1985 codec->commands = NULL; 1986 codec->responses_received = 0; 1987 codec->verbs_sent = 0; 1988 codec->sc = sc; 1989 codec->cad = i; 1990 sc->codecs[i] = codec; 1991 hdac_probe_codec(codec); 1992 } 1993 } 1994 /* All codecs have been probed, now try to attach drivers to them */ 1995 /* bus_generic_attach(sc->dev); */ 1996} 1997 1998/**************************************************************************** 1999 * void hdac_probe_codec(struct hdac_softc *, int) 2000 * 2001 * Probe a the given codec_id for available function groups. 2002 ****************************************************************************/ 2003static void 2004hdac_probe_codec(struct hdac_codec *codec) 2005{ 2006 struct hdac_softc *sc = codec->sc; 2007 uint32_t vendorid, revisionid, subnode; 2008 int startnode; 2009 int endnode; 2010 int i; 2011 nid_t cad = codec->cad; 2012 2013 HDA_BOOTVERBOSE( 2014 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2015 ); 2016 vendorid = hdac_command(sc, 2017 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2018 cad); 2019 revisionid = hdac_command(sc, 2020 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2021 cad); 2022 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2023 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2024 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2025 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2026 2027 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2028 device_printf(sc->dev, "Codec #%d is not responding!" 2029 " Probing aborted.\n", cad); 2030 return; 2031 } 2032 2033 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2034 cad, hdac_codec_name(codec)); 2035 HDA_BOOTVERBOSE( 2036 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2037 hdac_codec_id(codec)); 2038 device_printf(sc->dev, " Vendor: 0x%04x\n", 2039 codec->vendor_id); 2040 device_printf(sc->dev, " Device: 0x%04x\n", 2041 codec->device_id); 2042 device_printf(sc->dev, " Revision: 0x%02x\n", 2043 codec->revision_id); 2044 device_printf(sc->dev, " Stepping: 0x%02x\n", 2045 codec->stepping_id); 2046 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2047 sc->pci_subvendor); 2048 ); 2049 subnode = hdac_command(sc, 2050 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2051 cad); 2052 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2053 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2054 2055 HDA_BOOTHVERBOSE( 2056 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2057 startnode, endnode); 2058 ); 2059 2060 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2061 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2062 if (codec->fgs == NULL) { 2063 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2064 __func__); 2065 return; 2066 } 2067 2068 for (i = startnode; i < endnode; i++) 2069 hdac_probe_function(codec, i); 2070 return; 2071} 2072 2073/* 2074 * Probe codec function and add it to the list. 2075 */ 2076static void 2077hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2078{ 2079 struct hdac_softc *sc = codec->sc; 2080 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2081 uint32_t fctgrptype; 2082 uint32_t res; 2083 nid_t cad = codec->cad; 2084 2085 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2086 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2087 2088 devinfo->nid = nid; 2089 devinfo->node_type = fctgrptype; 2090 devinfo->codec = codec; 2091 2092 res = hdac_command(sc, 2093 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2094 2095 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2096 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2097 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2098 2099 HDA_BOOTVERBOSE( 2100 device_printf(sc->dev, 2101 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2102 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2103 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2104 "unknown", nid, devinfo->startnode, devinfo->endnode, 2105 devinfo->nodecnt); 2106 ); 2107 2108 if (devinfo->nodecnt > 0) 2109 devinfo->widget = (struct hdac_widget *)malloc( 2110 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2111 M_NOWAIT | M_ZERO); 2112 else 2113 devinfo->widget = NULL; 2114 2115 if (devinfo->widget == NULL) { 2116 device_printf(sc->dev, "unable to allocate widgets!\n"); 2117 devinfo->endnode = devinfo->startnode; 2118 devinfo->nodecnt = 0; 2119 return; 2120 } 2121 2122 codec->num_fgs++; 2123} 2124 2125static void 2126hdac_widget_connection_parse(struct hdac_widget *w) 2127{ 2128 struct hdac_softc *sc = w->devinfo->codec->sc; 2129 uint32_t res; 2130 int i, j, max, ents, entnum; 2131 nid_t cad = w->devinfo->codec->cad; 2132 nid_t nid = w->nid; 2133 nid_t cnid, addcnid, prevcnid; 2134 2135 w->nconns = 0; 2136 2137 res = hdac_command(sc, 2138 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2139 2140 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2141 2142 if (ents < 1) 2143 return; 2144 2145 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2146 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2147 prevcnid = 0; 2148 2149#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2150#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2151#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2152#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2153#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2154 2155 for (i = 0; i < ents; i += entnum) { 2156 res = hdac_command(sc, 2157 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2158 for (j = 0; j < entnum; j++) { 2159 cnid = CONN_CNID(res, entnum, j); 2160 if (cnid == 0) { 2161 if (w->nconns < ents) 2162 device_printf(sc->dev, 2163 "%s: nid=%d WARNING: zero cnid " 2164 "entnum=%d j=%d index=%d " 2165 "entries=%d found=%d res=0x%08x\n", 2166 __func__, nid, entnum, j, i, 2167 ents, w->nconns, res); 2168 else 2169 goto getconns_out; 2170 } 2171 if (cnid < w->devinfo->startnode || 2172 cnid >= w->devinfo->endnode) { 2173 HDA_BOOTVERBOSE( 2174 device_printf(sc->dev, 2175 "GHOST: nid=%d j=%d " 2176 "entnum=%d index=%d res=0x%08x\n", 2177 nid, j, entnum, i, res); 2178 ); 2179 } 2180 if (CONN_RANGE(res, entnum, j) == 0) 2181 addcnid = cnid; 2182 else if (prevcnid == 0 || prevcnid >= cnid) { 2183 device_printf(sc->dev, 2184 "%s: WARNING: Invalid child range " 2185 "nid=%d index=%d j=%d entnum=%d " 2186 "prevcnid=%d cnid=%d res=0x%08x\n", 2187 __func__, nid, i, j, entnum, prevcnid, 2188 cnid, res); 2189 addcnid = cnid; 2190 } else 2191 addcnid = prevcnid + 1; 2192 while (addcnid <= cnid) { 2193 if (w->nconns > max) { 2194 device_printf(sc->dev, 2195 "Adding %d (nid=%d): " 2196 "Max connection reached! max=%d\n", 2197 addcnid, nid, max + 1); 2198 goto getconns_out; 2199 } 2200 w->connsenable[w->nconns] = 1; 2201 w->conns[w->nconns++] = addcnid++; 2202 } 2203 prevcnid = cnid; 2204 } 2205 } 2206 2207getconns_out: 2208 return; 2209} 2210 2211static uint32_t 2212hdac_widget_pin_patch(uint32_t config, const char *str) 2213{ 2214 char buf[256]; 2215 char *key, *value, *rest, *bad; 2216 int ival, i; 2217 2218 strlcpy(buf, str, sizeof(buf)); 2219 rest = buf; 2220 while ((key = strsep(&rest, "=")) != NULL) { 2221 value = strsep(&rest, " \t"); 2222 if (value == NULL) 2223 break; 2224 ival = strtol(value, &bad, 10); 2225 if (strcmp(key, "seq") == 0) { 2226 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2227 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2228 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2229 } else if (strcmp(key, "as") == 0) { 2230 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2231 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2232 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2233 } else if (strcmp(key, "misc") == 0) { 2234 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2235 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2236 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2237 } else if (strcmp(key, "color") == 0) { 2238 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2239 if (bad[0] == 0) { 2240 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2241 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2242 }; 2243 for (i = 0; i < 16; i++) { 2244 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2245 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2246 break; 2247 } 2248 } 2249 } else if (strcmp(key, "ctype") == 0) { 2250 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2251 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2252 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2253 } else if (strcmp(key, "device") == 0) { 2254 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2255 if (bad[0] == 0) { 2256 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2257 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2258 continue; 2259 }; 2260 for (i = 0; i < 16; i++) { 2261 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2262 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2263 break; 2264 } 2265 } 2266 } else if (strcmp(key, "loc") == 0) { 2267 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2268 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2269 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2270 } else if (strcmp(key, "conn") == 0) { 2271 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2272 if (bad[0] == 0) { 2273 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2274 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2275 continue; 2276 }; 2277 for (i = 0; i < 4; i++) { 2278 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2279 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2280 break; 2281 } 2282 } 2283 } 2284 } 2285 return (config); 2286} 2287 2288static uint32_t 2289hdac_widget_pin_getconfig(struct hdac_widget *w) 2290{ 2291 struct hdac_softc *sc; 2292 uint32_t config, orig, id; 2293 nid_t cad, nid; 2294 char buf[32]; 2295 const char *res = NULL, *patch = NULL; 2296 2297 sc = w->devinfo->codec->sc; 2298 cad = w->devinfo->codec->cad; 2299 nid = w->nid; 2300 id = hdac_codec_id(w->devinfo->codec); 2301 2302 config = hdac_command(sc, 2303 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2304 cad); 2305 orig = config; 2306 2307 HDA_BOOTVERBOSE( 2308 hdac_dump_pin_config(w, orig); 2309 ); 2310 2311 /* XXX: Old patches require complete review. 2312 * Now they may create more problem then solve due to 2313 * incorrect associations. 2314 */ 2315 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2316 switch (nid) { 2317 case 26: 2318 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2319 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2320 break; 2321 case 27: 2322 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2323 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2324 break; 2325 default: 2326 break; 2327 } 2328 } else if (id == HDA_CODEC_ALC880 && 2329 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2330 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2331 /* 2332 * Super broken BIOS 2333 */ 2334 switch (nid) { 2335 case 24: /* MIC1 */ 2336 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2337 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2338 break; 2339 case 25: /* XXX MIC2 */ 2340 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2341 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2342 break; 2343 case 26: /* LINE1 */ 2344 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2345 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2346 break; 2347 case 27: /* XXX LINE2 */ 2348 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2349 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2350 break; 2351 case 28: /* CD */ 2352 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2353 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2354 break; 2355 } 2356 } else if (id == HDA_CODEC_ALC883 && 2357 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2358 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2359 switch (nid) { 2360 case 25: 2361 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2362 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2363 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2364 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2365 break; 2366 case 28: 2367 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2368 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2369 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2370 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2371 break; 2372 } 2373 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2374 HP_V3000_SUBVENDOR) { 2375 switch (nid) { 2376 case 18: 2377 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2378 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2379 break; 2380 case 20: 2381 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2382 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2383 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2384 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2385 break; 2386 case 21: 2387 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2388 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2389 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2390 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2391 break; 2392 } 2393 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2394 HP_DV5000_SUBVENDOR) { 2395 switch (nid) { 2396 case 20: 2397 case 21: 2398 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2399 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2400 break; 2401 } 2402 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2403 ASUS_W6F_SUBVENDOR) { 2404 switch (nid) { 2405 case 11: 2406 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2408 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2409 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2410 break; 2411 case 12: 2412 case 14: 2413 case 16: 2414 case 31: 2415 case 32: 2416 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2417 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2418 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2419 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2420 break; 2421 case 15: 2422 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2423 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2424 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2425 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2426 break; 2427 } 2428 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2429 UNIWILL_9075_SUBVENDOR) { 2430 switch (nid) { 2431 case 15: 2432 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2433 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2434 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2435 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2436 break; 2437 } 2438 } 2439 2440 /* New patches */ 2441 if (id == HDA_CODEC_AD1986A && 2442 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2443 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2444 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2445 switch (nid) { 2446 case 26: /* Headphones with redirection */ 2447 patch = "as=1 seq=15"; 2448 break; 2449 case 28: /* 5.1 out => 2.0 out + 1 input */ 2450 patch = "device=Line-in as=8 seq=1"; 2451 break; 2452 case 29: /* Can't use this as input, as the only available mic 2453 * preamplifier is busy by front panel mic (nid 31). 2454 * If you want to use this rear connector as mic input, 2455 * you have to disable the front panel one. */ 2456 patch = "as=0"; 2457 break; 2458 case 31: /* Lot of inputs configured with as=15 and unusable */ 2459 patch = "as=8 seq=3"; 2460 break; 2461 case 32: 2462 patch = "as=8 seq=4"; 2463 break; 2464 case 34: 2465 patch = "as=8 seq=5"; 2466 break; 2467 case 36: 2468 patch = "as=8 seq=6"; 2469 break; 2470 } 2471 } else if (id == HDA_CODEC_ALC260 && 2472 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2473 switch (nid) { 2474 case 16: 2475 patch = "seq=15 device=Headphones"; 2476 break; 2477 } 2478 } else if (id == HDA_CODEC_ALC268) { 2479 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2480 switch (nid) { 2481 case 20: /* Headphones Jack */ 2482 patch = "as=1 seq=15"; 2483 break; 2484 } 2485 } 2486 } 2487 2488 if (patch != NULL) 2489 config = hdac_widget_pin_patch(config, patch); 2490 2491 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2492 if (resource_string_value(device_get_name(sc->dev), 2493 device_get_unit(sc->dev), buf, &res) == 0) { 2494 if (strncmp(res, "0x", 2) == 0) { 2495 config = strtol(res + 2, NULL, 16); 2496 } else { 2497 config = hdac_widget_pin_patch(config, res); 2498 } 2499 } 2500 2501 HDA_BOOTVERBOSE( 2502 if (config != orig) 2503 device_printf(sc->dev, 2504 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2505 nid, orig, config); 2506 ); 2507 2508 return (config); 2509} 2510 2511static uint32_t 2512hdac_widget_pin_getcaps(struct hdac_widget *w) 2513{ 2514 struct hdac_softc *sc; 2515 uint32_t caps, orig, id; 2516 nid_t cad, nid; 2517 2518 sc = w->devinfo->codec->sc; 2519 cad = w->devinfo->codec->cad; 2520 nid = w->nid; 2521 id = hdac_codec_id(w->devinfo->codec); 2522 2523 caps = hdac_command(sc, 2524 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2525 orig = caps; 2526 2527 HDA_BOOTVERBOSE( 2528 if (caps != orig) 2529 device_printf(sc->dev, 2530 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2531 nid, orig, caps); 2532 ); 2533 2534 return (caps); 2535} 2536 2537static void 2538hdac_widget_pin_parse(struct hdac_widget *w) 2539{ 2540 struct hdac_softc *sc = w->devinfo->codec->sc; 2541 uint32_t config, pincap; 2542 const char *devstr; 2543 nid_t cad = w->devinfo->codec->cad; 2544 nid_t nid = w->nid; 2545 int conn, color; 2546 2547 config = hdac_widget_pin_getconfig(w); 2548 w->wclass.pin.config = config; 2549 2550 pincap = hdac_widget_pin_getcaps(w); 2551 w->wclass.pin.cap = pincap; 2552 2553 w->wclass.pin.ctrl = hdac_command(sc, 2554 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2555 2556 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2557 w->param.eapdbtl = hdac_command(sc, 2558 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2559 w->param.eapdbtl &= 0x7; 2560 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2561 } else 2562 w->param.eapdbtl = HDAC_INVALID; 2563 2564 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2565 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2566 2567 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2568 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2569 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2570 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2571 2572 strlcat(w->name, ": ", sizeof(w->name)); 2573 strlcat(w->name, devstr, sizeof(w->name)); 2574 strlcat(w->name, " (", sizeof(w->name)); 2575 if (conn == 0 && color != 0 && color != 15) { 2576 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2577 strlcat(w->name, " ", sizeof(w->name)); 2578 } 2579 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2580 strlcat(w->name, ")", sizeof(w->name)); 2581} 2582 2583static uint32_t 2584hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2585{ 2586 struct hdac_softc *sc; 2587 uint32_t caps, orig, id; 2588 nid_t cad, nid, beeper = -1; 2589 2590 sc = w->devinfo->codec->sc; 2591 cad = w->devinfo->codec->cad; 2592 nid = w->nid; 2593 id = hdac_codec_id(w->devinfo->codec); 2594 2595 caps = hdac_command(sc, 2596 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2597 cad); 2598 orig = caps; 2599 2600 /* On some codecs beeper is an input pin, but it is not recordable 2601 alone. Also most of BIOSes does not declare beeper pin. 2602 Change beeper pin node type to beeper to help parser. */ 2603 *waspin = 0; 2604 switch (id) { 2605 case HDA_CODEC_AD1882: 2606 case HDA_CODEC_AD1883: 2607 case HDA_CODEC_AD1984: 2608 case HDA_CODEC_AD1984A: 2609 case HDA_CODEC_AD1984B: 2610 case HDA_CODEC_AD1987: 2611 case HDA_CODEC_AD1988: 2612 case HDA_CODEC_AD1988B: 2613 case HDA_CODEC_AD1989B: 2614 beeper = 26; 2615 break; 2616 case HDA_CODEC_ALC260: 2617 beeper = 23; 2618 break; 2619 case HDA_CODEC_ALC262: 2620 case HDA_CODEC_ALC268: 2621 case HDA_CODEC_ALC880: 2622 case HDA_CODEC_ALC882: 2623 case HDA_CODEC_ALC883: 2624 case HDA_CODEC_ALC885: 2625 case HDA_CODEC_ALC888: 2626 case HDA_CODEC_ALC889: 2627 beeper = 29; 2628 break; 2629 } 2630 if (nid == beeper) { 2631 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2632 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2633 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2634 *waspin = 1; 2635 } 2636 2637 HDA_BOOTVERBOSE( 2638 if (caps != orig) { 2639 device_printf(sc->dev, 2640 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2641 nid, orig, caps); 2642 } 2643 ); 2644 2645 return (caps); 2646} 2647 2648static void 2649hdac_widget_parse(struct hdac_widget *w) 2650{ 2651 struct hdac_softc *sc = w->devinfo->codec->sc; 2652 uint32_t wcap, cap; 2653 char *typestr; 2654 nid_t cad = w->devinfo->codec->cad; 2655 nid_t nid = w->nid; 2656 2657 wcap = hdac_widget_getcaps(w, &w->waspin); 2658 2659 w->param.widget_cap = wcap; 2660 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2661 2662 switch (w->type) { 2663 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2664 typestr = "audio output"; 2665 break; 2666 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2667 typestr = "audio input"; 2668 break; 2669 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2670 typestr = "audio mixer"; 2671 break; 2672 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2673 typestr = "audio selector"; 2674 break; 2675 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2676 typestr = "pin"; 2677 break; 2678 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2679 typestr = "power widget"; 2680 break; 2681 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2682 typestr = "volume widget"; 2683 break; 2684 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2685 typestr = "beep widget"; 2686 break; 2687 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2688 typestr = "vendor widget"; 2689 break; 2690 default: 2691 typestr = "unknown type"; 2692 break; 2693 } 2694 2695 strlcpy(w->name, typestr, sizeof(w->name)); 2696 2697 hdac_widget_connection_parse(w); 2698 2699 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2700 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2701 w->param.outamp_cap = 2702 hdac_command(sc, 2703 HDA_CMD_GET_PARAMETER(cad, nid, 2704 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2705 else 2706 w->param.outamp_cap = 2707 w->devinfo->function.audio.outamp_cap; 2708 } else 2709 w->param.outamp_cap = 0; 2710 2711 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2712 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2713 w->param.inamp_cap = 2714 hdac_command(sc, 2715 HDA_CMD_GET_PARAMETER(cad, nid, 2716 HDA_PARAM_INPUT_AMP_CAP), cad); 2717 else 2718 w->param.inamp_cap = 2719 w->devinfo->function.audio.inamp_cap; 2720 } else 2721 w->param.inamp_cap = 0; 2722 2723 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2724 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2725 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2726 cap = hdac_command(sc, 2727 HDA_CMD_GET_PARAMETER(cad, nid, 2728 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2729 w->param.supp_stream_formats = (cap != 0) ? cap : 2730 w->devinfo->function.audio.supp_stream_formats; 2731 cap = hdac_command(sc, 2732 HDA_CMD_GET_PARAMETER(cad, nid, 2733 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2734 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2735 w->devinfo->function.audio.supp_pcm_size_rate; 2736 } else { 2737 w->param.supp_stream_formats = 2738 w->devinfo->function.audio.supp_stream_formats; 2739 w->param.supp_pcm_size_rate = 2740 w->devinfo->function.audio.supp_pcm_size_rate; 2741 } 2742 } else { 2743 w->param.supp_stream_formats = 0; 2744 w->param.supp_pcm_size_rate = 0; 2745 } 2746 2747 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2748 hdac_widget_pin_parse(w); 2749} 2750 2751static struct hdac_widget * 2752hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2753{ 2754 if (devinfo == NULL || devinfo->widget == NULL || 2755 nid < devinfo->startnode || nid >= devinfo->endnode) 2756 return (NULL); 2757 return (&devinfo->widget[nid - devinfo->startnode]); 2758} 2759 2760static __inline int 2761hda_poll_channel(struct hdac_chan *ch) 2762{ 2763 uint32_t sz, delta; 2764 volatile uint32_t ptr; 2765 2766 if (!(ch->flags & HDAC_CHN_RUNNING)) 2767 return (0); 2768 2769 sz = ch->blksz * ch->blkcnt; 2770 if (ch->dmapos != NULL) 2771 ptr = *(ch->dmapos); 2772 else 2773 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2774 ch->off + HDAC_SDLPIB); 2775 ch->ptr = ptr; 2776 ptr %= sz; 2777 ptr &= ~(ch->blksz - 1); 2778 delta = (sz + ptr - ch->prevptr) % sz; 2779 2780 if (delta < ch->blksz) 2781 return (0); 2782 2783 ch->prevptr = ptr; 2784 2785 return (1); 2786} 2787 2788static void 2789hda_poll_callback(void *arg) 2790{ 2791 struct hdac_softc *sc = arg; 2792 uint32_t trigger; 2793 int i, active = 0; 2794 2795 if (sc == NULL) 2796 return; 2797 2798 hdac_lock(sc); 2799 if (sc->polling == 0) { 2800 hdac_unlock(sc); 2801 return; 2802 } 2803 2804 trigger = 0; 2805 for (i = 0; i < sc->num_chans; i++) { 2806 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2807 continue; 2808 active = 1; 2809 if (hda_poll_channel(&sc->chans[i])) 2810 trigger |= (1 << i); 2811 } 2812 2813 /* XXX */ 2814 if (active) 2815 callout_reset(&sc->poll_hda, sc->poll_ticks, 2816 hda_poll_callback, sc); 2817 2818 hdac_unlock(sc); 2819 2820 for (i = 0; i < sc->num_chans; i++) { 2821 if (trigger & (1 << i)) 2822 chn_intr(sc->chans[i].c); 2823 } 2824} 2825 2826static int 2827hdac_rirb_flush(struct hdac_softc *sc) 2828{ 2829 struct hdac_rirb *rirb_base, *rirb; 2830 struct hdac_codec *codec; 2831 struct hdac_command_list *commands; 2832 nid_t cad; 2833 uint32_t resp; 2834 uint8_t rirbwp; 2835 int ret; 2836 2837 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2838 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2839#if 0 2840 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2841 BUS_DMASYNC_POSTREAD); 2842#endif 2843 2844 ret = 0; 2845 2846 while (sc->rirb_rp != rirbwp) { 2847 sc->rirb_rp++; 2848 sc->rirb_rp %= sc->rirb_size; 2849 rirb = &rirb_base[sc->rirb_rp]; 2850 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2851 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2852 sc->codecs[cad] == NULL) 2853 continue; 2854 resp = rirb->response; 2855 codec = sc->codecs[cad]; 2856 commands = codec->commands; 2857 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2858 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2859 ((resp >> 26) & 0xffff); 2860 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2861 } else if (commands != NULL && commands->num_commands > 0 && 2862 codec->responses_received < commands->num_commands) 2863 commands->responses[codec->responses_received++] = 2864 resp; 2865 ret++; 2866 } 2867 2868 return (ret); 2869} 2870 2871static int 2872hdac_unsolq_flush(struct hdac_softc *sc) 2873{ 2874 nid_t cad; 2875 uint32_t tag; 2876 int ret = 0; 2877 2878 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2879 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2880 while (sc->unsolq_rp != sc->unsolq_wp) { 2881 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2882 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2883 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2884 hdac_unsolicited_handler(sc->codecs[cad], tag); 2885 ret++; 2886 } 2887 sc->unsolq_st = HDAC_UNSOLQ_READY; 2888 } 2889 2890 return (ret); 2891} 2892 2893static void 2894hdac_poll_callback(void *arg) 2895{ 2896 struct hdac_softc *sc = arg; 2897 if (sc == NULL) 2898 return; 2899 2900 hdac_lock(sc); 2901 if (sc->polling == 0 || sc->poll_ival == 0) { 2902 hdac_unlock(sc); 2903 return; 2904 } 2905 if (hdac_rirb_flush(sc) != 0) 2906 hdac_unsolq_flush(sc); 2907 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2908 hdac_unlock(sc); 2909} 2910 2911static void 2912hdac_poll_reinit(struct hdac_softc *sc) 2913{ 2914 int i, pollticks, min = 1000000; 2915 struct hdac_chan *ch; 2916 2917 for (i = 0; i < sc->num_chans; i++) { 2918 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2919 continue; 2920 ch = &sc->chans[i]; 2921 pollticks = ((uint64_t)hz * ch->blksz) / 2922 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2923 pollticks >>= 1; 2924 if (pollticks > hz) 2925 pollticks = hz; 2926 if (pollticks < 1) { 2927 HDA_BOOTVERBOSE( 2928 device_printf(sc->dev, 2929 "%s: pollticks=%d < 1 !\n", 2930 __func__, pollticks); 2931 ); 2932 pollticks = 1; 2933 } 2934 if (min > pollticks) 2935 min = pollticks; 2936 } 2937 HDA_BOOTVERBOSE( 2938 device_printf(sc->dev, 2939 "%s: pollticks %d -> %d\n", 2940 __func__, sc->poll_ticks, min); 2941 ); 2942 sc->poll_ticks = min; 2943 if (min == 1000000) 2944 callout_stop(&sc->poll_hda); 2945 else 2946 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2947} 2948 2949static void 2950hdac_stream_stop(struct hdac_chan *ch) 2951{ 2952 struct hdac_softc *sc = ch->devinfo->codec->sc; 2953 uint32_t ctl; 2954 2955 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2956 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2957 HDAC_SDCTL_RUN); 2958 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2959 2960 ch->flags &= ~HDAC_CHN_RUNNING; 2961 2962 if (sc->polling != 0) 2963 hdac_poll_reinit(sc); 2964 2965 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2966 ctl &= ~(1 << (ch->off >> 5)); 2967 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2968} 2969 2970static void 2971hdac_stream_start(struct hdac_chan *ch) 2972{ 2973 struct hdac_softc *sc = ch->devinfo->codec->sc; 2974 uint32_t ctl; 2975 2976 ch->flags |= HDAC_CHN_RUNNING; 2977 2978 if (sc->polling != 0) 2979 hdac_poll_reinit(sc); 2980 2981 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2982 ctl |= 1 << (ch->off >> 5); 2983 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2984 2985 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2986 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2987 HDAC_SDCTL_RUN; 2988 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2989} 2990 2991static void 2992hdac_stream_reset(struct hdac_chan *ch) 2993{ 2994 struct hdac_softc *sc = ch->devinfo->codec->sc; 2995 int timeout = 1000; 2996 int to = timeout; 2997 uint32_t ctl; 2998 2999 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3000 ctl |= HDAC_SDCTL_SRST; 3001 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3002 do { 3003 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3004 if (ctl & HDAC_SDCTL_SRST) 3005 break; 3006 DELAY(10); 3007 } while (--to); 3008 if (!(ctl & HDAC_SDCTL_SRST)) { 3009 device_printf(sc->dev, "timeout in reset\n"); 3010 } 3011 ctl &= ~HDAC_SDCTL_SRST; 3012 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3013 to = timeout; 3014 do { 3015 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3016 if (!(ctl & HDAC_SDCTL_SRST)) 3017 break; 3018 DELAY(10); 3019 } while (--to); 3020 if (ctl & HDAC_SDCTL_SRST) 3021 device_printf(sc->dev, "can't reset!\n"); 3022} 3023 3024static void 3025hdac_stream_setid(struct hdac_chan *ch) 3026{ 3027 struct hdac_softc *sc = ch->devinfo->codec->sc; 3028 uint32_t ctl; 3029 3030 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3031 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3032 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3033 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3034} 3035 3036static void 3037hdac_bdl_setup(struct hdac_chan *ch) 3038{ 3039 struct hdac_softc *sc = ch->devinfo->codec->sc; 3040 struct hdac_bdle *bdle; 3041 uint64_t addr; 3042 uint32_t blksz, blkcnt; 3043 int i; 3044 3045 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3046 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3047 3048 blksz = ch->blksz; 3049 blkcnt = ch->blkcnt; 3050 3051 for (i = 0; i < blkcnt; i++, bdle++) { 3052 bdle->addrl = (uint32_t)addr; 3053 bdle->addrh = (uint32_t)(addr >> 32); 3054 bdle->len = blksz; 3055 bdle->ioc = 1; 3056 addr += blksz; 3057 } 3058 3059 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3060 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3061 addr = ch->bdl_dma.dma_paddr; 3062 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3063 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3064 if (ch->dmapos != NULL && 3065 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3066 addr = sc->pos_dma.dma_paddr; 3067 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3068 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3069 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3070 } 3071} 3072 3073static int 3074hdac_bdl_alloc(struct hdac_chan *ch) 3075{ 3076 struct hdac_softc *sc = ch->devinfo->codec->sc; 3077 int rc; 3078 3079 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3080 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3081 if (rc) { 3082 device_printf(sc->dev, "can't alloc bdl\n"); 3083 return (rc); 3084 } 3085 3086 return (0); 3087} 3088 3089static void 3090hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3091 int index, int lmute, int rmute, 3092 int left, int right, int dir) 3093{ 3094 uint16_t v = 0; 3095 3096 if (sc == NULL) 3097 return; 3098 3099 if (left != right || lmute != rmute) { 3100 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3101 (lmute << 7) | left; 3102 hdac_command(sc, 3103 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3104 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3105 (rmute << 7) | right; 3106 } else 3107 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3108 (lmute << 7) | left; 3109 3110 hdac_command(sc, 3111 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3112} 3113 3114static void 3115hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3116 int left, int right) 3117{ 3118 struct hdac_softc *sc; 3119 nid_t nid, cad; 3120 int lmute, rmute; 3121 3122 sc = ctl->widget->devinfo->codec->sc; 3123 cad = ctl->widget->devinfo->codec->cad; 3124 nid = ctl->widget->nid; 3125 3126 /* Save new values if valid. */ 3127 if (mute != HDA_AMP_MUTE_DEFAULT) 3128 ctl->muted = mute; 3129 if (left != HDA_AMP_VOL_DEFAULT) 3130 ctl->left = left; 3131 if (right != HDA_AMP_VOL_DEFAULT) 3132 ctl->right = right; 3133 /* Prepare effective values */ 3134 if (ctl->forcemute) { 3135 lmute = 1; 3136 rmute = 1; 3137 left = 0; 3138 right = 0; 3139 } else { 3140 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3141 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3142 left = ctl->left; 3143 right = ctl->right; 3144 } 3145 /* Apply effective values */ 3146 if (ctl->dir & HDA_CTL_OUT) 3147 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3148 lmute, rmute, left, right, 0); 3149 if (ctl->dir & HDA_CTL_IN) 3150 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3151 lmute, rmute, left, right, 1); 3152} 3153 3154static void 3155hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3156{ 3157 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3158 return; 3159 hdac_command(w->devinfo->codec->sc, 3160 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3161 w->nid, index), w->devinfo->codec->cad); 3162 w->selconn = index; 3163} 3164 3165 3166/**************************************************************************** 3167 * uint32_t hdac_command_sendone_internal 3168 * 3169 * Wrapper function that sends only one command to a given codec 3170 ****************************************************************************/ 3171static uint32_t 3172hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3173{ 3174 struct hdac_command_list cl; 3175 uint32_t response = HDAC_INVALID; 3176 3177 if (!hdac_lockowned(sc)) 3178 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3179 cl.num_commands = 1; 3180 cl.verbs = &verb; 3181 cl.responses = &response; 3182 3183 hdac_command_send_internal(sc, &cl, cad); 3184 3185 return (response); 3186} 3187 3188/**************************************************************************** 3189 * hdac_command_send_internal 3190 * 3191 * Send a command list to the codec via the corb. We queue as much verbs as 3192 * we can and msleep on the codec. When the interrupt get the responses 3193 * back from the rirb, it will wake us up so we can queue the remaining verbs 3194 * if any. 3195 ****************************************************************************/ 3196static void 3197hdac_command_send_internal(struct hdac_softc *sc, 3198 struct hdac_command_list *commands, nid_t cad) 3199{ 3200 struct hdac_codec *codec; 3201 int corbrp; 3202 uint32_t *corb; 3203 int timeout; 3204 int retry = 10; 3205 struct hdac_rirb *rirb_base; 3206 3207 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3208 commands->num_commands < 1) 3209 return; 3210 3211 codec = sc->codecs[cad]; 3212 codec->commands = commands; 3213 codec->responses_received = 0; 3214 codec->verbs_sent = 0; 3215 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3216 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3217 3218 do { 3219 if (codec->verbs_sent != commands->num_commands) { 3220 /* Queue as many verbs as possible */ 3221 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3222#if 0 3223 bus_dmamap_sync(sc->corb_dma.dma_tag, 3224 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3225#endif 3226 while (codec->verbs_sent != commands->num_commands && 3227 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3228 sc->corb_wp++; 3229 sc->corb_wp %= sc->corb_size; 3230 corb[sc->corb_wp] = 3231 commands->verbs[codec->verbs_sent++]; 3232 } 3233 3234 /* Send the verbs to the codecs */ 3235#if 0 3236 bus_dmamap_sync(sc->corb_dma.dma_tag, 3237 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3238#endif 3239 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3240 } 3241 3242 timeout = 1000; 3243 while (hdac_rirb_flush(sc) == 0 && --timeout) 3244 DELAY(10); 3245 } while ((codec->verbs_sent != commands->num_commands || 3246 codec->responses_received != commands->num_commands) && --retry); 3247 3248 if (retry == 0) 3249 device_printf(sc->dev, 3250 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3251 __func__, commands->num_commands, codec->verbs_sent, 3252 codec->responses_received); 3253 3254 codec->commands = NULL; 3255 codec->responses_received = 0; 3256 codec->verbs_sent = 0; 3257 3258 hdac_unsolq_flush(sc); 3259} 3260 3261 3262/**************************************************************************** 3263 * Device Methods 3264 ****************************************************************************/ 3265 3266/**************************************************************************** 3267 * int hdac_probe(device_t) 3268 * 3269 * Probe for the presence of an hdac. If none is found, check for a generic 3270 * match using the subclass of the device. 3271 ****************************************************************************/ 3272static int 3273hdac_probe(device_t dev) 3274{ 3275 int i, result; 3276 uint32_t model; 3277 uint16_t class, subclass; 3278 char desc[64]; 3279 3280 model = (uint32_t)pci_get_device(dev) << 16; 3281 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3282 class = pci_get_class(dev); 3283 subclass = pci_get_subclass(dev); 3284 3285 bzero(desc, sizeof(desc)); 3286 result = ENXIO; 3287 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3288 if (hdac_devices[i].model == model) { 3289 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3290 result = BUS_PROBE_DEFAULT; 3291 break; 3292 } 3293 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3294 class == PCIC_MULTIMEDIA && 3295 subclass == PCIS_MULTIMEDIA_HDA) { 3296 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3297 result = BUS_PROBE_GENERIC; 3298 break; 3299 } 3300 } 3301 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3302 subclass == PCIS_MULTIMEDIA_HDA) { 3303 strlcpy(desc, "Generic", sizeof(desc)); 3304 result = BUS_PROBE_GENERIC; 3305 } 3306 if (result != ENXIO) { 3307 strlcat(desc, " High Definition Audio Controller", 3308 sizeof(desc)); 3309 device_set_desc_copy(dev, desc); 3310 } 3311 3312 return (result); 3313} 3314 3315static void * 3316hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3317 struct pcm_channel *c, int dir) 3318{ 3319 struct hdac_pcm_devinfo *pdevinfo = data; 3320 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3321 struct hdac_softc *sc = devinfo->codec->sc; 3322 struct hdac_chan *ch; 3323 int i, ord = 0, chid; 3324 3325 hdac_lock(sc); 3326 3327 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3328 ch = &sc->chans[chid]; 3329 for (i = 0; i < sc->num_chans && i < chid; i++) { 3330 if (ch->dir == sc->chans[i].dir) 3331 ord++; 3332 } 3333 if (dir == PCMDIR_PLAY) { 3334 ch->off = (sc->num_iss + ord) << 5; 3335 } else { 3336 ch->off = ord << 5; 3337 } 3338 3339 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3340 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3341 ch->pcmrates[0] = 48000; 3342 ch->pcmrates[1] = 0; 3343 } 3344 if (sc->pos_dma.dma_vaddr != NULL) 3345 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3346 (sc->streamcnt * 8)); 3347 else 3348 ch->dmapos = NULL; 3349 ch->sid = ++sc->streamcnt; 3350 ch->dir = dir; 3351 ch->b = b; 3352 ch->c = c; 3353 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3354 ch->blkcnt = pdevinfo->chan_blkcnt; 3355 hdac_unlock(sc); 3356 3357 if (hdac_bdl_alloc(ch) != 0) { 3358 ch->blkcnt = 0; 3359 return (NULL); 3360 } 3361 3362 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3363 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3364 pdevinfo->chan_size) != 0) 3365 return (NULL); 3366 3367 return (ch); 3368} 3369 3370static int 3371hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3372{ 3373 struct hdac_chan *ch = data; 3374 int i; 3375 3376 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3377 if (format == ch->caps.fmtlist[i]) { 3378 ch->fmt = format; 3379 return (0); 3380 } 3381 } 3382 3383 return (EINVAL); 3384} 3385 3386static uint32_t 3387hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3388{ 3389 struct hdac_chan *ch = data; 3390 uint32_t spd = 0, threshold; 3391 int i; 3392 3393 for (i = 0; ch->pcmrates[i] != 0; i++) { 3394 spd = ch->pcmrates[i]; 3395 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3396 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3397 if (speed < threshold) 3398 break; 3399 } 3400 3401 if (spd == 0) /* impossible */ 3402 ch->spd = 48000; 3403 else 3404 ch->spd = spd; 3405 3406 return (ch->spd); 3407} 3408 3409static void 3410hdac_stream_setup(struct hdac_chan *ch) 3411{ 3412 struct hdac_softc *sc = ch->devinfo->codec->sc; 3413 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3414 struct hdac_widget *w; 3415 int i, chn, totalchn, c; 3416 nid_t cad = ch->devinfo->codec->cad; 3417 uint16_t fmt, dfmt; 3418 3419 HDA_BOOTHVERBOSE( 3420 device_printf(ch->pdevinfo->dev, 3421 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3422 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3423 ch->fmt, ch->spd); 3424 ); 3425 fmt = 0; 3426 if (ch->fmt & AFMT_S16_LE) 3427 fmt |= ch->bit16 << 4; 3428 else if (ch->fmt & AFMT_S32_LE) 3429 fmt |= ch->bit32 << 4; 3430 else 3431 fmt |= 1 << 4; 3432 3433 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3434 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3435 fmt |= hda_rate_tab[i].base; 3436 fmt |= hda_rate_tab[i].mul; 3437 fmt |= hda_rate_tab[i].div; 3438 break; 3439 } 3440 } 3441 3442 totalchn = AFMT_CHANNEL(ch->fmt); 3443 if (totalchn > 1) 3444 fmt |= 1; 3445 3446 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3447 3448 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3449 if (ch->fmt & AFMT_AC3) 3450 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3451 3452 chn = 0; 3453 for (i = 0; ch->io[i] != -1; i++) { 3454 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3455 if (w == NULL) 3456 continue; 3457 3458 if (as->hpredir >= 0 && i == as->pincnt) 3459 chn = 0; 3460 HDA_BOOTHVERBOSE( 3461 device_printf(ch->pdevinfo->dev, 3462 "PCMDIR_%s: Stream setup nid=%d: " 3463 "fmt=0x%04x, dfmt=0x%04x\n", 3464 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3465 ch->io[i], fmt, dfmt); 3466 ); 3467 hdac_command(sc, 3468 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3469 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3470 hdac_command(sc, 3471 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3472 cad); 3473 } 3474 /* If HP redirection is enabled, but failed to use same 3475 DAC make last DAC one to duplicate first one. */ 3476 if (as->hpredir >= 0 && i == as->pincnt) { 3477 c = (ch->sid << 4); 3478 } else if (chn >= totalchn) { 3479 /* This is until OSS will support multichannel. 3480 Should be: c = 0; to disable unused DAC */ 3481 c = (ch->sid << 4); 3482 }else { 3483 c = (ch->sid << 4) | chn; 3484 } 3485 hdac_command(sc, 3486 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3487#if 0 3488 hdac_command(sc, 3489 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3490 hdac_command(sc, 3491 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3492 hdac_command(sc, 3493 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3494#endif 3495 chn += 3496 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3497 2 : 1; 3498 } 3499} 3500 3501static int 3502hdac_channel_setfragments(kobj_t obj, void *data, 3503 uint32_t blksz, uint32_t blkcnt) 3504{ 3505 struct hdac_chan *ch = data; 3506 struct hdac_softc *sc = ch->devinfo->codec->sc; 3507 3508 blksz &= HDA_BLK_ALIGN; 3509 3510 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3511 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3512 if (blksz < HDA_BLK_MIN) 3513 blksz = HDA_BLK_MIN; 3514 if (blkcnt > HDA_BDL_MAX) 3515 blkcnt = HDA_BDL_MAX; 3516 if (blkcnt < HDA_BDL_MIN) 3517 blkcnt = HDA_BDL_MIN; 3518 3519 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3520 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3521 blkcnt >>= 1; 3522 else if ((blksz >> 1) >= HDA_BLK_MIN) 3523 blksz >>= 1; 3524 else 3525 break; 3526 } 3527 3528 if ((sndbuf_getblksz(ch->b) != blksz || 3529 sndbuf_getblkcnt(ch->b) != blkcnt) && 3530 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3531 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3532 __func__, blksz, blkcnt); 3533 3534 ch->blksz = sndbuf_getblksz(ch->b); 3535 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3536 3537 return (0); 3538} 3539 3540static uint32_t 3541hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3542{ 3543 struct hdac_chan *ch = data; 3544 3545 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3546 3547 return (ch->blksz); 3548} 3549 3550static void 3551hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3552{ 3553 struct hdac_devinfo *devinfo = ch->devinfo; 3554 struct hdac_widget *w; 3555 nid_t cad = devinfo->codec->cad; 3556 int i; 3557 3558 hdac_stream_stop(ch); 3559 3560 for (i = 0; ch->io[i] != -1; i++) { 3561 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3562 if (w == NULL) 3563 continue; 3564 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3565 hdac_command(sc, 3566 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3567 cad); 3568 } 3569 hdac_command(sc, 3570 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3571 0), cad); 3572 } 3573} 3574 3575static void 3576hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3577{ 3578 ch->ptr = 0; 3579 ch->prevptr = 0; 3580 hdac_stream_stop(ch); 3581 hdac_stream_reset(ch); 3582 hdac_bdl_setup(ch); 3583 hdac_stream_setid(ch); 3584 hdac_stream_setup(ch); 3585 hdac_stream_start(ch); 3586} 3587 3588static int 3589hdac_channel_trigger(kobj_t obj, void *data, int go) 3590{ 3591 struct hdac_chan *ch = data; 3592 struct hdac_softc *sc = ch->devinfo->codec->sc; 3593 3594 if (!PCMTRIG_COMMON(go)) 3595 return (0); 3596 3597 hdac_lock(sc); 3598 switch (go) { 3599 case PCMTRIG_START: 3600 hdac_channel_start(sc, ch); 3601 break; 3602 case PCMTRIG_STOP: 3603 case PCMTRIG_ABORT: 3604 hdac_channel_stop(sc, ch); 3605 break; 3606 default: 3607 break; 3608 } 3609 hdac_unlock(sc); 3610 3611 return (0); 3612} 3613 3614static uint32_t 3615hdac_channel_getptr(kobj_t obj, void *data) 3616{ 3617 struct hdac_chan *ch = data; 3618 struct hdac_softc *sc = ch->devinfo->codec->sc; 3619 uint32_t ptr; 3620 3621 hdac_lock(sc); 3622 if (sc->polling != 0) 3623 ptr = ch->ptr; 3624 else if (ch->dmapos != NULL) 3625 ptr = *(ch->dmapos); 3626 else 3627 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3628 hdac_unlock(sc); 3629 3630 /* 3631 * Round to available space and force 128 bytes aligment. 3632 */ 3633 ptr %= ch->blksz * ch->blkcnt; 3634 ptr &= HDA_BLK_ALIGN; 3635 3636 return (ptr); 3637} 3638 3639static struct pcmchan_caps * 3640hdac_channel_getcaps(kobj_t obj, void *data) 3641{ 3642 return (&((struct hdac_chan *)data)->caps); 3643} 3644 3645static kobj_method_t hdac_channel_methods[] = { 3646 KOBJMETHOD(channel_init, hdac_channel_init), 3647 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3648 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3649 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3650 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3651 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3652 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3653 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3654 KOBJMETHOD_END 3655}; 3656CHANNEL_DECLARE(hdac_channel); 3657 3658static int 3659hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3660{ 3661 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3662 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3663 struct hdac_softc *sc = devinfo->codec->sc; 3664 struct hdac_widget *w, *cw; 3665 struct hdac_audio_ctl *ctl; 3666 uint32_t mask, recmask, id; 3667 int i, j, softpcmvol; 3668 3669 hdac_lock(sc); 3670 3671 /* Make sure that in case of soft volume it won't stay muted. */ 3672 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3673 pdevinfo->left[i] = 100; 3674 pdevinfo->right[i] = 100; 3675 } 3676 3677 mask = 0; 3678 recmask = 0; 3679 id = hdac_codec_id(devinfo->codec); 3680 3681 /* Declate EAPD as ogain control. */ 3682 if (pdevinfo->play >= 0) { 3683 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3684 w = hdac_widget_get(devinfo, i); 3685 if (w == NULL || w->enable == 0) 3686 continue; 3687 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3688 w->param.eapdbtl == HDAC_INVALID || 3689 w->bindas != sc->chans[pdevinfo->play].as) 3690 continue; 3691 mask |= SOUND_MASK_OGAIN; 3692 break; 3693 } 3694 } 3695 3696 /* Declare volume controls assigned to this association. */ 3697 i = 0; 3698 ctl = NULL; 3699 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3700 if (ctl->enable == 0) 3701 continue; 3702 if ((pdevinfo->play >= 0 && 3703 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3704 (pdevinfo->rec >= 0 && 3705 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3706 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3707 mask |= ctl->ossmask; 3708 } 3709 3710 /* Declare record sources available to this association. */ 3711 if (pdevinfo->rec >= 0) { 3712 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3713 for (i = 0; ch->io[i] != -1; i++) { 3714 w = hdac_widget_get(devinfo, ch->io[i]); 3715 if (w == NULL || w->enable == 0) 3716 continue; 3717 for (j = 0; j < w->nconns; j++) { 3718 if (w->connsenable[j] == 0) 3719 continue; 3720 cw = hdac_widget_get(devinfo, w->conns[j]); 3721 if (cw == NULL || cw->enable == 0) 3722 continue; 3723 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3724 cw->bindas != -2) 3725 continue; 3726 recmask |= cw->ossmask; 3727 } 3728 } 3729 } 3730 3731 /* Declare soft PCM volume if needed. */ 3732 if (pdevinfo->play >= 0) { 3733 ctl = NULL; 3734 if ((mask & SOUND_MASK_PCM) == 0 || 3735 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3736 softpcmvol = 1; 3737 mask |= SOUND_MASK_PCM; 3738 } else { 3739 softpcmvol = 0; 3740 i = 0; 3741 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3742 if (ctl->enable == 0) 3743 continue; 3744 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3745 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3746 continue; 3747 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3748 continue; 3749 if (ctl->step > 0) 3750 break; 3751 } 3752 } 3753 3754 if (softpcmvol == 1 || ctl == NULL) { 3755 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3756 HDA_BOOTVERBOSE( 3757 device_printf(pdevinfo->dev, 3758 "%s Soft PCM volume\n", 3759 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3760 ); 3761 } 3762 } 3763 3764 /* Declare master volume if needed. */ 3765 if (pdevinfo->play >= 0) { 3766 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3767 SOUND_MASK_PCM) { 3768 mask |= SOUND_MASK_VOLUME; 3769 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3770 SOUND_MASK_PCM); 3771 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3772 SOUND_MIXER_NONE); 3773 HDA_BOOTVERBOSE( 3774 device_printf(pdevinfo->dev, 3775 "Forcing master volume with PCM\n"); 3776 ); 3777 } 3778 } 3779 3780 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3781 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3782 3783 mix_setrecdevs(m, recmask); 3784 mix_setdevs(m, mask); 3785 3786 hdac_unlock(sc); 3787 3788 return (0); 3789} 3790 3791static int 3792hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3793 unsigned left, unsigned right) 3794{ 3795 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3796 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3797 struct hdac_softc *sc = devinfo->codec->sc; 3798 struct hdac_widget *w; 3799 struct hdac_audio_ctl *ctl; 3800 uint32_t mute; 3801 int lvol, rvol; 3802 int i, j; 3803 3804 hdac_lock(sc); 3805 /* Save new values. */ 3806 pdevinfo->left[dev] = left; 3807 pdevinfo->right[dev] = right; 3808 3809 /* 'ogain' is the special case implemented with EAPD. */ 3810 if (dev == SOUND_MIXER_OGAIN) { 3811 uint32_t orig; 3812 w = NULL; 3813 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3814 w = hdac_widget_get(devinfo, i); 3815 if (w == NULL || w->enable == 0) 3816 continue; 3817 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3818 w->param.eapdbtl == HDAC_INVALID) 3819 continue; 3820 break; 3821 } 3822 if (i >= devinfo->endnode) { 3823 hdac_unlock(sc); 3824 return (-1); 3825 } 3826 orig = w->param.eapdbtl; 3827 if (left == 0) 3828 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3829 else 3830 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3831 if (orig != w->param.eapdbtl) { 3832 uint32_t val; 3833 3834 val = w->param.eapdbtl; 3835 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3836 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3837 hdac_command(sc, 3838 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3839 w->nid, val), devinfo->codec->cad); 3840 } 3841 hdac_unlock(sc); 3842 return (left | (left << 8)); 3843 } 3844 3845 /* Recalculate all controls related to this OSS device. */ 3846 i = 0; 3847 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3848 if (ctl->enable == 0 || 3849 !(ctl->ossmask & (1 << dev))) 3850 continue; 3851 if (!((pdevinfo->play >= 0 && 3852 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3853 (pdevinfo->rec >= 0 && 3854 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3855 ctl->widget->bindas == -2)) 3856 continue; 3857 3858 lvol = 100; 3859 rvol = 100; 3860 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3861 if (ctl->ossmask & (1 << j)) { 3862 lvol = lvol * pdevinfo->left[j] / 100; 3863 rvol = rvol * pdevinfo->right[j] / 100; 3864 } 3865 } 3866 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3867 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3868 lvol = (lvol * ctl->step + 50) / 100; 3869 rvol = (rvol * ctl->step + 50) / 100; 3870 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3871 } 3872 hdac_unlock(sc); 3873 3874 return (left | (right << 8)); 3875} 3876 3877/* 3878 * Commutate specified record source. 3879 */ 3880static uint32_t 3881hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3882{ 3883 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3884 struct hdac_widget *w, *cw; 3885 struct hdac_audio_ctl *ctl; 3886 char buf[64]; 3887 int i, muted; 3888 uint32_t res = 0; 3889 3890 if (depth > HDA_PARSE_MAXDEPTH) 3891 return (0); 3892 3893 w = hdac_widget_get(devinfo, nid); 3894 if (w == NULL || w->enable == 0) 3895 return (0); 3896 3897 for (i = 0; i < w->nconns; i++) { 3898 if (w->connsenable[i] == 0) 3899 continue; 3900 cw = hdac_widget_get(devinfo, w->conns[i]); 3901 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3902 continue; 3903 /* Call recursively to trace signal to it's source if needed. */ 3904 if ((src & cw->ossmask) != 0) { 3905 if (cw->ossdev < 0) { 3906 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3907 w->conns[i], depth + 1); 3908 } else { 3909 res |= cw->ossmask; 3910 } 3911 } 3912 /* We have two special cases: mixers and others (selectors). */ 3913 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3914 ctl = hdac_audio_ctl_amp_get(devinfo, 3915 w->nid, HDA_CTL_IN, i, 1); 3916 if (ctl == NULL) 3917 continue; 3918 /* If we have input control on this node mute them 3919 * according to requested sources. */ 3920 muted = (src & cw->ossmask) ? 0 : 1; 3921 if (muted != ctl->forcemute) { 3922 ctl->forcemute = muted; 3923 hdac_audio_ctl_amp_set(ctl, 3924 HDA_AMP_MUTE_DEFAULT, 3925 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3926 } 3927 HDA_BOOTHVERBOSE( 3928 device_printf(pdevinfo->dev, 3929 "Recsel (%s): nid %d source %d %s\n", 3930 hdac_audio_ctl_ossmixer_mask2allname( 3931 src, buf, sizeof(buf)), 3932 nid, i, muted?"mute":"unmute"); 3933 ); 3934 } else { 3935 if (w->nconns == 1) 3936 break; 3937 if ((src & cw->ossmask) == 0) 3938 continue; 3939 /* If we found requested source - select it and exit. */ 3940 hdac_widget_connection_select(w, i); 3941 HDA_BOOTHVERBOSE( 3942 device_printf(pdevinfo->dev, 3943 "Recsel (%s): nid %d source %d select\n", 3944 hdac_audio_ctl_ossmixer_mask2allname( 3945 src, buf, sizeof(buf)), 3946 nid, i); 3947 ); 3948 break; 3949 } 3950 } 3951 return (res); 3952} 3953 3954static uint32_t 3955hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3956{ 3957 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3958 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3959 struct hdac_widget *w; 3960 struct hdac_softc *sc = devinfo->codec->sc; 3961 struct hdac_chan *ch; 3962 int i; 3963 uint32_t ret = 0xffffffff; 3964 3965 hdac_lock(sc); 3966 3967 /* Commutate requested recsrc for each ADC. */ 3968 ch = &sc->chans[pdevinfo->rec]; 3969 for (i = 0; ch->io[i] != -1; i++) { 3970 w = hdac_widget_get(devinfo, ch->io[i]); 3971 if (w == NULL || w->enable == 0) 3972 continue; 3973 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3974 } 3975 3976 hdac_unlock(sc); 3977 3978 return ((ret == 0xffffffff)? 0 : ret); 3979} 3980 3981static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3982 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3983 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3984 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3985 KOBJMETHOD_END 3986}; 3987MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3988 3989static void 3990hdac_unsolq_task(void *context, int pending) 3991{ 3992 struct hdac_softc *sc; 3993 3994 sc = (struct hdac_softc *)context; 3995 3996 hdac_lock(sc); 3997 hdac_unsolq_flush(sc); 3998 hdac_unlock(sc); 3999} 4000 4001/**************************************************************************** 4002 * int hdac_attach(device_t) 4003 * 4004 * Attach the device into the kernel. Interrupts usually won't be enabled 4005 * when this function is called. Setup everything that doesn't require 4006 * interrupts and defer probing of codecs until interrupts are enabled. 4007 ****************************************************************************/ 4008static int 4009hdac_attach(device_t dev) 4010{ 4011 struct hdac_softc *sc; 4012 int result; 4013 int i, devid = -1; 4014 uint32_t model; 4015 uint16_t class, subclass; 4016 uint16_t vendor; 4017 uint8_t v; 4018 4019 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4020 4021 model = (uint32_t)pci_get_device(dev) << 16; 4022 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4023 class = pci_get_class(dev); 4024 subclass = pci_get_subclass(dev); 4025 4026 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4027 if (hdac_devices[i].model == model) { 4028 devid = i; 4029 break; 4030 } 4031 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4032 class == PCIC_MULTIMEDIA && 4033 subclass == PCIS_MULTIMEDIA_HDA) { 4034 devid = i; 4035 break; 4036 } 4037 } 4038 4039 sc = device_get_softc(dev); 4040 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4041 sc->dev = dev; 4042 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4043 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4044 vendor = pci_get_vendor(dev); 4045 4046 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4047 /* Screw nx6325 - subdevice/subvendor swapped */ 4048 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4049 } 4050 4051 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4052 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4053 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4054 4055 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4056 4057 sc->poll_ticks = 1000000; 4058 sc->poll_ival = HDAC_POLL_INTERVAL; 4059 if (resource_int_value(device_get_name(dev), 4060 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4061 sc->polling = 1; 4062 else 4063 sc->polling = 0; 4064 4065 sc->hdabus = NULL; 4066 for (i = 0; i < HDAC_CODEC_MAX; i++) 4067 sc->codecs[i] = NULL; 4068 4069 pci_enable_busmaster(dev); 4070 4071 if (vendor == INTEL_VENDORID) { 4072 /* TCSEL -> TC0 */ 4073 v = pci_read_config(dev, 0x44, 1); 4074 pci_write_config(dev, 0x44, v & 0xf8, 1); 4075 HDA_BOOTHVERBOSE( 4076 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4077 pci_read_config(dev, 0x44, 1)); 4078 ); 4079 } 4080 4081 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4082 sc->flags &= ~HDAC_F_MSI; 4083 else 4084 sc->flags |= HDAC_F_MSI; 4085 if (resource_int_value(device_get_name(dev), 4086 device_get_unit(dev), "msi", &i) == 0) { 4087 if (i == 0) 4088 sc->flags &= ~HDAC_F_MSI; 4089 else 4090 sc->flags |= HDAC_F_MSI; 4091 } 4092 4093#if defined(__i386__) || defined(__amd64__) 4094 sc->flags |= HDAC_F_DMA_NOCACHE; 4095 4096 if (resource_int_value(device_get_name(dev), 4097 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4098#else 4099 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4100#endif 4101 /* 4102 * Try to enable PCIe snoop to avoid messing around with 4103 * uncacheable DMA attribute. Since PCIe snoop register 4104 * config is pretty much vendor specific, there are no 4105 * general solutions on how to enable it, forcing us (even 4106 * Microsoft) to enable uncacheable or write combined DMA 4107 * by default. 4108 * 4109 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4110 */ 4111 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4112 if (hdac_pcie_snoop[i].vendor != vendor) 4113 continue; 4114 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4115 if (hdac_pcie_snoop[i].reg == 0x00) 4116 break; 4117 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4118 if ((v & hdac_pcie_snoop[i].enable) == 4119 hdac_pcie_snoop[i].enable) 4120 break; 4121 v &= hdac_pcie_snoop[i].mask; 4122 v |= hdac_pcie_snoop[i].enable; 4123 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4124 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4125 if ((v & hdac_pcie_snoop[i].enable) != 4126 hdac_pcie_snoop[i].enable) { 4127 HDA_BOOTVERBOSE( 4128 device_printf(dev, 4129 "WARNING: Failed to enable PCIe " 4130 "snoop!\n"); 4131 ); 4132#if defined(__i386__) || defined(__amd64__) 4133 sc->flags |= HDAC_F_DMA_NOCACHE; 4134#endif 4135 } 4136 break; 4137 } 4138#if defined(__i386__) || defined(__amd64__) 4139 } 4140#endif 4141 4142 HDA_BOOTHVERBOSE( 4143 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4144 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4145 "Uncacheable" : "PCIe snoop", vendor); 4146 ); 4147 4148 /* Allocate resources */ 4149 result = hdac_mem_alloc(sc); 4150 if (result != 0) 4151 goto hdac_attach_fail; 4152 result = hdac_irq_alloc(sc); 4153 if (result != 0) 4154 goto hdac_attach_fail; 4155 4156 /* Get Capabilities */ 4157 result = hdac_get_capabilities(sc); 4158 if (result != 0) 4159 goto hdac_attach_fail; 4160 4161 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4162 sc->support_64bit = 0; 4163 4164 /* Allocate CORB and RIRB dma memory */ 4165 result = hdac_dma_alloc(sc, &sc->corb_dma, 4166 sc->corb_size * sizeof(uint32_t)); 4167 if (result != 0) 4168 goto hdac_attach_fail; 4169 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4170 sc->rirb_size * sizeof(struct hdac_rirb)); 4171 if (result != 0) 4172 goto hdac_attach_fail; 4173 4174 result = bus_dma_tag_create( 4175 bus_get_dma_tag(sc->dev), /* parent */ 4176 HDAC_DMA_ALIGNMENT, /* alignment */ 4177 0, /* boundary */ 4178 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4179 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4180 BUS_SPACE_MAXADDR, /* highaddr */ 4181 NULL, /* filtfunc */ 4182 NULL, /* fistfuncarg */ 4183 HDA_BUFSZ_MAX, /* maxsize */ 4184 1, /* nsegments */ 4185 HDA_BUFSZ_MAX, /* maxsegsz */ 4186 0, /* flags */ 4187 NULL, /* lockfunc */ 4188 NULL, /* lockfuncarg */ 4189 &sc->chan_dmat); /* dmat */ 4190 if (result != 0) { 4191 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4192 __func__, result); 4193 goto hdac_attach_fail; 4194 } 4195 4196 /* Quiesce everything */ 4197 HDA_BOOTHVERBOSE( 4198 device_printf(dev, "Reset controller...\n"); 4199 ); 4200 hdac_reset(sc, 1); 4201 4202 /* Initialize the CORB and RIRB */ 4203 hdac_corb_init(sc); 4204 hdac_rirb_init(sc); 4205 4206 /* Defer remaining of initialization until interrupts are enabled */ 4207 sc->intrhook.ich_func = hdac_attach2; 4208 sc->intrhook.ich_arg = (void *)sc; 4209 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4210 sc->intrhook.ich_func = NULL; 4211 hdac_attach2((void *)sc); 4212 } 4213 4214 return (0); 4215 4216hdac_attach_fail: 4217 hdac_irq_free(sc); 4218 hdac_dma_free(sc, &sc->rirb_dma); 4219 hdac_dma_free(sc, &sc->corb_dma); 4220 hdac_mem_free(sc); 4221 snd_mtxfree(sc->lock); 4222 free(sc, M_DEVBUF); 4223 4224 return (ENXIO); 4225} 4226 4227static void 4228hdac_audio_parse(struct hdac_devinfo *devinfo) 4229{ 4230 struct hdac_codec *codec = devinfo->codec; 4231 struct hdac_softc *sc = codec->sc; 4232 struct hdac_widget *w; 4233 uint32_t res; 4234 int i; 4235 nid_t cad, nid; 4236 4237 cad = devinfo->codec->cad; 4238 nid = devinfo->nid; 4239 4240 res = hdac_command(sc, 4241 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4242 devinfo->function.audio.gpio = res; 4243 4244 HDA_BOOTVERBOSE( 4245 device_printf(sc->dev, "GPIO: 0x%08x " 4246 "NumGPIO=%d NumGPO=%d " 4247 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4248 devinfo->function.audio.gpio, 4249 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4250 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4251 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4252 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4253 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4254 ); 4255 4256 res = hdac_command(sc, 4257 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4258 cad); 4259 devinfo->function.audio.supp_stream_formats = res; 4260 4261 res = hdac_command(sc, 4262 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4263 cad); 4264 devinfo->function.audio.supp_pcm_size_rate = res; 4265 4266 res = hdac_command(sc, 4267 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4268 cad); 4269 devinfo->function.audio.outamp_cap = res; 4270 4271 res = hdac_command(sc, 4272 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4273 cad); 4274 devinfo->function.audio.inamp_cap = res; 4275 4276 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4277 w = hdac_widget_get(devinfo, i); 4278 if (w == NULL) 4279 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4280 else { 4281 w->devinfo = devinfo; 4282 w->nid = i; 4283 w->enable = 1; 4284 w->selconn = -1; 4285 w->pflags = 0; 4286 w->ossdev = -1; 4287 w->bindas = -1; 4288 w->param.eapdbtl = HDAC_INVALID; 4289 hdac_widget_parse(w); 4290 } 4291 } 4292} 4293 4294static void 4295hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4296{ 4297 struct hdac_softc *sc = devinfo->codec->sc; 4298 struct hdac_audio_ctl *ctls; 4299 struct hdac_widget *w, *cw; 4300 int i, j, cnt, max, ocap, icap; 4301 int mute, offset, step, size; 4302 4303 /* XXX This is redundant */ 4304 max = 0; 4305 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4306 w = hdac_widget_get(devinfo, i); 4307 if (w == NULL || w->enable == 0) 4308 continue; 4309 if (w->param.outamp_cap != 0) 4310 max++; 4311 if (w->param.inamp_cap != 0) { 4312 switch (w->type) { 4313 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4314 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4315 for (j = 0; j < w->nconns; j++) { 4316 cw = hdac_widget_get(devinfo, 4317 w->conns[j]); 4318 if (cw == NULL || cw->enable == 0) 4319 continue; 4320 max++; 4321 } 4322 break; 4323 default: 4324 max++; 4325 break; 4326 } 4327 } 4328 } 4329 4330 devinfo->function.audio.ctlcnt = max; 4331 4332 if (max < 1) 4333 return; 4334 4335 ctls = (struct hdac_audio_ctl *)malloc( 4336 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4337 4338 if (ctls == NULL) { 4339 /* Blekh! */ 4340 device_printf(sc->dev, "unable to allocate ctls!\n"); 4341 devinfo->function.audio.ctlcnt = 0; 4342 return; 4343 } 4344 4345 cnt = 0; 4346 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4347 if (cnt >= max) { 4348 device_printf(sc->dev, "%s: Ctl overflow!\n", 4349 __func__); 4350 break; 4351 } 4352 w = hdac_widget_get(devinfo, i); 4353 if (w == NULL || w->enable == 0) 4354 continue; 4355 ocap = w->param.outamp_cap; 4356 icap = w->param.inamp_cap; 4357 if (ocap != 0) { 4358 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4359 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4360 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4361 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4362 /*if (offset > step) { 4363 HDA_BOOTVERBOSE( 4364 device_printf(sc->dev, 4365 "BUGGY outamp: nid=%d " 4366 "[offset=%d > step=%d]\n", 4367 w->nid, offset, step); 4368 ); 4369 offset = step; 4370 }*/ 4371 ctls[cnt].enable = 1; 4372 ctls[cnt].widget = w; 4373 ctls[cnt].mute = mute; 4374 ctls[cnt].step = step; 4375 ctls[cnt].size = size; 4376 ctls[cnt].offset = offset; 4377 ctls[cnt].left = offset; 4378 ctls[cnt].right = offset; 4379 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4380 w->waspin) 4381 ctls[cnt].ndir = HDA_CTL_IN; 4382 else 4383 ctls[cnt].ndir = HDA_CTL_OUT; 4384 ctls[cnt++].dir = HDA_CTL_OUT; 4385 } 4386 4387 if (icap != 0) { 4388 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4389 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4390 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4391 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4392 /*if (offset > step) { 4393 HDA_BOOTVERBOSE( 4394 device_printf(sc->dev, 4395 "BUGGY inamp: nid=%d " 4396 "[offset=%d > step=%d]\n", 4397 w->nid, offset, step); 4398 ); 4399 offset = step; 4400 }*/ 4401 switch (w->type) { 4402 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4403 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4404 for (j = 0; j < w->nconns; j++) { 4405 if (cnt >= max) { 4406 device_printf(sc->dev, 4407 "%s: Ctl overflow!\n", 4408 __func__); 4409 break; 4410 } 4411 cw = hdac_widget_get(devinfo, 4412 w->conns[j]); 4413 if (cw == NULL || cw->enable == 0) 4414 continue; 4415 ctls[cnt].enable = 1; 4416 ctls[cnt].widget = w; 4417 ctls[cnt].childwidget = cw; 4418 ctls[cnt].index = j; 4419 ctls[cnt].mute = mute; 4420 ctls[cnt].step = step; 4421 ctls[cnt].size = size; 4422 ctls[cnt].offset = offset; 4423 ctls[cnt].left = offset; 4424 ctls[cnt].right = offset; 4425 ctls[cnt].ndir = HDA_CTL_IN; 4426 ctls[cnt++].dir = HDA_CTL_IN; 4427 } 4428 break; 4429 default: 4430 if (cnt >= max) { 4431 device_printf(sc->dev, 4432 "%s: Ctl overflow!\n", 4433 __func__); 4434 break; 4435 } 4436 ctls[cnt].enable = 1; 4437 ctls[cnt].widget = w; 4438 ctls[cnt].mute = mute; 4439 ctls[cnt].step = step; 4440 ctls[cnt].size = size; 4441 ctls[cnt].offset = offset; 4442 ctls[cnt].left = offset; 4443 ctls[cnt].right = offset; 4444 if (w->type == 4445 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4446 ctls[cnt].ndir = HDA_CTL_OUT; 4447 else 4448 ctls[cnt].ndir = HDA_CTL_IN; 4449 ctls[cnt++].dir = HDA_CTL_IN; 4450 break; 4451 } 4452 } 4453 } 4454 4455 devinfo->function.audio.ctl = ctls; 4456} 4457 4458static void 4459hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4460{ 4461 struct hdac_softc *sc = devinfo->codec->sc; 4462 struct hdac_audio_as *as; 4463 struct hdac_widget *w; 4464 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4465 4466 /* Count present associations */ 4467 max = 0; 4468 for (j = 1; j < 16; j++) { 4469 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4470 w = hdac_widget_get(devinfo, i); 4471 if (w == NULL || w->enable == 0) 4472 continue; 4473 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4474 continue; 4475 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4476 != j) 4477 continue; 4478 max++; 4479 if (j != 15) /* There could be many 1-pin assocs #15 */ 4480 break; 4481 } 4482 } 4483 4484 devinfo->function.audio.ascnt = max; 4485 4486 if (max < 1) 4487 return; 4488 4489 as = (struct hdac_audio_as *)malloc( 4490 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4491 4492 if (as == NULL) { 4493 /* Blekh! */ 4494 device_printf(sc->dev, "unable to allocate assocs!\n"); 4495 devinfo->function.audio.ascnt = 0; 4496 return; 4497 } 4498 4499 for (i = 0; i < max; i++) { 4500 as[i].hpredir = -1; 4501 as[i].chan = -1; 4502 as[i].digital = 0; 4503 } 4504 4505 /* Scan associations skipping as=0. */ 4506 cnt = 0; 4507 for (j = 1; j < 16; j++) { 4508 first = 16; 4509 hpredir = 0; 4510 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4511 w = hdac_widget_get(devinfo, i); 4512 if (w == NULL || w->enable == 0) 4513 continue; 4514 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4515 continue; 4516 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4517 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4518 if (assoc != j) { 4519 continue; 4520 } 4521 KASSERT(cnt < max, 4522 ("%s: Associations owerflow (%d of %d)", 4523 __func__, cnt, max)); 4524 type = w->wclass.pin.config & 4525 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4526 /* Get pin direction. */ 4527 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4528 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4529 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4530 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4531 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4532 dir = HDA_CTL_OUT; 4533 else 4534 dir = HDA_CTL_IN; 4535 /* If this is a first pin - create new association. */ 4536 if (as[cnt].pincnt == 0) { 4537 as[cnt].enable = 1; 4538 as[cnt].index = j; 4539 as[cnt].dir = dir; 4540 } 4541 if (seq < first) 4542 first = seq; 4543 /* Check association correctness. */ 4544 if (as[cnt].pins[seq] != 0) { 4545 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4546 "in association %d! Disabling association.\n", 4547 __func__, seq, w->nid, j); 4548 as[cnt].enable = 0; 4549 } 4550 if (dir != as[cnt].dir) { 4551 device_printf(sc->dev, "%s: Pin %d has wrong " 4552 "direction for association %d! Disabling " 4553 "association.\n", 4554 __func__, w->nid, j); 4555 as[cnt].enable = 0; 4556 } 4557 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4558 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4559 as[cnt].digital = 3; 4560 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4561 as[cnt].digital = 2; 4562 else 4563 as[cnt].digital = 1; 4564 } 4565 /* Headphones with seq=15 may mean redirection. */ 4566 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4567 seq == 15) 4568 hpredir = 1; 4569 as[cnt].pins[seq] = w->nid; 4570 as[cnt].pincnt++; 4571 /* Association 15 is a multiple unassociated pins. */ 4572 if (j == 15) 4573 cnt++; 4574 } 4575 if (j != 15 && as[cnt].pincnt > 0) { 4576 if (hpredir && as[cnt].pincnt > 1) 4577 as[cnt].hpredir = first; 4578 cnt++; 4579 } 4580 } 4581 HDA_BOOTVERBOSE( 4582 device_printf(sc->dev, 4583 "%d associations found:\n", max); 4584 for (i = 0; i < max; i++) { 4585 device_printf(sc->dev, 4586 "Association %d (%d) %s%s:\n", 4587 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4588 as[i].enable?"":" (disabled)"); 4589 for (j = 0; j < 16; j++) { 4590 if (as[i].pins[j] == 0) 4591 continue; 4592 device_printf(sc->dev, 4593 " Pin nid=%d seq=%d\n", 4594 as[i].pins[j], j); 4595 } 4596 } 4597 ); 4598 4599 devinfo->function.audio.as = as; 4600} 4601 4602static const struct { 4603 uint32_t model; 4604 uint32_t id; 4605 uint32_t set, unset; 4606} hdac_quirks[] = { 4607 /* 4608 * XXX Force stereo quirk. Monoural recording / playback 4609 * on few codecs (especially ALC880) seems broken or 4610 * perhaps unsupported. 4611 */ 4612 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4613 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4614 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4615 HDA_QUIRK_GPIO0, 0 }, 4616 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4617 HDA_QUIRK_GPIO0, 0 }, 4618 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4619 HDA_QUIRK_GPIO0, 0 }, 4620 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4621 HDA_QUIRK_GPIO0, 0 }, 4622 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4623 HDA_QUIRK_GPIO0, 0 }, 4624 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4625 HDA_QUIRK_GPIO0, 0 }, 4626 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4627 HDA_QUIRK_EAPDINV, 0 }, 4628 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4629 HDA_QUIRK_EAPDINV, 0 }, 4630 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4631 HDA_QUIRK_OVREF, 0 }, 4632 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4633 HDA_QUIRK_OVREF, 0 }, 4634 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4635 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4636 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4637 HDA_QUIRK_GPIO1, 0 }, 4638 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4639 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4640 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4641 HDA_QUIRK_EAPDINV, 0 }, 4642 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4643 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4644 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4645 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4646 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4647 HDA_QUIRK_GPIO0, 0 }, 4648 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4649 HDA_QUIRK_GPIO2, 0 }, 4650 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4651 HDA_QUIRK_GPIO0, 0 }, 4652 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4653 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4654 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4655 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4656 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4657 0, HDA_QUIRK_FORCESTEREO } 4658}; 4659#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4660 4661static void 4662hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4663{ 4664 struct hdac_widget *w; 4665 uint32_t id, subvendor; 4666 int i; 4667 4668 id = hdac_codec_id(devinfo->codec); 4669 subvendor = devinfo->codec->sc->pci_subvendor; 4670 4671 /* 4672 * Quirks 4673 */ 4674 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4675 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4676 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4677 continue; 4678 if (hdac_quirks[i].set != 0) 4679 devinfo->function.audio.quirks |= 4680 hdac_quirks[i].set; 4681 if (hdac_quirks[i].unset != 0) 4682 devinfo->function.audio.quirks &= 4683 ~(hdac_quirks[i].unset); 4684 } 4685 4686 switch (id) { 4687#if 0 4688 case HDA_CODEC_ALC883: 4689 /* 4690 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4691 * Clear vref cap for jack connectivity. 4692 */ 4693 w = hdac_widget_get(devinfo, 24); 4694 if (w != NULL && w->enable != 0 && w->type == 4695 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4696 (w->wclass.pin.config & 4697 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4698 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4699 w->wclass.pin.cap &= ~( 4700 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4701 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4702 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4703 w = hdac_widget_get(devinfo, 25); 4704 if (w != NULL && w->enable != 0 && w->type == 4705 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4706 (w->wclass.pin.config & 4707 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4708 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4709 w->wclass.pin.cap &= ~( 4710 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4711 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4712 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4713 /* 4714 * nid: 26 = Line-in, leave it alone. 4715 */ 4716 break; 4717#endif 4718 case HDA_CODEC_AD1983: 4719 /* 4720 * This codec has several possible usages, but none 4721 * fit the parser best. Help parser to choose better. 4722 */ 4723 /* Disable direct unmixed playback to get pcm volume. */ 4724 w = hdac_widget_get(devinfo, 5); 4725 if (w != NULL) 4726 w->connsenable[0] = 0; 4727 w = hdac_widget_get(devinfo, 6); 4728 if (w != NULL) 4729 w->connsenable[0] = 0; 4730 w = hdac_widget_get(devinfo, 11); 4731 if (w != NULL) 4732 w->connsenable[0] = 0; 4733 /* Disable mic and line selectors. */ 4734 w = hdac_widget_get(devinfo, 12); 4735 if (w != NULL) 4736 w->connsenable[1] = 0; 4737 w = hdac_widget_get(devinfo, 13); 4738 if (w != NULL) 4739 w->connsenable[1] = 0; 4740 /* Disable recording from mono playback mix. */ 4741 w = hdac_widget_get(devinfo, 20); 4742 if (w != NULL) 4743 w->connsenable[3] = 0; 4744 break; 4745 case HDA_CODEC_AD1986A: 4746 /* 4747 * This codec has overcomplicated input mixing. 4748 * Make some cleaning there. 4749 */ 4750 /* Disable input mono mixer. Not needed and not supported. */ 4751 w = hdac_widget_get(devinfo, 43); 4752 if (w != NULL) 4753 w->enable = 0; 4754 /* Disable any with any input mixing mesh. Use separately. */ 4755 w = hdac_widget_get(devinfo, 39); 4756 if (w != NULL) 4757 w->enable = 0; 4758 w = hdac_widget_get(devinfo, 40); 4759 if (w != NULL) 4760 w->enable = 0; 4761 w = hdac_widget_get(devinfo, 41); 4762 if (w != NULL) 4763 w->enable = 0; 4764 w = hdac_widget_get(devinfo, 42); 4765 if (w != NULL) 4766 w->enable = 0; 4767 /* Disable duplicate mixer node connector. */ 4768 w = hdac_widget_get(devinfo, 15); 4769 if (w != NULL) 4770 w->connsenable[3] = 0; 4771 /* There is only one mic preamplifier, use it effectively. */ 4772 w = hdac_widget_get(devinfo, 31); 4773 if (w != NULL) { 4774 if ((w->wclass.pin.config & 4775 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4776 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4777 w = hdac_widget_get(devinfo, 16); 4778 if (w != NULL) 4779 w->connsenable[2] = 0; 4780 } else { 4781 w = hdac_widget_get(devinfo, 15); 4782 if (w != NULL) 4783 w->connsenable[0] = 0; 4784 } 4785 } 4786 w = hdac_widget_get(devinfo, 32); 4787 if (w != NULL) { 4788 if ((w->wclass.pin.config & 4789 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4790 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4791 w = hdac_widget_get(devinfo, 16); 4792 if (w != NULL) 4793 w->connsenable[0] = 0; 4794 } else { 4795 w = hdac_widget_get(devinfo, 15); 4796 if (w != NULL) 4797 w->connsenable[1] = 0; 4798 } 4799 } 4800 4801 if (subvendor == ASUS_A8X_SUBVENDOR) { 4802 /* 4803 * This is just plain ridiculous.. There 4804 * are several A8 series that share the same 4805 * pci id but works differently (EAPD). 4806 */ 4807 w = hdac_widget_get(devinfo, 26); 4808 if (w != NULL && w->type == 4809 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4810 (w->wclass.pin.config & 4811 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4812 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4813 devinfo->function.audio.quirks &= 4814 ~HDA_QUIRK_EAPDINV; 4815 } 4816 break; 4817 case HDA_CODEC_AD1981HD: 4818 /* 4819 * This codec has very unusual design with several 4820 * points inappropriate for the present parser. 4821 */ 4822 /* Disable recording from mono playback mix. */ 4823 w = hdac_widget_get(devinfo, 21); 4824 if (w != NULL) 4825 w->connsenable[3] = 0; 4826 /* Disable rear to front mic mixer, use separately. */ 4827 w = hdac_widget_get(devinfo, 31); 4828 if (w != NULL) 4829 w->enable = 0; 4830 /* Disable playback mixer, use direct bypass. */ 4831 w = hdac_widget_get(devinfo, 14); 4832 if (w != NULL) 4833 w->enable = 0; 4834 break; 4835 } 4836} 4837 4838/* 4839 * Trace path from DAC to pin. 4840 */ 4841static nid_t 4842hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4843 int dupseq, int min, int only, int depth) 4844{ 4845 struct hdac_widget *w; 4846 int i, im = -1; 4847 nid_t m = 0, ret; 4848 4849 if (depth > HDA_PARSE_MAXDEPTH) 4850 return (0); 4851 w = hdac_widget_get(devinfo, nid); 4852 if (w == NULL || w->enable == 0) 4853 return (0); 4854 HDA_BOOTHVERBOSE( 4855 if (!only) { 4856 device_printf(devinfo->codec->sc->dev, 4857 " %*stracing via nid %d\n", 4858 depth + 1, "", w->nid); 4859 } 4860 ); 4861 /* Use only unused widgets */ 4862 if (w->bindas >= 0 && w->bindas != as) { 4863 HDA_BOOTHVERBOSE( 4864 if (!only) { 4865 device_printf(devinfo->codec->sc->dev, 4866 " %*snid %d busy by association %d\n", 4867 depth + 1, "", w->nid, w->bindas); 4868 } 4869 ); 4870 return (0); 4871 } 4872 if (dupseq < 0) { 4873 if (w->bindseqmask != 0) { 4874 HDA_BOOTHVERBOSE( 4875 if (!only) { 4876 device_printf(devinfo->codec->sc->dev, 4877 " %*snid %d busy by seqmask %x\n", 4878 depth + 1, "", w->nid, w->bindseqmask); 4879 } 4880 ); 4881 return (0); 4882 } 4883 } else { 4884 /* If this is headphones - allow duplicate first pin. */ 4885 if (w->bindseqmask != 0 && 4886 (w->bindseqmask & (1 << dupseq)) == 0) { 4887 HDA_BOOTHVERBOSE( 4888 device_printf(devinfo->codec->sc->dev, 4889 " %*snid %d busy by seqmask %x\n", 4890 depth + 1, "", w->nid, w->bindseqmask); 4891 ); 4892 return (0); 4893 } 4894 } 4895 4896 switch (w->type) { 4897 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4898 /* Do not traverse input. AD1988 has digital monitor 4899 for which we are not ready. */ 4900 break; 4901 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4902 /* If we are tracing HP take only dac of first pin. */ 4903 if ((only == 0 || only == w->nid) && 4904 (w->nid >= min) && (dupseq < 0 || w->nid == 4905 devinfo->function.audio.as[as].dacs[dupseq])) 4906 m = w->nid; 4907 break; 4908 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4909 if (depth > 0) 4910 break; 4911 /* Fall */ 4912 default: 4913 /* Find reachable DACs with smallest nid respecting constraints. */ 4914 for (i = 0; i < w->nconns; i++) { 4915 if (w->connsenable[i] == 0) 4916 continue; 4917 if (w->selconn != -1 && w->selconn != i) 4918 continue; 4919 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4920 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4921 if (m == 0 || ret < m) { 4922 m = ret; 4923 im = i; 4924 } 4925 if (only || dupseq >= 0) 4926 break; 4927 } 4928 } 4929 if (m && only && ((w->nconns > 1 && 4930 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4931 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4932 w->selconn = im; 4933 break; 4934 } 4935 if (m && only) { 4936 w->bindas = as; 4937 w->bindseqmask |= (1 << seq); 4938 } 4939 HDA_BOOTHVERBOSE( 4940 if (!only) { 4941 device_printf(devinfo->codec->sc->dev, 4942 " %*snid %d returned %d\n", 4943 depth + 1, "", w->nid, m); 4944 } 4945 ); 4946 return (m); 4947} 4948 4949/* 4950 * Trace path from widget to ADC. 4951 */ 4952static nid_t 4953hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4954 int only, int depth) 4955{ 4956 struct hdac_widget *w, *wc; 4957 int i, j; 4958 nid_t res = 0; 4959 4960 if (depth > HDA_PARSE_MAXDEPTH) 4961 return (0); 4962 w = hdac_widget_get(devinfo, nid); 4963 if (w == NULL || w->enable == 0) 4964 return (0); 4965 HDA_BOOTHVERBOSE( 4966 device_printf(devinfo->codec->sc->dev, 4967 " %*stracing via nid %d\n", 4968 depth + 1, "", w->nid); 4969 ); 4970 /* Use only unused widgets */ 4971 if (w->bindas >= 0 && w->bindas != as) { 4972 HDA_BOOTHVERBOSE( 4973 device_printf(devinfo->codec->sc->dev, 4974 " %*snid %d busy by association %d\n", 4975 depth + 1, "", w->nid, w->bindas); 4976 ); 4977 return (0); 4978 } 4979 4980 switch (w->type) { 4981 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4982 /* If we are tracing HP take only dac of first pin. */ 4983 if (only == w->nid) 4984 res = 1; 4985 break; 4986 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4987 if (depth > 0) 4988 break; 4989 /* Fall */ 4990 default: 4991 /* Try to find reachable ADCs with specified nid. */ 4992 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4993 wc = hdac_widget_get(devinfo, j); 4994 if (wc == NULL || wc->enable == 0) 4995 continue; 4996 for (i = 0; i < wc->nconns; i++) { 4997 if (wc->connsenable[i] == 0) 4998 continue; 4999 if (wc->conns[i] != nid) 5000 continue; 5001 if (hdac_audio_trace_adc(devinfo, as, seq, 5002 j, only, depth + 1) != 0) { 5003 res = 1; 5004 if (((wc->nconns > 1 && 5005 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5006 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5007 wc->selconn == -1) 5008 wc->selconn = i; 5009 } 5010 } 5011 } 5012 break; 5013 } 5014 if (res) { 5015 w->bindas = as; 5016 w->bindseqmask |= (1 << seq); 5017 } 5018 HDA_BOOTHVERBOSE( 5019 device_printf(devinfo->codec->sc->dev, 5020 " %*snid %d returned %d\n", 5021 depth + 1, "", w->nid, res); 5022 ); 5023 return (res); 5024} 5025 5026/* 5027 * Erase trace path of the specified association. 5028 */ 5029static void 5030hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5031{ 5032 struct hdac_widget *w; 5033 int i; 5034 5035 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5036 w = hdac_widget_get(devinfo, i); 5037 if (w == NULL || w->enable == 0) 5038 continue; 5039 if (w->bindas == as) { 5040 if (seq >= 0) { 5041 w->bindseqmask &= ~(1 << seq); 5042 if (w->bindseqmask == 0) { 5043 w->bindas = -1; 5044 w->selconn = -1; 5045 } 5046 } else { 5047 w->bindas = -1; 5048 w->bindseqmask = 0; 5049 w->selconn = -1; 5050 } 5051 } 5052 } 5053} 5054 5055/* 5056 * Trace association path from DAC to output 5057 */ 5058static int 5059hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5060{ 5061 struct hdac_audio_as *ases = devinfo->function.audio.as; 5062 int i, hpredir; 5063 nid_t min, res; 5064 5065 /* Find next pin */ 5066 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5067 ; 5068 /* Check if there is no any left. If so - we succeeded. */ 5069 if (i == 16) 5070 return (1); 5071 5072 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5073 min = 0; 5074 res = 0; 5075 do { 5076 HDA_BOOTHVERBOSE( 5077 device_printf(devinfo->codec->sc->dev, 5078 " Tracing pin %d with min nid %d", 5079 ases[as].pins[i], min); 5080 if (hpredir >= 0) 5081 printf(" and hpredir %d", hpredir); 5082 printf("\n"); 5083 ); 5084 /* Trace this pin taking min nid into account. */ 5085 res = hdac_audio_trace_dac(devinfo, as, i, 5086 ases[as].pins[i], hpredir, min, 0, 0); 5087 if (res == 0) { 5088 /* If we failed - return to previous and redo it. */ 5089 HDA_BOOTVERBOSE( 5090 device_printf(devinfo->codec->sc->dev, 5091 " Unable to trace pin %d seq %d with min " 5092 "nid %d", 5093 ases[as].pins[i], i, min); 5094 if (hpredir >= 0) 5095 printf(" and hpredir %d", hpredir); 5096 printf("\n"); 5097 ); 5098 return (0); 5099 } 5100 HDA_BOOTVERBOSE( 5101 device_printf(devinfo->codec->sc->dev, 5102 " Pin %d traced to DAC %d", 5103 ases[as].pins[i], res); 5104 if (hpredir >= 0) 5105 printf(" and hpredir %d", hpredir); 5106 if (ases[as].fakeredir) 5107 printf(" with fake redirection"); 5108 printf("\n"); 5109 ); 5110 /* Trace again to mark the path */ 5111 hdac_audio_trace_dac(devinfo, as, i, 5112 ases[as].pins[i], hpredir, min, res, 0); 5113 ases[as].dacs[i] = res; 5114 /* We succeeded, so call next. */ 5115 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5116 return (1); 5117 /* If next failed, we should retry with next min */ 5118 hdac_audio_undo_trace(devinfo, as, i); 5119 ases[as].dacs[i] = 0; 5120 min = res + 1; 5121 } while (1); 5122} 5123 5124/* 5125 * Trace association path from input to ADC 5126 */ 5127static int 5128hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5129{ 5130 struct hdac_audio_as *ases = devinfo->function.audio.as; 5131 struct hdac_widget *w; 5132 int i, j, k; 5133 5134 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5135 w = hdac_widget_get(devinfo, j); 5136 if (w == NULL || w->enable == 0) 5137 continue; 5138 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5139 continue; 5140 if (w->bindas >= 0 && w->bindas != as) 5141 continue; 5142 5143 /* Find next pin */ 5144 for (i = 0; i < 16; i++) { 5145 if (ases[as].pins[i] == 0) 5146 continue; 5147 5148 HDA_BOOTHVERBOSE( 5149 device_printf(devinfo->codec->sc->dev, 5150 " Tracing pin %d to ADC %d\n", 5151 ases[as].pins[i], j); 5152 ); 5153 /* Trace this pin taking goal into account. */ 5154 if (hdac_audio_trace_adc(devinfo, as, i, 5155 ases[as].pins[i], j, 0) == 0) { 5156 /* If we failed - return to previous and redo it. */ 5157 HDA_BOOTVERBOSE( 5158 device_printf(devinfo->codec->sc->dev, 5159 " Unable to trace pin %d to ADC %d, undo traces\n", 5160 ases[as].pins[i], j); 5161 ); 5162 hdac_audio_undo_trace(devinfo, as, -1); 5163 for (k = 0; k < 16; k++) 5164 ases[as].dacs[k] = 0; 5165 break; 5166 } 5167 HDA_BOOTVERBOSE( 5168 device_printf(devinfo->codec->sc->dev, 5169 " Pin %d traced to ADC %d\n", 5170 ases[as].pins[i], j); 5171 ); 5172 ases[as].dacs[i] = j; 5173 } 5174 if (i == 16) 5175 return (1); 5176 } 5177 return (0); 5178} 5179 5180/* 5181 * Trace input monitor path from mixer to output association. 5182 */ 5183static int 5184hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5185{ 5186 struct hdac_audio_as *ases = devinfo->function.audio.as; 5187 struct hdac_widget *w, *wc; 5188 int i, j; 5189 nid_t res = 0; 5190 5191 if (depth > HDA_PARSE_MAXDEPTH) 5192 return (0); 5193 w = hdac_widget_get(devinfo, nid); 5194 if (w == NULL || w->enable == 0) 5195 return (0); 5196 HDA_BOOTHVERBOSE( 5197 device_printf(devinfo->codec->sc->dev, 5198 " %*stracing via nid %d\n", 5199 depth + 1, "", w->nid); 5200 ); 5201 /* Use only unused widgets */ 5202 if (depth > 0 && w->bindas != -1) { 5203 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5204 HDA_BOOTHVERBOSE( 5205 device_printf(devinfo->codec->sc->dev, 5206 " %*snid %d found output association %d\n", 5207 depth + 1, "", w->nid, w->bindas); 5208 ); 5209 return (1); 5210 } else { 5211 HDA_BOOTHVERBOSE( 5212 device_printf(devinfo->codec->sc->dev, 5213 " %*snid %d busy by input association %d\n", 5214 depth + 1, "", w->nid, w->bindas); 5215 ); 5216 return (0); 5217 } 5218 } 5219 5220 switch (w->type) { 5221 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5222 /* Do not traverse input. AD1988 has digital monitor 5223 for which we are not ready. */ 5224 break; 5225 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5226 if (depth > 0) 5227 break; 5228 /* Fall */ 5229 default: 5230 /* Try to find reachable ADCs with specified nid. */ 5231 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5232 wc = hdac_widget_get(devinfo, j); 5233 if (wc == NULL || wc->enable == 0) 5234 continue; 5235 for (i = 0; i < wc->nconns; i++) { 5236 if (wc->connsenable[i] == 0) 5237 continue; 5238 if (wc->conns[i] != nid) 5239 continue; 5240 if (hdac_audio_trace_to_out(devinfo, 5241 j, depth + 1) != 0) { 5242 res = 1; 5243 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5244 wc->selconn == -1) 5245 wc->selconn = i; 5246 } 5247 } 5248 } 5249 break; 5250 } 5251 if (res) 5252 w->bindas = -2; 5253 5254 HDA_BOOTHVERBOSE( 5255 device_printf(devinfo->codec->sc->dev, 5256 " %*snid %d returned %d\n", 5257 depth + 1, "", w->nid, res); 5258 ); 5259 return (res); 5260} 5261 5262/* 5263 * Trace extra associations (beeper, monitor) 5264 */ 5265static void 5266hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5267{ 5268 struct hdac_audio_as *as = devinfo->function.audio.as; 5269 struct hdac_widget *w; 5270 int j; 5271 5272 /* Input monitor */ 5273 /* Find mixer associated with input, but supplying signal 5274 for output associations. Hope it will be input monitor. */ 5275 HDA_BOOTVERBOSE( 5276 device_printf(devinfo->codec->sc->dev, 5277 "Tracing input monitor\n"); 5278 ); 5279 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5280 w = hdac_widget_get(devinfo, j); 5281 if (w == NULL || w->enable == 0) 5282 continue; 5283 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5284 continue; 5285 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5286 continue; 5287 HDA_BOOTVERBOSE( 5288 device_printf(devinfo->codec->sc->dev, 5289 " Tracing nid %d to out\n", 5290 j); 5291 ); 5292 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5293 HDA_BOOTVERBOSE( 5294 device_printf(devinfo->codec->sc->dev, 5295 " nid %d is input monitor\n", 5296 w->nid); 5297 ); 5298 w->pflags |= HDA_ADC_MONITOR; 5299 w->ossdev = SOUND_MIXER_IMIX; 5300 } 5301 } 5302 5303 /* Beeper */ 5304 HDA_BOOTVERBOSE( 5305 device_printf(devinfo->codec->sc->dev, 5306 "Tracing beeper\n"); 5307 ); 5308 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5309 w = hdac_widget_get(devinfo, j); 5310 if (w == NULL || w->enable == 0) 5311 continue; 5312 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5313 continue; 5314 HDA_BOOTHVERBOSE( 5315 device_printf(devinfo->codec->sc->dev, 5316 " Tracing nid %d to out\n", 5317 j); 5318 ); 5319 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5320 HDA_BOOTVERBOSE( 5321 device_printf(devinfo->codec->sc->dev, 5322 " nid %d traced to out\n", 5323 j); 5324 ); 5325 } 5326 w->bindas = -2; 5327 } 5328} 5329 5330/* 5331 * Bind assotiations to PCM channels 5332 */ 5333static void 5334hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5335{ 5336 struct hdac_softc *sc = devinfo->codec->sc; 5337 struct hdac_audio_as *as = devinfo->function.audio.as; 5338 int j, cnt = 0, free; 5339 5340 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5341 if (as[j].enable) 5342 cnt++; 5343 } 5344 if (sc->num_chans == 0) { 5345 sc->chans = (struct hdac_chan *)malloc( 5346 sizeof(struct hdac_chan) * cnt, 5347 M_HDAC, M_ZERO | M_NOWAIT); 5348 if (sc->chans == NULL) { 5349 device_printf(sc->dev, 5350 "Channels memory allocation failed!\n"); 5351 return; 5352 } 5353 } else { 5354 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5355 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5356 M_HDAC, M_ZERO | M_NOWAIT); 5357 if (sc->chans == NULL) { 5358 sc->num_chans = 0; 5359 device_printf(sc->dev, 5360 "Channels memory allocation failed!\n"); 5361 return; 5362 } 5363 /* Fixup relative pointers after realloc */ 5364 for (j = 0; j < sc->num_chans; j++) 5365 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5366 } 5367 free = sc->num_chans; 5368 sc->num_chans += cnt; 5369 5370 for (j = free; j < free + cnt; j++) { 5371 sc->chans[j].devinfo = devinfo; 5372 sc->chans[j].as = -1; 5373 } 5374 5375 /* Assign associations in order of their numbers, */ 5376 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5377 if (as[j].enable == 0) 5378 continue; 5379 5380 as[j].chan = free; 5381 sc->chans[free].as = j; 5382 sc->chans[free].dir = 5383 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5384 hdac_pcmchannel_setup(&sc->chans[free]); 5385 free++; 5386 } 5387} 5388 5389static void 5390hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5391{ 5392 struct hdac_widget *w; 5393 int i; 5394 5395 /* Disable power and volume widgets. */ 5396 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5397 w = hdac_widget_get(devinfo, i); 5398 if (w == NULL || w->enable == 0) 5399 continue; 5400 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5401 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5402 w->enable = 0; 5403 HDA_BOOTHVERBOSE( 5404 device_printf(devinfo->codec->sc->dev, 5405 " Disabling nid %d due to it's" 5406 " non-audio type.\n", 5407 w->nid); 5408 ); 5409 } 5410 } 5411} 5412 5413static void 5414hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5415{ 5416 struct hdac_widget *w, *cw; 5417 struct hdac_audio_ctl *ctl; 5418 int done, found, i, j, k; 5419 5420 /* Disable useless pins. */ 5421 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5422 w = hdac_widget_get(devinfo, i); 5423 if (w == NULL || w->enable == 0) 5424 continue; 5425 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5426 if ((w->wclass.pin.config & 5427 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5428 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5429 w->enable = 0; 5430 HDA_BOOTHVERBOSE( 5431 device_printf(devinfo->codec->sc->dev, 5432 " Disabling pin nid %d due" 5433 " to None connectivity.\n", 5434 w->nid); 5435 ); 5436 } else if ((w->wclass.pin.config & 5437 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5438 w->enable = 0; 5439 HDA_BOOTHVERBOSE( 5440 device_printf(devinfo->codec->sc->dev, 5441 " Disabling unassociated" 5442 " pin nid %d.\n", 5443 w->nid); 5444 ); 5445 } 5446 } 5447 } 5448 do { 5449 done = 1; 5450 /* Disable and mute controls for disabled widgets. */ 5451 i = 0; 5452 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5453 if (ctl->enable == 0) 5454 continue; 5455 if (ctl->widget->enable == 0 || 5456 (ctl->childwidget != NULL && 5457 ctl->childwidget->enable == 0)) { 5458 ctl->forcemute = 1; 5459 ctl->muted = HDA_AMP_MUTE_ALL; 5460 ctl->left = 0; 5461 ctl->right = 0; 5462 ctl->enable = 0; 5463 if (ctl->ndir == HDA_CTL_IN) 5464 ctl->widget->connsenable[ctl->index] = 0; 5465 done = 0; 5466 HDA_BOOTHVERBOSE( 5467 device_printf(devinfo->codec->sc->dev, 5468 " Disabling ctl %d nid %d cnid %d due" 5469 " to disabled widget.\n", i, 5470 ctl->widget->nid, 5471 (ctl->childwidget != NULL)? 5472 ctl->childwidget->nid:-1); 5473 ); 5474 } 5475 } 5476 /* Disable useless widgets. */ 5477 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5478 w = hdac_widget_get(devinfo, i); 5479 if (w == NULL || w->enable == 0) 5480 continue; 5481 /* Disable inputs with disabled child widgets. */ 5482 for (j = 0; j < w->nconns; j++) { 5483 if (w->connsenable[j]) { 5484 cw = hdac_widget_get(devinfo, w->conns[j]); 5485 if (cw == NULL || cw->enable == 0) { 5486 w->connsenable[j] = 0; 5487 HDA_BOOTHVERBOSE( 5488 device_printf(devinfo->codec->sc->dev, 5489 " Disabling nid %d connection %d due" 5490 " to disabled child widget.\n", 5491 i, j); 5492 ); 5493 } 5494 } 5495 } 5496 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5497 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5498 continue; 5499 /* Disable mixers and selectors without inputs. */ 5500 found = 0; 5501 for (j = 0; j < w->nconns; j++) { 5502 if (w->connsenable[j]) { 5503 found = 1; 5504 break; 5505 } 5506 } 5507 if (found == 0) { 5508 w->enable = 0; 5509 done = 0; 5510 HDA_BOOTHVERBOSE( 5511 device_printf(devinfo->codec->sc->dev, 5512 " Disabling nid %d due to all it's" 5513 " inputs disabled.\n", w->nid); 5514 ); 5515 } 5516 /* Disable nodes without consumers. */ 5517 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5518 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5519 continue; 5520 found = 0; 5521 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5522 cw = hdac_widget_get(devinfo, k); 5523 if (cw == NULL || cw->enable == 0) 5524 continue; 5525 for (j = 0; j < cw->nconns; j++) { 5526 if (cw->connsenable[j] && cw->conns[j] == i) { 5527 found = 1; 5528 break; 5529 } 5530 } 5531 } 5532 if (found == 0) { 5533 w->enable = 0; 5534 done = 0; 5535 HDA_BOOTHVERBOSE( 5536 device_printf(devinfo->codec->sc->dev, 5537 " Disabling nid %d due to all it's" 5538 " consumers disabled.\n", w->nid); 5539 ); 5540 } 5541 } 5542 } while (done == 0); 5543 5544} 5545 5546static void 5547hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5548{ 5549 struct hdac_audio_as *as = devinfo->function.audio.as; 5550 struct hdac_widget *w, *cw; 5551 struct hdac_audio_ctl *ctl; 5552 int i, j, k; 5553 5554 /* Disable unassosiated widgets. */ 5555 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5556 w = hdac_widget_get(devinfo, i); 5557 if (w == NULL || w->enable == 0) 5558 continue; 5559 if (w->bindas == -1) { 5560 w->enable = 0; 5561 HDA_BOOTHVERBOSE( 5562 device_printf(devinfo->codec->sc->dev, 5563 " Disabling unassociated nid %d.\n", 5564 w->nid); 5565 ); 5566 } 5567 } 5568 /* Disable input connections on input pin and 5569 * output on output. */ 5570 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5571 w = hdac_widget_get(devinfo, i); 5572 if (w == NULL || w->enable == 0) 5573 continue; 5574 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5575 continue; 5576 if (w->bindas < 0) 5577 continue; 5578 if (as[w->bindas].dir == HDA_CTL_IN) { 5579 for (j = 0; j < w->nconns; j++) { 5580 if (w->connsenable[j] == 0) 5581 continue; 5582 w->connsenable[j] = 0; 5583 HDA_BOOTHVERBOSE( 5584 device_printf(devinfo->codec->sc->dev, 5585 " Disabling connection to input pin " 5586 "nid %d conn %d.\n", 5587 i, j); 5588 ); 5589 } 5590 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5591 HDA_CTL_IN, -1, 1); 5592 if (ctl && ctl->enable) { 5593 ctl->forcemute = 1; 5594 ctl->muted = HDA_AMP_MUTE_ALL; 5595 ctl->left = 0; 5596 ctl->right = 0; 5597 ctl->enable = 0; 5598 } 5599 } else { 5600 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5601 HDA_CTL_OUT, -1, 1); 5602 if (ctl && ctl->enable) { 5603 ctl->forcemute = 1; 5604 ctl->muted = HDA_AMP_MUTE_ALL; 5605 ctl->left = 0; 5606 ctl->right = 0; 5607 ctl->enable = 0; 5608 } 5609 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5610 cw = hdac_widget_get(devinfo, k); 5611 if (cw == NULL || cw->enable == 0) 5612 continue; 5613 for (j = 0; j < cw->nconns; j++) { 5614 if (cw->connsenable[j] && cw->conns[j] == i) { 5615 cw->connsenable[j] = 0; 5616 HDA_BOOTHVERBOSE( 5617 device_printf(devinfo->codec->sc->dev, 5618 " Disabling connection from output pin " 5619 "nid %d conn %d cnid %d.\n", 5620 k, j, i); 5621 ); 5622 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5623 cw->nconns > 1) 5624 continue; 5625 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5626 HDA_CTL_IN, j, 1); 5627 if (ctl && ctl->enable) { 5628 ctl->forcemute = 1; 5629 ctl->muted = HDA_AMP_MUTE_ALL; 5630 ctl->left = 0; 5631 ctl->right = 0; 5632 ctl->enable = 0; 5633 } 5634 } 5635 } 5636 } 5637 } 5638 } 5639} 5640 5641static void 5642hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5643{ 5644 struct hdac_audio_as *as = devinfo->function.audio.as; 5645 struct hdac_widget *w; 5646 int i, j; 5647 5648 /* On playback path we can safely disable all unseleted inputs. */ 5649 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5650 w = hdac_widget_get(devinfo, i); 5651 if (w == NULL || w->enable == 0) 5652 continue; 5653 if (w->nconns <= 1) 5654 continue; 5655 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5656 continue; 5657 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5658 continue; 5659 for (j = 0; j < w->nconns; j++) { 5660 if (w->connsenable[j] == 0) 5661 continue; 5662 if (w->selconn < 0 || w->selconn == j) 5663 continue; 5664 w->connsenable[j] = 0; 5665 HDA_BOOTHVERBOSE( 5666 device_printf(devinfo->codec->sc->dev, 5667 " Disabling unselected connection " 5668 "nid %d conn %d.\n", 5669 i, j); 5670 ); 5671 } 5672 } 5673} 5674 5675static void 5676hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5677{ 5678 struct hdac_widget *w, *cw; 5679 struct hdac_audio_ctl *ctl; 5680 int i, j; 5681 5682 /* Disable crossassociatement and unwanted crosschannel connections. */ 5683 /* ... using selectors */ 5684 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5685 w = hdac_widget_get(devinfo, i); 5686 if (w == NULL || w->enable == 0) 5687 continue; 5688 if (w->nconns <= 1) 5689 continue; 5690 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5691 continue; 5692 if (w->bindas == -2) 5693 continue; 5694 for (j = 0; j < w->nconns; j++) { 5695 if (w->connsenable[j] == 0) 5696 continue; 5697 cw = hdac_widget_get(devinfo, w->conns[j]); 5698 if (cw == NULL || w->enable == 0) 5699 continue; 5700 if (cw->bindas == -2) 5701 continue; 5702 if (w->bindas == cw->bindas && 5703 (w->bindseqmask & cw->bindseqmask) != 0) 5704 continue; 5705 w->connsenable[j] = 0; 5706 HDA_BOOTHVERBOSE( 5707 device_printf(devinfo->codec->sc->dev, 5708 " Disabling crossassociatement connection " 5709 "nid %d conn %d cnid %d.\n", 5710 i, j, cw->nid); 5711 ); 5712 } 5713 } 5714 /* ... using controls */ 5715 i = 0; 5716 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5717 if (ctl->enable == 0 || ctl->childwidget == NULL) 5718 continue; 5719 if (ctl->widget->bindas == -2 || 5720 ctl->childwidget->bindas == -2) 5721 continue; 5722 if (ctl->widget->bindas != ctl->childwidget->bindas || 5723 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5724 ctl->forcemute = 1; 5725 ctl->muted = HDA_AMP_MUTE_ALL; 5726 ctl->left = 0; 5727 ctl->right = 0; 5728 ctl->enable = 0; 5729 if (ctl->ndir == HDA_CTL_IN) 5730 ctl->widget->connsenable[ctl->index] = 0; 5731 HDA_BOOTHVERBOSE( 5732 device_printf(devinfo->codec->sc->dev, 5733 " Disabling crossassociatement connection " 5734 "ctl %d nid %d cnid %d.\n", i, 5735 ctl->widget->nid, 5736 ctl->childwidget->nid); 5737 ); 5738 } 5739 } 5740 5741} 5742 5743#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5744 5745/* 5746 * Find controls to control amplification for source. 5747 */ 5748static int 5749hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5750 int ossdev, int ctlable, int depth, int need) 5751{ 5752 struct hdac_widget *w, *wc; 5753 struct hdac_audio_ctl *ctl; 5754 int i, j, conns = 0, rneed; 5755 5756 if (depth > HDA_PARSE_MAXDEPTH) 5757 return (need); 5758 5759 w = hdac_widget_get(devinfo, nid); 5760 if (w == NULL || w->enable == 0) 5761 return (need); 5762 5763 /* Count number of active inputs. */ 5764 if (depth > 0) { 5765 for (j = 0; j < w->nconns; j++) { 5766 if (w->connsenable[j]) 5767 conns++; 5768 } 5769 } 5770 5771 /* If this is not a first step - use input mixer. 5772 Pins have common input ctl so care must be taken. */ 5773 if (depth > 0 && ctlable && (conns == 1 || 5774 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5775 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5776 index, 1); 5777 if (ctl) { 5778 if (HDA_CTL_GIVE(ctl) & need) 5779 ctl->ossmask |= (1 << ossdev); 5780 else 5781 ctl->possmask |= (1 << ossdev); 5782 need &= ~HDA_CTL_GIVE(ctl); 5783 } 5784 } 5785 5786 /* If widget has own ossdev - not traverse it. 5787 It will be traversed on it's own. */ 5788 if (w->ossdev >= 0 && depth > 0) 5789 return (need); 5790 5791 /* We must not traverse pin */ 5792 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5793 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5794 depth > 0) 5795 return (need); 5796 5797 /* record that this widget exports such signal, */ 5798 w->ossmask |= (1 << ossdev); 5799 5800 /* If signals mixed, we can't assign controls farther. 5801 * Ignore this on depth zero. Caller must knows why. 5802 * Ignore this for static selectors if this input selected. 5803 */ 5804 if (conns > 1) 5805 ctlable = 0; 5806 5807 if (ctlable) { 5808 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5809 if (ctl) { 5810 if (HDA_CTL_GIVE(ctl) & need) 5811 ctl->ossmask |= (1 << ossdev); 5812 else 5813 ctl->possmask |= (1 << ossdev); 5814 need &= ~HDA_CTL_GIVE(ctl); 5815 } 5816 } 5817 5818 rneed = 0; 5819 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5820 wc = hdac_widget_get(devinfo, i); 5821 if (wc == NULL || wc->enable == 0) 5822 continue; 5823 for (j = 0; j < wc->nconns; j++) { 5824 if (wc->connsenable[j] && wc->conns[j] == nid) { 5825 rneed |= hdac_audio_ctl_source_amp(devinfo, 5826 wc->nid, j, ossdev, ctlable, depth + 1, need); 5827 } 5828 } 5829 } 5830 rneed &= need; 5831 5832 return (rneed); 5833} 5834 5835/* 5836 * Find controls to control amplification for destination. 5837 */ 5838static void 5839hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5840 int ossdev, int depth, int need) 5841{ 5842 struct hdac_audio_as *as = devinfo->function.audio.as; 5843 struct hdac_widget *w, *wc; 5844 struct hdac_audio_ctl *ctl; 5845 int i, j, consumers; 5846 5847 if (depth > HDA_PARSE_MAXDEPTH) 5848 return; 5849 5850 w = hdac_widget_get(devinfo, nid); 5851 if (w == NULL || w->enable == 0) 5852 return; 5853 5854 if (depth > 0) { 5855 /* If this node produce output for several consumers, 5856 we can't touch it. */ 5857 consumers = 0; 5858 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5859 wc = hdac_widget_get(devinfo, i); 5860 if (wc == NULL || wc->enable == 0) 5861 continue; 5862 for (j = 0; j < wc->nconns; j++) { 5863 if (wc->connsenable[j] && wc->conns[j] == nid) 5864 consumers++; 5865 } 5866 } 5867 /* The only exception is if real HP redirection is configured 5868 and this is a duplication point. 5869 XXX: Actually exception is not completely correct. 5870 XXX: Duplication point check is not perfect. */ 5871 if ((consumers == 2 && (w->bindas < 0 || 5872 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5873 (w->bindseqmask & (1 << 15)) == 0)) || 5874 consumers > 2) 5875 return; 5876 5877 /* Else use it's output mixer. */ 5878 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5879 HDA_CTL_OUT, -1, 1); 5880 if (ctl) { 5881 if (HDA_CTL_GIVE(ctl) & need) 5882 ctl->ossmask |= (1 << ossdev); 5883 else 5884 ctl->possmask |= (1 << ossdev); 5885 need &= ~HDA_CTL_GIVE(ctl); 5886 } 5887 } 5888 5889 /* We must not traverse pin */ 5890 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5891 depth > 0) 5892 return; 5893 5894 for (i = 0; i < w->nconns; i++) { 5895 int tneed = need; 5896 if (w->connsenable[i] == 0) 5897 continue; 5898 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5899 HDA_CTL_IN, i, 1); 5900 if (ctl) { 5901 if (HDA_CTL_GIVE(ctl) & tneed) 5902 ctl->ossmask |= (1 << ossdev); 5903 else 5904 ctl->possmask |= (1 << ossdev); 5905 tneed &= ~HDA_CTL_GIVE(ctl); 5906 } 5907 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5908 depth + 1, tneed); 5909 } 5910} 5911 5912/* 5913 * Assign OSS names to sound sources 5914 */ 5915static void 5916hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5917{ 5918 struct hdac_audio_as *as = devinfo->function.audio.as; 5919 struct hdac_widget *w; 5920 int i, j; 5921 int type = -1, use, used = 0; 5922 static const int types[7][13] = { 5923 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5924 SOUND_MIXER_LINE3, -1 }, /* line */ 5925 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5926 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5927 { SOUND_MIXER_CD, -1 }, /* cd */ 5928 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5929 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5930 -1 }, /* digital */ 5931 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5932 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5933 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5934 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5935 -1 } /* others */ 5936 }; 5937 5938 /* Surely known names */ 5939 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5940 w = hdac_widget_get(devinfo, i); 5941 if (w == NULL || w->enable == 0) 5942 continue; 5943 if (w->bindas == -1) 5944 continue; 5945 use = -1; 5946 switch (w->type) { 5947 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5948 if (as[w->bindas].dir == HDA_CTL_OUT) 5949 break; 5950 type = -1; 5951 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5952 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5953 type = 0; 5954 break; 5955 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5956 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5957 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5958 break; 5959 type = 1; 5960 break; 5961 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5962 type = 3; 5963 break; 5964 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5965 type = 4; 5966 break; 5967 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5968 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5969 type = 5; 5970 break; 5971 } 5972 if (type == -1) 5973 break; 5974 j = 0; 5975 while (types[type][j] >= 0 && 5976 (used & (1 << types[type][j])) != 0) { 5977 j++; 5978 } 5979 if (types[type][j] >= 0) 5980 use = types[type][j]; 5981 break; 5982 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5983 use = SOUND_MIXER_PCM; 5984 break; 5985 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5986 use = SOUND_MIXER_SPEAKER; 5987 break; 5988 default: 5989 break; 5990 } 5991 if (use >= 0) { 5992 w->ossdev = use; 5993 used |= (1 << use); 5994 } 5995 } 5996 /* Semi-known names */ 5997 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5998 w = hdac_widget_get(devinfo, i); 5999 if (w == NULL || w->enable == 0) 6000 continue; 6001 if (w->ossdev >= 0) 6002 continue; 6003 if (w->bindas == -1) 6004 continue; 6005 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6006 continue; 6007 if (as[w->bindas].dir == HDA_CTL_OUT) 6008 continue; 6009 type = -1; 6010 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6011 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6012 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6013 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6014 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6015 type = 0; 6016 break; 6017 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6018 type = 2; 6019 break; 6020 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6021 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6022 type = 5; 6023 break; 6024 } 6025 if (type == -1) 6026 break; 6027 j = 0; 6028 while (types[type][j] >= 0 && 6029 (used & (1 << types[type][j])) != 0) { 6030 j++; 6031 } 6032 if (types[type][j] >= 0) { 6033 w->ossdev = types[type][j]; 6034 used |= (1 << types[type][j]); 6035 } 6036 } 6037 /* Others */ 6038 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6039 w = hdac_widget_get(devinfo, i); 6040 if (w == NULL || w->enable == 0) 6041 continue; 6042 if (w->ossdev >= 0) 6043 continue; 6044 if (w->bindas == -1) 6045 continue; 6046 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6047 continue; 6048 if (as[w->bindas].dir == HDA_CTL_OUT) 6049 continue; 6050 j = 0; 6051 while (types[6][j] >= 0 && 6052 (used & (1 << types[6][j])) != 0) { 6053 j++; 6054 } 6055 if (types[6][j] >= 0) { 6056 w->ossdev = types[6][j]; 6057 used |= (1 << types[6][j]); 6058 } 6059 } 6060} 6061 6062static void 6063hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6064{ 6065 struct hdac_audio_as *as = devinfo->function.audio.as; 6066 int j, res; 6067 6068 /* Trace all associations in order of their numbers, */ 6069 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6070 if (as[j].enable == 0) 6071 continue; 6072 HDA_BOOTVERBOSE( 6073 device_printf(devinfo->codec->sc->dev, 6074 "Tracing association %d (%d)\n", j, as[j].index); 6075 ); 6076 if (as[j].dir == HDA_CTL_OUT) { 6077retry: 6078 res = hdac_audio_trace_as_out(devinfo, j, 0); 6079 if (res == 0 && as[j].hpredir >= 0 && 6080 as[j].fakeredir == 0) { 6081 /* If codec can't do analog HP redirection 6082 try to make it using one more DAC. */ 6083 as[j].fakeredir = 1; 6084 goto retry; 6085 } 6086 } else { 6087 res = hdac_audio_trace_as_in(devinfo, j); 6088 } 6089 if (res) { 6090 HDA_BOOTVERBOSE( 6091 device_printf(devinfo->codec->sc->dev, 6092 "Association %d (%d) trace succeeded\n", 6093 j, as[j].index); 6094 ); 6095 } else { 6096 HDA_BOOTVERBOSE( 6097 device_printf(devinfo->codec->sc->dev, 6098 "Association %d (%d) trace failed\n", 6099 j, as[j].index); 6100 ); 6101 as[j].enable = 0; 6102 } 6103 } 6104 6105 /* Trace mixer and beeper pseudo associations. */ 6106 hdac_audio_trace_as_extra(devinfo); 6107} 6108 6109static void 6110hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6111{ 6112 struct hdac_audio_as *as = devinfo->function.audio.as; 6113 struct hdac_audio_ctl *ctl; 6114 struct hdac_widget *w; 6115 int i; 6116 6117 /* Assign mixers to the tree. */ 6118 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6119 w = hdac_widget_get(devinfo, i); 6120 if (w == NULL || w->enable == 0) 6121 continue; 6122 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6123 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6124 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6125 as[w->bindas].dir == HDA_CTL_IN)) { 6126 if (w->ossdev < 0) 6127 continue; 6128 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6129 w->ossdev, 1, 0, 1); 6130 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6131 if (w->ossdev < 0) 6132 continue; 6133 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6134 w->ossdev, 1, 0, 1)) { 6135 /* If we are unable to control input monitor 6136 as source - try to control it as destination. */ 6137 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6138 w->ossdev, 0, 1); 6139 } 6140 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6141 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6142 SOUND_MIXER_RECLEV, 0, 1); 6143 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6144 as[w->bindas].dir == HDA_CTL_OUT) { 6145 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6146 SOUND_MIXER_VOLUME, 0, 1); 6147 } 6148 } 6149 /* Treat unrequired as possible. */ 6150 i = 0; 6151 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6152 if (ctl->ossmask == 0) 6153 ctl->ossmask = ctl->possmask; 6154 } 6155} 6156 6157static void 6158hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6159{ 6160 struct hdac_audio_as *as = devinfo->function.audio.as; 6161 struct hdac_widget *w; 6162 uint32_t pincap; 6163 int i; 6164 6165 for (i = 0; i < devinfo->nodecnt; i++) { 6166 w = &devinfo->widget[i]; 6167 if (w == NULL) 6168 continue; 6169 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6170 continue; 6171 6172 pincap = w->wclass.pin.cap; 6173 6174 /* Disable everything. */ 6175 w->wclass.pin.ctrl &= ~( 6176 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6177 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6178 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6179 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6180 6181 if (w->enable == 0 || 6182 w->bindas < 0 || as[w->bindas].enable == 0) { 6183 /* Pin is unused so left it disabled. */ 6184 continue; 6185 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6186 /* Input pin, configure for input. */ 6187 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6188 w->wclass.pin.ctrl |= 6189 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6190 6191 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6192 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6193 w->wclass.pin.ctrl |= 6194 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6195 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6196 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6197 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6198 w->wclass.pin.ctrl |= 6199 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6200 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6201 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6202 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6203 w->wclass.pin.ctrl |= 6204 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6205 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6206 } else { 6207 /* Output pin, configure for output. */ 6208 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6209 w->wclass.pin.ctrl |= 6210 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6211 6212 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6213 (w->wclass.pin.config & 6214 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6215 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6216 w->wclass.pin.ctrl |= 6217 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6218 6219 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6220 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6221 w->wclass.pin.ctrl |= 6222 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6223 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6224 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6225 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6226 w->wclass.pin.ctrl |= 6227 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6228 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6229 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6230 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6231 w->wclass.pin.ctrl |= 6232 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6233 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6234 } 6235 } 6236} 6237 6238static void 6239hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6240{ 6241 struct hdac_audio_ctl *ctl; 6242 int i, z; 6243 6244 i = 0; 6245 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6246 if (ctl->enable == 0 || ctl->ossmask != 0) { 6247 /* Mute disabled and mixer controllable controls. 6248 * Last will be initialized by mixer_init(). 6249 * This expected to reduce click on startup. */ 6250 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6251 continue; 6252 } 6253 /* Init fixed controls to 0dB amplification. */ 6254 z = ctl->offset; 6255 if (z > ctl->step) 6256 z = ctl->step; 6257 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6258 } 6259} 6260 6261static void 6262hdac_audio_commit(struct hdac_devinfo *devinfo) 6263{ 6264 struct hdac_softc *sc = devinfo->codec->sc; 6265 struct hdac_widget *w; 6266 nid_t cad; 6267 uint32_t gdata, gmask, gdir; 6268 int commitgpio, numgpio; 6269 int i; 6270 6271 cad = devinfo->codec->cad; 6272 6273 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6274 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6275 0x7e7, 0), cad); 6276 6277 /* Commit controls. */ 6278 hdac_audio_ctl_commit(devinfo); 6279 6280 /* Commit selectors, pins and EAPD. */ 6281 for (i = 0; i < devinfo->nodecnt; i++) { 6282 w = &devinfo->widget[i]; 6283 if (w == NULL) 6284 continue; 6285 if (w->selconn == -1) 6286 w->selconn = 0; 6287 if (w->nconns > 0) 6288 hdac_widget_connection_select(w, w->selconn); 6289 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6290 hdac_command(sc, 6291 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6292 w->wclass.pin.ctrl), cad); 6293 } 6294 if (w->param.eapdbtl != HDAC_INVALID) { 6295 uint32_t val; 6296 6297 val = w->param.eapdbtl; 6298 if (devinfo->function.audio.quirks & 6299 HDA_QUIRK_EAPDINV) 6300 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6301 hdac_command(sc, 6302 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6303 val), cad); 6304 } 6305 } 6306 6307 /* Commit GPIOs. */ 6308 gdata = 0; 6309 gmask = 0; 6310 gdir = 0; 6311 commitgpio = 0; 6312 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6313 devinfo->function.audio.gpio); 6314 6315 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6316 commitgpio = (numgpio > 0) ? 1 : 0; 6317 else { 6318 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6319 if (!(devinfo->function.audio.quirks & 6320 (1 << i))) 6321 continue; 6322 if (commitgpio == 0) { 6323 commitgpio = 1; 6324 HDA_BOOTVERBOSE( 6325 gdata = hdac_command(sc, 6326 HDA_CMD_GET_GPIO_DATA(cad, 6327 devinfo->nid), cad); 6328 gmask = hdac_command(sc, 6329 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6330 devinfo->nid), cad); 6331 gdir = hdac_command(sc, 6332 HDA_CMD_GET_GPIO_DIRECTION(cad, 6333 devinfo->nid), cad); 6334 device_printf(sc->dev, 6335 "GPIO init: data=0x%08x " 6336 "mask=0x%08x dir=0x%08x\n", 6337 gdata, gmask, gdir); 6338 gdata = 0; 6339 gmask = 0; 6340 gdir = 0; 6341 ); 6342 } 6343 gdata |= 1 << i; 6344 gmask |= 1 << i; 6345 gdir |= 1 << i; 6346 } 6347 } 6348 6349 if (commitgpio != 0) { 6350 HDA_BOOTVERBOSE( 6351 device_printf(sc->dev, 6352 "GPIO commit: data=0x%08x mask=0x%08x " 6353 "dir=0x%08x\n", 6354 gdata, gmask, gdir); 6355 ); 6356 hdac_command(sc, 6357 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6358 gmask), cad); 6359 hdac_command(sc, 6360 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6361 gdir), cad); 6362 hdac_command(sc, 6363 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6364 gdata), cad); 6365 } 6366} 6367 6368static void 6369hdac_powerup(struct hdac_devinfo *devinfo) 6370{ 6371 struct hdac_softc *sc = devinfo->codec->sc; 6372 nid_t cad = devinfo->codec->cad; 6373 int i; 6374 6375 hdac_command(sc, 6376 HDA_CMD_SET_POWER_STATE(cad, 6377 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6378 cad); 6379 DELAY(100); 6380 6381 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6382 hdac_command(sc, 6383 HDA_CMD_SET_POWER_STATE(cad, 6384 i, HDA_CMD_POWER_STATE_D0), 6385 cad); 6386 } 6387 DELAY(1000); 6388} 6389 6390static int 6391hdac_pcmchannel_setup(struct hdac_chan *ch) 6392{ 6393 struct hdac_devinfo *devinfo = ch->devinfo; 6394 struct hdac_audio_as *as = devinfo->function.audio.as; 6395 struct hdac_widget *w; 6396 uint32_t cap, fmtcap, pcmcap; 6397 int i, j, ret, max; 6398 6399 ch->caps = hdac_caps; 6400 ch->caps.fmtlist = ch->fmtlist; 6401 ch->bit16 = 1; 6402 ch->bit32 = 0; 6403 ch->pcmrates[0] = 48000; 6404 ch->pcmrates[1] = 0; 6405 6406 ret = 0; 6407 fmtcap = devinfo->function.audio.supp_stream_formats; 6408 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6409 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6410 6411 for (i = 0; i < 16 && ret < max; i++) { 6412 /* Check as is correct */ 6413 if (ch->as < 0) 6414 break; 6415 /* Cound only present DACs */ 6416 if (as[ch->as].dacs[i] <= 0) 6417 continue; 6418 /* Ignore duplicates */ 6419 for (j = 0; j < ret; j++) { 6420 if (ch->io[j] == as[ch->as].dacs[i]) 6421 break; 6422 } 6423 if (j < ret) 6424 continue; 6425 6426 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6427 if (w == NULL || w->enable == 0) 6428 continue; 6429 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6430 continue; 6431 cap = w->param.supp_stream_formats; 6432 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6433 }*/ 6434 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6435 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6436 continue; 6437 /* Many codec does not declare AC3 support on SPDIF. 6438 I don't beleave that they doesn't support it! */ 6439 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6440 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6441 if (ret == 0) { 6442 fmtcap = cap; 6443 pcmcap = w->param.supp_pcm_size_rate; 6444 } else { 6445 fmtcap &= cap; 6446 pcmcap &= w->param.supp_pcm_size_rate; 6447 } 6448 ch->io[ret++] = as[ch->as].dacs[i]; 6449 } 6450 ch->io[ret] = -1; 6451 6452 ch->supp_stream_formats = fmtcap; 6453 ch->supp_pcm_size_rate = pcmcap; 6454 6455 /* 6456 * 8bit = 0 6457 * 16bit = 1 6458 * 20bit = 2 6459 * 24bit = 3 6460 * 32bit = 4 6461 */ 6462 if (ret > 0) { 6463 i = 0; 6464 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6465 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6466 ch->bit16 = 1; 6467 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6468 ch->bit16 = 0; 6469 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6470 ch->bit32 = 4; 6471 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6472 ch->bit32 = 3; 6473 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6474 ch->bit32 = 2; 6475 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6476 ch->fmtlist[i++] = 6477 SND_FORMAT(AFMT_S16_LE, 1, 0); 6478 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6479 if (ch->bit32 > 0) { 6480 if (!(devinfo->function.audio.quirks & 6481 HDA_QUIRK_FORCESTEREO)) 6482 ch->fmtlist[i++] = 6483 SND_FORMAT(AFMT_S32_LE, 1, 0); 6484 ch->fmtlist[i++] = 6485 SND_FORMAT(AFMT_S32_LE, 2, 0); 6486 } 6487 } 6488 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6489 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6490 } 6491 ch->fmtlist[i] = 0; 6492 i = 0; 6493 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6494 ch->pcmrates[i++] = 8000; 6495 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6496 ch->pcmrates[i++] = 11025; 6497 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6498 ch->pcmrates[i++] = 16000; 6499 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6500 ch->pcmrates[i++] = 22050; 6501 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6502 ch->pcmrates[i++] = 32000; 6503 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6504 ch->pcmrates[i++] = 44100; 6505 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6506 ch->pcmrates[i++] = 48000; 6507 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6508 ch->pcmrates[i++] = 88200; 6509 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6510 ch->pcmrates[i++] = 96000; 6511 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6512 ch->pcmrates[i++] = 176400; 6513 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6514 ch->pcmrates[i++] = 192000; 6515 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6516 ch->pcmrates[i] = 0; 6517 if (i > 0) { 6518 ch->caps.minspeed = ch->pcmrates[0]; 6519 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6520 } 6521 } 6522 6523 return (ret); 6524} 6525 6526static void 6527hdac_create_pcms(struct hdac_devinfo *devinfo) 6528{ 6529 struct hdac_softc *sc = devinfo->codec->sc; 6530 struct hdac_audio_as *as = devinfo->function.audio.as; 6531 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6532 6533 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6534 if (as[i].enable == 0) 6535 continue; 6536 if (as[i].dir == HDA_CTL_IN) { 6537 if (as[i].digital) 6538 drdev++; 6539 else 6540 ardev++; 6541 } else { 6542 if (as[i].digital) 6543 dpdev++; 6544 else 6545 apdev++; 6546 } 6547 } 6548 devinfo->function.audio.num_devs = 6549 max(ardev, apdev) + max(drdev, dpdev); 6550 devinfo->function.audio.devs = 6551 (struct hdac_pcm_devinfo *)malloc( 6552 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6553 M_HDAC, M_ZERO | M_NOWAIT); 6554 if (devinfo->function.audio.devs == NULL) { 6555 device_printf(sc->dev, 6556 "Unable to allocate memory for devices\n"); 6557 return; 6558 } 6559 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6560 devinfo->function.audio.devs[i].index = i; 6561 devinfo->function.audio.devs[i].devinfo = devinfo; 6562 devinfo->function.audio.devs[i].play = -1; 6563 devinfo->function.audio.devs[i].rec = -1; 6564 devinfo->function.audio.devs[i].digital = 255; 6565 } 6566 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6567 if (as[i].enable == 0) 6568 continue; 6569 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6570 if (devinfo->function.audio.devs[j].digital != 255 && 6571 (!devinfo->function.audio.devs[j].digital) == 6572 (!as[i].digital)) 6573 continue; 6574 if (as[i].dir == HDA_CTL_IN) { 6575 if (devinfo->function.audio.devs[j].rec >= 0) 6576 continue; 6577 devinfo->function.audio.devs[j].rec 6578 = as[i].chan; 6579 } else { 6580 if (devinfo->function.audio.devs[j].play >= 0) 6581 continue; 6582 devinfo->function.audio.devs[j].play 6583 = as[i].chan; 6584 } 6585 sc->chans[as[i].chan].pdevinfo = 6586 &devinfo->function.audio.devs[j]; 6587 devinfo->function.audio.devs[j].digital = 6588 as[i].digital; 6589 break; 6590 } 6591 } 6592 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6593 struct hdac_pcm_devinfo *pdevinfo = 6594 &devinfo->function.audio.devs[i]; 6595 pdevinfo->dev = 6596 device_add_child(sc->dev, "pcm", -1); 6597 device_set_ivars(pdevinfo->dev, 6598 (void *)pdevinfo); 6599 } 6600} 6601 6602static void 6603hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6604{ 6605 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6606 struct hdac_audio_ctl *ctl; 6607 struct hdac_softc *sc = devinfo->codec->sc; 6608 char buf[64]; 6609 int i, j, printed; 6610 6611 if (flag == 0) { 6612 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6613 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6614 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6615 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6616 } 6617 6618 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6619 if ((flag & (1 << j)) == 0) 6620 continue; 6621 i = 0; 6622 printed = 0; 6623 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6624 if (ctl->enable == 0 || 6625 ctl->widget->enable == 0) 6626 continue; 6627 if (!((pdevinfo->play >= 0 && 6628 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6629 (pdevinfo->rec >= 0 && 6630 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6631 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6632 continue; 6633 if ((ctl->ossmask & (1 << j)) == 0) 6634 continue; 6635 6636 if (printed == 0) { 6637 device_printf(pdevinfo->dev, "\n"); 6638 if (banner != NULL) { 6639 device_printf(pdevinfo->dev, "%s", banner); 6640 } else { 6641 device_printf(pdevinfo->dev, "Unknown Ctl"); 6642 } 6643 printf(" (OSS: %s)\n", 6644 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6645 buf, sizeof(buf))); 6646 device_printf(pdevinfo->dev, " |\n"); 6647 printed = 1; 6648 } 6649 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6650 ctl->widget->nid, 6651 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6652 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6653 printf(" %2d): ", ctl->index); 6654 else 6655 printf("): "); 6656 if (ctl->step > 0) { 6657 printf("%+d/%+ddB (%d steps)%s\n", 6658 (0 - ctl->offset) * (ctl->size + 1) / 4, 6659 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6660 ctl->step + 1, 6661 ctl->mute?" + mute":""); 6662 } else 6663 printf("%s\n", ctl->mute?"mute":""); 6664 } 6665 } 6666} 6667 6668static void 6669hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6670{ 6671 uint32_t cap; 6672 6673 cap = fcap; 6674 if (cap != 0) { 6675 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6676 device_printf(dev, " "); 6677 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6678 printf(" AC3"); 6679 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6680 printf(" FLOAT32"); 6681 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6682 printf(" PCM"); 6683 printf("\n"); 6684 } 6685 cap = pcmcap; 6686 if (cap != 0) { 6687 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6688 device_printf(dev, " "); 6689 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6690 printf(" 8"); 6691 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6692 printf(" 16"); 6693 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6694 printf(" 20"); 6695 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6696 printf(" 24"); 6697 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6698 printf(" 32"); 6699 printf(" bits,"); 6700 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6701 printf(" 8"); 6702 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6703 printf(" 11"); 6704 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6705 printf(" 16"); 6706 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6707 printf(" 22"); 6708 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6709 printf(" 32"); 6710 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6711 printf(" 44"); 6712 printf(" 48"); 6713 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6714 printf(" 88"); 6715 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6716 printf(" 96"); 6717 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6718 printf(" 176"); 6719 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6720 printf(" 192"); 6721 printf(" KHz\n"); 6722 } 6723} 6724 6725static void 6726hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6727{ 6728 uint32_t pincap; 6729 6730 pincap = w->wclass.pin.cap; 6731 6732 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6733 device_printf(sc->dev, " "); 6734 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6735 printf(" ISC"); 6736 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6737 printf(" TRQD"); 6738 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6739 printf(" PDC"); 6740 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6741 printf(" HP"); 6742 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6743 printf(" OUT"); 6744 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6745 printf(" IN"); 6746 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6747 printf(" BAL"); 6748 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6749 printf(" HDMI"); 6750 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6751 printf(" VREF["); 6752 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6753 printf(" 50"); 6754 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6755 printf(" 80"); 6756 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6757 printf(" 100"); 6758 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6759 printf(" GROUND"); 6760 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6761 printf(" HIZ"); 6762 printf(" ]"); 6763 } 6764 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6765 printf(" EAPD"); 6766 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6767 printf(" DP"); 6768 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6769 printf(" HBR"); 6770 printf("\n"); 6771 device_printf(sc->dev, " Pin config: 0x%08x\n", 6772 w->wclass.pin.config); 6773 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6774 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6775 printf(" HP"); 6776 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6777 printf(" IN"); 6778 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6779 printf(" OUT"); 6780 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6781 printf(" VREFs"); 6782 printf("\n"); 6783} 6784 6785static void 6786hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6787{ 6788 struct hdac_softc *sc = w->devinfo->codec->sc; 6789 6790 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6791 "jack %2d loc %2d color %7s misc %d%s\n", 6792 w->nid, conf, 6793 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6794 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6795 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6796 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6797 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6798 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6799 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6800 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6801 (w->enable == 0)?" [DISABLED]":""); 6802} 6803 6804static void 6805hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6806{ 6807 struct hdac_widget *w; 6808 int i; 6809 6810 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6811 w = hdac_widget_get(devinfo, i); 6812 if (w == NULL) 6813 continue; 6814 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6815 continue; 6816 hdac_dump_pin_config(w, w->wclass.pin.config); 6817 } 6818} 6819 6820static void 6821hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6822{ 6823 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6824 device_printf(sc->dev, " " 6825 "mute=%d step=%d size=%d offset=%d\n", 6826 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6827 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6828 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6829 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6830} 6831 6832static void 6833hdac_dump_nodes(struct hdac_devinfo *devinfo) 6834{ 6835 struct hdac_softc *sc = devinfo->codec->sc; 6836 static char *ossname[] = SOUND_DEVICE_NAMES; 6837 struct hdac_widget *w, *cw; 6838 char buf[64]; 6839 int i, j; 6840 6841 device_printf(sc->dev, "\n"); 6842 device_printf(sc->dev, "Default Parameter\n"); 6843 device_printf(sc->dev, "-----------------\n"); 6844 hdac_dump_audio_formats(sc->dev, 6845 devinfo->function.audio.supp_stream_formats, 6846 devinfo->function.audio.supp_pcm_size_rate); 6847 device_printf(sc->dev, " IN amp: 0x%08x\n", 6848 devinfo->function.audio.inamp_cap); 6849 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6850 devinfo->function.audio.outamp_cap); 6851 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6852 w = hdac_widget_get(devinfo, i); 6853 if (w == NULL) { 6854 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6855 continue; 6856 } 6857 device_printf(sc->dev, "\n"); 6858 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6859 (w->enable == 0) ? " [DISABLED]" : ""); 6860 device_printf(sc->dev, " Name: %s\n", w->name); 6861 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6862 w->param.widget_cap); 6863 if (w->param.widget_cap & 0x0ee1) { 6864 device_printf(sc->dev, " "); 6865 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6866 printf(" LRSWAP"); 6867 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6868 printf(" PWR"); 6869 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6870 printf(" DIGITAL"); 6871 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6872 printf(" UNSOL"); 6873 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6874 printf(" PROC"); 6875 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6876 printf(" STRIPE"); 6877 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 6878 if (j == 1) 6879 printf(" STEREO"); 6880 else if (j > 1) 6881 printf(" %dCH", j + 1); 6882 printf("\n"); 6883 } 6884 if (w->bindas != -1) { 6885 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6886 w->bindas, w->bindseqmask); 6887 } 6888 if (w->ossmask != 0 || w->ossdev >= 0) { 6889 device_printf(sc->dev, " OSS: %s", 6890 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6891 if (w->ossdev >= 0) 6892 printf(" (%s)", ossname[w->ossdev]); 6893 printf("\n"); 6894 } 6895 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6896 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6897 hdac_dump_audio_formats(sc->dev, 6898 w->param.supp_stream_formats, 6899 w->param.supp_pcm_size_rate); 6900 } else if (w->type == 6901 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6902 hdac_dump_pin(sc, w); 6903 if (w->param.eapdbtl != HDAC_INVALID) 6904 device_printf(sc->dev, " EAPD: 0x%08x\n", 6905 w->param.eapdbtl); 6906 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6907 w->param.outamp_cap != 0) 6908 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6909 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6910 w->param.inamp_cap != 0) 6911 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6912 if (w->nconns > 0) { 6913 device_printf(sc->dev, " connections: %d\n", w->nconns); 6914 device_printf(sc->dev, " |\n"); 6915 } 6916 for (j = 0; j < w->nconns; j++) { 6917 cw = hdac_widget_get(devinfo, w->conns[j]); 6918 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6919 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6920 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6921 if (cw == NULL) 6922 printf(" [UNKNOWN]"); 6923 else if (cw->enable == 0) 6924 printf(" [DISABLED]"); 6925 if (w->nconns > 1 && w->selconn == j && w->type != 6926 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6927 printf(" (selected)"); 6928 printf("\n"); 6929 } 6930 } 6931 6932} 6933 6934static void 6935hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6936{ 6937 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6938 struct hdac_widget *w, *cw; 6939 char buf[64]; 6940 int i, printed = 0; 6941 6942 if (depth > HDA_PARSE_MAXDEPTH) 6943 return; 6944 6945 w = hdac_widget_get(devinfo, nid); 6946 if (w == NULL || w->enable == 0) 6947 return; 6948 6949 if (depth == 0) 6950 device_printf(pdevinfo->dev, "%*s", 4, ""); 6951 else 6952 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6953 printf("nid=%d [%s]", w->nid, w->name); 6954 6955 if (depth > 0) { 6956 if (w->ossmask == 0) { 6957 printf("\n"); 6958 return; 6959 } 6960 printf(" [src: %s]", 6961 hdac_audio_ctl_ossmixer_mask2allname( 6962 w->ossmask, buf, sizeof(buf))); 6963 if (w->ossdev >= 0) { 6964 printf("\n"); 6965 return; 6966 } 6967 } 6968 printf("\n"); 6969 6970 for (i = 0; i < w->nconns; i++) { 6971 if (w->connsenable[i] == 0) 6972 continue; 6973 cw = hdac_widget_get(devinfo, w->conns[i]); 6974 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6975 continue; 6976 if (printed == 0) { 6977 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6978 printed = 1; 6979 } 6980 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6981 } 6982 6983} 6984 6985static void 6986hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6987{ 6988 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6989 struct hdac_softc *sc = devinfo->codec->sc; 6990 struct hdac_widget *w; 6991 int i, printed = 0; 6992 6993 if (pdevinfo->play < 0) 6994 return; 6995 6996 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6997 w = hdac_widget_get(devinfo, i); 6998 if (w == NULL || w->enable == 0) 6999 continue; 7000 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7001 continue; 7002 if (w->bindas != sc->chans[pdevinfo->play].as) 7003 continue; 7004 if (printed == 0) { 7005 printed = 1; 7006 device_printf(pdevinfo->dev, "\n"); 7007 device_printf(pdevinfo->dev, "Playback:\n"); 7008 } 7009 device_printf(pdevinfo->dev, "\n"); 7010 hdac_dump_dst_nid(pdevinfo, i, 0); 7011 } 7012} 7013 7014static void 7015hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7016{ 7017 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7018 struct hdac_softc *sc = devinfo->codec->sc; 7019 struct hdac_widget *w; 7020 int i; 7021 int printed = 0; 7022 7023 if (pdevinfo->rec < 0) 7024 return; 7025 7026 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7027 w = hdac_widget_get(devinfo, i); 7028 if (w == NULL || w->enable == 0) 7029 continue; 7030 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7031 continue; 7032 if (w->bindas != sc->chans[pdevinfo->rec].as) 7033 continue; 7034 if (printed == 0) { 7035 printed = 1; 7036 device_printf(pdevinfo->dev, "\n"); 7037 device_printf(pdevinfo->dev, "Record:\n"); 7038 } 7039 device_printf(pdevinfo->dev, "\n"); 7040 hdac_dump_dst_nid(pdevinfo, i, 0); 7041 } 7042} 7043 7044static void 7045hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7046{ 7047 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7048 struct hdac_widget *w; 7049 int i; 7050 int printed = 0; 7051 7052 if (pdevinfo->index != 0) 7053 return; 7054 7055 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7056 w = hdac_widget_get(devinfo, i); 7057 if (w == NULL || w->enable == 0) 7058 continue; 7059 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7060 continue; 7061 if (printed == 0) { 7062 printed = 1; 7063 device_printf(pdevinfo->dev, "\n"); 7064 device_printf(pdevinfo->dev, "Input Mix:\n"); 7065 } 7066 device_printf(pdevinfo->dev, "\n"); 7067 hdac_dump_dst_nid(pdevinfo, i, 0); 7068 } 7069} 7070 7071static void 7072hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7073{ 7074 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7075 nid_t *nids; 7076 int i; 7077 7078 if (pdevinfo->play >= 0) { 7079 i = pdevinfo->play; 7080 device_printf(pdevinfo->dev, "\n"); 7081 device_printf(pdevinfo->dev, "Playback:\n"); 7082 device_printf(pdevinfo->dev, "\n"); 7083 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7084 sc->chans[i].supp_pcm_size_rate); 7085 device_printf(pdevinfo->dev, " DAC:"); 7086 for (nids = sc->chans[i].io; *nids != -1; nids++) 7087 printf(" %d", *nids); 7088 printf("\n"); 7089 } 7090 if (pdevinfo->rec >= 0) { 7091 i = pdevinfo->rec; 7092 device_printf(pdevinfo->dev, "\n"); 7093 device_printf(pdevinfo->dev, "Record:\n"); 7094 device_printf(pdevinfo->dev, "\n"); 7095 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7096 sc->chans[i].supp_pcm_size_rate); 7097 device_printf(pdevinfo->dev, " ADC:"); 7098 for (nids = sc->chans[i].io; *nids != -1; nids++) 7099 printf(" %d", *nids); 7100 printf("\n"); 7101 } 7102} 7103 7104static void 7105hdac_release_resources(struct hdac_softc *sc) 7106{ 7107 int i, j; 7108 7109 if (sc == NULL) 7110 return; 7111 7112 hdac_lock(sc); 7113 sc->polling = 0; 7114 sc->poll_ival = 0; 7115 callout_stop(&sc->poll_hda); 7116 callout_stop(&sc->poll_hdac); 7117 callout_stop(&sc->poll_jack); 7118 hdac_reset(sc, 0); 7119 hdac_unlock(sc); 7120 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7121 callout_drain(&sc->poll_hda); 7122 callout_drain(&sc->poll_hdac); 7123 callout_drain(&sc->poll_jack); 7124 7125 hdac_irq_free(sc); 7126 7127 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7128 if (sc->codecs[i] == NULL) 7129 continue; 7130 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7131 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7132 if (sc->codecs[i]->fgs[j].node_type == 7133 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7134 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7135 M_HDAC); 7136 free(sc->codecs[i]->fgs[j].function.audio.as, 7137 M_HDAC); 7138 free(sc->codecs[i]->fgs[j].function.audio.devs, 7139 M_HDAC); 7140 } 7141 } 7142 free(sc->codecs[i]->fgs, M_HDAC); 7143 free(sc->codecs[i], M_HDAC); 7144 sc->codecs[i] = NULL; 7145 } 7146 7147 hdac_dma_free(sc, &sc->pos_dma); 7148 hdac_dma_free(sc, &sc->rirb_dma); 7149 hdac_dma_free(sc, &sc->corb_dma); 7150 for (i = 0; i < sc->num_chans; i++) { 7151 if (sc->chans[i].blkcnt > 0) 7152 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7153 } 7154 free(sc->chans, M_HDAC); 7155 if (sc->chan_dmat != NULL) { 7156 bus_dma_tag_destroy(sc->chan_dmat); 7157 sc->chan_dmat = NULL; 7158 } 7159 hdac_mem_free(sc); 7160 snd_mtxfree(sc->lock); 7161} 7162 7163/* This function surely going to make its way into upper level someday. */ 7164static void 7165hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7166{ 7167 const char *res = NULL; 7168 int i = 0, j, k, len, inv; 7169 7170 if (on != NULL) 7171 *on = 0; 7172 if (off != NULL) 7173 *off = 0; 7174 if (sc == NULL) 7175 return; 7176 if (resource_string_value(device_get_name(sc->dev), 7177 device_get_unit(sc->dev), "config", &res) != 0) 7178 return; 7179 if (!(res != NULL && strlen(res) > 0)) 7180 return; 7181 HDA_BOOTVERBOSE( 7182 device_printf(sc->dev, "HDA Config:"); 7183 ); 7184 for (;;) { 7185 while (res[i] != '\0' && 7186 (res[i] == ',' || isspace(res[i]) != 0)) 7187 i++; 7188 if (res[i] == '\0') { 7189 HDA_BOOTVERBOSE( 7190 printf("\n"); 7191 ); 7192 return; 7193 } 7194 j = i; 7195 while (res[j] != '\0' && 7196 !(res[j] == ',' || isspace(res[j]) != 0)) 7197 j++; 7198 len = j - i; 7199 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7200 inv = 2; 7201 else 7202 inv = 0; 7203 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7204 if (strncmp(res + i + inv, 7205 hdac_quirks_tab[k].key, len - inv) != 0) 7206 continue; 7207 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7208 continue; 7209 HDA_BOOTVERBOSE( 7210 printf(" %s%s", (inv != 0) ? "no" : "", 7211 hdac_quirks_tab[k].key); 7212 ); 7213 if (inv == 0 && on != NULL) 7214 *on |= hdac_quirks_tab[k].value; 7215 else if (inv != 0 && off != NULL) 7216 *off |= hdac_quirks_tab[k].value; 7217 break; 7218 } 7219 i = j; 7220 } 7221} 7222 7223static int 7224sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7225{ 7226 struct hdac_softc *sc; 7227 device_t dev; 7228 uint32_t ctl; 7229 int err, val; 7230 7231 dev = oidp->oid_arg1; 7232 sc = device_get_softc(dev); 7233 if (sc == NULL) 7234 return (EINVAL); 7235 hdac_lock(sc); 7236 val = sc->polling; 7237 hdac_unlock(sc); 7238 err = sysctl_handle_int(oidp, &val, 0, req); 7239 7240 if (err != 0 || req->newptr == NULL) 7241 return (err); 7242 if (val < 0 || val > 1) 7243 return (EINVAL); 7244 7245 hdac_lock(sc); 7246 if (val != sc->polling) { 7247 if (val == 0) { 7248 callout_stop(&sc->poll_hda); 7249 callout_stop(&sc->poll_hdac); 7250 hdac_unlock(sc); 7251 callout_drain(&sc->poll_hda); 7252 callout_drain(&sc->poll_hdac); 7253 hdac_lock(sc); 7254 sc->polling = 0; 7255 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7256 ctl |= HDAC_INTCTL_GIE; 7257 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7258 } else { 7259 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7260 ctl &= ~HDAC_INTCTL_GIE; 7261 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7262 hdac_unlock(sc); 7263 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7264 hdac_lock(sc); 7265 sc->polling = 1; 7266 hdac_poll_reinit(sc); 7267 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7268 } 7269 } 7270 hdac_unlock(sc); 7271 7272 return (err); 7273} 7274 7275static int 7276sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7277{ 7278 struct hdac_softc *sc; 7279 device_t dev; 7280 int err, val; 7281 7282 dev = oidp->oid_arg1; 7283 sc = device_get_softc(dev); 7284 if (sc == NULL) 7285 return (EINVAL); 7286 hdac_lock(sc); 7287 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7288 hdac_unlock(sc); 7289 err = sysctl_handle_int(oidp, &val, 0, req); 7290 7291 if (err != 0 || req->newptr == NULL) 7292 return (err); 7293 7294 if (val < 1) 7295 val = 1; 7296 if (val > 5000) 7297 val = 5000; 7298 val = ((uint64_t)val * hz) / 1000; 7299 if (val < 1) 7300 val = 1; 7301 if (val > (hz * 5)) 7302 val = hz * 5; 7303 7304 hdac_lock(sc); 7305 sc->poll_ival = val; 7306 hdac_unlock(sc); 7307 7308 return (err); 7309} 7310 7311static int 7312sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7313{ 7314 struct hdac_softc *sc; 7315 struct hdac_codec *codec; 7316 struct hdac_devinfo *devinfo; 7317 struct hdac_widget *w; 7318 device_t dev; 7319 uint32_t res, pincap, delay; 7320 int codec_index, fg_index; 7321 int i, err, val; 7322 nid_t cad; 7323 7324 dev = oidp->oid_arg1; 7325 sc = device_get_softc(dev); 7326 if (sc == NULL) 7327 return (EINVAL); 7328 val = 0; 7329 err = sysctl_handle_int(oidp, &val, 0, req); 7330 if (err != 0 || req->newptr == NULL || val == 0) 7331 return (err); 7332 7333 /* XXX: Temporary. For debugging. */ 7334 if (val == 100) { 7335 hdac_suspend(dev); 7336 return (0); 7337 } else if (val == 101) { 7338 hdac_resume(dev); 7339 return (0); 7340 } 7341 7342 hdac_lock(sc); 7343 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7344 codec = sc->codecs[codec_index]; 7345 if (codec == NULL) 7346 continue; 7347 cad = codec->cad; 7348 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7349 devinfo = &codec->fgs[fg_index]; 7350 if (devinfo->node_type != 7351 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7352 continue; 7353 7354 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7355 codec_index, devinfo->nid); 7356 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7357 w = hdac_widget_get(devinfo, i); 7358 if (w == NULL || w->type != 7359 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7360 continue; 7361 hdac_dump_pin_config(w, w->wclass.pin.config); 7362 pincap = w->wclass.pin.cap; 7363 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7364 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7365 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7366 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7367 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7368 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7369 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7370 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7371 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7372 delay = 0; 7373 hdac_command(sc, 7374 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7375 do { 7376 res = hdac_command(sc, 7377 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7378 if (res != 0x7fffffff && res != 0xffffffff) 7379 break; 7380 DELAY(10); 7381 } while (++delay < 10000); 7382 } else { 7383 delay = 0; 7384 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7385 w->nid), cad); 7386 } 7387 printf(" Sense: 0x%08x", res); 7388 if (delay > 0) 7389 printf(" delay %dus", delay * 10); 7390 } 7391 printf("\n"); 7392 } 7393 device_printf(dev, 7394 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7395 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7396 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7397 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7398 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7399 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7400 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7401 device_printf(dev, " GPI:"); 7402 res = hdac_command(sc, 7403 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7404 printf(" data=0x%08x", res); 7405 res = hdac_command(sc, 7406 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7407 cad); 7408 printf(" wake=0x%08x", res); 7409 res = hdac_command(sc, 7410 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7411 cad); 7412 printf(" unsol=0x%08x", res); 7413 res = hdac_command(sc, 7414 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7415 printf(" sticky=0x%08x\n", res); 7416 } 7417 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7418 device_printf(dev, " GPO:"); 7419 res = hdac_command(sc, 7420 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7421 printf(" data=0x%08x\n", res); 7422 } 7423 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7424 device_printf(dev, "GPIO:"); 7425 res = hdac_command(sc, 7426 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7427 printf(" data=0x%08x", res); 7428 res = hdac_command(sc, 7429 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7430 printf(" enable=0x%08x", res); 7431 res = hdac_command(sc, 7432 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7433 printf(" direction=0x%08x\n", res); 7434 res = hdac_command(sc, 7435 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7436 device_printf(dev, " wake=0x%08x", res); 7437 res = hdac_command(sc, 7438 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7439 cad); 7440 printf(" unsol=0x%08x", res); 7441 res = hdac_command(sc, 7442 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7443 printf(" sticky=0x%08x\n", res); 7444 } 7445 } 7446 } 7447 hdac_unlock(sc); 7448 return (0); 7449} 7450 7451static void 7452hdac_attach2(void *arg) 7453{ 7454 struct hdac_codec *codec; 7455 struct hdac_softc *sc; 7456 struct hdac_audio_ctl *ctl; 7457 uint32_t quirks_on, quirks_off; 7458 int codec_index, fg_index; 7459 int i, dmaalloc = 0; 7460 struct hdac_devinfo *devinfo; 7461 7462 sc = (struct hdac_softc *)arg; 7463 7464 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7465 7466 HDA_BOOTHVERBOSE( 7467 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7468 quirks_on, quirks_off); 7469 ); 7470 7471 hdac_lock(sc); 7472 7473 /* Remove ourselves from the config hooks */ 7474 if (sc->intrhook.ich_func != NULL) { 7475 config_intrhook_disestablish(&sc->intrhook); 7476 sc->intrhook.ich_func = NULL; 7477 } 7478 7479 /* Start the corb and rirb engines */ 7480 HDA_BOOTHVERBOSE( 7481 device_printf(sc->dev, "Starting CORB Engine...\n"); 7482 ); 7483 hdac_corb_start(sc); 7484 HDA_BOOTHVERBOSE( 7485 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7486 ); 7487 hdac_rirb_start(sc); 7488 7489 HDA_BOOTHVERBOSE( 7490 device_printf(sc->dev, 7491 "Enabling controller interrupt...\n"); 7492 ); 7493 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7494 HDAC_GCTL_UNSOL); 7495 if (sc->polling == 0) { 7496 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7497 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7498 } else { 7499 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7500 } 7501 DELAY(1000); 7502 7503 HDA_BOOTHVERBOSE( 7504 device_printf(sc->dev, 7505 "Scanning HDA codecs ...\n"); 7506 ); 7507 hdac_scan_codecs(sc); 7508 7509 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7510 codec = sc->codecs[codec_index]; 7511 if (codec == NULL) 7512 continue; 7513 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7514 devinfo = &codec->fgs[fg_index]; 7515 HDA_BOOTVERBOSE( 7516 device_printf(sc->dev, "\n"); 7517 device_printf(sc->dev, 7518 "Processing %s FG cad=%d nid=%d...\n", 7519 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7520 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7521 "unknown", 7522 devinfo->codec->cad, devinfo->nid); 7523 ); 7524 if (devinfo->node_type != 7525 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7526 HDA_BOOTHVERBOSE( 7527 device_printf(sc->dev, 7528 "Powering down...\n"); 7529 ); 7530 hdac_command(sc, 7531 HDA_CMD_SET_POWER_STATE(codec->cad, 7532 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7533 codec->cad); 7534 continue; 7535 } 7536 7537 HDA_BOOTHVERBOSE( 7538 device_printf(sc->dev, "Powering up...\n"); 7539 ); 7540 hdac_powerup(devinfo); 7541 HDA_BOOTHVERBOSE( 7542 device_printf(sc->dev, "Parsing audio FG...\n"); 7543 ); 7544 hdac_audio_parse(devinfo); 7545 HDA_BOOTHVERBOSE( 7546 device_printf(sc->dev, "Parsing Ctls...\n"); 7547 ); 7548 hdac_audio_ctl_parse(devinfo); 7549 HDA_BOOTHVERBOSE( 7550 device_printf(sc->dev, "Parsing vendor patch...\n"); 7551 ); 7552 hdac_vendor_patch_parse(devinfo); 7553 devinfo->function.audio.quirks |= quirks_on; 7554 devinfo->function.audio.quirks &= ~quirks_off; 7555 7556 HDA_BOOTHVERBOSE( 7557 device_printf(sc->dev, "Disabling nonaudio...\n"); 7558 ); 7559 hdac_audio_disable_nonaudio(devinfo); 7560 HDA_BOOTHVERBOSE( 7561 device_printf(sc->dev, "Disabling useless...\n"); 7562 ); 7563 hdac_audio_disable_useless(devinfo); 7564 HDA_BOOTVERBOSE( 7565 device_printf(sc->dev, "Patched pins configuration:\n"); 7566 hdac_dump_pin_configs(devinfo); 7567 ); 7568 HDA_BOOTHVERBOSE( 7569 device_printf(sc->dev, "Parsing pin associations...\n"); 7570 ); 7571 hdac_audio_as_parse(devinfo); 7572 HDA_BOOTHVERBOSE( 7573 device_printf(sc->dev, "Building AFG tree...\n"); 7574 ); 7575 hdac_audio_build_tree(devinfo); 7576 HDA_BOOTHVERBOSE( 7577 device_printf(sc->dev, "Disabling unassociated " 7578 "widgets...\n"); 7579 ); 7580 hdac_audio_disable_unas(devinfo); 7581 HDA_BOOTHVERBOSE( 7582 device_printf(sc->dev, "Disabling nonselected " 7583 "inputs...\n"); 7584 ); 7585 hdac_audio_disable_notselected(devinfo); 7586 HDA_BOOTHVERBOSE( 7587 device_printf(sc->dev, "Disabling useless...\n"); 7588 ); 7589 hdac_audio_disable_useless(devinfo); 7590 HDA_BOOTHVERBOSE( 7591 device_printf(sc->dev, "Disabling " 7592 "crossassociatement connections...\n"); 7593 ); 7594 hdac_audio_disable_crossas(devinfo); 7595 HDA_BOOTHVERBOSE( 7596 device_printf(sc->dev, "Disabling useless...\n"); 7597 ); 7598 hdac_audio_disable_useless(devinfo); 7599 HDA_BOOTHVERBOSE( 7600 device_printf(sc->dev, "Binding associations to channels...\n"); 7601 ); 7602 hdac_audio_bind_as(devinfo); 7603 HDA_BOOTHVERBOSE( 7604 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7605 ); 7606 hdac_audio_assign_names(devinfo); 7607 HDA_BOOTHVERBOSE( 7608 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7609 ); 7610 hdac_audio_assign_mixers(devinfo); 7611 HDA_BOOTHVERBOSE( 7612 device_printf(sc->dev, "Preparing pin controls...\n"); 7613 ); 7614 hdac_audio_prepare_pin_ctrl(devinfo); 7615 HDA_BOOTHVERBOSE( 7616 device_printf(sc->dev, "AFG commit...\n"); 7617 ); 7618 hdac_audio_commit(devinfo); 7619 HDA_BOOTHVERBOSE( 7620 device_printf(sc->dev, "HP switch init...\n"); 7621 ); 7622 hdac_hp_switch_init(devinfo); 7623 7624 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7625 dmaalloc == 0) { 7626 if (hdac_dma_alloc(sc, &sc->pos_dma, 7627 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7628 HDA_BOOTVERBOSE( 7629 device_printf(sc->dev, "Failed to " 7630 "allocate DMA pos buffer " 7631 "(non-fatal)\n"); 7632 ); 7633 } else 7634 dmaalloc = 1; 7635 } 7636 7637 HDA_BOOTHVERBOSE( 7638 device_printf(sc->dev, "Creating PCM devices...\n"); 7639 ); 7640 hdac_create_pcms(devinfo); 7641 7642 HDA_BOOTVERBOSE( 7643 if (devinfo->function.audio.quirks != 0) { 7644 device_printf(sc->dev, "FG config/quirks:"); 7645 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7646 if ((devinfo->function.audio.quirks & 7647 hdac_quirks_tab[i].value) == 7648 hdac_quirks_tab[i].value) 7649 printf(" %s", hdac_quirks_tab[i].key); 7650 } 7651 printf("\n"); 7652 } 7653 7654 device_printf(sc->dev, "\n"); 7655 device_printf(sc->dev, "+-------------------+\n"); 7656 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7657 device_printf(sc->dev, "+-------------------+\n"); 7658 hdac_dump_nodes(devinfo); 7659 ); 7660 7661 HDA_BOOTHVERBOSE( 7662 device_printf(sc->dev, "\n"); 7663 device_printf(sc->dev, "+------------------------+\n"); 7664 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7665 device_printf(sc->dev, "+------------------------+\n"); 7666 device_printf(sc->dev, "\n"); 7667 i = 0; 7668 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7669 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7670 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7671 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7672 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7673 ctl->index); 7674 if (ctl->childwidget != NULL) 7675 printf(" cnid %3d", ctl->childwidget->nid); 7676 else 7677 printf(" "); 7678 printf(" ossmask=0x%08x\n", 7679 ctl->ossmask); 7680 device_printf(sc->dev, 7681 " mute: %d step: %3d size: %3d off: %3d%s\n", 7682 ctl->mute, ctl->step, ctl->size, ctl->offset, 7683 (ctl->enable == 0) ? " [DISABLED]" : 7684 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7685 } 7686 ); 7687 } 7688 } 7689 hdac_unlock(sc); 7690 7691 HDA_BOOTVERBOSE( 7692 device_printf(sc->dev, "\n"); 7693 ); 7694 7695 bus_generic_attach(sc->dev); 7696 7697 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7698 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7699 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7700 sysctl_hdac_polling, "I", "Enable polling mode"); 7701 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7702 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7703 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7704 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7705 "Controller/Jack Sense polling interval (1-1000 ms)"); 7706 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7707 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7708 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7709 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7710} 7711 7712/**************************************************************************** 7713 * int hdac_suspend(device_t) 7714 * 7715 * Suspend and power down HDA bus and codecs. 7716 ****************************************************************************/ 7717static int 7718hdac_suspend(device_t dev) 7719{ 7720 struct hdac_softc *sc; 7721 struct hdac_codec *codec; 7722 struct hdac_devinfo *devinfo; 7723 int codec_index, fg_index, i; 7724 7725 HDA_BOOTHVERBOSE( 7726 device_printf(dev, "Suspend...\n"); 7727 ); 7728 7729 sc = device_get_softc(dev); 7730 hdac_lock(sc); 7731 7732 HDA_BOOTHVERBOSE( 7733 device_printf(dev, "Stop streams...\n"); 7734 ); 7735 for (i = 0; i < sc->num_chans; i++) { 7736 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7737 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7738 hdac_channel_stop(sc, &sc->chans[i]); 7739 } 7740 } 7741 7742 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7743 codec = sc->codecs[codec_index]; 7744 if (codec == NULL) 7745 continue; 7746 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7747 devinfo = &codec->fgs[fg_index]; 7748 HDA_BOOTHVERBOSE( 7749 device_printf(dev, 7750 "Power down FG" 7751 " cad=%d nid=%d to the D3 state...\n", 7752 codec->cad, devinfo->nid); 7753 ); 7754 hdac_command(sc, 7755 HDA_CMD_SET_POWER_STATE(codec->cad, 7756 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7757 codec->cad); 7758 } 7759 } 7760 7761 HDA_BOOTHVERBOSE( 7762 device_printf(dev, "Reset controller...\n"); 7763 ); 7764 callout_stop(&sc->poll_hda); 7765 callout_stop(&sc->poll_hdac); 7766 callout_stop(&sc->poll_jack); 7767 hdac_reset(sc, 0); 7768 hdac_unlock(sc); 7769 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7770 callout_drain(&sc->poll_hda); 7771 callout_drain(&sc->poll_hdac); 7772 callout_drain(&sc->poll_jack); 7773 7774 HDA_BOOTHVERBOSE( 7775 device_printf(dev, "Suspend done\n"); 7776 ); 7777 7778 return (0); 7779} 7780 7781/**************************************************************************** 7782 * int hdac_resume(device_t) 7783 * 7784 * Powerup and restore HDA bus and codecs state. 7785 ****************************************************************************/ 7786static int 7787hdac_resume(device_t dev) 7788{ 7789 struct hdac_softc *sc; 7790 struct hdac_codec *codec; 7791 struct hdac_devinfo *devinfo; 7792 int codec_index, fg_index, i; 7793 7794 HDA_BOOTHVERBOSE( 7795 device_printf(dev, "Resume...\n"); 7796 ); 7797 7798 sc = device_get_softc(dev); 7799 hdac_lock(sc); 7800 7801 /* Quiesce everything */ 7802 HDA_BOOTHVERBOSE( 7803 device_printf(dev, "Reset controller...\n"); 7804 ); 7805 hdac_reset(sc, 1); 7806 7807 /* Initialize the CORB and RIRB */ 7808 hdac_corb_init(sc); 7809 hdac_rirb_init(sc); 7810 7811 /* Start the corb and rirb engines */ 7812 HDA_BOOTHVERBOSE( 7813 device_printf(dev, "Starting CORB Engine...\n"); 7814 ); 7815 hdac_corb_start(sc); 7816 HDA_BOOTHVERBOSE( 7817 device_printf(dev, "Starting RIRB Engine...\n"); 7818 ); 7819 hdac_rirb_start(sc); 7820 7821 HDA_BOOTHVERBOSE( 7822 device_printf(dev, 7823 "Enabling controller interrupt...\n"); 7824 ); 7825 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7826 HDAC_GCTL_UNSOL); 7827 if (sc->polling == 0) { 7828 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7829 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7830 } else { 7831 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7832 } 7833 DELAY(1000); 7834 7835 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7836 codec = sc->codecs[codec_index]; 7837 if (codec == NULL) 7838 continue; 7839 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7840 devinfo = &codec->fgs[fg_index]; 7841 if (devinfo->node_type != 7842 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7843 HDA_BOOTHVERBOSE( 7844 device_printf(dev, 7845 "Power down unsupported non-audio FG" 7846 " cad=%d nid=%d to the D3 state...\n", 7847 codec->cad, devinfo->nid); 7848 ); 7849 hdac_command(sc, 7850 HDA_CMD_SET_POWER_STATE(codec->cad, 7851 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7852 codec->cad); 7853 continue; 7854 } 7855 7856 HDA_BOOTHVERBOSE( 7857 device_printf(dev, 7858 "Power up audio FG cad=%d nid=%d...\n", 7859 devinfo->codec->cad, devinfo->nid); 7860 ); 7861 hdac_powerup(devinfo); 7862 HDA_BOOTHVERBOSE( 7863 device_printf(dev, "AFG commit...\n"); 7864 ); 7865 hdac_audio_commit(devinfo); 7866 HDA_BOOTHVERBOSE( 7867 device_printf(dev, "HP switch init...\n"); 7868 ); 7869 hdac_hp_switch_init(devinfo); 7870 7871 hdac_unlock(sc); 7872 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7873 struct hdac_pcm_devinfo *pdevinfo = 7874 &devinfo->function.audio.devs[i]; 7875 HDA_BOOTHVERBOSE( 7876 device_printf(pdevinfo->dev, 7877 "OSS mixer reinitialization...\n"); 7878 ); 7879 if (mixer_reinit(pdevinfo->dev) == -1) 7880 device_printf(pdevinfo->dev, 7881 "unable to reinitialize the mixer\n"); 7882 } 7883 hdac_lock(sc); 7884 } 7885 } 7886 7887 HDA_BOOTHVERBOSE( 7888 device_printf(dev, "Start streams...\n"); 7889 ); 7890 for (i = 0; i < sc->num_chans; i++) { 7891 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7892 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7893 hdac_channel_start(sc, &sc->chans[i]); 7894 } 7895 } 7896 7897 hdac_unlock(sc); 7898 7899 HDA_BOOTHVERBOSE( 7900 device_printf(dev, "Resume done\n"); 7901 ); 7902 7903 return (0); 7904} 7905/**************************************************************************** 7906 * int hdac_detach(device_t) 7907 * 7908 * Detach and free up resources utilized by the hdac device. 7909 ****************************************************************************/ 7910static int 7911hdac_detach(device_t dev) 7912{ 7913 struct hdac_softc *sc; 7914 device_t *devlist; 7915 int i, devcount, error; 7916 7917 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7918 return (error); 7919 for (i = 0; i < devcount; i++) { 7920 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7921 free(devlist, M_TEMP); 7922 return (error); 7923 } 7924 } 7925 free(devlist, M_TEMP); 7926 7927 sc = device_get_softc(dev); 7928 hdac_release_resources(sc); 7929 7930 return (0); 7931} 7932 7933static int 7934hdac_print_child(device_t dev, device_t child) 7935{ 7936 struct hdac_pcm_devinfo *pdevinfo = 7937 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7938 int retval; 7939 7940 retval = bus_print_child_header(dev, child); 7941 retval += printf(" at cad %d nid %d", 7942 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7943 retval += bus_print_child_footer(dev, child); 7944 7945 return (retval); 7946} 7947 7948static device_method_t hdac_methods[] = { 7949 /* device interface */ 7950 DEVMETHOD(device_probe, hdac_probe), 7951 DEVMETHOD(device_attach, hdac_attach), 7952 DEVMETHOD(device_detach, hdac_detach), 7953 DEVMETHOD(device_suspend, hdac_suspend), 7954 DEVMETHOD(device_resume, hdac_resume), 7955 /* Bus interface */ 7956 DEVMETHOD(bus_print_child, hdac_print_child), 7957 { 0, 0 } 7958}; 7959 7960static driver_t hdac_driver = { 7961 "hdac", 7962 hdac_methods, 7963 sizeof(struct hdac_softc), 7964}; 7965 7966static devclass_t hdac_devclass; 7967 7968DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7969MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7970MODULE_VERSION(snd_hda, 1); 7971 7972static int 7973hdac_pcm_probe(device_t dev) 7974{ 7975 struct hdac_pcm_devinfo *pdevinfo = 7976 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7977 char buf[128]; 7978 7979 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7980 hdac_codec_name(pdevinfo->devinfo->codec), 7981 pdevinfo->index, 7982 (pdevinfo->digital == 3)?"DisplayPort": 7983 ((pdevinfo->digital == 2)?"HDMI": 7984 ((pdevinfo->digital)?"Digital":"Analog"))); 7985 device_set_desc_copy(dev, buf); 7986 return (0); 7987} 7988 7989static int 7990hdac_pcm_attach(device_t dev) 7991{ 7992 struct hdac_pcm_devinfo *pdevinfo = 7993 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7994 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7995 char status[SND_STATUSLEN]; 7996 int i; 7997 7998 pdevinfo->chan_size = pcm_getbuffersize(dev, 7999 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8000 8001 HDA_BOOTVERBOSE( 8002 device_printf(dev, "+--------------------------------------+\n"); 8003 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8004 device_printf(dev, "+--------------------------------------+\n"); 8005 hdac_dump_pcmchannels(pdevinfo); 8006 device_printf(dev, "\n"); 8007 device_printf(dev, "+-------------------------------+\n"); 8008 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8009 device_printf(dev, "+-------------------------------+\n"); 8010 hdac_dump_dac(pdevinfo); 8011 hdac_dump_adc(pdevinfo); 8012 hdac_dump_mix(pdevinfo); 8013 device_printf(dev, "\n"); 8014 device_printf(dev, "+-------------------------+\n"); 8015 device_printf(dev, "| DUMPING Volume Controls |\n"); 8016 device_printf(dev, "+-------------------------+\n"); 8017 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8018 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8019 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8020 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8021 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8022 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8023 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8024 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8025 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8026 hdac_dump_ctls(pdevinfo, NULL, 0); 8027 device_printf(dev, "\n"); 8028 ); 8029 8030 if (resource_int_value(device_get_name(dev), 8031 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8032 i &= HDA_BLK_ALIGN; 8033 if (i < HDA_BLK_MIN) 8034 i = HDA_BLK_MIN; 8035 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8036 i = 0; 8037 while (pdevinfo->chan_blkcnt >> i) 8038 i++; 8039 pdevinfo->chan_blkcnt = 1 << (i - 1); 8040 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8041 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8042 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8043 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8044 } else 8045 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8046 8047 /* 8048 * We don't register interrupt handler with snd_setup_intr 8049 * in pcm device. Mark pcm device as MPSAFE manually. 8050 */ 8051 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8052 8053 HDA_BOOTHVERBOSE( 8054 device_printf(dev, "OSS mixer initialization...\n"); 8055 ); 8056 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8057 device_printf(dev, "Can't register mixer\n"); 8058 8059 HDA_BOOTHVERBOSE( 8060 device_printf(dev, "Registering PCM channels...\n"); 8061 ); 8062 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8063 (pdevinfo->rec >= 0)?1:0) != 0) 8064 device_printf(dev, "Can't register PCM\n"); 8065 8066 pdevinfo->registered++; 8067 8068 if (pdevinfo->play >= 0) 8069 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8070 if (pdevinfo->rec >= 0) 8071 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8072 8073 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8074 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8075 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8076 pcm_setstatus(dev, status); 8077 8078 return (0); 8079} 8080 8081static int 8082hdac_pcm_detach(device_t dev) 8083{ 8084 struct hdac_pcm_devinfo *pdevinfo = 8085 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8086 int err; 8087 8088 if (pdevinfo->registered > 0) { 8089 err = pcm_unregister(dev); 8090 if (err != 0) 8091 return (err); 8092 } 8093 8094 return (0); 8095} 8096 8097static device_method_t hdac_pcm_methods[] = { 8098 /* device interface */ 8099 DEVMETHOD(device_probe, hdac_pcm_probe), 8100 DEVMETHOD(device_attach, hdac_pcm_attach), 8101 DEVMETHOD(device_detach, hdac_pcm_detach), 8102 { 0, 0 } 8103}; 8104 8105static driver_t hdac_pcm_driver = { 8106 "pcm", 8107 hdac_pcm_methods, 8108 PCM_SOFTC_SIZE, 8109}; 8110 8111DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8112 8113