hdac.c revision 167609
1139825Simp/*- 2103619Sgrehan * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3103619Sgrehan * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4103619Sgrehan * All rights reserved. 5103619Sgrehan * 6103619Sgrehan * Redistribution and use in source and binary forms, with or without 7103619Sgrehan * modification, are permitted provided that the following conditions 8103619Sgrehan * are met: 9103619Sgrehan * 1. Redistributions of source code must retain the above copyright 10103619Sgrehan * notice, this list of conditions and the following disclaimer. 11103619Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 12103619Sgrehan * notice, this list of conditions and the following disclaimer in the 13103619Sgrehan * documentation and/or other materials provided with the distribution. 14103619Sgrehan * 15103619Sgrehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16103619Sgrehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17103619Sgrehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18103619Sgrehan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19103619Sgrehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20103619Sgrehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21103619Sgrehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22103619Sgrehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23103619Sgrehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24103619Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25103619Sgrehan * SUCH DAMAGE. 26103619Sgrehan */ 27103619Sgrehan 28103619Sgrehan/* 29103619Sgrehan * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 30103619Sgrehan * that this driver still in its early stage, and possible of rewrite are 31103619Sgrehan * pretty much guaranteed. There are supposedly several distinct parent/child 32103619Sgrehan * busses to make this "perfect", but as for now and for the sake of 33103619Sgrehan * simplicity, everything is gobble up within single source. 34103619Sgrehan * 35103619Sgrehan * List of subsys: 36103619Sgrehan * 1) HDA Controller support 37103619Sgrehan * 2) HDA Codecs support, which may include 38131102Sgrehan * - HDA 39103619Sgrehan * - Modem 40103619Sgrehan * - HDMI 41103619Sgrehan * 3) Widget parser - the real magic of why this driver works on so 42103619Sgrehan * many hardwares with minimal vendor specific quirk. The original 43103619Sgrehan * parser was written using Ruby and can be found at 44103619Sgrehan * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45103619Sgrehan * ruby parser take the verbose dmesg dump as its input. Refer to 46103619Sgrehan * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47103619Sgrehan * interesting documents, especially UAA (Universal Audio Architecture). 48103619Sgrehan * 4) Possible vendor specific support. 49103619Sgrehan * (snd_hda_intel, snd_hda_ati, etc..) 50133589Smarius * 51153050Smarius * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52103619Sgrehan * Compaq V3000 with Conexant HDA. 53103619Sgrehan * 54103619Sgrehan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55103619Sgrehan * * * 56103619Sgrehan * * This driver is a collaborative effort made by: * 57103619Sgrehan * * * 58103619Sgrehan * * Stephane E. Potvin <sepotvin@videotron.ca> * 59131400Sgrehan * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60131400Sgrehan * * Wesley Morgan <morganw@chemikals.org> * 61131400Sgrehan * * Daniel Eischen <deischen@FreeBSD.org> * 62131400Sgrehan * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63131400Sgrehan * * Ariff Abdullah <ariff@FreeBSD.org> * 64131400Sgrehan * * * 65131400Sgrehan * * ....and various people from freebsd-multimedia@FreeBSD.org * 66131400Sgrehan * * * 67131400Sgrehan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 68131400Sgrehan */ 69103619Sgrehan 70103619Sgrehan#include <sys/ctype.h> 71103619Sgrehan 72103619Sgrehan#include <dev/sound/pcm/sound.h> 73103619Sgrehan#include <dev/pci/pcireg.h> 74103619Sgrehan#include <dev/pci/pcivar.h> 75103619Sgrehan 76103619Sgrehan#include <dev/sound/pci/hda/hdac_private.h> 77103619Sgrehan#include <dev/sound/pci/hda/hdac_reg.h> 78103619Sgrehan#include <dev/sound/pci/hda/hda_reg.h> 79103619Sgrehan#include <dev/sound/pci/hda/hdac.h> 80103619Sgrehan 81103619Sgrehan#include "mixer_if.h" 82103619Sgrehan 83103619Sgrehan#define HDA_DRV_TEST_REV "20070316_0041" 84153050Smarius#define HDA_WIDGET_PARSER_REV 1 85103619Sgrehan 86103619SgrehanSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 167609 2007-03-15 17:23:38Z ariff $"); 87103619Sgrehan 88103619Sgrehan#undef HDA_DEBUG_ENABLED 89103619Sgrehan#define HDA_DEBUG_ENABLED 1 90103619Sgrehan 91103619Sgrehan#ifdef HDA_DEBUG_ENABLED 92103619Sgrehan#define HDA_DEBUG(stmt) do { \ 93103619Sgrehan stmt \ 94103619Sgrehan} while(0) 95103619Sgrehan#else 96103619Sgrehan#define HDA_DEBUG(stmt) 97103619Sgrehan#endif 98103619Sgrehan 99103619Sgrehan#define HDA_BOOTVERBOSE(stmt) do { \ 100103619Sgrehan if (bootverbose) { \ 101103619Sgrehan stmt \ 102103619Sgrehan } \ 103103619Sgrehan} while(0) 104103619Sgrehan 105103619Sgrehan#if 1 106103619Sgrehan#undef HDAC_INTR_EXTRA 107103619Sgrehan#define HDAC_INTR_EXTRA 1 108103619Sgrehan#endif 109103619Sgrehan 110186128Snwhitehorn#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111186128Snwhitehorn#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112133589Smarius#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113153050Smarius#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114153050Smarius 115153050Smarius#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116153050Smarius#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117153050Smarius (fl) == 0xffffffff || \ 118153050Smarius (((fl) & 0xffff0000) == 0xffff0000 && \ 119133589Smarius ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120103619Sgrehan (((fl) & 0x0000ffff) == 0x0000ffff && \ 121103619Sgrehan ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122103619Sgrehan#define HDA_MATCH_ALL 0xffffffff 123103619Sgrehan#define HDAC_INVALID 0xffffffff 124103619Sgrehan 125103619Sgrehan#define HDA_MODEL_CONSTRUCT(vendor, model) \ 126103619Sgrehan (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 127103619Sgrehan 128103619Sgrehan/* Controller models */ 129103619Sgrehan 130103619Sgrehan/* Intel */ 131103619Sgrehan#define INTEL_VENDORID 0x8086 132103619Sgrehan#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 133103619Sgrehan#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 134103619Sgrehan#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 135103619Sgrehan#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 136103619Sgrehan#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 137103619Sgrehan 138103619Sgrehan/* Nvidia */ 139103619Sgrehan#define NVIDIA_VENDORID 0x10de 140112428Sgrehan#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 141112428Sgrehan#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 142103619Sgrehan#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 143112428Sgrehan#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 144183882Snwhitehorn#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 145183882Snwhitehorn#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 146112428Sgrehan#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 147103619Sgrehan 148103619Sgrehan/* ATI */ 149103619Sgrehan#define ATI_VENDORID 0x1002 150103619Sgrehan#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 151103619Sgrehan#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 152103619Sgrehan#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 153108991Sbenno 154108991Sbenno/* VIA */ 155186805Snwhitehorn#define VIA_VENDORID 0x1106 156108991Sbenno#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 157108991Sbenno#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 158108991Sbenno 159108991Sbenno/* SiS */ 160103619Sgrehan#define SIS_VENDORID 0x1039 161103619Sgrehan#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 162108991Sbenno#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 163108991Sbenno 164108991Sbenno/* OEM/subvendors */ 165108991Sbenno 166186805Snwhitehorn/* Intel */ 167186805Snwhitehorn#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 168186805Snwhitehorn 169108991Sbenno/* HP/Compaq */ 170108991Sbenno#define HP_VENDORID 0x103c 171103619Sgrehan#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 172108991Sbenno#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 173103619Sgrehan#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 174108991Sbenno#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 175103619Sgrehan#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 176108991Sbenno#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 177108991Sbenno/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 178108991Sbenno#define HP_NX6325_SUBVENDORX 0x103c30b0 179103619Sgrehan 180103619Sgrehan/* Dell */ 181103619Sgrehan#define DELL_VENDORID 0x1028 182103619Sgrehan#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 183103619Sgrehan#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 184103619Sgrehan#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 185103619Sgrehan 186103619Sgrehan/* Clevo */ 187103619Sgrehan#define CLEVO_VENDORID 0x1558 188103619Sgrehan#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 189178599Smarcel#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 190178599Smarcel 191178599Smarcel/* Acer */ 192108991Sbenno#define ACER_VENDORID 0x1025 193178599Smarcel#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 194178599Smarcel#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 195108991Sbenno 196108991Sbenno/* Asus */ 197108991Sbenno#define ASUS_VENDORID 0x1043 198186728Snwhitehorn#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 199186728Snwhitehorn#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 200186728Snwhitehorn#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 201178599Smarcel#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 202178599Smarcel#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 203178599Smarcel#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 204178599Smarcel 205178599Smarcel/* IBM / Lenovo */ 206178599Smarcel#define IBM_VENDORID 0x1014 207178599Smarcel#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 208108991Sbenno#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 209108991Sbenno 210108991Sbenno/* Lenovo */ 211178599Smarcel#define LENOVO_VENDORID 0x17aa 212108991Sbenno#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 213108991Sbenno#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 214178599Smarcel 215178599Smarcel/* Samsung */ 216178599Smarcel#define SAMSUNG_VENDORID 0x144d 217108991Sbenno#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 218178599Smarcel#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 219178599Smarcel 220178599Smarcel/* Medion ? */ 221103619Sgrehan#define MEDION_VENDORID 0x161f 222103619Sgrehan#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 223103619Sgrehan#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 224103619Sgrehan 225103619Sgrehan/* 226103619Sgrehan * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 227110080Sbenno * instead of their own, which is beyond my comprehension 228110080Sbenno * (see HDA_CODEC_STAC9221 below). 229110080Sbenno */ 230110080Sbenno#define APPLE_INTEL_MAC 0x76808384 231110080Sbenno 232110080Sbenno/* LG Electronics */ 233110080Sbenno#define LG_VENDORID 0x1854 234110080Sbenno#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 235110080Sbenno#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 236110080Sbenno 237110080Sbenno/* Fujitsu Siemens */ 238103619Sgrehan#define FS_VENDORID 0x1734 239103619Sgrehan#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 240103619Sgrehan#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 241103619Sgrehan 242103619Sgrehan/* Toshiba */ 243103619Sgrehan#define TOSHIBA_VENDORID 0x1179 244103619Sgrehan#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 245103619Sgrehan#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 246103619Sgrehan 247103619Sgrehan/* Micro-Star International (MSI) */ 248103619Sgrehan#define MSI_VENDORID 0x1462 249103619Sgrehan#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 250103619Sgrehan#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 251103619Sgrehan 252103619Sgrehan/* Misc constants.. */ 253103619Sgrehan#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 254103619Sgrehan#define HDA_AMP_MUTE_NONE (0) 255103619Sgrehan#define HDA_AMP_MUTE_LEFT (1 << 0) 256103619Sgrehan#define HDA_AMP_MUTE_RIGHT (1 << 1) 257103619Sgrehan#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 258103619Sgrehan 259103619Sgrehan#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 260103619Sgrehan#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 261103619Sgrehan 262133862Smarius#define HDA_DAC_PATH (1 << 0) 263103619Sgrehan#define HDA_ADC_PATH (1 << 1) 264103619Sgrehan#define HDA_ADC_RECSEL (1 << 2) 265103619Sgrehan 266103619Sgrehan#define HDA_CTL_OUT (1 << 0) 267103619Sgrehan#define HDA_CTL_IN (1 << 1) 268103619Sgrehan#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT) 269103619Sgrehan 270103619Sgrehan#define HDA_GPIO_MAX 15 271103619Sgrehan/* 0 - 14 = GPIO */ 272108991Sbenno#define HDA_QUIRK_GPIO0 (1 << 0) 273103619Sgrehan#define HDA_QUIRK_GPIO1 (1 << 1) 274103619Sgrehan#define HDA_QUIRK_GPIO2 (1 << 2) 275179746Skevlo#define HDA_QUIRK_GPIOFLUSH (1 << 15) 276103619Sgrehan#define HDA_QUIRK_SOFTPCMVOL (1 << 16) 277103619Sgrehan#define HDA_QUIRK_FIXEDRATE (1 << 17) 278183882Snwhitehorn#define HDA_QUIRK_FORCESTEREO (1 << 18) 279103619Sgrehan#define HDA_QUIRK_EAPDINV (1 << 19) 280103619Sgrehan#define HDA_QUIRK_VREF (1 << 20) 281103619Sgrehan 282103619Sgrehanstatic const struct { 283103619Sgrehan char *key; 284103619Sgrehan uint32_t value; 285103619Sgrehan} hdac_quirks_tab[] = { 286103619Sgrehan { "gpio0", HDA_QUIRK_GPIO0 }, 287103619Sgrehan { "gpio1", HDA_QUIRK_GPIO1 }, 288103619Sgrehan { "gpio2", HDA_QUIRK_GPIO2 }, 289103619Sgrehan { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 290103619Sgrehan { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 291103619Sgrehan { "fixedrate", HDA_QUIRK_FIXEDRATE }, 292110080Sbenno { "forcestereo", HDA_QUIRK_FORCESTEREO }, 293179746Skevlo { "eapdinv", HDA_QUIRK_EAPDINV }, 294179746Skevlo { "vref", HDA_QUIRK_VREF }, 295179746Skevlo}; 296179746Skevlo#define HDAC_QUIRKS_TAB_LEN \ 297179746Skevlo (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 298179746Skevlo 299179746Skevlo#define HDA_BDL_MIN 2 300103619Sgrehan#define HDA_BDL_MAX 256 301179746Skevlo#define HDA_BDL_DEFAULT HDA_BDL_MIN 302179746Skevlo 303103619Sgrehan#define HDA_BUFSZ_MIN 4096 304103619Sgrehan#define HDA_BUFSZ_MAX 65536 305103619Sgrehan#define HDA_BUFSZ_DEFAULT 16384 306103619Sgrehan 307103619Sgrehan#define HDA_PARSE_MAXDEPTH 10 308103619Sgrehan 309153050Smarius#define HDAC_UNSOLTAG_EVENT_HP 0x00 310153050Smarius 311153050SmariusMALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 312153050Smarius 313153050Smariusenum { 314153050Smarius HDA_PARSE_MIXER, 315153050Smarius HDA_PARSE_DIRECT 316108991Sbenno}; 317153050Smarius 318153050Smarius/* Default */ 319103619Sgrehanstatic uint32_t hdac_fmt[] = { 320103619Sgrehan AFMT_STEREO | AFMT_S16_LE, 321153050Smarius 0 322153050Smarius}; 323153050Smarius 324186805Snwhitehornstatic struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 325186805Snwhitehorn 326186805Snwhitehornstatic const struct { 327186805Snwhitehorn uint32_t model; 328153050Smarius char *desc; 329153050Smarius} hdac_devices[] = { 330153050Smarius { HDA_INTEL_82801F, "Intel 82801F" }, 331153050Smarius { HDA_INTEL_82801G, "Intel 82801G" }, 332103619Sgrehan { HDA_INTEL_82801H, "Intel 82801H" }, 333153050Smarius { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 334153050Smarius { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 335153050Smarius { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 336153050Smarius { HDA_NVIDIA_MCP61A, "NVidia MCP61A" }, 337153050Smarius { HDA_NVIDIA_MCP61B, "NVidia MCP61B" }, 338153050Smarius { HDA_NVIDIA_MCP65A, "NVidia MCP65A" }, 339153050Smarius { HDA_NVIDIA_MCP65B, "NVidia MCP65B" }, 340103619Sgrehan { HDA_ATI_SB450, "ATI SB450" }, 341153050Smarius { HDA_ATI_SB600, "ATI SB600" }, 342103619Sgrehan { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 343103619Sgrehan { HDA_SIS_966, "SiS 966" }, 344103619Sgrehan /* Unknown */ 345103619Sgrehan { HDA_INTEL_ALL, "Intel (Unknown)" }, 346103619Sgrehan { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 347103619Sgrehan { HDA_ATI_ALL, "ATI (Unknown)" }, 348103619Sgrehan { HDA_VIA_ALL, "VIA (Unknown)" }, 349103619Sgrehan { HDA_SIS_ALL, "SiS (Unknown)" }, 350103619Sgrehan}; 351103619Sgrehan#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 352103619Sgrehan 353103619Sgrehanstatic const struct { 354103619Sgrehan uint32_t rate; 355103619Sgrehan int valid; 356103619Sgrehan uint16_t base; 357103619Sgrehan uint16_t mul; 358103619Sgrehan uint16_t div; 359103619Sgrehan} hda_rate_tab[] = { 360103619Sgrehan { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 361103619Sgrehan { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 362103619Sgrehan { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 363103619Sgrehan { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 364103619Sgrehan { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 365103619Sgrehan { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 366103619Sgrehan { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 367103619Sgrehan { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 368103619Sgrehan { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 369103619Sgrehan { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 370103619Sgrehan { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 371103619Sgrehan { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 372110080Sbenno { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 373110080Sbenno { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 374133589Smarius { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 375103619Sgrehan { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 376103619Sgrehan { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 377110080Sbenno { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 378110080Sbenno { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 379103619Sgrehan { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 380133589Smarius { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 381133589Smarius { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 382133589Smarius { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 383110080Sbenno { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 384110080Sbenno { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 385110080Sbenno { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 386103619Sgrehan { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 387103619Sgrehan { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 388103619Sgrehan { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 389103619Sgrehan { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 390103619Sgrehan { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 391103619Sgrehan { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 392103619Sgrehan { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 393103619Sgrehan { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 394110080Sbenno { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 395110080Sbenno}; 396110080Sbenno#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 397110080Sbenno 398110080Sbenno/* All codecs you can eat... */ 399110080Sbenno#define HDA_CODEC_CONSTRUCT(vendor, id) \ 400110080Sbenno (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 401103619Sgrehan 402103619Sgrehan/* Realtek */ 403108994Sbenno#define REALTEK_VENDORID 0x10ec 404103619Sgrehan#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 405103619Sgrehan#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 406103619Sgrehan#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 407103619Sgrehan#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 408103619Sgrehan#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 409103619Sgrehan#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 410103619Sgrehan#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 411110080Sbenno 412110080Sbenno/* Analog Device */ 413110080Sbenno#define ANALOGDEVICE_VENDORID 0x11d4 414110080Sbenno#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1981) 415110080Sbenno#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1983) 416110080Sbenno#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0x1986) 417110080Sbenno#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICE, 0xffff) 418110080Sbenno 419110080Sbenno/* CMedia */ 420110080Sbenno#define CMEDIA_VENDORID 0x434d 421110080Sbenno#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 422110080Sbenno#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 423110080Sbenno 424110080Sbenno/* Sigmatel */ 425110080Sbenno#define SIGMATEL_VENDORID 0x8384 426110080Sbenno#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 427110080Sbenno#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 428110080Sbenno#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 429110080Sbenno#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 430110080Sbenno#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 431110080Sbenno#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 432110080Sbenno#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 433110080Sbenno 434110080Sbenno/* 435103619Sgrehan * Conexant 436103619Sgrehan * 437110080Sbenno * Ok, the truth is, I don't have any idea at all whether 438103619Sgrehan * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only 439184299Snwhitehorn * place that tell me it is "Venice" is from its Windows driver INF. 440184299Snwhitehorn * 441184299Snwhitehorn * Venice - CX????? 442184299Snwhitehorn * Waikiki - CX20551-22 443184299Snwhitehorn */ 444110436Sbenno#define CONEXANT_VENDORID 0x14f1 445110436Sbenno#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 446110436Sbenno#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 447178599Smarcel#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 448110436Sbenno 449178599Smarcel 450110436Sbenno/* Codecs */ 451110436Sbennostatic const struct { 452110436Sbenno uint32_t id; 453110436Sbenno char *name; 454110436Sbenno} hdac_codecs[] = { 455110436Sbenno { HDA_CODEC_ALC260, "Realtek ALC260" }, 456110436Sbenno { HDA_CODEC_ALC861, "Realtek ALC861" }, 457110436Sbenno { HDA_CODEC_ALC880, "Realtek ALC880" }, 458110436Sbenno { HDA_CODEC_ALC882, "Realtek ALC882" }, 459110436Sbenno { HDA_CODEC_ALC883, "Realtek ALC883" }, 460108994Sbenno { HDA_CODEC_ALC888, "Realtek ALC888" }, 461108994Sbenno { HDA_CODEC_AD1981HD, "Analog Device AD1981HD" }, 462110080Sbenno { HDA_CODEC_AD1983, "Analog Device AD1983" }, 463103619Sgrehan { HDA_CODEC_AD1986A, "Analog Device AD1986A" }, 464103619Sgrehan { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 465103619Sgrehan { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 466103619Sgrehan { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 467103619Sgrehan { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 468103619Sgrehan { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 469110080Sbenno { HDA_CODEC_STAC9227, "Sigmatel STAC9227" }, 470110080Sbenno { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 471103619Sgrehan { HDA_CODEC_CXVENICE, "Conexant Venice" }, 472110080Sbenno { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" }, 473110080Sbenno /* Unknown codec */ 474110080Sbenno { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 475103619Sgrehan { HDA_CODEC_ADXXXX, "Analog Device (Unknown)" }, 476103619Sgrehan { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 477103619Sgrehan { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 478157895Simp { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 479103619Sgrehan}; 480103619Sgrehan#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 481103619Sgrehan 482103619Sgrehanenum { 483103619Sgrehan HDAC_HP_SWITCH_CTL, 484103619Sgrehan HDAC_HP_SWITCH_CTRL 485103619Sgrehan}; 486103619Sgrehan 487103619Sgrehanstatic const struct { 488103619Sgrehan uint32_t model; 489103619Sgrehan uint32_t id; 490110080Sbenno int type; 491103619Sgrehan int inverted; 492103619Sgrehan nid_t hpnid; 493103619Sgrehan nid_t spkrnid[8]; 494103619Sgrehan nid_t eapdnid; 495103619Sgrehan} hdac_hp_switch[] = { 496103619Sgrehan /* Specific OEM models */ 497103619Sgrehan { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 498103619Sgrehan 17, { 16, -1 }, 16 }, 499103619Sgrehan { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 500103619Sgrehan 6, { 5, -1 }, 5 }, 501103619Sgrehan { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 502103619Sgrehan 6, { 5, -1 }, 5 }, 503103619Sgrehan { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 504103619Sgrehan 6, { 5, -1 }, 5 }, 505103619Sgrehan { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 506103619Sgrehan 6, { 5, -1 }, -1 }, 507103619Sgrehan { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 508103619Sgrehan 13, { 14, -1 }, -1 }, 509103619Sgrehan { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 510103619Sgrehan 13, { 14, -1 }, -1 }, 511103619Sgrehan { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL, 0, 512103619Sgrehan 10, { 13, -1 }, -1 }, 513103619Sgrehan { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 514103619Sgrehan 26, { 27, -1 }, -1 }, 515103619Sgrehan { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL, 0, 516103619Sgrehan 27, { 20, -1 }, -1 }, 517103619Sgrehan { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 518103619Sgrehan 20, { 21, -1 }, -1 }, 519103619Sgrehan { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 520103619Sgrehan 20, { 27, -1 }, -1 }, 521103619Sgrehan /* 522103619Sgrehan * All models that at least come from the same vendor with 523103619Sgrehan * simmilar codec. 524103619Sgrehan */ 525103619Sgrehan { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL, 0, 526174822Smarcel 17, { 16, -1 }, 16 }, 527103619Sgrehan { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 528103619Sgrehan 6, { 5, -1 }, 5 }, 529103619Sgrehan { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL, 0, 530103619Sgrehan 6, { 5, -1 }, -1 }, 531103619Sgrehan { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL, 0, 532103619Sgrehan 13, { 14, -1 }, -1 }, 533103619Sgrehan { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL, 1, 534103619Sgrehan 26, { 27, -1 }, -1 }, 535103619Sgrehan#if 0 536103619Sgrehan { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL, 0, 537103619Sgrehan 20, { 21, -1 }, -1 }, 538103619Sgrehan#endif 539103619Sgrehan}; 540103619Sgrehan#define HDAC_HP_SWITCH_LEN \ 541103619Sgrehan (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0])) 542103619Sgrehan 543103619Sgrehanstatic const struct { 544103619Sgrehan uint32_t model; 545103619Sgrehan uint32_t id; 546103619Sgrehan nid_t eapdnid; 547103619Sgrehan int hp_switch; 548103619Sgrehan} hdac_eapd_switch[] = { 549103619Sgrehan { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 }, 550103619Sgrehan { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 551103619Sgrehan { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 }, 552103619Sgrehan}; 553103619Sgrehan#define HDAC_EAPD_SWITCH_LEN \ 554103619Sgrehan (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0])) 555133589Smarius 556133589Smarius/**************************************************************************** 557153050Smarius * Function prototypes 558153050Smarius ****************************************************************************/ 559133589Smariusstatic void hdac_intr_handler(void *); 560133589Smariusstatic int hdac_reset(struct hdac_softc *); 561153050Smariusstatic int hdac_get_capabilities(struct hdac_softc *); 562153050Smariusstatic void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 563133589Smariusstatic int hdac_dma_alloc(struct hdac_softc *, 564133589Smarius struct hdac_dma *, bus_size_t); 565133589Smariusstatic void hdac_dma_free(struct hdac_dma *); 566153050Smariusstatic int hdac_mem_alloc(struct hdac_softc *); 567153050Smariusstatic void hdac_mem_free(struct hdac_softc *); 568133589Smariusstatic int hdac_irq_alloc(struct hdac_softc *); 569static void hdac_irq_free(struct hdac_softc *); 570static void hdac_corb_init(struct hdac_softc *); 571static void hdac_rirb_init(struct hdac_softc *); 572static void hdac_corb_start(struct hdac_softc *); 573static void hdac_rirb_start(struct hdac_softc *); 574static void hdac_scan_codecs(struct hdac_softc *); 575static int hdac_probe_codec(struct hdac_codec *); 576static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t); 577static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *); 578 579static void hdac_attach2(void *); 580 581static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 582 uint32_t, int); 583static void hdac_command_send_internal(struct hdac_softc *, 584 struct hdac_command_list *, int); 585 586static int hdac_probe(device_t); 587static int hdac_attach(device_t); 588static int hdac_detach(device_t); 589static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 590static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 591 uint32_t, int, int); 592static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 593 nid_t, int, int); 594static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 595 nid_t, nid_t, int, int, int, int, int, int); 596static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *); 597static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 598 599static int hdac_rirb_flush(struct hdac_softc *sc); 600static int hdac_unsolq_flush(struct hdac_softc *sc); 601 602#define hdac_command(a1, a2, a3) \ 603 hdac_command_sendone_internal(a1, a2, a3) 604 605#define hdac_codec_id(d) \ 606 ((uint32_t)((d == NULL) ? 0x00000000 : \ 607 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \ 608 ((uint32_t)(d)->device_id & 0x0000ffff)))) 609 610static char * 611hdac_codec_name(struct hdac_devinfo *devinfo) 612{ 613 uint32_t id; 614 int i; 615 616 id = hdac_codec_id(devinfo); 617 618 for (i = 0; i < HDAC_CODECS_LEN; i++) { 619 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 620 return (hdac_codecs[i].name); 621 } 622 623 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 624} 625 626static char * 627hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask) 628{ 629 static char *ossname[] = SOUND_DEVICE_NAMES; 630 static char *unknown = "???"; 631 int i; 632 633 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) { 634 if (devmask & (1 << i)) 635 return (ossname[i]); 636 } 637 return (unknown); 638} 639 640static void 641hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 642{ 643 static char *ossname[] = SOUND_DEVICE_NAMES; 644 int i, first = 1; 645 646 bzero(buf, len); 647 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 648 if (mask & (1 << i)) { 649 if (first == 0) 650 strlcat(buf, ", ", len); 651 strlcat(buf, ossname[i], len); 652 first = 0; 653 } 654 } 655} 656 657static struct hdac_audio_ctl * 658hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 659{ 660 if (devinfo == NULL || 661 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 662 index == NULL || devinfo->function.audio.ctl == NULL || 663 devinfo->function.audio.ctlcnt < 1 || 664 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 665 return (NULL); 666 return (&devinfo->function.audio.ctl[(*index)++]); 667} 668 669static struct hdac_audio_ctl * 670hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, 671 int index, int cnt) 672{ 673 struct hdac_audio_ctl *ctl, *retctl = NULL; 674 int i, at, atindex, found = 0; 675 676 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 677 return (NULL); 678 679 at = cnt; 680 if (at == 0) 681 at = 1; 682 else if (at < 0) 683 at = -1; 684 atindex = index; 685 if (atindex < 0) 686 atindex = -1; 687 688 i = 0; 689 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 690 if (ctl->enable == 0 || ctl->widget == NULL) 691 continue; 692 if (!(ctl->widget->nid == nid && (atindex == -1 || 693 ctl->index == atindex))) 694 continue; 695 found++; 696 if (found == cnt) 697 return (ctl); 698 retctl = ctl; 699 } 700 701 return ((at == -1) ? retctl : NULL); 702} 703 704static void 705hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 706{ 707 struct hdac_softc *sc; 708 struct hdac_widget *w; 709 struct hdac_audio_ctl *ctl; 710 uint32_t id, res; 711 int i = 0, j, forcemute; 712 nid_t cad; 713 714 if (devinfo == NULL || devinfo->codec == NULL || 715 devinfo->codec->sc == NULL) 716 return; 717 718 sc = devinfo->codec->sc; 719 cad = devinfo->codec->cad; 720 id = hdac_codec_id(devinfo); 721 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 722 if (HDA_DEV_MATCH(hdac_hp_switch[i].model, 723 sc->pci_subvendor) && 724 hdac_hp_switch[i].id == id) 725 break; 726 } 727 728 if (i >= HDAC_HP_SWITCH_LEN) 729 return; 730 731 forcemute = 0; 732 if (hdac_hp_switch[i].eapdnid != -1) { 733 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid); 734 if (w != NULL && w->param.eapdbtl != HDAC_INVALID) 735 forcemute = (w->param.eapdbtl & 736 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1; 737 } 738 739 res = hdac_command(sc, 740 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad); 741 HDA_BOOTVERBOSE( 742 device_printf(sc->dev, 743 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n", 744 hdac_hp_switch[i].hpnid, res); 745 ); 746 res >>= 31; 747 res ^= hdac_hp_switch[i].inverted; 748 749 switch (hdac_hp_switch[i].type) { 750 case HDAC_HP_SWITCH_CTL: 751 ctl = hdac_audio_ctl_amp_get(devinfo, 752 hdac_hp_switch[i].hpnid, 0, 1); 753 if (ctl != NULL) { 754 ctl->muted = (res != 0 && forcemute == 0) ? 755 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL; 756 hdac_audio_ctl_amp_set(ctl, 757 HDA_AMP_MUTE_DEFAULT, ctl->left, 758 ctl->right); 759 } 760 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 761 ctl = hdac_audio_ctl_amp_get(devinfo, 762 hdac_hp_switch[i].spkrnid[j], 0, 1); 763 if (ctl != NULL) { 764 ctl->muted = (res != 0 || forcemute == 1) ? 765 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE; 766 hdac_audio_ctl_amp_set(ctl, 767 HDA_AMP_MUTE_DEFAULT, ctl->left, 768 ctl->right); 769 } 770 } 771 break; 772 case HDAC_HP_SWITCH_CTRL: 773 if (res != 0) { 774 /* HP in */ 775 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 776 if (w != NULL && w->type == 777 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 778 if (forcemute == 0) 779 w->wclass.pin.ctrl |= 780 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 781 else 782 w->wclass.pin.ctrl &= 783 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 784 hdac_command(sc, 785 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 786 w->wclass.pin.ctrl), cad); 787 } 788 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 789 w = hdac_widget_get(devinfo, 790 hdac_hp_switch[i].spkrnid[j]); 791 if (w != NULL && w->type == 792 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 793 w->wclass.pin.ctrl &= 794 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 795 hdac_command(sc, 796 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 797 w->nid, 798 w->wclass.pin.ctrl), cad); 799 } 800 } 801 } else { 802 /* HP out */ 803 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 804 if (w != NULL && w->type == 805 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 806 w->wclass.pin.ctrl &= 807 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 808 hdac_command(sc, 809 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 810 w->wclass.pin.ctrl), cad); 811 } 812 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) { 813 w = hdac_widget_get(devinfo, 814 hdac_hp_switch[i].spkrnid[j]); 815 if (w != NULL && w->type == 816 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 817 if (forcemute == 0) 818 w->wclass.pin.ctrl |= 819 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 820 else 821 w->wclass.pin.ctrl &= 822 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 823 hdac_command(sc, 824 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 825 w->nid, 826 w->wclass.pin.ctrl), cad); 827 } 828 } 829 } 830 break; 831 default: 832 break; 833 } 834} 835 836static void 837hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 838{ 839 struct hdac_softc *sc; 840 struct hdac_devinfo *devinfo = NULL; 841 device_t *devlist = NULL; 842 int devcount, i; 843 844 if (codec == NULL || codec->sc == NULL) 845 return; 846 847 sc = codec->sc; 848 849 HDA_BOOTVERBOSE( 850 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag); 851 ); 852 853 device_get_children(sc->dev, &devlist, &devcount); 854 for (i = 0; devlist != NULL && i < devcount; i++) { 855 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 856 if (devinfo != NULL && devinfo->node_type == 857 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 858 devinfo->codec != NULL && 859 devinfo->codec->cad == codec->cad) { 860 break; 861 } else 862 devinfo = NULL; 863 } 864 if (devlist != NULL) 865 free(devlist, M_TEMP); 866 867 if (devinfo == NULL) 868 return; 869 870 switch (tag) { 871 case HDAC_UNSOLTAG_EVENT_HP: 872 hdac_hp_switch_handler(devinfo); 873 break; 874 default: 875 break; 876 } 877} 878 879static int 880hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 881{ 882 /* XXX to be removed */ 883#ifdef HDAC_INTR_EXTRA 884 uint32_t res; 885#endif 886 887 if (ch->blkcnt == 0) 888 return (0); 889 890 /* XXX to be removed */ 891#ifdef HDAC_INTR_EXTRA 892 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 893#endif 894 895 /* XXX to be removed */ 896#ifdef HDAC_INTR_EXTRA 897 HDA_BOOTVERBOSE( 898 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 899 device_printf(sc->dev, 900 "PCMDIR_%s intr triggered beyond stream boundary:" 901 "%08x\n", 902 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 903 ); 904#endif 905 906 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 907 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 908 909 /* XXX to be removed */ 910#ifdef HDAC_INTR_EXTRA 911 if (res & HDAC_SDSTS_BCIS) { 912#endif 913 return (1); 914 /* XXX to be removed */ 915#ifdef HDAC_INTR_EXTRA 916 } 917#endif 918 919 return (0); 920} 921 922/**************************************************************************** 923 * void hdac_intr_handler(void *) 924 * 925 * Interrupt handler. Processes interrupts received from the hdac. 926 ****************************************************************************/ 927static void 928hdac_intr_handler(void *context) 929{ 930 struct hdac_softc *sc; 931 uint32_t intsts; 932 uint8_t rirbsts; 933 struct hdac_rirb *rirb_base; 934 uint32_t trigger = 0; 935 936 sc = (struct hdac_softc *)context; 937 938 hdac_lock(sc); 939 if (sc->polling != 0) { 940 hdac_unlock(sc); 941 return; 942 } 943 /* Do we have anything to do? */ 944 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 945 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 946 hdac_unlock(sc); 947 return; 948 } 949 950 /* Was this a controller interrupt? */ 951 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 952 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 953 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 954 /* Get as many responses that we can */ 955 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 956 HDAC_WRITE_1(&sc->mem, 957 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 958 hdac_rirb_flush(sc); 959 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 960 } 961 /* XXX to be removed */ 962 /* Clear interrupt and exit */ 963#ifdef HDAC_INTR_EXTRA 964 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 965#endif 966 } 967 968 hdac_unsolq_flush(sc); 969 970 if (intsts & HDAC_INTSTS_SIS_MASK) { 971 if ((intsts & (1 << sc->num_iss)) && 972 hdac_stream_intr(sc, &sc->play) != 0) 973 trigger |= 1; 974 if ((intsts & (1 << 0)) && 975 hdac_stream_intr(sc, &sc->rec) != 0) 976 trigger |= 2; 977 /* XXX to be removed */ 978#ifdef HDAC_INTR_EXTRA 979 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 980 HDAC_INTSTS_SIS_MASK); 981#endif 982 } 983 984 hdac_unlock(sc); 985 986 if (trigger & 1) 987 chn_intr(sc->play.c); 988 if (trigger & 2) 989 chn_intr(sc->rec.c); 990} 991 992/**************************************************************************** 993 * int hdac_reset(hdac_softc *) 994 * 995 * Reset the hdac to a quiescent and known state. 996 ****************************************************************************/ 997static int 998hdac_reset(struct hdac_softc *sc) 999{ 1000 uint32_t gctl; 1001 int count, i; 1002 1003 /* 1004 * Stop all Streams DMA engine 1005 */ 1006 for (i = 0; i < sc->num_iss; i++) 1007 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1008 for (i = 0; i < sc->num_oss; i++) 1009 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1010 for (i = 0; i < sc->num_bss; i++) 1011 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1012 1013 /* 1014 * Stop Control DMA engines 1015 */ 1016 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1017 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1018 1019 /* 1020 * Reset the controller. The reset must remain asserted for 1021 * a minimum of 100us. 1022 */ 1023 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1024 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1025 count = 10000; 1026 do { 1027 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1028 if (!(gctl & HDAC_GCTL_CRST)) 1029 break; 1030 DELAY(10); 1031 } while (--count); 1032 if (gctl & HDAC_GCTL_CRST) { 1033 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1034 return (ENXIO); 1035 } 1036 DELAY(100); 1037 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1038 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1039 count = 10000; 1040 do { 1041 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1042 if (gctl & HDAC_GCTL_CRST) 1043 break; 1044 DELAY(10); 1045 } while (--count); 1046 if (!(gctl & HDAC_GCTL_CRST)) { 1047 device_printf(sc->dev, "Device stuck in reset\n"); 1048 return (ENXIO); 1049 } 1050 1051 /* 1052 * Wait for codecs to finish their own reset sequence. The delay here 1053 * should be of 250us but for some reasons, on it's not enough on my 1054 * computer. Let's use twice as much as necessary to make sure that 1055 * it's reset properly. 1056 */ 1057 DELAY(1000); 1058 1059 return (0); 1060} 1061 1062 1063/**************************************************************************** 1064 * int hdac_get_capabilities(struct hdac_softc *); 1065 * 1066 * Retreive the general capabilities of the hdac; 1067 * Number of Input Streams 1068 * Number of Output Streams 1069 * Number of bidirectional Streams 1070 * 64bit ready 1071 * CORB and RIRB sizes 1072 ****************************************************************************/ 1073static int 1074hdac_get_capabilities(struct hdac_softc *sc) 1075{ 1076 uint16_t gcap; 1077 uint8_t corbsize, rirbsize; 1078 1079 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1080 sc->num_iss = HDAC_GCAP_ISS(gcap); 1081 sc->num_oss = HDAC_GCAP_OSS(gcap); 1082 sc->num_bss = HDAC_GCAP_BSS(gcap); 1083 1084 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1085 1086 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1087 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1088 HDAC_CORBSIZE_CORBSZCAP_256) 1089 sc->corb_size = 256; 1090 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1091 HDAC_CORBSIZE_CORBSZCAP_16) 1092 sc->corb_size = 16; 1093 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1094 HDAC_CORBSIZE_CORBSZCAP_2) 1095 sc->corb_size = 2; 1096 else { 1097 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1098 __func__, corbsize); 1099 return (ENXIO); 1100 } 1101 1102 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1103 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1104 HDAC_RIRBSIZE_RIRBSZCAP_256) 1105 sc->rirb_size = 256; 1106 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1107 HDAC_RIRBSIZE_RIRBSZCAP_16) 1108 sc->rirb_size = 16; 1109 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1110 HDAC_RIRBSIZE_RIRBSZCAP_2) 1111 sc->rirb_size = 2; 1112 else { 1113 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1114 __func__, rirbsize); 1115 return (ENXIO); 1116 } 1117 1118 return (0); 1119} 1120 1121 1122/**************************************************************************** 1123 * void hdac_dma_cb 1124 * 1125 * This function is called by bus_dmamap_load when the mapping has been 1126 * established. We just record the physical address of the mapping into 1127 * the struct hdac_dma passed in. 1128 ****************************************************************************/ 1129static void 1130hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1131{ 1132 struct hdac_dma *dma; 1133 1134 if (error == 0) { 1135 dma = (struct hdac_dma *)callback_arg; 1136 dma->dma_paddr = segs[0].ds_addr; 1137 } 1138} 1139 1140static void 1141hdac_dma_nocache(void *ptr) 1142{ 1143#if 0 1144#if defined(__i386__) || defined(__amd64__) 1145 pt_entry_t *pte; 1146 vm_offset_t va; 1147 1148 va = (vm_offset_t)ptr; 1149 pte = vtopte(va); 1150 if (pte) { 1151 *pte |= PG_N; 1152 invltlb(); 1153 } 1154#endif 1155#endif 1156} 1157 1158/**************************************************************************** 1159 * int hdac_dma_alloc 1160 * 1161 * This function allocate and setup a dma region (struct hdac_dma). 1162 * It must be freed by a corresponding hdac_dma_free. 1163 ****************************************************************************/ 1164static int 1165hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1166{ 1167 int result; 1168 int lowaddr; 1169 1170 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1171 BUS_SPACE_MAXADDR_32BIT; 1172 bzero(dma, sizeof(*dma)); 1173 1174 /* 1175 * Create a DMA tag 1176 */ 1177 result = bus_dma_tag_create(NULL, /* parent */ 1178 HDAC_DMA_ALIGNMENT, /* alignment */ 1179 0, /* boundary */ 1180 lowaddr, /* lowaddr */ 1181 BUS_SPACE_MAXADDR, /* highaddr */ 1182 NULL, /* filtfunc */ 1183 NULL, /* fistfuncarg */ 1184 size, /* maxsize */ 1185 1, /* nsegments */ 1186 size, /* maxsegsz */ 1187 0, /* flags */ 1188 NULL, /* lockfunc */ 1189 NULL, /* lockfuncarg */ 1190 &dma->dma_tag); /* dmat */ 1191 if (result != 0) { 1192 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1193 __func__, result); 1194 goto fail; 1195 } 1196 1197 /* 1198 * Allocate DMA memory 1199 */ 1200 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1201 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 1202 if (result != 0) { 1203 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1204 __func__, result); 1205 goto fail; 1206 } 1207 1208 /* 1209 * Map the memory 1210 */ 1211 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1212 (void *)dma->dma_vaddr, size, hdac_dma_cb, (void *)dma, 1213 BUS_DMA_NOWAIT); 1214 if (result != 0 || dma->dma_paddr == 0) { 1215 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1216 __func__, result); 1217 goto fail; 1218 } 1219 bzero((void *)dma->dma_vaddr, size); 1220 hdac_dma_nocache(dma->dma_vaddr); 1221 1222 return (0); 1223fail: 1224 if (dma->dma_map != NULL) 1225 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1226 if (dma->dma_tag != NULL) 1227 bus_dma_tag_destroy(dma->dma_tag); 1228 return (result); 1229} 1230 1231 1232/**************************************************************************** 1233 * void hdac_dma_free(struct hdac_dma *) 1234 * 1235 * Free a struct dhac_dma that has been previously allocated via the 1236 * hdac_dma_alloc function. 1237 ****************************************************************************/ 1238static void 1239hdac_dma_free(struct hdac_dma *dma) 1240{ 1241 if (dma->dma_tag != NULL) { 1242 /* Flush caches */ 1243 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1244 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1245 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1246 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1247 bus_dma_tag_destroy(dma->dma_tag); 1248 } 1249} 1250 1251/**************************************************************************** 1252 * int hdac_mem_alloc(struct hdac_softc *) 1253 * 1254 * Allocate all the bus resources necessary to speak with the physical 1255 * controller. 1256 ****************************************************************************/ 1257static int 1258hdac_mem_alloc(struct hdac_softc *sc) 1259{ 1260 struct hdac_mem *mem; 1261 1262 mem = &sc->mem; 1263 mem->mem_rid = PCIR_BAR(0); 1264 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1265 &mem->mem_rid, RF_ACTIVE); 1266 if (mem->mem_res == NULL) { 1267 device_printf(sc->dev, 1268 "%s: Unable to allocate memory resource\n", __func__); 1269 return (ENOMEM); 1270 } 1271 mem->mem_tag = rman_get_bustag(mem->mem_res); 1272 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1273 1274 return (0); 1275} 1276 1277/**************************************************************************** 1278 * void hdac_mem_free(struct hdac_softc *) 1279 * 1280 * Free up resources previously allocated by hdac_mem_alloc. 1281 ****************************************************************************/ 1282static void 1283hdac_mem_free(struct hdac_softc *sc) 1284{ 1285 struct hdac_mem *mem; 1286 1287 mem = &sc->mem; 1288 if (mem->mem_res != NULL) 1289 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1290 mem->mem_res); 1291 mem->mem_res = NULL; 1292} 1293 1294/**************************************************************************** 1295 * int hdac_irq_alloc(struct hdac_softc *) 1296 * 1297 * Allocate and setup the resources necessary for interrupt handling. 1298 ****************************************************************************/ 1299static int 1300hdac_irq_alloc(struct hdac_softc *sc) 1301{ 1302 struct hdac_irq *irq; 1303 int result; 1304 1305 irq = &sc->irq; 1306 irq->irq_rid = 0x0; 1307 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1308 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1309 if (irq->irq_res == NULL) { 1310 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1311 __func__); 1312 goto fail; 1313 } 1314 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE, 1315 hdac_intr_handler, sc, &irq->irq_handle); 1316 if (result != 0) { 1317 device_printf(sc->dev, 1318 "%s: Unable to setup interrupt handler (%x)\n", 1319 __func__, result); 1320 goto fail; 1321 } 1322 1323 return (0); 1324 1325fail: 1326 hdac_irq_free(sc); 1327 1328 return (ENXIO); 1329} 1330 1331/**************************************************************************** 1332 * void hdac_irq_free(struct hdac_softc *) 1333 * 1334 * Free up resources previously allocated by hdac_irq_alloc. 1335 ****************************************************************************/ 1336static void 1337hdac_irq_free(struct hdac_softc *sc) 1338{ 1339 struct hdac_irq *irq; 1340 1341 irq = &sc->irq; 1342 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1343 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1344 if (irq->irq_res != NULL) 1345 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1346 irq->irq_res); 1347 irq->irq_handle = NULL; 1348 irq->irq_res = NULL; 1349} 1350 1351/**************************************************************************** 1352 * void hdac_corb_init(struct hdac_softc *) 1353 * 1354 * Initialize the corb registers for operations but do not start it up yet. 1355 * The CORB engine must not be running when this function is called. 1356 ****************************************************************************/ 1357static void 1358hdac_corb_init(struct hdac_softc *sc) 1359{ 1360 uint8_t corbsize; 1361 uint64_t corbpaddr; 1362 1363 /* Setup the CORB size. */ 1364 switch (sc->corb_size) { 1365 case 256: 1366 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1367 break; 1368 case 16: 1369 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1370 break; 1371 case 2: 1372 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1373 break; 1374 default: 1375 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1376 } 1377 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1378 1379 /* Setup the CORB Address in the hdac */ 1380 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1381 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1382 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1383 1384 /* Set the WP and RP */ 1385 sc->corb_wp = 0; 1386 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1387 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1388 /* 1389 * The HDA specification indicates that the CORBRPRST bit will always 1390 * read as zero. Unfortunately, it seems that at least the 82801G 1391 * doesn't reset the bit to zero, which stalls the corb engine. 1392 * manually reset the bit to zero before continuing. 1393 */ 1394 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1395 1396 /* Enable CORB error reporting */ 1397#if 0 1398 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1399#endif 1400} 1401 1402/**************************************************************************** 1403 * void hdac_rirb_init(struct hdac_softc *) 1404 * 1405 * Initialize the rirb registers for operations but do not start it up yet. 1406 * The RIRB engine must not be running when this function is called. 1407 ****************************************************************************/ 1408static void 1409hdac_rirb_init(struct hdac_softc *sc) 1410{ 1411 uint8_t rirbsize; 1412 uint64_t rirbpaddr; 1413 1414 /* Setup the RIRB size. */ 1415 switch (sc->rirb_size) { 1416 case 256: 1417 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1418 break; 1419 case 16: 1420 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1421 break; 1422 case 2: 1423 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1424 break; 1425 default: 1426 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1427 } 1428 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1429 1430 /* Setup the RIRB Address in the hdac */ 1431 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1432 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1433 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1434 1435 /* Setup the WP and RP */ 1436 sc->rirb_rp = 0; 1437 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1438 1439 if (sc->polling == 0) { 1440 /* Setup the interrupt threshold */ 1441 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1442 1443 /* Enable Overrun and response received reporting */ 1444#if 0 1445 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1446 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1447#else 1448 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1449#endif 1450 } 1451 1452 /* 1453 * Make sure that the Host CPU cache doesn't contain any dirty 1454 * cache lines that falls in the rirb. If I understood correctly, it 1455 * should be sufficient to do this only once as the rirb is purely 1456 * read-only from now on. 1457 */ 1458 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1459 BUS_DMASYNC_PREREAD); 1460} 1461 1462/**************************************************************************** 1463 * void hdac_corb_start(hdac_softc *) 1464 * 1465 * Startup the corb DMA engine 1466 ****************************************************************************/ 1467static void 1468hdac_corb_start(struct hdac_softc *sc) 1469{ 1470 uint32_t corbctl; 1471 1472 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1473 corbctl |= HDAC_CORBCTL_CORBRUN; 1474 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1475} 1476 1477/**************************************************************************** 1478 * void hdac_rirb_start(hdac_softc *) 1479 * 1480 * Startup the rirb DMA engine 1481 ****************************************************************************/ 1482static void 1483hdac_rirb_start(struct hdac_softc *sc) 1484{ 1485 uint32_t rirbctl; 1486 1487 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1488 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1489 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1490} 1491 1492 1493/**************************************************************************** 1494 * void hdac_scan_codecs(struct hdac_softc *) 1495 * 1496 * Scan the bus for available codecs. 1497 ****************************************************************************/ 1498static void 1499hdac_scan_codecs(struct hdac_softc *sc) 1500{ 1501 struct hdac_codec *codec; 1502 int i; 1503 uint16_t statests; 1504 1505 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1506 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1507 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1508 /* We have found a codec. */ 1509 hdac_unlock(sc); 1510 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1511 M_HDAC, M_ZERO | M_NOWAIT); 1512 hdac_lock(sc); 1513 if (codec == NULL) { 1514 device_printf(sc->dev, 1515 "Unable to allocate memory for codec\n"); 1516 continue; 1517 } 1518 codec->commands = NULL; 1519 codec->responses_received = 0; 1520 codec->verbs_sent = 0; 1521 codec->sc = sc; 1522 codec->cad = i; 1523 sc->codecs[i] = codec; 1524 if (hdac_probe_codec(codec) != 0) 1525 break; 1526 } 1527 } 1528 /* All codecs have been probed, now try to attach drivers to them */ 1529 /* bus_generic_attach(sc->dev); */ 1530} 1531 1532/**************************************************************************** 1533 * void hdac_probe_codec(struct hdac_softc *, int) 1534 * 1535 * Probe a the given codec_id for available function groups. 1536 ****************************************************************************/ 1537static int 1538hdac_probe_codec(struct hdac_codec *codec) 1539{ 1540 struct hdac_softc *sc = codec->sc; 1541 struct hdac_devinfo *devinfo; 1542 uint32_t vendorid, revisionid, subnode; 1543 int startnode; 1544 int endnode; 1545 int i; 1546 nid_t cad = codec->cad; 1547 1548 HDA_BOOTVERBOSE( 1549 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad); 1550 ); 1551 vendorid = hdac_command(sc, 1552 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1553 cad); 1554 revisionid = hdac_command(sc, 1555 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 1556 cad); 1557 subnode = hdac_command(sc, 1558 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 1559 cad); 1560 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 1561 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 1562 1563 HDA_BOOTVERBOSE( 1564 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n", 1565 startnode, endnode); 1566 ); 1567 for (i = startnode; i < endnode; i++) { 1568 devinfo = hdac_probe_function(codec, i); 1569 if (devinfo != NULL) { 1570 /* XXX Ignore other FG. */ 1571 devinfo->vendor_id = 1572 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1573 devinfo->device_id = 1574 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1575 devinfo->revision_id = 1576 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1577 devinfo->stepping_id = 1578 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1579 HDA_BOOTVERBOSE( 1580 device_printf(sc->dev, 1581 "HDA_DEBUG: \tFound AFG nid=%d " 1582 "[startnode=%d endnode=%d]\n", 1583 devinfo->nid, startnode, endnode); 1584 ); 1585 return (1); 1586 } 1587 } 1588 1589 HDA_BOOTVERBOSE( 1590 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n"); 1591 ); 1592 return (0); 1593} 1594 1595static struct hdac_devinfo * 1596hdac_probe_function(struct hdac_codec *codec, nid_t nid) 1597{ 1598 struct hdac_softc *sc = codec->sc; 1599 struct hdac_devinfo *devinfo; 1600 uint32_t fctgrptype; 1601 nid_t cad = codec->cad; 1602 1603 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 1604 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 1605 1606 /* XXX For now, ignore other FG. */ 1607 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 1608 return (NULL); 1609 1610 hdac_unlock(sc); 1611 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC, 1612 M_NOWAIT | M_ZERO); 1613 hdac_lock(sc); 1614 if (devinfo == NULL) { 1615 device_printf(sc->dev, "%s: Unable to allocate ivar\n", 1616 __func__); 1617 return (NULL); 1618 } 1619 1620 devinfo->nid = nid; 1621 devinfo->node_type = fctgrptype; 1622 devinfo->codec = codec; 1623 1624 hdac_add_child(sc, devinfo); 1625 1626 return (devinfo); 1627} 1628 1629static void 1630hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo) 1631{ 1632 devinfo->dev = device_add_child(sc->dev, NULL, -1); 1633 device_set_ivars(devinfo->dev, (void *)devinfo); 1634 /* XXX - Print more information when booting verbose??? */ 1635} 1636 1637static void 1638hdac_widget_connection_parse(struct hdac_widget *w) 1639{ 1640 struct hdac_softc *sc = w->devinfo->codec->sc; 1641 uint32_t res; 1642 int i, j, max, found, entnum, cnid; 1643 nid_t cad = w->devinfo->codec->cad; 1644 nid_t nid = w->nid; 1645 1646 res = hdac_command(sc, 1647 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 1648 1649 w->nconns = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 1650 1651 if (w->nconns < 1) 1652 return; 1653 1654 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 1655 res = 0; 1656 i = 0; 1657 found = 0; 1658 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 1659 1660 while (i < w->nconns) { 1661 res = hdac_command(sc, 1662 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 1663 for (j = 0; j < entnum; j++) { 1664 cnid = res; 1665 cnid >>= (32 / entnum) * j; 1666 cnid &= (1 << (32 / entnum)) - 1; 1667 if (cnid == 0) 1668 continue; 1669 if (found > max) { 1670 device_printf(sc->dev, 1671 "node %d: Adding %d: " 1672 "Max connection reached!\n", 1673 nid, cnid); 1674 continue; 1675 } 1676 w->conns[found++] = cnid; 1677 } 1678 i += entnum; 1679 } 1680 1681 HDA_BOOTVERBOSE( 1682 if (w->nconns != found) { 1683 device_printf(sc->dev, 1684 "HDA_DEBUG: nid=%d WARNING!!! Connection " 1685 "length=%d != found=%d\n", 1686 nid, w->nconns, found); 1687 } 1688 ); 1689} 1690 1691static uint32_t 1692hdac_widget_pin_getconfig(struct hdac_widget *w) 1693{ 1694 struct hdac_softc *sc; 1695 uint32_t config, orig, id; 1696 nid_t cad, nid; 1697 1698 sc = w->devinfo->codec->sc; 1699 cad = w->devinfo->codec->cad; 1700 nid = w->nid; 1701 id = hdac_codec_id(w->devinfo); 1702 1703 config = hdac_command(sc, 1704 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 1705 cad); 1706 orig = config; 1707 1708 /* 1709 * XXX REWRITE!!!! Don't argue! 1710 */ 1711 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 1712 switch (nid) { 1713 case 26: 1714 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1715 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1716 break; 1717 case 27: 1718 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1719 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 1720 break; 1721 } 1722 } else if (id == HDA_CODEC_ALC880 && 1723 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 1724 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 1725 /* 1726 * Super broken BIOS 1727 */ 1728 switch (nid) { 1729 case 20: 1730 break; 1731 case 21: 1732 break; 1733 case 22: 1734 break; 1735 case 23: 1736 break; 1737 case 24: /* MIC1 */ 1738 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1739 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1740 break; 1741 case 25: /* XXX MIC2 */ 1742 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1743 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 1744 break; 1745 case 26: /* LINE1 */ 1746 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1747 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1748 break; 1749 case 27: /* XXX LINE2 */ 1750 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1751 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 1752 break; 1753 case 28: /* CD */ 1754 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 1755 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 1756 break; 1757 case 30: 1758 break; 1759 case 31: 1760 break; 1761 default: 1762 break; 1763 } 1764 } else if (id == HDA_CODEC_ALC883 && 1765 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 1766 switch (nid) { 1767 case 25: 1768 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1769 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1770 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1771 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1772 break; 1773 default: 1774 break; 1775 } 1776 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor == 1777 HP_V3000_SUBVENDOR) { 1778 switch (nid) { 1779 case 18: 1780 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 1781 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 1782 break; 1783 case 20: 1784 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1785 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1786 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 1787 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1788 break; 1789 case 21: 1790 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 1791 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 1792 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 1793 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 1794 break; 1795 default: 1796 break; 1797 } 1798 } 1799 1800 HDA_BOOTVERBOSE( 1801 if (config != orig) 1802 device_printf(sc->dev, 1803 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n", 1804 nid, orig, config); 1805 ); 1806 1807 return (config); 1808} 1809 1810static uint32_t 1811hdac_widget_pin_getcaps(struct hdac_widget *w) 1812{ 1813 struct hdac_softc *sc; 1814 uint32_t caps, orig, id; 1815 nid_t cad, nid; 1816 1817 sc = w->devinfo->codec->sc; 1818 cad = w->devinfo->codec->cad; 1819 nid = w->nid; 1820 id = hdac_codec_id(w->devinfo); 1821 1822 caps = hdac_command(sc, 1823 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 1824 orig = caps; 1825 1826 HDA_BOOTVERBOSE( 1827 if (caps != orig) 1828 device_printf(sc->dev, 1829 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n", 1830 nid, orig, caps); 1831 ); 1832 1833 return (caps); 1834} 1835 1836static void 1837hdac_widget_pin_parse(struct hdac_widget *w) 1838{ 1839 struct hdac_softc *sc = w->devinfo->codec->sc; 1840 uint32_t config, pincap; 1841 char *devstr, *connstr; 1842 nid_t cad = w->devinfo->codec->cad; 1843 nid_t nid = w->nid; 1844 1845 config = hdac_widget_pin_getconfig(w); 1846 w->wclass.pin.config = config; 1847 1848 pincap = hdac_widget_pin_getcaps(w); 1849 w->wclass.pin.cap = pincap; 1850 1851 w->wclass.pin.ctrl = hdac_command(sc, 1852 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) & 1853 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 1854 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 1855 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE); 1856 1857 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 1858 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 1859 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 1860 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1861 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 1862 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 1863 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 1864 w->param.eapdbtl = hdac_command(sc, 1865 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 1866 w->param.eapdbtl &= 0x7; 1867 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 1868 } else 1869 w->param.eapdbtl = HDAC_INVALID; 1870 1871 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 1872 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 1873 devstr = "line out"; 1874 break; 1875 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 1876 devstr = "speaker"; 1877 break; 1878 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 1879 devstr = "headphones out"; 1880 break; 1881 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 1882 devstr = "CD"; 1883 break; 1884 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 1885 devstr = "SPDIF out"; 1886 break; 1887 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 1888 devstr = "digital (other) out"; 1889 break; 1890 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE: 1891 devstr = "modem, line side"; 1892 break; 1893 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET: 1894 devstr = "modem, handset side"; 1895 break; 1896 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 1897 devstr = "line in"; 1898 break; 1899 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 1900 devstr = "AUX"; 1901 break; 1902 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 1903 devstr = "Mic in"; 1904 break; 1905 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY: 1906 devstr = "telephony"; 1907 break; 1908 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 1909 devstr = "SPDIF in"; 1910 break; 1911 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 1912 devstr = "digital (other) in"; 1913 break; 1914 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER: 1915 devstr = "other"; 1916 break; 1917 default: 1918 devstr = "unknown"; 1919 break; 1920 } 1921 1922 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) { 1923 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK: 1924 connstr = "jack"; 1925 break; 1926 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE: 1927 connstr = "none"; 1928 break; 1929 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED: 1930 connstr = "fixed"; 1931 break; 1932 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH: 1933 connstr = "jack / fixed"; 1934 break; 1935 default: 1936 connstr = "unknown"; 1937 break; 1938 } 1939 1940 strlcat(w->name, ": ", sizeof(w->name)); 1941 strlcat(w->name, devstr, sizeof(w->name)); 1942 strlcat(w->name, " (", sizeof(w->name)); 1943 strlcat(w->name, connstr, sizeof(w->name)); 1944 strlcat(w->name, ")", sizeof(w->name)); 1945} 1946 1947static void 1948hdac_widget_parse(struct hdac_widget *w) 1949{ 1950 struct hdac_softc *sc = w->devinfo->codec->sc; 1951 uint32_t wcap, cap; 1952 char *typestr; 1953 nid_t cad = w->devinfo->codec->cad; 1954 nid_t nid = w->nid; 1955 1956 wcap = hdac_command(sc, 1957 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 1958 cad); 1959 w->param.widget_cap = wcap; 1960 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 1961 1962 switch (w->type) { 1963 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 1964 typestr = "audio output"; 1965 break; 1966 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 1967 typestr = "audio input"; 1968 break; 1969 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 1970 typestr = "audio mixer"; 1971 break; 1972 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 1973 typestr = "audio selector"; 1974 break; 1975 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 1976 typestr = "pin"; 1977 break; 1978 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 1979 typestr = "power widget"; 1980 break; 1981 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 1982 typestr = "volume widget"; 1983 break; 1984 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 1985 typestr = "beep widget"; 1986 break; 1987 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 1988 typestr = "vendor widget"; 1989 break; 1990 default: 1991 typestr = "unknown type"; 1992 break; 1993 } 1994 1995 strlcpy(w->name, typestr, sizeof(w->name)); 1996 1997 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) { 1998 hdac_command(sc, 1999 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), 2000 cad); 2001 DELAY(1000); 2002 } 2003 2004 hdac_widget_connection_parse(w); 2005 2006 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2007 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2008 w->param.outamp_cap = 2009 hdac_command(sc, 2010 HDA_CMD_GET_PARAMETER(cad, nid, 2011 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2012 else 2013 w->param.outamp_cap = 2014 w->devinfo->function.audio.outamp_cap; 2015 } else 2016 w->param.outamp_cap = 0; 2017 2018 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2019 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2020 w->param.inamp_cap = 2021 hdac_command(sc, 2022 HDA_CMD_GET_PARAMETER(cad, nid, 2023 HDA_PARAM_INPUT_AMP_CAP), cad); 2024 else 2025 w->param.inamp_cap = 2026 w->devinfo->function.audio.inamp_cap; 2027 } else 2028 w->param.inamp_cap = 0; 2029 2030 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2031 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2032 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2033 cap = hdac_command(sc, 2034 HDA_CMD_GET_PARAMETER(cad, nid, 2035 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2036 w->param.supp_stream_formats = (cap != 0) ? cap : 2037 w->devinfo->function.audio.supp_stream_formats; 2038 cap = hdac_command(sc, 2039 HDA_CMD_GET_PARAMETER(cad, nid, 2040 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2041 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2042 w->devinfo->function.audio.supp_pcm_size_rate; 2043 } else { 2044 w->param.supp_stream_formats = 2045 w->devinfo->function.audio.supp_stream_formats; 2046 w->param.supp_pcm_size_rate = 2047 w->devinfo->function.audio.supp_pcm_size_rate; 2048 } 2049 } else { 2050 w->param.supp_stream_formats = 0; 2051 w->param.supp_pcm_size_rate = 0; 2052 } 2053 2054 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2055 hdac_widget_pin_parse(w); 2056} 2057 2058static struct hdac_widget * 2059hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2060{ 2061 if (devinfo == NULL || devinfo->widget == NULL || 2062 nid < devinfo->startnode || nid >= devinfo->endnode) 2063 return (NULL); 2064 return (&devinfo->widget[nid - devinfo->startnode]); 2065} 2066 2067static __inline int 2068hda_poll_channel(struct hdac_chan *ch) 2069{ 2070 uint32_t sz, delta; 2071 volatile uint32_t ptr; 2072 2073 if (ch->active == 0) 2074 return (0); 2075 2076 sz = ch->blksz * ch->blkcnt; 2077 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, ch->off + HDAC_SDLPIB); 2078 ch->ptr = ptr; 2079 ptr %= sz; 2080 ptr &= ~(ch->blksz - 1); 2081 delta = (sz + ptr - ch->prevptr) % sz; 2082 2083 if (delta < ch->blksz) 2084 return (0); 2085 2086 ch->prevptr = ptr; 2087 2088 return (1); 2089} 2090 2091#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active) 2092 2093static void 2094hda_poll_callback(void *arg) 2095{ 2096 struct hdac_softc *sc = arg; 2097 uint32_t trigger = 0; 2098 2099 if (sc == NULL) 2100 return; 2101 2102 hdac_lock(sc); 2103 if (sc->polling == 0 || hda_chan_active(sc) == 0) { 2104 hdac_unlock(sc); 2105 return; 2106 } 2107 2108 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0; 2109 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0; 2110 2111 /* XXX */ 2112 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/, 2113 hda_poll_callback, sc); 2114 2115 hdac_unlock(sc); 2116 2117 if (trigger & 1) 2118 chn_intr(sc->play.c); 2119 if (trigger & 2) 2120 chn_intr(sc->rec.c); 2121} 2122 2123static int 2124hdac_rirb_flush(struct hdac_softc *sc) 2125{ 2126 struct hdac_rirb *rirb_base, *rirb; 2127 struct hdac_codec *codec; 2128 struct hdac_command_list *commands; 2129 nid_t cad; 2130 uint32_t resp; 2131 uint8_t rirbwp; 2132 int ret = 0; 2133 2134 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2135 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2136 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2137 BUS_DMASYNC_POSTREAD); 2138 2139 while (sc->rirb_rp != rirbwp) { 2140 sc->rirb_rp++; 2141 sc->rirb_rp %= sc->rirb_size; 2142 rirb = &rirb_base[sc->rirb_rp]; 2143 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2144 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2145 sc->codecs[cad] == NULL) 2146 continue; 2147 resp = rirb->response; 2148 codec = sc->codecs[cad]; 2149 commands = codec->commands; 2150 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2151 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2152 ((resp >> 26) & 0xffff); 2153 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2154 } else if (commands != NULL && commands->num_commands > 0 && 2155 codec->responses_received < commands->num_commands) 2156 commands->responses[codec->responses_received++] = 2157 resp; 2158 ret++; 2159 } 2160 2161 return (ret); 2162} 2163 2164static int 2165hdac_unsolq_flush(struct hdac_softc *sc) 2166{ 2167 nid_t cad; 2168 uint32_t tag; 2169 int ret = 0; 2170 2171 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2172 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2173 while (sc->unsolq_rp != sc->unsolq_wp) { 2174 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2175 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2176 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2177 hdac_unsolicited_handler(sc->codecs[cad], tag); 2178 ret++; 2179 } 2180 sc->unsolq_st = HDAC_UNSOLQ_READY; 2181 } 2182 2183 return (ret); 2184} 2185 2186static void 2187hdac_poll_callback(void *arg) 2188{ 2189 struct hdac_softc *sc = arg; 2190 if (sc == NULL) 2191 return; 2192 2193 hdac_lock(sc); 2194 if (sc->polling == 0) { 2195 hdac_unlock(sc); 2196 return; 2197 } 2198 hdac_rirb_flush(sc); 2199 hdac_unsolq_flush(sc); 2200 callout_reset(&sc->poll_hdac, max(hz >> 2, 1), 2201 hdac_poll_callback, sc); 2202 hdac_unlock(sc); 2203} 2204 2205static void 2206hdac_stream_stop(struct hdac_chan *ch) 2207{ 2208 struct hdac_softc *sc = ch->devinfo->codec->sc; 2209 uint32_t ctl; 2210 2211 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2212 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2213 HDAC_SDCTL_RUN); 2214 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2215 2216 ch->active = 0; 2217 2218 if (sc->polling != 0) { 2219 int pollticks; 2220 2221 if (hda_chan_active(sc) == 0) { 2222 callout_stop(&sc->poll_hda); 2223 sc->poll_ticks = 1; 2224 } else { 2225 if (sc->play.active != 0) 2226 ch = &sc->play; 2227 else 2228 ch = &sc->rec; 2229 pollticks = ((uint64_t)hz * ch->blksz) / 2230 ((uint64_t)sndbuf_getbps(ch->b) * 2231 sndbuf_getspd(ch->b)); 2232 pollticks >>= 2; 2233 if (pollticks > hz) 2234 pollticks = hz; 2235 if (pollticks < 1) { 2236 HDA_BOOTVERBOSE( 2237 device_printf(sc->dev, 2238 "%s: pollticks=%d < 1 !\n", 2239 __func__, pollticks); 2240 ); 2241 pollticks = 1; 2242 } 2243 if (pollticks > sc->poll_ticks) { 2244 HDA_BOOTVERBOSE( 2245 device_printf(sc->dev, 2246 "%s: pollticks %d -> %d\n", 2247 __func__, sc->poll_ticks, 2248 pollticks); 2249 ); 2250 sc->poll_ticks = pollticks; 2251 callout_reset(&sc->poll_hda, 1, 2252 hda_poll_callback, sc); 2253 } 2254 } 2255 } else { 2256 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2257 ctl &= ~(1 << (ch->off >> 5)); 2258 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2259 } 2260} 2261 2262static void 2263hdac_stream_start(struct hdac_chan *ch) 2264{ 2265 struct hdac_softc *sc = ch->devinfo->codec->sc; 2266 uint32_t ctl; 2267 2268 if (sc->polling != 0) { 2269 int pollticks; 2270 2271 pollticks = ((uint64_t)hz * ch->blksz) / 2272 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b)); 2273 pollticks >>= 2; 2274 if (pollticks > hz) 2275 pollticks = hz; 2276 if (pollticks < 1) { 2277 HDA_BOOTVERBOSE( 2278 device_printf(sc->dev, 2279 "%s: pollticks=%d < 1 !\n", 2280 __func__, pollticks); 2281 ); 2282 pollticks = 1; 2283 } 2284 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) { 2285 HDA_BOOTVERBOSE( 2286 if (hda_chan_active(sc) == 0) { 2287 device_printf(sc->dev, 2288 "%s: pollticks=%d\n", 2289 __func__, pollticks); 2290 } else { 2291 device_printf(sc->dev, 2292 "%s: pollticks %d -> %d\n", 2293 __func__, sc->poll_ticks, 2294 pollticks); 2295 } 2296 ); 2297 sc->poll_ticks = pollticks; 2298 callout_reset(&sc->poll_hda, 1, hda_poll_callback, 2299 sc); 2300 } 2301 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2302 ctl |= HDAC_SDCTL_RUN; 2303 } else { 2304 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2305 ctl |= 1 << (ch->off >> 5); 2306 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2307 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2308 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2309 HDAC_SDCTL_RUN; 2310 } 2311 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2312 2313 ch->active = 1; 2314} 2315 2316static void 2317hdac_stream_reset(struct hdac_chan *ch) 2318{ 2319 struct hdac_softc *sc = ch->devinfo->codec->sc; 2320 int timeout = 1000; 2321 int to = timeout; 2322 uint32_t ctl; 2323 2324 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2325 ctl |= HDAC_SDCTL_SRST; 2326 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2327 do { 2328 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2329 if (ctl & HDAC_SDCTL_SRST) 2330 break; 2331 DELAY(10); 2332 } while (--to); 2333 if (!(ctl & HDAC_SDCTL_SRST)) { 2334 device_printf(sc->dev, "timeout in reset\n"); 2335 } 2336 ctl &= ~HDAC_SDCTL_SRST; 2337 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2338 to = timeout; 2339 do { 2340 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2341 if (!(ctl & HDAC_SDCTL_SRST)) 2342 break; 2343 DELAY(10); 2344 } while (--to); 2345 if (ctl & HDAC_SDCTL_SRST) 2346 device_printf(sc->dev, "can't reset!\n"); 2347} 2348 2349static void 2350hdac_stream_setid(struct hdac_chan *ch) 2351{ 2352 struct hdac_softc *sc = ch->devinfo->codec->sc; 2353 uint32_t ctl; 2354 2355 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 2356 ctl &= ~HDAC_SDCTL2_STRM_MASK; 2357 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 2358 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 2359} 2360 2361static void 2362hdac_bdl_setup(struct hdac_chan *ch) 2363{ 2364 struct hdac_softc *sc = ch->devinfo->codec->sc; 2365 struct hdac_bdle *bdle; 2366 uint64_t addr; 2367 uint32_t blksz, blkcnt; 2368 int i; 2369 2370 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 2371 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 2372 2373 if (sc->polling != 0) { 2374 blksz = ch->blksz * ch->blkcnt; 2375 blkcnt = 1; 2376 } else { 2377 blksz = ch->blksz; 2378 blkcnt = ch->blkcnt; 2379 } 2380 2381 for (i = 0; i < blkcnt; i++, bdle++) { 2382 bdle->addrl = (uint32_t)addr; 2383 bdle->addrh = (uint32_t)(addr >> 32); 2384 bdle->len = blksz; 2385 bdle->ioc = 1 ^ sc->polling; 2386 addr += blksz; 2387 } 2388 2389 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 2390 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 2391 addr = ch->bdl_dma.dma_paddr; 2392 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 2393 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 2394} 2395 2396static int 2397hdac_bdl_alloc(struct hdac_chan *ch) 2398{ 2399 struct hdac_softc *sc = ch->devinfo->codec->sc; 2400 int rc; 2401 2402 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 2403 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 2404 if (rc) { 2405 device_printf(sc->dev, "can't alloc bdl\n"); 2406 return (rc); 2407 } 2408 hdac_dma_nocache(ch->bdl_dma.dma_vaddr); 2409 2410 return (0); 2411} 2412 2413static void 2414hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 2415 int index, int lmute, int rmute, 2416 int left, int right, int dir) 2417{ 2418 uint16_t v = 0; 2419 2420 if (sc == NULL) 2421 return; 2422 2423 if (left != right || lmute != rmute) { 2424 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 2425 (lmute << 7) | left; 2426 hdac_command(sc, 2427 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2428 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 2429 (rmute << 7) | right; 2430 } else 2431 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 2432 (lmute << 7) | left; 2433 2434 hdac_command(sc, 2435 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 2436} 2437 2438static void 2439hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 2440 int left, int right) 2441{ 2442 struct hdac_softc *sc; 2443 nid_t nid, cad; 2444 int lmute, rmute; 2445 2446 if (ctl == NULL || ctl->widget == NULL || 2447 ctl->widget->devinfo == NULL || 2448 ctl->widget->devinfo->codec == NULL || 2449 ctl->widget->devinfo->codec->sc == NULL) 2450 return; 2451 2452 sc = ctl->widget->devinfo->codec->sc; 2453 cad = ctl->widget->devinfo->codec->cad; 2454 nid = ctl->widget->nid; 2455 2456 if (mute == HDA_AMP_MUTE_DEFAULT) { 2457 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 2458 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 2459 } else { 2460 lmute = HDA_AMP_LEFT_MUTED(mute); 2461 rmute = HDA_AMP_RIGHT_MUTED(mute); 2462 } 2463 2464 if (ctl->dir & HDA_CTL_OUT) 2465 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2466 lmute, rmute, left, right, 0); 2467 if (ctl->dir & HDA_CTL_IN) 2468 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 2469 lmute, rmute, left, right, 1); 2470 ctl->left = left; 2471 ctl->right = right; 2472} 2473 2474static void 2475hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 2476{ 2477 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 2478 return; 2479 hdac_command(w->devinfo->codec->sc, 2480 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 2481 w->nid, index), w->devinfo->codec->cad); 2482 w->selconn = index; 2483} 2484 2485 2486/**************************************************************************** 2487 * uint32_t hdac_command_sendone_internal 2488 * 2489 * Wrapper function that sends only one command to a given codec 2490 ****************************************************************************/ 2491static uint32_t 2492hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 2493{ 2494 struct hdac_command_list cl; 2495 uint32_t response = HDAC_INVALID; 2496 2497 if (!hdac_lockowned(sc)) 2498 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 2499 cl.num_commands = 1; 2500 cl.verbs = &verb; 2501 cl.responses = &response; 2502 2503 hdac_command_send_internal(sc, &cl, cad); 2504 2505 return (response); 2506} 2507 2508/**************************************************************************** 2509 * hdac_command_send_internal 2510 * 2511 * Send a command list to the codec via the corb. We queue as much verbs as 2512 * we can and msleep on the codec. When the interrupt get the responses 2513 * back from the rirb, it will wake us up so we can queue the remaining verbs 2514 * if any. 2515 ****************************************************************************/ 2516static void 2517hdac_command_send_internal(struct hdac_softc *sc, 2518 struct hdac_command_list *commands, nid_t cad) 2519{ 2520 struct hdac_codec *codec; 2521 int corbrp; 2522 uint32_t *corb; 2523 int timeout; 2524 int retry = 10; 2525 struct hdac_rirb *rirb_base; 2526 2527 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 2528 commands->num_commands < 1) 2529 return; 2530 2531 codec = sc->codecs[cad]; 2532 codec->commands = commands; 2533 codec->responses_received = 0; 2534 codec->verbs_sent = 0; 2535 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 2536 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2537 2538 do { 2539 if (codec->verbs_sent != commands->num_commands) { 2540 /* Queue as many verbs as possible */ 2541 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 2542 bus_dmamap_sync(sc->corb_dma.dma_tag, 2543 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 2544 while (codec->verbs_sent != commands->num_commands && 2545 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 2546 sc->corb_wp++; 2547 sc->corb_wp %= sc->corb_size; 2548 corb[sc->corb_wp] = 2549 commands->verbs[codec->verbs_sent++]; 2550 } 2551 2552 /* Send the verbs to the codecs */ 2553 bus_dmamap_sync(sc->corb_dma.dma_tag, 2554 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 2555 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 2556 } 2557 2558 timeout = 1000; 2559 while (hdac_rirb_flush(sc) == 0 && --timeout) 2560 DELAY(10); 2561 } while ((codec->verbs_sent != commands->num_commands || 2562 codec->responses_received != commands->num_commands) && --retry); 2563 2564 if (retry == 0) 2565 device_printf(sc->dev, 2566 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 2567 __func__, commands->num_commands, codec->verbs_sent, 2568 codec->responses_received); 2569 2570 codec->commands = NULL; 2571 codec->responses_received = 0; 2572 codec->verbs_sent = 0; 2573 2574 hdac_unsolq_flush(sc); 2575} 2576 2577 2578/**************************************************************************** 2579 * Device Methods 2580 ****************************************************************************/ 2581 2582/**************************************************************************** 2583 * int hdac_probe(device_t) 2584 * 2585 * Probe for the presence of an hdac. If none is found, check for a generic 2586 * match using the subclass of the device. 2587 ****************************************************************************/ 2588static int 2589hdac_probe(device_t dev) 2590{ 2591 int i, result; 2592 uint32_t model; 2593 uint16_t class, subclass; 2594 char desc[64]; 2595 2596 model = (uint32_t)pci_get_device(dev) << 16; 2597 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 2598 class = pci_get_class(dev); 2599 subclass = pci_get_subclass(dev); 2600 2601 bzero(desc, sizeof(desc)); 2602 result = ENXIO; 2603 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 2604 if (hdac_devices[i].model == model) { 2605 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2606 result = BUS_PROBE_DEFAULT; 2607 break; 2608 } 2609 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 2610 class == PCIC_MULTIMEDIA && 2611 subclass == PCIS_MULTIMEDIA_HDA) { 2612 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 2613 result = BUS_PROBE_GENERIC; 2614 break; 2615 } 2616 } 2617 if (result == ENXIO && class == PCIC_MULTIMEDIA && 2618 subclass == PCIS_MULTIMEDIA_HDA) { 2619 strlcpy(desc, "Generic", sizeof(desc)); 2620 result = BUS_PROBE_GENERIC; 2621 } 2622 if (result != ENXIO) { 2623 strlcat(desc, " High Definition Audio Controller", 2624 sizeof(desc)); 2625 device_set_desc_copy(dev, desc); 2626 } 2627 2628 return (result); 2629} 2630 2631static void * 2632hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 2633 struct pcm_channel *c, int dir) 2634{ 2635 struct hdac_devinfo *devinfo = data; 2636 struct hdac_softc *sc = devinfo->codec->sc; 2637 struct hdac_chan *ch; 2638 2639 hdac_lock(sc); 2640 if (dir == PCMDIR_PLAY) { 2641 ch = &sc->play; 2642 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5; 2643 ch->dir = PCMDIR_PLAY; 2644 ch->sid = ++sc->streamcnt; 2645 devinfo->function.audio.playcnt++; 2646 } else { 2647 ch = &sc->rec; 2648 ch->off = devinfo->function.audio.reccnt << 5; 2649 ch->dir = PCMDIR_REC; 2650 ch->sid = ++sc->streamcnt; 2651 devinfo->function.audio.reccnt++; 2652 } 2653 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 2654 ch->caps.minspeed = ch->caps.maxspeed = 48000; 2655 ch->pcmrates[0] = 48000; 2656 ch->pcmrates[1] = 0; 2657 } 2658 ch->b = b; 2659 ch->c = c; 2660 ch->devinfo = devinfo; 2661 ch->blksz = sc->chan_size / sc->chan_blkcnt; 2662 ch->blkcnt = sc->chan_blkcnt; 2663 hdac_unlock(sc); 2664 2665 if (hdac_bdl_alloc(ch) != 0) { 2666 ch->blkcnt = 0; 2667 return (NULL); 2668 } 2669 2670 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0) 2671 return (NULL); 2672 2673 hdac_dma_nocache(ch->b->buf); 2674 2675 return (ch); 2676} 2677 2678static int 2679hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 2680{ 2681 struct hdac_chan *ch = data; 2682 int i; 2683 2684 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 2685 if (format == ch->caps.fmtlist[i]) { 2686 ch->fmt = format; 2687 return (0); 2688 } 2689 } 2690 2691 return (EINVAL); 2692} 2693 2694static int 2695hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 2696{ 2697 struct hdac_chan *ch = data; 2698 uint32_t spd = 0, threshold; 2699 int i; 2700 2701 for (i = 0; ch->pcmrates[i] != 0; i++) { 2702 spd = ch->pcmrates[i]; 2703 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 2704 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 2705 if (speed < threshold) 2706 break; 2707 } 2708 2709 if (spd == 0) /* impossible */ 2710 ch->spd = 48000; 2711 else 2712 ch->spd = spd; 2713 2714 return (ch->spd); 2715} 2716 2717static void 2718hdac_stream_setup(struct hdac_chan *ch) 2719{ 2720 struct hdac_softc *sc = ch->devinfo->codec->sc; 2721 int i; 2722 nid_t cad = ch->devinfo->codec->cad; 2723 uint16_t fmt; 2724 2725 fmt = 0; 2726 if (ch->fmt & AFMT_S16_LE) 2727 fmt |= ch->bit16 << 4; 2728 else if (ch->fmt & AFMT_S32_LE) 2729 fmt |= ch->bit32 << 4; 2730 else 2731 fmt |= 1 << 4; 2732 2733 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 2734 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 2735 fmt |= hda_rate_tab[i].base; 2736 fmt |= hda_rate_tab[i].mul; 2737 fmt |= hda_rate_tab[i].div; 2738 break; 2739 } 2740 } 2741 2742 if (ch->fmt & AFMT_STEREO) 2743 fmt |= 1; 2744 2745 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 2746 2747 for (i = 0; ch->io[i] != -1; i++) { 2748 HDA_BOOTVERBOSE( 2749 device_printf(sc->dev, 2750 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d " 2751 "fmt=0x%08x\n", 2752 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 2753 ch->io[i], fmt); 2754 ); 2755 hdac_command(sc, 2756 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 2757 hdac_command(sc, 2758 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2759 ch->sid << 4), cad); 2760 } 2761} 2762 2763static int 2764hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 2765{ 2766 struct hdac_chan *ch = data; 2767 struct hdac_softc *sc = ch->devinfo->codec->sc; 2768 2769 blksz &= ~0x7f; 2770 if (blksz < 0x80) 2771 blksz = 0x80; 2772 2773 if ((blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->b)) 2774 blksz = sndbuf_getmaxsize(ch->b) / ch->blkcnt; 2775 2776 if ((sndbuf_getblksz(ch->b) != blksz || 2777 sndbuf_getblkcnt(ch->b) != ch->blkcnt) && 2778 sndbuf_resize(ch->b, ch->blkcnt, blksz) != 0) 2779 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 2780 __func__, blksz, ch->blkcnt); 2781 2782 ch->blksz = sndbuf_getblksz(ch->b); 2783 2784 return (ch->blksz); 2785} 2786 2787static void 2788hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 2789{ 2790 struct hdac_devinfo *devinfo = ch->devinfo; 2791 nid_t cad = devinfo->codec->cad; 2792 int i; 2793 2794 hdac_stream_stop(ch); 2795 2796 for (i = 0; ch->io[i] != -1; i++) { 2797 hdac_command(sc, 2798 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 2799 0), cad); 2800 } 2801} 2802 2803static void 2804hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 2805{ 2806 ch->ptr = 0; 2807 ch->prevptr = 0; 2808 hdac_stream_stop(ch); 2809 hdac_stream_reset(ch); 2810 hdac_bdl_setup(ch); 2811 hdac_stream_setid(ch); 2812 hdac_stream_setup(ch); 2813 hdac_stream_start(ch); 2814} 2815 2816static int 2817hdac_channel_trigger(kobj_t obj, void *data, int go) 2818{ 2819 struct hdac_chan *ch = data; 2820 struct hdac_softc *sc = ch->devinfo->codec->sc; 2821 2822 hdac_lock(sc); 2823 switch (go) { 2824 case PCMTRIG_START: 2825 hdac_channel_start(sc, ch); 2826 break; 2827 case PCMTRIG_STOP: 2828 case PCMTRIG_ABORT: 2829 hdac_channel_stop(sc, ch); 2830 break; 2831 } 2832 hdac_unlock(sc); 2833 2834 return (0); 2835} 2836 2837static int 2838hdac_channel_getptr(kobj_t obj, void *data) 2839{ 2840 struct hdac_chan *ch = data; 2841 struct hdac_softc *sc = ch->devinfo->codec->sc; 2842 uint32_t ptr; 2843 2844 hdac_lock(sc); 2845 if (sc->polling != 0) 2846 ptr = ch->ptr; 2847 else 2848 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 2849 hdac_unlock(sc); 2850 2851 /* 2852 * Round to available space and force 128 bytes aligment. 2853 */ 2854 ptr %= ch->blksz * ch->blkcnt; 2855 ptr &= ~0x7f; 2856 2857 return (ptr); 2858} 2859 2860static struct pcmchan_caps * 2861hdac_channel_getcaps(kobj_t obj, void *data) 2862{ 2863 return (&((struct hdac_chan *)data)->caps); 2864} 2865 2866static kobj_method_t hdac_channel_methods[] = { 2867 KOBJMETHOD(channel_init, hdac_channel_init), 2868 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 2869 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 2870 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 2871 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 2872 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 2873 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 2874 { 0, 0 } 2875}; 2876CHANNEL_DECLARE(hdac_channel); 2877 2878static int 2879hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 2880{ 2881 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 2882 struct hdac_softc *sc = devinfo->codec->sc; 2883 struct hdac_widget *w, *cw; 2884 struct hdac_audio_ctl *ctl; 2885 uint32_t mask, recmask, id; 2886 int i, j, softpcmvol; 2887 nid_t cad; 2888 2889 hdac_lock(sc); 2890 2891 mask = 0; 2892 recmask = 0; 2893 2894 id = hdac_codec_id(devinfo); 2895 cad = devinfo->codec->cad; 2896 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) { 2897 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model, 2898 sc->pci_subvendor) && 2899 hdac_hp_switch[i].id == id)) 2900 continue; 2901 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid); 2902 if (w != NULL && w->enable != 0 2903 && w->type == 2904 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 2905 HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 2906 hdac_command(sc, 2907 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, 2908 w->nid, 2909 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE| 2910 HDAC_UNSOLTAG_EVENT_HP), cad); 2911 hdac_hp_switch_handler(devinfo); 2912 HDA_BOOTVERBOSE( 2913 device_printf(sc->dev, 2914 "HDA_DEBUG: Enabling headphone/speaker " 2915 "audio routing switching:\n"); 2916 device_printf(sc->dev, 2917 "HDA_DEBUG: \tindex=%d nid=%d " 2918 "pci_subvendor=0x%08x " 2919 "codec=0x%08x\n", 2920 i, w->nid, sc->pci_subvendor, id); 2921 ); 2922 } 2923 break; 2924 } 2925 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 2926 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model, 2927 sc->pci_subvendor) && 2928 hdac_eapd_switch[i].id == id)) 2929 continue; 2930 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 2931 if (w == NULL || w->enable == 0) 2932 break; 2933 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 2934 w->param.eapdbtl == HDAC_INVALID) 2935 break; 2936 mask |= SOUND_MASK_OGAIN; 2937 break; 2938 } 2939 2940 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 2941 w = hdac_widget_get(devinfo, i); 2942 if (w == NULL || w->enable == 0) 2943 continue; 2944 mask |= w->ctlflags; 2945 if (!(w->pflags & HDA_ADC_RECSEL)) 2946 continue; 2947 for (j = 0; j < w->nconns; j++) { 2948 cw = hdac_widget_get(devinfo, w->conns[j]); 2949 if (cw == NULL || cw->enable == 0) 2950 continue; 2951 recmask |= cw->ctlflags; 2952 } 2953 } 2954 2955 if (!(mask & SOUND_MASK_PCM)) { 2956 softpcmvol = 1; 2957 mask |= SOUND_MASK_PCM; 2958 } else 2959 softpcmvol = (devinfo->function.audio.quirks & 2960 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0; 2961 2962 i = 0; 2963 ctl = NULL; 2964 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 2965 if (ctl->widget == NULL || ctl->enable == 0) 2966 continue; 2967 if (!(ctl->ossmask & SOUND_MASK_PCM)) 2968 continue; 2969 if (ctl->step > 0) 2970 break; 2971 } 2972 2973 if (softpcmvol == 1 || ctl == NULL) { 2974 struct snddev_info *d = NULL; 2975 d = device_get_softc(sc->dev); 2976 if (d != NULL) { 2977 d->flags |= SD_F_SOFTPCMVOL; 2978 HDA_BOOTVERBOSE( 2979 device_printf(sc->dev, 2980 "HDA_DEBUG: %s Soft PCM volume\n", 2981 (softpcmvol == 1) ? 2982 "Forcing" : "Enabling"); 2983 ); 2984 } 2985 i = 0; 2986 /* 2987 * XXX Temporary quirk for STAC9220, until the parser 2988 * become smarter. 2989 */ 2990 if (id == HDA_CODEC_STAC9220) { 2991 mask |= SOUND_MASK_VOLUME; 2992 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 2993 NULL) { 2994 if (ctl->widget == NULL || ctl->enable == 0) 2995 continue; 2996 if (ctl->widget->nid == 11 && ctl->index == 0) { 2997 ctl->ossmask = SOUND_MASK_VOLUME; 2998 ctl->ossval = 100 | (100 << 8); 2999 } else 3000 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3001 } 3002 } else if (id == HDA_CODEC_STAC9221) { 3003 mask |= SOUND_MASK_VOLUME; 3004 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3005 NULL) { 3006 if (ctl->widget == NULL) 3007 continue; 3008 if (ctl->widget->nid == 2 && ctl->index == 0) { 3009 ctl->enable = 1; 3010 ctl->ossmask = SOUND_MASK_VOLUME; 3011 ctl->ossval = 100 | (100 << 8); 3012 } else if (ctl->enable == 0) 3013 continue; 3014 else 3015 ctl->ossmask &= ~SOUND_MASK_VOLUME; 3016 } 3017 } else { 3018 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3019 SOUND_MASK_PCM); 3020 if (!(mask & SOUND_MASK_VOLUME)) 3021 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3022 SOUND_MIXER_NONE); 3023 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != 3024 NULL) { 3025 if (ctl->widget == NULL || ctl->enable == 0) 3026 continue; 3027 if (!HDA_FLAG_MATCH(ctl->ossmask, 3028 SOUND_MASK_VOLUME | SOUND_MASK_PCM)) 3029 continue; 3030 if (!(ctl->mute == 1 && ctl->step == 0)) 3031 ctl->enable = 0; 3032 } 3033 } 3034 } 3035 3036 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER); 3037 3038 mix_setrecdevs(m, recmask); 3039 mix_setdevs(m, mask); 3040 3041 hdac_unlock(sc); 3042 3043 return (0); 3044} 3045 3046static int 3047hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3048 unsigned left, unsigned right) 3049{ 3050 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3051 struct hdac_softc *sc = devinfo->codec->sc; 3052 struct hdac_widget *w; 3053 struct hdac_audio_ctl *ctl; 3054 uint32_t id, mute; 3055 int lvol, rvol, mlvol, mrvol; 3056 int i = 0; 3057 3058 hdac_lock(sc); 3059 if (dev == SOUND_MIXER_OGAIN) { 3060 uint32_t orig; 3061 /*if (left != right || !(left == 0 || left == 1)) { 3062 hdac_unlock(sc); 3063 return (-1); 3064 }*/ 3065 id = hdac_codec_id(devinfo); 3066 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) { 3067 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model, 3068 sc->pci_subvendor) && 3069 hdac_eapd_switch[i].id == id) 3070 break; 3071 } 3072 if (i >= HDAC_EAPD_SWITCH_LEN) { 3073 hdac_unlock(sc); 3074 return (-1); 3075 } 3076 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid); 3077 if (w == NULL || 3078 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3079 w->param.eapdbtl == HDAC_INVALID) { 3080 hdac_unlock(sc); 3081 return (-1); 3082 } 3083 orig = w->param.eapdbtl; 3084 if (left == 0) 3085 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3086 else 3087 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3088 if (orig != w->param.eapdbtl) { 3089 uint32_t val; 3090 3091 if (hdac_eapd_switch[i].hp_switch != 0) 3092 hdac_hp_switch_handler(devinfo); 3093 val = w->param.eapdbtl; 3094 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3095 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3096 hdac_command(sc, 3097 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3098 w->nid, val), devinfo->codec->cad); 3099 } 3100 hdac_unlock(sc); 3101 return (left | (left << 8)); 3102 } 3103 if (dev == SOUND_MIXER_VOLUME) 3104 devinfo->function.audio.mvol = left | (right << 8); 3105 3106 mlvol = devinfo->function.audio.mvol & 0x7f; 3107 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f; 3108 lvol = 0; 3109 rvol = 0; 3110 3111 i = 0; 3112 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3113 if (ctl->widget == NULL || ctl->enable == 0 || 3114 !(ctl->ossmask & (1 << dev))) 3115 continue; 3116 switch (dev) { 3117 case SOUND_MIXER_VOLUME: 3118 lvol = ((ctl->ossval & 0x7f) * left) / 100; 3119 lvol = (lvol * ctl->step) / 100; 3120 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100; 3121 rvol = (rvol * ctl->step) / 100; 3122 break; 3123 default: 3124 if (ctl->ossmask & SOUND_MASK_VOLUME) { 3125 lvol = (left * mlvol) / 100; 3126 lvol = (lvol * ctl->step) / 100; 3127 rvol = (right * mrvol) / 100; 3128 rvol = (rvol * ctl->step) / 100; 3129 } else { 3130 lvol = (left * ctl->step) / 100; 3131 rvol = (right * ctl->step) / 100; 3132 } 3133 ctl->ossval = left | (right << 8); 3134 break; 3135 } 3136 mute = 0; 3137 if (ctl->step < 1) { 3138 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT : 3139 (ctl->muted & HDA_AMP_MUTE_LEFT); 3140 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 3141 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3142 } else { 3143 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT : 3144 (ctl->muted & HDA_AMP_MUTE_LEFT); 3145 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 3146 (ctl->muted & HDA_AMP_MUTE_RIGHT); 3147 } 3148 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3149 } 3150 hdac_unlock(sc); 3151 3152 return (left | (right << 8)); 3153} 3154 3155static int 3156hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3157{ 3158 struct hdac_devinfo *devinfo = mix_getdevinfo(m); 3159 struct hdac_widget *w, *cw; 3160 struct hdac_softc *sc = devinfo->codec->sc; 3161 uint32_t ret = src, target; 3162 int i, j; 3163 3164 target = 0; 3165 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3166 if (src & (1 << i)) { 3167 target = 1 << i; 3168 break; 3169 } 3170 } 3171 3172 hdac_lock(sc); 3173 3174 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3175 w = hdac_widget_get(devinfo, i); 3176 if (w == NULL || w->enable == 0) 3177 continue; 3178 if (!(w->pflags & HDA_ADC_RECSEL)) 3179 continue; 3180 for (j = 0; j < w->nconns; j++) { 3181 cw = hdac_widget_get(devinfo, w->conns[j]); 3182 if (cw == NULL || cw->enable == 0) 3183 continue; 3184 if ((target == SOUND_MASK_VOLUME && 3185 cw->type != 3186 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 3187 (target != SOUND_MASK_VOLUME && 3188 cw->type == 3189 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)) 3190 continue; 3191 if (cw->ctlflags & target) { 3192 hdac_widget_connection_select(w, j); 3193 ret = target; 3194 j += w->nconns; 3195 } 3196 } 3197 } 3198 3199 hdac_unlock(sc); 3200 3201 return (ret); 3202} 3203 3204static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3205 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3206 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3207 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3208 { 0, 0 } 3209}; 3210MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3211 3212/**************************************************************************** 3213 * int hdac_attach(device_t) 3214 * 3215 * Attach the device into the kernel. Interrupts usually won't be enabled 3216 * when this function is called. Setup everything that doesn't require 3217 * interrupts and defer probing of codecs until interrupts are enabled. 3218 ****************************************************************************/ 3219static int 3220hdac_attach(device_t dev) 3221{ 3222 struct hdac_softc *sc; 3223 int result; 3224 int i = 0; 3225 3226 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO); 3227 if (sc == NULL) { 3228 device_printf(dev, "cannot allocate softc\n"); 3229 return (ENOMEM); 3230 } 3231 3232 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3233 if (sc->lock == NULL) { 3234 device_printf(dev, "mutex creation failed\n"); 3235 free(sc, M_DEVBUF); 3236 return (ENOMEM); 3237 } 3238 3239 sc->dev = dev; 3240 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3241 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3242 3243 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3244 /* Screw nx6325 - subdevice/subvendor swapped */ 3245 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3246 } 3247 3248 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3249 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 3250 3251 sc->poll_ticks = 1; 3252 if (resource_int_value(device_get_name(sc->dev), 3253 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 3254 sc->polling = 1; 3255 else 3256 sc->polling = 0; 3257 3258 sc->chan_size = pcm_getbuffersize(dev, 3259 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 3260 3261 if (resource_int_value(device_get_name(sc->dev), 3262 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 3263 i &= ~0x7f; 3264 if (i < 0x80) 3265 i = 0x80; 3266 sc->chan_blkcnt = sc->chan_size / i; 3267 i = 0; 3268 while (sc->chan_blkcnt >> i) 3269 i++; 3270 sc->chan_blkcnt = 1 << (i - 1); 3271 if (sc->chan_blkcnt < HDA_BDL_MIN) 3272 sc->chan_blkcnt = HDA_BDL_MIN; 3273 else if (sc->chan_blkcnt > HDA_BDL_MAX) 3274 sc->chan_blkcnt = HDA_BDL_MAX; 3275 } else 3276 sc->chan_blkcnt = HDA_BDL_DEFAULT; 3277 3278 result = bus_dma_tag_create(NULL, /* parent */ 3279 HDAC_DMA_ALIGNMENT, /* alignment */ 3280 0, /* boundary */ 3281 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3282 BUS_SPACE_MAXADDR, /* highaddr */ 3283 NULL, /* filtfunc */ 3284 NULL, /* fistfuncarg */ 3285 sc->chan_size, /* maxsize */ 3286 1, /* nsegments */ 3287 sc->chan_size, /* maxsegsz */ 3288 0, /* flags */ 3289 NULL, /* lockfunc */ 3290 NULL, /* lockfuncarg */ 3291 &sc->chan_dmat); /* dmat */ 3292 if (result != 0) { 3293 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 3294 __func__, result); 3295 snd_mtxfree(sc->lock); 3296 free(sc, M_DEVBUF); 3297 return (ENXIO); 3298 } 3299 3300 3301 sc->hdabus = NULL; 3302 for (i = 0; i < HDAC_CODEC_MAX; i++) 3303 sc->codecs[i] = NULL; 3304 3305 pci_enable_busmaster(dev); 3306 3307 /* Allocate resources */ 3308 result = hdac_mem_alloc(sc); 3309 if (result != 0) 3310 goto hdac_attach_fail; 3311 result = hdac_irq_alloc(sc); 3312 if (result != 0) 3313 goto hdac_attach_fail; 3314 3315 /* Get Capabilities */ 3316 result = hdac_get_capabilities(sc); 3317 if (result != 0) 3318 goto hdac_attach_fail; 3319 3320 /* Allocate CORB and RIRB dma memory */ 3321 result = hdac_dma_alloc(sc, &sc->corb_dma, 3322 sc->corb_size * sizeof(uint32_t)); 3323 if (result != 0) 3324 goto hdac_attach_fail; 3325 result = hdac_dma_alloc(sc, &sc->rirb_dma, 3326 sc->rirb_size * sizeof(struct hdac_rirb)); 3327 if (result != 0) 3328 goto hdac_attach_fail; 3329 3330 /* Quiesce everything */ 3331 hdac_reset(sc); 3332 3333 /* Disable PCI-Express QOS */ 3334 pci_write_config(sc->dev, 0x44, 3335 pci_read_config(sc->dev, 0x44, 1) & 0xf8, 1); 3336 3337 /* Initialize the CORB and RIRB */ 3338 hdac_corb_init(sc); 3339 hdac_rirb_init(sc); 3340 3341 /* Defer remaining of initialization until interrupts are enabled */ 3342 sc->intrhook.ich_func = hdac_attach2; 3343 sc->intrhook.ich_arg = (void *)sc; 3344 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 3345 sc->intrhook.ich_func = NULL; 3346 hdac_attach2((void *)sc); 3347 } 3348 3349 return (0); 3350 3351hdac_attach_fail: 3352 hdac_dma_free(&sc->rirb_dma); 3353 hdac_dma_free(&sc->corb_dma); 3354 hdac_irq_free(sc); 3355 hdac_mem_free(sc); 3356 snd_mtxfree(sc->lock); 3357 free(sc, M_DEVBUF); 3358 3359 return (ENXIO); 3360} 3361 3362static void 3363hdac_audio_parse(struct hdac_devinfo *devinfo) 3364{ 3365 struct hdac_softc *sc = devinfo->codec->sc; 3366 struct hdac_widget *w; 3367 uint32_t res; 3368 int i; 3369 nid_t cad, nid; 3370 3371 cad = devinfo->codec->cad; 3372 nid = devinfo->nid; 3373 3374 hdac_command(sc, 3375 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad); 3376 3377 DELAY(100); 3378 3379 res = hdac_command(sc, 3380 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 3381 3382 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 3383 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 3384 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 3385 3386 HDA_BOOTVERBOSE( 3387 device_printf(sc->dev, " Vendor: 0x%08x\n", 3388 devinfo->vendor_id); 3389 device_printf(sc->dev, " Device: 0x%08x\n", 3390 devinfo->device_id); 3391 device_printf(sc->dev, " Revision: 0x%08x\n", 3392 devinfo->revision_id); 3393 device_printf(sc->dev, " Stepping: 0x%08x\n", 3394 devinfo->stepping_id); 3395 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 3396 sc->pci_subvendor); 3397 device_printf(sc->dev, " Nodes: start=%d " 3398 "endnode=%d total=%d\n", 3399 devinfo->startnode, devinfo->endnode, devinfo->nodecnt); 3400 ); 3401 3402 res = hdac_command(sc, 3403 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 3404 cad); 3405 devinfo->function.audio.supp_stream_formats = res; 3406 3407 res = hdac_command(sc, 3408 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 3409 cad); 3410 devinfo->function.audio.supp_pcm_size_rate = res; 3411 3412 res = hdac_command(sc, 3413 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 3414 cad); 3415 devinfo->function.audio.outamp_cap = res; 3416 3417 res = hdac_command(sc, 3418 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 3419 cad); 3420 devinfo->function.audio.inamp_cap = res; 3421 3422 if (devinfo->nodecnt > 0) { 3423 hdac_unlock(sc); 3424 devinfo->widget = (struct hdac_widget *)malloc( 3425 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 3426 M_NOWAIT | M_ZERO); 3427 hdac_lock(sc); 3428 } else 3429 devinfo->widget = NULL; 3430 3431 if (devinfo->widget == NULL) { 3432 device_printf(sc->dev, "unable to allocate widgets!\n"); 3433 devinfo->endnode = devinfo->startnode; 3434 devinfo->nodecnt = 0; 3435 return; 3436 } 3437 3438 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3439 w = hdac_widget_get(devinfo, i); 3440 if (w == NULL) 3441 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 3442 else { 3443 w->devinfo = devinfo; 3444 w->nid = i; 3445 w->enable = 1; 3446 w->selconn = -1; 3447 w->pflags = 0; 3448 w->ctlflags = 0; 3449 w->param.eapdbtl = HDAC_INVALID; 3450 hdac_widget_parse(w); 3451 } 3452 } 3453} 3454 3455static void 3456hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 3457{ 3458 struct hdac_softc *sc = devinfo->codec->sc; 3459 struct hdac_audio_ctl *ctls; 3460 struct hdac_widget *w, *cw; 3461 int i, j, cnt, max, ocap, icap; 3462 int mute, offset, step, size; 3463 3464 /* XXX This is redundant */ 3465 max = 0; 3466 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3467 w = hdac_widget_get(devinfo, i); 3468 if (w == NULL || w->enable == 0) 3469 continue; 3470 if (w->param.outamp_cap != 0) 3471 max++; 3472 if (w->param.inamp_cap != 0) { 3473 switch (w->type) { 3474 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3475 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3476 for (j = 0; j < w->nconns; j++) { 3477 cw = hdac_widget_get(devinfo, 3478 w->conns[j]); 3479 if (cw == NULL || cw->enable == 0) 3480 continue; 3481 max++; 3482 } 3483 break; 3484 default: 3485 max++; 3486 break; 3487 } 3488 } 3489 } 3490 3491 devinfo->function.audio.ctlcnt = max; 3492 3493 if (max < 1) 3494 return; 3495 3496 hdac_unlock(sc); 3497 ctls = (struct hdac_audio_ctl *)malloc( 3498 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 3499 hdac_lock(sc); 3500 3501 if (ctls == NULL) { 3502 /* Blekh! */ 3503 device_printf(sc->dev, "unable to allocate ctls!\n"); 3504 devinfo->function.audio.ctlcnt = 0; 3505 return; 3506 } 3507 3508 cnt = 0; 3509 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 3510 if (cnt >= max) { 3511 device_printf(sc->dev, "%s: Ctl overflow!\n", 3512 __func__); 3513 break; 3514 } 3515 w = hdac_widget_get(devinfo, i); 3516 if (w == NULL || w->enable == 0) 3517 continue; 3518 ocap = w->param.outamp_cap; 3519 icap = w->param.inamp_cap; 3520 if (ocap != 0) { 3521 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 3522 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 3523 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 3524 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 3525 /*if (offset > step) { 3526 HDA_BOOTVERBOSE( 3527 device_printf(sc->dev, 3528 "HDA_DEBUG: BUGGY outamp: nid=%d " 3529 "[offset=%d > step=%d]\n", 3530 w->nid, offset, step); 3531 ); 3532 offset = step; 3533 }*/ 3534 ctls[cnt].enable = 1; 3535 ctls[cnt].widget = w; 3536 ctls[cnt].mute = mute; 3537 ctls[cnt].step = step; 3538 ctls[cnt].size = size; 3539 ctls[cnt].offset = offset; 3540 ctls[cnt].left = offset; 3541 ctls[cnt].right = offset; 3542 ctls[cnt++].dir = HDA_CTL_OUT; 3543 } 3544 3545 if (icap != 0) { 3546 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 3547 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 3548 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 3549 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 3550 /*if (offset > step) { 3551 HDA_BOOTVERBOSE( 3552 device_printf(sc->dev, 3553 "HDA_DEBUG: BUGGY inamp: nid=%d " 3554 "[offset=%d > step=%d]\n", 3555 w->nid, offset, step); 3556 ); 3557 offset = step; 3558 }*/ 3559 switch (w->type) { 3560 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3561 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3562 for (j = 0; j < w->nconns; j++) { 3563 if (cnt >= max) { 3564 device_printf(sc->dev, 3565 "%s: Ctl overflow!\n", 3566 __func__); 3567 break; 3568 } 3569 cw = hdac_widget_get(devinfo, 3570 w->conns[j]); 3571 if (cw == NULL || cw->enable == 0) 3572 continue; 3573 ctls[cnt].enable = 1; 3574 ctls[cnt].widget = w; 3575 ctls[cnt].childwidget = cw; 3576 ctls[cnt].index = j; 3577 ctls[cnt].mute = mute; 3578 ctls[cnt].step = step; 3579 ctls[cnt].size = size; 3580 ctls[cnt].offset = offset; 3581 ctls[cnt].left = offset; 3582 ctls[cnt].right = offset; 3583 ctls[cnt++].dir = HDA_CTL_IN; 3584 } 3585 break; 3586 default: 3587 if (cnt >= max) { 3588 device_printf(sc->dev, 3589 "%s: Ctl overflow!\n", 3590 __func__); 3591 break; 3592 } 3593 ctls[cnt].enable = 1; 3594 ctls[cnt].widget = w; 3595 ctls[cnt].mute = mute; 3596 ctls[cnt].step = step; 3597 ctls[cnt].size = size; 3598 ctls[cnt].offset = offset; 3599 ctls[cnt].left = offset; 3600 ctls[cnt].right = offset; 3601 ctls[cnt++].dir = HDA_CTL_IN; 3602 break; 3603 } 3604 } 3605 } 3606 3607 devinfo->function.audio.ctl = ctls; 3608} 3609 3610static const struct { 3611 uint32_t model; 3612 uint32_t id; 3613 uint32_t set, unset; 3614} hdac_quirks[] = { 3615 /* 3616 * XXX Force stereo quirk. Monoural recording / playback 3617 * on few codecs (especially ALC880) seems broken or 3618 * perhaps unsupported. 3619 */ 3620 { HDA_MATCH_ALL, HDA_MATCH_ALL, 3621 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_VREF, 0 }, 3622 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 3623 HDA_QUIRK_GPIO0, 0 }, 3624 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 3625 HDA_QUIRK_GPIO0, 0 }, 3626 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 3627 HDA_QUIRK_GPIO0, 0 }, 3628 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 3629 HDA_QUIRK_EAPDINV, 0 }, 3630 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A, 3631 HDA_QUIRK_EAPDINV, 0 }, 3632 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 3633 HDA_QUIRK_GPIO1, 0 }, 3634 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 3635 HDA_QUIRK_EAPDINV, 0 }, 3636 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 3637 HDA_QUIRK_EAPDINV, 0 }, 3638 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 3639 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 3640 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE, 3641 0, HDA_QUIRK_FORCESTEREO }, 3642 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX, 3643 HDA_QUIRK_SOFTPCMVOL, 0 } 3644}; 3645#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 3646 3647static void 3648hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 3649{ 3650 struct hdac_widget *w; 3651 struct hdac_audio_ctl *ctl; 3652 uint32_t id, subvendor; 3653 int i; 3654 3655 id = hdac_codec_id(devinfo); 3656 subvendor = devinfo->codec->sc->pci_subvendor; 3657 3658 /* 3659 * Quirks 3660 */ 3661 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 3662 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 3663 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 3664 continue; 3665 if (hdac_quirks[i].set != 0) 3666 devinfo->function.audio.quirks |= 3667 hdac_quirks[i].set; 3668 if (hdac_quirks[i].unset != 0) 3669 devinfo->function.audio.quirks &= 3670 ~(hdac_quirks[i].unset); 3671 } 3672 3673 switch (id) { 3674 case HDA_CODEC_ALC260: 3675 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3676 w = hdac_widget_get(devinfo, i); 3677 if (w == NULL || w->enable == 0) 3678 continue; 3679 if (w->type != 3680 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 3681 continue; 3682 if (w->nid != 5) 3683 w->enable = 0; 3684 } 3685 if (subvendor == HP_XW4300_SUBVENDOR) { 3686 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1); 3687 if (ctl != NULL && ctl->widget != NULL) { 3688 ctl->ossmask = SOUND_MASK_SPEAKER; 3689 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3690 } 3691 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1); 3692 if (ctl != NULL && ctl->widget != NULL) { 3693 ctl->ossmask = SOUND_MASK_SPEAKER; 3694 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER; 3695 } 3696 } 3697 break; 3698 case HDA_CODEC_ALC861: 3699 ctl = hdac_audio_ctl_amp_get(devinfo, 28, 1, 1); 3700 if (ctl != NULL) 3701 ctl->muted = HDA_AMP_MUTE_ALL; 3702 break; 3703 case HDA_CODEC_ALC880: 3704 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3705 w = hdac_widget_get(devinfo, i); 3706 if (w == NULL || w->enable == 0) 3707 continue; 3708 if (w->type == 3709 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3710 w->nid != 9 && w->nid != 29) { 3711 w->enable = 0; 3712 } else if (w->type != 3713 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET && 3714 w->nid == 29) { 3715 w->type = 3716 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET; 3717 w->param.widget_cap &= 3718 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 3719 w->param.widget_cap |= 3720 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 3721 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 3722 strlcpy(w->name, "beep widget", sizeof(w->name)); 3723 } 3724 } 3725 break; 3726 case HDA_CODEC_ALC883: 3727 /* 3728 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 3729 * Clear vref cap for jack connectivity. 3730 */ 3731 w = hdac_widget_get(devinfo, 24); 3732 if (w != NULL && w->enable != 0 && w->type == 3733 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3734 (w->wclass.pin.config & 3735 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3736 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3737 w->wclass.pin.cap &= ~( 3738 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3739 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3740 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3741 w = hdac_widget_get(devinfo, 25); 3742 if (w != NULL && w->enable != 0 && w->type == 3743 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3744 (w->wclass.pin.config & 3745 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 3746 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 3747 w->wclass.pin.cap &= ~( 3748 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 3749 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 3750 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 3751 /* 3752 * nid: 26 = Line-in, leave it alone. 3753 */ 3754 break; 3755 case HDA_CODEC_AD1981HD: 3756 w = hdac_widget_get(devinfo, 11); 3757 if (w != NULL && w->enable != 0 && w->nconns > 3) 3758 w->selconn = 3; 3759 if (subvendor == IBM_M52_SUBVENDOR) { 3760 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1); 3761 if (ctl != NULL) 3762 ctl->ossmask = SOUND_MASK_SPEAKER; 3763 } 3764 break; 3765 case HDA_CODEC_AD1986A: 3766 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3767 w = hdac_widget_get(devinfo, i); 3768 if (w == NULL || w->enable == 0) 3769 continue; 3770 if (w->type != 3771 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3772 continue; 3773 if (w->nid != 3) 3774 w->enable = 0; 3775 } 3776 break; 3777 case HDA_CODEC_STAC9221: 3778 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3779 w = hdac_widget_get(devinfo, i); 3780 if (w == NULL || w->enable == 0) 3781 continue; 3782 if (w->type != 3783 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) 3784 continue; 3785 if (w->nid != 2) 3786 w->enable = 0; 3787 } 3788 break; 3789 case HDA_CODEC_STAC9221D: 3790 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3791 w = hdac_widget_get(devinfo, i); 3792 if (w == NULL || w->enable == 0) 3793 continue; 3794 if (w->type == 3795 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 3796 w->nid != 6) 3797 w->enable = 0; 3798 3799 } 3800 break; 3801 default: 3802 break; 3803 } 3804} 3805 3806static int 3807hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo) 3808{ 3809 int *dev = &devinfo->function.audio.ossidx; 3810 3811 while (*dev < SOUND_MIXER_NRDEVICES) { 3812 switch (*dev) { 3813 case SOUND_MIXER_VOLUME: 3814 case SOUND_MIXER_BASS: 3815 case SOUND_MIXER_TREBLE: 3816 case SOUND_MIXER_PCM: 3817 case SOUND_MIXER_SPEAKER: 3818 case SOUND_MIXER_LINE: 3819 case SOUND_MIXER_MIC: 3820 case SOUND_MIXER_CD: 3821 case SOUND_MIXER_RECLEV: 3822 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */ 3823 (*dev)++; 3824 break; 3825 default: 3826 return (*dev)++; 3827 break; 3828 } 3829 } 3830 3831 return (-1); 3832} 3833 3834static int 3835hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3836{ 3837 struct hdac_widget *w; 3838 int i, ret = 0; 3839 3840 if (depth > HDA_PARSE_MAXDEPTH) 3841 return (0); 3842 w = hdac_widget_get(devinfo, nid); 3843 if (w == NULL || w->enable == 0) 3844 return (0); 3845 switch (w->type) { 3846 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 3847 w->pflags |= HDA_DAC_PATH; 3848 ret = 1; 3849 break; 3850 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3851 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3852 for (i = 0; i < w->nconns; i++) { 3853 if (hdac_widget_find_dac_path(devinfo, 3854 w->conns[i], depth + 1) != 0) { 3855 if (w->selconn == -1) 3856 w->selconn = i; 3857 ret = 1; 3858 w->pflags |= HDA_DAC_PATH; 3859 } 3860 } 3861 break; 3862 default: 3863 break; 3864 } 3865 return (ret); 3866} 3867 3868static int 3869hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth) 3870{ 3871 struct hdac_widget *w; 3872 int i, conndev, ret = 0; 3873 3874 if (depth > HDA_PARSE_MAXDEPTH) 3875 return (0); 3876 w = hdac_widget_get(devinfo, nid); 3877 if (w == NULL || w->enable == 0) 3878 return (0); 3879 switch (w->type) { 3880 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 3881 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 3882 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3883 for (i = 0; i < w->nconns; i++) { 3884 if (hdac_widget_find_adc_path(devinfo, w->conns[i], 3885 depth + 1) != 0) { 3886 if (w->selconn == -1) 3887 w->selconn = i; 3888 w->pflags |= HDA_ADC_PATH; 3889 ret = 1; 3890 } 3891 } 3892 break; 3893 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 3894 conndev = w->wclass.pin.config & 3895 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3896 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3897 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD || 3898 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN || 3899 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) { 3900 w->pflags |= HDA_ADC_PATH; 3901 ret = 1; 3902 } 3903 break; 3904 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 3905 if (w->pflags & HDA_DAC_PATH) { 3906 w->pflags |= HDA_ADC_PATH; 3907 ret = 1; 3908 } 3909 break;*/ 3910 default: 3911 break; 3912 } 3913 return (ret); 3914} 3915 3916static uint32_t 3917hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo, 3918 nid_t nid, nid_t pnid, int index, int depth) 3919{ 3920 struct hdac_widget *w, *pw; 3921 struct hdac_audio_ctl *ctl; 3922 uint32_t fl = 0; 3923 int i, ossdev, conndev, strategy; 3924 3925 if (depth > HDA_PARSE_MAXDEPTH) 3926 return (0); 3927 3928 w = hdac_widget_get(devinfo, nid); 3929 if (w == NULL || w->enable == 0) 3930 return (0); 3931 3932 pw = hdac_widget_get(devinfo, pnid); 3933 strategy = devinfo->function.audio.parsing_strategy; 3934 3935 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 3936 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) { 3937 for (i = 0; i < w->nconns; i++) { 3938 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i], 3939 w->nid, i, depth + 1); 3940 } 3941 w->ctlflags |= fl; 3942 return (fl); 3943 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT && 3944 (w->pflags & HDA_DAC_PATH)) { 3945 i = 0; 3946 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3947 if (ctl->enable == 0 || ctl->widget == NULL) 3948 continue; 3949 /* XXX This should be compressed! */ 3950 if ((ctl->widget->nid == w->nid) || 3951 (ctl->widget->nid == pnid && ctl->index == index && 3952 (ctl->dir & HDA_CTL_IN)) || 3953 (ctl->widget->nid == pnid && pw != NULL && 3954 pw->type == 3955 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 3956 (pw->nconns < 2 || pw->selconn == index || 3957 pw->selconn == -1) && 3958 (ctl->dir & HDA_CTL_OUT)) || 3959 (strategy == HDA_PARSE_DIRECT && 3960 ctl->widget->nid == w->nid)) { 3961 /*if (pw != NULL && pw->selconn == -1) 3962 pw->selconn = index; 3963 fl |= SOUND_MASK_VOLUME; 3964 fl |= SOUND_MASK_PCM; 3965 ctl->ossmask |= SOUND_MASK_VOLUME; 3966 ctl->ossmask |= SOUND_MASK_PCM; 3967 ctl->ossdev = SOUND_MIXER_PCM;*/ 3968 if (!(w->ctlflags & SOUND_MASK_PCM) || 3969 (pw != NULL && 3970 !(pw->ctlflags & SOUND_MASK_PCM))) { 3971 fl |= SOUND_MASK_VOLUME; 3972 fl |= SOUND_MASK_PCM; 3973 ctl->ossmask |= SOUND_MASK_VOLUME; 3974 ctl->ossmask |= SOUND_MASK_PCM; 3975 ctl->ossdev = SOUND_MIXER_PCM; 3976 w->ctlflags |= SOUND_MASK_VOLUME; 3977 w->ctlflags |= SOUND_MASK_PCM; 3978 if (pw != NULL) { 3979 if (pw->selconn == -1) 3980 pw->selconn = index; 3981 pw->ctlflags |= 3982 SOUND_MASK_VOLUME; 3983 pw->ctlflags |= 3984 SOUND_MASK_PCM; 3985 } 3986 } 3987 } 3988 } 3989 w->ctlflags |= fl; 3990 return (fl); 3991 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 3992 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) && 3993 (w->pflags & HDA_ADC_PATH)) { 3994 conndev = w->wclass.pin.config & 3995 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 3996 i = 0; 3997 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3998 if (ctl->enable == 0 || ctl->widget == NULL) 3999 continue; 4000 /* XXX This should be compressed! */ 4001 if (((ctl->widget->nid == pnid && ctl->index == index && 4002 (ctl->dir & HDA_CTL_IN)) || 4003 (ctl->widget->nid == pnid && pw != NULL && 4004 pw->type == 4005 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4006 (pw->nconns < 2 || pw->selconn == index || 4007 pw->selconn == -1) && 4008 (ctl->dir & HDA_CTL_OUT)) || 4009 (strategy == HDA_PARSE_DIRECT && 4010 ctl->widget->nid == w->nid)) && 4011 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4012 if (pw != NULL && pw->selconn == -1) 4013 pw->selconn = index; 4014 ossdev = 0; 4015 switch (conndev) { 4016 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 4017 ossdev = SOUND_MIXER_MIC; 4018 break; 4019 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 4020 ossdev = SOUND_MIXER_LINE; 4021 break; 4022 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 4023 ossdev = SOUND_MIXER_CD; 4024 break; 4025 default: 4026 ossdev = 4027 hdac_audio_ctl_ossmixer_getnextdev( 4028 devinfo); 4029 if (ossdev < 0) 4030 ossdev = 0; 4031 break; 4032 } 4033 if (strategy == HDA_PARSE_MIXER) { 4034 fl |= SOUND_MASK_VOLUME; 4035 ctl->ossmask |= SOUND_MASK_VOLUME; 4036 } 4037 fl |= 1 << ossdev; 4038 ctl->ossmask |= 1 << ossdev; 4039 ctl->ossdev = ossdev; 4040 } 4041 } 4042 w->ctlflags |= fl; 4043 return (fl); 4044 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4045 i = 0; 4046 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4047 if (ctl->enable == 0 || ctl->widget == NULL) 4048 continue; 4049 /* XXX This should be compressed! */ 4050 if (((ctl->widget->nid == pnid && ctl->index == index && 4051 (ctl->dir & HDA_CTL_IN)) || 4052 (ctl->widget->nid == pnid && pw != NULL && 4053 pw->type == 4054 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 4055 (pw->nconns < 2 || pw->selconn == index || 4056 pw->selconn == -1) && 4057 (ctl->dir & HDA_CTL_OUT)) || 4058 (strategy == HDA_PARSE_DIRECT && 4059 ctl->widget->nid == w->nid)) && 4060 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) { 4061 if (pw != NULL && pw->selconn == -1) 4062 pw->selconn = index; 4063 fl |= SOUND_MASK_VOLUME; 4064 fl |= SOUND_MASK_SPEAKER; 4065 ctl->ossmask |= SOUND_MASK_VOLUME; 4066 ctl->ossmask |= SOUND_MASK_SPEAKER; 4067 ctl->ossdev = SOUND_MIXER_SPEAKER; 4068 } 4069 } 4070 w->ctlflags |= fl; 4071 return (fl); 4072 } 4073 return (0); 4074} 4075 4076static uint32_t 4077hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4078{ 4079 struct hdac_widget *w, *cw; 4080 struct hdac_audio_ctl *ctl; 4081 uint32_t fl; 4082 int i; 4083 4084 if (depth > HDA_PARSE_MAXDEPTH) 4085 return (0); 4086 4087 w = hdac_widget_get(devinfo, nid); 4088 if (w == NULL || w->enable == 0) 4089 return (0); 4090 /*if (!(w->pflags & HDA_ADC_PATH)) 4091 return (0); 4092 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4093 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4094 return (0);*/ 4095 i = 0; 4096 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4097 if (ctl->enable == 0 || ctl->widget == NULL) 4098 continue; 4099 if (ctl->widget->nid == nid) { 4100 ctl->ossmask |= SOUND_MASK_RECLEV; 4101 w->ctlflags |= SOUND_MASK_RECLEV; 4102 return (SOUND_MASK_RECLEV); 4103 } 4104 } 4105 for (i = 0; i < w->nconns; i++) { 4106 cw = hdac_widget_get(devinfo, w->conns[i]); 4107 if (cw == NULL || cw->enable == 0) 4108 continue; 4109 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4110 continue; 4111 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1); 4112 if (fl != 0) { 4113 cw->ctlflags |= fl; 4114 w->ctlflags |= fl; 4115 return (fl); 4116 } 4117 } 4118 return (0); 4119} 4120 4121static int 4122hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4123{ 4124 struct hdac_widget *w, *cw; 4125 int i, child = 0; 4126 4127 if (depth > HDA_PARSE_MAXDEPTH) 4128 return (0); 4129 4130 w = hdac_widget_get(devinfo, nid); 4131 if (w == NULL || w->enable == 0) 4132 return (0); 4133 /*if (!(w->pflags & HDA_ADC_PATH)) 4134 return (0); 4135 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 4136 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4137 return (0);*/ 4138 /* XXX weak! */ 4139 for (i = 0; i < w->nconns; i++) { 4140 cw = hdac_widget_get(devinfo, w->conns[i]); 4141 if (cw == NULL) 4142 continue; 4143 if (++child > 1) { 4144 w->pflags |= HDA_ADC_RECSEL; 4145 return (1); 4146 } 4147 } 4148 for (i = 0; i < w->nconns; i++) { 4149 if (hdac_audio_ctl_recsel_build(devinfo, 4150 w->conns[i], depth + 1) != 0) 4151 return (1); 4152 } 4153 return (0); 4154} 4155 4156static int 4157hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo) 4158{ 4159 struct hdac_widget *w, *cw; 4160 int i, j, conndev, found_dac = 0; 4161 int strategy; 4162 4163 strategy = devinfo->function.audio.parsing_strategy; 4164 4165 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4166 w = hdac_widget_get(devinfo, i); 4167 if (w == NULL || w->enable == 0) 4168 continue; 4169 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4170 continue; 4171 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap)) 4172 continue; 4173 conndev = w->wclass.pin.config & 4174 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4175 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4176 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4177 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT)) 4178 continue; 4179 for (j = 0; j < w->nconns; j++) { 4180 cw = hdac_widget_get(devinfo, w->conns[j]); 4181 if (cw == NULL || cw->enable == 0) 4182 continue; 4183 if (strategy == HDA_PARSE_MIXER && !(cw->type == 4184 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4185 cw->type == 4186 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4187 continue; 4188 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0) 4189 != 0) { 4190 if (w->selconn == -1) 4191 w->selconn = j; 4192 w->pflags |= HDA_DAC_PATH; 4193 found_dac++; 4194 } 4195 } 4196 } 4197 4198 return (found_dac); 4199} 4200 4201static void 4202hdac_audio_build_tree(struct hdac_devinfo *devinfo) 4203{ 4204 struct hdac_widget *w; 4205 struct hdac_audio_ctl *ctl; 4206 int i, j, dacs, strategy; 4207 4208 /* Construct DAC path */ 4209 strategy = HDA_PARSE_MIXER; 4210 devinfo->function.audio.parsing_strategy = strategy; 4211 HDA_BOOTVERBOSE( 4212 device_printf(devinfo->codec->sc->dev, 4213 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n", 4214 HDA_WIDGET_PARSER_REV); 4215 ); 4216 dacs = hdac_audio_build_tree_strategy(devinfo); 4217 if (dacs == 0) { 4218 HDA_BOOTVERBOSE( 4219 device_printf(devinfo->codec->sc->dev, 4220 "HDA_DEBUG: HWiP: 0 DAC path found! " 4221 "Retrying parser " 4222 "using HDA_PARSE_DIRECT strategy.\n"); 4223 ); 4224 strategy = HDA_PARSE_DIRECT; 4225 devinfo->function.audio.parsing_strategy = strategy; 4226 dacs = hdac_audio_build_tree_strategy(devinfo); 4227 } 4228 4229 HDA_BOOTVERBOSE( 4230 device_printf(devinfo->codec->sc->dev, 4231 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s " 4232 "strategy.\n", 4233 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT"); 4234 ); 4235 4236 /* Construct ADC path */ 4237 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4238 w = hdac_widget_get(devinfo, i); 4239 if (w == NULL || w->enable == 0) 4240 continue; 4241 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 4242 continue; 4243 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0); 4244 } 4245 4246 /* Output mixers */ 4247 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4248 w = hdac_widget_get(devinfo, i); 4249 if (w == NULL || w->enable == 0) 4250 continue; 4251 if ((strategy == HDA_PARSE_MIXER && 4252 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER || 4253 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) 4254 && (w->pflags & HDA_DAC_PATH)) || 4255 (strategy == HDA_PARSE_DIRECT && (w->pflags & 4256 (HDA_DAC_PATH | HDA_ADC_PATH)))) { 4257 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo, 4258 w->nid, devinfo->startnode - 1, 0, 0); 4259 } else if (w->type == 4260 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) { 4261 j = 0; 4262 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) != 4263 NULL) { 4264 if (ctl->enable == 0 || ctl->widget == NULL) 4265 continue; 4266 if (ctl->widget->nid != w->nid) 4267 continue; 4268 ctl->ossmask |= SOUND_MASK_VOLUME; 4269 ctl->ossmask |= SOUND_MASK_SPEAKER; 4270 ctl->ossdev = SOUND_MIXER_SPEAKER; 4271 w->ctlflags |= SOUND_MASK_VOLUME; 4272 w->ctlflags |= SOUND_MASK_SPEAKER; 4273 } 4274 } 4275 } 4276 4277 /* Input mixers (rec) */ 4278 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4279 w = hdac_widget_get(devinfo, i); 4280 if (w == NULL || w->enable == 0) 4281 continue; 4282 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT && 4283 w->pflags & HDA_ADC_PATH)) 4284 continue; 4285 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0); 4286 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0); 4287 } 4288} 4289 4290#define HDA_COMMIT_CONN (1 << 0) 4291#define HDA_COMMIT_CTRL (1 << 1) 4292#define HDA_COMMIT_EAPD (1 << 2) 4293#define HDA_COMMIT_GPIO (1 << 3) 4294#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \ 4295 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO) 4296 4297static void 4298hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl) 4299{ 4300 struct hdac_softc *sc = devinfo->codec->sc; 4301 struct hdac_widget *w; 4302 nid_t cad; 4303 int i; 4304 4305 if (!(cfl & HDA_COMMIT_ALL)) 4306 return; 4307 4308 cad = devinfo->codec->cad; 4309 4310 if (cfl & HDA_COMMIT_GPIO) { 4311 uint32_t gdata, gmask, gdir; 4312 int commitgpio = 0; 4313 4314 gdata = 0; 4315 gmask = 0; 4316 gdir = 0; 4317 4318 if (sc->pci_subvendor == APPLE_INTEL_MAC) 4319 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 4320 0x7e7, 0), cad); 4321 4322 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 4323 commitgpio = 1; 4324 else { 4325 for (i = 0; i < HDA_GPIO_MAX; i++) { 4326 if (!(devinfo->function.audio.quirks & 4327 (1 << i))) 4328 continue; 4329 if (commitgpio == 0) { 4330 commitgpio = 1; 4331 gdata = hdac_command(sc, 4332 HDA_CMD_GET_GPIO_DATA(cad, 4333 devinfo->nid), cad); 4334 gmask = hdac_command(sc, 4335 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 4336 devinfo->nid), cad); 4337 gdir = hdac_command(sc, 4338 HDA_CMD_GET_GPIO_DIRECTION(cad, 4339 devinfo->nid), cad); 4340 HDA_BOOTVERBOSE( 4341 device_printf(sc->dev, 4342 "GPIO init: data=0x%08x " 4343 "mask=0x%08x dir=0x%08x\n", 4344 gdata, gmask, gdir); 4345 ); 4346 } 4347 gdata |= 1 << i; 4348 gmask |= 1 << i; 4349 gdir |= 1 << i; 4350 } 4351 } 4352 4353 if (commitgpio != 0) { 4354 HDA_BOOTVERBOSE( 4355 device_printf(sc->dev, 4356 "GPIO commit: data=0x%08x mask=0x%08x " 4357 "dir=0x%08x\n", 4358 gdata, gmask, gdir); 4359 ); 4360 hdac_command(sc, 4361 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 4362 gmask), cad); 4363 hdac_command(sc, 4364 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 4365 gdir), cad); 4366 hdac_command(sc, 4367 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 4368 gdata), cad); 4369 } 4370 } 4371 4372 for (i = 0; i < devinfo->nodecnt; i++) { 4373 w = &devinfo->widget[i]; 4374 if (w == NULL || w->enable == 0) 4375 continue; 4376 if (cfl & HDA_COMMIT_CONN) { 4377 if (w->selconn == -1) 4378 w->selconn = 0; 4379 if (w->nconns > 0) 4380 hdac_widget_connection_select(w, w->selconn); 4381 } 4382 if ((cfl & HDA_COMMIT_CTRL) && 4383 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4384 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) == 4385 (HDA_DAC_PATH | HDA_ADC_PATH)) 4386 device_printf(sc->dev, "WARNING: node %d " 4387 "participate both for DAC/ADC!\n", w->nid); 4388 if (w->pflags & HDA_DAC_PATH) { 4389 w->wclass.pin.ctrl &= 4390 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 4391 if ((w->wclass.pin.config & 4392 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) != 4393 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 4394 w->wclass.pin.ctrl &= 4395 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 4396 } else if (w->pflags & HDA_ADC_PATH) { 4397 w->wclass.pin.ctrl &= 4398 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4399 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE); 4400 if (w->devinfo->function.audio.quirks & HDA_QUIRK_VREF) { 4401 uint32_t pincap = w->wclass.pin.cap; 4402 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4403 w->wclass.pin.ctrl |= 4404 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4405 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 4406 ); 4407 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4408 w->wclass.pin.ctrl |= 4409 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4410 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4411 ); 4412 else if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4413 w->wclass.pin.ctrl |= 4414 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 4415 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 4416 ); 4417 } 4418 } else 4419 w->wclass.pin.ctrl &= ~( 4420 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 4421 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 4422 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 4423 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 4424 hdac_command(sc, 4425 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 4426 w->wclass.pin.ctrl), cad); 4427 } 4428 if ((cfl & HDA_COMMIT_EAPD) && 4429 w->param.eapdbtl != HDAC_INVALID) { 4430 uint32_t val; 4431 4432 val = w->param.eapdbtl; 4433 if (devinfo->function.audio.quirks & 4434 HDA_QUIRK_EAPDINV) 4435 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 4436 hdac_command(sc, 4437 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 4438 val), cad); 4439 4440 } 4441 DELAY(1000); 4442 } 4443} 4444 4445static void 4446hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 4447{ 4448 struct hdac_softc *sc = devinfo->codec->sc; 4449 struct hdac_audio_ctl *ctl; 4450 int i; 4451 4452 devinfo->function.audio.mvol = 100 | (100 << 8); 4453 i = 0; 4454 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4455 if (ctl->enable == 0 || ctl->widget == NULL) { 4456 HDA_BOOTVERBOSE( 4457 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4458 i, (ctl->widget != NULL) ? 4459 ctl->widget->nid : -1); 4460 if (ctl->childwidget != NULL) 4461 printf(" childnid=%d", 4462 ctl->childwidget->nid); 4463 if (ctl->widget == NULL) 4464 printf(" NULL WIDGET!"); 4465 printf(" DISABLED\n"); 4466 ); 4467 continue; 4468 } 4469 HDA_BOOTVERBOSE( 4470 if (ctl->ossmask == 0) { 4471 device_printf(sc->dev, "[%2d] Ctl nid=%d", 4472 i, ctl->widget->nid); 4473 if (ctl->childwidget != NULL) 4474 printf(" childnid=%d", 4475 ctl->childwidget->nid); 4476 printf(" Bind to NONE\n"); 4477 } 4478 ); 4479 if (ctl->step > 0) { 4480 ctl->ossval = (ctl->left * 100) / ctl->step; 4481 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8; 4482 } else 4483 ctl->ossval = 0; 4484 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT, 4485 ctl->left, ctl->right); 4486 } 4487} 4488 4489static int 4490hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir) 4491{ 4492 struct hdac_chan *ch; 4493 struct hdac_widget *w; 4494 uint32_t cap, fmtcap, pcmcap, path; 4495 int i, type, ret, max; 4496 4497 if (dir == PCMDIR_PLAY) { 4498 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT; 4499 ch = &devinfo->codec->sc->play; 4500 path = HDA_DAC_PATH; 4501 } else { 4502 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT; 4503 ch = &devinfo->codec->sc->rec; 4504 path = HDA_ADC_PATH; 4505 } 4506 4507 ch->caps = hdac_caps; 4508 ch->caps.fmtlist = ch->fmtlist; 4509 ch->bit16 = 1; 4510 ch->bit32 = 0; 4511 ch->pcmrates[0] = 48000; 4512 ch->pcmrates[1] = 0; 4513 4514 ret = 0; 4515 fmtcap = devinfo->function.audio.supp_stream_formats; 4516 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 4517 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 4518 4519 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) { 4520 w = hdac_widget_get(devinfo, i); 4521 if (w == NULL || w->enable == 0 || w->type != type || 4522 !(w->pflags & path)) 4523 continue; 4524 cap = w->param.widget_cap; 4525 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap)) 4526 continue;*/ 4527 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap)) 4528 continue; 4529 cap = w->param.supp_stream_formats; 4530 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) { 4531 } 4532 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 4533 }*/ 4534 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4535 continue; 4536 if (ret == 0) { 4537 fmtcap = w->param.supp_stream_formats; 4538 pcmcap = w->param.supp_pcm_size_rate; 4539 } else { 4540 fmtcap &= w->param.supp_stream_formats; 4541 pcmcap &= w->param.supp_pcm_size_rate; 4542 } 4543 ch->io[ret++] = i; 4544 } 4545 ch->io[ret] = -1; 4546 4547 ch->supp_stream_formats = fmtcap; 4548 ch->supp_pcm_size_rate = pcmcap; 4549 4550 /* 4551 * 8bit = 0 4552 * 16bit = 1 4553 * 20bit = 2 4554 * 24bit = 3 4555 * 32bit = 4 4556 */ 4557 if (ret > 0) { 4558 cap = pcmcap; 4559 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4560 ch->bit16 = 1; 4561 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4562 ch->bit16 = 0; 4563 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4564 ch->bit32 = 4; 4565 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4566 ch->bit32 = 3; 4567 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4568 ch->bit32 = 2; 4569 i = 0; 4570 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 4571 ch->fmtlist[i++] = AFMT_S16_LE; 4572 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 4573 if (ch->bit32 > 0) { 4574 if (!(devinfo->function.audio.quirks & 4575 HDA_QUIRK_FORCESTEREO)) 4576 ch->fmtlist[i++] = AFMT_S32_LE; 4577 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 4578 } 4579 ch->fmtlist[i] = 0; 4580 i = 0; 4581 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4582 ch->pcmrates[i++] = 8000; 4583 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4584 ch->pcmrates[i++] = 11025; 4585 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4586 ch->pcmrates[i++] = 16000; 4587 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4588 ch->pcmrates[i++] = 22050; 4589 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4590 ch->pcmrates[i++] = 32000; 4591 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4592 ch->pcmrates[i++] = 44100; 4593 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */ 4594 ch->pcmrates[i++] = 48000; 4595 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4596 ch->pcmrates[i++] = 88200; 4597 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4598 ch->pcmrates[i++] = 96000; 4599 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4600 ch->pcmrates[i++] = 176400; 4601 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4602 ch->pcmrates[i++] = 192000; 4603 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */ 4604 ch->pcmrates[i] = 0; 4605 if (i > 0) { 4606 ch->caps.minspeed = ch->pcmrates[0]; 4607 ch->caps.maxspeed = ch->pcmrates[i - 1]; 4608 } 4609 } 4610 4611 return (ret); 4612} 4613 4614static void 4615hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag) 4616{ 4617 struct hdac_audio_ctl *ctl; 4618 struct hdac_softc *sc = devinfo->codec->sc; 4619 int i; 4620 uint32_t fl = 0; 4621 4622 4623 if (flag == 0) { 4624 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM | 4625 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 4626 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN; 4627 } 4628 4629 i = 0; 4630 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4631 if (ctl->enable == 0 || ctl->widget == NULL || 4632 ctl->widget->enable == 0) 4633 continue; 4634 if ((flag == 0 && (ctl->ossmask & ~fl)) || 4635 (flag != 0 && (ctl->ossmask & flag))) { 4636 if (banner != NULL) { 4637 device_printf(sc->dev, "\n"); 4638 device_printf(sc->dev, "%s\n", banner); 4639 } 4640 goto hdac_ctl_dump_it_all; 4641 } 4642 } 4643 4644 return; 4645 4646hdac_ctl_dump_it_all: 4647 i = 0; 4648 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 4649 if (ctl->enable == 0 || ctl->widget == NULL || 4650 ctl->widget->enable == 0) 4651 continue; 4652 if (!((flag == 0 && (ctl->ossmask & ~fl)) || 4653 (flag != 0 && (ctl->ossmask & flag)))) 4654 continue; 4655 if (flag == 0) { 4656 device_printf(sc->dev, "\n"); 4657 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n", 4658 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask)); 4659 } 4660 device_printf(sc->dev, " |\n"); 4661 device_printf(sc->dev, " +- nid: %2d index: %2d ", 4662 ctl->widget->nid, ctl->index); 4663 if (ctl->childwidget != NULL) 4664 printf("(nid: %2d) ", ctl->childwidget->nid); 4665 else 4666 printf(" "); 4667 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n", 4668 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir, 4669 ctl->ossmask); 4670 } 4671} 4672 4673static void 4674hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap) 4675{ 4676 uint32_t cap; 4677 4678 cap = fcap; 4679 if (cap != 0) { 4680 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap); 4681 device_printf(sc->dev, " Format:"); 4682 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 4683 printf(" AC3"); 4684 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 4685 printf(" FLOAT32"); 4686 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 4687 printf(" PCM"); 4688 printf("\n"); 4689 } 4690 cap = pcmcap; 4691 if (cap != 0) { 4692 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap); 4693 device_printf(sc->dev, " PCM size:"); 4694 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 4695 printf(" 8"); 4696 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 4697 printf(" 16"); 4698 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 4699 printf(" 20"); 4700 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 4701 printf(" 24"); 4702 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 4703 printf(" 32"); 4704 printf("\n"); 4705 device_printf(sc->dev, " PCM rate:"); 4706 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 4707 printf(" 8"); 4708 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 4709 printf(" 11"); 4710 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 4711 printf(" 16"); 4712 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 4713 printf(" 22"); 4714 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 4715 printf(" 32"); 4716 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 4717 printf(" 44"); 4718 printf(" 48"); 4719 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 4720 printf(" 88"); 4721 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 4722 printf(" 96"); 4723 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 4724 printf(" 176"); 4725 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 4726 printf(" 192"); 4727 printf("\n"); 4728 } 4729} 4730 4731static void 4732hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 4733{ 4734 uint32_t pincap, wcap; 4735 4736 pincap = w->wclass.pin.cap; 4737 wcap = w->param.widget_cap; 4738 4739 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 4740 device_printf(sc->dev, " "); 4741 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 4742 printf(" ISC"); 4743 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 4744 printf(" TRQD"); 4745 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 4746 printf(" PDC"); 4747 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 4748 printf(" HP"); 4749 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 4750 printf(" OUT"); 4751 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 4752 printf(" IN"); 4753 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 4754 printf(" BAL"); 4755 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 4756 printf(" VREF["); 4757 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 4758 printf(" 50"); 4759 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 4760 printf(" 80"); 4761 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 4762 printf(" 100"); 4763 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 4764 printf(" GROUND"); 4765 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 4766 printf(" HIZ"); 4767 printf(" ]"); 4768 } 4769 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 4770 printf(" EAPD"); 4771 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap)) 4772 printf(" : UNSOL"); 4773 printf("\n"); 4774 device_printf(sc->dev, " Pin config: 0x%08x\n", 4775 w->wclass.pin.config); 4776 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 4777 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 4778 printf(" HP"); 4779 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 4780 printf(" IN"); 4781 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 4782 printf(" OUT"); 4783 printf("\n"); 4784} 4785 4786static void 4787hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 4788{ 4789 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 4790 device_printf(sc->dev, " " 4791 "mute=%d step=%d size=%d offset=%d\n", 4792 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 4793 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 4794 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 4795 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 4796} 4797 4798static void 4799hdac_dump_nodes(struct hdac_devinfo *devinfo) 4800{ 4801 struct hdac_softc *sc = devinfo->codec->sc; 4802 struct hdac_widget *w, *cw; 4803 int i, j; 4804 4805 device_printf(sc->dev, "\n"); 4806 device_printf(sc->dev, "Default Parameter\n"); 4807 device_printf(sc->dev, "-----------------\n"); 4808 hdac_dump_audio_formats(sc, 4809 devinfo->function.audio.supp_stream_formats, 4810 devinfo->function.audio.supp_pcm_size_rate); 4811 device_printf(sc->dev, " IN amp: 0x%08x\n", 4812 devinfo->function.audio.inamp_cap); 4813 device_printf(sc->dev, " OUT amp: 0x%08x\n", 4814 devinfo->function.audio.outamp_cap); 4815 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4816 w = hdac_widget_get(devinfo, i); 4817 if (w == NULL) { 4818 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 4819 continue; 4820 } 4821 device_printf(sc->dev, "\n"); 4822 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid, 4823 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ? 4824 "DIGITAL" : "ANALOG", 4825 (w->enable == 0) ? " [DISABLED]" : ""); 4826 device_printf(sc->dev, " name: %s\n", w->name); 4827 device_printf(sc->dev, " widget_cap: 0x%08x\n", 4828 w->param.widget_cap); 4829 device_printf(sc->dev, " Parse flags: 0x%08x\n", 4830 w->pflags); 4831 device_printf(sc->dev, " Ctl flags: 0x%08x\n", 4832 w->ctlflags); 4833 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 4834 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 4835 hdac_dump_audio_formats(sc, 4836 w->param.supp_stream_formats, 4837 w->param.supp_pcm_size_rate); 4838 } else if (w->type == 4839 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4840 hdac_dump_pin(sc, w); 4841 if (w->param.eapdbtl != HDAC_INVALID) 4842 device_printf(sc->dev, " EAPD: 0x%08x\n", 4843 w->param.eapdbtl); 4844 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 4845 w->param.outamp_cap != 0) 4846 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 4847 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 4848 w->param.inamp_cap != 0) 4849 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 4850 device_printf(sc->dev, " connections: %d\n", w->nconns); 4851 for (j = 0; j < w->nconns; j++) { 4852 cw = hdac_widget_get(devinfo, w->conns[j]); 4853 device_printf(sc->dev, " |\n"); 4854 device_printf(sc->dev, " + <- nid=%d [%s]", 4855 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 4856 if (cw == NULL) 4857 printf(" [UNKNOWN]"); 4858 else if (cw->enable == 0) 4859 printf(" [DISABLED]"); 4860 if (w->nconns > 1 && w->selconn == j && w->type != 4861 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 4862 printf(" (selected)"); 4863 printf("\n"); 4864 } 4865 } 4866 4867} 4868 4869static int 4870hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth) 4871{ 4872 struct hdac_widget *w, *cw; 4873 struct hdac_softc *sc = devinfo->codec->sc; 4874 int i; 4875 4876 if (depth > HDA_PARSE_MAXDEPTH) 4877 return (0); 4878 4879 w = hdac_widget_get(devinfo, nid); 4880 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH)) 4881 return (0); 4882 4883 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 4884 device_printf(sc->dev, "\n"); 4885 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4886 device_printf(sc->dev, " ^\n"); 4887 device_printf(sc->dev, " |\n"); 4888 device_printf(sc->dev, " +-----<------+\n"); 4889 } else { 4890 device_printf(sc->dev, " ^\n"); 4891 device_printf(sc->dev, " |\n"); 4892 device_printf(sc->dev, " "); 4893 printf(" nid=%d [%s]\n", w->nid, w->name); 4894 } 4895 4896 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) { 4897 return (1); 4898 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4899 for (i = 0; i < w->nconns; i++) { 4900 cw = hdac_widget_get(devinfo, w->conns[i]); 4901 if (cw == NULL || cw->enable == 0 || cw->type == 4902 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4903 continue; 4904 if (hdac_dump_dac_internal(devinfo, cw->nid, 4905 depth + 1) != 0) 4906 return (1); 4907 } 4908 } else if ((w->type == 4909 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR || 4910 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 4911 w->selconn > -1 && w->selconn < w->nconns) { 4912 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn], 4913 depth + 1) != 0) 4914 return (1); 4915 } 4916 4917 return (0); 4918} 4919 4920static void 4921hdac_dump_dac(struct hdac_devinfo *devinfo) 4922{ 4923 struct hdac_widget *w; 4924 struct hdac_softc *sc = devinfo->codec->sc; 4925 int i, printed = 0; 4926 4927 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4928 w = hdac_widget_get(devinfo, i); 4929 if (w == NULL || w->enable == 0) 4930 continue; 4931 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4932 !(w->pflags & HDA_DAC_PATH)) 4933 continue; 4934 if (printed == 0) { 4935 printed = 1; 4936 device_printf(sc->dev, "\n"); 4937 device_printf(sc->dev, "Playback path:\n"); 4938 } 4939 hdac_dump_dac_internal(devinfo, w->nid, 0); 4940 } 4941} 4942 4943static void 4944hdac_dump_adc(struct hdac_devinfo *devinfo) 4945{ 4946 struct hdac_widget *w, *cw; 4947 struct hdac_softc *sc = devinfo->codec->sc; 4948 int i, j; 4949 int printed = 0; 4950 char ossdevs[256]; 4951 4952 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4953 w = hdac_widget_get(devinfo, i); 4954 if (w == NULL || w->enable == 0) 4955 continue; 4956 if (!(w->pflags & HDA_ADC_RECSEL)) 4957 continue; 4958 if (printed == 0) { 4959 printed = 1; 4960 device_printf(sc->dev, "\n"); 4961 device_printf(sc->dev, "Recording sources:\n"); 4962 } 4963 device_printf(sc->dev, "\n"); 4964 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name); 4965 for (j = 0; j < w->nconns; j++) { 4966 cw = hdac_widget_get(devinfo, w->conns[j]); 4967 if (cw == NULL || cw->enable == 0) 4968 continue; 4969 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags, 4970 ossdevs, sizeof(ossdevs)); 4971 device_printf(sc->dev, " |\n"); 4972 device_printf(sc->dev, " + <- nid=%d [%s]", 4973 cw->nid, cw->name); 4974 if (strlen(ossdevs) > 0) { 4975 printf(" [recsrc: %s]", ossdevs); 4976 } 4977 printf("\n"); 4978 } 4979 } 4980} 4981 4982static void 4983hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt) 4984{ 4985 nid_t *nids; 4986 4987 if (pcnt > 0) { 4988 device_printf(sc->dev, "\n"); 4989 device_printf(sc->dev, " PCM Playback: %d\n", pcnt); 4990 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 4991 sc->play.supp_pcm_size_rate); 4992 device_printf(sc->dev, " DAC:"); 4993 for (nids = sc->play.io; *nids != -1; nids++) 4994 printf(" %d", *nids); 4995 printf("\n"); 4996 } 4997 4998 if (rcnt > 0) { 4999 device_printf(sc->dev, "\n"); 5000 device_printf(sc->dev, " PCM Record: %d\n", rcnt); 5001 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats, 5002 sc->rec.supp_pcm_size_rate); 5003 device_printf(sc->dev, " ADC:"); 5004 for (nids = sc->rec.io; *nids != -1; nids++) 5005 printf(" %d", *nids); 5006 printf("\n"); 5007 } 5008} 5009 5010static void 5011hdac_release_resources(struct hdac_softc *sc) 5012{ 5013 struct hdac_devinfo *devinfo = NULL; 5014 device_t *devlist = NULL; 5015 int i, devcount; 5016 5017 if (sc == NULL) 5018 return; 5019 5020 hdac_lock(sc); 5021 if (sc->polling != 0) 5022 callout_stop(&sc->poll_hdac); 5023 hdac_reset(sc); 5024 hdac_unlock(sc); 5025 snd_mtxfree(sc->lock); 5026 5027 device_get_children(sc->dev, &devlist, &devcount); 5028 for (i = 0; devlist != NULL && i < devcount; i++) { 5029 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5030 if (devinfo == NULL) 5031 continue; 5032 if (devinfo->widget != NULL) 5033 free(devinfo->widget, M_HDAC); 5034 if (devinfo->node_type == 5035 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO && 5036 devinfo->function.audio.ctl != NULL) 5037 free(devinfo->function.audio.ctl, M_HDAC); 5038 free(devinfo, M_HDAC); 5039 device_delete_child(sc->dev, devlist[i]); 5040 } 5041 if (devlist != NULL) 5042 free(devlist, M_TEMP); 5043 5044 for (i = 0; i < HDAC_CODEC_MAX; i++) { 5045 if (sc->codecs[i] != NULL) 5046 free(sc->codecs[i], M_HDAC); 5047 sc->codecs[i] = NULL; 5048 } 5049 5050 hdac_dma_free(&sc->rirb_dma); 5051 hdac_dma_free(&sc->corb_dma); 5052 if (sc->play.blkcnt > 0) 5053 hdac_dma_free(&sc->play.bdl_dma); 5054 if (sc->rec.blkcnt > 0) 5055 hdac_dma_free(&sc->rec.bdl_dma); 5056 hdac_irq_free(sc); 5057 hdac_mem_free(sc); 5058 free(sc, M_DEVBUF); 5059 5060} 5061 5062/* This function surely going to make its way into upper level someday. */ 5063static void 5064hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 5065{ 5066 const char *res = NULL; 5067 int i = 0, j, k, len, inv; 5068 5069 if (on != NULL) 5070 *on = 0; 5071 if (off != NULL) 5072 *off = 0; 5073 if (sc == NULL) 5074 return; 5075 if (resource_string_value(device_get_name(sc->dev), 5076 device_get_unit(sc->dev), "config", &res) != 0) 5077 return; 5078 if (!(res != NULL && strlen(res) > 0)) 5079 return; 5080 HDA_BOOTVERBOSE( 5081 device_printf(sc->dev, "HDA_DEBUG: HDA Config:"); 5082 ); 5083 for (;;) { 5084 while (res[i] != '\0' && 5085 (res[i] == ',' || isspace(res[i]) != 0)) 5086 i++; 5087 if (res[i] == '\0') { 5088 HDA_BOOTVERBOSE( 5089 printf("\n"); 5090 ); 5091 return; 5092 } 5093 j = i; 5094 while (res[j] != '\0' && 5095 !(res[j] == ',' || isspace(res[j]) != 0)) 5096 j++; 5097 len = j - i; 5098 if (len > 2 && strncmp(res + i, "no", 2) == 0) 5099 inv = 2; 5100 else 5101 inv = 0; 5102 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 5103 if (strncmp(res + i + inv, 5104 hdac_quirks_tab[k].key, len - inv) != 0) 5105 continue; 5106 if (len - inv != strlen(hdac_quirks_tab[k].key)) 5107 break; 5108 HDA_BOOTVERBOSE( 5109 printf(" %s%s", (inv != 0) ? "no" : "", 5110 hdac_quirks_tab[k].key); 5111 ); 5112 if (inv == 0 && on != NULL) 5113 *on |= hdac_quirks_tab[k].value; 5114 else if (inv != 0 && off != NULL) 5115 *off |= hdac_quirks_tab[k].value; 5116 break; 5117 } 5118 i = j; 5119 } 5120} 5121 5122#ifdef SND_DYNSYSCTL 5123static int 5124sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 5125{ 5126 struct hdac_softc *sc; 5127 struct hdac_devinfo *devinfo; 5128 device_t dev; 5129 uint32_t ctl; 5130 int err, val; 5131 5132 dev = oidp->oid_arg1; 5133 devinfo = pcm_getdevinfo(dev); 5134 if (devinfo == NULL || devinfo->codec == NULL || 5135 devinfo->codec->sc == NULL) 5136 return (EINVAL); 5137 sc = devinfo->codec->sc; 5138 hdac_lock(sc); 5139 val = sc->polling; 5140 hdac_unlock(sc); 5141 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 5142 5143 if (err || req->newptr == NULL) 5144 return (err); 5145 if (val < 0 || val > 1) 5146 return (EINVAL); 5147 5148 hdac_lock(sc); 5149 if (val != sc->polling) { 5150 if (hda_chan_active(sc) != 0) 5151 err = EBUSY; 5152 else if (val == 0) { 5153 callout_stop(&sc->poll_hdac); 5154 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 5155 sc->rirb_size / 2); 5156 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5157 ctl |= HDAC_RIRBCTL_RINTCTL; 5158 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5159 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5160 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5161 sc->polling = 0; 5162 DELAY(1000); 5163 } else { 5164 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0); 5165 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0); 5166 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 5167 ctl &= ~HDAC_RIRBCTL_RINTCTL; 5168 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl); 5169 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, 5170 sc); 5171 sc->polling = 1; 5172 DELAY(1000); 5173 } 5174 } 5175 hdac_unlock(sc); 5176 5177 return (err); 5178} 5179#endif 5180 5181static void 5182hdac_attach2(void *arg) 5183{ 5184 struct hdac_softc *sc; 5185 struct hdac_widget *w; 5186 struct hdac_audio_ctl *ctl; 5187 uint32_t quirks_on, quirks_off; 5188 int pcnt, rcnt; 5189 int i; 5190 char status[SND_STATUSLEN]; 5191 device_t *devlist = NULL; 5192 int devcount; 5193 struct hdac_devinfo *devinfo = NULL; 5194 5195 sc = (struct hdac_softc *)arg; 5196 5197 hdac_config_fetch(sc, &quirks_on, &quirks_off); 5198 5199 HDA_BOOTVERBOSE( 5200 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n", 5201 quirks_on, quirks_off); 5202 ); 5203 5204 hdac_lock(sc); 5205 5206 /* Remove ourselves from the config hooks */ 5207 if (sc->intrhook.ich_func != NULL) { 5208 config_intrhook_disestablish(&sc->intrhook); 5209 sc->intrhook.ich_func = NULL; 5210 } 5211 5212 /* Start the corb and rirb engines */ 5213 HDA_BOOTVERBOSE( 5214 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n"); 5215 ); 5216 hdac_corb_start(sc); 5217 HDA_BOOTVERBOSE( 5218 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n"); 5219 ); 5220 hdac_rirb_start(sc); 5221 5222 HDA_BOOTVERBOSE( 5223 device_printf(sc->dev, 5224 "HDA_DEBUG: Enabling controller interrupt...\n"); 5225 ); 5226 if (sc->polling == 0) 5227 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 5228 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 5229 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 5230 HDAC_GCTL_UNSOL); 5231 5232 DELAY(1000); 5233 5234 HDA_BOOTVERBOSE( 5235 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n"); 5236 ); 5237 hdac_scan_codecs(sc); 5238 5239 device_get_children(sc->dev, &devlist, &devcount); 5240 for (i = 0; devlist != NULL && i < devcount; i++) { 5241 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]); 5242 if (devinfo != NULL && devinfo->node_type == 5243 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 5244 break; 5245 } else 5246 devinfo = NULL; 5247 } 5248 if (devlist != NULL) 5249 free(devlist, M_TEMP); 5250 5251 if (devinfo == NULL) { 5252 hdac_unlock(sc); 5253 device_printf(sc->dev, "Audio Function Group not found!\n"); 5254 hdac_release_resources(sc); 5255 return; 5256 } 5257 5258 HDA_BOOTVERBOSE( 5259 device_printf(sc->dev, 5260 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n", 5261 devinfo->nid, devinfo->codec->cad); 5262 ); 5263 hdac_audio_parse(devinfo); 5264 HDA_BOOTVERBOSE( 5265 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n"); 5266 ); 5267 hdac_audio_ctl_parse(devinfo); 5268 HDA_BOOTVERBOSE( 5269 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n"); 5270 ); 5271 hdac_vendor_patch_parse(devinfo); 5272 if (quirks_on != 0) 5273 devinfo->function.audio.quirks |= quirks_on; 5274 if (quirks_off != 0) 5275 devinfo->function.audio.quirks &= ~quirks_off; 5276 5277 /* XXX Disable all DIGITAL path. */ 5278 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5279 w = hdac_widget_get(devinfo, i); 5280 if (w == NULL) 5281 continue; 5282 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 5283 w->enable = 0; 5284 continue; 5285 } 5286 /* XXX Disable useless pin ? */ 5287 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5288 (w->wclass.pin.config & 5289 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5290 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 5291 w->enable = 0; 5292 } 5293 i = 0; 5294 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5295 if (ctl->widget == NULL) 5296 continue; 5297 w = ctl->widget; 5298 if (w->enable == 0) 5299 ctl->enable = 0; 5300 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5301 ctl->enable = 0; 5302 w = ctl->childwidget; 5303 if (w == NULL) 5304 continue; 5305 if (w->enable == 0 || 5306 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 5307 ctl->enable = 0; 5308 } 5309 5310 HDA_BOOTVERBOSE( 5311 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n"); 5312 ); 5313 hdac_audio_build_tree(devinfo); 5314 5315 HDA_BOOTVERBOSE( 5316 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n"); 5317 ); 5318 hdac_audio_commit(devinfo, HDA_COMMIT_ALL); 5319 HDA_BOOTVERBOSE( 5320 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n"); 5321 ); 5322 hdac_audio_ctl_commit(devinfo); 5323 5324 HDA_BOOTVERBOSE( 5325 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n"); 5326 ); 5327 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY); 5328 HDA_BOOTVERBOSE( 5329 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n"); 5330 ); 5331 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC); 5332 5333 hdac_unlock(sc); 5334 HDA_BOOTVERBOSE( 5335 device_printf(sc->dev, 5336 "HDA_DEBUG: OSS mixer initialization...\n"); 5337 ); 5338 5339 /* 5340 * There is no point of return after this. If the driver failed, 5341 * so be it. Let the detach procedure do all the cleanup. 5342 */ 5343 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0) 5344 device_printf(sc->dev, "Can't register mixer\n"); 5345 5346 if (pcnt > 0) 5347 pcnt = 1; 5348 if (rcnt > 0) 5349 rcnt = 1; 5350 5351 HDA_BOOTVERBOSE( 5352 device_printf(sc->dev, 5353 "HDA_DEBUG: Registering PCM channels...\n"); 5354 ); 5355 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0) 5356 device_printf(sc->dev, "Can't register PCM\n"); 5357 5358 sc->registered++; 5359 5360 for (i = 0; i < pcnt; i++) 5361 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo); 5362 for (i = 0; i < rcnt; i++) 5363 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo); 5364 5365#ifdef SND_DYNSYSCTL 5366 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5367 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 5368 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 5369 sysctl_hdac_polling, "I", "Enable polling mode"); 5370#endif 5371 5372 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]", 5373 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res), 5374 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV); 5375 pcm_setstatus(sc->dev, status); 5376 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo)); 5377 HDA_BOOTVERBOSE( 5378 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n", 5379 hdac_codec_id(devinfo)); 5380 ); 5381 device_printf(sc->dev, "<HDA Driver Revision: %s>\n", 5382 HDA_DRV_TEST_REV); 5383 5384 HDA_BOOTVERBOSE( 5385 if (devinfo->function.audio.quirks != 0) { 5386 device_printf(sc->dev, "\n"); 5387 device_printf(sc->dev, "HDA config/quirks:"); 5388 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 5389 if (devinfo->function.audio.quirks & 5390 hdac_quirks_tab[i].value) 5391 printf(" %s", hdac_quirks_tab[i].key); 5392 } 5393 printf("\n"); 5394 } 5395 device_printf(sc->dev, "\n"); 5396 device_printf(sc->dev, "+-------------------+\n"); 5397 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 5398 device_printf(sc->dev, "+-------------------+\n"); 5399 hdac_dump_nodes(devinfo); 5400 device_printf(sc->dev, "\n"); 5401 device_printf(sc->dev, "+------------------------+\n"); 5402 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 5403 device_printf(sc->dev, "+------------------------+\n"); 5404 device_printf(sc->dev, "\n"); 5405 i = 0; 5406 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5407 device_printf(sc->dev, "%3d: nid=%d", i, 5408 (ctl->widget != NULL) ? ctl->widget->nid : -1); 5409 if (ctl->childwidget != NULL) 5410 printf(" cnid=%d", ctl->childwidget->nid); 5411 printf(" dir=0x%x index=%d " 5412 "ossmask=0x%08x ossdev=%d%s\n", 5413 ctl->dir, ctl->index, 5414 ctl->ossmask, ctl->ossdev, 5415 (ctl->enable == 0) ? " [DISABLED]" : ""); 5416 } 5417 device_printf(sc->dev, "\n"); 5418 device_printf(sc->dev, "+-----------------------------------+\n"); 5419 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n"); 5420 device_printf(sc->dev, "+-----------------------------------+\n"); 5421 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME); 5422 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM); 5423 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD); 5424 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC); 5425 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE); 5426 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV); 5427 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER); 5428 hdac_dump_ctls(devinfo, NULL, 0); 5429 hdac_dump_dac(devinfo); 5430 hdac_dump_adc(devinfo); 5431 device_printf(sc->dev, "\n"); 5432 device_printf(sc->dev, "+--------------------------------------+\n"); 5433 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n"); 5434 device_printf(sc->dev, "+--------------------------------------+\n"); 5435 hdac_dump_pcmchannels(sc, pcnt, rcnt); 5436 ); 5437 5438 if (sc->polling != 0) { 5439 hdac_lock(sc); 5440 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 5441 hdac_unlock(sc); 5442 } 5443} 5444 5445/**************************************************************************** 5446 * int hdac_detach(device_t) 5447 * 5448 * Detach and free up resources utilized by the hdac device. 5449 ****************************************************************************/ 5450static int 5451hdac_detach(device_t dev) 5452{ 5453 struct hdac_softc *sc = NULL; 5454 struct hdac_devinfo *devinfo = NULL; 5455 int err; 5456 5457 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev); 5458 if (devinfo != NULL && devinfo->codec != NULL) 5459 sc = devinfo->codec->sc; 5460 if (sc == NULL) 5461 return (0); 5462 5463 if (sc->registered > 0) { 5464 err = pcm_unregister(dev); 5465 if (err != 0) 5466 return (err); 5467 } 5468 5469 hdac_release_resources(sc); 5470 5471 return (0); 5472} 5473 5474static device_method_t hdac_methods[] = { 5475 /* device interface */ 5476 DEVMETHOD(device_probe, hdac_probe), 5477 DEVMETHOD(device_attach, hdac_attach), 5478 DEVMETHOD(device_detach, hdac_detach), 5479 { 0, 0 } 5480}; 5481 5482static driver_t hdac_driver = { 5483 "pcm", 5484 hdac_methods, 5485 PCM_SOFTC_SIZE, 5486}; 5487 5488DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0); 5489MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 5490MODULE_VERSION(snd_hda, 1); 5491