cmi.c revision 166904
1/*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * This driver exists largely as a result of other people's efforts. 27 * Much of register handling is based on NetBSD CMI8x38 audio driver 28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30 * registers and the 8738 mixer devices. His Linux driver was also a 31 * useful reference point. 32 * 33 * TODO: MIDI 34 * 35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36 * 37 * This card/code does not always manage to sample at 44100 - actual 38 * rate drifts slightly between recordings (usually 0-3%). No 39 * differences visible in register dumps between times that work and 40 * those that don't. 41 */ 42 43#include <dev/sound/pcm/sound.h> 44#include <dev/sound/pci/cmireg.h> 45#include <dev/sound/isa/sb.h> 46 47#include <dev/pci/pcireg.h> 48#include <dev/pci/pcivar.h> 49 50#include <sys/sysctl.h> 51#include <dev/sound/midi/mpu401.h> 52 53#include "mixer_if.h" 54#include "mpufoi_if.h" 55 56SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cmi.c 166904 2007-02-23 13:47:34Z netchild $"); 57 58/* Supported chip ID's */ 59#define CMI8338A_PCI_ID 0x010013f6 60#define CMI8338B_PCI_ID 0x010113f6 61#define CMI8738_PCI_ID 0x011113f6 62#define CMI8738B_PCI_ID 0x011213f6 63 64/* Buffer size max is 64k for permitted DMA boundaries */ 65#define CMI_DEFAULT_BUFSZ 16384 66 67/* Interrupts per length of buffer */ 68#define CMI_INTR_PER_BUFFER 2 69 70/* Clarify meaning of named defines in cmireg.h */ 71#define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 72#define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 73#define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 74#define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 75 76/* Our indication of custom mixer control */ 77#define CMPCI_NON_SB16_CONTROL 0xff 78 79/* Debugging macro's */ 80#undef DEB 81#ifndef DEB 82#define DEB(x) /* x */ 83#endif /* DEB */ 84 85#ifndef DEBMIX 86#define DEBMIX(x) /* x */ 87#endif /* DEBMIX */ 88 89/* ------------------------------------------------------------------------- */ 90/* Structures */ 91 92struct sc_info; 93 94struct sc_chinfo { 95 struct sc_info *parent; 96 struct pcm_channel *channel; 97 struct snd_dbuf *buffer; 98 u_int32_t fmt, spd, phys_buf, bps; 99 u_int32_t dma_active:1, dma_was_active:1; 100 int dir; 101}; 102 103struct sc_info { 104 device_t dev; 105 106 bus_space_tag_t st; 107 bus_space_handle_t sh; 108 bus_dma_tag_t parent_dmat; 109 struct resource *reg, *irq; 110 int regid, irqid; 111 void *ih; 112 struct mtx *lock; 113 114 int spdif_enabled; 115 unsigned int bufsz; 116 struct sc_chinfo pch, rch; 117 118 struct mpu401 *mpu; 119 mpu401_intr_t *mpu_intr; 120 struct resource *mpu_reg; 121 int mpu_regid; 122 bus_space_tag_t mpu_bt; 123 bus_space_handle_t mpu_bh; 124}; 125 126/* Channel caps */ 127 128static u_int32_t cmi_fmt[] = { 129 AFMT_U8, 130 AFMT_STEREO | AFMT_U8, 131 AFMT_S16_LE, 132 AFMT_STEREO | AFMT_S16_LE, 133 0 134}; 135 136static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 137 138/* ------------------------------------------------------------------------- */ 139/* Register Utilities */ 140 141static u_int32_t 142cmi_rd(struct sc_info *sc, int regno, int size) 143{ 144 switch (size) { 145 case 1: 146 return bus_space_read_1(sc->st, sc->sh, regno); 147 case 2: 148 return bus_space_read_2(sc->st, sc->sh, regno); 149 case 4: 150 return bus_space_read_4(sc->st, sc->sh, regno); 151 default: 152 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 153 return 0xFFFFFFFF; 154 } 155} 156 157static void 158cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 159{ 160 switch (size) { 161 case 1: 162 bus_space_write_1(sc->st, sc->sh, regno, data); 163 break; 164 case 2: 165 bus_space_write_2(sc->st, sc->sh, regno, data); 166 break; 167 case 4: 168 bus_space_write_4(sc->st, sc->sh, regno, data); 169 break; 170 } 171} 172 173static void 174cmi_partial_wr4(struct sc_info *sc, 175 int reg, int shift, u_int32_t mask, u_int32_t val) 176{ 177 u_int32_t r; 178 179 r = cmi_rd(sc, reg, 4); 180 r &= ~(mask << shift); 181 r |= val << shift; 182 cmi_wr(sc, reg, r, 4); 183} 184 185static void 186cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 187{ 188 u_int32_t r; 189 190 r = cmi_rd(sc, reg, 4); 191 r &= ~mask; 192 cmi_wr(sc, reg, r, 4); 193} 194 195static void 196cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 197{ 198 u_int32_t r; 199 200 r = cmi_rd(sc, reg, 4); 201 r |= mask; 202 cmi_wr(sc, reg, r, 4); 203} 204 205/* ------------------------------------------------------------------------- */ 206/* Rate Mapping */ 207 208static int cmi_rates[] = {5512, 8000, 11025, 16000, 209 22050, 32000, 44100, 48000}; 210#define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 211 212/* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 213 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 214 215static u_int32_t 216cmpci_rate_to_regvalue(int rate) 217{ 218 int i, r; 219 220 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 221 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 222 break; 223 } 224 } 225 226 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 227 228 r = ((i >> 1) | (i << 2)) & 0x07; 229 return r; 230} 231 232static int 233cmpci_regvalue_to_rate(u_int32_t r) 234{ 235 int i; 236 237 i = ((r << 1) | (r >> 2)) & 0x07; 238 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 239 return cmi_rates[i]; 240} 241 242/* ------------------------------------------------------------------------- */ 243/* ADC/DAC control - there are 2 dma channels on 8738, either can be 244 * playback or capture. We use ch0 for playback and ch1 for capture. */ 245 246static void 247cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 248{ 249 u_int32_t s, i, sz; 250 251 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 252 253 cmi_wr(sc, base, ch->phys_buf, 4); 254 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 255 256 s = sz / ch->bps - 1; 257 cmi_wr(sc, base + 4, s, 2); 258 259 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 260 cmi_wr(sc, base + 6, i, 2); 261} 262 263 264static void 265cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 266{ 267 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 268 269 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 270 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 271 CMPCI_REG_CH0_INTR_ENABLE); 272 273 ch->dma_active = 1; 274} 275 276static u_int32_t 277cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 278{ 279 u_int32_t r = ch->dma_active; 280 281 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 282 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 283 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 284 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 285 ch->dma_active = 0; 286 return r; 287} 288 289static void 290cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 291{ 292 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 293 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 294 /* Enable Interrupts */ 295 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 296 CMPCI_REG_CH1_INTR_ENABLE); 297 DEB(printf("cmi_ch1_start: dma prog\n")); 298 ch->dma_active = 1; 299} 300 301static u_int32_t 302cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 303{ 304 u_int32_t r = ch->dma_active; 305 306 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 307 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 308 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 309 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 310 ch->dma_active = 0; 311 return r; 312} 313 314static void 315cmi_spdif_speed(struct sc_info *sc, int speed) { 316 u_int32_t fcr1, lcr, mcr; 317 318 if (speed >= 44100) { 319 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 320 lcr = CMPCI_REG_XSPDIF_ENABLE; 321 mcr = (speed == 48000) ? 322 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 323 } else { 324 fcr1 = mcr = lcr = 0; 325 } 326 327 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 328 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 329 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 330 CMPCI_REG_SPDIF0_ENABLE, fcr1); 331 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 332 CMPCI_REG_XSPDIF_ENABLE, lcr); 333} 334 335/* ------------------------------------------------------------------------- */ 336/* Channel Interface implementation */ 337 338static void * 339cmichan_init(kobj_t obj, void *devinfo, 340 struct snd_dbuf *b, struct pcm_channel *c, int dir) 341{ 342 struct sc_info *sc = devinfo; 343 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 344 345 ch->parent = sc; 346 ch->channel = c; 347 ch->bps = 1; 348 ch->fmt = AFMT_U8; 349 ch->spd = DSP_DEFAULT_SPEED; 350 ch->buffer = b; 351 ch->dma_active = 0; 352 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 353 DEB(printf("cmichan_init failed\n")); 354 return NULL; 355 } 356 357 ch->dir = dir; 358 snd_mtxlock(sc->lock); 359 if (ch->dir == PCMDIR_PLAY) { 360 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 361 } else { 362 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 363 } 364 snd_mtxunlock(sc->lock); 365 366 return ch; 367} 368 369static int 370cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 371{ 372 struct sc_chinfo *ch = data; 373 struct sc_info *sc = ch->parent; 374 u_int32_t f; 375 376 if (format & AFMT_S16_LE) { 377 f = CMPCI_REG_FORMAT_16BIT; 378 ch->bps = 2; 379 } else { 380 f = CMPCI_REG_FORMAT_8BIT; 381 ch->bps = 1; 382 } 383 384 if (format & AFMT_STEREO) { 385 f |= CMPCI_REG_FORMAT_STEREO; 386 ch->bps *= 2; 387 } else { 388 f |= CMPCI_REG_FORMAT_MONO; 389 } 390 391 snd_mtxlock(sc->lock); 392 if (ch->dir == PCMDIR_PLAY) { 393 cmi_partial_wr4(ch->parent, 394 CMPCI_REG_CHANNEL_FORMAT, 395 CMPCI_REG_CH0_FORMAT_SHIFT, 396 CMPCI_REG_CH0_FORMAT_MASK, 397 f); 398 } else { 399 cmi_partial_wr4(ch->parent, 400 CMPCI_REG_CHANNEL_FORMAT, 401 CMPCI_REG_CH1_FORMAT_SHIFT, 402 CMPCI_REG_CH1_FORMAT_MASK, 403 f); 404 } 405 snd_mtxunlock(sc->lock); 406 ch->fmt = format; 407 408 return 0; 409} 410 411static int 412cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 413{ 414 struct sc_chinfo *ch = data; 415 struct sc_info *sc = ch->parent; 416 u_int32_t r, rsp; 417 418 r = cmpci_rate_to_regvalue(speed); 419 snd_mtxlock(sc->lock); 420 if (ch->dir == PCMDIR_PLAY) { 421 if (speed < 44100) { 422 /* disable if req before rate change */ 423 cmi_spdif_speed(ch->parent, speed); 424 } 425 cmi_partial_wr4(ch->parent, 426 CMPCI_REG_FUNC_1, 427 CMPCI_REG_DAC_FS_SHIFT, 428 CMPCI_REG_DAC_FS_MASK, 429 r); 430 if (speed >= 44100 && ch->parent->spdif_enabled) { 431 /* enable if req after rate change */ 432 cmi_spdif_speed(ch->parent, speed); 433 } 434 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 435 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 436 rsp &= CMPCI_REG_DAC_FS_MASK; 437 } else { 438 cmi_partial_wr4(ch->parent, 439 CMPCI_REG_FUNC_1, 440 CMPCI_REG_ADC_FS_SHIFT, 441 CMPCI_REG_ADC_FS_MASK, 442 r); 443 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 444 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 445 rsp &= CMPCI_REG_ADC_FS_MASK; 446 } 447 snd_mtxunlock(sc->lock); 448 ch->spd = cmpci_regvalue_to_rate(r); 449 450 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 451 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 452 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 453 454 return ch->spd; 455} 456 457static int 458cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 459{ 460 struct sc_chinfo *ch = data; 461 struct sc_info *sc = ch->parent; 462 463 /* user has requested interrupts every blocksize bytes */ 464 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 465 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 466 } 467 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 468 469 return blocksize; 470} 471 472static int 473cmichan_trigger(kobj_t obj, void *data, int go) 474{ 475 struct sc_chinfo *ch = data; 476 struct sc_info *sc = ch->parent; 477 478 snd_mtxlock(sc->lock); 479 if (ch->dir == PCMDIR_PLAY) { 480 switch(go) { 481 case PCMTRIG_START: 482 cmi_ch0_start(sc, ch); 483 break; 484 case PCMTRIG_ABORT: 485 cmi_ch0_stop(sc, ch); 486 break; 487 } 488 } else { 489 switch(go) { 490 case PCMTRIG_START: 491 cmi_ch1_start(sc, ch); 492 break; 493 case PCMTRIG_ABORT: 494 cmi_ch1_stop(sc, ch); 495 break; 496 } 497 } 498 snd_mtxunlock(sc->lock); 499 return 0; 500} 501 502static int 503cmichan_getptr(kobj_t obj, void *data) 504{ 505 struct sc_chinfo *ch = data; 506 struct sc_info *sc = ch->parent; 507 u_int32_t physptr, bufptr, sz; 508 509 snd_mtxlock(sc->lock); 510 if (ch->dir == PCMDIR_PLAY) { 511 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 512 } else { 513 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 514 } 515 snd_mtxunlock(sc->lock); 516 517 sz = sndbuf_getsize(ch->buffer); 518 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 519 520 return bufptr; 521} 522 523static void 524cmi_intr(void *data) 525{ 526 struct sc_info *sc = data; 527 u_int32_t intrstat; 528 u_int32_t toclear; 529 530 snd_mtxlock(sc->lock); 531 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 532 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 533 534 toclear = 0; 535 if (intrstat & CMPCI_REG_CH0_INTR) { 536 toclear |= CMPCI_REG_CH0_INTR_ENABLE; 537 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 538 } 539 540 if (intrstat & CMPCI_REG_CH1_INTR) { 541 toclear |= CMPCI_REG_CH1_INTR_ENABLE; 542 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 543 } 544 545 if (toclear) { 546 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 547 snd_mtxunlock(sc->lock); 548 549 /* Signal interrupts to channel */ 550 if (intrstat & CMPCI_REG_CH0_INTR) { 551 chn_intr(sc->pch.channel); 552 } 553 554 if (intrstat & CMPCI_REG_CH1_INTR) { 555 chn_intr(sc->rch.channel); 556 } 557 558 snd_mtxlock(sc->lock); 559 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 560 561 } 562 } 563 if(sc->mpu_intr) { 564 (sc->mpu_intr)(sc->mpu); 565 } 566 snd_mtxunlock(sc->lock); 567 return; 568} 569 570static struct pcmchan_caps * 571cmichan_getcaps(kobj_t obj, void *data) 572{ 573 return &cmi_caps; 574} 575 576static kobj_method_t cmichan_methods[] = { 577 KOBJMETHOD(channel_init, cmichan_init), 578 KOBJMETHOD(channel_setformat, cmichan_setformat), 579 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 580 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 581 KOBJMETHOD(channel_trigger, cmichan_trigger), 582 KOBJMETHOD(channel_getptr, cmichan_getptr), 583 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 584 { 0, 0 } 585}; 586CHANNEL_DECLARE(cmichan); 587 588/* ------------------------------------------------------------------------- */ 589/* Mixer - sb16 with kinks */ 590 591static void 592cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 593{ 594 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 595 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 596} 597 598static u_int8_t 599cmimix_rd(struct sc_info *sc, u_int8_t port) 600{ 601 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 602 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 603} 604 605struct sb16props { 606 u_int8_t rreg; /* right reg chan register */ 607 u_int8_t stereo:1; /* (no explanation needed, honest) */ 608 u_int8_t rec:1; /* recording source */ 609 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 610 u_int8_t oselect; /* output select mask */ 611 u_int8_t iselect; /* right input select mask */ 612} static const cmt[SOUND_MIXER_NRDEVICES] = { 613 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 614 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 615 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 616 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 617 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 618 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 619 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 620 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 621 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 622 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 623 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 624 /* These controls are not implemented in CMI8738, but maybe at a 625 future date. They are not documented in C-Media documentation, 626 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 627 */ 628 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 629 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 630 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 631 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 632 /* The mic pre-amp is implemented with non-SB16 compatible 633 registers. */ 634 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 635}; 636 637#define MIXER_GAIN_REG_RTOL(r) (r - 1) 638 639static int 640cmimix_init(struct snd_mixer *m) 641{ 642 struct sc_info *sc = mix_getdevinfo(m); 643 u_int32_t i,v; 644 645 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 646 if (cmt[i].bits) v |= 1 << i; 647 } 648 mix_setdevs(m, v); 649 650 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 651 if (cmt[i].rec) v |= 1 << i; 652 } 653 mix_setrecdevs(m, v); 654 655 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 656 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 657 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 658 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 659 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 660 return 0; 661} 662 663static int 664cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 665{ 666 struct sc_info *sc = mix_getdevinfo(m); 667 u_int32_t r, l, max; 668 u_int8_t v; 669 670 max = (1 << cmt[dev].bits) - 1; 671 672 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 673 /* For time being this can only be one thing (mic in 674 * mic/aux reg) */ 675 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 676 l = left * max / 100; 677 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 678 v |= ((l << 1) | (~l >> 3)) & 0x0f; 679 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 680 return 0; 681 } 682 683 l = (left * max / 100) << (8 - cmt[dev].bits); 684 if (cmt[dev].stereo) { 685 r = (right * max / 100) << (8 - cmt[dev].bits); 686 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 687 cmimix_wr(sc, cmt[dev].rreg, r); 688 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 689 "value 0x%02x:0x%02x\n", 690 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 691 } else { 692 r = l; 693 cmimix_wr(sc, cmt[dev].rreg, l); 694 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 695 "value 0x%02x:0x%02x\n", 696 dev, cmt[dev].rreg, l, l)); 697 } 698 699 /* Zero gain does not mute channel from output, but this does... */ 700 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 701 if (l == 0 && r == 0) { 702 v &= ~cmt[dev].oselect; 703 } else { 704 v |= cmt[dev].oselect; 705 } 706 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 707 708 return 0; 709} 710 711static int 712cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 713{ 714 struct sc_info *sc = mix_getdevinfo(m); 715 u_int32_t i, ml, sl; 716 717 ml = sl = 0; 718 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 719 if ((1<<i) & src) { 720 if (cmt[i].stereo) { 721 sl |= cmt[i].iselect; 722 } else { 723 ml |= cmt[i].iselect; 724 } 725 } 726 } 727 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 728 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 729 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 730 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 731 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 732 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 733 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 734 735 return src; 736} 737 738/* Optional SPDIF support. */ 739 740static int 741cmi_initsys(struct sc_info* sc) 742{ 743#ifdef SND_DYNSYSCTL 744 /* XXX: an user should be able to set this with a control tool, 745 if not done before 7.0-RELEASE, this needs to be converted 746 to a device specific sysctl "dev.pcm.X.yyy" via 747 device_get_sysctl_*() as discussed on multimedia@ in msg-id 748 <861wujij2q.fsf@xps.des.no> */ 749 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 750 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 751 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 752 &sc->spdif_enabled, 0, 753 "enable SPDIF output at 44.1 kHz and above"); 754#endif /* SND_DYNSYSCTL */ 755 return 0; 756} 757 758/* ------------------------------------------------------------------------- */ 759static kobj_method_t cmi_mixer_methods[] = { 760 KOBJMETHOD(mixer_init, cmimix_init), 761 KOBJMETHOD(mixer_set, cmimix_set), 762 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 763 { 0, 0 } 764}; 765MIXER_DECLARE(cmi_mixer); 766 767/* 768 * mpu401 functions 769 */ 770 771static unsigned char 772cmi_mread(void *arg, struct sc_info *sc, int reg) 773{ 774 unsigned int d; 775 776 d = bus_space_read_1(0,0, 0x330 + reg); 777 /* printf("cmi_mread: reg %x %x\n",reg, d); 778 */ 779 return d; 780} 781 782static void 783cmi_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b) 784{ 785 786 bus_space_write_1(0,0,0x330 + reg , b); 787} 788 789static int 790cmi_muninit(void *arg, struct sc_info *sc) 791{ 792 793 snd_mtxlock(sc->lock); 794 sc->mpu_intr = 0; 795 sc->mpu = 0; 796 snd_mtxunlock(sc->lock); 797 798 return 0; 799} 800 801static kobj_method_t cmi_mpu_methods[] = { 802 KOBJMETHOD(mpufoi_read, cmi_mread), 803 KOBJMETHOD(mpufoi_write, cmi_mwrite), 804 KOBJMETHOD(mpufoi_uninit, cmi_muninit), 805 { 0, 0 } 806}; 807 808static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0); 809 810static void 811cmi_midiattach(struct sc_info *sc) { 812/* 813 const struct { 814 int port,bits; 815 } *p, ports[] = { 816 {0x330,0}, 817 {0x320,1}, 818 {0x310,2}, 819 {0x300,3}, 820 {0,0} } ; 821 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does 822 anyone know how to bus_space tag? 823*/ 824 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 825 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL, 826 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT); 827 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL, 828 0 << CMPCI_REG_VMPUSEL_SHIFT ); 829 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 830 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr); 831} 832 833 834 835/* ------------------------------------------------------------------------- */ 836/* Power and reset */ 837 838static void 839cmi_power(struct sc_info *sc, int state) 840{ 841 switch (state) { 842 case 0: /* full power */ 843 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 844 break; 845 default: 846 /* power off */ 847 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 848 break; 849 } 850} 851 852static int 853cmi_init(struct sc_info *sc) 854{ 855 /* Effect reset */ 856 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 857 DELAY(100); 858 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 859 860 /* Disable interrupts and channels */ 861 cmi_clr4(sc, CMPCI_REG_FUNC_0, 862 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 863 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 864 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 865 866 /* Configure DMA channels, ch0 = play, ch1 = capture */ 867 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 868 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 869 870 /* Attempt to enable 4 Channel output */ 871 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 872 873 /* Disable SPDIF1 - not compatible with config */ 874 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 875 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 876 877 return 0; 878} 879 880static void 881cmi_uninit(struct sc_info *sc) 882{ 883 /* Disable interrupts and channels */ 884 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 885 CMPCI_REG_CH0_INTR_ENABLE | 886 CMPCI_REG_CH1_INTR_ENABLE | 887 CMPCI_REG_TDMA_INTR_ENABLE); 888 cmi_clr4(sc, CMPCI_REG_FUNC_0, 889 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 890 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 891 892 if( sc->mpu ) 893 sc->mpu_intr = 0; 894} 895 896/* ------------------------------------------------------------------------- */ 897/* Bus and device registration */ 898static int 899cmi_probe(device_t dev) 900{ 901 switch(pci_get_devid(dev)) { 902 case CMI8338A_PCI_ID: 903 device_set_desc(dev, "CMedia CMI8338A"); 904 return BUS_PROBE_DEFAULT; 905 case CMI8338B_PCI_ID: 906 device_set_desc(dev, "CMedia CMI8338B"); 907 return BUS_PROBE_DEFAULT; 908 case CMI8738_PCI_ID: 909 device_set_desc(dev, "CMedia CMI8738"); 910 return BUS_PROBE_DEFAULT; 911 case CMI8738B_PCI_ID: 912 device_set_desc(dev, "CMedia CMI8738B"); 913 return BUS_PROBE_DEFAULT; 914 default: 915 return ENXIO; 916 } 917} 918 919static int 920cmi_attach(device_t dev) 921{ 922 struct sc_info *sc; 923 u_int32_t data; 924 char status[SND_STATUSLEN]; 925 926 sc = malloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO); 927 if (sc == NULL) { 928 device_printf(dev, "cannot allocate softc\n"); 929 return ENXIO; 930 } 931 932 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 933 data = pci_read_config(dev, PCIR_COMMAND, 2); 934 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 935 pci_write_config(dev, PCIR_COMMAND, data, 2); 936 data = pci_read_config(dev, PCIR_COMMAND, 2); 937 938 sc->dev = dev; 939 sc->regid = PCIR_BAR(0); 940 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 941 RF_ACTIVE); 942 if (!sc->reg) { 943 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 944 goto bad; 945 } 946 sc->st = rman_get_bustag(sc->reg); 947 sc->sh = rman_get_bushandle(sc->reg); 948 949 cmi_midiattach(sc); 950 951 sc->irqid = 0; 952 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 953 RF_ACTIVE | RF_SHAREABLE); 954 if (!sc->irq || 955 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 956 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 957 goto bad; 958 } 959 960 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 961 962 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 963 /*boundary*/0, 964 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 965 /*highaddr*/BUS_SPACE_MAXADDR, 966 /*filter*/NULL, /*filterarg*/NULL, 967 /*maxsize*/sc->bufsz, /*nsegments*/1, 968 /*maxsegz*/0x3ffff, /*flags*/0, 969 /*lockfunc*/NULL, 970 /*lockfunc*/NULL, 971 &sc->parent_dmat) != 0) { 972 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 973 goto bad; 974 } 975 976 cmi_power(sc, 0); 977 if (cmi_init(sc)) 978 goto bad; 979 980 if (mixer_init(dev, &cmi_mixer_class, sc)) 981 goto bad; 982 983 if (pcm_register(dev, sc, 1, 1)) 984 goto bad; 985 986 cmi_initsys(sc); 987 988 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 989 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 990 991 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 992 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 993 pcm_setstatus(dev, status); 994 995 DEB(printf("cmi_attach: succeeded\n")); 996 return 0; 997 998 bad: 999 if (sc->parent_dmat) 1000 bus_dma_tag_destroy(sc->parent_dmat); 1001 if (sc->ih) 1002 bus_teardown_intr(dev, sc->irq, sc->ih); 1003 if (sc->irq) 1004 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1005 if (sc->reg) 1006 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1007 if (sc->lock) 1008 snd_mtxfree(sc->lock); 1009 if (sc) 1010 free(sc, M_DEVBUF); 1011 1012 return ENXIO; 1013} 1014 1015static int 1016cmi_detach(device_t dev) 1017{ 1018 struct sc_info *sc; 1019 int r; 1020 1021 r = pcm_unregister(dev); 1022 if (r) return r; 1023 1024 sc = pcm_getdevinfo(dev); 1025 cmi_uninit(sc); 1026 cmi_power(sc, 3); 1027 1028 bus_dma_tag_destroy(sc->parent_dmat); 1029 bus_teardown_intr(dev, sc->irq, sc->ih); 1030 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1031 if(sc->mpu) 1032 mpu401_uninit(sc->mpu); 1033 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1034 if (sc->mpu_reg) 1035 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg); 1036 1037 snd_mtxfree(sc->lock); 1038 free(sc, M_DEVBUF); 1039 1040 return 0; 1041} 1042 1043static int 1044cmi_suspend(device_t dev) 1045{ 1046 struct sc_info *sc = pcm_getdevinfo(dev); 1047 1048 snd_mtxlock(sc->lock); 1049 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 1050 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 1051 cmi_power(sc, 3); 1052 snd_mtxunlock(sc->lock); 1053 return 0; 1054} 1055 1056static int 1057cmi_resume(device_t dev) 1058{ 1059 struct sc_info *sc = pcm_getdevinfo(dev); 1060 1061 snd_mtxlock(sc->lock); 1062 cmi_power(sc, 0); 1063 if (cmi_init(sc) != 0) { 1064 device_printf(dev, "unable to reinitialize the card\n"); 1065 snd_mtxunlock(sc->lock); 1066 return ENXIO; 1067 } 1068 1069 if (mixer_reinit(dev) == -1) { 1070 device_printf(dev, "unable to reinitialize the mixer\n"); 1071 snd_mtxunlock(sc->lock); 1072 return ENXIO; 1073 } 1074 1075 if (sc->pch.dma_was_active) { 1076 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 1077 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 1078 cmi_ch0_start(sc, &sc->pch); 1079 } 1080 1081 if (sc->rch.dma_was_active) { 1082 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 1083 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 1084 cmi_ch1_start(sc, &sc->rch); 1085 } 1086 snd_mtxunlock(sc->lock); 1087 return 0; 1088} 1089 1090static device_method_t cmi_methods[] = { 1091 DEVMETHOD(device_probe, cmi_probe), 1092 DEVMETHOD(device_attach, cmi_attach), 1093 DEVMETHOD(device_detach, cmi_detach), 1094 DEVMETHOD(device_resume, cmi_resume), 1095 DEVMETHOD(device_suspend, cmi_suspend), 1096 { 0, 0 } 1097}; 1098 1099static driver_t cmi_driver = { 1100 "pcm", 1101 cmi_methods, 1102 PCM_SOFTC_SIZE 1103}; 1104 1105DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0); 1106MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1107MODULE_DEPEND(snd_cmi, midi, 1,1,1); 1108MODULE_VERSION(snd_cmi, 1); 1109