aureal.c revision 70134 
1/*
2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/sound/pci/aureal.c 70134 2000-12-18 01:36:41Z cg $
27 */
28
29#include <dev/sound/pcm/sound.h>
30#include <dev/sound/pcm/ac97.h>
31#include <dev/sound/pci/aureal.h>
32
33#include <pci/pcireg.h>
34#include <pci/pcivar.h>
35
36/* PCI IDs of supported chips */
37#define AU8820_PCI_ID 0x000112eb
38
39/* channel interface */
40static u_int32_t au_playfmt[] = {
41	AFMT_U8,
42	AFMT_STEREO | AFMT_U8,
43	AFMT_S16_LE,
44	AFMT_STEREO | AFMT_S16_LE,
45	0
46};
47static pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0};
48
49static u_int32_t au_recfmt[] = {
50	AFMT_U8,
51	AFMT_STEREO | AFMT_U8,
52	AFMT_S16_LE,
53	AFMT_STEREO | AFMT_S16_LE,
54	0
55};
56static pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0};
57
58/* -------------------------------------------------------------------- */
59
60struct au_info;
61
62struct au_chinfo {
63	struct au_info *parent;
64	pcm_channel *channel;
65	snd_dbuf *buffer;
66	int dir;
67};
68
69struct au_info {
70	int unit;
71
72	bus_space_tag_t st[3];
73	bus_space_handle_t sh[3];
74
75	bus_dma_tag_t	parent_dmat;
76
77	u_int32_t	x[32], y[128];
78	char		z[128];
79	u_int32_t	routes[4], interrupts;
80	struct au_chinfo pch;
81};
82
83static int      au_init(device_t dev, struct au_info *au);
84static void     au_intr(void *);
85
86/* -------------------------------------------------------------------- */
87
88static u_int32_t
89au_rd(struct au_info *au, int mapno, int regno, int size)
90{
91	switch(size) {
92	case 1:
93		return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
94	case 2:
95		return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
96	case 4:
97		return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
98	default:
99		return 0xffffffff;
100	}
101}
102
103static void
104au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
105{
106	switch(size) {
107	case 1:
108		bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
109		break;
110	case 2:
111		bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
112		break;
113	case 4:
114		bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
115		break;
116	}
117}
118
119/* -------------------------------------------------------------------- */
120
121static int
122au_rdcd(kobj_t obj, void *arg, int regno)
123{
124	struct au_info *au = (struct au_info *)arg;
125	int i=0, j=0;
126
127	regno<<=16;
128	au_wr(au, 0, AU_REG_CODECIO, regno, 4);
129	while (j<50) {
130		i=au_rd(au, 0, AU_REG_CODECIO, 4);
131		if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
132		DELAY(j * 200 + 2000);
133		j++;
134	}
135	if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n",
136		au->unit, (regno & AU_CDC_REGMASK)>>16, i);
137	return i & AU_CDC_DATAMASK;
138}
139
140static int
141au_wrcd(kobj_t obj, void *arg, int regno, u_int32_t data)
142{
143	struct au_info *au = (struct au_info *)arg;
144	int i, j, tries;
145	i=j=tries=0;
146	do {
147		while (j<50 && (i & AU_CDC_WROK) == 0) {
148			i=au_rd(au, 0, AU_REG_CODECST, 4);
149			DELAY(2000);
150			j++;
151		}
152		if (j==50) printf("codec timeout during write of register %x, data %x\n",
153				  regno, data);
154		au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
155/*		DELAY(20000);
156		i=au_rdcd(au, regno);
157*/		tries++;
158	} while (0); /* (i != data && tries < 3); */
159	/*
160	if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
161	*/
162
163	return 0;
164}
165
166static kobj_method_t au_ac97_methods[] = {
167    	KOBJMETHOD(ac97_read,		au_rdcd),
168    	KOBJMETHOD(ac97_write,		au_wrcd),
169	{ 0, 0 }
170};
171AC97_DECLARE(au_ac97);
172
173/* -------------------------------------------------------------------- */
174
175static void
176au_setbit(u_int32_t *p, char bit, u_int32_t value)
177{
178	p += bit >> 5;
179	bit &= 0x1f;
180	*p &= ~ (1 << bit);
181	*p |= (value << bit);
182}
183
184static void
185au_addroute(struct au_info *au, int a, int b, int route)
186{
187	int j = 0x1099c+(a<<2);
188	if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
189
190	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
191 	au_wr(au, 0, j, route | (b<<7), 4);
192	au->y[route]=au->x[a];
193	au->x[a]=route;
194	au->z[route]=a & 0x000000ff;
195	au_setbit(au->routes, route, 1);
196}
197
198static void
199au_delroute(struct au_info *au, int route)
200{
201	int i;
202	int j=au->z[route];
203
204	au_setbit(au->routes, route, 0);
205	au->z[route]=0x1f;
206	i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
207	au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
208	au->y[i & 0x7f]=au->y[route];
209	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
210	if (au->x[j] == route) au->x[j]=au->y[route];
211	au->y[route]=0x7f;
212}
213
214static void
215au_encodec(struct au_info *au, char channel)
216{
217	au_wr(au, 0, AU_REG_CODECEN,
218	      au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
219}
220
221static void
222au_clrfifo(struct au_info *au, u_int32_t c)
223{
224	u_int32_t i;
225
226	for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
227}
228
229static void
230au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
231{
232	int x;
233
234	x = au_rd(au, 0, AU_REG_ADB, 4);
235	x &= ~(1 << c);
236	x |= (enable << c);
237	au_wr(au, 0, AU_REG_ADB, x, 4);
238}
239
240static void
241au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
242{
243	struct au_info *au = ch->parent;
244	int i, stereo = (format & AFMT_STEREO)? 1 : 0;
245	u_int32_t baseaddr = vtophys(ch->buffer->buf);
246
247	au_wr(au, 0, 0x1061c, 0, 4);
248	au_wr(au, 0, 0x10620, 0, 4);
249	au_wr(au, 0, 0x10624, 0, 4);
250	switch(format & ~AFMT_STEREO) {
251		case 1:
252			i=0xb000;
253			break;
254		case 2:
255			i=0xf000;
256			break;
257 		case 8:
258			i=0x7000;
259			break;
260		case 16:
261			i=0x23000;
262			break;
263		default:
264			i=0x3000;
265	}
266	au_wr(au, 0, 0x10200, baseaddr, 4);
267	au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
268	au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
269	au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
270
271	au_wr(au, 0, 0x10400, 0xdeffffff, 4);
272	au_wr(au, 0, 0x10404, 0xfcffffff, 4);
273
274	au_wr(au, 0, 0x10580, i, 4);
275
276	au_wr(au, 0, 0x10210, baseaddr, 4);
277	au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
278	au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
279	au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
280
281	au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
282	au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
283
284	au_wr(au, 0, 0x10584, i, 4);
285
286	au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
287	au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
288
289	au_addroute(au, 0x11, 0, 0x58);
290	au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
291}
292
293/* -------------------------------------------------------------------- */
294/* channel interface */
295static void *
296auchan_init(kobj_t obj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
297{
298	struct au_info *au = devinfo;
299	struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
300
301	ch->parent = au;
302	ch->channel = c;
303	ch->buffer = b;
304	ch->buffer->bufsize = AU_BUFFSIZE;
305	ch->dir = dir;
306	if (chn_allocbuf(ch->buffer, au->parent_dmat) == -1) return NULL;
307	return ch;
308}
309
310static int
311auchan_setformat(kobj_t obj, void *data, u_int32_t format)
312{
313	struct au_chinfo *ch = data;
314
315	if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
316	return 0;
317}
318
319static int
320auchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
321{
322	struct au_chinfo *ch = data;
323	if (ch->dir == PCMDIR_PLAY) {
324	} else {
325	}
326	return speed;
327}
328
329static int
330auchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
331{
332	return blocksize;
333}
334
335static int
336auchan_trigger(kobj_t obj, void *data, int go)
337{
338	struct au_chinfo *ch = data;
339	struct au_info *au = ch->parent;
340
341	if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
342		return 0;
343
344	if (ch->dir == PCMDIR_PLAY) {
345		au_setadb(au, 0x11, (go)? 1 : 0);
346		if (!go) {
347			au_wr(au, 0, 0xf800, 0, 4);
348			au_wr(au, 0, 0xf804, 0, 4);
349			au_delroute(au, 0x58);
350			au_delroute(au, 0x59);
351		}
352	} else {
353	}
354	return 0;
355}
356
357static int
358auchan_getptr(kobj_t obj, void *data)
359{
360	struct au_chinfo *ch = data;
361	struct au_info *au = ch->parent;
362	if (ch->dir == PCMDIR_PLAY) {
363		return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
364	} else {
365		return 0;
366	}
367}
368
369static pcmchan_caps *
370auchan_getcaps(kobj_t obj, void *data)
371{
372	struct au_chinfo *ch = data;
373	return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
374}
375
376static kobj_method_t auchan_methods[] = {
377    	KOBJMETHOD(channel_init,		auchan_init),
378    	KOBJMETHOD(channel_setformat,		auchan_setformat),
379    	KOBJMETHOD(channel_setspeed,		auchan_setspeed),
380    	KOBJMETHOD(channel_setblocksize,	auchan_setblocksize),
381    	KOBJMETHOD(channel_trigger,		auchan_trigger),
382    	KOBJMETHOD(channel_getptr,		auchan_getptr),
383    	KOBJMETHOD(channel_getcaps,		auchan_getcaps),
384	{ 0, 0 }
385};
386CHANNEL_DECLARE(auchan);
387
388/* -------------------------------------------------------------------- */
389/* The interrupt handler */
390static void
391au_intr (void *p)
392{
393	struct au_info *au = p;
394	u_int32_t	intsrc, i;
395
396	au->interrupts++;
397	intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
398	printf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
399	if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit);
400	if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit);
401	if (intsrc & AU_IRQ_UNKNOWN) {
402		(void)au_rd(au, 0, AU_REG_UNK1, 4);
403		au_wr(au, 0, AU_REG_UNK1, 0, 4);
404		au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
405	}
406	if (intsrc & AU_IRQ_PCMOUT) {
407	       	i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
408	       	chn_intr(au->pch.channel);
409		(void)au_rd(au, 0, AU_REG_UNK3, 4);
410		(void)au_rd(au, 0, AU_REG_UNK4, 4);
411		(void)au_rd(au, 0, AU_REG_UNK5, 4);
412	}
413/* don't support midi
414	if (intsrc & AU_IRQ_MIDI) {
415		i=au_rd(au, 0, 0x11004, 4);
416		j=10;
417		while (i & 0xff) {
418			if (j-- <= 0) break;
419			i=au_rd(au, 0, 0x11000, 4);
420			if ((au->midi_stat & 1) && (au->midi_out))
421				au->midi_out(au->midi_devno, i);
422			i=au_rd(au, 0, 0x11004);
423		}
424	}
425*/
426	au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
427	au_rd(au, 0, AU_REG_IRQSRC, 4);
428}
429
430
431/* -------------------------------------------------------------------- */
432
433/* Probe and attach the card */
434
435static int
436au_init(device_t dev, struct au_info *au)
437{
438	u_int32_t	i, j;
439
440	au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
441	DELAY(100000);
442
443	/* init codec */
444	/* cold reset */
445	for (i=0; i<32; i++) {
446		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
447		DELAY(10000);
448	}
449	if (1) {
450		au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
451		DELAY(10000);
452		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
453		DELAY(10000);
454	} else {
455		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
456 		DELAY(100000);
457		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
458		DELAY(100000);
459		au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
460		DELAY(100000);
461		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
462		DELAY(100000);
463		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
464		DELAY(100000);
465		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
466		DELAY(100000);
467	}
468
469	/* init */
470	for (i=0; i<32; i++) {
471		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
472		DELAY(10000);
473	}
474	au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
475	DELAY(10000);
476	au_wr(au, 0, AU_REG_CODECEN, 0, 4);
477
478	/* setup codec */
479	i=j=0;
480	while (j<100 && (i & AU_CDC_READY)==0) {
481		i=au_rd(au, 0, AU_REG_CODECST, 4);
482		DELAY(1000);
483		j++;
484	}
485	if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
486
487   	/* init adb */
488	/*au->x5c=0;*/
489	for (i=0; i<32;  i++) au->x[i]=i+0x67;
490	for (i=0; i<128; i++) au->y[i]=0x7f;
491	for (i=0; i<128; i++) au->z[i]=0x1f;
492	au_wr(au, 0, AU_REG_ADB, 0, 4);
493	for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
494
495	/* test */
496	i=au_rd(au, 0, 0x107c0, 4);
497 	if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
498
499	/* install mixer */
500	au_wr(au, 0, AU_REG_IRQGLOB,
501	      au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
502	/* braindead but it's what the oss/linux driver does
503	 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
504	 */
505	au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
506	/*au->x1e4=0;*/
507
508	/* attach channel */
509	au_addroute(au, 0x11, 0x48, 0x02);
510	au_addroute(au, 0x11, 0x49, 0x03);
511	au_encodec(au, 0);
512	au_encodec(au, 1);
513
514	for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
515	for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
516	au_wr(au, 0, 0xf8c0, 0x0843, 4);
517	for (i=0; i<4; i++) au_clrfifo(au, i);
518
519	return (0);
520}
521
522static int
523au_testirq(struct au_info *au)
524{
525	au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
526	au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
527	au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
528	DELAY(1000000);
529	if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit);
530	/* this apparently generates an irq */
531	return 0;
532}
533
534static int
535au_pci_probe(device_t dev)
536{
537	if (pci_get_devid(dev) == AU8820_PCI_ID) {
538		device_set_desc(dev, "Aureal Vortex 8820");
539		return 0;
540	}
541
542	return ENXIO;
543}
544
545static int
546au_pci_attach(device_t dev)
547{
548	u_int32_t	data;
549	struct au_info *au;
550	int		type[10];
551	int		regid[10];
552	struct resource *reg[10];
553	int		i, j, mapped = 0;
554	int		irqid;
555	struct resource *irq = 0;
556	void		*ih = 0;
557	struct ac97_info *codec;
558	char 		status[SND_STATUSLEN];
559
560	if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT)) == NULL) {
561		device_printf(dev, "cannot allocate softc\n");
562		return ENXIO;
563	}
564
565	bzero(au, sizeof(*au));
566	au->unit = device_get_unit(dev);
567
568	data = pci_read_config(dev, PCIR_COMMAND, 2);
569	data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
570	pci_write_config(dev, PCIR_COMMAND, data, 2);
571	data = pci_read_config(dev, PCIR_COMMAND, 2);
572
573	j=0;
574	/* XXX dfr: is this strictly necessary? */
575	for (i=0; i<PCI_MAXMAPS_0; i++) {
576#if 0
577		/* Slapped wrist: config_id and map are private structures */
578		if (bootverbose) {
579			printf("pcm%d: map %d - allocating ", unit, i+1);
580			printf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
581			printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
582					    "io" : "memory");
583			printf("at 0x%x...", config_id->map[i].base);
584		}
585#endif
586		regid[j] = PCIR_MAPS + i*4;
587		type[j] = SYS_RES_MEMORY;
588		reg[j] = bus_alloc_resource(dev, type[j], &regid[j],
589					    0, ~0, 1, RF_ACTIVE);
590		if (!reg[j]) {
591			type[j] = SYS_RES_IOPORT;
592			reg[j] = bus_alloc_resource(dev, type[j], &regid[j],
593						    0, ~0, 1, RF_ACTIVE);
594		}
595		if (reg[j]) {
596			au->st[i] = rman_get_bustag(reg[j]);
597			au->sh[i] = rman_get_bushandle(reg[j]);
598			mapped++;
599		}
600#if 0
601		if (bootverbose) printf("%s\n", mapped? "ok" : "failed");
602#endif
603		if (mapped) j++;
604		if (j == 10) {
605			/* XXX */
606			device_printf(dev, "too many resources");
607			goto bad;
608		}
609	}
610
611#if 0
612	if (j < config_id->nummaps) {
613		printf("pcm%d: unable to map a required resource\n", unit);
614		free(au, M_DEVBUF);
615		return;
616	}
617#endif
618
619	au_wr(au, 0, AU_REG_IRQEN, 0, 4);
620
621	irqid = 0;
622	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
623				 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
624	if (!irq
625	    || bus_setup_intr(dev, irq, INTR_TYPE_TTY, au_intr, au, &ih)) {
626		device_printf(dev, "unable to map interrupt\n");
627		goto bad;
628	}
629
630	if (au_testirq(au)) device_printf(dev, "irq test failed\n");
631
632	if (au_init(dev, au) == -1) {
633		device_printf(dev, "unable to initialize the card\n");
634		goto bad;
635	}
636
637	codec = AC97_CREATE(dev, au, au_ac97);
638	if (codec == NULL) goto bad;
639	if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
640
641	if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
642		/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
643		/*highaddr*/BUS_SPACE_MAXADDR,
644		/*filter*/NULL, /*filterarg*/NULL,
645		/*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
646		/*flags*/0, &au->parent_dmat) != 0) {
647		device_printf(dev, "unable to create dma tag\n");
648		goto bad;
649	}
650
651	snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
652		 (type[0] == SYS_RES_IOPORT)? "io" : "memory",
653		 rman_get_start(reg[0]), rman_get_start(irq));
654
655	if (pcm_register(dev, au, 1, 1)) goto bad;
656	/* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
657	pcm_addchan(dev, PCMDIR_PLAY, &auchan_class, au);
658	pcm_setstatus(dev, status);
659
660	return 0;
661
662 bad:
663	if (au) free(au, M_DEVBUF);
664	for (i = 0; i < j; i++)
665		bus_release_resource(dev, type[i], regid[i], reg[i]);
666	if (ih) bus_teardown_intr(dev, irq, ih);
667	if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
668	return ENXIO;
669}
670
671static device_method_t au_methods[] = {
672	/* Device interface */
673	DEVMETHOD(device_probe,		au_pci_probe),
674	DEVMETHOD(device_attach,	au_pci_attach),
675
676	{ 0, 0 }
677};
678
679static driver_t au_driver = {
680	"pcm",
681	au_methods,
682	sizeof(snddev_info),
683};
684
685static devclass_t pcm_devclass;
686
687DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, 0, 0);
688MODULE_DEPEND(snd_aureal, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
689MODULE_VERSION(snd_aureal, 1);
690