aureal.c revision 64881 
1/*
2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/sound/pci/aureal.c 64881 2000-08-20 22:18:56Z cg $
27 */
28
29#include <dev/sound/pcm/sound.h>
30#include <dev/sound/pcm/ac97.h>
31#include <dev/sound/pci/aureal.h>
32
33#include <pci/pcireg.h>
34#include <pci/pcivar.h>
35
36/* PCI IDs of supported chips */
37#define AU8820_PCI_ID 0x000112eb
38
39/* channel interface */
40static void *auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
41static int auchan_setdir(void *data, int dir);
42static int auchan_setformat(void *data, u_int32_t format);
43static int auchan_setspeed(void *data, u_int32_t speed);
44static int auchan_setblocksize(void *data, u_int32_t blocksize);
45static int auchan_trigger(void *data, int go);
46static int auchan_getptr(void *data);
47static pcmchan_caps *auchan_getcaps(void *data);
48
49static u_int32_t au_playfmt[] = {
50	AFMT_U8,
51	AFMT_STEREO | AFMT_U8,
52	AFMT_S16_LE,
53	AFMT_STEREO | AFMT_S16_LE,
54	0
55};
56static pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0};
57
58static u_int32_t au_recfmt[] = {
59	AFMT_U8,
60	AFMT_STEREO | AFMT_U8,
61	AFMT_S16_LE,
62	AFMT_STEREO | AFMT_S16_LE,
63	0
64};
65static pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0};
66
67static pcm_channel au_chantemplate = {
68	auchan_init,
69	auchan_setdir,
70	auchan_setformat,
71	auchan_setspeed,
72	auchan_setblocksize,
73	auchan_trigger,
74	auchan_getptr,
75	auchan_getcaps,
76};
77
78/* -------------------------------------------------------------------- */
79
80static u_int32_t au_rdcd(void *arg, int regno);
81static void au_wrcd(void *arg, int regno, u_int32_t data);
82
83struct au_info;
84
85struct au_chinfo {
86	struct au_info *parent;
87	pcm_channel *channel;
88	snd_dbuf *buffer;
89	int dir;
90};
91
92struct au_info {
93	int unit;
94
95	bus_space_tag_t st[3];
96	bus_space_handle_t sh[3];
97
98	bus_dma_tag_t	parent_dmat;
99
100	u_int32_t	x[32], y[128];
101	char		z[128];
102	u_int32_t	routes[4], interrupts;
103	struct au_chinfo pch;
104};
105
106static int      au_init(device_t dev, struct au_info *au);
107static void     au_intr(void *);
108
109/* -------------------------------------------------------------------- */
110
111static u_int32_t
112au_rd(struct au_info *au, int mapno, int regno, int size)
113{
114	switch(size) {
115	case 1:
116		return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
117	case 2:
118		return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
119	case 4:
120		return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
121	default:
122		return 0xffffffff;
123	}
124}
125
126static void
127au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
128{
129	switch(size) {
130	case 1:
131		bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
132		break;
133	case 2:
134		bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
135		break;
136	case 4:
137		bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
138		break;
139	}
140}
141
142static u_int32_t
143au_rdcd(void *arg, int regno)
144{
145	struct au_info *au = (struct au_info *)arg;
146	int i=0, j=0;
147
148	regno<<=16;
149	au_wr(au, 0, AU_REG_CODECIO, regno, 4);
150	while (j<50) {
151		i=au_rd(au, 0, AU_REG_CODECIO, 4);
152		if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
153		DELAY(j * 200 + 2000);
154		j++;
155	}
156	if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n",
157		au->unit, (regno & AU_CDC_REGMASK)>>16, i);
158	return i & AU_CDC_DATAMASK;
159}
160
161static void
162au_wrcd(void *arg, int regno, u_int32_t data)
163{
164	struct au_info *au = (struct au_info *)arg;
165	int i, j, tries;
166	i=j=tries=0;
167	do {
168		while (j<50 && (i & AU_CDC_WROK) == 0) {
169			i=au_rd(au, 0, AU_REG_CODECST, 4);
170			DELAY(2000);
171			j++;
172		}
173		if (j==50) printf("codec timeout during write of register %x, data %x\n",
174				  regno, data);
175		au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
176/*		DELAY(20000);
177		i=au_rdcd(au, regno);
178*/		tries++;
179	} while (0); /* (i != data && tries < 3); */
180	/*
181	if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
182	*/
183}
184
185static void
186au_setbit(u_int32_t *p, char bit, u_int32_t value)
187{
188	p += bit >> 5;
189	bit &= 0x1f;
190	*p &= ~ (1 << bit);
191	*p |= (value << bit);
192}
193
194static void
195au_addroute(struct au_info *au, int a, int b, int route)
196{
197	int j = 0x1099c+(a<<2);
198	if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
199
200	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
201 	au_wr(au, 0, j, route | (b<<7), 4);
202	au->y[route]=au->x[a];
203	au->x[a]=route;
204	au->z[route]=a & 0x000000ff;
205	au_setbit(au->routes, route, 1);
206}
207
208static void
209au_delroute(struct au_info *au, int route)
210{
211	int i;
212	int j=au->z[route];
213
214	au_setbit(au->routes, route, 0);
215	au->z[route]=0x1f;
216	i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
217	au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
218	au->y[i & 0x7f]=au->y[route];
219	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
220	if (au->x[j] == route) au->x[j]=au->y[route];
221	au->y[route]=0x7f;
222}
223
224static void
225au_encodec(struct au_info *au, char channel)
226{
227	au_wr(au, 0, AU_REG_CODECEN,
228	      au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
229}
230
231static void
232au_clrfifo(struct au_info *au, u_int32_t c)
233{
234	u_int32_t i;
235
236	for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
237}
238
239static void
240au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
241{
242	int x;
243
244	x = au_rd(au, 0, AU_REG_ADB, 4);
245	x &= ~(1 << c);
246	x |= (enable << c);
247	au_wr(au, 0, AU_REG_ADB, x, 4);
248}
249
250static void
251au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
252{
253	struct au_info *au = ch->parent;
254	int i, stereo = (format & AFMT_STEREO)? 1 : 0;
255	u_int32_t baseaddr = vtophys(ch->buffer->buf);
256
257	au_wr(au, 0, 0x1061c, 0, 4);
258	au_wr(au, 0, 0x10620, 0, 4);
259	au_wr(au, 0, 0x10624, 0, 4);
260	switch(format & ~AFMT_STEREO) {
261		case 1:
262			i=0xb000;
263			break;
264		case 2:
265			i=0xf000;
266			break;
267 		case 8:
268			i=0x7000;
269			break;
270		case 16:
271			i=0x23000;
272			break;
273		default:
274			i=0x3000;
275	}
276	au_wr(au, 0, 0x10200, baseaddr, 4);
277	au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
278	au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
279	au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
280
281	au_wr(au, 0, 0x10400, 0xdeffffff, 4);
282	au_wr(au, 0, 0x10404, 0xfcffffff, 4);
283
284	au_wr(au, 0, 0x10580, i, 4);
285
286	au_wr(au, 0, 0x10210, baseaddr, 4);
287	au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
288	au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
289	au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
290
291	au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
292	au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
293
294	au_wr(au, 0, 0x10584, i, 4);
295
296	au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
297	au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
298
299	au_addroute(au, 0x11, 0, 0x58);
300	au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
301}
302
303/* channel interface */
304static void *
305auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
306{
307	struct au_info *au = devinfo;
308	struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
309
310	ch->parent = au;
311	ch->channel = c;
312	ch->buffer = b;
313	ch->buffer->bufsize = AU_BUFFSIZE;
314	if (chn_allocbuf(ch->buffer, au->parent_dmat) == -1) return NULL;
315	return ch;
316}
317
318static int
319auchan_setdir(void *data, int dir)
320{
321	struct au_chinfo *ch = data;
322	if (dir == PCMDIR_PLAY) {
323	} else {
324	}
325	ch->dir = dir;
326	return 0;
327}
328
329static int
330auchan_setformat(void *data, u_int32_t format)
331{
332	struct au_chinfo *ch = data;
333
334	if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
335	return 0;
336}
337
338static int
339auchan_setspeed(void *data, u_int32_t speed)
340{
341	struct au_chinfo *ch = data;
342	if (ch->dir == PCMDIR_PLAY) {
343	} else {
344	}
345	return speed;
346}
347
348static int
349auchan_setblocksize(void *data, u_int32_t blocksize)
350{
351	return blocksize;
352}
353
354static int
355auchan_trigger(void *data, int go)
356{
357	struct au_chinfo *ch = data;
358	struct au_info *au = ch->parent;
359
360	if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
361		return 0;
362
363	if (ch->dir == PCMDIR_PLAY) {
364		au_setadb(au, 0x11, (go)? 1 : 0);
365		if (!go) {
366			au_wr(au, 0, 0xf800, 0, 4);
367			au_wr(au, 0, 0xf804, 0, 4);
368			au_delroute(au, 0x58);
369			au_delroute(au, 0x59);
370		}
371	} else {
372	}
373	return 0;
374}
375
376static int
377auchan_getptr(void *data)
378{
379	struct au_chinfo *ch = data;
380	struct au_info *au = ch->parent;
381	if (ch->dir == PCMDIR_PLAY) {
382		return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
383	} else {
384		return 0;
385	}
386}
387
388static pcmchan_caps *
389auchan_getcaps(void *data)
390{
391	struct au_chinfo *ch = data;
392	return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
393}
394
395/* The interrupt handler */
396static void
397au_intr (void *p)
398{
399	struct au_info *au = p;
400	u_int32_t	intsrc, i;
401
402	au->interrupts++;
403	intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
404	printf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
405	if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit);
406	if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit);
407	if (intsrc & AU_IRQ_UNKNOWN) {
408		(void)au_rd(au, 0, AU_REG_UNK1, 4);
409		au_wr(au, 0, AU_REG_UNK1, 0, 4);
410		au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
411	}
412	if (intsrc & AU_IRQ_PCMOUT) {
413	       	i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
414	       	chn_intr(au->pch.channel);
415		(void)au_rd(au, 0, AU_REG_UNK3, 4);
416		(void)au_rd(au, 0, AU_REG_UNK4, 4);
417		(void)au_rd(au, 0, AU_REG_UNK5, 4);
418	}
419/* don't support midi
420	if (intsrc & AU_IRQ_MIDI) {
421		i=au_rd(au, 0, 0x11004, 4);
422		j=10;
423		while (i & 0xff) {
424			if (j-- <= 0) break;
425			i=au_rd(au, 0, 0x11000, 4);
426			if ((au->midi_stat & 1) && (au->midi_out))
427				au->midi_out(au->midi_devno, i);
428			i=au_rd(au, 0, 0x11004);
429		}
430	}
431*/
432	au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
433	au_rd(au, 0, AU_REG_IRQSRC, 4);
434}
435
436
437/* -------------------------------------------------------------------- */
438
439/* Probe and attach the card */
440
441static int
442au_init(device_t dev, struct au_info *au)
443{
444	u_int32_t	i, j;
445
446	au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
447	DELAY(100000);
448
449	/* init codec */
450	/* cold reset */
451	for (i=0; i<32; i++) {
452		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
453		DELAY(10000);
454	}
455	if (1) {
456		au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
457		DELAY(10000);
458		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
459		DELAY(10000);
460	} else {
461		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
462 		DELAY(100000);
463		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
464		DELAY(100000);
465		au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
466		DELAY(100000);
467		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
468		DELAY(100000);
469		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
470		DELAY(100000);
471		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
472		DELAY(100000);
473	}
474
475	/* init */
476	for (i=0; i<32; i++) {
477		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
478		DELAY(10000);
479	}
480	au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
481	DELAY(10000);
482	au_wr(au, 0, AU_REG_CODECEN, 0, 4);
483
484	/* setup codec */
485	i=j=0;
486	while (j<100 && (i & AU_CDC_READY)==0) {
487		i=au_rd(au, 0, AU_REG_CODECST, 4);
488		DELAY(1000);
489		j++;
490	}
491	if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
492
493   	/* init adb */
494	/*au->x5c=0;*/
495	for (i=0; i<32;  i++) au->x[i]=i+0x67;
496	for (i=0; i<128; i++) au->y[i]=0x7f;
497	for (i=0; i<128; i++) au->z[i]=0x1f;
498	au_wr(au, 0, AU_REG_ADB, 0, 4);
499	for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
500
501	/* test */
502	i=au_rd(au, 0, 0x107c0, 4);
503 	if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
504
505	/* install mixer */
506	au_wr(au, 0, AU_REG_IRQGLOB,
507	      au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
508	/* braindead but it's what the oss/linux driver does
509	 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
510	 */
511	au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
512	/*au->x1e4=0;*/
513
514	/* attach channel */
515	au_addroute(au, 0x11, 0x48, 0x02);
516	au_addroute(au, 0x11, 0x49, 0x03);
517	au_encodec(au, 0);
518	au_encodec(au, 1);
519
520	for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
521	for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
522	au_wr(au, 0, 0xf8c0, 0x0843, 4);
523	for (i=0; i<4; i++) au_clrfifo(au, i);
524
525	return (0);
526}
527
528static int
529au_testirq(struct au_info *au)
530{
531	au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
532	au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
533	au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
534	DELAY(1000000);
535	if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit);
536	/* this apparently generates an irq */
537	return 0;
538}
539
540static int
541au_pci_probe(device_t dev)
542{
543	if (pci_get_devid(dev) == AU8820_PCI_ID) {
544		device_set_desc(dev, "Aureal Vortex 8820");
545		return 0;
546	}
547
548	return ENXIO;
549}
550
551static int
552au_pci_attach(device_t dev)
553{
554	snddev_info    *d;
555	u_int32_t	data;
556	struct au_info *au;
557	int		type[10];
558	int		regid[10];
559	struct resource *reg[10];
560	int		i, j, mapped = 0;
561	int		irqid;
562	struct resource *irq = 0;
563	void		*ih = 0;
564	struct ac97_info *codec;
565	char 		status[SND_STATUSLEN];
566
567	d = device_get_softc(dev);
568	if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT)) == NULL) {
569		device_printf(dev, "cannot allocate softc\n");
570		return ENXIO;
571	}
572
573	bzero(au, sizeof(*au));
574	au->unit = device_get_unit(dev);
575
576	data = pci_read_config(dev, PCIR_COMMAND, 2);
577	data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
578	pci_write_config(dev, PCIR_COMMAND, data, 2);
579	data = pci_read_config(dev, PCIR_COMMAND, 2);
580
581	j=0;
582	/* XXX dfr: is this strictly necessary? */
583	for (i=0; i<PCI_MAXMAPS_0; i++) {
584#if 0
585		/* Slapped wrist: config_id and map are private structures */
586		if (bootverbose) {
587			printf("pcm%d: map %d - allocating ", unit, i+1);
588			printf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
589			printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
590					    "io" : "memory");
591			printf("at 0x%x...", config_id->map[i].base);
592		}
593#endif
594		regid[j] = PCIR_MAPS + i*4;
595		type[j] = SYS_RES_MEMORY;
596		reg[j] = bus_alloc_resource(dev, type[j], &regid[j],
597					    0, ~0, 1, RF_ACTIVE);
598		if (!reg[j]) {
599			type[j] = SYS_RES_IOPORT;
600			reg[j] = bus_alloc_resource(dev, type[j], &regid[j],
601						    0, ~0, 1, RF_ACTIVE);
602		}
603		if (reg[j]) {
604			au->st[i] = rman_get_bustag(reg[j]);
605			au->sh[i] = rman_get_bushandle(reg[j]);
606			mapped++;
607		}
608#if 0
609		if (bootverbose) printf("%s\n", mapped? "ok" : "failed");
610#endif
611		if (mapped) j++;
612		if (j == 10) {
613			/* XXX */
614			device_printf(dev, "too many resources");
615			goto bad;
616		}
617	}
618
619#if 0
620	if (j < config_id->nummaps) {
621		printf("pcm%d: unable to map a required resource\n", unit);
622		free(au, M_DEVBUF);
623		return;
624	}
625#endif
626
627	au_wr(au, 0, AU_REG_IRQEN, 0, 4);
628
629	irqid = 0;
630	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
631				 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
632	if (!irq
633	    || bus_setup_intr(dev, irq, INTR_TYPE_TTY, au_intr, au, &ih)) {
634		device_printf(dev, "unable to map interrupt\n");
635		goto bad;
636	}
637
638	if (au_testirq(au)) device_printf(dev, "irq test failed\n");
639
640	if (au_init(dev, au) == -1) {
641		device_printf(dev, "unable to initialize the card\n");
642		goto bad;
643	}
644
645	codec = ac97_create(dev, au, NULL, au_rdcd, au_wrcd);
646	if (codec == NULL) goto bad;
647	if (mixer_init(d, &ac97_mixer, codec) == -1) goto bad;
648
649	if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
650		/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
651		/*highaddr*/BUS_SPACE_MAXADDR,
652		/*filter*/NULL, /*filterarg*/NULL,
653		/*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
654		/*flags*/0, &au->parent_dmat) != 0) {
655		device_printf(dev, "unable to create dma tag\n");
656		goto bad;
657	}
658
659	snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
660		 (type[0] == SYS_RES_IOPORT)? "io" : "memory",
661		 rman_get_start(reg[0]), rman_get_start(irq));
662
663	if (pcm_register(dev, au, 1, 1)) goto bad;
664	/* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
665	pcm_addchan(dev, PCMDIR_PLAY, &au_chantemplate, au);
666	pcm_setstatus(dev, status);
667
668	return 0;
669
670 bad:
671	if (au) free(au, M_DEVBUF);
672	for (i = 0; i < j; i++)
673		bus_release_resource(dev, type[i], regid[i], reg[i]);
674	if (ih) bus_teardown_intr(dev, irq, ih);
675	if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
676	return ENXIO;
677}
678
679static device_method_t au_methods[] = {
680	/* Device interface */
681	DEVMETHOD(device_probe,		au_pci_probe),
682	DEVMETHOD(device_attach,	au_pci_attach),
683
684	{ 0, 0 }
685};
686
687static driver_t au_driver = {
688	"pcm",
689	au_methods,
690	sizeof(snddev_info),
691};
692
693static devclass_t pcm_devclass;
694
695DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, 0, 0);
696MODULE_DEPEND(snd_aureal, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
697MODULE_VERSION(snd_aureal, 1);
698