aureal.c revision 53465 
1/*
2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/sound/pci/aureal.c 53465 1999-11-20 16:50:33Z cg $
27 */
28
29#include "pci.h"
30#include "pcm.h"
31
32#include <dev/sound/pcm/sound.h>
33#include <dev/sound/pcm/ac97.h>
34#include <dev/sound/pci/aureal.h>
35
36#include <pci/pcireg.h>
37#include <pci/pcivar.h>
38
39#if NPCI != 0
40
41/* PCI IDs of supported chips */
42#define AU8820_PCI_ID 0x000112eb
43
44/* channel interface */
45static void *auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
46static int auchan_setdir(void *data, int dir);
47static int auchan_setformat(void *data, u_int32_t format);
48static int auchan_setspeed(void *data, u_int32_t speed);
49static int auchan_setblocksize(void *data, u_int32_t blocksize);
50static int auchan_trigger(void *data, int go);
51static int auchan_getptr(void *data);
52static pcmchan_caps *auchan_getcaps(void *data);
53
54static pcmchan_caps au_playcaps = {
55	4000, 48000,
56	AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
57	AFMT_STEREO | AFMT_S16_LE
58};
59
60static pcmchan_caps au_reccaps = {
61	4000, 48000,
62	AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
63	AFMT_STEREO | AFMT_S16_LE
64};
65
66static pcm_channel au_chantemplate = {
67	auchan_init,
68	auchan_setdir,
69	auchan_setformat,
70	auchan_setspeed,
71	auchan_setblocksize,
72	auchan_trigger,
73	auchan_getptr,
74	auchan_getcaps,
75};
76
77/* -------------------------------------------------------------------- */
78
79static u_int32_t au_rdcd(void *arg, int regno);
80static void au_wrcd(void *arg, int regno, u_int32_t data);
81
82struct au_info;
83
84struct au_chinfo {
85	struct au_info *parent;
86	pcm_channel *channel;
87	snd_dbuf *buffer;
88	int dir;
89};
90
91struct au_info {
92	int unit;
93
94	bus_space_tag_t st[3];
95	bus_space_handle_t sh[3];
96
97	bus_dma_tag_t	parent_dmat;
98
99	u_int32_t	x[32], y[128];
100	char		z[128];
101	u_int32_t	routes[4], interrupts;
102	struct au_chinfo pch;
103};
104
105static int      au_init(device_t dev, struct au_info *au);
106static void     au_intr(void *);
107
108/* -------------------------------------------------------------------- */
109
110static u_int32_t
111au_rd(struct au_info *au, int mapno, int regno, int size)
112{
113	switch(size) {
114	case 1:
115		return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
116	case 2:
117		return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
118	case 4:
119		return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
120	default:
121		return 0xffffffff;
122	}
123}
124
125static void
126au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
127{
128	switch(size) {
129	case 1:
130		bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
131		break;
132	case 2:
133		bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
134		break;
135	case 4:
136		bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
137		break;
138	}
139}
140
141static u_int32_t
142au_rdcd(void *arg, int regno)
143{
144	struct au_info *au = (struct au_info *)arg;
145	int i=0, j=0;
146
147	regno<<=16;
148	au_wr(au, 0, AU_REG_CODECIO, regno, 4);
149	while (j<50) {
150		i=au_rd(au, 0, AU_REG_CODECIO, 4);
151		if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
152		DELAY(j * 200 + 2000);
153		j++;
154	}
155	if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n",
156		au->unit, (regno & AU_CDC_REGMASK)>>16, i);
157	return i & AU_CDC_DATAMASK;
158}
159
160static void
161au_wrcd(void *arg, int regno, u_int32_t data)
162{
163	struct au_info *au = (struct au_info *)arg;
164	int i, j, tries;
165	i=j=tries=0;
166	do {
167		while (j<50 && (i & AU_CDC_WROK) == 0) {
168			i=au_rd(au, 0, AU_REG_CODECST, 4);
169			DELAY(2000);
170			j++;
171		}
172		if (j==50) printf("codec timeout during write of register %x, data %x\n",
173				  regno, data);
174		au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
175/*		DELAY(20000);
176		i=au_rdcd(au, regno);
177*/		tries++;
178	} while (0); /* (i != data && tries < 3); */
179	/*
180	if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
181	*/
182}
183
184static void
185au_setbit(u_int32_t *p, char bit, u_int32_t value)
186{
187	p += bit >> 5;
188	bit &= 0x1f;
189	*p &= ~ (1 << bit);
190	*p |= (value << bit);
191}
192
193static void
194au_addroute(struct au_info *au, int a, int b, int route)
195{
196	int j = 0x1099c+(a<<2);
197	if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
198
199	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
200 	au_wr(au, 0, j, route | (b<<7), 4);
201	au->y[route]=au->x[a];
202	au->x[a]=route;
203	au->z[route]=a & 0x000000ff;
204	au_setbit(au->routes, route, 1);
205}
206
207static void
208au_delroute(struct au_info *au, int route)
209{
210	int i;
211	int j=au->z[route];
212
213	au_setbit(au->routes, route, 0);
214	au->z[route]=0x1f;
215	i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
216	au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
217	au->y[i & 0x7f]=au->y[route];
218	au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
219	if (au->x[j] == route) au->x[j]=au->y[route];
220	au->y[route]=0x7f;
221}
222
223static void
224au_encodec(struct au_info *au, char channel)
225{
226	au_wr(au, 0, AU_REG_CODECEN,
227	      au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
228}
229
230static void
231au_clrfifo(struct au_info *au, u_int32_t c)
232{
233	u_int32_t i;
234
235	for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
236}
237
238static void
239au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
240{
241	int x;
242
243	x = au_rd(au, 0, AU_REG_ADB, 4);
244	x &= ~(1 << c);
245	x |= (enable << c);
246	au_wr(au, 0, AU_REG_ADB, x, 4);
247}
248
249static void
250au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
251{
252	struct au_info *au = ch->parent;
253	int i, stereo = (format & AFMT_STEREO)? 1 : 0;
254	u_int32_t baseaddr = vtophys(ch->buffer->buf);
255
256	au_wr(au, 0, 0x1061c, 0, 4);
257	au_wr(au, 0, 0x10620, 0, 4);
258	au_wr(au, 0, 0x10624, 0, 4);
259	switch(format & ~AFMT_STEREO) {
260		case 1:
261			i=0xb000;
262			break;
263		case 2:
264			i=0xf000;
265			break;
266 		case 8:
267			i=0x7000;
268			break;
269		case 16:
270			i=0x23000;
271			break;
272		default:
273			i=0x3000;
274	}
275	au_wr(au, 0, 0x10200, baseaddr, 4);
276	au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
277	au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
278	au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
279
280	au_wr(au, 0, 0x10400, 0xdeffffff, 4);
281	au_wr(au, 0, 0x10404, 0xfcffffff, 4);
282
283	au_wr(au, 0, 0x10580, i, 4);
284
285	au_wr(au, 0, 0x10210, baseaddr, 4);
286	au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
287	au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
288	au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
289
290	au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
291	au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
292
293	au_wr(au, 0, 0x10584, i, 4);
294
295	au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
296	au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
297
298	au_addroute(au, 0x11, 0, 0x58);
299	au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
300}
301
302/* channel interface */
303static void *
304auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
305{
306	struct au_info *au = devinfo;
307	struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
308
309	ch->parent = au;
310	ch->channel = c;
311	ch->buffer = b;
312	ch->buffer->bufsize = AU_BUFFSIZE;
313	if (chn_allocbuf(ch->buffer, au->parent_dmat) == -1) return NULL;
314	return ch;
315}
316
317static int
318auchan_setdir(void *data, int dir)
319{
320	struct au_chinfo *ch = data;
321	if (dir == PCMDIR_PLAY) {
322	} else {
323	}
324	ch->dir = dir;
325	return 0;
326}
327
328static int
329auchan_setformat(void *data, u_int32_t format)
330{
331	struct au_chinfo *ch = data;
332
333	if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
334	return 0;
335}
336
337static int
338auchan_setspeed(void *data, u_int32_t speed)
339{
340	struct au_chinfo *ch = data;
341	if (ch->dir == PCMDIR_PLAY) {
342	} else {
343	}
344	return speed;
345}
346
347static int
348auchan_setblocksize(void *data, u_int32_t blocksize)
349{
350	return blocksize;
351}
352
353static int
354auchan_trigger(void *data, int go)
355{
356	struct au_chinfo *ch = data;
357	struct au_info *au = ch->parent;
358	if (ch->dir == PCMDIR_PLAY) {
359		au_setadb(au, 0x11, (go)? 1 : 0);
360		if (!go) {
361			au_wr(au, 0, 0xf800, 0, 4);
362			au_wr(au, 0, 0xf804, 0, 4);
363			au_delroute(au, 0x58);
364			au_delroute(au, 0x59);
365		}
366	} else {
367	}
368	return 0;
369}
370
371static int
372auchan_getptr(void *data)
373{
374	struct au_chinfo *ch = data;
375	struct au_info *au = ch->parent;
376	if (ch->dir == PCMDIR_PLAY) {
377		return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
378	} else {
379		return 0;
380	}
381}
382
383static pcmchan_caps *
384auchan_getcaps(void *data)
385{
386	struct au_chinfo *ch = data;
387	return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
388}
389
390/* The interrupt handler */
391static void
392au_intr (void *p)
393{
394	struct au_info *au = p;
395	u_int32_t	intsrc, i;
396
397	au->interrupts++;
398	intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
399	printf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
400	if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit);
401	if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit);
402	if (intsrc & AU_IRQ_UNKNOWN) {
403		(void)au_rd(au, 0, AU_REG_UNK1, 4);
404		au_wr(au, 0, AU_REG_UNK1, 0, 4);
405		au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
406	}
407	if (intsrc & AU_IRQ_PCMOUT) {
408	       	i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
409	       	chn_intr(au->pch.channel);
410		(void)au_rd(au, 0, AU_REG_UNK3, 4);
411		(void)au_rd(au, 0, AU_REG_UNK4, 4);
412		(void)au_rd(au, 0, AU_REG_UNK5, 4);
413	}
414/* don't support midi
415	if (intsrc & AU_IRQ_MIDI) {
416		i=au_rd(au, 0, 0x11004, 4);
417		j=10;
418		while (i & 0xff) {
419			if (j-- <= 0) break;
420			i=au_rd(au, 0, 0x11000, 4);
421			if ((au->midi_stat & 1) && (au->midi_out))
422				au->midi_out(au->midi_devno, i);
423			i=au_rd(au, 0, 0x11004);
424		}
425	}
426*/
427	au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
428	au_rd(au, 0, AU_REG_IRQSRC, 4);
429}
430
431
432/* -------------------------------------------------------------------- */
433
434/* Probe and attach the card */
435
436static int
437au_init(device_t dev, struct au_info *au)
438{
439	u_int32_t	i, j;
440
441	au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
442	DELAY(100000);
443
444	/* init codec */
445	/* cold reset */
446	for (i=0; i<32; i++) {
447		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
448		DELAY(10000);
449	}
450	if (1) {
451		au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
452		DELAY(10000);
453		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
454		DELAY(10000);
455	} else {
456		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
457 		DELAY(100000);
458		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
459		DELAY(100000);
460		au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
461		DELAY(100000);
462		au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
463		DELAY(100000);
464		au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
465		DELAY(100000);
466		au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
467		DELAY(100000);
468	}
469
470	/* init */
471	for (i=0; i<32; i++) {
472		au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
473		DELAY(10000);
474	}
475	au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
476	DELAY(10000);
477	au_wr(au, 0, AU_REG_CODECEN, 0, 4);
478
479	/* setup codec */
480	i=j=0;
481	while (j<100 && (i & AU_CDC_READY)==0) {
482		i=au_rd(au, 0, AU_REG_CODECST, 4);
483		DELAY(1000);
484		j++;
485	}
486	if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
487
488   	/* init adb */
489	/*au->x5c=0;*/
490	for (i=0; i<32;  i++) au->x[i]=i+0x67;
491	for (i=0; i<128; i++) au->y[i]=0x7f;
492	for (i=0; i<128; i++) au->z[i]=0x1f;
493	au_wr(au, 0, AU_REG_ADB, 0, 4);
494	for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
495
496	/* test */
497	i=au_rd(au, 0, 0x107c0, 4);
498 	if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
499
500	/* install mixer */
501	au_wr(au, 0, AU_REG_IRQGLOB,
502	      au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
503	/* braindead but it's what the oss/linux driver does
504	 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
505	 */
506	au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
507	/*au->x1e4=0;*/
508
509	/* attach channel */
510	au_addroute(au, 0x11, 0x48, 0x02);
511	au_addroute(au, 0x11, 0x49, 0x03);
512	au_encodec(au, 0);
513	au_encodec(au, 1);
514
515	for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
516	for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
517	au_wr(au, 0, 0xf8c0, 0x0843, 4);
518	for (i=0; i<4; i++) au_clrfifo(au, i);
519
520	return (0);
521}
522
523static int
524au_testirq(struct au_info *au)
525{
526	au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
527	au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
528	au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
529	DELAY(1000000);
530	if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit);
531	/* this apparently generates an irq */
532	return 0;
533}
534
535static int
536au_pci_probe(device_t dev)
537{
538	if (pci_get_devid(dev) == AU8820_PCI_ID) {
539		device_set_desc(dev, "Aureal Vortex 8820");
540		return 0;
541	}
542
543	return ENXIO;
544}
545
546static int
547au_pci_attach(device_t dev)
548{
549	snddev_info    *d;
550	u_int32_t	data;
551	struct au_info *au;
552	int		type[10];
553	int		regid[10];
554	struct resource *reg[10];
555	int		i, j, mapped = 0;
556	int		irqid;
557	struct resource *irq = 0;
558	void		*ih = 0;
559	struct ac97_info *codec;
560	char 		status[SND_STATUSLEN];
561
562	d = device_get_softc(dev);
563	if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT)) == NULL) {
564		device_printf(dev, "cannot allocate softc\n");
565		return ENXIO;
566	}
567
568	bzero(au, sizeof(*au));
569	au->unit = device_get_unit(dev);
570
571	data = pci_read_config(dev, PCIR_COMMAND, 2);
572	data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
573	pci_write_config(dev, PCIR_COMMAND, data, 2);
574	data = pci_read_config(dev, PCIR_COMMAND, 2);
575
576	j=0;
577	/* XXX dfr: is this strictly necessary? */
578	for (i=0; i<PCI_MAXMAPS_0; i++) {
579#if 0
580		/* Slapped wrist: config_id and map are private structures */
581		if (bootverbose) {
582			printf("pcm%d: map %d - allocating ", unit, i+1);
583			printf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
584			printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
585					    "io" : "memory");
586			printf("at 0x%x...", config_id->map[i].base);
587		}
588#endif
589		regid[j] = PCIR_MAPS + i*4;
590		type[j] = SYS_RES_MEMORY;
591		reg[j] = bus_alloc_resource(dev, type[j], &regid[j],
592					    0, ~0, 1, RF_ACTIVE);
593		if (!reg[j]) {
594			type[j] = SYS_RES_IOPORT;
595			reg[j] = bus_alloc_resource(dev, type[j], &regid[j],
596						    0, ~0, 1, RF_ACTIVE);
597		}
598		if (reg[j]) {
599			au->st[i] = rman_get_bustag(reg[j]);
600			au->sh[i] = rman_get_bushandle(reg[j]);
601			mapped++;
602		}
603#if 0
604		if (bootverbose) printf("%s\n", mapped? "ok" : "failed");
605#endif
606		if (mapped) j++;
607		if (j == 10) {
608			/* XXX */
609			device_printf(dev, "too many resources");
610			goto bad;
611		}
612	}
613
614#if 0
615	if (j < config_id->nummaps) {
616		printf("pcm%d: unable to map a required resource\n", unit);
617		free(au, M_DEVBUF);
618		return;
619	}
620#endif
621
622	au_wr(au, 0, AU_REG_IRQEN, 0, 4);
623
624	irqid = 0;
625	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
626				 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
627	if (!irq
628	    || bus_setup_intr(dev, irq, INTR_TYPE_TTY, au_intr, au, &ih)) {
629		device_printf(dev, "unable to map interrupt\n");
630		goto bad;
631	}
632
633	if (au_testirq(au)) device_printf(dev, "irq test failed\n");
634
635	if (au_init(dev, au) == -1) {
636		device_printf(dev, "unable to initialize the card\n");
637		goto bad;
638	}
639
640	codec = ac97_create(au, au_rdcd, au_wrcd);
641	if (codec == NULL) goto bad;
642	mixer_init(d, &ac97_mixer, codec);
643
644	if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
645		/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
646		/*highaddr*/BUS_SPACE_MAXADDR,
647		/*filter*/NULL, /*filterarg*/NULL,
648		/*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
649		/*flags*/0, &au->parent_dmat) != 0) {
650		device_printf(dev, "unable to create dma tag\n");
651		goto bad;
652	}
653
654	snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
655		 (type[0] == SYS_RES_IOPORT)? "io" : "memory",
656		 rman_get_start(reg[0]), rman_get_start(irq));
657
658	if (pcm_register(dev, au, 1, 1)) goto bad;
659	/* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
660	pcm_addchan(dev, PCMDIR_PLAY, &au_chantemplate, au);
661	pcm_setstatus(dev, status);
662
663	return 0;
664
665 bad:
666	if (au) free(au, M_DEVBUF);
667	for (i = 0; i < j; i++)
668		bus_release_resource(dev, type[i], regid[i], reg[i]);
669	if (ih) bus_teardown_intr(dev, irq, ih);
670	if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
671	return ENXIO;
672}
673
674static device_method_t au_methods[] = {
675	/* Device interface */
676	DEVMETHOD(device_probe,		au_pci_probe),
677	DEVMETHOD(device_attach,	au_pci_attach),
678
679	{ 0, 0 }
680};
681
682static driver_t au_driver = {
683	"pcm",
684	au_methods,
685	sizeof(snddev_info),
686};
687
688static devclass_t pcm_devclass;
689
690DRIVER_MODULE(au, pci, au_driver, pcm_devclass, 0, 0);
691
692#endif /* NPCI != 0 */
693
694