if_skreg.h revision 160738
1/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/sk/if_skreg.h 160738 2006-07-27 05:06:43Z yongari $ 35 */ 36 37/*- 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* Values to keep the different chip revisions apart (SK_CHIPVER). */ 54#define SK_GENESIS 0x0A 55#define SK_YUKON 0xB0 56#define SK_YUKON_LITE 0xB1 57#define SK_YUKON_LP 0xB2 58#define SK_YUKON_XL 0xB3 59#define SK_YUKON_EC_U 0xB4 60#define SK_YUKON_EC 0xB6 61#define SK_YUKON_FE 0xB7 62#define SK_YUKON_FAMILY(x) ((x) & 0xB0) 63#define SK_IS_YUKON2(sc) \ 64 ((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE) 65 66/* Known revisions in SK_CONFIG. */ 67#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */ 68#define SK_YUKON_LITE_REV_A1 0x3 69#define SK_YUKON_LITE_REV_A3 0x7 70 71#define SK_YUKON_EC_REV_A1 0x0 72#define SK_YUKON_EC_REV_A2 0x1 73#define SK_YUKON_EC_REV_A3 0x2 74 75/* 76 * SysKonnect PCI vendor ID 77 */ 78#define VENDORID_SK 0x1148 79 80/* 81 * Marvell PCI vendor ID 82 */ 83#define VENDORID_MARVELL 0x11AB 84 85/* 86 * SK-NET gigabit ethernet device IDs 87 */ 88#define DEVICEID_SK_V1 0x4300 89#define DEVICEID_SK_V2 0x4320 90 91/* 92 * Marvell gigabit ethernet device IDs 93 */ 94#define DEVICEID_MRVL_4360 0x4360 95#define DEVICEID_MRVL_4361 0x4361 96#define DEVICEID_MRVL_4362 0x4362 97 98/* 99 * Belkin F5D5005 100 */ 101#define DEVICEID_BELKIN_5005 0x5005 102 103/* 104 * 3Com PCI vendor ID 105 */ 106#define VENDORID_3COM 0x10b7 107 108/* 109 * 3Com gigabit ethernet device ID 110 */ 111#define DEVICEID_3COM_3C940 0x1700 112 113/* 114 * Linksys PCI vendor ID 115 */ 116#define VENDORID_LINKSYS 0x1737 117 118/* 119 * Linksys gigabit ethernet device ID 120 */ 121#define DEVICEID_LINKSYS_EG1032 0x1032 122 123/* 124 * Linksys gigabit ethernet rev 2 sub-device ID 125 */ 126#define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015 127 128/* 129 * D-Link PCI vendor ID 130 */ 131#define VENDORID_DLINK 0x1186 132 133/* 134 * D-Link gigabit ethernet device ID 135 */ 136#define DEVICEID_DLINK_DGE530T_A1 0x4c00 137#define DEVICEID_DLINK_DGE530T_B1 0x4b01 138 139/* 140 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 141 * but internally it has a 16K register space. This 16K space is 142 * divided into 128-byte blocks. The first 128 bytes of the I/O 143 * window represent the first block, which is permanently mapped 144 * at the start of the window. The other 127 blocks can be mapped 145 * to the second 128 bytes of the I/O window by setting the desired 146 * block value in the RAP register in block 0. Not all of the 127 147 * blocks are actually used. Most registers are 32 bits wide, but 148 * there are a few 16-bit and 8-bit ones as well. 149 */ 150 151 152/* Start of remappable register window. */ 153#define SK_WIN_BASE 0x0080 154 155/* Size of a window */ 156#define SK_WIN_LEN 0x80 157 158#define SK_WIN_MASK 0x3F80 159#define SK_REG_MASK 0x7F 160 161/* Compute the window of a given register (for the RAP register) */ 162#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 163 164/* Compute the relative offset of a register within the window */ 165#define SK_REG(reg) ((reg) & SK_REG_MASK) 166 167#define SK_PORT_A 0 168#define SK_PORT_B 1 169 170/* 171 * Compute offset of port-specific register. Since there are two 172 * ports, there are two of some GEnesis modules (e.g. two sets of 173 * DMA queues, two sets of FIFO control registers, etc...). Normally, 174 * the block for port 0 is at offset 0x0 and the block for port 1 is 175 * at offset 0x80 (i.e. the next page over). However for the transmit 176 * BMUs and RAMbuffers, there are two blocks for each port: one for 177 * the sync transmit queue and one for the async queue (which we don't 178 * use). However instead of ordering them like this: 179 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 180 * SysKonnect has instead ordered them like this: 181 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 182 * This means that when referencing the TX BMU and RAMbuffer registers, 183 * we have to double the block offset (0x80 * 2) in order to reach the 184 * second queue. This prevents us from using the same formula 185 * (sk_port * 0x80) to compute the offsets for all of the port-specific 186 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 187 * The simplest thing is to provide an extra argument to these macros: 188 * the 'skip' parameter. The 'skip' value is the number of extra pages 189 * for skip when computing the port0/port1 offsets. For most registers, 190 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 191 */ 192#define SK_IF_READ_4(sc_if, skip, reg) \ 193 sk_win_read_4(sc_if->sk_softc, reg + \ 194 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 195#define SK_IF_READ_2(sc_if, skip, reg) \ 196 sk_win_read_2(sc_if->sk_softc, reg + \ 197 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 198#define SK_IF_READ_1(sc_if, skip, reg) \ 199 sk_win_read_1(sc_if->sk_softc, reg + \ 200 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 201 202#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 203 sk_win_write_4(sc_if->sk_softc, \ 204 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 205#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 206 sk_win_write_2(sc_if->sk_softc, \ 207 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 208#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 209 sk_win_write_1(sc_if->sk_softc, \ 210 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 211 212/* Block 0 registers, permanently mapped at iobase. */ 213#define SK_RAP 0x0000 214#define SK_CSR 0x0004 215#define SK_LED 0x0006 216#define SK_ISR 0x0008 /* interrupt source */ 217#define SK_IMR 0x000C /* interrupt mask */ 218#define SK_IESR 0x0010 /* interrupt hardware error source */ 219#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 220#define SK_ISSR 0x0018 /* special interrupt source */ 221#define SK_XM_IMR0 0x0020 222#define SK_XM_ISR0 0x0028 223#define SK_XM_PHYADDR0 0x0030 224#define SK_XM_PHYDATA0 0x0034 225#define SK_XM_IMR1 0x0040 226#define SK_XM_ISR1 0x0048 227#define SK_XM_PHYADDR1 0x0050 228#define SK_XM_PHYDATA1 0x0054 229#define SK_BMU_RX_CSR0 0x0060 230#define SK_BMU_RX_CSR1 0x0064 231#define SK_BMU_TXS_CSR0 0x0068 232#define SK_BMU_TXA_CSR0 0x006C 233#define SK_BMU_TXS_CSR1 0x0070 234#define SK_BMU_TXA_CSR1 0x0074 235 236/* SK_CSR register */ 237#define SK_CSR_SW_RESET 0x0001 238#define SK_CSR_SW_UNRESET 0x0002 239#define SK_CSR_MASTER_RESET 0x0004 240#define SK_CSR_MASTER_UNRESET 0x0008 241#define SK_CSR_MASTER_STOP 0x0010 242#define SK_CSR_MASTER_DONE 0x0020 243#define SK_CSR_SW_IRQ_CLEAR 0x0040 244#define SK_CSR_SW_IRQ_SET 0x0080 245#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 246#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 247 248/* SK_LED register */ 249#define SK_LED_GREEN_OFF 0x01 250#define SK_LED_GREEN_ON 0x02 251 252/* SK_ISR register */ 253#define SK_ISR_TX2_AS_CHECK 0x00000001 254#define SK_ISR_TX2_AS_EOF 0x00000002 255#define SK_ISR_TX2_AS_EOB 0x00000004 256#define SK_ISR_TX2_S_CHECK 0x00000008 257#define SK_ISR_TX2_S_EOF 0x00000010 258#define SK_ISR_TX2_S_EOB 0x00000020 259#define SK_ISR_TX1_AS_CHECK 0x00000040 260#define SK_ISR_TX1_AS_EOF 0x00000080 261#define SK_ISR_TX1_AS_EOB 0x00000100 262#define SK_ISR_TX1_S_CHECK 0x00000200 263#define SK_ISR_TX1_S_EOF 0x00000400 264#define SK_ISR_TX1_S_EOB 0x00000800 265#define SK_ISR_RX2_CHECK 0x00001000 266#define SK_ISR_RX2_EOF 0x00002000 267#define SK_ISR_RX2_EOB 0x00004000 268#define SK_ISR_RX1_CHECK 0x00008000 269#define SK_ISR_RX1_EOF 0x00010000 270#define SK_ISR_RX1_EOB 0x00020000 271#define SK_ISR_LINK2_OFLOW 0x00040000 272#define SK_ISR_MAC2 0x00080000 273#define SK_ISR_LINK1_OFLOW 0x00100000 274#define SK_ISR_MAC1 0x00200000 275#define SK_ISR_TIMER 0x00400000 276#define SK_ISR_EXTERNAL_REG 0x00800000 277#define SK_ISR_SW 0x01000000 278#define SK_ISR_I2C_RDY 0x02000000 279#define SK_ISR_TX2_TIMEO 0x04000000 280#define SK_ISR_TX1_TIMEO 0x08000000 281#define SK_ISR_RX2_TIMEO 0x10000000 282#define SK_ISR_RX1_TIMEO 0x20000000 283#define SK_ISR_RSVD 0x40000000 284#define SK_ISR_HWERR 0x80000000 285 286/* SK_IMR register */ 287#define SK_IMR_TX2_AS_CHECK 0x00000001 288#define SK_IMR_TX2_AS_EOF 0x00000002 289#define SK_IMR_TX2_AS_EOB 0x00000004 290#define SK_IMR_TX2_S_CHECK 0x00000008 291#define SK_IMR_TX2_S_EOF 0x00000010 292#define SK_IMR_TX2_S_EOB 0x00000020 293#define SK_IMR_TX1_AS_CHECK 0x00000040 294#define SK_IMR_TX1_AS_EOF 0x00000080 295#define SK_IMR_TX1_AS_EOB 0x00000100 296#define SK_IMR_TX1_S_CHECK 0x00000200 297#define SK_IMR_TX1_S_EOF 0x00000400 298#define SK_IMR_TX1_S_EOB 0x00000800 299#define SK_IMR_RX2_CHECK 0x00001000 300#define SK_IMR_RX2_EOF 0x00002000 301#define SK_IMR_RX2_EOB 0x00004000 302#define SK_IMR_RX1_CHECK 0x00008000 303#define SK_IMR_RX1_EOF 0x00010000 304#define SK_IMR_RX1_EOB 0x00020000 305#define SK_IMR_LINK2_OFLOW 0x00040000 306#define SK_IMR_MAC2 0x00080000 307#define SK_IMR_LINK1_OFLOW 0x00100000 308#define SK_IMR_MAC1 0x00200000 309#define SK_IMR_TIMER 0x00400000 310#define SK_IMR_EXTERNAL_REG 0x00800000 311#define SK_IMR_SW 0x01000000 312#define SK_IMR_I2C_RDY 0x02000000 313#define SK_IMR_TX2_TIMEO 0x04000000 314#define SK_IMR_TX1_TIMEO 0x08000000 315#define SK_IMR_RX2_TIMEO 0x10000000 316#define SK_IMR_RX1_TIMEO 0x20000000 317#define SK_IMR_RSVD 0x40000000 318#define SK_IMR_HWERR 0x80000000 319 320#define SK_INTRS1 \ 321 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 322 323#define SK_INTRS2 \ 324 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 325 326/* SK_IESR register */ 327#define SK_IESR_PAR_RX2 0x00000001 328#define SK_IESR_PAR_RX1 0x00000002 329#define SK_IESR_PAR_MAC2 0x00000004 330#define SK_IESR_PAR_MAC1 0x00000008 331#define SK_IESR_PAR_WR_RAM 0x00000010 332#define SK_IESR_PAR_RD_RAM 0x00000020 333#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 334#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 335#define SK_IESR_NO_STS_MAC2 0x00000100 336#define SK_IESR_NO_STS_MAC1 0x00000200 337#define SK_IESR_IRQ_STS 0x00000400 338#define SK_IESR_MASTERERR 0x00000800 339 340/* SK_IEMR register */ 341#define SK_IEMR_PAR_RX2 0x00000001 342#define SK_IEMR_PAR_RX1 0x00000002 343#define SK_IEMR_PAR_MAC2 0x00000004 344#define SK_IEMR_PAR_MAC1 0x00000008 345#define SK_IEMR_PAR_WR_RAM 0x00000010 346#define SK_IEMR_PAR_RD_RAM 0x00000020 347#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 348#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 349#define SK_IEMR_NO_STS_MAC2 0x00000100 350#define SK_IEMR_NO_STS_MAC1 0x00000200 351#define SK_IEMR_IRQ_STS 0x00000400 352#define SK_IEMR_MASTERERR 0x00000800 353 354/* Block 2 */ 355#define SK_MAC0_0 0x0100 356#define SK_MAC0_1 0x0104 357#define SK_MAC1_0 0x0108 358#define SK_MAC1_1 0x010C 359#define SK_MAC2_0 0x0110 360#define SK_MAC2_1 0x0114 361#define SK_CONNTYPE 0x0118 362#define SK_PMDTYPE 0x0119 363#define SK_CONFIG 0x011A 364#define SK_CHIPVER 0x011B 365#define SK_EPROM0 0x011C 366#define SK_EPROM1 0x011D /* yukon/genesis */ 367#define SK_Y2_CLKGATE 0x011D /* yukon 2 */ 368#define SK_EPROM2 0x011E /* yukon/genesis */ 369#define SK_Y2_HWRES 0x011E /* yukon 2 */ 370#define SK_EPROM3 0x011F 371#define SK_EP_ADDR 0x0120 372#define SK_EP_DATA 0x0124 373#define SK_EP_LOADCTL 0x0128 374#define SK_EP_LOADTST 0x0129 375#define SK_TIMERINIT 0x0130 376#define SK_TIMER 0x0134 377#define SK_TIMERCTL 0x0138 378#define SK_TIMERTST 0x0139 379#define SK_IMTIMERINIT 0x0140 380#define SK_IMTIMER 0x0144 381#define SK_IMTIMERCTL 0x0148 382#define SK_IMTIMERTST 0x0149 383#define SK_IMMR 0x014C 384#define SK_IHWEMR 0x0150 385#define SK_TESTCTL1 0x0158 386#define SK_TESTCTL2 0x0159 387#define SK_GPIO 0x015C 388#define SK_I2CHWCTL 0x0160 389#define SK_I2CHWDATA 0x0164 390#define SK_I2CHWIRQ 0x0168 391#define SK_I2CSW 0x016C 392#define SK_BLNKINIT 0x0170 393#define SK_BLNKCOUNT 0x0174 394#define SK_BLNKCTL 0x0178 395#define SK_BLNKSTS 0x0179 396#define SK_BLNKTST 0x017A 397 398#define SK_IMCTL_STOP 0x02 399#define SK_IMCTL_START 0x04 400 401#define SK_IMTIMER_TICKS_GENESIS 53 402#define SK_IMTIMER_TICKS_YUKON 78 403#define SK_IMTIMER_TICKS_YUKON_EC 125 404#define SK_IM_USECS(x, t) ((x) * (t)) 405 406#define SK_IM_MIN 10 407#define SK_IM_DEFAULT 100 408#define SK_IM_MAX 10000 409 410/* 411 * The SK_EPROM0 register contains a byte that describes the 412 * amount of SRAM mounted on the NIC. The value also tells if 413 * the chips are 64K or 128K. This affects the RAMbuffer address 414 * offset that we need to use. 415 */ 416#define SK_RAMSIZE_512K_64 0x1 417#define SK_RAMSIZE_1024K_128 0x2 418#define SK_RAMSIZE_1024K_64 0x3 419#define SK_RAMSIZE_2048K_128 0x4 420 421#define SK_RBOFF_0 0x0 422#define SK_RBOFF_80000 0x80000 423 424/* 425 * SK_EEPROM1 contains the PHY type, which may be XMAC for 426 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 427 * PHY. 428 */ 429#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 430#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 431#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 432#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 433#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 434#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 435 436/* 437 * PHY addresses. 438 */ 439#define SK_PHYADDR_XMAC 0x0 440#define SK_PHYADDR_BCOM 0x1 441#define SK_PHYADDR_LONE 0x3 442#define SK_PHYADDR_NAT 0x0 443#define SK_PHYADDR_MARV 0x0 444 445#define SK_CONFIG_SINGLEMAC 0x01 446#define SK_CONFIG_DIS_DSL_CLK 0x02 447 448#define SK_PMD_1000BASELX 0x4C 449#define SK_PMD_1000BASESX 0x53 450#define SK_PMD_1000BASECX 0x43 451#define SK_PMD_1000BASETX 0x54 452 453/* GPIO bits */ 454#define SK_GPIO_DAT0 0x00000001 455#define SK_GPIO_DAT1 0x00000002 456#define SK_GPIO_DAT2 0x00000004 457#define SK_GPIO_DAT3 0x00000008 458#define SK_GPIO_DAT4 0x00000010 459#define SK_GPIO_DAT5 0x00000020 460#define SK_GPIO_DAT6 0x00000040 461#define SK_GPIO_DAT7 0x00000080 462#define SK_GPIO_DAT8 0x00000100 463#define SK_GPIO_DAT9 0x00000200 464#define SK_GPIO_DIR0 0x00010000 465#define SK_GPIO_DIR1 0x00020000 466#define SK_GPIO_DIR2 0x00040000 467#define SK_GPIO_DIR3 0x00080000 468#define SK_GPIO_DIR4 0x00100000 469#define SK_GPIO_DIR5 0x00200000 470#define SK_GPIO_DIR6 0x00400000 471#define SK_GPIO_DIR7 0x00800000 472#define SK_GPIO_DIR8 0x01000000 473#define SK_GPIO_DIR9 0x02000000 474 475#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */ 476 477#define SK_Y2_HWRES_LINK_1 0x01 478#define SK_Y2_HWRES_LINK_2 0x02 479#define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) 480#define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) 481 482/* Block 3 Ram interface and MAC arbiter registers */ 483#define SK_RAMADDR 0x0180 484#define SK_RAMDATA0 0x0184 485#define SK_RAMDATA1 0x0188 486#define SK_TO0 0x0190 487#define SK_TO1 0x0191 488#define SK_TO2 0x0192 489#define SK_TO3 0x0193 490#define SK_TO4 0x0194 491#define SK_TO5 0x0195 492#define SK_TO6 0x0196 493#define SK_TO7 0x0197 494#define SK_TO8 0x0198 495#define SK_TO9 0x0199 496#define SK_TO10 0x019A 497#define SK_TO11 0x019B 498#define SK_RITIMEO_TMR 0x019C 499#define SK_RAMCTL 0x01A0 500#define SK_RITIMER_TST 0x01A2 501 502#define SK_RAMCTL_RESET 0x0001 503#define SK_RAMCTL_UNRESET 0x0002 504#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 505#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 506 507/* Mac arbiter registers */ 508#define SK_MINIT_RX1 0x01B0 509#define SK_MINIT_RX2 0x01B1 510#define SK_MINIT_TX1 0x01B2 511#define SK_MINIT_TX2 0x01B3 512#define SK_MTIMEO_RX1 0x01B4 513#define SK_MTIMEO_RX2 0x01B5 514#define SK_MTIMEO_TX1 0x01B6 515#define SK_MTIEMO_TX2 0x01B7 516#define SK_MACARB_CTL 0x01B8 517#define SK_MTIMER_TST 0x01BA 518#define SK_RCINIT_RX1 0x01C0 519#define SK_RCINIT_RX2 0x01C1 520#define SK_RCINIT_TX1 0x01C2 521#define SK_RCINIT_TX2 0x01C3 522#define SK_RCTIMEO_RX1 0x01C4 523#define SK_RCTIMEO_RX2 0x01C5 524#define SK_RCTIMEO_TX1 0x01C6 525#define SK_RCTIMEO_TX2 0x01C7 526#define SK_RECOVERY_CTL 0x01C8 527#define SK_RCTIMER_TST 0x01CA 528 529/* Packet arbiter registers */ 530#define SK_RXPA1_TINIT 0x01D0 531#define SK_RXPA2_TINIT 0x01D4 532#define SK_TXPA1_TINIT 0x01D8 533#define SK_TXPA2_TINIT 0x01DC 534#define SK_RXPA1_TIMEO 0x01E0 535#define SK_RXPA2_TIMEO 0x01E4 536#define SK_TXPA1_TIMEO 0x01E8 537#define SK_TXPA2_TIMEO 0x01EC 538#define SK_PKTARB_CTL 0x01F0 539#define SK_PKTATB_TST 0x01F2 540 541#define SK_PKTARB_TIMEOUT 0x2000 542 543#define SK_PKTARBCTL_RESET 0x0001 544#define SK_PKTARBCTL_UNRESET 0x0002 545#define SK_PKTARBCTL_RXTO1_OFF 0x0004 546#define SK_PKTARBCTL_RXTO1_ON 0x0008 547#define SK_PKTARBCTL_RXTO2_OFF 0x0010 548#define SK_PKTARBCTL_RXTO2_ON 0x0020 549#define SK_PKTARBCTL_TXTO1_OFF 0x0040 550#define SK_PKTARBCTL_TXTO1_ON 0x0080 551#define SK_PKTARBCTL_TXTO2_OFF 0x0100 552#define SK_PKTARBCTL_TXTO2_ON 0x0200 553#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 554#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 555#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 556#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 557 558#define SK_MINIT_XMAC_B2 54 559#define SK_MINIT_XMAC_C1 63 560 561#define SK_MACARBCTL_RESET 0x0001 562#define SK_MACARBCTL_UNRESET 0x0002 563#define SK_MACARBCTL_FASTOE_OFF 0x0004 564#define SK_MACARBCRL_FASTOE_ON 0x0008 565 566#define SK_RCINIT_XMAC_B2 54 567#define SK_RCINIT_XMAC_C1 0 568 569#define SK_RECOVERYCTL_RX1_OFF 0x0001 570#define SK_RECOVERYCTL_RX1_ON 0x0002 571#define SK_RECOVERYCTL_RX2_OFF 0x0004 572#define SK_RECOVERYCTL_RX2_ON 0x0008 573#define SK_RECOVERYCTL_TX1_OFF 0x0010 574#define SK_RECOVERYCTL_TX1_ON 0x0020 575#define SK_RECOVERYCTL_TX2_OFF 0x0040 576#define SK_RECOVERYCTL_TX2_ON 0x0080 577 578#define SK_RECOVERY_XMAC_B2 \ 579 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 580 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 581 582#define SK_RECOVERY_XMAC_C1 \ 583 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 584 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 585 586/* Block 4 -- TX Arbiter MAC 1 */ 587#define SK_TXAR1_TIMERINIT 0x0200 588#define SK_TXAR1_TIMERVAL 0x0204 589#define SK_TXAR1_LIMITINIT 0x0208 590#define SK_TXAR1_LIMITCNT 0x020C 591#define SK_TXAR1_COUNTERCTL 0x0210 592#define SK_TXAR1_COUNTERTST 0x0212 593#define SK_TXAR1_COUNTERSTS 0x0212 594 595/* Block 5 -- TX Arbiter MAC 2 */ 596#define SK_TXAR2_TIMERINIT 0x0280 597#define SK_TXAR2_TIMERVAL 0x0284 598#define SK_TXAR2_LIMITINIT 0x0288 599#define SK_TXAR2_LIMITCNT 0x028C 600#define SK_TXAR2_COUNTERCTL 0x0290 601#define SK_TXAR2_COUNTERTST 0x0291 602#define SK_TXAR2_COUNTERSTS 0x0292 603 604#define SK_TXARCTL_OFF 0x01 605#define SK_TXARCTL_ON 0x02 606#define SK_TXARCTL_RATECTL_OFF 0x04 607#define SK_TXARCTL_RATECTL_ON 0x08 608#define SK_TXARCTL_ALLOC_OFF 0x10 609#define SK_TXARCTL_ALLOC_ON 0x20 610#define SK_TXARCTL_FSYNC_OFF 0x40 611#define SK_TXARCTL_FSYNC_ON 0x80 612 613/* Block 6 -- External registers */ 614#define SK_EXTREG_BASE 0x300 615#define SK_EXTREG_END 0x37C 616 617/* Block 7 -- PCI config registers */ 618#define SK_PCI_BASE 0x0380 619#define SK_PCI_END 0x03FC 620 621/* Compute offset of mirrored PCI register */ 622#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 623 624/* Block 8 -- RX queue 1 */ 625#define SK_RXQ1_BUFCNT 0x0400 626#define SK_RXQ1_BUFCTL 0x0402 627#define SK_RXQ1_NEXTDESC 0x0404 628#define SK_RXQ1_RXBUF_LO 0x0408 629#define SK_RXQ1_RXBUF_HI 0x040C 630#define SK_RXQ1_RXSTAT 0x0410 631#define SK_RXQ1_TIMESTAMP 0x0414 632#define SK_RXQ1_CSUM1 0x0418 633#define SK_RXQ1_CSUM2 0x041A 634#define SK_RXQ1_CSUM1_START 0x041C 635#define SK_RXQ1_CSUM2_START 0x041E 636#define SK_RXQ1_CURADDR_LO 0x0420 637#define SK_RXQ1_CURADDR_HI 0x0424 638#define SK_RXQ1_CURCNT_LO 0x0428 639#define SK_RXQ1_CURCNT_HI 0x042C 640#define SK_RXQ1_CURBYTES 0x0430 641#define SK_RXQ1_BMU_CSR 0x0434 642#define SK_RXQ1_WATERMARK 0x0438 643#define SK_RXQ1_FLAG 0x043A 644#define SK_RXQ1_TEST1 0x043C 645#define SK_RXQ1_TEST2 0x0440 646#define SK_RXQ1_TEST3 0x0444 647 648/* Block 9 -- RX queue 2 */ 649#define SK_RXQ2_BUFCNT 0x0480 650#define SK_RXQ2_BUFCTL 0x0482 651#define SK_RXQ2_NEXTDESC 0x0484 652#define SK_RXQ2_RXBUF_LO 0x0488 653#define SK_RXQ2_RXBUF_HI 0x048C 654#define SK_RXQ2_RXSTAT 0x0490 655#define SK_RXQ2_TIMESTAMP 0x0494 656#define SK_RXQ2_CSUM1 0x0498 657#define SK_RXQ2_CSUM2 0x049A 658#define SK_RXQ2_CSUM1_START 0x049C 659#define SK_RXQ2_CSUM2_START 0x049E 660#define SK_RXQ2_CURADDR_LO 0x04A0 661#define SK_RXQ2_CURADDR_HI 0x04A4 662#define SK_RXQ2_CURCNT_LO 0x04A8 663#define SK_RXQ2_CURCNT_HI 0x04AC 664#define SK_RXQ2_CURBYTES 0x04B0 665#define SK_RXQ2_BMU_CSR 0x04B4 666#define SK_RXQ2_WATERMARK 0x04B8 667#define SK_RXQ2_FLAG 0x04BA 668#define SK_RXQ2_TEST1 0x04BC 669#define SK_RXQ2_TEST2 0x04C0 670#define SK_RXQ2_TEST3 0x04C4 671 672#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 673#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 674#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 675#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 676#define SK_RXBMU_RX_START 0x00000010 677#define SK_RXBMU_RX_STOP 0x00000020 678#define SK_RXBMU_POLL_OFF 0x00000040 679#define SK_RXBMU_POLL_ON 0x00000080 680#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 681#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 682#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 683#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 684#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 685#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 686#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 687#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 688#define SK_RXBMU_PFI_SM_RESET 0x00010000 689#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 690#define SK_RXBMU_FIFO_RESET 0x00040000 691#define SK_RXBMU_FIFO_UNRESET 0x00080000 692#define SK_RXBMU_DESC_RESET 0x00100000 693#define SK_RXBMU_DESC_UNRESET 0x00200000 694#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 695 696#define SK_RXBMU_ONLINE \ 697 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 698 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 699 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 700 SK_RXBMU_DESC_UNRESET) 701 702#define SK_RXBMU_OFFLINE \ 703 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 704 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 705 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 706 SK_RXBMU_DESC_RESET) 707 708/* Block 12 -- TX sync queue 1 */ 709#define SK_TXQS1_BUFCNT 0x0600 710#define SK_TXQS1_BUFCTL 0x0602 711#define SK_TXQS1_NEXTDESC 0x0604 712#define SK_TXQS1_RXBUF_LO 0x0608 713#define SK_TXQS1_RXBUF_HI 0x060C 714#define SK_TXQS1_RXSTAT 0x0610 715#define SK_TXQS1_CSUM_STARTVAL 0x0614 716#define SK_TXQS1_CSUM_STARTPOS 0x0618 717#define SK_TXQS1_CSUM_WRITEPOS 0x061A 718#define SK_TXQS1_CURADDR_LO 0x0620 719#define SK_TXQS1_CURADDR_HI 0x0624 720#define SK_TXQS1_CURCNT_LO 0x0628 721#define SK_TXQS1_CURCNT_HI 0x062C 722#define SK_TXQS1_CURBYTES 0x0630 723#define SK_TXQS1_BMU_CSR 0x0634 724#define SK_TXQS1_WATERMARK 0x0638 725#define SK_TXQS1_FLAG 0x063A 726#define SK_TXQS1_TEST1 0x063C 727#define SK_TXQS1_TEST2 0x0640 728#define SK_TXQS1_TEST3 0x0644 729 730/* Block 13 -- TX async queue 1 */ 731#define SK_TXQA1_BUFCNT 0x0680 732#define SK_TXQA1_BUFCTL 0x0682 733#define SK_TXQA1_NEXTDESC 0x0684 734#define SK_TXQA1_RXBUF_LO 0x0688 735#define SK_TXQA1_RXBUF_HI 0x068C 736#define SK_TXQA1_RXSTAT 0x0690 737#define SK_TXQA1_CSUM_STARTVAL 0x0694 738#define SK_TXQA1_CSUM_STARTPOS 0x0698 739#define SK_TXQA1_CSUM_WRITEPOS 0x069A 740#define SK_TXQA1_CURADDR_LO 0x06A0 741#define SK_TXQA1_CURADDR_HI 0x06A4 742#define SK_TXQA1_CURCNT_LO 0x06A8 743#define SK_TXQA1_CURCNT_HI 0x06AC 744#define SK_TXQA1_CURBYTES 0x06B0 745#define SK_TXQA1_BMU_CSR 0x06B4 746#define SK_TXQA1_WATERMARK 0x06B8 747#define SK_TXQA1_FLAG 0x06BA 748#define SK_TXQA1_TEST1 0x06BC 749#define SK_TXQA1_TEST2 0x06C0 750#define SK_TXQA1_TEST3 0x06C4 751 752/* Block 14 -- TX sync queue 2 */ 753#define SK_TXQS2_BUFCNT 0x0700 754#define SK_TXQS2_BUFCTL 0x0702 755#define SK_TXQS2_NEXTDESC 0x0704 756#define SK_TXQS2_RXBUF_LO 0x0708 757#define SK_TXQS2_RXBUF_HI 0x070C 758#define SK_TXQS2_RXSTAT 0x0710 759#define SK_TXQS2_CSUM_STARTVAL 0x0714 760#define SK_TXQS2_CSUM_STARTPOS 0x0718 761#define SK_TXQS2_CSUM_WRITEPOS 0x071A 762#define SK_TXQS2_CURADDR_LO 0x0720 763#define SK_TXQS2_CURADDR_HI 0x0724 764#define SK_TXQS2_CURCNT_LO 0x0728 765#define SK_TXQS2_CURCNT_HI 0x072C 766#define SK_TXQS2_CURBYTES 0x0730 767#define SK_TXQS2_BMU_CSR 0x0734 768#define SK_TXQS2_WATERMARK 0x0738 769#define SK_TXQS2_FLAG 0x073A 770#define SK_TXQS2_TEST1 0x073C 771#define SK_TXQS2_TEST2 0x0740 772#define SK_TXQS2_TEST3 0x0744 773 774/* Block 15 -- TX async queue 2 */ 775#define SK_TXQA2_BUFCNT 0x0780 776#define SK_TXQA2_BUFCTL 0x0782 777#define SK_TXQA2_NEXTDESC 0x0784 778#define SK_TXQA2_RXBUF_LO 0x0788 779#define SK_TXQA2_RXBUF_HI 0x078C 780#define SK_TXQA2_RXSTAT 0x0790 781#define SK_TXQA2_CSUM_STARTVAL 0x0794 782#define SK_TXQA2_CSUM_STARTPOS 0x0798 783#define SK_TXQA2_CSUM_WRITEPOS 0x079A 784#define SK_TXQA2_CURADDR_LO 0x07A0 785#define SK_TXQA2_CURADDR_HI 0x07A4 786#define SK_TXQA2_CURCNT_LO 0x07A8 787#define SK_TXQA2_CURCNT_HI 0x07AC 788#define SK_TXQA2_CURBYTES 0x07B0 789#define SK_TXQA2_BMU_CSR 0x07B4 790#define SK_TXQA2_WATERMARK 0x07B8 791#define SK_TXQA2_FLAG 0x07BA 792#define SK_TXQA2_TEST1 0x07BC 793#define SK_TXQA2_TEST2 0x07C0 794#define SK_TXQA2_TEST3 0x07C4 795 796#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 797#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 798#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 799#define SK_TXBMU_TX_START 0x00000010 800#define SK_TXBMU_TX_STOP 0x00000020 801#define SK_TXBMU_POLL_OFF 0x00000040 802#define SK_TXBMU_POLL_ON 0x00000080 803#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 804#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 805#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 806#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 807#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 808#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 809#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 810#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 811#define SK_TXBMU_PFI_SM_RESET 0x00010000 812#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 813#define SK_TXBMU_FIFO_RESET 0x00040000 814#define SK_TXBMU_FIFO_UNRESET 0x00080000 815#define SK_TXBMU_DESC_RESET 0x00100000 816#define SK_TXBMU_DESC_UNRESET 0x00200000 817#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 818 819#define SK_TXBMU_ONLINE \ 820 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 821 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 822 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 823 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON) 824 825#define SK_TXBMU_OFFLINE \ 826 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 827 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 828 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 829 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF) 830 831/* Block 16 -- Receive RAMbuffer 1 */ 832#define SK_RXRB1_START 0x0800 833#define SK_RXRB1_END 0x0804 834#define SK_RXRB1_WR_PTR 0x0808 835#define SK_RXRB1_RD_PTR 0x080C 836#define SK_RXRB1_UTHR_PAUSE 0x0810 837#define SK_RXRB1_LTHR_PAUSE 0x0814 838#define SK_RXRB1_UTHR_HIPRIO 0x0818 839#define SK_RXRB1_UTHR_LOPRIO 0x081C 840#define SK_RXRB1_PKTCNT 0x0820 841#define SK_RXRB1_LVL 0x0824 842#define SK_RXRB1_CTLTST 0x0828 843 844/* Block 17 -- Receive RAMbuffer 2 */ 845#define SK_RXRB2_START 0x0880 846#define SK_RXRB2_END 0x0884 847#define SK_RXRB2_WR_PTR 0x0888 848#define SK_RXRB2_RD_PTR 0x088C 849#define SK_RXRB2_UTHR_PAUSE 0x0890 850#define SK_RXRB2_LTHR_PAUSE 0x0894 851#define SK_RXRB2_UTHR_HIPRIO 0x0898 852#define SK_RXRB2_UTHR_LOPRIO 0x089C 853#define SK_RXRB2_PKTCNT 0x08A0 854#define SK_RXRB2_LVL 0x08A4 855#define SK_RXRB2_CTLTST 0x08A8 856 857/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 858#define SK_TXRBS1_START 0x0A00 859#define SK_TXRBS1_END 0x0A04 860#define SK_TXRBS1_WR_PTR 0x0A08 861#define SK_TXRBS1_RD_PTR 0x0A0C 862#define SK_TXRBS1_PKTCNT 0x0A20 863#define SK_TXRBS1_LVL 0x0A24 864#define SK_TXRBS1_CTLTST 0x0A28 865 866/* Block 21 -- Async. Transmit RAMbuffer 1 */ 867#define SK_TXRBA1_START 0x0A80 868#define SK_TXRBA1_END 0x0A84 869#define SK_TXRBA1_WR_PTR 0x0A88 870#define SK_TXRBA1_RD_PTR 0x0A8C 871#define SK_TXRBA1_PKTCNT 0x0AA0 872#define SK_TXRBA1_LVL 0x0AA4 873#define SK_TXRBA1_CTLTST 0x0AA8 874 875/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 876#define SK_TXRBS2_START 0x0B00 877#define SK_TXRBS2_END 0x0B04 878#define SK_TXRBS2_WR_PTR 0x0B08 879#define SK_TXRBS2_RD_PTR 0x0B0C 880#define SK_TXRBS2_PKTCNT 0x0B20 881#define SK_TXRBS2_LVL 0x0B24 882#define SK_TXRBS2_CTLTST 0x0B28 883 884/* Block 23 -- Async. Transmit RAMbuffer 2 */ 885#define SK_TXRBA2_START 0x0B80 886#define SK_TXRBA2_END 0x0B84 887#define SK_TXRBA2_WR_PTR 0x0B88 888#define SK_TXRBA2_RD_PTR 0x0B8C 889#define SK_TXRBA2_PKTCNT 0x0BA0 890#define SK_TXRBA2_LVL 0x0BA4 891#define SK_TXRBA2_CTLTST 0x0BA8 892 893#define SK_RBCTL_RESET 0x00000001 894#define SK_RBCTL_UNRESET 0x00000002 895#define SK_RBCTL_OFF 0x00000004 896#define SK_RBCTL_ON 0x00000008 897#define SK_RBCTL_STORENFWD_OFF 0x00000010 898#define SK_RBCTL_STORENFWD_ON 0x00000020 899 900/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 901#define SK_RXF1_END 0x0C00 902#define SK_RXF1_WPTR 0x0C04 903#define SK_RXF1_RPTR 0x0C0C 904#define SK_RXF1_PKTCNT 0x0C10 905#define SK_RXF1_LVL 0x0C14 906#define SK_RXF1_MACCTL 0x0C18 907#define SK_RXF1_CTL 0x0C1C 908#define SK_RXLED1_CNTINIT 0x0C20 909#define SK_RXLED1_COUNTER 0x0C24 910#define SK_RXLED1_CTL 0x0C28 911#define SK_RXLED1_TST 0x0C29 912#define SK_LINK_SYNC1_CINIT 0x0C30 913#define SK_LINK_SYNC1_COUNTER 0x0C34 914#define SK_LINK_SYNC1_CTL 0x0C38 915#define SK_LINK_SYNC1_TST 0x0C39 916#define SK_LINKLED1_CTL 0x0C3C 917 918#define SK_FIFO_END 0x3F 919 920/* Receive MAC FIFO 1 (Yukon Only) */ 921#define SK_RXMF1_END 0x0C40 922#define SK_RXMF1_THRESHOLD 0x0C44 923#define SK_RXMF1_CTRL_TEST 0x0C48 924#define SK_RXMF1_FLUSH_MASK 0x0C4C 925#define SK_RXMF1_FLUSH_THRESHOLD 0x0C50 926#define SK_RXMF1_WRITE_PTR 0x0C60 927#define SK_RXMF1_WRITE_LEVEL 0x0C68 928#define SK_RXMF1_READ_PTR 0x0C70 929#define SK_RXMF1_READ_LEVEL 0x0C78 930 931/* Receive MAC FIFO 1 Control/Test */ 932#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 933#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 934#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 935#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 936#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 937#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 938#define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */ 939#define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */ 940#define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */ 941#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 942#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 943#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 944#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 945#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 946 947#define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */ 948 949/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 950#define SK_RXF2_END 0x0C80 951#define SK_RXF2_WPTR 0x0C84 952#define SK_RXF2_RPTR 0x0C8C 953#define SK_RXF2_PKTCNT 0x0C90 954#define SK_RXF2_LVL 0x0C94 955#define SK_RXF2_MACCTL 0x0C98 956#define SK_RXF2_CTL 0x0C9C 957#define SK_RXLED2_CNTINIT 0x0CA0 958#define SK_RXLED2_COUNTER 0x0CA4 959#define SK_RXLED2_CTL 0x0CA8 960#define SK_RXLED2_TST 0x0CA9 961#define SK_LINK_SYNC2_CINIT 0x0CB0 962#define SK_LINK_SYNC2_COUNTER 0x0CB4 963#define SK_LINK_SYNC2_CTL 0x0CB8 964#define SK_LINK_SYNC2_TST 0x0CB9 965#define SK_LINKLED2_CTL 0x0CBC 966 967#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 968#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 969#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 970#define SK_RXMACCTL_RSTAMP_ON 0x00000008 971#define SK_RXMACCTL_FLUSH_OFF 0x00000010 972#define SK_RXMACCTL_FLUSH_ON 0x00000020 973#define SK_RXMACCTL_PAUSE_OFF 0x00000040 974#define SK_RXMACCTL_PAUSE_ON 0x00000080 975#define SK_RXMACCTL_AFULL_OFF 0x00000100 976#define SK_RXMACCTL_AFULL_ON 0x00000200 977#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 978#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 979#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 980#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 981#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 982#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 983 984#define SK_RXLEDCTL_ENABLE 0x0001 985#define SK_RXLEDCTL_COUNTER_STOP 0x0002 986#define SK_RXLEDCTL_COUNTER_START 0x0004 987 988#define SK_LINKLED_OFF 0x0001 989#define SK_LINKLED_ON 0x0002 990#define SK_LINKLED_LINKSYNC_OFF 0x0004 991#define SK_LINKLED_LINKSYNC_ON 0x0008 992#define SK_LINKLED_BLINK_OFF 0x0010 993#define SK_LINKLED_BLINK_ON 0x0020 994 995/* Block 26 -- TX MAC FIFO 1 regisrers */ 996#define SK_TXF1_END 0x0D00 997#define SK_TXF1_WPTR 0x0D04 998#define SK_TXF1_RPTR 0x0D0C 999#define SK_TXF1_PKTCNT 0x0D10 1000#define SK_TXF1_LVL 0x0D14 1001#define SK_TXF1_MACCTL 0x0D18 1002#define SK_TXF1_CTL 0x0D1C 1003#define SK_TXLED1_CNTINIT 0x0D20 1004#define SK_TXLED1_COUNTER 0x0D24 1005#define SK_TXLED1_CTL 0x0D28 1006#define SK_TXLED1_TST 0x0D29 1007 1008/* Transmit MAC FIFO 1 (Yukon Only) */ 1009#define SK_TXMF1_END 0x0D40 1010#define SK_TXMF1_THRESHOLD 0x0D44 1011#define SK_TXMF1_CTRL_TEST 0x0D48 1012#define SK_TXMF1_WRITE_PTR 0x0D60 1013#define SK_TXMF1_WRITE_SHADOW 0x0D64 1014#define SK_TXMF1_WRITE_LEVEL 0x0D68 1015#define SK_TXMF1_READ_PTR 0x0D70 1016#define SK_TXMF1_RESTART_PTR 0x0D74 1017#define SK_TXMF1_READ_LEVEL 0x0D78 1018 1019/* Transmit MAC FIFO Control/Test */ 1020#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 1021#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 1022#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 1023#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 1024#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 1025#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 1026#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 1027#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 1028#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 1029#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 1030#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 1031#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 1032#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 1033 1034/* Block 27 -- TX MAC FIFO 2 regisrers */ 1035#define SK_TXF2_END 0x0D80 1036#define SK_TXF2_WPTR 0x0D84 1037#define SK_TXF2_RPTR 0x0D8C 1038#define SK_TXF2_PKTCNT 0x0D90 1039#define SK_TXF2_LVL 0x0D94 1040#define SK_TXF2_MACCTL 0x0D98 1041#define SK_TXF2_CTL 0x0D9C 1042#define SK_TXLED2_CNTINIT 0x0DA0 1043#define SK_TXLED2_COUNTER 0x0DA4 1044#define SK_TXLED2_CTL 0x0DA8 1045#define SK_TXLED2_TST 0x0DA9 1046 1047#define SK_TXMACCTL_XMAC_RESET 0x00000001 1048#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 1049#define SK_TXMACCTL_LOOP_OFF 0x00000004 1050#define SK_TXMACCTL_LOOP_ON 0x00000008 1051#define SK_TXMACCTL_FLUSH_OFF 0x00000010 1052#define SK_TXMACCTL_FLUSH_ON 0x00000020 1053#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1054#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1055#define SK_TXMACCTL_AFULL_OFF 0x00000100 1056#define SK_TXMACCTL_AFULL_ON 0x00000200 1057#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1058#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1059#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1060#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1061#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1062#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1063 1064#define SK_TXLEDCTL_ENABLE 0x0001 1065#define SK_TXLEDCTL_COUNTER_STOP 0x0002 1066#define SK_TXLEDCTL_COUNTER_START 0x0004 1067 1068#define SK_FIFO_RESET 0x00000001 1069#define SK_FIFO_UNRESET 0x00000002 1070#define SK_FIFO_OFF 0x00000004 1071#define SK_FIFO_ON 0x00000008 1072 1073/* Block 28 -- Descriptor Poll Timer */ 1074#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1075#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1076 1077#define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */ 1078 1079#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1080#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1081#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1082 1083#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1084#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1085#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1086#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1087 1088/* Block 29 -- reserved */ 1089 1090/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1091#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1092#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1093#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1094#define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */ 1095#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1096#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1097#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1098#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1099#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1100#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1101#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1102#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1103#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1104#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1105#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1106#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1107#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1108#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1109#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1110#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1111#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1112#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1113#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1114#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1115#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1116#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1117#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1118#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1119#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1120 1121#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1122#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1123#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1124#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1125#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1126#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1127 1128#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1129#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1130#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1131#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1132#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1133#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1134#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1135#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1136#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1137#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1138#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1139#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1140#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1141#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1142#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1143#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1144#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1145#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1146#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1147#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1148#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1149#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1150#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1151 1152#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1153 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1154#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1155 SK_GPHY_HWCFG_M_2 ) 1156#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1157 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1158 1159#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1160#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1161#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1162#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1163#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1164#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1165 1166#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1167#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1168 1169/* Block 31 -- reserved */ 1170 1171/* Block 32-33 -- Pattern Ram */ 1172#define SK_WOL_PRAM 0x1000 1173 1174/* Block 0x22 - 0x3f -- reserved */ 1175 1176/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1177#define SK_XMAC1_BASE 0x2000 1178 1179/* Block 0x50 to 0x5F -- MARV 1 registers */ 1180#define SK_MARV1_BASE 0x2800 1181 1182/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1183#define SK_XMAC2_BASE 0x3000 1184 1185/* Block 0x70 to 0x7F -- MARV 2 registers */ 1186#define SK_MARV2_BASE 0x3800 1187 1188/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1189#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1190 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1191 1192#if 0 1193#define SK_XM_READ_4(sc, reg) \ 1194 ((sk_win_read_2(sc->sk_softc, \ 1195 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1196 ((sk_win_read_2(sc->sk_softc, \ 1197 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1198 1199#define SK_XM_WRITE_4(sc, reg, val) \ 1200 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1201 ((val) & 0xFFFF)); \ 1202 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1203 ((val) >> 16) & 0xFFFF) 1204#else 1205#define SK_XM_READ_4(sc, reg) \ 1206 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1207 1208#define SK_XM_WRITE_4(sc, reg, val) \ 1209 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1210#endif 1211 1212#define SK_XM_READ_2(sc, reg) \ 1213 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1214 1215#define SK_XM_WRITE_2(sc, reg, val) \ 1216 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1217 1218#define SK_XM_SETBIT_4(sc, reg, x) \ 1219 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1220 1221#define SK_XM_CLRBIT_4(sc, reg, x) \ 1222 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1223 1224#define SK_XM_SETBIT_2(sc, reg, x) \ 1225 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1226 1227#define SK_XM_CLRBIT_2(sc, reg, x) \ 1228 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1229 1230/* Compute relative offset of an MARV register in the MARV window(s). */ 1231#define SK_YU_REG(sc, reg) \ 1232 ((reg) + SK_MARV1_BASE + \ 1233 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1234 1235#define SK_YU_READ_4(sc, reg) \ 1236 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1237 1238#define SK_YU_READ_2(sc, reg) \ 1239 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1240 1241#define SK_YU_WRITE_4(sc, reg, val) \ 1242 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1243 1244#define SK_YU_WRITE_2(sc, reg, val) \ 1245 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1246 1247#define SK_YU_SETBIT_4(sc, reg, x) \ 1248 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1249 1250#define SK_YU_CLRBIT_4(sc, reg, x) \ 1251 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1252 1253#define SK_YU_SETBIT_2(sc, reg, x) \ 1254 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1255 1256#define SK_YU_CLRBIT_2(sc, reg, x) \ 1257 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1258 1259/* 1260 * The default FIFO threshold on the XMAC II is 4 bytes. On 1261 * dual port NICs, this often leads to transmit underruns, so we 1262 * bump the threshold a little. 1263 */ 1264#define SK_XM_TX_FIFOTHRESH 512 1265 1266#define SK_PCI_VENDOR_ID 0x0000 1267#define SK_PCI_DEVICE_ID 0x0002 1268#define SK_PCI_COMMAND 0x0004 1269#define SK_PCI_STATUS 0x0006 1270#define SK_PCI_REVID 0x0008 1271#define SK_PCI_CLASSCODE 0x0009 1272#define SK_PCI_CACHELEN 0x000C 1273#define SK_PCI_LATENCY_TIMER 0x000D 1274#define SK_PCI_HEADER_TYPE 0x000E 1275#define SK_PCI_LOMEM 0x0010 1276#define SK_PCI_LOIO 0x0014 1277#define SK_PCI_SUBVEN_ID 0x002C 1278#define SK_PCI_SYBSYS_ID 0x002E 1279#define SK_PCI_BIOSROM 0x0030 1280#define SK_PCI_INTLINE 0x003C 1281#define SK_PCI_INTPIN 0x003D 1282#define SK_PCI_MINGNT 0x003E 1283#define SK_PCI_MINLAT 0x003F 1284 1285/* device specific PCI registers */ 1286#define SK_PCI_OURREG1 0x0040 1287#define SK_PCI_OURREG2 0x0044 1288#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1289#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1290#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1291#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1292#define SK_PCI_PME_EVENT 0x004F 1293#define SK_PCI_VPD_CAPID 0x0050 1294#define SK_PCI_VPD_NEXTPTR 0x0051 1295#define SK_PCI_VPD_ADDR 0x0052 1296#define SK_PCI_VPD_DATA 0x0054 1297 1298#define SK_PSTATE_MASK 0x0003 1299#define SK_PSTATE_D0 0x0000 1300#define SK_PSTATE_D1 0x0001 1301#define SK_PSTATE_D2 0x0002 1302#define SK_PSTATE_D3 0x0003 1303#define SK_PME_EN 0x0010 1304#define SK_PME_STATUS 0x8000 1305 1306/* 1307 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1308 * read is complete. Set to 1 to initiate a write, will become 0 1309 * when write is finished. 1310 */ 1311#define SK_VPD_FLAG 0x8000 1312 1313/* VPD structures */ 1314struct vpd_res { 1315 u_int8_t vr_id; 1316 u_int8_t vr_len; 1317 u_int8_t vr_pad; 1318}; 1319 1320struct vpd_key { 1321 char vk_key[2]; 1322 u_int8_t vk_len; 1323}; 1324 1325#define VPD_RES_ID 0x82 /* ID string */ 1326#define VPD_RES_READ 0x90 /* start of read only area */ 1327#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1328#define VPD_RES_END 0x78 /* end tag */ 1329 1330#define CSR_WRITE_4(sc, reg, val) \ 1331 bus_write_4((sc)->sk_res[0], (reg), (val)) 1332#define CSR_WRITE_2(sc, reg, val) \ 1333 bus_write_2((sc)->sk_res[0], (reg), (val)) 1334#define CSR_WRITE_1(sc, reg, val) \ 1335 bus_write_1((sc)->sk_res[0], (reg), (val)) 1336 1337#define CSR_READ_4(sc, reg) \ 1338 bus_read_4((sc)->sk_res[0], (reg)) 1339#define CSR_READ_2(sc, reg) \ 1340 bus_read_2((sc)->sk_res[0], (reg)) 1341#define CSR_READ_1(sc, reg) \ 1342 bus_read_1((sc)->sk_res[0], (reg)) 1343 1344struct sk_type { 1345 u_int16_t sk_vid; 1346 u_int16_t sk_did; 1347 char *sk_name; 1348}; 1349 1350#define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 1351#define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32) 1352 1353#define SK_RING_ALIGN 64 1354 1355/* RX queue descriptor data structure */ 1356struct sk_rx_desc { 1357 u_int32_t sk_ctl; 1358 u_int32_t sk_next; 1359 u_int32_t sk_data_lo; 1360 u_int32_t sk_data_hi; 1361 u_int32_t sk_xmac_rxstat; 1362 u_int32_t sk_timestamp; 1363 u_int32_t sk_csum; 1364 u_int32_t sk_csum_start; 1365}; 1366 1367#define SK_OPCODE_DEFAULT 0x00550000 1368#define SK_OPCODE_CSUM 0x00560000 1369 1370#define SK_RXCTL_LEN 0x0000FFFF 1371#define SK_RXCTL_OPCODE 0x00FF0000 1372#define SK_RXCTL_TSTAMP_VALID 0x01000000 1373#define SK_RXCTL_STATUS_VALID 0x02000000 1374#define SK_RXCTL_DEV0 0x04000000 1375#define SK_RXCTL_EOF_INTR 0x08000000 1376#define SK_RXCTL_EOB_INTR 0x10000000 1377#define SK_RXCTL_LASTFRAG 0x20000000 1378#define SK_RXCTL_FIRSTFRAG 0x40000000 1379#define SK_RXCTL_OWN 0x80000000 1380 1381#define SK_RXSTAT \ 1382 (SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1383 1384struct sk_tx_desc { 1385 u_int32_t sk_ctl; 1386 u_int32_t sk_next; 1387 u_int32_t sk_data_lo; 1388 u_int32_t sk_data_hi; 1389 u_int32_t sk_xmac_txstat; 1390 u_int32_t sk_csum_startval; 1391 u_int32_t sk_csum_start; 1392 u_int32_t sk_rsvd1; 1393}; 1394 1395#define SK_TXCTL_LEN 0x0000FFFF 1396#define SK_TXCTL_OPCODE 0x00FF0000 1397#define SK_TXCTL_SW 0x01000000 1398#define SK_TXCTL_NOCRC 0x02000000 1399#define SK_TXCTL_STORENFWD 0x04000000 1400#define SK_TXCTL_EOF_INTR 0x08000000 1401#define SK_TXCTL_EOB_INTR 0x10000000 1402#define SK_TXCTL_LASTFRAG 0x20000000 1403#define SK_TXCTL_FIRSTFRAG 0x40000000 1404#define SK_TXCTL_OWN 0x80000000 1405 1406#define SK_TXSTAT \ 1407 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1408 1409#define SK_RXBYTES(x) ((x) & 0x0000FFFF) 1410#define SK_TXBYTES SK_RXBYTES 1411 1412#define SK_TX_RING_CNT 512 1413#define SK_RX_RING_CNT 256 1414#define SK_JUMBO_RX_RING_CNT 256 1415#define SK_MAXTXSEGS 32 1416#define SK_MAXRXSEGS 32 1417 1418/* 1419 * Jumbo buffer stuff. Note that we must allocate more jumbo 1420 * buffers than there are descriptors in the receive ring. This 1421 * is because we don't know how long it will take for a packet 1422 * to be released after we hand it off to the upper protocol 1423 * layers. To be safe, we allocate 1.5 times the number of 1424 * receive descriptors. 1425 */ 1426#define SK_JUMBO_FRAMELEN 9018 1427#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1428#define SK_MAX_FRAMELEN \ 1429 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 1430#define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 1431#define SK_JSLOTS ((SK_RX_RING_CNT * 3) / 2) 1432 1433#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1434#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1435 (SK_JRAWLEN % sizeof(u_int64_t)))) 1436#define SK_JPAGESZ PAGE_SIZE 1437#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1438#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1439 1440struct sk_jpool_entry { 1441 int slot; 1442 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1443}; 1444 1445struct sk_txdesc { 1446 struct mbuf *tx_m; 1447 bus_dmamap_t tx_dmamap; 1448 STAILQ_ENTRY(sk_txdesc) tx_q; 1449}; 1450 1451STAILQ_HEAD(sk_txdq, sk_txdesc); 1452 1453struct sk_rxdesc { 1454 struct mbuf *rx_m; 1455 bus_dmamap_t rx_dmamap; 1456}; 1457 1458struct sk_chain_data { 1459 bus_dma_tag_t sk_parent_tag; 1460 bus_dma_tag_t sk_tx_tag; 1461 struct sk_txdesc sk_txdesc[SK_TX_RING_CNT]; 1462 struct sk_txdq sk_txfreeq; 1463 struct sk_txdq sk_txbusyq; 1464 bus_dma_tag_t sk_rx_tag; 1465 struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT]; 1466 bus_dma_tag_t sk_tx_ring_tag; 1467 bus_dma_tag_t sk_rx_ring_tag; 1468 bus_dmamap_t sk_tx_ring_map; 1469 bus_dmamap_t sk_rx_ring_map; 1470 bus_dmamap_t sk_rx_sparemap; 1471 bus_dma_tag_t sk_jumbo_rx_tag; 1472 bus_dma_tag_t sk_jumbo_tag; 1473 bus_dmamap_t sk_jumbo_map; 1474 bus_dma_tag_t sk_jumbo_mtag; 1475 caddr_t sk_jslots[SK_JSLOTS]; 1476 struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT]; 1477 bus_dma_tag_t sk_jumbo_rx_ring_tag; 1478 bus_dmamap_t sk_jumbo_rx_ring_map; 1479 bus_dmamap_t sk_jumbo_rx_sparemap; 1480 int sk_tx_prod; 1481 int sk_tx_cons; 1482 int sk_tx_cnt; 1483 int sk_rx_cons; 1484 int sk_jumbo_rx_cons; 1485}; 1486 1487struct sk_ring_data { 1488 struct sk_tx_desc *sk_tx_ring; 1489 bus_addr_t sk_tx_ring_paddr; 1490 struct sk_rx_desc *sk_rx_ring; 1491 bus_addr_t sk_rx_ring_paddr; 1492 struct sk_rx_desc *sk_jumbo_rx_ring; 1493 bus_addr_t sk_jumbo_rx_ring_paddr; 1494 void *sk_jumbo_buf; 1495 bus_addr_t sk_jumbo_buf_paddr; 1496}; 1497 1498#define SK_TX_RING_ADDR(sc, i) \ 1499 ((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i)) 1500#define SK_RX_RING_ADDR(sc, i) \ 1501 ((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1502#define SK_JUMBO_RX_RING_ADDR(sc, i) \ 1503 ((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1504 1505#define SK_TX_RING_SZ \ 1506 (sizeof(struct sk_tx_desc) * SK_TX_RING_CNT) 1507#define SK_RX_RING_SZ \ 1508 (sizeof(struct sk_rx_desc) * SK_RX_RING_CNT) 1509#define SK_JUMBO_RX_RING_SZ \ 1510 (sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT) 1511 1512struct sk_bcom_hack { 1513 int reg; 1514 int val; 1515}; 1516 1517#define SK_INC(x, y) (x) = (x + 1) % y 1518 1519/* Forward decl. */ 1520struct sk_if_softc; 1521 1522/* Softc for the GEnesis controller. */ 1523struct sk_softc { 1524 struct resource *sk_res[2]; /* I/O and IRQ resources */ 1525 struct resource_spec *sk_res_spec; 1526 void *sk_intrhand; /* irq handler handle */ 1527 device_t sk_dev; 1528 u_int8_t sk_type; 1529 u_int8_t sk_rev; 1530 u_int8_t spare; 1531 char *sk_vpd_prodname; 1532 char *sk_vpd_readonly; 1533 uint16_t sk_vpd_readonly_len; 1534 u_int32_t sk_rboff; /* RAMbuffer offset */ 1535 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1536 u_int32_t sk_pmd; /* physical media type */ 1537 u_int32_t sk_coppertype; 1538 u_int32_t sk_intrmask; 1539 int sk_int_mod; 1540 int sk_int_ticks; 1541 int sk_suspended; 1542 struct sk_if_softc *sk_if[2]; 1543 device_t sk_devs[2]; 1544 struct mtx sk_mii_mtx; 1545 struct mtx sk_mtx; 1546}; 1547 1548#define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1549#define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1550#define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1551#define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc) 1552#define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc) 1553#define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc) 1554#define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx) 1555#define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx) 1556 1557/* Softc for each logical interface */ 1558struct sk_if_softc { 1559 struct ifnet *sk_ifp; /* interface info */ 1560 device_t sk_miibus; 1561 device_t sk_if_dev; 1562 u_int8_t sk_port; /* port # on controller */ 1563 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1564 u_int32_t sk_rx_ramstart; 1565 u_int32_t sk_rx_ramend; 1566 u_int32_t sk_tx_ramstart; 1567 u_int32_t sk_tx_ramend; 1568 int sk_phytype; 1569 int sk_phyaddr; 1570 int sk_link; 1571 struct callout sk_tick_ch; 1572 struct sk_chain_data sk_cdata; 1573 struct sk_ring_data sk_rdata; 1574 struct sk_softc *sk_softc; /* parent controller */ 1575 int sk_tx_bmu; /* TX BMU register */ 1576 int sk_if_flags; 1577 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1578 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1579 struct mtx sk_jlist_mtx; 1580}; 1581 1582#define SK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->sk_jlist_mtx) 1583#define SK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_jlist_mtx) 1584 1585#define SK_TIMEOUT 1000 1586