if_skreg.h revision 158096
1/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/sk/if_skreg.h 158096 2006-04-28 03:17:37Z sobomax $ 35 */ 36 37/*- 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* Values to keep the different chip revisions apart (SK_CHIPVER). */ 54#define SK_GENESIS 0x0A 55#define SK_YUKON 0xB0 56#define SK_YUKON_LITE 0xB1 57#define SK_YUKON_LP 0xB2 58#define SK_YUKON_XL 0xB3 59#define SK_YUKON_EC_U 0xB4 60#define SK_YUKON_EC 0xB6 61#define SK_YUKON_FE 0xB7 62#define SK_YUKON_FAMILY(x) ((x) & 0xB0) 63#define SK_IS_YUKON2(sc) \ 64 ((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE) 65 66/* Known revisions in SK_CONFIG. */ 67#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */ 68#define SK_YUKON_LITE_REV_A1 0x3 69#define SK_YUKON_LITE_REV_A3 0x7 70 71#define SK_YUKON_EC_REV_A1 0x0 72#define SK_YUKON_EC_REV_A2 0x1 73#define SK_YUKON_EC_REV_A3 0x2 74 75/* 76 * SysKonnect PCI vendor ID 77 */ 78#define VENDORID_SK 0x1148 79 80/* 81 * Marvell PCI vendor ID 82 */ 83#define VENDORID_MARVELL 0x11AB 84 85/* 86 * SK-NET gigabit ethernet device IDs 87 */ 88#define DEVICEID_SK_V1 0x4300 89#define DEVICEID_SK_V2 0x4320 90 91/* 92 * Marvell gigabit ethernet device IDs 93 */ 94#define DEVICEID_MRVL_4360 0x4360 95#define DEVICEID_MRVL_4361 0x4361 96#define DEVICEID_MRVL_4362 0x4362 97 98/* 99 * Belkin F5D5005 100 */ 101#define DEVICEID_BELKIN_5005 0x5005 102 103/* 104 * 3Com PCI vendor ID 105 */ 106#define VENDORID_3COM 0x10b7 107 108/* 109 * 3Com gigabit ethernet device ID 110 */ 111#define DEVICEID_3COM_3C940 0x1700 112 113/* 114 * Linksys PCI vendor ID 115 */ 116#define VENDORID_LINKSYS 0x1737 117 118/* 119 * Linksys gigabit ethernet device ID 120 */ 121#define DEVICEID_LINKSYS_EG1032 0x1032 122 123/* 124 * Linksys gigabit ethernet rev 2 sub-device ID 125 */ 126#define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015 127 128/* 129 * D-Link PCI vendor ID 130 */ 131#define VENDORID_DLINK 0x1186 132 133/* 134 * D-Link gigabit ethernet device ID 135 */ 136#define DEVICEID_DLINK_DGE530T 0x4c00 137 138/* 139 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 140 * but internally it has a 16K register space. This 16K space is 141 * divided into 128-byte blocks. The first 128 bytes of the I/O 142 * window represent the first block, which is permanently mapped 143 * at the start of the window. The other 127 blocks can be mapped 144 * to the second 128 bytes of the I/O window by setting the desired 145 * block value in the RAP register in block 0. Not all of the 127 146 * blocks are actually used. Most registers are 32 bits wide, but 147 * there are a few 16-bit and 8-bit ones as well. 148 */ 149 150 151/* Start of remappable register window. */ 152#define SK_WIN_BASE 0x0080 153 154/* Size of a window */ 155#define SK_WIN_LEN 0x80 156 157#define SK_WIN_MASK 0x3F80 158#define SK_REG_MASK 0x7F 159 160/* Compute the window of a given register (for the RAP register) */ 161#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 162 163/* Compute the relative offset of a register within the window */ 164#define SK_REG(reg) ((reg) & SK_REG_MASK) 165 166#define SK_PORT_A 0 167#define SK_PORT_B 1 168 169/* 170 * Compute offset of port-specific register. Since there are two 171 * ports, there are two of some GEnesis modules (e.g. two sets of 172 * DMA queues, two sets of FIFO control registers, etc...). Normally, 173 * the block for port 0 is at offset 0x0 and the block for port 1 is 174 * at offset 0x80 (i.e. the next page over). However for the transmit 175 * BMUs and RAMbuffers, there are two blocks for each port: one for 176 * the sync transmit queue and one for the async queue (which we don't 177 * use). However instead of ordering them like this: 178 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 179 * SysKonnect has instead ordered them like this: 180 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 181 * This means that when referencing the TX BMU and RAMbuffer registers, 182 * we have to double the block offset (0x80 * 2) in order to reach the 183 * second queue. This prevents us from using the same formula 184 * (sk_port * 0x80) to compute the offsets for all of the port-specific 185 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 186 * The simplest thing is to provide an extra argument to these macros: 187 * the 'skip' parameter. The 'skip' value is the number of extra pages 188 * for skip when computing the port0/port1 offsets. For most registers, 189 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 190 */ 191#define SK_IF_READ_4(sc_if, skip, reg) \ 192 sk_win_read_4(sc_if->sk_softc, reg + \ 193 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 194#define SK_IF_READ_2(sc_if, skip, reg) \ 195 sk_win_read_2(sc_if->sk_softc, reg + \ 196 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 197#define SK_IF_READ_1(sc_if, skip, reg) \ 198 sk_win_read_1(sc_if->sk_softc, reg + \ 199 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 200 201#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 202 sk_win_write_4(sc_if->sk_softc, \ 203 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 204#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 205 sk_win_write_2(sc_if->sk_softc, \ 206 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 207#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 208 sk_win_write_1(sc_if->sk_softc, \ 209 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 210 211/* Block 0 registers, permanently mapped at iobase. */ 212#define SK_RAP 0x0000 213#define SK_CSR 0x0004 214#define SK_LED 0x0006 215#define SK_ISR 0x0008 /* interrupt source */ 216#define SK_IMR 0x000C /* interrupt mask */ 217#define SK_IESR 0x0010 /* interrupt hardware error source */ 218#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 219#define SK_ISSR 0x0018 /* special interrupt source */ 220#define SK_XM_IMR0 0x0020 221#define SK_XM_ISR0 0x0028 222#define SK_XM_PHYADDR0 0x0030 223#define SK_XM_PHYDATA0 0x0034 224#define SK_XM_IMR1 0x0040 225#define SK_XM_ISR1 0x0048 226#define SK_XM_PHYADDR1 0x0050 227#define SK_XM_PHYDATA1 0x0054 228#define SK_BMU_RX_CSR0 0x0060 229#define SK_BMU_RX_CSR1 0x0064 230#define SK_BMU_TXS_CSR0 0x0068 231#define SK_BMU_TXA_CSR0 0x006C 232#define SK_BMU_TXS_CSR1 0x0070 233#define SK_BMU_TXA_CSR1 0x0074 234 235/* SK_CSR register */ 236#define SK_CSR_SW_RESET 0x0001 237#define SK_CSR_SW_UNRESET 0x0002 238#define SK_CSR_MASTER_RESET 0x0004 239#define SK_CSR_MASTER_UNRESET 0x0008 240#define SK_CSR_MASTER_STOP 0x0010 241#define SK_CSR_MASTER_DONE 0x0020 242#define SK_CSR_SW_IRQ_CLEAR 0x0040 243#define SK_CSR_SW_IRQ_SET 0x0080 244#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 245#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 246 247/* SK_LED register */ 248#define SK_LED_GREEN_OFF 0x01 249#define SK_LED_GREEN_ON 0x02 250 251/* SK_ISR register */ 252#define SK_ISR_TX2_AS_CHECK 0x00000001 253#define SK_ISR_TX2_AS_EOF 0x00000002 254#define SK_ISR_TX2_AS_EOB 0x00000004 255#define SK_ISR_TX2_S_CHECK 0x00000008 256#define SK_ISR_TX2_S_EOF 0x00000010 257#define SK_ISR_TX2_S_EOB 0x00000020 258#define SK_ISR_TX1_AS_CHECK 0x00000040 259#define SK_ISR_TX1_AS_EOF 0x00000080 260#define SK_ISR_TX1_AS_EOB 0x00000100 261#define SK_ISR_TX1_S_CHECK 0x00000200 262#define SK_ISR_TX1_S_EOF 0x00000400 263#define SK_ISR_TX1_S_EOB 0x00000800 264#define SK_ISR_RX2_CHECK 0x00001000 265#define SK_ISR_RX2_EOF 0x00002000 266#define SK_ISR_RX2_EOB 0x00004000 267#define SK_ISR_RX1_CHECK 0x00008000 268#define SK_ISR_RX1_EOF 0x00010000 269#define SK_ISR_RX1_EOB 0x00020000 270#define SK_ISR_LINK2_OFLOW 0x00040000 271#define SK_ISR_MAC2 0x00080000 272#define SK_ISR_LINK1_OFLOW 0x00100000 273#define SK_ISR_MAC1 0x00200000 274#define SK_ISR_TIMER 0x00400000 275#define SK_ISR_EXTERNAL_REG 0x00800000 276#define SK_ISR_SW 0x01000000 277#define SK_ISR_I2C_RDY 0x02000000 278#define SK_ISR_TX2_TIMEO 0x04000000 279#define SK_ISR_TX1_TIMEO 0x08000000 280#define SK_ISR_RX2_TIMEO 0x10000000 281#define SK_ISR_RX1_TIMEO 0x20000000 282#define SK_ISR_RSVD 0x40000000 283#define SK_ISR_HWERR 0x80000000 284 285/* SK_IMR register */ 286#define SK_IMR_TX2_AS_CHECK 0x00000001 287#define SK_IMR_TX2_AS_EOF 0x00000002 288#define SK_IMR_TX2_AS_EOB 0x00000004 289#define SK_IMR_TX2_S_CHECK 0x00000008 290#define SK_IMR_TX2_S_EOF 0x00000010 291#define SK_IMR_TX2_S_EOB 0x00000020 292#define SK_IMR_TX1_AS_CHECK 0x00000040 293#define SK_IMR_TX1_AS_EOF 0x00000080 294#define SK_IMR_TX1_AS_EOB 0x00000100 295#define SK_IMR_TX1_S_CHECK 0x00000200 296#define SK_IMR_TX1_S_EOF 0x00000400 297#define SK_IMR_TX1_S_EOB 0x00000800 298#define SK_IMR_RX2_CHECK 0x00001000 299#define SK_IMR_RX2_EOF 0x00002000 300#define SK_IMR_RX2_EOB 0x00004000 301#define SK_IMR_RX1_CHECK 0x00008000 302#define SK_IMR_RX1_EOF 0x00010000 303#define SK_IMR_RX1_EOB 0x00020000 304#define SK_IMR_LINK2_OFLOW 0x00040000 305#define SK_IMR_MAC2 0x00080000 306#define SK_IMR_LINK1_OFLOW 0x00100000 307#define SK_IMR_MAC1 0x00200000 308#define SK_IMR_TIMER 0x00400000 309#define SK_IMR_EXTERNAL_REG 0x00800000 310#define SK_IMR_SW 0x01000000 311#define SK_IMR_I2C_RDY 0x02000000 312#define SK_IMR_TX2_TIMEO 0x04000000 313#define SK_IMR_TX1_TIMEO 0x08000000 314#define SK_IMR_RX2_TIMEO 0x10000000 315#define SK_IMR_RX1_TIMEO 0x20000000 316#define SK_IMR_RSVD 0x40000000 317#define SK_IMR_HWERR 0x80000000 318 319#define SK_INTRS1 \ 320 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 321 322#define SK_INTRS2 \ 323 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 324 325/* SK_IESR register */ 326#define SK_IESR_PAR_RX2 0x00000001 327#define SK_IESR_PAR_RX1 0x00000002 328#define SK_IESR_PAR_MAC2 0x00000004 329#define SK_IESR_PAR_MAC1 0x00000008 330#define SK_IESR_PAR_WR_RAM 0x00000010 331#define SK_IESR_PAR_RD_RAM 0x00000020 332#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 333#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 334#define SK_IESR_NO_STS_MAC2 0x00000100 335#define SK_IESR_NO_STS_MAC1 0x00000200 336#define SK_IESR_IRQ_STS 0x00000400 337#define SK_IESR_MASTERERR 0x00000800 338 339/* SK_IEMR register */ 340#define SK_IEMR_PAR_RX2 0x00000001 341#define SK_IEMR_PAR_RX1 0x00000002 342#define SK_IEMR_PAR_MAC2 0x00000004 343#define SK_IEMR_PAR_MAC1 0x00000008 344#define SK_IEMR_PAR_WR_RAM 0x00000010 345#define SK_IEMR_PAR_RD_RAM 0x00000020 346#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 347#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 348#define SK_IEMR_NO_STS_MAC2 0x00000100 349#define SK_IEMR_NO_STS_MAC1 0x00000200 350#define SK_IEMR_IRQ_STS 0x00000400 351#define SK_IEMR_MASTERERR 0x00000800 352 353/* Block 2 */ 354#define SK_MAC0_0 0x0100 355#define SK_MAC0_1 0x0104 356#define SK_MAC1_0 0x0108 357#define SK_MAC1_1 0x010C 358#define SK_MAC2_0 0x0110 359#define SK_MAC2_1 0x0114 360#define SK_CONNTYPE 0x0118 361#define SK_PMDTYPE 0x0119 362#define SK_CONFIG 0x011A 363#define SK_CHIPVER 0x011B 364#define SK_EPROM0 0x011C 365#define SK_EPROM1 0x011D /* yukon/genesis */ 366#define SK_Y2_CLKGATE 0x011D /* yukon 2 */ 367#define SK_EPROM2 0x011E /* yukon/genesis */ 368#define SK_Y2_HWRES 0x011E /* yukon 2 */ 369#define SK_EPROM3 0x011F 370#define SK_EP_ADDR 0x0120 371#define SK_EP_DATA 0x0124 372#define SK_EP_LOADCTL 0x0128 373#define SK_EP_LOADTST 0x0129 374#define SK_TIMERINIT 0x0130 375#define SK_TIMER 0x0134 376#define SK_TIMERCTL 0x0138 377#define SK_TIMERTST 0x0139 378#define SK_IMTIMERINIT 0x0140 379#define SK_IMTIMER 0x0144 380#define SK_IMTIMERCTL 0x0148 381#define SK_IMTIMERTST 0x0149 382#define SK_IMMR 0x014C 383#define SK_IHWEMR 0x0150 384#define SK_TESTCTL1 0x0158 385#define SK_TESTCTL2 0x0159 386#define SK_GPIO 0x015C 387#define SK_I2CHWCTL 0x0160 388#define SK_I2CHWDATA 0x0164 389#define SK_I2CHWIRQ 0x0168 390#define SK_I2CSW 0x016C 391#define SK_BLNKINIT 0x0170 392#define SK_BLNKCOUNT 0x0174 393#define SK_BLNKCTL 0x0178 394#define SK_BLNKSTS 0x0179 395#define SK_BLNKTST 0x017A 396 397#define SK_IMCTL_STOP 0x02 398#define SK_IMCTL_START 0x04 399 400#define SK_IMTIMER_TICKS_GENESIS 53 401#define SK_IMTIMER_TICKS_YUKON 78 402#define SK_IMTIMER_TICKS_YUKON_EC 125 403#define SK_IM_USECS(x, t) ((x) * (t)) 404 405#define SK_IM_MIN 10 406#define SK_IM_DEFAULT 100 407#define SK_IM_MAX 10000 408 409/* 410 * The SK_EPROM0 register contains a byte that describes the 411 * amount of SRAM mounted on the NIC. The value also tells if 412 * the chips are 64K or 128K. This affects the RAMbuffer address 413 * offset that we need to use. 414 */ 415#define SK_RAMSIZE_512K_64 0x1 416#define SK_RAMSIZE_1024K_128 0x2 417#define SK_RAMSIZE_1024K_64 0x3 418#define SK_RAMSIZE_2048K_128 0x4 419 420#define SK_RBOFF_0 0x0 421#define SK_RBOFF_80000 0x80000 422 423/* 424 * SK_EEPROM1 contains the PHY type, which may be XMAC for 425 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 426 * PHY. 427 */ 428#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 429#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 430#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 431#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 432#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 433#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 434 435/* 436 * PHY addresses. 437 */ 438#define SK_PHYADDR_XMAC 0x0 439#define SK_PHYADDR_BCOM 0x1 440#define SK_PHYADDR_LONE 0x3 441#define SK_PHYADDR_NAT 0x0 442#define SK_PHYADDR_MARV 0x0 443 444#define SK_CONFIG_SINGLEMAC 0x01 445#define SK_CONFIG_DIS_DSL_CLK 0x02 446 447#define SK_PMD_1000BASELX 0x4C 448#define SK_PMD_1000BASESX 0x53 449#define SK_PMD_1000BASECX 0x43 450#define SK_PMD_1000BASETX 0x54 451 452/* GPIO bits */ 453#define SK_GPIO_DAT0 0x00000001 454#define SK_GPIO_DAT1 0x00000002 455#define SK_GPIO_DAT2 0x00000004 456#define SK_GPIO_DAT3 0x00000008 457#define SK_GPIO_DAT4 0x00000010 458#define SK_GPIO_DAT5 0x00000020 459#define SK_GPIO_DAT6 0x00000040 460#define SK_GPIO_DAT7 0x00000080 461#define SK_GPIO_DAT8 0x00000100 462#define SK_GPIO_DAT9 0x00000200 463#define SK_GPIO_DIR0 0x00010000 464#define SK_GPIO_DIR1 0x00020000 465#define SK_GPIO_DIR2 0x00040000 466#define SK_GPIO_DIR3 0x00080000 467#define SK_GPIO_DIR4 0x00100000 468#define SK_GPIO_DIR5 0x00200000 469#define SK_GPIO_DIR6 0x00400000 470#define SK_GPIO_DIR7 0x00800000 471#define SK_GPIO_DIR8 0x01000000 472#define SK_GPIO_DIR9 0x02000000 473 474#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */ 475 476#define SK_Y2_HWRES_LINK_1 0x01 477#define SK_Y2_HWRES_LINK_2 0x02 478#define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) 479#define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2) 480 481/* Block 3 Ram interface and MAC arbiter registers */ 482#define SK_RAMADDR 0x0180 483#define SK_RAMDATA0 0x0184 484#define SK_RAMDATA1 0x0188 485#define SK_TO0 0x0190 486#define SK_TO1 0x0191 487#define SK_TO2 0x0192 488#define SK_TO3 0x0193 489#define SK_TO4 0x0194 490#define SK_TO5 0x0195 491#define SK_TO6 0x0196 492#define SK_TO7 0x0197 493#define SK_TO8 0x0198 494#define SK_TO9 0x0199 495#define SK_TO10 0x019A 496#define SK_TO11 0x019B 497#define SK_RITIMEO_TMR 0x019C 498#define SK_RAMCTL 0x01A0 499#define SK_RITIMER_TST 0x01A2 500 501#define SK_RAMCTL_RESET 0x0001 502#define SK_RAMCTL_UNRESET 0x0002 503#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 504#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 505 506/* Mac arbiter registers */ 507#define SK_MINIT_RX1 0x01B0 508#define SK_MINIT_RX2 0x01B1 509#define SK_MINIT_TX1 0x01B2 510#define SK_MINIT_TX2 0x01B3 511#define SK_MTIMEO_RX1 0x01B4 512#define SK_MTIMEO_RX2 0x01B5 513#define SK_MTIMEO_TX1 0x01B6 514#define SK_MTIEMO_TX2 0x01B7 515#define SK_MACARB_CTL 0x01B8 516#define SK_MTIMER_TST 0x01BA 517#define SK_RCINIT_RX1 0x01C0 518#define SK_RCINIT_RX2 0x01C1 519#define SK_RCINIT_TX1 0x01C2 520#define SK_RCINIT_TX2 0x01C3 521#define SK_RCTIMEO_RX1 0x01C4 522#define SK_RCTIMEO_RX2 0x01C5 523#define SK_RCTIMEO_TX1 0x01C6 524#define SK_RCTIMEO_TX2 0x01C7 525#define SK_RECOVERY_CTL 0x01C8 526#define SK_RCTIMER_TST 0x01CA 527 528/* Packet arbiter registers */ 529#define SK_RXPA1_TINIT 0x01D0 530#define SK_RXPA2_TINIT 0x01D4 531#define SK_TXPA1_TINIT 0x01D8 532#define SK_TXPA2_TINIT 0x01DC 533#define SK_RXPA1_TIMEO 0x01E0 534#define SK_RXPA2_TIMEO 0x01E4 535#define SK_TXPA1_TIMEO 0x01E8 536#define SK_TXPA2_TIMEO 0x01EC 537#define SK_PKTARB_CTL 0x01F0 538#define SK_PKTATB_TST 0x01F2 539 540#define SK_PKTARB_TIMEOUT 0x2000 541 542#define SK_PKTARBCTL_RESET 0x0001 543#define SK_PKTARBCTL_UNRESET 0x0002 544#define SK_PKTARBCTL_RXTO1_OFF 0x0004 545#define SK_PKTARBCTL_RXTO1_ON 0x0008 546#define SK_PKTARBCTL_RXTO2_OFF 0x0010 547#define SK_PKTARBCTL_RXTO2_ON 0x0020 548#define SK_PKTARBCTL_TXTO1_OFF 0x0040 549#define SK_PKTARBCTL_TXTO1_ON 0x0080 550#define SK_PKTARBCTL_TXTO2_OFF 0x0100 551#define SK_PKTARBCTL_TXTO2_ON 0x0200 552#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 553#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 554#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 555#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 556 557#define SK_MINIT_XMAC_B2 54 558#define SK_MINIT_XMAC_C1 63 559 560#define SK_MACARBCTL_RESET 0x0001 561#define SK_MACARBCTL_UNRESET 0x0002 562#define SK_MACARBCTL_FASTOE_OFF 0x0004 563#define SK_MACARBCRL_FASTOE_ON 0x0008 564 565#define SK_RCINIT_XMAC_B2 54 566#define SK_RCINIT_XMAC_C1 0 567 568#define SK_RECOVERYCTL_RX1_OFF 0x0001 569#define SK_RECOVERYCTL_RX1_ON 0x0002 570#define SK_RECOVERYCTL_RX2_OFF 0x0004 571#define SK_RECOVERYCTL_RX2_ON 0x0008 572#define SK_RECOVERYCTL_TX1_OFF 0x0010 573#define SK_RECOVERYCTL_TX1_ON 0x0020 574#define SK_RECOVERYCTL_TX2_OFF 0x0040 575#define SK_RECOVERYCTL_TX2_ON 0x0080 576 577#define SK_RECOVERY_XMAC_B2 \ 578 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 579 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 580 581#define SK_RECOVERY_XMAC_C1 \ 582 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 583 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 584 585/* Block 4 -- TX Arbiter MAC 1 */ 586#define SK_TXAR1_TIMERINIT 0x0200 587#define SK_TXAR1_TIMERVAL 0x0204 588#define SK_TXAR1_LIMITINIT 0x0208 589#define SK_TXAR1_LIMITCNT 0x020C 590#define SK_TXAR1_COUNTERCTL 0x0210 591#define SK_TXAR1_COUNTERTST 0x0212 592#define SK_TXAR1_COUNTERSTS 0x0212 593 594/* Block 5 -- TX Arbiter MAC 2 */ 595#define SK_TXAR2_TIMERINIT 0x0280 596#define SK_TXAR2_TIMERVAL 0x0284 597#define SK_TXAR2_LIMITINIT 0x0288 598#define SK_TXAR2_LIMITCNT 0x028C 599#define SK_TXAR2_COUNTERCTL 0x0290 600#define SK_TXAR2_COUNTERTST 0x0291 601#define SK_TXAR2_COUNTERSTS 0x0292 602 603#define SK_TXARCTL_OFF 0x01 604#define SK_TXARCTL_ON 0x02 605#define SK_TXARCTL_RATECTL_OFF 0x04 606#define SK_TXARCTL_RATECTL_ON 0x08 607#define SK_TXARCTL_ALLOC_OFF 0x10 608#define SK_TXARCTL_ALLOC_ON 0x20 609#define SK_TXARCTL_FSYNC_OFF 0x40 610#define SK_TXARCTL_FSYNC_ON 0x80 611 612/* Block 6 -- External registers */ 613#define SK_EXTREG_BASE 0x300 614#define SK_EXTREG_END 0x37C 615 616/* Block 7 -- PCI config registers */ 617#define SK_PCI_BASE 0x0380 618#define SK_PCI_END 0x03FC 619 620/* Compute offset of mirrored PCI register */ 621#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 622 623/* Block 8 -- RX queue 1 */ 624#define SK_RXQ1_BUFCNT 0x0400 625#define SK_RXQ1_BUFCTL 0x0402 626#define SK_RXQ1_NEXTDESC 0x0404 627#define SK_RXQ1_RXBUF_LO 0x0408 628#define SK_RXQ1_RXBUF_HI 0x040C 629#define SK_RXQ1_RXSTAT 0x0410 630#define SK_RXQ1_TIMESTAMP 0x0414 631#define SK_RXQ1_CSUM1 0x0418 632#define SK_RXQ1_CSUM2 0x041A 633#define SK_RXQ1_CSUM1_START 0x041C 634#define SK_RXQ1_CSUM2_START 0x041E 635#define SK_RXQ1_CURADDR_LO 0x0420 636#define SK_RXQ1_CURADDR_HI 0x0424 637#define SK_RXQ1_CURCNT_LO 0x0428 638#define SK_RXQ1_CURCNT_HI 0x042C 639#define SK_RXQ1_CURBYTES 0x0430 640#define SK_RXQ1_BMU_CSR 0x0434 641#define SK_RXQ1_WATERMARK 0x0438 642#define SK_RXQ1_FLAG 0x043A 643#define SK_RXQ1_TEST1 0x043C 644#define SK_RXQ1_TEST2 0x0440 645#define SK_RXQ1_TEST3 0x0444 646 647/* Block 9 -- RX queue 2 */ 648#define SK_RXQ2_BUFCNT 0x0480 649#define SK_RXQ2_BUFCTL 0x0482 650#define SK_RXQ2_NEXTDESC 0x0484 651#define SK_RXQ2_RXBUF_LO 0x0488 652#define SK_RXQ2_RXBUF_HI 0x048C 653#define SK_RXQ2_RXSTAT 0x0490 654#define SK_RXQ2_TIMESTAMP 0x0494 655#define SK_RXQ2_CSUM1 0x0498 656#define SK_RXQ2_CSUM2 0x049A 657#define SK_RXQ2_CSUM1_START 0x049C 658#define SK_RXQ2_CSUM2_START 0x049E 659#define SK_RXQ2_CURADDR_LO 0x04A0 660#define SK_RXQ2_CURADDR_HI 0x04A4 661#define SK_RXQ2_CURCNT_LO 0x04A8 662#define SK_RXQ2_CURCNT_HI 0x04AC 663#define SK_RXQ2_CURBYTES 0x04B0 664#define SK_RXQ2_BMU_CSR 0x04B4 665#define SK_RXQ2_WATERMARK 0x04B8 666#define SK_RXQ2_FLAG 0x04BA 667#define SK_RXQ2_TEST1 0x04BC 668#define SK_RXQ2_TEST2 0x04C0 669#define SK_RXQ2_TEST3 0x04C4 670 671#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 672#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 673#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 674#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 675#define SK_RXBMU_RX_START 0x00000010 676#define SK_RXBMU_RX_STOP 0x00000020 677#define SK_RXBMU_POLL_OFF 0x00000040 678#define SK_RXBMU_POLL_ON 0x00000080 679#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 680#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 681#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 682#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 683#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 684#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 685#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 686#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 687#define SK_RXBMU_PFI_SM_RESET 0x00010000 688#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 689#define SK_RXBMU_FIFO_RESET 0x00040000 690#define SK_RXBMU_FIFO_UNRESET 0x00080000 691#define SK_RXBMU_DESC_RESET 0x00100000 692#define SK_RXBMU_DESC_UNRESET 0x00200000 693#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 694 695#define SK_RXBMU_ONLINE \ 696 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 697 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 698 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 699 SK_RXBMU_DESC_UNRESET) 700 701#define SK_RXBMU_OFFLINE \ 702 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 703 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 704 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 705 SK_RXBMU_DESC_RESET) 706 707/* Block 12 -- TX sync queue 1 */ 708#define SK_TXQS1_BUFCNT 0x0600 709#define SK_TXQS1_BUFCTL 0x0602 710#define SK_TXQS1_NEXTDESC 0x0604 711#define SK_TXQS1_RXBUF_LO 0x0608 712#define SK_TXQS1_RXBUF_HI 0x060C 713#define SK_TXQS1_RXSTAT 0x0610 714#define SK_TXQS1_CSUM_STARTVAL 0x0614 715#define SK_TXQS1_CSUM_STARTPOS 0x0618 716#define SK_TXQS1_CSUM_WRITEPOS 0x061A 717#define SK_TXQS1_CURADDR_LO 0x0620 718#define SK_TXQS1_CURADDR_HI 0x0624 719#define SK_TXQS1_CURCNT_LO 0x0628 720#define SK_TXQS1_CURCNT_HI 0x062C 721#define SK_TXQS1_CURBYTES 0x0630 722#define SK_TXQS1_BMU_CSR 0x0634 723#define SK_TXQS1_WATERMARK 0x0638 724#define SK_TXQS1_FLAG 0x063A 725#define SK_TXQS1_TEST1 0x063C 726#define SK_TXQS1_TEST2 0x0640 727#define SK_TXQS1_TEST3 0x0644 728 729/* Block 13 -- TX async queue 1 */ 730#define SK_TXQA1_BUFCNT 0x0680 731#define SK_TXQA1_BUFCTL 0x0682 732#define SK_TXQA1_NEXTDESC 0x0684 733#define SK_TXQA1_RXBUF_LO 0x0688 734#define SK_TXQA1_RXBUF_HI 0x068C 735#define SK_TXQA1_RXSTAT 0x0690 736#define SK_TXQA1_CSUM_STARTVAL 0x0694 737#define SK_TXQA1_CSUM_STARTPOS 0x0698 738#define SK_TXQA1_CSUM_WRITEPOS 0x069A 739#define SK_TXQA1_CURADDR_LO 0x06A0 740#define SK_TXQA1_CURADDR_HI 0x06A4 741#define SK_TXQA1_CURCNT_LO 0x06A8 742#define SK_TXQA1_CURCNT_HI 0x06AC 743#define SK_TXQA1_CURBYTES 0x06B0 744#define SK_TXQA1_BMU_CSR 0x06B4 745#define SK_TXQA1_WATERMARK 0x06B8 746#define SK_TXQA1_FLAG 0x06BA 747#define SK_TXQA1_TEST1 0x06BC 748#define SK_TXQA1_TEST2 0x06C0 749#define SK_TXQA1_TEST3 0x06C4 750 751/* Block 14 -- TX sync queue 2 */ 752#define SK_TXQS2_BUFCNT 0x0700 753#define SK_TXQS2_BUFCTL 0x0702 754#define SK_TXQS2_NEXTDESC 0x0704 755#define SK_TXQS2_RXBUF_LO 0x0708 756#define SK_TXQS2_RXBUF_HI 0x070C 757#define SK_TXQS2_RXSTAT 0x0710 758#define SK_TXQS2_CSUM_STARTVAL 0x0714 759#define SK_TXQS2_CSUM_STARTPOS 0x0718 760#define SK_TXQS2_CSUM_WRITEPOS 0x071A 761#define SK_TXQS2_CURADDR_LO 0x0720 762#define SK_TXQS2_CURADDR_HI 0x0724 763#define SK_TXQS2_CURCNT_LO 0x0728 764#define SK_TXQS2_CURCNT_HI 0x072C 765#define SK_TXQS2_CURBYTES 0x0730 766#define SK_TXQS2_BMU_CSR 0x0734 767#define SK_TXQS2_WATERMARK 0x0738 768#define SK_TXQS2_FLAG 0x073A 769#define SK_TXQS2_TEST1 0x073C 770#define SK_TXQS2_TEST2 0x0740 771#define SK_TXQS2_TEST3 0x0744 772 773/* Block 15 -- TX async queue 2 */ 774#define SK_TXQA2_BUFCNT 0x0780 775#define SK_TXQA2_BUFCTL 0x0782 776#define SK_TXQA2_NEXTDESC 0x0784 777#define SK_TXQA2_RXBUF_LO 0x0788 778#define SK_TXQA2_RXBUF_HI 0x078C 779#define SK_TXQA2_RXSTAT 0x0790 780#define SK_TXQA2_CSUM_STARTVAL 0x0794 781#define SK_TXQA2_CSUM_STARTPOS 0x0798 782#define SK_TXQA2_CSUM_WRITEPOS 0x079A 783#define SK_TXQA2_CURADDR_LO 0x07A0 784#define SK_TXQA2_CURADDR_HI 0x07A4 785#define SK_TXQA2_CURCNT_LO 0x07A8 786#define SK_TXQA2_CURCNT_HI 0x07AC 787#define SK_TXQA2_CURBYTES 0x07B0 788#define SK_TXQA2_BMU_CSR 0x07B4 789#define SK_TXQA2_WATERMARK 0x07B8 790#define SK_TXQA2_FLAG 0x07BA 791#define SK_TXQA2_TEST1 0x07BC 792#define SK_TXQA2_TEST2 0x07C0 793#define SK_TXQA2_TEST3 0x07C4 794 795#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 796#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 797#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 798#define SK_TXBMU_TX_START 0x00000010 799#define SK_TXBMU_TX_STOP 0x00000020 800#define SK_TXBMU_POLL_OFF 0x00000040 801#define SK_TXBMU_POLL_ON 0x00000080 802#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 803#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 804#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 805#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 806#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 807#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 808#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 809#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 810#define SK_TXBMU_PFI_SM_RESET 0x00010000 811#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 812#define SK_TXBMU_FIFO_RESET 0x00040000 813#define SK_TXBMU_FIFO_UNRESET 0x00080000 814#define SK_TXBMU_DESC_RESET 0x00100000 815#define SK_TXBMU_DESC_UNRESET 0x00200000 816#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 817 818#define SK_TXBMU_ONLINE \ 819 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 820 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 821 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 822 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON) 823 824#define SK_TXBMU_OFFLINE \ 825 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 826 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 827 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 828 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF) 829 830/* Block 16 -- Receive RAMbuffer 1 */ 831#define SK_RXRB1_START 0x0800 832#define SK_RXRB1_END 0x0804 833#define SK_RXRB1_WR_PTR 0x0808 834#define SK_RXRB1_RD_PTR 0x080C 835#define SK_RXRB1_UTHR_PAUSE 0x0810 836#define SK_RXRB1_LTHR_PAUSE 0x0814 837#define SK_RXRB1_UTHR_HIPRIO 0x0818 838#define SK_RXRB1_UTHR_LOPRIO 0x081C 839#define SK_RXRB1_PKTCNT 0x0820 840#define SK_RXRB1_LVL 0x0824 841#define SK_RXRB1_CTLTST 0x0828 842 843/* Block 17 -- Receive RAMbuffer 2 */ 844#define SK_RXRB2_START 0x0880 845#define SK_RXRB2_END 0x0884 846#define SK_RXRB2_WR_PTR 0x0888 847#define SK_RXRB2_RD_PTR 0x088C 848#define SK_RXRB2_UTHR_PAUSE 0x0890 849#define SK_RXRB2_LTHR_PAUSE 0x0894 850#define SK_RXRB2_UTHR_HIPRIO 0x0898 851#define SK_RXRB2_UTHR_LOPRIO 0x089C 852#define SK_RXRB2_PKTCNT 0x08A0 853#define SK_RXRB2_LVL 0x08A4 854#define SK_RXRB2_CTLTST 0x08A8 855 856/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 857#define SK_TXRBS1_START 0x0A00 858#define SK_TXRBS1_END 0x0A04 859#define SK_TXRBS1_WR_PTR 0x0A08 860#define SK_TXRBS1_RD_PTR 0x0A0C 861#define SK_TXRBS1_PKTCNT 0x0A20 862#define SK_TXRBS1_LVL 0x0A24 863#define SK_TXRBS1_CTLTST 0x0A28 864 865/* Block 21 -- Async. Transmit RAMbuffer 1 */ 866#define SK_TXRBA1_START 0x0A80 867#define SK_TXRBA1_END 0x0A84 868#define SK_TXRBA1_WR_PTR 0x0A88 869#define SK_TXRBA1_RD_PTR 0x0A8C 870#define SK_TXRBA1_PKTCNT 0x0AA0 871#define SK_TXRBA1_LVL 0x0AA4 872#define SK_TXRBA1_CTLTST 0x0AA8 873 874/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 875#define SK_TXRBS2_START 0x0B00 876#define SK_TXRBS2_END 0x0B04 877#define SK_TXRBS2_WR_PTR 0x0B08 878#define SK_TXRBS2_RD_PTR 0x0B0C 879#define SK_TXRBS2_PKTCNT 0x0B20 880#define SK_TXRBS2_LVL 0x0B24 881#define SK_TXRBS2_CTLTST 0x0B28 882 883/* Block 23 -- Async. Transmit RAMbuffer 2 */ 884#define SK_TXRBA2_START 0x0B80 885#define SK_TXRBA2_END 0x0B84 886#define SK_TXRBA2_WR_PTR 0x0B88 887#define SK_TXRBA2_RD_PTR 0x0B8C 888#define SK_TXRBA2_PKTCNT 0x0BA0 889#define SK_TXRBA2_LVL 0x0BA4 890#define SK_TXRBA2_CTLTST 0x0BA8 891 892#define SK_RBCTL_RESET 0x00000001 893#define SK_RBCTL_UNRESET 0x00000002 894#define SK_RBCTL_OFF 0x00000004 895#define SK_RBCTL_ON 0x00000008 896#define SK_RBCTL_STORENFWD_OFF 0x00000010 897#define SK_RBCTL_STORENFWD_ON 0x00000020 898 899/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 900#define SK_RXF1_END 0x0C00 901#define SK_RXF1_WPTR 0x0C04 902#define SK_RXF1_RPTR 0x0C0C 903#define SK_RXF1_PKTCNT 0x0C10 904#define SK_RXF1_LVL 0x0C14 905#define SK_RXF1_MACCTL 0x0C18 906#define SK_RXF1_CTL 0x0C1C 907#define SK_RXLED1_CNTINIT 0x0C20 908#define SK_RXLED1_COUNTER 0x0C24 909#define SK_RXLED1_CTL 0x0C28 910#define SK_RXLED1_TST 0x0C29 911#define SK_LINK_SYNC1_CINIT 0x0C30 912#define SK_LINK_SYNC1_COUNTER 0x0C34 913#define SK_LINK_SYNC1_CTL 0x0C38 914#define SK_LINK_SYNC1_TST 0x0C39 915#define SK_LINKLED1_CTL 0x0C3C 916 917#define SK_FIFO_END 0x3F 918 919/* Receive MAC FIFO 1 (Yukon Only) */ 920#define SK_RXMF1_END 0x0C40 921#define SK_RXMF1_THRESHOLD 0x0C44 922#define SK_RXMF1_CTRL_TEST 0x0C48 923#define SK_RXMF1_FLUSH_MASK 0x0C4C 924#define SK_RXMF1_FLUSH_THRESHOLD 0x0C50 925#define SK_RXMF1_WRITE_PTR 0x0C60 926#define SK_RXMF1_WRITE_LEVEL 0x0C68 927#define SK_RXMF1_READ_PTR 0x0C70 928#define SK_RXMF1_READ_LEVEL 0x0C78 929 930/* Receive MAC FIFO 1 Contro/Test */ 931#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 932#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 933#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 934#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 935#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 936#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 937#define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */ 938#define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */ 939#define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */ 940#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 941#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 942#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 943#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 944#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 945 946#define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */ 947 948/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 949#define SK_RXF2_END 0x0C80 950#define SK_RXF2_WPTR 0x0C84 951#define SK_RXF2_RPTR 0x0C8C 952#define SK_RXF2_PKTCNT 0x0C90 953#define SK_RXF2_LVL 0x0C94 954#define SK_RXF2_MACCTL 0x0C98 955#define SK_RXF2_CTL 0x0C9C 956#define SK_RXLED2_CNTINIT 0x0CA0 957#define SK_RXLED2_COUNTER 0x0CA4 958#define SK_RXLED2_CTL 0x0CA8 959#define SK_RXLED2_TST 0x0CA9 960#define SK_LINK_SYNC2_CINIT 0x0CB0 961#define SK_LINK_SYNC2_COUNTER 0x0CB4 962#define SK_LINK_SYNC2_CTL 0x0CB8 963#define SK_LINK_SYNC2_TST 0x0CB9 964#define SK_LINKLED2_CTL 0x0CBC 965 966#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 967#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 968#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 969#define SK_RXMACCTL_RSTAMP_ON 0x00000008 970#define SK_RXMACCTL_FLUSH_OFF 0x00000010 971#define SK_RXMACCTL_FLUSH_ON 0x00000020 972#define SK_RXMACCTL_PAUSE_OFF 0x00000040 973#define SK_RXMACCTL_PAUSE_ON 0x00000080 974#define SK_RXMACCTL_AFULL_OFF 0x00000100 975#define SK_RXMACCTL_AFULL_ON 0x00000200 976#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 977#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 978#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 979#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 980#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 981#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 982 983#define SK_RXLEDCTL_ENABLE 0x0001 984#define SK_RXLEDCTL_COUNTER_STOP 0x0002 985#define SK_RXLEDCTL_COUNTER_START 0x0004 986 987#define SK_LINKLED_OFF 0x0001 988#define SK_LINKLED_ON 0x0002 989#define SK_LINKLED_LINKSYNC_OFF 0x0004 990#define SK_LINKLED_LINKSYNC_ON 0x0008 991#define SK_LINKLED_BLINK_OFF 0x0010 992#define SK_LINKLED_BLINK_ON 0x0020 993 994/* Block 26 -- TX MAC FIFO 1 regisrers */ 995#define SK_TXF1_END 0x0D00 996#define SK_TXF1_WPTR 0x0D04 997#define SK_TXF1_RPTR 0x0D0C 998#define SK_TXF1_PKTCNT 0x0D10 999#define SK_TXF1_LVL 0x0D14 1000#define SK_TXF1_MACCTL 0x0D18 1001#define SK_TXF1_CTL 0x0D1C 1002#define SK_TXLED1_CNTINIT 0x0D20 1003#define SK_TXLED1_COUNTER 0x0D24 1004#define SK_TXLED1_CTL 0x0D28 1005#define SK_TXLED1_TST 0x0D29 1006 1007/* Transmit MAC FIFO 1 (Yukon Only) */ 1008#define SK_TXMF1_END 0x0D40 1009#define SK_TXMF1_THRESHOLD 0x0D44 1010#define SK_TXMF1_CTRL_TEST 0x0D48 1011#define SK_TXMF1_WRITE_PTR 0x0D60 1012#define SK_TXMF1_WRITE_SHADOW 0x0D64 1013#define SK_TXMF1_WRITE_LEVEL 0x0D68 1014#define SK_TXMF1_READ_PTR 0x0D70 1015#define SK_TXMF1_RESTART_PTR 0x0D74 1016#define SK_TXMF1_READ_LEVEL 0x0D78 1017 1018/* Transmit MAC FIFO Control/Test */ 1019#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 1020#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 1021#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 1022#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 1023#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 1024#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 1025#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 1026#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 1027#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 1028#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 1029#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 1030#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 1031#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 1032 1033/* Block 27 -- TX MAC FIFO 2 regisrers */ 1034#define SK_TXF2_END 0x0D80 1035#define SK_TXF2_WPTR 0x0D84 1036#define SK_TXF2_RPTR 0x0D8C 1037#define SK_TXF2_PKTCNT 0x0D90 1038#define SK_TXF2_LVL 0x0D94 1039#define SK_TXF2_MACCTL 0x0D98 1040#define SK_TXF2_CTL 0x0D9C 1041#define SK_TXLED2_CNTINIT 0x0DA0 1042#define SK_TXLED2_COUNTER 0x0DA4 1043#define SK_TXLED2_CTL 0x0DA8 1044#define SK_TXLED2_TST 0x0DA9 1045 1046#define SK_TXMACCTL_XMAC_RESET 0x00000001 1047#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 1048#define SK_TXMACCTL_LOOP_OFF 0x00000004 1049#define SK_TXMACCTL_LOOP_ON 0x00000008 1050#define SK_TXMACCTL_FLUSH_OFF 0x00000010 1051#define SK_TXMACCTL_FLUSH_ON 0x00000020 1052#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1053#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1054#define SK_TXMACCTL_AFULL_OFF 0x00000100 1055#define SK_TXMACCTL_AFULL_ON 0x00000200 1056#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1057#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1058#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1059#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1060#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1061#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1062 1063#define SK_TXLEDCTL_ENABLE 0x0001 1064#define SK_TXLEDCTL_COUNTER_STOP 0x0002 1065#define SK_TXLEDCTL_COUNTER_START 0x0004 1066 1067#define SK_FIFO_RESET 0x00000001 1068#define SK_FIFO_UNRESET 0x00000002 1069#define SK_FIFO_OFF 0x00000004 1070#define SK_FIFO_ON 0x00000008 1071 1072/* Block 28 -- Descriptor Poll Timer */ 1073#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1074#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1075 1076#define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */ 1077 1078#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1079#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1080#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1081 1082#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1083#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1084#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1085#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1086 1087/* Block 29 -- reserved */ 1088 1089/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1090#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1091#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1092#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1093#define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */ 1094#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1095#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1096#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1097#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1098#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1099#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1100#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1101#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1102#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1103#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1104#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1105#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1106#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1107#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1108#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1109#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1110#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1111#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1112#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1113#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1114#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1115#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1116#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1117#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1118#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1119 1120#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1121#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1122#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1123#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1124#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1125#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1126 1127#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1128#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1129#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1130#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1131#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1132#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1133#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1134#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1135#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1136#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1137#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1138#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1139#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1140#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1141#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1142#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1143#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1144#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1145#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1146#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1147#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1148#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1149#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1150 1151#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1152 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1153#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1154 SK_GPHY_HWCFG_M_2 ) 1155#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1156 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1157 1158#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1159#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1160#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1161#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1162#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1163#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1164 1165#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1166#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1167 1168/* Block 31 -- reserved */ 1169 1170/* Block 32-33 -- Pattern Ram */ 1171#define SK_WOL_PRAM 0x1000 1172 1173/* Block 0x22 - 0x3f -- reserved */ 1174 1175/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1176#define SK_XMAC1_BASE 0x2000 1177 1178/* Block 0x50 to 0x5F -- MARV 1 registers */ 1179#define SK_MARV1_BASE 0x2800 1180 1181/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1182#define SK_XMAC2_BASE 0x3000 1183 1184/* Block 0x70 to 0x7F -- MARV 2 registers */ 1185#define SK_MARV2_BASE 0x3800 1186 1187/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1188#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1189 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1190 1191#if 0 1192#define SK_XM_READ_4(sc, reg) \ 1193 ((sk_win_read_2(sc->sk_softc, \ 1194 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1195 ((sk_win_read_2(sc->sk_softc, \ 1196 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1197 1198#define SK_XM_WRITE_4(sc, reg, val) \ 1199 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1200 ((val) & 0xFFFF)); \ 1201 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1202 ((val) >> 16) & 0xFFFF) 1203#else 1204#define SK_XM_READ_4(sc, reg) \ 1205 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1206 1207#define SK_XM_WRITE_4(sc, reg, val) \ 1208 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1209#endif 1210 1211#define SK_XM_READ_2(sc, reg) \ 1212 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1213 1214#define SK_XM_WRITE_2(sc, reg, val) \ 1215 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1216 1217#define SK_XM_SETBIT_4(sc, reg, x) \ 1218 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1219 1220#define SK_XM_CLRBIT_4(sc, reg, x) \ 1221 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1222 1223#define SK_XM_SETBIT_2(sc, reg, x) \ 1224 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1225 1226#define SK_XM_CLRBIT_2(sc, reg, x) \ 1227 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1228 1229/* Compute relative offset of an MARV register in the MARV window(s). */ 1230#define SK_YU_REG(sc, reg) \ 1231 ((reg) + SK_MARV1_BASE + \ 1232 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1233 1234#define SK_YU_READ_4(sc, reg) \ 1235 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1236 1237#define SK_YU_READ_2(sc, reg) \ 1238 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1239 1240#define SK_YU_WRITE_4(sc, reg, val) \ 1241 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1242 1243#define SK_YU_WRITE_2(sc, reg, val) \ 1244 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1245 1246#define SK_YU_SETBIT_4(sc, reg, x) \ 1247 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1248 1249#define SK_YU_CLRBIT_4(sc, reg, x) \ 1250 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1251 1252#define SK_YU_SETBIT_2(sc, reg, x) \ 1253 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1254 1255#define SK_YU_CLRBIT_2(sc, reg, x) \ 1256 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1257 1258/* 1259 * The default FIFO threshold on the XMAC II is 4 bytes. On 1260 * dual port NICs, this often leads to transmit underruns, so we 1261 * bump the threshold a little. 1262 */ 1263#define SK_XM_TX_FIFOTHRESH 512 1264 1265#define SK_PCI_VENDOR_ID 0x0000 1266#define SK_PCI_DEVICE_ID 0x0002 1267#define SK_PCI_COMMAND 0x0004 1268#define SK_PCI_STATUS 0x0006 1269#define SK_PCI_REVID 0x0008 1270#define SK_PCI_CLASSCODE 0x0009 1271#define SK_PCI_CACHELEN 0x000C 1272#define SK_PCI_LATENCY_TIMER 0x000D 1273#define SK_PCI_HEADER_TYPE 0x000E 1274#define SK_PCI_LOMEM 0x0010 1275#define SK_PCI_LOIO 0x0014 1276#define SK_PCI_SUBVEN_ID 0x002C 1277#define SK_PCI_SYBSYS_ID 0x002E 1278#define SK_PCI_BIOSROM 0x0030 1279#define SK_PCI_INTLINE 0x003C 1280#define SK_PCI_INTPIN 0x003D 1281#define SK_PCI_MINGNT 0x003E 1282#define SK_PCI_MINLAT 0x003F 1283 1284/* device specific PCI registers */ 1285#define SK_PCI_OURREG1 0x0040 1286#define SK_PCI_OURREG2 0x0044 1287#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1288#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1289#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1290#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1291#define SK_PCI_PME_EVENT 0x004F 1292#define SK_PCI_VPD_CAPID 0x0050 1293#define SK_PCI_VPD_NEXTPTR 0x0051 1294#define SK_PCI_VPD_ADDR 0x0052 1295#define SK_PCI_VPD_DATA 0x0054 1296 1297#define SK_PSTATE_MASK 0x0003 1298#define SK_PSTATE_D0 0x0000 1299#define SK_PSTATE_D1 0x0001 1300#define SK_PSTATE_D2 0x0002 1301#define SK_PSTATE_D3 0x0003 1302#define SK_PME_EN 0x0010 1303#define SK_PME_STATUS 0x8000 1304 1305/* 1306 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1307 * read is complete. Set to 1 to initiate a write, will become 0 1308 * when write is finished. 1309 */ 1310#define SK_VPD_FLAG 0x8000 1311 1312/* VPD structures */ 1313struct vpd_res { 1314 u_int8_t vr_id; 1315 u_int8_t vr_len; 1316 u_int8_t vr_pad; 1317}; 1318 1319struct vpd_key { 1320 char vk_key[2]; 1321 u_int8_t vk_len; 1322}; 1323 1324#define VPD_RES_ID 0x82 /* ID string */ 1325#define VPD_RES_READ 0x90 /* start of read only area */ 1326#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1327#define VPD_RES_END 0x78 /* end tag */ 1328 1329#define CSR_WRITE_4(sc, reg, val) \ 1330 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1331#define CSR_WRITE_2(sc, reg, val) \ 1332 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1333#define CSR_WRITE_1(sc, reg, val) \ 1334 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1335 1336#define CSR_READ_4(sc, reg) \ 1337 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1338#define CSR_READ_2(sc, reg) \ 1339 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1340#define CSR_READ_1(sc, reg) \ 1341 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1342 1343struct sk_type { 1344 u_int16_t sk_vid; 1345 u_int16_t sk_did; 1346 char *sk_name; 1347}; 1348 1349#define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 1350#define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32) 1351 1352#define SK_RING_ALIGN 64 1353 1354/* RX queue descriptor data structure */ 1355struct sk_rx_desc { 1356 u_int32_t sk_ctl; 1357 u_int32_t sk_next; 1358 u_int32_t sk_data_lo; 1359 u_int32_t sk_data_hi; 1360 u_int32_t sk_xmac_rxstat; 1361 u_int32_t sk_timestamp; 1362 u_int32_t sk_csum; 1363 u_int32_t sk_csum_start; 1364}; 1365 1366#define SK_OPCODE_DEFAULT 0x00550000 1367#define SK_OPCODE_CSUM 0x00560000 1368 1369#define SK_RXCTL_LEN 0x0000FFFF 1370#define SK_RXCTL_OPCODE 0x00FF0000 1371#define SK_RXCTL_TSTAMP_VALID 0x01000000 1372#define SK_RXCTL_STATUS_VALID 0x02000000 1373#define SK_RXCTL_DEV0 0x04000000 1374#define SK_RXCTL_EOF_INTR 0x08000000 1375#define SK_RXCTL_EOB_INTR 0x10000000 1376#define SK_RXCTL_LASTFRAG 0x20000000 1377#define SK_RXCTL_FIRSTFRAG 0x40000000 1378#define SK_RXCTL_OWN 0x80000000 1379 1380#define SK_RXSTAT \ 1381 (SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1382 1383struct sk_tx_desc { 1384 u_int32_t sk_ctl; 1385 u_int32_t sk_next; 1386 u_int32_t sk_data_lo; 1387 u_int32_t sk_data_hi; 1388 u_int32_t sk_xmac_txstat; 1389 u_int32_t sk_csum_startval; 1390 u_int32_t sk_csum_start; 1391 u_int32_t sk_rsvd1; 1392}; 1393 1394#define SK_TXCTL_LEN 0x0000FFFF 1395#define SK_TXCTL_OPCODE 0x00FF0000 1396#define SK_TXCTL_SW 0x01000000 1397#define SK_TXCTL_NOCRC 0x02000000 1398#define SK_TXCTL_STORENFWD 0x04000000 1399#define SK_TXCTL_EOF_INTR 0x08000000 1400#define SK_TXCTL_EOB_INTR 0x10000000 1401#define SK_TXCTL_LASTFRAG 0x20000000 1402#define SK_TXCTL_FIRSTFRAG 0x40000000 1403#define SK_TXCTL_OWN 0x80000000 1404 1405#define SK_TXSTAT \ 1406 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1407 1408#define SK_RXBYTES(x) ((x) & 0x0000FFFF) 1409#define SK_TXBYTES SK_RXBYTES 1410 1411#define SK_TX_RING_CNT 512 1412#define SK_RX_RING_CNT 256 1413#define SK_JUMBO_RX_RING_CNT 256 1414#define SK_MAXTXSEGS 32 1415#define SK_MAXRXSEGS 32 1416 1417/* 1418 * Jumbo buffer stuff. Note that we must allocate more jumbo 1419 * buffers than there are descriptors in the receive ring. This 1420 * is because we don't know how long it will take for a packet 1421 * to be released after we hand it off to the upper protocol 1422 * layers. To be safe, we allocate 1.5 times the number of 1423 * receive descriptors. 1424 */ 1425#define SK_JUMBO_FRAMELEN 9018 1426#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1427#define SK_MAX_FRAMELEN \ 1428 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 1429#define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 1430#define SK_JSLOTS ((SK_RX_RING_CNT * 3) / 2) 1431 1432#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1433#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1434 (SK_JRAWLEN % sizeof(u_int64_t)))) 1435#define SK_JPAGESZ PAGE_SIZE 1436#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1437#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1438 1439struct sk_jpool_entry { 1440 int slot; 1441 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1442}; 1443 1444struct sk_txdesc { 1445 struct mbuf *tx_m; 1446 bus_dmamap_t tx_dmamap; 1447 STAILQ_ENTRY(sk_txdesc) tx_q; 1448}; 1449 1450STAILQ_HEAD(sk_txdq, sk_txdesc); 1451 1452struct sk_rxdesc { 1453 struct mbuf *rx_m; 1454 bus_dmamap_t rx_dmamap; 1455}; 1456 1457struct sk_chain_data { 1458 bus_dma_tag_t sk_parent_tag; 1459 bus_dma_tag_t sk_tx_tag; 1460 struct sk_txdesc sk_txdesc[SK_TX_RING_CNT]; 1461 struct sk_txdq sk_txfreeq; 1462 struct sk_txdq sk_txbusyq; 1463 bus_dma_tag_t sk_rx_tag; 1464 struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT]; 1465 bus_dma_tag_t sk_tx_ring_tag; 1466 bus_dma_tag_t sk_rx_ring_tag; 1467 bus_dmamap_t sk_tx_ring_map; 1468 bus_dmamap_t sk_rx_ring_map; 1469 bus_dmamap_t sk_rx_sparemap; 1470 bus_dma_tag_t sk_jumbo_rx_tag; 1471 bus_dma_tag_t sk_jumbo_tag; 1472 bus_dmamap_t sk_jumbo_map; 1473 bus_dma_tag_t sk_jumbo_mtag; 1474 caddr_t sk_jslots[SK_JSLOTS]; 1475 struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT]; 1476 bus_dma_tag_t sk_jumbo_rx_ring_tag; 1477 bus_dmamap_t sk_jumbo_rx_ring_map; 1478 bus_dmamap_t sk_jumbo_rx_sparemap; 1479 int sk_tx_prod; 1480 int sk_tx_cons; 1481 int sk_tx_cnt; 1482 int sk_rx_cons; 1483 int sk_jumbo_rx_cons; 1484}; 1485 1486struct sk_ring_data { 1487 struct sk_tx_desc *sk_tx_ring; 1488 bus_addr_t sk_tx_ring_paddr; 1489 struct sk_rx_desc *sk_rx_ring; 1490 bus_addr_t sk_rx_ring_paddr; 1491 struct sk_rx_desc *sk_jumbo_rx_ring; 1492 bus_addr_t sk_jumbo_rx_ring_paddr; 1493 void *sk_jumbo_buf; 1494 bus_addr_t sk_jumbo_buf_paddr; 1495}; 1496 1497#define SK_TX_RING_ADDR(sc, i) \ 1498 ((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i)) 1499#define SK_RX_RING_ADDR(sc, i) \ 1500 ((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1501#define SK_JUMBO_RX_RING_ADDR(sc, i) \ 1502 ((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1503 1504#define SK_TX_RING_SZ \ 1505 (sizeof(struct sk_tx_desc) * SK_TX_RING_CNT) 1506#define SK_RX_RING_SZ \ 1507 (sizeof(struct sk_rx_desc) * SK_RX_RING_CNT) 1508#define SK_JUMBO_RX_RING_SZ \ 1509 (sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT) 1510 1511struct sk_bcom_hack { 1512 int reg; 1513 int val; 1514}; 1515 1516#define SK_INC(x, y) (x) = (x + 1) % y 1517 1518/* Forward decl. */ 1519struct sk_if_softc; 1520 1521/* Softc for the GEnesis controller. */ 1522struct sk_softc { 1523 bus_space_handle_t sk_bhandle; /* bus space handle */ 1524 bus_space_tag_t sk_btag; /* bus space tag */ 1525 void *sk_intrhand; /* irq handler handle */ 1526 struct resource *sk_irq; /* IRQ resource handle */ 1527 struct resource *sk_res; /* I/O or shared mem handle */ 1528 device_t sk_dev; 1529 u_int8_t sk_type; 1530 u_int8_t sk_rev; 1531 u_int8_t spare; 1532 char *sk_vpd_prodname; 1533 char *sk_vpd_readonly; 1534 uint16_t sk_vpd_readonly_len; 1535 u_int32_t sk_rboff; /* RAMbuffer offset */ 1536 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1537 u_int32_t sk_pmd; /* physical media type */ 1538 u_int32_t sk_intrmask; 1539 int sk_int_mod; 1540 int sk_int_ticks; 1541 int sk_suspended; 1542 struct sk_if_softc *sk_if[2]; 1543 device_t sk_devs[2]; 1544 struct mtx sk_mii_mtx; 1545 struct mtx sk_mtx; 1546}; 1547 1548#define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1549#define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1550#define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1551#define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc) 1552#define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc) 1553#define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc) 1554#define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx) 1555#define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx) 1556 1557/* Softc for each logical interface */ 1558struct sk_if_softc { 1559 struct ifnet *sk_ifp; /* interface info */ 1560 device_t sk_miibus; 1561 device_t sk_if_dev; 1562 u_int8_t sk_port; /* port # on controller */ 1563 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1564 u_int32_t sk_rx_ramstart; 1565 u_int32_t sk_rx_ramend; 1566 u_int32_t sk_tx_ramstart; 1567 u_int32_t sk_tx_ramend; 1568 int sk_phytype; 1569 int sk_phyaddr; 1570 int sk_link; 1571 struct callout sk_tick_ch; 1572 struct sk_chain_data sk_cdata; 1573 struct sk_ring_data sk_rdata; 1574 struct sk_softc *sk_softc; /* parent controller */ 1575 int sk_tx_bmu; /* TX BMU register */ 1576 int sk_if_flags; 1577 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1578 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1579 struct mtx sk_jlist_mtx; 1580}; 1581 1582#define SK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->sk_jlist_mtx) 1583#define SK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_jlist_mtx) 1584 1585#define SK_TIMEOUT 1000 1586