if_skreg.h revision 151341
1/* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/sk/if_skreg.h 151341 2005-10-14 18:51:30Z jhb $ 35 */ 36 37/*- 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53/* Values to keep the different chip revisions apart (SK_CHIPVER). */ 54#define SK_GENESIS 0x0A 55#define SK_YUKON 0xB0 56#define SK_YUKON_LITE 0xB1 57#define SK_YUKON_LP 0xB2 58#define SK_YUKON_FAMILY(x) ((x) & 0xB0) 59 60/* Known revisions in SK_CONFIG. */ 61#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */ 62#define SK_YUKON_LITE_REV_A1 0x3 63#define SK_YUKON_LITE_REV_A3 0x7 64 65/* 66 * SysKonnect PCI vendor ID 67 */ 68#define VENDORID_SK 0x1148 69 70/* 71 * Marvell PCI vendor ID 72 */ 73#define VENDORID_MARVELL 0x11AB 74 75/* 76 * SK-NET gigabit ethernet device IDs 77 */ 78#define DEVICEID_SK_V1 0x4300 79#define DEVICEID_SK_V2 0x4320 80 81/* 82 * Belkin F5D5005 83 */ 84#define DEVICEID_BELKIN_5005 0x5005 85 86/* 87 * 3Com PCI vendor ID 88 */ 89#define VENDORID_3COM 0x10b7 90 91/* 92 * 3Com gigabit ethernet device ID 93 */ 94#define DEVICEID_3COM_3C940 0x1700 95 96/* 97 * Linksys PCI vendor ID 98 */ 99#define VENDORID_LINKSYS 0x1737 100 101/* 102 * Linksys gigabit ethernet device ID 103 */ 104#define DEVICEID_LINKSYS_EG1032 0x1032 105 106/* 107 * Linksys gigabit ethernet rev 2 sub-device ID 108 */ 109#define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015 110 111/* 112 * D-Link PCI vendor ID 113 */ 114#define VENDORID_DLINK 0x1186 115 116/* 117 * D-Link gigabit ethernet device ID 118 */ 119#define DEVICEID_DLINK_DGE530T 0x4c00 120 121/* 122 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 123 * but internally it has a 16K register space. This 16K space is 124 * divided into 128-byte blocks. The first 128 bytes of the I/O 125 * window represent the first block, which is permanently mapped 126 * at the start of the window. The other 127 blocks can be mapped 127 * to the second 128 bytes of the I/O window by setting the desired 128 * block value in the RAP register in block 0. Not all of the 127 129 * blocks are actually used. Most registers are 32 bits wide, but 130 * there are a few 16-bit and 8-bit ones as well. 131 */ 132 133 134/* Start of remappable register window. */ 135#define SK_WIN_BASE 0x0080 136 137/* Size of a window */ 138#define SK_WIN_LEN 0x80 139 140#define SK_WIN_MASK 0x3F80 141#define SK_REG_MASK 0x7F 142 143/* Compute the window of a given register (for the RAP register) */ 144#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 145 146/* Compute the relative offset of a register within the window */ 147#define SK_REG(reg) ((reg) & SK_REG_MASK) 148 149#define SK_PORT_A 0 150#define SK_PORT_B 1 151 152/* 153 * Compute offset of port-specific register. Since there are two 154 * ports, there are two of some GEnesis modules (e.g. two sets of 155 * DMA queues, two sets of FIFO control registers, etc...). Normally, 156 * the block for port 0 is at offset 0x0 and the block for port 1 is 157 * at offset 0x80 (i.e. the next page over). However for the transmit 158 * BMUs and RAMbuffers, there are two blocks for each port: one for 159 * the sync transmit queue and one for the async queue (which we don't 160 * use). However instead of ordering them like this: 161 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 162 * SysKonnect has instead ordered them like this: 163 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 164 * This means that when referencing the TX BMU and RAMbuffer registers, 165 * we have to double the block offset (0x80 * 2) in order to reach the 166 * second queue. This prevents us from using the same formula 167 * (sk_port * 0x80) to compute the offsets for all of the port-specific 168 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 169 * The simplest thing is to provide an extra argument to these macros: 170 * the 'skip' parameter. The 'skip' value is the number of extra pages 171 * for skip when computing the port0/port1 offsets. For most registers, 172 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 173 */ 174#define SK_IF_READ_4(sc_if, skip, reg) \ 175 sk_win_read_4(sc_if->sk_softc, reg + \ 176 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 177#define SK_IF_READ_2(sc_if, skip, reg) \ 178 sk_win_read_2(sc_if->sk_softc, reg + \ 179 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 180#define SK_IF_READ_1(sc_if, skip, reg) \ 181 sk_win_read_1(sc_if->sk_softc, reg + \ 182 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 183 184#define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 185 sk_win_write_4(sc_if->sk_softc, \ 186 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 187#define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 188 sk_win_write_2(sc_if->sk_softc, \ 189 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 190#define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 191 sk_win_write_1(sc_if->sk_softc, \ 192 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 193 194/* Block 0 registers, permanently mapped at iobase. */ 195#define SK_RAP 0x0000 196#define SK_CSR 0x0004 197#define SK_LED 0x0006 198#define SK_ISR 0x0008 /* interrupt source */ 199#define SK_IMR 0x000C /* interrupt mask */ 200#define SK_IESR 0x0010 /* interrupt hardware error source */ 201#define SK_IEMR 0x0014 /* interrupt hardware error mask */ 202#define SK_ISSR 0x0018 /* special interrupt source */ 203#define SK_XM_IMR0 0x0020 204#define SK_XM_ISR0 0x0028 205#define SK_XM_PHYADDR0 0x0030 206#define SK_XM_PHYDATA0 0x0034 207#define SK_XM_IMR1 0x0040 208#define SK_XM_ISR1 0x0048 209#define SK_XM_PHYADDR1 0x0050 210#define SK_XM_PHYDATA1 0x0054 211#define SK_BMU_RX_CSR0 0x0060 212#define SK_BMU_RX_CSR1 0x0064 213#define SK_BMU_TXS_CSR0 0x0068 214#define SK_BMU_TXA_CSR0 0x006C 215#define SK_BMU_TXS_CSR1 0x0070 216#define SK_BMU_TXA_CSR1 0x0074 217 218/* SK_CSR register */ 219#define SK_CSR_SW_RESET 0x0001 220#define SK_CSR_SW_UNRESET 0x0002 221#define SK_CSR_MASTER_RESET 0x0004 222#define SK_CSR_MASTER_UNRESET 0x0008 223#define SK_CSR_MASTER_STOP 0x0010 224#define SK_CSR_MASTER_DONE 0x0020 225#define SK_CSR_SW_IRQ_CLEAR 0x0040 226#define SK_CSR_SW_IRQ_SET 0x0080 227#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 228#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 229 230/* SK_LED register */ 231#define SK_LED_GREEN_OFF 0x01 232#define SK_LED_GREEN_ON 0x02 233 234/* SK_ISR register */ 235#define SK_ISR_TX2_AS_CHECK 0x00000001 236#define SK_ISR_TX2_AS_EOF 0x00000002 237#define SK_ISR_TX2_AS_EOB 0x00000004 238#define SK_ISR_TX2_S_CHECK 0x00000008 239#define SK_ISR_TX2_S_EOF 0x00000010 240#define SK_ISR_TX2_S_EOB 0x00000020 241#define SK_ISR_TX1_AS_CHECK 0x00000040 242#define SK_ISR_TX1_AS_EOF 0x00000080 243#define SK_ISR_TX1_AS_EOB 0x00000100 244#define SK_ISR_TX1_S_CHECK 0x00000200 245#define SK_ISR_TX1_S_EOF 0x00000400 246#define SK_ISR_TX1_S_EOB 0x00000800 247#define SK_ISR_RX2_CHECK 0x00001000 248#define SK_ISR_RX2_EOF 0x00002000 249#define SK_ISR_RX2_EOB 0x00004000 250#define SK_ISR_RX1_CHECK 0x00008000 251#define SK_ISR_RX1_EOF 0x00010000 252#define SK_ISR_RX1_EOB 0x00020000 253#define SK_ISR_LINK2_OFLOW 0x00040000 254#define SK_ISR_MAC2 0x00080000 255#define SK_ISR_LINK1_OFLOW 0x00100000 256#define SK_ISR_MAC1 0x00200000 257#define SK_ISR_TIMER 0x00400000 258#define SK_ISR_EXTERNAL_REG 0x00800000 259#define SK_ISR_SW 0x01000000 260#define SK_ISR_I2C_RDY 0x02000000 261#define SK_ISR_TX2_TIMEO 0x04000000 262#define SK_ISR_TX1_TIMEO 0x08000000 263#define SK_ISR_RX2_TIMEO 0x10000000 264#define SK_ISR_RX1_TIMEO 0x20000000 265#define SK_ISR_RSVD 0x40000000 266#define SK_ISR_HWERR 0x80000000 267 268/* SK_IMR register */ 269#define SK_IMR_TX2_AS_CHECK 0x00000001 270#define SK_IMR_TX2_AS_EOF 0x00000002 271#define SK_IMR_TX2_AS_EOB 0x00000004 272#define SK_IMR_TX2_S_CHECK 0x00000008 273#define SK_IMR_TX2_S_EOF 0x00000010 274#define SK_IMR_TX2_S_EOB 0x00000020 275#define SK_IMR_TX1_AS_CHECK 0x00000040 276#define SK_IMR_TX1_AS_EOF 0x00000080 277#define SK_IMR_TX1_AS_EOB 0x00000100 278#define SK_IMR_TX1_S_CHECK 0x00000200 279#define SK_IMR_TX1_S_EOF 0x00000400 280#define SK_IMR_TX1_S_EOB 0x00000800 281#define SK_IMR_RX2_CHECK 0x00001000 282#define SK_IMR_RX2_EOF 0x00002000 283#define SK_IMR_RX2_EOB 0x00004000 284#define SK_IMR_RX1_CHECK 0x00008000 285#define SK_IMR_RX1_EOF 0x00010000 286#define SK_IMR_RX1_EOB 0x00020000 287#define SK_IMR_LINK2_OFLOW 0x00040000 288#define SK_IMR_MAC2 0x00080000 289#define SK_IMR_LINK1_OFLOW 0x00100000 290#define SK_IMR_MAC1 0x00200000 291#define SK_IMR_TIMER 0x00400000 292#define SK_IMR_EXTERNAL_REG 0x00800000 293#define SK_IMR_SW 0x01000000 294#define SK_IMR_I2C_RDY 0x02000000 295#define SK_IMR_TX2_TIMEO 0x04000000 296#define SK_IMR_TX1_TIMEO 0x08000000 297#define SK_IMR_RX2_TIMEO 0x10000000 298#define SK_IMR_RX1_TIMEO 0x20000000 299#define SK_IMR_RSVD 0x40000000 300#define SK_IMR_HWERR 0x80000000 301 302#define SK_INTRS1 \ 303 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 304 305#define SK_INTRS2 \ 306 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 307 308/* SK_IESR register */ 309#define SK_IESR_PAR_RX2 0x00000001 310#define SK_IESR_PAR_RX1 0x00000002 311#define SK_IESR_PAR_MAC2 0x00000004 312#define SK_IESR_PAR_MAC1 0x00000008 313#define SK_IESR_PAR_WR_RAM 0x00000010 314#define SK_IESR_PAR_RD_RAM 0x00000020 315#define SK_IESR_NO_TSTAMP_MAC2 0x00000040 316#define SK_IESR_NO_TSTAMO_MAC1 0x00000080 317#define SK_IESR_NO_STS_MAC2 0x00000100 318#define SK_IESR_NO_STS_MAC1 0x00000200 319#define SK_IESR_IRQ_STS 0x00000400 320#define SK_IESR_MASTERERR 0x00000800 321 322/* SK_IEMR register */ 323#define SK_IEMR_PAR_RX2 0x00000001 324#define SK_IEMR_PAR_RX1 0x00000002 325#define SK_IEMR_PAR_MAC2 0x00000004 326#define SK_IEMR_PAR_MAC1 0x00000008 327#define SK_IEMR_PAR_WR_RAM 0x00000010 328#define SK_IEMR_PAR_RD_RAM 0x00000020 329#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 330#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 331#define SK_IEMR_NO_STS_MAC2 0x00000100 332#define SK_IEMR_NO_STS_MAC1 0x00000200 333#define SK_IEMR_IRQ_STS 0x00000400 334#define SK_IEMR_MASTERERR 0x00000800 335 336/* Block 2 */ 337#define SK_MAC0_0 0x0100 338#define SK_MAC0_1 0x0104 339#define SK_MAC1_0 0x0108 340#define SK_MAC1_1 0x010C 341#define SK_MAC2_0 0x0110 342#define SK_MAC2_1 0x0114 343#define SK_CONNTYPE 0x0118 344#define SK_PMDTYPE 0x0119 345#define SK_CONFIG 0x011A 346#define SK_CHIPVER 0x011B 347#define SK_EPROM0 0x011C 348#define SK_EPROM1 0x011D 349#define SK_EPROM2 0x011E 350#define SK_EPROM3 0x011F 351#define SK_EP_ADDR 0x0120 352#define SK_EP_DATA 0x0124 353#define SK_EP_LOADCTL 0x0128 354#define SK_EP_LOADTST 0x0129 355#define SK_TIMERINIT 0x0130 356#define SK_TIMER 0x0134 357#define SK_TIMERCTL 0x0138 358#define SK_TIMERTST 0x0139 359#define SK_IMTIMERINIT 0x0140 360#define SK_IMTIMER 0x0144 361#define SK_IMTIMERCTL 0x0148 362#define SK_IMTIMERTST 0x0149 363#define SK_IMMR 0x014C 364#define SK_IHWEMR 0x0150 365#define SK_TESTCTL1 0x0158 366#define SK_TESTCTL2 0x0159 367#define SK_GPIO 0x015C 368#define SK_I2CHWCTL 0x0160 369#define SK_I2CHWDATA 0x0164 370#define SK_I2CHWIRQ 0x0168 371#define SK_I2CSW 0x016C 372#define SK_BLNKINIT 0x0170 373#define SK_BLNKCOUNT 0x0174 374#define SK_BLNKCTL 0x0178 375#define SK_BLNKSTS 0x0179 376#define SK_BLNKTST 0x017A 377 378#define SK_IMCTL_STOP 0x02 379#define SK_IMCTL_START 0x04 380 381#define SK_IMTIMER_TICKS 54 382#define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 383 384#define SK_IM_MIN 10 385#define SK_IM_DEFAULT 100 386#define SK_IM_MAX 10000 387 388/* 389 * The SK_EPROM0 register contains a byte that describes the 390 * amount of SRAM mounted on the NIC. The value also tells if 391 * the chips are 64K or 128K. This affects the RAMbuffer address 392 * offset that we need to use. 393 */ 394#define SK_RAMSIZE_512K_64 0x1 395#define SK_RAMSIZE_1024K_128 0x2 396#define SK_RAMSIZE_1024K_64 0x3 397#define SK_RAMSIZE_2048K_128 0x4 398 399#define SK_RBOFF_0 0x0 400#define SK_RBOFF_80000 0x80000 401 402/* 403 * SK_EEPROM1 contains the PHY type, which may be XMAC for 404 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 405 * PHY. 406 */ 407#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 408#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 409#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 410#define SK_PHYTYPE_NAT 3 /* National DP83891 */ 411#define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 412#define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 413 414/* 415 * PHY addresses. 416 */ 417#define SK_PHYADDR_XMAC 0x0 418#define SK_PHYADDR_BCOM 0x1 419#define SK_PHYADDR_LONE 0x3 420#define SK_PHYADDR_NAT 0x0 421#define SK_PHYADDR_MARV 0x0 422 423#define SK_CONFIG_SINGLEMAC 0x01 424#define SK_CONFIG_DIS_DSL_CLK 0x02 425 426#define SK_PMD_1000BASELX 0x4C 427#define SK_PMD_1000BASESX 0x53 428#define SK_PMD_1000BASECX 0x43 429#define SK_PMD_1000BASETX 0x54 430 431/* GPIO bits */ 432#define SK_GPIO_DAT0 0x00000001 433#define SK_GPIO_DAT1 0x00000002 434#define SK_GPIO_DAT2 0x00000004 435#define SK_GPIO_DAT3 0x00000008 436#define SK_GPIO_DAT4 0x00000010 437#define SK_GPIO_DAT5 0x00000020 438#define SK_GPIO_DAT6 0x00000040 439#define SK_GPIO_DAT7 0x00000080 440#define SK_GPIO_DAT8 0x00000100 441#define SK_GPIO_DAT9 0x00000200 442#define SK_GPIO_DIR0 0x00010000 443#define SK_GPIO_DIR1 0x00020000 444#define SK_GPIO_DIR2 0x00040000 445#define SK_GPIO_DIR3 0x00080000 446#define SK_GPIO_DIR4 0x00100000 447#define SK_GPIO_DIR5 0x00200000 448#define SK_GPIO_DIR6 0x00400000 449#define SK_GPIO_DIR7 0x00800000 450#define SK_GPIO_DIR8 0x01000000 451#define SK_GPIO_DIR9 0x02000000 452 453/* Block 3 Ram interface and MAC arbiter registers */ 454#define SK_RAMADDR 0x0180 455#define SK_RAMDATA0 0x0184 456#define SK_RAMDATA1 0x0188 457#define SK_TO0 0x0190 458#define SK_TO1 0x0191 459#define SK_TO2 0x0192 460#define SK_TO3 0x0193 461#define SK_TO4 0x0194 462#define SK_TO5 0x0195 463#define SK_TO6 0x0196 464#define SK_TO7 0x0197 465#define SK_TO8 0x0198 466#define SK_TO9 0x0199 467#define SK_TO10 0x019A 468#define SK_TO11 0x019B 469#define SK_RITIMEO_TMR 0x019C 470#define SK_RAMCTL 0x01A0 471#define SK_RITIMER_TST 0x01A2 472 473#define SK_RAMCTL_RESET 0x0001 474#define SK_RAMCTL_UNRESET 0x0002 475#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 476#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 477 478/* Mac arbiter registers */ 479#define SK_MINIT_RX1 0x01B0 480#define SK_MINIT_RX2 0x01B1 481#define SK_MINIT_TX1 0x01B2 482#define SK_MINIT_TX2 0x01B3 483#define SK_MTIMEO_RX1 0x01B4 484#define SK_MTIMEO_RX2 0x01B5 485#define SK_MTIMEO_TX1 0x01B6 486#define SK_MTIEMO_TX2 0x01B7 487#define SK_MACARB_CTL 0x01B8 488#define SK_MTIMER_TST 0x01BA 489#define SK_RCINIT_RX1 0x01C0 490#define SK_RCINIT_RX2 0x01C1 491#define SK_RCINIT_TX1 0x01C2 492#define SK_RCINIT_TX2 0x01C3 493#define SK_RCTIMEO_RX1 0x01C4 494#define SK_RCTIMEO_RX2 0x01C5 495#define SK_RCTIMEO_TX1 0x01C6 496#define SK_RCTIMEO_TX2 0x01C7 497#define SK_RECOVERY_CTL 0x01C8 498#define SK_RCTIMER_TST 0x01CA 499 500/* Packet arbiter registers */ 501#define SK_RXPA1_TINIT 0x01D0 502#define SK_RXPA2_TINIT 0x01D4 503#define SK_TXPA1_TINIT 0x01D8 504#define SK_TXPA2_TINIT 0x01DC 505#define SK_RXPA1_TIMEO 0x01E0 506#define SK_RXPA2_TIMEO 0x01E4 507#define SK_TXPA1_TIMEO 0x01E8 508#define SK_TXPA2_TIMEO 0x01EC 509#define SK_PKTARB_CTL 0x01F0 510#define SK_PKTATB_TST 0x01F2 511 512#define SK_PKTARB_TIMEOUT 0x2000 513 514#define SK_PKTARBCTL_RESET 0x0001 515#define SK_PKTARBCTL_UNRESET 0x0002 516#define SK_PKTARBCTL_RXTO1_OFF 0x0004 517#define SK_PKTARBCTL_RXTO1_ON 0x0008 518#define SK_PKTARBCTL_RXTO2_OFF 0x0010 519#define SK_PKTARBCTL_RXTO2_ON 0x0020 520#define SK_PKTARBCTL_TXTO1_OFF 0x0040 521#define SK_PKTARBCTL_TXTO1_ON 0x0080 522#define SK_PKTARBCTL_TXTO2_OFF 0x0100 523#define SK_PKTARBCTL_TXTO2_ON 0x0200 524#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 525#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 526#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 527#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 528 529#define SK_MINIT_XMAC_B2 54 530#define SK_MINIT_XMAC_C1 63 531 532#define SK_MACARBCTL_RESET 0x0001 533#define SK_MACARBCTL_UNRESET 0x0002 534#define SK_MACARBCTL_FASTOE_OFF 0x0004 535#define SK_MACARBCRL_FASTOE_ON 0x0008 536 537#define SK_RCINIT_XMAC_B2 54 538#define SK_RCINIT_XMAC_C1 0 539 540#define SK_RECOVERYCTL_RX1_OFF 0x0001 541#define SK_RECOVERYCTL_RX1_ON 0x0002 542#define SK_RECOVERYCTL_RX2_OFF 0x0004 543#define SK_RECOVERYCTL_RX2_ON 0x0008 544#define SK_RECOVERYCTL_TX1_OFF 0x0010 545#define SK_RECOVERYCTL_TX1_ON 0x0020 546#define SK_RECOVERYCTL_TX2_OFF 0x0040 547#define SK_RECOVERYCTL_TX2_ON 0x0080 548 549#define SK_RECOVERY_XMAC_B2 \ 550 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 551 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 552 553#define SK_RECOVERY_XMAC_C1 \ 554 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 555 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 556 557/* Block 4 -- TX Arbiter MAC 1 */ 558#define SK_TXAR1_TIMERINIT 0x0200 559#define SK_TXAR1_TIMERVAL 0x0204 560#define SK_TXAR1_LIMITINIT 0x0208 561#define SK_TXAR1_LIMITCNT 0x020C 562#define SK_TXAR1_COUNTERCTL 0x0210 563#define SK_TXAR1_COUNTERTST 0x0212 564#define SK_TXAR1_COUNTERSTS 0x0212 565 566/* Block 5 -- TX Arbiter MAC 2 */ 567#define SK_TXAR2_TIMERINIT 0x0280 568#define SK_TXAR2_TIMERVAL 0x0284 569#define SK_TXAR2_LIMITINIT 0x0288 570#define SK_TXAR2_LIMITCNT 0x028C 571#define SK_TXAR2_COUNTERCTL 0x0290 572#define SK_TXAR2_COUNTERTST 0x0291 573#define SK_TXAR2_COUNTERSTS 0x0292 574 575#define SK_TXARCTL_OFF 0x01 576#define SK_TXARCTL_ON 0x02 577#define SK_TXARCTL_RATECTL_OFF 0x04 578#define SK_TXARCTL_RATECTL_ON 0x08 579#define SK_TXARCTL_ALLOC_OFF 0x10 580#define SK_TXARCTL_ALLOC_ON 0x20 581#define SK_TXARCTL_FSYNC_OFF 0x40 582#define SK_TXARCTL_FSYNC_ON 0x80 583 584/* Block 6 -- External registers */ 585#define SK_EXTREG_BASE 0x300 586#define SK_EXTREG_END 0x37C 587 588/* Block 7 -- PCI config registers */ 589#define SK_PCI_BASE 0x0380 590#define SK_PCI_END 0x03FC 591 592/* Compute offset of mirrored PCI register */ 593#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 594 595/* Block 8 -- RX queue 1 */ 596#define SK_RXQ1_BUFCNT 0x0400 597#define SK_RXQ1_BUFCTL 0x0402 598#define SK_RXQ1_NEXTDESC 0x0404 599#define SK_RXQ1_RXBUF_LO 0x0408 600#define SK_RXQ1_RXBUF_HI 0x040C 601#define SK_RXQ1_RXSTAT 0x0410 602#define SK_RXQ1_TIMESTAMP 0x0414 603#define SK_RXQ1_CSUM1 0x0418 604#define SK_RXQ1_CSUM2 0x041A 605#define SK_RXQ1_CSUM1_START 0x041C 606#define SK_RXQ1_CSUM2_START 0x041E 607#define SK_RXQ1_CURADDR_LO 0x0420 608#define SK_RXQ1_CURADDR_HI 0x0424 609#define SK_RXQ1_CURCNT_LO 0x0428 610#define SK_RXQ1_CURCNT_HI 0x042C 611#define SK_RXQ1_CURBYTES 0x0430 612#define SK_RXQ1_BMU_CSR 0x0434 613#define SK_RXQ1_WATERMARK 0x0438 614#define SK_RXQ1_FLAG 0x043A 615#define SK_RXQ1_TEST1 0x043C 616#define SK_RXQ1_TEST2 0x0440 617#define SK_RXQ1_TEST3 0x0444 618 619/* Block 9 -- RX queue 2 */ 620#define SK_RXQ2_BUFCNT 0x0480 621#define SK_RXQ2_BUFCTL 0x0482 622#define SK_RXQ2_NEXTDESC 0x0484 623#define SK_RXQ2_RXBUF_LO 0x0488 624#define SK_RXQ2_RXBUF_HI 0x048C 625#define SK_RXQ2_RXSTAT 0x0490 626#define SK_RXQ2_TIMESTAMP 0x0494 627#define SK_RXQ2_CSUM1 0x0498 628#define SK_RXQ2_CSUM2 0x049A 629#define SK_RXQ2_CSUM1_START 0x049C 630#define SK_RXQ2_CSUM2_START 0x049E 631#define SK_RXQ2_CURADDR_LO 0x04A0 632#define SK_RXQ2_CURADDR_HI 0x04A4 633#define SK_RXQ2_CURCNT_LO 0x04A8 634#define SK_RXQ2_CURCNT_HI 0x04AC 635#define SK_RXQ2_CURBYTES 0x04B0 636#define SK_RXQ2_BMU_CSR 0x04B4 637#define SK_RXQ2_WATERMARK 0x04B8 638#define SK_RXQ2_FLAG 0x04BA 639#define SK_RXQ2_TEST1 0x04BC 640#define SK_RXQ2_TEST2 0x04C0 641#define SK_RXQ2_TEST3 0x04C4 642 643#define SK_RXBMU_CLR_IRQ_ERR 0x00000001 644#define SK_RXBMU_CLR_IRQ_EOF 0x00000002 645#define SK_RXBMU_CLR_IRQ_EOB 0x00000004 646#define SK_RXBMU_CLR_IRQ_PAR 0x00000008 647#define SK_RXBMU_RX_START 0x00000010 648#define SK_RXBMU_RX_STOP 0x00000020 649#define SK_RXBMU_POLL_OFF 0x00000040 650#define SK_RXBMU_POLL_ON 0x00000080 651#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 652#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 653#define SK_RXBMU_DESCWR_SM_RESET 0x00000400 654#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 655#define SK_RXBMU_DESCRD_SM_RESET 0x00001000 656#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 657#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 658#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 659#define SK_RXBMU_PFI_SM_RESET 0x00010000 660#define SK_RXBMU_PFI_SM_UNRESET 0x00020000 661#define SK_RXBMU_FIFO_RESET 0x00040000 662#define SK_RXBMU_FIFO_UNRESET 0x00080000 663#define SK_RXBMU_DESC_RESET 0x00100000 664#define SK_RXBMU_DESC_UNRESET 0x00200000 665#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 666 667#define SK_RXBMU_ONLINE \ 668 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 669 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 670 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 671 SK_RXBMU_DESC_UNRESET) 672 673#define SK_RXBMU_OFFLINE \ 674 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 675 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 676 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 677 SK_RXBMU_DESC_RESET) 678 679/* Block 12 -- TX sync queue 1 */ 680#define SK_TXQS1_BUFCNT 0x0600 681#define SK_TXQS1_BUFCTL 0x0602 682#define SK_TXQS1_NEXTDESC 0x0604 683#define SK_TXQS1_RXBUF_LO 0x0608 684#define SK_TXQS1_RXBUF_HI 0x060C 685#define SK_TXQS1_RXSTAT 0x0610 686#define SK_TXQS1_CSUM_STARTVAL 0x0614 687#define SK_TXQS1_CSUM_STARTPOS 0x0618 688#define SK_TXQS1_CSUM_WRITEPOS 0x061A 689#define SK_TXQS1_CURADDR_LO 0x0620 690#define SK_TXQS1_CURADDR_HI 0x0624 691#define SK_TXQS1_CURCNT_LO 0x0628 692#define SK_TXQS1_CURCNT_HI 0x062C 693#define SK_TXQS1_CURBYTES 0x0630 694#define SK_TXQS1_BMU_CSR 0x0634 695#define SK_TXQS1_WATERMARK 0x0638 696#define SK_TXQS1_FLAG 0x063A 697#define SK_TXQS1_TEST1 0x063C 698#define SK_TXQS1_TEST2 0x0640 699#define SK_TXQS1_TEST3 0x0644 700 701/* Block 13 -- TX async queue 1 */ 702#define SK_TXQA1_BUFCNT 0x0680 703#define SK_TXQA1_BUFCTL 0x0682 704#define SK_TXQA1_NEXTDESC 0x0684 705#define SK_TXQA1_RXBUF_LO 0x0688 706#define SK_TXQA1_RXBUF_HI 0x068C 707#define SK_TXQA1_RXSTAT 0x0690 708#define SK_TXQA1_CSUM_STARTVAL 0x0694 709#define SK_TXQA1_CSUM_STARTPOS 0x0698 710#define SK_TXQA1_CSUM_WRITEPOS 0x069A 711#define SK_TXQA1_CURADDR_LO 0x06A0 712#define SK_TXQA1_CURADDR_HI 0x06A4 713#define SK_TXQA1_CURCNT_LO 0x06A8 714#define SK_TXQA1_CURCNT_HI 0x06AC 715#define SK_TXQA1_CURBYTES 0x06B0 716#define SK_TXQA1_BMU_CSR 0x06B4 717#define SK_TXQA1_WATERMARK 0x06B8 718#define SK_TXQA1_FLAG 0x06BA 719#define SK_TXQA1_TEST1 0x06BC 720#define SK_TXQA1_TEST2 0x06C0 721#define SK_TXQA1_TEST3 0x06C4 722 723/* Block 14 -- TX sync queue 2 */ 724#define SK_TXQS2_BUFCNT 0x0700 725#define SK_TXQS2_BUFCTL 0x0702 726#define SK_TXQS2_NEXTDESC 0x0704 727#define SK_TXQS2_RXBUF_LO 0x0708 728#define SK_TXQS2_RXBUF_HI 0x070C 729#define SK_TXQS2_RXSTAT 0x0710 730#define SK_TXQS2_CSUM_STARTVAL 0x0714 731#define SK_TXQS2_CSUM_STARTPOS 0x0718 732#define SK_TXQS2_CSUM_WRITEPOS 0x071A 733#define SK_TXQS2_CURADDR_LO 0x0720 734#define SK_TXQS2_CURADDR_HI 0x0724 735#define SK_TXQS2_CURCNT_LO 0x0728 736#define SK_TXQS2_CURCNT_HI 0x072C 737#define SK_TXQS2_CURBYTES 0x0730 738#define SK_TXQS2_BMU_CSR 0x0734 739#define SK_TXQS2_WATERMARK 0x0738 740#define SK_TXQS2_FLAG 0x073A 741#define SK_TXQS2_TEST1 0x073C 742#define SK_TXQS2_TEST2 0x0740 743#define SK_TXQS2_TEST3 0x0744 744 745/* Block 15 -- TX async queue 2 */ 746#define SK_TXQA2_BUFCNT 0x0780 747#define SK_TXQA2_BUFCTL 0x0782 748#define SK_TXQA2_NEXTDESC 0x0784 749#define SK_TXQA2_RXBUF_LO 0x0788 750#define SK_TXQA2_RXBUF_HI 0x078C 751#define SK_TXQA2_RXSTAT 0x0790 752#define SK_TXQA2_CSUM_STARTVAL 0x0794 753#define SK_TXQA2_CSUM_STARTPOS 0x0798 754#define SK_TXQA2_CSUM_WRITEPOS 0x079A 755#define SK_TXQA2_CURADDR_LO 0x07A0 756#define SK_TXQA2_CURADDR_HI 0x07A4 757#define SK_TXQA2_CURCNT_LO 0x07A8 758#define SK_TXQA2_CURCNT_HI 0x07AC 759#define SK_TXQA2_CURBYTES 0x07B0 760#define SK_TXQA2_BMU_CSR 0x07B4 761#define SK_TXQA2_WATERMARK 0x07B8 762#define SK_TXQA2_FLAG 0x07BA 763#define SK_TXQA2_TEST1 0x07BC 764#define SK_TXQA2_TEST2 0x07C0 765#define SK_TXQA2_TEST3 0x07C4 766 767#define SK_TXBMU_CLR_IRQ_ERR 0x00000001 768#define SK_TXBMU_CLR_IRQ_EOF 0x00000002 769#define SK_TXBMU_CLR_IRQ_EOB 0x00000004 770#define SK_TXBMU_TX_START 0x00000010 771#define SK_TXBMU_TX_STOP 0x00000020 772#define SK_TXBMU_POLL_OFF 0x00000040 773#define SK_TXBMU_POLL_ON 0x00000080 774#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 775#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 776#define SK_TXBMU_DESCWR_SM_RESET 0x00000400 777#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 778#define SK_TXBMU_DESCRD_SM_RESET 0x00001000 779#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 780#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 781#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 782#define SK_TXBMU_PFI_SM_RESET 0x00010000 783#define SK_TXBMU_PFI_SM_UNRESET 0x00020000 784#define SK_TXBMU_FIFO_RESET 0x00040000 785#define SK_TXBMU_FIFO_UNRESET 0x00080000 786#define SK_TXBMU_DESC_RESET 0x00100000 787#define SK_TXBMU_DESC_UNRESET 0x00200000 788#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 789 790#define SK_TXBMU_ONLINE \ 791 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 792 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 793 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 794 SK_TXBMU_DESC_UNRESET) 795 796#define SK_TXBMU_OFFLINE \ 797 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 798 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 799 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 800 SK_TXBMU_DESC_RESET) 801 802/* Block 16 -- Receive RAMbuffer 1 */ 803#define SK_RXRB1_START 0x0800 804#define SK_RXRB1_END 0x0804 805#define SK_RXRB1_WR_PTR 0x0808 806#define SK_RXRB1_RD_PTR 0x080C 807#define SK_RXRB1_UTHR_PAUSE 0x0810 808#define SK_RXRB1_LTHR_PAUSE 0x0814 809#define SK_RXRB1_UTHR_HIPRIO 0x0818 810#define SK_RXRB1_UTHR_LOPRIO 0x081C 811#define SK_RXRB1_PKTCNT 0x0820 812#define SK_RXRB1_LVL 0x0824 813#define SK_RXRB1_CTLTST 0x0828 814 815/* Block 17 -- Receive RAMbuffer 2 */ 816#define SK_RXRB2_START 0x0880 817#define SK_RXRB2_END 0x0884 818#define SK_RXRB2_WR_PTR 0x0888 819#define SK_RXRB2_RD_PTR 0x088C 820#define SK_RXRB2_UTHR_PAUSE 0x0890 821#define SK_RXRB2_LTHR_PAUSE 0x0894 822#define SK_RXRB2_UTHR_HIPRIO 0x0898 823#define SK_RXRB2_UTHR_LOPRIO 0x089C 824#define SK_RXRB2_PKTCNT 0x08A0 825#define SK_RXRB2_LVL 0x08A4 826#define SK_RXRB2_CTLTST 0x08A8 827 828/* Block 20 -- Sync. Transmit RAMbuffer 1 */ 829#define SK_TXRBS1_START 0x0A00 830#define SK_TXRBS1_END 0x0A04 831#define SK_TXRBS1_WR_PTR 0x0A08 832#define SK_TXRBS1_RD_PTR 0x0A0C 833#define SK_TXRBS1_PKTCNT 0x0A20 834#define SK_TXRBS1_LVL 0x0A24 835#define SK_TXRBS1_CTLTST 0x0A28 836 837/* Block 21 -- Async. Transmit RAMbuffer 1 */ 838#define SK_TXRBA1_START 0x0A80 839#define SK_TXRBA1_END 0x0A84 840#define SK_TXRBA1_WR_PTR 0x0A88 841#define SK_TXRBA1_RD_PTR 0x0A8C 842#define SK_TXRBA1_PKTCNT 0x0AA0 843#define SK_TXRBA1_LVL 0x0AA4 844#define SK_TXRBA1_CTLTST 0x0AA8 845 846/* Block 22 -- Sync. Transmit RAMbuffer 2 */ 847#define SK_TXRBS2_START 0x0B00 848#define SK_TXRBS2_END 0x0B04 849#define SK_TXRBS2_WR_PTR 0x0B08 850#define SK_TXRBS2_RD_PTR 0x0B0C 851#define SK_TXRBS2_PKTCNT 0x0B20 852#define SK_TXRBS2_LVL 0x0B24 853#define SK_TXRBS2_CTLTST 0x0B28 854 855/* Block 23 -- Async. Transmit RAMbuffer 2 */ 856#define SK_TXRBA2_START 0x0B80 857#define SK_TXRBA2_END 0x0B84 858#define SK_TXRBA2_WR_PTR 0x0B88 859#define SK_TXRBA2_RD_PTR 0x0B8C 860#define SK_TXRBA2_PKTCNT 0x0BA0 861#define SK_TXRBA2_LVL 0x0BA4 862#define SK_TXRBA2_CTLTST 0x0BA8 863 864#define SK_RBCTL_RESET 0x00000001 865#define SK_RBCTL_UNRESET 0x00000002 866#define SK_RBCTL_OFF 0x00000004 867#define SK_RBCTL_ON 0x00000008 868#define SK_RBCTL_STORENFWD_OFF 0x00000010 869#define SK_RBCTL_STORENFWD_ON 0x00000020 870 871/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 872#define SK_RXF1_END 0x0C00 873#define SK_RXF1_WPTR 0x0C04 874#define SK_RXF1_RPTR 0x0C0C 875#define SK_RXF1_PKTCNT 0x0C10 876#define SK_RXF1_LVL 0x0C14 877#define SK_RXF1_MACCTL 0x0C18 878#define SK_RXF1_CTL 0x0C1C 879#define SK_RXLED1_CNTINIT 0x0C20 880#define SK_RXLED1_COUNTER 0x0C24 881#define SK_RXLED1_CTL 0x0C28 882#define SK_RXLED1_TST 0x0C29 883#define SK_LINK_SYNC1_CINIT 0x0C30 884#define SK_LINK_SYNC1_COUNTER 0x0C34 885#define SK_LINK_SYNC1_CTL 0x0C38 886#define SK_LINK_SYNC1_TST 0x0C39 887#define SK_LINKLED1_CTL 0x0C3C 888 889#define SK_FIFO_END 0x3F 890 891/* Receive MAC FIFO 1 (Yukon Only) */ 892#define SK_RXMF1_END 0x0C40 893#define SK_RXMF1_THRESHOLD 0x0C44 894#define SK_RXMF1_CTRL_TEST 0x0C48 895#define SK_RXMF1_WRITE_PTR 0x0C60 896#define SK_RXMF1_WRITE_LEVEL 0x0C68 897#define SK_RXMF1_READ_PTR 0x0C70 898#define SK_RXMF1_READ_LEVEL 0x0C78 899 900#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 901#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 902#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 903#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 904#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 905#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 906#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 907#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 908#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 909#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 910#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 911#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 912 913/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 914#define SK_RXF2_END 0x0C80 915#define SK_RXF2_WPTR 0x0C84 916#define SK_RXF2_RPTR 0x0C8C 917#define SK_RXF2_PKTCNT 0x0C90 918#define SK_RXF2_LVL 0x0C94 919#define SK_RXF2_MACCTL 0x0C98 920#define SK_RXF2_CTL 0x0C9C 921#define SK_RXLED2_CNTINIT 0x0CA0 922#define SK_RXLED2_COUNTER 0x0CA4 923#define SK_RXLED2_CTL 0x0CA8 924#define SK_RXLED2_TST 0x0CA9 925#define SK_LINK_SYNC2_CINIT 0x0CB0 926#define SK_LINK_SYNC2_COUNTER 0x0CB4 927#define SK_LINK_SYNC2_CTL 0x0CB8 928#define SK_LINK_SYNC2_TST 0x0CB9 929#define SK_LINKLED2_CTL 0x0CBC 930 931#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 932#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 933#define SK_RXMACCTL_TSTAMP_OFF 0x00000004 934#define SK_RXMACCTL_RSTAMP_ON 0x00000008 935#define SK_RXMACCTL_FLUSH_OFF 0x00000010 936#define SK_RXMACCTL_FLUSH_ON 0x00000020 937#define SK_RXMACCTL_PAUSE_OFF 0x00000040 938#define SK_RXMACCTL_PAUSE_ON 0x00000080 939#define SK_RXMACCTL_AFULL_OFF 0x00000100 940#define SK_RXMACCTL_AFULL_ON 0x00000200 941#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 942#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 943#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 944#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 945#define SK_RXMACCTL_STS_TIMEO 0x00FF0000 946#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 947 948#define SK_RXLEDCTL_ENABLE 0x0001 949#define SK_RXLEDCTL_COUNTER_STOP 0x0002 950#define SK_RXLEDCTL_COUNTER_START 0x0004 951 952#define SK_LINKLED_OFF 0x0001 953#define SK_LINKLED_ON 0x0002 954#define SK_LINKLED_LINKSYNC_OFF 0x0004 955#define SK_LINKLED_LINKSYNC_ON 0x0008 956#define SK_LINKLED_BLINK_OFF 0x0010 957#define SK_LINKLED_BLINK_ON 0x0020 958 959/* Block 26 -- TX MAC FIFO 1 regisrers */ 960#define SK_TXF1_END 0x0D00 961#define SK_TXF1_WPTR 0x0D04 962#define SK_TXF1_RPTR 0x0D0C 963#define SK_TXF1_PKTCNT 0x0D10 964#define SK_TXF1_LVL 0x0D14 965#define SK_TXF1_MACCTL 0x0D18 966#define SK_TXF1_CTL 0x0D1C 967#define SK_TXLED1_CNTINIT 0x0D20 968#define SK_TXLED1_COUNTER 0x0D24 969#define SK_TXLED1_CTL 0x0D28 970#define SK_TXLED1_TST 0x0D29 971 972/* Receive MAC FIFO 1 (Yukon Only) */ 973#define SK_TXMF1_END 0x0D40 974#define SK_TXMF1_THRESHOLD 0x0D44 975#define SK_TXMF1_CTRL_TEST 0x0D48 976#define SK_TXMF1_WRITE_PTR 0x0D60 977#define SK_TXMF1_WRITE_SHADOW 0x0D64 978#define SK_TXMF1_WRITE_LEVEL 0x0D68 979#define SK_TXMF1_READ_PTR 0x0D70 980#define SK_TXMF1_RESTART_PTR 0x0D74 981#define SK_TXMF1_READ_LEVEL 0x0D78 982 983#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 984#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 985#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 986#define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 987#define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 988#define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 989#define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 990#define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 991#define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 992#define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 993#define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 994#define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 995#define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 996 997/* Block 27 -- TX MAC FIFO 2 regisrers */ 998#define SK_TXF2_END 0x0D80 999#define SK_TXF2_WPTR 0x0D84 1000#define SK_TXF2_RPTR 0x0D8C 1001#define SK_TXF2_PKTCNT 0x0D90 1002#define SK_TXF2_LVL 0x0D94 1003#define SK_TXF2_MACCTL 0x0D98 1004#define SK_TXF2_CTL 0x0D9C 1005#define SK_TXLED2_CNTINIT 0x0DA0 1006#define SK_TXLED2_COUNTER 0x0DA4 1007#define SK_TXLED2_CTL 0x0DA8 1008#define SK_TXLED2_TST 0x0DA9 1009 1010#define SK_TXMACCTL_XMAC_RESET 0x00000001 1011#define SK_TXMACCTL_XMAC_UNRESET 0x00000002 1012#define SK_TXMACCTL_LOOP_OFF 0x00000004 1013#define SK_TXMACCTL_LOOP_ON 0x00000008 1014#define SK_TXMACCTL_FLUSH_OFF 0x00000010 1015#define SK_TXMACCTL_FLUSH_ON 0x00000020 1016#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1017#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1018#define SK_TXMACCTL_AFULL_OFF 0x00000100 1019#define SK_TXMACCTL_AFULL_ON 0x00000200 1020#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1021#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1022#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1023#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1024#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1025#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1026 1027#define SK_TXLEDCTL_ENABLE 0x0001 1028#define SK_TXLEDCTL_COUNTER_STOP 0x0002 1029#define SK_TXLEDCTL_COUNTER_START 0x0004 1030 1031#define SK_FIFO_RESET 0x00000001 1032#define SK_FIFO_UNRESET 0x00000002 1033#define SK_FIFO_OFF 0x00000004 1034#define SK_FIFO_ON 0x00000008 1035 1036/* Block 28 -- Descriptor Poll Timer */ 1037#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1038#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1039 1040#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1041#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1042#define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1043 1044#define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1045#define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1046#define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1047#define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1048 1049/* Block 29 -- reserved */ 1050 1051/* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1052#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1053#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1054#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1055#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1056#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1057#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1058#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1059#define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1060#define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1061#define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1062#define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1063#define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1064#define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1065#define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1066#define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1067#define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1068#define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1069#define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1070#define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1071#define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1072#define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1073#define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1074#define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1075#define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1076#define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1077#define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1078#define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1079#define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1080#define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1081 1082#define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1083#define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1084#define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1085#define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1086#define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1087#define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1088 1089#define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1090#define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1091#define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1092#define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1093#define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1094#define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1095#define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1096#define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1097#define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1098#define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1099#define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1100#define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1101#define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1102#define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1103#define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1104#define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1105#define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1106#define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1107#define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1108#define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1109#define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1110#define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1111#define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1112 1113#define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1114 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1115#define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1116 SK_GPHY_HWCFG_M_2 ) 1117#define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1118 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1119 1120#define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1121#define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1122#define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1123#define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1124#define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1125#define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1126 1127#define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1128#define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1129 1130/* Block 31 -- reserved */ 1131 1132/* Block 32-33 -- Pattern Ram */ 1133#define SK_WOL_PRAM 0x1000 1134 1135/* Block 0x22 - 0x3f -- reserved */ 1136 1137/* Block 0x40 to 0x4F -- XMAC 1 registers */ 1138#define SK_XMAC1_BASE 0x2000 1139 1140/* Block 0x50 to 0x5F -- MARV 1 registers */ 1141#define SK_MARV1_BASE 0x2800 1142 1143/* Block 0x60 to 0x6F -- XMAC 2 registers */ 1144#define SK_XMAC2_BASE 0x3000 1145 1146/* Block 0x70 to 0x7F -- MARV 2 registers */ 1147#define SK_MARV2_BASE 0x3800 1148 1149/* Compute relative offset of an XMAC register in the XMAC window(s). */ 1150#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1151 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1152 1153#if 0 1154#define SK_XM_READ_4(sc, reg) \ 1155 ((sk_win_read_2(sc->sk_softc, \ 1156 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1157 ((sk_win_read_2(sc->sk_softc, \ 1158 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1159 1160#define SK_XM_WRITE_4(sc, reg, val) \ 1161 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1162 ((val) & 0xFFFF)); \ 1163 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1164 ((val) >> 16) & 0xFFFF) 1165#else 1166#define SK_XM_READ_4(sc, reg) \ 1167 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1168 1169#define SK_XM_WRITE_4(sc, reg, val) \ 1170 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1171#endif 1172 1173#define SK_XM_READ_2(sc, reg) \ 1174 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1175 1176#define SK_XM_WRITE_2(sc, reg, val) \ 1177 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1178 1179#define SK_XM_SETBIT_4(sc, reg, x) \ 1180 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1181 1182#define SK_XM_CLRBIT_4(sc, reg, x) \ 1183 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1184 1185#define SK_XM_SETBIT_2(sc, reg, x) \ 1186 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1187 1188#define SK_XM_CLRBIT_2(sc, reg, x) \ 1189 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1190 1191/* Compute relative offset of an MARV register in the MARV window(s). */ 1192#define SK_YU_REG(sc, reg) \ 1193 ((reg) + SK_MARV1_BASE + \ 1194 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1195 1196#define SK_YU_READ_4(sc, reg) \ 1197 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1198 1199#define SK_YU_READ_2(sc, reg) \ 1200 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1201 1202#define SK_YU_WRITE_4(sc, reg, val) \ 1203 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1204 1205#define SK_YU_WRITE_2(sc, reg, val) \ 1206 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1207 1208#define SK_YU_SETBIT_4(sc, reg, x) \ 1209 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1210 1211#define SK_YU_CLRBIT_4(sc, reg, x) \ 1212 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1213 1214#define SK_YU_SETBIT_2(sc, reg, x) \ 1215 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1216 1217#define SK_YU_CLRBIT_2(sc, reg, x) \ 1218 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1219 1220/* 1221 * The default FIFO threshold on the XMAC II is 4 bytes. On 1222 * dual port NICs, this often leads to transmit underruns, so we 1223 * bump the threshold a little. 1224 */ 1225#define SK_XM_TX_FIFOTHRESH 512 1226 1227#define SK_PCI_VENDOR_ID 0x0000 1228#define SK_PCI_DEVICE_ID 0x0002 1229#define SK_PCI_COMMAND 0x0004 1230#define SK_PCI_STATUS 0x0006 1231#define SK_PCI_REVID 0x0008 1232#define SK_PCI_CLASSCODE 0x0009 1233#define SK_PCI_CACHELEN 0x000C 1234#define SK_PCI_LATENCY_TIMER 0x000D 1235#define SK_PCI_HEADER_TYPE 0x000E 1236#define SK_PCI_LOMEM 0x0010 1237#define SK_PCI_LOIO 0x0014 1238#define SK_PCI_SUBVEN_ID 0x002C 1239#define SK_PCI_SYBSYS_ID 0x002E 1240#define SK_PCI_BIOSROM 0x0030 1241#define SK_PCI_INTLINE 0x003C 1242#define SK_PCI_INTPIN 0x003D 1243#define SK_PCI_MINGNT 0x003E 1244#define SK_PCI_MINLAT 0x003F 1245 1246/* device specific PCI registers */ 1247#define SK_PCI_OURREG1 0x0040 1248#define SK_PCI_OURREG2 0x0044 1249#define SK_PCI_CAPID 0x0048 /* 8 bits */ 1250#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1251#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1252#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1253#define SK_PCI_PME_EVENT 0x004F 1254#define SK_PCI_VPD_CAPID 0x0050 1255#define SK_PCI_VPD_NEXTPTR 0x0051 1256#define SK_PCI_VPD_ADDR 0x0052 1257#define SK_PCI_VPD_DATA 0x0054 1258 1259#define SK_PSTATE_MASK 0x0003 1260#define SK_PSTATE_D0 0x0000 1261#define SK_PSTATE_D1 0x0001 1262#define SK_PSTATE_D2 0x0002 1263#define SK_PSTATE_D3 0x0003 1264#define SK_PME_EN 0x0010 1265#define SK_PME_STATUS 0x8000 1266 1267/* 1268 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1269 * read is complete. Set to 1 to initiate a write, will become 0 1270 * when write is finished. 1271 */ 1272#define SK_VPD_FLAG 0x8000 1273 1274/* VPD structures */ 1275struct vpd_res { 1276 u_int8_t vr_id; 1277 u_int8_t vr_len; 1278 u_int8_t vr_pad; 1279}; 1280 1281struct vpd_key { 1282 char vk_key[2]; 1283 u_int8_t vk_len; 1284}; 1285 1286#define VPD_RES_ID 0x82 /* ID string */ 1287#define VPD_RES_READ 0x90 /* start of read only area */ 1288#define VPD_RES_WRITE 0x81 /* start of read/write area */ 1289#define VPD_RES_END 0x78 /* end tag */ 1290 1291#define CSR_WRITE_4(sc, reg, val) \ 1292 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1293#define CSR_WRITE_2(sc, reg, val) \ 1294 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1295#define CSR_WRITE_1(sc, reg, val) \ 1296 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1297 1298#define CSR_READ_4(sc, reg) \ 1299 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1300#define CSR_READ_2(sc, reg) \ 1301 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1302#define CSR_READ_1(sc, reg) \ 1303 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1304 1305struct sk_type { 1306 u_int16_t sk_vid; 1307 u_int16_t sk_did; 1308 char *sk_name; 1309}; 1310 1311/* RX queue descriptor data structure */ 1312struct sk_rx_desc { 1313 u_int32_t sk_ctl; 1314 u_int32_t sk_next; 1315 u_int32_t sk_data_lo; 1316 u_int32_t sk_data_hi; 1317 u_int32_t sk_xmac_rxstat; 1318 u_int32_t sk_timestamp; 1319 u_int16_t sk_csum2; 1320 u_int16_t sk_csum1; 1321 u_int16_t sk_csum2_start; 1322 u_int16_t sk_csum1_start; 1323}; 1324 1325#define SK_OPCODE_DEFAULT 0x00550000 1326#define SK_OPCODE_CSUM 0x00560000 1327 1328#define SK_RXCTL_LEN 0x0000FFFF 1329#define SK_RXCTL_OPCODE 0x00FF0000 1330#define SK_RXCTL_TSTAMP_VALID 0x01000000 1331#define SK_RXCTL_STATUS_VALID 0x02000000 1332#define SK_RXCTL_DEV0 0x04000000 1333#define SK_RXCTL_EOF_INTR 0x08000000 1334#define SK_RXCTL_EOB_INTR 0x10000000 1335#define SK_RXCTL_LASTFRAG 0x20000000 1336#define SK_RXCTL_FIRSTFRAG 0x40000000 1337#define SK_RXCTL_OWN 0x80000000 1338 1339#define SK_RXSTAT \ 1340 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1341 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1342 1343struct sk_tx_desc { 1344 u_int32_t sk_ctl; 1345 u_int32_t sk_next; 1346 u_int32_t sk_data_lo; 1347 u_int32_t sk_data_hi; 1348 u_int32_t sk_xmac_txstat; 1349 u_int16_t sk_rsvd0; 1350 u_int16_t sk_csum_startval; 1351 u_int16_t sk_csum_startpos; 1352 u_int16_t sk_csum_writepos; 1353 u_int32_t sk_rsvd1; 1354}; 1355 1356#define SK_TXCTL_LEN 0x0000FFFF 1357#define SK_TXCTL_OPCODE 0x00FF0000 1358#define SK_TXCTL_SW 0x01000000 1359#define SK_TXCTL_NOCRC 0x02000000 1360#define SK_TXCTL_STORENFWD 0x04000000 1361#define SK_TXCTL_EOF_INTR 0x08000000 1362#define SK_TXCTL_EOB_INTR 0x10000000 1363#define SK_TXCTL_LASTFRAG 0x20000000 1364#define SK_TXCTL_FIRSTFRAG 0x40000000 1365#define SK_TXCTL_OWN 0x80000000 1366 1367#define SK_TXSTAT \ 1368 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1369 1370#define SK_RXBYTES(x) (x) & 0x0000FFFF; 1371#define SK_TXBYTES SK_RXBYTES 1372 1373#define SK_TX_RING_CNT 512 1374#define SK_RX_RING_CNT 256 1375 1376/* 1377 * Jumbo buffer stuff. Note that we must allocate more jumbo 1378 * buffers than there are descriptors in the receive ring. This 1379 * is because we don't know how long it will take for a packet 1380 * to be released after we hand it off to the upper protocol 1381 * layers. To be safe, we allocate 1.5 times the number of 1382 * receive descriptors. 1383 */ 1384#define SK_JUMBO_FRAMELEN 9018 1385#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1386#define SK_JSLOTS ((SK_RX_RING_CNT * 3) / 2) 1387 1388#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1389#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \ 1390 (SK_JRAWLEN % sizeof(u_int64_t)))) 1391#define SK_JPAGESZ PAGE_SIZE 1392#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1393#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1394 1395struct sk_jpool_entry { 1396 int slot; 1397 SLIST_ENTRY(sk_jpool_entry) jpool_entries; 1398}; 1399 1400struct sk_chain { 1401 void *sk_desc; 1402 struct mbuf *sk_mbuf; 1403 struct sk_chain *sk_next; 1404}; 1405 1406struct sk_chain_data { 1407 struct sk_chain sk_tx_chain[SK_TX_RING_CNT]; 1408 struct sk_chain sk_rx_chain[SK_RX_RING_CNT]; 1409 int sk_tx_prod; 1410 int sk_tx_cons; 1411 int sk_tx_cnt; 1412 int sk_rx_prod; 1413 int sk_rx_cons; 1414 int sk_rx_cnt; 1415 /* Stick the jumbo mem management stuff here too. */ 1416 caddr_t sk_jslots[SK_JSLOTS]; 1417 void *sk_jumbo_buf; 1418 1419}; 1420 1421struct sk_ring_data { 1422 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT]; 1423 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT]; 1424}; 1425 1426struct sk_bcom_hack { 1427 int reg; 1428 int val; 1429}; 1430 1431#define SK_INC(x, y) (x) = (x + 1) % y 1432 1433/* Forward decl. */ 1434struct sk_if_softc; 1435 1436/* Softc for the GEnesis controller. */ 1437struct sk_softc { 1438 bus_space_handle_t sk_bhandle; /* bus space handle */ 1439 bus_space_tag_t sk_btag; /* bus space tag */ 1440 void *sk_intrhand; /* irq handler handle */ 1441 struct resource *sk_irq; /* IRQ resource handle */ 1442 struct resource *sk_res; /* I/O or shared mem handle */ 1443 u_int8_t sk_unit; /* controller number */ 1444 u_int8_t sk_type; 1445 u_int8_t sk_rev; 1446 u_int8_t spare; 1447 char *sk_vpd_prodname; 1448 char *sk_vpd_readonly; 1449 uint16_t sk_vpd_readonly_len; 1450 u_int32_t sk_rboff; /* RAMbuffer offset */ 1451 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1452 u_int32_t sk_pmd; /* physical media type */ 1453 u_int32_t sk_intrmask; 1454 int sk_int_mod; 1455 struct sk_if_softc *sk_if[2]; 1456 device_t sk_devs[2]; 1457 struct mtx sk_mtx; 1458}; 1459 1460#define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1461#define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1462#define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1463#define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc) 1464#define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc) 1465#define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc) 1466 1467/* Softc for each logical interface */ 1468struct sk_if_softc { 1469 struct ifnet *sk_ifp; /* interface info */ 1470 device_t sk_miibus; 1471 u_int8_t sk_unit; /* interface number */ 1472 u_int8_t sk_port; /* port # on controller */ 1473 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1474 u_int32_t sk_rx_ramstart; 1475 u_int32_t sk_rx_ramend; 1476 u_int32_t sk_tx_ramstart; 1477 u_int32_t sk_tx_ramend; 1478 int sk_phytype; 1479 int sk_phyaddr; 1480 device_t sk_dev; 1481 int sk_cnt; 1482 int sk_link; 1483 struct callout_handle sk_tick_ch; 1484 struct sk_chain_data sk_cdata; 1485 struct sk_ring_data *sk_rdata; 1486 struct sk_softc *sk_softc; /* parent controller */ 1487 int sk_tx_bmu; /* TX BMU register */ 1488 int sk_if_flags; 1489 SLIST_HEAD(__sk_jfreehead, sk_jpool_entry) sk_jfree_listhead; 1490 SLIST_HEAD(__sk_jinusehead, sk_jpool_entry) sk_jinuse_listhead; 1491 struct mtx sk_jlist_mtx; 1492}; 1493 1494#define SK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->sk_jlist_mtx) 1495#define SK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_jlist_mtx) 1496 1497#define SK_MAXUNIT 256 1498#define SK_TIMEOUT 1000 1499#define ETHER_ALIGN 2 1500 1501#ifdef __alpha__ 1502#undef vtophys 1503#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1504#endif 1505